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DisplayPort IP Core User Guide

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1. 15 Nibble Code Word 15 Nibble Code Word for Packet Payload for Packet Header 0 0 0 0 0 0 0 0 0 0 nb0 0 nb1 0 nb2 0 nb3 0 nb4 0 nb5 0 nb6 nb0 nb7 nb1 po po pl pl The following figure shows a typical secondary stream packet with the four byte header HBO HB1 HB2 and HB3 and 32 byte payload DBO DB31 Each symbol has an associated parity nibble PBO PB11 Downstream logic can use the start of packet and end of packet to determine if the current input is a header or payload symbol Data is clocked out of the rxN ss port using the rx ss clk signal This signal is the same phase and frequency as the main link lane 0 clock Altera Corporation DisplayPort Sink CJ Send Feedback UG 01131 2015 05 04 Figure 5 9 Typical Secondary Stream Packet 0 DB15 DB31 0 DB14 DB30 0 DB13 DB29 HB3 DB12 DB28 0 DB11 DB27 0 DB10 DB26 0 DB9 DB25 HB2 DB8 DB24 0 DB7 DB23 0 DB6 DB22 0 DB5 DB21 HB1 DB4 DB20 0 DB3 DB19 0 DB2 DB18 0 D I DB17 HBO DBO DB16 End of Packet Start of Packet Valid Audio Interface Audio Interface 5 21 Data 127 0 The audio interfaces are downstream from the secondary stream decoder They extract and decode the audio infoframe packets audio timestamp packets and audio sample data The audio timesta
2. 2015 05 04 Location Name Address Without With Controller Controller EST_CRC_R_Cr 0x0240 Yes EST_CRC_G_Y 0x0242 Yes EST CRC B Cb 0x0244 Yes TEST_SINK_MISC 0x0246 Yes PHY TEST PATTERN 0x0248 mE Yes TEST 80BIT CUSTOM PATTERN 0x0250 to 0x0250 Yes 0x0259 EST RESPONSE 0x0260 Yes EST EDID CHECKSUM 0x0261 Yes SE EST_SINK 0x0270 Yes Yes PAYLOAD_TABLE_UPDATE_STATUS 0x02C0 Yes VC PAYLOAD ID SLOT 1 to 63 0x02C1 Yes IEEE OUI 0x0300 Yes IEEE OUI 0x0301 Yes IEEE OUI 0x0302 Yes DEVICE IDENTIFICATION STRING 0x0303 Yes HARDWARE REVISION 0x0309 Yes FWSW_MAJOR 0x030A Yes FWSW MINOR 0x030B Yes RESERVED 0x030C Yes RESERVED 0x030D Yes RESERVED 0x030E Yes RESERVED 0x030F Yes IEEE OUI 0x0400 Yes DisplayPort Sink Register Map and DPCD Locations LJ Send Feedback Altera Corporation UG 01131 10 38 Sink Supported DPCD Locations 2015 05 04 Location Name Address Without With Controller Controller IEEE OUI 0x0401 Yes IEEE OUI 0x0402 Yes DEVICE IDENTIFICATION STRING 0x0403 Yes HARDWARE_REVISION 0x0409 Yes FWSW_MAJOR 0x040A Yes FWSW_MINOR 0x040B m
3. 4 20 Source Clock Tree 2015 05 04 Figure 4 10 Source Clock Tree Recovered Clock from Transceiv r DisplayPort Encoder 270 135 81 67 5 40 5 MHz Transceiver Block t ss dk t Audio Clock txN_audio_clk Y Audio Data gt Front End Audio sme HH 5540 H Main Audio FIFO Encoder Link 0 Secondary Secondary Stream Sync HSSIO1 Main Stream Data Encoder Link 1 Pixel Clock Back End 4 b vid dl Y Encoder i gt Syne HS302 gt Main Link 2 e Front End gt mea Video FIFO i Y L Sync Ep HSS03 Main aux dk i Link 3 AUX Controller Legend gt tx ss dh dk T lk CMU PLL pe txN vid clk Controller gt aux dk A Interface gt txN audio ck Altera Corporation Transceiver Reference Clock Signal s from PLL or Dedicated Pin 135 MHz DisplayPort Source C Send Feedback DisplayPort Sink 2015 05 04 UG 01131 amp Subscribe Send Feedback Sink Overview The DisplayPort sink has a scalable main link with 1 2 or 4 lanes for a total up to 21 6 Gbps bandwidth A bidirectional AUX channel with 1 Mbps Manchester encoding provides side band communication The sink drives a hot plug detect HPD signal to notify the source that a sink is present Additionally it provides an interrupt mechanism so that the sink can get the source s attention Figure 5 1 DisplayPort Sink Block Diagra
4. Quartus II IP bitec reconfig alt lt prefix gt gip Ouartus II IP files that list the reguired files NM submodule files bitec clkrec dist qip bitec clkrec qip runall tcl Script to set up the project generate the IP and Qsys system and compile assignments tcl Top level TCL file to create the project assignments Scripts build ip tcl TCL file to build the DisplayPort example design IP blocks build sw sh Script to compile the software example sdc Top level SDC file Miscellaneous bitec clkrec sdc Clock recovery core SDC file dp demo sra Directory containing the example application Software files source code in the software btc dprx syslib System library for the RX API directory btc dptx syslib System library for the TX API Build the FPGA Design In this step you use a script to build and compile the FPGA design Type the command runall tcl This script basically builds the IPs and software as well as performs Quartus full compilation Load and Run the Software In this step you load the software into the device and run the software 1 Ina Windows Command Prompt navigate to the hardware demonstration software directory 2 Launch a Nios II command shell You can launch it using several methods for example from the Windows task bar or within the Qsys system 3 From within the Nios II command shell execute the following command to program the device download the Nios II program and
5. 29 20 Unused 19 16 VCP_ID3 VC payload ID for Stream 3 15 12 VCP_1D2 VC payload ID for Stream 2 11 8 VCP_ID1 VC payload ID for Stream 1 7 4 VCP_IDO VC payload ID for Stream 0 3 1 Unused 0 MST_EN Enable or disable MST e 1 MST framing e 0 SST framing When you assert VCPTAB UPD FORCE the sink forces the VC payload table contained in DPRX_MST_VCP When you assert VCPTAB UPD REO the sink requests the VC payload table contained in DPRX_MST_VCP ABO through DPRX MST VCPTAB7 to be taken immediately into use ABO to DPRX_MST_VCPTAB7 to be taken into use after the next ACT sequence is detected The VC Payload ID values 1 15 used for VCP_ID0 to VCP ID3 are different from those used by the DisplayPort source 1 63 The GPU must remap these values The values used have to match those in the VC Payload ID table DPRX MST VCPTABO to DPRX_MST_VCPTAB7 registers MST controller status Address 0x00a1 Direction RO Reset 0x00000 000 Table 10 33 DPRX_MST_STATUS1 Bits mn IL CCS CE 31 Unused 30 MCE ee ee lu e e 1 ACT sequence detected and VC payload updated e O No change to VC payload ID table 29 0 Unused VCPTAB ACT ACK resets to 0 when vc TAB UPD RI VCPTAB UPD RI EQ deasserted vCPTAB ACT ACK is set to 1 if EQ is asserted and the ACT sequence is detected signalling that the table contained in DPRX MST VCPTABO to DPRX_MST_VCPTAB7 registers ha
6. MAX LINK RATE 0x0001 Yes Yes MAX LANE COUNT 0x0002 Yes Yes MAX DOWNSPREAD 0x0003 Yes Yes NORP 0x0004 Yes Yes DOWNSTREAMPORT PRESENT 0x0005 Yes Yes MAIN LINK CHANNEL CODING 0x0006 Yes Yes DOWN STREAM PORT COUNT 0x0007 Yes Yes RECEIVE PORTO CAP 0 0x0008 Yes Yes RECEIVE PORTO CAP 1 0x0009 Yes Yes RECEIVE PORT1 CAP 0 0x000A Yes Yes RECEIVE PORT1 CAP 1 0x000B Yes Yes I2C SPEED CONTROL 0x000C Ves DisplayPort Sink Register Map and DPCD Locations CJ Send Feedback Altera Corporation UG 01131 10 34 Sink Supported DPCD Locations 2015 05 04 Location Name Address Without With Controller Controller EDP CONFIGURATION CAP 0x000D Yes TRAINING AUX RD INTERVAL 0x000E Yes ADAPTER CAP 0x000F Yes FAUX CAP 0x0020 Yes MST CAP 0x0021 Yes NUMBER OF AUDIO ENDPOINTS 0x0022 Yes GUID 0x0030 Yes DWN STRM PORTX CAP 0x0080 Yes Yes LINK BW SET 0x0100 Yes Yes ANE COUNT SET 0x0101 Yes Yes TRAINING_PATTERN_SET 0x0102 Yes Yes TRAINING LANEO SET 0x0103 Yes Yes TRAINING LANE1 SET 0x0104 Yes Yes TRAINING LANE2 SET 0x0105 Yes Yes TRAINING LANE3 SET 0x0106 Yes Yes DOWNSPREAD CTRL 0x0107 Yes Yes MAIN LI
7. VC payload ID or slot 23 27 24 VCPSLOT22 VC payload ID or slot 22 23 20 VCPSLOT21 VC payload ID or slot 21 19 16 VCPSLOT20 VC payload ID or slot 20 15 12 VCPSLOT19 VC payload ID or slot 19 11 8 VCPSLOT18 VC payload ID or slot 18 7 4 VCPSLOT17 VC payload ID or slot 17 3 0 VCPSLOT16 VC payload ID or slot 16 DPRX MST VCPTAB3 VC Payload ID Table Address 0x00a5 Direction RW Reset 0x00000000 Table 10 37 DPRX MST VCPTAB3 Bits 5o meme no O 31 28 VCPSLOT31 VC payload ID or slot 31 27 24 VCPSLOT30 VC payload ID or slot 30 DisplayPort Sink Register Map and DPCD Locations LJ Send Feedback Altera Corporation 10 20 DPRX_MST_VCPTAB4 UG 01131 2015 05 04 mn IL CCS CE 23 20 VCPSLOT29 VC payload ID or slot 29 19 16 VCPSLOT28 VC payload ID or slot 28 15 12 VCPSLOT27 VC payload ID or slot 27 11 8 VCPSLOT26 VC payload ID or slot 26 7 4 VCPSLOT25 VC payload ID or slot 25 3 0 VCPSLOT24 VC payload ID or slot 24 DPRX_MST_VCPTAB4 VC Payload ID Table Address 0x00a6 Direction RW Reset 0x00000000 Table 10 38 DPRX_MST_VCPTAB4 Bits mn JI CCS CE 31 28 VCPSLOT39 VC payload ID or slot 39 27 24 VCPSLOT38 VC payload ID or slot 38 23 20 VCPSLOT37 VC payload ID or slot 37 19 16 VCPSLOT36 VC payload ID or slot 36 15 12 VCPSLOT35 VC payload ID or slot 35 11 8 VCPSLOT34 VC payload ID or slot 34 7 4 VCPSLOT33 VC payload ID or slot 33 3 0
8. 15 Nibble Code Word 15 Nibble Code Word for Packet Payload for Packet Header 0 0 0 0 0 0 0 0 0 0 nb 0 nb1 0 nb2 0 nb3 0 nb4 0 nb5 0 nb6 nb0 nb7 nb1 po po pl pl The following figure shows a typical secondary stream packet with a four byte header HBO HB1 HB2 and HB3 and a 32 byte payload DBO DB31 The core calculates the associated parity bytes The secondary stream interface uses the start of packet SOP and end of packet EOP to determine if the current input is a header or payload Payloads that only contain the first 16 bytes can assert the EOP on the second cycle to terminate the packet sequence Data is clocked in to the secondary stream interface through the tx ss c1k This clock is the same phase and frequency as the main link lane 0 clock DisplayPort Source Altera Corporation LJ Send Feedback 4 16 Audio Interface Figure 4 8 Typical Secondary Stream Packet 0 DB15 DB31 0 DB14 DB30 0 DB13 DB29 HB3 DB12 DB28 0 DB11 DB27 0 DB10 DB26 0 DB9 DB25 HB2 DB8 DB24 0 DB7 DB23 0 DB6 DB22 0 DB5 DB21 HB1 DB4 DB20 0 DB3 DB19 0 DB2 DB18 0 D I DB17 HBO DBO DB16 End of Packet Start of Packet Valid Audio Interface UG 01131 2015 05 04 Data 127 0 The audio encoder is upstream of the secondary stream encoder It generates the Audio InfoFrame Timestamp and Audio sa
9. This LED illuminates for 4 lane designs DisplayPort IP Core Hardware Demonstration CJ Send Feedback Altera Corporation UG 01131 6 4 Clock Recovery Core 2015 05 04 USER_LED 7 6 These LEDs indicate the RX link rate e 00 RBR e 01 HBR e 10 HBR2 Tip When creating your own design note the following design tips e The Bitec daughter card has inverted transceiver polarity When creating your own sink RX design use the Invert transceiver polarity option to enable or disable inverted polarity e The DisplayPort standard reverses the RX and TX transceiver channels to minimize noise for one or two lane applications If you create your own design targeting the Bitec daughter card ensure that the following signals share the same transceiver channel e TXO0 and Rx3 e TX1 and Rx2 e TX2andgxi e TX3 and RXO Refer to the assignments tcl file for an example of how the channels are assigned in the hardware demonstration Clock Recovery Core The clock recovery core is a single encrypted module called bitec_clkrec Figure 6 3 Clock Recovery Core Integration Diagram The figure below shows the integration diagram of the clock recovery core RX Video Clock Video Output Image Port Video Output uu Recovered Video Clock EE RX Link Rate Recovered Video Clock x2 gt RX Link Clock Control Clock To synthesize the video pixel clock from the link clock the clock reco
10. DisplayPort Sink LJ Send Feedback Altera Corporation 5 12 Sink Interfaces Table 5 9 RX Transceiver Interface n is the number of RX lanes s is the number of symbols per clock Note Connect the DisplayPort signals to the Native PHY signals of the same name Interface Clock Direction Domain UG 01131 2015 05 04 Description Clock rx std clkout n 1 0 Taput RX transceiver recovered clock Conduit IMS CN rx parallel Input Parallel data from RX clkout date mer 1 1 20 transceiver Conduit N A rx is lockedtoref n Input When asserted 1 0 indicates that the RX CDR PLL is locked to the reference clock Conduit N A ez is Input When asserted lockedtodata n 1 0 indicates that the RX CDR PLL is locked to the incoming data Conduit rx XCVI rx bitslip n 1 0 Output Use to control bit clkout slipping manually RX transceiver interface Conduit N A rx cal busy n 1 01 Input Calibration in progress signal from RX transceiver Conduit xcvr mgmt rx analogreset n Output When asserted resets clk 1 0 the RX CDR Conduit xcvr_mgmt_ rx_digitalreset n Output When asserted resets clk 1 0 the RX PCS Conduit xcvr mgmt rx set locktoref n Output Forces the RX CDR clk 1 0 circuitry to lock to the phase and frequency of the input reference clock Conduit xcvr mgmt rx set locktodata n Output Forces the RX CDR clk 1 01 circuitry to lock to the received data Altera C
11. Unused Ex Transaction data 12 received in the last request or data 15 for the next reply DPRX AUX BYTE16 AUX Transaction Byte 16 Register Address 0x0113 Direction RW Reset 0x00000000 Table 10 61 DPRX AUX BYTE16 Bits CS OS CE 31 8 Unused 7 0 ens Transaction data 13 received in the last request DPRX_AUX_BYTE17 AUX Transaction Byte 17 Register Address 0x0114 Direction RW Reset 0x00000000 Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Table 10 62 DPRX_AUX_BYTE17 Bits DPRX_AUX_BYTE18 10 31 RS COS Function O 31 8 Unused 7 0 Eeer DPRX_AUX_BYTE18 AUX Transaction Byte 18 Register Address 0x0115 Direction RW Reset 0x00000000 Table 10 63 DPRX_AUX_BYTE18 Bits Transaction data 14 received in the last request KSS CE 31 8 Unused DPRX AUX I2CO Transaction data 15 received in the last reguest AUX to I2C0 management The sink routes all AUX channel accesses to I C slave addresses of values between START ADDR and Address 0x0116 WO 0x00000000 Table 10 64 DPRX AUX 12CO Bits END ADDR to I2C0 RS OS C MN 31 15 Unused 14 8 END_ADDR IC slave end address 7 Unused 6 0 START ADDR EC slave start address DPRX AUX I2C1 AUX to I2C1 management The sink routes all AUX channel accesses to I C slave addresses of values between START ADDR and Di
12. 127 120 Lane 3 symbol n 3 119 112 Lane 3 symbol n 2 111 104 Lane 3 symbol n 1 103 96 Lane 3 symbol n 95 88 Lane 2 symbol n 3 87 80 Lane 2 symbol n 2 79 72 Lane 2 symbol n 1 71 64 Lane 2 symbol n 63 56 Lane 1 symbol n 3 55 48 Lane 1 symbol n 2 47 40 Lane 1 symbol n 1 39 32 Lane 1 symbol n 31 24 Lane 0 symbol n 3 23 16 Lane 0 symbol n 2 15 8 Lane 0 symbol n 1 DisplayPort Sink Altera Corporation LJ Send Feedback UG 01131 5 16 Video Interface 2015 05 04 7 0 Lane 0 symbol When data is received data is produced on lane 0 lanes 0 and 1 or on all four lanes according to how many lanes are currently used and link trained on the main link The IP core provides the data output immediately after the data passes through the descrambler and features all control symbols data and original timing As data is always valid at each and every clock cycle the rxN stream valid signal remains asserted Video Interface This interface rxN video out allows access to the video data as a non Avalon ST stream You can use this stream to interface with an external pixel clock recovery function The stream provides synchroniza tion pulses at the start and end of active lines and at the start and end of active frames Figure 5 4 Video Out Image Port Timing Diagram rxN vid data le em rxN vid valid rxN vid sol rxN vid eol rxN_vid_sof
13. EN equals 1 cR LOCK and sYM LOCK bits register DPRX RX STATUS are forced to 1 for lanes that are not being tested Table 10 6 DPRX BER CONTROL Bits RS CCS MN 31 28 Unused 27 ROLE Writing this bit at 1 resets lane 3 bit error counter in register DPRX BER CNTI1 Always reads as 0 26 SE Writing this bit at 1 resets lane 2 bit error counter in register DPRX BER CNTI1 Always reads as 0 25 P Writing this bit at 1 resets lane 1 bit error counter in register DPRX BER CNTIO Always reads as 0 24 0 Writing this bit at 1 resets lane 0 bit error counter in register DPRX BER CNTIO Always reads as 0 DisplayPort Sink Register Map and DPCD Locations CJ Send Feedback Altera Corporation 10 6 DPRX_BER_CONTROL UG 01131 2015 05 04 RS CCS CE 23 Unused 22 21 PHY_SINK_T EST_LANE SEL Specifies the lane that is being tested when PHY_SINK_ TEST LANE EN is l e 00 Lane 0 e Ol Lanel e 10 Lane2 e 11 Lane3 20 ISIC SION IE EST_LANE EN Writing this bit at 1 enables single lane PHY test Write 0 to disable single lane PHY test 19 RST3 Writing this bit at 1 resets the lane 3 bit error counter in register DPRX_BER_CNT1 Always reads as 0 18 RS Writing this bit at 1 resets the lane 2 bit error counter in register DPRX_BER_CNT1 Always reads as 0 17
14. _ gt tx ss dk a DN msa conduit gt tx_mgmt gt gt dk DisplayPort Source Encoder Video Input AUX Debug Stream Video Clock Avalon ST Interface Audio Input TX Transceiver Interface Audio Clock AUX Interface AUX Clock Secondary Stream Avalon ST Interface MSA Input gt tx aux debug I tx xcvr interface Transceiver Management Calibration Clock Transceiver Management Clock TX Analog Reconfiguration TX Reconfiguration Oh cal t xcvr_mgmt_clk gt tx analog reconfig gt tx reconfig o Controller Interface Avalon MM Interface Avalon MM Interface Clock Interrupt gt tx mgmt interrupt Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 Main Data Path 4 3 Figure 4 3 DisplayPort Source Functional Block Diagram Fixed MSA txN_msa i Multiplexer Measure E MSA D Legend Video Generator gt tx ss dk 3J3 dk DN vid dk Tote p aux dk i gt txN audio ck Video Input PE gt DCFIFO gt Gearbox FIFO L Packetize gt Steer txN video in Blank Start gt Generator gt We gt 40 Bit Quad Symbol or TT 20 Bit Dua
15. Address 0x0105 Direction RW Reset 000000000 Table 10 47 DPRX_AUX_BYTE2 Bits nm Wuess function O O 31 8 Unused 7 0 BYTE Transaction length 3 0 received in the last request or data 2 for the next reply refer to DisplayPort specification DPRX_AUX_BYTE3 AUX Transaction Byte 3 Register Address 0x0106 Direction RW Reset 0x00000000 DisplayPort Sink Register Map and DPCD Locations Altera Corporation CJ Send Feedback UG 01131 10 26 DPRX_AUX_BYTE4 2015 05 04 Table 10 48 DPRX_AUX_BYTE3 Bits RS COS hmmm O 31 8 Unused 7 0 BYRE Transaction data 0 received in the last request or data 3 for the next reply DPRX_AUX_BYTE4 AUX Transaction Byte 4 Register Address 0x0107 Direction RW Reset 0x00000000 Table 10 49 DPRX_AUX_BYTE4 Bits KC I C 31 8 Unused Transaction data 1 received in the last reguest or data 4 for the next reply DPRX AUX BYTES AUX Transaction Byte 5 Register Address 0x0108 Direction RW Reset 0x00000000 Table 10 50 DPRX AUX BYTES Bits pst 1 Wes function O 31 8 Unused 7 0 BYTE Transaction data 2 received in the last request or data 5 for the next reply DPRX_AUX_BYTE6 AUX Transaction Byte 6 Register Address 0x0109 Direction RW Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_AUX_BYTE7 10 27 Reset 0x00000000 Table 10 51 DPRX_AUX_BY
16. Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Source Link Voltage and Pre Emphasis Controls 9 9 Table 9 18 DPTXO_MSA_MISC1 Bits mn JI CS ee O 31 7 Unused 6 COLORIMETRY 0 ITU R BT601 5 1 ITU R BT709 5 5 DYNAMIC_RANGE 0 VESA from 0 to maximum 1 CEA range 4 3 COMPONENT_FORMAT 00 RGB 01 YCbCr 4 2 2 10 YCbCr 4 4 4 11 Reserved 2 0 BPP Bits per pixel format e 000 6 bpc e 001 8 bpc e 010 10bpc e 011 2 12bpc e 100 16 bpc Source Link Voltage and Pre Emphasis Controls This section describes the registers for the link voltage and pre emphasis controls DPTX PRE VOLTO These ports drive the respective tx analog reconfig ports Address 0x0010 Direction RW Reset 0x00000000 Table 9 19 DPTX PRE VOLTO Bits mn JI CS ee O 31 4 Unused 3 2 PREO Pre emphasis output on lane 0 1 0 VOLTO Voltage swing output on lane 0 DisplayPort Source Register Map and DPCD Locations Altera Corporation E Send Feedback UG 01131 9 10 DPTX_PRE_VOLT1 2015 05 04 DPTX_PRE_VOLT1 These ports drive the respective tx_analog_reconfig ports Address 0x0011 Direction RW Reset 0x00000000 Table 9 20 DPTX_PRE_VOLT1 Bits mn JI CS ee O 31 4 Unused 3 PREI Pre emphasis output on lane 1 1 0 VOLTI Voltage swing output on lane 1 DPTX_PRE_VOLT2 These ports drive the respective tx_analog_reconfig ports Address
17. Table 9 29 DPTX_MST_CONTROL1 Bits mn IL CS non O 31 VaR a IER eae This flag always reads back at 0 1 Force VC payload ID table update 30 VCPTAB_UPD_REQ This flag always reads back at 0 1 Request for VC payload ID table update 29 20 Unused 19 16 VCP_ID3 VC payload ID for Stream 3 15 12 VCP_ID2 VC payload ID for Stream 2 11 8 VCP_ID1 VC payload ID for Stream 1 7 4 VCP_IDO VC payload ID for Stream 0 3 1 Unused Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_MST_VCPTABO 9 15 RS CCS CE MST_EN Enable or disable MST e 1 MST framing e 0 SST framing When you assert VCPTAB UPD FORCI DPTX MST VCPTABO through DPTX generated in this case When you assert VCPTAB UPD RI DPTX MST VCPTABO VC Payload ID Table Address 0x00a2 Direction RW Reset 0x00000000 Table 9 30 DPTX MST VCPTABO Bits mn CCS Fan O E the source forces the VC payload table contained in ST VCPTAB7 to be taken immediately into use No ACT sequence is EQ the source requests to generate an ACT sequence and after that use the VC payload table contained in DPTX MST VCPTABO through DPTX_MST_VCPTAB7 31 28 VCPSLOT7 VC payload ID or slot 7 27 24 VCPSLOT6 VC payload ID or slot 6 23 20 VCPSLOTS VC payload ID or slot 5 19 16 VCPSLOT4 VC payload ID or slot 4 15 12 VCPSLOT3 VC payload ID or slot 3 11 8 VCPSLOT2 V
18. UG 01131 2015 05 04 HSMC Connector J4B RX_SENSE_N Output The sink uses this to detect the source power e 0 Source DisplayPort cable is not powered e 1 Source DisplayPort cable is powered This is connected to the sink rx_pwr_detect input In the demonstration design the rx_pwr_detect input is set to 1 in the RTL RX_HPD TX_HPD Input Output RX Hot Plug Detect The sink asserts HPD when both rx_cable_detect and rx_pwr_detect are set to 1 and HPD is enabled TX Hot Plug Detect The HPD pulse duration is used to determine an HPD event type Hot Plugging Unplugging or HPD IRQ RX_ENA Input Device enable for RX Main Link redriver TX_ENA Input Device enable for TX Main Link redriver BNO D IR SPC NUD IROL ING VO RX AUX channel differential pair If the external AUX driver receiver chip SN65MLVD200 U3 is populated on Bitec card the FPGA device should not drive these differential signals To avoid bus contention remove the on chip bidirectional buffer aux buffer rx in the demonstration top module Instead the FPGA device should use AUX RX DRV IN AUX RX DRV OE and AUX RX DRV OUT signals Note The EECH and bx aux OUT signals are inverted If the external AUX driver receiver chip is used undo the inversion AUX_RX_DRV_IN AUX_RX_DRV_OE Output Input RX AUX channel input Use this signal if the external AUX dr
19. tret p e ERROR GENER UK K Edge 10 31 DPRX AUX RESBT uscita FN DIR FUE RU nine 10 32 DPRA AUX HDPD ih perreperrenerecrerperrererre rer ri re e Y fer renerrerer ea Ko dna kz KAVKA AREA 10 32 Sink Supported DPCD Locations eerie entente neto e epi dann XR Siehe He ne pen Kk tenons 10 33 Additional FOr AaG OD Me M A 1 Document Revision History eet tert trt tette trier as ee ee SIE EUIS RE SHE HEURE eae tese de bordes aede A 1 Altera Corporation DisplayPort IP Core Quick Reference 2015 05 04 UG 01131 GX subscribe Send Feedback This document describes the Altera DisplayPort MegaCore function which provides support for next generation video display interface technology The DisplayPort IP core is part of the MegaCore IP Library which is distributed with the Quartus II software and is downloadable from the Altera website at www altera com Note For system requirements and installation instructions refer to the Altera Software Installation and Licensing Manual CS CE Version 15 0 Release Date May 2015 Release Information Ordering Code IP DP Product ID 0109 Vendor ID 6AF7 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademar
20. UG 01131 2015 05 04 31 28 VCPSLOT63 VC payload ID or slot 63 27 24 VCPSLOT62 VC payload ID or slot 62 23 20 VCPSLOT61 VC payload ID or slot 61 19 16 VCPSLOT60 VC payload ID or slot 60 15 12 VCPSLOTS9 VC payload ID or slot 59 11 8 VCPSLOT58 VC payload ID or slot 58 7 4 VCPSLOTS7 VC payload ID or slot 57 3 0 VCPSLOT56 VC payload ID or slot 56 Sink AUX Controller Interface The following sections describe the registers for the AUX Controller interface DPRX AUX CONTROL For transaction reguests 1 Wait for MSG READY in register DPRX AUX STATUS to be 1 or enable the interrupt with AUX IRO EN and wait for the interrupt reguest Read the transaction request total length from LENGTH Read the transaction request command from DPRX AUX COMMAND which clears MSG R ENGTH Read the transaction request data payload from registers DPRX AUX BYTI ENGTH 1 bytes For transaction replies 1 2 3 Altera Corporation EO to DPRX AUX BYTI Wait for READY TO TX in register DPRX AUX STATUS to be 1 Implement a timeout Write registers DPRX AUX COMMAND to DPRX AUX BYTE18 with transaction command and data payload Write LENGTH with the transaction total message length 1 to 17 1 for the command plus 1 to 16 for the data payload and set Tx STROBE to 1 This sequence starts the reply transmission EADY and E15 read DisplayPor
21. btc dprx edid set Prototype int btc dprx edid set BYTE rx idx E port BYTE edid data E num blocks Thread safe Yes Available from ISR Yes Include lt lbore core Sedem gt Return 0 success 1 fail Parameters e rx idx Sink instance index 0 3 e port RX port stream number 0 3 edid data Pointer to EDID data memory e num blocks EDID size in blocks Description This function allows the controller to set the content of the sink s EDID implemented in the system library The library references the EDID data and does not copy it One block is 128 bytes long The system library accepts a maximum of 4 blocks 512 byte long EDIDs Each streaming sink port has its own EDID Example btc dprx edid set 0 0 pmy edid 2 DisplayPort API Reference L Send Feedback Altera Corporation UG 01131 8 8 btc_dprx_hpd_get 2015 05 04 btc_dprx_hpd_get Prototype int btc_dprx_hpd_ get BYTE rx_idx Thread safe Yes Available from ISR Yes Include loc chow Syslis In Return 0 success 1 fail Parameters rx idx Sink instance index 0 3 Description Returns the current logic level of the RX HPD Example btc dprx hpd get 0 Related Information btc dprx hpd pulse on page 8 8 e btc dprx hpd set on page 8 9 btc dprx hpd pulse Prototype void btc dprx hpd pulse BYTE rx idx
22. receiver U4 is populated DP RX Connector J1 CONFIG1 Input Cable Adapter Detect for dual mode support CONFIG2 Not used RTN PWR Input Return signal for DP PWR DisplayPort IP Core Hardware Demonstration CJ Send Feedback Altera Corporation UG 01131 6 20 Required Hardware 2015 05 04 DP RX Connector J1 E Output DP PwR 3 3V 500mA for sink side cable adapter A standard DisplayPort cable must have no wire for this pin DP RX Connector J2 CONFIG1 Input Cable Adapter Detect for dual mode support CONFIG2 Not used RTN_PWR Input Return signal for DP PWR s Output DP PwR 3 3V 500mA for source side cable adapter A standard DP cable must have no wire for this pin Example 6 1 Main Link Re driver Programming Example Bitec DP daughter card has Main Link redriver SN75DP130 that boosts link performance In typical applications the redriver EO VOD pre emphasis levels can be set automatically based on link training In some cases you may want to manually configure the settings The following is an example code that manually configures the redriver EQ VOD Pre emphasis settings Note The bitec_i2c_write function is called inside main c in the demonstration software I C address 0x58 is the write address for the RX redriver J RK KK k k k k k k AA RA AA AA AIA AA kk A k k k ke koe ke ke Disable link training DP130 reg 0x04 data 0x00 J BOK RK K
23. 0x0012 Direction RW Reset 0x00000000 Table 9 21 DPTX_PRE_VOLT2 Bits mn JI CS ee O 31 4 Unused 3 PREZ Pre emphasis output on lane 2 1 0 SOLUS Voltage swing output on lane 2 DPTX PRE VOLT3 These ports drive the respective tx analog reconfig ports Address 0x0013 Direction RW Reset 0x00000000 Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_RECONFIG 9 11 Table 9 22 DPTX_PRE_VOLT3 Bits mn JI CS ee O 31 4 Unused B PRES Pre emphasis output on lane 3 1 0 VOLTS Voltage swing output on lane 3 DPTX_RECONFIG RECONFIG LINKRATI RECONFIG ANALOG drives the tx analog reconfig port tx analog reconfig reg while E drives the tx reconfig port tx reconfig reg GXB BUSY connects to the tx analog reconfig input ports tx analog reconfig busy and tx reconfig tx reconfig busy Address 0x0014 Direction RW Reset 0x00000000 Table 9 23 DPTX RECONFIG Bits O CE 31 CXB_ BUSY Read only flag where e 0 Transceiver is not busy 1 Transceiver is busy 30 2 Unused 1 S DINKRATE This flag always reads back at 0 1 Reconfigure the transceiver with the link rate in DPTX_TX_CONTROL TX_LINK_RATE 0 REC ONETC TANATOS This flag always reads back at 0 1 Reconfigure transceiver with analog values in DPTX_PRE_VOLTO 3 Source Timestamp The Nios II processor can use this global free runni
24. ALTERA_HSMC_SE ALTERA_HSMC_SE NS ALTERA_HSMC_SE Figure 6 8 TI Redriver to DisplayPort Source Connector Schematic Diagram 3X mono uz 8 1 88888842 SKS SSC H ams 2 vi he our a ob S er bee 1 a C7 DAT gue it h 3 n 31 AUX SNK P P AUX SKN 1 H LIH Aux suo E 1 r AUXSN ET CAD SNK R5 n LiL ax NEE RIG EH mx SIE GE me NC 0 VOD DRES FI 1 NM SN75DP130 EI a 100 Dm Dm AUX TX DRV OE 33V 33V A m RARE 8 AMU c nomoro T d a AUX TX PC 04 cse ca Ca Cet cu co CAB c5 AUX TX De IN Ggs Du 0001 Quot 0001 Dm Dm Quoot 22UF Dm gt lap AXTXN 0 2 i i L L n i SN65MLVD200 me HSMC DISPLAYPORT d 2 DisplayPort IP Core Hardware Demonstration CJ Send Feedback Altera Corporation UG 01131 6 16 Required Hardware 2015 05 04 Figure 6 9 DisplayPort Sink Connector to TI Redriver Schematic Diagram ee ERT SN7SDP130 ut HSMA_RX_PIS 0 22 HOMA RX NBS IL Ae 2
25. HPD de btc_dp else if IRQ_HP lt check if Te btc_dp lt Disable nested ndler 0 cmd address length data ource ISR Implementation E HPD IRQ interrupt d Sink EDID gt set video output resolution tx link training asserted tx video enable 0 D link status st Automation request tx test autom interrupt BTC DPTX DISABLE HPD IRQ btc dprx syslib A PI Reference This section provides information about the DisplayPort sink system library functions btc dprx syslib including e C prototype Function description e Whether the fun e Whether the fun e Example ction is thread safe when running in a multi threaded environment ction can be invoked from an ISR btc dprx aux get reguest Prototype int btc dprx aux get reguest BYTE rx idx BYTE cmd unsigned int address BYTE length BYTE data Thread safe Yes DisplayPort API Reference E Send Feedback Altera Corporation UG 01131 8 4 btc_dprx_aux_handler 2015 05 04 Available from ISR Yes Include lt art obe syellilo ia gt Return 0 success 1 fail Parameters Description e rx idx Sink instance index 0 3 e cmd Pointer to command e address Pointer to address e length Pointer to length 0 16 e data Pointer to data received This function retrieves an AUX channel reguest issued by the connec
26. PMA controls dynamically e Altera Transceiver PHY IP Core User Guide Provides more information about how to reconfigure the transceiver for 28 nm devices e AN 676 Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Arria V Physical Media Attachment PMA controls dynamically e AN 678 High Speed Link Tuning Using Signal Conditioning Circuitry Provides more information about link tuning e Arria 10 Transceiver PHY User Guide Provides more information about how to reconfigure the transceiver for Arria 10 devices Secondary Stream Interface The secondary streams data can be received through the rxN ss interfaces The interfaces do not allow for back pressure and assume the downstream logic can handle complete packets The rxN_ss interface does not distinguish between the types of packets it receives The format of the rxN_ss interface output corresponds to four 15 nibble code words as specified by the DisplayPort 1 2a specification section 2 2 6 3 These 15 nibble code words are typically supplied to the DisplayPort Sink Altera Corporation E Send Feedback UG 01131 5 20 Secondary Stream Interface 2015 05 04 downstream Reed Solomon decoder The format differs for both header and payload as shown in the following figure Figure 5 8 rxN_ss Input Data Format
27. RO Reset 0x00000000 Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Table 9 6 DPTXO_MSA_HTOTAL Bits DPTXO MSA VTOTAL 9 5 mn JI osmueeme 1 ee O 31 16 Unused 15 0 HTOTAL DPTXO MSA VTOTAL Address 0x0023 Direction RO Reset 0x00000000 Table 9 7 DPTXO MSA VTOTAL Bits Main stream attribute HTOTAL mn JI Sun 0 Faden O 31 16 Unused 15 0 VTOTAL DPTXO MSA HSP Address 0x0024 Direction RO Reset 0x00000000 Table 9 8 DPTXO_MSA_HSP Bits Main stream attribute VTOTAL mn JI CS ee O 31 1 Unused Main stream attribute horizontal 0 HSP sync polarity 0 Positive 1 Negative DPTXO_MSA_HSW Address 0x0025 Direction RO Reset 0x00000000 DisplayPort Source Register Map and DPCD Locations CJ Send Feedback Altera Corporation UG 01131 9 6 DPTXO MSA HSTART 2015 05 04 Table 9 9 DPTXO MSA HSW Bits mn JI CS ee O 31 15 Unused 14 0 HSW Main stream attribute horizontal sync width DPTXO MSA HSTART Address 0x0026 Direction RO Reset 0x00000000 Table 9 10 DPTXO_MSA_HSTART Bits mn Sun 0 Faden O 31 16 Unused 15 0 HSTART Main stream attribute HSTART DPTXO MSA VSTART Address 0x0027 Direction RO Reset 0x00000000 Table 9 11 DPTXO MSA VSTART Bits mn JI Sun non O 31 16 Unused 15 0 Main stream attribute VSTART DPTXO MSA VSP Address 0x0028
28. ip make simscript spd a10 dp spd spd gxb tx gxb tx spd spd gxb rx gxb rx spd spd gxb tx atx pll gxb tx atx pll spd spd gxb tx reset gxb tx reset spd spd gxb rx reset gxb rx reset spd Arria V Cyclone V and Stratix V devices where prefix is av for Arria V devices cv for Cyclone V devices and sv for Stratix V devices ip make simscript spd prefix xcvr reconfig spd spd prefix dp spd spd prefix native phy rx spd spd prefix native phy tx spd Compile and simulate the design in the ModelSim software vsim c do msim dp tcl The simulation sends several frames of video after reconfiguring the DisplayPort source TX and sink RX to use the HBR 2 7 G rate A successful result is seen by the CTS test automation logic s CRC checks These checks compare the CRC of the transmitted image with the result measured at the sink The result is successful if the sink detects three matching frames Example 7 1 Example Successful Result Testing Link HBR Rate Training Pattern 1 Testing Video Input Frame Number 00 Testing Link HBR Rate Training Pattern 2 TX Frequency Change Detected Measured Frequency 135 MHz RX Frequency Change Detected Measured Frequency 135 MHz SINK CRC_R 9b40 CRC_G 9b40 CRC_B 9b40 SOURCE CRC R 9b40 CRC G 9b40 CRC B 9b40 Pass Test Completed DisplayPort IP Core Simulation Example Altera Corporation CJ Send Feedb
29. om 888888 nop e TEE Z Me LANE a N ouTon Non EN Ml Lane 3 P HSMA RX Nez Axe al omp mip l bt H ME LANE N our Nin 2 T ML LANE 2 P HEMA BY NDS IL naue Las ep 3 MELARE TN GH EE SEA NP Cas cit X3 EH C M HSMA RX N3C25 OF La C2 nm a ML LANE ON leen pii om np pias KTE Mane Gute Nan 48 1 ML LANE 0 P CONFIG CONFIGO Reh ER MEE ao RXSCL DOC SCC Doc TE pre gt AUX RK FC 33 OF 24 AUX SNKp AUX SRCp Hal RTN PWR AUXSNKn AUX SRCR Re ha GENE HPOLSNK HPDLSRC R22 2440 H we ADOR Eau l 3 E Zr XS Fr Rat HK EI g e NX RSTN Tash f woo pres 8888 Ro T Wm T Oh AUX RX NC ae AUX RANC d aw AUX RX DRV OE T aw o TTA fe us 3 LD AUX_RX_DRV_ OUT DE Fa a aux Rx PC d AUX RX DRIN sii aux RX NC e 15 FERRITE 4 Table 6 5 Bitec DisplayPort Daughter Card Signals The following table describes the signals of the Bitec DisplayPort daughter card with HSMC connector 6 HSMC Connector J4A HSMA_TX_CP 3 0 HSMA_TX_ Input TX Main Link lane 3 0 differential signals CN 3 0 In the demonstration design TX Main Link redriver s EQ VOD and pre emphasis settings are self configured based on link training If necessary you can customize the settings via DC program ming IC address for TX Main Link redriver write 0x5C read 0x5D Altera Corporation DisplayPort IP Core Hardware Demonstration C
30. vidin clk Input Pixel clock vidin data Input Pixel data BPP PIXEL S DER CLOCK 1 0 vidin_valid Input You must assert this signal when all signals on this port are valid vidin sol Input Start of video line vidin eol Input End of video line vidin sof Input Start of video frame vidin eof Input End of video frame vidin_ Input You must assert this locked signal when the Display Port RX is locked to a valid received video stream e 1 Video locked e 0 Video unlocked DisplayPort IP Core Hardware Demonstration E Send Feedback Altera Corporation UG 01131 6 10 Video Input Port 2015 05 04 rec_clk Output Reconstructed video clock rec clk x2 Output Reconstructed video clock double frequency vidout Output Pixel data BPP PIXEL S PER CLOCK 1 0 hsync Output Horizontal sync This signal can be active high or active low depending on the sync polarity from MSA vsync Output Vertical sync This signal can be active high or active low depending on the sync polarity from MSA Video Output Conduit rec clk de Output Data enable This signal is always active high field2 Output The clock recovery core asserts this signal during the second video field for interlaced timings reset out Output The clock recovery core asserts this signal when the other video output signals are not valid This signal is asynchronous Video Input Port
31. 0 Clock unlocked lane 3 1 Clock locked lane 3 2 CR LOCZ 0 Clock unlocked lane 2 1 Clock locked lane 2 1 CR_LOCKL 0 Clock unlocked lane 1 1 Clock locked lane 1 0 CRLOCKO 0 Clock unlocked lane 0 1 Clock locked lane 0 This register is also available in read only mode when not using a controller Table 10 5 DPRX_RX_STATUS Bits Non Controller Mode pst 1 Suen Function O 31 17 Unused 16 1 This flag can be reset by writing it to 1 0 Symbol lock on all lanes in use 1 Symbol lock lost on one or more of the used lanes 15 8 Unused 7 SuM LOCKS 0 Symbol unlocked lane 3 1 Symbol locked lane 3 6 SYM_LOCK2 0 Symbol unlocked lane 2 1 Symbol locked lane 2 Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_BER_CONTROL 10 5 mn Suen function NI 5 SUM LOCRI 0 Symbol unlocked lane 1 1 Symbol locked lane 1 4 SYM_LOCKO 0 Symbol unlocked lane 0 1 Symbol locked lane 0 3 CR LOCKS 0 Clock unlocked lane 3 1 Clock locked lane 3 2 CR_LOCK2 0 Clock unlocked lane 2 1 Clock locked lane 2 1 CR LOCHI 0 Clock unlocked lane 1 1 Clock locked lane 1 0 CR_LOCKO 0 Clock unlocked lane 0 1 Clock locked lane 0 DPRX_BER_CONTROL Address 0x0002 Direction CRW Reset 0x00000000 Note When PHY SINK T EST LANE
32. 0x58 Ox1f 0x01 DPCD data 0x01 Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Required Hardware 6 21 J BR RK RK KR KK KK KK RR RR ck k ck k ck ck ck ck ck OK K Program VOD Level 1 and Pre emphasis Level 0 for lane 1 DPCD addr 0x00104 data 0x01 J BOR RK KK k k kk kk kok kk kok kk kk kk kk kk kk KCKCKCk KCKCKCk KCKCkCk KCKCk ck k ck ck ck ck kk ok k bitec i2c write 0x58 Oxlc 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Ox1d 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Oxle 0x04 DPCD addr 7 0 0x04 bitec i2c write 0x58 Ox1f 0x01 DPCD data 0x01 J BOR RR RK k RK KK RR Ck kCkCkCk kCk kCK k CK AXA Ck Ck k ck k ck ck ck ck ck ck ck kk Program VOD Level 1 and Pre emphasis Level 0 for lane 2 DPCD addr 0x00105 data 0x01 J BOR RK k kok k k k k k k k kk kk kk kk kk kk kk KCKCKCk KCKCKCk KCKCKCk KCKCKCk k Ck Ck ck k ck ck ck ck ck ck ck K bitec i2c write 0x58 Ox1c 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Ox1d 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Ox1e 0x05 DPCD addr 7 0 0x05 bitec i2c write 0x58 Ox1f 0x01 DPCD data 0x01 J BOR RK k kok k k k kk kk kok kk kk kk kk kk kk KCKCKCk kk kk KCKCKCk kk kk kk Ck ck k ck ck ck ck ck kk K Program VOD Level 1 and Pre emphasis Level 0 for lane 3 DPCD addr 0x00106 data 0x01 BR RK kok k k k kok kk kok kk kok kk kk kk kk kk kk kk kk KCKCKCk kk k
33. 26 DPIX AUX BYTELA e 9 27 DPTX AUX BY TELS EE 9 27 DPIX AUX EE 9 27 DPIX AUX BY RER EE 9 28 DPIZ AUX BY RE 9 28 DP UX AUX RESE NEE 9 28 Source Supported DPCD Locations 9 29 DisplayPort Sink Register Map and DPCD Locations eee 10 1 EEN 10 1 DPRX RX CONTROLE nn s ooo oa nes 10 1 DPRX RX SIALUS 5 raten iln niet nine 10 3 DPRX BER CONTROB nitemsnennanontimnnanaruiinnnionouses 10 5 DPRX_BERZON Eesen Eet ee 10 7 EE E Ee 10 7 Sink Tiens NEEN 10 7 Sink Geteste canes in SN 10 7 IER Oe RR LU 10 7 DPIX BER OM EE 10 8 sinic MSA Re ro M M 10 8 DPRK MSA CR KE 10 9 DPRX0 MSA NVID e age ete eege teret b eee d teo rua a e ten eee Deae 10 9 Altera Corporation TOC 6 Altera Corporation DPRXO MS WES LO UT s akad 10 9 DPRX0 MSA VTOTA EE 10 9 DPRXD MSA TASB essen acti daseti indecl dou naka kladn aaa 10 10 DPRXO MSA EE 10 10 DPRXDOMSA NN 10 10 DPRXO MSA VSTAR Lii aet t cte ieri e ee ein 10 11 DPRXU MSA VSD DU HENARES IBN nil 10 11 DOS V SW P dt mc koku sek nn 10 11 DOR MS ETV D TE E 10 12 DPRXO VHEIGEHL aie memes mise datant 10 12 DPRXU MSA IMTS COs scvacsesiascvcasacrwerercanisaciasa tennis 10 12 DPRXO MSA MISGL airport tr odtud gees tais Dr hr Dea P ro E Gas 10 13 OPRAV BD EE 10 13 Sink Audio REGISTRES cites naine dira nee aa 10 14 DPRXO_AUD MAUD ontarien 10 14 DPRX0 AUD NAUD E 10 14 IR NE EA E 10 14 IBS ON PEE UU Em 10 15 DPRXD AUD EE 10 15 DPRXO
34. 4 lanes e Maximum video input color depth 24 bits per pixel bpp e Pixel input mode 1 pixel per clock Symbol per Device Direction 7 087 9 580 16 576 Single 9 957 11 121 1 153 31 424 30 Arria 10 stream SST 16 075 10 205 465 27 424 27 29 075 13 605 646 39 776 40 7 176 9 432 1 015 16 576 30 gt 9 881 10 793 1 221 31 424 30 16 340 10 213 499 27 424 27 Arria V 29 258 13 568 715 39 776 40 GX 13 337 15 901 30 336 MST 20 913 19 551 1 952 57 472 52 2 rem 31 790 20 095 879 47 680 54 58 333 27 433 1 357 65 472 80 7 137 9 446 1 035 16 576 30 Cyclone scr 9 817 10 886 1 229 31 424 30 V GX 16 343 10 157 604 27 424 27 29 326 13 537 825 39 776 40 7 006 9 569 966 15 552 28 Stratix cop 9 967 11 087 1 065 30 400 28 V GX 16 340 10 213 499 27 424 27 29 258 13 568 39 776 Related Information Fitter Resources Reports More information about Quartus II resource utilization reporting About This IP Core LJ Send Feedback Altera Corporation Getting Started 2015 05 04 UG 01131 amp Subscribe L J Send Feedback This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with the DisplayPort IP core The IP core is installed as part of the Quartus II installation process You can select and parameterize any Altera IP
35. API Reference E Send Feedback Altera Corporation UG 01131 8 10 btc_dprx_syslib_info 2015 05 04 El Return 0 success 1 fail Parameters e rx idx Sink instance index 0 3 e rx base addr RX base address e rx irq id RXIRQ ID e rx irg num RX IRQ number rx num of sinks Number of streaming sinks used 1 4 options OR ed options for this instance or 0 if unused Description This function declares a sink RX instance to the system library It should be invoked once for each existing sink instance starting from rx_idx 0 After all sinks have been declared invoke btc dprx syslib init Example btc dprx syslib add rx 0 BITEC DP 0 AV RX CONTROL BASE BITEC DP 0 AV RX CONTROL IRO INTERRUPT CONTROLLER ID BITEC DP 0 AV RX CONTROL IRO 2 BTC DPRX OPT DISABLE ERRMON Related Information btc dprx syslib init on page 8 11 btc dprx syslib info Prototype void btc dprx syslib info BYTE max sink num BYTE mst support Thread safe Yes Available from ISR Yes Include lt brce eos sySililo ia gt Return None Parameters e max sink num Pointer for maximum number of sinks supported e mst support Pointer for MST support Description This function returns information about the system library capabilities On return max sink numis set with the maximum number of supported sink instances 1 4 and m
36. Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Source CRC Registers 9 13 mU o site Function 2 0 Ce COUNT Channel count e 000 1 channel e 001 2 channels e 111 8 channels Source CRC Registers The CRC registers are allocated at addresses e 0x0030 through 0x0032 for Stream 0 e 0x0050 through 0x0052 for Stream 1 e 0x0070 through 0x0072 for Stream 2 e 0x0090 through 0x0092 for Stream 3 Note Only registers for Stream 0 are listed in the following sections Computed video CRC red component DPTX0_CRC_R bits Address 0x0030 Direction RO Reset 0x00000000 Table 9 26 DPTXO_CRC_R Bits mn JI CS ee O 31 16 Unused 15 0 CRER Input video CRC for the red component Computed video CRC green component DPTX0_CRC_G bits Address 0x0031 Direction RO Reset 0x00000000 Table 9 27 DPTXO_CRC_G Bits m CE 31 16 Unused DisplayPort Source Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 9 14 Source MST Registers 2015 05 04 CE CR NE 15 0 CRC_G Input video CRC for the green component Computed video CRC blue component DPTx0 CRC B bits Address 0x0032 Direction RO Reset 0x00000000 Table 9 28 DPTXO_CRC_B Bits mn CS ee O 31 16 Unused 15 0 BCB Input video CRC for the blue component Source MST Registers MST controller control Address 0x00a0 Direction RW
37. DPCD Locations Sink Supported DPCD Locations on page 10 33 provides a list of DPCD locations currently supported inbtc dprx syslib sink instantiations Read accesses to unsupported locations receive a response of NATIVE ACK with data content set to zero Write accesses to unsupported locations receive a response of NATIVE NACK Altera Corporation DisplayPort API Reference C Send Feedback DisplayPort Source Register Map and DPCD Locations 2015 05 04 UG 01131 GX subscribe Send Feedback DisplayPort source instantiations require an embedded controller Nios II processor or another controller to act as the policy maker Table 9 1 describes the notation used to describe the registers Table 9 1 Notation EE INN KH NN RW Read write RO Read only WO Write only CRO Clear on read or write read only CWO Clear on read or write write only Source General Registers This section describes the general registers DPTX TX CONTROL The IRQ is asserted when AUX IRO EN 1 and in register DPTX AUX CONTROL flag MSG READY 1 IRQ is de asserted by setting AUX IRO EN to 0 or reading from DPTX aux COMMAND IRQ is also asserted if HPD IRO EN 1 and a new HPD event is detected HPD_EVENT in register DPTX TX STATUS different from 00 IRQ is de asserted by setting HPD IRO EN to 0 or reading from DPTX TX STATUS The Tx LINK RATE drives the respective tx_reconfig port
38. DPRX e 0x00a3 DPRX e 0x00a4 DPRX e 0x00a5 DPRX e 0x00a6 DPRX e 0x00a7 DPRX e 0x00a8 DPRX e 0x00a9 DPRx CON NU U U U U U U U STA G TS 0 1 ROL1 Us1 _VCP ABO _VCP AB1 _VCP AB2 _VCP AB3 _VCP AB4 _VCP AB5 _VCP AB6 _VCP AB7 Additional Information C Send Feedback UG 01131 2015 05 04 Document Revision History A 3 ol Changed the value of the following source register bits e 0x0000 Bits RX LINK RATI e 0x0001 Bits RX LINK RATE e 0x0002 Bits RSTI3 RSTI2 RSTI1 RSTIO Added new signals E clk_cal Calibration clock for transceiver management interface tx link rate Main link rate expressed in multiples of Te 270Mbps rx link rate _ 8bits TX signals for Stream 1 2 and 3 txN video in txN vid clk txN audio CN audio clk CxN ss CXN msa conduit RX signals for Stream 1 2 and 3 rxN video out ISSN viel elik rxN audio rxN ss rxN msa conduit rxN stream Changed the following signal names e rx xcvr clkout to rx ss clk tx xcvr clkout fOtx ss clk Additional Information LJ Send Feedback Altera Corporation A 4 Document Revision History UG 01131 2015 05 04 K RE EE June 2014 2014 06 30 Altera Corporation Native PHY is removed from the IP core included information abo
39. Direction RO Reset 0x00000000 Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTXO MSA VSW 9 7 Table 9 12 DPTXO MSA VSP Bits mn JI CS ee O 31 1 Unused 0 VSP Main stream attribute vertical sync polarity e 0 Positive e 1 Negative DPTXO MSA VSW Address 0x0029 Direction RO Reset 0x00000000 Table 9 13 DPTXO_MSA_VSW Bits mn JI CS ee O 31 15 Unused 14 0 VSW Main stream attribute vertical sync width DPTXO MSA HWIDTH Address 0x002a Direction RO Reset 0x00000000 Table 9 14 DPTXO_MSA_HWIDTH Bits mn JI Sun non O 31 16 Unused 15 0 HWIDTH Main stream attribute HWIDTH DPTXO MSA VHEIGHT Address 0x002b Direction RO Reset 0x00000000 DisplayPort Source Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 9 8 DPTXO MSA MISCO 2015 05 04 Table 9 15 DPTXO MSA VHEIGHT Bits mn CS ee O 31 16 Unused 15 0 VHEIGHT Main stream attribute VHEIGHT DPTXO MSA MISCO Address 0x002c Direction RO Reset 0x00000000 Table 9 16 DPTXO MSA MISCO Bits mn CS ee O 31 8 Unused 7 0 MISCO Main stream attribute MISCO DPTXO MSA MISC1 Address 0x002d Direction RO Reset 0x00000000 Table 9 17 DPTXO MSA MISC1 Bits mn JI osueme non O 31 8 Unused Main stream attribute MISCI DPTXO MSA COLOUR Address 0x002e Direction RW Reset 0x00000001
40. OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase You need only purchase a license for MegaCore IP cores if you decide to take your design to production OpenCore Plus supports the following evaluations O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01131 3 2 Specifying IP Core Parameters and Options 2015 05 04 e Simulate the behavior of a lice
41. PERIOD_NS parameter accordingly RX link clock Clock N A rx_link_clk Input DisplayPort transceiver link clock This clock is a divided version of the RX main link clock or divided by 4 e Divided by 2 when the sink core is instantiated in 20 bit mode 2 symbols per clock e Divided by 4 when the sink core is instantiated in 40 bit mode 4 symbols per clock reset Reset a areset Input Asynchronous reset This is an active high signal DisplayPort IP Core Hardware Demonstration Altera Corporation CJ Send Feedback 6 8 Clock Recovery Interface UG 01131 2015 05 04 RX link rate Conduit asynchronou s rx link rate 1 0 Input DisplayPort RX link rate e 00 RBR 1 67 Gbps e OL HBR 2 70 Gbps e 10 HBR2 5 40 Gbps You need this informa tion for the clock recovery clock to correctly calculate the fPLL parameters RX MSA Conduit rx link clk rx msa 216 0 Input A set of different signals containing the following information e MSA attributes and status e VB ID attributes and status e Received video blanking timing You must connect this set of signals as is from the DisplayPort IP core to the clock recovery core Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Clock Recovery Interface 6 9 Video Input Conduit vidin_clk
42. RGB 1 YCbCr 4 2 2 2 YCbCr 4 4 4 e bpc Color depth bpc 0 6 1 8 2 10 3 12 4 16 e range 0 VESA 1 CEA H colorimetry 0 BT601 5 1 BT709 5 Description This function sets the color space for TX transmitted video Example lo clac Set color seme LAND 012 btc_dptx_syslib_init Prototype int btc_dptx_syslib_init unsigned int tx_base_addr unsigned int tx_irq_id unsigned int tx_irq_num Thread safe No Available from ISR No Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters e tx base addr TX base address e tx irq id TX IRQ ID e tx i rq num IX IRQ number Altera Corporation DisplayPort API Reference L Send Feedback UG 01131 R 2015 05 04 btc dptx syslib monitor 8 19 Description Initializes the system library Should be invoked as the first function in the library by main Set the base address of TX or RX to BTC_NOT_PRESENT if TX or RX not instantiated Example btc dptx syslib init BITEC DP 0 AV TX CONTROL BASE BITEC DP 0 AV TX CONTROL IRO INTERRUPT CONTROLLER ID BITEC DP 0 AV TX CONTROL IRQ btc dptx syslib monitor Prototype int btc dptx syslib monitor void Thread safe No Available from ISR Yes Include btc dptx syslib h Return 0 success 1 fail Parameters No Description This function calls the system library source housekeepi
43. Send Feedback Altera Corporation About This IP Core 2015 05 04 UG 01131 amp Subscribe Send Feedback This document describes the Altera DisplayPort MegaCore function which provides support for next generation video display interface technology The Video Electronics Standards Association VESA defines the DisplayPort standard as an open digital communications interface for use in internal connections such as e Interfaces within a PC or monitor e External display connections including interfaces between a PC and monitor or projector between a PC and TV or between a device such as a DVD player and TV display The Altera DisplayPort source has a scalable main link with 1 2 or 4 lanes for a total up to 21 6 Gbps bandwidth A bidirectional AUX channel with 1 Mbps Manchester encoding provides side band communication The sink uses a hot plug detect HPD signal to announce its presence and the source uses the same signal to initiate link configuration Figure 2 1 DisplayPort Source and Sink Communication The main link has three selectable data rates 1 62 2 7 and 5 4 Gbps Lane 0 Data 1 62 2 7 or 5 4 Gbps Lane 1 Data 1 62 2 7 or 5 4 Gbps Lane 2 Data 1 62 2 7 or 5 4 Gbps Source Lane 3 Data 1 62 2 7 or 5 4 Gbps AUX Channel 1 Mbps Hot Plug Detect Sink O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QU
44. Send Feedback UG 01131 2015 05 04 0 Required Hardware 6 17 HSMC Connector J4A BOMA BOs I8 S Olo ESMA E INT Sin 0 Output RX Main Link lane 3 0 differential signals The demonstration software sets the RX Main Link redriver s EQ settings Refer to main c provided in the demonstration software directory Depending on the channel condition you may want to try various combinations of the EQ VOD pre emphasis settings to achieve optimal link perform ance LC address for RX Main Link redriver write 0x58 read 0x59 SCL_CTL SDA CTL LO DC bus signals to configure the TX and RX Main Link redriver EQ VOD pre emphasis settings TDO_TDI RX_CAD Not used Input HSMC Con nector J4B Cable Adapter Detect This is used to select DisplayPort mode or TMDS mode in the Main Link redrivers 0 DP mode 1 TMDS mode The demonstration design selects the DisplayPort mode RX_CAD 0 RX_SENSE P Output The sink uses this to detect the presence of the source device e 0 Source DisplayPort cable is plugged e 1 Source DisplayPort cable is not plugged When connecting this to the sink rx_cable_detect active high input inverted signal should be used In the demonstration design the rx_cable_detect input is set to 1 in the RTL DisplayPort IP Core Hardware Demonstration E Send Feedback Altera Corporation 6 18 Required Hardware
45. Setting LANE COUNT to 00000 causes the transmitter GXB to always send a logical zero i e a constant voltage level You can use this function to cause a power down for link layer compliance testing Address 0x0000 Direction RW 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 9 2 DPTX_TX_CONTROL Reset 0x00000000 Table 9 2 DPTX_TX_CONTROL Bits UG 01131 2015 05 04 mo mme functio
46. VCPSLOT32 VC payload ID or slot 32 DPRX_MST_VCPTAB5 VC Payload ID Table Address 0x00a7 Direction RW Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Reset 0x00000000 Table 10 39 DPRX MST VCPTAB5 Bits mn CCS Fan 31 28 DPRX MST VCPTAB6 10 21 VCPSLOT47 VC payload ID or slot 47 27 24 VCPSLOT46 VC payload ID or slot 46 23 20 VCPSLOT45 VC payload ID or slot 45 19 16 VCPSLOT44 VC payload ID or slot 44 15 12 VCPSLOT43 VC payload ID or slot 43 11 8 VCPSLOT42 VC payload ID or slot 42 7 4 VCPSLOT41 VC payload ID or slot 41 3 0 VCPSLOT40 VC payload ID or slot 40 DPRX_MST_VCPTAB6 VC Payload ID Table Address 0x00a8 Direction RW Reset 0x00000000 Table 10 40 DPRX_MST_VCPTAB6 Bits mn IL CCS o O 31 28 VCPSLOT55 VC payload ID or slot 55 27 24 VCPSLOT54 VC payload ID or slot 54 23 20 VCPSLOTS3 VC payload ID or slot 53 19 16 VCPSLOT52 VC payload ID or slot 52 15 12 VCPSLOT51 VC payload ID or slot 51 11 8 VCPSLOT50 VC payload ID or slot 50 7 4 VCPSLOT49 VC payload ID or slot 49 3 0 VCPSLOT48 VC payload ID or slot 48 DisplayPort Sink Register Map and DPCD Locations E Send Feedback Altera Corporation 10 22 DPRX_MST_VCPTAB7 DPRX_MST_VCPTAB7 VC Payload ID Table Address 0x00a9 Direction RW Reset 0x00000000 Table 10 41 DPRX_MST_VCPTAB7 Bits mn ee CE
47. Yes RESERVED 0x040C to 0x04FF 0x040C Yes IEEE OUI 0x0500 Yes Yes IEEE OUI 0x0501 Yes Yes IEEE OUI 0x0502 Yes Yes DEVICE IDENTIFICATION STRING 0x0503 Yes HARDWARE REVISION 0x0509 Yes FWSW MAJOR 0x050A Yes FWSW_MINOR 0x050B Yes RESERVED 0x050C to 0x05FF 0x050C Yes SET_POWER_STATE 0x0600 Yes Yes DOWN_REQ 0x1000 to 0x102F 0x1000 Yes DOWN_REP 0x1400 to 0x142F 0x 1400 Yes SINK_COUNT_ESI 0x2002 Yes DEVICE SERVICE IRO VECTOR ESIO 0x2003 Yes DEVICE SERVICE IRO VECTOR ESI1 0x2004 Yes LINK SERVICE IRO VECTOR ESIO 0x2005 Yes LANEO 1 STATUS 0x200C Yes Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Location Name E2_3_STATUS_ESI Sink Supported DPCD Locations 10 39 Address Without Controller With Controller 0x200D LANE ALIGN STATUS UPDATED ESI 0x200E SINK STATUS ESI 0x200F DisplayPort Sink Register Map and DPCD Locations LJ Send Feedback Altera Corporation Additional Information 2015 05 04 UG 01131 GX subscribe Send Feedback Document Revision History The following table lists the revision history for this document Table A 1 Document Revision History l May 2015 2015 05 04 e Added Arria 10 support e Updated color support e RGB 18 24 30 36 or 48 bpp e YCbCr 4 4 4 24 30 36 or 48 bpp e YCbCr 4 2 2 16 20 24 or 32 bpp e Removed information abou
48. You must connect the clock recovery core video input port to the DisplayPort sink core video output image port Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Transceiver and Clocking 6 11 Figure 6 5 Video Input Port Timing Diagram vidin data CUT vidin valid vidin sol vidin eol vidin_sof vidin_oef When the PIXELS_PER_CLOCK parameter is greater than 1 all input pixels are supposed to be valid when you assert vidin_valid The parameter only supports timings with horizontal active width divisible by 2 PIXELS_PER_CLOCK 2 or 4 PIXELS_PER_CLOCK 4 The clock recovery core video output port produces pixel data with standard hsync vsync or de timing All signals are synchronous to the reconstructed video clock rec_c1x unless mentioned otherwise For designs using a TX transceiver you can use rec_c1x as its reference clock You can use rec clk x2 asa reference clock for transceivers that have reference clocks with frequencies lower than the minimum pixel clock frequency received For example the Video Graphics Array VGA 25 MHz resolution when the transceiver s minimum reference clock is 40 MHz The clock recovery core asserts reset_out when the remaining port signals are not valid For example during a recovered video resolution change when the rec clk and rec clk x2 signals are not yet l
49. address DPCD start address e size Number of bytes 1 16 e data Pointer to data to be written Description This function writes 1 to 16 data bytes to the connected DisplayPort sink s DPCD Example btc_dptx_aux_write 0x600 1 data ptr Altera Corporation DisplayPort API Reference G send Feedback UG 01131 2015 05 04 Related Information btc_dptx_baseaddr 8 15 btc_dptx_aux_read on page 8 13 btc_dptx_baseaddr Prototype unsigned int btc_dptx_baseaddr void Thread safe Yes Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters No Description This function returns the base address of the TX instance connected to the given port number Example addr btc dptx baseaddr btc dptx edid block read Prototype int btc dptx edid block read BYTE block BYTE data Thread safe No Available from ISR Yes Include btc dptx syslib h gt Return 0 success 1 fail Parameters e block Block number 0 3 e data Pointer for data to be read Description Reads one block 128 bytes from the EDID of the connected DisplayPort sink Example btc dptx edid block read 2 pdata DisplayPort API Reference LJ Send Feedback Altera Corporation UG 01131 8 16 btc_dptx_edid_read 2015 05 04 Related Information btc_dptx_edid_read on page 8 16 btc_dptx_edid_read SSS ee SE ee nal Prototyp
50. aux tx video in VGA tx serial data rx video out DisplayPort IP Core a10_dp qsys rx serial data rx_aux Reconfiguration Management Altera Corporation DisplayPort IP Core Simulation Example C Send Feedback UG 01131 2015 05 04 Design Walkthrough 7 3 Figure 7 2 Simulation Example Block Diagram for Arria V and Stratix V Devices The files are named lt prefix gt _ lt name gt lt extension gt where lt prefix gt represents the device av for Arria V devices and sv for Stratix V devices dk100 ck162 dk16 dk270 tx vid dkrx vid dk D aux tx mgmt Native PHY IP Core tx serial data T tx video in DisplayPort IP Core lt prefix gt native phy tx v lt prefix gt _dp v rx_video_ out Native PHY IP Core rx_serial_ data lt prefix gt _native_phy_rx v IX aux 1 Transceiver eet Reconfiguration Management Ip C Design Walkthrough Setting up and running the DisplayPort simulation example consists of the following steps 1 Copy the simulation files to your target directory 2 Generate the IP simulation files and scripts and compile and simulate 3 View the results You use a script to automate these steps Copy the Simulation Files to Your Working Directory Copy the simulation example files to your working directory using the command cp r lt IP root directory gt altera altera_dp sim_example lt device gt lt working directory gt where lt device gt is a10 for Arria 10 devices av for Arria V device
51. channel in real time DisplayPort Sink Altera Corporation LJ Send Feedback 5 4 Embedded DisplayPort eDP Support Embedded DisplayPort eDP Support UG 01131 2015 05 04 The DisplayPort IP core is compliant with eDP version 1 3 eDP is based on the VESA DisplayPort standard It has the same electrical interface and can share the same video port on the controller The DisplayPort IP core supports e Full normal link training default e Fast link training mandatory eDP feature Sink Parameters You set parameters for the sink using the DisplayPort parameter editor Table 5 1 Sink Parameters Device family Select the targeted device family Arria V GX Arria V GZ Cyclone V or Stratix V matches the project device family Support DisplayPort sink Turn on to enable DisplayPort sink Maximum video output color depth RX maximum link rate Specify the video output interface port bits per color Determines top level video output port width for example 6 bpc 18 bits 16 bpc 48 bits Select the maximum link rate 5 4 Gbps 2 7 Gbps 1 62 Gbps Note Cyclone V devices do not support 5 4 Gbps Maximum lane count Select the maximum lanes desired 1 2 or 4 Symbol input mode Specify how many symbols are transferred during each clock cycle dual or quad symbol or RX transceiver data width dual 20 bits or quad 40 bits Dual symbol mode saves logic resource but requires
52. data channels as per maximum lane count parameter This value is for non bonded mode Enable simplified data interface Data rate 2700 Mbps when TX maximum link rate 2 7 Gbps TX local clock division factor TX PMA 2 when TX RX maximum link rate 2 7Gbps Enable TX PLL dynamic reconfiguration On Number of TX PLLs 1 Main TX PLL logical index 0 Number of TX PLL reference clock 1 PLL type CMU Reference clock frequency 135 MHz Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Transceiver and Clocking 6 13 TX PLLO Selected reference clock source 0 xl or xN Note If you select x1 you must instantiate Selected clock network the PHY instance multiple times for all data channels as per maximum lane count parameter This value is for non bonded mode Enable CDR dynamic reconfiguration On Number of CDR reference clocks 1 Selected CDR reference clock 0 Selected CDR reference clock frequency 135 MHz PPM detector threshold 1000 ppm Enable rx_is_lockedtodata port On Enable rx_is_lockedtoref port O Enable rx_set_locktodata and rx_set_locktoref ports On Standard PCS protocol mode Basic Standard PCS PMA interface width 20 when symbol output mode is dual Byte Serializer and Deserializer Enable TX byte serializer Off when symbol output mode is dual Enable RX byte deserial
53. ennemie J 6 14 deser Sale MC 6 22 Set Up the Hardwaresiiinninnanannnantin dinars 6 23 Copy the Design Files to Your Working Dir tofy insisshonsnnss 6 23 Build the e i D 6 25 Logd and R n Be SOL WAR s ananas ane 6 25 View th Result nn ensure ententes 6 26 DisplayPort IP Core Simulation Example 7 1 Design Walkthrough e 7 3 Copy the Simulation Files to Your Working Directory ss 7 3 Generate the IP Simulation Files and Scripts and Compile and Simulate 7 6 View the RESUMES c 7 8 DisplayPort API Rekter eege Eege 8 1 Using the LIDTA Vis T EES 8 1 btc dorx syslib API Reference aiser ierg 8 3 bte dprx aux aN Re a an ne ee en ot 8 3 o eiii inim dictio TAA OR RN O O nn ne 8 4 ET POSE SG sce abd bati Apad ai dna disca de No M diat e tude 8 5 bte dprx bas addi ER 8 6 bte dprx dped gpu EE ee 8 6 Die edid Seco en eire day oba rest reer 8 7 bte dprz WE E 8 8 bic dprz Bod pulses EE 8 8 e NGS eonun pcg ah Dae iter de ec 8 9 Die xps E A6 oko PT un pain ants que quavis ri eun pei RE 8 9 bte dprx syslib M ii RT P nana nt ae 8 10 bte E e 8 11 Die pe SO MORE na R O O O ania E ENSERES 8 11 Altera Corporation TOC 4 eise Merci API BR er ta RR 8 12 Dbe pte ae DC r
54. ex vid eof rx vid data J y rx_cvi_datavalid rx ei f rx cvi h sync IX Cvi v sync rx cvi locked Ix cvi de Ix cvi data y y y Arria 10 Finite State Machine FSM The flow charts show the FSM flow for Arria 10 transceivers DisplayPort IP Core Simulation Example Altera Corporation E Send Feedback S UG 01131 7 12 Arria 10 Finite State Machine FSM 2015 05 04 Figure 7 7 Reconfiguration Top Manager FSM for Arria 10 Devices This flow chart shows the reconfiguration FSM flow for Arria 10 transceivers When the transceiver detects a reconfiguration request _reconfig_req it triggers the reconfiguration manager to reconfigure RX TX and TX Analog and exercise the respective Avalon MM cycle in sequence FSM_IDLE rx_reconfig_req tx_pll_reconfig_req tx_reconfig_req FSM_START_RECONFIG lt rx_reconfig_req 1 A10_dp_rx_reconfig_mgmt tx pll reconfig req 1 A10 dp txpll reconfig mgmt tx reconfig req 1 A10 dp tx reconfig mgmt n FSM_END_RECONFIG Altera Corporation DisplayPort IP Core Simulation Example CJ Send Feedback UG 01131 2015 05 04 Arria 10 Finite State Machine FSM 7 13 Figure 7 8 RX TX and TX Analog Reconfiguration Manager FSM for Arria 10 Devices This flow chart shows the reconfigurati
55. gt DON video out a rxN_vid_clk gt rxN_msa_conduit gt DON stream rx aux 4 aux dk JM x params gt rx aux debug Transceiver Management Calibration Clock Transceiver Management Clock RX Reconfiguration Oh cal xcvr_mgmt_clk gt rx reconfig rx mgmt gt dk gt Controller Interface Avalon MM Interface Avalon MM Interface Clock Interrupt rx mgmt interrupt DisplayPort Sink C Send Feedback UG 01131 cu 2015 05 04 Sink Functional Description Figure 5 3 DisplayPort Sink Functional Block Diagram IRO gt Control HPD gt SC pM DCFIFO Ep Secondary Stream rxN_ss 20 Bit Dual Symbol AB pe Deskew H gt De Scrambler DP2ST gt Gearbox gt DCFIFO Steering gt Video Output or 40 Bit Quad Symbol 9 rxN video out Data from Transceiver rx xevr interface VB ID Legend gt Decoder P gt rx ss dk p gt dk MSA PN vid clk gt Decoder aux dk Bidirectional AUX Data IX aux AUX gt gt Controller Registers La Avalon MM rx mgmt Controller HPD 3 9 p gt AUX Debug Stream rx aux debug The device transceiver sends 20 bit dual symbol or 40 bit quad symbo
56. nan o ae aaa u nn OR 4 7 Controller Inforiace uses D add vU nanas dp x QUPD UK id 4 11 AUX MD Up M 4 12 Video Te Ge EMT EC 4 12 TX Transceiver TR EMA names dura 4 13 Transceiver Reconfiguration feras asian pins 4 14 Transceiver Analog Reconfiguration Interfaces 4 14 Secondary Er ne se totales 4 14 A di Bettener 4 16 MOA TOM uza bd eo 4 18 Source Clock TEEB side dukddiias ends od vsv zasodv kk 4 19 Display a nd nn no o Us Nash es 5 1 le 5 1 Sink Functional Description eec ende pe dee ap dedi dat iri nd ed tes a i diee 5 1 Embedded DisplayPort eDP SUDDUOEL antenne 5 4 KE 5 4 Sink Uber la cess tee 5 6 Altera Corporation Controller Interface Ren e es 5 13 AUX TMA euer anna annales 5 13 IR 5 14 VID O Ua LE A ed nn nn none 5 16 RX Transceiver HET eege 5 19 Transceiver Reconfiguration ter andes einn IRSE RARI NIRORM DIA EAT UE N UA IE MIR AUS 5 19 Secondary Stream DUterfase seu qe adi bre PUES RU dE CR A nn 5 19 ARR RDS KE co SNNT MMC 5 21 MSA Interface RT 5 22 Sink Clock ue c 5 24 DisplayPort IP Core Hardware Demonstration eese 6 1 idi la qii D M 6 4 Clock Recovery Core Paramelers erp SECH 6 5 Clock Recovery Miter co P 6 6 Transceiver and Clockine m 6 11 Required NAT
57. one Example btc_dprx_aux_post_reply 0 0x10 0 NULL Reply AUX_NACK Related Information btc_dprx_aux_get_request on page 8 3 btc_dprx_baseaddr Prototype unsigned int btc_dprx_baseaddr BYTE rx_idx Thread safe Yes Available from ISR Yes Include lt btc dprx syslib h gt Return 0 success 1 fail Parameters rx idx Sink instance index 0 3 Description This function returns the RX instance s base address connected to the given port number Example addr btc_dprx_baseaddr 0 btc_dprx_dpcd_gpu_access Prototype int btc_dprx_dpcd_gpu_access BYTE rx idx BYTE wrcmd unsigned int address BYTE length BYTE data Thread safe Yes Available from ISR Yes Include lt late goes syelilo ia gt Altera Corporation DisplayPort API Reference C Send Feedback UG 01131 2015 05 04 btc_dprx_edid_set 8 7 Return 0 success 1 fail Parameters e rx idx Sink instance index 0 3 e wrcmd 0 read 1 write e address Address e length Length 1 255 e data Pointer to data Description This function allows the controller to access the sink s DPCD locations implemented in the system library for reading and writing data data must point to a location containing length bytes writes or be able to accommodate length bytes reads Example btc dprx dpcd gpu access 0 1 0x00000 1 pwrdata
58. registers HPD IRO ENis 1 and the IP core detects a new HPD event HPD F V ENT provides information about the event that caused the interrupt The interrupt and on F register Address 0x0001 Direction CRO Reset 0x00000000 Table 9 3 DPTX_TX_STATUS Bits mn JI CS ee O VENT bit fields are both cleared by reading the DPTX TX STATUS 31 4 Unused 3 RESERVED Reserved 2 HEDLDSVEL Current HPD logic level 1 0 ss EVENT HPD event causing IRQ read to clear e 00 No event e 01 HPD plug event long HPD e 10 HPD IRQ short HPD e 11 Reserved DisplayPort Source Register Map and DPCD Locations Altera Corporation E Send Feedback UG 01131 9 4 Source MSA Registers 2015 05 04 Source MSA Registers The MSA registers are allocated at addresses e 0x0020 through 0x002e for Stream 0 e 0x0040 through 0x004e for Stream 1 e 0x0060 through 0x006e for Stream 2 e 0x0080 through 0x008e for Stream 3 Note Only registers for Stream 0 are listed in the following sections DPTXO MSA MVID Address 0x0020 Direction RO Reset 0x00000000 Table 9 4 DPTXO MSA MVID Bits mn JI Sun non O 31 24 Unused 23 0 MVID Main stream attribute MVID DPTXO MSA NVID Address 0x0021 Direction RO Reset 0x00000000 Table 9 5 DPTXO MSA NVID Bits mn JI CS ee O 31 24 Unused 23 0 NVID Main stream attribute NVID DPTXO MSA HTOTAL Address 0x0022 Direction
59. resource of video measurement In this scenario the DisplayPort source uses the MSA values presented on the txN_msa_conduit signal bundle shown below wire 191 0 txN_msa_conduit Mvid 23 0 Nvid 23 0 Htotal 15 0 Vtotal 15 0 HSP HSW 14 0 Hstart 15 0 Vstart 15 0 VSP VSW 14 0 Hwidth 15 0 Vheight 15 0 MISCO 7 0 MISC1 7 0 Table 4 12 txN_msa_conduit Port Signals 191 168 Mvid 23 0 Mvid for the main video stream Used for stream clock recovery from link symbol clock 167 144 Reesen Nvid for the main video stream Used for stream clock recovery from link symbol clock 143 128 Htotal 15 0 Horizontal total of received video stream in pixels 127 112 Vtotal 15 0 Vertical total of received video stream in lines 111 HSP H sync polarity 0 Active high 1 Active low 110 96 HSW 14 0 H sync width in pixels 95 80 Hstart 15 0 Horizontal active start from H sync start in pixels H sync width Horizontal back porch Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 Source Clock Tree 4 19 79 64 Vstart 15 0 Vertical active start from V sync start in lines V sync width Vertical back porch 63 VSP V sync polarity 0 Active high 1 Active low 62 48 VSW 14 0 V sync width in lines 47 32 Hwidth 15 0 Active video width in pixels 31 16 Vheight 15 0 Active video height in lines 15 8 MISCO 7 0 The mrsco 7 1 and misc11 7 fields indic
60. rxN vid eol Outp ut rxN vid sof Outp ut rxN_ i vi deo_out Conduit rx vid cik rxN_vid_eof Outp Video output ut rxN_vid_locked Outp ut rxN_vid_overflow Outp ut rxN vid data 3v p 1 0 Outp ut Table 5 5 AUX Interface aux clk Clock aux_clk Input AUX channel clock aux reset Reset aux_clk aux_reset Input AUX channel reset Altera Corporation DisplayPort Sink C Send Feedback UG 01131 2015 05 04 Sink Interfaces 5 9 rx_aux_in Input rx_aux_out Outp ut rx_aux_oe Outp ut IX aux Conduit aux clk AUX channel interface rx hpd Outp ut rx cable detect Input rx pwr detect Input rx aux debug Output data 31 0 rx aux debug valid Outp ut rx aux debug sop Outp ut Avalon ST stream of oe AV ST aux_clk AUX data for debug rx aux debug eop Outp debugging ut rx aux debug err Outp ut rx aux debug cha Outp ut DisplayPort Sink Altera Corporation LJ Send Feedback 5 1 Sink Interfaces UG 01131 2015 05 04 EDID rx_edid AV MM aux_clk rx edid address 7 0 Output rx edid read Outp ut rx edid write Outp ut rx edid writedata 7 0 Outp ut rx edid readdata 7 0 Input rx edid waitrequest Input Avalon MM master interface to external on chip memory for EDID Table 5 6 Debugging Interface s is the number of symbols per clock and uw is the stream number Direction Description I
61. the core to run at twice the clock frequency of quad symbol mode If timing closure is a problem in the device you should consider using quad symbol mode Altera Corporation DisplayPort Sink C Send Feedback UG 01131 2015 05 04 Sink Parameters 5 5 Pixel output mode Select the number of pixels per clock single dual or quad symbol e Ifyou select dual pixels per clock the pixel clock is of the full rate clock and the video port becomes two times wider e Ifyou select four pixels per clock the pixel clock is of the full rate clock and the video port becomes four times wider Sink scrambler seed value Specify the initial seed value for the scrambler block Use 16 hFFFF for DP and 16 hFFFFE for eDP Invert transceiver polarity Turn on to invert the transceiver polarity Export MSA Turn on to enable the sink to export the MSA interface to the top level port interface IEEE OUI Specify an IEEE organizationally unique identifier OUT as part of the DPCD registers Enable GPU control Turn on to use an embedded controller to control the sink Enable AUX debug stream Turn on to enable AUX traffic output to an Avalon ST port Support CTS test automation Support secondary data channel Turn on to support automated test features Turn on to enable secondary data Support audio data channel Turn on to enable audio packet decoding Number of audio data channels Spe
62. 02F 0x1000 UP REP 0x1200 to 0x122F 0x1200 DOWN REP 0x1400 to 0x142F 0x1400 UP REO 0x1600 to 0x162F 0x1600 Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback DisplayPort Sink Register Map and DPCD Locations 1 0 2015 05 04 UG 01131 DZ subscribe Send Feedback DisplayPort sink instantiations greatly benefit from and may optionally use an embedded controller Nios II processor or another controller This section describes the register map Table 10 1 Notation KZ C RW Read write RO Read only WO Write only CRO Clear on read or write read only CWO Clear on read or write write only Sink General Registers This section describes the general registers DPRX_RX_CONTROL The IRQ is asserted when AUX IRO EN 1 and in register DPRX AUX CONTROL the flag MSG READY 1 IRQ is de asserted by setting AUX IRO EN to 0 or reading from DPRX AUX COMMAND RECONFIG_LINKRATE drives the rx reconfig reg RX LINK RATE drives rx link rate Address 0x0000 Direction RW Reset 0x00000000 CH 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holde
63. 31 2015 05 04 Source Interfaces 4 9 Table 4 4 Video Interface v is the number of bits per color p is the pixels per clock 1 single 2 dual and 4 quad N is the stream number for example tx vid clk represents Stream 0 tx1 vid clk represents Stream 1 and so on txN_vid_ Clock txN vid clk Input Video clock clk txN vid data 3v p 1 0 Input txN vid v sync p 1 0 Input Video data and txN_ i standard H V synchro Conduit txN vid clk txN vid h sync p 1 0 Input m video in nization video port txN vid f p 1 0 Input input txN vid de p 1 0 Input Table 4 5 AUX Interface aux ck Clock aux_cik Input AUX channel clock aux reset Reset aux_cik aux_reset Input AUX channel reset tx_aux_in Input tx_aux_out Outp ut tx aux Conduit dus ik AUX channel interface tX aux oe Outp ut tx hpd Input tx aux debug Output data 31 0 tx aux debug valid Outp ut tx aux debug sop Outp t Avalon ST stream of d b AV ST aux_clk AUX data for ebug tx aux debug eop Outp debugging ut tx aux debug err Outp ut tx aux debug cha Outp ut DisplayPort Source Altera Corporation LJ Send Feedback UG 01131 4 10 Source Interfaces 2015 05 04 Table 4 6 Secondary Interface N is the stream number for example tx msa conduit represents Stream 0 tx1 msa conduit represents Stream 1 and so on t
64. 5 05 04 btc_dptx_syslib API Reference This section provides information about the DisplayPort source system library functions btc_dptx_syslib including C prototype Function description Whether the function is thread safe when running in a multi threaded environment Whether the function can be invoked from an ISR Example btc_dptx_aux_i2c_read Prototype int btc_dptx_aux_i2c_read BYTE address BYTE size BYTE data BYTE mot Thread safe No Available from ISR Yes Include lt love eors melen gt Return 0 success 1 fail Parameters e address I C address e size Number of bytes 1 16 e data Pointer to data to be read e mot Middle of transaction 0 or 1 Description This function reads 1 to 16 data bytes from the connected DisplayPort sink s PC interface mapped over the AUX channel Example btc_dptx_aux_i2c_read 0x50 16 data 1 Related Information btc_dptx_aux_i2c_write on page 8 13 Altera Corporation DisplayPort API Reference C Send Feedback UG 01131 2015 05 04 btc_dptx_aux_i2c_write 8 13 btc_dptx_aux_i2c_write Prototype int btc_dptx_aux_i2c_write BYTE address BYTE size BYTE data BYTE mot Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters e address I2C address e size Number of bytes 1 16 e data Pointe
65. ARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 Iso 9001 2008 Registered UG 01131 2 2 Device Family Support 2015 05 04 Device Family Support The following table lists the link rate support offered by the DisplayPort IP core for each Altera device family Table 2 1 Link Rate Support by Device Family RBR Reduced Bit Rate HBR High Bit Rate Arria 10 RBR HBR HBR2 RBR HBR HBR2 Arria V GX RBR HBR RBR HBR HBR2 Arria V GZ RBR HBR HBR2 RBR HBR HBR2 Cyclone V RBR HBR RBR HBR Stratix V RBR HBR HBR2 RBR HBR HB
66. AUD ALTES cie tft ree throat ot repe coe ot aibi ged tese db RESTEN sens 10 15 IRE CES LEES IT e H 10 16 Sink MST Register M 10 16 DPRX MSI VGPLADBU nant nn ARR 10 17 DPRX MSI e RN EE 10 18 DOP RA IIS TV CP TA B nement mean non 10 19 DPRX MSL VCP TABS EE 10 19 RINNEN 10 20 DPRX e RE 10 20 DPRY MSI VOPTIADBD seau e 10 21 DPRX MSL VGOPLADBZ7 nznecotitera i t tiit im a kout dita Coo peat dao 10 22 Sink AUX Controller Interface ounce uev dd ipa tex UH Re vH ER AKA nier 10 22 DPRX AUX CONTROL nitri innt tea ciae eei ese evo ctia a envase po eost ee 10 22 DPD AUX STATUS asserebat manne 10 23 DPRX AUX COMMAND tait eie dein e end esee antenne nie 10 24 DPR AUX MIU M MD Hr 10 24 DPRX AUX BY DEL dd centre nitore ba umi dansante 10 25 DORE E BYTE enr 10 25 DPRX AUX BY E32 ttt torta i Leitern or da nadia 10 25 DPRX AUX Ch A NEE 10 26 DPRX AUX BY VES EE 10 26 DPA EE EEGs C T natal 10 26 DPRX AUX BY RE 10 27 DPRX AUX BYLDBEBLeaenstontiinsirakede ies dv nba tu e e t ak ds kde dne 10 27 DPRX AUX BYTE EE 10 27 DPRX AUX PV De se nee UMANE d natif 10 28 DPRX AUX BY Ai RER 10 28 DPRX AUX BY TE nn 10 29 DPRX_AUX_BYVEIS E 10 29 DPRX AUX BYTE E 10 29 DPRX AUX BYTES isese reens eresse eau 10 30 DPRX AUX Ai NEE 10 30 DPRX AUX BYTB 17 4uiiaa iier ertet t eee eye ed miettes 10 30 DPRX AUX BYLPELIBS eant diente end nias nine mien eee 10 31 iure dE ia dU o T 10 31 DPRX AUX I2 LL
67. B or YCbCr 4 4 4 24 bpp Turn on to support 24 bpp encoding 10 bpc RGB or YCbCr 4 4 4 30 bpp Turn on to support 30 bpp encoding 12 bpc RGB or YCbCr 4 4 4 36 bpp Turn on to support 36 bpp encoding 16 bpc RGB or YCbCr 4 4 4 48 bpp Turn on to support 48 bpp decoding 8 bpc YCbCr 4 2 2 16 bpp Turn on to support 16 bpp encoding 10 bpc YCbCr 4 2 2 20 bpp Turn on to support 20 bpp encoding 12 bpc YCbCr 4 2 2 24 bpp Turn on to support 24 bpp encoding Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 Source Interfaces 4 7 16 bpc YCbCr 4 2 2 32 bpp Turn on to support 32 bpp encoding Support MST Turn on to enable multi stream support Max stream count Select the maximum amount of streams supported 1 4 Source Interfaces The following tables list the source s port interfaces Your instantiation contains only the interfaces that you have enabled Table 4 2 Controller Interface Clock Input Clock for embedded controller reset Reset clk reset Input Reset for embedded controller tx_mgmt_address 8 0 Input tx_mgmt_chipselect Input tx_mgmt_read Input tx mgmt write Input Avalon MM interface tx mgmt AV MM clk 3 Input for embedded writedata 31 0 controller tx mgmt readdata 31 0 Outp ut tx mgmt waitrequest Outp ut tx mgmt IRQ clk ee de Output Interrupt
68. C payload ID or slot 2 7 4 TED VC payload ID or slot 1 3 0 Reserved Reserved DPTX MST VCPTAB1 VC Payload ID Table Address 0x00a3 Direction RW Reset 0x00000000 DisplayPort Source Register Map and DPCD Locations LJ Send Feedback Altera Corporation 9 16 DPTX_MST_VCPTAB2 Table 9 31 DPTX_MST_VCPTAB1 Bits mn IL nn lee O 31 28 UG 01131 2015 05 04 VCPSLOT15 VC payload ID or slot 15 27 24 VCPSLOT14 VC payload ID or slot 14 23 20 VCPSLOT13 VC payload ID or slot 13 19 16 VCPSLOT12 VC payload ID or slot 12 15 12 VCPSLOT11 VC payload ID or slot 11 11 8 VCPSLOT10 VC payload ID or slot 10 7 4 VCPSLOT9 VC payload ID or slot 9 3 0 VCPSLOT8 VC payload ID or slot 8 DPTX MST VCPTAB2 VC Payload ID Table Address 0x00a4 Direction RW Reset 0x00000000 Table 9 32 DPTX MST VCPTAB2 Bits m o O 31 28 VCPSLOT23 VC payload ID or slot 23 27 24 VCPSLOT22 VC payload ID or slot 22 23 20 VCPSLOT21 VC payload ID or slot 21 19 16 VCPSLOT20 VC payload ID or slot 20 15 12 VCPSLOT19 VC payload ID or slot 19 7 4 VCPSLOT17 VC payload ID or slot 17 3 0 VCPSLOT16 VC payload ID or slot 16 Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_MST_VCPTAB3 VC Payload ID Table Address 0x00a5 Direction RW Reset 0x00000000 Table 9 33 DPTX_MST_VCPTAB3 Bits DPTX_MST_VCPTAB3 9 17 mn IL CCS C
69. D te ROSES 0 Busy sending a reply or waiting for a request 1 Ready to send a reply 29 2 Unused 1 SRC_PWR_DETECT 0 Upstream power not detected 1 Upstream power detected 0 SRC_CABLE_DETECT 0 Upstream cable not detected 1 Upstream cable detected DPRX_AUX_COMMAND AUX transaction command register DPRX AUX COMMAND Table 10 44 DPRX_AUX_COMMAND Bits Address 0x0102 Direction RW Reset 000000000 m o ES Fem O 31 8 Unused 7 0 COMMAND AUX transaction command for the next reply or received in the last request refer to the DisplayPort specification Reading of this register clears MSG READY and LENGTH in DPRX_ AUX_CONTROL register DPRX_AUX_BYTEO AUX Transaction Byte 0 Register Address 0x0103 Direction RW Reset 0x00000000 Table 10 45 DPRX_AUX_BYTEO Bits pst o BitName function O 31 8 Unused Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_AUX_BYTE1 10 25 DC CU a 7 0 BYTE Transaction address 15 8 received in the last request or data 0 for the next reply DPRX_AUX_BYTE1 AUX Transaction Byte 1 Register Address 0x0104 Direction RW Reset 0x00000000 Table 10 46 DPRX_AUX_BYTE1 Bits nm CCS Fumction O 31 8 Unused 7 0 BYTE Transaction address 7 1 received in the last request or data 1 for the next reply DPRX_AUX_BYTE2 AUX Transaction Byte 2 Register
70. DisplayPort IP Core User Guide GX subscribe UG 01131 2015 05 04 LJ Send Feedback 101 Innovation Drive San Jose CA 95134 al OPS BJAN www altera com TOC 2 Contents DisplayPort IP Core Quick Reference essseessessssesssossseesseessessssessseesseessesssses 1 1 Abo t This IP 0 T 2 1 Device Family E EE 2 2 IP Gore VeriBealiob acusa WR PENNE URN A AR ue hice Mi Re 2 2 Performance and Resource e aon iss aie ois nee nent an d 2 2 Sektor 3 1 Installing and Licensing IP Cones casisssciasssssncssesssnsnachssventsnesadasaisesnsdvesvsuinvessdesvesssncvachisvaninsasetansttesssonesvenias 3 1 OpenCore Plus IP Evaluation erret tette pee te be i eani see aes E be sese peg 3 1 Specifying IP Core Parameters and ODptIOBS annual 3 2 Simulatino the Bom Savana 3 2 Simulating with the ModelSim SIulatOt eres ed osa oaa bab ui sip ERR EH lie 3 3 Compiling the Full Design and Programming the PPGA ea giebt ri eee 3 3 KO WE 4 1 SOUrce OVERVIEW sn E mnt sente E tnt de sien dress terne io 4 1 Source Functional Description 4 2 Main BR ER savensasvarnaceucnnl eia EEA Eaa ES EEE ERNEA EEES 4 3 Embedded DisplayPort eDP Support ss sessseeessssseesessreesssstessserresssrtetssseressnrttesnsrretsrreesneresrrere 4 5 Source ParamMetersissssscsisssassscsssssnssosvecasessvsvesssssssssvesesnsdesdesesesce tonstssossesasesco cased sot vesnevssesvassssndss ACEN 4 5 Source TART AEG op
71. E 31 28 VCPSLOT31 VC payload ID or slot 31 27 24 VCPSLOT30 VC payload ID or slot 30 23 20 VCPSLOT29 VC payload ID or slot 29 19 16 VCPSLOT28 VC payload ID or slot 28 15 12 VCPSLOT27 VC payload ID or slot 27 11 8 VCPSLOT26 VC payload ID or slot 26 7 4 VCPSLOT25 VC payload ID or slot 25 3 0 VCPSLOT24 VC payload ID or slot 24 DPTX MST VCPTAB4 VC Payload ID Table Address 0x00a6 Direction RW Reset 0x00000000 Table 9 34 DPTX MST VCPTABA Bits mn ee CE 31 28 VCPSLOT39 VC payload ID or slot 39 27 24 VCPSLOT38 VC payload ID or slot 38 23 20 VCPSLOT37 VC payload ID or slot 37 19 16 VCPSLOT36 VC payload ID or slot 36 15 12 VCPSLOT35 VC payload ID or slot 35 DisplayPort Source Register Map and DPCD Locations CJ Send Feedback Altera Corporation 9 18 DPTX_MST_VCPTAB5 UG 01131 2015 05 04 mn ee CE 11 8 VCPSLOT34 VC payload ID or slot 34 7 4 VCPSLOT33 VC payload ID or slot 33 3 0 VCPSLOT32 VC payload ID or slot 32 DPTX_MST_VCPTAB5 VC Payload ID Table Address 0x00a7 Direction RW Reset 0x00000000 Table 9 35 DPTX_MST_VCPTABS Bits m o O 31 28 VCPSLOT47 VC payload ID or slot 47 27 24 VCPSLOT46 VC payload ID or slot 46 23 20 VCPSLOT45 VC payload ID or slot 45 19 16 VCPSLOT44 VC payload ID or slot 44 15 12 VCPSLOT43 VC payload ID or slot 43 11 8 VCPSLOT42 VC payload ID or slot 42 7 4 VCPSLOT41 VC payl
72. ER reset Input Reset for embedded controller Altera Corporation DisplayPort Sink CJ Send Feedback UG 01131 2015 05 04 Sink Interfaces 5 7 rx_mgmt_address 8 0 Input rx_mgmt_chipselect Input rx_mgmt_read Input 0 Input Avalon MM interface rx mgmt AV MM elk for embedded a un Input controller writedata 31 0 rx_mgmt_readdata 31 0 Outp ut rx mgmt waitrequest Outp ut rx mgmt IRO clk rx mgmt irq Output Interrupt for irq embedded controller Table 5 3 Transceiver Management Interface XCVI_ Clock ZOVE NOME OLR Input Transceiver mgmt dk management clock clk cal Clock N A clk cal Input Calibration clock rx link rate 1 0 Output rx link rate Outp 8bits 7 0 ut e dou O Transceiver link rate reconfi Conduit ES e econ eg ed Outp reconfiguration 5 5 ut handshaking rx reconfig ack Input rx reconfig busy Input Note Value of rx link rate 1 0 0 1 62Gbps 1 2 70Gbps 2 5 40Gbps value of rx link rate 8bits 7 0 0x06 1 62Gbps 0x0a 2 70Gbps 0x 14 5 40Gbps DisplayPort Sink Altera Corporation LJ Send Feedback UG 01131 5 8 Sink Interfaces 2015 05 04 Table 5 4 Video Interface v is the number of bits per color p is the pixels per clock 1 single 2 dual and 4 quad and n is the stream number rxN_vid_ Clock rxN_vid_clk Input Video clock clk rxN vid valid p 1 0 Output rxN vid sol Outp ut
73. K KK KK IRR RA RA IRA RA RA I A I A KR ke koe Disable DP130 link training to enable I2C programming bitec i2c write 0x58 0x04 0x00 J BOK RK KK IK KR RA AA AIA K K k K k CK k EK A Kk k kk k ke koe ke ke Program link bandwidth settings to HBR2 DPCD addr 0x00100 data 0x14 J BOK RK KK ECKC Ck RR AAA AA AAA A Kk kk k kk k ke koe ke ke bitec i2c write 0x58 Ox1c 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Ox1d 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Ox1e 0x00 DPCD add 7 0 0x00 bitec i2c write 0x58 Ox1f 0x14 DPCD data 0x14 J OK KK kk k k k k k k k k k AIA k Kk k k k kk ke kk koe ke ae Program lane count to 4 DPCD addr 0x00101 data 0x4 J BK RK KK RRR RR RA AA AA AA AIA AA A A k kk k AK k bitec i2c write 0x58 Ox1c 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Ox1d 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Oxle 0x01 DPCD addr 7 0 0x01 bitec i2c write 0x58 Ox1f 0x04 DPCD data 0x4 J BOK KKK kk k k AAA AA AR AAA IAA A k k k k ke ke ke koe ke ke Program VOD Level 1 and Pre emphasis Level 0 for lane 0 DPCD addr 0x00103 data 0x01 J BOK RK KK RRR ARR ECKCKCKC KK ECKCKCKC AA k kk k kk kk ke koe ke ke bitec i2c write 0x58 Oxlc 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Oxld 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Oxle 0x03 DPCD addr 7 0 0x03 bitec i2c write
74. NK CHANNEL CODING SET 0x0108 Yes Yes I2C SPEED CONTROL 0x0109 Yes EDP CONFIGURATION SET 0x010A Yes LINK_QUAL_LANEO_SE 0x010B Yes LINK QUAL LANE1 SF 0x010C Yes LINK_QUAL_LANE2_SE 0x010D Yes LINK OUAL LANE3 SF 0x010E Yes Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 Sink Supported DPCD Locations 10 35 2015 05 04 Location Name Address Without With Controller Controller TRAINING LANEO 1 SET2 0x010F Yes TRAINING_LANE2_3_SET2 0x0110 Yes MSTM_CTRL 0x0111 Yes AUDIO_DELAY 7 0 0x0112 Yes AUDIO_DELAY 15 8 0x0113 Yes AUDIO_DELAY 23 6 0x0114 Yes ADAPTER_CTRL 0x01A0 Yes BRANCH DEVICE CTRL 0x01A1 Yes PAYLOAD ALLOCATE SET 0x01C0 Yes PAYLOAD ALLOCATE START TIME SLOT 0x01C1 Yes PAYLOAD ALLOCATE TIME SLOT COUNT 0x01C2 Yes SINK COUNT 0x0200 Yes Yes DEVICE SERVICE IRO VECTOR 0x0201 Yes Yes LANEO 1 STATUS 0x0202 Yes Yes LANE2_3_STATUS 0x0203 Yes Yes LANE ALIGN STATUS UPDATED 0x0204 Yes Yes SINK STATUS 0x0205 Yes Yes ADJUST REQUEST LANEO 1 0x0206 Yes Yes ADJUST REQUEST LANE2 3 0x0207 Yes Yes SYMBOL ERROR COUNT LANEO 0x0210 Yes Yes SYMBOL ERROR COUNT LANE1 0x0212 Yes Yes SYMBOL ERROR COUNT LANE2 0x0214 Yes Yes SYMBOL ERROR COUNT LANE3 0x0216 Yes Ye
75. R2 IP Core Verification Before releasing a publicly available version of the DisplayPort IP core Altera runs a comprehensive verification suite in the current version of the Quartus II software These tests use standalone methods and the Qsys system integration tool to create the instance files These files are tested in simulation and hardware to confirm functionality Altera tests and verifies the DisplayPort IP core in hardware for different platforms and environments The DisplayPort IP core has been tested at VESA Plugtest events and passes the Unigraf DisplayPort Link Layer CTS tests Performance and Resource Utilization This section contains tables showing IP core variation size and performance examples The following table lists the resources and expected performance for selected variations The results were obtained using the Quartus II software v15 0 for the following devices e Arria V SAGXFB3H4F40C5 e Cyclone V SCGTFD9E5F35C7 e Stratix V SSGXEA7K2F40C2 e Arria 10 10AX115S2F45I2SGES Altera Corporation About This IP Core C Send Feedback UG 01131 T 2015 05 04 Performance and Resource Utilization 2 3 Table 2 2 DisplayPort IP Core FPGA Resource Utilization The table below shows the resource information for Arria V and Cyclone V devices using M10K Arria 10 and Stratix V devices using M20K The resources were obtained using the following parameter settings e Mode duplex e Maximum lane count
76. RST1 Writing this bit at 1 resets lane 1 bit error counter in register DPRX_BER_CNTO Always reads as 0 16 RSTO Writing this bit at 1 resets lane 0 bit error counter in register DPRX_BER_CNTO Always reads as 0 15 14 Unused 13 11 PATT3 Pattern selection for lane 3 e 000 No test pattern normal mode e 011 PRBS7 e 101 HBR2Compliance EYE pattern 10 8 PATT2 Pattern selection for lane 2 e 000 No test pattern normal mode e 011 PRBS7 e 101 HBR2 Compliance EYE pattern 785 PATT1 Pattern selection for lane 1 e 000 No test pattern normal mode e 011 PRBS7 e 101 HBR2 Compliance EYE pattern 4 2 PATTO Pattern selection for lane 0 e 000 No test pattern normal mode e 011 PRBS7 e 101 HBR2 Compliance EYE pattern Altera Corporation DisplayPort Sink Register Map and DPCD Locations G send Feedback UG 01131 m 2015 05 04 DPRX BER CNTO E CCS CE 1 0 CNTSEL Count selection e 00 Disparity and illegal comma codes e 01 Disparity e 10 Illegal comma codes e 11 Reserved DPRX_BER_CNTO These registers are exposed in DPCD locations syMBOL_ERROR_COUNT_LANEO and SYMBOL_ERROR_COUNT_LANE1 DPRX_BER_CNT1 These registers are exposed in DPCD locations syMBOL_ERROR_COUNT_LANE2 and SYMBOL ERROR COUNT LANE3 Sink Timestamp The Nios II processor can use this global free
77. RXO MSA VSW Bits S NN 31 15 Unused 14 0 MEM Main stream attribute vertical synchronization width DPRXO MSA HWIDTH TX control register DPRX0 Maa HWIDTH Address 0x002a Direction RO Reset 0x00000000 Table 10 20 DPRXO MSA HWIDTH Bits mn JI oseme 1 Faden O 31 16 Unused 15 0 oT Main stream attribute HWIDTH DPRXO_MSA_VHEIGHT Address 0x002b Direction RO Reset 0x00000000 Table 10 21 DPRXO_MSA_WHEIGHT Bits mn JI CS ee O 31 16 Unused 15 0 VHEIGHT Main stream attribute VHEIGHT DPRXO MSA MISCO Address 0x002c Direction RO Reset 0x00000000 Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRXO MSA MISC1 10 13 Table 10 22 DPRXO MSA MISCO Bits mn JI Sun non O 31 8 Unused 7 0 MISCO Main stream attribute MISCO DPRXO_MSA_MISC1 Address 0x002d Direction RO Reset 0x00000000 Table 10 23 DPRXO_MSA_MISC1 Bits mn JI CS ee O 31 8 Unused 7 0 MISCI Main stream attribute MISCI DPRXO VBID VB ID register DPRX0 VBID Address 0x002e Direction RO Reset 0x00000000 Table 10 24 DPRXO VBID Bits nm Ins TI NI 31 8 Unused 7 MSA LOCK 0 MSA unlocked 1 MSA locked on all lanes 6 VBPD Bock 0 VB ID unlocked 1 VB ID locked on all lanes 5 0 eo VB ID flags refer to the DisplayPort specification DisplayPort Sink Register Map and DPCD Locations Altera Corpo
78. STM_CTRL 0x0111 DPCP ADDR TX GTC VALUE7 0 0x0154 DPCP ADDR TX GTC VALUE15 8 0x0155 DPCP ADDR TX GTC VALUE23 16 0x0156 DPCP ADDR TX GTC VALUE31 24 0x0157 DPCP ADDR RX GTC VALUE PHASE SKF 0x0158 DPCP ADDR TX GTC FREQ LOCK DONE 0x0159 PAYLOAD ALLOCATE SET 0x01C0 DisplayPort Source Register Map and DPCD Locations E Send Feedback Altera Corporation 9 30 Source Supported DPCD Locations UG 01131 2015 05 04 PAYLOAD_ALLOCATE_START_TIME_SLO 0x01C1 PAYLOAD ALLOCATE TIME SLOT COUNT 0x01C2 SINK COUNT 0x0200 DEVICE SERVICE IRO VECTOR 0x0201 ANE0 1 STATUS 0x0202 LANE2 3 STATUS 0x0203 ANE ALIGN STATUS UPDATED 0x0204 SINK STATUS 0x0205 ADJUST REQUEST LANEO 1 0x0206 ADJUST REQUEST LANE2 3 0x0207 SYMBOL ERROR COUNT LANEO 0x0210 SYMBOL ERROR COUNT LANE1 0x0212 SYMBOL ERROR COUNT LANE2 0x0214 SYMBOL ERROR COUNT LANE3 0x0216 EST REQUEST 0x0218 EST LINK RATE 0x0219 EST LANE COUN 0x0220 PHY TEST PATTERN 0x0248 EST 80BIT CUSTOM PATTERN 0x0250 to 0x0259 0x0250 EST RESPONSE 0x0260 EST EDID CHECKSUM 0x0261 PAYLOAD TABLE UPDATE STATUS 0x02C0 VC PAYLOAD ID SLOT 1 0x02C1 to 0x02FF 0x02C1 SET POWER STATE 0x0600 DOWN REO 0x1000 to 0x1
79. TE Transaction data 1 for the next request or data 4 received in the last reply DPTX AUX BYTE5 AUX Transaction Byte 5 Register Address 0x0107 Direction RW Reset 0x00000000 DisplayPort Source Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 9 24 DPTX_AUX_BYTE6 2015 05 04 Table 9 46 DPTX AUX BYTES Bits RS We Il NN 31 8 Unused 7 0 BYTE Transaction data 2 for the next reguest or data 5 received in the last reply DPTX AUX BYTE6 AUX Transaction Byte 6 Register Address 0x0108 Direction RW Reset 0x00000000 Table 9 47 DPTX AUX BYTE6 Bits K CE C 31 8 Unused Transaction data 3 for the next reguest or data 6 received in the last reply DPTX AUX BYTE7 AUX Transaction Byte 7 Register Address 0x0109 Direction RW Reset 0x00000000 Table 9 48 DPTX AUX BYTE7 Bits RS ES CE Unused BYTHE Transaction data 4 for the next request or data 7 received in the last reply DPTX_AUX_BYTE8 AUX Transaction Byte 8 Register Address 0x010a Direction RW Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_AUX_BYTE9 9 25 Reset 0x00000000 Table 9 49 DPTX AUX BYTE8 Bits mn OS CE 31 8 Unused 7 0 BYTE Transaction data 5 for the next request or data 8 received in the last reply DPTX_AUX_BYTE9 AUX Transaction Byte 9 Register Address 0x010b D
80. TE6 Bits nm foo Benam MN 31 8 Unused 7 0 BYTE Transaction data 3 received in the last request or data 6 for the next reply DPRX_AUX_BYTE7 AUX Transaction Byte 7 Register Address 0x010a Direction RW Reset 0x00000000 Table 10 52 DPRX_AUX_BYTE7 Bits RS ES Fen O 31 8 Unused 7 0 BYTE Transaction data 4 received in the last request or data 7 for the next reply DPRX AUX BYTE8 AUX Transaction Byte 8 Register Address 0x010b Direction RW Reset 0x00000000 Table 10 53 DPRX AUX BYTES Bits RS CS Fmdon O 31 8 Unused 7 0 BYTE Transaction data 5 received in the last request or data 8 for the next reply DPRX_AUX_BYTE9 AUX Transaction Byte 9 Register Address 0x010c DisplayPort Sink Register Map and DPCD Locations Altera Corporation E Send Feedback UG 01131 10 28 DPRX_AUX_BYTE10 2015 05 04 Direction RW Reset 0x00000000 Table 10 54 DPRX_AUX_BYTE9 Bits CS CENE MN 31 8 Unused 7 0 BYTE Transaction data 6 received in the last request or data 9 for the next reply DPRX_AUX_BYTE10 AUX Transaction Byte 10 Register Address 0x010d Direction RW Reset 0x00000000 Table 10 55 DPRX_AUX_BYTE10 Bits mn o ame O CE 31 8 Unused 7 0 BYTE Transaction data 7 received in the last request or data 10 for the next reply DPRX_AUX_BYTE11 AUX Transaction Byte 11 Register Address 0x010e Direction RW Res
81. These signals are only used with MST mode You should tie the signals to VCC when the sink is not in MST mode The sink core keeps the rx_hpa signal deasserted if both the rx_cable_detect and rx_pwr_detect signals are not asserted AUX Debug Interface The AUX controller lets you capture all bytes sent from and received by the AUX channel which is useful for debugging The IP core supports a standard stream interface that can drive an Avalon ST FIFO component directly Table 5 10 Sink AUX Debug Interface Ports The table below describes the stream ports rx aux debug data 31 0 The sink AUX debug interface inserts a 1 us timestamp counter in bits 31 8 Bits 7 0 represent the bytes received or transmitted rx_aux_debug_valid Qualifies valid stream data rx aux debug sop Indicates the message packet s first byte DisplayPort Sink L Send Feedback Altera Corporation UG 01131 5 14 EDID Interface 2015 05 04 rx_aux_debug_eop Indicates the message packet s last byte The last byte should be ignored and is not part of the message rx aux debug err Indicates if the core detects an error in the current byte A EUR dobugecne Indicates the direction of the current byte 1 byte transmitted by the source 0 byte received from the sink EDID Interface You can use the Avalon MM EDID interface to access an on chip memory region containing the sink s EDID data The AUX sink controller reads an
82. Thread safe Yes Available from Yes ISR Include bee eios sys lUo n gt Return Dee rx idx Sink instance index 0 3 Description This function deasserts i e sets to 0 the RX HPD for 750 s You can use this function to send an IRO HPD pulse to the connected DisplayPort source Before invoking this function you must have invoked btc dprx hpd set with level 1 i e HPD must be set to 1 Example bte dprx pulse 0 Altera Corporation DisplayPort API Reference GJ send Feedback UG 01131 2015 05 04 Related Information e btc dprx hpd get on page 8 8 e btc dprx hpd set on page 8 9 btc_dprx_hpd_set Prototype btc_dprx_hpd_set 8 9 void btc_dprx_hpd_set BYTE rx_idx int level Thread safe Yes Available from ISR Yes Include lt btc dprx syslib h gt Return Parameters e rx idx Sink instance index 0 3 e level 0orl Description This function allows the controller to set the logic level of the RX HPD Example btc dprx hpd set 0 1 Related Information e btc dprx hpd get on page 8 8 btc dprx hpd pulse on page 8 8 btc dprx syslib add rx Prototype int btc dprx syslib add rx BYTE rx idx unsigned int rx base addr unsigned int rx irg id unsigned int rx irg num unsigned int rx num of sinks unsigned int options Thread safe No Available from ISR No Include lt lace eos sySlilo ia gt DisplayPort
83. UG 01131 2015 05 04 Sink Clock Tree 5 25 Figure 5 11 Sink Clock Tree Transceiver Block 270 135 81 67 5 40 5 MHz DisplayPort Decoder e b gt Recovered Clock i i i from Transceiver rx ss dk Main 13 HsSI0 He oro gt Audio din Data Decoder Link 0 Main HAAT DCO gt Secondary Link 1 Stream Data Front End Pixel Clock uum Decoder rxN vid dk Main gt HSSI02 gt DCO gt gt Link 2 Back End a Lech CH H Video FIFO Video Data Main gt Heim gt oero LS OT aux dk Link3 AUX Legend Controller gt rx ss ck m dk dk i p rxN vid clk Controller gt aux dk Interface 135 MHz gt Transceiver Reference Clock Signals from PLL or Dedicated Pin Related Information Clock Recovery Core on page 6 4 Provides more information about determining the optimum frequency DisplayPort Sink LJ Send Feedback Altera Corporation DisplayPort IP Core Hardware Demonstration 2015 05 04 UG 01131 amp Subscribe L J Send Feedback The Altera DisplayPort hardware demonstration evaluates the functionality of the DisplayPort IP core and provides a starting point for you to create your own design The example design uses a fully functional OpenCor
84. UX Transaction Byte 0 Register Address 0x0102 Direction RW Reset 0x00000000 Table 9 41 DPTX AUX BYTEO Bits KO function O 31 8 Unused 7 0 BYTE Transaction address 15 8 for the next request or data 0 received in the last reply DPTX_AUX_BYTE1 AUX Transaction Byte 1 Register Address 0x0103 Direction RW Reset 0x00000000 Table 9 42 DPTX_AUX_BYTE1 Bits BELLNM GNE Dmoe O 31 8 Unused 7 0 BYTE Transaction address 7 1 for the next request or data 1 received in the last reply DPTX_AUX_BYTE2 AUX Transaction Byte 2 Register Address 0x0104 Direction RW Reset 0x00000000 Table 9 43 DPTX_AUX_BYTE2 Bits mn TI COS oe O O 31 8 Unused Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_AUX_BYTE3 9 23 DC A EVE 7 0 ITE Transaction length 3 0 for the next request or data 2 received in the last reply refer to the DisplayPort specification for details DPTX AUX BYTE3 AUX Transaction Byte 3 Register Address 0x0105 Direction RW Reset 0x00000000 Table 9 44 DPTX AUX BYTES Bits nm K Fametion O Unused PUE Transaction data 0 for the next request or data 3 received in the last reply DPTX_AUX_BYTE4 AUX Transaction Byte 4 Register Address 0x0106 Direction RW Reset 0x00000000 Table 9 45 DPTX_AUX_BYTE4 Bits mn Suen O Function O 31 8 Unused 7 0 BY
85. X_MST_TAVG_TS Bits mn IL CCS nao O 31 Unused 30 24 TAVE TSS Target Average Timeslots for Stream 3 23 Unused 22 16 Tave TSZ Target Average Timeslots for Stream 2 15 Unused 14 8 TAVE TEI Target Average Timeslots for Stream 1 7 Unused 6 0 TAVE TSU Target Average Timeslots for Stream 0 TAVG_TSx is expressed as the fractional part of the number of timeslots per MTU occupied by Stream x times 64 assuming the allocated timeslots are the ceiling of this number For example if 4 7 timeslots MTU are occupied 5 timeslots MTU are allocated in the VCP ID table TAVG_TSx CEIL FRAC 4 7 64 CEIL 0 7 64 45 The achieved precision for Target Average Timeslots regulation is 1 64 0 015625 If TAvG TSx is set to a value greater than 63 VCP fill is sent to each allocated timeslot Source AUX Controller Interface This section describes the registers that connect with the AUX controller interface DPTX_AUX_CONTROL For transaction requests 1 Wait for READY TO TX to be 1 2 Write registers DPTX AUX COMMAND to DPTX AUX BYTE18 with the transaction command address length 0 15 fields and data payload 3 Write LENGTH with the transaction s total message length 3 for header 1 for length byte 0 to 16 for data bytes 4 The reguest transmission begins Altera Corporation DisplayPort Source Register Map and DPCD Locations G send Feedback UG 01131 Seen 2015 05 04 DPTX_AUX_CMD Fo
86. _WR state also checks whether another channel needs to be updated If yes the operation moves to the INIT state to start the operation for the next channel After all channels are reconfigured the RESET state initiates the reset to the transceiver reset module to complete the entire operation When the reset module is ready the operation moves to DONE and IDLE Altera Corporation DisplayPort API Reference 2015 05 04 UG 01131 amp Subscribe Send Feedback You can use the DisplayPort IP core to instantiate sources and sinks Source instantiations require an embedded controller Nios II processor or another controller to act as the policy maker Sink instantia tions greatly benefit from and may optionally use a controller Altera provides software for source and sink instantiations as two system libraries for the Nios II processor btc_dptx_syslib and btc dprx syslib respectively The IP core includes an example main program dp_demo_src main c which demonstrates basic system library use Using the Library The following figure describes a typical user application flow The user application must initialize the library as its first operation Next the application should initialize the instantiated devices sink and or source partly in the btc_dptx_syslib and btc_dprx_syslib data structures and partly in the user application You must also implement interrupt service routines ISRs to handle interrupts generated by the Displ
87. ack UG 01131 7 8 View the Results 2015 05 04 View the Results You can view the results in the ModelSim GUI by loading various do files in the Wave viewer 1 2 In the ModelSim Tcl window execute the dataset open command dataset open vsim wlf 3 4 Load the do files to view the waveforms refer back to Table 7 1 for a listing of the files Launch the ModelSim GUI with the vsim command Select View gt Open Wave files Figure 7 3 RX Reconfiguration Waveform tx analog reconfig reg tx analog reconfig ack tx analog reconfig busy In the timing diagram below rx link rate is set to 1 HBR When the core makes a request the rx reconfig reg port goes high The user logic asserts rx reconfig ack and then reconfigures the transceiver During reconfiguration the user logic holds rx reconfig busy high the user logic drives it low when reconfiguration completes xcvr_mgmt_clk rx_link_rate rx_reconfig_req rx_reconfig_ack rx_reconfig_busy tx link rate tx vod tx emp tx reconfig reg tx_reconfig_ack tx_reconfig_busy reconfig busy reconfig mgmt address LL LJ reconfig mgmt write reconfig_mgmt_writedata reconfig_mgmt_waitrequest reconfig_mgmt_read reconfig_mgmt_readdata Altera Corporation DisplayPort IP Core Sim
88. ains tuta nei md reb A o bebe pro p dent 9 8 DPTX0 MSA e IER EE 9 8 Source Link Voltage and Pre Emphasis Controls etos cit rectkeria sadi rh teen era best d ees Idee ah 9 9 DPTX PRE A EK 9 9 DPTX_PRE VOLT ds detente 9 10 DPIX PRE VOLT E 9 10 DPTX PRE VOLT eg 9 10 DP RR 9 11 Source Timestamp icici ss C 9 11 Source Audio RCI St CIS nan end ant at dei 9 12 Source GRE Registre edd 9 13 Source MST R gistets ase etes Ee che Ee Eege needs 9 14 Altera Corporation DPIX MS VP d tii dete mr ennemie 9 15 DPIX MSL VCP LAB lis tetra teet tera iris 9 15 DP TR MOT V GP TAB 2 cccaiisenavctinianctnanswnnweraanaiiieuntisandameamunaiuamebest 9 16 DPTX_MST_V CPTAB EE 9 17 DPIX MSE VOPDSRDA eue enr nou tei 9 17 DP TX MSL e E 9 18 DPIX MST VGCPDADOG citu near nu Nes 9 18 DPIX MSI VEPTABZ7 niet indienne nina 9 19 DPIX MST EN 9 20 Source AUX Controller M rite sement 9 20 DPIX AUX e AR RT E 9 20 DPIX AUX AR EE 9 21 IPIE AUX BY RE 9 22 DPIX AUX BYTE aas itor hatte rato teet ttt nt t n ntt 9 22 DPIX AUX BY qr Uc on ddd 9 22 DPIX ERKENNEN 9 23 DPIX AUX BYTBA sy ennui rates 9 23 DPIX AUX BYTE5 o rtt ater t aee re dt dea p hodna 9 23 DPIX AVX EC RE 9 24 DPIX AUX A A RE 9 24 DPTX AUX DY EBD annee ananas re Rae 9 24 DPIX AUX BY RE 9 25 DPTX AUX BYTELHU E 9 25 DPTX EECHER EEN RE 9 25 DPIX AUX D co T M ie 9 26 DPIX AUX BYLEL3 a2 tn eet ette eee dental 9
89. ate the color encoding format The color depth is indicated in Mtsco 7 5 7 0 MISCL 720 Source Clock Tree e 000 6 bpc e 001 8bpc e 010 10bpc e 011 12bpc e 100 16bpc For details about the encoding format refer to the DisplayPort v1 2 specification The source uses the following clocks Local pixel clock xN vid c1k which clocks video data into the IP core e Main link clock tx ss c1k which clocks data out of the IP core and into the high speed serial output HSSI components The main link clock is the output of the CMU PLL clock You can supply the CMU PLL with the single reference clock 135 MHz You can use other frequencies by changing the CMU PLL divider ratios and or reconfiguring the transceiver The 20 or 40 bit data fed to the HSSI is synchronized to a single HSSI 0 clock If you select the dual symbol mode option this clock is equal to the link rate divided by 20 270 135 or 81 MHz If you turn on quad symbol mode this clock is equal to the link rate divided by 40 135 67 5 or 40 5 MHz 16 MHz clock aux c1k which the IP core requires to encode or decode the AUX channel A separate clock c1k clocks the Avalon MM interface txN audio clk for the audio interface DisplayPort Source LJ Send Feedback Altera Corporation UG 01131
90. ath determines the video geometry required for the DisplayPort main stream attributes MSA which are sent once every vertical blanking interval Optionally the IP core can import a fixed MSA data parameter from an external port removing the measurement logic This feature is useful for embedded systems that only use known resolutions and synchronous pixel clocks Blank Generator Path The blank generator path determines when to send the blank start comma codes with their corresponding video data packets This path can operate in enhanced or standard framing mode Multiplexer The IP core multiplexes the packetized data MSA data and blank generator data into a single stream The combined data goes through 8B 10B encoding and is available as a 20 bit double rate or a 40 bit quad rate DisplayPort encoded video port The 20 or 40 bit port connects directly to the Altera high speed output transceiver During training periods the source can send the DisplayPort clock recovery and symbol lock test patterns training pattern 1 training pattern 2 and training pattern 3 respectively upon receiving the request from downstream DisplayPort sink The source also implements an AUX channel controller which you access using an embedded controller The embedded controller acts as an Avalon MM master and sends read write commands to the Avalon MM slave interface The IP core clocks the AUX channel using a 16 MHz clock input aux c1k Related Informa
91. ayPort core When initialization completes the user application should periodically invoke the library monitoring function Figure 8 1 Typical User Application Flow Initialize btc_dpxx_syslib y Initialize Source Sink y Initialize Source Sink ISR C y btc_dpxx_syslib Monitor 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01131 8 2 Using the L
92. bit MSB is placed in byte pes 2 bit 7 If the audio data size is less than 24 bits unused least signifi Byte 0 bits 7 0 cant bits LSB must be zero padded V Byte 3 bit 0 Validity flag U Byte 3 bit 1 User bit C Byte 3 bit 2 Channel status P Byte 3 bit 3 Parity bit PR Byte 3 bits 4 5 Preamble code and its correspondence with IEC 60958 preamble 00 Subframe 1 and start of the audio block 11101000 preamble 01 Subframel 1110010 preamble 10 Subframe 2 1110100 preamble R Byte3 bit 6 Reserved bit must be 0 DisplayPort Source Altera Corporation LJ Send Feedback UG 01131 4 18 MSA Interface 2015 05 04 SP Byte 3 bit 7 Sample present bit 1 Sample information is present and can be processed 0 Sample information is not present All one sample channels used or unused must have the same sample present bit value This bit is useful for situations in which 2 channel audio is transported over a 4 lane main link In this operation main link lanes 2 and 3 may or may not have the audio sample data This bit indicates whether the audio sample is present or not The source automatically generates the Audio InfoFrame and fills it with only information about the number of channels used Use the audio channel status to provide any information about the audio stream needed by downstream devices MSA Interface For applications that use a known video source signal you can remove the added
93. cify the number of audio channels supported Note To use this parameter you must turn on the Support secondary data channel parameter 6 bpc RGB or YCbCr 4 4 4 18 bpp Turn on to support 18 bpp decoding 8 bpc RGB or YCbCr 4 4 4 24 bpp 10 bpc RGB or YCbCr 4 4 4 30 bpp Turn on to support 24 bpp decoding Turn on to support 30 bpp decoding 12 bpc RGB or YCbCr 4 4 4 36 bpp Turn on to support 36 bpp decoding DisplayPort Sink L Send Feedback Altera Corporation 5 6 Sink Interfaces UG 01131 2015 05 04 16 bpc RGB or YCbCr 4 4 4 48 bpp Turn on to support 48 bpp decoding 8 bpc YCbCr 4 2 2 16 bpp Turn on to support 16 bpp decoding Reserved for future use 10 bpc YCbCr 4 2 2 20 bpp Turn on to support 20 bpp decoding Reserved for future use 12 bpc YCbCr 4 2 2 24 bpp Turn on to support 24 bpp decoding Reserved for future use 16 bpc YCbCr 4 2 2 32 bpp Turn on to support 32 bpp decoding Reserved for future use Support MST Turn on to enable multi stream support You have to turn on Enable GPU control to support MST Max stream count Select the maximum amount of streams supported 1 4 Sink Interfaces The following tables summarize the sink s interfaces Your instantiation contains only the interfaces that you have enabled Table 5 2 Controller Interface Clock Input Clock for embedded controller reset Reset P
94. ck kk bitec i2c write 0x58 0x07 0x05 J BR KK RK RK k k k k kk kk kk kk k k k k K K KKK AKA AKA kCK KCKCKCKCKCK AX AXA AXA AXA kc k k ck k ck ck ck ck ck kk Set EO level to 13dB HBR2 for lane 2 DP130 reg 0x09 data 0x05 J BR RR RK RK k k k k K k k k K k k k K K KA KKK AAA AAA AAA KE KCKCkCK KCKCKCK CKCK KC k KC k k ck k ck ck ck ck ck ck ck kk bitec i2c write 0x58 0x09 0x05 BR RK k k k k k k kk kk kk kk kk kCKCkCk KCKCKCk KCKCKCKCKCKCKCkCKCKCKCK KCKCKCk KCKCKCk KCKCKCK KCkCkCk k ck ck ck ck ck ck ck kk Set EQ level to 13dB HBR2 for lane 3 DP130 reg 0x0b data 0x05 J BR KR RK RK k k k k k k kk kk k RK K K RK kCKCkCK kCKCKCKCKCK KCK KE KE KE KE Ck Ck k ck k ck ck ck ck ck ck ck bitec i2c write 0x58 0x0b 0x05 DisplayPort IP Core Hardware Demonstration LJ Send Feedback Altera Corporation UG 01131 6 22 Design Walkthrough 2015 05 04 Example 6 2 Example Hardware Setup Figure 6 10 Example Hardware Setup Using FPGA Development Board Bitec Daughter Card and Cables Related Information e Altera Stratix V GX FPGA Development Kit e Arria V GX FPGA Starter Kit e Cyclone V GT FPGA Development Kit e Arria 10 FPGA Development Kit Design Walkthrough Setting up and running the DisplayPort hardware demonstration consists of the following steps A variety of scripts automate these steps 1 Set up the hardware 2 Copy the design files to your working directory 3 Build the FPGA
95. core from the library Altera provides an integrated parameter editor that allows you to customize the DisplayPort IP core to support a wide variety of applications The parameter editor guides you through the setting of parameter values and selection of optional ports Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license Some Altera MegaCore IP functions require that you purchase a separate license for production use However the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software After you are satisfied with functionality and perfformance visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 3 1 IP Core Installation Path 71 acds _ quartus Contains the Quartus II software ip Contains the Altera IP Library and third party IP cores altera Contains the Altera IP Library source code _ a IP core name gt Contains the IP core source files Note The default IP installation directory on Windows is lt drive gt altera lt version number gt on Linux it is home directory gt laltera version number Related Information e Altera Licensing Site e Altera Software Installation and Licensing Manual OpenCore Plus IP Evaluation Altera s free
96. crambler disabled 6 5 Unused 4 0 DP Lane count e 00001 1 e 00010 2 e 00100 4 This register is also available in read only mode when not using a controller Altera Corporation DisplayPort Sink Register Map and DPCD Locations E Send Feedback UG 01131 2015 05 04 DPRX_RX_STATUS 10 3 Table 10 3 DPRX_RX_CONTROL Bits Non Controller Mode nm ECS be O 31 24 Unused 23 16 te Main link rate expressed as multiples of 270 Mbps 0x06 1 62 Gbps e 0x0a 2 7 Gbps 0x14 5 4 Gbps 15 5 Unused 4 0 TAN COUNT Lane count e 00001 1 e 0001022 e 00100 4 DPRX_RX_STATUS GXB_BUSY connects to the rx_reconfig_busy input port Address 0x0001 Direction CRO Reset 0x00000000 Table 10 4 DPRX_RX_STATUS Bits m een OS 31 18 Unused 17 EE 0 Transceiver not busy 1 Transceiver busy 16 pa Ose This flag can be reset by writing it to 1 0 Symbol lock on all lanes in use 1 Symbol lock lost on one or more of the used lanes 15 8 Unused 7 SYM LOCKS 0 Symbol unlocked lane 3 1 Symbol locked lane 3 DisplayPort Sink Register Map and DPCD Locations CJ Send Feedback Altera Corporation 10 4 DPRX_RX_STATUS UG 01131 2015 05 04 mn CCS een O 6 Oe 0 Symbol unlocked lane 2 1 Symbol locked lane 2 5 SEM BODEM 0 Symbol unlocked lane 1 1 Symbol locked lane 1 4 SM LOCKO 0 Symbol unlocked lane 0 1 Symbol locked lane 0 3 CR_LOCK3
97. d writes to this memory region according to traffic on the AUX channel The Avalon MM interface uses an 8 bit address with an 8 bit data bus The interface assumes a read latency of 1 Note The IP core does not instantiate this interface if your design uses a controller to control the sink for instance when you turn on the Enable GPU control parameter Refer to the VESA Enhanced Extended Display Identification Data Implementation Guide for more information Debugging Interface Link Parameters Interface The sink provides link level data for debugging and configuring external components using the rx_lane_count port Video Stream Out Interface This interface provides access to the post scrambler DisplayPort data which is useful for low level debugging source equipment The 8 bit symbols received are organized as shown in the following tables where n increases with time at each main link clock cycle by 2 for dual symbol mode or by 4 for quad symbol mode Table 5 11 rxN stream data Dual Symbol Mode 63 56 Lane 3 symbol n 1 55 48 Lane 3 symbol n 47 40 Lane 2 symbol n 1 Altera Corporation DisplayPort Sink C Send Feedback UG 01131 2015 05 04 Video Stream Out Interface 5 15 a ne Se XI 39 32 Lane 2 symbol n 31 24 Lane 1 symbol n 1 23 16 Lane 1 symbol n 15 8 Lane 0 symbol n 1 7 0 Lane 0 symbol n Table 5 12 rxN_stream_data Quad Symbol Mode
98. ders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 4 2 Source Functional Description Source Functional Description UG 01131 2015 05 04 The DisplayPort source has a complete set of parameters for optimizing device resources The DisplayPort source consists of a DisplayPort encoder block a transceiver management block and a controller interface block with an Avalon MM interface for connecting with an embedded controller such as a Nios II processor You configure the ports using an RTL wrapper instantiation or by implementing the IP core as a Qsys component Figure 4 2 DisplayPort Source Top Level Block Diagram txN_video_in gt txN_vid_clk txN_audio 39 txN_audio_ ck D aux 4t 9 aux dk txN_ss
99. design 4 Build the software download it into the FPGA and run the software 5 Power up the DisplayPort monitor and view the results Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Set Up the Hardware Set up the hardware using the following steps Set Up the Hardware 6 23 1 Connect the Bitec daughter card to the FPGA development board 2 Connect the development board to your PC using a USB cable Note The FPGA development board has an On Board USB Blaster II connection If your version of the board does not have this connection you can use an external USB Blaster cable Refer to the documentation for your board for more information 3 Connect a DisplayPort cable from the DisplayPort TX on the Bitec HSMC daughter card to a Display Port monitor do not power up the monitor 4 Power up the development board 5 Connect one end of a DisplayPort cable to your PC do not connect the other end to anything Copy the Design Files to Your Working Directory In this step you copy the hardware demonstration files to your working directory Copy the files using the command cp r IP root directory gt altera altera dp hw demo lt device board working directory where device board is av sk 4k for Arria V GX starter kit cv for Cyclone V GT development kit and sv for Stratix V development kit Your working directory should contain the files shown in the
100. e int btc_dptx_edid_read BYTE data Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters data Pointer for data to be read Description This function reads the complete EDID of the connected DisplayPort sink data must be able to contain the whole EDID allow for 512 bytes Example btc dptx edid read pdata Related Information btc dptx edid block read on page 8 15 btc dptx fast link training ii o a CGCCDJULIAlAAAOOGG G LULUAALDZALLLLLPi LEUEXAXA ALELZO Prototype int btc dptx fast link training unsigned int link rate unsigned int lane count unsigned int volt swing unsigned int pre emph unsigned int new cfg Thread safe No Available from ISR Yes Include loto cots mais gt Return 0 success 1 fail Altera Corporation DisplayPort API Reference G send Feedback UG 01131 2015 05 04 EE Parameters e link rate Link rate Gbps 0 1 62 1 2 70 2 5 40 e lane _count l 2 or 4 H volt swing 1 2 or 3 H pre emph 0 1 2 or 3 e new cfg ignore the other parameters 1 use provided parameters btc_dptx_link_training 8 17 Description This function performs fast link training with the connected DisplayPort sink When performing fast link training the IP core outputs training pattern 1 for 1 ms followed by training pattern 2 for 1 ms The function ret
101. e 5 19 assign vid h sync rx_vid_h_sync assign vid_de rx_vid_valid assign vid v sync rx vid v sync RX Transceiver Interface The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core The DisplayPort IP core uses a soft 8B 10B decoder This interface receives RX transceiver recovered data rx parallel data in either dual symbol 20 bit or quad symbol 40 bit mode and drives the digital reset rx digitalreset analog reset rx analogreset and controls the CDR circuitry locking mode Transceiver Reconfiguration Interface You can reconfigure the transceiver to accept a single reference clock of 135 MHz for all bit rates RBR HBR and HBR2 During run time you can reconfigure the transceiver to operate in either one of the bit rate by changing RX CDR PLLs divider ratio When the IP core makes a request the rx reconfig reg port goes high The user logic asserts rx_reconfig_ack and then reconfigures the transceiver During reconfiguration the user logic holds rx_reconfig_busy high The user logic drives it low when reconfiguration completes Note The transceiver requires a reconfiguration controller Reset the transceiver to a default state upon power up Related Information e AN 645 Dynamic Reconfiguration of PMA Controls in Stratix V Devices Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Stratix V Physical Media Attachment
102. e CRC B f1bb 88 MISCO 46 MISC1 68 The Nios II AUX printout shows each message packet on a separate line The first field is the incremental timestamp in microseconds e The second field indicates whether the message packet is from or to the DisplayPort sink SNK or source SRC e The next two fields show the request and response headers and payloads The DPCD address field on request messages are decoded into the respective DPCD location names When connected and enabled usi ER PB 0 on the development board illuminates to indicate that the DisplayPort receiver has locked correctly DisplayPort IP Core Hardware Demonstration E Send Feedback Altera Corporation DisplayPort IP Core Simulation Example 2015 05 04 UG 01131 amp Subscribe Send Feedback The Altera DisplayPort simulation example allows you to evaluate the functionality of the DisplayPort IP Core and provides a starting point for you to create your own simulation This example targets the ModelSim SE simulator The simulation example instantiates the DisplayPort IP core with default settings TX and RX enabled and 8 bits per color The core has the Support CTS test automation parameter turned on which is required for the simulation to pass The test harness instantiates the design under test DUT and a VGA driver It also generates the clocks and top level stimulus The design manipulates the tx mgmt interface in the main loop to establi
103. e DCFIFO crosses the data into the main link clock domain cx ss clk generated by the transceiver which can be 270 135 81 67 5 or 40 5 MHz depending on the actual main link rate requested and the symbols per clock 3 The gearbox resamples the video data according to the specified color depth You can optimize the gearbox by implementing fewer color depths For example you can reduce the resources required to implement the system by supporting only the color depths you need instead of the complete set of color depths specified in the DisplayPort specification 4 TheIP core packetizes the re sampled data The DisplayPort specification requires data to be sent in a transfer unit TU which can be 32 to 64 link symbols long To reduce complexity the DisplayPort source uses a fixed 64 symbol TU The specification also requires that the video data be evenly distrib uted within the TUs composing a full active video line A throttle function distributes the data and regulates it to ensure that the TUs leaving the IP core are evenly packed Note A minimal DisplayPort system should support both 6 and 8 bpc The VESA DisplayPort specifica tion requires support for a mandatory VGA fail safe mode 640 x 480 at 6 bpc The packetizer punctuates the outgoing 16 bit data stream with the correct packet comma codes Internally the packetizer uses a symbol and a TU counter to ensure that it respects the TU boundaries Measurement Path The measurement p
104. e Plus evaluation version giving you the freedom to explore the core and understand its performance in hardware The design is 4Kp60 capable and performs a loop through for a standard DisplayPort video stream You connect a DisplayPort enabled device such as a graphics card with DisplayPort interface to the Transceiver Native PHY RX and the DisplayPort sink input The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data You require the clock recovery feature to produce video without using a frame buffer The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX The DisplayPort source port of the HSMC daughter card transmits the image to a monitor Note If you use another Altera development board you must change the device assignments and the pin assignments You make these changes in the assignments tcl file If you use another DisplayPort daughter card you must change the pin assignments Qsys system and software O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks
105. e in either one of the bit rate by changing TX CMU PLL divide ratio When the IP core makes a request the tx reconfig reg port goes high The user logic asserts tx_reconfig_ack and then reconfigures the transceiver During reconfiguration the user logic holds tx_reconfig_busy high The user logic drives it low when reconfiguration completes Note The transceiver requires a reconfiguration controller Reset the transceiver to a default state upon power up Related Information e AN 645 Dynamic Reconfiguration of PMA Controls in Stratix V Devices Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Stratix V Physical Media Attachment PMA controls dynamically e Altera Transceiver PHY IP Core User Guide Provides more information about how to reconfigure the transceiver for 28 nm devices e AN 676 Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Arria V Physical Media Attachment PMA controls dynamically e AN 678 High Speed Link Tuning Using Signal Conditioning Circuitry Provides more information about link tuning e Arria 10 Transceiver PHY User Guide Provides more information about how to reconfigure the transceiver for Arria 10 devices Transceiver Analog Reconfiguration Interface The tx_analog_reconfig interface uses the tx_vod a
106. ead dod dn anneau 8 12 bic dpix ac DE WII mens cid pc asi REN aD d odi R E CI ee Hic NEE CN nd p a REN RE 8 13 pte dptx aux ME 8 13 Dte dpt atx SPETIB ON ne moe epee ces ee a 8 14 bte Ap basoa delsi dak odn st a dns 8 15 bic dptz edid block Fed dd tee ON Rs 8 15 BIC pix PA eet ee eee ee em a 8 16 bt dpEc Tasb link EE odd ooo o noo siu du ho koa ka nl 8 16 Dic dptx link URAN E nn beate ean ov oto E oer peru t REE DRE 8 17 bte dpt dice odi le MM O O P yvision n aa e T nE 8 18 Dte doe Tu ET 8 18 bic dpt ele 8 19 btc sd pt fest QUtOTI ante ee t SEI REM GR EI MERERI AT ERROREM ak SEU I EMEN ERIS 8 19 bic dpix video enable aei bos ER HHVN NIV WI IH PERI DA A0 nae anes 8 20 Dle sv Additional T VUES Sn en dana ubude Deed ond uci 8 20 btc_dprx_syslib Supported DPCD EE sine ide tue tec 8 20 DisplayPort Source Register Map and DPCD Locations 9 1 Source General RODISEBES sednou needed einen one uri iu 9 1 DPTX_IX CONTRO EE 9 1 IERCH KEN HR 9 3 Source MSA Mut cm 9 4 DPTX0 MSA MVIDY EE 9 4 DDT MS MV ennemie name satin 9 4 DPIX0 MSA RR RER EE 9 4 DPTXOMSALV TOTAL nn ann Nains 9 5 MEY PPX UNT M SNL 9 5 Ip e M HSV T dote 9 5 DPTX0 KE RE 9 6 DPTXO MSA VSTART WEE 9 6 MP EXO MSA VS EE 9 6 DPTXO MSA E 9 7 DPTX0 MSA IWID ILEH nineteenth n eR RUE RESI EREE aea REEF REEF SUE 9 7 DPIX0 MSA VHEIGH WEE 9 7 DPTXO MSA E DE 9 8 DPTX0_ MS MISC a Sn pA ret
107. ecific applications where provided e Specify parameters defining the IP core functionality port configurations and device specific features e Specify options for generation of a timing netlist simulation model testbench or example design where applicable e Specify options for processing the IP core files in other EDA tools Click Generate to generate the IP core and supporting files including simulation models Click Close when file generation completes Click Finish If you generate the DisplayPort IP core instance in a Quartus II project you are prompted to add Quartus II IP File qip and Quartus II Simulation IP File sip to the current Quartus II project SON Simulating the Design You can simulate your DisplayPort IP core variation using the simulation model that the Quartus II software generates The simulation model files are generated in vendor specific subdirectories of your project directory The DisplayPort IP core includes a simulation example The following sections teach you how to simulate the generated DisplayPort IP core variation with the generated simulation model Altera Corporation Getting Started C Send Feedback UG 01131 2015 05 04 Simulating with the ModelSim Simulator 3 3 Related Information DisplayPort IP Core Simulation Example on page 7 1 The Altera DisplayPort simulation example allows you to evaluate the functionality of the DisplayPort IP Core and provides a starting point
108. ed and rxN_vid_data The following table describes how to connect the CVI and DisplayPort sink signals Table 5 13 Connecting CVI Signals to DisplayPort Sink Stream 0 Signals vid_data rx_vid_data Video data vid_datavalid Drive high because the video data is not oversam pled vid_t Drive low because the video data is progressive vid locked zx vid locked The core asserts this signal when a stable stream is present vid_de rx_vid_valid Indicates the active picture region of a line vael Im syne eeh The rx_vid_eol signal generates the vid_h_sync pulse by delaying it by 1 clock cycle to appear in the horizontal blanking period after the active video ends rx_vid_valid is deasserted vid_v_sync rx_vid_eof The rx_vid_eof signal generates the vid_v_sync pulse by delaying it by 1 clock cycle to appear in the vertical blanking period after the active video ends rx vid validis deasserted Example 5 1 Verilog HDL CVI DisplayPort Sink Example CVI V sync and H sync are derived from delayed versions of the eol and eof signals always begin posedge clk_video rx vid h sync lt rx_vid_eol rx vid v sync lt rx vid eof end assign vid data rx vid data assign vid datavalid 1 bl assign vid f 1 b0 assign vid locked rx vid locked Altera Corporation DisplayPort Sink G send Feedback UG 01131 2015 05 04 RX Transceiver Interfac
109. ed HBR2 support for Arria V and Arria V GZ devices e Added information about eDP support e Updated the API reference May 2013 13 0 e Added information on audio support e Added HBR2 support for Stratix V devices e Added information on secondary data support February 2013 12 1 SP1 Beta Second beta release e Updated the filenames for the hardware demonstration and simulation example e Added chapter describing the IP core s compilation example e Miscellaneous updates December 2012 12 1 Beta Initial beta release Additional Information LJ Send Feedback Altera Corporation
110. eguest DPTX AUX RESET Address 0x0117 Direction WO Reset 0x00000000 Table 9 60 DPTX AUX RESET Bits nm o oiam O K 31 1 Unused 0 CLEAR Asserting CLEAR resets the AUX Controller state machine e 0 No action e 1 AUX Controller reset Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Source Supported DPCD Locations Source Supported DPCD Locations 9 29 The following table describes the DPCD locations or location groups that are supported in DisplayPort source instantiations Table 9 61 DPCD Locations DPCD_REV 0x0000 MAX_LINK_RATE 0x0001 AX LANE COUNT 0x0002 TRAINING AUX RD INTERVAL 0x000E MST CAP 0x0021 GUID 0x0030 DPCP ADDR RX GTC VALUE7 0 0x0054 DPCP ADDR RX GTC VALUE15 8 0x0055 DPCP ADDR RX GTC VALUE23 16 0x0056 DPCP ADDR RX GTC VALUE31 24 0x0057 DPCP ADDR RX GTC MSTR REO 0x0058 DPCP ADDR RX GTC FREC LOCK DONE 0x0059 LINK BW SET 0x0100 LANE COUNT SET 0x0101 RAINING PATTERN SET 0x0102 RAINING LANEO SET 0x0103 RAINING_LANE1_SET 0x0104 RAINING_LANE2_SET 0x0105 RAINING_LANE3_SET 0x0106 DOWNSPREAD_CTRL 0x0107
111. eiver Conduit xcvr meme tx_digitalreset n Output Resets the digital TX clk 1201 portion of TX transceiver Conduit N A tx_analogreset n Output Resets the analog TX 1 0 portion of TX transceiver Conduit N A tx cal busy n 1 0 Input Calibration in progress signal from TX transceiver Conduit N A tx pll locked Input PLL locked signal from TX transceiver Controller Interface The controller interface allows you to control the source from an external or on chip controller such as the Nios II processor The controller can control the DisplayPort link parameters and the AUX channel controller The AUX channel controller interface works with a simple serial port type peripheral that operates in a polled mode Because the DisplayPort AUX protocol is a master slave interface the DisplayPort source the master starts a transaction by sending a request and then waits for a reply from the attached sink The controller interface includes a single interrupt source The interrupt notifies the controller of an HPD signal state change Your system can interrogate the DP TX STATUS register to determine the cause of the interrupt Writing to the pP TX STATUS register clears the pending interrupt event Related Information e Multiplexer on page 4 4 e DisplayPort Source Register Map and DPCD Locations on page 9 1 DisplayPort source instantiations require an embedded controller Nios II processor or another controller to act a
112. ent software performs the link training management Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 DisplayPort IP Core Hardware Demonstration 6 3 Figure 6 2 Hardware Demonstration Block Diagram Video Transceiver PLL PLL Control Clock 60 MHz Video Clock AUX Clock 135 MHz 160 MHz 16 MHz Qsys System control qsys RX Clock E DisplayPort IP Core Recover RX E Biter vn Native ER DisplayPort Core gt PH Ty A A Management RX TX Nios II Avalon MM Processor AUX Debug RX TX Avalon ST Y y FSM Transceiver Reconfiguration During operation you can adjust the DisplayPort source resolution graphics card from the PC and observe the effect on the IP core The Nios II software prints the source and sink AUX channel activity Press a push button to print the current TX and RX MSAs Table 6 1 LED Function The development board user LEDs illuminate to indicate the function described in the table below USER_LED 0 This LED indicates that source is successfully lane trained and is sending video rxN_vid_locked drives this LED This LED turns off if the source is not driving good video USER_LED 1 This LED illuminates for 1 lane designs USER_LED 2 This LED illuminates for 2 lane designs USER LED 3
113. et 0x00000000 Table 10 56 DPRX_AUX_BYTE11 Bits ptf mme function O 31 8 Unused 7 0 BYTE Transaction data 8 received in the last request or data 11 for the next reply Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_AUX_BYTE12 10 29 DPRX_AUX_BYTE12 AUX Transaction Byte 12 Register Address 0x010f Direction RW Reset 0x00000000 Table 10 57 DPRX_AUX_BYTE12 Bits nm fo eiename TI moien O 31 8 Unused 7 0 BYTE Transaction data 9 received in the last request or data 12 for the next reply DPRX_AUX_BYTE13 AUX Transaction Byte 13 Register Address 0x0110 Direction RW Reset 000000000 Table 10 58 DPRX_AUX_BYTE13 Bits 5 o mime o Fon O 31 8 Unused 7 0 BYTE Transaction data 10 received in the last request or data 13 for the next reply DPRX_AUX_BYTE14 AUX Transaction Byte 14 Register Address 0x0111 Direction RW Reset 0x00000000 Table 10 59 DPRX_AUX_BYTE14 Bits O hmm O 31 8 Unused DisplayPort Sink Register Map and DPCD Locations Altera Corporation E Send Feedback UG 01131 10 30 DPRX_AUX_BYTE15 2015 05 04 DCE AC VE 7 0 s Transaction data 11 received in the last reguest or data 14 for the next reply DPRX AUX BYTE15 AUX Transaction Byte 15 Register Address 0x0112 Direction RW Reset 0x00000000 Table 10 60 DPRX AUX BYTE15 Bits RS gw Am O
114. ettings reconfig mgmt hw ctrl v Reconfiguration manager top level Kee E reconfig_mgmt_write v Reconfiguration manager FSM for a single write design files command clk gen v Clock generation file freq check sv Top level file for the frequency checker rx freq check sv RX frequency checker tx freq check sv TX frequency checker DisplayPort IP Core Simulation Example Altera Corporation CJ Send Feedback UG 01131 7 6 Generate the IP Simulation Files and Scripts and Compile and Simulate 2015 05 04 vga_driver v VGA driver generates a test image lt prefix gt _ dp v IP Catalog variant for the DisplayPort IP Core prefix xevr_reconfig v IP Catalog variant for the transceiver reconfiguration IP Catalog files COTE prefix native phy nx v IP Catalog variant for the RX transceiver prefix native phy DA IP Catalog variant for the TX transceiver runall sh This script generates the IP simulation files and scripts and compiles and simulates them Scripts msim dp tcl Compiles and simulates the design in the ModelSim software Waveform do all do Waveform that shows a combination of all waveforms reconfig do Waveform that shows the signals involved in reconfi guring the transceiver rx video out do Waveform that shows the rx video out signals from files the DisplayPort IP core mapped to the CVI input tx video in do Waveform that shows the tx vid v sy
115. f for Stream 2 e 0x0080 through 0x008f for Stream 3 Note Only registers for Stream 0 are listed in the following sections Registers for Stream 0 are also available in non controller mode Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRXO MSA MVID 10 9 DPRXO MSA MVID Address 0x0020 Direction RO Reset 0x00000000 Table 10 10 DPRXO MSA MVID Bits mn JI Sun non O 31 24 Unused 23 0 MYLD Main stream attribute MVID DPRXO_MSA_NVID Address 0x0021 Direction RO Reset 0x00000000 Table 10 11 DPRXO_MSA_NVID Bits mn JI CS ee O 31 24 Unused 23 0 VID Main stream attribute NVID DPRXO MSA HTOTAL Address 0x0022 Direction RO Reset 0x00000000 Table 10 12 DPRXO MSA HTOTAL Bits mn CS Faden O 31 16 Unused 15 0 BO Main stream attribute HTOTAL DPRXO MSA VTOTAL Address 0x0023 Direction RO DisplayPort Sink Register Map and DPCD Locations Altera Corporation Ei Send Feedback 10 10 DPRXO MSA HSP Reset 0x00000000 Table 10 13 DPRXO MSA VTOTAL Bits UG 01131 2015 05 04 mn JI Sun 0 Faden O 31 16 Unused 15 0 DPRXO MSA HSP MSA horizontal synchronization polarity register DPRX0 MSA HSP Address 0x0024 Direction RO Reset 0x00000000 Table 10 14 DPRXO MSA HSP Bits Main stream attribute VTOTAL mto ee Fen O 31 1 Unused 0 HSP Main stream attribute horiz
116. following table DisplayPort IP Core Hardware Demonstration Altera Corporation E Send Feedback 6 24 Copy the Design Files to Your Working Directory Table 6 6 Hardware Demonstration Files UG 01131 2015 05 04 Files are named with lt prefix gt _ lt name gt lt extension gt where lt prefix gt represents the device av for Arria V devices cv for Cyclone V devices and sv for Stratix V devices Verilog HDL design files top v Top level design file bitec_reconfig_alt_ lt prefix gt v Reconfiguration manager top level This module is a high level FSM that generates the control signals to reconfigure the VOD and pre emphasis selects the PLL reference clock and reconfigures clock divider setting It loops through all the channels and transceiver settings altera_pll_reconfig_core v altera_pll_reconfig_mif_reader v altera_pll_reconfig_top v bitec_cc_fifo v bitec_cc_pulse v bitec_clkrev v bitec_fpll_cntrl v bitec_fpll_reconf v bitec loop cntrl v bitec vsyncgen v clkrec pll lt prefix gt v Clock recovery core encrypted design files IP Catalog files video_pll lt prefix gt v pll 135 v gxb reconfig v gxb reset v gxb rx v gxb tx v IP Catalog variants for the various helper IP cores Qsys system control qsys Osys system file Altera Corporation DisplayPort IP Core Hardware Demonstration G send Feedback UG 01131 2015 05 04 Build the FPGA Design 6 25
117. for irq 7 embedded controller DisplayPort Source Altera Corporation CJ Send Feedback 4 8 Source Interfaces Table 4 3 Transceiver Management Interface nis the number of TX lanes UG 01131 2015 05 04 SCHT Clock xcvr mgmt Plk Input Transceiver mgmt_clk management clock clk_cal Clock N A clk_cal Input A 50 MHz calibration clock input This clock must be synchronous to the clock used for the Transceiver Reconfiguration block xvcr mgmt clk external to the Display Port sink tx vod 2n 1 0 Output tx emp 2n 1 0 Outp ut tx_ Transceiver analog i xcvr mgmt tx analog reconfig req Outp analog Conduit reconfiguration clk ut y reconfig handshaking tx_analog_reconfig_ack Input tx_analog_reconfig_ Input busy tx_link_rate 1 0 Output tx_link_rate_ Outp 8bits 7 0 ut Transceiver link rate tx_ xcvr mgmt reconfig Condit clk tx_reconfig_req Input FOR ion e handshaking tx_reconfig_ack Input tx_reconfig_busy Input Note Value of tx_link_rate 1 0 0 1 62Gbps 1 2 70Gbps 2 5 40Gbps value of tx_link_rate_8bits 7 0 0x06 1 62Gbps 0x0a 2 70Gbps 0x 14 5 40Gbps Note For devices using a 50 MHz xcvr_mgmt_c1k clock connect the same clock directly also to the clk cal signal For devices using a 100 MHz xcvr mgmt c1k clock connect the same clock to clk cal signal through a by 2 divider Altera Corporation DisplayPort Source C Send Feedback UG 011
118. for you to create your own simulation This example targets the ModelSim SE simulator Simulating with the ModelSim Simulator To simulate using the Mentor Graphics ModelSim simulator perform the following steps 1 Start the ModelSim simulator 2 In ModelSim change directory to the project simulation directory lt variation gt _sim mentor 3 Type the following commands to set up the required libraries and compile the generated simulation model do msim_setup tcl ld run all Compiling the Full Design and Programming the FPGA You can use the Start Compilation command on the Processing menu in the Ouartus II software to compile your design After successfully compiling your design program the targeted Altera device with the Programmer and verify the design in hardware Related Information e Quartus II Incremental Compilation for Hierarchical and Team Based Design Provides more information about compiling the design e Quartus II Programmer Provides more information about programming the device Getting Started Altera Corporation CJ Send Feedback DisplayPort Source 2015 05 04 UG 01131 amp Subscribe Send Feedback Source Overview The DisplayPort source has a scalable main link with 1 2 or 4 lanes for a total up to 21 6 Gbps bandwidth A bidirectional AUX channel with 1 Mbps Manchester encoding provides side band communication Figure 4 1 DisplayPort Source Lane 0 Data 1 62 2 7 or 5 4 Gbps La
119. ghter card Main Link TI DisplayPort L P Connector Redriver i E ud z So u rce Main Link wm TI i DisplayPort jn H Connector Lal Sink Redriver The following figures illustrate the schematic diagrams of the Bitec HSMC daughter card Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Required Hardware Figure 6 7 HSMC Connector Schematic Diagram 6 15 EEN DO 11 0 moo feo WHe mum gt L oso De a x D3 Papa DOC X0 D42 D43 4 3481 88v dE Lei c xD Da 05 48 lt RX_ENA PET D45 X ps DDK JDA pe D47 aw N aw 12V D De rl bas E 34 D10 on RX SCL DDC gt t D50 D51 Hi 12V HI 12 H pd on e xi om x 14 15 d x31 Lm DM Gelee aiy rj JE Die 017 x 125 pse 057 SH D18 D19 AI TX SbA poc BL D58 Ces Lens Gd as iw x D20 021 TX soL Doc BL peo E xo D23 Kan ele Ces a Nr v s Ga P aw Ou D24 D25 D64 Des SESESENE aa B L ARE Xu P av tr t 3 i 12V x82 vos 29 x x143 bes ee XE pao D31 REJ AUX RX DRV IN 5145 1 D70 D71 e aw 1N H8 P aiw 12V TX CAD 532 033 AUX RX DRV OE x14 D72 073 IU pa 035 AUX RX DRV OUT XSL pra ee av 12v H MA Ea v Eater ake te RL eke s pH akon arr d Lax CO CKA mav KO RECH PSNTa GND GND GND GND GND GND GND GND
120. i stream support MST 4Kp60 resolution support Source e Embedded controller AUX channel operation e Accepts standard H sync V sync data enable RGB and YCbCr input video formats e Supports audio and video streams Sink e Finite state machine FSM or embedded controller AUX channel operation e Produces a proprietary video output Auxiliary channel for 2 way communica tion link and device management Hot plug detect HPD e Sink announces its presence e Sink requests the source s attention AC coupling and low EMI Altera Corporation DisplayPort IP Core Quick Reference C Send Feedback UG 01131 2015 05 04 DisplayPort IP Core Quick Reference 1 3 CS CE Typical Application Device Family Support Interfaces within a PC or monitor e External display connections including interfaces between a PC and monitor or projector between a PC and TV or between a device such as a DVD player and TV display Arria 10 preliminary Arria V GX Arria V GZ Cyclone V and Stratix V FPGA devices Refer to the What s New in Altera IP page of the Altera website for detailed information Design Tools e IP Catalog in the Quartus II software for IP design instantiation and compilation TimeQuest timing analyzer in the Quartus II software for timing analysis e ModelSim Altera software for design simulation Related Information What s New in Altera IP DisplayPort IP Core Quick Reference E
121. ibrary 2015 05 04 The following figure shows a more detailed view of these operations For a sink application the user application must initialize the DPCD content and the EDID Additionally for both source and sink applications an interrupt ISR must be registered Figure 8 2 Typical Source and Sink User Application Library Calls Source Sink btc dptx syslib init btc dprx syslib add rx i btc dprx syslib mt Y Register the TX ISR gt BI DPTX ENABLE HPD IRO btc dprx dpcd gpu access btc dprx edid set gt lt Register the RX ISR gt y BTC DPRX ENABLE IRO btc dptx syslib monitor y btc_dprx_syslib_monitor Sink instantiations issue an interrupt to the GPU when an AUX channel Request is received from the connected source Source instantiations issue an interrupt to the GPU when a logic state change is detected on the HPD signal generated by the connected DisplayPort sink Because sources always act as AUX channel masters they can manage AUX communication by initiating a transaction by sending a request and then polling the IP core registers waiting to receive a reply Optionally source instantiations can also issue an interrupt to the GPU when an AUX channel reply is received from the connected DisplayPort sink allowing the GPU to execute other tasks while waiting for AUX channel replies Enable or disable
122. irection RW Reset 0x00000000 Table 9 50 DPTX_AUX_BYTE9 Bits pst ES hmmm O 31 8 Unused 7 0 BYTE Transaction data 6 for the next request or data 9 received in the last reply DPTX_AUX_BYTE10 AUX Transaction Byte 10 Register Address 0x010c Direction RW Reset 000000000 Table 9 51 DPTX_AUX_BYTE10 Bits RS OS CE 31 8 Unused 7 0 BYTE Transaction data 7 for the next request or data 10 received in the last reply DPTX_AUX_BYTE11 AUX Transaction Byte 11 Register Address 0x010d DisplayPort Source Register Map and DPCD Locations Altera Corporation Ei Send Feedback 9 26 DPTX_AUX_BYTE12 eet Direction RW Reset 0x00000000 Table 9 52 DPTX_AUX_BYTE11 Bits RS oeme cc OS 31 8 Unused 7 0 BYTE Transaction data 8 for the next request or data 11 received in the last reply DPTX_AUX_BYTE12 AUX Transaction Byte 12 Register Address 0x010e Direction RW Reset 0x00000000 Table 9 53 DPTX_AUX_BYTE12 Bits nm NENNEN OS Unused BYTE Transaction data 9 for the next request or data 12 received in the last reply DPTX_AUX_BYTE13 AUX Transaction Byte 13 Register Address 0x010f Direction RW Reset 0x00000000 Table 9 54 DPTX_AUX_BYTE13 Bits nm O foo pn TI hmmm O 31 8 Unused 7 0 BYTE Transaction data 10 for the next request or data 13 received in the last reply Altera Corporation DisplayPort Source Registe
123. ived from the sink Related Information AN 522 Implementing Bus LVDS Interface in Supported Altera Device Families Video Interface The core sends video to be encoded through the txN video in interface which provides a standard H sync and V sync input with support for interlaced or progressive video You specify the data input width via a parameter The same input port transfers RGB and YCbCr data in either 4 4 4 or 4 2 2 color format Data is most significant bit aligned and formatted for 4 4 4 Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 TX Transceiver Interface 4 13 Figure 4 4 Video Input Data Format 18 bpp to 48 bpp port width when txN_video_in port width is 48 16 bpc 1 pixel per clock 18 bpp RGB 24 bpp RGB YCBCr444 8 bpc 30 bpp RGB YCBCr444 10 bpc 36 bpp RGB YCBCr444 12 bpc 48 bpp RGB YCBCr444 16 bpc txN_vid_data 47 0 The following figure shows the sub sampled 4 2 2 color format for a video port width of n The most significant half of the video port always transfers the Y component while the least significant half of the video port transfers the alternate Cr or Cb component If the Y Cb Cr component widths are less than n 2 they must be most significant bit aligned with respect to the n and n 2 1 boundaries Figure 4 5 Sub Sampled 4 2 2 Color Format Video Port n 1 n 2 n 2 1 0 txN vid data n 1 0 If you set the P
124. iver receiver U3 is populated RX AUX channel output enable Use this signal if the external AUX driver receiver U3 is populated Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Required Hardware 6 19 HSMC Connector J4B AUX_RX_DRV_OUT Input RX AUX channel output Use this signal if the external AUX driver receiver U3 is populated TX CAD RX SDA DDC Ri SCL DDC Not used m SIDA DDC 1 SCI DDC EISE EIS OD enim ORL OU AUX_TX_PC AUX_TX_NC HSMC Con nector J4C TX AUX channel differential pair If the external AUX driver receiver chip SN65MLVD200 U4 is populated on Bitec card the FPGA device should not drive these differential signals To avoid bus contention remove the on chip bidirectional buffer aux_buffer_tx in the demonstration top module Instead the FPGA device should use AUX TX DRV IN AUX TX DRV OE and Aux TX DRV OUT signals Note Thetx aux inandtx aux out signals are inverted If the external AUX driver receiver chip is used undo the inversion AUX TX DRV IN Output TX AUX channel input Use this signal if the external AUX driver receiver U4 is populated AUX TX DRV OE Input TX AUX channel output enable Use this signal if the external AUX driver receiver U4 is populated AUX TX DRV OUT Input TX AUX channel output Use this signal if the external AUX driver
125. ixel input mode option to Dual or Quad the IP core sends two or four pixels in parallel respectively To support video resolutions with horizontal active front porch or back porch of a length not divisible by 2 or 4 the following signals are widened e Horizontal and vertical syncs e Data enable The following figure shows the pixel data order from least significant bits to most significant bits Figure 4 6 Video Input Data Alignment For RGB 18 bpp when txN_video_in port width is 96 8 bpc 4 pixels per clock 95 E n P u 23 0 txN vid data 95 0 ns ST Pixel 3 Pixel 2 Pixel 1 Pixel 0 TX Transceiver Interface The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core The DisplayPort IP uses a soft 8B 10B encoder This interface provides TX encoded video data tx_parallel_data in either dual symbol 20 bit or quad symbol 40 bit mode and drives the digital DisplayPort Source Altera Corporation E Send Feedback UG 01131 4 14 Transceiver Reconfiguration Interface 2015 05 04 reset tx_digitalreset analog reset tx_analogreset and PLL powerdown signals tx pll powerdown of the transceiver Transceiver Reconfiguration Interface You can reconfigure the transceiver to accept single reference clock The single reference clock is a 135 MHz clock for all bit rates RBR HBR and HBR2 e During run time you can reconfigure the transceiver to operat
126. izer Off when symbol output mode is dual Note Currently only Arria V GX Arria V GZ and Stratix V devices support 5 4 Gbps operation DisplayPort IP Core Hardware Demonstration Altera Corporation E Send Feedback UG 01131 6 14 Required Hardware 2015 05 04 Required Hardware The hardware demonstration requires the following hardware e Altera FPGA kit includes USB cable to connect the board to your PC the demonstration supports the following kits e Stratix V GX FPGA Development Kit e Arria V GX FPGA Starter Kit e Cyclone V GT FPGA Development Kit Arria 10 FPGA Development Kit e Bitec DisplayPort HSMC daughter card e PC with a DisplayPort output e Monitor with a DisplayPort input e Two DisplayPort cables e One cable connects from the graphics card to the FPGA development board e The other cable connects from the FPGA development board to the monitor Note Altera recommends that you first test the PC and monitor by connecting the PC directly to the monitor to ensure that you have all drivers installed correctly The Bitec HSMC DisplayPort daughter card connects Altera FPGA devices to the DisplayPort source and sink devices High speed 5 4Gbps DisplayPort redrivers are used on both the source and sink signal paths to improve signal integrity The redrivers ensure close PHY layer compatibility at the DisplayPort connectors Figure 6 6 Bitec HSMC Daughter Card The figure shows a high level diagram of the Bitec HSMC dau
127. k K Ck Ck ck k ck ck ck KA KE K bitec i2c write 0x58 Oxlc 0x00 DPCD addr 19 16 0x0 bitec i2c write 0x58 Ox1d 0x01 DPCD addr 15 8 0x01 bitec i2c write 0x58 Oxle 0x06 DPCD addr 7 0 0x06 bitec i2c write 0x58 Ox1f 0x01 DPCD data 0x01 J BR RK RK k k k k kok k k k k kk kk kk kk KCKCKCKCKCKCKCk KCKCKCk KCKCKCK KCKCKCKCKCKCKCk KE Ck ck k ck k ck ck ck kk May want to adjust squelch level DP130 reg 0x03 data 0x08 J BR RK RK RK k k kok k k kk kk kk kk kk kk kk kk kk KCKCKCKCKCKCKCKCKCKCKCK KCKCKCk OR Ck ck k ck OR I IO bitec i2c write 0x58 0x03 0x08 40mV J BR RK RR KK RK RR OK KR KK kk kk kk kk ke ke Enable EQ DP130 reg 0x05 data 0x80 J BR RK RK k k k k k k k kk kk kk kk kk Ck k A ck ck ck kkk bitec i2c write 0x58 0x05 0x80 BR RK k kok k k k kk kk kk kk kk kk kk kk kk KCKCKCK KCKCKCk KCKCKCK KCKCKCk KCKCKCk kk kk KCk Ck Ck k ck ck ck kk kk Set EO level to 13dB HBR2 for lane 0 DP130 reg 0x05 data 0x85 J BR KK RK k k k k k K k K k K K K K K ARE OK AAA AAA kCKCKCKCkCKCKCKCKCKCKCKCKCKCKCKCKCK KCK Ck ck k ck k ck ck ck ck ck kk bitec i2c write 0x58 0x05 0x85 BOR RK k kok k k k kk kk kok kk kk kk kk kCkCkCKCKCKCKCK kk kk kk kk KCKCKCkCKCKCKCk KCKCKCk k kck ck kk kk k Set EO level to 13dB HBR2 for lane 1 DP130 reg 0x07 data 0x05 BR RK kok k k k kk kk kk kk kk kk kk KCKCKCK KCKCKCk KCKCKCK KCKCKCk KCKCKCK KCKCKCk KCKCKCK X ck ck ck ck ck ck
128. ks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 3001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYAN 1 2 DisplayPort IP Core Quick Reference UG 01131 2015 05 04 o mm o Bem OS Core Features IP Core Information Conforms to the Video Electronics Standards Association VESA specifica tion version 1 2a Scalable main data link e 1 2 or 4 lane operation e 1 62 2 7 and 5 4 gigabits per second Gbps per lane with an embedded clock Color support e RGB 18 24 30 36 or 48 bits per pixel bpp color depths e YCbCr 4 4 4 24 30 36 or 48 bpp color depths e YCbCr 4 2 2 16 20 24 or 32 bpp color depths 40 bit quad symbol and 20 bit dual symbol transceiver data interface Support for 1 2 or 4 parallel pixels per clock Mult
129. l parallel DisplayPort data to the sink Each data lane is clocked in to the IP core by its own respective clock output from the transceiver Inside the sink the four independent clock domains are synchronized to the lane 0 clock Then the IP core performs the following actions 1 The IP core aligns the data stream and performs 8B 10B decoding 2 The IP core deskews the data and then descrambles it 3 The IP core splits the unscrambled data stream into parallel paths a The SS decoder block performs secondary stream decoding which the core transfers into the rx ss clk domain through a DCFIFO b The main data path extracts all pixel data from the incoming stream Then the gearbox block resamples the pixel data into the current bit per pixel data width Next the IP core crosses the pixel data into the rxN vid clk domain through a DCFIFO Finally the IP core steers the data into a single dual or quad pixel data stream c MSA decode path d Video decode path You configure the sink to output the video data as a proprietary data stream You specify the output pixel data width at 6 8 10 12 or 16 bpc This format can interface with downstream Altera Video and Image Processing VIP Suite components The AUX controller can operate in an autonomous mode in which the sink controls all AUX channel activity without an external embedded controller The IP core outputs an AUX debugging stream so that you can inspect the activity on the AUX
130. l Symbol Data to Transceiver Video Data Packt Generator Audio Stream ae A ncoder txN audio Secondary DCFIFO Secondary Data p Stream Encoder txN ss a Training Pattern 1 Training Pattern 2 gt m Bidirectional AUX Data Avalon MM lt 4 gt e l i AUX Debug Stream bx mgmt egisters ontroller HPD The source accepts a standard H sync V sync and data enable video stream for encoding The IP core latches and processes the video data before processing it using the txN_video_in input N represents the stream number tx_video_in Stream 0 tx1 video in Stream 1 tx2_video_in Stream 2 and tx3_video_in Stream 3 The video data width supports 6 to 16 bits per color bpc and is user selectable If you set the Pixel input mode option to Dual or Quad the video input can accept two or four pixels per clock thereby extending the pixel clock rate capability Main Data Path The main data path consists of the packetizer measurement and blank generator paths The IP core multiplexes data from these three paths and outputs it through an 8B 10B encoder DisplayPort Source Altera Corporation E Send Feedback UG 01131 4 4 Packetizer Path 2015 05 04 Packetizer Path The packetizer path provides video data resampling and packetization and consists of the following steps 1 The pixel steer block decimates the data to the requested lane count 1 2 or 4 2 Th
131. l data across the high speed serial interface HSSI The HSSI requires a 135 MHz clock for correct data locking You can supply this frequency to the HSSI using a reference clock provided by an Altera PLL or pins The IP core synchronizes HSSI 20 or 40 bit data to a single HSSI 0 clock that clocks the data into the DisplayPort front end decoder e Ifyou select dual symbol mode this clock is equal to the link rate divided by 20 270 135 or 81 MHz e Ifyou turn on quad symbol mode this clock is equal to the link rate divided by 40 135 67 5 or 40 5 MHZ The IP core crosses the reconstructed pixel data into a local pixel clock rxN vid cik through an output DCFIFO which drives the pixel stream output The rxN_vid_clk must be higher than or equal to the pixel clock in the up stream source If rxN vid clk is slower than the up stream pixel clock the DCFIFO overflows If the rxN vid clk is faster than the up stream source pixel clock the output port experiences a de assertion of the valid port on cycles in which pixel data is not available The optimum frequency is the exact clock rate in the up stream source You require pixel clock recovery techniques to determine this clock frequency Secondary stream data is clocked by rx ss cik The sink IP core also requires a 16 MHz clock aux c1k to drive the internal AUX controller and an Avalon clock for the Avalon MM interface c1k Altera Corporation DisplayPort Sink G send Feedback
132. launch a debug terminal nios2 configure sof project name sof USB cable number nios2 terminal USB cable number DisplayPort IP Core Hardware Demonstration LJ Send Feedback Altera Corporation 6 26 View the Results UG 01131 2015 05 04 Note To find lt USB cable number gt use the jtagconfig command Note Refer to the Nios II Software Build Tools Reference chapter in the Nios II Software Developer s Handbook for a description of the commands in these scripts View the Results In this step you view the results of the hardware demonstration in the Nios II command shell and on the DisplayPort monitor 1 Power up the connected DisplayPort monitor 2 Connect the free end of the Display Port cable that you connected to your PC to the DisplayPort RX on the Bitec HSMC daughter card The PC now has the DisplayPort monitor available as a second monitor The hardware demonstration loops through and displays the graphic card output as received by the sink core Note Some PC drivers and graphic card adapters do not enable the DisplayPort hardware automati cally upon hot plug detection You may need to start the adapter s control utility e g Catalist Control Center nVidia Control Panel etc and manually enable the DisplayPort display Figure 6 11 Loop through Hardware Demonstration 3 You can use your graphic card control panel to adjust the resolution of the DisplayPort monitor which typically res
133. m Lane 0 Data 1 62 2 7 or 5 4 Gbps Lane 1 Data 1 62 2 7 or 5 4 Gbps Lane 2 Data 1 62 2 7 or 5 4 Gbps Source Lane 3 Data 1 62 2 7 or 5 4 Gbps AUX Channel 1 Mbps Hot Plug Detect 2S LI LK Sink The main link has three selectable data rates 1 62 2 7 and 5 4 Gbps The source device sets the lane count and link rate combination referred to as the policy according to the sink s capabilities and required video bandwidth The AUX channel is an AC coupled differential pair for bidirectional communication The signaling is a self clocked Manchester encoding at 1 Mbps Like 100 T Ethernet the encoder uses a preceding synchro nization pattern in each 16 byte maximum packet The AUX channel uses a master slave hierarchy in which the source master initiates all communication Sink Functional Description The DisplayPort sink has a complete set of parameters for optimizing device resources The DisplayPort sink consists of a DisplayPort decoder block a transceiver management block and a controller interface block with an Avalon MM interface for connecting with an embedded controller such as the Nios II processor You can configure the ports using an RTL wrapper instantiation or implementing the IP core as a Osys component 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS OUARTUS and STRATIX words and logos are trademarks of Altera Corporation a
134. mendis that you set about 60 MHz to achieve timing closure DEVICE FAMILY Arria V Identifies the family of the device used The values are Arria V Stratix V and Cyclone V FIXED NVID Ws Specifies the configuration of the DisplayPort RX received video clocking used Set to 0 for synchronous clocking where the value of Nvid is variable Set to 1 for asynchronous clocking where the Nvid value is fixed to 32 h8000 32 768 PIXELS PER CLOCK 1 Specifies how many pixels in parallel for each clock cycle are gathered from the DisplayPort RX Set to 1 for single pixel 2 for dual or 4 for four pixels per clock cycle BPP 24 Specifies the width in bits of a single pixel Set to 18 for 6 bit color 24 for 8 bit color and so on up to 48 for 16 bit color Note Most DisplayPort source devices transmit video using asynchronous clocking For optimized resource usage Altera recommends you to set parameter FIXED_NVID to 1 Clock Recovery Interface The following table lists the signals for the clock recovery core Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Clock Recovery Interface 6 7 Table 6 3 Clock Recovery Interface Signals control clock Clock Input Control logic clock This clock runs the loop controller and fPLL reconfiguration related blocks Note Altera recommends that you set about 60 MHz to achieve timing closure Set the CLK_
135. mp packet payload contains M and N values which the sink uses to recover the source s audio sample clock The rxN audio port uses the values to generate the rxN audio valid signal according to sample audio data Data is clocked out using the rx_ss_c1x signal The rx_ss_c1x signal comes from the rx parallel clock from the RX transceiver This clock runs at link data rate 20 for dual symbol mode and link data rate 40 for quad symbol mode The sink generates the rxN_audio_valid signal using the M and N values and asserts it at the current audio sample clock rate The rxN_audio_mute signal indicates whether audio data is present on the DisplayPort interface DisplayPort Sink E Send Feedback Altera Corporation UG 01131 5 22 MSA Interface 2015 05 04 Figure 5 10 rxN_audio Data Output rxN audio Ipcm data rx ss clk rxN audio valid Audio Sample Period The captured audio infoframe is available on the audio port The 5 byte port corresponds to the 5 bytes used in the audio infoframe refer to CEA 861 D The audio infoframe describes the type of audio content MSA Interface The rxN msa conduit ports allow designs access to the MSA and VB ID parameters on a top level port The following table shows the 217 bit port bundle assignments The prefixes msa and vbid denote parameters from the MSA and Vertical Blank ID VB ID packets respectively The sink as
136. mple packets from the incoming audio sample data stream Then it sends the three packet types to the secondary stream encoder before they are transmitted to the downstream sink device The audio port is parameterized for the number of audio channels required in the design You can use 2 or 8 channels Each channel s audio data is sent to the txN audio lpcm data port The IP core requires a txN audio valid signal for designs in which the txN audio clk signal is higher than the actual sample clock The txN_audio_valid signal qualifies the audio data on the txN_audio_lpcm_data input Altera Corporation DisplayPort Source CJ Send Feedback UG 01131 2015 05 04 Audio Interface 4 17 Table 4 10 Audio Signals EXN audio elk Audio interface input clock ca audio valid Audio input data valid txN_audio_mute When asserted indicates that audio muting is enabled txN_audio_lpcm_data m 32 m channel 32 bit audio sample data sO Figure 4 9 Audio Sample Data Bits The packing format uses an IEC 60958 type encoding 31 24 23 16 15 8 7 0 7 B3 07 B2 017 B1 0 7 BO 0 31 30 29 28 27 26 25 24 23 0 SP R PR P C UJV MSB Audio Sample Word 23 0 LSB Table 4 11 Audio Sample Bit Field Definitions Audio sample Byte 2 bits 7 0 Audio data The data content depends on the audio coding type For word Byte 1 bits 7 0 LPCM audio the audio most significant
137. n 2 n 2 1 0 rxN vid data n 1 0 If you set the Pixel output mode option to Dual or Quad the IP core outputs two or four pixels in parallel respectively To support video resolutions with horizontal active front and pack porches with lengths that are not divisible by two or four rxN vid validis widened For example for two pixels per clock rxN_vid_valid 0 is asserted when pixel N belongs to active video and rxN vid valid 1 is asserted when pixel n 1 belongs to active video The following figure shows the pixel data order from least significant bits to most significant bits Figure 5 7 Video Output Alignment For RGB 18 bpp when rxN video out Port Width is 96 8 bpc 4 Pixels per Clock 95 e E m o e o rxN vid data 95 0 se ez sy Ba Pixel 3 Pixel 2 Pixel 1 Pixel 0 Related Information Video and Image Processing Suite User Guide Provides more information about Clocked Video Input DisplayPort Sink Altera Corporation CJ Send Feedback 5 18 Clocked Video Input Interface Clocked Video Input Interface 2 UG 01131 015 05 04 The rxN_video_out interface may interface with a clocked video input CVI CVI accepts the following video signals with a separate synchronization mode dat avalid de h_sync v sync f locked and data The DisplayPort rxN_video_out interface has the following signals rxN_vid_valid rxN_vid_sol rxN_vid_eol rxN_vid_sof rxN_vid_eof rxN_vid_lock
138. n O 31 EE Enables an IRQ issued to the Nios II processor on an HPD event e 0 disable l enable 30 AU IRO EN Enables an IRQ issued to the Nios II processor when an AUX channel transaction reply is received from the sink e 0 disable e 1 enable 29 Unused 28 21 PE Main link rate expressed as multiples of 270 Mbps e 0x06 1 62 Gbps e 0x0a 2 7 Gbps e 0x14 5 4 Gbps 20 Reserved Reserved 19 o 0 Standard framing 1 Enhanced framing 18 15 Unused 14 ASINC CLOCK 0 Synchronous reserved for future use 1 Asynchronous Note The core only supports asynchronous clock mode for 14 1 release The register bit is always set to 1 13 10 Unused 9 5 LANE COUNT Lane count e 00000 Reserved e 00001 1 e 00010 2 e 00100 4 4 Unused Altera Corporation DisplayPort Source Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPTX_TX_STATUS 9 3 nm 1 mess function O 3 0 E Current training pattern e 0000 Normal video e 0001 Training pattern 1 e 0010 Training pattern 2 e 0011 Training pattern 3 e 0111 Video idle pattern e 1001 D10 2 test pattern same as training pattern 1 e 1010 Symbol error rate measurement pattern e 1011 PRBS7 e 1100 80 bit custom pattern e 1101 HBR2 compliance test pattern CP2520 pattern 1 DPTX_TX_STATUS The IP core issues an IRQ to the Nios II processor if the DPTX TX CONTROL
139. nc tx vid h sync de tx vid de tx vid f andtx vid data 23 0 signals at 256 pixels per line and 8 bpp i readme txt Documentation for the simulation example Miscellaneous files edid memory hex Initial content for the EDID ROM Generate the IP Simulation Files and Scripts and Compile and Simulate In this step you use a script to generate the IP simulation files and scripts and compile and simulate them Type the command sh runall sh Altera Corporation DisplayPort IP Core Simulation Example G send Feedback UG 01131 2015 05 04 Generate the IP Simulation Files and Scripts and Compile and Simulate 7 7 This script executes the following commands Generate the simulation files for the DisplayPort transceivers and transceiver reconfiguration IP cores Arria 10 devices e qsys generate al0 dp gsys syn sim e qsys generate gxb rx qsys syn sim e qsys generate gxb tx qsys syn sim e qsys generate gxb tx atx pll gsys syn sim e qsys generate gxb tx reset gsys syn sim Arria V Cyclone V and Stratix V devices where prefix is av for Arria V devices cv for Cyclone V devices and sv for Stratix V devices e qmegawiz silent lt prefix gt _xcvr_reconfig v e qmegawiz silent lt prefix gt _dp v e qmegawiz silent lt prefix gt native phy rx v e qmegawiz silent prefix native phy tx v Merge the four resulting msim setup tcl scripts to create a single mentor msim setup tcl Arria 10 devices
140. nd registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 5 2 Figure 5 2 DisplayPort Sink Top Level Block Diagram Altera Corporation Sink Functional Description DisplayPort Sink Ix edid 3 Ix xcvr interface gt Decode r Secondary Stream gt nl ss Avalon ST Interface 939 nN ss dk Audio Output 93 nM audio UG 01131 2015 05 04 Video Output Video Clock MSA Output Stream Debug AUX Interface AUX Clock Link Parameters EDID Interface RX Transceiver Interface AUX Debug Stream Avalon ST Interface
141. nd tx emp transceiver management control ports You must map these ports for the device you are using To change these values the core drives tx analog reconfig req high Then the user logic sets tx analog reconfig ack high to acknowledge and drives tx analog reconfig busy high during reconfiguration When reconfiguration completes the user logic drives tx analog reconfig busy low Secondary Stream Interface You can transmit the secondary stream data over the DisplayPort main link through the secondary stream txN ss interface This interface uses handshaking and back pressure to control packet delivery Internally the core uses a FIFO to store packets until a slot becomes available on the main link If the FIFO fills up the secondary stream interface stops accepting packets and applies back pressure The packet must be available at the time of sending because the txN ss port does not support forward pressure Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 Secondary Stream Interface 4 15 The txN ss interface input data format corresponds to four 15 nibble code words as specified by the DisplayPort version 1 2a specification section 2 2 6 3 The upstream Reed Solomon encoder supplies these 15 nibble code words The format differs for header and payload as shown in the following figure Figure 4 7 Secondary Stream Input Data Format
142. ne 1 Data 1 62 2 7 or 5 4 Gbps Lane 2 Data 1 62 2 7 or 5 4 Gbps Source Lane 3 Data 1 62 2 7 or 5 4 Gbps AUX Channel 1 Mbps Hot Plug Detect Sink The main link has three selectable data rates 1 62 2 7 and 5 4 Gbps The source device sets the lane count and link rate combination referred to as the policy according to the sink s capabilities and required video bandwidth The IP core transmits the video and audio streams on the main link with embedded clocking The IP core transmits data in a scrambled ANSI 8B 10B format The data transmission includes redundancy for error detection The secondary data stream such as an audio stream uses a Reed Solomon encoder for error correction The AUX channel is an AC coupled differential pair for bidirectional communication The signaling is a self clocked Manchester encoding at 1 Mbps As in the 100 T Ethernet protocol the encoder uses a preceding synchronization pattern in each 16 byte maximum packet The AUX channel uses a master slave hierarchy in which the source master initiates all communication 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective hol
143. ng counter to generate timestamps and delays The same counter is used in both sink and source instantiations DPRX_TIMESTAMP is DPTX_TIMESTAMP Address 0x001F Direction RO Reset 0x00000000 DisplayPort Source Register Map and DPCD Locations CJ Send Feedback always equal to Altera Corporation 9 12 Source Audio Registers Table 9 24 DPTX_TIMESTAMP Bits mn oome CE 31 24 Unused UG 01131 2015 05 04 8 b00000000 23 0 Source Audio Registers TIMI Som Free running counter value 1 tick equals 100 us The Audio registers are allocated at addresses 0x002f for Stream 0 0x004f for Stream 1 0x006f for Stream 2 0x008f for Stream 3 Note Only registers for Stream 0 are listed in the following sections The following register controls the values related to the audio data stream 0 Address 0x002f Direction RW Reset The maximum number of channels supported minus 1 0x00000000 to 0x00000007 Table 9 25 DPTXO AUD CONTROL Bits OS NNI 31 SORT MUTE 1 Audio is muted 0 Audio is muted if tx_audio_mute is asserted 30 24 Unused 17 16 DERBER Audio InfoFrame LFE playback level LFEPBL see CEA 861 E specification 15 8 ca Audio InfoFrame channel allocation CA see CEA 861 E specification 7 4 zs Audio InfoFrame level shift value LSV see CEA 861 E specification 3 DIL 2 Audio InfoFrame down mix inhibit flag DM_INH see CEA 861 E specification Altera
144. ng monitor The software should invoke this function periodically or at least every 50 ms Example btc dptx syslib monitor btc dptx test autom Prototype int btc dptx test autom void Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters No DisplayPort API Reference Altera Corporation E Send Feedback UG 01131 8 20 btc_dptx_video_enable 2015 05 04 Description This function handles test automation requests from the connected DisplayPort sink You should invoke this function after the IP core senses an HPD IRQ and identifies it as a test automation request The function implements TEST_LINK_ TRAINING and TEST_EDID_READ Example btc dptx test autom btc dptx video enable Prototype int btc dptx video enable BYTE enabled Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Drm enabled output idle pattern 1 output active video Description This function enables the TX to output either active video or an idle pattern After successful link training the TX outputs active video by default Example btc dptx video enable 1 btc dpxx syslib Additional Types In addition to the standard ANSI C defined types btc dpxx syslib uses the following types e define BYTI E unsigned char btc dprx syslib Supported
145. nsed IP core in your system e Verify the functionality size and speed of the IP core quickly and easily e Generate time limited device programming files for designs that include IP cores e Program a device with your IP core and verify your design in hardware OpenCore Plus evaluation supports the following two operation modes e Untethered run the design containing the licensed IP for a limited time e Tethered run the design containing the licensed IP for a longer time or indefinitely This requires a connection between your board and the host computer Note All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times out Specifying IP Core Parameters and Options Follow these steps to specify the DisplayPort IP core parameters and options 1 Create a Quartus II project using the New Project Wizard available from the File menu 2 On the Tools menu click IP Catalog 3 Under Installed IP double click Library gt Interface gt Protocols gt Audio amp Video gt DisplayPort The parameter editor appears 4 Specify a top level name for your custom IP variation This name identifies the IP core variation files in your project If prompted also specify the targeted Altera device family and output file HDL preference Click OK 5 Specify parameters and options in the DisplayPort parameter editor e Optionally select preset parameter values Presets specify all initial parameter values for sp
146. nterface Signal Type Clock Domain Link Parameters Conduit aux_clk rx lane count 4 0 Output Sink current link lane rx_params count value rxN_stream_ Output data 4 8 s 1 0 rxN stream ctrl 4 s Outp 120 ut Debuggin Raw symbol output 8818 Conduit rx ss clk y P rxN_stream rxN_stream_valid Outp stream ut rxN stream clk Outp ut Table 5 7 Secondary Interface N is the stream number for example rx msa conduit represents Stream 0 rx1 msa conduit represents Stream l andsoon rx ss clk Output rx ss ck m Clock Altera Corporation DisplayPort Sink C Send Feedback UG 01131 2015 05 04 Sink Interfaces 5 1 Conduit rx s5s_clk rxN_msa 216 0 Output Output for current m MSA parameters msa received from the conduit source rxN ss data 159 0 Output rxN ss valid Outp ut Sonny Secondary stream Stream AV ST rx ss clk ry EN cs rxN_ss_sop Outp interface m ut rxN ss eop Outp ut Table 5 8 Audio Interface m is the number of RX audio channels n is the stream number for example rx audio represents Stream 0 rxl audio represents Stream 1 and so on Description Interface Signal Type Clock Direction Domain rxN audio lpom Output data m 32 1 0 rxN audio valid Outp ut rxN audio mute Outp ut rxN audio Outp infoframe 39 0 ut Audio rxN audio Conduit rx SS clk Decoded audio data
147. nvalid or being updated 1 MSA fields are valid 191 168 msa Mvid 23 0 Mvid value for the main video stream Used for stream clock recovery from link symbol clock 167 144 msa BYT Nvid value for the main video stream Used for stream clock recovery from link symbol clock 143 128 msa Htotal 15 0 Horizontal total of received video stream in pixels 127112 msa Vtotal 15 0 Vertical total of received video stream in lines 111 msa_HSP H sync polarity 0 Active high 1 Active low 110 96 msa_HSW 14 0 H sync width in pixel count 95 80 msa_Hstart 15 0 Horizontal active start from H sync start in pixels H sync width Horizontal back porch 79 64 msa_Vstart 15 0 Vertical active start from V sync start in lines V sync width Vertical back porch 63 msa_VSP V sync polarity 0 Active high 1 Active low 62 48 msa_VSW 14 0 V sync width in lines 47 32 msa_Hwidth 15 0 Active video width in pixels 31 16 msa_Vheight 15 0 Active video height in lines DisplayPort Sink Altera Corporation LJ Send Feedback UG 01131 5 24 Sink Clock Tree 2015 05 04 NC C GR NN 15 8 msa MISC0 7 0 The mrsco 7 1 and MIsc1 7 fields indicate the color encoding format The color depth is indicated in MISCO 7 5 7 0 msa_MISC1 7 0 000 6 bpc e 001 8bpc e 010 10 bpc e 011 12bpc e 100 16 bpc For details about the encoding format refer to the Display Port v1 2 specification Sink Clock Tree The IP core receives DisplayPort seria
148. oad ID or slot 41 3 0 VCPSLOT40 VC payload ID or slot 40 DPTX_MST_VCPTAB6 VC Payload ID Table Address 0x00a8 Direction RW Reset 0x00000000 Altera Corporation DisplayPort Source Register Map and DPCD Locations CJ Send Feedback UG 01131 2015 05 04 Table 9 36 DPTX MST VCPTAB6 Bits DPTX MST VCPTAB7 9 19 mn CCS CE 31 28 VCPSLOTSS VC payload ID or slot 55 27 24 VCPSLOTS4 VC payload ID or slot 54 23 20 VCPSLOT53 VC payload ID or slot 53 19 16 VCPSLOT52 VC payload ID or slot 52 15 12 VCPSLOT51 VC payload ID or slot 51 11 8 VCPSLOT50 VC payload ID or slot 50 7 4 VCPSLOT49 VC payload ID or slot 49 3 0 VCPSLOT48 VC payload ID or slot 48 DPTX_MST_VCPTAB7 VC Payload ID Table Address 0x00a9 Direction RW Reset 0x00000000 Table 9 37 DPTX_MST_VCPTAB7 Bits mn IL ann CE 31 28 VCPSLOT63 VC payload ID or slot 63 27 24 VCPSLOT62 VC payload ID or slot 62 23 20 VCPSLOT61 VC payload ID or slot 61 19 16 VCPSLOT60 VC payload ID or slot 60 15 12 VCPSLOTS9 VC payload ID or slot 59 11 8 VCPSLOT58 VC payload ID or slot 58 7 4 VCPSLOT57 VC payload ID or slot 57 3 0 VCPSLOT56 VC payload ID or slot 56 DisplayPort Source Register Map and DPCD Locations E Send Feedback Altera Corporation 9 20 UG 01131 DPTX_MST_TAVG_TS 2015 05 04 DPTX_MST_TAVG_TS Target Average Timeslots Address 0x00aa Direction RW Reset 0x40404040 Table 9 38 DPT
149. ocked and stable Altera recommends that you use reset out to reset the downstream logic connected to the video output port During the hardware demonstration operation you can adjust the DisplayPort source resolution graphics card from the PC and observe the effect on the IP core The Nios II software prints the source and sink AUX channel activity Press one of the push buttons to print the current TX and RX MSA Transceiver and Clocking The device s Gigabit transceivers operate at 5 4 2 7 and 1 62 Gbps and require a 135 MHz single reference clock When the link rate changes the state machine only reconfigures the transceiver PLL settings Table 6 4 Arria V Transceiver Native PHY TX and RX Settings The table shows the Arria V Transceiver Native PHY settings for TX and RX using a single reference clock Datapath Options Enable TX datapath On Enable RX datapath On DisplayPort IP Core Hardware Demonstration Altera Corporation CJ Send Feedback UG 01131 6 12 Transceiver and Clocking 2015 05 04 Parameters Single Reference Clock Settings Datapath Options Enable standard PCS On 1 2 or 4 Number of data channels Bonding mode Note If you select 1 or 2 you must instantiate the PHY instance multiple times for all data channels as per maximum lane count parameter These values are for non bonded mode x1 or xN Note If you select x1 you must instantiate the PHY instance multiple times for all
150. ode saves logic resource but requires the core to run at twice the clock frequency of quad symbol mode If timing closure is a problem in the device you should consider using quad symbol mode DisplayPort Source L Send Feedback Altera Corporation 4 6 Source Parameters UG 01131 2015 05 04 Pixel input mode Select the number of pixels per clock single dual or quad symbol e Ifyou select dual pixels per clock the pixel clock is of the full rate clock and the video port becomes two times wider e Ifyou select four pixels per clock the pixel clock is of the full rate clock and the video port becomes four times wider Scrambler seed value Specify the initial seed for the scrambler block Use 16 hFFFF for normal DP and 16 hFFFE for eDP Enable AUX debug stream Turn on to send source AUX traffic output to an Avalon ST port Import fixed MSA Turn on to enable the source to accept a fixed MSA value from an external port Support CTS test automation Turn on to support CTS test automation Support secondary data channel Turn on to enable secondary data Support audio data channel Turn on to enable audio packet encoding Note To use this parameter you must turn on the Support secondary data channel parameter Number of audio data channels Specify the number of audio channels supported 6 bpc RGB or YCbCr 4 4 4 18 bpp Turn on to support 18 bpp encoding 8 bpc RG
151. on flow for the RX TX and TX Analog The FSM flow is similar for RX TX and TX Analog The FSM happens in sequence and it is controlled by the Reconfiguration Top Manager The Arria 10 reconfiguration uses read modified write operation to ensure only affected configuration register bits are updated IDLE v INIT gt v INIT WR TRANS If Last Offset no END INIT END INIT WR If Last Channel RESET DONE DisplayPort IP Core Simulation Example E Send Feedback The INIT state loads 0x02 to data and 0x00 to address for each channel The INIT_WR state initiates the Avalon MM write cycle Writing 0x02 to address 0x00 takes over the transceiver microcontroller The RD state reads the respective offset data from the transceiver The MOD state loads the read data and the data to be updated reconfigured or modified into the data array The WR state initiates the Avalon MM write cycle to the respective offset The TRANS state checks whether this offset is the last one that needs to be modified or updated If no go back to the RD MOD WR operation If yes move to the next channel or the operation is done Before moving to the next channel or DONE the END_INIT state loads 0x03 to data and 0x00 to address for each channel END_INIT_WR initiates the Avalon MM write operation to hand over the microcontroller ownership The END_INIT
152. ontal synchronization polarity 0 Positive 1 Negative DPRXO MSA HSW MSA horizontal synchronization width register DPRX0 MSA HSW Address 0x0025 Direction RO Reset 0x 00000000 Table 10 15 DPRXO MSA HSW Bits nm Il deme An O 31 15 Unused 14 0 HSW DPRXO MSA HSTART Address 0x0026 Direction RO Altera Corporation Main stream attribute horizontal synchronization width DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Reset 0x00000000 Table 10 16 DPRXO_MSA_HSTART Bits DPRXO_MSA_VSTART 10 11 mn JI CS ee O 31 16 15 0 DPRXO_MSA_VSTART Address 0x0027 Direction RO Reset 0x00000000 Table 10 17 DPRXO_MSA_VSTART Bits Main stream attribute HSTART mn JI CS ee O 31 16 15 0 DPRXO MSA VSP MSA vertical synchronization polarity register DPRX0 MSA VSP Address 0x0028 Direction RO Reset 0x00000000 Table 10 18 DPRXO MSA VSP Bits Main stream attribute VSTART pst mm O o hmmm O 31 1 Unused 0 VSP Main stream attribute vertical synchronization polarity 0 Positive 1 Negative DPRXO MSA VSW MSA vertical synchronization width register DPRXO_MSA_VSW Address 0x0029 DisplayPort Sink Register Map and DPCD Locations LJ Send Feedback Altera Corporation UG 01131 10 12 DPRXO MSA HWIDTH 2015 05 04 Direction RO Reset 0x00000000 Table 10 19 DP
153. or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01131 6 2 DisplayPort IP Core Hardware Demonstration 2015 05 04 Figure 6 1 Hardware Demonstration Overview FPGA Development Board User LEDs FPGA Transceiver Le DisplayPort IP Core Native PHY DisplayPort Source Sink RX nVidia ATI gt dock Li d Recovery splay e Transceiver Nios Il Processor A espaol ke m Native PHY Source 19 The DisplayPort sink uses its internal state machine to negotiate link training upon power up A Nios II embedded processor performs the source link managem
154. orporation DisplayPort Sink C Send Feedback UG 01131 2015 05 04 Controller Interface 5 13 Controller Interface The controller interface allows you to control the sink from an external or on chip controller such as the Nios II processor for debugging The controller interface is an Avalon MM slave that also allows access to the sink s internal status registers The sink asserts the rx mgmt irg port when issuing an interrupt to the controller Related Information DisplayPort Sink Register Map and DPCD Locations on page 10 1 AUX Interface The IP core has three ports to control the serial data across the AUX channel e Data input rx_aux_in e Data output rx_aux_out e Output enable rx aux oe The output enable port controls the direction of data across the bidirec tional link The AUX channel s physical layer is a bidirectional 2 5 V SSTL Class II interface A state machine decodes the incoming AUX channel s Manchester encoded data using the 16 MHz clock The message parsing drives the state machine input directly The state machine performs all lane training and EDID link layer services The sink s AUX interface also generates appropriate HPD IRQ events These events occur if the sink s main link decoder detects a signal loss The sink core uses the rx_cable_detect signal to detect when a source upstream device is physically connected and the rx_pwr_detect signal to detect when a source device is powered
155. pecification DPRXO AUD AIF2 Received audio InfoFrame register DPRX0 AUD AIF2 Address 0x0034 Direction RO Reset 0x00000000 Table 10 29 DPRXO AUD AIF2 Bits nm 1 mess Ihnen O 31 8 Unused 7 0 R Received audio InfoFrame byte 2 refer to CEA 861 E specification DPRXO AUD AIF3 Received audio InfoFrame register DPRX0 AUD AIF3 Address 0x0035 DisplayPort Sink Register Map and DPCD Locations Altera Corporation CJ Send Feedback UG 01131 10 16 DPRXO AUD AIF4 2015 05 04 Direction RO Reset 0x00000000 Table 10 30 DPRXO AUD AIF3 Bits 31 8 Unused 70 cub Received audio InfoFrame byte 3 refer to CEA 861 E specification DPRXO AUD AIF4 Received audio InfoFrame register DPRX0 AUD AIF4 Address 0x0036 Direction RO Reset 0x00000000 Table 10 31 DPRXO AUD AIF4 Bits CS Wuess A O 31 8 Unused 7 0 BL Received audio InfoFrame byte 4 refer to CEA 861 E specification Sink MST Registers MST controller control Address 0x00a0 Direction RW Reset 0x00000000 Table 10 32 DPRX MST CONTROL Bits mn CCS Fano 3 VOP TAB MPR POR This flag always reads back at 0 1 Force VC payload ID table update 30 BB e 1 Request for VC payload ID table update e 0 No change to VC payload ID table Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_MST_VCPTABO 10 17 mn IL CCS Fano
156. r Map and DPCD Locations C Send Feedback UG 01131 ET 2015 05 04 DPTX AUX BYTE14 5 DPTX AUX BYTE14 AUX Transaction Byte 14 Register Address 0x0110 Direction RW Reset 0x00000000 Table 9 55 DPTX AUX BYTE14 Bits nm We o Fein O 31 8 Unused 7 0 BYTE Transaction data 11 for the next request or data 14 received in the last reply DPTX_AUX_BYTE15 AUX Transaction Byte 15 Register Address 0x0111 Direction RW Reset 0x00000000 Table 9 56 DPTX_AUX_BYTE15 Bits nm JI NN n OS 31 8 Unused 7 0 BYTE Transaction data 12 for the next request or data 15 received in the last reply DPTX_AUX_BYTE16 AUX Transaction Byte 16 Register Address 0x0112 Direction RW Reset 000000000 Table 9 57 DPTX_AUX_BYTE16 Bits mn 1 CS bom O 31 8 Unused 7 0 emus Transaction data 13 for the next request DisplayPort Source Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 9 28 DPTX_AUX_BYTE17 2015 05 04 DPTX_AUX_BYTE17 AUX Transaction Byte 17 Register Address 0x0113 Direction RW Reset 0x00000000 Table 9 58 DPTX_AUX_BYTE17 Bits nm Inn TI CE 31 8 Unused 7 0 BYTE Transaction data 14 for the next reguest DPTX AUX BYTE18 AUX Transaction Byte 18 Register Address 0x0114 Direction RW Reset 0x00000000 Table 9 59 DPTX AUX BYTE18 Bits nm OOo Benem O CE 31 8 Unused 7 0 Sne Transaction data 15 for the next r
157. r to data to be written e mot Middle of transaction 0 or 1 Description This function writes 1 to 16 data bytes to the connected DisplayPort sink s I C interface mapped over the AUX channel Example IEC kees autre 120 vite 050 i eS 1 p Related Information btc dptx aux i2c read on page 8 12 btc dptx aux read Prototype int btc dptx aux read unsigned int address BYTE size BYTE data Thread safe No Available from ISR Yes Include bee cote sells ia gt DisplayPort API Reference Altera Corporation LJ Send Feedback UG 01131 8 14 btc_dptx_aux_write 2015 05 04 Return e 0 AUX_ACK replied e 1 Source internal error e 2 Reply timeout e 3 AUX NACK replied e 4 AUX DEFER replied e 5 Invalid reply Parameters e address DPCD start address e size Number of bytes 1 16 e data Pointer for data to be read Description This function reads 1 to 16 data bytes from the connected DisplayPort sink s DPCD Example btc_dptx_aux_read 0x202 2 amp status Related Information btc_dptx_aux_write on page 8 14 btc_dptx_aux_write Prototype int btc_dptx_aux_write unsigned int address BYTE size BYTE data Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return e O AUX ACK replied e 1 Source internal error e 2 Reply timeout e 3 AUX NACK replied e 4 AUX DEFER replied e 5 Invalid reply Parameters e
158. r transaction replies 1 Issue a transaction request 2 Wait for MSG_READY to be 1 Implement a timeout 3 Read the transaction reply s total length from LENGTH 4 Read the transaction reply s command from the DPTX AUX COMMAND register This transaction clears MSG_READY and LENGTH 5 Read the transaction reply s data payload from registers DPTX_AUX_BYTEO to DPTX_AUX_BYTE15 read LENGTH 1 bytes Address 0x0100 Direction RW Reset 0x00000000 Table 9 39 DPTX_AUX_CONTROL Bits RS CS CE 31 MSG READY 0 Waiting for a reply 1 A reply has been completely received 30 READS TO Is 0 Busy sending a request or waiting for a reply 1 Ready to send a request 29 5 Unused 4 0 TENGI For the next transaction request total length of message to be transmitted 3 20 for the last received transaction reply total length of message received 1 17 DPTX_AUX_CMD Address 0x0101 Direction RW Reset 0x00000000 Table 9 40 DPTX AUX CMD Bits 5t o CCS Fon O 31 8 Unused 7 0 COMMAND AUX transaction command for the next request or received in the most recent reply refer to the Display Port specification for details Reading of this register clears MSG READY and LENGTH in DPTX AUX CONTROL register DisplayPort Source Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 9 22 DPTX_AUX_BYTEO 2015 05 04 DPTX_AUX_BYTEO A
159. ration E Send Feedback UG 01131 10 14 Sink Audio Registers 2015 05 04 Sink Audio Registers The audio registers are allocated at addresses e 0x0030 through 0x003f for Stream 0 e 0x0050 through 0x005f for Stream 1 e 0x0070 through 0x007f for Stream 2 e 0x0090 through 0x009f for Stream 3 Note Only registers for Stream 0 are listed in the following sections DPRXO AUD MAUD Received audio Maud register DPRX0 AUD MAUD Address 0x0030 Direction RO Reset 0x00000000 Table 10 25 DPRXO AUD MAUD Bits mn JI CS ee O 31 24 Unused 23 0 MID Received audio Maud DPRXO AUD NAUD Received audio Naud register DPRX0 AUD NAUD Address 0x0031 Direction RO Reset 0x00000000 Table 10 26 DPRXO AUD NAUD Bits m ee O 31 24 Unused 23 0 AUD Received audio Naud DPRXO AUD AIFO Received audio InfoFrame register DPRXO_AUD_AIFO Address 0x0032 Direction RO Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRXO_AUD_AIF1 10 15 Reset 0x00000000 Table 10 27 DPRXO_AUD_AIFO Bits RS COS Droe O 31 8 Unused 7 0 AT Received audio InfoFrame byte 0 refer to CEA 861 E specification DPRXO AUD AIF1 Received audio InfoFrame register DPRX0 AUD AIF1 Address 0x0033 Direction RO Reset 0x00000000 Table 10 28 DPRXO AUD AIF1 Bits dm mo O 31 8 Unused 7 0 ATE Received audio InfoFrame byte 1 refer to CEA 861 E s
160. rs as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 10 2 DPRX_RX_CONTROL Table 10 2 DPRX_RX_CONTROL Bits UG 01131 2015 05 04 nm o mme O CE 31 30 Unused 29 LORTAC TINE e 0 Link Quality Analysis not used e 1 Link Quality Analysis in progress 28 24 Unused 23 16 9 Main link rate expressed as multiples of 270 Mbps e 0x06 1 62 Gbps e 0x0a 2 7 Gbps e 0x14 5 4 Gbps 15 14 Unused 13 a TE This flag always reads back at 0 1 Reconfigure the transceiver with link rate Rx LINK RATE 12 11 Unused 10 CAPERE EI 0 Sink transceiver enabled 1 Sink transceiver reset 9 8 TS Current training pattern e 00 Normal video e 01 Training pattern 1 e 10 Training pattern 2 7 5 0 Scrambler enabled 1 S
161. running counter to generate timestamps and delays The same counter is used in both sink and source instantiations DPRX_TIMESTAMP is always equal to DPTX_TIMESTAMP Address 0x0005 Direction RO Reset 0x00000000 Table 10 7 DPRX_TIMESTAMP Bits mn JI CS ee O 31 24 Unused 8 b00000000 23 0 TIMESTAMP Free running counter value 1 tick equals 100 us Sink Bit Error Counters DPRX BER CNTIO Internal bit error counters for lane 0 and lane 1 Address 0x0006 Direction RO DisplayPort Sink Register Map and DPCD Locations Altera Corporation LJ Send Feedback UG 01131 10 8 DPRX_BER_CNTI1 2015 05 04 Reset 0x00000000 Table 10 8 DPRX_BER_CNTIO Bits mn JI CS ee O 31 Unused 30 16 care Symbol error counter for lane 1 15 Unused 14 0 le Symbol error counter for lane 0 These registers are meant for internal use and are not exposed in the DPCD DPRX BER CNTI1 Bit error counter register for lane 2 and lane 3 Address 0x0007 Direction RO Reset 0x 00000000 Table 10 9 DPRX BER CNTI1 Bits mn JI osmueme non O 31 Unused 30 16 Eas Symbol error counter for lane 3 15 Unused 14 0 QUE Symbol error counter for lane 2 These registers are meant for internal use and are not exposed in the DPCD Sink MSA Registers The MSA registers are allocated at addresses e 0x0020 through 0x002f for Stream 0 e 0x0040 through 0x004f for Stream 1 e 0x0060 through 0x006
162. rxN_vid_eof The rxN vid overflow signal is always valid regardless of the logical state of rxN_vid_ valid rxN_vid_overflow is asserted for at least one clock cycle when the sink core internal video data FIFO runs into an overflow condition This condition can occur when the rxN vid clk frequency is too low to transport the received video data successfully You specify the maximum data color depth in the DisplayPort parameter editor The same output port transfers both RGB and YCbCr data in either 4 4 4 or 4 2 2 color format Data is most significant bit aligned and formatted for 4 4 4 Altera Corporation DisplayPort Sink GJ send Feedback UG 01131 2015 05 04 Video Interface 5 17 Figure 5 5 Video Output Data Format 18 bpp to 48 bpp Port Width when rxN_video_out port width is 48 16 bpc 1 Pixel per Clock 18 bpp RGB 24 bpp RGB YCBCr444 8 bpc 30 bpp RGB YCBCr444 10 bpc 36 bpp RGB YCBCr444 12 bpc 48 bpp RGB YCBCr444 16 bpc rxN_vid_data 47 0 The following figure shows the sub sampled 4 2 2 color format for a video port width of n The most significant half of the video port always transfers the Y component while the least significant half of the video port transfers the alternate Cr or Cb component If the Y Cb Cr component widths are less than n 2 they are most significant bit aligned with respect to the n and n 2 1 boundaries Figure 5 6 Sub Sampled 4 2 2 Color Format Video Port n 1
163. s DisplayPort Sink Register Map and DPCD Locations CJ Send Feedback Altera Corporation UG 01131 10 36 Sink Supported DPCD Locations 2015 05 04 Location Name Address Without With Controller Controller TEST_REQUEST 0x0218 Yes EST_LINK_RATE 0x0219 SH Yes MEST LANE COUNT 0x0220 Yes EST_PATTERN 0x0221 Yes EST H TOTAL LSB 0x0222 Yes EST H TOTAL MSp 0x0223 Yes TEST_V_TOTAL_LSB 0x0224 Yes EST V TOTAL MSB 0x0225 Yes TEST H START LSB 0x0226 Yes EST_H_START_MSB 0x0227 Yes BOT _V_START LSB 0x0228 Yes EST V START MSB 0x0229 Yes ESAM SPN CSB 0x022A Yes Seck EST_HSYNC_MSB 0x022B Yes HSE SAN CSB 0x022C Yes NM EST VSYNC MSB 0x022D Yes EST H WIDTH LSB 0x022E Yes EST H WIDTH MSB 0x022F Yes HUE DV RC ETE SES 0x0230 Yes ae EST V HEIGHT MSp 0x0231 Yes TES TEMI SCRESB 0x0232 Yes EST MISC MSB 0x0233 Yes EST REFRESH RATE NUMERATOR 0x0234 Yes z Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 Sink Supported DPCD Locations 10 37
164. s cv for Cyclone V devices and sv for Stratix V devices Your working directory should contain the files shown below DisplayPort IP Core Simulation Example Altera Corporation CJ Send Feedback 7 4 Copy the Simulation Files to Your Working Directory UG 01131 2015 05 04 Table 7 1 Simulation Example Files for Arria 10 Devices System Verilog a10 dp harness sv Top level test harness HDL design files a10 dp example v Design under test DUT dp analog mappings v Table translating VOD and pre emphasis settings a10 dp reconfig mgmt v Reconfiguration manager top level a10 dp rx reconfig mgmt v Reconfiguration manager FSM for an RX a10 dp txpll reconfig mgmt v Reconfiguration manager FSM for a TX Mesi ede a10 dp tx reconfig mgmt v Reconfiguration manager FSM for a TX analog clk gen v Clock generation file freq check sv Top level file for the frequency checker rx freq check sv RX frequency checker tx freq check sv TX frequency checker vga driver v VGA driver generates a test image a10 dp qsys IP Catalog variant for the DisplayPort IP Core gxb rx qsys IP Catalog variant for the RX transceiver IP Catalog files 9 b _tx qsys IP Catalog variant for the TX transceiver gxb tx atx pll qsys IP Catalog variant for the Transceiver ATX PLL gxb tx reset qsys IP Catalog variant for the PHY Reset Controller runall sh This script generates the IP simulation files and scrip
165. s block uses the received MSA to create h sync v sync and data enable signals that are synchronized to the recovered video clock e Loop Controller This block monitors the FIFO fill level and regulates its throughput by altering the original Mvid value read from the MSA The block feeds the modified Mvid to the fPLL Controller which calculates a set of parameters suitable for the fPLL Controller This set of parameters provides the value to create a recovered video clock frequency corresponding to the new Mvid value The calculated fPLL parameters are written by the PLL Reconfiguration Avalon Master to the Altera PLL Reconfiguration Controller internal registers e Reconfiguration Controller This block serializes the parameter values and writes them to the Altera fPLL IP core e Altera fPLL Generates the recovered video clock and a second clock with twice the frequency Clock Recovery Core Parameters You can use these parameters to configure the clock recovery core DisplayPort IP Core Hardware Demonstration Altera Corporation CJ Send Feedback UG 01131 6 6 Clock Recovery Interface 2015 05 04 Table 6 2 Clock Recovery Core Parameters SYMBOLS_PER_CLOCK 4 Specifies the configuration of the DisplayPort RX transceiver used Set to 2 for 20 bit mode 2 symbols per clock or to 4 for 40 bit mode 4 symbols per clock CLK PERIOD NS 10 Specifies the period in nanoseconds of the clock signal connected to the port Altera recom
166. s the policy maker DisplayPort Source LJ Send Feedback Altera Corporation 4 12 AUX Interface AUX Interface UG 01131 2015 05 04 The IP core has three ports that control the serial data across the AUX channel e Data input tx_aux_in e Data output tx_aux_out e Output enable tx aux oe The output enable port controls the direction of data across the bidirec tional link These ports are clocked by the source s 16 MHz clock aux c1k The AUX channels physical layer is a bidirectional 2 5 V SSTL Class II interface The source s AUX controller allows you to capture all bytes sent from and received by the AUX channel which is useful for debugging The IP core provides a standard stream interface that you can use to drive an Avalon ST FIFO component directly Table 4 9 Source AUX Debug Interface Ports tx_aux_debug_data 31 0 The source AUX debug interface inserts a 1 us timestamp counter in bits 31 8 bits 7 0 represent the byte received or transmitted tx aux debug valid Qualifies valid stream data tx aux debug sop Indicates the message packet s first byte tx aux debug eop Indicates the message packet s last byte The last byte should be ignored and is not part of the message tx aux debug err Indicates if the IP core detects an error in the current byte tx aux debug cha Indicates the direction of the current byte 1 byte transmitted by the source 0 byte rece
167. serts bit msa valid when all msa_ signals are valid and deasserts during MSA update The sink assigns the MSA parameters to zero when it is not receiving valid video data The sink asserts the msa lock bit when the MSA fields have been correctly formatted for the last 15 video frames Because msa lock changes state only when msa_valid 1 you can use its rising edge to strobe new MSA values following an idle video period for example when the source changes video resolution You can use its deasserted state to invalidate received video data The sink asserts bit vbid_st robe for one clock cycle when it detects the VB ID and all voia signals are valid to be read Table 5 14 rxN_msa_conduit Port Signals 216 msa_lock 0 MSA fields format error 1 MSA fields correctly formatted 215 vbid_strobe 0 VB ID fields invalid 1 VB ID fields valid Altera Corporation DisplayPort Sink L send Feedback UG 01131 2015 05 04 MSA Interface 5 23 214 209 vbid vote teen VB ID bit field e vbid 0 VerticalBlanking Flag e vbid 1 FieldID Flag for progressive video this remains 0 e vbid 2 Interlace Flag e vbid 3 NoVideoStream Flag e vbid 4 AudioMute Flag e vbid 5 HDCP SYNC DETECT 208 201 vbid_Mvid 7 0 Least significant 8 bits of Mvid for the video stream 200 193 vbid_Maud 7 0 Least significant 8 bits of Maud for the audio stream 192 msa_valid 0 MSA fields are i
168. sh a link and send several frames of video data The test harness checks that the sent data s CRC matches the received data s CRC for three frames 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 7 UG 01131 7 2 DisplayPort IP Core Simulation Example 2015 05 04 Figure 7 1 Simulation Example Block Diagram for Arria 10 Devices dk100 dk16 dk135 tx vid dk rx vid dk tx mgmt D
169. source and sink interrupts with the following library macros e B PTX ENABLE HPD IRQ e BTC DPTX DISABLE HPD IRQ e B PTX ENABLE AUX IRQ e BTC DPTX DISABLE AUX IRQ e BTC DPRX ENABLE IRQ e BTC DPRX DISABLE IRO btc dprx syslib manages one to four sink instances by disabling all GPU interrupts when invoked and restoring them to their previous state on exiting Therefore most of the library public functions implement critical sections The GPU main program should minimize overhead when serving interrupts generated by sink instances i e interrupts related to a connected source s AUX channel requests Interrupts generated by source instances i e interrupts related to a connected sink s HPD activity can be served with a lower priority In designs where the same GPU handles both source and sink instances the GPU must allow for nested interrupts originated by sinks That is a sink must be allowed to interrupt a source interrupt service routine but not another sink interrupt service routine Altera Corporation DisplayPort API Reference C Send Feedback UG 01131 2015 05 04 Example 8 1 Typical S btc_dprx_aux_ge btc_dprx_syslib API Reference 8 3 ink ISR Implementation t request 0 amp cmd amp address amp length data btc_dprx_aux_ha Example 8 2 Typical S BTC_DPTX_DISABL lt Enable nested if HPD asserte lt read btc_dp else if
170. splayPort Sink Register Map and DPCD Locations Ei Send Feedback END_ADDR to I2CI Altera Corporation UG 01131 10 32 DPRX_AUX_RESET 2015 05 04 Address 0x0117 WO 0x00000000 Table 10 65 DPRX_AUX_I2C1 Bits nm OS bmge O 31 15 Unused 14 8 PRD EC slave end address 7 Unused 6 0 SEART ADDR EC slave start address DPRX_AUX_RESET Address 0x0118 Direction WO Reset 0x00000000 Table 10 66 DPRX_AUX_RESET Bits CS ECS umction O 31 1 Unused 0 CLEAR Asserting CLEAR resets the AUX controller state machine e 0 2 No action e 1 AUX Controller reset DPRX_AUX_HPD HPD control Address 0x0119 Direction RW Reset 0x00000000 Table 10 67 DPRX_AUX_HPD Bits KC T C 31 13 Unused Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 Sink Supported DPCD Locations 10 33 pst ECS bm OS 12 EE Writing this bit at 1 generates a 0 75 ms long HPD IRQ low pulse This bit is WO To use this bit HPD_EN must be 1 11 HPD_EN HPD logic level 0 Deasserted low 1 Asserted high 10 0 Unused Sink Supported DPCD Locations The following table describes the DPCD locations or location groups that are supported in DisplayPort sink instantiations Table 10 68 DPCD Locations Location Name Address Without With Controller Controller EV Yes Yes DPCD RI 0x0000
171. st support is set to zero if MST is not supported and 1 if it is supported Example btc dprx syslib info pmaxsink pmst Altera Corporation DisplayPort API Reference C Send Feedback UG 01131 2015 05 04 btc_dprx_syslib_init 8 11 btc_dprx_syslib_init Prototype int btc_dprx_syslib_init void Thread safe No Available from ISR No Include lt btc dprx syslib h gt Return 0 success 1 fail Parameters No Description This function initializes the system library It should be invoked once after bt c_ dprx syslib add rx Example btc dprx syslib init Related Information btc dprx syslib add rx on page 8 9 btc dprx syslib monitor p Prototype int btc dprx syslib monitor void Thread safe No Available from Yes ISR Include lt bee cl sysililo ia gt Return 0 success 1 fail Parameters No Description This function calls the system library sink housekeeping monitor which is responsible for e Handling RX side received sideband message requests e Forwarding RX side sideband message replies The software should invoke this function periodically or at least every 50 ms Example Jace corz sywellilo monitor h p DisplayPort API Reference E Send Feedback Altera Corporation UG 01131 8 12 btc_dptx_syslib API Reference 201
172. t address only requests length is the original 1en byte sent by the source incremented by one When the request is a read data is not used and can be NULL This function provides all the functionality of the DPCD registers implemented inside the system library including e DPCD locations read write support e EDID read support e Link training execution e Forwarding of AUX channel replies back to the source btc dprx aux handler 0 pcmd padd plen pwrdata Related Information btc dprx aux get request on page 8 3 btc dprx aux post reply Prototype int btc dprx aux post reply BYTE rx idx BYTE cmd BYTE size BYTE data Thread safe Yes Available from Yes ISR Include btc dprx syslib h gt Return 0 success 1 fail Parameters e rx idx Sink instance index 0 3 e cma Command e size Number of data bytes transmitted 0 16 e data Pointer to data transmitted DisplayPort API Reference L Send Feedback Altera Corporation UG 01131 8 6 btc_dprx_baseaddr 2015 05 04 EE Description This function transmits an AUX channel reply to the connected DisplayPort source cmd is the reply command byte refer to the DisplayPort specification for more details When the reply includes read data data fills with the data bytes sent to the source To support replies with no data returned size is the actual 1en byte sent to the source incremented by
173. t Link Quality Generation register These bits are now combined into the DPTX TX CONTROL register e Added information about DPTX TEST 80BIT PATTERN1 3 bits e Added source supported DPCD locations e Added new sink supported DPCD location bits TEST REQUEST EST_LINK_RATE TEST_LANE_COUNT PHY_TEST_PATTERN and EST_80BIT_CUSTOM_PATTERN e Added Arria 10 information for the DisplayPort IP core hardware demonstration and simulation example December 2014 2014 12 30 Edited the DisplayPort RX link rate Clock Recovery interface for HBR2 from 4 50 Gbps to 5 40 Gbps 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as e
174. t Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_AUX_STATUS 10 23 The sink asserts the IRQ when Aux IRO EN 1 and MSG READY 1 To deassert IRO set AUx IRO EN to 0 or read from DPRX_AUX_COMMAND Address 0x0100 Direction RW Reset 0x00000000 Table 10 42 DPRX_AUX_CONTROL Bits ooo e deme oe O 31 MSG READY 0 Waiting for a request 1 A request has been completely received 30 PERDIH TIOTA 0 Busy sending a reply or request waiting 1 Ready to send a reply 29 9 Unused 8 RUX TROC EN Issues an IRQ to Nios II processor when the sink receives an AUX channel transaction from the source 0 Disable 1 Enable 7 TEZSTROBE Writing this bit at 1 starts a reply transmission Always read this bit as 0 6 5 Unused 4 0 DENSIS For the next transaction reply total length of message to be transmitted 1 17 for the last received transaction request total length of message received 1 17 DPRX AUX STATUS AUX transaction status register DPRX AUX STATUS Address 0x0101 Direction RO Reset 0x00000000 Table 10 43 DPRX AUX STATUS Bits mo ES Fx O 31 MSG READY 0 Waiting for a request 1 Receives a request DisplayPort Sink Register Map and DPCD Locations Altera Corporation LJ Send Feedback 10 24 DPRX_AUX_COMMAND UG 01131 2015 05 04 nm mue TI bmoe O 30 BEA
175. ted DisplayPort source cmd and address are the command byte and the address in the original reguest received respectively refer to the DisplayPort specification for more details When the request is a write data fills with the data bytes sent by the source To support address only requests length is the original 1en byte sent by the source incremented by one Example btc dprx aux get _ request 0 pcmd padd plen pwrdata Related Information btc dprx aux handler on page 8 4 btc dprx aux handler E Prototype int btc dprx aux handler BYTE rx idx BYTE cmd unsigned int address BYTE length BYTE data Thread safe Yes Available from Yes ISR Include btc dprx syslib h gt Return 0 success 1 fail Parameters e rx_idx Sink instance index 0 3 e cmd Command e address Address H length Length 0 16 e data Pointer to data being written Altera Corporation DisplayPort API Reference C Send Feedback UG 01131 2015 05 04 btc_dprx_aux_post_reply 8 5 Description Example This function processes an AUX channel request issued by the connected DisplayPort source cmd and address are the command byte and the address in the original request received respectively refer to the DisplayPort specification for more details When the request is a write data must point to the data bytes sent by the source To suppor
176. tion Controller Interface on page 4 11 Altera Corporation DisplayPort Source C Send Feedback UG 01131 2015 05 04 Embedded DisplayPort eDP Support Embedded DisplayPort eDP Support 4 5 The DisplayPort IP core is compliant with eDP version 1 3 eDP is based on the VESA DisplayPort standard It has the same electrical interface and can share the same video port on the controller The DisplayPort IP core supports e Full normal link training default e Fast link training mandatory eDP feature Source Parameters You set parameters for the source using the DisplayPort parameter editor Table 4 1 Source Parameters Device family Select the targeted device family Arria 10 Arria V GX Arria V GZ Cyclone V or Stratix V matches the project device family Support DisplayPort source Turn on to enable DisplayPort source Maximum video input color depth TX maximum link rate Select the video input interface port bits per color Determines top level video input port width for example 6 bpc 18 bpp 16 bpc 48 bpp Select the the maximum link rate 5 4 Gbps 2 7 Gbps 1 62 Gbps Note Cyclone V devices do not support 5 4 Gbps Maximum lane count Select the maximum lanes desired 1 2 or 4 Symbol output mode Specify how many symbols are transferred during each clock cycle dual or quad symbol or TX transceiver data width dual 20 bits or quad 40 bits Dual symbol m
177. ts and compiles and simulates them Scripts msim dp tcl Compiles and simulates the design in the ModelSim software Altera Corporation DisplayPort IP Core Simulation Example G send Feedback UG 01131 2015 05 04 Copy the Simulation Files to Your Working Directory 7 5 DR EE C all do Waveform that shows a combination of all waveforms reconfig do Waveform that shows the signals involved in reconfi guring the transceiver Waveform d files m video out do Waveform that shows the rx video out signals from the DisplayPort IP core mapped to the CVI input tx video in do Waveform that shows the tx vid v sync tx vid h sync de tx vid de tx vid f and tx vid data 23 0 signals at 256 pixels per line and 8 bpp i Miscellaneous files readme txt Documentation for the simulation example edid memory hex Initial content for the EDID ROM Table 7 2 Simulation Example Files for Arria V Cyclone V and Stratix V Devices Files are named prefix name extension where prefix represents the device av for Arria V devices cv for Cyclone V devices and sv for Stratix V devices System Verilog prefix dp harness sv Top level test harness HDL design files prefix dp example v Design under test DUT dp mif mappings v Table translating MIF mappings for transceiver reconfiguration dp analog mappings v Table translating VOD and pre emphasis s
178. ulation Example CJ Send Feedback UG 01131 2015 05 04 Figure 7 4 TX Reconfiguration Waveform View the Results 7 9 In the timing diagram below tx_1ink_rate is set to 1 HBR When the core makes a request the tx reconfig reg port goes high The user logic asserts tx_reconfig_ack and then reconfigures the transceiver During reconfiguration the user logic holds tx_reconfig_busy high the user logic drives it low when reconfiguration completes xcvr_mgmt_clk rx_link_rate rx_reconfig_req rx_reconfig_ack rx_reconfig_busy tx_link_rate tx_reconfig_req tx_reconfig_ack tx_reconfig_busy tx_vod tx_emp tx_analog_reconfig_req tx_analog_reconfig_ack tx_analog_reconfig_busy reconfig_busy reconfig_mgmt_address reconfig_mgmt_write reconfig_mgmt_writedata reconfig_mgmt_waitrequest reconfig_mgmt_read reconfig_mgmt_readdata DisplayPort IP Core Simulation Example E Send Feedback 01 Altera Corporation UG 01131 7 10 View the Results 2015 05 04 Figure 7 5 TX Analog Reconfiguration Waveform In the timing diagram below tx vod and tx emp are both set to 00 When the core makes a request the tx_analog_reconfig_req port goes high The user logic asserts tx_analog_reconfig_ack and then reconfigures the transceiver During reconfiguration the
179. ults in link training related AUX channel traffic and a corresponding new image size on the monitor Note If you do not see visible output on the monitor press push button CPU RESETN to generate a reset causing the DisplayPort TX core to re train the link Press push button 0 USER PB 0 to retrieve MSA statistics from the source and sink connections The Nios II Command Shell displays the AUX channel traffic during link training with the monitor Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Figure 6 12 MSA Output View the Results 6 27 TX Main stream attributes MISC1 D42C Nvid 2726 Utotal 6664 HSW 0112 Ustart 4668 USU 6666 2568 Uheight 1688 9065 CRC G 9292 CRC wess Stream 1 66 MISC1 6666 Nvid 6668 Utotal 6668 HSU 4668 Ustart 6666 USU z BAHA Uheight 66606 CRC G 6668 8000 1646 6632 6643 PON S 6668 6868 6868 6686 6868 6868 noon TX Link configuration Stream B ID lock 1 MSA lock 1 3FC4 Nuid 8068 2726 Utotal 1646 6686 HSU 6832 6112 Ustart 6843 6868 USW 6606 2568 Uheight 1668 Stream 1 B ID lock 1 MSR lock 1 2DE6 Nu id 8068 2592 Utotal 1245 6861 HSU 6268 6536 Ustart 6842 6868 USW 6866 1926 Vhe ight 1268 RA Link configuration SYM Done 5466 Mbps 4686 BER1 III BER3 66 MISCA 46 MISCi 66 36a8 CRC G 12
180. urns a 1 if link training fails or if the DPCD flag No AUX HANDSHAKE LINK TRAINING 0 at location 00103h e Ifnew_cfg 1 the IP core updates the sink s DPCD with the provided 1ink_ rate and lane_count sets its own transceiver with the provided volt_swing and pre_emph and then performs fast link training Ifnew_cfg 0 the IP core uses the current transceiver setting link rate and lane count and performs fast link training Example IEC _ Clot fast link itraimime il 4 1 d z Related Information btc_dptx_link_training on page 8 17 btc_dptx_link_training Prototype int btc_dptx_link_training unsigned int link_rate unsigned int lane_count Thread safe No Available from ISR Yes Include lt btc dptx syslib h gt Return 0 success 1 fail Parameters link rate Link rate Gbps 0 1 62 1 2 70 2 5 40 e lane count 1 2 or 4 Description This function performs link training with the connected DisplayPort sink Example btc dptx link training 1 4 DisplayPort API Reference Altera Corporation L Send Feedback 8 18 btc_dptx_set_color_space UG 01131 2015 05 04 btc_dptx_set_color_space Prototype int btc dptx set color space BYTE format BYTE bpc BYTE range BYTE colorimetry Thread safe No Available from ISR Yes Include loc etse aale oz Return 0 success 1 fail Parameters e format 0
181. user logic holds tx_analog_reconfig_busy high the user logic drives it low when reconfiguration completes xcvr mgmt ck rx link rate rx reconfig req rx reconfig ack rx reconfig busy tx link rate tx reconfig reg tx_reconfig_ack tx_reconfig_busy tx_vod 00 D emp 00 tx analog reconfig reg tx analog reconfig ack tx analog reconfig busy reconfig busy reconfig mgmt address H y reconfig_mgmt_write reconfig_mgmt_writedata H y X reconfig_mgmt_waitrequest reconfig_mgmt_read reconfig_mgmt_readdata y Altera Corporation DisplayPort IP Core Simulation Example CJ Send Feedback UG 01131 2015 05 04 Figure 7 6 RX Video Waveform Arria 10 Finite State Machine FSM 7 11 This timing diagram shows an example RX video waveform when interfacing to CVI The rx_vid_eol signal generates the h_sync pulse by delaying it by 1 clock cycle to appear in the horizontal blanking period after the active video ends VALID is deasserted The rx_vid_eof signal generates the v_sync pulse by delaying it by 1 clock cycle to appear in the vertical blanking period after the active video ends VALID is deasserted IX vid dk rx vid valid rx vid sol rx vid eol Ix vid sof
182. ut how to instantiate the PHY outside the DisplayPort IP core Updated the source and sink block diagrams Updated the source and sink register map information Added new sink register bits e LOA ACTIVE e PHY SINK TEST LANE SEL e PHY SINK TEST LANE EN e AUX IRO EN e TX STROBE e DPRX AUX STATUS bits e DPRX AUX I2C0 bits e DPRX AUX I2C0 bits e DPRX AUX HPD bits Removed these sink register bits e HPD IRO e HPD EN e DPRX AUX IRO EN bits Added a new source register bit e VIOTAL Added source TX transceiver interface signals Removed these source signals e xcvr refclk e tx serial data e xcvr reconfig Added sink audio and RX transceiver interface signals Removed these sink signals e xcvr refclk e rx serial data e xcvr reconfig Added information about Transceiver Reconfiguration Interface for source and sink Added information about single clock reference 135MHz for source and sink Added information about Bitec HSMC DisplayPort daughter card in the Hardware Demonstration chapter Updated the API reference Additional Information C Send Feedback UG 01131 2015 05 04 Document Revision History A 5 I RE EE November 2013 13 1 e Updated the source and sink register map information e Added dual and quad pixel mode support e Added support for quad symbol 40 bit transceiver data interface e Added support for Cyclone V devices e Add
183. ve been taken into use DPRX MST VCPTABO VC Payload ID Table DisplayPort Sink Register Map and DPCD Locations LJ Send Feedback Altera Corporation UG 01131 10 18 DPRX_MST_VCPTAB1 2015 05 04 Address 0x00a2 Direction RW Reset 0x00000000 Table 10 34 DPRX_MST_VCPTABO Bits mn ee CE 31 28 VCPSLOT7 VC payload ID or slot 7 27 24 VCPSLOT6 VC payload ID or slot 6 23 20 VCPSLOTS VC payload ID or slot 5 19 16 VCPSLOT4 VC payload ID or slot 4 15 12 VCPSLOT3 VC payload ID or slot 3 11 8 VCPSLOT2 VC payload ID or slot 2 74 VCPSLOTI VC payload ID or slot 1 3 0 Reserved Reserved DPRX MST VCPTAB1 VC Payload ID Table Address 0x00a3 Direction RW Reset 0x00000000 Table 10 35 DPRX MST VCPTABI Bits mo CCS Fan 31 28 VCPSLOT15 VC payload ID or slot 15 27 24 VCPSLOT14 VC payload ID or slot 14 23 20 VCPSLOT13 VC payload ID or slot 13 19 16 VCPSLOT12 VC payload ID or slot 12 15 12 VCPSLOT11 VC payload ID or slot 11 11 8 VCPSLOT10 VC payload ID or slot 10 7 4 VCPSLOT9 VC payload ID or slot 9 Altera Corporation DisplayPort Sink Register Map and DPCD Locations C Send Feedback UG 01131 2015 05 04 DPRX_MST_VCPTAB2 10 19 mn o ooa non O 3 0 VCPSLOT8 DPRX MST VCPTAB2 VC Payload ID Table Address 0x00a4 Direction RW Reset 0x00000000 Table 10 36 DPRX MST VCPTAB2 Bits VC payload ID or slot 8 mn IL CCS CE 31 28 VCPSLOT23
184. very core gathers information about the current MSA and the currently used link rate from the DisplayPort sink Altera Corporation DisplayPort IP Core Hardware Demonstration C Send Feedback UG 01131 2015 05 04 Clock Recovery Core Parameters 6 5 The clock recovery core produces resynchronized video data together with the following clocks e Recovered video pixel clock e Second clock with twice the recovered pixel clock frequency The video output data is synchronous to the recovered video clock You can use the second clock as a reference clock for the TX transceiver which is optionally used to serialize the video output data Figure 6 4 Clock Recovery Core Functional Diagram The following shows a simplified functional diagram of the clock recovery core RX MSA p Video Timing video Output Syncs Generator Video Input Data gt gt gt Video Output Data FIFO RX Video Clock gt v Fill Status Loop Recovered Video Clock RX Link Altera fPLL Controller Clock Recovered Video Clock x2 fPLL Controller fPLL Altera fPLL Reconfiguration P gt Reconfiguration Avalon Master Controller The clock recovery core clocks the video data input gathered from the DisplayPort sink into a dual clock FIFO at the received video clock speed The core reads from the video data input using the recovered video clock e Video Timing Generator Thi
185. x ss clk Clock tx ss clk Output TX transceiver clock out and clock for secondary stream MSA Conduit tx_ss_clk txN_msa 191 0 Input Input port for fixed MSA parameters txN_ P msa_ conduit txN_ss_data 127 0 Input txN_ss_valid Input Secondary e Stream AV ST ik txN_ss_ready utp econdary stream SE Beggen ut interface txN_ss txN ss sop Input txN ss eop Input Table 4 7 Audio Interface mis the number of TX audio channels n is the stream number for example tx audio represents Stream 0 tx1 audio represents Stream 1 and so on Interface Signal Type Clock Direction Description Domain Clock xN_audio_clk Input Audio clock Audio ee Input txN audio Condit txN_audio S Audio sample data clk txN_audio_valid Input interface txN_audio_mute Input Altera Corporation DisplayPort Source CJ Send Feedback UG 01131 2015 05 04 Table 4 8 TX Transceiver Interface n is the number of TX lanes s is the number of symbols per clock Controller Interface 4 11 Note Connect the DisplayPort signals to the Native PHY signals of the same name Interface Port Type Clock Direction Description Domain TX transceiver interface Clock tx std clkout n 1 0 Input TX transceiver clock out Conduit tx std tx parallel Output Parallel data for TX clkout data n s 10 1 0 transceiver Conduit N A tx_pll_powerdown Output PLL power down for TX transc
186. xpressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN DIS RYA 101 Innovation Drive San Jose CA 95134 A 2 Document Revision History UG 01131 2015 05 04 I RE EE December 2014 Altera Corporation 2014 12 15 Added information about multi stream support MST 1 to 4 source and sink streams You can access this feature using these parameters e Support MST e Max stream count Added support for 4Kp60 resolution Added information about clock recovery feature for the hardware demonstration Removed information for double reference clocks 162MHz and 270MHz for transceiver clocking The IP core no longer supports double reference clocks Added new source registers e 0x00a0 DP1 _MST_CONTROL1 e 0x00a2 DP S _VCP ABO e 0x00a3 DP _VCP AB e 0x00a3 DP _VCP AB1 _VCP AB2 e 0x00a5 DP _VCP AB3 e 0x00a6 DP _VCP AB4 e 0x00a7 DP _VCP AB5 rx x X x e 0x00a4 DPTX x x x e 0x00a8 DPTX X NU U U U U U U U _VCP AB6 e 0x00a9 DP _VCP AB7 e 0x00aa DPTX M S _TAV Added new sink registers e 0x0006 DPRX_BER_CNTI e 0x0007 DPRX BER CNTI e 0x00a0 DPRx MS e 0x00al DPRX MS e 0x00a2

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