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SmartFusion2 High Speed DDR Interfaces User's Guide

1. ree 7 Figure 1 13 FIC 2 Configuration When enabling this option the MDDR APB S PCLK and FIC 2 APB M PCLK signals are exposed in SmartDesign MDDR APB S PCLK must be connected to FIC 2 APB M PCLK The FIC 2 APB M PCLK clock is generated from the MSS CCC and is identical to M3 CLK 4 VO Configuration I O settings such as like ODT and drive strength can be configured as shown in Figure 1 14 using the I O Editor in the Libero design software AE VO Editor E m z z Sa Bile Edit View Tools Help O SR E 506 ee I O Editor Port Name Direction 1 0 standard Pin Number Locked Bankname 10 state in Fiash Freeze mode Resistor Pull 1 0 avaiable in Flash Freeze mode v Schmitt Tigger Od T 7 MDDR OE Output ssTLISI E29 7 Banko TRISTATE None B MDDR_CLK Output SSTLISI A25 Vi BankO TRISTATE None aa Output SSTLISI B25 7 Banko TRISTATE None MDDR_CS_N Output SSTLISI F29 v Banko TRISTATE None MDDR DM RDQS 0 Inout SSTLISI D13 V Banko TRISTATE None On 40 MDDR DM RDQS 1 Inout SSTLISI D16 Vv Banko TRISTATE None On 40 MDDR DQ 0 Inout SSTLISI A12 Vi BankO TRISTATE None On 40 MDDR POL Inout SSTLISI B12 v Banko TRISTATE None On 40 MDDR_DQ 2 Inout SSTLISI D12 v BankO TRISTATE None oa O
2. AHBIF 0 va En REY remar H rs Corea HEL Ite 0 er WIK HEESEN Figure 2 24 SmartDesign Canvas 14 To verify the design in Libero SoC create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor Simulate the design and observe the AHBI read and write transactions Note Microsemi provides the System Builder tool to simplify design creation To use System Builder select Use System Builder while creating a new project from the Design Templates and Creators panel in Libero SoC Follow the steps in the System builder Device Features GUI and generate the design 200 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR Memory Device Examples This section describes how to connect DDR memories to SmartFusion2 FDDR PADs with examples Example 1 Connecting 32 Bit DDR2 to FDDR PADs Figure 2 25 shows DDR2 SDRAM connected to the FDDR of a SmartFusion2 device Micron s MT47H64M16 is a 128 MB density device with x16 data width The FDDR is configured in Full Bus Width mode and without SECDED The total amount of DDR2 memory connected to the FDDR is 256 MB FDDR_PADS MT47H64M16 Se N pia SASN hr ae
3. Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 8 1 CO_WU_RXDATA_INT_ECC 0x0 Internal SECDED This contains the SECDED associated with the data bus Data on this bus is presented to the Internal SECDED decode logic 0 CO WU RXDATA MASK INT ECC 0x0 Mask to be used during production test 62 Revision 2 Table 1 33 DDRC ADDR MAP COL 1 CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_ADDR_MAP_COL_1_CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 15 12 REG DDRC ADDRMAP COL B2 0x0 Full bus width mode Selects column address bit 3 Half bus width mode Selects column address bit 4 Quarter bus width mode Selects column address bit 5 Valid range 0 to 7 Internal base 2 The selected address bit is determined by adding the internal base to the value of this field 11 8 REG_DDRC_ADDRMAP_COL_B3 0x0 Full bus width mode Selects column address bit 4 Half bus width mode Selects column addre
4. Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 0 REG_DDRC_DIS_DQ 0x0 When 1 DDRC will not de queue any transactions from the CAM Bypass will also be disabled All transactions are queued in the CAM This is for debug only no reads or writes are issued to DRAM as long as this is asserted This bit is intended to be switched on the fly DDRC_MODE_CR Table 1 30 DDRC MODE CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 8 REG_DDRC_DDR3 0x0 1 DDR3 operating mode 0 DDR2 operating mode 7 REG_DDRC_MOBILE 0x0 1 Mobile LPDDR1 DRAM device in use 0 Non mobile DRAM device in use 6 REG DDRC SDRAM 0x0 1 SDRAM mode 0 Non SDRAM mode Only present in designs that support SDRAM and or mSDR devices 5 REG DDRC TEST MODE 0x0 1 Controller is in test mode 0 Controller is in normal mode 4 2 REG DDRC MODE 0x0 DRAM SECDED mode 000 No SECDED 101 SECDED enabled All other selections are reserved 1 0 REG DDRC DATA BUS WIDTH 0x0 00 Full DQ bus width to DRAM 01 Half DQ bus width
5. Bus Width M2S050 FG896 M2S080 M2S120 FC1152 Full bus width v vA Half bus width v vA Quarter bus width v Burst Mode The DDR controller performs burst write operations to DDR memory depending on the Burst mode selection Burst mode is selected as sequential or interleaving by configuring REG DDRC BURST MODE to 1 or 0 Burst length can be selected as 4 8 or 16 by configuring REG DDRC BURST RDWR Supported burst modes for DDR SDRAM types and PHY widths are given in Table 2 13 For M2S050 only sequential Burst mode and a burst length of 8 is supported Table 2 13 Supported Burst Modes for M2S080 and M25120 Sequential Interleaving Bus Width Memory Type 32 4 LPDDR1 v DDR2 v DDR3 16 LPDDR1 DDR2 DDR3 LPDDR1 DDR3 DDR2 SESISISISISISISIS l Configuring Dynamic DRAM Constraints Timing parameters for DDR memories must be configured according to the DDR memory specification Dynamic DRAM constraints are subdivided into three basic categories e Bank constraints affect the transactions that are scheduled to a given bank e Rank constraints affect the transactions that are scheduled to a given rank e Global constraints affect all transactions Dynamic DRAM Bank Constraints Revision 2 189 I Microsemi Fabric DDR Subsystem The timing constraints which affect the transactions to a bank are listed in Table 2 14 The c
6. Bit Name Reset Description Number Value 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 F AXI AHB MODE 0x0 1 AXI interface in the fabric will be selected 0 AHB interface in the fabric will be selected PHY SELF REF EN Table 2 30 PHY SELF REF EN Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 PHY_SELF_REF_EN 0x0 If1 automatic calibration lock is enabled FDDR_FAB_PLL_CLK_SR Table 2 31 FDDR FAB PLL CLK SR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 FAB_PLL_LOCK 0x0 Indicates the lock status of the FPLL FDDR_FPLL_CLK_SR Table 2 32 FDDR FPLL CLK SR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read
7. Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_RD_DQS_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_RD_DQS_SLAVE_DELAY If REG PHY RD DQS SLAVE FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY RD DQS SLAVE FORCE CR Table 1 143 PHY RD DQS SLAVE FORCE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_RD_DQS_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for read DQS slave DLL with the value of PHY_RD_DQS_SLAVE_DELAY 120 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_RD_DQS_SLAVE_RATIO_1_CR Table 1 144 PHY RD DQS SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY RD DQS SLAVE RATIO 0x0040 1
8. MDDR DQS TMATCH ECC OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH ECC IN AXI or AHB interface depending on configuration 12 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide AXI Slave Interface Table 1 5 shows the MDDR AXI slave interface signals with their descriptions These signals will be available only if MDDR interface is configured for AXI mode For more details of AXI protocol refer to AMBA AXI v1 0 protocol specification Table 1 5 AXI Slave Interface Signals Signal Name Direction Polarity Description MDDR DDR AXI S ARREADY Output High Indicates whether or not the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready MDDR DDR AXI S AWREADY Output High Indicates that the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready MDDR DDR AXI S BID 3 0 Output Indicates response ID The identification tag of the write response MDDR DDR AXI S BRESP 1 0 Output Indicates write response This signal indicates the status of the write transaction 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error MDDR DDR AXI S BVALID Output High Indicates whether a valid write response is available 1 Write respo
9. Revision 2 117 lt gt Microsemi MDDR Subsystem PHY GATELVL INIT RATIO 2 CR Table 1 135 PHY GATELVL INIT RATIO 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_GATELVL_INIT_RATIO Ox0 31 16 of REG_PHY_GATELVL_INIT_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY_GATELVL_INIT_RATIO_3 CR Table 1 136 PHY_GATELVL_INIT_RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_GATELVL_INIT_RATIO Ox0 47 32 of REG_PHY_GATELVL_INIT_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY_GATELVL_INIT_RATIO_4_CR Table 1 137 PHY GATELVL INIT RATIO 4 CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 0 REG_PHY_GATELVL_INIT_RATI
10. 3 0 REG_DDRC_ADDRMAP_COL_B11 0x0 Full bus width mode Selects column address bit 13 Half bus width mode Unused To make it unused this should be tied to OxF Quarter bus width mode Unused To make it unused this should be tied to OxF Valid range 0 to 7 and 15 Internal base 11 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 11 is set to 0 64 Revision 2 DDRC ADDR MAP ROW 1 CR Table 1 35 DDRC ADDR MAP ROW 1 CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 15 12 IREG DDRC ADDRMAP ROW BO 0x0 Selects the address bits used as row address bit 0 Valid range 0 to 11 Internal base 6 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 11 8 REG DDRC ADDRMAP ROW B1 0x0 Selects the address bits used as row address bit 1 Valid range 0 to 11 Internal base 7 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 7 4 REG DDRC ADDRMAP ROW B2 11 0x0 S
11. REG DDRC DIS WC REG DDRC DIS ACT BYPASS REG DDRC DIS RD BYPASS 0x0 0x0 0x0 When 1 disable write combine Only present in designs supporting activate bypass When 1 disable bypass path for high priority read activates Only present in designs supporting read bypass When 1 disable bypass path for high priority read page hits REG_DDRC_DIS_PRE_BYPASS 0x0 Only present in designs supporting precharge bypass When 1 disable bypass path for high priority precharges REG DDRC DIS COLLISION PAGE OPT 0x0 When this is set to 0 auto precharge is disabled for the flushed command in a collision case Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same address with REG_DDRC_DIS_WC bit 1 where same address comparisons exclude the two address bits representing the critical word REG DDRC DIS SCRUB 0x0 This feature is not supported Only the default value works 1 Disable SECDED scrubs 0 Enable SECDED scrubs Valid only when REG_DDRC_ECC_MODE 100 or 101 Revision 2 75 lt gt Microsemi MDDR Subsystem DDRC_MODE_REG_RD_WR_CR Table 1 55 DDRC_MODE_REG_RD_WR_CR Bit Number Name Reset Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi
12. 11 6 REG DDRC T RC 0x0 tRC Minimum time between activates to same bank specification 65 ns for DDR2 400 and smaller for faster parts Unit clocks 5 0 REG_DDRC_T_FAW 0x0 tFAW Valid only in burst of 8 mode At most 4 banks must be activated in a rolling window of tFAW cycles Unit clocks DDRC_DRAM_RD_WR_LATENCY_CR Table 1 45 DDRC_DRAM_RD_WR_LATENCY_CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_DDRC_WRITE_LATENCY 0x0 Number of clocks between the write command to write data enable PHY 4 0 REG_DDRC_READ_LATENCY 0x0 Time from read command to read data on DRAM interface Unit clocks This signal is present for designs supporting LPDDR1 DRAM only It is used to calculate when the DRAM clock may be stopped Revision 2 69 lt gt Microsemi MDDR Subsystem DDRC_DRAM_RD_WR_PRE_CR Table 1 46 e DDRC DRAM RD WR PRE CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG DDRC WR2PRE 0x0 Minimum time between write and precharge
13. Note 1 Some registers map multiple source address bits REG DDRC ADDRMAP ROW BO 11 2 To arrive at the right address for the DDR controller the system address or AXI address bits 4 0 are mapped by the MDDR In full bus width mode the system address bits 4 0 are used to map the lower column address bits CO C1 C2 In half bus width mode the system address bits 4 0 are used to map the lower column address bits CO C1 C2 C3 ak ON gt Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Example In this example the Address map registers are configured to access a 512 MB DDR3 SDRAM memory MT41J512M8RA from the MDDR subsystem The 512M x 8 bit DDR3 memory module has 3 bank address lines 16 rows and 10 columns The column address bits 3 to 9 are mapped for system address bit 5 to system address bit 11 To map the column 3 bit C3 to address 5 the field is configured to 3 as the base value is 2 Similarly the other column address bits are configured DDRC_ADDR_MAP_COL_1_CR 0x3333 DDRC_ADDR_MAP_COL_2_CR 0x3FFF DDRC_ADDR_MAP_COL_3_CR 0x3300 The bank address bits 0 to 2 are mapped for system address bit 12 to system address bit 14 To map the bank bit0 to address 12 the field is configured to A as the base value is 2 Similarly the other bank address bits are configured DDRC_ADDR_MAP_BANK_CR 0xAAA The row add
14. The FPLL generates a lock signal FPLL_LOCK to indicate that the FPLL is locked onto the CLK_BASE signal The precision of the FPLL_LOCK discrimination can be adjusted using the lock window controls The lock window represents the phase error window for lock assertion The lock window can be adjusted between 500 parts per million ppm and 32 000 ppm in powers of 2 The integration of the lock period can be adjusted using a built in lock counter The lock counter or lock delay indicates the number of reference clock cycles to wait after the FPLL is locked for asserting the FPLL_LOCK signal The lock delay is useful for avoiding false toggling of the FPLL lock signal The lock counter can be configured between 32 and 32 768 cycles in multiples of 2 There are two interrupts to indicate FPLL lock assertion and deassertion The FPLL_LOCK signal can also be monitored by user logic in the FPGA fabric FACC Within the FDDR clock controller the FACC is responsible for interfacing with the FPLL generating the aligned clocks required by the FDDR subsystem and controlling the alignment of FPGA fabric interface clocks The clocks generated by the FACC are as follows e FDDR_CLK clocks the FDDR subsystem FDDR_CLK can be operated up to 333 MHz depending on the type of DDR present in the system e DDR_FIC_CLK clocks the DDR FIG and defines the frequency at which the connected FPGA fabric subsystem is intended to operate e FACC divider divides the
15. Not supported in this version of the DDRC controller always reads as zero 10 REG_DDRC_BURST_MODE 0x0 1 Interleaved burst mode 0 Sequential burst mode The burst mode programmed in the DRAM mode register and the order of the input data to the controller should both match the value programmed in the REG DDRC BURST MODE register 9 2 REG DDRC GO2CRITICAL HYSTERESIS 0x0 Indicates the number of that CO_GS_GO2CRITICAL_RD or CO_GS_GO2CRITICAL_WR must be asserted before the corresponding queue moves to the critical state in the DDRC cycles REG_DDRC_PREFER_WRITE 0x0 If set the bank selector prefers writes over reads REG_DDRC_FORCE_LOW_PRI_N 0x0 Active Low signal When asserted 0 all incoming transactions are forced to low priority Forcing the incoming transactions to low priority implicitly turns off bypass Revision 2 83 lt gt Microsemi MDDR Subsystem DDRC_PERF_PARAM_3_CR Table 1 70 DDRC PERF PARAM 3 CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG DDRC EN 2T TIMING MODE 0x0 1 DDRC uses 2T timing 0 DDRC uses 1T timing DDRC DFI RDDATA EN CR Table 1 71 DDRC DFI RDDATA EN CR Bit Reset
16. operation 0 REG PHY RDC FIFO RST ERR CNT CLR 0x0 Clear reset for counter RDC FIFO RST ERR CNT 0 No clear 1 Clear Revision 2 131 lt gt Microsemi MDDR Subsystem PHY_RDC_WE_TO_RE_DELAY_CR Table 1 171 PHY RDC WE TO RE DELAY CR Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 REG_PHY_RDC_WE_TO_RE_DELAY 0x0 Register input specified in number of clock cycles This is valid only if USE_FIXED_RE is High As read capture FIFO depth is limited to 8 entries only the recommended value for this port is less than 8 even though a higher number may work in some cases depending upon memory system design PHY_USE_FIXED_RE_CR Table 1 172 PHY USE FIXED RE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_USE_FIXED_RE 0x0 1 PHY generates FIFO read enable after fixed number of clock cycles as defined by REG_PHY_RDC_WE_TO_RE_DELAY 3 0 0 PHY uses the NOT_EMPTY method to do the read enable generation Note This port must be
17. 15 0 REG DDRC EMR 0x0402 Value to be loaded into DRAM EMR registers Bits 9 7 are for OCD and the setting in this register is ignored The controller sets those bits appropriately 68 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_INIT_EMR2_CR Table 1 42 DDRC INIT EMR2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_EMR2 0x0 Value to be loaded into DRAM EMR2 registers DDRC_INIT_EMR3_CR Table 1 43 DDRC INIT EMR3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG DDRC EMR3 0x0 Value to be loaded into DRAM EMR 3 registers DDRC_DRAM_BANK_TIMING_PARAM_CR Table 1 44 DDRC DRAM BANK TIMING PARAM CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
18. 57 I Microsemi MDDR Subsystem Table 1 24 DDR Controller Configuration Register continued Address Register Reset Register Name Offset Type Source Description DDRC LUE ADDRESS 1 SR 0x104 RO PRESET_N DDRC last uncorrected error address register DDRC LUE ADDRESS 2 SR 0x108 RO PRESET_N DDRC last uncorrected error address register DDRC_LCE_SYNDROME_1_SR 0x10C RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 2 SR 0x110 RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 3 SR 0x114 RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 4 SR 0x118 RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 5 SR 0x11C RO PRESET NIDDRC last corrected error syndrome register DDRC_LCE_ADDRESS_1_SR 0x120 RO PRESET NIDDRC last corrected error address register DDRC LCE ADDRESS 2 SR 0x124 RO PRESET NIDDRC last corrected error address register DDRC LCB NUMBER SR 0x128 RO PRESET NIDDRC last corrected bit number register DDRC LCB MASK 1 SR 0x12C RO PRESET NIDDRC last corrected bit mask status register DDRC_LCB_MASK_2_SR 0x130 RO PRESET NIDDRC last corrected bit mask status register DDRC LCB MASK 3 SR 0x134 RO PRESET NIDDRC last corrected bit mask status register DDRC LCB MASK 4 SR 0x138 RO PRESET NIDDRC last corrected bit mask status register DDRC ECC INT SR 0x13C RO
19. Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 2 11 FDDR Configurations for Accessing DDR3 Memories at 333 MHz continued Register Name and Desired Value for Configured Value Field Value to be Loaded MT41J512M8RA tCCD 2 2 clks tRCD 6 18 ns DDRC_PWR_SAVE_1_CR 0x506 Clocks to power down 3 3 32 96clks Self refresh gap 0x14 20 20 32 640clks DDRC ZQ LONG TIME CR 0x200 512 ciks ZQ SHORT TIME CR 0x40 64 ciks DDRC PERF PARAM 1 CR 0x4000 Burst length 0x2 Burst length is 8 HPR_QUEUE_PARAM_1_CR 0x80F8 XACT_RUN_LENGTH 0x8 8 transactions MIN_NON_CRITICAL OxF 15 clks MAX STARVE 0x1 15 clks HPR QUEUE PARAM 2 CR MAX_STARVE 0x7 DDRC_PERF_PARAM_2_CR 0x0 Burst mode Sequential FIC_2 Configuration This is required for initializing the FDDR registers from Cortex M3 processor Configure the FIC_2 Peripheral Initialization block as shown in Figure 2 11 to expose the FIC 2 APB MASTER interface in Libero SmartDesign CoreSF2Config must be instantiated in SmartDesign and make the connections Revision 2 187 I Microsemi Fabric DDR Subsystem illustrated in the FIC 2 Configurator Figure 2 11 shows the connectivity between the APB configuration interface and FDDR subsystem Figure 2 11 FIC Configuration While enabling this option the APB S PCLK and FIC 2 APB M PCLK signals are exposed in SmartDesign The
20. Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 54 48 bits of REG PHY FIFO WE SLAVE RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY GATELVL INIT MODE CR Table 1 133 PHY GATELVL INIT MODE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY GATELVL INIT MODE 0x0 The user programmable init ratio selection mode 1 Selects a_ starting ratio value based on REG_PHY_GATELVL_INIT_RATIO port 0 Selects a starting ratio value based on write leveling of the same data slice PHY_GATELVL_INIT_RATIO_1_CR Table 1 134 PHY GATELVL INIT RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_GATELVL_INIT_RATIO Ox0 15 0 of REG_PHY_GATELVL_INIT_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc
21. Valid range 0 to 11 and 15 Internal base 20 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 14 is set to 0 3 0 REG_DDRC_ADDRMAP_ROW_B15 0x0 Selects the address bit used as row address bit 15 Valid range 0 to 11 and 15 Internal base 21 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 15 is set to 0 66 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_INIT_1_CR Table 1 37 DDRC INIT 1 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 REG_DDRC_PRE_OCD_X32 0x0 Wait period before driving the OCD Complete command to DRAM Units are in counts of a global timer that pulses every 32 clock cycles There is no known specific requirement for this It may be set to zero 7 1 REG_DDRC_FINAL_WAIT_X32 0x0 Cycles to wait after completing the DRAM initialization sequence before starting the dynamic scheduler Units are in counts of a global timer that pulses every 32 clock cycles There is known specific requirement for this it may be set to
22. 15 0 REG_PHY_BIST_SHIFT_DQ OxO 15 0 bits of REG PHY BIST SHIFT DQ Determines whether early shifting is required for a particular DQ bit when REG PHY BIST MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift Revision 2 109 lt gt Microsemi MDDR Subsystem PHY_BIST_TEST_SHIFT_PATTERN_2_CR Table 1 111 PHY BIST TEST SHIFT PATTERN 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_SHIFT_DQ Ox0 31 16 bits of REG_PHY_BIST_SHIFT_DQ Determines whether early shifting is required for a particular DQ bit when REG PHY BIST MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift PHY BIST TEST SHIFT PATTERN 3 CR Table 1 112 PHY BIST TEST SHIFT PATTERN 3 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 0 REG_PHY_BIST_SHIFT_DQ 0x0 43 32 bits of REG_PHY_BIST_SHIFT_DQ Determines whether early shifting is required for a particular DQ bit whe
23. 160 Revision 1 Updated Fabric DDR Subsystem section SAR 41901 161 November 2012 dated MDDR Subsystem section SAR 41901 7 Updated Fabric DDR Subsystem section SAR 41979 161 Updated the user s guide SAR 42443 NA Updated MDDR Subsystem section SAR 42751 7 Revision 2 239 lt gt Microsemi B Product Support Microsemi SoC Products Group backs its products with various support services including Customer Service Customer Technical Support Center a website electronic mail and worldwide sales offices This appendix contains information about contacting Microsemi SoC Products Group and using these support services Customer Service Contact Customer Service for non technical product support such as product pricing product upgrades update information order status and authorization From North America call 800 262 1060 From the rest of the world call 650 318 4460 Fax from anywhere in the world 408 643 6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware software and design questions about Microsemi SoC Products The Customer Technical Support Center spends a great deal of time creating application notes answers to common design cycle questions documentation of known issues and various FAQs So before you contact us please visit our online resources It
24. 3 2 REG_DDRC_RANKO_WR_ODT 0x0 0 Indicates which remote ODTs should be turned on during a write to rank 0 Each rank has a remote ODT in the DRAM which can be turned on by setting the appropriate bit here Set this bit to 1 to enable its ODT 1 Uppermost bit is unused 1 0 REG_DDRC_RANKO_RD_ODT 0x0 0 Indicates which remote ODTs should be turned on during a read to rank 0 Each rank has a remote ODT in the DRAM which can be turned on by setting the appropriate bit here Set this bit to 1 to enable its ODT 1 Uppermost bit is unused Revision 2 73 lt gt Microsemi MDDR Subsystem DDRC ODT PARAM 2 CR Table 1 53 DDRC ODT PARAM 2 CR Bit Number Reset Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 6 REG_DDRC_RD_ODT_HOLD 0x0 Cycles to hold ODT for a READ command 0 ODT signal is ON for 1 cycle 1 ODT signal is ON for 2 cycles and so on 5 2 REG_DDRC_WR_ODT_HOLD 0x0 1 0 REG_DDRC_WR_ODT_BLOCK 0x0 Cycles to hold ODT for a WRITE command 0 ODT signal is ON for 1 cycle 1 ODT signal is ON for 2 cycles and so on 00 Block read write scheduling for 1 cycle when write requires changing ODT settings 01 Block read write scheduling f
25. CLK_N CSN RASN WEN ADDR 12 0 BA 2 0 LDM LDQS DQ 1 0 Figure 1 28 x16 LPDR1SDRAM Connection to MDDR Revision 2 53 I Microsemi MDDR Subsystem MDDR Configuration Registers This section provides MDDR subsystem registers along with the address offset functionality and bit definitions The registers are categorized based on the controller blocks in the MDDR subsystem Table 1 22 lists the categories of registers and their offset addresses The base address of the MDDR subsystem registers is 0x40020800 Table 1 22 Address Table for Register Interfaces Registers Address Offset Space DDR Controller Configuration Register 0x000 0x1FC PHY Configuration Register Summary 0x200 0x3FC DDR FIC Configuration Register Summary 0x400 0x4FC Reserved 0x500 0x7FC SYSREG Configuration Register Summary In addition to the specific MDDR subsystem registers the registers listed in Table 1 23 also control the behavior of the MDDR subsystem These registers are located in the SYSREG section of the user s guide and are listed here for convenience Refer to the System Register Block in the SmartFusion2 Microcontroller Subsystem User s Guide for a detailed description of each register and associated bits Table 1 23 e SYSREG Configuration Register Summary Register Flash sg Write Reset Source Description Register Name ype Protect MDDR_CR RW P Register
26. DDRC LUE SYNDROME 4 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 63 48 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CR is written over by the system 94 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_LUE_SYNDROME_5_SR Table 1 88 DDRC LUE SYNDROME 5 SR Bit Reset Number Name Value Description 16 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a res
27. DDRC_DRAM_RD_WR_PRE_CR 0x058 RW PRESET_N DDRC DRAM Read Write Precharge Timing register Revision 2 55 I Microsemi MDDR Subsystem Table 1 24 DDR Controller Configuration Register continued 56 Revision 2 Address Register Reset Register Name Offset Type Source Description DDRC DRAM MR TIMING PARAM CR 0x05C RW PRESET_N DDRC DRAM Mode Register Timing Parameter register DDRC DRAM RAS TIMING CR 0x060 RW PRESET_N DDRC DRAM RAS Timing Parameter register DDRC_DRAM_RD_WR_TRNARND_TIME_CR 0x064 RW PRESET_N DDRC DRAM Read Write Turn around Timing register DDRC_DRAM_T_PD_CR 0x068 RW PRESET NIDDRC DRAM Power Down Parameter register DDRC DRAM BANK ACT TIMING CR 0x06C RW PRESET_N DDRC DRAM Bank Activate Timing Parameter register DDRC_ODT_PARAM_1_CR 0x070 RW PRESET_N DDRC ODT Delay Control register DDRC ODT PARAM 2 CR 0x074 RW PRESET_N DDRC ODT Hold Block cycles register DDRC ADDR MAP COL 3 CR 0x078 RW PRESET_N Upper byte is DDRC Column Address Map register and lower byte controls debug features DDRC MODE REG RD WR CR 0x07C RW PRESET N DDRC Mode Register Read Write Command register DDRC MODE REG DATA CR 0x080 RW PRESET NIDDRC Mode Register Write Data Register DDRC PWR SAVE 1 CR 0x084 RW PRESET N DDRC Power Save register DDRC PWR SAVE 2 CR 0x088 RW PRESET N DDRC Power Save register
28. FIC Fabric interface controller LPDDR Low power double data rate MDDR MSS double data rate SMC Soft memory controller List of Changes The following table lists critical changes that were made in each revision Changes Page OE 2 ee ae Address Mapping section SAR 45761 Eid April 2013 Revision 1 Updated 3 Dual AHB Interface section SAR 41901 November 2012 214 Revision 2 lt gt Microsemi 3 DDR Bridge Introduction The DDR bridge facilitates multiple AHB bus masters to access a single AXI slave and optimizes read and write operations from multiple AHB masters to a single external DDR memory SmartFusion2 devices have three instances of the DDR bridge one each for the microcontroller subsystem MSS FDDR and MDDR subsystems as shown in Figure 3 1 The DDR bridge implemented in the MSS shown in red provides an interface between AHB masters within the MSS for accessing DDR memory The DDR bridge implemented in the MDDR subsystem shown in green provides an interface between the user implemented AHB masters in the FPGA fabric for accessing DDR memory Similarly the DDR bridge in the FDDR subsystem facilitates fabric masters to access DDR memory ARM Cortex M3 rit FFI par bit AHB AXI M S Transaction 2 bit AHB Controller MDDR Subsystem AHB s Matrix DDR FIC M 32 bit AHB FPGA Fabric AXI Transaction DDR S Controller Memory FDDR
29. Mode M2S050 FG896 M2S080 M2S120 FC1152 Full bus width mode FDDR DQ ECC 3 0 FDDR DQ ECC 3 0 Half bus width mode FDDR DQ ECC 1 0 FDDR DQ ECC 1 0 Quarter bus width mode FDDR DQ ECC 0 When the controller detects a correctable SECDED error it does the following e Generates an interrupt signal which can be monitored by reading the interrupt status register DDRC_ECC_INT_SR The FDDR also generates ECCINT interrupt signal which can be monitored from FPGA fabric Sends the corrected data to the read requested MSS FPGA fabric master as part of the read data Sends the SECDED error information to the DDRC_LCE_SYNDROME_1_SR register e Performs a read modify write operation to correct the data present in the DRAM Revision 2 179 I Microsemi Fabric DDR Subsystem 180 When the controller detects an uncorrectable error it does the following e Generates an interrupt signal which can be monitored by reading the interrupt status register DDRC_ECC_INT_SR The FDDR also generates an ECC_INT interrupt signal which can be monitored from FPGA fabric Sends the data with error to the read requested MSS FPGA fabric master as part of the read data Sends the SECDED error information to the DDRC_LUE_SYNDROME_1_SR register The following SECDED Registers can be monitored for identifying the exact location of an error in the DDR SDRAM 1 DDRC_LUE_ADDRESS_1_SR and DDRC LUE ADDRESS 2 SR give the row bank column infor
30. Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_DDRC_DFI_T_RDDATA_EN 0x0 Time from the assertion of a READ command on the DFI interface to the assertion of the DDRC DFI RDDATA EN signal Program this to RL 1 where RL is the read latency of the DRAM For LPDDR1 this should be set to RL Units Clocks DDRC DFI MIN CTRLUPD TIMING CR Table 1 72 DDRC DFI MIN CTRLUPD TIMING CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG DDRC DFI T CTRLUP MIN 0x03 Specifies the minimum number of clock cycles that the DDRC DFI CTRLUPD REQ signal must be asserted Lowest value to assign to this variable is 0x3 Units Clocks 84 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC DFI MAX CTRLUPD TIMING CR Table 1 73 DDRC DFI MAX CTRLUPD TIMING CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the
31. PRESET NIDDRC SECDED interrupt status register DDRC ECC INT CLR REG 0x140 RW PRESET N DDRC SECDED interrupt clear register 58 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR Controller Configuration Register Bit Definitions DDRC_DYN_SOFT_RESET_CR Table 1 25 DDRC DYN SOFT RESET CR Bit Number Name Reset Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 AXIRESET 0x1 Set when main AXI reset signal is asserted Reads and writes to the dynamic registers should not be carried out This is a read only bit 1 RESET_APB_REG 0x0 Full soft reset If this bit is set when the soft reset bit is written as 1 all APB registers reset to the power up state 0 REG DDRC SOFT RSTB 0x0 This is a soft reset 0 Puts the controller into reset 1 Takes the controller out of reset The controller should be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APB configuration registers Once the soft reset bit is asserted the APB register should be modified as required DDRC_DYN_REFRESH_1_CR Table 1 26 DDRC DYN REFRESH 1 CR Bit Reset N
32. Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0401 31 16 bits of REG PHY WR DATA SLAVE RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 Revision 2 127 lt gt Microsemi MDDR Subsystem PHY_WR_DATA_SLAVE_RATIO_3_ Table 1 162 PHY WR DATA SLAVE RATIO 3 CR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0401 47 32 bits of REG_PHY_WR_DATA_SLAVE_RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay
33. Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_FIFOWEIN_RATIO 0x0 31 16 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM PHY FIFO 3 SR Table 1 196 PHY FIFO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_RDLVL_FIFOWEIN_RATIO 0x0 47 32 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM 140 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY FIFO 4 SR Table 1 197 PHY FIFO 4 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 7 REG_PHY_RDC_FIFO_RST_ERR_CNT 0x0 Counter for counting how many times the pointers of read capture FIFO differ when they are reset by DLL_CALIB 6 0 PHY_REG_RDLVL_FIFOWEIN_RATIO 0x0 54 48 bits of PHY_REG_RDLVL_FIFOWEIN_RATIO
34. Table 1 115 PHY CTRL SLAVE RATIO CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG PHY CTRL SLAVE RATIO 0x0 Ratio value for address command launches timing in PHY CTRL macro This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line PHY_CTRL_SLAVE_FORCE_CR Table 1 116 PHY CTRL SLAVE FORCE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY CTRL SLAVE FORCE 0x0 1 Overwrite the delay tap value for address command timing slave DLL with the value of the REG PHY RD DQS SLAVE DELAY bus Revision 2 111 I Microsemi MDDR Subsystem PHY CTRL SLAVE DELAY CR Table 1 117 PHY CTRL SLAVE DELAY CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved
35. the security features that made third generation Microsemi SoC devices the gold standard for security in the PLD industry Also included are unique design and data security features and use models new to the PLD industry SmartFusion2 flash based FPGA fabric has zero FIT configuration rate due to its single event upset SEU immunity which is critical in reliability applications This document describes the SmartFusion2 security features and error detection and correction EDAC capabilities SmartFusion2 Programming User s Guide Describes different programming modes supported in SmartFusion2 devices High level schematics of these programming methods are also provided as a reference Important board level considerations are discussed Related Documents Tutorials Interfacing SmartFusion2 SoC FPGA with DDR3 Memory through MDDR Controller Tutorial 6 Revision 2 lt gt Microsemi 1 MDDR Subsystem Introduction The MDDR is a hardened ASIC block for interfacing the DDR2 DDR3 and LPDDR1 memories The MDDR subsystem is used to access DDR memories for high speed data transfers and code execution The MDDR subsystem includes a DDR memory controller DDR PHY and arbitration logic to support multiple masters DDR memory connected to the MDDR subsystem can be accessed by the MSS masters and master logic implemented in the FPGA fabric FPGA fabric master The MSS masters communicate with the MDDR subsystem through an MSS DDR bridge that
36. to the FPLL FDDR_SOFT_RESET 0x51C RW PRESETN Soft reset register for FDDR FDDR_IO_CALIB 0x520 RW PRESETN Configurations register for DDRIO calibration block FDDR_INTERRUPT_ENABLE 0x524 RW PRESETN Interrupt enable register F AXI AHB MODE SEL 0x528 RW PRESETN Selects AXI AHB interface in the fabric PHY SELF REF EN 0x52C RW PRESETN Automatic calibration lock is enabled FDDR_FAB_PLL_CLK_SR 0x530 RO PRESETN Indicates the lock status of the fabric_ PLL FDDR FPLL CLK SR 0x534 RO PRESETN Indicates the lock status of the fabric PLL FDDR INTERRUPT SR 0x53C RO PRESETN Interrupt status register FDDR 10 CALIB SR 0x544 RO PRESETN 1 O calibration status register FDDR FATC RESET 0x548 RW P PRESETN Reset to fabric portion of the fabric alignment test circuit 204 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide FDDR SYSREG Configuration Register Bit Definitions PLL_CONFIG_LOW_1 Table 2 19 PLL CONFIG LOW 1 Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 6 PLL_FEEDBACK_DIVISOR 0x2 Can be configured to control the corresponding configuration input of the MPLL Feedback divider value SSE 0 binary value 1 00000000 1
37. 1111111111 1 024 Feedback divider value SSE 1 binary value 1 0000000 1 1111111 128 5 0 PLL_REF_DIVISOR 0x1 Can be configured to control the corresponding configuration input of the MPLL Reference divider value binary value 1 000000 1 PLL_CONFIG_LOW_2 Table 2 20 PLL_CONFIG_LOW_2 Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 PLL_OUTPUT_DIVISOR 0x2 Configures the amount of division to be performed on the internal multiplied PLL clock in order to generate the DDR clock Output divider value 000 1 001 2 010 4 011 8 100 16 101 32 It is possible to configure the PLL output divider as 1 this setting must not be used when the DDR is operational Revision 2 205 I Microsemi Fabric DDR Subsystem Table 2 21 PLL CONFIG HIGH PLL CONFIG HIGH Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 PLL_PD 0x0 When PD is asserted the PLL will power down and outputs
38. 15 0 PHY REG BIST ERR 0x0 15 0 bits of PHY REG BIST ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG PHY BIST ERR CLR must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bits Revision 2 135 lt gt Microsemi MDDR Subsystem PHY_BIST_ERROR_2_SR Table 1 180 PHY BIST ERROR 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY REG BIST ERR Ox0 31 16 bits of PHY REG BIST ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG PHY BIST ERR CLR port must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bits PHY BIST ERROR 3 SR Table 1 181 PHY BIST ERROR 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a re
39. 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 REG_PHY_DQ_OFFSET 0x0 34 32 bits of REG_PHY_DQ_OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG_PHY_USE_WR_LEVEL 1 Revision 2 113 lt gt Microsemi MDDR Subsystem PHY_DIS_CALIB_RST_CR Table 1 123 PHY_DIS_CALIB_RST_CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_DIS_CALIB_RST 0x0 Disables the resetting of the read capture FIFO pointers with DLL_CALIB internally generated signal The pointers are reset to ensure that the PHY can recover if the appropriate number of DQS edges is not observed after a read command which can happen when the DQS squelch timing is manually overridden via the debug registers 0 Enable 1 Disable PHY_DLL_LOCK_DIFF_CR Table 1 124 PHY DLL LOCK DIFF CR Bit Number Reset Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved
40. 34 FDDR_IO_CALIB_SR FDDR_IO_CALIB_SR Bit Reset Number Name Value Description 31 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 CALIB_PCOMP 0x01 The state of the P analog comparator 13 CALIB_NCOMP 0x01 The state of the N analog comparator 12 7 CALIB_PCODE Ox3F The current PCODE value set on the FDDR DDR I O bank 6 1 CALIB NCODE Ox3F The current NCODE value set on the FDDR DDR I O bank 0 CALIB_STATUS 0x0 This is 1 when the codes are actually locked For the first run after reset this would be asserted 1 cycle after CALIB_INTRPT For in between runs this would be asserted only when the DRAM is put into self refresh or there is an override from the firmware CALIB LOCK Table 2 35 FDDR FATC RESET FDDR FATC RESET Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 FATC_RESET 0x1 Reset to the fabric portion of the fabric alignment test circuit 1 Reset active Revision 2 213 I Microsemi Fabric DDR Subsystem Glossary Acronyms ECC Error correction code FDDR Fabric double data rate
41. 39 The DDR controller completes the critical transactions with high priority Write Combine The DDR controller combines multiple writes to the same address into a single write to DDR memory When a new write collides with the queued write the DDR controller overwrites the data for the queued write with that from the new write and only performs one write transaction The write combine functionality can be disabled by setting the register bit REG_DDRC_DIS_WC to 1 SECDED The DDR controller supports built in SECDED capability for correcting single bit errors and detecting dual bit errors The SECDED feature can be enabled by setting REG DDRC MODE of DDRC_MODE_CR to 101 When SECDED is enabled the DDR controller adds 8 bits of SECDED data to every 64 bits of data When SECDED is enabled a write operation computes and stores a SECDED code along with the data and a read operation reads and checks the data against the stored SECDED code Revision 2 25 I Microsemi MDDR Subsystem The SECDED bits are interlaced with the data bits as shown in Table 1 11 Table 1 11 SECDED DQ Lines at DDR SECDED Data Pins M2S005 M2S010 M2S025 VF400 M2S050 VF400 M2S080 M2S120 Mode FG484 FG484 M2S050 FG896 M2S075 FG484 FC1152 Full bus width MDDR DQ ECC MDDR DQ ECC mode 3 0 3 0 Half bus width MDDR DQ ECC MDDR DQ ECC MDDR DQ ECC MDDR DQ ECC MDDR DQ ECC mode 1 0 1 0 1 0 1 0 1 0 Qu
42. Control PHY Interface Training Interface DDR Controller 16 Bit APB Register Interface Figure 1 6 DDR Controller Block Diagram The following sections describe key functions of the DDR controller Address Mapping Read and write requests to the DDR controller requires a system address The controller is responsible for mapping this system address with rank bank row and column address to DRAM The address mapper maps linear request addresses to DDR memory addresses by selecting the source bit that maps to each and every applicable DDR memory address bit The address map interface registers can be configured to map source address bits to DRAM address for more information refer to Address Mapping section on page 38 in Configuring the MDDR features Transaction Scheduling The DDR controller schedules the read and write transactions to DDR memory The DDR controller classifies the transactions into three types based on the commands from the AXI transaction controller e Low priority reads LPR e High priority reads HPR Writes WR Each type of transaction has a queue and the queued transactions can be in normal state or in critical state The transactions in a queue moves from normal state to critical state when that transaction is not serviced for a count of MAX_STARVE_X32 clocks The MAX_STARVE_X32 values for each queue can be configured using the DDR controller performance registers refer Performance section on page
43. DDR memory It also includes read buffers for AHB masters to efficiently read data from the external DDR memory All buffers within the DDR bridge are implemented with latches and hence are not subject to single event upsets SEUs The external DDR memory regions can be configured to be non bufferable If a master interface requests a write or read to a non bufferable region the DDR bridge is essentially bypassed The size of the non bufferable address space can also be configured 216 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide AHB Interface 0 to connect with AHB Master R WCB and Read Write Access Control AHB Interface 1 to connect with AHB Master To AXI Slave AHB Interface 2 to ith AHB M connect wit aster WCB and Read Read Access Control AHB Interface 3 to connect with AHB Master WCB and Read Buffer Figure 3 2 DDR Bridge Functional Block Diagram Arbitration between the four AHB interfaces is handled as follows e Fixed priority between AHB Interfaces 0 and 1 with 0 having the highest priority Round robin arbitration between interfaces 2 and 3 Details of Operation This section provides a functional description of each block in the DDR Bridge as shown in Figure 3 2 Write Combining Buffer The write combining buffer WCB combines multiple write transactions from the AHB master into AXI burst transactions The WCB has a user configurable bur
44. DDRC ZQ LONG TIME CR 0x08C RW PRESET N DDRC ZQ Long Time Calibration register DDRC ZQ SHORT TIME CR 0x090 RW PRESET_N DDRC ZQ Short Time Calibration register DDRC ZQ SHORT INT REFRESH MARGIN 1 CR 0x094 RW PRESET N DDRC ZQ Short Time Calibration register DDRC ZQ SHORT INT REFRESH MARGIN 2 CR 0x098 RW PRESET N DDRC ZQ Short Time Calibration register DDRC PERF PARAM 1 CR 0x09C RW PRESET_N DDRC Performance Parameter register DDRC HPR QUEUE PARAM 1 CR 0x0A0 RW PRESET_N DDRC Performance Parameter register DDRC HPR QUEUE PARAM 2 CR 0x0A4 RW PRESET_N DDRC Performance Parameter register DDRC_LPR_QUEUE_PARAM_1_CR 0x0A8 RW PRESET_N DDRC Performance Parameter register DDRC_LPR_QUEUE_PARAM_2_CR 0x0AC RW PRESET_N DDRC Performance Parameter register lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 24 DDR Controller Configuration Register continued Address Register Reset Register Name Offset Type Source Description DDRC_WR_QUEUE_PARAM_CR 0x0BO RW PRESET_N DDRC Performance Parameter register DDRC_PERF_PARAM_2_CR 0x0B4 RW PRESET_N DDRC Performance Parameter register DDRC_PERF_PARAM_3_CR 0x0B8 RW PRESET_N DDRC Performance Parameter register DDRC DFI RDDATA EN CR 0x0BC RW PRESET_N DDRC DFI Read Command Timing register DDRC DFI MIN CTRLUPD TIMING CR 0x0C0 RW PRESET_N DDRC DFI Controller Update
45. DELAY 1 CR 0x2A8 RW PRESET N Delay value for write DQS PHY WR DQS SLAVE DELAY 2 CR Ox2AC RW PRESET N Delay value for write DQS PHY WR DQS SLAVE DELAY 3 CR 0x2B0 RW PRESET N Delay value for write DQS PHY WR DQS SLAVE FORCE CR 0x2B4 RW PRESET Nl Overwriting delay value selection reg for write DQS PHY WR DQS SLAVE RATIO 1 CR 0x2B8 RW PRESET N Ratio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 2 CR 0x2BC RW PRESET NlRatio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 3 CR 0x2C0 RW PRESET N Ratio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 4 CR 0x2C4 RW PRESET N Ratio value for write DQS slave DLL PHY WR DATA SLAVE DELAY 1 CR 0x2C8 RW PRESET N Delay value for write DATA PHY WR DATA SLAVE DELAY 2 CR 0x2CC RW PRESET N Delay value for write DATA PHY WR DATA SLAVE DELAY 3 CR 0x2D0 RW PRESET N Delay value for write DATA PHY WR DATA SLAVE FORCE CR 0x2D4 RW PRESET_N Overwriting delay value selection reg for write DATA PHY WR DATA SLAVE RATIO 1 CR 0x2D8 RW PRESET_N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 2 CR 0x2DC RW PRESET N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 3 CR 0x2E0 RW PRESET N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 4 CR 0x2E4 RW PRESET N Ratio value for write DATA slave DLL PHY WRILVL INIT MODE CR 0x2E8 RW PRESET Nl3lInitialization ratio selection register used by write leveling Revision 2 105 I Microsem
46. DYN REFRESH 1 CR 0x008 RW PRESET NIDDRC Refresh Control register DDRC DYN REFRESH 2 CR 0x00C RW PRESET_N DDRC Refresh Control register DDRC_DYN_POWERDOWN_CR 0x010 RW PRESET N DDRC Power Down Control register DDRC DYN DEBUG CR 0x014 RW PRESET_N DDRC Debug register DDRC MODE CR 0x018 RW PRESET NIDDRC Mode register DDRC ADDR MAP BANK CR 0x01C RW PRESET_N DDRC Bank Address Map register DDRC ECC DATA MASK CR 0x020 RW PRESET NIDDRC SECDED Test Data register DDRC ADDR MAP COL 1 CR 0x024 RW PRESET_N DDRC Column Address Map register DDRC ADDR MAP COL 2 CR 0x028 RW PRESET_N DDRC Column Address Map register DDRC ADDR MAP ROW 1 CR 0x02C RW PRESET_N DDRC Row Address Map register DDRC ADDR MAP ROW 2 CR 0x030 RW PRESET_N DDRC Row Address Map register DDRC INIT 1 CR 0x034 RW PRESET_N DDRC Initialization Control register DDRC CKE RSTN CYCLES 1 CR 0x038 RW PRESET N DDRC Initialization Control register DDRC CKE RSTN CYCLES 2 CR 0x03C RW PRESET_N DDRC Initialization Control register DDRC INIT MR CR 0x040 RW PRESET_N DDRC MR Initialization register DDRC_INIT_EMR_CR 0x044 RW PRESET_N DDRC EMR Initialization register DDRC_INIT_EMR2_CR 0x048 RW PRESET_N DDRC EMR2 Initialization register DDRC_INIT_EMR3_CR 0x04C RW PRESET_N DDRC EMR3 Initialization register DDRC_DRAM_BANK_TIMING_PARAM_CR 0x050 RW PRESET_N DDRC DRAM Bank Timing Parameter register DDRC_DRAM_RD_WR_LATENCY_CR 0x054 RW PRESET_N DDRC DRAM Write Latency register
47. Data Slice 1 Read Data Interface DQ 23 16 DQS Data Slice 2 Training Interface el MDLL ee DQ 31 24 DQS Data Slice 3 ps Da E0GS9JDAS ECC Data Slice 4 Write Data Interface Control Interface Memory Controls Figure 1 7 DDR PHY Block Diagram Revision 2 27 I Microsemi MDDR Subsystem The DDR PHY consists of five byte wide data slices and one control slice The data slice 4 is reserved for SECDED and other data slices for the actual data transfer The data slices 2 and 3 are not present in the SmartFusion2 M25005 M25010 M25025 and M2S075 devices The unused data slices can be disabled to save power by configuring the PHY_DATA_SLICE_IN_USE_CR register The byte wide data slices contain the slave DLLs for write data write DQS and read DQS The registers can be configured to set the slave DLL ratio values which are required when training is disabled These ratio values determine the delays to write data write DQS and read DQS The PHY has a FIFO for reading the data from all the slices in the same clock cycle The primary function of the PHY control slice is to control the timing of the generation of all the DDR memory address and control signals Ratio logic functions are used to adjust the signal timing for each signal edge and these are controlled by the master DLL There are two kinds of DLLs the master DLL and the slave DLL The DLLs are responsible for creating the precise timing windows required by the DDR memori
48. High Speed DDR Interfaces User s Guide PHY_DYN_BIST_TEST_ERRCLR_2_CR Table 1 108 PHY DYN BIST TEST ERRCLR 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_ERR_CLR 0x0 31 16 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect PHY_DYN_BIST_TEST_ERRCLR_3_CR Table 1 109 PHY DYN BIST TEST ERRCLR 3 CR Bit Reset Number Name Value Description 31 12 Reserved Ox0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 0 REG_PHY_BIST_ERR_CLR 0x0 43 32 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect PHY_BIST_TEST_SHIFT_PATTERN_1_CR Table 1 110 PHY BIST TEST SHIFT PATTERN 1 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
49. If single or dual AHB 32 interfaces are selected DDR_FIC converts the single dual 32 bit AHBL master transactions from the FPGA fabric to 64 bit AXI transactions In this mode the DDR bridge embedded as part of the DDR_FIC is enabled The DDR bridge has an arbiter which arbitrates read and write requests from the two AHB masters on a round robin priority scheme Refer to the DDR Bridge chapter on page 215 for a detailed description The DDR_FIC input interface is clocked by the FPGA fabric clock and the MDDR is clocked by MDDR_CLK from the MSS clock conditioning circuit CCC Clock ratios between MDDR_CLK and DDR_FIC clock can vary Supported ratios are shown in Table 1 10 Clock ratios can be configured through Libero System on Chip SoC software or through system register MSSDDR_FACC1_CR For more information refer to the MDDR Clock Configuration section on page 33 Table 1 9 MDDR CLK to FPGA Fabric Clock Ratios DIVISOR_A 1 0 FIC64_DIVISOR 2 0 MDDR_CLK FPGA FABRIC Clock Ratio 00 000 1 1 00 001 2 1 00 010 4 1 00 100 8 1 00 101 16 1 01 000 2 1 01 001 4 1 01 010 8 1 mme 11 000 3 1 22 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 9 MDDR CLK to FPGA Fabric Clock Ratios continued DIVISOR Af 1 0 FIC64 DIVISOR 2 0 MDDR CLK FPGA FABRIC Clock Ratio 11 001 6 1 11 010 12 1 AXI Transaction Controller The AXI transa
50. If the SMC_FIC is enabled the MDDR subsystem will not be available In SMC_FIC mode the DDRIOs associated with the MDDR subsystem are available for user applications Figure 4 1 shows a soft memory controller instantiated in the FPGA fabric for interfacing with external memory ARM Cortex M3 AHB Bus Matrix FPGA Fabric l D S Cache IDC MSS 64 Bit AXI Controller DS 4 DDR Bridge IC D S i HPDMA 64 Bit AXI or 32 Bit AHBLite Soft Memory Controller External Memory Figure 4 1 System Level SMC FIC Block Diagram Revision 2 227 I Microsemi Soft Memory Controller Fabric Interface Controller Functional Description The SMC FIC receives 64 bit AXI transactions from the MSS DDR bridge and converts them into 64 bit AXI or 32 bit AHB Lite transactions to the SMC in the FPGA fabric Figure 4 2 shows the block diagram of the SMC FIC The SMC FIC has two bridges e The AXI AHB bridge converts 64 bit AXI transactions into 32 bit AHB transactions It implements the AXI master to AHBL master protocol translator This bridge is enabled when the SMC_FIC is configured for a 32 bit AHB interface e The AXI AXI bridge facilitates 64 bit AXI transactions from the MSS DDR bridge to the 64 bit AXI FPGA fabric interface This bridge is enabled when the SMC FIC is configured for a 64 bit AXI interface The SMC FIC receives a clock from the MSS CCC that is identical to M3 CLK MSS peripherals can access the external mem
51. Introduction The FDDR is a hardened ASIC block for interfacing the DDR2 DDR3 and LPDDR1 memories The FDDR subsystem is used to access DDR memories for high speed data transfers and code execution The FDDR subsystem includes the DDR memory controller DDR PHY and arbitration logic to support multiple masters FPGA fabric masters communicate with the DDR memories interfaced to the FDDR subsystem through AXI or AHB interfaces Features Integrated on chip DDR memory controller and PHY Configurable to support LPDDR1 DDR2 and DDR3 memory devices Up to 667 Mbps 333 MHz DDR performance Supports memory densities up to 4 GB Supports 8 16 32 bit data bus width modes Supports a maximum of 8 memory banks Supports 1 2 or 4 ranks of memory Single error correction and double error detection SECDED enable or disable feature Supports DRAM burst lengths of 4 8 or 16 depending on configured Bus width mode and DDR type Support for sequential and interleaved burst ordering Programs internal control for ZQ short calibration cycles for DDR3 configurations Supports dynamic scheduling to optimize bandwidth and latency Supports self refresh entry and exit on software command Supports deep power down entry and exit on software command Flexible address mapper logic to allow application specific mapping of row column bank and rank bits Configurable support for 1T or 2T timing on the DDR SDRAM control signals Supports autonomous DRAM
52. Low when processor serves the interrupt 154 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR_FIC_NUM_AHB_MASTERS_CR Table 1 228 DDR FIC NUM AHB MASTERS CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 CFG_NUM_AHB_MASTERS 0x0 Defines whether one or two AHBL 32 bit masters are implemented in the fabric 0 One 32 bit AHB master implemented in fabric 1 Two 32 bit AHB masters implemented in fabric 3 0 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation DDR_FIC_HPB_ERR_ADDR_1_SR Table 1 229 DDR FIC HPB ERR ADDR 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M1_ERR_ADD 0x0 15 0 bits of DDR FIC M1 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this registe
53. Min Time register DDRC DFI MAX CTRLUPD TIMING CR 0x0C4 RW PRESET NIDDRC DFI Controller Update Max Time register DDRC DFI WR LVL CONTROL 1 CR 0x0C8 RW PRESET N DDRC DFI Write Levelling Control register DDRC DFI WR LVL CONTROL 2 CR 0x0CC RW PRESET_N DDRC DFI Write Levelling Control register DDRC DFI RD LVL CONTROL 1 CR 0x0D0 RW PRESET NIDDRC DFI Read Levelling Control register DDRC DFI RD LVL CONTROL 2 CR 0x0D4 RW PRESET NIDDRC DFI Read Levelling Control register DDRC DFI CTRLUPD TIME INTERVAL CR 0x0D8 RW PRESET_N DDRC DFI Controller Update Time Interval register DDRC DYN SOFT RESET ALIAS CR 0x0DC RW PRESET_N DDRC reset register DDRC_AXI_FABRIC_PRI_ID_CR 0x0E0 RW PRESET N DDRC AXI Interface Fabric Priority ID Register DDRC SR 0x0E4 RO PRESET NIDDRC Status register SECDED Registers DDRC SINGLE ERR CNT STATUS SR 0x0E8 RO PRESET NIDDRC single error count Status register DDRC DOUBLE ERR CNT STATUS SR 0x0EC RO PRESET NIDDRC double error count status register DDRC LUE SYNDROME 1 SR 0x0FO RO PRESET_N DDRC last uncorrected error syndrome register DDRC LUE SYNDROME 2 SR 0x0F4 RO PRESET_N DDRC last uncorrected error syndrome register DDRC_LUE_SYNDROME_3_SR 0x0F8 RO PRESET_N DDRC last uncorrected error syndrome register DDRC LUE SYNDROME 4 SR 0x0FC RO PRESET_N DDRC last uncorrected error syndrome register DDRC LUE SYNDROME 5 SR 0x100 RO PRESET_N DDRC last uncorrected error syndrome register Revision 2
54. To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M1_WBEMPTY 0x0 1 Write buffer of AHBL master1 does not have valid data 0 Default 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_M2_RBEMPTY 0x0 1 Read buffer of AHBL master2 does not have valid data 0 Default 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M2_WBEMPTY 0x0 1 Write buffer of AHBL master2 does not have valid data 0 Default DDR_FIC_SW_HPB_LOCKOUT_SR Table 1 234 DDR FIC SW HPB LOCKOUT SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide 7 5 3 1 compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_LCKTOUT 0x0 Indicates lock counter in arbiter reached its maximum value Lock counter 20 bit starts counting when a locked request gets access to a bus and will be cleared when the lock signal becomes logic 0 DDR_FIC_M2_WDSBL_DN 0x0 High indicates AHBL
55. a reserved bit should be preserved across a read modify write operation 11 3 REG_DDRC_POST_CKE_X1024 0x0 Cycles to wait after driving CKE High to start the DRAM initialization sequence Units 1 024 clocks DDR Typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds SDR Typically requires this to be programmed for a delay of 100 us to 200 us 1 0 REG_DDRC_PRE_CKE_X1024 0x0 9 0 bits of REG_DDRC_PRE_CKE_X1024 Cycles to wait after reset before driving CKE High to start the DRAM initialization sequence Units 1 024 clock cycles DDR2 specifications typically require this to be programmed for a delay of gt 200 us DDRC_INIT_MR_CR Table 1 40 DDRC INIT MR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_MR 0x095A Value to be loaded into the DRAM Mode register Bit 8 is for the DLL and the setting here is ignored The controller sets appropriately DDRC_INIT_EMR_CR Table 1 41 DDRC INIT EMR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
56. and the queued transactions can be in normal state or in critical state The transactions in a queue moves from normal state to critical state when that transaction is not serviced for a count of MAX_STARVE_X32 clocks The MAX_STARVE_X32 values for each queue can be configured using the DDR controller performance registers refer to the Performance section on page 193 The DDR controller completes the critical transactions with high priority Write Combine The DDR controller combines multiple writes to the same address into a single write to DDR memory When a new write collides with the queued write the DDR controller overwrites the data for the queued write with that from the new write and only performs one write transaction The write combine functionality can be disabled by setting the register bit REG_DDRC_DIS_WC to 1 SECDED The DDR controller supports built in SECDED capability for correcting single bit errors and detecting dual bit errors The SECDED feature can be enabled by setting REG DDRC MODE of DDRC MODE CR to 101 When SECDED is enabled the DDR controller adds 8 bits of SECDED data to every 64 bits of data When SECDED is enabled a write operation computes and stores a SECDED code along with the data and a read operation reads and checks the data against the stored SECDED code The SECDED bits are interlaced with the data bits as shown in Table 2 10 Table 2 10 SECDED DQ Lines at DDR SECDED Data Pins
57. at the DRAM 130 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WR_RD_RL_CR Table 1 169 PHY WR RD RL CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_PHY_WR_RL_DELAY 0x0 This delay determines when to select the active rank s ratio logic delay for write data and write DQS slave delay lines after PHY receives a write command at the control interface This is only used for multi rank designs when REG PHY USE RANKO DELAYS 0 This must be programmed as Write Latency 4 with a minimum value of 1 4 0 REG_PHY_RD_RL_DELAY 0x0 This delay determines when to select the active rank s ratio logic delay for FIFO_WE and read DQS slave delay lines after PHY receives a read command at the control interface This is only used for multi rank designs when REG PHY USE RANKO DELAYS 0 PHY DYN RDC FIFO RST ERR CNT CLR CR Table 1 170 PHY DYN RDC FIFO RST ERR CNT CLR CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write
58. before traffic is blocked and the refreshes are forced to execute Closing pages to perform a refresh is a one time penalty that must be paid for each group of refreshes therefore performing refreshes in a burst reduces the per refresh penalty of these page closings Higher numbers for burst_of_N_refresh slightly increases utilization lower numbers decreases the worst case latency associated with refreshes 0x0 Single refresh 0x1 Burst of 2 0x7 Burst of 8 refresh DDRC_DYN_POWERDOWN_CR Table 1 28 DDRC DYN POWERDOWN CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 1 REG_DDRC_POWERDOWN_EN 0x1 If true the controller goes into power down after a programmable number of cycles REG_DDRC_POWERDOWN_TO_X32 This register bit may be reprogrammed during the course of normal operation 0 REG_DDRC_DEEPPOWERDOWN_EN 0x0 1 Controller puts the DRAM into deep power down mode when the transaction store is empty 0 Brings controller out of deep power down mode Present only in designs that have mobile support 60 Revision 2 DDRC DYN DEBUG CR Table 1 29 DDRC DYN DEBUG CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide
59. bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 0 REG_PHY_CTRL_SLAVE_DELAY 0x0 If REG_PHY_RD_DQS_SLAVE_FORCE is 1 replace delay tap value for address command timing slave DLL with this value PHY_DATA_SLICE_IN_USE_CR Table 1 118 PHY DATA SLICE IN USE CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_DATA_SLICE_IN_USE 0x0 Data bus width selection for read FIFO RE generation One bit for each data slice 1 Data slice is valid 0 Read data responses are ignored Note The PHY data slice 0 must always be enabled PHY_LVL_NUM_OF_DQ0_CR Table 1 119 PHY_LVL_NUM_OF_DQ0_CR Bit Reset Number Name Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 4 REG PHY GATELVL NUM OF DQO 0x0 This register value determines the number of samples for dq0 in for each ratio increment by the gate training FSM NUM OF ITERATION REG PHY GATELVL NUM OF DQ0 1 3 0 REG PHY WRLVL NUM OF DQ0O 0
60. bit is set when the soft reset bit is written as 1 all APB registers reset to the power up state REG_DDRC_SOFT_RSTB 0x0 This is a soft reset 0 Puts the controller into reset 1 Takes the controller out of reset The controller should be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APB configuration registers Once the soft reset bit is asserted the APB register should be modified as required DDRC AXI FABRIC PRI ID CR Table 1 80 DDRC AXI FABRIC PRI ID CR Bit Number Name Reset Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 4 PRIORITY_ENABLE_BIT 0x0 This is to set the priority of the fabric master ID 01 Indicates that the ID is higher priority but still lower than the ICache and DSG bus 10 11 Indicates that the ID has the highest priority even higher than ICache and DSG bus to be used for isochronous traffic display applications only This only affects the reads Writes would still have the priority lower than Cache DSG 00 None of the master IDs from the fabric have a higher priority 3 0 PRIORITY_ID 0x0 If the Priority Enable bit is 1 this ID will have a
61. can drive this signal Low to extend a transfer MDDR DDR AHB1 S HWDATA 31 0 Input Indicates AHB write data from Fabric master APB Slave Interface Table 1 8 shows the MDDR APB slave interface signals with their descriptions For more details of APB protocol refer to AMBA APB v3 0 protocol specification Table 1 8 e MDDR APB Slave Interface Signals Signal Name Direction Polarity Description MDDR APB S PREADY Output High Indicates APB Ready signal to Fabric master MDDR APB S PSLVERR Output High Indicates error condition on an APB transfer to Fabric master MDDR APB S PRDATA 15 0 Output Indicates APB read data to Fabric master 18 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 8 e MDDR APB Slave Interface Signals continued Signal Name Direction Polarity Description MDDR_APB_S_PENABLE Input High Indicates APB enable from Fabric master The enable signal is used to indicate the second cycle of an APB transfer MDDR_APB_S_PSEL Input High Indicates APB slave select signal from Fabric master MDDR_APB_S_PWRITE Input High Indicates APB write control signal form Fabric master MDDR APB S PADDR 10 2 Input Indicates APB address initiated by Fabric master MDDR APB S PWDATA 15 0 Input Indicates APB write data from Fabric master Initialization Before the MDDR subsystem is active it goes through an initializat
62. control information valid 0 Address and control information not valid AXI S AWADDRI 31 0 Input Indicates write address The write address bus gives the address of the first transfer in a write burst transaction AXI S AWBURST 1 0 Input Indicates burst type The burst type coupled with the size information details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved AXI S AWID 3 0 Input Indicates identification tag for the write address group of signals Revision 2 169 I Microsemi Fabric DDR Subsystem Table 2 5 e FDDR AXI Slave Interface Signals continued Signal Name Direction Polarity Description AXI S AWLEN 3 0 Input Indicates burst length The burst length gives the exact number of transfers in a burst This information determines the number of data transfers associated with the address 0000 1 0001 0010 0011 0100 0101 0110 0111 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 MNA AN AXI S AWLOCK 1 0 Input Indicates lock type This signal provides additional information about the atomic characteristics of the write transfer 00 Normal access 01 Exclusive access 10 Locked a
63. driven to DRAM 38 The DDR memories require delays after initializing the mode registers The following registers must be configured for the delay requirements for the DDR memories The DDR controller uses these delay values while initializing the DDR memories e DDRC CKE RSTN CYCLES 1 CR recommended value is 0x4242 DDRC CKE RSTN CYCLES 2 CR recommended value is 0x8 Address Mapping The DDR controller maps linear request addresses to DDR memory addresses by selecting the source bit that maps to each and every applicable DDR memory address bit Each DDR memory address bit has an associated register vector to determine its source The source address bit number is determined by adding the internal base of a given register to the programmed value for that register as described in EQ 1 Internal base register value source address bit number EQ 1 For example reading the description for REG DDRC ADDRMAP COL B3 the internal base is 3 so when the full data bus is in use the column bit 4 is determined by 3 register value If this register is programmed to 2 then the source address bit is 3 2 5 The address mapping registers are listed below DDRC_ADDR_MAP_BANK_CR DDRC_ADDR_MAP_COL_1_CR DDRC_ADDR_MAP_COL_2_CR DDRC_ADDR_MAP_COL_3_CR DDRC_ADDR_MAP_ROW_1_CR 6 DDRC_ADDR_MAP_ROW_2_CR While configuring the registers ensure that two DDR memory address bits are not determined by the same source address bit
64. high speed clock coming from the FPLL to generate the DDR FIC clock according to the configured division ratios The possible FDDR CLK DDR FIC_CLK ratios are 1 1 2 1 3 1 4 1 6 1 8 1 12 1 and 16 1 The FACC includes no glitch multiplexers NGMUXs to feed the DDR FIC clock with a standby clock CK_STANDBY during the FPLL initialization During initialization the FDDR is not operational until after FPLL lock is achieved However the glitchfree multiplexers are still used to ensure that the clock being driven to DDR_FIC during this time comes from the RC oscillator avoiding the potentially high frequency output of the FPLL which may be outside of the supported range of operation of DDR_FIC FPLL Initialization In order to attain clock alignment between the FPGA fabric and the FDDR subsystem it is necessary to use the FPLL to perform deskewing of the FDDR clocks After the FPLL is initialized it typically takes over 500 divided reference clock cycles for lock to be achieved The FPLL lock assertion time is also dependent on the FPLL lock parameters lock window and lock delay There is no provision made for operation of the FDDR subsystem before FPLL lock is achieved Revision 2 175 I Microsemi Fabric DDR Subsystem PLL Lock Monitoring The FDDR has an input CLK BASE PLL LOGCGK to monitor the fabric PLL lock It must be connected to the lock signal generated by the fabric PLL which is being used to generate the base clock to the FD
65. is 1 replace delay tap value for write data slave DLL with this value Revision 2 125 lt gt Microsemi MDDR Subsystem PHY_WR_DATA_SLAVE_DELAY_2_CR Table 1 157 PHY WR DATA SLAVE DELAY 2 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 31 16 bits of REG_PHY_WR_DATA_SLAVE_DELAY If REG PHY WR DATA SLAVE FORCE is 1 replace delay tap value for write data slave DLL with this value PHY WR DATA SLAVE DELAY 3 CR Table 1 158 PHY WR DATA SLAVE DELAY 3 CR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_WR_DATA_SLAVE_DELAY If REG PHY WR DATA SLAVE FORCE is 1 replace delay tap value for write data slave DLL with this value PHY WR DATA SLAVE FORCE CR Table 1 159 PHY WR DATA SLAVE FORCE CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 S
66. is very likely we have already answered your questions Technical Support Visit the Customer Support website www microsemi com soc support search default aspx for more information and support Many answers available on the searchable web resource include diagrams illustrations and links to other resources on the website Website You can browse a variety of technical and non technical information on the SoC home page at www microsemi com soc Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website Email You can communicate your technical questions to our email address and receive answers back by email fax or phone Also if you have design problems you can email your design files to receive assistance We constantly monitor the email account throughout the day When sending your request to us please be sure to include your full name company name and your contact information for efficient processing of your request The technical support email address is soc_tech microsemi com Revision 2 241 lt gt Microsemi Product Support My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases Outside the U S Customers needing assistance outside the US time zones can either contact technical support via em
67. lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 92 Revision 2 Table 1 86 e DDRC LUE SYNDROME 3 SR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_LUE_SYNDROME_3_SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 47 32 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CR is written over by the system Revision 2 93 lt gt Microsemi MDDR Subsystem DDRC LUE SYNDROME 4 SR Table 1 87
68. master2 write buffer is disabled DDR_FIC_M2_RDSBL_DN 0x0 High indicates AHBL master2 read buffer is disabled DDR_FIC_M1_WDSBL_DN 0x0 High indicates AHBL master1 read buffer is disabled o N AJ Oo DDR FIC M1 RDSBL DN 0x0 High indicates AHBL master1 write buffer is disabled Revision 2 157 lt gt Microsemi MDDR Subsystem DDR_FIC_SW_HPD_WERR_SR Table 1 235 DDR FIC SW HPD WERR SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR FIC M1 WR ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes Low when the processor serves an interrupt and makes a clear bit for AHBL master1 7 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M2_WR_ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes Low when processor serves the interrupt DDR_LOCK_TIMEOUTVAL_1_CR Table 1 236 DDR LOCK TIMEOUTVAL 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software sho
69. of the MDDR subsystem is shown in Figure 1 1 DDR SDRAM MSS Cortex M3 Processor S D l z AXI MDDR DDR IO DER Transaction MSS DDR Controller Bridge Contoller Controller E g D APB Config Reg DDR FIC HPDMA AHB Bus Matrix 16 Bit APB 64 Bit AX Single FIC 2 FIC 0 FIC 1 An 32 Bit AHBL Dual 32 B t AHBL t USB TSE OTG MAC APB AXI AHB Master Master FPGA FABRIC SmartFusion2 SoC FPGA Figure 1 1 System Level MDDR Block Diagram The MDDR subsystem accepts data transfer requests from AXI or AHB interfaces Any read write transactions to the DDR memories can occur through the following four paths 1 The Cortex M3 processor can access DDR memories through the MSS DDR bridge for data and code execution High performance DMA HPDMA controller can access DDR memories through the MSS DDR bridge for high speed data transactions Other MSS masters for example FIC 0 FIC 1 and PDMA can access DDR memories through the MSS DDR bridge AXI or AHBL masters in the FPGA fabric can access DDR memories through DDR FIC interface Memory Configurations The SmartFusion2 SoC FPGA MDDR subsystem supports a wide range of common memory types configurations and densities as shown in Table 1 1 on page 9 If SECDED mode is enabled in the MDDR controller the external memory module must be connected to the following Data line
70. periodic calibrations The DDR controller performs ZQ calibration by issuing a ZQ calibration long ZQCL command and ZQ calibration short ZQCS command ZQCL is used to perform initial calibration during the power up initialization sequence This command is allowed for a period of tZQinit as specified by memory vendor The value of tZQinit can be configured through register bits REG DDRC T ZQ LONG NOP The ZQCS command is used to perform periodic calibration to account for voltage and temperature variations A shorter timing window is provided to perform calibration and transfer of values as defined by timing parameter tZQCS The tZQCS parameter can be configured through register bits REG_DDRC_T_ZQ_SHORT_NOP Revision 2 173 I Microsemi Fabric DDR Subsystem 174 Other activities are not performed by the controller for the duration of tZQinit and tZQCS All DRAM banks are precharged and tRP met before ZQCL or ZQCS commands are issued by the DDR controller DRAM Training This is applicable for DDR3 only If this option is enabled the DDR controller performs PHY training after reset The order of training sequence is given below e Write leveling e Read leveling DQS gate training Data eye training Write Leveling The write leveling process locates the delay at which the write DQS rising edge aligns with the rising edge of the memory clock By identifying this delay the system can accurately align the write DQS
71. replace delay tap value for read DQS slave DLL with this value PHY WR DQS SLAVE FORCE CR Table 1 151 PHY WR DQS SLAVE FORCE CR Bit Number Name Reset Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_WR_DQS_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for read DQS slave DLL with the value of the REG_PHY_WR_DQS_SLAVE_DELAY bus bit 4 is for PHY Data slice 4 bit 3 for PHY Data slice 3 and so on Revision 2 123 lt gt Microsemi MDDR Subsystem PHY_WR_DQS_SLAVE_RATIO_1_CR Table 1 152 PHY WR DQS SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 15 0 bits of REG PHY WR DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the sl
72. reserved bit should be preserved across a read modify write operation 0 CFGR LOCK TIMEOUT EN 0x0 1 Lock timeout feature is enabled and generated interrupt is 0 Lock timeout feature is disabled and interrupt is not generated DDR FIC RDWR ERR SR Table 1 239 DDR FIC RDWR ERR SR Bit Reset Number Name Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 0 DDR_FIC_CFG_RDWR_ERR_SR 0x0 Read address of math error register Revision 2 159 I Microsemi MDDR Subsystem Glossary Acronyms ECC Error correction code FDDR Fabric double data rate FIC Fabric interface controller LPDDR Low power double data rate MDDR MSS double data rate SMC Soft memory controller List of Changes The following table lists critical changes that were made in each revision bm A A Revision 2 Updated Address Mapping section SAR 45761 April 2013 Updated MDDR Memory Map section SAR 44198 Revision 1 Updated 3 Dual AHB Interface from FPGA Fabric section SAR 41901 November 2012 f pdated Table 1 14 SAR 41979 Updated Features section under Introduction SAR 42751 Updated Table 1 2 SAR 42751 98 160 Revision 2 lt gt Microsemi 2 Fabric DDR Subsystem
73. selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 96 Revision 2 DDRC LCE SYNDROME 2 SR Table 1 92 DDRC LCE SYNDROME 2 SR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES Ox0 31 16 bits of DDRC_REG_ECC_SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it then the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error
74. slave interface signals with their descriptions These signals will be available only if FDDR interface is configured for dual AHB mode Table 2 7 FDDR AHB Slave Interface Signals Signal Name Direction Polarity Description AHB1 S HREADYOUT Output High Indicates that a transfer has finished on the bus The signal is asserted LOW to extend a transfer Input to Fabric master AHB1 S HRESP Output High Indicates AHB transfer response to Fabric master AHB1 S HRDATA 31 0 Output Indicates AHB read data to Fabric master AHB1 S HSEL Input High Indicates AHB slave select signal from Fabric master AHB1 8 HADDR 31 0 Input Indicates AHB address initiated by Fabric master AHB1 S HBURST 2 0 Input Indicates AHB burst type from Fabric master AHB1 S HSIZE 1 0 Input Indicates AHB transfer size from Fabric master AHB1 S HTRANS 1 0 Input Indicates AHB transfer type from Fabric master AHB1 8 HMASTLOCK Input High Indicates AHB master lock signal from Fabric master AHB1 S HWRITE Input High Indicates AHB write control signal from Fabric master AHB1_S_HREADY Input High Indicates that a transfer has finished on the bus Fabric master can drive this signal LOW to extend a transfer AHB1 8 HWDATA 31 0 Input Indicates AHB write data from Fabric master APB Slave Table 2 8 shows the FDDR APB slave interface signals with their descriptions For more details of APB protocol refer to AMB
75. the bus master during read operations How to Use SMC FIC This section describes how to use SMC FIC in an application and contains the following sub sections e Design Flow Use Model 1 Accessing SDRAM from MSS Through CoreSDR_AXI Design Flow The SMC_FIC can be enabled and configured through the MSS external memory configurator which is part of the MSS configurator in the Libero SoC design software Figure 4 3 on page 234 shows the MSS external memory configurator The external memory type interface must be selected as Application Accesses Single Data Rate Memory from MSS to enable the SMC_FIC Select the type of interface as AXI or AHB 32 After completing the configuration the selected interface is exposed in SmartDesign This interface must be connected to the SMC through CoreAXI or CoreAHB Microsemi provides CoreSDR_AHB and CoreSDR AXI SMC IPs for interfacing with external SDRAM Any other custom soft memory controller can also be implemented in the FPGA fabric to access the external memories Revision 2 233 I Microsemi Soft Memory Controller Fabric Interface Controller E MSS External Memory Configurator External Memory Type Interface Configuration Application accesses Double Data Rate Memory Memory Configuration Type DDR2 Width 15 ECC Memory Access From MSS Using a Single AHBLite Interface Using Two AHB Interfaces amp Application accesses Single Data Rate Memory from MSS Memory
76. the lock signal is still asserted the counter will start counting again How to Use DDR Bridge 220 This section describes how to use DDR Bridge in an application and contains the following sub sections Design Flow Use Model 1 High Speed Data Transactions from Cortex M3 Processor e Use Model 2 Selecting Non Bufferable Region Design Flow MSS DDR Bridge Configurations The MSS DDR bridge is statically configured through the DDR bridge configurator of the MSS configurator in Libero SoC as shown in Figure 3 5 on page 221 Configurable parameters are as follows Write buffer time out counter This allows to configure the 10 bit timer of write buffer for time out value By default this is configured for maximum wait time 0x3FF to buffer the write transactions For configuring to other values enter a 10 bit hexadecimal value in the provided field of DDR bridge configurator Select timeout value to a non zero value for buffering the write transactions e Non bufferable region size The size of non bufferable memory region can be selected from a drop down menu in the DDR bridge configurator The menu has the options to select the region from 64 KB to 1 GB It also has an option none to select the complete memory as bufferable The default selection is 64 KB e Non bufferable region address The base address of the non bufferable memory region can be selected by configuring this field The value must be configured as a 16 bit hexade
77. value of a reserved bit should be preserved across a read modify write operation 9 0 REG DDRC DFI T CTRLUP MAX 0x40 Specifies the maximum number of clock cycles that the DDRC_DFI_CTRLUPD_REQ signal can assert Lowest value to assign to this variable is 0x40 Units Clocks DDRC DFI WR LVL CONTROL 1 CR Table 1 74 e DDRC DFI WR LVL CONTROL 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG DDRC DFI WRLVL MAX X1024 0x0 7 0 bits of REG DDRC DFI WRLVL MAX X1024 Write leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI WRLVL RESP to a write leveling enable signal DDRC DFI WRLVL EN Only applicable when connecting to PHY s operating in PHY WrLvl Evaluation mode Units 1 024 clocks Only present in designs that support DDR3 devices 7 0 REG DDRC WRLVL WW 0x0 Write leveling write to write delay Specifies the minimum number of clock cycles from the assertion of a DDRC DFI WRLVL STROBE signal to the next DDRC DFI WRLVL STROBE signal Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units Clocks
78. will be Low PD has precedence over all other functions 14 PLL_FSE 0x0 Chooses between internal and external input paths 0 FB pin input 1 Internal feedback FB should be tied off High or Low and not left floating when FSE is High FB should connect directly or through the clock tree to PLLOUT when FSE is Low SSE is ineffective when FSE 0 13 PLL_MODE_3V3 0x1 Analog voltage selection 1 3 3 V 0 25 V 12 PLL MODE 1V2 0x1 Core voltage selection 1 1 2 V 0 1 0 V The wrong selection when operating at 1 V the jitter is not within the required limit for operation of DDR may cause the PLL not to function but will not damage the PLL 11 PLL_BYPASS 0x1 If 1 powers down the PLL core and bypasses it such that PLLOUT tracks REFCK BYPASS has precedence over RESET Microsemi recommends that either BYPASS or RESET are asserted until all configuration controls are set in the desired working value and the power supply and reference clock are stable within operating range 10 7 PLL_LOCKCNT OxF Configured to control the corresponding configuration input of the MPLL LOCK counter Value 2 binary value 5 0000 32 1111 1048576 For the number of reference cycles before LOCK is asserted from LOCK being detected 206 Revision 2 Table 2 21 PLL CONFIG HIGH continued lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Number Name Reset Value Description 6 4 PLL_LOCKW
79. within the memory clock The DDR controller drives subsequent write strobes for every write to write delay specified by REG DDRC WRLVL WW until the PHY drives the response signal High The DDR controller performs the following steps 1 Sets up the DDR memory in Write leveling mode by sending the appropriate MR1 command 2 Sets the write leveling enable bit for the PHY and sends out periodically timed write level strobes to the PHY while sending out DEVSEL commands on the DDR memory command interface 3 Once the PHY completes measurements it sets the write level response bits which then signal the DDRC to stop the leveling process and lower the write leveling enable bit Ifthe REG DDRC DFI WR LEVEL EN bit is configured to 1 the write leveling is enabled as part of the initialization sequence Read Leveling There are two Read leveling modes 1 DQS gate training The purpose of gate training is to locate the optimum delay that can be applied to the DQS gate such that it functions properly To enable the Read DQS gate training as part of the initialization sequence set the REG DDRC DFI RD DQS GATE LEVEL bit to 1 2 Data eye training The goal of data eye training is to identify the delay at which the read DQS rising edge aligns with the beginning and end transitions of the associated DQ data eye To enable the Read data eye training as part of the initialization sequence set the REG DDRC DFI RD DATA EYE TRAIN bit to 1 By ide
80. 0 MHz v APB 1 QK M3_CLK a 111 000 MHz FPGA Fabric Interface Clocks v EICO CK M3CLK a 111 000 MHz FIC 1 Cik M3_CLK Figure 2 19 MSS CCC Configuration 5 Instantiate the FDDRC macro in the SmartDesign canvas Revision 2 197 I Microsemi Fabric DDR Subsystem 6 Configure the FDDR and select the dual AHB interface as shown in Figure 2 20 In this example the design is created to access DDR3 memory with a 32 bit data width The FDDR clock is configured to 333 MHz and DDR FIC is configured to 111 MHz E Fabric External Memory DDR Controller Configurator 2 femten Configuration Memory Configuration Type DoRs ecc Memory Access FPGA Fabric Interface Using Two AHB 32 Interfaces v FDDR_CLK Frequency MHz 333 DDR_FIC CLK_BASE Divisor 111 MHz FPLL Configuration Supply Voltage Use FAB_PLL_LOCK 7 Interrupts Enable Interrupts E Edit Registers Gens ES Gap Figure 2 20 FDDR Configuration 7 Click Edit Registers and configure the registers or import the register configuration file according to the application requirements Refer to the FDDR Subsystem Features Configuration section on page 189 to configure the necessary registers 198 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide 8 Instantiate the clock resources FAB_CCC and chip oscillators in the SmartDesign canvas and c
81. 000 MHz W Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK Cortex M3 and MSS Main Clock M3 CLK 111 MHz 111 000 MHz MDDR Clocks vV MDDR CLK m3 OK 3 y 333 000 MHz UV por SMC FIC CLK MDDR_CLK Byt 111 000 MHz MSS APB 0 1 Sub busses Clocks v APB 0 CLK M3 CK 1 000 MHz v APB 1 CIK M3 OKK 000 MHz kor SBN FPGA Fabric Interface Clocks Figure 1 12 e MDDR Clock Configuration 34 If the MDDR CLK ratio to M3 CLK is a multiple of 3 DDR SMC FIC CLK s ratio to MDDR CLK must also be a multiple of 3 and vice versa The configurator issues an error if this requirement is not met This limitation is imposed by the internal implementation of the MSS CCC FIC 2 Configuration This is required to initialize the MDDR registers optional when initializing from MSS Configure FIC 2 peripheral initialization block as shown in Figure 1 13 on page 35 to expose the MDDR APB interface MDDR_APB_SLAVE interface in Libero SmartDesign Use the MDDR_APB_SLAVE interface to connect with the APB master logic in the FPGA fabric Revision 2 lt S Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide 3 E MSS Fabric Interface Controller FIC 2 Configurator Configuration Initialize Peripherals Using Cortex M3 v MSS DDR F Fabric DDR and or SERDES Blocks EE s ES CoreSF2Config
82. 110 Region 0 Region 1 Region 2 Region 3 0111 Region 0 Region 1 Region 4 Region 5 1000 Region 0 Region 1 Region 6 Region 7 1001 Region 0 Region 1 Region 8 Region 9 1010 Region 0 Region 1 Region 10 Region 11 1011 Region 0 Region 1 Region 12 Region 13 1100 Region 0 Region 1 Region 14 Region 15 Revision 2 41 lt gt Microsemi MDDR Subsystem If 2 GB of DDR memory is connected to MDDR only 8 regions are available 0 7 Table 1 20 shows the DDR regions available for address mode settings Table 1 20 Accessed DDR Memory Regions Based on Mode Settings for a 2 GB Memory DDR Memory Regions Visible at MSS DDR Address Space for Different Modes MSS DDR Space 0 MSS DDR Space 1 MSS DDR Space 2 MSS DDR Space 3 Address Space 0xA0000000 0xB0000000 0xC0000000 0xD0000000 Mapping Modes OxAFFFFFFF 0xBFFFFFFF OxCFFFFFFF 0xDFFFFFFF 0000 Region 2 Region 3 Region 4 Region 5 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 0011 Region 4 Region 5 Region 6 Region 7 0110 Region 0 Region 1 Region 2 Region 3 0111 Region 0 Region 1 Region 4 Region 5 1000 Region 0 Region 1 Region 6 Region 7 If 1 GB of DDR memory is connected to MDDR only 4 regions are available 0 4 Table 1 21 shows the DDR regions available for address mode settings Table 1 21 Accessed DDR Memory Regions Based on Mode Settings for a 2 GB Memory MSS DDR Space 0 MS
83. 2 ieee nee eek ti Pa FE Bu AE A gee has tee eee eee gad ene 28 Design FIOW 4 ass ske n den wa da See Shee ees eet ead eek ged ania oe hea ea ae meres 28 Use Model 1 Accessing MDDR from FPGA Fabric Through the AXI Interface 0 0 0 0 42 Use Model 2 Accessing MDDR from FPGA Fabric Through the AHB Interface 0 000 eee eee eee 46 Use Model 3 Accessing MDDR from Cortex M3 Processor 1 0 0 0c cece eee 48 Use Model 4 Accessing MDDR from the HPDMA 0 000 c cece eee 50 DDR Memory Device Examples 0 0 00 cette teens 50 MDDR Configuration Registers 0 0 nen tenes 54 SYSREG Configuration Register Summary 0000 cece ete 54 DDR Controller Configuration Register Summary 000 00 cette eee 55 DDR Controller Configuration Register Bit Definitions 00 eee ee 59 PHY Configuration Register Summary 000000 nee eee 104 PHY Configuration Register Bit Definitions 0 0 00 ete 108 DDR FIC Configuration Registers Summary 00 0c eee eee eee 150 DDR FIC Configuration Register Bit Definitions 0 00 0 ttt 151 Glossa NT 160 ACKONYMS sea CX daphne ea we ane dhe E ER ect ete Ea ad 4 cae dee ae R Gael Paranoia ee eA 160 Histor Changes 4 2 sc624 EEE T a Seid tat dee a Sayeed mead da eees 160 2 Fabie DDR Subsystem asau bsdatbaalaemilel Aen we ddl seem eMaadbanrdendksatn wade 161 Introduction 13405 1565 Leb be beer eid nb be eld ee bee
84. 4 To map the bank bit0 to address 12 the field is configured to A as the base value is 2 Similarly the other bank address bits are configured DDRC ADDR MAP BANK CR 0xAAA The row address bits 0 to 15 are mapped for system address bit 15 to system address bit 27 To map the bank bitO to address 15 the field is configured to 9 as the base value is 6 Similarly the other bank address bits are configured DDRC ADDR MAP ROW 1 CR 0x9999 DDRC ADDR MAP ROW 2 CR Ox9FF Note The FDDR can access the 4 GB address space 0x00000000 OxFFFFFFFF But in this example 512 MB 0x00000000 0x1FFFFFFF DDR3 SDRAM is connected to the 16 address lines of MDDR The memory visible in the other memory space is mirrored of this 512 MB memory DDR Mode Registers After reset the DDR controller initializes the mode registers of DDR memory with the values in the following registers The mode registers must be configured according to the specification of the external DDR memory when the controller is in soft reset e DDRC INIT MR CR e DDRC INIT EMR CR e DDRC INIT EMR2 CR e DDRC INIT EMR3 CR The T MOD and T MRD bits in DDRC DRAM MR TIMING PARAM CR must be configured to the required delay values T MOD and T MRD are delays between loading the mode registers Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide SECDED To enable SECDED mode set the REG DDRC MODE bits to 101 in DDRC MODE CR The P
85. 5 PHY Configuration Register Summary continued Reset Register Name Offset Type Source Description PHY FIFO 1 SR 0x360 RO PRESET N FIFO status register PHY FIFO 2 SR 0x364 RO PRESET N FIFO status register PHY FIFO 3 SR 0x368 RO PRESET Nl FIFO status register PHY FIFO 4 SR 0x36C RO PRESET_N FIFO status register PHY MASTER DLL SR 0x370 RO PRESET N Master DLL status register PHY DLL SLAVE VALUE 1 SR 0x374 RO PRESET NlJSlave DLL status register PHY DLL SLAVE VALUE 2 SR 0x378 RO PRESET N Slave DLL status register PHY STATUS OF IN DELAY VAL 1 SR 0x37C RO PRESET NIIN delay status register PHY STATUS OF IN DELAY VAL 2 SR 0x380 RO PRESET NIIN delay status register PHY STATUS OF OUT DELAY VAL 1 SR 0x384 RO PRESET N OUT delay status register PHY STATUS OF OUT DELAY VAL 2 SR 0x388 RO PRESET N OUT delay status register PHY DLL LOCK AND SLAVE VAL SR 0x38C RO PRESET NIDLL lock status register PHY CTRL OUTPUT FILTER SR 0x390 RO PRESET Nl Control output filter status register PHY RD DQS SLAVE DLL VAL 1 SR 0x398 RO PRESET_N Read DQS slave DLL status register PHY RD DQS SLAVE DLL VAL 2 SR 0x39C RO PRESET N Read DQS slave DLL status register PHY RD DQS SLAVE DLL VAL 3 SR Ox3A0 RO PRESET_N Read DQS slave DLL status register PHY WR DATA SLAVE DLL VAL 1 SR 0x3A4 RO PRESET N Write DATA slave DLL status regi
86. 5 0 DDRC_LCB_MASK 0x0 61 48 bits of DDRC_LCB_MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High This mask does not indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane DDRC_ECC_INT_SR Table 1 103 DDRC ECC INT SR Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 DDRC_ECC_STATUS_SR 0x0 Bit 0 1 Indicates the SECDED interrupt is due to a single error Bit 1 1 Indicates the SECDED interrupt is due to a double error Bit 3 Always 1 DDRC_ECC_INT_CLR_REG Table 1 104 DDRC ECC INT CLR REG Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDRC_ECC_INT_CLR_REG 0x0 This register should be written by the processor when it has read the SECDED erro
87. 5 0 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY RD DQS SLAVE RATIO 2 Table 1 145 PHY RD DQS SLAVE RATIO 2 CR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_RATIO 0x0401 31 16 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 Revision 2 121 lt gt Microsemi MDDR Subsystem PHY_RD_DQS_SLAVE_RATIO_3_CR Table 1 146 PHY RD DQS SLAVE RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the va
88. A APB v3 0 protocol specification Table 2 8 FDDR APB Slave Interface Signals Signal Name Direction Polarity Description APB 8 PREADY Output High Indicates APB Ready signal to Fabric master APB_S_PSLVERR Output High Indicates error condition on an APB transfer to Fabric master APB 8 PRDATA 15 0 Output Indicates APB read data to Fabric master APB S PENABLE Input High Indicates APB enable from Fabric master The enable signal is used to indicate the second cycle of an APB transfer APB_S_PSEL Input High Indicates APB slave select signal from Fabric master APB_S_PWRITE Input High Indicates APB write control signal form Fabric master APB S PADDR 10 2 Input Indicates APB address initiated by Fabric master APB 8 PWDATA 15 0 Input Indicates APB write data from Fabric master Initialization Before the FDDR subsystem is active it goes through an initialization phase and this process starts with a reset sequence For DDR3 memories the initialization phase also includes ZQ calibration and DRAM training 172 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Reset Sequence Figure 2 3 shows the required reset sequence for FDDR subsystem from the power on reset stage The CORE_RESET_N signal of the FDDR subsystem must be asserted after MSS_RESET_N_M2F and FDDR FPLL lock go High and APB register configuration is complete Assertion of C
89. AM ODT 0 Termination Off 1 Termination On FDDR RAS N Out Low DRAM RASN FDDR RESET N Out Low DRAM reset for DDR3 FDDR WE N Out Low DRAM WEN FDDR ADDR 15 0 Out Dram address bits FDDR BA 2 0 Out Dram bank address FDDR_DM_RDQSJ3 0 In out DRAM data mask from bidirectional pads FDDR_DQSJ3 0 In out DRAM single ended data strobe output for bidirectional pads FDDR DGS N 3 0 In out DRAM single ended data strobe output for bidirectional pads FDDR DQ 31 0 In out DRAM data input or output for bidirectional pads FDDR DQ ECC 3 0 In out DRAM data input or output for SECDED FDDR DM RDQS ECC In out High DRAM single ended data strobe output for bidirectional pads FDDR DQS ECC In out High DRAM single ended data strobe output for bidirectional pads FDDR DQS ECC N In out Low DRAM data input or output for bidirectional pads FDDR DQS TMATCH 0 IN In High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH 0 OUT FDDR DQS TMATCH 1 IN In High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH 1 OUT Note AXI or AHB interface depending on configuration 166 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 2 4 e FDDR Subsystem Interface Signals continued Signal Name Type P
90. Access Using an AXI Interface 5 Using a Single AHBLite Interface Figure 4 3 MSS External Memory Configurator Use Model 1 Accessing SDRAM from MSS Through CoreSDR_AXI This use model describes how to use the SMC_FIC to access external SDR memory from MSS It uses the AXI interface of SMC FIC to connect to CoreSDR AXI CoreSDR AXI is an AXI based SDR memory controller The steps provided below are required to access the external SDR memory from CoreSDR AXI 1 Instantiate the SmartFusion2 MSS component onto the SmartDesign canvas 2 Configure the SmartFusion2 MSS peripheral components to meet application needs using MSS configurator 3 Configure the external memory interface type and select Using an AXI Interface as shown in Figure 4 3 234 Revision 2 4 amp Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Instantiate and configure CoreAXI so that the master slot MO is enabled for the slave slot SO as shown in Figure 4 4 The slot size selection must be matched with the amount of external memory space Configuration z l R Configuring COREAXI 0 COREAXI 20103 Memory space Memory space 16 256MB slots beginning at address 0x00000000 wv 64 Y AXI data width Enable master access MO can access slave slot0 V MO can access slave slot 2 MO can access slave slot 4 MO can access slave slot 6 MO can access slave slot 8 MO
91. Anon bufferable or locked transaction is initiated by any master An Invalidate command is issued A buffer disable command is issued An error response from DDR for the expected word read Arbiter The DDR bridge arbiter includes two independent arbitration controllers for read and write requests Write Access Controller The write access controller WAC arbitrates write requests from the WCBs and grants access to one of the requesting masters based on its priority Combinations of fixed and round robin priorities are assigned to the following masters e Master Interface 1 Fixed first priority Master Interface 0 is read only e Round robin between Master Interface 2 and Master Interface 3 for second and third priorities All transactions from a single master have a dedicated master ID Revision 2 219 I Microsemi DDR Bridge Once a burst transaction is initiated to the external DDR memory the transactions are completed without an interruption No other master even a high priority master can interrupt this process Subsequent write requests from the same master are held until the previous write transactions are completed to the external DDR memory Subsequent write requests from other masters can be accepted and allowed to write into WCB but the DDR bridge does not write this data until the previous write transactions are completed to the external DDR memory Read Access Controller The read access controller RAC arbitra
92. Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 12 DDRC REG ECC BANK 0x0 Bank where the SECDED error occurred Only present in designs that support SECDED 11 0 DDRC REG ECC COL 0x0 Column where the SECDED error occurred Col 0 is always set to 0 coming out of the controller This bit is overwritten by the register module and indicates whether the error came from upper or lower lane Only present in designs that support SECDED Table 1 91 DDRC LCE SYNDROME 1 SR DDRC LCE SYNDROME 1 SR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 15 0 bits of DDRC_REG_ECC_SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is
93. C FPGA High Speed DDR Interfaces User s Guide Details of Operation This section provides a functional description of each block in the FDDR subsystem as shown in Figure 2 4 Clock Controller The FDDR subsystem has a dedicated clock controller for generating aligned clocks to all the FDDR sub blocks for correct operation and synchronous communication with user logic in the FPGA fabric The base clock CLK_BASE for the FDDR comes from a fabric CCC or an external source through the FPGA fabric The FDDR clock controller is associated with a dedicated PLL FPLL for clock synthesis and deskewing the internal DDR_FIC clock from the base clock The FDDR clock controller consists of an FPLL and fabric alignment clock controller FACC FPLL The CLK_BASE from the FPGA fabric is used as a reference clock to the FPLL and is multiplied to generate a clock frequency of upto 333 MHz The CLK_BASE can be generated from a fabric CCC PLL one of the on chip oscillators or directly from multi standard user I Os MSIO through FPGA fabric The supplies required to power the FPLL are device core supply VDD for digital section and analog supply FDDR_PLL_VDDA for analog section The FDDR PLL VDDA can be 2 5 V or 3 3 V based on the power supply availability on the board The analog power supply voltage 2 5 V or 3 3 V does not impact the FPLL frequency range Refer to the SmartFusion2 SoC FPGA Datasheet for the FPLL operational range and characteristics
94. DR Within the FDDR subsystem there are two interrupts related to the PLL lock A lock interrupt indicating FPLL lock achieved and an FPLL lock lost interrupt Each of these two interrupts has a corresponding interrupt enable bit in the FDDR subsystem registers It is also possible to read the state of the two PLL lock signals through the FDDR registers In the event of loss of FPLL lock even though its output is not exactly in phase lock with the reference the FPLL still generates a clock User logic in the FPGA fabric can use the FPLL_LOCK signal to prevent communication with the FDDR subsystem during this time DDR_FIC Figure 2 4 shows the DDR_FIC block diagram 64 Bit AXI Single 32 Bit AHBL Dual 32 Bit AHBL Slave Interface AXI Transaction Controller AXI AXI Synchronous Bridge 16 Bit APB Configuration Configuration Bus Registers Figure 2 4 DDR FIC Block Diagram 176 Fabric masters can access the FDDR subsystem in the following ways Single AXI 64 interface Single AHB 32 interface e Dual AHB 32 bit interfaces If the AXI 64 interface is selected the DDR FIC acts as an AXI to AXI synchronous bridge In this mode DDR_FIC provides FPGA fabric masters that access the FDDR subsystem through locked transactions For this purpose a user configurable 20 bit down counter keeps track of the duration of the locked transfer If the transfer is not completed before the down counter reaches zero a single clock cycle
95. DRC DRAM RAS TIMING CR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 5 REG_DDRC_T_RAS_MAX 0x0 tRAS max Maximum time between activate and precharge to same bank Maximum time that a page can be kept open specification 70 us Minimum value of this register is 1 Zero is invalid Unit Multiples of 1 024 clocks 4 0 REG_DDRC_T_RAS_MIN 0x0 tRAS min Minimum time between activate and precharge to the same bank specification 45 ns Unit clocks DDRC_DRAM_RD_WR_TRNARND_TIME_CR Table 1 49 DDRC_DRAM_RD_WR_TRNARND_TIME_CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_DDRC_RD2WR 0x0 RL BL 2 2 WL Minimum time from READ command to WRITE command Include time for bus turnaround and all per bank per rank and global constraints Unit clocks where WL Write latency BL Burst length This must match the value programmed in the BL bit of the mode register to the DRAM RL Read latency CAS latency 4 0 REG DDRC WR2RD 0x0 WL tWTR BL 2 Minimu
96. DRC SINGLE ERR CNT STATUS SR Bit Reset Number Name Value Description 31 0 DDRC SINGLE ERR CNT STATUS REG 0x0 Single error count status If the count reaches OxFFFF it is held and only cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 90 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_DOUBLE_ERR_CNT_STATUS_SR Table 1 83 DDRC DOUBLE ERR CNT STATUS SR Bit Reset Number Name Value Description 31 0 DDRC DOUBLE ERR CNT STATUS REG 0x0 Double error count status If the count reaches OxFFFF then it is held and only cleared after DDRC ECC ERR READ DONE CR is written over by the system Table 1 84 DDRC LUE SYNDROME 1 SR DDRC LUE SYNDROME 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 15 0 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than
97. DRC ZQ SHORT INT REFRESH MARGIN 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 4 REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024 0x0 11 0 bits of REG_DDRC_T_ZQ_SHORT_INTERVAL_ X1024 Average interval to wait between automatically issuing ZQ calibration short ZQCS commands to DDR3 devices Not considered if REG_DDRC_DIS_AUTO_ZQ 1 Units 1 024 clock cycles This is only present for implementations supporting DDR3 devices 3 0 REG_DDRC_REFRESH_MARGIN 0x02 Threshold value in number of clock cycles before the critical refresh or page timer expires A critical refresh is to be issued before this threshold is reached Microsemi recommends using the default value Unit Multiples of 32 clocks DDRC ZQ SHORT INT REFRESH MARGIN 2 CR Table 1 62 DDRC ZQ SHORT INT REFRESH MARGIN 2 CR Bit Reset Number Name Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 0 REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024 0x0 19 12 bits of REG_DDRC_T_ZQ_SHORT_INTERVAL_X10 24 Average interval to wait between automa
98. ELAY VAL 2 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_OF_IN_DELAY_VALUE 0x0 26 16 bits of PHY REG STATUS OF IN DELAY VALUE The coarse and fine values going into the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 Revision 2 143 lt gt Microsemi MDDR Subsystem PHY_STATUS_OF_OUT_DELAY_VAL_1_SR Table 1 203 PHY STATUS OF OUT DELAY VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_OF_OUT_DELAY_VALUE OxO 15 0 bits of PHY_REG_STATUS_OF_OUT_DELA Y_VALUE The coarse and fine values coming out of the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 PHY_STATUS_OF_OUT_DELAY_VAL_2_SR Table 1 204 PHY STATUS OF OUT DELAY VAL 2 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To pr
99. ET N 50 MHz Clock Enable Enable I Os PE DDRIO Calibration SC MSS RESET N o MPLL Lock o MDDR_AXI_RESET_N oo Figure 1 3 Reset Sequence 20 ZQ Calibration This is applicable for DDR3 only The ZQ calibration command is used to calibrate DRAM output drivers Ron and on die termination ODT values The DDR3 SDRAM needs a longer time to calibrate Ron and ODT at initialization and a relatively smaller time to perform periodic calibrations The DDR controller performs ZQ calibration by issuing a ZQ calibration long ZQCL command and ZQ calibration short ZQCS command ZQCL is used to perform initial calibration during the power up initialization sequence This command is allowed for a period of tZQinit as specified by memory vendor The value of tZQinit can be configured through register bits REG DDRC T ZQ LONG NOP The ZQCS command is used to perform periodic calibration to account for voltage and temperature variations A shorter timing window is provided to perform calibration and transfer of values as defined by timing parameter tZQCS The tZQCS parameter can be configured through register bits REG_DDRC_T_ZQ_SHORT_NOP Other activities are not performed by the controller for the duration of tZQinit and tZQCS All DRAM banks are precharged and tRP met before ZQCL or ZQCS commands are issued by the DDR controller DRAM Training This is applicable for DDR3 only If this option is enabled the DDR controller performs PHY
100. EVEL 0x0 Read DQS gate training control 0 Use register programmed ratio values 1 Use ratio for delay line calculated by DQS gate leveling This can be used in DDR2 mode also Note This port must be set to 0 when PHY is not working in DDR2 DDR3 mode REG PHY USE RD DATA EYE LEVEL 0x0 Read data eye training control 0 Use register programmed ratio values 1 Use ratio for delay line calculated by data eye leveling Note This port must be set to 0 when PHY is not working in DDR3 mode Revision 2 133 lt gt Microsemi MDDR Subsystem PHY_DYN_CONFIG_CR Table 1 175 PHY DYN CONFIG CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 REG PHY DIS PHY CTRL RSTN 0x0 Disable the PHY control macro reset 1 PHY control macro does not get reset 0 PHY control macro gets reset default 3 REG PHY LPDDR1 0x0 If the PHY is operating in LPDDR1 mode 2 REG PHY BL2 0x0 Burst length control 1 Burst length 2 0 Other burst length 1 REG_PHY_CLK_STALL_LEVEL 0x0 This port determines whether the delay line clock stalls at High or Low level The expected input is a very slow clock to avoid asymmetric aging in delay lines This port is implementation specific a
101. FDDR s APB S PCLK and APB S PRESET N have to be connected to FIC 2 APB M PCLK and FIC 2 APB M PRESET N The FIC 2 APB M PCLK clock is generated from MSSCCC and is identical to M3 CLK 4 I O Configuration I O settings such as ODT and drive strength can be configured as shown in Figure 2 12 using the I O Editor in Libero SoC Resistor Pull 1 0 available in Flash Freeze mode Schmitt Trioger r j Figure 2 12 I O Configuration 188 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide FDDR Subsystem Features Configuration The FDDR subsystem registers must be initialized before accessing DDR memory through the FDDR subsystem This section provides the necessary registers to configure the features of the FDDR All registers are listed with their bit definitions in the FDDR Configuration Registers section on page 203 section Memory Type DDRC_MODE_CR must be configured to select the memory type DDR2 DDR3 or LPDDR1 to access memory from the FDDR subsystem Bus Width Configurations The FDDR supports various bus widths as listed in Table 2 12 The FDDR can be programmed to work in full half or quarter Bus width mode by configuring the DDRC MODE CR and PHY DATA SLICE IN USE CR registers when the controller is in soft reset Table 2 12 Supported Bus Widths
102. FDDR_DQS_N 2 FDDR_DQ 23 16 MT41J512M8RA FDDR DM RDQS 3 FDDR DQS 3 FDDR DQS N 3 FDDR DQ 31 24 MT41J512M8RA FDDR_DM_RDQS_ECC FDDR_DQS_ECC FDDR_DQS_ECC_N FDDR DQ ECC 3 0 DQ 3 0 MT41J512M8RA Figure 2 26 x8 DDR3 SDRAM Connection to FDDR 202 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Example 3 Connecting 16 Bit LPDDR to FDDR_PADs with SECDED Figure 2 27 shows LPDDR1 SDRAM connected to the FDDR of a SmartFusion2 device The Micron s MT46H32M16LF is a 64 MB density device with x16 data width The FDDR is configured in Full Bus Width mode with SECDED enabled The SDRAM connected to FDDR DQ ECC 1 0 is used to store SECDED bits The total amount of LPDDR1 memory excluding memory for SECDED connected to FDDR is 64 MB FDDR_PADS MT46H32M16LF FDDR_CAS_N CASN FDDR_CKE CKE FDDR CLK u i S CLK P FDDR CLK NT CLK N CSN FDDR_RAS_N Lt RASN FDDR we N h ET WEN FDDR_ADDR 12 0 ADDR 12 0 FDDR Balto LJ i iit BA 20 FDDR DM RDQS 1 0 ETT TTT TN UDM LDM FDDR DQS 0 LDQS FDDR DQSN1 PJ TT UDQS FDDR DQ 15 0 DQ 15 0 FDDR DM RDQS ECC FDDR DQS ECC FDDR DQ ECC 1 0 MT46H32M16LF CASN CKE CLK P CLK_N CSN RASN WEN ADDR 12 0 BA 2 0 LDM LDQS DQN 0 Figure 2 27 x16 LPDR1SDRAM Connection to FDDR FDDR Configuration Registers This section provides FDDR subsystem registers along with the address offset functionality and bit definit
103. Fusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 105 PHY Configuration Register Summary continued Reset Register Name Offset Type Source Description PHY GATELVL INIT RATIO 1 CR 0x270 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 2 CR 0x274 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 3 CR 0x278 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 4 CR 0x27C RW PRESET NIlInit ratio value configuration register PHY LOCAL ODT CR 0x280 RW PRESET N PHY ODT control register PHY INVERT CLKOUT CR 0x284 RW PRESET_N PHY DRAM clock polarity change register PHY RD DQS SLAVE DELAY 1 CR 0x288 RW PRESET N Delay value for read DQS PHY RD DQS SLAVE DELAY 2 CR 0x28C RW PRESET N Delay value for read DQS PHY RD DQS SLAVE DELAY 3 CR 0x290 RW PRESET N Delay value for read DQS PHY RD DQS SLAVE FORCE CR 0x294 RW PRESET Nl Overwriting delay value selection reg for read DQS PHY RD DQS SLAVE RATIO 1 CR 0x298 RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 2 CR 0x29C RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 3 CR 0x2A0 RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 4 CR 0x2A4 RW PRESET N Ratio value for read DQS slave DLL PHY WR DQS SLAVE
104. GA High Speed Serial SmartFusion2 devices integrate hard high speed serial Interfaces User s Guide interfaces PCle XAUI XGXS SERDES for accessing external bulk memories This document describes the SmartFusion2 high speed serial interfaces SmartFusion2 Clocking Resources User s Guide SmartFusion2 clocking resources include oscillators FPGA fabric global network and clock conditioning circuitry CCCs with dedicated phase locked loops PLLs These clocking resources provide flexible clocking schemes to the on chip hard IP blocks MSS fabric DDR FDDR subsystem and high speed serial interfaces PCle XAUI XGXS SERDES and logic implemented in the FPGA fabric SmartFusion2 Low Power Design User s Guide In addition to low static power consumption during normal operation SmartFusion2 devices support an ultra low power Static mode Flash Freeze mode with power consumption less than 1 mW Flash Freeze mode retains all the SRAM and register data which enables fast recovery to Active mode This document describes the SmartFusion2 Flash Freeze mode entry and exit mechanisms SmartFusion2 System Controller User s Guide The system controller manages programming of the SmartFusion2 device and handles system service requests The subsystems interfaces and system services in the system controller are discussed in this user s guide SmartFusion2 Security and Reliability User s Guide The SmartFusion2 device family incorporates essentially all
105. G_DDRC_T_RC Minimum time between two successive activates to a given bank Row precharge command period tRP REG_DDRC_T_RP Minimum time from a precharge command to the next command affecting that bank Minimum bank active time tRAS min REG_DDRC_T_RAS MIN Minimum time from an activate command to a precharge command to the same bank Maximum bank active time tRAS max RAS to CAS delay tRCD REG DDRC T RAS MAX REG DDRC T RCD Maximum time from an activate command to a precharge command to the same bank Minimum time from an activate command to a Read or Write command to the same bank Write command period tWR REG_DDRC_WR2PRE Minimum time from a Write command to a precharge command to the same bank Read to precharge delay REG_DDRC_RD2PRE Minimum time from a Read command to a precharge command to the same bank Set this to the current value of additive latency plus half of the burst length Dynamic DRAM Rank Constraints The timing constraints which affect the transactions to a rank are listed in Table 1 16 The control bit field must be configured as per the DDR memory vendor specification Table 1 16 Dynamically Enforced Bank Constraints Timing Constraints of DDR Memory Control Bit Description Nominal refresh cycle time tRFC nom or tREFI REG DDRC T RFC NOM X32 Average time between refreshes for a given rank The actual time betwee
106. HY DATA SLICE IN USE CR register must be configured to enable data slice 4 of the PHY The register value REG DDRC LPR NUM ENTRIES in the performance register DDRC PERF PARAM 1 CR must be increased by 1 to the value used in Normal mode without SECDED Read Write Latencies The read and write latencies between DDR controller and DDR PHY can be configured Configure the DDRC DRAM RD WR LATENGY CR register for adding latencies for read and writes Performance The DDR controller has several performance registers which can be used to increase the speed of the read and write transactions to DDR memory The DDR controller has a transaction store shared for low and high priority transactions The DDRC_PERF_PARAM_1_CR register can be configured for allocating the transaction store between the low and high priority transactions For example if the REG DDRC LPR NUM ENTRIES field is configured to 0 the controller allocates more time to high priority transactions The ratio for LPR HPR is 1 7 as the transaction store depth is 8 The DDRC_HPR_QUEUE_PARAM_1_CR DDRC_LPR_QUEUE_PARAM_1_CR and DDRC WR QUEUE PARAM CR registers can be configured for the minimum clock values for treating the transactions in the HPR LPR and WR queue as critical and non critical To force all incoming transactions to low priority configure the DDRC_PERF_PARAM_2_CR register By default it is configured to force all the incoming transactions to low priority Th
107. HY DYN RESET CR 0x31C RW PRESET NIThis register will bring the PHY out of reset PHY LEVELLING FAILURE SR 0x320 RO PRESET_N Leveling failure status register PHY BIST ERROR 1 SR 0x324 RO PRESET NIBIST error status register PHY BIST ERROR 2 SR 0x328 RO PRESET_N BIST error status register PHY BIST ERROR 3 SR 0x32C RO PRESET NIBIST error status register PHY WRLVL DQS RATIO 1 SR 0x330 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 2 SR 0x334 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 3 SR 0x338 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 4 SR 0x33C RO PRESET N Write level DQS ratio status register PHY WRLVL DQ RATIO 1 SR 0x340 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 2 SR 0x344 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 3 SR 0x348 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 4 SR 0x34C RO PRESET N Write level DQ ratio status register PHY RDLVL DQS RATIO 1 SR 0x350 RO PRESET_N Read level DQS ratio status register PHY RDLVL DQS RATIO 2 SR 0x354 RO PRESET N Read level DQS ratio status register PHY RDLVL DQS RATIO 3 SR 0x358 RO PRESET N Read level DQS ratio status register PHY RDLVL DQS RATIO 4 SR 0x35C RO PRESET_N Read level DQS ratio status register I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 10
108. IN 0x0 000 500 ppm 100 8000 ppm 001 1000 ppm 101 16000 ppm 010 2000 ppm 110 32000 ppm 011 4000 ppm 111 64000 ppm Phase error window for Lock assertion as a fraction of divided reference period Values are at typical PVT only and are not PVT compensated 3 0 PLL_FILTER_RANGE 0x9 PLL filter range 0000 BYPASS 0111 18 29 MHz 0001 1 1 6 MHz 1000 29 46 MHz 0010 1 6 2 6 MHz 1001 46 75 MHz 0011 2 6 4 2 MHz 1010 75 120 MHz 0100 4 2 6 8 MHz 1011 120 200 MHz 0101 6 8 11 MHz 0110 11 18 MHz Table 2 22 FDDR FACC CLK EN FDDR FACC CLK EN Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_CLK_EN 0x1 Enables the clock to the DDR memory controller Revision 2 207 I Microsemi Fabric DDR Subsystem FDDR FACC MUX CONFIG Table 2 23 FDDR FACC MUX CONFIG Bit Number Name Reset Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation FACC_FAB_REF_SEL 0x0 Selects the source of the reference clock to be supplied to the FPLL 0 25 50 MH
109. L_DQS_RATIO 0x0 31 16 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS PHY WRLVL DQS RATIO 3 SR Table 1 184 PHY WRLVL DQS RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQS_RATIO 0x0 47 32 bits of PHY REG WRLVL DQS RATIO Ratio value generated by the write leveling FSM for write DQS PHY_WRLVL_DQS_RATIO_4_SR Table 1 185 PHY WRLVL DQS RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_WRLVL_DQS_RATIO 0x0 49 48 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS Revision 2 137 lt gt Microsemi MDDR Subsystem PHY_WRLVL_DQ_RATIO_1_SR Table 1 186 PHY WRLVL DQ RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reser
110. Libero SoC SYSREG Control Register for SMC FIC Complete descriptions of each register and bit are located in the System Register Map chapter of the SmartFusion2 Microcontroller Subsystem User s Guide and are listed here for clarity Table 4 3 e MDDR CR Register Register Name MDDR CR Register Type RW P Flash Write Protect Register Reset Source PORESET N Description MDDR configuration register 236 Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Glossary Acronyms AXI Advanced extensible interface AHB Lite AMBA high performance bus Lite AHBL AMBA high performance bus Lite DDRIO DDR input output ENVMO Embedded nonvolatile memory 0 HPDMA High performance peripheral direct memory access INCR Increment MSIO Multi standard input output MSS Microcontroller subsystem MSSDDR Microcontroller subsystem DDR SMC FIC Soft memory controller fabric interface controller SYSREG System register Revision 2 237 lt gt Microsemi A List of Changes The following table lists critical changes that were made in each revision of the chapter in the user s guide Date Changes Page Revision 2 Restructured the user s guide SARs 47314 45974 45616 43424 46149 NA April 2013 46446 Updated Address Mapping section SAR 45761 160 and 214 Updated MDDR Memory Map section SAR 44198
111. MHz Figure 1 18 e MDDR Clock Configuration 6 Instantiate the clock resources FAB CCC and chip oscillators in the SmartDesign canvas and configure as required 7 Instantiate user AXI master logic in the SmartDesign canvas to access the MDDR through the AXI interface Make sure that the AXI master logic accesses the MDDR after configuring the MDDR registers from the APB master The AXI master clock should be same as DDR SMC FIC CLK 8 Instantiate user APB master logic in the SmartDesign canvas to configure the MDDR registers through the APB interface The APB master logic should initialize the registers after the MSS comes out of reset The APB clock must be connected to FIC 2 APB M PCLK 9 Connect the AXI master and APB master to the MSS component through CoreAXI and CoreAPB or use the auto connect option in SmartDesign 10 Make the other connections in the SmartDesign canvas as shown in Figure 1 19 on page 45 44 Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide CoreAPB3 0 L r SYSRESET 0 DEVRST N FOWER ON RESET N A osco ROOSC_25_50MHZ_OCC_O gr RCOSC_25_50MHZ_OCC_IN X IFIC 2 APB MASTER Figure 1 19 e SmartDesign Canvas 11 To verify the design in Libero SoC software create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory ve
112. MW commands This is classed as an AXI write address channel sideband signal and is valid with the AWVALID signal Only used when SECDED is enabled CLK BASE PLL LOCK In High Fabric PLL lock input FPLL LOCK Out High PLL lock status of DDR PLL Interrupts PLL LOCK INT Out High PLL lock interrupt PLL_LOCKLOST_INT Out High PLL lock lost interrupt ECC_INT Out High Sticky interrupt on APB clock Generated on ECC errors from the DDR controller IO CALIB INT Out High Sticky Interrupt on APB clock Generated on code lock from the I O calibration block FIC INT Out High Sticky interrupt on APB clock Generated on error conditions from the DDR_FIC Note AXI or AHB interface depending on configuration Revision 2 165 lt gt Microsemi Fabric DDR Subsystem Table 2 4 e FDDR Subsystem Interface Signals continued Signal Name Type Polarity Description Bus Interfaces AXI SLAVE Bus AXI slave interface 1 0 bus AHBO SLAVE Bus AHBO slave interface 3 0 bus AHB1 SLAVE Bus AHB1 slave interface 3 0 bus APB SLAVE Bus APB slave interface 3 0 bus DRAM Interface FDDR CAS N Out Low DRAM CASN FDDR CKE Out High DRAM CKE FDDR CLK Out DRAM single ended clock for differential pads FDDR_CLK_N Out DRAM single ended clock for differential pads FDDR_CS_N Out Low DRAM CSN FDDR_ODT Out High DR
113. M_2_CR registers These must be configured before taking the controller out of soft reset They are applied to every read or write issued by the controller Soft Resets Set the REG_DDRC_SOFT_RSTB bit of DDRC_DYN_SOFT_RESET_CR to 0 to reset the DDR controller To release the DDR controller from reset set the REG_DDRC_SOFT_RSTB bit of DDRC_DYN_SOFT_RESET_ALIAS_CR to 1 MDDR Memory Map The address map to access the DDR memory from MSS masters through MDDR is OxA0000000 OxDFFFFFFF which is 1 GB But the MDDR can support up to 4 GB of memory out of which only 1 GB of this memory is accessible at a time from the Cortex M3 processor or MSS masters through the AHB bus matrix DDR_FIC can access the entire 4 GB memory To enable MSS masters to access 4 GB the DDR address space 0x00000000 0xFFFFFFFF is divided into 16 DDR regions as shown in Table 1 16 on page 37 Each region is of 256 MB So 4 regions together form 1 GB The MSS masters can access any of these four regions at a time depending on the Address Space Mapping mode configured for that particular master using the DDRB_CR register in SYSREG The DDRB CR register has four 4 bit fields DDR IDC MAP DDR SW MAP DDR HPD MAP and DDR DS MAP that can be configured to select the DDR Address Space Mapping modes from 0 to 12 The Address Space Mapping modes for a 4 GB memory are shown in Table 1 19 on page 41 For example if the DDR SW MAP is configured as 0001 then the AHB bus
114. N MSS DDR bridge buffer empty status register Revision 2 223 amp Microsemi DDR Bridge Table 3 2 e SYSREG Control Registers continued Register Flash Write Register Name Type Protect Reset Source Description DDRB_DSBL_DN_SR RO SYSRESET_N MSS DDR bridge disable buffer status register DDRB_STATUS RO SYSRESET_N Indicates MSS DDR bridge status MSS_EXTERNAL_SR SW1C SYSRESET N MSS external status register MSSDDR FACC1 CR RW P Field CC RESET N MSS DDR fabric alignment clock controller 1 configuration register DDR Bridge Control Registers in MDDR and FDDR Table 3 3 lists MSS DDR bridge control registers in the MDDR and FDDR Refer to the MDDR Subsystem chapter on page 7 and the Fabric DDR Subsystem chapter on page 161 for a detailed description of each register and bit Table 3 3 DDR Bridge Control Registers in MDDR and FDDR Address Reset Register Name Offset R W Source Description DDR FIC NB ADDR CR 0x400 RW PRESET N Indicates the base address of the non bufferable address region DDR FIC NBRWB SIZE CR 0x404 RW PRESET N l Indicates the size of the non bufferable address region DDR FIC BUF TIMER CR 0x408 RW PRESET_N 10 bit timer interface used to configure the timeout register DDR FIC HPD SW RW EN CR 0x40C RW PRESET N Enable write buffer and read buffer register for AHB Lite AHBL mast
115. NON CRITICAL OxF 15 clks MAX_STARVE 0x1 15 clks HPR_QUEUE_PARAM_2_CR MAX_STARVE 0x7 DDRC_PERF_PARAM_2_CR 0x0 Burst mode Sequential MDDR Clock Configuration The MDDR subsystem operates on MDDR_CLK which comes from MSS_CCC The MDDR_CLK must be selected as a multiple 1 2 3 4 6 or 8 of M3 CLK This clock value can be configured through the MSS CCC configurator in Libero SoC as shown in Figure 1 11 The maximum frequency of MDDR_CLK is 333 33 MHz E MSS Clock Conditioning Circuitry Configurator System Clocks Advanced Options Clock Source CLK_BASE 111 00 MHz v Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK Cortex M3 and MSS Main Clock M3 CLK 111 MHz 111 000 MHz MDDR Clocks v MDDR CLK M3_CLK e 333 000 MHz v DDR SMC FIC CLK MDDF 111 000 MHz 4 MSS APB 0 1 Sub busses Clocks 6 st APR N AIK M2 wie FTI Ann MHz Figure 1 11 MDDR Clock Configuration Revision 2 33 I Microsemi MDDR Subsystem DDR SMC FIC CLK drives the DDR FIC slave interface and defines the frequency at which the FPGA fabric subsystem connected to this interface is intended to run DDR SMC FIC CLK can be configured as a ratio of MDDR_CLK 1 2 3 4 6 8 12 16 or 32 through the MSS_CCC configurator in Libero SoC as shown in Figure 1 12 The maximum frequency of DDR SMC CLK is 200 MHz 3 MSS Clock Conditioning Circuitry Configurator System Clocks Advanced Options Clock Source CLK_BASE 111
116. O 0x0 54 48 of REG_PHY_GATELVL_INIT_RATIO Lowest 11 R bits are from data slice 0 next 11 R bits are for data slice 1 etc Revision 2 PHY LOCAL ODT CR Table 1 138 PHY LOCAL ODT CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 2 REG_PHY_IDLE_LOCAL_ODT 0x0 The user programmable initialization ratio selection mode 01 Selects a starting ratio value based on the REG_PHY_GATELVL_INIT_RATIO port 00 Selects a starting ratio value based on write leveling of the same data slice 1 REG_PHY_WR_LOCAL_ODT 0x0 Tied to 0 0 REG_PHY_RD_LOCAL_ODT 0x0 _ Tied to 0 PHY_INVERT_CLKOUT_CR Table 1 139 PHY INVERT CLKOUT CR Bit Name Reset Description Number Value 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY INVERT CLKOUT 0x0 Inverts the polarity of the DRAM clock 0 Core clock is passed on to DRAM Most common usage mode 1 Inverted core clock is passed on to DRAM Use this
117. OCK 1 0 Output Indicates lock type This signal provides additional information about the atomic characteristics of the write transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved Revision 2 231 I Microsemi Soft Memory Controller Fabric Interface Controller Table 4 1 e SMC FIC 64 bit AXI Port List continued 232 Signal Direction Polarity Description MDDR SMC AXI M ARLOCK 1 0 Output Indicates lock type This signal provides additional information about the atomic characteristics of the read transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved MDDR SMC AXI M BID 3 0 Input Indicates response ID The identification tag of the write response The MDDR SMC AXI M BID value must match the MDDR SMC AXI M AWID value of the write transaction to which the slave is responding MDDR SMC AXI M RID 3 0 Input Read ID tag This signal is the ID tag of the read data group of signals The MDDR SMC AXI M RID value is generated by the slave and must match the MDDR SMC AXI M ARID value of the read transaction to which it is responding MDDR SMC AXI M RRESP 1 0 Input Indicates read response This signal indicates the status of the read transfer 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error MDDR SMC AXI M BRESP 1 0 Input Indicates write response This signal indicates the status of the write trans
118. ORE_RESET_N signifies the end of the reset sequence Microsemi provides CoreSF2Reset IP to simplify the initialization process The DDR controller performs external DRAM memory reset and initialization as per the JEDEC specification including reset refresh and mode registers DDRIO Calibration Each DDRIO has an ODT feature which is calibrated depending on the DDR I O standard DDR I O calibration occurs after the DDR I Os are enabled If the impedance feature is enabled impedance can be programmed to the desired value in three ways e Calibrate the ODT driver impedance with a calibration block e Calibrate the ODT driver impedance with fixed calibration codes Configure the ODT driver impedance to the desired value directly The FDDR_IO_CALIB_CR register can be configured for changing the ODT value to the desired value For more information on DDR 1 O calibration refer to the Configurable ODT and Driver Impedance section of the I O s chapter in the SmartFusion2 FPGA Fabric Architecture User s Guide PO_RESET_N APB S PRESET_N DDRIO Calibration MSS_RESET_N_M2F EE FPLL LOCK EE SG FDDR APB Register Configuration CORE RESET N Er Figure 2 3 Reset Sequence ZQ Calibration ZQ calibration is applicable for DDR3 only This is used to calibrate DRAM output drivers Roy and on die termination ODT values DDR3 SDRAM needs a longer time to calibrate Ron and ODT at initialization and a relatively smaller time to perform
119. PORESET N MDDR Configuration register MDDR_IO_CALIB_CR RW P Register PORESET N MDDR1 O Calibration Control register MSSDDR_PLL_STATUS_LOW_CR Used to control the corresponding RINGE Register CC_RESET_N configuration input of the MPLL MSSDDR_PLL_STATUS_HIGH_CR Used to control the corresponding RW P Register CC_RESET_N configuration input of the MPLL register MSSDDR_FACC1_CR MSS DDR Fabric Alignment Clock RWP Field OG RESET N Controller 1 Configuration register MSSDDR FACC2 CR p MSS DDR Fabric Alignment Clock REP pe EE NESEN Controller 2 Configuration register MSSDDR CLK CALIB STATUS i Used to start an FPGA fabric RW P Register SYSRESET N calibration test circuit DDRB_CR RW P Register SYSRESET_N MSS DDR bridge configuration register MSSDDR_PLL_STATUS RO MSS DDR PLL Status register MDDR_IO_CALIB_STATUS RO PORESET_N DDR I O Calibration Status register MSSDDR CLK CALIB STATUS RO E SYSRESET N MSS DDR Clock Calibration Status register SOFT RESET CR RW P Bit SYSRESET N Soft reset control register 54 Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR Controller Configuration Register Summary Table 1 24 DDR Controller Configuration Register Address Register Reset Register Name Offset Type Source Description DDRC DYN SOFT RESET CR 0x000 RW RO PRESET N DDRC Reset register DDRC
120. R SR indicates the location of the bit that caused the single bit error in the SECDED case encoded value 4 DDRC ECC INT SR indicates whether the SECDED interrupt is because of a single bit error or double bit error The interrupt can be cleared by writing zeros to DDRC ECC INT CLR REG Power Saving Modes The DDR controller can operate DDR memories in three power saving modes 1 Precharge power down 2 Self refresh 3 Deep power down Precharge Power Down If REG DDRC POWERDOWN EN 1 the DDR controller automatically keeps DDR memory in precharge power down mode when the period specified by REG DDRC POWERDOWN TO X32 register has passed while the controller is idle except for issuing refreshes The controller automatically performs the precharge power down exit on any of the following conditions e A refresh cycle is required to any rank in the system e The controller receives a new request from the core logic e REG DDRC POWERDOWN EN is set to 0 26 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Self Refresh The DDR controller keeps the DDR memory devices in Self refresh mode whenever the REG_DDRC_SELFREF_EN register bit is set and no reads or writes are pending in the controller The DDR controller can be programmed to issue single refreshes at a time REG_DDRC_REFRESH_BURST 0 to minimize the worst case impact of a forced refresh cycle It can be programmed to burst the maxi
121. Ratio value generated by read gate training FSM PHY_MASTER_DLL_SR Table 1 198 PHY MASTER DLL SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 3 PHY_REG_STATUS_OF_IN_LOCK_STATE 0x0 Lock status from the output filter module inside the master DLL 2 bits per MDLL PHY has 3 MDLLs Bit 0 Fine delay line lock status 1 Locked 0 Unlocked Bit 1 Coarse delay line lock status 1 Locked 0 Unlocked 2 0 PHY REG STATUS DLL LOCK 0x0 _ Status signal 1 Master DLL is locked 0 Master DLL is not locked Three bits correspond to three MDLLs Revision 2 141 lt gt Microsemi MDDR Subsystem PHY_DLL_SLAVE_VALUE_1_SR Table 1 199 PHY DLL SLAVE VALUE 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_DLL_SLAVE_VALUE 0x0 15 0 bits of PHY_REG_STATUS_DLL_SLAVE_VALUE Shows the current coarse and fine delay values measured for a full cycle shift by each master DLL This is a 27 bit register 9 bits for each DLL 1 0 Fine value 8 2 Coar
122. Revision 2 85 lt gt Microsemi MDDR Subsystem DDRC DFI WR LVL CONTROL 2 CR Table 1 75 DDRC DFI WR LVL CONTROL 2 CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 5 REG_DDRC_DFI_T_WLMRD 0x0 First DQS DQS rising edge after write leveling mode is programmed Only present in designs that support DDR3 devices Units Clocks 4 REG DDRC DFI WR LEVEL EN 0x0 1 Write leveling mode has been enabled as part of the initialization sequence Only present in designs that support DDR3 devices 3 0 REG DDRC DFI WRLVL MAX X1024 0x0 11 8 bits of REG DDRC DFI WRLVL MAX X1024 Write leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI WRLVL RESP to a write leveling enable signal DDRC DFI WRLVL EN Only applicable when connecting to PHYs operating in PHY write leveling evaluation mode Units 1 024 clocks Only present in designs that support DDR3 devices DDRC DFI RD LVL CONTROL 1 CR Table 1 76 DDRC DFI RD LVL CONTROL 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the
123. S DDR Space 1 MSS DDR Space 2 DDR Memory Regions Visible at MSS DDR Address Space for Different Modes MSS DDR Space 3 Address Space 0xA0000000 0xB0000000 0xC0000000 0xD0000000 Mapping Modes OxAFFFFFFF 0xBFFFFFFF OxCFFFFFFF 0xDFFFFFFF 0000 Region 2 Region 3 Region 0 Region 1 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 Use Model 1 Accessing MDDR from FPGA Fabric Through the AXI Interface The MDDR subsystem can be used to access DDR memory as shown in Figure 1 15 on page 43 The AXI master in the FPGA fabric accesses the DDR memory through the MDDR subsystem The MDDR registers are configured from FPGA fabric through the APB interface The APB master in the FPGA fabric asserts a ready signal to indicate that the DDR memory is successfully initialized The read write and read modify write transactions are initiated by the AXI master to read or write the data into the DDR memory after receiving the ready signal from APB master 42 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide AXI MSS DDR DDR DDR Bridge SDRAM Controller el FPGA Fabric Figure 1 15 e MDDR with AXI Interface Use the following steps to access the MDDR from the AXI master in the FPGA fabric 1 Instantiate the SmartFusion2 MSS component onto the SmartDesign canvas 2 Configure the SmartFusion2 MSS peripheral components as requi
124. SLAVE DLL VALUE OxO 15 0 bits of PHY REG STATUS WR DQS SLAV E DLL VALUE Delay value applied to write DQS slave DLL PHY WR DQS SLAVE DLL VAL 2 SR Table 1 217 PHY WR DQS SLAVE DLL VAL 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY REG STATUS WR DQS SLAV E DLL VALUE Delay value applied to write DQS slave DLL PHY WR DQS SLAVE DLL VAL 3 SR Table 1 218 PHY WR DQS SLAVE DLL VAL 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY REG STATUS WR DQS SLAVE DLL VALUE 0x0 44 32 bits of PHY REG STATUS WR DQS SLAV E DLL VALUE Delay value applied to write DQS slave DLL Revision 2 149 I Microsemi MDDR Subsystem PHY CTRL SLAVE DLL VAL SR Table 1 219 PHY CTRL SLAVE DLL VAL SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility w
125. SOFT_RESET_CR 0x000 read write Ox4 Ox4 32 REG_DDRC_SOFT_RSTB read write 00 MT oo RESET APB REG read write 00 060 1 1 E AXIRESET read write Od Od 2 2 7 DDRC_DYN_REFRESH_1_CR 0x008 read write 0x1188 0x1188 32 DDRC_DYN_REFRESH_2_CR 000c read write 0x290 0x290 32 DDRC_DYN_POWERDOWN_CR 0010 read write 0x2 02 32 DDRC_DYN_DEBUG_CR 0x014 read write 00 00 32 DDRC MODE CR 0018 read write 0x0 0x0 32 DDRC_ADDR_MAP_BANK_CR dic read write 0x0 0x0 32 DDRC_ECC_DATA_MASK_CR 0x020 read write 0x0 0x0 32 DDRC_ADDR_MAP_COL_1_CR 0x024 read write 0x0 0x0 32 DDRC_ADDR_MAP_COL_2_CR 0028 read write 00 00 32 DDRC ADDR MAP ROW 1 CR 002c read write 00 0x0 32 DDRC_ADDR_MAP_ROW_2_CR 0x030 read write 0x0 0x0 32 DDRC_INIT_1_CR 0x034 read write Od 0d 32 DDRC_CKE_RSTN_CYCLES_CR1 0038 read write 0x0 0x0 32 DDRC_CKE_RSTN_CYCLES_CR2 003c read write 0x0 0x0 32 DDRC_INIT_MR_CR 0x040 read write 095a 095a 32 DDRC_INIT_EMR_CR 0x044 read write 0x402 0x402 32 DDRC_INIT_EMR2_CR 0x048 read write 0x0 0x0 32 DDRC_INIT_EMR3_CR Ox04c read write 0x0 0x0 32 DDRC_DRAM_BANK_TIMING_PARAM_CR 0x050 read write 0x0 0x0 16 DDRC_DRAM_RD_WR_LATENCY_CR 0x054 read write 0x0 0x0 32 DDRC_DRAM_RD_WR_PRE_CR 0x058 read write 0x0 0x0 32 DDRC_DRAM_MR_TIMING_PARAM_CR Ox05c read write 0x0 0x0 32 DDRC_DRAM_RAS_TIMING_CR 0x060 read write 0x0 0x0 32 DDRC_DRAM_RD_WR_TRNARND_TIME_CR 0x064 read write 0x0 0x0 16 DDRC_DRAM_T_PD_CR 0x068 read write 0x0 0x0 32 DDRC_DRAM_BANK_ACT_TIMING_CR 0x06 read wri
126. SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide amp Microsemi lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table of Contents About This Guide 5 Purpose var vatn acaba dasa a Meret are kaerekereedeet ate et bee ae doe dG Seale Sib e secs 5 COMENS ae 5 Additional Documentation 0 2 0 nett ae 5 Related DOCUMENTS s ar 41s eee EEE EE EE EE 6 TUONAlS sunassteavedeserdate oon DOR EE dead ea E ae de dae desk rase eee seke s k ee ea Rae 6 i IMBDRSUDSYStEMccscsa5c ited o hd a G seed LESAGE ad add dee 7 al ao e 8 e Co a lemme ae terer vee aie ar ot ere aa eT nO a fe 7 Features kuuavart steered ke se anses Genese he Sledge EO E AEA a ed ARE ea E Rap 6 husene a ee ee ie Er 7 Memory Configurations iuaataaeae suse ks ahead teva tvedereudad jedd sa bek a a a aea a banks sa hen dd dete 8 Performance sgoinn drbsrsn db A shad h a Se ye arter SOenkssedue sad TSG SALGSAGENT Ames Abad 9 OVNEN Aa be tg 10 Functional Description a a s 29 a sp ek kranen s k ka Pee dok kal ka EEE Fade da EEE ke id di 10 Architecture OVErVlEW esasi ina fa duene nut gh ale made sene bed ket ease Jin id ea de ng se 10 Port lists arv rase Alene data a a a oh ged a cag 11 Initialization vaavvsrcsasesrassrrrae sa orka sene TEKST tn aCe aaa BERE Hane Sieey a nae ethane ste GRRE oi 19 Details of Operation seris gene add dot Bead dee E aa Sydde least Liane aided toi sed 21 How to Use the MDDR 24
127. Subsystem Figure 3 1 DDR Bridges in the SmartFusion2 SoC FPGA Device Revision 2 215 amp Microsemi DDR Bridge The DDR bridge supports a single 64 bit AXI and up to four 32 bit AHB interfaces The four MSS AHB masters are fixed as shown in Table 3 1 The DDR bridges in the MDDR and FDDR subsystems support only two AHB interfaces out of four and these can be used for user implemented AHB masters Table 3 1 SmartFusion2 SoC FPGA DDR Bridge Interface DDR Bridge Sub AHB Interface 0 AHB Interface 1 AHB Interface 2 AHB Interface 3 System Read Only R W R W R W AXI Interface MSS Cache controller Cache controller AHB bus matrix HPDMA MDDR IDC DS subsystem MDDR Not available Not available AHB master interface 0 AHB master interface 1 MDDR subsystem FDDR Not available Not available AHB master interface 0 AHB master interface 1 FDDR subsystem Note Ifthe AXI bus is selected as the interface between the FPGA fabric and the MDDR FDDR subsystem the DDR bridge in these subsystems is not used Functional Description This section provides the detailed description of the DDRBridge which contains the following sections e Architecture Overview e Details of Operation Architecture Overview The DDR bridge consists of two main components read and write combining buffers WCB and an arbiter as shown in Figure 3 2 on page 217 The DDR bridge buffers AHB write transactions into write combining buffers before bursting out to external
128. TRL SLAVE DELAY CR 0x22C RW PRESET NIPHY control slice DLL slave delay register PHY DATA SLICE IN USE CR 0x230 RW PRESET N PHY data slice in use register PHY LVL NUM OF DQO0 CR 0x234 RW PRESET N PHY receiver on off control register PHY DQ OFFSET 1 CR 0x238 RW PRESET_N Selection register of offset value from DQS to DQ PHY DQ OFFSET 2 CR 0x23C RW PRESET NlJSelection register of offset value from DQS to DQ PHY DQ OFFSET 3 CR 0x240 RW PRESET N Selection register of offset value from DQS to DQ PHY DIS CALIB RST CR 0x244 RW PRESET Nl Calibration reset disabling register PHY DLL LOCK DIFF CR 0x248 RW PRESET_N Selects the maximum number of delay line taps PHY FIFO WE IN DELAY 1 CR 0x24C RW PRESET N Delay value for FIFO WE PHY FIFO WE IN DELAY 2 CR 0x250 RW PRESET N Delay value for FIFO WE PHY FIFO WE IN DELAY 3 CR 0x254 RW PRESET N Delay value for FIFO WE PHY FIFO WE IN FORCE CR 0x258 RW PRESET Nl Overwriting delay value selection reg for FIFO WE PHY FIFO WE SLAVE RATIO 1 CR 0x25C RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 2 CR 0x260 RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 3 CR 0x264 RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 4 CR 0x268 RW PRESET N Ratio value for FIFO WE slave DLL PHY GATELVL INIT MODE CR 0x26C RW PRESET_N Init ratio selection register 104 Revision 2 IX Microsemi Smart
129. WRLVL_INIT_RATIO PORT 0 Selects a starting ratio value based on write leveling of previous data slice PHY_WRLVL_INIT_RATIO_CR Table 1 165 PHY WRLVL INIT RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 15 0 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM PHY_WRLVL_INIT_RATIO_2_CR Table 1 166 PHY WRLVL INIT RATIO 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 31 16 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew be
130. _RAS_N MDDR_RESET_N MDDR_WE_N MDDR_ADDR 15 0 MDDR BA 2 0 MDDR_DQ 15 8 f DQ 7 01 MT41J512M8RA MDDR DQ 23 16 _ _ _ _ DQ 7 0 MT41J512M8RA MDDR DQ 31 24 lt lt DQ 7 0 MT41J512M8RA MDDR_DM_RDQS _ECC lt AAANYN AAA om MDDR_DQS_ECC a ir tps Figure 1 27 x8 DDR3 SDRAM Connection to MDDR 52 MDDR_DM_RDQS 0 lt lt DM MDDR_DQS_ECC_N e Dast MDDR_DQ_ECC 3 0 CASN CKE CLK_P CLK_N CSN ODT RASN RSTN WEN ADDR 15 0 BA 2 0 MT41J512M8RA DQ 3 0 mMT41J512M8RA Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Example 3 Connecting 16 Bit LPDDR to MDDR_PADs with SECDED Figure 1 28 shows LPDDR1 SDRAM connected to the MDDR of a SmartFusion2 device The micron s MT46H32M16LF is a 64 MB density device with x16 data width The MDDR is configured in full bus width mode with SECDED enabled The SDRAM connected to MDDR DQ ECC 1 0 is used to store SECDED bits The total amount of LPDDR1 memory excluding memory for SECDED connected to MDDR is 64 MB MDDR PADS MT46H32M16LF MDDR CAS N CASN CKE CLK P CLK_N CSN aan Raen Ed SASN MDDR we N TITT WEN done anonn oI ADORNA MDDR BA 1 0 SSS FLERE BA 2 0 MDDR DM RDQS 1 0 UDM LDM MDDR DQS 0 EHEHE LDQS MDDR DQS 1 UDQS MDDR DQ 15 0 DQ 15 0 MDDR DM RDQS ECC MDDR DQS ECC MDDR DQ ECC 1 0 MT46H32M16LF CASN CKE CLK P
131. _SLAVE_RATIO 0x0 15 0 bits of REG_PHY_FIFO_WE_SLAVE_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY FIFO WE SLAVE RATIO 2 CR Table 1 130 PHY FIFO WE SLAVE RATIO 2 CR Bit Name Reset Description Number Value 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 31 16 bits of REG_PHY_FIFO_WE_SLAVE_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY FIFO WE SLAVE RATIO 3 CR Table 1 131 PHY FIFO WE SLAVE RATIO 3 CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 47 32 bits of REG PHY FIFO WE SLAVE RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc 116 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_FIFO_WE_SLAVE_RATIO_4_CR Table 1 132 PHY_FIFO_WE_SLAVE_RATIO 4 CR Bit Reset Number Name Value Description 31 7 Reserved 0x0
132. abric master through DDR FIC can be programmed to have a higher priority by configuring the PRIORITY_ID and PRIORITY ENABLE BIT bit fields in the DDRC AXI FABRIC PRI ID CR register Transaction Handler The transaction handler converts AXI transactions into DDR controller commands The transaction handler works on one transaction at a time from the read write port queue that is selected by the priority block The transaction handler has a write command controller and read command controller for write and read transactions The write command controller fetches the command from the AXI slave write port and sends a pure write instruction to the DDR controller If SECDED is enabled a read modified write RMW instruction is sent to the DDR controller The read command controller generates read transactions to the DDR controller Reorder Buffer The reorder buffer receives data from the DDR controller and orders the data as requested by the AXI master when a single AXI transaction is split into multiple DDR controller transactions depending on the transfer size DDR Controller The DDR controller receives requests from the AXI transaction controller performs the address mapping from system addresses to DRAM addresses rank bank row and column and prioritizes requests to minimize the latency of reads especially high priority reads and maximize page hits It also ensures that DRAM is properly initialized all requests are made to DRAM legally ac
133. aces User s Guide DDRC LCE SYNDROME 4 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 63 48 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CRis written over by the system Revision 2 99 lt gt Microsemi MDDR Subsystem DDRC LCE SYNDROME 5 SR Table 1 95 DDRC LCE SYNDROME 5 SR Bit Reset Number Name Value Description 16 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be p
134. action 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error MDDR SMC AXI M RDATA 63 0 Input Indicates read data Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 4 2 e SMC FIC 32 bit AHB Lite Port List Signal Direction Polarity Description MDDR_SMC_AHB_M_HMASTLOCK Output High Indicates that the current master is performing a locked sequence of transfers MDDR_SMC_AHB_M_HWRITE Output High Indicates write control signal When High this signal indicates a write transfer and when Low a read transfer MDDR_SMC_AHB_M_HRESP Input High The transfer response indicates the status of transfer MDDR_SMC_AHB_M_HREADY Input High When High the signal indicates that a transfer has been completed on the bus This signal may be driven Low to extend a transfer MDDR SMC AHB M HBURST 1 0 Output Indicates the burst type MDDR SMC AHB M HTRANS 1 0 Output Indicates the type of the current transfer 00 Idle 01 Busy 10 Non sequential 11 Sequential MDDR SMC AHB M HSIZE 1 0 Output Indicates the size of the transfer 00 Byte 01 Half word 10 Word MDDR SMC AHB M HWDATA 31 0 Output The write data bus is used to transfer data during write operations MDDR SMC AHB M HADDR 31 0 Output Indicates address bus MDDR SMC AHB M HRDATA 31 0 Input The read data bus is used to transfer data from bus slaves to
135. ad Buffer 7 HPOMA Master Enable Write Combining Buffer Enable Read Buffer SWITCH Master Enable Write Combining Buffer Enable Read Buffer IDC Master Enable Read Buffer 7 DOR Burst Size for Read Write Buffers 32 Bytes rm fr E Configuring MSS DDR Bridge for Use Model 1 Use Model 2 Selecting Non Bufferable Region This use model shows the use of the non bufferable region selection in the DDR bridge The buffering creates more latency in the applications which access non continuous memory locations In such cases non bufferable region selection provides high throughput than bufferable For example when Cortex M3 processor fetches the data from data region that is stack and the application has bulk data transactions then keeping the data region as bufferable and code region as non bufferable is preferred In this use model the application uses only 256 MB of memory segment 0xB000_0000 to OXBFFF FFFF as non bufferable and the other memory region as bufferable Figure 3 7 on page 223 shows the selection of the non bufferable region Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide r FA Configuring DORS MSS_DDRB 0 0 500 Configuration Write Buffer Time Out Counter nx Non Bufferable Regon Size 25 MB Non Bufferable Region Address Upper 16 bits 0x8000 OS Master Enable Write Combining Buffer Enable Read Buffer HPOMA Master Enable Write Combining Buffe
136. ad modify write operation 0 PHY_RESET 0x0 A 1 in this register will bring the PHY out of reset This is dynamic and synchronized internally before giving to PHY PHY_LEVELLING_FAILURE_SR Table 1 178 PHY_LEVELLING_FAILURE_SR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 10 PHY_REG_RDLVL_INC_FAIL 0x0 Incremental read leveling fail status flag for each PHY data slice 1 Incremental read leveling test has failed 0 Incremental read leveling test has passed 9 5 PHY_REG_WRLVL_INC_FAIL 0x0 Incremental write leveling fail status flag for each PHY data slice 1 Incremental write leveling test has failed 0 Incremental write leveling test has passed 4 0 PHY_REG_GATELVL_INC_FAIL 0x0 Incremental gate leveling fail status flag for each PHY data slice 1 Incremental gate leveling test has failed 0 Incremental gate leveling test has passed PHY_BIST_ERROR_1_SR Table 1 179 PHY BIST ERROR 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
137. ady AXI S BID 3 0 Output Indicates response ID The identification tag of the write response AXI S BRESP 1 0 Output Indicates write response This signal indicates the status of the write transaction 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error AXI S BVALID Output High Indicates whether a valid write response is available 1 Write response available 0 Write response not available AXI S RDATA 63 0 Output Indicates read data AXI S RID 3 0 Output Read ID tag This signal is the ID tag of the read data group of signals AXI S RLAST Output High Indicates the last transfer in a read burst Revision 2 167 I Microsemi Fabric DDR Subsystem Table 2 5 FDDR AXI Slave Interface Signals continued Signal Name Direction Polarity Description AXI 8 RRESP 1 0 Output Indicates read response This signal indicates the status of the read transfer 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error AXI 8 RVALID Output Indicates whether the required read data is available and the read transfer can complete 1 Read data available 0 Read data not available AXI S WREADY Output High Indicates whether the slave can accept the write data 1 Slave ready 0 Slave not ready AXI 8 ARADDR 31 0 Input Indicates initial address of a read burst
138. ail soc_tech microsemi com or contact a local sales office Sales office listings can be found at www microsemi com soc company contact default aspx ITAR Technical Support 242 For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations ITAR contact us via soc_tech_itar microsemi com Alternatively within My Cases select Yes in the ITAR drop down list For a complete list of ITAR regulated Microsemi FPGAs visit the ITAR web page Revision 2 Microsemi Corporation NASDAQ MSCC offers a comprehensive portfolio of semiconductor solutions for aerospace defense and security enterprise and communications and industrial and alternative energy markets Products include high performance high reliability analog and RF devices mixed signal and RF integrated circuits customizable SoCs FPGAs and complete subsystems Microsemi is headquartered in Aliso Viejo Calif Learn more at Microsemi www microsemi com Microsemi Corporate Headquarters ee beeper tert ag USA 2013 Microsemi Corporation All rights reserved Microsemi and the Microsemi logo are trademarks of ithin the i i i i i i i Sales 1 949 380 6136 Microsemi Corporation All other trademarks and service marks are the property of their respective owners Fax 1 949 215 4996 50200330 2 4 13
139. ailable only if MDDR interface is configured for single or dual AHB mode For more details of AHB protocol refer to AMBA AHB v3 0 protocol specification Table 1 6 AHB Slave Interface Signals Signal Name Direction Polarity Description MDDR DDR AHBO S HREADYOUT Output High Indicates that a transfer has finished on the bus The signal is asserted Low to extend a transfer Input to Fabric master MDDR DDR AHBO S HRESP Output High Indicates AHB transfer response to Fabric master MDDR DDR AHBO S HRDATA 31 0 Output Indicates AHB read data to Fabric master MDDR DDR AHBO S HSEL Input High Indicates AHB slave select signal from Fabric master MDDR DDR AHBO S HADDR 31 0 Input Indicates AHB address initiated by Fabric master MDDR DDR AHBO S HBURST 2 0 Input Indicates AHB burst type from Fabric master MDDR DDR AHBO S HSIZE 1 0 Input Indicates AHB transfer size from Fabric master MDDR DDR AHBO S HTRANS 1 0 Input Indicates AHB transfer type from Fabric master Revision 2 17 lt gt Microsemi MDDR Subsystem Table 1 6 AHB Slave Interface Signals continued Signal Name Direction Polarity Description MDDR DDR AHBO S HMASTLOCK Input High Indicates AHB master lock signal from Fabric master MDDR DDR AHBO S HWRITE Input High Indicates AHB write control signal from Fabric master MDDR DDR AHBO S HREADY Input High Indicates that a transfer has finished on the bus Fabric master can
140. alue of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 15 0 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG_PHY_WR_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value 122 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY WR DQS SLAVE DELAY 2 CR Table 1 149 PHY WR DQS SLAVE DELAY 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 31 16 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG PHY WR DQS SLAVE FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY WR DQS SLAVE DELAY 3 CR Table 1 150 PHY WR DQS SLAVE DELAY 3 CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG PHY WR DQS SLAVE FORCE is 1
141. ame Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 12 DDRC REG ECC BANK 0x0 Bank where the SECDED error occurred 11 0 DDRC_REG_ECC_COL 0x0 Column where the SECDED error occurred Col 0 is always set to 0 coming out of the controller This bit is overwritten by the register module and indicates whether the error came from upper or lower lane DDRC LCB NUMBER SR Table 1 98 DDRC LCB NUMBER SR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 0 DDRC_LCB_BIT_NUM 0x0 Indicates the location of the bit that caused a single bit error in SECDED case encoded value If more than one data lane has an error in it the lower data lane is selected This register is 7 bits wide in order to handle 72 bits of the data present in a single lane This does not indicate CORRECTED_BIT_NUM in the case of device correction SECDED The encoding is only present in designs that support SECDED DDRC_LCB_MASK_1_SR Table 1 99 DDRC LCB MASK 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 So
142. ands from the AXI transaction controller These commands are queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM constraints transaction priorities and dependencies between the transactions The DDR controller in turn issues commands to the PHY module which launches and captures data to and from the DDR SDRAM The DDR PHY converts the DDR controller commands into the actual timing relationships and DDR signaling necessary to communicate with the memory device The 16 bit APB configuration bus provides an interface for configuring the FDDR subsystem registers Port List Table 2 4 FDDR Subsystem Interface Signals Signal Name Type Polarity Description APB_S_PCLK In APB clock This clock drives all the registers of the APB interface APB_S_PRESET_N In Low APB reset signal This is an active low signal This drives the APB interface and is used to generate the soft reset for the DDR controller as well CORE_RESET_N In Low Global reset This resets the DDR_FIC DDRC PHY DDRAXI logic CLK_BASE In Base clock to the FDDR clock controller AXI S RMW In High AXI mode only Indicates whether all bytes of a 64 bit lane are valid for all beats of an AXI transfer 0 Indicates that all bytes in all beats are valid in the burst and the controller should default to write commands 1 Indicates that some bytes are invalid and the controller should default to R
143. ank address MDDR DM RDQS 3 0 In out DRAM data mask from bidirectional pads MDDR DQS 3 0 In out DRAM single ended data strobe output for bidirectional pads MDDR DGS N 3 0 In out DRAM single ended data strobe output for bidirectional pads MDDR DQ 31 0 In out DRAM data input output for bidirectional pads MDDR DQ ECC 3 0 In out DRAM data input output for SECDED MDDR DM RDQS ECC In out High DRAM single ended data strobe output for bidirectional pads MDDR DQS ECC In out High DRAM single ended data strobe output for bidirectional pads MDDR_DQS_ECC_N In out Low DRAM data input output for bidirectional pads MDDR DQS TMATCH 0 IN In High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH 0 OUT MDDR DQS TMATCH 1 IN In High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH 1 OUT MDDR DQS TMATCH 0 OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH 0 IN MDDR DQS TMATCH 1 OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH 1 IN MDDR DQS TMATCH ECC IN In High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH ECC OUT
144. ap boundary 11 Reserved MDDR DDR AXI S ARID 3 0 Input Indicates identification tag for the read address group of signals MDDR DDR AXI S ARLEN 3 0 Input Indicates burst length The burst length gives the exact number of transfers in a burst 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 16 Non AOUN A 2 O apwond o 14 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 5 AXI Slave Interface Signals continued Signal Name Direction Polarity Description MDDR_DDR_AXI_S_ARLOCK 1 0 Input Indicates lock type This signal provides additional information about the atomic characteristics of the read transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved MDDR_DDR_AXI_S_ARSIZE 1 0 Input Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 MDDR_DDR_AXI_S_ARVALID Input High Indicates the validity of read address and control information 1 Address and control information valid 0 Address and control information not valid MDDR_DDR_AXI_S_AWADDRJ 31 0 Input Indicates write address The write address bus gives the address of the first transfer in a write burst transaction MDDR DDR AXI S AWBURST 1 0 Input Indicates burst type The burst type coupled with the size inf
145. apping registers are listed below DDRC_ADDR_MAP_BANK_CR DDRC_ADDR_MAP_COL_1_CR DDRC ADDR MAP COL 2 CR DDRC ADDR MAP COL 3 CR DDRC ADDR MAP ROW 1 CR 6 DDRC ADDR MAP ROW 2 CR While configuring the registers ensure that two DDR memory address bits are not determined by the same source address bit Note 1 Some registers map multiple source address bits REG DDRC ADDRMAP ROW BO 11 2 To arrive at the right address for the DDR controller the system address or AXI address bits 4 0 are mapped by the FDDR In Full Bus Width mode the system address bits 4 0 are used to map the lower column address bits CO C1 C2 In Half Bus Width mode the system address bits 4 0 are used to map the lower column address bits CO C1 C2 C3 Example aR WN gt In this example the Address map registers are configured to access a 512 MB DDR3 SDRAM memory MT41J512M8RA from the FDDR subsystem The 512M x 8 bit DDR3 memory module has 3 bank address lines 16 rows and 10 columns The column address bits 3 to 9 are mapped for system address bit 5 to system address bit 11 To map the column 3 bit C3 to address 5 the field is configured to 3 as the base value is 2 Similarly the other column address bits are configured DDRC ADDR MAP COL 1 CR 0x3333 DDRC ADDR MAP COL 2 CR 0x3FFF DDRC ADDR MAP COL 3 CR 0x3300 The bank address bits 0 to 2 are mapped for system address bit 12 to system address bit 1
146. arter bus MDDR DQ ECC MDDR DQ ECC width mode 0 0 When the controller detects a correctable SECDED error it does the following e Generates an interrupt signal which can be monitored by reading the interrupt status register DDRC_ECC_INT_SR The ECCINT interrupt is mapped to the group0 interrupt signal MSS INT M2F 12 of the fabric interface interrupt controller FIIC Sends the corrected data to the read requested MSS FPGA fabric master as part of the read data Sends the SECDED error information to the DDRC_LCE_SYNDROME_1_SR register e Performs a read modify write operation to correct the data present in the DRAM When the controller detects an uncorrectable error it does the following Generates an interrupt signal which can be monitored by reading the interrupt status register DDRC ECC INT SR The ECCINT interrupt is mapped to the group0 interrupt signal MSS_INT_M2F 12 of the FIIC Sends the data with error to the read requested MSS FPGA fabric master as part of the read data Sends the SECDED error information to the DDRC_LUE_SYNDROME_1_SR register The following SECDED Registers can be monitored for identifying the exact location of an error in the DDR SDRAM 1 DDRC_LUE_ADDRESS_1_SR and DDRC LUE ADDRESS 2 SR give the row bank column information of the SECDED unrecoverable error 2 DDRC LCE ADDRESS 1 SR and DDRC LCE ADDRESS 2 SR give the row bank column information of the SECDED error correction 3 DDRC LCB NUMBE
147. atio is 4 1 100 CLK A CLK BASE REGEN ratio is 8 1 101 CLK A CLK BASE REGEN ratio is 16 1 110 CLK A CLK BASE REGEN ratio is 32 1 Other values Reserved 4 3 DIVISOR A 0x0 Selects the ratio between CLK_SRC and CLK_A which is an intermediate clock within the FACC 00 CLK_SRC CLK_A ratio is 1 1 01 CLK_SRC CLK_A ratio is 2 1 10 CLK_SRC CLK_A ratio is 3 1 11 Reserved 2 0 DDR_FIC_DIVISOR 0x0 Selects the ratio between CLK_A and CLK_DDR_FIC 000 CLK_A CLK_DDR_ FIC ratio is 1 1 001 CLK_A CLK_DDR_ FIC ratio is 2 1 010 CLK_A CLK DDR FIC ratio is 4 1 100 CLK_A CLK DDR FIC ratio is 8 1 101 CLK A CLK DDR FIC ratio is 16 1 110 CLK A CLK DDR FIC ratio is 32 1 Other values Reserved Revision 2 209 PLL DELAY LINE SEL Table 2 25 PLL DELAY LINE SEL Bit Number Name Reset Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 2 PLL_FB_DEL_SEL 0x0 Selects the delay values that are added to the FPLL feedback clock before being output to the FPLL 00 No buffer delay 01 One buffer delay 10 Two buffers delay 11 Three buffers delay 1 0 PLL_REF_DEL_SEL 0x0 Selects the delay values that are added to the FPLL reference clock before being output t
148. ation are available 1 Address and control information available 0 Address and control information not available 16 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 5 AXI Slave Interface Signals continued Signal Name Direction Polarity Description MDDR_DDR_AXI_S_BREADY Input High Indicates whether or not the master can accept the response information 1 Master ready 0 Master not ready MDDR_DDR_AXI_S_RREADY Input High Indicates whether or not the master can accept the read data and response information 1 Master ready 0 Master not ready MDDR DDR AXI S VWDATA 63 0 Input Indicates write data MDDR DDR AXI S WID 3 0 Input Indicates response ID The identification tag of the write response MDDR DDR AXI S WLAST Input High Indicates the last transfer in a write burst MDDR DDR AXI S WSTRB 7 0 Input Indicates which byte lanes to update in memory MDDR DDR AXI S WVALID Input High Indicates whether or not valid write data and strobes are available 1 Write data and strobes available 0 Write data and strobes not available MDDR DQS TMATCH ECC OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to MDDR DQS TMATCH ECC IN AHB Slave Interface Table 1 6 shows the MDDR AHB slave interface signals with their descriptions These signals will be av
149. ation for SmartFusion2 Devices M2S005 M2S010 MDDR Bus M2S025 VF400 M2S050 VF400 M2S080 M2S120 Width FG484 FG484 M2S050 FG896 M2S075 FG484 FC1152 36 bit Bank0 85 pins Bank2 85 pins 32 bit Bank0 76 pins Bank2 76 pins 18 bit Bank0 59 pins Bank0 59 pins Bank0 59 pins Bank0 59 pins Bank2 59 pins 16 bit Bank0 52 pins Banko 52 pins Bank0 52 pins Bank0 52 pins Bank2 52 pins 9 bit Banko 47 pins Bank2 47 pins 8 bit Bank0 41 pins Bank2 41 pins Functional Description This section provides the detailed description of the MDDR subsystem which contains the following sections Arch Architecture Overview Port List Initialization Details of Operation itecture Overview The functional block diagram of the MDDR subsystem is shown in Figure 1 2 The main components include the DDR fabric interface controller DDR FIC AXI transaction handler DDR memory controller and DDR PHY 64 Bit AXI Connected to MSS DDR Bridge 64 Bit AXI Single 32 Bit AHBL Dual 32 Bit AHBL Slave Interface 16 Bit APB Configuration B AXI Transaction DDR Controller Controller DDR FIC US Configuration Registers Figure 1 2 MDDR Subsystem Functional Block Diagram The DDR FIC facilitates communication between the FPGA fabric masters and AXI transaction controller The DDR FIC can be configured to provide either one 64 b
150. ations Register Freld Name Access 4 DDRC DYN SOFT RESET CR read wite REG DDRC SOFT RSTB read write RESET_APB_REG read wnite AXIRESET read write DORC DYN REFRESH 1 CR read write DORC OYN REFRESH 2 CR read write DORC DYN POWERDOWN CR read write DDRC_DYN_DEBUG_CR read write DORC MODE CR read write DDRC_ADOR_MAP_BANK_CR read write DORC_ECC_DATA_MASK_CR read write DORC ADOR MAP COL 1 CR read write DORC ADDR MAP COL 2 CR tead wnte DDRC ADDR MAP ROW 1 CR read write DORC_ADDR_MAP_ROW_2 CR DORC_INIT_1_CR d write DORC_CKE_RSTN_CYCLES_ CRI read write DDRC_CKE_RSTN_CYCLES_CR2 read write tead write read write read write read write 4 a tead write DORC_DRAM_RD_WR_LATENCY_CR read write DORC_DRAM_RD_WR_PRE_CR read write DORC DRAM MR TIMING PARAM CR read write DDRC_DRAM_RAS_TIMING_CR read write SESEESES REEERE DORC DORAM RD V R TRNARND TIME CR read write DORC_DRAM_T_PD_CR read write DDRC DRAM BANK ACT TIMING CR read wiite DDRC_OOT_PARAM_1_CR read write DORC OOT PARAM 2 CR read wnte b DDRC ADDR MAP COL 3 CR teadewerite Register Field Description DORC_DYN_SOFT_RESET_CR REG_DDRC_SOFT_RSTB This is a Soft Reset 0 Puts the Controller into reset 1 Takes the Controller out of Reset Controller shouid be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APS configurabon registers once the soft reset bit is asserted the APS register shouid be modified as requi
151. ave delay line Default value 0x40 PHY WR DQS SLAVE RATIO 2 CR Table 1 153 PHY WR DQS SLAVE RATIO 2 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 31 16 bits of REG_PHY_WR_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 124 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WR_DQS_SLAVE_RATIO_3_CR Table 1 154 PHY WR DQS SLAVE RATIO 3 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 47 32 bits of REG_PHY_WR_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by t
152. bebe de dd bh oie bie 161 Features ses cin bain ee tha a ads akkar fa kua aa Rae aes kg bas wea ude he badd ele harneed a 161 Memory Configurations e asas ea a i Were Soden tide apts Sed aa ratte ie palatine endive a a pe 162 Performance Lasqsaunm apene ease eo anaa T sk Gude opie det Ada keen a ads E eae ee Pace aa ack 163 VO UtlZ N ss sir ee See kreert 164 Functional DESenption cece eae aes sat Skred EG Soe Een ee a d d reke aed a dets 164 Architecture Overview La Lygra adie te otc ape ata ave sdee anda nade Auld dicate aude When Oho AAS a aa aT EES Gabba het bas bera 164 POF EIST isceguc arid antine cease E 20 today darn wed atomate hem Ladd aden duse od Fhe Rene ee ose bas ee Sates 165 Initialization wo6c teehee dled ee ds Pabedan ee dod hee a aed baad Pad ete eee eae mesken 172 Details of Operation asviartaversse ranet eet BA ceding E EETA E A deal Panic dtia b te sets Beene 175 How to Use the FDDR 222 sau asaeteeodd es Ak Seed Sig Skid he yaw eld eae Rate od ag 182 Design FIOW sierran Seu hostage as ere See ead heehee earl dw ah adhere etna team aN aoe 182 Use Model 1 Accessing FDDR from FPGA Fabric Through AXI Interface 0 eee 193 Use Model 2 Accessing FDDR from FPGA Fabric Through AHB Interface 0 0 eee 196 Revision 2 2 lt gt Microsemi Table of Contents DDR Memory Device Examples muses vag vakade a eii bk ka eee eed eee ee dae eee 201 FDDR Configuration Registers 1 0 ett 203 FDDR SYSREG Conf
153. ber Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_REG_STATUS_FIFO_WE_SLAV E_DLL_VALUE Delay value applied to FIFO WE slave DLL PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR Table 1 215 PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 44 32 bits of PHY_REG_STATUS_FIFO_WE_SLAV E_DLL_VALUE Delay value applied to FIFO WE slave DLL 148 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WR_DQS_SLAVE_DLL_VAL_1_SR Table 1 216 PHY WR DQS SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY REG STATUS WR DQS
154. bit should be preserved across a read modify write operation 3 0 REG_PHY_DLL_LOCK_DIFF 0x0 The maximum number of delay line taps variations allowed while maintaining the master DLL lock This is calculated as total jitter delay line tap size Where total jitter is half of incoming clock jitter pp delay line jitter pp PHY_FIFO_WE_IN_DELAY_1_CR Table 1 125 PHY_FIFO_WE_IN_DELAY_1_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY FIFO WE IN DELAY 0x0 15 0 bits of REG PHY FIFO WE IN DELAY Delay value to be used when REG PHY FIFO WE IN FORCEX is set to 1 114 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_FIFO_WE_IN_DELAY_2_CR Table 1 126 PHY FIFO WE IN DELAY 2 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY FIFO WE IN DELAY 0x0 31 16 bits of REG PHY FIFO WE IN DELAY Delay value to be used when REG PHY FIFO WE IN FORCEX is set t
155. can access slave slot 10 MO can access slave slot 12 MO can access slave slot 14 Select AXI channel ID width Figure 4 4 Core AXI Configuration 5 MO can access slave slot 1 MO can access slave slot 3 MO can access slave slot 5 MO can access slave slot 7 MO can access slave slot 9 MO can access slave slot 11 MO can access slave slot 13 MO can access slave slot 15 4 v Instantiate and configure CoreSDR AXI to match the external memory parameters 6 Connect the subsystem together as shown in Figure 4 5 on page 236 Connect the MSS SMC FIC master interface port MDDR SMC AXI MASTER to the CoreAXI bus mirrored master MO Connect the CoreAXI mirrored slave bus interface BIF port SO to the slave BIF port of the CoreSDR AXI core instance Revision 2 235 I Microsemi Soft Memory Controller Fabric Interface Controller SMC HC MSS 0 MCCC GK BASE MMUART 0 PADSE Figure 4 5 Subsystem Connections in SmartDesign pE IMMUART 0 PADS MSS SMC FIC master BIF to CoreAXI mirror master BIF connection CoreAXI mirrored slave BIF to CoreSDR AXI slave BIF connection DQ 15 0 amp 4 Refer to the Accessing External SDRAM through Fabric tutorial which describes the steps for creating a design that accesses external SDR memory from the Cortex M3 processor The tutorial also explains the steps for simulating the design in
156. ccess 11 Reserved AXI S AWSIZE 1 0 Input Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 AXI S AWVALID Input High Indicates whether valid write address and control information are available 1 Address and control information available 0 Address and control information not available AXI S BREADY Input High Indicates whether the master can accept the response information 1 Master ready 0 Master not ready AXI S RREADY Input High Indicates whether the master can accept the read data and response information 1 Master ready 0 Master not ready AXI S WDATA 63 0 Input Indicates write data 170 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 2 5 FDDR AXI Slave Interface Signals continued Signal Name Direction Polarity Description AXI 8 WID 3 0 Input Indicates response ID The identification tag of the write response AXI 8 WLAST Input High Indicates the last transfer in a write burst AXI S WSTRB 7 0 Input Indicates which byte lanes to update in memory AXI S WVALID Input High Indicates whether valid write data and strobes are available 1 Write data and strobes available 0 Write data and strobes not available AHB Slave Table 2 6 shows the FDDR AHB slave interface signals
157. cimal address The default address is 0xA000 If the non bufferable region size and address is left as default then the 64 KB memory from 0xA0000000 address to 0xA0010000 address will be non bufferable Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Enable or disable respective buffers allocated for each master The selection of disabling the write read buffer makes all transactions without buffering By default buffering is enabled DDR burst size for read write buffers The DDR bridge configurator allows to select the size of read write buffers as 32 bytes or 16 bytes I BR Configuring DORE MSS_DORB 0 0500 g ler et Configuration Write Buffer Time Out Counter OXF Non Buffer able Regon Suze 648 v Non Bufferable Region Address Upper 16 bits 0xA000 OS Master Enable Write Combining Buffer V Enable Read Buffer 17 HPOMA Master Enable Write Combining Buffer 7 Enable Read Buffer SWITCH Master Enable Write Combining Buffer 4 Enable Read Buffer IDC Master Enable Read Buffer 4 DOR Burst Size for Read Write Buffers 32 Bytes z EE C Gee K 4 Figure 3 5 Configuring MSS DDR Bridge MDDR FDDR DDR Bridge Configurations The DDR bridge in the MDDR or FDDR subsystem can be configured through the DDR_FIC registers shown in Table 3 3 on page 224 The possible configurations and corresponding registers are as follows Enable or disable the write and read buffers of
158. ck is 200 MHz The DDR FIC clock has to be driven from FPGA fabric The FPLL LOCK signal can be exposed to the FPGA fabric to monitor the health of the PLL loss of lock requires special handling by the application The interrupts in the FDDR subsystem can be exposed in SmartDesign by selecting the Enable Interrupts check box Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Edit Registers The configurator also has an option Edit Registers for configuring the FDDR subsystem registers to access external DDR memory The register values have to be calculated according to the application requirements and DDR memory specifications Refer to the FDDR Subsystem Features Configuration section on page 189 for the details of necessary register configurations for using the FDDR subsystem features The firmware generated by Libero SoC stores these configurations and the FDDR subsystem registers are initialized by the Cortex M3 processor during the Systemlnit phase of the firmware projects SoftConsole IAR Keil projects generated by Libero SoC Figure 2 10 shows the Registers Configuration window which enables configuration of the FDDR subsystem registers The register bit description is displayed at the bottom of the configurator on selection of the register bits The Actual Value field must be modified to suit the application The configurator also provides the option to import and export register configur
159. counting for associated DRAM constraints refreshes are inserted as required and the DRAM enters and exits various power saving modes appropriately Figure 2 6 shows the DDR controller connections in the FDDR subsystem AXI Transaction Interface Controller Control PHY DDR Controller Interface 16 Bit APB Training Register Interface Interface Figure 2 6 DDR Controller Block Diagram 178 Revision 2 3 Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide The following sections describe key functions of the DDR controller Address Mapping Read and write requests to the DDR controller requires a system address The controller is responsible for mapping this system address with rank bank row and column address to DRAM The address mapper maps linear request addresses to DDR memory addresses by selecting the source bit that maps to each and every applicable DDR memory address bit The address map interface registers can be configured to map source address bits to DRAM address for more information refer to Address Mapping section on page 191 on configuring the FDDR features Transaction Scheduling The DDR controller schedules the read and write transactions to DDR memory The DDR controller classifies the transactions into three types based on the commands from the AXI transaction controller e Low priority reads LPR High priority reads HPR Writes WR Each type of transaction has a queue
160. cted to the MDDR of a SmartFusion2 device Micron s MT47H64M16 is a 128 MB density device with x16 data width The MDDR is configured in full bus width mode and without SECDED The total amount of DDR2 memory connected to MDDR is 256 MB Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide MDDR_PADS MT47H64M16 MDDR_CAS_N MDDR CKE ee MDOR Gu MDDR CLK NER MDDR ODT LT MDDR RAS N LT MDDR WENL TT TT MDDR ADDR 12 0 GE 1 VG ADDR 12 0 MDDR BA 2 0 Lu TT TT BA 2 0 MDDR DM RDQS 1 0 PIT TT TT DM MDDR DQS 1 0 EO UDQS LDQS MDDR DQS N 1 0 Eee ep UDQS LDQS MDDR_DQ 15 0 fase sees DQ 15 0 MDDR DM RDQS 3 2 MDDR DQS 3 2 MDDR DQS N 3 2 MDDR DQ 31 16 MT47H64M16 CASN CKE CLK P CLK N CSN ODT RASN WEN ADDR 12 0 BA 2 0 DM UDQS LDQS UDQS LDQS DQ 15 0 Figure 1 26 x16 DDR2 SDRAM Connected to MDDR Revision 2 51 CI Microsemi MDDR Subsystem Example 2 Connecting 32 Bit DDR3 to MDDR PADs with SECDED Figure 1 27 shows DDR3 SDRAM connected to the MDDR of a SmartFusion2 device Micron s MT41J512M8RA is a 512 MB density device with x8 data width The MDDR is configured in full bus width mode with SECDED enabled The SDRAM connected to MDDR DQ ECC 3 0 is used to store SECDED bits The total amount of DDR3 memory excluding memory for SECDED connected to MDDR is 2 GB MDDR PADS MDDR CAS N MDDR CKE MDDR CLK MDDR_CLK_N MDDR_CS_N MDDR_ODT MDDR
161. ction controller receives 64 bit AXI transactions from various masters MSS DDR bridge and DDR FIC and translates them into DDR controller transactions Figure 1 5 shows the block diagram of the AXI transaction controller interfaced with the DDR controller The AXI transaction controller performs arbitration of the read write requests initiated by AXI compliant masters AXI Transaction Controller Transaction Handler AXI Slave endt DDR Re Order Buffer 64 Bit AXI Bus from DDR FIC Figure 1 5 AXI Transaction Controller Block Diagram The AXI transaction controller comprises four major blocks 1 AXI slave interface 2 Priority block 3 Transaction handler 4 Reorder buffer AXI Slave Interfaces The AXI transaction controller has two 64 bit AXI slave interfaces one from the MSS DDR bridge and the other from DDR FIC Each of the AXI slave ports is 64 bits wide and is in compliance with the standard AXI protocol Each transaction has an ID related to the master interface Transactions with the same ID are completed in order while the transactions with different read IDs can be completed in any order depending on when the instruction is executed by the DDR controller If a master requires ordering between transactions the same ID should be used The AXI slave interface has individual read and write ports The read port queues read AXI transactions and it can hold up to four read transactions The write port handles onl
162. d LPDDR1 Configurations Memory Width in SECDED SmartFusion2 Devices Density Width Mode M2S050 FG896 M2S080 M2S120 FC1152 128M x32 x36 y v x16 x18 v v x8 x9 v 256M x32 x36 Vv v x16 x18 v v x8 x9 v 512M x32 x36 Vv v x16 x18 v v x8 x9 v 1G x32 x36 Vv v x16 x18 v v x8 x9 v 2G x32 x36 v v x16 x18 v v x8 x9 v 4G x32 x36 x16 x18 x8 x9 v Performance Table 2 2 shows the maximum and minimum data rates supported by the FDDR subsystem for supported memory types Table 2 2 e DDR Speeds Memory Type Maximum Data Rate Mbps LPDDR1 400 Mbps 200 MHz DDR2 667 Mbps 333 MHz DDR3 667 Mbps 333 MHz Revision 2 163 I Microsemi Fabric DDR Subsystem I O Utilization Table 2 3 shows the I O utilization for SmartFusion2 devices corresponding to supported bus widths The remaining I Os in bank 0 can be used for general purposes Table 2 3 I O Utilization for SmartFusion2 Devices FDDR Bus Width M2S050 FG896 M2S080 M2S120 FC1152 36 bit Bank5 85 pins Bank1 85 pins 32 bit Bank5 76 pins Bank1 76 pins 18 bit Bank5 59 pins Bank1 59 pins 16 bit Bank5 52 pins Bank1 52 pins 9 bit Bank1 47 pins 8 bit Bank1 41 pins Functional Description This section provides a detailed description of the FDDR subsystem in the following sections e Architecture Ov
163. d bit should be preserved across a read modify write operation 8 DDR_FIC_LTO_CLR 0x0 Clear signal to lock timeout interrupt 7 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M2_WR_ERCLR 0x0 Clear bit for error status of AHBL master2 write buffer Once it goes High error status is cleared 3 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M1_WR_ERCLR 0x0 Clear bit for error status posted by AHBL master1 write buffer Once it goes High error status is cleared Table 1 227 DDR FIC ERR INT ENABLE DDR FIC ERR INT ENABLE Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 SYR_SW_WR_ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes Low when processor serves interrupt and makes clear bit for AHBL master1 0 SYR HPD WR ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes
164. drive this signal Low to extend a transfer MDDR DDR AHBO S HWDATA 31 0 Input Indicates AHB write data from Fabric master Table 1 7 shows the MDDR AHB slave interface signals with their descriptions These signals will be available only if MDDR interface is configured for dual AHB mode Table 1 7 e MDDR AHB Slave Interface Signals Signal Name Direction Polarity Description MDDR DDR AHB1 S HREADYOUT Output High Indicates that a transfer has finished on the bus The signal is asserted Low to extend a transfer Input to Fabric master MDDR DDR AHB1 S HRESP Output High Indicates AHB transfer response to Fabric master MDDR DDR AHB1 S HRDATA 31 0 Output Indicates AHB read data to Fabric master MDDR DDR AHB1 S HSEL Input High Indicates AHB slave select signal from Fabric master MDDR DDR AHB1 S HADDR 31 0 Input Indicates AHB address initiated by Fabric master MDDR DDR AHB1 S HBURST 2 0 Input Indicates AHB burst type from Fabric master MDDR DDR AHB1 S HSIZE 1 0 Input Indicates AHB transfer size from Fabric master MDDR DDR AHB1 S HTRANS 1 0 Input Indicates AHB transfer type from Fabric master MDDR DDR AHB1 S HMASTLOCK Input High Indicates AHB master lock signal from Fabric master MDDR DDR AHB1 S HWRITE Input High Indicates AHB write control signal from Fabric master MDDR DDR AHB1 S HREADY Input High Indicates that a transfer has finished on the bus Fabric master
165. e DRAM can be used in 1T or 2T Timing mode by configuring the DDRC PERF PARAM 3 CR register ODT Controls The ODT for a specific rank of memory can be enabled or disabled by configuring the DDRC_ODT_PARAM_1_CR and DDRC_ODT_PARAM_2_CR registers These must be configured before taking the controller out of soft reset They are applied to every read or write issued by the controller Soft Resets Set the REG DDRC SOFT RSTB bit of DDRC DYN SOFT RESET CR to 0 to reset the DDR controller To release the DDR controller from reset set the REG DDRC SOFT RSTB bit of DDRC DYN SOFT RESET ALIAS CRto 1 Use Model 1 Accessing FDDR from FPGA Fabric Through AXI Interface The AXI master in the FPGA fabric can accesses the DDR memory through the FDDR subsystem as shown in Figure 2 13 on page 194 The FDDR registers are configured from FPGA fabric through the APB interface The APB master in the FPGA fabric asserts a ready signal to the AXI master indicating successful initialization of the DDR memory Revision 2 193 I Microsemi Fabric DDR Subsystem Read write and read modify write transactions are initiated by the AXI master to read or write the data into the DDR memory after receiving a ready signal from the APB master FPGA Fabric AXI Master APB Master User Logic Logic APB S PCLK APB S PRESET N AXI S RMW CORE RESET N CLK BASE FAB PLL LOCK FDDR SmartFusion2 Figure 2 13 FDDR with AXI Interface Use the following step
166. e impact of a forced refresh cycle It can be programmed to burst the maximum number of refreshes allowed for DDR REFRESH_BURST 7 for performing 8 refreshes at a time to minimize the bandwidth lost when refreshing the pages The controller takes the DDR memory out of Self refresh mode whenever the REG_DDRC_SELFREF_EN input is deasserted or new commands are received by the controller Deep Power Down This is supported only for LPDDR1 The DDR controller puts the DDR SDRAM devices in Deep Power down mode whenever the REG_DDRC_DEEPPOWERDOWN_EN bit is set and no reads or writes are pending in the DDR controller The DDR controller automatically exits Deep Power down mode and reruns the initialization sequence when the REG_DDRC_DEEPPOWERDOWN_EN bit is reset to 0 The contents of DDR memory may be lost upon entry into Deep Power down mode DRAM Initialization After Reset the DDR controller initializes DDR memories through an initialization sequence depending on the type of DDR memory used For more information on the initialization process refer to the JEDEC specification Revision 2 lt 2 Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR PHY SmartFusion2 devices have a built in hardened DDR PHY block for interfacing with external DDR memories The DDR PHY processes read and write requests from the DDR controller and translates them into specific signals within the timing constraints of the target DDR mem
167. e preserved across a read modify write operation module inside the PHY_CTRL Master DLL Bit 9 Fine delay line lock status 1 Locked 0 Unlocked Bit 10 Coarse delay line lock status 1 Locked 0 Unlocked 8 0 PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE 0x0 The coarse and fine values going into the output filter in the PHY CTRL master DLL 1 0 Fine value 8 2 Coarse value Revision 2 145 lt gt Microsemi MDDR Subsystem PHY_RD_DQS_SLAVE_DLL_VAL_1_SR Table 1 207 PHY RD DQS SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE OxO 15 0 bits of PHY STATUS RD DQS SLAVE DLL VALUE Delay value applied to read DQS slave DLL PHY RD DQS SLAVE DLL VAL 2 SR Table 1 208 PHY RD DQS SLAVE DLL VAL 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_RD_DQS_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_STATUS_RD_DQS_SLAVE_D LL_VALUE De
168. ee Saati fa Se nie ale gate el igen wea Gane agen ater ema aker dere 225 TErMINGIOGY Limet ewww ododandevdeAdudase chooe ee doe ge heh bewbentee hese ade oh bbe ede a bh et 225 4 Soft Memory Controller Fabric Interface Controller 0 0 000 eee 227 Introduction sie seie pen hehe Ge ae bande baetaeehladreeeeeden eed ear ledavia crbiowtaves 227 Functional DESC tony ins attneessnkem kes ser b let Gia doe D Peake eee a eee Pee Pere bee 228 POM EISE cinere tedden ada tek oes datakurs cote sea Se Ea ee eae ees Eee saa ae be geo eee oe 228 How to Use SMC_FIC hakk ded pee pee ee pe Eke Eie Ele pe Ee Eee Pe Be Ee 233 Design FIOW ai eshedslev rates keel ope stue am Espe k r sakke ke Era oe Med ke ae ae ee Eo ga ee 233 Use Model 1 Accessing SDRAM from MSS Through CoreSDR AXI aavvavnne varene ravnene rare 234 SYSREG Control Register for SMC FIC 1 2 neta 236 GlOSSAN aud SS ah rw etd ad ae Se oe des sd ariske eee ae Grener at 237 ACronyms ost g vsbnssdtaudssdLr sa keesevese at are hanske endovadestrr same fed sant thy ook hilse 237 Ay ister Cnanges uaLsd vadaska naa b e 6gecsakes E EE INE dane ga sanke d 239 B Product SUP POR ara raa idea eed Bia ides lech Hae aca Gud aed MR ea Dean STG 241 Customer Service nse oie dba isi psi eide fekk eek ea ees Sg eae Re bod kile ware edit are ewe A 241 Customer Technical Support Center 0 0 teeta 241 Technical Support sieis ranri Save a Ave roee ks tee eS aback ad sedate Shares Aske Fede
169. elects the address bits used as row address bits 2 to 11 Valid Range 0 to 11 Internal Base 8 for row address bit 2 9 for row address bit 3 10 for row address bit 4 15 for row address bit 9 16 for row address bit 10 17 for row address bit 11 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 3 0 REG_DDRC_ADDRMAP_ROW_B12 0x0 Selects the address bit used as row address bit 12 Valid Range 0 to 11 and 15 Internal Base 18 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 12 is set to 0 Revision 2 65 lt gt Microsemi MDDR Subsystem DDRC_ADDR_MAP_ROW_2_CR Table 1 36 DDRC ADDR MAP ROW 2 CR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 REG_DDRC_ADDRMAP_ROW_B13 0x0 Selects the address bits used as row address bit 13 Valid range 0 to 11 and 15 Internal base 19 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 13 is set to 0 7 4 REG_DDRC_ADDRMAP_ROW_B14 0x0 Selects the address bit used as row address bit 14
170. encies between DDR controller and DDR PHY can be configured Configure the DDRC DRAM RD WR LATENCY CR register for adding latencies for read and writes Performance The DDR controller has several performance registers which can be used to increase the speed of the read and write transactions to DDR memory The DDR controller has a transaction store shared for low and high priority transactions The DDRC_PERF_PARAM_1_CR register can be configured for allocating the transaction store between the low and high priority transactions For example if the REG DDRC LPR NUM ENTRIES field is configured to 0 the controller allocates more time to high priority transactions The ratio for LPR HPR is 1 7 as the transaction store depth is 8 Revision 2 39 lt gt Microsemi MDDR Subsystem 40 The DDRC HPR QUEUE PARAM 1 CR DDRC_LPR_QUEUE_PARAM_1_CR and DDRC WR QUEUE PARAM CR registers can be configured for the minimum clock values for treating the transactions in the HPR LPR and WR queue as critical and non critical To force all incoming transactions to low priority configure the DDRC PERF PARAM 2 CR register By default it is configured to force all the incoming transactions to low priority The DRAM can be used in 1T or 2T Timing mode by configuring the DDRC PERF PARAM 3 CR register ODT Controls The ODT for a specific rank of memory can be enabled or disabled by configuring the DDRC_ODT_PARAM_1_CR and DDRC_ODT_PARA
171. er configuring the FDDR registers from the APB master The AXI master clock frequency should be same as FDDR DDR_FIC clock frequency 5 Instantiate user APB master logic in the SmartDesign canvas to configure the FDDR registers through the APB interface 6 Connect the AXI master to the FDDR AXI slave interface Connect the APB master to the FDDR APB slave interface through CoreAPB 7 Make the other connections in the SmartDesign canvas as shown in Figure 2 16 SYSRESET_O DE RST N FOWER ON RESET NIR AXI Master 0 FA Figure 2 16 e SmartDesign Canvas Revision 2 195 amp Microsemi Fabric DDR Subsystem SmartFusion2 8 To verify the design in Libero SoC create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor Simulate the design and observe the AXI read and write transactions Note The FDDR subsystem can be configured using the Cortex M3 processor without having an APB master in the FPGA fabric In this case the MSS General Purpose Input Output GPIO can be used to indicate that the DDR memory has been successfully initialized Use Model 2 Accessing FDDR from FPGA Fabric Through AHB Interface This use model shows an example of accessing DDR memory through the FDDR subsystem from two AHB masters Figure 2 17 FIC 0 is used as AHB master 0 and user logic in the fabric is used as AHB master 1 The FDDR registers are config
172. er interface type clocking and DDR I O settings FDDR register initialization FDDR subsystem registers can be initialized using the ARM Cortex M3 processor or FPGA fabric master After MSS reset the FDDR registers have to be configured according to application and DDR memory specification The FDDR Subsystem Features Configuration section on page 189 provides the details of required register configuration for FDDR features While configuring the registers the soft reset to the DDR controller must be asserted After releasing the soft reset the DDR controller performs DDR memory initialization and sets the status bits in DDRC_SR Revision 2 amp Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide FDDRC Macro Configuration Libero Design Flow FIC_2 Configuration Configure DDR I O Settings in I O Editor for example ODT Drive Strength After FDDR Reset Set the Soft Reset Bit to 0 Configure the FDDR Registers Required Steps for FDDR Initialization Set the Soft Reset Bit to 1 2 mal Start Read Writes to DDR Memory Figure 2 8 Design Flow The configuration steps in the flow chart are explained in detail in the below sections Revision 2 183 I Microsemi Fabric DDR Subsystem FDDRC Macro Configuration The FDDRC macro in the Libero IP Catalog has to be instantiated in SmartDesign to access the external DDR memory through the FDDR subsystem The FDDRC macro confi
173. er1 and master2 DDR FIC HPD SW RW INVAL CR 0x410 RW PRESET N l Invalidates write buffer and read buffer for AHBL master1 and master2 DDR LOCK TIMEOUTVAL 1 CR 0x440 RW PRESET N Indicates maximum number of cycles a master can hold the bus for a locked transfer DDR LOCK TIMEOUTVAL 2 CR 0x444 RW PRESET N l Indicates maximum number of cycles a master can hold the bus for a locked transfer 224 Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Glossary Acronyms DDR Double data rate RAC Read access controller SEU Single event upsets WAC Write access controller WCB Write combining buffer Terminology Flush Operation Writing the data in the Write combining buffer into DDR memory Non bufferable Address The address is within the range of defined non bufferable region TAG Region It is the range of bufferable data for write read transactions from the address of initial transaction Revision 2 225 lt gt Microsemi 4 Soft Memory Controller Fabric Interface Controller Introduction The SmartFusion2 soft memory controller fabric interface controller SMC_FIC is used to access external bulk memories other than DDR through the FPGA fabric The SMC_FIC can be used with a soft memory controller for the MSS to access memories such as SDRAM flash and SRAM MSS masters communicate with the SMC_FIC through an MSS DDR bridge present in the MSS
174. erved bit should be preserved across a read modify write operation 7 0 DDRC_REG_ECC_SYNDROMES 0x0 71 64 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system DDRC_LUE_ADDRESS_1_SR Table 1 89 DDRC LUE ADDRESS 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_ROW 0x0 Row where the SECDED error occurred Only present in designs that support SECDED Revision 2 95 lt gt Microsemi MDDR Subsystem DDRC_LUE_ADDRESS_2_SR Table 1 90 DDRC LUE ADDRESS 2 SR
175. erview e Port List e Initialization e Details of Operation Architecture Overview A functional block diagram of the FDDR subsystem is shown in Figure 2 2 The main components include the DDR fabric interface controller DDR FIC AXI transaction handler DDR memory controller and DDR PHY CLK_BASE Clock FDDR_CLK FPLL_LOCK ontroller Poe DDR FIC Transaction DDR Controller PHY Controller CLK BASE PLL LOCK CORE RESET N 64 Bit AXI Single 32 Bit AHBL Dual 32 Bit AHBL Slave Interface 64 Bit APB Configuration Bus Configuration Registers Figure 2 2 FDDR Subsystem Functional Block Diagram The FDDR subsystem has a dedicated clock controller for generating clocks to the components of FDDR from the base clock CLK_BASE The CLK_BASE for the FDDR originates from a fabric CCC or an external source through the FPGA fabric The DDR FIC facilitates communication between the FPGA fabric masters and AXI transaction controller The DDR_FIC can be configured to provide either one 64 bit AXI slave interface or two independent 32 bit AHB Lite AHBL slave interfaces to the FPGA fabric masters 164 Revision 2 3 Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide The AXI transaction controller receives read and write requests from AXI masters DDR FIC and schedules for the DDR controller by translating them into DDR controller commands The DDR controller receives the comm
176. es to read and write data The master DLL measures the cycle period in terms of a number of taps and passes this number through the ratio logic to the slave DLLs The Rank Tracker returns the rank number when the PHY gets a read write request at the read write interface The training logic in the PHY determines the correct delay programming for the read data DQS and write DQS signals The training logic adjusts the delays and evaluates the results to locate the appropriate edges The DDR controller assists by enabling and disabling the leveling logic in the DDR memories and the PHY by generating the necessary read commands or write strobes The PHY informs the DDR controller when it has completed training which triggers the DDRC to stop generating commands and to return to normal operation How to Use the MDDR 28 This section describes how to use the MDDR subsystem in the design It contains the following sections Design Flow e Use Model 1 Accessing MDDR from FPGA Fabric Through the AXI Interface e Use Model 2 Accessing MDDR from FPGA Fabric Through the AHB Interface e Use Model 3 Accessing MDDR from Cortex M3 Processor Use Model 4 Accessing MDDR from the HPDMA DDR Memory Device Examples Design Flow The flow chart Figure 1 8 on page 29 illustrates the design flow for using the MDDR subsystem to access external DDR memory The design flow consists of two parts 1 Libero SoC flow This includes configuring the type
177. etting this port as 0 will stop the BIST generator checker In order to run BIST tests this port must be set along with REG_PHY_LOOPBACK 2 1 REG PHY BIST MODE 0x0 The mode bits select the pattern type generated by the BIST generator All the patterns are transmitted continuously once enabled 00 Constant pattern 0 repeated on each DQ bit 01 Low frequency pattern 00001111 repeated on each DQ bit 10 PRBS pattern 247 1 PRBS pattern repeated on each DQ bit Each DQ bit always has same data value except when early shifting in PRBS mode is requested REG PHY BIST FORCE ERR 0x0 This register bit is used to check that the BIST checker is not giving a false pass When this port is set to 1 the data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error Table 1 107 PHY DYN BIST TEST ERRCLR 1 CR PHY DYN BIST TEST ERRCLR 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_ERR_CLR 0x0 15 0 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect 108 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA
178. f a read burst transaction 230 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 4 1 e SMC FIC 64 bit AXI Port List continued Signal Direction Polarity Description MDDR SMC AXI M ARLEN 3 0 Output Indicates burst length The burst length gives the exact number of transfers in a burst 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 oND AUN MDDR SMC AXI M ARSIZE 1 0 Output Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 MDDR SMC AXI M ARBURST 1 0 Output Indicates burst type The burst type coupled with the size information provides details on how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved MDDR_SMC_AXI_M_AWADDR 31 0 Output Indicates write address The write address bus gives the address of the first transfer in a write burst transaction MDDR SMC AXI M AWSIZE 1 0 Output Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 MDDR SMC AXI M AWL
179. ftware should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 15 0 bits of DDRC_LCB_MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC REG ECC CORRECTED ERR is High This mask doesn t indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane Revision 2 101 lt gt Microsemi MDDR Subsystem DDRC_LCB_MASK_2_SR Table 1 100 DDRC_LCB_MASK_2_SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 31 16 bits of DDRC LCB MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC REG ECC CORRECTED ERR is High This mask does not indicate a
180. gurator shown in Figure 2 9 enables configuration of the FDDR subsystem E Fabric External Memory DDR Controller Configurator o mis Configuration Memory Configuration Type DDR2 width 32 ecc no Memory Access FPGA Fabric Interface Using an AXI 64 Interface X FDDR_CLK Frequency MHz 100 DDR FIC CLK_BASE Divisor 1 v 100 MHz FPLL Configuration Supply Voltage 2 5V Use FAB PLL LOCK Interrupts Enable Interrupts Edit Registers _ Hep ov ama Cancel Figure 2 9 Fabric External Memory DDR Controller Configurator 184 Depending on the application requirement select the memory Type as DDR2 DDR3 or LPDDR The Width of the memory can be selected as 32 bit 16 bit or 8 bit and the ECC SECDED can be enabled or disabled Select FPGA Fabric Interface type as AXI single AHBLite or two AHBLite On completion of the configuration the selected interface is exposed in SmartDesign User logic in the FPGA fabric can access DDR memory through the FDDR using these interfaces Clock Configuration The FDDR subsystem operates on FDDR CLK frequency which can be configured up to 333 MHz The DDR FIC clock CLK_BASE drives the DDR FIC slave interface and defines the frequency at which the FPGA fabric subsystem connected to this interface is intended to run DDR FIC clock can be configured as a ratio 1 2 3 4 6 8 12 or 16 of FDDR CLK The maximum frequency of DDR FIC clo
181. he shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DQS_SLAVE_RATIO_4_CR Table 1 155 PHY WR DQS SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 49 48 bits of REG_PHY_WR_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DATA_SLAVE_DELAY_1_CR Table 1 156 PHY_WR_DATA_SLAVE_DELAY_1_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 15 0 bits of REG PHY WR DATA SLAVE DELAY If REG PHY WR DATA SLAVE FORCE
182. high priority transaction store Note In designs with ECC number of lpr and wr credits issued to the core is 1 less than the non ECC case 1 entry each is reserved in wr and lpr cam for storing the RMW requests arising out of Single bit Error Correction RMW operation DDRC_HPR_QUEUE_PARAM_1_CR Table 1 64 e DDRC HPR QUEUE PARAM 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 REG DDRC HPR MAX STARVE X32 0x0 Lower 1 bit of REG DDRC HPR MAX STARVE X32 Number of clocks that the HPR queue can be starved before it goes critical Unit 32 clocks 14 4 REG_DDRC_HPR_MIN_NON_CRITICAL 0x0 Number of clocks that the HPR queue is guaranteed to be non critical Unit 32 clocks 3 0 REG DDRC HPR XACT RUN LENGTH 0x0 Number of transactions that are serviced once the HPR queue goes critical is the smaller of this value and number of transactions available Units Transactions Revision 2 81 lt gt Microsemi MDDR Subsystem DDRC_HPR_QUEUE_PARAM_2_CR Table 1 65 DDRC HPR QUEUE PARAM 2 CR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with fut
183. higher priority over other IDs Revision 2 89 lt gt Microsemi MDDR Subsystem DDRC_SR Table 1 81 DDRC SR Bit Reset Number Name Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 3 DDRC CORE REG OPERATING MODE 0x0 Operating mode This is 3 bits wide in designs with mobile support and 2 bits in all other designs Non mobile designs 000 Init 001 Normal 010 Power down 011 Self Refresh Mobile designs 000 Init 001 Normal 010 Power down 011 Self refresh 1XX Deep power down 2 DDRC_REG_TRDLVL_MAX_ERROR 0x0 Single pulse output 1 indicates the RDRLVL_MAX timer has timed out 1 DDRC_REG_TWRLVL_MAX_ERROR 0x0 Single pulse output 1 indicates the WRLVL MAX timer has timed out 0 DDRC REG MR WR BUSY 0x0 1 Indicates that a mode register write operation is in progress 0 Indicates that the core can initiate a mode register write operation Core must initiate an MR write operation only if this signal is Low This signal goes High in the clock after the controller accepts the write request It goes Low when the MR write command is issued to the DRAM Any MR write command that is received when DDRC_REG_MR_WR_BUSY is High is not accepted Table 1 82 DDRC SINGLE ERR CNT STATUS SR D
184. i MDDR Subsystem Table 1 105 PHY Configuration Register Summary continued 106 Revision 2 Reset Register Name Offset Type Source Description PHY WRLVL INIT RATIO 1 CR Ox2EC RW PRESET Nl Configuring register for initialization ratio used by write leveling PHY WRLVL INIT RATIO 2 CR 0x2F0 RW PRESET Nl Configuring register for initialization ratio used by write leveling PHY WRLVL INIT RATIO 3 CR 0x2F4 RW PRESET Nl Configuring register for initialization ratio used by write leveling PHY WRLVL INIT RATIO 4 CR 0x2F8 RW PRESET Nl Configuring register for initialization ratio used by write leveling PHY WR RD RL CR Ox2FC RW PRESET NlIConfigurable register for delays to read and write PHY DYN RDC FIFO RST ERR CNT C R CR 0x300 RW PRESET_N Reset register for counter PHY RDC WE TO RE DELAY CR 0x304 RW PRESET N Configurable register for delay between WE and RE PHY USE FIXED RE CR 0x308 RW PRESET_N Selection register for generating read enable to FIFO PHY USE RANKO DELAYS CR 0x30C RW PRESET N Delay selection This applies to multi rank designs only PHY USE LVL TRNG LEVEL CTRL CR 0x310 RW PRESET N Training control register PHY DYN CONFIG CR 0x314 RW PRESET N PHY dynamically controlled register PHY RD WR GATE LVL CR 0x318 RW PRESET N Training mode selection register P
185. i ae FDDR_CLK CLK_P FDDR_CLK_N CLK_N po FDDR CS N H CSN FooR opr LG ODT roor Ras NTT TNT easy FDDR WEN Sd WEN FDDR ADDR12 0 l LET TT TT ADDR 12 0 FDDR Balzo LTTE BA 2 0 FDDR DM RDQS 1 0 ERR DM FDDR DQS 1 0 ptt TT TT UDQS LDQS FDDR DQS N 1 0 PPT TT TT UDQS LDQSH spe PORN DQN5 0 FDDR DQ 15 0 FDDR DM RDQS 3 2 FDDR DQS 3 2 FDDR DQS N 3 2 FDDR DQ 31 16 MT47H64M16 CASN CKE CLK P CLK_N CSN ODT RASN WEN ADDR 12 0 BA 2 0 DM UDQS LDQS UDQS LDQSH DQ 15 0 Figure 2 25 x16 DDR2 SDRAM Connected to FDDR Example 2 Connecting 32 Bit DDR3 to FDDR PADs with SECDED Figure 2 26 on page 202 shows DDR3 SDRAM connected to the FDDR of a SmartFusion2 device Micron s MT41J512M8RA is a 512 MB density device with x8 data width The FDDR is configured in Full Bus Width mode with SECDED enabled The SDRAM connected to FDDR DQ ECC 3 0 is used to store SECDED bits The total amount of DDR3 memory excluding memory for SECDED connected to FDDR is 2 GB Revision 2 201 I Microsemi Fabric DDR Subsystem FDDR PADS FDDR_CAS_N CASN FDDR_CKE CKE FDDR_CLK CLK_P FDDR_CLK_N CLK_N FDDR_CS_N CSN FDDR_ODT ODT FDDR_RAS_N RASN FDDR_RESET_N RSTN FDDR_WE_N WEN FDDR ADDR 15 0 ADDR 15 0 FDDR BA 2 0 FDDR DM RDQS 0 FDDR DQS 0 FDDR DQS N 0 FDDR DQ 7 0 MT41J512M8RA FDDR DM RDQS 1 FDDR DQS 1 FDDR DGQS N 1 FDDR DQ 15 8 MT41J512M8RA FDDR DM RDQS 2 FDDR_DQS 2
186. iguration Register Summary vvvuuavanvnvararr vever ranere narr rene 204 FDDR SYSREG Configuration Register Bit Definitions 0 0 renere renere rare 205 GIOSSAN ud Sa oe Sateen whe sei er Leal Peo rs AEE HEGER 214 AGCFONYIMS veastiaosaadder she h de dosnt tree oe eae Maidan Sheet ican be ated nd aar a Mba bead eee f des 214 Listof Changes s meea Gee heehee eee eee kg G RR Ce Ae ee ee a ee he eae ke 214 S DDR Bidge sva see NTS ee 215 Introduction SE EEE EE EEE RT ER 215 Functional Description 2s ke d eakagekteae Sale e Skien kal ed fasiten Bie Gas GASK KG Eb sklie Eek eked 216 Architecture OVERVIEW cei eoue eraa horse skrek GARE ket dokken Gaia ee Gnd LED age sk adr anse 216 Details or Operation ansa seier teee eap e yaa aie dd ske eine e ATE egge Seen e aa priate edged Sekken alr aen a E 217 Howto Use DDR Bridges 224 care wh knee se KNR eee See Fed aa klase kes Ne EED skaden 220 Design FIOW vasiyuasasaaridke verkene e sere oni ayo ef ete nad dine a aa EA EE Kindle ae det les sed fade ea ie wae 220 Use Model 1 High Speed Data Transactions from Cortex M3 Processor 000 cece eee eee eee eee 222 Use Model 2 Selecting Non Bufferable Region 0 000 222 SYSREG Control Registers 0 2 ete eae 223 DDR Bridge Control Registers in MDDR and FDDR 0 00 cece 224 GOSSEN aena tae ester oe Sie Go hee See ae e Se ee he SO Ee eared Cora hee ene eee 225 ACKONYMS eee ere arket das ease eb Sh
187. ining logic This mode can be enabled for incremental read and write leveling by configuring the PHY RD WR GATE LVL CR register This mode must be enabled only after initial training is completed The PHY generates a flag bit when incremental leveling fails indicating that the interval was too large The status of incremental training can be read in the PHY LEVELLING FAILURE SR register Details of Operation This section provides a functional description of each block in the MDDR subsystem DDR FIC Figure 1 4 on page 22 shows the DDR FIC block diagram Revision 2 21 I Microsemi MDDR Subsystem 64 Bit AXI Single p h DDR Bridge 32 Bit AHBL MUX g AXI Transaction Dual 32 Bit AHBL Controller Slave Interface AXI AXI Synchronous Bridge 16 Bit APB Configuration Configuration Bus Registers Figure 1 4 DDR FIC Block Diagram Fabric masters can access the MDDR subsystem in the following ways Single AXI 64 interface Single AHB 32 interface e Dual AHB 32 bit interfaces If the AX1 64 interface is selected the DDR FIC acts as an AXI to AXI synchronous bridge In this mode DDR_FIC provides FPGA fabric masters to access the MDDR subsystem through locked transactions For this purpose a user configurable 20 bit down counter keeps track of the duration of the locked transfer If the transfer is not completed before the down counter reaches zero a single clock cycle pulse interrupt is generated to the fabric interface
188. ion phase and this process starts with a reset sequence For DDR3 memories the initialization phase also includes ZQ calibration and DRAM training Reset Sequence Figure 1 3 on page 20 shows the reset sequence for MDDR subsystem from power on reset stage The MDDR subsystem comes out of reset after MPLL Lock is asserted by the MSSS CCC De assertion of MDDR AXI RESET N signifies the end of the reset sequence The MDDR reset can be generated by asserting MDDR CTLR SOFTRESET bit in SOFT RESET CR to 1 The DDR controller performs external DRAM memory reset and initialization as per the JEDEC specification including reset refresh and mode registers DDRIO Calibration Each DDRIO has an ODT feature which is calibrated depending on the DDR I O standard DDR I O calibration occurs after the DDR I Os are enabled If the impedance feature is enabled impedance can be programmed to the desired value in three ways e Calibrate the ODT driver impedance with a calibration block e Calibrate the ODT driver impedance with fixed calibration codes e Configure the ODT driver impedance to the desired value directly The system register MDDR_IO_CALIB_CR can be configured for changing the ODT value to the desired value For more information on DDR O calibration refer to the Configurable ODT and Driver Impedance section of the I O s chapter in the SmartFusion2 FPGA Fabric Architecture User s Guide Revision 2 19 I Microsemi MDDR Subsystem PO RES
189. ions The registers are categorized based on the controller blocks in the FDDR subsystem Table 2 17 lists the categories of registers and their offset addresses Table 2 17 Address Table for Register Interfaces Registers Address Offset Space DDR Controller Configuration Register 0x000 0x1FC PHY Configuration Register Summary 0x200 0x3FC DDR_FIC Configuration Register Summary 0x400 0x4FC Reserved 0x500 0x7FC Revision 2 203 I Microsemi Fabric DDR Subsystem FDDR SYSREG Configuration Register Summary Table 2 18 FDDR SYSREG Address Register Reset Register Name Offset Type Flash Source Description PLL CONFIG LOW 1 0x500 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of the MPLL PLL CONFIG LOW 2 0x504 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of the MPLL PLL CONFIG HIGH 0x508 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of the MPLL FDDR FACC CLK EN 0x50C RW P PRESETN Enables the clock to the DDR memory controller FDDR_FACC_MUX_CONFIG 0x510 RW P PRESETN Selects the standby glitchfree multiplexers within the fabric alignment clock controller FACC FDDR_FACC_DIVISOR_RATIO 0x514 RW P PRESETN Selects the ratio between CLK_A and CLK_DDR_FIC PLL_DELAY_LINE_SEL 0x518 RW P PRESETN Selects the delay values to be added
190. ions properly To enable the Read DQS gate training as part of the initialization sequence set the REG DDRC DFI RD DQS GATE LEVEL bit to 1 2 Data eye training The goal of data eye training is to identify the delay at which the read DQS rising edge aligns with the beginning and end transitions of the associated DQ data eye To enable the Read data eye training as part of the initialization sequence set the REG DDRC DFI RD DATA EYE TRAIN bit to 1 By identifying these delays the system can calculate the midpoint between the delays and accurately center the read DQS within the DQ data eye The DDR controller drives subsequent read transactions for every read to read delay specified by REG DDRC RDLVL RR until the PHY drives the response signal High The DDR controller performs the below steps 1 Sets up the DDR memory for read leveling mode by sending the appropriate MR3 command which forces the DDR memory to respond to read commands with a 1 0 1 0 1 pattern 2 Sets the relevant read leveling enable bit and sends out periodically timed read commands on the DDR memory command interface 3 Once the PHY completes its measurements it sets the read level response bits which then signal the DDR controller to stop the leveling process and lower the read leveling enable bit Incremental Training This is applicable for all DDR memories The PHY supports incremental training where the data path delays are incremented or decremented by 1 by the tra
191. is resets the DDR FIC DDRC PHY DDRAXI logic MDDR DDR AXI S RMW In High AXI mode only Indicates whether all bytes of a 64 bit lane are valid for all beats of an AXI transfer 0 Indicates that all bytes in all beats are valid in the burst and the controller should default to write commands 1 Indicates that some bytes are invalid and the controller should default to RMW commands This is classed as an AXI write address channel sideband signal and is valid with the AWVALID signal Bus Interfaces AXI SLAVE Bus AXI slave interface 1 0 bus AHBO SLAVE Bus AHBO slave interface 3 0 bus AHB1 SLAVE Bus AHB1 slave interface 3 0 bus APB SLAVE Bus APB slave interface 3 0 bus DRAM Interface MDDR_CAS_N Out Low DRAM CASN MDDR CKE Out High DRAM CKE MDDR CLK Out DRAM single ended clock for differential pads MDDR CLK N Out DRAM single ended clock for differential pads MDDR CS N Out Low DRAM CSN MDDR_ODT Out High DRAM ODT 0 Termination Off 1 Termination On MDDR_RAS_N Out Low DRAM RASN AXI or AHB interface depending on configuration Revision 2 11 lt gt Microsemi MDDR Subsystem Table 1 4 e MDDR Subsystem Interface Signals continued Signal Name Type Polarity Description MDDR RESET N Out Low DRAM reset for DDR3 MDDR WE N Out Low DRAM WEN MDDR_ADDR 15 0 Out Dram address bits MDDR BA 2 0 Out Dram b
192. is selected by the priority block The transaction handler has a write command controller and read command controller for write and read transactions The write command controller fetches the command from the AXI slave write port and sends a pure write instruction to the DDR controller If SECDED is enabled a read modified write RMW instruction is sent to the DDR controller The read command controller generates read transactions to the DDR controller Reorder Buffer The reorder buffer receives data from the DDR controller and orders the data as requested by the AXI master when a single AXI transaction is split into multiple DDR controller transactions depending on the transfer size DDR Controller The DDR controller receives requests from the AXI transaction controller performs the address mapping from system addresses to DRAM addresses rank bank row and column and prioritizes requests to minimize the latency of reads especially high priority reads and maximize page hits It also ensures that DRAM is properly initialized all requests are made to DRAM legally accounting for associated DRAM constraints refreshes are inserted as required and the DRAM enters and exits various power saving modes appropriately Figure 1 6 on page 25 shows the DDR controller connections in the MDDR subsystem 24 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide AXI Transaction Interface Controller
193. it AXI slave interface or two indepen The AXI DDR FI 10 dent 32 bit AHB Lite AHBL slave interfaces to the FPGA fabric masters transaction controller receives read and write requests from AXI masters MSS DDR bridge and C and schedules for the DDR controller by translating them into DDR controller commands Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide The DDR controller receives the commands from the AXI transaction controller These commands are queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM constraints transaction priorities and dependencies between the transactions The DDR controller in turn issues commands to the PHY module which launches and captures data to and from the DDR SDRAM The DDR PHY converts the DDR controller commands into the actual timing relationships and DDR signaling necessary to communicate with the memory device The 16 bit APB configuration bus provides an interface to configure the MDDR subsystem registers Port List Table 1 4 e MDDR Subsystem Interface Signals Signal Name Type Polarity Description APB 8 PCLK In APB clock This clock drives all the registers of the APB interface APB S PRESET N In Low APB reset signal This is an active low signal This drives the APB interface and is used to generate the soft reset for the DDR controller as well MDDR DDR CORE RESET N In Low Global reset Th
194. ite operation 12 6 REG DDRC POST SELFREF GAP X32 0x10 Minimum time to wait after coming out of self refresh before doing anything This must be larger than all the constraints that exist specifications maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks Unit Multiples of 32 clocks 5 1 REG DDRC POWERDOWN TO X32 0x06 After this many clocks of NOP or DESELECT the controller puts the DRAM into power down This must be enabled in the Master Control register Unit Multiples of 32 clocks REG_DDRC_CLOCK_STOP_EN 0x0 1 Stops the clock to the PHY whenever a clock is not required by LPDDR1 0 Clock will never be stopped This is only present for implementations supporting mobile LPDDR1 devices DDRC PWR SAVE 2 CR Table 1 58 DDRC PWR SAVE 2 CR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 REG_DDRC_DIS_PAD_PD 0x0 1 Disable the pad power down feature 0 Enable the pad power down feature Used only in non DFI designs 10 3 REG DDRC DEEPPOWERDOWN TO X1024 0x0 Not supported 2 0 REG DDRC PAD PD 0x0 If pads have a power saving mode this is the greater of the time for the pads to e
195. ith future products the value of a reserved bit should be preserved across a read modify write operation 8 0 PHY REG STATUS PHY CTRL SLAVE DLL VALUE 0x0 Delay value applied to write DQS slave DLL DDR FIC Configuration Registers Summary Table 1 220 DDR FIC Configuration Register Summary Address Reset Register Name Offset R W Source Description DDR FIC NB ADDR CR 0x400 RW PRESET NlIndicates the base address of the non bufferable address region DDR FIC NBRWB SIZE CR 0x404 RW PRESET NlIndicates the size of the non bufferable address region DDR FIC BUF TIMER CR 0x408 RW PRESET N 10 bit timer interface used to configure the timeout register DDR FIC HPD SW RW EN CR 0x40C RW PRESET Nlj Enable write buffer and read buffer register for AHBL master1 and master2 DDR FIC HPD SW RW INVAL CR 0x410 RW PRESET NlInvalidates write buffer and read buffer for AHBL master1 and master2 DDR FIC SW WR ERCLR CR 0x414 RW PRESET N Clear bit for error status by AHBL master1 and master2 write buffer DDR FIC ERR INT ENABLE 0x418 RW PRESET N Used for Interrupt generation DDR FIC NUM AHB MASTERS CR 0x41C RW PRESET N Defines whether one or two AHBL 32 bit masters are implemented in fabric DDR FIC HPB ERR ADDR 1 SR 0x420 RO PRESET Nl Tag of write buffer for which error response is received is placed in this register DDR FIC HPB ERR ADDR 2 SR 0
196. k specification 15 ns for DDR2 400 and lower for faster devices Unit clocks 9 7 REG_DDRC_T_CCD 0x0 tCCD Minimum time between two reads or two writes from bank A to bank B specification 2 cycles is this value 1 Unit clocks 6 4 REG_DDRC_T_RRD 0x0 tRRD Minimum time between activates from bank A to bank B specification 10 ns or less Unit clocks 3 0 REG_DDRC_T_RP 0x0 tRP Minimum time from precharge to activate of same bank Unit clocks 72 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_ODT_PARAM_1_CR Table 1 52 DDRC_ODT_PARAM_1_CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 8 REG_DDRC_RD_ODT_DELAY 0x0 The delay in clock cycles from issuing a READ command to setting ODT values associated with that command Recommended value for DDR2 is CL 4 7 4 REG_DDRC_WR_ODT_DELAY 0x0 The delay in clock cycles from issuing a WRITE command to setting ODT values associated with that command The recommended value for DDR2 is CL 5 Where CL is CAS latency DDR ODT has a 2 cycle on time delay and a 2 5 cycle off time delay ODT setting should remain constant for the entire time that DQS is driven by the controller
197. k diagram of the AXI transaction controller interfaced with the DDR controller AXI Transaction Controller Transaction Handler 64 Bit AXI Bus AXI Slave Priority Block DDR PHY from DDR FIC Interface Controller Re Order Buffer Figure 2 5 AXI Transaction Controller Block Diagram Revision 2 177 I Microsemi Fabric DDR Subsystem The AXI transaction controller comprises four major blocks AXI slave interface e Priority block e Transaction handler e Reorder buffer AXI Slave Interfaces The AXI transaction controller has a 64 bit AXI slave interface from DDR FIC The AXI slave port is 64 bits wide and is in compliance with the standard AXI protocol Each transaction has an ID related to the master interface Transactions with the same ID are completed in order while the transactions with different read IDs can be completed in any order depending on when the instruction is executed by the DDR controller If a master requires ordering between the transactions the same ID should be used The AXI slave interface has individual read and write ports The read port queues read AXI transactions and it can hold upto four read transactions The write port handles only one write transaction at a time and generates the handshaking signals on the AXI interface Priority Block The priority block prioritizes AXI read write transactions and provides control to the transaction handler AXI read transactions have higher priority The f
198. lay value applied to read DQS slave DLL PHY_RD_DQS_SLAVE_DLL_VAL_3_SR Table 1 209 PHY RD DQS SLAVE DLL VAL 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_RD_DQS_SLAVE_DLL_VALUE 0x0 44 32 bits of PHY STATUS RD DQS SLAVE DLL VALUE Delay value applied to read DQS slave DLL 146 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WR_DATA_SLAVE_DLL_VAL_1_SR Table 1 210 PHY WR DATA SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 0x0 15 0 bits of PHY_REG_STATUS_WR_DATA_SLA VE_DLL_VALUE Delay value applied to write data slave DLL PHY WR DATA SLAVE DLL VAL 2 SR Table 1 211 PHY WR DATA SLAVE DLL VAL 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products
199. lue of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY RD DQS SLAVE RATIO 0x4010 47 32 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_RD_DQS_SLAVE_RATIO_4_CR Table 1 147 PHY RD DQS SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_RD_DQS_SLAVE_RATIO 0x0 49 48 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DQS_SLAVE_DELAY_1_CR Table 1 148 PHY WR DQS SLAVE DELAY 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the v
200. m time from WRITE command to READ command Includes time for bus turnaround and recovery times and all per bank per rank and global constraints Unit clocks where WL Write latency BL Burst length This should match the value programmed in the BL bit of the mode register to the DRAM tWTR Internal WRITE to READ command delay This comes directly from the DRAM specifications Revision 2 71 lt gt Microsemi MDDR Subsystem DDRC_DRAM_T_PD_CR Table 1 50 DDRC DRAM T PD CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 4 REG_DDRC_T_XP 0x0 tXP Minimum time after power down exit to any operation Units clocks 3 0 REG_DDRC_T_CKE 0x0 Minimum number of cycles of CKE High Low during power down and self refresh Unit clocks DDRC_DRAM_BANK_ACT_TIMING_CR Table 1 51 DDRC DRAM BANK ACT TIMING CR Bit Reset Number Name Value Description 31 14 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 13 10 REG_DDRC_T_RCD 0x0 tRCD Minimum time from activate to READ or WRITE command to same ban
201. mation of the SECDED unrecoverable error 2 DDRC LCE ADDRESS 1 SR and DDRC LCE ADDRESS 2 SR give the row bank column information of the SECDED error correction 3 DDRC LCB NUMBER SR indicates the location of the bit that caused the single bit error in the SECDED case encoded value 4 DDRC_ECC_INT_SR indicates whether the SECDED interrupt is because of a single bit error or double bit error The interrupt can be cleared by writing zeros to DDRC_ECC_INT_CLR_REG Power Saving Modes The DDR controller can operate DDR memories in three power saving modes e Precharge power down Self refresh e Deep power down Precharge Power Down If REG_DDRC_POWERDOWN_EN 1 the DDR controller automatically keeps DDR memory in Precharge power down mode when the period specified by REG_DDRC_POWERDOWN_TO_X32 register has passed while the controller is idle except for issuing refreshes The controller automatically performs the precharge power down exit on any of the following conditions A refresh cycle is required to any rank in the system The controller receives a new request from the core logic REG DDRC POWERDOWN EN is set to 0 Self Refresh The DDR controller keeps the DDR memory devices in Self refresh mode whenever the REG DDRC SELFREF EN register bit is set and no reads or writes are pending in the controller The DDR controller can be programmed to issue single refreshes at a time REG DDRC REFRESH BURST 0 to minimize the worst cas
202. matrix can access 0 1 2 and 3 regions of DDR that is the accessible DDR memory from AHB bus matrix is 0x00000000 0x4FFFFFFF which is 1 GB Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 18 DDR Memory Regions DDR Memory Region DDR Memory Space 0x00000000 0xOFFFFFFF 0x 10000000 0x1FFFFFFF 0x20000000 0x2FFFFFFF 0x30000000 0x3FFFFFFF 0x40000000 0x4FFFFFFF 0x50000000 0x5FFFFFFF 0x60000000 0x6FFFFFFF 0x70000000 0x7FFFFFFF 0x80000000 0x8FFFFFFF 0x90000000 0x9FFFFFFF 0xA0000000 0xAFFFFFFF 0xB0000000 0xBFFFFFFF 0xC0000000 0xCFFFFFFF 0xD0000000 0xDFFFFFFF 0xE0000000 0xEFFFFFFF 2 0xF0000000 0xFFFFFFFF OO OO NI J om AJ OJN oO N wo _ BK Table 1 19 Accessed DDR Memory Regions Based on Mode Settings for a 4 GB Memory DDR Memory Regions Visible at MSS DDR Address Space for Different Modes MSS DDR Space 0 MSS DDR Space 1 MSS DDR Space 2 MSS DDR Space 3 Address Space 0xA0000000 0xB0000000 0xC0000000 0xD0000000 Mapping Modes OxAFFFFFFF 0xBFFFFFFF OxCFFFFFFF 0xDFFFFFFF 0000 Region 10 Region 11 Region 12 Region 13 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 0011 Region 4 Region 5 Region 6 Region 7 0100 Region 8 Region 9 Region 10 Region 11 0101 Region 12 Region 13 Region 14 Region 15 0
203. modify write operation 0 FPLL_LOCK 0x0 Indicates the lock status of the fabric PLL 212 Revision 2 FDDR INTERRUPT SR Table 2 33 FDDR INTERRUPT SR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation DDR_FIC_INT 0x0 Indicates interrupt from DDR_FIC 3 IO CALIB INT 0x0 The interrupt is generated when the calibration is finished For the calibration after reset this typically would be followed by locking the codes directly For in between runs during functional operation of DDR the assertion of an interrupt does not guarantee lock because the state machine would wait for the ideal time DRAM self refresh for locking This can be used by firmware to insert the ideal time and provides an indication that locked codes are available 2 FDDR_ECC_INT 0x0 Indicates when the ECC interrupt from the FDDR subsystem is asserted 1 PLL_LOCKLOST_INT 0x0 This bit indicates that a falling edge event occurred on the MPLL_LOCK signal This indicates that the MPLL lost lock 0 PLL LOCK INT 0x0 This bit indicates that a rising edge event occurred on the MPLL_LOCK signal This indicates that the MPLL came into lock Table 2
204. mum number of refreshes allowed for DDR REFRESH BURST 7 for performing 8 refreshes at a time to minimize the bandwidth lost when refreshing the pages The controller takes the DDR memory out of Self refresh mode whenever the REG_DDRC_SELFREF_EN input is deasserted or new commands are received by the controller Deep Power Down This is supported only for LPDDR1 The DDR controller puts the DDR SDRAM devices in Deep Power down mode whenever the REG_DDRC_DEEPPOWERDOWN_EN bit is set and no reads or writes are pending in the DDR controller The DDR controller automatically exits Deep power down mode and reruns the initialization sequence when the REG_DDRC_DEEPPOWERDOWN_EN bit is reset to 0 The contents of DDR memory may lost upon entry into deep Power down mode DRAM Initialization After Reset the DDR controller initializes DDR memories through an initialization sequence depending on the type of DDR memory used For more information on the initialization process refer to the JEDEC specification DDR PHY SmartFusion2 devices have a built in hardened DDR PHY block for interfacing with external DDR memories The DDR PHY processes read and write requests from the DDR controller and translate them into specific signals within the timing constraints of the target DDR memory The DDR PHY is composed of functional units including control slice master DLL ratio logic and rank tracker as shown in Figure 1 7 DQI7 0 DAS DQ 15 8J DQS MDLL
205. n empty The read transaction store both high and low priority is the default preferred transaction store and the write transaction store is the alternate store When Prefer write over read is set this is reversed 4 REG DDRC PAGECLOSE 0x0 1 Bank is closed and kept closed if no transactions are available for it This is different from auto precharge a Explicit precharge commands are used and not read write with auto precharge and b Page is not closed after a read write if there is another read write pending to the same page 0 Bank remains open until there is a need to close it to opena different page or for page timeout or refresh timeout This does not apply when auto refresh is used 80 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 63 DDRC PERF PARAM 1 CR continued Bit Reset Number Name Value Description 3 Reserved This bit must always be set to zero 2 0 REG DDRC LPR NUM ENTRIES 0x03 Number of entries in the low priority transaction store is this value plus 1 READ CAM DEPTH REG DDRC LPR NUM ENTRIES 1 is the number of entries available for the high priority transaction store READ CAM DEPTH Depth of the read transaction store Setting this to maximum value allocates all entries to low priority transaction store Setting this to 0 allocates 1 entry to low priority transaction store and the rest to
206. n 40 MDDR DQ 3 Inout SSTLISI E12 VI BankO TRISTATE None On 40 MDDR_DQ 4 Inout SSTLISI Als Vi Banko TRISTATE None On 40 MDDR DQ S Inout SSTLISI D14 V BankO TRISTATE None On 40 Mee PORS Inout SSTLISI E14 V Banko TRISTATE None Q 0 Figure 1 14 I O Configuration Revision 2 35 I Microsemi MDDR Subsystem MDDR Subsystem Features Configuration The MDDR subsystem registers must be initialized before accessing DDR memory through the MDDR subsystem This section provides the necessary registers to configure the features of the MDDR AIl registers are listed with their bit definitions in the MDDR Configuration Registers section on page 54 section Memory Type DDRC MODE CR must be configured to select the memory type DDR2 DDR3 or LPDDR1 to access from MDDR subsystem Bus Width Configurations The MDDR supports various bus widths as listed in Table 1 13 The MDDR can be programmed to work in full half or quarter Bus width mode by configuring the DDRC MODE CR and PHY DATA SLICE IN USE CR registers when the controller is in soft reset Table 1 13 Supported Bus Widths M2S005 M2S010 M2S025 M2S050 VF400 M2S050 M2S075 M2S080 M2S120 Bus Width VF400 FG484 FG484 FG896 FG484 FC1152 Full bus width V v Half bus width v v v v v Quarter bus v v width Burst Mode The DDR controller performs the burst write operations to DDR memory depending
207. n REG PHY BIST MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift PHY LOOPBACK TEST CR Table 1 113 PHY DYN LOOPBACK CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_LOOPBACK 0x0 Loopback testing 1 Enable 0 Disable Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_BOARD_LOOPBACK_CR Table 1 114 PHY BOARD LOOPBACK CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_PHY_BOARD_LPBK_TX 0x0 _ External board loopback testing 1 This slice behaves as a transmitter for board loopback 0 Default This port must always be set to 0 except when in external board level loopback test mode 4 0 REG_PHY_BOARD_LPBK_RX 0x0 External board loopback testing 1 This slice behaves as a receiver for board loopback 0 Disable This port must always be set to 0 except when in external board level loopback test mode PHY_CTRL_SLAVE_RATIO_CR
208. n any two refresh commands may be larger or smaller than this this represents the maximum time allowed between refresh commands to a given rank when averaged over a large period of time Minimum refresh cycle time tRFC min REG DDRC T RFC MIN Minimum time from refresh to refresh or activate RAS to rAS delay tRRD REG DDRC T RRD Minimum time between activates from bank A to bank B RAS to CAS delay tCCD REG DDRC T CCD Minimum time between two reads or two writes from bank A to bank B Four active Wi tWorkndow tFAW REG DDRC T FAW Sliding time window in which a maximum of 4 bank activates are allowed in an 8 bank design In a 4 bank design set this register to 0x1 Revision 2 37 lt gt Microsemi MDDR Subsystem Dynamic DRAM Global Constraints The timing constraints which affect global transactions are listed in Table 1 17 The control bit field must be configured as per the DDR memory vendor specification Table 1 17 Dynamic DRAM Global Constraints Timing Constraint Control Bit Description Read to write turnaround time REG_DDRC_RD2WR Minimum time to allow between issuing any Read command and issuing any WRITE command Write to read turnaround time REG_DDRC_WR2RD Minimum time to allow between issuing any Write command and issuing any Read command Write latency REG DDRC WRITE LATENGY Time after a Write command that write data should be
209. nd Write to read turnaround time REG_DDRC_WR2RD Minimum time to allow between issuing any Write command and issuing any Read command Write latency REG_DDRC_WRITE_LATENCY Time after a Write command that write data should be driven to DRAM The DDR memories require delays after initializing the mode registers The following registers must be configured for delay requirements for the DDR memories The DDR controller uses these delay values while initializing the DDR memories DDRC_CKE_RSTN_CYCLES_1_CR recommended value is 0x4242 DDRC CKE RSTN CYCLES 2 CR recommended value is 0x8 Address Mapping The DDR controller maps linear request addresses to DDR memory addresses by selecting the source bit that maps to each and every applicable DDR memory address bit Each DDR memory address bit has an associated register vector to determine its source The source address bit number is determined by adding the internal base of a given register to the programmed value for that register as described in EQ 1 Internal base register value source address bit number EQ 1 For example reading the description for REG DDRC ADDRMAP COL B3 the internal base is 3 so when the full data bus is in use the column bit 4 is determined by 3 register value Revision 2 191 I Microsemi Fabric DDR Subsystem 192 If this register is programmed to 2 then the source address bit is 3 2 5 The address m
210. nd may not be available in all PHYs 1 REG PHY CMD LATENCY 0x0 Extra command latency 1 Command bus has 1 extra cycle of latency 0 Default This port is available only when MEMP_CMD_PIPELINE is defined PHY_RD_WR_GATE_LVL_CR Table 1 176 PHY RD WR GATE LVL CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 10 REG_PHY_GATELVL_INC_MODE 0x0 Incremental read DQS gate training mode One bit for each data slice 1 Incremental read gate training 0 Normal read gate training 9 5 REG_PHY_WRLVL_INC_MODE 0x0 Incremental write leveling mode One bit for each data slice 1 Incremental write leveling 0 Normal write leveling 4 0 REG_PHY_RDLVL_INC_MODE 0x0 Incremental read data eye training mode One bit for each data slice 1 Incremental read data eye training 134 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_DYN_RESET_CR Table 1 177 PHY DYN RESET CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a re
211. ndicates the size of the non bufferable address region The region sizes are as follows 0000 Reserved default 0001 64 KB bufferable region 0010 128 KB bufferable region 0011 256 KB bufferable region 0100 512 KB bufferable region 0101 1 MB bufferable region 0110 2 MB bufferable region 0111 4 MB bufferable region 1000 8 MB bufferable region 1001 16 MB bufferable region 1010 32 MB bufferable region 1011 64 MB bufferable region 1100 128 MB bufferable region 1101 256 MB bufferable region 1110 512 MB bufferable region 1111 1 GB bufferable region DDR_FIC_BUF_TIMER_CR Table 1 223 DDR FIC BUF TIMER CR Bit Reset Number Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 DDR_FIC_TIMER 0x0 10 bit timer interface used to configure timeout register Once timer reaches the timeout value a flush request is generated by the flush controller in the DDR_FIC This port is common for all buffers 152 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR_FIC_HPD_SW_RW_EN_CR Table 1 224 DDR FIC HPD SW RW EN CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To pro
212. ndor Simulate the design and observe the AXI read and write transactions Note The MDDR subsystem can be configured using the Cortex M3 processor without having an APB master In this case the MSS GPIO can be used to indicate that the DDR memory has been successfully initialized Revision 2 45 I Microsemi MDDR Subsystem Use Model 2 Accessing MDDR from FPGA Fabric Through the AHB Interface The MDDR subsystem can be used to access the DDR memory as shown in Figure 1 20 The MDDR register can be configured through the MSS or user logic AHB master in the FPGA fabric MSS Ra MSS DDR MSS DDR DDR Transaction Bridge Masters SDRAM Controller Controller AHB Lite FPGA Fabric Figure 1 20 e MDDR with Single AHB Interface To use a dual rather than single AHB interface to the MDDR set the CFG NUM AHB MASTERS bit in the DDR FIC NUM AHB MASTERS CR register to 1 46 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide MSS AHB Masters AXI MSS DDR DDR Transaction ee Controller Controller AHB Lite AHB Lite FPGA Fabric Figure 1 21 MDDR with Dual AHB Interface The steps for accessing the MDDR from one or two AHB masters in the FPGA fabric is the same as in Use Model 1 Accessing MDDR from FPGA Fabric Through the AXI Interface section on page 42 except for the following 1 The single AHB or two AHB interfaces must be selected in the MSS external mem
213. nse available 0 Write response not available MDDR DDR AXI S RDATA 63 0 Output Indicates read data MDDR DDR AXI S RID 3 0 Output Read ID tag This signal is the ID tag of the read data group of signals MDDR DDR AXI S RLAST Output High Indicates the last transfer in a read burst MDDR DDR AXI S RRESP 1 0 Output Indicates read response This signal indicates the status of the read transfer 00 Normal access 01 Exclusive access 10 Slave error 11 Decode error MDDR DDR AXI S RVALID Output Indicates whether the required read data is available and the read transfer can complete 1 Read data available 0 Read data not available Revision 2 13 I Microsemi MDDR Subsystem Table 1 5 AXI Slave Interface Signals continued Signal Name Direction Polarity Description MDDR DDR AXI S WREADY Output High Indicates whether the slave can accept the write data 1 Slave ready 0 Slave not ready MDDR DDR MDDR DDR AXI S ARADDR 31 0 Input Indicates initial address of a read burst transaction MDDR DDR AXI 8 ARBURST 1 0 Input Indicates burst type The burst type coupled with the size information details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wr
214. nter power down or the time for the pads to exit power down Used only in non DFI designs Unit clocks Revision 2 77 lt gt Microsemi MDDR Subsystem DDRC_ZQ_LONG_TIME_CR Table 1 59 DDRC ZQ LONG TIME CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG_DDRC_T_ZQ_LONG_NOP 0x0 Number of cycles of NOP required after a ZQCL ZQ calibration long command is issued to DRAM Units Clock cycles This is only present for implementations supporting DDR3 devices DDRC_ZQ_SHORT_TIME_CR Table 1 60 DDRC ZQ SHORT TIME CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG DDRC T ZQ SHORT NOP 0x0 Number of cycles of NOP required after a ZQCS ZQ calibration short command is issued to DRAM Units Clock cycles This is only present for implementations supporting DDR3 devices 78 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR Table 1 61 D
215. ntifying these delays the system can calculate the midpoint between the delays and accurately center the read DQS within the DQ data eye The DDR controller drives subsequent read transactions for every read to read delay specified by REG DDRC RDLVL RR until the PHY drives the response signal High The DDR controller performs the following steps 1 Sets up the DDR memory for read leveling mode by sending the appropriate MR3 command which forces the DDR memory to respond to read commands with a 1 0 1 0 1 pattern 2 Sets the relevant read leveling enable bit and sends out periodically timed read commands on the DDR memory command interface 3 Once the PHY completes its measurements it sets the read level response bits which then signal the DDR controller to stop the leveling process and lower the read leveling enable bit Incremental Training This is applicable for all DDR memories The PHY supports incremental training where the data path delays are incremented or decremented by 1 by the training logic This mode can be enabled for incremental read and write leveling by configuring the PHY RD WR GATE LVL CR register This mode must be enabled only after the initial training is completed The PHY generates a flag bit when the incremental leveling fails indicating that the interval was too large The status of the incremental training can be read in the PHY LEVELLING FAILURE SR register Revision 2 lt gt Microsemi SmartFusion2 So
216. ny correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane DDRC_LCB_MASK_3_SR Table 1 101 DDRC LCB MASK 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 47 32 bits of DDRC LCB MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High This mask does not indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane 102 Revision 2 DDRC LCB MASK 4 SR Table 1 102 DDRC LCB MASK 4 SR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1
217. o 1 Table 1 127 PHY FIFO WE IN DELAY 3 CR PHY FIFO WE IN DELAY 3 CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG PHY FIFO WE IN DELAY 0x0 44 32 bits of REG PHY FIFO WE IN DELAY Delay value to be used when REG PHY FIFO WE IN FORCEX is set to 1 Table 1 128 PHY FIFO WE IN FORCE CR PHY FIFO WE IN FORCE CR Bit Reset Number Name Value Description 7 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_FIFO_WE_IN_FORCE 0x0 1 Overwrite the delay tap value for the FIFO_WE slave DLL with the value of the REG PHY FIFO WE IN DELAY bus Revision 2 115 lt gt Microsemi MDDR Subsystem PHY_FIFO_WE_SLAVE_RATIO_1_CR Table 1 129 PHY FIFO WE SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE
218. o the FPLL 00 No buffer delay 01 One buffer delay 10 Two buffers delay 11 Three buffers delay FDDR_SOFT_RESET Table 2 26 FDDR SOFT RESET Bit Number Name Reset Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation FDDR_DDR_FIC_SOFTRESET 0x1 When 1 holds the DDR_FIC AXI AHB interface controller in reset FDDR_CTLR_SOFTRESET 0x1 When 1 holds the FDDR subsystem in reset lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide FDDR_IO_CALIB Table 2 27 FDDR_IO_CALIB Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 CALIB_TRIM 0x0 Indicates override of the calibration value from the pc code programmed code values in the DDRIO calibration block 13 CALIB_LOCK 0x0 Used in the DDRIO calibration block as an override to lock the codes during intermediate runs When the firmware receives CALIB_INTRPT it may choose to assert this signal by prior knowledge of the traffic without g
219. of DDR memory choosing fabric master interface type clocking and DDR I O settings 2 MDDR register initialization The MDDR subsystem registers can be initialized using the Cortex M3 processor or FPGA fabric master After MSS resets the MDDR registers must be configured according to application and DDR memory specification The MDDR Subsystem Features Configuration section on page 36 provides the details of required register configuration for MDDR features While configuring the registers the soft reset to the DDR controller must be asserted After releasing the soft reset the DDR controller performs DDR memory initialization and sets the status bits in DDRC_SR Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide MSS external memory configuration MDDR clock configuration Libero design flow FIC_2 configuration Configure DDR I O settings in I O Editor for example ODT drive strength After MSS reset Set the soft reset bit to 0 Configure the MDDR register Set the soft reset bit to 1 DDRC_SR 0 Start read write to DDR memory The configuration steps in the flow chart are explained below Required steps for MDDR initialization Figure 1 8 Design Flow Revision 2 29 I Microsemi MDDR Subsystem MSS External Memory Configuration The MDDR subsystem is configured through the MSS external memory configurator which is part of the MSS config
220. of lower source MUX 1 CLK SRC driven from output of upper source MUX 2 0 208 FACC STANDBY SEL 0x0 Selects the standby glitchfree multiplexers within the FACC This is used to allow one of four possible clocks to proceed through to the FDDR subsystem during FACC PLL initialization time before the MPLL comes into lock FACC_STANDBY_SEL 0 is used to select the lower standby MUX 0 CLK_STANDBY driven from CLK_25_50MHZ 1 CLK_STANDBY driven from CLK_XTAL FACC_STANDBY_SEL 1 is used to select upper standby MUX 0 CLK_STANDBY driven from CLK_1MHZ 1 CLK_STANDBY driven from ccc2asic FACC_STANDBY_SEL 2 is used to select the output standby MUX 0 CLK_STANDBY driven from output of lower standby MUX 1 CLK_STANDBY driven from output of upper standby MUX Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide FDDR_FACC_DIVISOR_RATIO Table 2 24 FDDR FACC DIVISOR RATIO Bit Reset Number Name Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 5 BASE_DIVISOR 0x0 Selects the ratio between CLK_A and the regenerated version of CLK BASE called CLK BASE REGEN Allowed values 000 CLK A CLK BASE REGEN ratio is 1 1 001 CLK A CLK BASE REGEN ratio is 2 1 010 CLK A CLK BASE REGEN r
221. oftware should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_WR_DATA_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for write data slave DLL with the value of the REG_PHY_WR_DATA_SLAVE_DELAY bus bit 4 is for PHY Data slice 4 bit 3 for PHY Data slice 3 and so on 126 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WR_DATA_SLAVE_RATIO_1_CR Table 1 160 PHY WR DATA SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY WR DATA SLAVE RATIO 0x0040 15 0 bits of REG PHY WR DATA SLAVE RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG PHY USE WR LEVEL 0 PHY WR DATA SLAVE RATIO 2 CR Table 1 161 PHY WR DATA SLAVE RATIO 2 CR Bit Reset Number Name Value Description 31 16
222. oing through the process of putting the DDR into self refresh 12 CALIB_START 0x0 Indicates that rerun of the calibration state machine is required in the DDRIO calibration block 11 6 NCODE 0x0 Indicates the DPC override NCODE from flash in DDRIO calibration This can also be overwritten from the firmware 5 0 PCODE 0x0 Indicates the PC override PCODE from flash in the DDRIO calibration block This is also be overwritten from the firmware FDDR_INTERRUPT_ENABLE Table 2 28 FDDR INTERRUPT ENABLE Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_INT_ENABLE 0x0 Masking bit to enable DDR FIC interrupt 5 IO CALIB INT ENABLE 0x0 Masking bit to enable DDR 1 O calibration interrupt 4 FDDR_ECC_INT_ENABLE 0x0 Masking bit to enable ECC error interrupt 3 FABRIC_PLL_LOCKLOST_INT_ENABLE 0x0 Masking bit to enable FAB PLL LOCK LOST interrupt 2 FABRIC_PLL_LOCK_INT_ENABLE 0x0 Masking bit to enable FAB_PLL_LOCK interrupt 1 FPLL_LOCKLOST_INT_ENABLE 0x0 Masking bit to enable FPLL_LOCK_LOST interrupt 0 FPLL_LOCK_INT_ENABLE 0x0 Masking bit to enable FPLL LOCK interrupt Revision 2 211 lt gt Microsemi Fabric DDR Subsystem F AXI AHB MODE SEL Table 2 29 F AXI AHB MODE SEL
223. olarity Description FDDR DQS TMATCH 0 OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH 0 IN FDDR DQS TMATCH 1 OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH 1 IN FDDR DQS TMATCH ECC IN High FIFO in signal DQS enables input for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH ECC OUT FDDR DQS TMATCH ECC OUT Out High FIFO out signal DQS enables output for timing match between DQS and system clock For simulations tie to FDDR DQS TMATCH ECC IN Note AXI or AHB interface depending on configuration AXI Slave Interface Table 2 5 shows the FDDR AXI slave interface signals with their descriptions These signals will be available only if FDDR interface is configured for AXI mode For more details of AXI protocol refer to AMBA AXI v1 0 protocol specification Table 2 5 FDDR AXI Slave Interface Signals Signal Name Direction Polarity Description AXI S ARREADY Output High Indicates whether the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready AXI S AWREADY Output High Indicates that the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not re
224. on the Burst mode selection Burst mode is selected as sequential or interleaving by configuring REG_DDRC_BURST_MODE to 1 or 0 Burst length can be selected as 4 8 or 16 by configuring REG_DDRC_BURST_RDWR Supported burst modes for DDR SDRAM types and PHY widths are given in Table 1 14 For M2S050 devices only sequential burst mode and a burst length of 8 are supported Table 1 14 Supported Burst Modes Sequential Interleaving 32 v LPDDR1 DDR2 v DDR3 16 LPDDR1 DDR2 DDR3 a 8 LPDDR1 DDR3 DDR2 SISISISISISISNSISIS Configuring Dynamic DRAM Constraints Timing parameters for DDR memories must be configured according to the DDR memory specification Dynamic DRAM constraints are subdivided into three basic categories Bank constraints affect the transactions that are scheduled to a given bank e Rank constraints affect the transactions that are scheduled to a given rank e Global constraints affect all transactions 36 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Dynamic DRAM Bank Constraints The timing constraints which affect the transactions to a bank are listed in Table 1 15 The control bit field must be configured as per the DDR memory vendor specification Table 1 15 Dynamically Enforced Bank Constraints Timing Constraint of DDR Memory Control Bit Description Row cycle time tRC RE
225. on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_DQS_RATIO 0x0 47 32 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM Revision 2 139 lt gt Microsemi MDDR Subsystem PHY_RDLVL_DQS_RATIO_4_SR Table 1 193 PHY RDLVL DQS RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_RDLVL_DQS_RATIO Ox0 49 48 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM PHY_FIFO_1_SR Table 1 194 PHY FIFO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY REG RDLVL FIFOWEIN RATIO 0x0 15 0 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM PHY FIFO 2 SR Table 1 195 PHY FIFO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0
226. one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Revision 2 91 lt gt Microsemi MDDR Subsystem DDRC_LUE_SYNDROME_2_SR Table 1 85 DDRC LUE SYNDROME 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 31 16 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper
227. onfigure as required In this example the fabric CCC is configured to generate 111 MHz as shown in Figure 2 21 A FAB CCC Configurator Basic Advanced PLL Options Basic Options Figure 2 21 Fabric CCC Configuration 9 Instantiate CoreSF2Config in the SmartDesign canvas and configure for FDDR as shown in Figure 2 22 Make the FIC_2 and FDDR APB interface connections to CoreSF2Config Figure 2 22 CoreSF2Config IP Configuration Revision 2 199 I Microsemi Fabric DDR Subsystem 10 Instantiate CoreSF2Reset in the SmartDesign canvas and configure for FDDR as shown in Figure 2 23 Make the connections to CoreSF2Reset and CoreSF2Config accordingly E Contguring CoreSF2Reset_0 KoreSF2Reset pail Corts oon OT JEST OUT mere Iver Figure 2 23 CoreSF2Config IP Configuration 11 Instantiate user AHB master logic in the SmartDesign canvas to access the FDDR through the AHB interface The AHB master clock frequency should be the same as the FDDR DDR FIC clock frequency 12 Connect the AHB master to the FDDR AHB slave0 interface through CoreAHBLite Connect the FIC 0 master to the FDDR AHB slave1 interface through CoreAHBLite 13 Make the other connections in the SmartDesign canvas as shown in Figure 2 24 SYSRESET 0 DEV T N FONER ON RESET CESTNE
228. ontrol bit field must be configured as per the DDR memory vendor specification Table 2 14 Dynamically Enforced Bank Constraints Timing Constraint of DDR Memory Control Bit Description Row cycle time tRC REG DDRC T RC Minimum time between two successive activates to a given bank Row precharge command REG DDRC T RP Minimum time from a precharge command to the next period tRP command affecting that bank Minimum bank active time REG DDRC T RAS MIN Minimum time from an activate command to a precharge tRAS min command to the same bank Maximum bank active time REG DDRC T RAS MAX Maximum time from an activate command to a precharge tRAS max command to the same bank RAS to CAS delay RCD REG DDRC T RCD Minimum time from an activate command to a Read or Write command to the same bank Write command period REG DDRC WR2PRE Minimum time from a Write command to a precharge tWR command to the same bank Read to precharge delay REG_DDRC_RD2PRE Minimum time from a Read command to a precharge command to the same bank Set this to the current value of additive latency plus half of the burst length 190 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Dynamic DRAM Rank Constraints The timing constraints which affect the transactions to a rank are listed in Table 2 15 The control bit field must be configured as per the DDR memory vend
229. or through MDDR The firmware project initializes the MDDR subsystem before executing the instructions in main with the register settings provided in the above step 4 Refer to the MDDR Tutorial which describes the steps to create the design for accessing the MDDR from the Cortex M3 processor The tutorial also explains the steps for simulating the design in Libero SoC Revision 2 49 I Microsemi MDDR Subsystem Use Model 4 Accessing MDDR from the HPDMA The HPDMA controller can access DDR SDRAM connected to the MDDR subsystem through the MSS DDR bridge as shown in Figure 1 25 ARM Cortex M3 Microcontroller SD l Controller J MSS DDR C Cache Transaction Bridge DS Controller l S D IC I I HPDMA AHB Bus Matrix Figure 1 25 Accessing MDDR from HPDMA 50 The steps for accessing the MDDR from the HPDMA are the same as in Use Model 3 Accessing MDDR from Cortex M3 Processor section on page 48 Use the generated firmware project to access DDR memory from the HPDMA through the MDDR The HPDMA driver has the MSS HPDMA start API to initiate memory transfers and DDR memory from and to other memory locations This API requires the parameter s source address destination address and number of bytes to transfer DDR Memory Device Examples This section describes how to connect DDR memories to SmartFusion2 MDDR PADs with examples Example 1 Connecting 32 Bit DDR2 to MDDR PADs Figure 1 26 shows DDR2 SDRAM conne
230. or 2 cycles when write requires changing ODT settings 10 Block read write scheduling for 3 cycles when write requires changing ODT settings 11 Reserved DDRC_ADDR_MAP_COL_3_CR Table 1 54 e DDRC ADDR MAP COL 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit 7 6 To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 12 REG DDRC ADDRMAP COL B5 0x0 Full bus width mode Selects column address bit 6 Half bus width mode Selects column address bit 7 Quarter bus width mode Selects column address bit 8 Valid range 0 to 7 Internal base 5 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field 74 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 54 e DDRC ADDR MAP COL 3 CR continued Bit Number Name Reset Value Description 11 8 REG DDRC ADDRMAP COL B6 0x0 Full bus width mode Selects column address bit 7 Half bus width mode Selects column address bit 8 Quarter bus width mode Selects column address bit 9 Valid range 0 to 7 Internal base 6 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field
231. or specification Table 2 15 Dynamically Enforced Bank Constraints Timing Constraints of DDR Memory Control Bit Description Nominal refresh cycle time RFC nom or tREFI REG DDRC T RFC NOM X32 Average time between refreshes for a given rank The actual time between any two refresh commands may be larger or smaller than this this represents the maximum time allowed between refresh commands to a given rank when averaged over a large period of time Minimum refresh cycle time tRFC min RAS to RAS delay tRRD REG DDRC T RFC MIN REG DDRC T RRD Minimum time from refresh to refresh or activate Minimum time between activates from bank A to bank B RAS to CAS delay tCCD REG DDRC T CCD Minimum time between two reads or two writes from bank A to bank B Four active Wi tWorkndow tFAW REG DDRC T FAW Sliding time window in which a maximum of 4 bank activates are allowed in an 8 bank design Ina 4 bank design set this register to 0x1 Dynamic DRAM Global Constraints The timing constraints which affect global transactions are listed in Table 2 16 The control bit field must be configured as per the DDR memory vendor specification Table 2 16 Dynamic DRAM Global Constraints Timing Constraint Control Bit Description Read to write turnaround time REG_DDRC_RD2WR Minimum time to allow between issuing any Read command and issuing any WRITE comma
232. ormation details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved MDDR DDR AXI S AWID 3 0 Input Indicates identification tag for the write address group of signals Revision 2 15 I Microsemi MDDR Subsystem Table 1 5 AXI Slave Interface Signals continued Signal Name Direction Polarity Description MDDR DDR AXI S AWLEN 3 0 Input Indicates burst length The burst length gives the exact number of transfers in a burst This information determines the number of data transfers associated with the address 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 MDDR DDR AXI S AWLOCK 1 0 Input Indicates lock type This signal provides additional information about the atomic characteristics of the write transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved MDDR DDR AXI S AWSIZE 1 0 Input Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 MDDR_DDR_AXI_S_AWVALID Input High Indicates whether or not valid write address and control inform
233. ory The DDR PHY is composed of functional units including control slice master DLL ratio logic and rank tracker as shown in Figure 2 7 DQI7 0 DAS Data Slice 0 Write Data Interface DQ 15 8J DQS gt Data Slice 1 Read Data Interface rem pares 16ybas Training Interface a DQ 31 24 DQS Data Slice 3 TT ca ecotsayoas eco Data Slice 4 Control Interface Memory Controls Control Slice The DDR PHY consists of five byte wide data slices and one control slice Data slice 4 is reserved for SECDED and other data slices are reserved for the actual data transfer Unused data slices can be disabled to save power by configuring the PHY DATA SLICE IN USE CR register The byte wide data slices contain the slave DLLs for write data write DQS and read DQS The registers can be configured to set the slave DLL ratio values which are required when training is disabled These ratio values determine the delays to write data write DQS and read DQS The PHY has a FIFO for reading the data from all the slices in the same clock cycle Figure 2 7 DDR PHY Block Diagram The primary function of the PHY control slice is to control the timing of the generation of all the DDR memory address and control signals Ratio logic functions are used to adjust the signal timing for each signal edge and these are controlled by the master DLL There are two kinds of DLLs the master DLL and the slave DLL The DLLs are responsible for creating the
234. ory configurator instead of AXI master 2 One or two AHB masters must be connected through CoreAHB s in the SmartDesign canvas Revision 2 47 lt gt Microsemi MDDR Subsystem Use Model 3 Accessing MDDR from Cortex M3 Processor The Cortex M3 processor can access the DDR SDRAM connected to the MDDR subsystem through the MSS DDR bridge as shown in Figure 1 22 ARM Cortex M3 Microcontroller SD l Cache AXI MSS DDR IDG controller DDR DDR i SDRAM Controller Cansaction Bridge Bg AHB Bus Matrix Figure 1 22 e Accessing MDDR from Cortex M3 Processor Use the following steps to access the MDDR from the Cortex M3 processor Instantiate the SmartFusion2 MSS component onto the SmartDesign canvas 2 Configure the SmartFusion2 MSS peripheral components as required using the MSS configurator 3 Configure the MDDR as shown in Figure 1 23 In this example the design is accessing DDR3 with a 32 bit data width E MSS External Memory Configurator External Memory Type Interface Configuration Application accesses Double Data Rate Memory Memory Configuration Type DDR3 v Width 32 kd Memory Access _ From FPGA Fabric Application accesses Single Data Rate Memory from MSS Memory Access Edit Registers Figure 1 23 MSS External Memory Configuration 48 Revision 2 4 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Click Edit Registers and config
235. ory through MDDR using these interfaces Revision 2 amp Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Edit Registers The configurator also has an option Edit Registers for configuring the MDDR subsystem registers to access external DDR memory The register values must be calculated according to the application requirements and DDR memory specifications Refer to the MDDR Subsystem Features Configuration section on page 36 for more information on the register configurations for using MDDR subsystem features The firmware generated by Libero SoC stores these configurations and the MDDR subsystem registers are initialized by the Cortex M3 processor during the system_init phase of the firmware projects SoftConsole IAR Keil projects generated by Libero SoC Figure 1 10 shows the Registers Configuration window which enables configuration of the MDDR subsystem registers The register bit description is displayed at the bottom of the configurator on selection of the register bits The actual value field must be modified as per the application requirement The configurator also provides the option to import and export the register configurations r Tom LLL a Data Format Hexadecimal Import Configuration Export Configuration Reset Configuration 7 Hide Read only ner meme Register Field Name Address Access Reset Value Actua Value wiatn Status gt 4 DDRC_DYN_
236. ory with the address space 0xA0000000 to 0xD0000000 The SMC FIC can be configured for 64 bit AXI or 32 bit AHBL by setting the F AXI AHB MODE bit in the MDDR CR register in the SYSREG block MSS DDR Bridge Interface Figure 4 2 SMC FIC Block Diagram Port List SMC_FIC 64 Bit AXI 32 Bit AHBL Master Interface Table 4 1 and Table 4 2 on page 233 show the 64 bit AXI and 32 bit AHBL port lists Note The SMC_FIC in M2S005 M2S010 and M2S025 devices provides only one 32 bit AHB Lite interface Table 4 1 e SMC FIC 64 bit AXI Port List Signal Direction Polarity Description MDDR SMC AXI M WLAST Output High Indicates the last transfer in a write burst MDDR SMC AXI M WVALID Output High Indicates whether or not valid write data and strobes are available 1 Write data and strobes available 0 Write data and strobes not available MDDR_SMC_AXI_M_BREADY Output High Indicates whether or not the master can accept the response information 1 Master ready 0 Master not ready MDDR SMC AXI M AWVALID Output High Indicates whether or not valid write address and control information are available 1 Address and control information available 0 Address and control information not available 228 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 4 1 e SMC FIC 64 bit AXI Port List continued Signal Direction Polarit
237. ould be preserved across a read modify write operation 6 DDR FIC fishM1 0x0 1 Flush read buffer for AHBL master1 0 Default 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_invalid_M1 0x0 1 Invalidate write buffer for AHBL master1 0 Default 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_flshM2 0x0 1 Flush write buffer for AHBL master2 0 Default Revision 2 153 I Microsemi MDDR Subsystem Table 1 225 DDR FIC HPD SW RW INVAL CR continued Bit Reset Number Name Value Description 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_invalid_M2 0x0 1 Invalidate read buffer for AHBL master2 0 Default DDR FIC SW WR ERCLR CR Table 1 226 DDR FIC SW WR ERCLR CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserve
238. ovide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_OF_OUT_DELAY_VALUE OxO 26 16 bits of PHY_REG_STATUS_OF_OUT_DELAY _ VALUE The coarse and fine values coming out of the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 144 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_DLL_LOCK_AND_SLAVE_VAL_SR Table 1 205 PHY DLL LOCK AND SLAVE VAL SR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 PHY_REG_STATUS_PHY_CTRL_DLL_LOCK 0x0 PHY CTRL Master DLL Status bits 1 Master DLL is locked 0 Master DLL is not locked 8 0 PHY REG STATUS PHY CTRL DLL SLAVE VALUE 0x0 Shows the current coarse and fine delay value going to the PHY CTRL slave DLL 1 0 Fine value 8 2 Coarse value PHY CTRL OUTPUT FILTER SR Table 1 206 PHY CTRL OUTPUT FILTER SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should b
239. power down entry and exit caused by lack of transaction arrival for programmable time Advanced power saving design includes necessary toggling of command address and data pins Revision 2 161 I Microsemi Fabric DDR Subsystem The system level block diagram of the FDDR subsystem is shown in Figure 2 1 ARM Cortex M3 Processor SD I Cache Controller S D IC AHB Bus Matrix FIC_2 FIC 0 FIC 1 APB AXI AHB Master Master FPGA Fabric 64 Bit AXI Single 32 Bit AHBL Dual 32 Bit AHBL ABP Cod par ae Register DDR DDR SDRAM Controller AXI SmartFusion2 Transaction F 6 Bit APB Controller Figure 2 1 System Level FDDR Block Diagram The FDDR subsystem accepts data transfer requests from AXI or AHB interfaces Any read or write transactions to the DDR memories can occur through the AXI or AHBL masters in the FPGA fabric through DDR FIC interface Memory Configurations The SmartFusion2 FDDR subsystem supports a wide range of common memory types configurations and densities as shown in Table 2 1 If SECDED mode is enabled in the FDDR controller the external memory module must be connected to the following Data lines FDDR_DQ_ECC 3 0 when data width is x32 Data lines FDDR DQ ECC 1 0 when data width is x16 Data line FDDR DQ ECC 0 when data width is x8 162 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 2 1 Supported Memory DDR2 DDR3 an
240. precise timing windows required by the DDR memories to read and write data The master DLL measures the cycle period in terms of a number of taps and passes this number through the ratio logic to the slave DLLs The Rank Tracker returns the rank number when the PHY gets a read write request at the read write interface The training logic in the PHY determines the correct delay programming for the read data DQS and write DQS signals The training logic adjusts the delays and evaluates the results to locate the appropriate edges The DDR controller assists by enabling and disabling the leveling logic in the DDR memories and PHY by generating the necessary read commands or write strobes The PHY informs the DDR controller when it has completed training which triggers the DDRC to stop generating commands and to return to normal operation Revision 2 181 I Microsemi Fabric DDR Subsystem How to Use the FDDR This section describes how to use the FDDR subsystem in a design It contains the following sections 182 Design Flow Use Model 1 Accessing FDDR from FPGA Fabric Through AXI Interface Use Model 2 Accessing FDDR from FPGA Fabric Through AHB Interface DDR Memory Device Examples Design Flow Figure 2 8 on page 183 illustrates the design flow for using the FDDR subsystem to access external DDR memory The design flow consists of two parts 1 Libero flow This includes configuring the type of DDR memory choosing fabric mast
241. provides an efficient access path FPGA fabric masters communicate with the MDDR subsystem through AXI or AHB interfaces Features Integrated on chip DDR memory controller and PHY Configurable to support LPDDR1 DDR2 and DDR3 memory devices Up to 667 Mbps 333 33 MHz DDR performance Supports memory densities up to 4 GB Supports 8 16 32 bit DDR standard dynamic random access memory SDRAM data bus width modes Supports a maximum of 8 memory banks Supports 1 2 or 4 ranks of memory Single error correction and double error detection SECDED enable disable feature Supports DRAM burst lengths of 4 8 or 16 depending on configured bus width mode and DDR type Support for sequential and interleaved burst ordering Programs internal control for ZQ short calibration cycles for DDR3 configurations Supports dynamic scheduling to optimize bandwidth and latency Supports self refresh entry and exit on software command Supports deep power down entry and exit on software command Flexible address mapper logic to allow application specific mapping of row column bank and rank bits Configurable support for 1T or 2T timing on the DDR SDRAM control signals Supports autonomous DRAM power down entry and exit caused by lack of transaction arrival for programmable time Advanced power saving design includes necessary toggling of command address and data pins Revision 2 7 I Microsemi MDDR Subsystem The system level block diagram
242. pulse interrupt is generated to the fabric interface If single or dual AHB 32 interfaces are selected DDR_FIC converts the single or dual 32 bit AHBL master transactions from the FPGA fabric to 64 bit AXI transactions The DDR bridge which is embedded as part of the DDR_FIC is enabled in this case The DDR bridge has an arbiter that uses a round robin priority scheme on read and write requests from the two AHB masters Refer to the DDR Bridge chapter on page 215 for a detailed description Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide The DDR FIC input interface is clocked by the FPGA fabric clock and the AXI transaction controller is clocked by MDDR_CLK from the FDDR clock controller Clock ratios between MDDR_CLK and DDR_FIC clock can vary Supported ratios are shown in Table 2 9 Clock ratios can be configured through Libero System on Chip SoC software or through the FDDR FACC DIVISOR RATIO register Table 2 9 FDDR CLK to FPGA Fabric Clock Ratios DIVISOR Af 1 0 DDR FIC DIVISOR 2 0 FDDR CLK FPGA FABRIC Clock Ratio 00 000 1 1 00 001 2 1 00 010 4 1 00 100 8 1 00 101 16 1 01 000 2 1 01 001 4 1 01 010 8 1 01 100 16 1 11 000 3 1 11 001 6 1 11 010 12 1 AXI Transaction Controller The AXI transaction controller receives 64 bit AXI transactions from DDR FIC and translates them into DDR controller transactions Figure 2 5 shows the bloc
243. r 4 Enable Read Buffer SWITCH Master Enable Write Combining Buffer 14 Enable Read Buffer IDC Master Enable Read Buffer 7 DOR Burst Size for Read Write Suffers 32 Bytes Cx Hep v Figure 3 7 Configuring MSS DDR Bridge for Use Model 2 SYSREG Control Registers Table 3 2 lists MSS DDR bridge Control registers in the SYSREG block Refer to the System Register Map chapter of the SmartFusion2 MSS User s Guide for a detailed description of each register and bit Table 3 2 e SYSREG Control Registers Register Flash Write Register Name Type Protect Reset Source Description DDRB BUF TIMER CR RW P Register SYSRESET N Uses a 10 bit timer interface to configure the timeout register in the write buffer module DDRB NB ADDR CR RW P Register SYSRESET N Indicates the base address of the non bufferable address region DDRB NB SIZE CR RW P Register SYSRESET N Indicates the size of the non bufferable address region DDRB CR RW P Register SYSRESET N MSS DDR bridge configuration register MSS IRQ ENABLE CR RW P Register SYSRESET N Configures interrupts to the Cortex M3 processor DDRB DS ERR ADR SR RO SYSRESET N MSS DDR bridge DS master error address status register DDRB HPD ERR ADR SR RO SYSRESET N MSS DDR bridge high performance DMA master error address status register DDRB SW ERR ADR SR RO SYSRESET N MSS DDR bridge switch error address status register DDRB BUF EMPTY SR RO SYSRESET
244. r as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded to 31 5 and 00000 to 4 0 Revision 2 155 lt gt Microsemi MDDR Subsystem DDR_FIC_HPB_ERR_ADDR_2_SR Table 1 230 DDR FIC HPB ERR ADDR 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M1_ERR_ADD 0x0 31 16 bits of DDR FIC M1 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded to 31 5 and 00000 to 4 0 DDR_FIC_SW_ERR_ADDR_1_SR Table 1 231 DDR FIC SW ERR ADDR 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR FIC M2 ERR ADD 0x0 Lower 16 bits Tag of write buffer for which error response is received is placed in this register The following values are
245. r dene ee 241 Website 21 2052 6eiepb bod be bid ske ped kes whe ed eke Paws ee biden hi badge kake ds 241 Contacting the Customer Technical Support Center 0 eee 241 Email 23 ott kates don fete tie 8 cogs ske inden macnn a ene niece lam dot Ett adekvat Maar bake Ea Ss 241 My Cases Le ee netted a E amet aa a tad eea se e ae e E O A 242 Outside the U S ised ceva edad araa k ee kite Baan a E e a sovne aa e a a eaa a dt 242 ITAR TechnicalSupportuasaaussaagasana sr dk eee eb eae E a E TETE E bade bakes Sh s 242 3 Revision 2 I Microsemi About This Guide Purpose This user s guide describes the high speed memory interfaces in SmartFusion 2 system on chip SoC field programmable gate array FPGA devices The high speed memory interfaces microcontroller subsystem double data rate MDDR subsystem and fabric double data rate FDDR subsystem provide access to double data rate DDR memories for high speed data transfers and code execution The DDR subsystems functionality configurations and their use models are discussed in this user s guide Contents This user s guide contains the following chapters Chapter 1 MDDR Subsystem e Chapter 2 Fabric DDR Subsystem e Chapter 3 DDR Bridge e Chapter 4 Soft Memory Controller Fabric Interface Controller Additional Documentation Table 1 lists additional documentation available on SmartFusion2 SoC FPGAs Refer to the web page for a complete and up to date listing www micro
246. r status information This helps to clear all the SECDED status information such as error counters and other SECDED registers The read value of this register is always 0 Revision 2 103 I Microsemi MDDR Subsystem PHY Configuration Register Summary Table 1 105 PHY Configuration Register Summary Reset Register Name Offset Type Source Description PHY DYN BIST TEST CR 0x200 RW PRESET N PHY BIST test configuration register PHY DYN BIST TEST ERRCLR 1 CR 0x204 RW PRESET N PHY BIST test error clear register PHY DYN BIST TEST ERRCLR 2 CR 0x208 RW PRESET N PHY BIST test error clear register PHY DYN BIST TEST ERRCLR 3 CR 0x20C RW PRESET NIPHY BIST test error clear register PHY BIST TEST SHIFT PATTERN 1 CR 0x210 RW PRESET N PHY BIST test shift pattern register PHY BIST TEST SHIFT PATTERN 2 CR 0x214 RW PRESET N PHY BIST test shift pattern register PHY BIST TEST SHIFT PATTERN 3 CR 0x218 RW PRESET N PHY BIST test shift pattern register PHY DYN LOOPBACK CR 0x21C RW PRESET NIPHY loopback test configuration register PHY BOARD LOOPBACK CR 0x220 RW PRESET N PHY Board loopback test configuration register PHY CTRL SLAVE RATIO CR 0x224 RW PRESET NIPHY control slice DLL slave ratio register PHY CTRL SLAVE FORCE CR 0x228 RW PRESET NIPHY control slice DLL slave force register PHY C
247. re should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_WRLVL_DQ_RATIO 0x0 49 48 bits of PHY_REG_WRLVL_DQ_RATIO Ratio value generated by the write leveling FSM for write data PHY_RDLVL_DQS_RATIO_1_SR Table 1 190 PHY RDLVL DQS RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_DQS_RATIO 0x0 15 0 bits of PHY_REG_RDLVL_DQS_RATIO Ratio value generated by read data eye training FSM PHY RDLVL DQS RATIO 2 SR Table 1 191 PHY RDLVL DQS RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_DQS_RATIO 0x0 31 16 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM PHY RDLVL DQS RATIO 3 SR Table 1 192 PHY RDLVL DQS RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely
248. red SSELETELET EEL BERESSESREEEE gt 5 Figure 2 10 Register Configuration Revision 2 185 lt gt Microsemi Fabric DDR Subsystem An example of FDDR register configurations for operating the DDR3 memory MT41J512M8RA with clock 333 MHz is shown in Table 2 11 Table 2 11 FDDR Configurations for Accessing DDR3 Memories at 333 MHz Register Name and Desired Value for Configured Value Field Value to be Loaded MT41J512M8RA DDRC_DYN_REFRESH_1_CR 0x27 de tRFC min Ox4F 237 ns Speculative refresh Ox1E 90 ns DDRC_DYN_REFRESH_2_CR 0x30 f tRFEI 0x61 0x61 97 32 clks 9 3 us DDRC INIT MR CR 0x520 Write recovery 3 DLL reset Yes CAS latency 6 Burst type Sequential Burst length 8 DDRC INIT EMR CR 0x44 Additive latency AL CL 1 Write levelization Enable DDRC DRAM BANK TIMING PARAM CR tRC 0x33 153 ns tFAW 0x20 96 ns DDRC_DRAM_RD_WR_LATENCY_CR 0x86 WL RL DDRC_DRAM_RD_WR_PRE_CR 0x1E5 Rd2pre 0x15 63 ns Wr2pre 0x11 51 ns DDRC_DRAM_MR_TIMING_PARAM_CR 0x58 tMOD 0xB 11 clks DDRC DRAM RAS TIMING CR 0x10F tRAS max OxF 15 1024 46 us tRAS min 0x8 24 ns DDRC DRAM RD WR TRNARND TIME CR 0x178 Rd2wr 0xB 11 clks Wr2rd 0x18 24 clks DDRC_DRAM_T_PD_CR 0x33 tXP 3 3 ciks tCKE 3 3 ciks DDRC DRAM BANK ACT TIMING CR 0x1947 tRP 7 21ns tRRD 4 12ns 186
249. red using the MSS configurator 3 Configure the MDDR and select the AXI interface as shown in Figure 1 16 In this example the design is created to access DDR3 memory with a 32 bit data width A MSS External Memory Configurator External Memory Type Interface Configuration Application accesses Double Data Rate Memory Memory Configuration Type DDR3 gt width 32 v ECC Memory Access From MSS V From FPGA Fabric Using an AXI Interface Using a Single AHBLite Interface Using Two AHB Interfaces Figure 1 16 MSS External Memory Configuration Revision 2 43 I Microsemi MDDR Subsystem 4 Configure FIC 2 Figure 1 17 to enable the MDDR subsystem APB interface for configuring the MDDR registers using APB master in the FPGA fabric 8 I MSS Fabric Interface Controller FIC 2 Configuratc Configuration Initialize Peripherals Using Cortex M3 v MSS DDR W Fabric DDR and or SERDES Blocks Figure 1 17 Configuring FIC 2 5 Configure the MSS CCC for MDDR CLK and DDR SMC FIC CLK In Figure 1 18 the MDDR clock is configured to 333 MHz and M3_CLK is configured to 111 MHz 8 I MSS Clock Conditioning Circuitry Configurator System Clocks Advanced Options Clock Source CLK_BASE 111 000 MHz 4 Monitor FPGA Fabric PLL Lock CLK BASE PLL LOCK Cortex M3 and MSS Main Clock M3 CLK 111 MHz 111 000 MHz MDDR Clocks v MDDR CLK M3_CLK 3 Y 333 000 MHz W DDR SMC FIC CLK MDDR CK I 111 000
250. reserved across a read modify write operation 7 0 DDRC_REG_ECC_SYNDROMES 0x0 71 64 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Table 1 96 DDRC LCE ADDRESS 1 SR DDRC LCE ADDRESS 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_ROW 0x0 Row where the SECDED error occurred 100 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_LCE_ADDRESS_2_SR Table 1 97 DDRC LCE ADDRESS 2 SR Bit Reset Number N
251. ress bits 0 to 15 are mapped for system address bit 15 to system address bit 27 To map the bank bitO to address 15 the field is configured to 9 as the base value is 6 Similarly the other bank address bits are configured DDRC_ADDR_MAP_ROW_1_CR 0x9999 DDRC_ADDR_MAP_ROW_2_CR 0x9FF Note The MDDR can access the 4 GB address space 0x00000000 OxFFFFFFFF But in this example 512 MB 0x00000000 0x1FFFFFFF DDR3 SDRAM is connected to the 16 address lines of MDDR The memory visible in the other memory space is mirrored of this 512 MB memory DDR Mode Registers After reset the DDR controller initializes the mode registers of DDR memory with the values in the following registers The mode registers must be configured according to the specification of the external DDR memory when the controller is in soft reset e DDRC INIT MR CR e DDRC INIT EMR CR e DDRC INIT EMR2 CR e DDRC INIT EMR3 CR The T MOD and T MRD bits in DDRC DRAM MR TIMING PARAM CR must be configured to the required delay values T MOD and T MRD are delays between loading the mode registers SECDED To enable SECDED mode set the REG DDRC MODE bits to 101 in DDRC MODE CR The PHY DATA SLICE IN USE CR register must be configured to enable data slice 4 of the PHY The register value REG DDRC LPR NUM ENTRIES in the performance register DDRC PERF PARAM 1 CR must be increased by 1 to the value used in Normal mode without SECDED Read Write Latencies The read and write lat
252. roducts the value of a reserved bit should be preserved across a a read modify write operation 15 12 REG DDRC ADDRMAP COL B8 0x0 Full bus width mode Selects column address bit 9 Half bus width mode Selects column address bit 11 Quarter bus width mode Selects column address bit 12 Valid range 0 to 7 and 15 Internal base 8 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 Note Per JEDEC DDR2 specification column address bit 10 is reserved for indicating auto precharge and hence no source address bit can be mapped to column address bit 10 11 8 REG_DDRC_ADDRMAP_COL_B9 0x0 Full bus width mode Selects column address bit 11 Half bus width mode Selects column address bit 12 Quarter bus width mode Selects column address bit 13 Valid range 0 to 7 and 15 Internal base 9 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 7 4 REG DDRC ADDRMAP COL B10 0x0 Full bus width mode Selects column address bit 12 Half bus width mode Selects column address bit 13 Quarter bus width mode Unused Should be set to 15 Valid range 0 to 7 and 15 Internal base 10 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 10 is set to 0
253. roller Table 4 1 e SMC FIC 64 bit AXI Port List continued Signal Direction Polarity Description MDDR SMC AXI M AWLEN 3 0 Output Indicates burst length The burst length gives the exact number of transfers in a burst This information determines the number of data transfers associated with the address 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 MDDR SMC AXI M AWBURST 1 0 Output Indicates burst type The burst type coupled with the size information provides details on how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved MDDR SMC AXI M AWID 3 0 Output Indicates identification tag for the write address group of signals MDDR SMC AXI M WDATA 63 0 Output Indicates write data MDDR SMC AXI M WID 3 0 Output Indicates ID tag of the write data transfer The SMC AX164 WID value must match the SMC AX164 AWID value of the write transaction MDDR SMC AXI M WSTRB 7 0 Output Indicates which byte lanes to update in memory MDDR SMC AXI M ARID 3 0 Output Indicates identification tag for the read address group of signals MDDR SMC AXI M ARADDR 31 0 Output Indicates initial address o
254. s MDDR DQ ECC 3 0 when data width is x32 Data lines MDDR_DQ_ECC 1 0 when data width is x16 Data line MDDR_DQ_ECC 0 when data width is x8 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 1 Supported Memory DDR2 DDR3 and LPDDR1 Configurations SmartFusion2 Devices M2S005 M2S0 Width 10 M2S025 M2S050 Memory in SECDED VF400 VF 400 M2S050 M2S075 M2S080 M2S Density Width Mode FG484 FG484 FG896 FG484 120 FC1152 128M x32 x36 v 7 v x16 x18 v v v v v x8 x9 7 256M x32 x36 v v x16 x18 v V v v v x8 x9 v J 512M x32 x36 v v x16 x18 v v v v v x8 x9 f v 1G x32 x36 v 7 v x16 x18 v v v v v x8 x9 v v 2G x32 x36 v v x16 x18 v v v v v x8 x9 v 4G x32 x36 x16 x18 x8 x9 v Performance Table 1 2 shows the maximum and minimum data rates supported by MDDR subsystem for supported memory types Table 1 2 e DDR Speeds Memory Type Maximum Data Rate Mbps LPDDR1 400 Mbps 200 MHz DDR2 667 Mbps 333 33 MHz DDR3 667 Mbps 333 33 MHz Revision 2 I Microsemi MDDR Subsystem I O Utilization Table 1 3 shows the I O utilization for SmartFusion2 devices corresponding to supported bus widths The remaining I Os in bank 0 can be used for general purposes Table 1 3 I O Utiliz
255. s to access the FDDR from the AXI master in the FPGA fabric 1 Instantiate the FDDRC macro in the SmartDesign canvas 2 Configure the FDDR and select the AXI interface as shown in Figure 2 14 In this example the design is created to access DDR3 memory with a 32 bit data width The FDDR clock is configured to 333 MHz and DDR FIC is configured to 111 MHz ir Fabric Extemal Memory DDR Conuoler Conqueror a Configuration Memory Configuration Memory Access FPGA Fabric Interface Using an AXI 64 Interface v FDDR_CLK Frequency MHz 333 DDR FIC CLK_BASE Divisor 13 w 111 MHz FPLL Configuration Supply Voltage 2 54 Use FAB_PLL_LOCK Interrupts Enable Interrupts Edit Registers ur T Figure 2 14 FDDR Configuration 194 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide 3 Instantiate the clock resources FAB_CCC and chip oscillators in the SmartDesign canvas and configure as required In this example the fabric CCC is configured to generate 111 MHz as shown in Figure 2 15 E FAB CCC Configurator Basic Advanced PLL Options Basic Options 100 MHz Dedicated Input Pad 0 v Figure 2 15 Fabric CCC Configuration 4 Instantiate user AXI master logic in the SmartDesign canvas to access the FDDR through the AXI interface Ensure that the AXI master logic accesses the FDDR aft
256. se value PHY_DLL_SLAVE_VALUE_2_SR Table 1 200 PHY_DLL_SLAVE_VALUE_2 SR Bit Number Name Reset Value Description 31 11 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_DLL_SLAVE_VALUE 0x0 26 16 bits of PHY REG STATUS DLL SLAVE VALUE Shows the current coarse and fine delay values measured for a full cycle shift by each master DLL This is a 27 bit register 9 bits for each DLL 1 0 Fine value 8 2 Coarse value 142 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY STATUS OF IN DELAY VAL 1 SR Table 1 201 PHY STATUS OF IN DELAY VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_OF_IN_DELAY_VALUE 0x0 15 0 bits of PHY REG STATUS OF IN DELAY VALUE The coarse and fine values going into the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 PHY_STATUS_OF_IN_DELAY_VAL_2_SR Table 1 202 PHY STATUS OF IN D
257. semi com soc products smartfusion2 docs aspx Table 1 Additional Documents 5 EE gt gt OOOO SmartFusion2 SoC FPGA Product Brief This product brief provides an overview of SmartFusion2 family features and development tools SmartFusion2 SoC FPGA Datasheet This datasheet contains SmartFusion2 DC and switching characteristics SmartFusion2 Pin Descriptions This document contains SmartFusion2 pin descriptions package outline drawings and links to pin tables in Excel format SmartFusion2 FPGA Fabric Architecture User s Guide SmartFusion2 SoC FPGAs integrate fourth generation flash based FPGA fabric The FPGA fabric composed of 4 input look up table LUT logic elements includes embedded memories and Mathblocks for DSP processing capabilities This document describes the SmartFusion2 FPGA fabric architecture embedded memories Mathblocks fabric routing and I Os SmartFusion2 Microcontroller Subsystem User s SmartFusion2 devices integrate a hard microcontroller Guide subsystem MSS The MSS consists of a ARM Cortex M3 processor with embedded trace macrocell ETM instruction cache embedded memories DMA engines communication peripherals timers real time counter RTC general purpose I Os and FPGA fabric interfaces This document describes the SmartFusion2 MSS and its internal peripherals Revision 2 5 I Microsemi About This Guide Table 1 Additional Documents continued BR NL SmartFusion2 SoC FP
258. served bit should be preserved across a read modify write operation 12 0 PHY REG BIST ERR 0x0 44 32 bits of PHY_REG_BIST_ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG_PHY_BIST_ERR_CLR port must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bits PHY WRLVL DQS RATIO 1 SR Table 1 182 PHY WRLVL DQS RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQS_RATIO 0x0 15 0 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS 136 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WRLVL_DQS_RATIO_2_SR Table 1 183 PHY WRLVL DQS RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLV
259. set High during the training leveling process when DDRC_DFI_WRLVL_EN DDRC DFI RDLVL EN DDRC DFI RDLVL GATE EN PORT is set High 132 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY USE RANKO DELAYS CR Table 1 173 PHY USE RANKO0 DELAYS CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY USE RANKO DELAYS 0x0 Delay selection This applies to multi rank designs only 1 Rank 0 delays are used for all ranks 0 Each rank uses its own delay This port must be set High when write latency lt 5 PHY USE LVL TRNG LEVEL CTRL CR Table 1 174 PHY USE LVL TRNG LEVEL CTRL CR Bit Number Name Reset Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation REG PHY USE WR LEVEL 0x0 Write leveling training control 0 Use register programmed ratio values 1 Use ratio for delay line calculated by write leveling Note This port must be set to 0 when PHY is not working in DDR3 mode REG_PHY_USE_RD_DQS_GATE_L
260. size of request from the master Each read buffer is associated with one specific master for reading it does not check the read addresses of other masters to determine whether that data can be read from the read buffer there is no cross buffer read access Figure 3 4 on page 219 shows the flow chart for read operation Write request 1 Write Request matching with WCB ag WCB empty Buffer the data based on WCB tag WCB full timeout Write the data in WCB to AXI slave Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Read request 1 Other master is holding the read transaction YES Read buffer is empty on bufferable read request Read address is Send read request to arbiter with burst size matching with buffer of read buffer size Send expected word to tag AHB Master Send read request to arbiter Make AHB master ready High Initiate single read transaction Make ready high Read data from buffer and send it to Master Figure 3 4 Flow Chart for Read Operation The read buffer is invalidated under the following conditions If the address from the master is outside the TAG region the current data in the read buffer is invalidated TAG mismatch To ensure proper data coherency every master s write address is tracked If an address matches that of the read buffer TAG the read entry is invalidated
261. ss a read modify write operation 5 REG DDRC DFI RD DATA EYE TRAIN 0x0 1 Read Data Eye training mode has been enabled as part of the initialization sequence 4 REG DDRC DFI RD DQS GATE LEVEL 0x0 1 Read DQS Gate Leveling mode has been enabled as part of the initialization sequence Only present in designs that support DDR3 devices 3 0 REG DDRC DFI RDLVL MAX X1024 0x0 12 8 bits Revision 2 Read leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI RDLVL RESP to a read leveling enable signal DDRC DFI RDLVL EN or DDRC DFI RDLVL GATE EN Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units 1 024 clocks 87 lt gt Microsemi MDDR Subsystem DDRC DFI CTRLUPD TIME INTERVAL CR Table 1 78 DDRC DFI CTRLUPD TIME INTERVAL CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG DDRC DFI T CTRLUPD INTERVAL MIN X1024 0x10 This is the minimum amount of time between controller initiated DFI update requests which will be executed whenever the controller is idle Set this number higher to reduce the frequency of update req
262. ss bit 5 Quarter bus width mode Selects column address bit 6 Valid range 0 to 7 Internal base 3 The selected address bit is determined by adding the internal base to the value of this field 7 4 REG DDRC ADDRMAP COL B4 0x0 Full bus width mode Selects column address bit 5 Half bus width mode Selects column address bit 6 Quarter bus width mode Selects column address bit 7 Valid Range 0 to 7 Internal base 4 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field 3 0 REG_DDRC_ADDRMAP_COL_B7 0x0 Full bus width mode Selects column address bit 8 Half bus width mode Selects column address bit 9 Quarter bus width mode Selects column address bit 11 Valid range 0 to 7 and 15 Internal base 7 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 Note Per JEDEC DDR2 specification column address bit 10 is reserved for indicating auto precharge and hence no source address bit can be mapped to column address bit 10 Revision 2 63 lt gt Microsemi MDDR Subsystem DDRC ADDR MAP COL 2 CR Table 1 34 e DDRC ADDR MAP COL 2 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future p
263. st size of 16 or 32 bytes Each WCB maintains a base address tag that stores the base address of the data to be combined in the buffer For each write transaction the address is compared with the WCB tag If the address matches the tag data is combined into the buffer The WCB writes to the correct byte location based on the offset address of the data WCB can also be disabled if buffering is not required The WCB has a 10 bit timer down counter which starts when the first bufferable write data is loaded into the WCB The timer starts decrementing its value at every positive edge of the AHB clock and when it reaches zero the data in the WCB is written to the AXI slave The WCB checks for any other master that has initiated a read to the same address for which data is already present in a write buffer or for which a write operation is ongoing If the address for a read request matches the write buffer tag the read request is held until the buffer is written completely to the AXI slave Revision 2 217 I Microsemi DDR Bridge Figure 3 3 shows the flowchart for WCB operation Figure 3 3 WCB Operation 218 Read Buffer The DDR bridge has a read buffer for each master to hold the fetched DDR burst data Each read buffer has a configurable burst size of 16 or 32 bytes For AHB Interface 0 the buffer length is fixed to 32 bytes The read buffer initiates a DDR burst size request for reads in the bufferable region regardless of the
264. ster PHY WR DATA SLAVE DLL VAL 2 SR 0x3A8 RO PRESET N Write DATA slave DLL status register PHY WR DATA SLAVE DLL VAL 3 SR Ox3AC RO PRESET N Write DATA slave DLL status register PHY FIFO WE SLAVE DLL VAL 1 SR 0x3B0 RO PRESET N FIFO WE slave DLL status register PHY FIFO WE SLAVE DLL VAL 2 SR 0x3B4 RO PRESET N FIFO WE slave DLL status register PHY FIFO WE SLAVE DLL VAL 3 SR 0x3B8 RO PRESET N FIFO WE slave DLL status register PHY WR DQS SLAVE DLL VAL 1 SR 0x3BC RO PRESET N Write DQS slave DLL status register PHY WR DQS SLAVE DLL VAL 2 SR 0x3C0 RO PRESET N Write DQS slave DLL status register PHY WR DQS SLAVE DLL VAL 2 SR 0x3C4 RO PRESET N Write DQS slave DLL status register PHY CTRL SLAVE DLL VAL SR 0x3C8 RO PRESET NI DLL controller status register Revision 2 107 I Microsemi MDDR Subsystem PHY Configuration Register Bit Definitions PHY DYN BIST TEST CR Table 1 106 PHY DYN BIST TEST CR Bit Number Name Reset Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation REG_PHY_AT_SPD_ATPG 0x0 1 Test with full clock speed but lower coverage 0 Test with lower clock speed but higher coverage REG_PHY_BIST_ENABLE 0x0 Enable the internal BIST generation and checker logic when this port is set High S
265. ster Bit Definitions DDR FIC NB ADDR CR Table 1 221 DDR FIC NB ADDR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR FIC NB ADD 0x0 This indicates the base address of the non bufferable address region DDR_FIC_NBRWB_SIZE_CR Table 1 222 DDR FIC NBRWB SIZE CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_WCB_SZ 0x0 Configures write buffer and read buffer size as per DDR burst size This port is common for all buffers Buffers can be configured to 16 byte or 32 byte size 0 Buffer size is configured to 16 bytes 1 Buffer size is configured to 32 bytes Revision 2 151 lt gt Microsemi MDDR Subsystem Table 1 222 DDR FIC NBRWB SIZE CR continued Bit Reset Number Name Value Description 7 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 DDR_FIC_NUBF_SZ 0x0 This signal i
266. t should be preserved across a read modify write operation REG_DDRC_MR_WR 0x0 When 1 is written and DDRC_REG_MR_WR_BUSY is Low a mode register read or write operation is started There is no need for the CPU to set this back to zero This bit always reads as zero Controller accepts this command if this signal is detected High and DDRC_REG_MR_WR_BUSY is detected Low 2 1 REG_DDRC_MR_ADDR REG_DDRC_MR_TYPE 0x0 0x0 Address of the Mode register that is to be written to 00 MRO 01 MR1 10 MR2 11 MR3 Indicates whether the Mode register operation is read or write 1 Read 0 Write DDRC_MODE_REG_DATA_CR Table 1 56 DDRC MODE REG DATA CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_MR_DATA 0x0 Mode register write data 76 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_PWR_SAVE_1_CR Table 1 57 DDRC PWR SAVE 1 CR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify wr
267. te 0x0 0x0 32 DDRC_ODT_PARAM_1_CR 0x070 read write 00 0x0 32 DDRC_ODT_PARAM_2_CR 0x074 read write 0x0 0x0 32 DDRC ADDR MAP COI 3 CR M078 read write 0 Ox 32 Register Field Description DDRC_DYN_SOFT_RESET_CR REG_DDRC_SOFT_RSTB This is a Soft Reset 0 Puts the Controller into reset 1 Takes the Controller out of Reset Controller should be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APB configuration registers once the soft reset bit is asserted the APB register should be modified as required Figure 1 10 Edit Registers Configuration files for accessing DDR3 memory on SmartFusion2 Development kit can be downloaded from www microsemi com soc documents MDDR3_16Bit_SB zip Configuration files for accessing LPDDR memory on SmartFusion2 Starter kit can be downloaded from www microsemi com soc documents LPDDR_Emcraft_Config zip Revision 2 31 lt gt Microsemi MDDR Subsystem An example of MDDR register configurations for operating the DDR3 memory MT41J512M8RA with clock 333 MHz is shown in Table 1 12 Table 1 12 MDDR Configurations for Accessing DDR3 Memories at 333 MHz Desired Value Register Name and Configured Value Field Value to be Loaded ENORA DDRC_DYN_REFRESH_1_CR 0x27 de tRFC min 0x4F 237 ns Speculative refresh 0
268. tes read requests from read buffers and grants access to one of the requesting masters depending on its priority Combinations of fixed and round robin priorities are assigned to the masters as below e Master Interface 0 and Master Interface 1 have fixed first and second priority Round robin between Master Interface 2 and Master Interface 3 for second and third priority The RAC also routes the read data from the AXI slave MDDR or FDDR to the corresponding master based on the Read data ID Locked Transactions The DDR bridge masters can initiate locked transfers by asserting the HMASTLOCK signal of the corresponding AHB interface These locked transactions are initiated only after all the pending write and read transactions are completed The arbiter has a 20 bit up counter for detecting a lock timeout condition The counter starts counting when a locked transaction is initiated on the bus When the counter reaches its maximum value an interrupt is generated to the Cortex M3 processor The error routine has to be stored in either eNVM or eSRAM for the Cortex M3 processor to fetch the interrupt service routine ISR without going through the DDR bridge As part of the ISR the Cortex M3 processor reads the SYSREG registers to identify the master and take appropriate action to release the arbiter from dead lock The interrupt can be cleared by setting the DDR_LOCKOUT bit in the MSS_EXTERNAL_SR from the SYSREG block If the interrupt is cleared and
269. the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY REG STATUS WR DATA SL AVE DLL VALUE Delay value applied to write data slave DLL PHY WR DATA SLAVE DLL VAL 3 SR Table 1 212 PHY WR DATA SLAVE DLL VAL 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 0x0 44 32 bits of Revision 2 PHY REG STATUS WR DATA SL AVE DLL VALUE Delay value applied to write data slave DLL 147 lt gt Microsemi MDDR Subsystem PHY_FIFO_WE_SLAVE_DLL_VAL_1_SR Table 1 213 PHY FIFO WE SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 15 0 bits of PHY_REG_STATUS_FIFO_WE_SLA VE_DLL_VALUE Delay value applied to FIFO WE slave DLL PHY_FIFO_WE_SLAVE_DLL_VAL_2_SR Table 1 214 PHY FIFO WE SLAVE DLL VAL 2 SR Bit Reset Num
270. the DDR bridge using the DDR_FIC_HPD_SW_RW_EN_CR register Configure buffer size to 32 bytes or 16 bytes using the DDR_FIC_NBRWB_SIZE_CR register Configure the non bufferable address using the DDR_FIC_NB_ADD register Configure the non bufferable size using the DDR_FIC_NBRWB_SIZE_CR register Configure the timeout value for each write buffer using the DDR FIC LOCK TIMEOUTVAL 1 CR and DDR FIC LOCK TIMEOUTVAL 2 CR registers Set the timeout value to maximum or a non Zero value The configuration registers for the MDDR DDR bridge and FDDR DDR bridge are also listed under the DDR FIC registers section in the MDDR and FDDR chapters Revision 2 221 amp Microsemi DDR Bridge Figure 3 6 222 Use Model 1 High Speed Data Transactions from Cortex M3 Processor This use model shows the use of the DDR bridge for increasing throughput from the Cortex M3 processor to external DDR memories The Cortex M3 processor performs only the single read and write transactions not the burst transactions The DDR bridge converts these single transactions into burst transactions and further increases the throughput The buffers for DS and IDC masters are enabled for this and the non bufferable size is selected as None as shown in Figure 3 6 R Configuring DORB MSS DDR8 0 0500 T T baa Configuration Write Buffer Time Out Counter Oxf Non Bufferable Region Address Upper 16 bits 0xA000 D Master Enable Write Combining Buffer v7 Enable Re
271. the value of a reserved bit should be preserved across a read modify write operation 10 0 REG DDRC LPR MAX STARVE X32 0x0 11 1 bits of REG DDRC HPR MAX STARVE X32 Number of clocks that the LPR queue can be starved before it goes critical Unit 32 clocks 82 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_WR_QUEUE_PARAM_CR Table 1 68 DDRC WR QUEUE PARAM CR Bit Number Name Reset Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 4 REG_DDRC_W_MIN_NON_CRITICAL 0x0 Number of clocks that the write queue is guaranteed to be non critical Unit 32 clocks 3 0 REG_DDRC_W_XACT_RUN_LENGTH DDRC_PERF_PARAM_2_CR Table 1 69 DDRC PERF PARAM 2 CR Bit Number Name 0x0 Reset Value Number of transactions that are serviced once the WR queue goes critical is the smaller of this value and number of transactions available Units Transactions Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 REG_DDRC_BURSTCHOP 0x0
272. tically issuing ZQ calibration short ZQCS commands to DDR3 devices Not considered if REG DDRC DIS AUTO ZQ 1 Units 1 024 clock cycles This is only present for implementations supporting DDR3 devices Revision 2 79 lt gt Microsemi MDDR Subsystem DDRC_PERF_PARAM_1_CR Table 1 63 DDRC PERF PARAM 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 13 REG_DDRC_BURST_RDWR 0x0 001 Burst length of 4 010 Burst length of 8 100 Burst length of 16 All other values are reserved This controls the burst size used to access the DRAM This must match the BL mode register setting in the DRAM The DDRC and AXI controllers are optimized for a burst length of 8 The recommended setting is 8 A burst length of 16 is only supported for LPDDR1 Setting to 16 when using LPDDR1 in half quarter bus mode may boost performance For systems that tend to do many single cycle random transactions a burst length of 4 may slightly improve system performance 12 Reserved 0x0 This bit must always be set to zero 11 5 REG DDRC RDWR IDLE GAP 0x04 When the preferred transaction store is empty for this many clock cycles switch to the alternate transaction store if it is no
273. to DRAM 10 Quarter DQ bus width to DRAM 11 Reserved Note The half bus width modes are only supported when the DRAM bus width is a multiple of 16 Revision 2 61 lt gt Microsemi MDDR Subsystem DDRC_ADDR_MAP_BANK_CR Table 1 31 DDRC ADDR MAP BANK CR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 7 4 REG DDRC ADDRMAP BANK BO REG DDRC ADDRMAP BANK B1 0x0 0x0 Selects the address bits used as bank address bit 0 Valid Range 0 to 14 Internal Base 2 The selected address bit for each of the bank address bits is determined by adding the internal base to the value of this field Selects the address bits used as bank address bit 1 Valid Range 0 to 14 Internal Base 3 The selected address bit for each of the bank address bits is determined by adding the internal base to the value of this field 3 0 REG DDRC ADDRMAP BANK B2 0x0 Selects the address bits used as bank address bit 2 Valid Range 0 to 14 and 15 Internal Base 4 The selected address bit is determined by adding the internal base to the value of this field If set to 15 bank address bit 2 is set to 0 DDRC_ECC_DATA_MASK_CR Table 1 32 DDRC ECC DATA MASK CR
274. to same bank specifications WL BL 2 tWR approximately 8 cycles 15 ns 14 clocks 400 MHz and less for lower frequencies Unit Clocks where WL Write latency BL Burst length This must match the value programmed in the BL bit of the mode register to the DRAM tWR Write recovery time This comes directly from the DRAM specs 4 0 REG_DDRC_RD2PRE 0x0 tRTP Minimum time from read to precharge of same bank specification tRTP for BL 4 and tRTP 2 for BL 8 tRTP 7 5 ns Unit clocks DDRC_DRAM_MR_TIMING_PARAM_CR Table 1 47 DDRC DRAM MR TIMING PARAM CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 3 REG_DDRC_T_MOD 0x0 Present for DDR3 only replaces REG DDRC T MRD functionality when used with DDR3 devices The mode register set command updates delay in number of clock cycles This is required to be programmed even when a design that supports DDR3 is running in DDR2 mode minimum is the larger of 12 clock cycles or 15 ns 2 0 REG_DDRC_T_MRD 0x0 tMRD Cycles between load mode commands Not used in DDR3 mode 70 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDRC_DRAM_RAS_TIMING_CR Table 1 48 D
275. training after reset The order of training sequence is given below e Write leveling e Read leveling DQS gate training Data eye training Write Leveling The write leveling process locates the delay at which the write DQS rising edge aligns with the rising edge of the memory clock By identifying this delay the system can accurately align the write DQS within the memory clock The DDR controller drives subsequent write strobes for every write to write delay specified by REG DDRC WRLVL WW until the PHY drives the response signal High Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide The DDR controller performs the following steps 1 Sets up the DDR memory in Write leveling mode by sending the appropriate MR1 command 2 Sets the write leveling enable bit for the PHY and sends out periodically timed write level strobes to the PHY while sending out DEVSEL commands on the DDR memory command interface 3 Once the PHY completes measurements it sets the write level response bits which then signal the DDRC to stop the leveling process and lower the write leveling enable bit If the REG DDRC DFI WR LEVEL EN bit is configured to 1 the write leveling enabled as part of the initialization sequence Read Leveling There are two read leveling modes 1 DQS gate training The purpose of gate training is to locate the optimum delay that can be applied to the DQS gate such that it funct
276. transaction AXI 8 ARBURST 1 0 Input Indicates burst type The burst type coupled with the size information details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved AXI 8 ARID 3 0 Input Indicates identification tag for the read address group of signals AXI 8 ARLEN 3 0 Input Indicates burst length The burst length gives the exact number of transfers in a burst 0000 1 0001 0010 0011 0100 0101 0110 0111 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 o Noon AUN 168 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 2 5 e FDDR AXI Slave Interface Signals continued Signal Name Direction Polarity Description AXI S ARLOCK 1 0 Input Indicates lock type This signal provides additional information about the atomic characteristics of the read transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved AXI S ARSIZE 1 0 Input Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 AXI S ARVALID Input High Indicates the validity of read address and control information 1 Address and
277. tween CLK and DQS at the DRAM Revision 2 129 lt gt Microsemi MDDR Subsystem PHY_WRLVL_INIT_RATIO_3_CR Table 1 167 PHY WRLVL INIT RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 47 32 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM PHY_WRLVL_INIT_RATIO_4_CR Table 1 168 PHY_WRLVL_INIT_RATIO_4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WRLVL_INIT_MODE 0x0 49 48 bits of REG_PHY_WRLVL_INIT_MODE The user programmable init ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE PORT is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS
278. uests which can have a small impact on the latency of the first read request when the controller is idle Units 1 024 clocks 7 0 REG_DDRC_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0x16 This is the maximum amount of time between controller initiated DFI update requests This timer resets with each update request when the timer expires traffic is blocked for a few cycles PHY can use this idle time to recalibrate the delay lines to the DLLs The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors Updates are required to maintain calibration over PVT but frequent updates may impact performance Units 1 024 clocks DDRC_DYN_SOFT_RESET_ALIAS_CR Table 1 79 DDRC DYN SOFT RESET ALIAS CR Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 AXIRESET 0x1 Set when main AXI reset signal is asserted Reads and writes to the dynamic registers should not be carried out This is a read only bit 88 Revision 2 Table 1 79 DDRC DYN SOFT RESET ALIAS CR continued Bit Number lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Name Reset Value Description 1 RESET APB REG 0x0 Full soft reset If this
279. uld not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 CFGR_LOCK_TIMEOUT_REG 0x0 15 0 bits of CFGR LOCK TIMEOUT REG Lock timeout 20 bit register Indicates maximum number of cycles a master can hold the bus for locked transfer If master holds the bus for locked transfer more than the required cycles an interrupt is generated 158 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR_LOCK_TIMEOUTVAL_2_CR Table 1 237 DDR LOCK TIMEOUTVAL 2 CR Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 CFGR_LOCK_TIMEOUT_REG 0x0 19 16 bits of CFGR LOCK TIMEOUT REG Lock timeout 20 bit register Indicates maximum number of cycles a master can hold the bus for locked transfer If master holds the bus for locked transfer more than the required cycles an interrupt is generated DDR FIC LOCK TIMEOUT EN CR Table 1 238 DDR FIC LOCK TIMEOUT EN CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a
280. umber Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 7 REG_DDRC_T_RFC_MIN 0x23 tRFC min Minimum time from refresh to refresh or activate specification 75 ns to 195 ns Unit clocks 6 REG_DDRC_REFRESH_UPDATE_LEVEL 0x0 Toggle this signal to indicate that the refresh register s have been updated The value is automatically updated when exiting soft reset so it does not need to be toggled initially 5 REG_DDRC_SELFREF_EN 0x0 If 1 then the controller puts the DRAM into self refresh when the transaction store is empty 4 0 REG_DDRC_REFRESH_TO_X32 0x8 Speculative refresh Revision 2 59 lt gt Microsemi MDDR Subsystem DDRC_DYN_REFRESH_2_CR Table 1 27 DDRC DYN REFRESH 2 CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 3 REG DDRC T RFC NOM X32 0x52 tREFI Average time between refreshes specification 7 8 us Unit multiples of 32 clocks 2 0 REG_DDRC_REFRESH_BURST 0x0 The programmed value plus one is the number of refresh timeouts that is allowed to accumulate
281. updated in this register as per buffer size Buffer size DDR FIC M2 ERR ADD 31 0 16 bits TAG 0000 32 bits TAG 27 1 00000 DDR FIC SW ERR ADDR 2 SR Table 1 232 DDR FIC SW ERR ADDR 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M2_ERR_ADD 0x0 31 16 bits of DDR FIC M2 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded to 31 5 and 00000 to 4 0 156 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide DDR_FIC_HPD_SW_WRB_EMPTY_SR Table 1 233 DDR FIC HPD SW WRB EMPTY SR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_M1_RBEMPTY 0x0 1 Read buffer of AHBL master1 does not have valid data 5 Reserved 0x0 Software should not rely on the value of a reserved bit
282. upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Revision 2 97 lt gt Microsemi MDDR Subsystem DDRC_LCE_SYNDROME_3_SR Table 1 93 DDRC LCE SYNDROME 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC REG ECC SYNDROMES 0x0 47 32 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 98 Revision 2 Table 1 94 e DDRC LCE SYNDROME 4 SR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interf
283. urator in the Libero SoC design software Figure 1 9 shows the MSS External Memory Configurator which give the following choices for the external memory interface type 1 Application accesses DDR 2 Application accesses SDRM through MSS memory access This option must be selected to enable SMC FIC For more information on using SMC FIC mode refer to the Soft Memory Controller Fabric Interface Controller chapter on page 227 E MSS External Memory Configurator External Memory Type Interface Configuration Application accesses Double Data Rate Memory Memory Configuration Type DDR2 v Width 32 l ECC Memory Access From MSS From FPGA Fabric Edit Registers Figure 1 9 MSS External Memory Configuration 30 Application Accesses DDR This option must be selected for accessing the external DDR memory through the MDDR subsystem Selecting this enables the configurator to configure the DDR memory type and fabric master interface type Depending on the application requirement select the memory type as DDR2 DDR3 or LPDDR The width of the memory can be selected as 32 bit 16 bit or 8 bit and the SECDED ECC can be enabled or disabled To access the MDDR from the FPGA fabric select From FPGA Fabric and the type of interface as AXI single AHBLite or two AHB Interfaces On completion of the configuration the selected interface is exposed in SmartDesign The user logic in the FPGA fabric can access the DDR mem
284. ure products the value of a reserved bit should be preserved across a read modify write operation 10 0 REG DDRC HPR MAX STARVE X32 0x0 11 1 bits of REG DDRC HPR MAX STARVE X32 Number of clocks that the HPR queue can be starved before it goes critical Unit 32 clocks Bit Number DDRC LPR QUEUE PARAM 1 CR Table 1 66 DDRC LPR QUEUE PARAM 1 CR Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 REG_DDRC_LPR_MAX_STARVE_X32 0x0 Lower 1 bit of REG DDRC LPR MAX STARVE X32 Number of clocks that the LPR queue can be starved before it goes critical Unit 32 clocks 14 4 REG DDRC LPR MIN NON CRITICAL 0x0 Number of clocks that the LPR queue is guaranteed to be non critical Unit 32 clocks 3 0 REG_DDRC_LPR_XACT_RUN_LENGTH 0x0 Number of transactions that are serviced once the LPR queue goes critical is the smaller of this value and number of transactions available Units Transactions DDRC_LPR_QUEUE_PARAM_2_CR Table 1 67 DDRC LPR QUEUE PARAM 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products
285. ure the registers or import the register configuration file according to the application requirements Refer to the MDDR Subsystem Features Configuration section on page 36 to configure the necessary registers Configure the MSSCCC for MDDR_CLK In this example MDDR_CLK is configured to 333 MHz as shown in Figure 1 24 E MSS Clock Conditioning Circuitry Configurator System Clocks Advanced Options Clock Source CLK_BASE 50 000 MHz V Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK Cortex M3 and MSS Main Clock M3 CLK 111 MHz 111 000 MHz MDDR Clocks v MDDR CLK M3_CLK 3 333 000 MHz Figure 1 24 Configuring MDDR CLK 6 10 11 12 13 Instantiate the clock resources FAB_CCC and chip oscillators in the SmartDesign canvas and configure as required Connect the clock resources to the MSS component in the SmartDesign canvas To verify the design in Libero SoC software create the SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor Write BFM commands for read and write transactions The MDDR_init bfm file will be generated by Libero SoC software containing the BFM commands to initialize the MDDR registers Simulate the design to verify the read write transactions to DDR memory Open I O Attribute Editor to configure the ODT and drive strengths Program the device Use the generated firmware project to access the DDR memory from the Cortex M3 process
286. ured from the Cortex M3 processor through CoreSF2Config The read write and read modify write transactions are initiated by the AXI master to read or write the data into the DDR memory after receiving the ready signal from the APB master ARM Cortex M3 Processor AHB Bus Matrix FPGA Fabric CORE_RESET_N CLK_BASE FAB_PLL_LOCK FDDR Figure 2 17 Accessing FDDR Subsystem Through Dual AHB Interface Use the following steps to access the FDDR from the AXI master in the FPGA fabric 1 Instantiate the SmartFusion2 MSS component in the SmartDesign canvas 2 Configure the SmartFusion2 MSS peripheral components as required using the MSS configurator Configure FIC 0 as the AHB master Revision 2 I Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide 3 Configure FIC 2 to enable the FIC 2 APB interface for configuring the FDDR subsystem registers from the Cortex M3 processor as shown in Figure 2 18 E MSS Fabric Interface Controller FIC 2 Configurator Figure 2 18 FIC 2 Configuration 4 Configure MSSCCC for the FIC 0 clock as shown in Figure 2 19 The FIC 0 clock is configured to 111 MHz E MSS Clock Conditioning Circuitry Configurator System Clocks Advanced Options Clock Source CLK BASE 111 000 MHz 7 Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK Cortex M3 and MSS Main Clock M3 CLK 111 MHz 111 000 MHz MSS APB 0 1 Sub busses Clocks v APB O CLK mM3_CK a 111 00
287. value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 PHY_WR_DATA_SLAVE_RATIO_4_CR Table 1 163 PHY WR DATA SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0 49 48 bits of REG_PHY_WR_DATA_SLAVE_RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 128 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_WRLVL_INIT_MODE_CR Table 1 164 PHY_WRLVL_INIT_MODE_CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_WRLVL_INIT_MODE 0x0 The user programmable init ratio selection mode 1 Selects a starting ratio value based on REG_PHY_
288. value of a reserved bit should be preserved across a read modify write operation 86 Revision 2 Table 1 76 DDRC DFI RD LVL CONTROL 1 CR continued Bit Number lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Name Reset Value Description 15 8 REG DDRC DFI RDLVL MAX X1024 0x0 7 0 bits Read leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI RDLVL RESP to a read leveling enable signal DDRC DFI RDLVL EN or DDRC DFI RDLVL GATE EN Only applicable when connecting to PHYs operating in PHY RadLvi Evaluation mode Only present in designs that support DDR3 devices Units 1 024 clocks 7 0 REG DDRC RDLVL RR 0x0 Only present in designs that support DDR3 devices Read leveling read to read delay Specifies the minimum number of clock cycles from the assertion of a read command to the next read command Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units Clocks DDRC DFI RD LVL CONTROL 2 CR Table 1 77 DDRC DFI RD LVL CONTROL 2 CR Bit Reset Number Name Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved acro
289. ved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 15 0 bits of PHY_REG_WRLVL_DQ_RATIO Ratio value generated by the write leveling FSM for write data PHY WRLVL DQ RATIO 2 SR Table 1 187 PHY WRLVL DQ RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 31 16 bits of PHY REG WRLVL DQ RATIO Ratio value generated by the write leveling FSM for write data Table 1 188 PHY WRLVL DQ RATIO 3 SR PHY WRLVL DQ RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 47 32 bits of PHY REG WRLVL DQ RATIO Ratio value generated by the write leveling FSM for write data 138 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY WRLVL DQ RATIO 4 SR Table 1 189 PHY WRLVL DQ RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Softwa
290. vide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_M1_REN 0x0 1 Enable read buffer for AHBL master1 0 Disable read buffer for AHBL master 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M1_WEN 0x0 1 Enable write buffer for AHBL master 1 0 Disable write buffer for AHBL master 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_M2_REN 0x0 1 Enable read buffer for AHBL master2 0 Disable read buffer for AHBL master2 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M2_WEN 0x0 1 Enable write buffer for AHBL master2 0 Disable write buffer for AHBL master2 DDR_FIC_HPD_SW_RW_INVAL_CR Table 1 225 DDR FIC HPD SW RW INVAL CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit sh
291. when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology This effectively delays the CLK to the DRAM device by half a cycle providing a CLK edge that DQS can align to during leveling PHY RD DQS SLAVE DELAY 1 CR Table 1 140 PHY RD DQS SLAVE DELAY 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_DELAY 0x0 15 0 bits of REG PHY RD DQS SLAVE DELAY If REG PHY RD DQS SLAVE FORGE is 1 replace delay tap value for read DQS slave DLL with this value Revision 2 119 lt gt Microsemi MDDR Subsystem PHY_RD_DQS_SLAVE_DELAY_2_CR Table 1 141 PHY RD DQS SLAVE DELAY 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_DELAY OxO 31 16 bits of REG_PHY_RD_DQS_SLAVE_DELAY If REG PHY RD DQS SLAVE FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY RD DQS SLAVE DELAY 3 CR Table 1 142 PHY RD DQS SLAVE DELAY 3 CR
292. with their descriptions These signals will be available only if FDDR interface is configured for single or dual AHB mode For more details of AHB protocol refer to AMBA AHB v3 0 protocol specification Table 2 6 e FDDR AHB Slave Interface Signals Signal Name Direction Polarity Description AHBO_S_HREADYOUT Output High Indicates that a transfer has finished on the bus The signal is asserted LOW to extend a transfer Input to Fabric master AHBO_S_HRESP Output High Indicates AHB transfer response to Fabric master AHBO S HRDATA 31 0 Output Indicates AHB read data to Fabric master AHBO 8 HSEL Input High Indicates AHB slave select signal from Fabric master AHBO S HADDR 31 0 Input Indicates AHB address initiated by Fabric master AHBO S HBURST 2 0 Input Indicates AHB burst type from Fabric master AHBO S HSIZE 1 0 Input Indicates AHB transfer size from Fabric master AHBO S HTRANS 1 0 Input Indicates AHB transfer type from Fabric master AHBO 8 HMASTLOCK Input High Indicates AHB master lock signal from Fabric master AHBO S HWRITE Input High Indicates AHB write control signal from Fabric master AHBO S HREADY Input High _ Indicates that a transfer has finished on the bus Fabric master can drive this signal LOW to extend a transfer AHBO S HWDATA 31 0 Input Indicates AHB write data from Fabric master Revision 2 171 I Microsemi Fabric DDR Subsystem Table 2 7 shows the FDDR AHB
293. x0 This register value determines the number of samples for dq0 in for each ratio increment by the write leveling FSM NUM_OF_ITERATION rEG_PHY_GATELVL_NUM_OF_DQ0 1 Revision 2 Table 1 120 PHY DQ OFFSET 1 CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide PHY_DQ_OFFSET_1_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_DQ_OFFSET 0x0240 15 0 bits of REG PHY DQ OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG_PHY_USE_WR_LEVEL 1 Table 1 121 PHY DQ OFFSET 2 CR PHY DQ OFFSET 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_DQ_OFFSET 0x4081 31 16 bits of REG PHY DQ OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG PHY USE WR LEVEL 1 Table 1 122 PHY DQ OFFSET 3 CR PHY DQ OFFSET 3 CR Bit Reset Number Name Value Description
294. x1E 90 ns DDRC DYN REFRESH 2 CR 0x30 f tRFEI 0x61 0x61 97 x32 ciks 9 3 us DDRC INIT MR CR 0x520 Write recovery 3 DLL reset Yes CAS latency 6 Burst type Sequential Burst length 8 DDRC INIT EMR CR 0x44 Additive latency AL CL 1 Write levelization Enable DDRC DRAM BANK TIMING PARAM CR tRC 0x33 153 ns tFAW 0x20 96 ns DDRC_DRAM_RD_WR_LATENCY_CR 0x86 WL RL 6 DDRC_DRAM_RD_WR_PRE_CR 0x1E5 Rd2pre 0x15 63 ns Wr2pre 0x11 51 ns DDRC_DRAM_MR_TIMING_PARAM_CR 0x58 tMOD 0xB 11 clks DDRC DRAM RAS TIMING CR 0x10F tRAS max OxF 15x1024 46 us tRAS min 0x8 24 ns DDRC_DRAM_RD_WR_TRNARND_TIME_CR 0x178 Rd2wr 0xB 11 clks Wr2rd 0x18 24 clks DDRC DRAM T PD CR 0x33 tXP 3 3 clks tCKE 3 3 clks 32 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 12 MDDR Configurations for Accessing DDR3 Memories at 333 MHz continued Desired Value Register Name and Configured Value Field Value to be Loaded wide Mika DDRC_DRAM_BANK_ACT_TIMING_CR 0x1947 tRP 7 21ns tRRD 4 12 ns tCCD 2 2 clks tRCD 6 18 ns DDRC_PWR_SAVE_1_CR 0x506 Clks to power down 3 3x32 96clks Self refresh gap 0x14 20 20x32 640clks DDRC_ZQ_LONG_TIME_CR 0x200 512 clks ZQ_SHORT_TIME_CR 0x40 64 clks DDRC_PERF_PARAM_1_CR 0x4000 Burst length 0x2 Burst length is 8 HPR QUEUE PARAM 1 CR 0x80F8 XACT RUN LENGTH 0x8 8 transactions MIN
295. x424 RO PRESET Nl Tag of write buffer for which error response is received is placed in this register DDR FIC SW ERR ADDR 1 SR 0x428 RO PRESET Nl Tag of write buffer for which error response is received is placed in this register DDR FIC SW ERR ADDR 2 SR 0x42C RO PRESET NlTag of write buffer for which error response is received is placed in this register DDR FIC HPD SW WRB EMPTY SR 0x430 RO PRESET NlIndicates valid data in read and write buffer for AHBL master1 and master2 DDR FIC SW HPB LOCKOUT SR 0x434 RO PRESET N Write and read buffer status register for AHBL master1 and master2 150 Revision 2 lt gt Microsemi SmartFusion2 SoC FPGA High Speed DDR Interfaces User s Guide Table 1 220 DDR FIC Configuration Register Summary continued Address Reset Register Name Offset R W Source Description DDR FIC SW HPD WERR SR 0x438 RO PRESET_N Error response register for bufferable write request DDR_LOCK_TIMEOUTVAL_1_CR 0x440 RW PRESET NlIndicates maximum number of cycles a master can hold the bus for locked transfer DDR LOCK TIMEOUTVAL 2 CR 0x444 RW PRESET NlIndicates maximum number of cycles a master can hold the bus for locked transfer DDR FIC LOCK TIMEOUT EN CR 0x448 RW PRESET Nl Lock timeout feature enable register DDR FIC RDWR ERR SR 0x460 RO PRESET NlIndicates read address of math error register DDR FIC Configuration Regi
296. y Description MDDR SMC AXI M ARVALID Output High Indicates whether or not valid read address and control information are available 1 Address and control information valid 0 Address and control information not valid MDDR SMC AXI M RREADY Output High Indicates whether or not the master can accept the read data and response information 1 Master ready 0 Master not ready MDDR SMC AXI M AWREADY Input High Indicates that the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready MDDR SMC AXI M WREADY Input High Indicates whether or not the slave can accept the write data 1 Slave ready 0 Slave not ready MDDR SMC AXI M BVALID Input High Indicates whether or not a valid write response is available 1 Write response available 0 Write response not available MDDR SMC AXI M ARREADY Input High Indicates whether or not the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready MDDR SMC AXI M RLAST Input High Indicates the last transfer in a read burst MDDR SMC AXI M RVALID Input High Indicates whether or not the required read data is available and the read transfer can complete 1 Read data available 0 Read data not available Revision 2 229 lt gt Microsemi Soft Memory Controller Fabric Interface Cont
297. y one write transaction at a time and generates the handshaking signals on the AXI interface Revision 2 23 lt gt Microsemi MDDR Subsystem Priority Block The priority block prioritizes AXI read write transactions and provides control to the transaction handler AXI read transactions have higher priority The default priority ordering is listed below Reads from the slave port of the MSS DDR bridge Reads from the slave port of DDR_FIC Writes from the slave port of the MSS DDR bridge Writes from the slave port of DDR_FIC The fabric master through DDR_FIC can be programmed to have a higher priority by configuring the PRIORITY_ID and PRIORITY ENABLE BIT bit fields in the DDRC_AXI_FABRIC_PRI_ID_CR register Priority levels to other masters can be programmed as well as shown in Table 1 10 B OON Table 1 10 Priority Level Configuration Default Priorities Transactions Priorities PRIORITY_ENABLE_BIT 01 PRIORITY_ENABLE_BIT 10 11 Reads from Cache 1 1 2 Reads from DSG bus 2 2 3 Reads from HPDMA AHB bus 3 4 4 Reads from Fabric master 4 3 1 having the ID as PRIORITY_ID Writes ffom DSG bus 5 Writes ffom HPDMA AHB bus Writes from Fabric master 7 6 6 having the ID as PRIORITY_ID Transaction Handler The transaction handler converts AXI transactions into DDR controller commands The transaction handler works on one transaction at a time from the read write port queue that
298. z RC oscillator selected as the reference clock for the FPLL 1 Fabric clock CLK_BASE selected as the reference clock for the FPLL FACC_GLMUX_SEL 0x1 Selects the four glitchfree multiplexers within the FACC which are related to the aligned clocks All four of these multiplexers are switched by one signal Allowed values 0 M3 CLK PCLKO PCLK1 CLK DDR FIG all driven from stage 2 dividers from CLK SRC 1 M3 CLK PCLKO PCLK1 CLK DDR FIG all driven from CLK STANDBY FACC PRE SRC SEL 0x0 Selects whether CLK 1MHZ or ccc2asic is to be fed into the source glitchfree multiplexer 0 CLK 1MHZ is fed into the source glitchfree multiplexer 1 ccc2asic is fed into the source glitchfree multiplexer 5 3 FACC_SRC_SEL 0x0 Selects the source multiplexer within the FACC This is used to allow one of four possible clocks to proceed through the FACC dividers for generation of normal functional run time FDDR subsystem clocks There are three individual 2 to 1 glitchfree multiplexers in the 4 to 1 source glitchfree multiplexer FACC_SRC_SEL 0 is used to select the lower source MUX 0 CLK SRC driven from CLK 25 50MHZ 1 CLK SRC driven from cik xtal FACC SRC SEL 1 is used to select the upper source MUX 0 CLK SRC driven from output of PRE SRC MUX either cik 1mhz or ccc2asic 1 CLK SRC driven from MDDR PLL OUT CLK FACC SRC SEL 2 is used to select output source MUX 0 CLK SRC driven from output
299. zero 0 REG_DDRC_SKIP_OCD 0x1 This register must be kept at 1 1 Indicates the controller is to skip the OCD adjustment step during DDR2 initialization OCD Default and OCD Exit is performed instead 0 Not supported DDRC CKE RSTN CYCLES 1 CR Table 1 38 DDRC CKE RSTN CYCLES 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG DDRC PRE CKE X1024 0x0 7 0 bits of REG DDRC PRE CKE X1024 Cycles to wait after reset before driving CKE High to start the DRAM initialization sequence Units 1 024 clock cycles DDR2 specifications typically require this to be programmed for a delay of gt 200 us 7 0 REG DDRC DRAM RSTN X1024 0x0 Number of cycles to assert DRAM reset signal during initialization sequence This is only present for implementations supporting DDR3 devices Revision 2 67 lt gt Microsemi MDDR Subsystem DDRC CKE RSTN CYCLES 2 CR Table 1 39 DDRC CKE RSTN CYCLES 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of

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