Home

MSP430x4xx Family User's Guide (Rev. D)

1. MMA MMAV 2 6 System Resets Interrupts and Operating Modes System Reset and Initialization Figure 2 4 Block Diagram of Non Maskable Interrupt Sources ACCV FCTL1 1 IE1 5 Clear PUC RST NMI ii VIF B S CCVIFG ACCVIE Flash Module OSCFault IFG1 1 IE1 1 PUC FIF 6 1 OF IFG OFIE NMI_IRQA IRQA Interrupt Request Accepted POR PUC KEYV Voc PUC System Reset Generator POR gt NMIRS IES TMSEL NMI WDTQn EQU PUC POR A A A e o WDTIFG IRQ IFG1 0 WDT Counter POR IRQA TMSEL WDTIE IE1 0 Clear e Watchdog Timer Module PUC System Resets Interrupts and Operating Modes 2 7 System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault A PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs The flash access violation can
2. eee 4 2 10 FLL Fail Safe Operation 43 FLL Clock Module Registers 0c cece cece eee nett eee 5 Flash Memory Controller ssseeeeeeeee m Im n nnn nn 5 1 Flash Memory Introduction 5 2 Flash Memory Segmentation 5 3 Flash Memory Operation issssssssssssssss e m 5 3 1 Flash Memory Timing 5 3 2 Erasing Flash Memory seeeseeeseee eene 5 3 3 Writing Flash Memory ssssssseeee IH 5 3 4 Flash Memory Access During Write or Erase 5 3 5 Stopping a Write or Erase Cycle 5 3 6 Configuring and Accessing the Flash Memory Controller 5 3 7 Flash Memory Controller 5 3 8 Programming Flash Memory 5 4 Flash Memory Registers 0 cece eee m 6 Supply Voltage Supervisor 0c cece 6 1 SVS Introduction ood oi aa tier ep ere peri S RP PU S S Ra RE x S MEME ESO ru CEP 6 2 1 Configuring the SVS 2 eet ees 6 2 2 SVS Comparator Operation 6 2 3 Changing the VLDx Bits 0 0c cece es 6 2 4 SVS Operating Rangs cerei merien eec
3. L M l M M M M 1 USART Peripheral Interface SPI Mode 15 13 USART Registers SPI Mode UxCTL USART Control Register rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Unused Bits Unused 7 6 12 1 Bit 5 I2C mode enable This bit selects 12C or SPI operation when SYNC 1 0 SPI mode 1 12C mode CHAR Bit 4 Character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI mode MM Bit 1 Master mode 0 USART is slave 1 USART is master SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state t Applies to USARTO on MSP430x15x and MSP430x16x devices only 15 14 USART Peripheral Interface SPI Mode USART Registers SPI Mode UxTCTL USART Transmit Control Register 7 rw 0 rw 0 CKPH CKPL SSELx Unused Unused STC TXEPT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Clock phase select Controls the phase of UCLK 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle Clock polarity select 0 The inactive level is low data is output with the rising edge of UCLK input d
4. 7 1 Hardware Multiplier Introduction 7 1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU This means its activities do not interfere with the CPU activities The multiplier registers are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Signed multiply accumulate c n Unsigned multiply accumulate c c 16x16 bits 16x8 bits 8x16 bits 8x8 bits The hardware multiplier block diagram is shown in Figure 7 1 Figure 7 1 Hardware Multiplier Block Diagram 0000 130h MPYS 132h MAC 134h MACS 136h Accessible Register MACS MPYS MPY MPYS MAC MACS 32 bit Multiplexer RESHI 13Ch RESLO 13Ah 31 rw rw 0 7 2 Hardware Multiplier Hardware Multiplier Operation 7 2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply signed multiply unsigned multiply accumulate and signed multiply accumulate operations The type of operation is selected by the address the first operand is written to The hardware multiplier has two 16 bit operand registers OP1 and OP2 and three result registers RESLO RESHI and SUMEXT RESLO stores the low word of the result RESHI stores the high word of the result and SUMEXT stores information about the result The result is rea
5. V 3 66 RISC 16 Bit CPU SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W src dst or SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst NOT src dst or dst src 1 C dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B R12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B R13 R11 Subtract MSDs with carry resulting from the LSDs Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Y
6. X 7 si7 omn S18 4 gt 19 7e 7y S19 20 7d 7g 7a Parallel S20 4 21 7h 7 7b Serial S21 4 22 8e 8f 8y Conversion 522 gt 23 8d 8g 8a 523 lt 24 8h 8c 8b S24 4 25 9e 9f 9y Sn 1 Sn S25 4 26 9d 9g Qa 526 4 27 9h 9c 9b S27 4 28 10e 10f 10 528 4 29 10d 10g 10 S29 4 30 10h 10c 106 COMO lt gt 31 COMO COM1 32 COM1 COM2 4 33 COM2 COM3 NC LCD Controller 18 13 LCD Controller Operation 3 Mux Mode Software Example 18 14 The 3mux rate can support nine segments for each digit The nine segments of a digit are located in 1 1 2 display memory bytes EQU EQU EQU EQU EQU EQU EQU EQU EQU 0040h 0400h 0200h 0010h 0001h 0002h 0020h 0100h 0004h The LSDigit of register Rx should be displayed The Table represents the on segments according to the LSDigit of register of Rx The register Ry is used ODDDIGRLA MOV EVNDIGRLA MOV RLA RLA RLA RLA BIC B BIS B SWPB MOV B Table DW LCD Controller Rx Table Rx Ry Ry amp LCDn Ry Ry amp LCDn 1 Table Rx Ry Ry Ry Ry Ry 070h amp LCDy41 Ry amp LCDn41 Ry Ry amp LCDny2 b c 9 07h amp LCDn 1 for temporary memory LCD in 3mux has 9 segments per digit word table required for displayed characters Load
7. Int DAC12 10UT 1 O int ext OA1O OA1 A5 int ext 2 OA2 OAxOUT OA1TAP OA2TAP OA1 OANx OA2 1 X OAFCx 24 5 OANx 0 OAFCx 7 OAxIO OAxI1 Int DAC12 0OUT Int DAC12 1OUT 1 1 RBOTTOM e OA2Rgorrom OA1 HL Ue 0 1 3 j OAFCx 1 e OAFCx 2 7 OAFBRx 4 e unused OAxOUT reserved OAFBRx 0 RBoTTOM OA2OUT OAOOUT OA1 OA1OUT OA2 OANx OA 16 3 16 2 OA Operation 16 2 1 OA Amplifier 16 2 2 OA Input 16 2 3 OA Output 16 4 OA The OA module is configured with user software The setup and operation of the OA is discussed in the following sections The OA is a configurable low current rail to rail operational amplifier It can be configured as an inverting amplifier or a non inverting amplifier or can be combined with other OA modules to form differential amplifiers The output slew rate of the OA can be configured for optimized settling time vs power consumption with the OAPMx bits When 00 the OA is off and the output is high impedance When OAPMx gt 0 the OA is on See the device specific datasheet for parameters The has configurable input selection The signals for the and inputs are individually selected with the OANx and OAPx bits and can be selected as external signals
8. f SD16GRP 1 SD16SC Set by Ch2 Auto dlea 4 Set by SW Auto clear l Channel2 Conversion Conversion E Conversion Conversion SDI6SNGL 0 7 L L SD16GRP 0 SD16SC Set by SW pru pe C Result written to SD16MEMx Time 20 14 SD16 SD16 Operation 20 2 9 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel SD16INCHx 110 Any other configuration is done as if an external channel was selected including SD16INTDLYx and SD16GAINx settings The typical temperature sensor transfer function is shown in Figure 20 11 When switching inputs of an SD16 channel to the temperature sensor adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are valid The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific data sheet for temperature sensor parameters Figure 20 11 Typical Temperature Sensor Transfer Function Volts 0 500 0 450 0 400 0 350 0 300 Vremp 1 257 TEMPc 343 349 mV 0 250 0 200 Celsius SD16 20 15 SD16 Operation 20 2 10 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel SD16IFG Li SD160VIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result An interrupt reques
9. EQUO EQU1 EQUO EQU1 EQUO TBIFG TBIFG TBIFG Interrupt Events Timer_B 13 15 Timer B Operation Ouiput Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depending on the output mode An example is shown in Figure 13 13 using TBCLO and TBCL1 Figure 13 13 Output Example Timer in Continuous Mode TBR max TBCLO TBCL1 Oh TBIFG EQU1 EQUO TBIFG EQU1 EQUO Interrupt Events 13 16 Timer B Timer B Operation Ouiput Example Timer in Up Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode An example is shown in Figure 13 14 using TBCLO and TBCL3 Figure 13 14 Output Example Timer in Up Down Mode TBR max TBCLO TBCL3 Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQU3 EQU3 EQU3 EQUS TBIFG EQUO TBIFG EQUO Events p T Note Switching Between Output Modes When switching between output modes one of the OUTMODX bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode
10. nm m A TDN 0 lowest implemented in byte format SFRs must be accessed using byte instructions See the device specific datasheet for the SFR configuration System Resets Interrupts and Operating Modes Operating Modes 2 3 Operating Modes The MSP430 family is designed for ultralow power applications and uses different operating modes shown in Figure 2 9 The operating modes take into account three different needs Ultralow power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2 8 Figure 2 8 Typical Current Consumption of 41x Devices vs Operating Modes ICC uA Q 1 MHz 315 270 225 180 135 90 45 AM LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 0 4 are configured with the CPUOFF OSCOFF SCGO and SCG1 bits in the status register The advantage of including the CPUOFF OSCOFF SCGO0 and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine The mode control bits and the stack can be accessed with an
11. ____ RISC 16 Bit CPU 3 39 Instruction Set EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable general interrupts EINT 1 GIE or 0008h OR SR gt SR src OR dst dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1lN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 0 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable sss 3 40 RISC 16 Bit CPU INCLW INC B Syntax Operation Emulation Description Status Bits Mode Bits Example Instructio
12. Note Length of I O Pin Interrupt Event Any external interrupt event should be at least 1 5 times MCLK or longer to ensure that it is accepted and the corresponding interrupt flag is set a Digital I O 9 5 Digital I O Operation Interrupt Edge Select Registers P1IES P2IES Each PxIES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PxIFGx flag is set with a low to high transition Bit 1 The PxIFGx flag is set with a high to low transition E S a Aa ETE EU Note Writing to PxIESx Writing to P1IES or P2IES can result in setting the corresponding interrupt flags PxIESx PxINx PxIFGx 0 5 1 0 Unchanged 0 2 1 1 May be set 10 0 May be set 1 10 Unchanged Interrupt Enable 1 P2IE Each bit enables the associated PxIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 9 2 6 Configuring Unused Port Pins Unused I O pins should be configured as I O function output direction and left unconnected on the PC board to reduce power consumption The value of the PxOUT bit is don t care since the pin is unconnected See chapter System Resets Interrupts and Operating Modes for termination unused pins 9 6 Digital O 9 3 Digital I O Registers Table 9 1 Digital I O Registers Port P1 P2 P3 P4 P5 P6 Digital I O Registers Seven registers are used to configure P1 and P2 Four registers are used to configure ports
13. P6 The digital I O registers are listed in Table 9 1 Register Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Short Form P1IN P1O0UT P1DIR P1IFG P1IES P1IE P1SEL 21 P2OUT P2DIR P2IFG P2IES P2IE P2SEL P3IN P3OUT P3DIR P3SEL P4IN 400 P4DIR P4SEL P5OUT P5DIR P5SEL P6IN P6OUT P6DIR P6SEL Address 020h 021h 022h 023h 024h 025h 026h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 030h 031h 032h 033h 034h 035h 036h 037h Register Type Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Initial State Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Un
14. TEXAS INSTRUMENTS MSP430x4xx Family User s Guide 2004 Mixed Signal Products SLAUO56D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other
15. eere 22 2 6 Using the Scan IF with LC Sensors 22 2 7 Using the Scan IF With Resistive Sensors 22 2 8 Quadrature Decoding 06 lt eee eee 22 9 Scan IF Registers tat ha ede ka PE Sha ee ee cepa bees xii Chapter 1 Introduction This chapter describes the architecture of the MSP430 Topic Page qi Afchitectllte e c cc Med 1 2 1 2 Flexible Clock System 1 2 1 3 Embedded Emulation 1 3 Address Space eee scenes es TN CUM E Ie ME 1 4 Architecture 1 1 Architecture The MSP430 incorporates a 16 bit RISC CPU peripherals and a flexible clock system that interconnect using a von Neumann common memory address bus MAB and memory data bus MDB Partnering a modern CPU with modular memory mapped analog and digital peripherals the MSP430 offers solutions for demanding mixed signal applications Key features of the MSP430x4xx family include Ultralow power architecture extends battery life 0 1 uA RAM retention 0 8 uA real time clock mode 250 uA MIPS active High performance analog ideal for precision measurement 12 bit or 10 bit ADC 200 ksps temperature sensor Vnef B 12 bit dual DAC B Comparator gated timers for measuring resistive elements B Supply voltage supervisor 16 bit RISC CPU enables new applications at a fraction of the code size B Large regi
16. pP PUC DCO wor Meli Resetwd1 PUC EQUT Resetwd2 KEYV from flash module MCLK T From watchdog timer peripheral module A POR is a device reset A POR is only generated by the following three events Powering up the device A low signal on the RST NMI pin when configured in the reset mode An SVS low condition when PORON 1 A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC signal Watchdog timer expiration when watchdog mode only Watchdog timer security key violation g A Flash memory security key violation 2 2 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 4 Brownout Reset BOR All MSP430x4xx devices have a brownout reset circuit The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the Vcc terminal The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed The operating levels are shown in Figure 2 2 The POR signal becomes active when Vcc crosses the level It remains active until Vcc crosses the Vg jr threshold and the delay t gor elapses The delay t gog is adaptive being longer for a slow ramping Voc The hysteresis Vnys g ensures that the supply voltage must drop below jr to generate another POR signa
17. Figure 20 1 SD16 Block Diagram A7 SD16LP SD16PRE1 1 SDi6REFON SD16 Control Block 1 1 1 V Reference SD16SSELx Mind e 12V SD16DIVx 1 MV MCLK 1 AVss Divider SMCLK 1 1 2 4 8 1 X TACLK i SD16VMIDON i 1 5 Temperature sensor Reference fM doe bonds tem E Ea id ot Ee s Me iu ee AT t edv rev A yd A cus 1 ge ann ge ger age ew ae ee Te 1 HE PR Channel 0 m acd aseo ie mde edem e T etm em emot TET Menor 1 1 Conversion Control Channel 1 j Temperature sensor Reference fM to prior channel 1 vy y Y ates Grou D16GRP p Start Conversion Logic SD16SGNL Conversion Control i from next channel 1 1 A1 SD16GAINx SD160SRx A2 i 1 2nd Order M XA Modulator 1 p A6 SD16DF SD16PRE1 i 1 1 1 1 i i i i 1 Channel 2 SD16 t Monee wesicns Seb esses See e seas ie Sasser ees 1
18. SIFCNT3x Bits 15 8 SIFTSMRP Bit7 SIFCLKFQx Bits 6 3 SIFFNOM Bit 2 SIFCLKG Bit 1 SIFCLKEN Bito 22 48 Scan IF rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 rw 0 rw 0 rw 0 rw 0 rw i rw Internal oscillator counter SIFCNT3 counts internal oscillator clock cycles during one ACLK period when SIFFNOM 0 or during four ACLK periods when SIFFNOM 1 after SIFCLKGON and SIFCLKEN are both set TSM repeat mode 0 Each TSM sequenceis triggered by the ACLK divider controlled with the SIFDIV3Ax and SIFDIV3Bx bits 1 Each TSM sequence is immediately started at the end of the previous sequence Internal oscillator frequency adjust These bits are used to adjust the internal oscillator frequency Each increase or decrease of the SIFCLKFQx bits increases or decreases the internal oscillator frequency by approximately 5 0000 Minimum frequency 1000 Nominal frequency 1111 Maximum frequency Internal oscillator nominal frequency 0 4 MHz 1 1 MHz Internal oscillator control When SIFCLKGON 1 and SIFCLKEN 1 the internal oscillator calibration is started SIFCLKGON is not used when SIFCLKEN 0 0 No internal oscillator calibration is started 1 The internal oscillator calibration is started when SIFCLKEN 1 Internal oscillator enable This bit selects the high frequency clock source for the TSM 0 TSM high frequency clock source is SMCLK 1 TSM high frequency clock source is the Scan IF internal osc
19. The XT2OFF bit disables the XT2 oscillator if XT2CLK is unused for MCLK SELMx 2 or CPUOFF 1 and SMCLK SELS 0 or SMCLKOFF 1 XT2 may be used with external clock signals on the XT2IN pin When used with an external signal the external frequency must meet the datasheet parameters for XT2 FLL Clock Module FLL Clock Module Operation 4 2 4 Digitally Controlled Oscillator DCO The DCO is an integrated ring oscillator with RC type characteristics The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N the lowest 7 bits of the SCFQCTL register The DCOPLUS bit sets the fpcoci k frequency to fpco orfpco p The FLLDx bits configure the divider D to 1 2 4 or 8 By default DCOPLUS 0 and D 2 providing a clock frequency of fpco 2 on fpcoci k The multiplier N 1 and D set the frequency of DCOCLK DCOPLUS 0 fpcocLk N 1 x facLk DCOPLUS 1 fpcocLK Dx N 1 X fACLK DCO Frequency Range The frequency range of fpco is selected with the FNx bits as listed in Table 4 1 The range control allows the DCO to operate near the center of the available taps for a given DCOCLK frequency The user must ensure that MCLK does not exceed the maximum operating frequency See the device specific datasheet for parameters Table 4 1 DCO Range Control Bits FN2 ypicalfpcoRange 0 0 0 0 0 65 6 1 0 1 1 3 12 1 0 0 1 X 2 17 9 1 X X 2 8 26 6 1 Xx x 4 2 46 4
20. USART Operation UART Mode 14 2 6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non standard source frequencies The baud rate generator uses one prescaler divider and a modulator as shown in Figure 14 7 This combination supports fractional divisors for baud rate generation The maximum USART baud rate is one third the UART source clock frequency BRCLK Figure 14 7 MSP430 Baud Rate Generator UCLKI ACLK SMCLK smeek Aul oee 0 or 1 Compare 0 or 1 Toggle FE BITCLK Modulation Data Shift Register R LSB first lt lt mx m7 8 A UxMCTL Bit Start Timing for each bit is shown in Figure 14 8 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 N 2 and 2 1 BRCLK periods where is the number of BRCLKs per BITCLK Figure 14 8 BITCLK Baud Rate Timing Majority Vote m o4 Y Y Bit Start l l Uy y y 1 BACIK A H A U UV UC UU L L i N 2 N 2 1 N 2 2 1 N2 N2 Counter i 2 N 2 1 N 2 2 0 N2 N24 110 2 S H 4 NTN m 0 J NEVEN INT N 2 INT N 2 m 1 i Nopp INT N 2 R 1 gt Bit Period Pe m corresponding modulation bit R Remainder from N 2 division USART Peripheral Interface UART Mode 14 11 USART Operation UART Mode Baud Rate Bit
21. Unused Read only Always read as 0 Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TACCRO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set CCIE Bit 4 CCI Bit 3 OUT Bit 2 COV Bit 1 CCIFG Bit 0 Timer A Registers Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output This bit indicates the state of the output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer A Interrupt Vector Register ro 7 15 14 13 12 11 10 9 8 ro ro ro ro ro 5 4 3 2 1 0 ro ro TAIVx Bits 15 0 ro ro r 0 r 0 r 0 ro Timer A Interrupt Vector value Interrupt TAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TACCR1 CCIFG Highest 04h Capture compare 2 TACCR2 CCIFG 06h Capture compare TACCR3 CCIFG 08h Capture compare 4t TACCR4 CCIFG OAh Timer ove
22. Watchdog timer hold This bit stops the watchdog timer Setting WDTHOLD 1 when the WDT is not in use conserves power 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select This bit selects the interrupt edge for the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear Setting WDTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0 No action 1 WDTONT 0000h Watchdog timer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag and or generate a PUC 00 Watchdog clock source 32768 01 Watchdog clock source 8192 10 Watchdog clock source 512 11 Watchdog clock source 64 10 8 Watchdog Timer Watchdog Timer Watchdog Timer Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 1 WDTIE Bit 0 Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because
23. 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output This bit indicates the state of the output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer B Registers TBIV Timer B Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro ro r 0 r 0 r 0 ro TBIVx Bits Timer B interrupt vector value 15 0 Interrupt TBIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 3t TBCCR3 CCIFG 08h Capture compare 41 TBCCR4 CCIFG OAh Capture compare 5t TBCCR5 CCIFG OCh Capture compare 6t TBCCR6 CCIFG OEh Timer overflow TBIFG Lowest t MSP430x4xx devices only Timer B 13 25 13 26 Timer B Chapter 14 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the asynchronous UART mode USARTO is implemented on the MSP430x42x and MSP430x43x devices In addition to USARTO
24. 1 the TSM starts immediately with the SIFSTMO state with the next ACLK cycle after encountering a state with a set SIFSTOP bit The SIFIFG2 interrupt flag is set when the TSM starts The SIFDIV3Ax and SIFDIV3Bx bits may be updated anytime during operation When updated the current TSM sequence will continue with the old settings until the last state of the sequence completes The new settings will take affect at the start of the next sequence TSM Control of the AFE TSM State Duration The TSM controls the AFE with the SIFCHx SIFLCEN SIFEX SIFCA SIFRSON SIFTESTS1 SIFDAC and SIFSTOP bits When any of these bits are set their corresponding signal s SIFCHx tsm SIFLCEN tsm SIFEX tsm SIFCA tsm SIFRSON tsm SIFTESTS1 tsm SIFDAC tsm and SIFSTOP tsm are high for the duration of the state Otherwise the corresponding signal s are low The duration of each state is individually configurable with the SIFREPEATx bits The duration of each state is SIFREPEATx 1 times the selected clock source For example if a state were defined with SIFREPEATx 3 and SIFACLK 1 the duration of that state would be 4 x ACLK cycles Because of clock synchronization the duration of each state is affected by the clock source for the previous state as shown in Table 22 5 Table 22 5 TSM State Duration 22 16 Scan IF SIFACLK For For Previous Current State State Duration T State 0 0 T SIFREPEATx 1 1 fSIFCLK
25. 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ONFETCH ROBIN ro ro ro ro ro rw 0 rw 0 rw 0 Reserved Bits Reserved Read only Always read as 0 15 3 DMA Bit 2 DMA on fetch ONFETCH 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin This bit enables the round robin DMA channel priorities ROBIN 0 DMA channel priority is DMA1 DMA2 1 DMA channel priority changes with each transfer ENNMI Bit 0 Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is completed normally further transfers are stopped and DMAABORT is set 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer 8 20 DMAxCTL DMA Channel x Control Register 15 Reserved rw 0 rw 0 Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMA DSTBYTE 14 13 12 11 10 9 8 DMADTx DMADSTINCRx DMASRCINCRx rw 0 7 6 5 4 3 2 1 0 DMA DMA DMA rw 0 0 0 0 0 0 0 Bit 15 Bits 14 12 Bits 11 10 Bits 9 8 Bit 7 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw rw rw rw rw Reserved DMA Transfer mode 000 Single transfer 001 Block transfer 010 Burst block transfer 011 Burst block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst b
26. 5d 5c 091h b h oO S19 4 20 5e 5g S20 gt 21 6f 6a Parallel S21 22 6h 6b Serial S22 gt 23 6d 6c Conversion S23 4 24 6g S24 gt 25 7 7 S25 4 26 7h 7b S26 4 27 7d 7c Sn 1 Sn S27 4 28 7e 79 528 4 29 Bf 8 S29 4 30 8h 8b S30 4 31 8 531 4 32 8e 8g COMO 4 33 COMO COM1 4 34 COM1 COM2 NC coms NC 18 10 LCD Controller 2 Mux Mode Software Example LCD Controller Operation All eight segments of a digit are often located in two display memory bytes with the 2mux display rate EQU EQU EQU EQU EQU EQU EQU EQU 002h 020h 008h 004h 040h 001h 080h 010h The register content of Rx should be displayed The Table represents the on segments according to the content of Rx Table Ry amp LCDn Ry i Ry i Ry amp LCDn 1 Load segment information into temporary memory Ry 0000 0000 gebh cdaf Note All bits of an LCD memory byte are written Ry 0000 0000 heda Ry 0000 0000 00 bhced Note All bits of an LCD memory byte are written displays 0 displays 8 LCD Controller 18 11 LCD Controller Operation 18 2 8 3 Mux Mode In 3 mux mode each MSP430 segment pin drives three LCD segments and three common lines COMO COM1 and are used Figure 18 8 shows some example 3 mux waveforms Figure 18 8 Example 3 Mux Wa
27. FLL_CTL1 FLL Control Register 1 7 r 4 3 2 1 0 rw 6 5 0 ro 1 rw 0 rw 0 rw 0 rw 0 rw 0 T Not present in MSP430x41x MSP430x42x devices Unused SMCLKOFF XT2OFF SELMx SELS FLL_DIVx Bit 7 Bit 6 Bit 5 Bits 4 3 Bit 2 SMCLK off This bit turns off SMCLK Not present in MSP430x41x MSPx42x devices 0 SMCLK is on 1 SMCLK is off XT2 off This bit turns off the XT2 oscillator Not present in MSP430x41x MSPx42x devices 0 XT2 is on 1 XT2 is off if itis not used for MCLK or SMCLK Select MCLK These bits select the MCLK source Not present in MSP430x41x MSP430x42x devices 00 DCOCLK 01 DCOCLK 10 XT2CLK 11 LFXT1CLK Select SMCLK This bit selects the SMCLK source Not present in MSP430x41x MSP430x42x devices 0 DCOCLK 1 XT2CLK ACLK divider 00 01 2 10 4 11 8 FLL Clock Module 4 15 FLL Clock Module Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 OFIE Bits 7 2 Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules See device specific datasheet IFG1 Inte
28. J UCLK USART SPI clock Master mode UCLK is an output Slave mode UCLK is an input STE Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode 4 Pin master mode When STE is high SIMO and UCLK operate normally When STE is low SIMO and UCLK are set to the input direction 4 pin slave mode When STE is high RX TX operation of the slave is disabled and SOMI is forced to the input direction When STE is low RX TX operation of the slave is enabled and SOMI operates normally 15 2 1 USART Initialization and Reset 15 4 The USART is reset by or by the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART in a reset condition When set the SWRST bit resets the URXIEx UTXIEx URXIFGx OE and FE bits and sets the UTXIFGx flag The USPIEx bit is not altered by SWRST Clearing SWRST releases the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12C mode to SPI mode Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B SWRST amp UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs USPIEx 4 Clear SWRST via software BIC B SWRST amp UxCTL 5 Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx rama WH Failure to follow this
29. MERAS ERASE Reserved 5 18 rw 0 Bits 15 8 Bit 7 Bit 6 Bits 5 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 ro ro ro rw 0 ro rw 0 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Block write mode WRT must also be set for block write mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on Write This bit is used to select any write mode WRT is automatically reset when EMEX is set 0 Write mode is off 1 Write mode is on Reserved Always read as 0 Mass erase and erase These bits are used together to select the erase mode MERAS and ERASE are automatically reset when EMEX is set MERAS ERASE Erase Cycle 0 0 No erase 0 1 Erase individual segment only 1 0 Erase all main memory segments 1 1 Erase all main and information memory segments Reserved Always read as 0 Flash Memory Controller Flash Memory Registers FCTL2 Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 rw 1 rw 0 FWKEYx FSSELx Bits 15 8 Bits 7 6 Bits 5 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Flash controller clock source select 00 ACLK 01 10 SMCLK 11 SMCLK Flash controller clock divider These six bits select the divider for the flash controller clock T
30. OUT 1 1 l OUTE6 Signal i i 1 1 i i EE mu EEEE EEEE Timer_B 13 3 Timer B Operation 13 2 Timer B Operation The Timer B module is configured with user software The setup and operation of Timer B is discussed in the following sections 13 2 1 16 Bit Timer Counter TBR Length The 16 bit timer counter register TBR increments or decrements depending on mode of operation with each rising edge of the clock signal TBR can be read or written with software Additionally the timer can generate an interrupt when it overflows TBR may be cleared by setting the TBCLR bit Setting TBCLR also clears the clock divider and count direction for up down mode 7 1l Note Modifying Timer B Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable and interrupt flag to avoid errant operating conditions When TBCLK is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Any write to TBR will take effect immediately Timer B is configurable to operate as an 8 10 12 or 16 bit timer with the CNTLx bits The maximum count value TBR max for the selectable lengths is OFFh O3FFh OFFFh and OFFFFh respectively Data written to the TBR register in 8 10 and 12 bit mode is right justif
31. SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected RISC 16 Bit CPU 3 65 Instruction Set SUB W SUB B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst Or SUB W src dst SUB B src dst dst NOT src 1 dst or dst src gt dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected See example at the SBC instruction See example at the SBC B instruction Note Borrow Is Treated as NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 LLLLLLSSS M A O
32. Timer Ais a 16 bit timer counter with three or five capture compare registers Timer A can support multiple capture compares PWM outputs and interval timing Timer A also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer A features include Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Three or five configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching L L UL Lu O Interrupt vector register for fast decoding of all Timer A interrupts The block diagram of Timer A is shown in Figure 12 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action will not take place LLLLL amp p 7 Note Second Timer A On Select Devices MSP430x415 MSP430x417 and MSP430xW42x devices implement a second Timer A with five capture compare registers On these devices both Timer A modules are identical in function
33. UxBR 13 since the ideal division factor is 13 65 UxMCTL 6B m7 0 m621 m5 1 m4 0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error Paua raie rate x 2x 1 6 0 x UxBR 0 1 0 x 100 2 54 Data bit DO Error Data bit D1 Error Data bit D2 Error Data bit D3 Error Data bit D4 Error Data bit D5 Error Data bit D6 Error Data bit D7 Error BRCLK baud rate BRGLK eX 6 1 x UxBR 1 1 1 x 100 5 08 baud rate X 6 2 x UxBR 1 1 2 x 100 0 29 Gers BRCLK sauc rate x 2x 1 6 3 x UxBR 2 I 1 100 2 83 x 2 1 6 4 x UxBR 2 1 4 100 1 9596 x 2x 1 6 5 x UxBR 3 1 5 x 100 0 59 x 2x 1 6 6 x UxBR 4 1 6 100 3 13 z audiate x 2x 1 6 7 x UxBR 4 1 100 1 66 z 5 x 2 1 6 8 UxBR 5 1 8 100 0 88 Parity bit Error Paua raie x 2 1 6 9 x UxBR 1 9 x 100 3 42 Stop bit 1 Error BRCLK BRCLK Emirats x 2x 1 6 10 x UxBR 6jI 1 10 x 10095 1 3796 The results show the maximum per bit error to be 5 0896 of a BITCLK period USART Peripheral Interface UART Mode 14 15 USART Operation UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in
34. before using the hardware multiplier Disable interrupts Required for DINT Load 1st operand Load 2nd operand Interrupts may be enable before Process results Hardware Multiplier Registers 7 3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7 4 Table 7 4 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Extension register SUMEXT Read 013Eh Undefined Hardware Multiplier 7 7 7 8 Hardware Multiplier Chapter 8 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention This chapter describes the operation of the DMA controller The DMA controller is implemented in MSP430xFG43x and implements only one DMA channel Topic 8 1 DMA Introduction 8 2 DMA Operation 8 3 DMA Registers 8 1 8 1 Introduction 8 2 The direct memory access DMA controller transfers data from one address to another without CPU intervention across the entire address range For example the DM
35. rw 0 Bit 15 14 Bit 13 12 Bit 11 Bit 10 9 Bit 8 Bits 7 5 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 5 rw 0 rw rw rw rw Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TBCCRx input signal See the device specific datasheet for specific signal connections 00 01 CCIxB 10 GND 11 Vcc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBOLxloads when TBR counts to 0 up or continuous mode TBCLx loads when TBR counts to TBCLO or to 0 up down mode 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TBCLO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set Timer B 13 23 Timer B Registers CCIE CCI OUT COV CCIFG 13 24 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer B Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled
36. 0 ADC12 off 1 ADC12 on ADC12MEMXx overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion Software controlled sample and conversion start ADC12SC and ENC may be set together with one instruction ADC12SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC12 Registers ADC12CTL1 ADC12 Control Register 1 15 14 13 12 11 10 9 8 rw 0 rw 0 7 6 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 rw 0 0 ADC12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Modifiable only when ENC 0 CSTART Bits ADDx 15 12 SHSx Bits 11 10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7 5 Conversion start address These bits select which ADC12 conversion memory register is used for a single conversion or for the first conversion in a sequence The value of CSTARTADDx is 0 to OFh corresponding to ADC12MEMO to ADC12MEM15 Sample and hold source select 00 ADC12SC bit 01 Timer A OUT1 10 Timer B OUTO 11 Timer B OUT1 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be eithe
37. 110 50 535 are LCD function 111 S0 S39 are LCD function LCD mux rate These bits select the LCD mode 00 Static 01 2 mux 10 3 mux 11 4 mux LCD segments on This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled 0 All LCD segments are off 1 All LCD segments are enabled and on or off according to their corresponding memory location Unused LCD On This bit turns on the LCD timing generator and R33 0 LCD timing generator and Ron are off 1 LCD timing generator and Ron are on LCD Controller 18 19 18 20 LCD Controller Chapter 19 ADC12 The ADC12 module is a high performance 12 bit analog to digital converter This chapter describes the ADC12 The ADC12 is implemented in the MSP430x43x and MSP430x44x devices Topic Page ADOT Introduction 19 2 19 27 ADC12 Operation 19 4 19 3 ADC 2 Registers TES 19 20 19 1 ADCt12 Introduction 19 1 ADC12 Introduction 19 2 ADC12 The ADC12 module supports fast 12 bit analog to digital conversions The module implements a 12 bit SAR core sample select control reference generator and a 16 conversion and control buffer The conversion and control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention ADC12 features include Greater than 200 ksps maximum conversion rat
38. 2 x MUX X fFrame For example to calculate fj cp for a 3 mux LCD with a frame frequency of 30 100Hz fFrame from LCD datasheet 30 100 Hz fLcp 2 x 3 x ferame fLCD min 180 Hz fLCD max 600 Hz select fj cp 32768 128 256 Hz or 32768 64 512 Hz See the LCD Controller chapter for more details on the LCD controller Interrupts The Basic Timer1 uses two bits in the SFRs for interrupt control Basic Timer1 interrupt flag BTIFG located in IFG2 7 _j Basic Timer1 interrupt enable BTIE located in IE2 7 The BTIFG flag is set after the selected time interval and requests a Basic Timer1 interrupt if the BTIE and the GIE bits are set The BTIFG flag is reset automatically when the interrupt is serviced or can be reset with software Basic Timer1 11 5 Basic Timer1 Introduction 11 3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 11 1 Table 11 1 Basic Timer1 Registers Register Short Form Register Type Address Initial State Basic Timer Control BTCTL Read write 040h Unchanged Basic Timer Counter 1 BTCNT1 Read write 046h Unchanged Basic Timer1 Counter 2 BTCNT2 Read write 047h Unchanged SFR interrupt flag register 2 IFG2 Read write 001h Reset with PUC SFR interrupt enable register 2 IE2 Read write 003h Reset with PUC Note The Basic Timer1 registers should be configured at power up There is no initial state for BTCTL BTCNT1 or BTCNT2 11 6 Basic Timer1 Basic Tim
39. A13 SHP SHTOx ISSH Ai4t 15 00 Ha ADC12SC Sample Timer 01 TA 4 1024 T Sync 10 SAMPCON 4 11 F TB1 SHT1x MSC Lf INCHx 0Bh Ref x ADC12MEMO ADC12MCTLO gt CSTARTADDx _ 16x12 16x8 i Memory Memory mH Buffer Control T CONSEQx z 1 NL Y AVss tmsp430FG43x devices only ADC12MEM15 ADC12MCTL15 ADC12 19 3 ADC12 Operation 19 2 ADC12 Operation The ADC12 module is configured with user software The setup and operation of the ADC12 is discussed in the following sections 19 2 1 12 Bit ADC Core The ADC core converts an analog input to its 12 bit digital representation and stores the result in conversion memory The core uses two programmable selectable voltage levels Vp and Vp to define the upper and lower limits of the conversion The digital output NApc is full scale OFFFh when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vg The input channel and the reference voltage levels Vp and Vp are defined in the conversion control memory The conversion formula for the ADC result Napc is Vin V V R N R T VR apc 4095 x The ADC12 core is configured by two control registers ADC12CTLO and ADC12CTL1 The core is enabled with the ADC12ON bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC 0 ENC m
40. ADC12IFGx Bits ADC12MEMXx Interrupt flag These bits are set when corresponding 15 0 ADC12MEMXx is loaded with a conversion result The ADC12IFGx bits are reset if the corresponding ADC12MEMX is accessed or may be reset with software 0 No interrupt pending 1 Interrupt pending 19 26 ADC12 ADC12IV ADC12 Interrupt Vector Register ro 7 ro ADC12IVx Bits 15 0 6 ro 5 4 3 ADC12 interrupt vector value ADC121V Contents 000h 002h 004h 006h 008h 00Ah 00Ch OOEh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEMXx overflow Conversion time overflow ADC12MEM60 interrupt flag ADC12MEM interrupt flag ADC12MEN2 interrupt flag ADC12MEMs3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEWN7 interrupt flag ADC12MEMS8 interrupt flag ADC12MENO interrupt flag ADC12MEM 10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM 13 interrupt flag ADC12MEM 14 interrupt flag ADC12MEM 15 interrupt flag 2 1 ADC12 Registers 15 14 13 12 11 10 9 8 ro ro ro ro ro 0 ro Interrupt Interrupt Flag Priority ADC12IFGO ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 ADC12 Highest Lowest 19 27 19 28 ADC12 5016 5016 module is
41. COMO lt 33 COMO COM1 NC COM2 NC COM3 NC LCD Controller 18 7 LCD Controller Operation Static Mode Software Example 18 8 All eight segments of a digit are often located in four display memory bytes with the static display method EQU EQU EQU EQU EQU EQU EQU EQU 001h 010h 002h 020h 004h 040h 008h 080h content of Rx Table LCD Controller MOV B Table MOV RRA MOV RRA MOV RRA MOV Ry amp LCDn Ry Ry amp LCDn 1 Ry Ry amp LCDn 2 Ry Ry amp LCDn 3 b c Rx RY The register content of Rx should be displayed The Table represents the on segments according to the Load segment information into temporary memory Ry 0000 0000 hfdb geca Note All bits of an LCD memory byte are written Ry 0000 0000 Ohfd bgec Note All bits of an LCD memory byte are written Ry 0000 0000 00hf Note All bits of an LCD memory byte are written Ry 0000 0000 000h fdbg Note All bits of an LCD memory byte are written displays 0 displays 1 LCD Controller Operation 18 2 7 2 Mux Mode In 2 mux mode each MSP430 segment pin drives two LCD segments and two common lines COMO and COM 1 are used Figure 18 6 shows some example 2 mux waveforms Figure 18 6 Example 2 Mux Waveforms COM1 V1 s a trame vi cw 1 V5 COMO V1 s III SP2 vi Pr PFU UU b SP1
42. DAC12RES DAC12DF DAC12_1Latch DAC12GRP ENC DAC12 1DAT DAC12_1DAT Updated DAC12 21 3 DAC12 Operation 21 2 DAC12 Operation The DAC12 module is configured with user software The setup and operation of the DAC12 is discussed in the following sections 21 2 1 DAC12 Core The DAC12 can be configured to operate in 8 or 12 bit mode using the DAC12RES bit The full scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit This feature allows the user to control the dynamic range of the DAC12 The DAC12DF bit allows the user to select between straight binary data and 2 s compliment data for the DAC When using straight binary data format the formula for the output voltage is given in Table 21 1 Table 21 1 DAC12 Full Scale Range Vref V REF or VREF Resolution DAC12RES DAC12IR Output Voltage Formula 12 bit 0 0 DAC12_xDAT 12 bit 0 1 DAC12_xDAT Vout Vref x 1096 i 1 eel 9 Vout Vref x 8x DACIA XDA 256 8 bit 1 1 DAC12_xDAT Vout Vref x 956 In 8 bit mode the maximum useable value for DAC12 xDAT is OFFh and in 12 bit mode the maximum useable value for DAC12 xDAT is OFFFh Values greater than these may be written to the register but all leading bits are ignored DAC12 Port Selection The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs When DAC12AMPx gt 0 the DAC 12 function is automatically selected for
43. DCOx Bits These bits select the DCO tap and are modified automatically by the FLL 7 3 MODx Bit 2 Most significant modulator bits Bit 2 is the modulator MSB These bits af fect the modulator pattern All MODx bits are modified automatically by the FLL FLL Clock Module 4 13 FLL Clock Module Registers FLL CTLO FLL Control Register 0 7 6 5 4 3 2 1 0 DCOPLUS XTS FLL XCAPxPF XT20Ft XT1OF LFOF DCOF rw 0 rw 0 rw 0 rw 0 ro ro r 1 r 1 T Not present in MSP430x41x MSP430x42x devices DCOPLUS Bit7 DCO output pre divider This bit selects if the DCO output is pre divided before sourcing MCLK or SMCLK The division rate is selected with the FLL DIV bits 0 DCO output is divided 1 DCO output is not divided XTS FLL Bit 6 LFTX1 mode select 0 Low frequency mode 1 High frequency mode XCAPxPF Bits Oscillator capacitor selection These bits select the effective capacitance 5 4 seen by the LFXT1 crystal or resonator 00 1 pF 01 6pF 10 8pF 11 10 pF XT20F Bit 3 XT2 oscillator fault Not present in MSP430x41x MSP430x42x devices 0 No fault condition present 1 Fault condition present XT10F Bit 2 LFXT1 high frequency oscillator fault 0 No fault condition present 1 Fault condition present LFOF Bit 1 LFXT1 low frequency oscillator fault 0 No fault condition present 1 Fault condition present DCOF Bit 0 DCO oscillator fault 0 No fault condition present 1 Fault condition present 4 14 FLL Clock Module FLL Clock Module Registers
44. Figure 14 3 An idle receive line is detected when 10 or more continuous ones marks are received after the first stop bit of a character When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWAKE bit is used as an address tag for each block of characters In the idle line multiprocessor format this bit is set when a received character is an address and is transferred to UXRXBUF Figure 14 3 Idle Line Format Blocks of pee ae Idle Periods of 10 Bits or More UTXDx URXDx Expanded UTXDx URXDx First Character Within Block Character Within Block Character Within Block Is Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits USART Peripheral Interface UART Mode 14 5 USART Operation UART Mode 14 6 The URXWIE bit is used to control data reception in the idle line multiprocessor format When the URXWIE bit is set all non address characters are assembled but not transferred into the UxRXBUF and interrupts are not generated When an address character is received the receiver is temporarily activated to transfer the character to UXRXBUF and sets the URXIFGx interrupt flag Any applicable error flag is also set The user can then validate the received address If an address is received user so
45. Table 14 2 for a 32 768 Hz watch crystal ACLK and a typical 1 048 576 Hz SMCLK The receive error is the accumulated time versus the ideal scanning time in the middle of each bit The transmit error is the accumulated timing error versus the ideal time of the bit period Table 14 2 Commonly Used Baud Rates Baud Rate Data and Errors Divide Divide by A BRCLK 32 768 Hz B BRCLK 1 048 576 Hz Max p d Max Max Baud TX TX RX Rate Ec EI 96 ES 96 ES 96 ical ER ES Error 1200 27 27 31 873 81 81 a 2 0 03 3 2 14 16 USART Peripheral Interface UART Mode USART Operation UART Mode 14 2 7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after or when SWRST 1 UTXIEx is reset after a or when SWRST 1 The operation is shown is Figure 14 10 Figure 14 10 Transmit Interrupt Operation UTXIEx PUC or SWRST l Tees ii Service equested a SWRST Character Moved From Buffer to Shift Register Data written to UXTXBUF IRQA
46. Toggle Reset EQU1 EQU1 EQU1 EQU1 Interrupt Events TBIFG EQUO TBIFG EQUO EQU3 EQU3 EQU3 EQU3 Timer_B Timer B Operation 13 2 4 Capture Compare Blocks Capture Mode Three or seven identical capture compare blocks TBCCRx are present in Timer B Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture is performed The timer value is copied into the TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bitto synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 13 10 Figure 13 10 Capture Signal SCS 1 CCI
47. USART Peripheral Interface UART Mode 14 17 USART Operation UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF An interrupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served when URXSE 0 or when UxRXBUF is read The operation is shown in Figure 14 11 Figure 14 11 Receive Interrupt Operation From URXD SYNC m Valid Start Bit Receiver Collects Character URXSE m O URXIEx Interrupt Service a Requested BRK RXEIE URXWIE pue 14 18 HOS URXIFGx 6 m SWRST PUC UxRXBUF Read URXSE IRQA Character Received or Break Detected URXEIE is used to enable or disable erroneous characters from setting URXIFGx When using multiprocessor addressing modes URXWIE is used to auto detect valid address characters and reject unwanted data characters Two types of characters do not set URXIFGx Erroneous characters when URXEIE 0 L Non address characters when URXWIE 1 When URXEIE 1 a break condition will set the BRK bit and the URXIF Gx flag USART Peripheral Interface UART Mode USART Operation UART Mode Receive Start Edge Detect Operation The URXSE bit enables
48. V1 h Resulting Voltage for V3 SP4 Segment h COMO SP2 OV SP2 Segment Is On V3 SP3 SP Segment Pin V1 Resulting Voltage for V3 Segment b COM1 SP2 H _ ov Segment Is Off V5 LCD Controller 18 9 LCD Controller Operation Figure 18 7 shows an example 2 mux LCD pin out LCD to MSP430 connections and the resulting segment mapping This is only an example Segment mapping in a user s application completely depends on the LCD pin out and on the MSP430 to LCD connections Figure 18 7 2 Mux LCD Example DIGIT8 DIGIT1 Pinout and Connections Display Memory Connections 1 13121110 430 Pins LCD Pinout PIN como com MABOAOh g e c d n 30 1 2 Digits SO gt 1 1f 1 O9Fh b h a f 28 __ S th p oe 26 pua S2 3 1d 1c 4 2 S4 5 21 2 O09Ch EMEN C 22 Digit 6 5 4x 5 2m om R 0 20 S6 7 2d 2c a a d S7 gt 8 2e 2g O9Ah 18 Digit 5 B8 9 3 32a 099h 5 so 4 10 ah db osn o ole 1 9 50 tr s om c eri a Md m S12 gt 13 df 4a 096h Ie aE 10 Digit 3 S13 4 14 4h 4b 095h MEE RENE 2 f gi S14 i5 4d ow L 9 3 sis ris do sch lt gt a S17 18 5h 5b EMEN c c d 2 Digiti S18 gt 19
49. X22 Y 6 Length Two or three words Operation Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 00006h R5 01080h OFF16h 00006h R5 01080h OFF14h 00002h R6 0108Ch OFF14h 00002h 0108Ch OFF12h 04596h PC OFF12h 04596h 0108Ch 01094h 0006h 01094h 01092h 05555h 010921 oi092n 01234h 01080h 01082h 01234h 01082h 01234h RISC 16 Bit CPU 3 11 Addressing Modes 3 3 3 Symbolic Mode The symbolic mode is described in Table 3 6 Table 3 6 Symbolic Mode Description Assembler Code Content of ROM MOV EDE TONI MOV X PC Y PC X EDE PC Y TONI PC Length Two or three words Operation Move the contents of the source address EDE contents of PC X to the destination address TONI contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution con
50. allowing the user to selectfromthe three available clock signals ACLK MCLK and SMCLK For optimal low power performance the ACLK can be configured to oscillate with a low power 32 786 Hz watch crystal providing a stable time base for the system and low power stand by operation The MCLK can be configured to operate from the on chip DCO stabilized by the FLL and can activate when requested by interrupt events The digital frequency locked loop provides decreased start time and stabilization delay over an analog phase locked loop A phase locked loop takes hundreds or thousands of clock cycles to start and stabilize The FLL starts immediately at its previous setting FLL Clock Module 4 5 FLL Clock Module Operation 4 2 2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow current consumption using a 32 768 Hz watch crystal in LF mode 0 A watch crystal connects to XIN and XOUT without any external components The LFXT1 oscillator supports high speed crystals or resonators when in HF mode XTS FLL 1 The high speed crystal or resonator connects to XIN and XOUT LFXT1 may be used with an external clock signal on the XIN pin in either LF or HF mode when XTS FLL 1 The input frequency range is 1 Hz 8 MHz When the input frequency is below 450 KHz the XT1OF bit may be set preventing the CPU from being clocked from the external frequency The software selectable XCAPxPF bits configure the internally provid
51. the MSP430x44x devices implement a second identical USART module USART1 Topic Page 14 1 USART Introduction UART Mode 14 2 USART Operation UART Mode 14 3 USART Registers UART Mode 14 1 USART Introduction UART Mode 14 1 USART Introduction UART Mode 14 2 In asynchronous mode the USART connects the MSP430 to an external System via two external pins URXD and UTXD UART mode is selected when the SYNC bit is cleared UART mode features include Lj 7 or 8 bit data with odd even or non parity Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive L L O Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression and address detection 0 L L Independent interrupt capability for receive and transmit Figure 14 1 shows the USART when configured for UART mode USART Peripheral Interface UART Mode USART Introduction UART Mode Figure 14 1 USAHT Block Diagram UART Mode SWRST URXEx URXEIE URXWIE FE PE OE BRK Receive Control Receive Status Receiver Buffer UXRXBUF RXERR RXWAKE Receiver Shift Register SSELO SP CHAR Baud Rate Gen
52. 0 0 0 0 rw 0 0 rw 0 6 rw rw rw rw 5 4 3 2 1 0 rw 0 SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2 22 42 rw 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Scan IF rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DAC on Setting this bit turns the DAC on regardless of the TSM control 0 The DAC is controlled by the TSM 1 The DAC is on Comparator on Setting this bit turns the comparator on regardless of the TSM control 0 The comparator is controlled by the TSM 1 The comparator is on Invert comparator output 0 Comparator output is not inverted 1 Comparator output is inverted Comparator input select This bit selects groups of signals for the comparator input 0 Comparator input is one of the SIFCHx channels selected with the channel select logic 1 Comparator input is one of the SIFCIx channels selected with the channel select logic and the SIFCISEL and SIFCACIS bits Comparator input select This bit is used with the SIFCACI3 bit to select the comparator input when SIFCAX 1 0 Comparator input is one of the SIFCIx channels selected with the channel select logic and SIFCACIS bit 1 Comparator input is the SIFCI channel Comparator input select This bit is selects the comparator input when SIFCISEL 0 and SIFCAX 1 0 Comparator input is selected with the channel select logic 1 Comparator input is
53. 0 5 OA Registers Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR OA 16 11 OA Registers OAxCTLO Opamp Control Register 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 OANx Bits Inverting input select These bits select the input signal for the OA inverting 7 6 input 00 OAXxIO 01 OAxMH 10 DACO internal 11 DAC 1 internal OAPx Bits Non inverting input select These bits select the input signal for the OA 5 4 non inverting input 00 OAxI0 01 10 DACO internal 11 DAC1 internal OAPMx Bits Slew rate select These bits select the slew rate vs current consumption for 3 2 the OA 00 Off output high Z 01 Slow 10 Medium 11 Fast OAADC1 Bit 1 OA output select This bit connects the OAx output to ADC12 input Ax when OAFCx gt 0 0 OAx output not connected to A1 A3 OA1 or A5 OA2 1 OAx output connected to A1 OA1 or A5 OA2 OAADCO Bit 0 OA output select This bit connects the OAx output to ADC12 input Ax 0 OAx output not connected to A12 A13 OA1 or A14 OA2 1 OAx output connected to A12 A13 OA1 or A14 OA2 16 12 OA OA Registers OAxCTL1 Opamp Control Register 1 7 5 4 3 2 1 0 OAFBRx OAFCx OARRIP rw 0 OAFBRx OAFCx Reserved OARRIP rw 0 Bits 7 5 Bits 4 2 Bit 1 Bit 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 OAx feedback resistor select 000 001
54. 0 1 SIFREPEATX x 1 facLK lt T lt SIFREPEATx 1 x 1 fACLK 1 0 SIFREPEATx 1 x 1 1 lt T lt SIFREPEATx 2 x lfsiFCLK 1 1 T SIFREPEATx 1 x t faci Scan IF Operation TSM State Clock Source Select The TSM clock source is individually configurable for each state The TSM can be clocked from ACLK or a high frequency clock selected with the SIFACLK bit When SIFACLK 1 ACLK is used for the state and when SIFACLK 0 the high frequency clock is used The high frequency clock can be sourced from SMCLK or the TSM internal oscillator selected by the SIFCLKEN bit The ACLK source can be divided by 1 2 4 or 8 with the SIFDIV2x bits and the high frequency clock can be divided by 1 2 4 or 8 with SIFDIV1x bits A set SIFCLKON bitis used to turn on the selected high frequency clock source for the duration of the state when it is not used for the state If the DCO is selected as the high frequency clock source it is automatically turned on regardless of the low power mode settings of the MSP430 The TSM internal oscillator generates a nominal frequency of 1MHz or 4MHz selected by the SIFFNOM bit and can be tuned in nominal 5 steps from 40 to 35 with the SIFCLKFQx The frequency and the steps differ from device to device See the device specific datasheet for parameters The TSM internal oscillator frequency can be measured with ACLK When SIFCLKEN 1 and SIFCLKGON 1 SIFONT3 is reset and beginning with
55. 1 After generation of the SIFSTOP tsm pulse the timing state machine will load and maintain the conditions defined in SIFTSMO In this state SIFLCEN tsm should be reset to ensure that all LC oscillators are shorted Figure 22 8 Timing State Machine Block Diagram SIFDIV3A SIFDIV3Bx Scan Period Scan IF Operation Set SIFIFG2 ACLK Divider 4 1255 SIFDIV2x Divider 1 2 4 8 SIFCLKEN SIFDIV1x SMCLK Divider 1 2 4 8 SIFEN SIFTSMRP SIFCHO SIFCH1 SIFLCEN SIFEX SIFCA SIFCLKON SIFRSON SIFTESTS1 SIFDAC SIFSTOP SIFACLK SIFREPEATO SIFREPEAT1 SIFREPEAT2 ACLK State Pointer and Control SIFCLK Stop SIFACLK SIFREPEATx SIFCHx tsm SIFLCEN tsm SIFEX tsm SIFCA tsm SIFCLKON tsm gt SIFRSON tsm Ls SIFTESTS1 tsm gt SIFDAC tsm t SIFSTOP tsm Set_SIFIFG1 SIFREPEAT3 SIFREPEAT4 SIFTSM22 SIFTSM23 SIFFNOM SIFOSC Out Enable SIFCLKFQx o SIFCLKGON SIFCLKEN U D SIFFLLON tsm Scan IF 22 15 Scan IF Operation TSM Operation The TSM state machine automatically starts and re starts periodically based on a divided ACLK start signal The SIFDIVSAx and SIFDIV3Bx bits select the ACLK division rate for the start signal when SIFTSMRP 0 For example if SIFDIV3A and SIFDIV3B are configured to 270 ACLK cycles then the TSM automatically starts every 270 ACLK cycles When SIFTSMRP
56. 1 Basic Timer1 interrupt enable This bit enables the BTIFG interrupt Because other bits in IE2 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 0 BTIFG Bit 7 Bits Basic Timer1 interrupt flag Because other bits in IFG2 may be used for other modules it is recommended to clear BTIFG automatically by servicing the interrupt or by using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet Basic Timer1 11 9 11 10 Basic Timer1 Chapter 12 Timer_A Timer Aisa 16 bittimer counter with multiple capture compare registers This chapter describes Timer A Timer A3 three capture compare registers is implemented in all MSP430x4xx devices Timer1 A5 five capture compare registers is also implemented on MSP430x415 MSP430x417 and MSP430xWA2x devices Topic Page jt2 irimergAsIntrod uctiongi 12 2 22 T 12 4 12 3 Timer A Registers eo ere oaa E ere 12 19 12 1 Timer A Introduction 12 1 Timer A Introduction 12 2 Timer A
57. 10 R13 ADD LSDs with no carry in ADDC B R13 10 R13 ADD medium Bits with carry ADDC B R13 10 R13 ADD MSDs with carry resulting from the LSDs RISC 16 Bit CPU 3 23 Instruction Set AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst gt dst The source operand and the destination operand are logically ANDed The result is placed into the destination N Set if result MSB is set reset if not set 2 Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 are used as a mask HOAA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI ee Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 40A5h are logically ANDed with the low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with OA5h JZ TONI Result is not zero 3 24 RISC 16 Bit CPU BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Clear bits in destination Clear bits in destination BIC src dst
58. 2 5 Frequency Locked Loop FLL The FLL continuously counts up or down a 10 bit frequency integrator The output of the frequency integrator that drives the DCO can be read in SCFI1 and SCFIO The count is adjusted 1 or 1 with each ACLK crystal period Five of the integrator bits SCFI1 bits 7 3 set the DCO frequency tap Twenty nine taps are implemented for the DCO 28 29 30 and 31 are equivalent and each is approximately 10 higher than the previous The modulator mixes two adjacent DCO frequencies to produce fractional taps SCFI1 bits 2 0 and SCFIO bits 1 0 are used for the modulator The DCO starts at the lowest tap after a PUC or when SCFIO and SCFI1 are cleared Time must be allowed for the DCO to settle on the proper tap for normal operation 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle FLL Clock Module 4 7 FLL Clock Module Operation 4 2 6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy reducing electromagnetic interference EMI The modulator mixes the two adjacent frequencies across 32 DCOCLK clock cycles The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate The modulator settings and DCO control are automatically controlled by the FLL hardware Figure 4 3 illustrates the modulator operation Figure 4 3 Modulator P
59. 4 Pulse Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete SHI 4 sample gt 4 Iconvert 3 isync 19 8 ADC12 ADC12 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsampje as shown below in Figure 19 5 An internal MUX on input resistance Ry max 2 in series with capacitor Cj max 40 pF is seen by the source The capacitor C voltage Vc must be charged to within 1 2 LSB of the source voltage Vs for an accurate 12 bit conversion Figure 19 5 Analog Input Equivalent Circuit Vs Rs MSP430 V Input voltage at pin Ax RI Vs External source voltage M Rgs External source resistance VC Internal MUX on input resistance Input capacitance CI Capacitance charging voltage The resistance of the source Rg and Hj affect tsample The following equation can be used to calculate the minimum sampling time tsample for a 12 bit conversion t Rg x In 213 x C 800ns gt sample Substituting the values for Rj and C given above the equation becomes t Rg 2kQ x 9 011 x 40pF 800ns gt sample For example if Rg is 10 tsample must be greater than 5 13 us ADC12 19 9 ADC12 Operation 19 2 5 Conversion Memory There are 16 ADC12MEMXx conversion memory regist
60. 514 kHz lt 0 FWKEY FSSEL1 FNO amp FCTL2 FWKEY amp FCTL3 FWKEY ERASE amp FCTL1 amp OFC10h BUSY amp FCTL3 L2 FWKEY LOCK amp FCTL3 Flash Memory Controller SMCLK lt 952 kHz Disable WDT Test BUSY Loop while busy SMCLK 2 Clear LOCK Enable erase Dummy write erase 51 Test BUSY Loop while busy set LOCK Re enable WDT Done 5 7 Flash Memory Operation 5 3 3 Writing Flash Memory The write modes selected by the WRT and BLKWRT bits are listed in Table 5 1 Interrupts are automatically disabled during a flash write and re enabled after the write Any interrupt that occurred during the write will have its associated flag set and will generate an interrupt request when re enabled Table 5 2 Write Modes Byte Word Write BLKWRT WRT Write Mode 0 1 Byte word write 1 1 Block write Both write modes use a sequence of individual write instructions but using the block write mode is approximately twice as fast as byte word mode because the voltage generator remains on for the complete block write Any instruction that modifies a destination can be used to modify a flash location in either byte word write mode or block write mode The BUSY bit is set while a write operation is active and cleared when the operation completes If the write operation is initiated from RAM the CPU must not access flash while BUSY 1 Otherwise an access violation occurs ACCVIFG is set and the flash w
61. 8 or 12 bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2 s compliment data format Self calibration option for offset correction ooo s5 L Q Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12 xDAT or DAC12 xCTL to describe register names When this occurs the x is used to indicate which DAC12 module is being discussed In cases where operation is identical the register is simply referred to as DAC12 xCTL The block diagram of the two DAC12 modules in the MSP430FG43x devices is shown in Figure 21 1 DAC12 Introduction Figure 21 1 DAC12 Block Diagram Ve REF gt __e _ _ _ To ADC 12 module VREF e e 2 5V or 1 5V reference from ADC12 DAC12SREFx DAC12AMPx DAC12IR 00 01 10 11 VR DAC12LSELx DAC12_0 DAC12_0OUT Latch Bypass DAC12RES DAC12DF DAC12 OLatch 4 DAC12_0DAT DAC12GRP PIS ENC DAC12_0DAT Updated DAC12SREFx DAC12AMPx DAC12IR 00 3 01 10 DAC12LSELx DAC12_1 DAC12 1OUT 4
62. A transfer is triggered when the TACCR2 CCIFG flag is set The TACCR2 CCIFG flag is automatically reset when the transfer starts If the TACCR2 CCIE bit is set the TACCR2 CCIFG flag will not trigger transfer A transfer is triggered when the TBCCR2 CCIFG flag is set The TBCCR2 CCIFG flag is automatically reset when the transfer starts If the TBCCR2 CCIE bit is set the TBCCR2 CCIFG flag will not trigger transfer A transfer is triggered when USARTO receives new data In 12 mode the trigger is the data received condition not the RXRDYIFG flag RXRDYIFG is not cleared when the transfer starts and setting RXRDYIFG with software will not trigger a transfer If RXRDYIE is set the data received condition will not trigger a transfer In UART or SPI mode a transfer is triggered when the URXIFGO flag is set URXIFGO is automatically reset when the transfer starts If URXIEO is set the URXIFGO flag will not trigger a transfer A transfer is triggered when USARTO is ready to transmit new data In 12C mode the trigger is the transmit ready condition not the TXRDYIFG flag TXRDYIFG is not cleared when the transfer starts and setting TXRDYIFG with software will not trigger a transfer If TXRDYIE is set the transmit ready condition will not trigger a transfer In UART or SPI mode a transfer is triggered when the UTXIFGO flag is set UTXIFGO is automatically reset when the transfer starts If UTXIEO is set the UTXIFGO flag will not trigger a tra
63. Bits These bits may be used by other modules See device specific datasheet 5 0 IE2 Interrupt Enable Register 2 T 6 5 4 3 2 1 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 3 0 14 28 USART Peripheral Interface UART Mode USART Registers UART Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGOt Bit7 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFGOT Bit6 USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Bits These bits may be used by other modules See device specific datasheet 5 0 IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interrupt pending 1 Interrupt pending URXIFG1 Bit 4 USART1 receive interrupt flag URXIFG1 is set when U1 RXBUF has received a complete cha
64. DAC12 21 11 DAC12 Registers DAC12 AMPx DAC12DF DAC12IE DAC12IFG DAC12 ENC DAC12 GRP 21 12 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC12 DAC12 amplifier setting These bits select settling time vs current consumption for the DAC12 input and output amplifiers DAC12AMPx Input Buffer 000 Off 001 Off 010 Low speed current 011 Low speed current 100 Low speed current 101 Medium speed current 110 Medium speed current 111 High speed current DAC12 data format 0 Straight binary 1 2 s compliment DAC12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending Output Buffer DAC12 off output high Z DAC12 off output 0 V Low speed current Medium speed current High speed current Medium speed current High speed current High speed current DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx gt 0 when DAC12LSELx 0 DAC12ENC is ignored 0 DAC12 disabled 1 DAC12 enabled DAC12 group Groups DAC12 x with the next higher DAC12 x Not used for DAC12 1 on MSP430FG43x devices 0 Not grouped 1 Grouped DAC12 Registers DAC12 xDAT DAC12 Data Register 15 14 13 12 11 10 9 8 0 0 0 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused These bits are always 0 and do not affect the DAC12 core 15 12 DAC12 Data Bits DAC12 data 11 0 DAC12 Data
65. DMA size The DMA size register defines the number of byte word data per 15 0 block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 00000h Transfer is disabled 00001h One byte or word is transferred 00002h Two bytes or words are transferred OFFFFh 65535 bytes or words are transferred 90 N 8 24 Chapter 9 Digital 1 0 This chapter describes the operation of the digital I O ports Ports P1 P6 are implemented in all MSP430x4xx devices Topic Page iDigitall O Introductionn 19 2 927 19 3 9 3 Digital l O Registers sses nonesma smaa aasa 9 7 9 1 Digital I O Introduction 9 1 Digital I O Introduction 9 2 Digital I O MSP430 devices have up to 6 digital I O ports implemented P1 P6 Each port has eight I O pins Every I O pin is individually configurable for input or output direction and each I O line can be individually read or written to Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmabl
66. FLL loop control Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPU off This bit when set turns off the CPU General interrupt enable This bit when set enables maskable interrupts When reset all maskable interrupts are disabled Negative bit This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative Word operation N is set to the value of bit 15 of the result N is set to the value of bit 7 of the result Byte operation Zero bit This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0 Carry bit This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred 3 2 4 Constant Generator Registers CG1 and CG2 CPU Registers Six commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 3 2 Table 3 2 Values of Constant Generators CG1 CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 The constant generator advantages are As 00 01 10 11 00 01 10 11 Constant 0 00004h 00008h 00000h 00001h 00002h OFFFFh No special instructions required Remarks Register mode Absolute address mode
67. Format DAC12 Data 12 bit binary The DAC 12 data are right justified Bit 11 is the MSB 12 bit 2 s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC 12 data are right justified Bit 7 is the MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2 s complement The DAC 12 data are right justified Bit 7 is the MSB sign Bits 11 8 are don t care and do not effect the DAC12 core DAC12 21 13 21 14 DAC12 Chapter 22 Scan IF The Scan IF peripheral automatically scans sensors and measures linear or rotational motion This chapter describes the Scan interface The Scan IF is implemented in the MSP430FW42x devices Topic Page 22 1 Sean IF introd ctionc tele 22 2 222 Scanill SE 22 4 22 3 5 181 amp 22 35 22 1 Scan IF Introduction 22 1 Scan IF Introduction 22 2 Scan IF The Scan IF module is used to automatically measure linear or rotational motion with the lowest possible power consumption The Scan IF consists of three blocks the analog front end AFE the processing state machine PSM and the timing state machine TSM The analog front end stimulates the sensors senses the signal levels and converts them into their digital representation The digital signals are passed into the processing state machine The processing state machine is used to analyze
68. MCLK LFXT1CLK 4 MCLK cycles Low power mode LPMO 1 MCLK DCOCLK 5 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 5 MCLK cycles 6 ust Low power mode LPMO 1 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 5 MCLK cycles 6 ust T The additional 6 us are neededto start the DCOCLK It is the t L PMx Parameter in the data sheet 8 15 8 2 7 Using with System Interrupts DMA transfers are not interruptible by system interrupts System interrupts remain pending until the completion of the transfer NMI interrupts can interrupt the DMA controller if the ENNMI bit is set System interrupt service routines are interrupted by DMA transfers If an interrupt service routine or other routine must execute with no interruptions the DMA controller should be disabled prior to executing the routine 8 2 8 DMA Controller Interrupts 8 16 Each DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero If the corresponding DMAIE and GIE bits are set an interrupt request is generated All DMAIFG flags source only one DMA controller interrupt vector and the interrupt vector is shared with the DAC12 module Software must check the DMAIFG and DAC12IFG flags to determine the source of the interrupt The DMAIFG flags are not reset automatically and must be reset by software 8 2 9 Using the I2C Module with the
69. Mode Comparator Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAxCTLO bits define the signal routing The OAx inputs are selected with the OAPx and OANXx bits The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits In this mode the output of the OAx is connected to and the inverting input of the OAx providing a unity gain buffer The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANXx bits are don t care The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits In this mode the output of the OAx is isolated from the resistor ladder is connected to AVss and Rgorrow is connected to AVcc The OAxTAP signal is connected to the inverting input of the OAx providing a comparator with a programmable threshold voltage selected by the OAFBRx bits The non inverting input is selected by the OAPx bits Hysteresis can be added by an external positive feedback resistor The external connection for the inverting input is disabled and the OANXx bits are don t care The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits OA 16 5 Non Inverting PGA Mode Inverting PGA Mode In this mode the output of the OAx is connected to and Rpgorrow is connected to AVss The OAXTAP signal is connected t
70. SD16 Channel 1 Input Control SD16INCTL1 Read write OBih Reset with PUC SD16 Channel 1 Preload SD16PRE1 Read write OB9h Reset with PUC SD16 Channel 2 Control SD16CCTL2 Read write 0106h Reset with PUC SD16 Channel 2 Conversion Memory SD16MEM2 Read write 0116h Reset with PUC SD16 Channel 2 Input Control SD16INCTL2 Read write OB2h Reset with PUC SD16 Channel 2 Preload SD16PRE2 Read write OBAh Reset with PUC 20 18 SD16 SD16 Registers SD16CTL SD16 Control Register 15 ro 7 rw 0 Reserved SD16LP SD16DIVx SD16SSELx SD16 VMIDON SD16 REFON SD160VIE Reserved 14 8 ro Bits 15 9 Bit 8 Bits 7 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 13 12 11 10 9 ro ro ro ro rw 0 5 4 3 2 1 0 SD16 SD16 SD16DIVx SD16SSELx VMIDON REFON SD160VIE rw 0 rw 0 rw 0 ro rw 0 rw 0 rw 0 Reserved Low power mode This bit selects a reduced speed reduced power mode for the SD16 0 Low power mode is disabled 1 Low power mode is enabled The maximum clock frequency for the SD16 is reduced SD16 clock divider 00 A 01 2 10 4 11 8 SD16 clock source select 00 MCLK 01 SMCLK 10 ACLK 11 External TACLK buffer on 0 Off 1 On Reference generator on 0 Reference off 1 Reference on SD16 overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled Reserved SD16 20 19 SD16 Registers
71. SD16CCTLx SD16 Channel x Control Register 15 14 13 12 11 10 9 8 ro ro ro ro ro rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 3016 18016 5016 spt6pF SD16IFG SD16SC SD16GRP rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r w 0 Reserved Bits Reserved 15 11 SD16SNGL Bit10 Single conversion mode select 0 Continuous conversion mode 1 Single conversion mode SD160SRx Bits Oversampling ratio 9 8 00 256 01 128 10 64 11 32 SD16 Bit 7 LSB toggle This bit when set causes SD16LSBACC to toggle each time LSBTOG the SD16MEM x register is read 0 SD16LSBACC does not toggle with each SD16MEMXx read 1 SD16LSBACC toggles with each SD16MEMx read SD16 Bit 6 LSB access This bit allows access to the upper or lower 16 bits of the LSBACC SD16 conversion result 0 SD16MEMXx contains the most significant 16 bits of the conversion 1 SD16MEM x contains the least significant 16 bits of the conversion SD160VIFG 5 5016 overflow interrupt flag 0 No overflow interrupt pending 1 Overflow interrupt pending SD16DF Bit 4 5016 data format 0 Offset binary 1 2 s complement SD16IE Bit 3 SD16 interrupt enable 0 Disabled 1 Enabled 20 20 SD16 SD16IFG SD16SC SD16GRP Bit 2 Bit 1 Bit 0 SD16 Registers 5016 interrupt flag SD16IFG is set when new conversion results are available SD16IFG is automatically reset when the corresponding SD16MEMXx register is read or may be cleared with software 0 No interrupt pending 1 Interrupt pend
72. SIFS1x and SIFS2x bits 22 44 Scan IF SIFIFGSETx Bits SIF3OUT SIF2OUT SIF1OUT SIFOOUT 6 4 Bit 3 Bit 2 Bit 1 Bit 0 Scan IF Registers SIFIFGO interrupt flag source These bits select when the SIFIFGO flag is set 000 001 010 011 100 101 110 111 SIFIFGO is set when SIFOOUT is set SIFIFGO is set when SIFOOUT is reset SIFIFGO is set when SIF1OUT is set SIFIFGO is set when SIF1OUT is reset SIFIFGO is set when SIF2OUT is set SIFIFGO is set when SIF2OUT is reset SIFIFGO is set when SIF3OUT is set SIFIFGO is set when SIF3OUT is reset AFE output bit 3 AFE output bit 2 AFE output bit 1 AFE output bit O Scan IF 22 45 Scan IF Registers SIFCTLA Scan IF Control Register 4 15 14 13 12 11 10 9 8 E woe om rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SIFCNTRST Bit 15 Counter reset Setting this bit enables the SIFCNT register to be reset when it is read 0 SIFCNT register is not reset when read 1 SIFONT register is reset when it is read SIFCNT2EN Bit14 SIFCNT2 enable 0 SIFCNT2 is disabled 1 SIFCNT2 is enabled SIFCNT1 Bit 13 SIFCNT1 decrement enable ENM 0 SIFCNT1 decrement is disabled 1 SIFCNT1 decrement is enabled SIFCNT1 Bit 12 SIFCNT1 increment enable ENP 0 SIFCNT1 increment is disabled 1 SIFCNT1 increment is enabled SIFQ7EN Bit 11 Q7 enable This bit enables bit Q7 for the next PSM state calculatio
73. SP2 a V1 olf SP2 Resulting Voltage for eto n SP3 J Vi SP5 SP8 Resulting Voltage for n U Az Segment b COMO SP2 0 V S t Is Off SP Segment Pin SERM 18 6 LCD Controller LCD Controller Operation Figure 18 5 shows an example static LCD pin out LCD to MSP430 connections and the resulting segment mapping This is only an example Segment mapping in a user s application depends on the LCD pin out and on the MSP430 to LCD connections Figure 18 5 Static LCD Example Pinout and Connections Display Memory Connections COM 3 2 1 0 2 1 0 430 Pins LCD Pinout PIN COMO 0AO0h n 30 S0 gt 1 1 O9Fh 28 51 gt 2 1b O9Eh 26 Digit 4 AH ama e 09Dh 204 _ G4 uw 5 1e 09Ch 22 S5 gt 6 1f O9Bh 20 NE S6 gt 7 1g 09Ah 18 Digit 3 S7 gt 8 1h S8 9 2a 099h 16 __ s9 10 2b 098h 14 S10 4 11 2c 097h 12 511 4 9 12 2d 096h 10 Digit 2 512 gt 13 2e 913 4 14 2 095h 8 __ S14 4 15 2g 094h 6 515 16 2h 4 E S16 lt 17 0988 Digit 1 S17 4 18 3b 092h S18 4 19 3c 091h 0 __ 519 4 20 520 4 21 521 4 22 3f Parallel Serial S22 gt 23 3g Conversion S23 lt 24 3h 524 gt 25 4a S25 4 26 4b s26 4 27 4 Sn 1 Sn S27 28 4d S28 4 29 4e S29 gt 30 4f S30 31 4g 531 0 32 4h
74. Tap 1 010 Tap 2 011 100 Tap4 101 5 110 111 Tap7 OAx function control This bit selects the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Comparing amplifier 100 Non inverting amplifier 101 Reserved 110 Inverting amplifier 111 Differential amplifier Reserved OA rail to rail input off 0 input signal range is rail to rail 1 OAx input signal range is limited See device datasheet for parameters OA 16 13 16 14 17 Comparator A Comparator A is an analog voltage comparator This chapter describes Comparator A Comparator A is implemented in all MSP430x4xx devices Topic Page 17 1 Comparator A Introduction 17 2 Comparator A Operation 17 3 Comparator A Registers 17 1 Comparator A Introduction 17 1 Comparator A Introduction The comparator A module supports precision slope analog to digital conversions supply voltage supervision and monitoring of external analog signals Features of Comparator A include Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator L L L LL Oo Q Comparator and reference generator can be powered down The Comparator_A block diagr
75. Timer A Registers 13 Timer RT aide adu 13 3 Timer B Introduction x Ev 13 1 1 Similarities and Differences From Timer A 13 2 Timer B Operation 13 2 1 16 Bit Timer Counter 13 2 2 Starting the Timer 00 cece eet n 13 2 3 Timer Mode Control eect e 13 2 4 Capture Compare Blocks 13 2 5 Output Unit a ec ees iod ean se redonda Ro dee 13 2 6 Timer B Interrupts RR RIPE REE 13 3 Timer B Registers 14 USART Peripheral Interface UART Mode 14 1 USART Introduction UART Mode 14 2 USART Operation UART Mode 14 2 1 USART Initialization and Reset 14 2 2 Character Format 0 0 ccc cette cnet nee n eens 14 2 3 Asynchronous Communication 14 2 4 USART Receive Enable 14 2 5 USART Transmit Enable 14 2 6 UART Baud Rate 14 2 7 USART Interrupts aen aeee parta n 14 3 USART Registers UART Mode 15 USART Peripheral Interface SPI Mode 15 1 USART Introduction SP
76. Tl intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice Tl is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated About This Manual Preface Read This First This manual discusses modules and peripherals of the MSP430x4xx family of devices Each
77. USART Peripheral Interface SPI Mode USART Operation SPI Mode 15 2 6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after or when SWRST 1 UTXIEx is reset after a or when SWRST 1 The operation is shown is Figure 15 10 Figure 15 10 Transmit Interrupt Operation UTXIEx r SYNC 1 L 4 PUC or SWRST Interrupt Service Requested UTXIFGx Voc Character Moved From Buffer to Shift Register SWRST Data moved to UXTXBUF IRQA Note Writing to UXTXBUF in SPI Mode Data written to UXTXBUF when UTXIFGx 0 and USPIEx 1 may result in erroneous data transmission LLLLLLLLL 3 USART Peripheral Interface SPI Mode 15 11 USART Operation SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF as shown in Figure 15 11 and Figure 15 12 An interrupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are r
78. Watchdog Timer Interrupts 10 2 5 WDT Enhancements 10 2 6 Operation in Low Power 10 2 7 Software Examples 10 3 Watchdog Timer Registers Contents 11 Basic TImer uuu see x ux xxu a a em 11 1 Basic Timer Introduction isssseseseee RR RII 11 2 Basic Timer Operation siissssssssssssssses 11 2 1 Basic Timer1 Counter One 11 2 2 Basic Timer1 Counter Two 11 2 3 16 bit Counter Mode nea 11 2 4 Basic Timer1 Operation Signal fLCD 11 2 5 Basic Timer Interrupts 0 00 cece eh 11 8 Basic Timerl Registers ontsa ti een 12 imer A eoo beds Cod doce Dua eere hid erac ta 12 1 Timer A Introduction 12 2 Timer A Operation 0 cece ttn eee 12 2 1 16 Bit Timer Counter odie sierici 0 0 ccc tenes 12 2 2 Starting the Timer wii ccs cen ck ode he eee ee eed ie epa 12 2 8 Timer Mode Control cee ete eee 12 2 4 Capture Compare Blocks 12 2 5 Output UNI 225 geata a aE d a a seat ore Penaeeeea ened 12 2 6 Timer_A Interrupts 2 5 esie pedes tieng Rave das 12 3
79. a multichannel 16 bit sigma delta analog to digital converter This chapter describes the SD16 The SD16 module is implemented the MSP430FE42x and MSP430F42x devices Topic Page 20 1 SD16 Introduction eri el 20 2 202 SD1b OD5rallon eem 20 4 20 3 SD167Registers 20 17 SD16 Introduction 20 1 SD16 Introduction 20 2 SD16 The SD16 module consists of up to three independent sigma delta analog to digital converters and an internal voltage reference Each channel has up to 8 fully differential multiplexed inputs including a built in temperature sensor The converters are based on second order oversampling sigma delta modulators and digital decimation filters The decimation filters are comb type filters with selectable oversampling ratios of up to 256 Additional filtering can be done in software Features of the SD16 include H O O O Oe m 16 bit sigma delta architecture Up to 3 independent simultaneously sampling ADC channels Up to 8 multiplexed differential analog inputs per channel Software selectable on chip reference voltage generation 1 2V Software selectable internal or external reference Built in temperature sensor accessible by all channels Up to 1 048576 MHz modulator input frequency fsample 4096kHz 256x oversampling Selectable low power conversion mode The block diagram of the SD16 module is shown in Figure 20 1 SD16 Introduction
80. a number in the TBIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer B interrupts do not affect the TBIV value Any access read or write of the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TBCCR 1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register TBCCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TBCCR2 CCIFG flag will generate another interrupt Timer B Operation TBIV Interrupt Handler Examples Thefollowing software example shows the recommended use of TBIV and the handling overhead The TBIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU clock cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR6 16 cycles Timer overflow TBIFG 14 cycles The following software example shows the recommended use of TBIV for Timer B3 Interrupt handler for TBC
81. a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt 0 before operation is performed the result has changed sign Figure 3 14 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 pego cet Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the MSB V Setif an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multiplied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 2 RLA B R7 Shift left low byte of R7 x 4 Note RLA Substitution The assembler does not recognize the instruction RLA R5 nor RLA B QRb5 It must be substituted by ADD R5 2 R5 or ADD B R5 1 R5 3 58 RISC 16 Bit CPU RLC W RLC B Syntax Operation Emulation Description Instruction Set Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C MSB lt MSB 1 LSB 1 lt LSB lt ADDC dst dst The destination operand is shifted left one
82. a state with a set Q6 bit SIFIFG5 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 4 This bitis set by the SIFCNT2 counter conditions selected with the SIFIS2x bits SIFIFG4 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 3 This bitis set by the SIFCNT1 counter conditions selected with the SIFIS1x bits SIFIFG3 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 2 This bit is set at the start of a TSM sequence SIFIFG2 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 1 This bit is set by the rising edge of the SIFSTOP tsm signal SIFIFG1 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 0 This bit is set by the SIFXOUT conditions selected by the SIFIFGSETx bits SIFIFGO must be reset with software 0 No interrupt pending 1 Interrupt pending Scan IF Registers SIFTESTD 1 Test cycle insertion Setting this bit inserts a test cycle between TSM cycles SIFTESTD is automatically reset at the end of the test cycle 0 No test cycle inserted 1 Test cycle inserted between TSM cycles SIFEN Bit 0 Scan interface enable Setting this bit enables the Scan IF 0 Scan IF disabled 1 Scan IF enabled Scan IF 22 41 Scan IF Registers SIFCTL2 Scan IF Control Register 2 rw 0 7 15 14 13 12 11 10 9 8 rw
83. addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits The DMASRCINCRXx bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCRx bits select if the destination address is incremented decremented or unchanged after each transfer Transfers may be byte to byte word to word byte to word or word to byte When transferring word to byte only the lower byte of the source word transfers When transferring byte to word the upper byte of the destination word is cleared when the transfer occurs Figure 8 2 DMA Addressing Modes 8 4 DMA DMA Controller Address Space Controller Address Space Fixed Aadress To Fixed Address Fixed Address To Block Of Addresses DMA DMA Controller Address Space Controller Address Space Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses 8 2 2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 8 1 Each channel is individually configurable for its transfer mode For example channel 0 may be configured in single transfer mode while channel 1 is configured for burst block transfer mode and channel 2 operates in repeated block mode The transfer mode is configured independently from the addressing mode Any addressing mode can be used with any transfer
84. affected The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 gt COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 m Continue with COUNT20 RISC 16 Bit CPU 3 49 Instruction Set JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example Jump if carry not set Jump if lower JNC label JLO label if C 20 PC 2x offset gt PC if C 2 1 execute following instruction The status register carry bit C is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the next instruction following the jump is executed JNC jumpif no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT ids Error handler start is Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 CMP B 2 STATUS JLO STL2 STATUS lt 2 T STATUS 2 2 continue here 3 50 RISC 16 Bit CPU JNE JNZ Syntax Operation Description Status Bits Example Instruction Set Jump if not equal Jump if not zero JNE la
85. an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12 2 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 12 2 Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated The output is set when the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is toggled when the timer counts to the TACCRx value The output period is double the timer period The output is reset when the timer counts to the TACCRx value It remains reset until another output mode is selected and affects the output The output is
86. and has a dedicated interrupt vector as shown in Figure 12 15 The TACCRO CCIFG flag is automatically reset when the TACCRO interrupt request is serviced Figure 12 15 Capture Compare TACCRO Interrupt Flag Capture IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer A interrupts do not affect the TAIV value Any access reador write of the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TACCR 1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register TACCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TACCR2 CCIFG flag will generate another interrupt Timer A 12 17 Timer A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the
87. be enabled to generate an NMI interrupt by setting the ACCVIE bit The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation 2 8 System Resets Interrupts and Operating Modes System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple source interrupt An NMI interrupt automatically resets the NMIIE OFIE and ACCVIE interrupt enable bits The user NMI service routine resets the interrupt flags and re enables the interrupt enable bits according to the application needs as shown in Figure 2 5 Figure 2 5 NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIE ACCVIE Reset OFIFG Reset ACCVIFG Reset NMIIFG User s Software User s Software User s Software Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional v Set NMIIE OFIE Example 1 ds within One BIS NMIIE OFIE ACCVIE amp 1 Instruction Example 2 BIS Mask amp 1 1 Mask enables only RETI End of NMI Interrupt Handler interrupt sources E 4 wer a a Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE The ACCVIE NMIIE and OFIE enable bits should not be set inside of an NMI interrupt service routine unless they are set by the last instruction of the routine before the RETI instruction Otherw
88. by setting the BTHOLD and BTDIV bits Counter Two The Basic Timer counter two BTCNT2 is an 8 bit timer counter directly accessible by software BTCNT2 can be sourced from ACLK or SMCLK or ACLK 256 when cascaded with BTCNT1 The BTCNT2 clock source is selected with the BTSSEL and BTDIV bits BTCNT2 can be stopped to reduce power consumption by setting the HOLD bit BTCNT2 sources the Basic Timer1 interrupt BTIFG The interrupt interval is selected with the BTIPx bits a SO aa Note Reading or Writing BTCNT1 and BTCNT2 When the CPU clock and counter clock are asynchronous any read from BTCNT1 or BTCNT2 may be unpredictable Any write to BTCNT1 or BTCNT2 take effect immediately 11 2 3 16 bit Counter Mode 11 4 Basic Timer1 The 16 bit timer counter mode is selected when control the BTDIV bit is set In this mode BTCNT1 is cascaded with BTCNT2 The clock source of BTCNT1 is ACLK and the clock source of BTCNT2 is ACLK 256 Basic Timer1 Introduction 11 2 4 Basic Timer1 Operation Signal fj cp 11 2 5 Basic Timer1 The LCD controller uses the fj cp signal from the BTCNT1 to generate the timing for common and segment lines ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating cp The fj cp frequency is selected with the BTFRFQx bits and can by ACLK 256 ACLK 128 ACLK 64 or ACLK 32 The proper fj cp frequency depends on the LCD s frame frequency and the LCD multiplex rate and is calculated by fi cp
89. counts The timer repeatedly counts up to the value of compare latch TBCLO which defines the period as shown in Figure 13 2 The number of timer counts in the period is TBCLO 1 When the timer value equals TBCLO the timer restarts counting from zero If up mode is selected when the timer value is greater than TBCLO the timer immediately restarts counting from zero Figure 13 2 Up Mode TBR max TBCLO Oh The TBCCRO CCIFG interrupt flag is set when the timer counts to the TBCLO value The TBIFG interrupt flag is set when the timer counts from TBCLO to zero Figure 12 3 shows the flag set cycle Figure 13 3 Up Mode Flag Setting Set TBIFG Set TBCCRO CCIFG Changing the Period Register TBCLO When changing TBCLO while the timer is running and when the TBCLO load mode is immediate if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero 13 6 Timer_B Timer B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR max and restarts from zero as shown in Figure 13 4 The compare latch TBCLO works the same way as the other capture compare registers Figure 13 4 Continuous Mode TBR max Oh The TBIFG interrupt flag
90. divider The capacitor voltage Vc must be charged to within LSB of the resistor divider voltage for an accurate 10 bit conversion See the device specific datasheet for parameters Figure 22 4 Analog Input Equivalent Circuit MSP430 VI Input voltage at pin SIFCHx R Ri Vs External source voltage S VI SIFCHx Rs External source resistance VS Ri SIFCHx Internal MUX on input resistance CISHC SIFCHXx Input capacitance CSHC SIFCHx VC Capacitance charging voltage The resistance of the source Rg and RigiFCHx affect tsampje The following equation can be used to calculate the minimum sampling time tgample for a 10 bit conversion 11 sample gt Ps RigiecHy X 2 D Substituting the values for and C given above the equation becomes t Rg 3k x 7 625 x 7pF 2 sample For example if Rg is 10 tgample must be greater than 684 ns 22 8 Scan IF Scan IF Operation Direct Analog And Digital Inputs By setting the SIFCAX bit external analog or digital signals can be connected directly to the comparator through the SIFCIx inputs This allows measurement capabilities for optical encoders and other sensors Comparator Input Selection And Output Bit Selection The SIFCAX and SIFSH bits select between the SIFCIx channels and the SIFCHx channels for the comparator input as described in Table 22 1 Table 22 1 SIFCAX and SIFSH Input Selection SIFCA
91. flash returns to read mode and all bits in the FCTL1 register are reset The result of the intended operation is unpredictable 5 3 6 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16 bit password protected read write registers Any read or write access must use word instructions and write accesses must include the write password OA5h in the upper byte Any write to any FCTLx register with any value other than OA5h in the upper byte is a security key violation sets the KEYV flag and triggers a PUC system reset Any read of any FCTLx registers reads 096h in the upper byte Any write to FCTL1 during an erase or byte word write operation is an access violation and sets ACCVIFG Writing to FCTL1 is allowed in block write mode when WAIT 1 but writing to FCTL1 in block write mode when WAIT 0 is an access violation and sets ACCVIFG Any write to FCTL2 when the BUSY 1 is an access violation Any FCTLx register may be read when BUSY 1 A read will not cause an access violation 5 3 7 Flash Memory Controller Interrupts The flash controller has two interrupt sources KEYV and ACCVIFG ACCVIFG is set when an access violation occurs When the ACCVIE bit is re enabled after a flash write or erase a set ACCVIFG flag will generate an interrupt request ACCVIFG sources the NMI interrupt vector so it is not necessary for GIE to be set for ACCVIFG to request an interrupt ACCVIFG may also be checked by software to deter
92. gt dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 3 32 RISC 16 Bit CPU CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear zero bit CLRZ 0924 or NOT src AND dst dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ RISC 16 Bit CPU 3 33 Instruction Set CMPI W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compare source and destination CMP src dst or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destinatio
93. handle these conditions appropriately Hardware Multiplier Hardware Multiplier Operation 7 2 3 Software Examples Examples for all multiplier modes follow All 8 8 modes use the absolute address for the registers because the assembler will not allow B access to word registers when using the labels from the standard definitions file 16x16 Unsigned Multiply MOV 01234h amp MPY Load first operand MOV 05678 amp 0 2 Load second operand bs Process results 8x8 Unsigned Multiply Absolute addressing MOV B 012h amp 0130h Load first operand MOV B 034h amp 0138h Load 2nd operand E Process results 16x16 Signed Multiply MOV 01234h amp MPYS Load first operand MOV 05678h amp OP2 Load 2nd operand P es Process results 8x8 Signed Multiply Absolute addressing MOV B 012h amp 0132h Load first operand SXT amp MPYS Sign extend first operand MOV B 034h amp 0138h Load 2nd operand SXT amp OP2 Sign extend 2nd operand triggers 2nd multiplication A Process results 16x16 Unsigned Multiply Accumulate MOV 01234h amp MAC Load first operand MOV 05678h amp OP2 Load 2nd operand bed Process results 8x8 Unsigned Multiply Accumulate Absolute addressing MOV B 012h amp 0134h Load first operand MOV B 034h amp 0138h Load 2nd operand Process results 16x16 Signed Multiply Accumulate MOV 01234h amp MACS Load first operand MOV 0567
94. handling overhead The TAIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block TACCRO 11 cycles Capture compare blocks TACCR1 TACCR2 16 cycles Lj Timer overflow TAIFG 14 cycles Interrupt handler for TACCRO CCIFG Cycles CCIFG 0 HND Start of handler Interrupt latency 6 RETI Interrupt handler for TAIFG TACCR1 and TACCR2 CCIFG TA HND Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 TACCR1 2 JMP CCIFG 2 HND Vector 4 TACCR2 2 RETI Vector 6 Reserved 5 RETI Vector 8 Reserved 5 TAIFG HND Vector 10 TAIFG Flag Task starts here RETI 5 CCIFG 2 HND Vector 4 TACCR2 Task starts here RETI Back to main program 5 CCIFG 1 HND Vector 2 TACCR1 s Task starts here RETI Back to main program 5 12 18 Timer A 12 3 Timer A Registers Timer A Registers The Timer A registers are listed in Table 12 3 and Table 12 4 Table 12 3 Timer Registers Register Timer A control TimerO A3 Control Timer A counter TimerO A3 counter Timer A capture compare control 0 TimerO A3 capture compare control 0 Timer A captu
95. i Set TBCCRx CCIFG Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 13 11 COV must be reset with software Timer B 13 11 Timer B Operation Figure 13 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Taken 1 Idle Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets bit CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TBCCTLx Setup TBCCTLx XOR CCISO amp TBCCTLx TBCCTLx TBR Compare Mode The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time intervals When TBR counts to the value in a TBCLx Interrupt flag CCIFG is set Internal signal EQUx 1 Li EQUXx affects the output according to the output mode 13 12 Timer B Timer B Operation Compare Latch TBCLx The TBCCRx compare latch TBCLx holds the data for the comparison to the timer value in compare mode
96. is connected to SIFVss and the SIFCOM input is connected to the mid voltage generator to excite the sensor The SIFLCEN tsm signal must be low for excitation While one channel is excited and measured all other channels are automatically disabled Only the selected channel is excited and measured The excitation period should be long enough to overload the LC sensor slightly After excitation the SIFCHx input is released from ground when SIFEX tsm 0 and the LC sensor can oscillate freely The oscillations will swing above the positive supply but will be clipped by the protection diode to the positive supply voltage plus one diode drop This gives consistent maximum oscillation amplitude At the end of the measurement the sensor should be shorted by setting SIFLCEN tsm 0 to remove any residual energy before the next measurement Mid Voltage Generator 22 6 Scan IF The mid voltage generator is on when SIFVCC2 1 and allows the LC sensors to oscillate freely The mid voltage generator requires a maximum of 6 ms to settle and requires ACLK to be active and operating at 32768 Hz Scan IF Operation Figure 22 3 Excitation and Sample And Hold Circuitry to SIFCHO L gt 18 Comparator SIFVSS W 1 0 SIFCOM e SIFEX tsm Tt l5 l Sample and Hold Q e e Damping 11 00 b pe SIFLCEN tsm gt 01 SIFTEN m 90 From Spr 1 0 Channel xcitatio
97. is set the UTXIFG1 flag will not trigger a transfer A transfer is triggered when the hardware multiplier is ready for a new operand No transfer is triggered No transfer is triggered A transfer is triggered when the DMAxIFG flag is set DMAOIFG triggers channel 1 DMA1IFG triggers channel 2 and DMA2IFG triggers channel 0 None of the DMAxIFG flags are automatically reset when the transfer starts A transfer is triggered by the external trigger DMAEO 8 13 8 2 1 Stopping Transfers There are two ways to stop DMA transfers in progress A single block or burst block transfer may be stopped with an NMI interrupt if the ENNMI bit is set in register DMACTL1 A burst block transfer may be stopped by clearing the DMAEN bit 8 2 5 DMA Channel Priorities 8 14 The default DMA channel priorities are DMA0 DMA1 DMAQ2 If two or three triggers happen simultaneously or are pending the channel with the highest priority completes its transfer single block or burst block transfer first then the second priority channel then the third priority channel Transfers in progress are not halted if a higher priority channel is triggered The higher priority channel waits until the transfer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bit is set the channel that completes a transfer becomes the lowest priority The order of the priority of the c
98. is set when the timer counts from TBR max to zero Figure 13 5 shows the flag set cycle Figure 13 5 Continuous Mode Flag Setting Timer Set TBIFG Timer B 13 7 Timer B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TBCLx latch in the interrupt service routine Figure 13 6 shows two separate time intervals tg and ty being added to the capture compare registers The time interval is controlled by hardware not software without impact from interrupt latency Up to three Timer or 7 Timer B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 13 6 Continuous Mode Time Intervals 13 8 TBR max TBCLOa Oh EQUO Interrupt EQUI Interrupt Timer_B TBCL1b TBCLic TBCLOb TBCLOc TROLON TBCLia TBCLid t t t Time intervals can be produced with other modes as well where TBCLO is used as the period register Their handling is more complex since the sum of the old TBCLx data and the new period can be higher than the TBCLO value When the sum of the previous TBCLx value plus t is greater than the TBCLO data the old TBCLO value must be subtracted to obtain the correct time interval Up Down Mode Timer B Operation The up down mode is us
99. is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Subtract LSDs SBC B 1 R12 Subtract carry from MSD Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 3 62 RISC 16 Bit CPU SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Set carry bit SETC 1 BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R R5 1 R6 2 0150h RISC 16 Bit CPU 3 63 Instruction Set SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 N BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected 3 64 RISC 16 Bit CPU Instruction Set
100. loaded when grouped First all TBCCRx registers of the group must be updated even when new TBCCRx data old TBCCRx data Second the load event must occur Table 13 3 Compare Latch Operating Modes TBCLGRPx Grouping Update Control 00 None Individual 01 TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCCR3 TBCL5 TBCL6 TBCCR5 10 TBCL1 TBCL2 TBCL3 TBCCR1 TBCL4 TBCL5 TBCL6 TBCCR4 11 TBCLO TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCL5 TBCL6 Timer_B 13 13 Timer B Operation 13 2 5 Output Unit Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals The TBOUTH pin function can be used to put all Timer B outputs into a high impedance state When the TBOUTH pin function is selected for the pin and when the pin is pulled high all Timer B outputs are in a high impedance state Output Modes The output modes are defined by the OUTMODx bits and are described in Table 13 4 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 13 4 Output Modes OUTMODx Mode Description 000 Output The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated 001 Set The output is set when the timer counts to the TBCLx val
101. may be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the ADC120V and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register the ADC120vV interrupt condition is reset automatically After the RETI instruction ofthe interrupt service routine is executed the ADC12IFG3 generates another interrupt ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead The ADC12IV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are LJ ADC12IFGO ADC121FG14 ADC12TOV and ADC12OV 16 cycles J ADC12IFG15 14 cycles The interrupt handler for ADC121FG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC121FG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT ADC12 Enter Interrupt Service Routine 6 ADD amp ADC121V PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2 JMP ADMO V
102. operates normally when STE is high When STE is low SIMO and UCLK are set to inputs and no longer drive the bus The error bit FE is set indicating a communication integrity violation to be handled by the user A low STE signal does not reset the USART module The STE input signal is not used in 3 pin master mode USART Peripheral Interface SPI Mode 15 5 USART Operation SPI Mode 15 2 3 Slave Mode Figure 15 3 USART Slave and External Master MASTER MSB COMMON SPI SPI Receive Buffer SPI Receive Bufer Receive Buffer UXRXBUF Receive Shift Register LSB MSB MSP430 USART Figure 15 3 shows the USART as a slave in both 3 pin and 4 pin configurations UCLK is used as the input for the SPI clock and must be supplied by the external master The data transfer rate is determined by this clock and not by the internal baud rate generator Data written to UXTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received When data is moved from the RX shift register to UXRXBUF the URXIFGx interrupt flag is set indicating that data has been received The overrun error bit OE is set when the previously received data is not read from UxRXBUF before new data is moved to UxRXBUF Four Pin SPI Slave Mode In 4 pin slave mode STE
103. or internal signals from one of the DAC12 modules One of the non inverting inputs is tied together internally for all OA modules The input signal swing is software selectable with the OARRIP bit When OARRIP 0 rail to rail input mode is selected and the OA uses higher quiescent current See the device datasheet for parameters The OA has configurable output selection The OA output signals can be routed to ADC12 inputs A12 A13 OA1 or A14 OA2 with the OAADCO bit When OAADCO 1 the OA output is connected to the corresponding ADC input internally and the external ADC input is not connected The OA output signals can also be routed to ADC12 inputs A1 OA1 or A5 OA2 when OAFCx 0 or when OAADC1 1 In this case the OA output is connected to both the ADC12 input internally and the corresponding pin on the device The OA output is also connected to an internal R ladder with the OAFCx bits The R ladder tap is selected with the OAFBRXx bits to provide programmable gain amplifier functionality 16 2 4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 16 1 Table 16 1 OA Mode Select OAFCx OA Mode 000 General purpose opamp 001 Unity gain buffer 010 Reserved 011 Comparator 100 Non inverting PGA amplifier 101 Reserved 110 Inverting PGA amplifier 111 Differential amplifier General Purpose Opamp Mode Unity Gain
104. segments Figure 5 2 Flash Memory Segments 4 KB Example 4 KB 256 byte FFFFh F000h 10FFh 1000h Flash Memory 4 kbyte Flash Main Memory 256 byte Flash Information Memory SegmentA SegmentB Flash Memory Controller 5 3 Flash Memory Operation 5 3 Flash Memory Operation The default mode of the flash memory is read mode In read mode the flash memory is not being erased or written the flash timing generator and voltage generator are off and the memory operates identically to ROM MSP430 flash memory is in system programmable ISP without the need for additional external voltage The CPU can program its own flash memory The flash memory write erase modes are selected with the BLKWRT WRT MERAS and ERASE bits and are Byte word write Block write Segment Erase Mass Erase all main memory segments O L All Erase all segments Reading or writing to flash memory while it is being programmed or erased is prohibited If CPU execution is required during the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 5 3 4 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 5 3 The flash timing generator operating frequency must be in the range from 257 kHz to 476 kHz see device specific datasheet Figure 5 3 Flash Memory Timing Ge
105. src dst DADC B dst dst C dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs RISC 16 Bit CPU 3 35 Instruction Set DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD src dst or DADD W src dst DADD B src dst src dst C dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the d
106. the next rising edge of ACLK SIFCNTS counts the clock cycles of the internal oscillator SIFCNTS counts the internal oscillator cycles for one ACLK period when SIFNOM 0 and four ACLK periods when SIFNOM 1 Reading SIFONTS while it is counting will result in reading 01h TSM Stop Condition The last state the TSM is marked with SIFSTOP 1 The duration of this last state is always one SIFCLK cycle regardless of the SIFACLK or SIFREPEATx settings The SIFIFG1 interrupt flag is set at when the TSM encounters a state with a set SIFSTOP bit Scan IF 22 17 Scan IF Operation TSM Test Cycles For calibration purposes to detect sensor drift or to measure signals other than the sensor signals a test cycle may be inserted between TSM cycles by setting the SIFTESTD bit The time between the TSM cycles is not altered by the test cycle insertion as shown in Figure 22 9 At the end of the test cycle the SIFTESTD bitis automatically cleared The TESTDX signalis active during the test cycle to control input and output channel selection TESTDX is generated after the SIFTESTD bit is set and the next TSM sequence completes Figure 22 9 Test Cycle Insertion TSM Active TSM Start Signal Divided ACLK Normal Test Normal Test Normal Cycle Normal Cycle Cycle Cycle Cycle Cycle TESTDX SIFTESTD SIFTESTD set by Software SIFTESTD automatically cleared 22 18 Scan IF Scan IF Opera
107. the division factor given by UxBR The timing for the start bit is determined by UxBR plus the next bit is determined by UxBR plus m1 and so on The modulation sequence begins with the LSB When the character is greater than 8 bits the modulation sequence restarts with and continues until all bits are processed Determining the Modulation Value 14 12 Determining the modulation value is an interactive process Using the timing error formula provided beginning with the start bit the individual bit errors are calculated with the corresponding modulator bit set and cleared The modulation bit setting with the lower error is selected and the next bit error is calculated This process is continued until all bit errors are minimized When acharacter contains more than 8 bits the modulation bits repeat For example the 9th bit of a character uses modulation bit 0 USART Peripheral Interface UART Mode USART Operation UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings By modulating each bit the cumulative bit error is reduced The individual bit error can be calculated by Error 96 nen x u 1 x UxBR Zm j x 100 With baud rate Desired baud rate BRCLK Input frequency UCLKI ACLK or SMCLK J Bit position 0 for the start bit 1 for data bit DO and so on UxBR Division factor in registers UXBR1 and UxBRO For example the transmit errors for
108. the following conditions are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 65 UxMCTL 6Bh m7 0 m6 1 m5 1 m4 0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error x 0 1 x UxBR 11 100 2 54 Data bit DO Error gre x 1 1 x UxBR 2 2 x 100 5 08 baud rate x 5 4 x UxBR 2 3 x 100 0 29 Data bit D1 Error BRCLK baud rate _ T BRGLK X 3 1 x UxBR 3 4 100 2 83 Data bit D3 Error 9 4 1 x UxBR 3 5 BRCLK Data bit D2 Error 100 1 95 baud rate BRGlK 1 x UxBR 4 6 baud rate BRCLK 6 1 x UxBR 5 7 baud rate E oy o BRCLK x 7 1 x UxBR 5 8 x 100 1 66 Data bit D4 Error x 100 0 59 Data bit D5 Error x 100 3 1396 Data bit D6 Error Data bit D7 Error aud rate y g 1 x UxBR 6 9 x 100 0 88 BRCLK x 100 3 42 BRCLK Stop bit 1 Error audale x 10 1 x UxBR 7 11 x 100 1 37 Parity bit Error E gt 9 1 UxBR 7 10 The results show the maximum per bit error to be 5 08 of a BITCLK period USART Peripheral Interface UART Mode 14 13 USART Operation UART Mode Receive Bit Timing Receive timing consists of two error sources The first is the bit to
109. to by R5 X e g table with address starting at X X can be an address or a label SP 2 5 SP PC 2 5 SP X R5 2 PC Indirect indirect R5 X RISC 16 Bit CPU 3 29 Instruction Set CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst CLR W dst CLR B dst 0 dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 TONI Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 TONI 3 30 RISC 16 Bit CPU CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear carry bit CLRC 0 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter RISC 16 Bit CPU 3 31 Instruction Set CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLRN 0 gt N or NOT src AND dst
110. to the destination Comment Valid only for a source operand Example MOV 45h TONI Before After Address Register Address Register Space Space OFF18h Oxxxxh PC OFF16h 01192h OFF16h 01192h OFF14h 00045h OFF14h 00045h OFF12h 040B0h PC OFF12h 040BOh OFF16h 010AAh 01192h 010AAh 010A8h 01234h O10A8h pioAgn 00045h 3 16 RISC 16 Bit CPU Instruction Set 3 4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions The core instructions are instructions that have unique op codes decoded by the CPU The emulated instructions are instructions that make code easier to write and read but do not have op codes themselves instead they are replaced automatically by the assembler with an equivalent core instruction There is no code or performance penalty for using emulated instruction There are three core instruction formats Dual operand Single operand Jump All single operand and dual operand instructions can be byte or word instructions by using B or W extensions Byte instructions are used to access byte data or byte peripherals Word instructions are used to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand de
111. user must assure the DAC12 settling time is not violated when using the DMA controller See the device specific data sheet for parameters _ DAC12 Operation 21 2 7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt The DAC12IFG bit is set when DAC12LSELx gt 0 and DAC12 data is latched from the DAC12 xDAT register into the data latch When DAC12LSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DAC12IE and GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset automatically It must be reset by software DAC12 21 9 DAC12 Registers 21 3 12 Registers The DAC12 registers are listed in Table 21 2 Table 21 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12 0 control DAC12 OCTL Read write 01COh Reset with POR DAC12_0 data DAC12 ODAT Read write 01C8h Reset with POR DAC12_1 control DAC12 1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR 21 10 DAC12 DAC12 Registers DAC12 xCTL DAC12 Control Register 15 DAC120PS rw 0 7 14 13 12 11 10 9 8 DAC12 DAC12SREFx DAC12RES DAC12LSELx CALON DAC12IR rw 0 6 4 3 2 1 0 DAC12 0 0 0 0 0
112. 0 UART is transmitting data and or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST 1 USART Peripheral Interface UART Mode 14 23 USART Registers UART Mode UxRCTL USART Receive Control Register rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag When PENA 0 PE is read as 0 0 No error 1 Character received with parity error OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read 0 No error 1 Overrun error occurred BRK Bit 4 Break detect flag 0 No break condition 1 Break condition occurred URXEIE Bit 3 Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx URXWIE Bit 2 Receive wake up interrupt enable This bit enables URXIFGx to be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx RXWAKE Bit 1 Receive wake up flag 0 Received character is data 1 Received character is an address RXERR Bit 0 Receive error flag This bit indicates a character was received with error s When RXERR 1 on or more error flags FE PE OE BRK is also set RXERR is cleared wh
113. 0176h 012Eh Address 0180h 0190h 0182h 0192h 0184h 0194h 0186h 0196h 0188h 0198h 018Ah 019Ah 011Eh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A 12 19 Timer A Registers TACTL Timer A Control Register 15 14 13 12 11 10 9 8 mm rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bits Unused 15 10 TASSELx Bits Timer A clock source select 9 8 00 TACLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 Bits Mode control Setting 00h when Timer A is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCRO 10 Continuous mode the timer counts up to OFFFFh 11 Up down mode the timer counts up to TACCRO then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer A clear Setting this bit resets TAR the TACLK divider and the count direction The TACLR bit is automatically reset and is always read as zero TAIE Bit 1 Timer A interr
114. 020h R9 Prepare counter MOV B QR10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Counter z 0 continue copying Copying completed 3 52 RISC 16 Bit CPU Syntax Operation Emulation Description Status Bits Instruction Set No operation NOP None MOV 0 R3 No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes L To fill one two or three memory words To adjust software timing Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 42 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to prevent unintended results For example if MOV 0 R4 0 R4 is used and the value in R4 is 120h then a security violation will occur with the watchdog timer address 120h because the security key was not used 1 RISC 16 Bit CPU 3 53 Instruction Set POP W Syntax Operation Em
115. 03h is written to it these bits show value of the currently selected DAC register Scan IF Registers SIFCNT Scan IF Counter Register SIFCNT2x Bits SIFCNT2 These bits are the SIFCNT2 counter SIFCNT2 is reset when 15 8 SIFEN 0 or if read when SIFCNTRST 1 SIFCNT1x Bits SIFCNT1 These bits are the SIFCNT1 counter SIFCNT1 is reset when 7 0 SIFEN 0 or if read when SIFCNTRST 1 SIFPSMV Scan IF Processing State Machine Vector Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SIFPSMVx Bits SIF PSM vector These bits are the address for the first state in the PSM state 15 0 table Scan IF 22 39 Scan IF Registers SIFCTL1 Scan IF Control Register 1 rw 0 rw 0 SIFIEx SIFIFG6 SIFIFG5 SIFIFG4 SIFIFG3 SIFIFG2 SIFIFG1 SIFIFGO 22 40 Bits 15 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Scan IF rw 0 rw 0 rw 0 rw 0 w 0 m m m ED JE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt Enable These bits enable or disable the interrupt request for the SIFIFGx bits 0 Interrupt disabled 1 Interrupt enabled SIF interrupt flag 6 This bit is set when the PSM transitions to a state with a set Q7 bit SIFIFG6 must be reset with software 0 No interrupt pending 1 Interrupt pending SIF interrupt flag 5 This bit is set when the PSM transitions to
116. 04292h 0A123h OFO16h 0A123h 01234h 01114h 0A123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code RISC 16 Bit CPU 3 13 Addressing Modes 3 3 5 Indirect Register Mode The indirect register mode is described in Table 3 8 Table 3 8 Indirect Mode Description Assembler Code Content of ROM MOV GR10 0 R11 MOV R10 0 R11 Length One or two words Operation Move the contents of the source address contents of R10 to the destination address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B R10 0 R11 Before After Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h OFF14h OFF12h 0000h R10 OFA33h OFF16h 0000h R10 OFA33h O4AEBh PC 11 002A7h OFF14h O4AEBh R11 002A7h OFAS32h 05BC1h OFA32h 05BC1h 002A8h 002A8h 002A7h 002A7h 002A6h 002A6h 3 14 RISC 16 Bit CPU Indirect Autoincrement Mode Addressing Modes The indirect autoincrement mode is described in Table 3 9 Table 3 9 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Content of ROM MOV GR10 0 R11 Move the contents of the source address contents of R10 to the destination addres
117. 1 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx ADC12 19 13 ADC12 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDXx bits The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re starts the sequence Figure 19 9 shows the repeat sequence of channels mode Figure 19 9 Repeat Sequence of Channels Mode CONSEQx 11 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r and 125 Wait for Trigger ENC 0 and EOS x 1 SAMPCON SAMPCON 1 Sample Input Channel Defined in If EOS x 1 then x ADC12MCTLx CSTARTADDx else if x lt 15 then x x 1 else SAMPCON Y 0 If EOS x 1 then x 1 x ADC12CLK CSTARTADDx else if x lt 15 then x x 1 else MSC 20 0 0 and SHP 1 1 x ADC12CLK ENC 1 and Conversion 1 EOS x 0 or Result Stored Into ADC12MEMx EOS x 0 ADCA2IFG x is Set X pointer to ADC12MCTLx 19 14 ADC12 ADC12 Operation Using the Multiple Sample and Convert MSC Bit To configur
118. 1111 1000 0000 RISC 16 Bit CPU 3 69 Instruction Set TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive 2 Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS J R7 is positive but not zero R7NEG ia R7 is negative R7ZERO R7 is zero The low byte of R7 is tested If itis negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS i Low byte of R7 is positive but not zero R7NEG Low byte of R7 is negative R7ZERO Low byte of R7 is zero 3 70 RISC 16 Bit CPU XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Exclusive OR of source with destination Exclusive OR of source with des
119. 2 0 then execute following instruction The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP QR7 R6 R6 R7 compare on signed numbers JL EDE Yes R6 lt R7 xus No proceed RISC 16 Bit CPU 3 47 Instruction Set JMP Jump unconditionally Syntax JMP label Operation PC 2x offset gt Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter 3 48 RISC 16 Bit CPU JN Syntax Operation Description Status Bits Example L 1 Instruction Set Jump if negative JN label if N 1 PC 2x offset gt PC if N 0 execute following instruction The negative bit N of the status register is tested If itis set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status bits are not
120. 20 3 SD16 Operation 20 2 SD16 Operation 20 2 1 ADC Core 20 2 2 Digital Filter 20 4 SD16 The SD16 module is configured with user software The setup and operation of the SD16 is discussed in the following sections The analog to digital conversion is performed by a 1 bit second order sigma delta modulator A single bit comparator within the modulator quantizes the input signal with the modulator frequency fy The resulting 1 bit data stream is averaged by the digital filter for the conversion result The digital filter processes the 1 bit data stream from the modulator using a SINC comb filter The transfer function is described in the z Domain by OSR 3 i E E and in the frequency domain by 3 3 sine OSRa sin OSR Hif OSR Lj SINC T sin x f M M where the oversampling rate OSR is the ratio of the modulator frequency fry to the sample frequency fs Figure 20 2 shows the filter s frequency response for an OSR of 32 The first filter notch is at fg fu OSR The notch s frequency can be adjusted by changing the modulators frequency fy using SD16SSELx and SD16DIVx and the oversampling rate using SD16OSRx The digital filter for each enabled ADC channel completes the decimation of the digital bit stream and outputs new conversion results to the corresponding SD16MEM x register at the sample frequency fs SD16 Operation Figure 20 2
121. 4 bit processing 8 bit processing 0 word processing 1 2 bit processing 1 word processing No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC is replaced by ADD dst 0 R3 dst RISC 16 Bit CPU 3 7 CPU Registers 3 2 5 General Purpose Registers R4 R15 The twelve registers R4 R15 are general purpose registers All of these registers can be used as data registers address pointers or index values and can be accessed with byte or word instructions as shown in Figure 3 7 Figure 3 7 Register Byte Byte Register Operations Register Byte Operation Byte Register Operation High Byte Low Byte High Byte Low Byte Register Memory Example Register Byte Operation Example Byt
122. 6 Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro r 0 r 0 r 0 r 0 ro SD16IVx Bits SD16 interrupt vector value 15 0 SD16IV Interrupt Contents Interrupt Source Interrupt Flag Priority 000h No interrupt pending 002h SD16MEMXx overflow SD16CCTLx Highest SD160VIFGT 004h SD16_0 Interrupt SD16CCTLO SD16IFG 006h SD16 1 Interrupt SD16CCTL1 SD16IFG 008h SD16 2 Interrupt SD16CCTL1 SD16IFG 00Ah Reserved 00Ch Reserved OOEh Reserved 010h Reserved Lowest T When an SD16 overflow occurs the user must check all SD16CCTLx SD160OVIFG flags in order to determine which channel overflowed SD16 20 23 20 24 SD16 21 12 The DAC12 module is 12 bit voltage output digital to analog converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430FG43x devices Topic Page 2I IBDAGI2 Introductiong tert hate eer eer 21 2 21 2 C DAC12 Operation 3 5 EET ener a 21 4 21 3 DAC12 Registers 2 e I ERIT 21 10 DAC12 Introduction 21 1 DAC12 Introduction 21 2 DAC12 The DAC12 module is a 12 bit voltage output DAC The DAC12 can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller When multiple DAC12 modules are present they may be grouped together for synchronous update operation Features of the DAC12 include 12 bit monotonic output
123. 7 as a transition state BIS OUTMOD_7 amp TBCCTLx Set output mode 7 BIC OUTMODx amp TBCCTLx Clear unwanted bits Timer_B 13 17 Timer B Operation 13 2 6 Timer B Interrupts Two interrupt vectors are associated with the 16 bit Timer B module TBCCRO interrupt vector for TBCCRO CCIFG Lj TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TBCCRx register In compare mode any CCIFG flag is set when TBR countsto the associated TBCLx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set TBCCRO Interrupt Vector The TBCCRO CCIFG flag has the highest Timer B interrupt priority and has a dedicated interrupt vector as shown in Figure 13 15 The TBCCRO CCIFG flag is automatically reset when the TBCCRO interrupt request is serviced Figure 13 15 Capture Compare TBCCRO Interrupt Flag Capture EQUO IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TBIV Interrupt Vector Generator 13 18 Timer_B The TBIFG flag and TBCCRx CCIFG flags excluding TBCCRO CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority enabled interrupt excluding TBCCRO CCIFG generates
124. 8h amp OP2 Load 2nd operand Process results 8x8 Signed Multiply Accumulate Absolute addressing MOV B 012h amp 0136h Load first operand SXT amp MACS Sign extend first operand MOV B 034h R5 Temp location for 2nd operand SXT R5 Sign extend 2nd operand MOV R5 amp 0 2 Load 2nd operand d Process results Hardware Multiplier 7 5 Hardware Multiplier Operation 7 2 4 7 2 5 7 6 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers At least one instruction is needed between loading the second operand and accessing one of the result registers Access multiplier results with indirect addressing RESLO address in R5 for indirect MOV RESLO R5 MOV amp OPER1 amp MPY MOV amp OPER2 amp OP2 NOP MOV 5 amp MOV 5 amp Using Interrupts n Load Load Need Move Move lst operand 2nd operand one cycle RESLO RESHI If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines Disable interrupts DINT NOP MOV xxh amp OP2 EINT Hardware Multiplier xxh amp MPY
125. 8h Reset with POR DMA channel 1 source address DMA1SA Read write 01EAh Unchanged DMA channel 1 destination address DMA1DA Read write 01ECh Unchanged DMA channel 1 transfer size DMA1SZ Read write 01EEh Unchanged DMA channel 2 control DMA2CTL Read write 01FO0h Reset with POR DMA channel 2 source address DMA2SA Read write 01F2h Unchanged DMA channel 2 destination address DMA2DA Read write 01F4h Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F6h Unchanged 8 18 DMACTLO Control Register 0 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 DMA1TSELx DMAOTSELx rw 0 Reserved DMA2 TSELx DMA1 TSELx DMAO TSELx rw 0 Bits 15 12 Bits 11 8 Bits 7 4 Bits rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved DMA trigger select These bits select the DMA transfer trigger 0000 DMAREQ bit software trigger 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFGO UART SPI mode USARTO data received I2C mode 0100 UTXIFGO UART SPI mode USARTO transmit ready 12C mode 0101 DAC12 OCTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCRO CCIFG bit 1000 TBCCRO CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action 1101 No action 1110 DMAOIFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAEO Same as DMA2TSELx Same as DMA2TSELx DMACTL1 DMA Control Register 1
126. 9 2 8 ADC12 Grounding and Noise Considerations As with any high resolution ADC appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 19 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accuracy Figure 19 11 ADC12 Grounding and Noise Considerations Digital Power Supply 7x Decoupling 10uF 100nF Analog Power Supply 7N Decoupling Using an External Positive Reference 10 Using the Internal n Reference Generator 10 FF Vngr VeREF Using an External Negative Reference 10uF 100nF ADC12 19 17 ADC12 Operation 19 2 9 ADC12 Interrupts The ADC12 has 18 interrupt sources ADC12IFGO ADC12IFG15 LJ ADC12OV A
127. A controller can move data from the ADC12 conversion memory to RAM MSP430FG43x devices implement only DMA channel Therefore some features described in this chapter are not applicable to MSP430FG43x devices Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Selectable edge or level triggered transfer Four addressing modes LLL uu O O Q Single block or burst block transfer modes The DMA controller block diagram is shown in Figure 8 1 Figure 8 1 Controller Block Diagram DMAOTSELx DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data received USARTO transmit ready DAC12 OIFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA2IFG DMAEO DMA1TSELx DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data received USARTO transmit ready DAC12 OIFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger D
128. C is set and continue until the SD16SC bit is cleared by software when the channel is not grouped with any other channel Clearing SD16SC immediately stops conversion of the selected channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMXx be read prior to clearing SD16SC to avoid reading an invalid result Figure 20 6 shows single channel operation for single conversion mode and continuous conversion mode Figure 20 6 Single Channel Operation Channel 0 SD16SNGL 1 SD16GRP 0 SD16SNGL 1 SDI6GRP 0 1 H Channel 2 i SD16SNGL 0 Conversion 2 SD16SC 4 Set by SW uto clear Conversion Conversion Conversion amp Conv 1 SD16GRP 0 SD16SC 4 Set by SW Cleared by SW Y Q Result written to SD16MEMx Time 20 10 SD16 SD16 Operation Group of Channels Single Conversion Consecutive SD16 channels can be grouped together with the SD16GRP bit to synchronize conversions Setting SD16GRP for a channel groups that channel with the next channel in the module For example setting SD16GRP for channel 0 groups that channel with channel 1 In this case channel 1 is the master channel enabling and disabling conversion of all channels in the group with its SD16SC bit The SD16GRP bit of the master channel is always 0 The SD16GRP bit of last channel i
129. CRO CCIFG Cycles CCIFG 0 HND yax Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB_HND Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 Module 1 2 JMP CCIFG 2 HND Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 TBIFG HND Vector 14 TIMOV Flag s Task starts here RETI 5 CCIFG_2_HND Vector 4 Module 2 T Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending CCIFG 1 HND Vector 6 Module 3 Task starts here JMP TB HND Look for pending ints 2 Timer B 13 19 Timer B Registers 13 3 Timer B Registers The Timer B registers are listed in Table 13 5 Table 13 5 Timer B Registers Register Short Form Register Type Address Initial State Timer B control TBCTL Read write 0180h Reset with POR Timer B counter TBR Read write 0190h Reset with POR Timer B capture compare control 0 TBCCTLO Read write 0182h Reset with POR Timer B capture compare 0 TBCCRO Read write 0192h Reset with POR Timer B capture compare control 1 TBCCTL1 Read write 0184h Reset with POR Timer capture compare 1 TBCCR1 Read write 0194h Reset with POR Timer B capture compare control 2 TBCCTL2 Read write 0186h Reset w
130. Clock Module Introduction 4 2 The frequency locked loop FLL clock module supports low system cost and ultralow power consumption Using three internal clock signals the user can select the best balance of performance and low power consumption The FLL features digital frequency locked loop FLL hardware The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator DCO frequency to a programmable multiple of the LFXT1 watch crystal frequency The FLL clock module can be configured to operate without any external components with one or two external crystals or with resonators under full software control The clock module includes two or three clock sources LFXT1CLK Low frequency high frequency oscillator that can be used either with low frequency 32768 Hz watch crystals or standard crystals resonators or external clock sources in 450 kHz to 8 MHz range XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range 1 DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics stabilized by the FLL Four clock signals are available from the module Auxiliary clock The ACLK is the LFXT1CLK clock source ACLK is software selectable for individual peripheral modules ACLK n Buffered output of the ACLK The ACLK n is ACL
131. Comb Filter s Frequency Response with OSR 32 0 S001 ee Pe ee dfs we wa ae Ws was we We we we ee We we es m 60 d i 2 a 804 ae Ad Pie ate oe ee eee bee ee ee eee ee 100 120 140 fs Frequency fm Figure 20 3 shows the digital filter step response and conversion points For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available The SD16INTDLYx bits can provide sufficient filter settling time for a full scale change at the ADC input If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion An asynchronous step will require one additional conversion before valid data is available Figure 20 3 Digital Filter Step Response and Conversion Points VrsR Asynchronous Step Synchronous Step Conversion Conversion SD16 20 5 SD16 Operation 20 2 3 Analog Input Range and PGA The full scale input voltage range for each analog input pair is dependent on the gain setting of the programmable gain amplifier of each channel The maximum full scale range is Vesp where Vrgg is defined by Vrer 2 Vrsr IN For a 1 2V reference the maximum fu
132. Controller The 12C module provides two trigger sources for the DMA controller The 12C module can trigger a transfer when new 12C data is received and the when the transmit data is needed The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the 12C module When RXDMAEN 1 the DMA controller can be used to transfer data from the 12C module after the I2C modules receives data When RXDMAEN 1 RXRDYIE is ignored and RXRDYIFG will not generate an interrupt When TXDMAEN 1 the controller can be used to transfer data to the 12C module for transmission When TXDMAEN 1 TXRDYIE is ignored and TXRDYIFG will not generate an interrupt 8 2 10 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMXx register to another location DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput of the ADC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur DMA transfers can be triggered from any ADC121FGx flag When CONSEQx 0 2 the ADC12IFGx flag for the ADC12MEMXx used for the conversion can trigger a DMA transfer When CONSEQx 1 3 the ADC12IF Gx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the correspondin
133. Conversion 524 gt 25 13d 13 139 13 525 4 26 18h 13c 13b 13a S26 27 14d 14e 14g 14 S27 lt 4 28 14h 14c 14b 14 Sn 1 Sn 528 4 29 15 15 15g 15 529 4 30 15h 15c 15b 15a COM3 4 34 COM3 18 16 LCD Controller 4 Mode Software Example LCD Controller Operation The 4mux rate supports eight segments for each digit EQU EQU EQU EQU EQU EQU EQU EQU The LSDigit of register The Table represents the 080h 040h 020h 001h 002h 008h 004h 010h 2 content of Rx MOV B Table amp 1 DB b c b c d e g atdt et ft g 9 All eight segments of a digit can often be located one display memory byte Rx should be displayed on segments according to the quus 15 all eight segments are written to the display memory displays 0 displays 1 displays d displays E displays F LCD Controller 18 17 LCD Controller Operation 18 3 LCD Controller Registers The LCD Controller registers are listed in Table 18 1 Table 18 1 LCD Controller Registers Register LCD control register LCD memory 1 LCD memory 2 LCD memory 3 LCD memory 4 LCD memory 5 LCD memory 6 LCD memory 7 LCD memory 8 LCD memory 9 LCD memory 10 LCD memory 11 LCD memory 12 LCD memory 13 LCD memory 14 LCD memory 15 LCD memory 16 LCD memory 17 LCD memory 18 LCD memory 19 LCD memory 20 Short Form LCDCTL LCDM1 LCD
134. DADD B src dst src dst C dst decimally T j i BIT B src dst src and dst 0 P T T BIC B src dst notsrc and dst dst BIS B src dst src or dst gt dst XOR B src dst src xor dst dst n AND B src dst src dst gt dst 0 ii The status bit is affected status bit is not affected 0 The status bit is cleared The status bit is set p BB B _ Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions c 3 18 RISC 16 Bit CPU 3 4 2 Single Operand Format Il Instructions Instruction Set Figure 3 10 illustrates the single operand instruction format Figure 3 10 Single Operand Instruction Format Table 3 12 lists and describes the single operand instructions Table 3 12 Single Operand Instructions Mnemonic S Reg D Reg RRC B dst RRA B dst PUSH B Src SWPB dst CALL dst RETI SXT dst Operation C gt MSB LSB gt C MSB 5 MSB 5 LSB5 C SP 2 gt SP src gt SP Swap bytes SP 2 gt SP PC 2 5 SP dst gt PC TOS gt SR SP 2 gt SP TOS gt PC SP 2 gt SP Bit 7 gt Bit 8 Bit 15 The status bit is affected The status bit is not affected 0 The status bit is clea
135. DC12MEMXx overflow Ly ADC12TOV ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set The ADC120V condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read The ADC12TOV condition is generated when another sample and conversion is requested before the current conversion is completed ADC12IV Interrupt Vector Generator 19 18 ADC12 All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector The interrupt vector register ADC12IV is used to determine which enabled ADC 12 interrupt source requested an interrupt The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV condition if either was the highest pending interrupt Neither interrupt condition has an accessible interrupt flag The ADC12IFGx flags are not reset by an ADC12IV access ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMXx register or
136. FIFG is set MCLK is sourced from the DCO and if OFIE is set the OFIFG requests an NMI interrupt When the interrupt is granted the OFIE is reset automatically The OFIFG flag must be cleared by software The source of the fault can be identified by checking the individual fault bits If a fault is detected for the crystal oscillator sourcing the MCLK the MCLK is automatically switched to the DCO for its clock source This does not change the SELMx bit settings This condition must be handled by user software eS Sees Note DCO Active During Oscillator Fault DCOCLK is active even at the lowest DCO tap The clock signal is available for the CPU to execute code and service an NMI during an oscillator fault Figure 4 4 Oscillator Fault Logic 4 10 t Oscillator Fault i DCO Fault LF_OscFault XTS_FLL Set OFIFG Flag XT1_OscFault XT2_OscFault FLL Clock Module FLL Clock Module Registers 4 3 Clock Module Registers The FLL registers are listed in Table 4 2 Table 4 2 FLL Registers Register Short Form Register Type Address Initial State System clock control SCFQCTL Read write 052h 01Fh with System clock frequency integrator 0 SCFIO Read write 050h 040h with PUC System clock frequency integrator 1 SCFI1 Read write 051h Reset with PUC control register 0 FLL CTLO Read write 053h 003h with PUC FLL control register 1 FLL CTL1 Read writ
137. Figure 17 2 RC Filter Response at the Output of the Comparator Terminal Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 17 2 4 Voltage Reference Generator The voltage reference generator is used to generate which can be applied to either comparator input terminal The CAREFx bits control the output of the voltage generator The CARSEL bit selects the comparator terminal to which VcAggr is applied If external signals are applied to both comparator input terminals the internal reference generator should be turned off to reduce current consumption The voltage reference generator can generate a fraction of the device s Vcc or a fixed transistor threshold voltage of 0 55 V Comparator A 17 5 Comparator A Operation 17 2 5 Comparator A Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I O port pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The CAPDx bits when set disable the corresponding P1 input buffer as shown in Figure 17 3 When current consumption is critica
138. Format SD16DF Format Analog Input SD16MEMxt Digital Filter Output OSR 256 eee FSR FFFF FFFFFF Unipolar 0 Offset ZERO 8000 800000 Binary FSR 0000 000000 n FSR 7FFF 7FFFFF Bipolar 1 Two s ZERO 0000 000000 complement FSR 8000 800000 t Independent of SD16OSRx setting SD16LSBACC 0 Figure 20 4 shows the relationship between the full scale input voltage range from Vesp to VfFsp and the conversion result The digital values for both data formats are illustrated Figure 20 4 Input Voltage vs Digital Output Unipolar Output Bipolar Output SD16MEMx SD16MEMx FFFFh L 4 7FFFh L 22 2 Input Voltage Input Voltage RUMP IX DEI l VFSR VFSR SD16 20 7 SD16 Operation Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits Figure 20 5 shows the digital filter output bits and their relation to SD16MEMx for each SD16OSRx setting The SD16L SBACC and SD16LSBTOG bits give access to the least significant bits of the digital filter output When SD16LSBACC 1 the 16 least significant bits of the digital filters output are read from SD16MEMx using word instructions The SD16MEMx register can also be accessed with byte instructions B returning only the 8 least significant bits of the digital filter output When SD16LSBTOG 1 the SD16LSBACC bit is automatically toggled each t
139. I Set TACCRx CCIFG l Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 12 11 COV must be reset with software Timer_A 12 11 Timer A Operation Figure 12 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken 1 Idle Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets CCI 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TACCTLx Setup TACCTLx XOR CCISO amp TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to the value in a TACCRx Interrupt flag CCIFG is set Internal signal EQUx 1 Lj EQUXx affects the output according to the output mode The input signal CCI is latched into SCCI 12 12 Timer A 12 2 5 Output Unit Timer A Operation Each capture compare block contains
140. I Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI No of Cycles WWID ADD WWIDAD DAWA WFAN A ATW NIA a oO wo YI A A N Length of Instruction TIO WN NIWD OO OO TO OO OO N NIN N IO H HIN NM H HAIN N N H MOV BR ADD XOR MOV AND BR XOR MOV XOR BR XOR MOV MOV MOV MOV MOV AND BR CMP MOV MOV MOV BRA MOV MOV MOV Example R5 R8 R9 R5 3 R6 R8 EDE R5 amp EDE R4 R5 R8 R5 8 R6 R5 EDE R5 amp EDE R5 R6 R94 R5 8 R6 R9 EDE R9 amp EDE 20 R9 2AEh 0300h 0 SP 33 EDE 33 amp EDE 2 R5 R7 2 R6 4 R7 3 R4 TONI 6 R9 3 R4 amp TONI EDE R6 EDE EDE TONI EDE 0 SP EDE amp TONI amp EDE R8 amp EDE amp EDE TONI amp EDE 0 SP amp EDE amp TONI RISC 16 Bit CPU 3 73 Instruction Set 3 4 5 Instruction Set Description The instruction map is shown in Figure 3 20 and the complete instruction set is summarized in Table 3 17 Figure 3 20 Core Instruction Map 000 040 080 100 140 180 1CO 200 240 280 2C0 300 340 380 L qp qq og dm p py pp qq p 3 74 RISC 16 Bit CPU Table 3 17 MSP430 Instruction Set Mnemonic Apc m t Q QQQ QuUuUtutu tu D D D D LRC LRN LRZt MP B ADC B T ADD B pintt EIN
141. I Mode sssesee RR RR 15 2 USART Operation SPI Mode 15 2 1 USART Initialization and Reset 15 2 2 Master Mode 0 ccc een teen eee a 15 2 3 Slave ase rte decade x ats n n aa rd 15 2 4 5 Enable ade wacko adeo echec he deans atone Cice Y alla ce Contents 15 2 5 Serial Clock Control 15 2 6 SPI Interrupts 2 iid cerae sd eee dan E dA acid dd a 15 3 USART Registers SPI Mode 16 OA RP E 16 1 OA Introduction 0 0 s m 16 2 OA Operation hm e ERR RRteR E sented 16 2 1 OA Amplifier 11 coca ue a hebr Lee edie dw Ran 16 2 2 OR TInpUE eaten tans eod suu ese ul 16 23 OA QUIDULD ne ise oreet oka aden el tbc ko Sam i dua Rud ah RR do 16 2 4 OA Configurations 16 3 OA Registers soni Rx RE Rue ko REEF ERES C ERR 17 Comparator vene ru Ex ERR Rum sued paie di a 17 1 Comparator A Introduction 0 00 cect eens 17 2 Comparator A Operation serasa aiea ia mii ama ioa ae a doi e 17 2 1 Comparator 2 ed qute Dead A h 17 2 2 Input Analog 1 52 8 Output Fiter ertet haoc ice duse as end tira RA e UR
142. IFGx 1 indicating a character was received The URXIFGx flag is cleared when user software reads UxRXBUF Interrupt handler for start condition and Character receive BRCLK DCO UORX Int BIT B URXIFGO amp IFG2 Test URXIFGx to determine JNE ST COND If start or character MOV B amp UxRXBUF dst Read buffer RETI i ST COND BIC B URXSE amp UOTCTL Clear URXS signal BIS B URXSE amp U0TCTL Re enable edge detect BIC SCG0 SCG1 0 SP Enable BRCLK DCO RETI Note Break Detect With Halted UART Clock When using the receive start edge detect feature a break condition cannot be detected when the BRCLK source is off LLLLLLL USART Peripheral Interface UART Mode 14 19 USART Operation UART Mode Receive Start Edge Detect Conditions When URXSE 1 glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored by the USART and no interrupt request will be generated as shown in Figure 14 12 See the device specific datasheet for parameters Figure 14 12 Glitch Suppression USART Receive Not Started URXDx URXS When a glitch is longer than t or a valid start bit occurs on URXDx the USART receive operation is started and a majority vote is taken as shown in Figure 14 13 If the majori
143. K divided by 1 2 4 or 8 and only used externally MCLK Master clock MCLK is software selectable as LFXT1CLK XT2CLK if available or MCLK can be divided by 1 2 4 or 8 within the FLL block MCLK is used by the CPU and system SMCLK Submain clock SMCLK is software selectable as XT2CLK if available or DCOCLK SMCLK is software selectable for individual peripheral modules The block diagram of the FLL clock module is shown in Figure 4 1 for the MSP430x44x and MSP430x43x The block diagram of the clock module is shown in Figure 4 2 for the MSP430x42x and MSP430x41x FLL Clock Module Figure 4 1 MSP430x44x and MSP430x43x Frequency Locked Loop FLL_DIVx Divider 1 2 4 8 ACLK n f Crystal ACLK OSCOFF XTS_FLL XIN SCGO PUC Enable Reset XOUT SELMx LFXT1 Oscillator Frequency CPUOFF XCAPxPE Integrator ae MCLK off DC M Generator Modulator DCOCLK i DCOPLUS Divider 4 DCO 1 2 4 8 SELS lbi B SMCLKOFF i XT20FF XT2IN XT2OUT XT2 Oscillator FLL Clock Module 4 3 Figure 4 2 MSP430x42x and MSP430x41x Frequency Locked Loop FLL DIVx Divider 1 2 4 8 f Crystal gt OSCOFF XTS FLL XIN SCGO PUC T i LFOff Enable Reset XOUT XT1Off LFXT1 Oscillator foo OPUR
144. L 0 Z FWKEY FSSEL1 FNO amp FCTL2 FWKEY amp FCTL3 HFWKEY WRT amp FCTL1 0123h amp OFF1Eh FWKEY amp FCTL1 FWKEY LOCK amp FCTL3 514 kHz lt SMCLK lt 952 kHz Disable WDT SMCLK 2 Clear LOCK Enable write 0123h gt OFF1Eh Done Clear WRT Set LOCK Re enable WDT Flash Memory Controller 5 9 Flash Memory Operation Initiating a Byte Word Write from RAM The flow to initiate a byte word write from RAM is shown in Figure 5 9 Figure 5 9 Initiating a Byte Word Write from RAM Disable watchdog Set WRT 0 LOCK 1 re enable watchdog Byte word write from RAM 514 kHz lt SMCLK lt 952 kHz Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD amp WDTCTL Disable WDT L1 BIT BUSY amp FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 amp FCTL2 SMCLK 2 MOV HFWKEY amp FCTL3 Clear LOCK MOV HFWKEY WRT amp FCTL1 Enable write MOV 0123h amp OFF1Eh 0123h gt OFFLEh L2 BIT BUSY amp FCTL3 Test BUSY JNZ L2 Loop while busy MOV HFWKEY amp FCTL1 Clear WRT MOV FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT 5 10 Flash Memory Controller Block Write Flash Memory Operation The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed A block is 64 bytes starting at Oxx00h Oxx40h Oxx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or O
145. L triggers 0 Edge sensitive rising edge 1 Level sensitive high level DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA Bit 1 DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI ABORT 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA start DMAREQ is reset automatically 0 No DMA start 1 Start DMA DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSAx Bits DMA source address The source address register points to the DMA source 15 0 address for single transfers orthe first source address for block transfers The source address register remains unchanged during block and burst block transfers 8 22 DMAxDA Destination Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxDAx Bits DMA destination address The destination address register points to the 15 0 destination address for single transfers or the first address for block transfers The DMAxDA register remains unchanged during block and burst block transfers DMAxSZ DMA Size Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSZx Bits
146. LI _JILILIL_ Idle Periods of No Significance UTXDx URXDx Expanded UTXDx URXDx First Character Within Block AD Bit Is 0 for Is an Address AD Bit Is 1 Data Within Block Idle Time Is of No Significance For address transmission in address bit multiprocessor mode the address bit of acharacter can be controlled by writing to the TXWAKE bit The value of the TXWAKE bit is loaded into the address bit of the character transferred from UxTXBUF to the transmit shift register automatically clearing the TXWAKE bit TXWAKE must not be cleared by software It is cleared by USART hardware after it is transferred to WUT or by setting SWRST USART Peripheral Interface UART Mode 14 7 USART Operation UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored See the device specific datasheet for parameters When a low period on URXDx exceeds t a majority vote is taken for the start bit Ifthe majority vote fails to detect a valid start bit the USART halts character reception and waits for the next low period on URXDx The majority vote is also used for each bit in a character to prevent bit errors The USART module automatically detects framing errors parity errors overrun errors and break conditions when receiving characters The bits FE PE OE and BRK are set when their respective cond
147. M2 LCDM3 LCDM4 LCDM5 LCDM6 LCDM7 LCDM8 LCDM9 LCDM10 LCDM11 LCDM12 LCDM13 LCDM14 LCDM15 LCDM16 LCDM17 LCDM18 LCDM19 LCDM20 18 18 LCD Controller Register Type Address Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh O9Eh 09Fh OAOh OAth 0A2h OA3h OA4h Initial State Reset with PUC Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged LCD Controller Operation LCDCTL LCD Control Register i rw 0 LCDPx LCDMXx LCDSON Unused LCDON Bits 7 5 Bits Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 LCDPx LCDMXx LCDSON LCDON rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 LCD Port Select These bits select the pin function to be port I O or LCD function for groups of segments pins These bits ONLY affect pins with multiplexed functions Dedicated LCD pins are always LCD function 000 No multiplexed pins are LCD function 001 S0 815 are LCD function 010 50 519 are LCD function 011 50 523 are LCD function 100 50 527 are LCD function 101 50 531 are LCD function
148. MAOIFG DMAEO DMA2TSELx DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data received USARTO transmit ready DAC12 OIFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA1IFG DMAEO 4 4 4 puy VG cp DMADSTINCRx DMADTx DMADSTBYTE 3 ROUNDROBIN DMA Channel 0 DMAOSA DMAODA DMAOSZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 1 DMA1SA DMA1DA DMA1SZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 2 DMA2SA DMA2DA DMA2SZ DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH Ctt JTAG Active NMI Interrupt Request ENNMI Address Space jm Halt CPU 8 8 2 Operation 8 2 1 The DMA controller is configured with user software The setup and operation of the DMA is discussed in the following sections DMA Addressing Modes The DMA controller has four addressing modes The addressing mode for each DMA channel is independently configurable For example channel 0 may transfer between two fixed addresses while channel 1 transfers between two blocks of addresses The addressing modes are shownin Figure 8 2 The addressing modes are Fixed address to fixed address Fixed address to block of addresses Block of addresses to fixed address Block of addresses to block of addresses The
149. Mx MSB LSB SD16LSBACC x 15 14 13 12111 10 9 8 7 6 5 4 8 2 1 0 20 8 5016 SD16 Operation 20 2 6 Channel Selection Analog Input Setup Each SD16 channel can convert up to 8 differential pair inputs multiplexed into the PGA Up to six input pairs A0 A5 are available externally on the device See the device specific data sheet for analog input pin information An internal temperature sensor is available to each channel using the A6 multiplexer input Input A7 is a shorted connection between the and input pair and can be used to calibrate the offset of each SD16 input stage The analog input of each channel is configured using the SD16INCTLx register These settings can be independently configured for each SD16 channel The SD16INCHx bits select one of eight differential input pairs of the analog multiplexer The gain for each PGA is selected by the SD16GAINx bits A total of eight gain settings are available During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the next decimation step of the digital filter After these bits are modified the next three conversions may be invalid due to the settling time of the digital filter This can be handled automatically with the SD16INTDLYx bits When SD16INTDLY 00h conversion interrupt requests will not begin until the 4 conversion after a start condition 20 2 7 Conversion Modes The SD16 module can be configured fo
150. O 10 Continuous The timer repeatedly counts from zero to OFFFFh 11 Up down The timer repeatedly counts from zero up to the value of TACCRO and back down to zero Timer A 12 5 Timer A Operation Up Mode The up mode is used if the timer period must be different from OFFFFh counts The timer repeatedly counts up to the value of compare register TACCRO which defines the period as shown in Figure 12 2 The number of timer counts in the period is TACCRO 1 When the timer value equals TACCRO the timer restarts counting from zero If up mode is selected when the timer value is greater than TACCRO the timer immediately restarts counting from zero Figure 12 2 Up Mode OFFFFh TACCRO Oh The TACCRO CCIFG interrupt flag is set when the timer counts to the TACCRO value The TAIFG interrupt flag is set when the timer counts from TACCRO to zero Figure 12 3 shows the flag set cycle Figure 12 3 Up Mode Flag Setting Timer Clock Timer Set TAIFG Set TACCRO CCIFG l l Changing the Period Register TACCRO 12 6 Timer A When changing TACCRO while the timer is running if the new period is greater thanor equalto the old period or greaterthan the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero Timer A Operation Continuous Mode I
151. OFG43x devices Topic Page OA Introd ction ccc coro m ETE N 16 2 16 22 04 Operations 2 16 4 T16 3zOAJBegisters eise 16 11 16 1 OA Introduction 16 1 OA Introduction 16 2 OA The OA op amps support front end analog signal conditioning prior to analog to digital conversion Features of the OA include Single supply low current operation Rail to rail output Software selectable Rail to Rail input Programmable settling time vs power consumption Software selectable configurations E LE LLL Software selectable feedback resistor ladder for PGA implementations Note Multiple OA Modules Some devices may integrate more than one OA module In the case where more than one is present on a device the multiple OA modules operate identically Throughout this chapter nomenclature appears such as OAxCTLO to describe register names When this occurs the x is used to indicate which OA module is being discussed In cases where operation is identical the register is simply referred to as OAxCTLO The block diagram of the OA module is shown in Figure 16 1 OA Introduction Figure 16 1 OA Block Diagram DADA OAADCO OAFOx 6 gt OANx 3 A12 ext A13 ext OA1 12 int A14 ext OA2 A13 int OA1 OAPx 14 int OA2 OAADC1 OAxIO OAFCx 0 OAQ 1 Int DAC12 0OUT A1 int ext
152. OS bit is set and a sequence mode is selected resetting the ENC bit does not stop the sequence To stop the sequence first select a single channel mode and then reset ENC LLLLLLSSS O OMMI 14 ADC12 19 15 ADC12 Operation 19 2 7 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 19 10 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific datasheet for parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source forthe temperature sensor However it does not enable the output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 19 10 Typical Temperature Sensor Transfer Function 19 16 ADC12 Volts 1 300 1 200 1 100 1 000 0 900 VTEMP 0 00355 TEMPc 0 986 0 800 0 700 Celsius ADC12 Operation 1
153. Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 mue ES Byte 0 Setif result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Set if initial destination is positive and initial carry is set otherwise reset SON OSCOFF CPUOFF and GIE are not affected 5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h R5 low byte of R5 is used RISC 16 Bit CPU 3 61 Instruction Set SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst Or SBC W dst SBC B dst dst OFFFFh C dst dst OFFh C dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13
154. P XCAPxPF 9 MCLK to CPU off DC M e Generator Modulator MCLK to Peripherals DCOCLK DCOPLUS Divider DCO 1 2 4 8 4 bco D e SMCLK 4 4 FLL Clock Module FLL Clock Module Operation 4 2 Clock Module Operation After a PUC MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency When a 32 768 Hz crystal is used for ACLK MCLK and SMCLK will stabilize to 1 048576 MHz Status register control bits SCGO SCG1 OSCOFF and CPUOFF configure the MSP430 operating modes and enable or disable components of the clock module See Chapter System Resets Interrupts and Operating Modes The SCFQCTL SCFIO SCFI1 FLL_CTLO andFLL registers configure the FLL clock module The FLL can be configured or reconfigured by software at any time during program execution Example MCLK 64 x ACLK 2097152 BIC GIE SR Disable interrupts MOV B 64 1 amp SCFQTL MCLK 64 ACLK DCOPLUS 0 MOV B FN_2 amp SCFIO Select DCO range BIS GIE SR Enable interrupts 4 21 Clock features for Low Power Applications Conflicting requirements typically exist in battery powered MSP430x4xx applications Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability Clock stability over operating temperature and supply voltage The FLL clock module addresses the above conflicting requirements by
155. PC RO points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 15 1__0 Program Counter Bits 15 to 1 ES The PC can be addressed with all instructions and addressing modes A few examples MOV LABEL PC Branch to address LABEL MOV LABEL PC Branch to address contained in LABEL MOV R14 PC Branch indirect to address in R14 3 4 RISC 16 Bit CPU CPU Registers 3 2 2 Stack Pointer SP The stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts It uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 3 3 shows the SP The SP is initialized into RAM by the user and is aligned to even addresses Figure 3 4 shows stack usage Figure 3 3 Stack Pointer 15 S Stack Pointer Bits 15 to 1 EX MOV 2 SP R6 Item I2 R6 MOV R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h onto TOS POP R8 R8 0123h Figure 3 4 Stack Usage Address PUSH 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 Oxxxh 6 Oxxxh 8 SP The special cases of using the SP as an argument to the PUSH and POP ins
156. PUOFF and GIE are not affected R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address must not be within the range EDE to EDE 0FEh L 1 MOV EDE R6 MOV 255 R10 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 3 12 Figure 3 12 Decrement Overlap EDE t TONI EDE 254 TONI 254 RISC 16 Bit CPU 3 37 Instruction Set DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost Set if result is negative reset if positive Set if dst contained 2 reset otherwise Reset if dst contained 0 or 1 set otherwise Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location Start
157. S38 Segment Output 20x Control 8 bits Display Memory 51 50 LCDP2 COM3 LCDP1 g Common COM2 LCDPO utpu Control COM1 LCDMX1 g 4 COMO LCDMXO g 4 LCDSON m VANB VCVD Baa 2222222222222 LCDON Timing Generator gt Analog Voltage Multiplexer Lop from Basic Timer OSCOFF from SR Static 2 4Mux External Resistors Rx Optional Contrast Control LCD Controller 18 3 LCD Controller Operation 18 2 LCD Controller Operation The LCD controller is configured with user software The setup and operation of LCD controller is discussed in the following sections 18 2 1 LCD Memory The LCD memory map is shown in Figure 18 2 Each memory bit corresponds to one LCD segment or is not used depending on the mode To turn on an LCD segment its corresponding memory bit is set Figure 18 2 LCD memory Associated 3 2 1101 32 11 0 Common Pins Associated Address 7 m Segment Pins OA4h 38 39 38 OA3h 36 37 36 0A2h 34 35 34 OA1h 32 33 32 OAOh 30 31 30 O9Fh 28 29 28 O9Eh 26 27 26 09Dh 24 25 24 09Ch 22 23 22 09Bh 20 21 20 09Ah 18 19 18 099h 16 17 16 098h 14 15 14 097h 12 13 12 096h 10 11 10 095h 8 9 8 094h 6 7 6 093h 4 5 4 092h 2 3 2 091h 0 1 0 18 2 2 Blinking the LCD The LCD controller supports blinking The LCDSON
158. SART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h with PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC EAA Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions USART Peripheral Interface UART Mode 14 21 USART Registers UART Mode UxCTL USART Control Register rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 PENA Bit 7 Parity enable 0 Parity disabled 1 Parity enabled Parity bit is generated UTXDx and expected URXDx In address bit multiprocessor mode the address bit is included in the parity calculation PEV Bit 6 Parity select PEV is not used when parity is d
159. SIFCI3 Sample and hold SIFVss select 0 The ground connection of the sample capacitor is connected to SIFVss regardless of the TSM control 1 The ground connection of the sample capacitor is controlled by the TSM Mid voltage generator 0 AVc c 2 generator is off 1 AVcc 2 generator is on if SIFSH 0 SIFSH SIFTEN SIFTCH1x SIFTCHOx SIFTCH1 OUT SIFTCHO OUT Bit 7 Bit 6 Bits 5 4 Bits 3 2 Bit 1 Bit 0 Scan IF Registers Sample and hold enable 0 Sample and hold is disabled 1 Sample and hold is enabled Excitation enable 0 Excitation circuitry is disabled 1 Excitation circuitry is enabled These bits select the comparator input for test channel 1 00 Comparator input is SIFCHO when SIFCAX 0 Comparator input is SIFCIO when SIFCAX 1 01 Comparator input is SIFCH1 when SIFCAX 0 Comparator input is SIFCI1 when SIFCAX 1 10 Comparator input is SIFCH2 when SIFCAX 0 Comparator input is SIFCI2 when SIFCAX 1 11 Comparator input is SIFCH3 when SIFCAX 0 Comparator input is SIFCI3 when SIFCAX 1 These bits select the comparator input for test channel 0 00 Comparator input is SIFCHO when SIFCAX 0 Comparator input is SIFCIO when SIFCAX 1 01 Comparator input is SIFCH1 when SIFCAX 0 Comparator input is SIFCI1 when SIFCAX 1 10 Comparator input is SIFCH2 when SIFCAX 0 Comparator input is SIFCI2 when SIFCAX 1 11 Comparator input is SIFCH3 when SIFCAX 0 Comparator input is SIFCI3 w
160. SP SR src TOS WDT Auxiliary Clock Analog to Digital Converter Brown Out Reset Bootstrap Loader Central Processing Unit Digital to Analog Converter Digitally Controlled Oscillator Destination Frequency Locked Loop General Interrupt Enable Integer portion of N 2 Input Output Interrupt Service Routine Least Significant Bit Least Significant Digit Low Power Mode Memory Address Bus Master Clock Memory Data Bus Most Significant Bit Most Significant Digit Non Maskable Interrupt Program Counter Power On Reset Power Up Clear Random Access Memory System Clock Generator Special Function Register Sub System Master Clock Stack Pointer Status Register Source Top of Stack Watchdog Timer See Basic Clock Module See System Resets Interrupts and Operating Modes See www ti com msp430 for application reports See RISC 16 Bit CPU See FLL Module See RISC 16 Bit CPU See FLL Module See System Resets Interrupts and Operating Modes See Digital I O See System Resets Interrupts and Operating Modes See FLL Module See System Resets Interrupts and Operating Modes See RISC 16 Bit CPU See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See FLL Module See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See Watchdog Timer Register Bit Conventions Register Bit Conventions Each regist
161. SZ Modify T SourceAdd Modify T DestAdd DMAxSZ gt 0 AND a multiple of 4 words bytes were transferred DMAxSZ 0 2x MCLK Burst State DMADTx 6 7 AND DMAxSZ 0 7 release CPU for 2XMCLK 8 11 8 2 3 Initiating Transfers Each DMA channel is independently configured for its trigger source with the DMAXxTSELx bits as described in Table 8 2 The DMAXTSELx bits should be modified only when the DMACTLx DMAEN bit is 0 Otherwise unpredictable DMA triggers may occur When selecting the trigger the trigger must not have already occurred or the transfer will not take place For example if the TACCR2 CCIFG bit is selected as a trigger and it is already set no transfer will occur until the next time the TACCR2 CCIFG bit is set Edge Sensitive Triggers When DMALEVEL 0 edge sensitive triggers are used and the rising edge ofthe trigger signal initiates the transfer In single transfer mode each transfer requires its own trigger When using block or burst block modes only one trigger is required to initiate the block or burst block transfer Level Sensitive Triggers When DMALEVEL 1 level sensitive triggers are used For proper operation level sensitive triggers can only be used when external trigger DMAEO is selected as the trigger DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain hi
162. SZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set When DMADTx 0 the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur In repeated single transfer mode the DMA controller remains enabled with DMAEN 1 and a transfer occurs every time a trigger occurs Figure 8 3 Single Transfer State Diagram DMAEN 0 DMAREQ 0 T Size DMADTx 0 DMAxDA T DestAdd AND DMAxSZ 0 OR DMAEN 0 DMAABORT 1 DMAxSZ ENNMI 1 OR DMAEN 0 2x MCLK AND NMI event DMALEVEL 1 AND Trigger 0 DMAEN 0 DMAEN 1 DMAxSZ gt T Size DMAxSA T_SourceAdd DMAABORT 0 Wait for Trigger Trigger AND DMALEVEL 0 OR Trigger 1 AND DMALEVEL 1 Hold CPU Transfer one word byte Decrement DMAxSZ Modify T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 DMAxS T Size gt DMAxSZ DMAxSA T SourceAdd DMADTIx 4 AND DMAxSZ 0 AND DMAEN 1 Modify T DestAdd Z gt 0 AND DMAEN 1 8 7 Block Transfers 8 8 In block transfer mode a transfer of a complete block of data occurs after one trigger When DMADTx 1 the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered After a block transfer has bee
163. T J J J J nc B T nv B T JC JHS JEQ JZ GE JL MP N JNC JLO NE JNZ MOV PUSH B 5 w w gt XT 5 src dst T Emulated Instruction Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z Compare source and destination Add C decimally to destination Add source and C decimally to dst Decrement destination Double decrement destination Disable interrupts Enable interrupts Increment destination Double increment destination Invert destination Jump if C set Jump if higher or same Jump if equal Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set Jump if lower Jump if not equal Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not C from destination Set C Set N Set Z Subtract source from destination Subtract source and not C from dst Swap bytes Extend sign Test destination Ex
164. TACCRO depending on the output mode An example is shown in Figure 12 14 using TACCRO and TACCR2 Figure 12 14 Output Example Timer in Up Down Mode OFFFFh TACCRO TACCR2 Oh EQU2 EQU2 EQU2 EQU2 TAIFG EQUO TAIFG EQUO Ine up Evens f Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS OUTMOD_7 amp TACCTLx Set output mode 7 BIC OUTMODx amp TACCTLx Clear unwanted bits 1 12 16 Timer A Operation 12 2 6 Timer A Interrupts TACCRO Interrupt Two interrupt vectors are associated with the 16 bit Timer A module TACCRO interrupt vector for TACCRO CCIFG 1 TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register In compare mode any CCIFG flag is set if TAR counts to the associated TACCRx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set The TACCRO CCIFG flag has the highest Timer A interrupt priority
165. TBCLx is buffered by TBCCRx The buffered compare latch gives the user control over when a compare period updates The user cannot directly access TBCLx Compare data is written to each TBCCRx and automatically transferred to TBCLx The timing of the transfer from TBCCRx to TBCLx is user selectable with the CLLDx bits as described in Table 13 2 Table 13 2 TBCLx Load Events CLLDx Description 00 New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to 01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCLO value or to 0 for up down mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as shown in Table 13 3 The CLLDx bits of the controlling TBCCRx must not be set to zero When the CLLDx bits of the controlling TBCCRx are set to zero all compare latches update immediately when their corresponding TBCCRx is written no compare latches are grouped Two conditions must existfor the compare latches to be
166. Table 22 3 Together with the last stored output of the comparator SIFXOUT the two levels can be used as an analog hysteresis as shown in Figure 22 6 The individual settings for the four inputs can be used to compensate for mismatches between the sensors Table 22 3 Selected DAC Registers Selected Output Bit Last Value of DAC Register Used SIFxOUT SIFxOUT SIFOOUT 0 SIFDACRO 1 SIFDACR1 SIF1OUT 0 SIFDACR2 1 SIFDACR3 SIF2OUT 0 SIFDACR4 1 SIFDACR5 SIFSOUT 0 SIFDACR6 1 SIFDACR7 Figure 22 6 Analog Hysteresis With DAC Registers SIFDACR2 DAC Output Voltage SIFDACR3 Input Voltage SIF1OUT When 1 the SIFDACR6 and SIFDACR7 registers used as the comparator reference as described in Table 22 4 Table 22 4 DAC Register Select When TESTDX 1 SIFTESTS1 tsm DAC Register Used 0 SIFDACR6 1 SIFDACR7 22 12 Scan IF Scan IF Operation Internal Signal Connections to Timer1 A5 The outputs of the analog front end are connected to 3 different capture compare registers of Timer1 A5 The output stage of the analog front end shown in Figure 22 7 provides two different modes that are selected by the SIFCS bit and provides the SIFOx signals to Timer1 A5 See the device specific datasheet for connection of these signals Figure 22 7 TimerA Output Stage of the Analog Front End TimerA Output Stage SIFCS 0 0 SIFEX tsm SIFTESTS1 tsm gt Comparator Output
167. The offset voltage of the DAC12 output amplifier can be positive or negative When the offset is negative the output amplifier attempts to drive the voltage negative but cannotdo so The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 21 4 Figure 21 4 Negative Offset Output Voltage 0 Negative Offset 27 DAC Data When the output amplifier has a positive offset a digital input of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code This is shown in Figure 21 5 Figure 21 5 Positive Offset Voc Output Voltage DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifier Setting the DAC12CALON bit initiates the offset calibration The calibration should complete before using the DAC12 When the calibration is complete the DAC12CALON bit is automatically reset The DAC12AMPx bits should be configured before calibration For best calibration results port and CPU activity should be minimized during calibration DAC12 21 7 DAC12 Operation 21 2 6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output Hardware ensures that a
168. Timing The first stage of the baud rate generator is the 16 bit counter and comparator Atthe beginning of each bit transmitted or received the counter is loaded with INT N 2 where N is the value stored in the combination of UXBRO and UxBR1 The counter reloads INT N 2 for each bit period half cycle giving a total bit period of N BRCLKs For a given BRCLK clock source the baud rate used determines the required division factor N N BRCLK baud rate The division factor N is often a non integer value of which the integer portion can be realized by the prescaler divider The second stage of the baud rate generator the modulator is used to meet the fractional part as closely as possible The factor N is then defined as N UxBR 1 5m i 0 Where N Target division factor UxBR 16 bit representation of registers UxBRO and UxBR1 Bit position in the character n Total number of bits in the character Data of each corresponding modulation bit 1 0 Baid ralis BRCLK _ BRCLK UxBR 15 m i 0 The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non integer divisor is needed Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit m is set Each time a bit is received or transmitted the next bit in the modulation control register determines the timing for that bit A set modulation bit increases the division factor by one while a cleared modulation bit maintains
169. UG Scan IF Debug Register Read Mode After 01h Is Written 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 PSM Bits 7 Q0 r r r r r r d Unused Bits Unused After 01h is written to SIFDEBUG these bits are always read as zero 15 13 TSM Index Bits When SIFDEBUG is read after 01h is written to it these bits show the TSM 12 8 register pointer index PSM Bits Bits When SIFDEBUG is read after 01h is written to it these bits show the PSM 7 0 bits Q7 QO SIFDEBUG Scan IF Debug Register Read Mode After 02h Is Written 15 14 13 12 11 10 9 8 Current SIFTSMx Register Contents r r r r r r r r 7 6 5 4 3 2 1 0 Current SIFTSMx Register Contents r r r r r r r r Bits When SIFDEBUG is read after 02h is written to it these bits show the TSM 15 0 output Scan IF 22 37 Scan IF Registers SIFDEBUG Scan IF Debug Register Read Mode After 03h Is Written 15 r 7 14 o f o f a tn r 6 13 12 11 10 9 8 r r r r r r 5 4 3 2 1 0 DAC Data r Unused DAC Register Unused DAC Data 22 38 r Bit 15 Bits 14 12 Bits 11 10 Bits 9 0 Scan IF r r r r F r Unused After 03h is written to SIFDEBUG this bit is always read as zero When SIFDEBUG is read after 03h is written to it these bits show which DAC register is currently selected to control the DAC Unused After 03h is written to SIFDEBUG these bits are always read as zero When SIFDEBUG is read after
170. Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 1 ME1 Read write 004h 000h with PUC SFR interrupt enable register 1 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC Table 15 2 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h with PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC V7 1 Note Modifying the SFR bits To avoid modifying control bits for other modules it is recommended to set or clear the and IFGx bits using BIS Bor BIC B instructions rather than MOV B Or CLR B instructions L
171. When using word instructions only even addresses may be used The low byte of a word is always an even address The high byte is atthe next odd address For example if a data word is located at address xxx4h then the low byte of that data word is located at address xxx4h and the high byte of that word is located at address xxx5h Figure 1 3 Bits Bytes and Words in a Byte Organized Memory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxxbh Word Low Byte xxx4h Introduction 1 5 1 6 Introduction Chapter 2 System Resets Interrupts and Operating Modes This chapter describes the MSP430x4xx system resets interrupts and operating modes Topic Page 2 1 System Reset and 1 22 2 220interruptsaecc 2 5 2 3 Operating Modes 2 13 2 4 Principles for Low Power Applications 2 5 Connection of Unused Pins 4 2 1 System Reset and Initialization 2 1 System Reset and Initialization The system reset circuitry shown in Figure 2 1 sources both a power on reset POR and a power up clear PUC signal Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 2 1 Power On Reset and Power Up Clear Schematic POR SVS POR 5 RST NMI WDTNMIT
172. X SIFSH Operation 0 0 SIFCHx and excitation circuitry is selected 0 1 SIFCHx and sample and hold circuitry is selected 1 X SIFCIx inputs are selected The TESTDX signal and SIFTESTS1 tsm signal select between the SIFxOUT output bits and the SIFTCHxOUT output bits for the comparator output as described in Table 22 2 TESTDX is controlled by the SIFTESTD bit Table 22 2 Selected Output Bits TESTDX SIFCH tsm SIFTESTS1 tsm Selected Output Bit 0 00 X SIFOOUT 0 01 X SIF1OUT 0 10 X SIF2OUT 0 11 X SIFSOUT 1 X 0 SIFTCHOOUT 1 X 1 SIFTCH1OUT When TESTDX 0 the SIFCHx tsm signals select which SIFCIx or SIFCHx channel is excited and connected to the comparator The SIFCHx tsm signals also select the corresponding output bit for the comparator result When TESTDX 1 channel selection depends on the SIFTESTS1 tsm signal When TESTDX 1 and SIFTESTS 1 tsm 0 input channel selection is controlled with the SIFTCHOx bits and the output bit is SIFTCHOOUT When TESTDX 1 and SIFTESTS 1 tsm 1 input channel selection is controlled with the SIFTCH1x bits and the output bit is SIFTCH1OUT Scan IF 22 9 Scan IF Operation When SIFCAX 1 the SIFCSEL and SIFCI3 bits select between the SIFCIx channels and the SIFCI input allowing storage of the comparator output for one input signal into the four output bits SIFOOUT SIFSOUT This can be used to observe the envelope function of sensors The output logic is enabled by the SIFRSON tsm s
173. YS MAC MACS RESHI Contents Upper 16 bits of the result The MSB is the sign of the result The remaining bits are the upper 15 bits of the result Two s complement notation is used for the result Upper 16 bits of the result Upper 16 bits of the result Two s complement notation is used for the result The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 7 3 Table 7 3 SUMEXT Contents MACS Underflow and Overflow 74 Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was negative The multiplier does not automatically detect underflow or overflow in the MACS mode The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is OFFFF FFFFh to 8000 0000h An overflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number An underflow occurs when the sum of two positive numbers yields a resultthatis in the range for a negative number In both of these cases the SUMEXT register contains the correct sign of the result OFFFFh for overflow and 0000h for underflow User software must detect and
174. able For this example S1 and S2 are set at the end of the next TSM sequence To calculate the next state the bits Q5 and 0 of the state 01 table entry together with the S1 and S2 signals are combined to form the next state Q1 is set In state 11 so SIFCNT1 will be incremented More complex state machines can be built by combining simple state machines to meet the requirements of specific applications Scan IF 22 25 Scan IF Operation 22 2 4 Scan IF Debug Register 22 26 Scan IF The Scan IF peripheral has a SIFDEBUG register for debugging and development Only the lower two bits should be written when writing to the SIFDEBUG register and only Mov instructions should be used write to SIFDEBUG After writing the lower two bits reading the SIFDEBUG contents gives the user different information After writing 00h to SIFDEBUG reading SIFDEBUG shows the last address read by the PSM After writing O1h to SIFDEBUG reading SIFDEBUG shows the index of the TSM and the PSM bits Q7 QO After writing 02h to SIFDEBUG reading SIFDEBUG shows the TSM output After writing 03h to SIFDEBUG reading SIFDEBUG shows which DAC register is selected and its contents 22 2 5 Scan IF Interrupts Scan IF Operation The Scan IF has one interrupt vector for seven interrupt flags listed in Table 22 7 Each interrupt flag has its own interrupt enable bit When an interrupt is enabled and the GIE bit is set the interrupt flag will generat
175. able and interrupt flag to avoid errant operating conditions When the TACLK is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Any write to TAR will take effect immediately _ Clock Source Select and Divider 12 4 Timer A The timer clock TACLK can be sourced from ACLK SMCLK or externally via TACLK or INCLK The clock source is selected with the TASSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The TACLK divider is reset when TACLR is set Timer A Operation 12 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by writing O to TACCRO The timer may then be restarted by writing a nonzero value to TACCRO In this scenario the timer starts incrementing in the up direction from zero 12 2 3 Timer Mode Control The timer has four modes of operation as described in Table 12 1 stop up continuous and up down The operating mode is selected with the bits Table 12 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of TACCR
176. access violation occurs ACCVIFG is set and the result is unpredictable Also if a write to flash is attempted with WRT 0 the ACCVIFG interrupt flag is set and the flash memory is unaffected When a byte word write or any erase operation is initiated from within flash memory the flash controller returns op code OSFFFh to the CPU at the next instruction fetch Op code O3FFFh is the JMP PC instruction This causes the CPU to loop until the flash operation is finished When the operation is finished and BUSY 0 the flash controller allows the CPU to fetch the proper op code and program execution resumes The flash access conditions while BUSY 1 are listed in Table 5 3 Table 5 3 Flash Access While BUSY 1 Flash Flash WAIT Result Operation Access Read 0 ACOVIFG 1 OSFFFh is the value read Any erase or Write 0 ACCVIFG 1 Write is ignored Byte word write inctruction 0 ACCVIFG 0 CPU fetches 03FFFh This fetch is the JMP PC instruction Any 0 ACCVIFG 1 LOCK 1 Read 1 ACCVIFG 0 OSFFFh is the value read Block write Write 1 ACCVIFG 0 Write is ignored Instruction 1 ACCVIFG 1 LOCK 1 fetch 5 14 Flash Memory Controller Flash Memory Operation 5 3 5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX Setting the EMEX bit stops the active operation immediately and stops the flash controller All flash operations cease the
177. additional system resources The benefits of embedded emulation include Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported L Development is in system subject to the same characteristics as the final application L Mixed signal integrity is preserved and not subject to cabling interference Introduction 1 3 Address Space 1 4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers SFRs peripherals RAM and Flash ROM memory as shown in Figure 1 2 See the device specific data sheets for specific memory maps Code access are always performed on even addresses Data can be accessed as bytes or words The addressable memory space is 64 KB with future expansion planned Figure 1 2 Memory Map OFFFFh OFFEOh OFFDFh 0200h O1FFh 0100h OFFh 010h OFh Oh 1 41 Flash ROM 1 4 22 RAM 1 4 Introduction Access Interrupt Vector Table Word Byte Flash ROM Word Byte Word Byte 16 Bit Peripheral Modules Word 8 Bit Peripheral Modules Byte Special Function Registers Byte The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is OFFFFh Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the tables to RAM before using them The i
178. am is shown in Figure 17 1 17 2 Comparator A Comparator A Introduction Figure 17 1 Comparator A Block Diagram Voc 0V P2CA0 CAEX of CAON E cao O r CCI1B CAOUT CA1 O 7 1 Set CAIFG P2CA1 Tau 2 0us CAREFx CARSEL 0 5x VCC 0 25 KEW ac Comparator_A 17 3 Comparator A Operation 17 2 Comparator A Operation 17 2 1 Comparator The comparator_A module is configured with user software The setup and operation of comparator_A is discussed in the following sections The comparator compares the analog voltages at the and input terminals If the terminal is more positive than the terminal the comparator output CAOUT is high The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to reduce current consumption When the comparator is switched off the CAOUT is always low 17 2 2 Input Analog Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow L Application of an external signal to the and terminals of the comparator Routing of an internal reference voltage to an associated output port pin Internally the input swi
179. and count rotation or motion The timing state machine controls the analog front end and the processing state machine The Scan IF features include m E m m m E E Support for different types of LC sensors Measurement of sensor signal envelope Measurement of sensor signal oscillation amplitude Support for resistive sensors such as Hall effect or giant magneto resistive GMR sensors Direct analog input for A D conversion Direct digital input for digital sensors such as optical decoders Support for quadrature decoding The Scan IF module block diagram is shown in Figure 22 1 Scan IF Introduction Figure 22 1 Scan IF Block Diagram Scan I F Analog Front End AFE gt To Timer A SIFCI SIFCI3 SIFCI2 D Interrupt Q Request SIFCH 5 Processing State SIFCIO S Machine PSM z Rotation SIFCH3 E Data SIFCH2 SIFCH1 9 SIFCHO SIFCOM Timing State DAC 10 Bit Machine TSM ACLK SIFVSS w RAM w oscillator SMCLK Scan IF 22 3 Scan IF Operation 22 2 Scan IF Operation The Scan IF is configured with user software The setup and operation of the Scan IF is discussed in the following sections 22 2 1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement The analog front end is automatically controlled by the timing state machine according to the information in the timing state machine table Th
180. ase the code needed for execution after the erase If this occurs CPU execution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 5 5 Figure 5 5 Erase Cycle from Within Flash Memory mode Segment Erase from flash 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD amp WDTCTL Disable WDT MOV FWKEY FSSEL1 FN0O amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY ERASE amp FCTL1 Enable segment erase CLR amp OFC10h Dummy write erase S1 MOV FWKEY LOCK amp FCTL3 Done set LOCK Re enable WDT 5 6 Flash Memory Controller Initiating an Erase from RAM Flash Memory Operation Any erase cycle may be initiated from RAM In this case the CPU is not held and can continue to execute code from RAM The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again If a flash access occurs while BUSY 1 itis an access violation ACCVIFG will be set and the erase results will be unpredictable The flow to initiate an erase from flash from RAM is shown in Figure 5 6 Figure 5 6 Erase Cycle from Within RAM Disable watchdog Set LOCK 1 re enable Segment Erase from RAM Assumes ACCVIE MOV BIT JNZ MOV MOV MOV CLR L2 BIT JNZ MOV L1 watchdog NMIIE OFIE WDTPW WDTHOLD amp WDTCTL BUSY amp FCTL3 11
181. askable Interrupts 2 2 8 8 2 2 2 Maskable Interrupts 0 00 cette eee 2 2 3 Interrupt Processing 0 00 niendee nte eens 2 2 4 Interrupt Vectors 2 00 el nnn 2 2 5 Special Function Registers 2 3 Operating Modes whe dae ead eae Dawe an eed s 2 3 1 Entering and Exiting Low Power 2 4 Principles for Low Power Applications 2 5 Connection of Unused Pins 0 cece eee eee eens 3 JRISC 16 BitCPU neces EE Kap MINE D ENSE EE MS 3 4 GPU IntrodUCllOn nec Se EReras RR RETE Ra Ra A etes 3 2 CGPULBSOISIGIS us os iiit Eois ostio ced tisch dob Rue Ru ce Ran deed e Bone a 3 2 1 Program Counter PC iimis dirina nin a ira a eee eae 3 2 3 Stack Pointer SP niii asai gai eee nee 3 2 8 Status Register SR 00 cece eee teens 3 2 4 Constant Generator Registers CG1 and CG2 3 2 5 General Purpose Registers R4 R15 3 3 Addressing Modes wea UA x eae DAY ey Rava Da 3 3 1 Register Mode hn 83 2 Indexed Mode iis e ES 39 3 9 Symbolic Mode 2 02 54 cc cence e mee RI xri need wh REN Y ee 3 3 4 Absolute Mode nisreen hn vii Contents 3 3 5 Indire
182. ata is latched with the falling edge of UCLK 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of UCLK Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Unused Slave transmit control 0 4 pin SPI mode STE enabled 1 3 pin SPI mode STE disabled Transmitter empty flag The TXEPT flag is not used in slave mode 0 Transmission active and or data waiting in UXTXBUF 1 UxTXBUF and TX shift register are empty USART Peripheral Interface SPI Mode 15 15 USART Registers SPI Mode UxRCTL USART Receive Control Register rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag This bit indicates a bus conflict when MM 1 and STC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Undefined Bit6 Unused OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Bit 4 Unused Unused Bit 3 Unused Unused Bit 2 Unused Unused Bit 1 Unused Unused Bit 0 Unused 15 16 USART Peripheral Interface SPI Mod
183. ate the timer continues its descent until it reaches zero The new period takes effect after the counter counts down to zero If the timer is counting in the up direction when the new period is latched into TBCLO and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value when TBCLO is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals see section Timer B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 13 9 the tgeag is tdead timer X TBCL1 TBCL3 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x The ability to simultaneously load grouped compare latches assures the dead times Figure 13 9 Output Unit in Up Down Mode 13 10 TBR max TBOLO wemmmm ICT eee TBOL4 JMf pem Mee TBCL3 JWf EL ppENORMMMW ERN Oh Dead Time Output Mode 6 Toggle Set Output Mode 2
184. ation to WDTCTL must be a word operation with 05Ah WDTPW in the upper byte Periodically clear an active watchdog MOV WDTPW WDTCNTCL amp WDTCTL Change watchdog timer interval MOV WDTPW WDTCNTL SSEL amp WDTCTL Stop the watchdog MOV WDTPW WDTHOLD amp WDTCTL Change WDT to interval timer mode clock 8192 interval MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL Watchdog Timer Watchdog Timer Watchdog Timer Registers 10 3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10 1 Table 10 1 Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with 1 WDTIFG is reset with POR Watchdog Timer Watchdog Timer 10 7 Watchdog Timer Registers WDTCTL Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW must be written as 05Ah rw 0 WDTPW WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx 7 6 5 4 3 2 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx 0 rO w rw Bits 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 0 1 rw 0 rw 0 rw 0 rw 0 rw 0 Watchdog timer password Always read as 069h Must be written as 05Ah or a PUC will be generated
185. atterns 4 8 NDCOmod wt 24 L 2 16 Lower DCO Tap Frequency fpco Upper DCO Tap Frequency fpco 1 f DCOCLK Cycles Shown for DCOCLK f ACLK x 32 One ACLK Cycle FLL Clock Module FLL Operation from Low Power Modes 4 2 7 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCGO 1 When the FLL is disabled the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized The DCO modulator is disabled when SCFQ M 2 0 When the DCO modulator is disabled the DCOCLK is adjusted to the nearest of the available DCO taps 4 2 8 FLL Operation from Low Power Modes An interrupt service request clears SCG1 CPUOFF and OSCOFF if set but does not clear SCGO This means that FLL operation from within an interrupt service routine entered from LPM1 2 3 or 4 the FLL remains disabled and the DCO operates at the previous setting as defined in SCFIO and SCFI1 SCGO can be cleared by user software if FLL operation is required 4 2 9 Buffered Clock Output ACLK may be divided by 1 2 4 or 8 and buffered out of the device on P1 5 The division rate is selected with the FLL_DIV bits The ACLK output is multiplexed with other pin functions When multiplexed the pin must be configured for the ACLK output BIS B P1SEL_5 amp P1SEL Select ACLK n signal as output for port P1 5 if BIS B P1DIR_5 amp P1DIR Select port P1 5 to ACLK n Signal fo
186. bel JNZ label If Z 0 PC 2x offset gt PC If Z 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump ioo if equal continue RISC 16 Bit CPU 3 51 Instruction Set MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Move source to destination Move source to destination MOV src dst or MOV W src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV QR104 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 4
187. bit is ANDed with each segment s memory bit When LCDSON 1 each segment is on or off according to its bit value When LCDSON 0 each LCD segment is off 18 2 3 LCD Timing Generation 18 4 The LCD controller uses the f cp signal from the Basic Timer1 to generate the timing for common and segment lines The proper frequency f cp depends on the LCD s requirement for framing frequency and LCD multiplex rate See the Basic Timer1 chapter for more information on configuring the fj cp frequency LCD Controller LCD Controller Operation 18 2 4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33 R23 R13 and R03 Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in Table 18 1 The resistor value R is typically 680 kQ Values of R from 100k to 1MQ can be used depending on LCD requirements R33 is a switched Vog output This allows the power to the resistor ladder to be turned off eliminating current consumption when the LCD is not used Table 18 1 External LCD Module Analog Voltage OSCOFF LCDMXx LCDON VA VB VD R33 X 0 0 0 0 0 Off 1 XX X 0 0 0 0 Off 0 00 1 V5 V1 V1 N5 V5BN1 V1 V5 On 0 01 1 V5 V1 V1 N5 V3N3 V1 V5 On 0 1x 1 V5 V1 V2NA V4AN2 VI V5 On LCD Contrast Control LCD contrast can be controlled by the ROS voltage level with external circuitry typically an additional resistor Rx to GND Increasing
188. bit timing error The second is the error between a start edge occurring and the start edge being accepted by the USART Figure 14 9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud rate clock Figure 14 9 Receive Error i 0 tideal to ty 1 2 4 5 6 7 1 11 12 1 14 1 2 4 5 6 7 9 1 11 12 1 14 1 2 3 4 5 e URXDx st DO D1 URXDS ST DO D1 lactual to t t2 Synchronization Error 0 5x BRCLK URXDS Int UxBR 2 m0 UxBR m1 13 1 14 UxBR m2 1340 13 LIA int 13 2 41 261 L7 H Majority Vote Taken Majority Vote Taken The ideal start bit timing tigeaj o is half the baud rate timing tpaug rate because the bitis tested in the middle of its period The ideal baud rate timing tiqea i for the remaining character bits is the baud rate timing tpaug The individual bit errors can be calculated by Error 96 2 x mo int UAB i x UxBR Tm e x 100 Where baud rate is the required baud rate BRCLK is the input frequency selected for UCLK ACLK or SMCLK j 0 for the start bit 1 for data bit DO and so on UxBR is the division factor in registers UXBR1 and UxBRO 14 14 USART Peripheral Interface UART Mode USART Operation UART Mode For example the receive errors for the following conditions are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK
189. bled SMCLK ACLK are active 0 1 0 1 LPM1 CPU MCLK DCO osc are disabled DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK ACLK are active 1 0 0 1 LPM2 CPU MCLK SMCLK DCO osc are disabled DC generator remains enabled ACLK is active 1 1 0 1 LPM3 CPU MCLK SMCLK DCO osc are disabled DC generator disabled ACLK is active 1 1 1 1 LPM4 CPU and all clocks disabled 2 14 System Resets Interrupts and Operating Modes Operating Modes 2 3 1 Entering and Exiting Low Power Modes An enabled interrupt event wakes the MSP430 from any of the low power operating modes The program flow is Enter interrupt service routine B The PC and SR are stored on the stack B The CPUOFF SCG1 and OSCOFF bits are automatically reset J Options for returning from the interrupt service routine B The original SR is popped from the stack restoring the previous operating mode B The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed Enter LPMO Example BIS GIE CPUOFF SR Enter LPMO H MEETS Program stops here Exit LPMO Interrupt Service Routine BIC SCPUOFF O0 SP Exit LPMO on RETI RETI Enter LPM3 Example BIS GIE CPUOFF SCG1 SCGO SR Enter LPM3 Program stops here Exit LPM3 Interrupt Service Routine BIC SCPUOFF SCG1 4SCGO 0 SP Exit LPM3 on RETI RETI E
190. c and Vp AVss 001 Vn VREF and VR AVss 010 Vg Vener and Vp AVss 011 Vengr and Vp AVss 100 Vg AVcc and Vp Vnggr Vengr 101 Vg Vref and Vp VREF Vengr 110 Vg Veggr and Vp VREF Venggr 111 Vg Verner and Vp VREF Vengr INCHx Bits Input channel select 3 0 0000 0001 A1 0010 A2 0011 0100 A4 0101 5 0110 A6 0111 A7 1000 VeREF 1001 VReF VeREF 1010 Temperature diode 1011 AVcc AVss 2 1100 AVcc AVss 2 A12 on MSP430FG43x devices 1101 AVcc AVsg 2 A13 on MSP430FG43x devices 1110 AVcc AVsg 2 A14 on MSP430FG43x devices 1111 AVcc AVgs 2 A15 on MSP430FG43x devices ADC12 19 25 ADC12 Registers ADC12IE ADC12 Interrupt Enable Register ADC121E15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IFG9 ADC12IE8 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 ADC12IE7 ADC12IE6G ADC12IE5 ADC12IEA ADC12IE3 ADC12IE2 ADC12IE1 ADC12IEO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IEx Bits Interrupt enable These bits enable or disable the interrupt request for the 15 0 ADC12IFGx bits 0 Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG15 IFG14 IFG13 IFG12 IFG11 IFG10 IFG9 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG7 IFG6 IFG5 IFG4 IFG3 IFG2 IFG1 IFGO n w 0 rw 0 rw 0 rw 0 rw 0 n w 0
191. cally configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup or halt the WDT prior to the expiration of the initial reset interval f Watchdog Timer Watchdog Timer Watchdog Timer Introduction Figure 10 1 Watchdog Timer Block Diagram WDTCTL MSB MDB 16 bit Password Counter Compare Generator 16 bit PUC lt gt Write Enable Low Byte MCLKT SMCLK WDTHOLD ACLK WDTNMIES WDTNMI WDTTMSEL TMSP430x42x and MSP430FE42x devices only Clock MCLK Active Request SMCLK Active ACLK Active Logict Watchdog Timer Watchdog Timer 10 3 Watchdog Timer Operation 10 2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register The WDTCTL register also contains control bits to configure the RST NMI pin WDTCTL is a 16 bit password protected read write register Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte Any write to WDTCTL with any value otherthan 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode Any read of WDTCTL reads 069h in the upper byte 10 2 1 Watchdog Timer Counter The watchdog timer counter WDTCNT is a 16 bit up counter that is not directly accessible by softwa
192. can IF Operation 22 2 8 Quadrature Decoding The Scan IF can be used to decode quadrature encoded signals Signals that are 90 out of phase with each other are said to be in quadrature To Create the signals two sensors are positioned depending on the slotting or coating of the encoder disk Figure 22 19 shows two examples for the sensor positions and a quadrature encoded signal waveform Figure 22 19 Sensor Position and Quadrature Signals Sensor A Sensor A Signal S1 Damping or dark area Signal S1 Es Sensor B 45 9 Signal S2 Sensor B Signal S2 OIO Sensor A Signal S1 ji Sensor B Signal S2 gt we LEe 1 LI LI Li Li o O B B B B B B Li Quadrature decoding requires knowing the previous quadrature pair 51 and S2 as well as the current pair Comparing these two pairs will tell the direction of the rotation For example if the current pair is 00 it can change to 01 or 10 depending on direction Any other change in the signal pair would represent an error as shown in Figure 22 20 Scan IF 22 33 Scan IF Operation Figure 22 20 Quadrature Decoding State Diagram 1 Correct State Transitions 94 2 Erroneous State Transitions To transfer the state encoding into counts it is necessary to decide what fraction of the rotation should be counted and on what state transitions In this examp
193. can IF control 2 SIFCTL2 Read write 01B8h Reset with POR Scan IF control 3 SIFCTL3 Read write 01BAh Reset with POR Scan IF control 4 SIFCTL4 Read write 01BCh Reset with POR Scan IF control 5 SIFCTL5 Read write 01BEh Reset with POR Scan IF DAC 0 SIFDACRO Read write 01 Unchanged Scan IF DAC 1 SIFDACR1 Read write 01C2h Unchanged Scan IF DAC 2 SIFDACR2 Read write 01C4h Unchanged Scan IF DAC 3 SIFDACR3 Read write 01C6h Unchanged Scan IF DAC 4 SIFDACR4 Read write 01C8h Unchanged Scan IF DAC 5 SIFDACR5 Read write 01CAh Unchanged Scan IF DAC 6 SIFDACR6 Read write 01CCh Unchanged Scan IF DAC 7 SIFDACR7 Read write 01CEh Unchanged Scan IF TSM 0 SIFTSMO Read write 01DOh Unchanged Scan IF TSM 1 SIFTSM1 Read write 01D2h Unchanged Scan IF TSM 2 SIFTSM2 Read write 01D4h Unchanged Scan IF TSM 3 SIFTSM3 Read write 01D6h Unchanged Scan IF TSM 4 SIFTSM4 Read write 01D8h Unchanged Scan IF TSM 5 SIFTSM5 Read write 01DAh Unchanged Scan IF TSM 6 SIFTSM6 Read write 01DCh Unchanged Scan IF TSM 7 SIFTSM7 Read write 01DEh Unchanged Scan IF TSM 8 SIFTSM8 Read write 01E0h Unchanged Scan IF TSM 9 SIFTSM9 Read write 01E2h Unchanged Scan IF TSM 10 SIFTSM10 Read write 01E4h Unchanged Scan IF TSM 11 SIFTSM11 Read write 01E6h Unchanged Scan IF TSM 12 SIFTSM12 Read write 01E8h Unchanged Scan IF TSM 13 SIFTSM13 Read write 01EAh Unchanged Scan IF TSM 14 SIFTSM14 Read write 01ECh Unchanged Scan IF TSM 15 SIFTSM15 Read write 01EEh Unchanged Scan IF TSM 16 SIFTSM16 Read write 01FOh U
194. cess of counting for the action to take place If a particular value is directly written to the counter then an associated action does not take place 1 13 1 1 Similarities and Differences From Timer A 13 2 Timer B Timer B is identical to Timer A with the following exceptions The length of Timer B is programmable to be 8 10 12 or 16 bits Timer B TBCCRx registers are double buffered and can be grouped All Timer B outputs can be put into a high impedance state The SCCI bit function is not implemented in Timer B Figure 13 1 Timer B Block Diagram Timer B Introduction pe Vee CIN Sere ng PEE See TT cae EEUU Tn nu c S DUE Timer Block TBSSELx Timer Clock T imer Bloc 1 15 0 1 1 1 n i 1 TBCLK 00 16 bit Timer Count TBR RC Pad EQUO 1 2 4 8 Mode i i ACLK 01 M Clear 8 10 12 16 SMCLK 10 CNTLx INCLK 11 TBCLR i 00 i TBCLGRPx 01 i Set TBIFG i i 10 Group T Load Logic i CCRO CCR1 CCR2 CCR3 CCR4 CCR5 Nu a eet ee eee ey ee AIT CCISx CM CCR6 x cov i SCS 1 CCI6A 00 Capture CCI6B ot Mode Ey i TBCCR6 GND 10 Timer Clock Sync TccR8 i VCC 11 i i CLLDx Compare Latch TBCL6 i Load Logic i 1 1 1 1 EQUO UP DOWN EQU6 cap i e i Set TBCCR6 CCIFG 1 1
195. changed Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Digital I O 9 7 9 8 Digital O Chapter 10 Watchdog Timer Watchdog Timer The watchdog timer is a 16 bit timer that can be used as a watchdog or as an interval timer This chapter describes the watchdog timer The watchdog timer is implemented in all MSP430x4xx devices The MSP430x42x and MSP430FE42x devices implement an enhanced WDT called WDT Topic Page 10 1 Watchdog Timer Introduction 10 2 Watchdog Timer Operation 10 2 Watchdog Timer Registers 10 1 Watchdog Timer Introduction 10 1 Watchdog Timer Introduction 10 2 The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts at selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source Can be stopped to conserve power UU oo oo Clock fail safe feature in WDT The WDT block diagram is shown in Figure 9 1 Note Watchdog Timer Powers Up Active After a PUC the WDT module is automati
196. clusive OR source and destination dst gt dst src dst 5 dst src dst gt dst src and dst dst not src and dst dst Src or dst dst src and dst dst PC 2 gt stack dst PC 0 2 dst 02C 0 gt N 02Z dst src dst C dst decimally Src dst C dst decimally dst 1 gt dst dst 2 dst 0 GIE 1o GIE dst 1 dst dst 2 dst not dst dst PC 2 x offset gt PC src gt dst SP gt dst SP 2 5 SP SP 2 SP src gt SP SP PC SP 2 gt SP dst OFFFFh C gt dst 12C 1 gt N 1 gt C dst not src 1 gt dst dst not src C dst dst OFFFFh 1 src xor dst dst RISC 16 Bit CPU Oo o Instruction Set N 2 Cc 0 0 0 2 1 1 2 1 1 3 75 3 76 Chapter 4 FLL Clock Module The FLL clock module provides the clocks for MSP430x4xx devices This chapter discusses the FLL clock module The FLL clock module is implemented in all MSP430x4xx devices Topic Page 41 FLL Clock Module Introduction 4 2 Clock Module 14 5 4 3 Clock Module Registers 4 1 41
197. ct Register Mode sssseseseeee ee 3 3 6 Indirect Autoincrement Mode 3 3 7 Immediate Mode nnn 3 4 Instruction Set eed det Dh de teu ier dn 3 4 1 Double Operand Format 1 3 4 2 Single Operand Format Il Instructions BAS Jumps debe E etm Et Rodas acte BLUE aie teats Ia a 3 4 4 Instruction Cycles and Lengths 3 4 5 Instruction Set Description A FLL Clock Module olm n erem ique de TERR dn 4 1 Clock Module Introduction sssssssssessse III 4 2 FLL Clock Module Operation 0 cece cent ee ee eae 4 21 Clock features for Low Power Applications 42 2 LEFXT1 Oscillator x ret tke De dedu e deg s 4239 I2 OSGAN 4 2 4 Digitally Controlled Oscillator 4 2 5 Frequency Locked Loop FLL 0 00 0 0 4 2 0 DCO Modulator cos sese en RR ARA RE EEG 4 2 7 Disabling the FLL Hardware and 4 2 8 FLL Operation from Low Power Modes 4 2 9 Buffered Clock Output
198. d MEM LEO 052h RISC 16 Bit CPU 3 43 Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C 1 2x offset gt If C 2 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The P1IN 1 signal is used to define or control the program flow BIT 01h amp P1IN State of signal gt Carry JC PROGA If carry 1 then execute program routine A desis Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 gt 15 E Continue here if R5 15 3 44 RISC 16 Bit CPU JEQ JZ Syntax Operation Description Status Bits Example Example Example Instruction Set Jump if equal jump if zero JEQ label JZ label IfZ 1 2x offset gt PC If Z 0 execute following instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump
199. d The PSM vector SIFPSMV mustto be initialized to point to the PSM state table Multiple state tables are possible by reconfiguring the SIFPSMV to different tables as needed The PSM block diagram is shown in Figure 22 11 Scan IF Operation Figure 22 11 Scan IF Processing State Machine Block Diagram SIFS1x SIFOOUT 00 SIF1OUT g e 01 SIF2OUT 10 SIF3OUT g 11 Ll SIFS2x SIFQ6EN SIFQ7EN SISTOP tsm PSM Operation State ees N RICO N 9 MSP430 Memory Range State Table Q7 QO SIFCNT1ENP SIFEN SIFIS1x 00 A4 E 01 Set SIFIFG3 sf 10 11 SIFCNT1ENM SIFCNTRST SIFIS2x 00 A4 01 Set SIFIFG4 sf 10 11 1 2 Set SIFIFG5 Q6 Ld Q7 Set SIFIFG7 At the falling edge of the SIFSTOP tsm signal the PSM moves the current state byte from the PSM state table to the PSM output latch The PSM has one dedicated channel of direct memory access so all accesses to the PSM state table s are done automatically with no CPU intervention Scan IF 22 21 Scan IF Operation The current state and next state logic are reset while the Scan IF is disabled One of the bytes stored at addresses SIFPSMV to SIFPSMV 3 will be loaded first depending on the S1 and S2 signals when the Scan IF is enabled Signals S1 and S2 form a 2 bit offset added to the SIFPSMV contents to d
200. d was written correctly 1 FCTLx password was written incorrectly Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy Flash Memory Controller Flash Memory Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE Bits 7 6 4 0 Bit 5 rw 0 These bits may be used by other modules See device specific datasheet Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Flash Memory Controller 5 21 5 22 Flash Memory Controller Chapter 6 Supply Voltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in all MSP430x4x devices Topic Page 6 1 SVS Introduction cube Lea 6 2 6 2 SVS Opetatloncc eL LM eee arene 6 4 6 34 SVS Registers 6 1 SVS Introduction 6 4 SVS Introduction The supply voltage supervisor SVS is used to monitor the AVcc supply voltage or an external voltage The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVcc monitoring Selectable generation of POR Output of SVS compara
201. d write 08Fh Reset with POR 19 20 ADC12 ADC12 Registers ADC12CTLO ADC12 Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when ENC 0 SHT1x Bits Sample and hold time These bits define the number of ADC12CLK cycles in 15 12 the sampling period for registers 12 8 to ADC12MEM 15 SHTOx Bits Sample and hold time These bits define the number of ADC12CLK cycles in 11 8 the sampling period for registers ADC12MEMO to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 256 1001 384 1010 512 1011 768 1100 1024 1101 1024 1110 1024 1111 1024 ADC12 19 21 ADC12 Registers MSC REF2 5V REFON ADC120N Bit 7 Bit 6 Bit 5 Bit 4 ADC120VIE Bit ADC12 TOVIE ENC ADC12SC 19 22 Bit 2 Bit 1 Bit 0 ADC12 Multiple sample and conversion Valid only for sequence or repeated modes The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 15V 1 2 5V Reference generator on 0 Reference off 1 Reference on ADC12 on
202. des 17 2 4 Voltage Reference 17 2 5 Comparator A Port Disable Register CAPD 17 2 6 Comparator A Interrupts 3 17 2 7 Comparator A Used to Measure Resistive Elements 17 3 Comparator A Registers ene 18 ECD Controller sis cent eel RR eee ees 18 1 LCD Controller Introduction 0 cece III 18 2 LCD Controller Operation ssssssssssessse eI 18 221 LOD Memoty ver DPEP HR A rus 18 2 2 Blinking the LOD lema eo dad ace id 18 2 3 LCD Timing Generation 00 cece cette 18 2 4 LCD Voltage Generation 18 2 5 ECD Outputs ies din ded dtd nnd diee eo deed aa AR 18 2 607 Static Mode eats etis ders ada beat Run Renee martes 19 2 4 2 M x MOUS ze odisse dtt 18 28 3 Mux MOJO 22 a ai Ra E da 18 2 9 4 Mux MOUS ciens adda homed he dane ed hr nerd 18 3 LCD Controller Registers 00 cece ett 9 opm 19 1 ADC12 Introduction ga ie e aa nn 19 2 ADC12 Op ration teed 19 2 1 12 Bit ADC Core nienn angaa teens 19 2 2 ADC12 Inputs and Multip
203. discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Pin functions internal signal connections and operational paramenters differ from device to device The user should consult the device specific datasheet for these details Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http www ti com msp430 This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference Notational Conventions Program examples are shown in a special typeface Glossary Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE INT N 2 ISR LSB LSD LPM MAB MCLK MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCLK
204. dog Timer The WDT interval should be changed together with WDTCNTCL 1 ina single instruction to avoid an unexpected immediate PUC or interrupt The WDT should be halted before changing the clock source to avoid a possible incorrect interval Watchdog Timer Watchdog Timer Watchdog Timer Operation 10 2 4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control The WDT interrupt flag WDTIFG located in IFG1 0 The WDT interrupt enable WDTIE located in IE1 0 When using the WDT in the watchdog mode the WDTIFG flag sources a reset vector interrupt The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the watchdog timer initiated the reset condition either by timing out or by a security key violation If WDTIFG is cleared the reset was caused by a different source When using the WDT in interval timer mode the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set The interval timer interrupt vector is different from the reset vector used in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with software 10 2 5 WDT Enhancements The WDT module provides enhanced functionality over the WDT The WDT provides a fail safe clocking feature a
205. dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X 3 28 RISC 16 Bit CPU CALL Syntax Operation Description Status Bits Example Instruction Set Subrouti
206. dy in three MCLK cycles and can be read with the next instruction after writing to OP2 except when using an indirect addressing mode to access the result When using indirect addressing for the result a NOP is required before the result is ready 7 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 7 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply operation Writing OP2 starts the selected operation with the values stored in OP1 and OP2 The result is written into the three result registers RESLO RESHI and SUMEXT Repeated multiply operations may be performed without reloading OP1 if the 1 value is used for successive operations It is not necessary to re write the OP1 value to perform the operations Table 7 1 OP1 addresses OP1 Address Register Name Operation 0130h MPY Unsigned multiply 0132h MPYS Signed multiply 0134h MAC Unsigned multiply accumulate 0136h MACS Signed multiply accumulate Hardware Multiplier 7 3 Hardware Multiplier Operation 7 2 2 Result Registers The result low register RESLO holds the lower 16 bits of the calculation result The result high register RESHI contents depend on the multiply operation and are listed in Table 7 2 Table 7 2 RESHI Contents Mode MPY MP
207. e Monotonic 12 bit converter with no missing codes Sample and hold with programmable sampling periods controlled by software or timers Conversion initiation by software Timer A or Timer B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference L L L Eight individually configurable external input channels twelve on MSP430FG43x devices L Conversion channels for internal temperature sensor AVcc and external references Lj Independent channel selectable reference sources for both positive and negative references Selectable conversion clock source Single channel repeat single channel sequence and repeat sequence conversion modes ADC core and reference voltage can be powered down separately Interrupt vector register for fast decoding of 18 ADC interrupts 16 conversion result storage registers The block diagram of ADC12 is shown in Figure 19 1 ADCt12 Introduction Figure 19 1 ADC12 Block Diagram REF2 5V REFON INCHx 0Ah VeREF VREF i 1 5 Vor 2 5 V Vngr VeREF Reference gt AVCC SREF1 ro SREFO ADC120SC AO SREF2 1 ADC120N ADC12SSELx A1 ds ADC12DIVx P Sample 00 A5 and Divider 01 ACLK 6 Hold 12 bit SAR a ewe S H Convert ADCI2CLK 11 SMCLK BUSY m A12 X
208. e Example Instruction Set Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C dst ADDC 0 dst ADDC B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD RISC 16 Bit CPU 3 21 Instruction Set ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst or ADD W Ssrc dst ADD B src dst src dst dst The source operand is added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if a
209. e USART Registers SPI Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 Rae rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBRO to set the baud rate Unpredictable SPI operation occurs if UxBR lt 2 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 Lx pe sos pose rw rw rw rw rw rw rw rw UxMCTLx Bits The modulation control register is not used for SPI mode and should be set 7 0 to 000h USART Peripheral Interface SPI Mode 15 17 USART Registers SPI Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 EES r r r r r r r f UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UXRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 KEABEKAESERENXERERE rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and contains current data to be 7 0 transmitted When seven bit character length is used the data should be MSB justified before being moved into UxTXBUF Data is transmitted MSB first Writing to UXTXBUF clears UTXIFGx 15 18 USART Peripheral Interface SPI Mode USART Regist
210. e 054h Reset with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUC FLL Clock Module 4 11 FLL Clock Module Registers SCFQCTL System Clock Control Register 7 rw 0 SCFQO M z rw 0 Bit 7 Bits 6 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 Modulation This enables or disables modulation 0 Modulation enabled 1 Modulation disabled Multiplier These bits set the multiplier value for the DCO When DCOPLUS 0 N 1 forystal When DCOPLUS 1 fpcocLk D x N 1 forystal SCFIO System Clock Frequency Integrator Register 0 7 6 5 4 3 2 1 0 ee rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FLLDx Bits FLL loop divider These bits divide fpcocLk in the FLL feedback loop 7 6 This results in an additional multiplier for the multiplier bits See also multi plier bits 00 01 2 10 11 8 FN x Bits DCO Range Control These bits select the fpco operating range 5 2 0000 0 65 6 1 MHz 0001 1 3 12 1 MHz 001x 2 17 9 MHz 01 2 8 26 6 MHz 1 4 2 46 MHz MODx Bits Least significant modulator bits Bit 0 is the modulator LSB These bits 1 0 affect the modulator pattern All MODx bits are modified automatically by 4 12 the FLL FLL Clock Module FLL Clock Module Registers SCFI1 System Clock Frequency Integrator Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0
211. e 15 5 Slave Transmit Enable State Diagram USPIEx 0 No Clock at UCLK Not Completed USPIEx 1 Idle State USPIEx 1 Transmit Transmitter Transmission ipsi Interrupt dd Enabled External Clock Active USPIEx 0 Present Character USPIEx 1 Transmitted PUC USPIEx 0 USART Peripheral Interface SPI Mode 15 7 15 8 USART Operation SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 15 6 and Figure 15 7 When USPIEx 0 UCLK is disabled from shifting data into the RX shift register Figure 15 6 SPI Master Receive Enable State Diagram USPIEx 0 No Data Written to UxTXBUF Not Completed USPIEx 1 Receive USPIEx 1 Handle Interrupt Enabled Data Written Character Conditions USPIEx 0 to UXTXBUF Character Received PUC USPIEx 1 USPIEx 0 Figure 15 7 SPI Slave Receive Enable State Diagram No Clock LK USPIEx 0 0 Clockat UG Not Completed USPIEx 1 Receive Idle State USPIEx 1 Handle Interrupt Receive Collects Conditions Disable Enabled External Clock Character USPIEx 0 Present Character USPIEx 1 Received PUC USPIEx 0 USART Peripheral Interface SPI Mode USART Operation SPI Mode 15 2 5 S
212. e 5 1 F7 1 Note Minimum Vcc During Flash Write or Erase The minimum Vcc voltage during a flash write or erase operation is 2 7 V If Vcc falls below 2 7 V during a write or erase the result of the write or erase will be unpredictable Figure 5 1 Flash Memory Module Block Diagram 5 2 Address Latch Data Latch Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator Flash Memory Controller Flash Memory Segmentation 5 2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments Single bits bytes or words can be written to flash memory but the segment is the smallest size of flash memory that can be erased Three erase modes provide the ability to erase single segment erase all main segments or erase all segments main and information segments The flash memory is partitioned into main and information memory sections There is no difference in the operation of the main and information memory sections Code or data can be located in either section The differences between the two sections are the segment size and the physical addresses The information memory has two 128 byte segments The main memory has two or more 512 byte segments See the device specific datasheet for the complete memory map of a device Figure 5 2 shows the flash segmentation using an example of 4 KB flash that has eight main segments and both information
213. e Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h 05Fh ADD B R5 0 R6 ADD B R6 R5 08 05Fh 012h 002h OA1h 00061h Mem 0203h 0 1 R5 00061h C 0 Z 0 N 1 C 0 Z 0 N 0 Low byte of register Addressed byte Addressed byte Low byte of register gt Addressed byte gt Low byte of register zero to High byte 3 8 RISC 16 Bit CPU 3 3 Addressing Modes Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions The bit numbers in Table 3 3 describe the contents of the As source and Ad destination mode bits Table 3 3 Source Destination Operand Addressing Modes As Ad 00 0 01 1 01 1 01 1 10 11 11 Addressing Mode Syntax Register mode Rn Indexed mode X Rn Symbolic mode ADDR Absolute mode amp ADDR Indirect register Rn mode Indirect Rn autoincrement Immediate mode N Description Register contents are operand Rn X points to the operand X is stored in the next word PC X points to the operand X is stored in the next word Indexed mode X PC is used The word following the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used Rn is used as a pointer to the operand Rn is used as a pointer to the operand Rn is incremented afterwards by 1
214. e an interrupt The interrupt flags are not automatically cleared They must be cleared with software Table 22 7 Scan IF Interrupts Interrupt Flag SIFIFGO SIFIFG1 SIFIFG2 SIFIFG3 SIFIFG4 SIFIFG5 SIFIFG6 Interrupt Condition SIFIFGO is set by one of the AFE SIFXOUT outputs selected with the SIFIFGSETx bits SIFIFG1 is set by the rising edge of the SIFSTOP tsm signal SIFIFG2 is set at the start of a TSM sequence SIFIFG3 is set at different count intervals of the SIFCNT1 counter selected with the SIFIS1x bits SIFIFGA is set at different count intervals of the SIFCNT2 counter selected with the SIFIS2x bits SIFIFG5 is set when the PSM transitions to a state with Q6 set SIFIFG6 is set when the PSM transitions to a state with Q7 set Interrupt flags SIFIFG3 and SIFIFG4 have hysteresis so that the interrupt flag is set only once if the counter oscillates around the interrupt level as shown in Figure 22 13 Figure 22 13 Interrupt Hysteresis Shown For Modulo 4 Interrupt Generation SIFCNT1 Interrupt Flag Not Set O Interrupt Flag Is Set Scan IF 22 27 Scan IF Operation 22 2 6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a damping material to measure rotation Rotation is measured with LC sensors by exciting the sensors and observing the resulting oscillation The oscillation is either damped or un damped by the rotating disk The oscillati
215. e analog front end block diagram is shown in Figure 22 2 Note Timing State Machine Signals Throughout this chapter signals from the TSM are noted in the signal name with tsm For example The signal SIFEX tsm comes from the TSM 22 4 Scan IF Operation Figure 22 2 Scan IF Analog Front End Block Diagram SIFCISEL SIFCACI3 SIFCI 4 10 01 00 SIFCAINV Output Stage SIFRSON tsm SIFCI1 SIFCIO SIFCA tsm SIEGAON SIFOOUT Sample Hold SIFCAX SIF1OUT SIFCH3 lt SIF2OUT SIFCH2 5 4 SIF3OUT SIFCH1 lt e SIFCHO lt SIFDAC tsm SIFDACON SIFTCHOOUT SIFTCH1OUT e bi t SIFTEN Excitation SIFDACR5 SIFDACR6 SIFDACR7 SIFLCEN tsm JESI 9 SIFTESTD SIFEX tsm e SIFTESTS 1 tsm 11 7 SIFTCH1x 2o SIFTCHOx 01 SIFCHx tsm Scan IF 22 5 Scan IF Operation Excitation The excitation circuitry is used to excite the LC sensors orto power the resistor dividers The excitation circuitry is shown in Figure 22 3 with one LC sensor connected When the SIFTEN bit is set and the SIFSH bit is cleared the excitation circuitry is enabled and the sample and hold circuitry is disabled When the SIFEX tsm signal from the timing state machine is high the SIFCHx input of the selected channel
216. e individual I Os Any combination of input or output n Individually configurable P1 and P2 interrupts Independent input and output data registers Digital I O Operation 9 2 Digital I O Operation The digital I O is configured with user software The setup and operation of the digital I O is discussed in the following sections 9 2 1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 0 The input is low Bit 1 The input is high Note Writing to Read Only Registers PxIN Writing to these read only registers results in increased current consumption while the write attempt is active EILILIIILI L 9 2 2 Output Registers PxOUT Each bit in each PXOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high 9 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I O pin regardless of the selected function for the pin PxDIR bits for I O pins that are selected for other module functions must be set as required by the other function Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direct
217. e o di e ie e o e 470 nF p Power Supply 470 nF Terminals SIFCI SIFCI3 SIFCI2 SIFCI1 SIFCIO SIFCH3 SIFCH2 SIFCH1 SIFCHO SIFCOM SIFVSS DVss AVss DVcc AVcc Scan IF 22 31 Scan IF Operation 22 2 7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation The damping material and magnets modify the electrical behavior of the sensor so that rotation and direction can be detected Rotation is measured with resistive sensors by connecting the resistor dividers to ground for a short time allowing current flow through the dividers The resistors are affected by the rotating disc creating different divider voltages The divider voltages are sampled with the sample and hold circuits After the signals have settled the dividers may be switched off to prevent current flow and reduce power consumption The DAC is used to set the reference level forthe comparator and the comparator detects ifthe sampled voltage is above or below the reference level If the sampled voltage is above the reference level the comparator output is high Figure 22 18 shows the connection for resistive sensors Figure 22 18 Resistive Sensor Connections ANN 9 9 e o SIFCOM SIFVSS DVss Power Supply 470 nF AVss Terminals o DVcc AVcc 22 32 Scan IF S
218. e the converter to perform successive conversions automatically and as quickly as possible a multiple sample and convert function is available When MSC 1 CONSEQx gt 0 and the sample timer is used the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting ENC bit Conversion data are unreliable en NEP Note No EOS Bit Set For Sequence If no E
219. eAdd AND D d 0 DMAxDA T DestAdd DMAEN 0 DMAABORT 1 DMAABORT 0 DMAEN 0 DMAREQ 0 T Size gt DMAxSZ Wait for Trigger 2x MCLK Hold CPU Transfer one word byte ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 Decrement DMAxSZ Modify T SourceAdd Modify T DestAdd Trigger AND DMALEVEL 0 OR Trigger 1 AND DMALEVEL 1 DMAxSA T_SourceAdd DMAxDA T DestAdd DMADTx 5 AND DMAxSZ 0 AND DMAEN 1 DMAxSZ gt 0 8 9 Burst Block Transfers 8 10 In burst block mode transfers are block transfers with CPU activity interleaved The CPU executes 2 MCLK cycles after every four byte word transfers of the block resulting in 2096 CPU execution capacity After the burst block CPU execution resumes at 10096 capacity and the DMAEN bit is cleared DMAEN must be set again before another burst block transfer can be triggered After a burst block transfer has been triggered further trigger signals occurring during the burst block transfer are ignored The burst block transfer state diagram is shown in Figure 8 5 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary re
220. ector 6 ADCI2IFGO 2 Vectors 8 32 2 JMP ADM14 Vector 34 ADC12IFG14 2 Handler for ADC12IFG15 starts here No JMP required ADM15 MOV amp ADC12MEM15 xxx Move result flag is reset noe Other instruction needed JMP INT ADC12 Check other int pending H ADC12IFG14 ADC12IFG1 handlers go here f ADMO MOV amp ADC12MEM0 xxx Move result flag is reset Other instruction needed RETI Return 5 ADTOV mp Handle Conv time overflow RETI Return 5 ADOV T Handle ADCMEMx overflow RETI Return 5 ADC12 19 19 ADC12 Registers 19 3 ADC12 Registers The ADC12 registers are listed in Table 19 2 Table 19 2 ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTLO Read write 01A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC12 interrupt flag register ADC12IFG Read write 01A4h Reset with POR ADC12 interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC12 interrupt vector word ADC12IV Read 01A8h Reset with POR ADC12 memory 0 ADC12MEMO Read write 0140h Unchanged ADC12 memory 1 ADC12MEM 1 Read write 0142h Unchanged ADC12 memory 2 ADC12MEM2 Read write 0144h Unchanged ADC12 memory 3 ADC12MEM3 Read write 0146h Unchanged ADC12 memory 4 ADC12MEM4 Read write 0148h Unchanged ADC12 memory 5 ADC12MEM5 Read write 014Ah Unchanged ADC12 memory 6 ADC12MEM6 Read write 014Ch Unchanged ADC12 memory 7 ADC12MEM7 Read
221. ed URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 3 0 15 20 USART Peripheral Interface SPI Mode USART Registers SPI Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGO Bit 7 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFGO Bit 6 USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Bits These bits may be used by other modules See device specific datasheet 5 0 IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFG1 Bit 4 USART1 receive interrupt flag URXIFG1 is set when U1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Bits These bits may be used by other modules See device specific datasheet 3 0 USART Peripheral Interface SPI Mode 15 21 15 22 USART Peripheral Interface SPI Mode Chapter 16 OA The OA is a general purpose operational amplifier This chapter describes the OA Three OA modules are implemented the MSPAS
222. ed during the last instruction and are pending for service The interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software The SR is cleared with the exception of SCGO which is left unchanged This terminates any low power mode Because the GIE bit is cleared further interrupts are disabled The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Figure 2 6 Interrupt Processing Before After Interrupt Interrupt TOS SP TOS 2 10 System Resets Interrupts and Operating Modes System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction RETI return from an interrupt service routine The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2 7 1 The SR with all previous settings pops from the stack All previous settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 7 Return From Interrupt Before After Return From Interrupt Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine When interrupt nesting is enabled any interrupt occurring during an interru
223. ed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The CPU can address the complete address range without paging The CPU features include Ly E m E RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six most used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Word and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3 1 RISC 16 Bit CPU CPU Introduction Figure 3 1 CPU Block Diagram MDB Memory Data Bus Memory Address Bus MAB 15 0 RO PC Program Counter gt 16 Zero 2 Carry C Overflow V Negative N RISC 16 Bit CPU 3 3 CPU Registers 3 2 CPU Registers The CPU incorporates sixteen 16 bit registers RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 3 2 1 Program Counter PC The 16 bit program counter
224. ed if the timer period must be different from TBR may counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare latch TBCLO and back down to zero as shown in Figure 13 7 The period is twice the value in TBCLO Note TBCLO TBR max If TBCLO gt TBR max the counter operates as if it were configured for continuous mode It does not count down from TBR may to zero Figure 13 7 Up Down Mode TBCLO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the TBCLK divider In up down mode the TBCCRO CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer period The TBCCRO CCIFG interrupt flag is set when the timer counts from 0 1 to TBCLO and TBIFG is set when the timer completes counting down from 0001h to 0000h Figure 13 8 shows the flag set cycle Figure 13 8 Up Down Mode Flag Setting Timer Clock Timer Up Down Set TBIFG Set TBCCRO CCIFG Timer B 13 9 Timer B Operation Changing the Value of Period Register TBCLO Use of the Up Down When changing TBCLO while the timer is running and counting in the down direction and when the TBCLO load mode is immedi
225. ed load capacitance for the LFXT1 crystal This capacitance can be selected as 1 6 8 or 10 pF Additional external capacitors can be added if necessary Software can disable LFXT1 by setting OSCOFF if this signal does not source MCLK SELM z 3 or CPUOFF 1 oO AOU COUAO A Note LFXT1 Oscillator Characteristics Low frequency crystals often require hundreds of milliseconds to start up depending on the crystal It is recommended to leave the LFXT1 oscillator on when in LF mode Ultralow power oscillators such as the LFXT1 in LF mode should be guarded from noise coupling from other sources The crystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces The default value of XCAPxPF is 0 providing a crystal load capacitance of 1 pF Reliable crystal operation may not be achieved unless the crystal is provided with the proper load capacitance either by selection of XCAPxPF values or by external capacitors lt 4 2 3 XT2 Oscillator 4 6 Some devices have a second crystal oscillator XT2 XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode except XT2 does not have internal load capacitors The required load capacitance for the high frequency crystal or resonator must be provided externally
226. egardless of the state of SIFQ6EN or SIFQ7EN The state is then updated with the next instruction fetch The worst case time between state transitions in this case is 6 MCLK cycles PSM Counters Scan IF Operation The PSM has two 8 bit counters SIFCNT1 and SIFCNT2 SIFCNT1 is updated with Q1 and Q2 and SIFCNT2 is updated with Q2 The counters can be read via the SIFCNT register If the SIFCNTRST bit is set each read access will reset the counters otherwise the counters remain unchanged when read If a count event occurs during a read access the count is postponed until the end of the read access but multiple count events during a read access will increment the counters only once When SIFEN 0 both counters are held in reset SIFCNT1 can increment or decrement based on Q1 and Q2 When SIFCNT1ENM 1 SIFCNT1 decrements on a transition to a state where bit Q2 is set When SIFCNT1ENP 1 SIFCNT1 increments on a transition to a state where bit Q1 is set When both bits SIFCNT1ENM and SIFCNT1ENM are set and both bits Q1 and Q2 are set on a state transition SIFCNT1 does not increment or decrement SIFCNT2 decrements based Q2 When SIFCNT2EN 1 SIFCNT2 decrements ona transition to a state where bit Q2 is set On the first count after a reset SIFCNT2 will roll over from zero to 255 OFFh When the next state is calculated to be the same state as the current state the counters SIFCNT1 and SIFCNT2 are incremented or decremented accordi
227. en UxRXBUF is read 0 No receive errors detected 1 Receive error detected 14 24 USART Peripheral Interface UART Mode USART Registers UART Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 SEES rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is lt UXBR lt OFFFFh where UxBR UxBR1 UxBR0 Unpredictable receive and transmit timing occurs if UxBR 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 qwe ose rw rw rw rw rw rw rw rw UxMCTLx Bits Modulation bits These bits select the modulation for BRCLK 7 0 USART Peripheral Interface UART Mode 14 25 USART Registers UART Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 EES r r r r r r r f UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UxRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 KEABEKAXESRERENXERERE rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to be 7 0 moved into the transmit shift register and transmitted UTXDx Writing to the tran
228. endent 8 bit timers that can also be cascaded to form one 16 bit timer function Some uses for the Basic Timer1 include J Real time clock RTC function Software time increments Basic Timer1 features include Selectable clock source Two independent cascadable 8 bit timers Interrupt capability LCD control signal generation The Basic Timer1 block diagram is shown in Figure 11 1 A Note Basic Timerl1 Initialization The Basic Timert module registers have no initial condition These registers must be configured by user software before use Basic Timer1 Introduction Figure 11 1 Basic Timer1 Block Diagram BTCNT1 BTFRFQx Q4 Q5 Q6 Q7 BTSSEL ACLK 256 SMCLK BTCNT2 Q0 Qi Q2 Q3 Q4 Q5 Q6 Q7 Basic Timer1 f cp Set BTIFG 11 3 Basic Timer1 Introduction 11 2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8 bit timers or one 16 bit timer with the BTCTL register The BTCTL register is an 8 bit read write register Any read or write access must use byte instructions The Basic Timer1 controls the LCD frame frequency with BTCNT1 11 2 1 Basic Timer1 Counter One 11 2 2 Basic Timer1 The Basic Timer1 counter one BTCNT1 is an 8 bit timer counter directly accessible by software BTCNT1 is incremented with ACLK and provides the frame frequency for the LCD controller BTCNT 1 can be stopped
229. er interrupt request Interrupt Delay Operation 20 16 SD16 The SD16INTDLYx bits control the timing for the first interrupt service request for the corresponding channel This feature delays the interrupt request for a completed conversion by up to four conversion cycles allowing the digital filter to settle prior to generating an interrupt request The delay is applied each time the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the channel are modified SD16INTDLYx disables overflow interrupt generation for the channel for the selected number of delay cycles Interrupt requests for the delayed conversions are not generated during the delay SD16 Operation SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead The SD16IV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are SD16OVIFG CHO SD16IFG CH1 SD16IFG 16 cycles 1 CH2 SD16lIFG 14 cycles The interrupt handler for channel 2 SD16IFG shows a way to check immediately if a higher prioritized interrupt occurred during the processing of the ISR This saves nine cycles if another SD16 interrupt is pending Interru
230. er is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as O Cleared by hardware Set by hardware Condition after PUC Condition after POR vi Contents 1 ss nOn 14 Architecture nes cca nea nea ge eda egg e Rd nea LEAVE de 1 2 Flexible Clock System 00 cece 1 39 Embedded Emulation 2 ned eae Read Ga Peden das ER ho 1 amp Address Space ERI ee ed ee OE ein 1 44 FHlash HOM nhe eae ER Ier 14 2 RAM Si eee RN EM IE 1 4 8 Peripheral Modules 0 cece I 1 4 4 Special Function Registers SFRs 1 4 5 Memory Organization 0 cece tenets 2 System Resets Interrupts and Operating Modes 2 1 System Reset and Initialization 2 1 1 Brownout Reset BOR 0 00 cece cent ene 2 1 2 Device Initial Conditions After System Reset 2 2 Jntert ptS sss oes uo kk ke Rmo rb e RE AERE EE REG RE 2 2 1 Non M
231. er1 Introduction BTCTL Basic Timer1 Control Register 3 2 1 0 7 6 5 TSSEL BTHOLD BTDIV rw rw rw BTSSEL BTHOLD BTDIV BTFRFQx BTIPx Bit 7 Bit 6 Bit 5 Bits 4 3 Bits 4 rw rw rw rw rw BTCNT2 clock select This bit together with the BTDIV bit selects the clock source for BTCNT2 See the description for BTDIV Basic Timer1 Hold 0 BTCNT1 and BTCNT2 are operational 1 BTONT 1 is held if BTDIV 1 BTCNT2 is held Basic Timer1 clock divide This bit together with the BTSSEL bit selects the clock source for BTCNT2 BTSSEL BTDIV BTCNT2 Clock Source 0 0 ACLK 0 1 ACLK 256 1 0 SMCLK 1 1 ACLK 256 fj cp frequency These bits control the LCD update frequency 00 facLK 32 01 facLKk 64 10 fAcLKk 128 11 fAcLK 256 Basic Timer1 Interrupt Interval 000 2 2 001 fci 2 2 010 fcLK2 8 011 fei 2 16 100 fei 2 32 101 2 64 110 2 128 111 2 256 Basic Timer1 Basic Timer1 Introduction BTCNT1 Basic Timer1 Counter 1 7 6 5 4 3 2 1 0 BTCNT1x rw rw rw rw rw rw rw rw BTCNT1x Bits BTCNT1 register The BTCNT1 register is the count of BTCNT1 7 0 BTCNT2 Basic Timer1 Counter 2 7 6 5 4 3 2 1 0 BTCNT2x rw rw rw rw rw rw rw rw BTCNT2x Bits BTCNT2 register The BTCNT2 register is the count of BTCNT2 7 0 11 8 Basic Timer Basic Timer1 Introduction IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 BTIE Bit 7 Bits 6
232. eration UART Mode 14 2 4 USART Receive Enable The receive enable bit URXEx enables or disables data reception on URXDx as shown in Figure 14 5 Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active The receive data buffer UxRXBUF contains the character moved from the RX shift register after the character is received Figure 14 5 State Diagram of Receiver Enable No Valid Start Bit Not Completed URXEx 1 Valid Start Bit Idle State Receiver Enabled Receiver Collects Character Receive Disable Handle Interrupt Conditions URXEx 0 Character Received URXEx 0 Note Re Enabling the Receiver Setting URXEx UART Mode When the receiver is disabled URXEx 0 re enabling the receiver URXEx 1 is asynchronous to any data stream that may be present on URXDx at the time Synchronization can be performed by testing for an idle line condition before receiving a valid character see URXWIE USART Peripheral Interface UART Mode 14 9 USART Operation UART Mode 14 2 5 USART Transmit Enable When UTXExis set the UART transmitter is enabled Transmission is initiated by writing data to UxTXBUF The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty and transmission begins This proc
233. erator Prescaler Dvider UxBRx Modulator UXMCTL SP CHAR SYNC 0 LISTEN MM SYNC SSEL1 UCLKS eo OO PEV PENA Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control SWRST UTXEx TXEPT STC iir uo Clock Phase and Polarity Refer to the device specific datasheet for SFR locations e 1 SIMO TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface UART Mode 14 3 USART Operation UART Mode 14 2 USART Operation UART Mode In UART mode the USART transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USART The transmit and receive functions use the same baud rate frequency 14 2 1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit After a PUC the SWRST bitis automatically set keeping the USART in a reset condition When set the SWRST bit resets the URXIEx UTXIEx URXIFGx RXWAKE TXWAKE RXERR BRK PE OE and FE bits and sets the UTXIFGx and TXEPT bits The receive and transmit enable flags URXEx and UTXEx are not altered by SWRST Clearing SWRST releases the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12C mode to UART mode Note Initializing or Re Configuring the USART Module The required USART initialization re configuration pr
234. erial Clock Control UCLK is provided by the master on the SPI bus When MM 1 BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 15 8 When MM 0 the USART clock is provided on the UCLK pin by the master and the baud rate generator is not used and the SSELx bits are don t care The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer Figure 15 8 SPI Baud Rate Generator UCLKI ACLK SMCLK SMCLK Compare 0 or 1 hu BITCLK gt R Modulation Data Shift Register R LSB first 7 8 m0 A UxMCTL Bit Start The 16 bit value of UXBRO UxBR1 is the division factor of the USART clock source BRCLK The maximum baud rate that can be generated in master mode is BRCLK 2 The modulator in the USART baud rate generator is not used for SPI mode and is recommended to be set to 000h The UCLK frequency is given by BRCLK Baud rate UxBR with UxBR UxBR1 UxBR0 USART Peripheral Interface SP Mode 15 9 USART Operation SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART Timing for each case is shown in Figure 15 9 Figure 15 9 USAHT SPI Timing CKPH CKPL 0 0 UCLK Cycle 1 2 8 4 5 6 7 8 0 1 UCLK 1 0 UCLK 1 1 UCLK 1 X Move to UXTXBUF TX Data Shifted Out RX Sample Points 15 10
235. ers SPI Mode ME1 Module Enable Register 1 T 6 5 4 3 2 1 0 USPIEO rw 0 Bit 7 Bit 6 Bits 5 0 This bit may be used by other modules See device specific datasheet USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 Bits Bit 4 Bits 3 0 rw 0 These bits may be used by other modules See device specific datasheet USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet USART Peripheral Interface SPI Mode 15 19 USART Registers SPI Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXIEO Bit 7 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEO Bit 6 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 5 0 IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabl
236. ers to store conversion results Each ADC12MEM x is configured with an associated ADC12MCTLx control register The SREFx bits define the voltage reference and the INCHx bits select the input channel The EOS bit defines the end of sequence when a sequential conversion mode is used A sequence rolls over from ADC12MEM15 to ADC12MEMO when the EOS bit in ADC12MCTL15 is not set The CSTARTADDx bits define the first ADC12MCTLx used for any conversion If the conversion mode is single channel or repeat single channel the CSTARTADDx points to the single ADC12MCTLx to be used If the conversion mode selected is either sequence of channels or repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes The sequence continues until an EOS bit in ADC12MCTLxis processed this is the last control byte processed When conversion results are written to a selected ADC12MEM x the corresponding flag in the ADC12IFGx register is set 19 2 6 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as discussed in Table 19 1 Table 19 1 Conversion Mode Summary 19 10 CONSEQx Mode Operation 00 Single channel A single channel is converted once single conversion 01 Sequence of A sequence of channels is converted once channels 10 Repeat s
237. es 0 No 1 RISC 16 Bit CPU 3 67 Instruction Set SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 lt gt bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3 18 Status bits are not affected OSCOFF CPUOFF and GIE are not affected Figure 3 18 Destination Operand Byte Swap Example Example 15 8 7 0 MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 in R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 the swapped value to R4 BIC 0FFOOh R5 Correct the result BIC 00FFh R4 Correct the result 3 68 RISC 16 Bit CPU SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Extend Sign SXT dst Bit 7 Bit 8 Bit 15 The sign of the low byte is extended into the high byte as shown in Figure 3 19 N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h 1000 0000 SXT R7 R7 OFF80h 1111
238. eset by a system reset signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read Figure 15 11 Receive Interrupt Operation SYNC g 5 NT SYNC 1 Valid Start Bit URXS Lo Receiver Collects Character URXSEm From URXD URXIEx Interrupt Service PES T Requested URXEIER URXIFGx URXWIE RXWAKE m SWRST PUC UxRXBUF Read URXSE IRQA Character Received Figure 15 12 Receive Interrupt State Diagram SWRST 1 URXIFGx 0 URXIEx 0 Wait For Next Start SWRST 1 Receive Character USPIEx 0 USPIEx 0 Interrupt Service Started GIE 0 URXIFGx 0 USPIEx 1 and URXIEx 1 and GIE 1 and Priority Valid Receive USPIEx 1 Character Completed 15 12 USART Peripheral Interface SP Mode USART Registers SPI Mode 15 3 USART Registers SPI Mode Table 15 1 lists the registers for all devices implementing a USART module Table 15 2 applies only to devices with a second USART module USART1 Table 15 1 USAHTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071h 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL Read write 073h
239. ess is shown in Figure 14 6 When the UTXEx bit is reset the transmitter is stopped Any data moved to UxTXBUF and any active transmission of data currently in the transmit shift register prior to clearing UTXEx will continue until all data transmission is completed Figure 14 6 State Diagram of Transmitter Enable 14 10 UTXEx 0 No Data Written to Transmit Buffer Not Completed UTXEx 1 Data Written to Transmit Buffer Idle State Transmitter Enabled Transmit Disable Handle Interrupt Conditions Transmission Active UTXEx 0 Character Transmitted UTXEx 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled UTXEx 1 data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx 1 Violation can result in an erroneous transmission if data in UXTXBUF is modified as it is being moved into the TX shift register It is recommended that the transmitter be disabled UTXEx 0 only after any active transmission is complete This is indicated by a set transmitter empty bit TXEPT 1 Any data written to UXTXBUF while the transmitter is disabled will be held in the buffer but will not be moved to the transmit shift register or transmitted Once UTXEx is set the data in the transmit buffer is immediately loaded into the transmit shift register and character transmission resumes USART Peripheral Interface UART Mode
240. estination are lost The result is not defined for non BCD numbers N Set if the MSB is 1 reset otherwise Z Set if result is zero reset otherwise C Set if the result is greater than 9999 Set if the result is greater than 99 V Undefined OSCOFF CPUOFF and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC clear carry DADD R5 R3 add LSDs DADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter in the RAM byte CNT is incremented by one CLRC clear carry DADD B 1 CNT increment decimal counter or SETC DADD B 0 CNT DADC B CNT 3 36 RISC 16 Bit CPU DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Instruction Set Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF C
241. etermine the first byte loaded to the PSM output latch For example when S2 1 S1 0 the first byte loaded by the PSM will be at the address SIFPSMV 2 The next byte and further subsequent bytes are determined by the next state calculations and are calculated by the PSM based on the state table contents and the values of signals S1 and S2 p Note SIFSTOP tsm Signal Frequency The SIFSTOP tsm signal frequency must be at least a factor of 32 lower than the MCLK Otherwise unpredictable operation could occur LLLLL LA A Next State Calculation 22 22 Scan IF Bits 0 and 3 5 Q0 Q3 Q4 Q5 and if enabled by SIFQGEN and SIFQ7EN bits 6 and 7 Q6 Q7 are used together with the signals S1 and S2 to calculate the next state When SIFQ6EN 1 Q6 is used in the next state calculation When SIFQ6EN 1 and SIFQ7EN 1 Q7 is used in the next state calculation The next state is When Q7 0 the PSM state is updated by the falling edge of the SIFSTOP tsm at the end of a TSM sequence After updating the current state the PSM moves the corresponding state table entry to the output latch When Q7 1 the next state is calculated immediately without waiting for the next falling edge of SIFSTOP tsm r
242. except for the additional capture compare registers Timer A Introduction Figure 12 1 thrTimer A Block Diagram EQUO Timer Block i TASSELx IDx MCx i TACLK 00 Divider 16 bit Timer Saul ACLK 01 1 2 4 8 gt TAR la Mode EQUO i Clear SMCLK 10 i INCLK 11 Set TAIFG MEME REPRE ORENSE CCRO CCR1 CCR2 CCR3 CCR4 i 1 CCISx CMx SCS CCI4A 00 Capture 01 15 0 TA1CCR4 Timer cios moors O i VCC 11 TT 5 i EQU4 Gap i i 1 SCCI Y i 4e e Set TA1CCR4 CCIFG i OUT i Output Unit4 OUT Signal i i Timer_A 12 3 Timer A Operation 12 2 Timer A Operation The Timer A module is configured with user software The setup and operation of Timer A is discussed in the following sections 12 2 1 16 Bit Timer Counter The 16 bit timer counter register TAR increments or decrements depending on mode of operation with each rising edge of the clock signal TAR can be read or written with software Additionally the timer can generate an interrupt when it overflows TAR may be cleared by setting the TACLR bit Setting TACLR also clears the clock divider and count direction for up down mode 7l Note Modifying Timer A Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt en
243. fined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used for the source src Ad The addressing bits responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation p B Note Destination Address Destination addresses are valid anywhere in the memory map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writable For example a masked ROM location would be a valid destination address but the contents are not modifiable so the results of the instruction would be lost _________________ RISC 16 Bit CPU 3 17 Instruction Set 3 4 1 Double Operand Format 1 Instructions Figure 3 9 illustrates the double operand instruction format Figure 3 9 Double Operand Instruction Format i5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 3 11 lists and describes the double operand instructions Table 3 11 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg V N Z C MOV B src dst src dst ADD B src dst src dst dst E ADDC B src dst src dst C dst ii B SUB B src dst dst not src 1 dst ii bi P SUBC B src dst dst not src C dst i CMP B src dst dst src E
244. for B instructions and by 2 for W instructions The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction Note Use of Labels EDE TONI TOM and LEO Throughout MSP430 documentation EDE TONI TOM and LEO are used as generic labels They are only labels They have no special meaning RISC 16 Bit CPU 3 9 Addressing Modes 3 3 1 Register Mode The register mode is described in Table 3 4 Table 3 4 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 3 10 RISC 16 Bit CPU Addressing Modes 3 3 2 Indexed Mode The indexed mode is described in Table 3 5 Table 3 5 Indexed Mode Description Assembler Code Content of ROM MOV 2 R5 6 R6 MOV X R5 Y R6
245. ftware can validate the address and must reset URXWIE to continue receiving data If URXWIE remains set only address characters will be received The URXWIE bit is not modified by the USART hardware automatically For address transmission in idle line multiprocessor format a precise idle period can be generated by the USART to generate address character identifiers on UTXDx The wake up temporary WUT flag is an internal flag double buffered with the user accessible TXWAKE bit When the transmitter is loaded from UxTXBUF WUT is also loaded from TXWAKE resetting the TXWAKE bit The following procedure sends out an idle frame to indicate an address character will follow 1 Set TXWAKE then write any character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The TXWAKE value is shifted to WUT and the contents of UXTXBUF are shifted to the transmit shift register when the shift register is ready for new data This sets WUT which suppresses the start data and parity bits of a normal transmission then transmits an idle period of exactly 11 bits When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period TXWAKE is reset automatically 2 Write desired address character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The new character representing the specified address is shifted out following the address identifying idle period on UTXDx Writing the fir
246. g ADC12MEMx 8 2 11 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12 xDAT register DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput to the DAC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12 For example an application that produces a sinusoidal waveform may store the sinusoid values in a table The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution The DAC12 xCTL DAC12IFG flag is automatically cleared when the controller accesses the DAC12 xDAT register 8 17 8 3 Registers The registers are listed in Table 8 4 Table 8 4 DMA Registers Register Short Form Register Type Address Initial State control 0 DMACTLO Read write 0122h Reset with POR DMA control 1 DMACTL1 Read write 0124h Reset with POR DMA channel 0 control DMAOCTL Read write 01E0h Reset with POR DMA channel 0 source address DMAOSA Read write 01E2h Unchanged DMA channel 0 destination address DMAODA Read write 01E4h Unchanged DMA channel 0 transfer size DMAOSZ Read write 01E6h Unchanged DMA channel 1 control DMA1CTL Read write 01E
247. g this state 1 DAC on during this state TSM test cycle control This bit selects for this state which channel control bits and which DAC registers are used for a test cycle 0 The SIFTCHOXx bits select the channel and SIFDACR6 is used for the DAC 1 The SIFTCH1x bits select the channel and SIFDACR7 is used for the DAC Internal output latches enabled This bit enables the internal latches of the AFE output stage 0 Output latches disabled 1 Output latches enabled SIFCLKON SIFCA SIFEX SIFLCEN SIFCHx Bit 5 Bit 4 Bit 3 Bit 2 Scan IF Registers High frequency clock on Setting this bitturns the high frequency clock source on for this state when SIFACLK 1 even though the high frequency clock is not used for the TSM When the high frequency clock is sourced from the DCO the DCO is forced on for this state regardless ofthe MSP430 low power mode 0 High frequency clock is off for this state when SIFACLK 1 1 High frequency clock is on for this state when SIFACLK 1 TSM comparator on Setting this bit turns the comparator on for this state when SIFCAON 0 0 Comparator off during this state 1 Comparator on during this state Excitation and sample and hold This bit together with the SIFSH and SIFTEN bits enables the excitation transistor or samples the input voltage during this state SIFLCEN must be set to 1 when SIFEX 1 0 Excitation transistor disabled when SIFSH 0 and SIFTEN 1 Sampling d
248. gh for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software If the DMA registers are not modified by software when the trigger signal goes high again the transfer resumes from where it was when the trigger signal went low When DMALEVEL 1 transfer modes selected when DMADTx 0 1 2 3 are recommended because the DMAEN bit is automatically reset after the configured transfer Halting Executing Instructions for DMA Transfers 8 12 The DMAONFETCH bit controls when the CPU is halted for a DMA transfer When DMAONFETCH 0 the CPU is halted immediately and the transfer begins when a trigger is received When 1 the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the transfer begins TT Note DMAONFETCH Must Be Used When The DMA Writes To Flash If the DMA controller is used to write to flash memory the DMAONFETCH bit must be set Otherwise unpredictable operation can result S Table 8 2 DMA Trigger Operation DMAxTSELx Operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A transfer is triggered when the DMAREQ bit is set The DMAREQ bit is automatically reset when the transfer starts
249. gisters The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set In repeated burst block mode the DMAEN bit remains set after completion of the burst block transfer and no further trigger signals are required to initiate another burst block transfer Another burst block transfer begins immediately after completion of a burst block transfer In this case the transfers must be stopped by clearing the DMAEN bit or by an NMI interrupt when ENNMI is set In repeated burst block mode the CPU executes at 2096 capacity continuously until the repeated burst block transfer is stopped Figure 8 5 Burst Block Transfer State Diagram DMAEN 0 T Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAEN 0 Nd DMAREQ 0 DMAEN T Size gt DMAxSZ DMAEN 1 DMAxSZ gt T Size DMADTx 2 3 DMAxSA T SourceAdd AND DMAxSZ 0 DMAxDA T DestAdd OR DMAEN 0 DMAABORT 1 DMAABORT 0 Wait for Trigger Trigger AND DMALEVEL 0 OR i 1 AND DMALEVEL 1 2 x MCLK Trigger Hold CPU Transfer one word byte ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 Decrement DMAx
250. gth 12 11 00 16 bit TBR max OF FFFh 01 12 bit TBR maxy OFFFh 11 8 bit TBR maxy OFFh Unused Bit10 Unused TBSSELx Bits Timer_B clock source select 9 8 00 TBCLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 01 2 10 4 11 8 MCx Bits Mode control Setting MCx 00h when Timer_B is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TBCLO 10 Continuous mode the timer counts up to the value set by TBCNTLx 11 Up down mode the timer counts up to TBCLO and down to 0000h Timer B 13 21 Timer B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer B clear Setting this bit resets TBR the TBCLK divider and the count direction The TBCLR bit is automatically reset and is always read as zero TBIE Bit 1 Timer B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer B Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits Timer B register The TBR register is the count of Timer B 15 0 13 22 Timer B Timer B Registers TBCCTLx Capture Compare Control Register 15 rw 0 CMx CCISx scs CLLDx OUTMODx 14 4 3 2 1 0 0 r 0 0 0
251. hannels always stays the same DMA0 DMA1 DMAQ2 for example DMA Priority Transfer Occurs New DMA Priority DMAO DMA1 DMA2 DMA1 DMA2 DMA1 DMA2 DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 2 DMAO When the ROUNDROBIN bit is cleared the channel priority returns to the default priority DMA channel priorites are not applicable to MSP430FG43x devices 8 2 6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst block transfer Each byte word transfer requires two MCLK cycles after synchronization and one cycle of wait time after the transfer Because the DMA controller uses MCLK the DMA cycle time is dependent on the MSP430 operating mode and clock system setup Ifthe MCLK source is active but the CPU is off the DMA controller will use the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DMA controller will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer completes MCLK is turned off The maximum DMA cycle time for all operating modes is shown in Table 8 3 Table 8 3 Maximum Single Transfer Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time _ Active mode MCLK DCOCLK 4 MCLK cycles Active mode
252. he device and the SVSON bit is cleared Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly Figure 6 2 SVSON state When Changing VLDx VLDx 15 SVSON VLD vs Time tsettle Supply Voltage Supervisor 6 5 SVS Operation 6 2 4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVcc is close to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 6 3 Figure 6 3 Operating Levels for SVS and Brownout Reset Circuit Software Sets VLD gt 0 Avec Msvs IT svSstart vi X hys SVS IT MB IT ne hv Brownout out a Out Brownout megion Region 1 0 SVSOUT d BOR SVSCircuit Active d BOR 1 0 LE T RE ta SVSon Set POR 14 0 H B undefined 6 6 Supply Voltage Supervisor SVS Registers 6 3 SVS Registers The SVS registers are listed in Table 6 1 Table 6 1 SVS Registers Register SVS Control Register Short Form Register Type Address Initial State SVSCTL Read write 050h Reset with POR SVSCTL SVS Control Register 7 rw 0 VLDx PORON SVSON SVSOP SVSFG 2 1 0 rw 0 r r rw 0 Bits 7 4 Bit 3 Bit 2 Bit 1 B
253. he divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx 03Fh the divisor is 64 Flash Memory Controller 5 19 Flash Memory Registers FCTL3 Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 ro ro rw 0 rw 1 r 1 rw 0 r w 0 FWKEYx Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY 5 20 Bits 15 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Reserved Always read as 0 Emergency exit 0 No emergency exit 1 Emergency exit Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte word write or erase operation and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode ends normally 0 Unlocked 1 Locked Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx passwor
254. hen SIFCAX 1 AFE output for test channel 1 AFE output for test channel 0 Scan IF 22 43 Scan IF Registers SIFCTL3 Scan IF Control Register 3 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 r 0 r 0 r 0 r 0 SIFS2x Bits S2 source select These bits select the S2 source for the PSM when SIFCS 15 44 1 00 SIFOOUT is the S2 source 01 SIF1OUT is the S2 source 10 SIF2OUT is the S2 source 11 SIF3OUT is the S2 source SIFS1x Bits 1 source select These bits select the S1 source fro the PSM when SIFCS 13 12 1 00 SIFOOUT is the S1 source 01 SIF1OUT is the S1 source 10 SIF2OUT is the S1 source 11 SIF3OUT is the S1 source SIFIS2x Bits SIFIFGA interrupt flag source 11 10 00 SIFIFG4 is set with each count of SIFCNT2 01 SIFIFG4 is set if SIFCNT2 modulo 4 0 10 SIFIFGA4 is set if SIFCNT2 modulo 64 0 11 SIFIFG4 is set when SIFCNT2 decrements from 01h to 00 SIFIS1x Bits SIFIFG3 interrupt flag source 9 8 00 SIFIFG3 is set with each count up or down of SIFCNT1 01 SIFIFG3 is set if SIFCNT1 modulo 4 0 10 SIFIFG3 is set if SIFCNT1 modulo 64 0 11 SIFIFGS is set when SIFCNT1 rolls over from OFFh to 00h SIFCS Bit 7 Comparator output Timer A input selection 0 The SIFEX tsm signal and the comparator output are connected to the TACCRx inputs 1 The SIFxOUT outputs are connected to the TACCRx inputs selected with the
255. heral modules in place of software driven functions For example Timer A and Timer B can automatically generate PWM and capture external timing with no CPU resources Calculated branching and fast table look ups should be used in place of flag polling and long software calculations Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used 2 5 Connection of Unused Pins The correct termination of all unused pins is listed in Table 2 2 Table 2 2 Connection of Unused Pins 2 16 Pin Potential Comment AVcc DVcc AVss DVss VREF Open VeREF DVss VnEr Vengr DVss XIN DVcc XOUT Open XT2IN DVss 43x and 44x devices XT20UT Open 43x and 44x devices Px 0 to Px 7 Open Switched to port function output direction RST NMI DVcc or Vcc Pullup resistor 100 R03 DVss COMO Open TDO Open TDI Open TMS Open TCK Open Sxx Open System Resets Interrupts and Operating Modes System Resets Interrupts and Operating Modes 2 17 2 18 System Resets Interrupts and Operating Modes 3 RISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic 3 1 3 2 3 3 3 4 CPU Introduction CPU Registers ree Addressing Modes InstructioniSeb a ee uS 3 1 CPU Introduction 3 1 CPU Introduction 3 2 The CPU incorporates features specifically design
256. i com sc msp430 Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in system and external custom programming solutions as shown in Figure 5 13 The user can choose to provide data to the MSP430 through any means available UART SPI etc User developed software can receive the data and program the flash memory Since this type of solution is developed by the user it can be completely customized to fit the application needs for programming erasing or updating the flash memory Figure 5 13 User Developed Programming Solution 5 16 Host Flash Memory Commands data etc L MSP430 CPU executes user software Read write flash memory Flash Memory Controller Flash Memory Registers 5 4 Flash Memory Registers The flash memory registers are listed in Table 5 4 Table 5 4 Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read write 012Ah 09642h with PUC Flash memory control register 3 FCTL3 Read write 012Ch 09618h with PUC Interrupt Enable 1 IE1 Read write 000h Reset with PUC Flash Memory Controller 5 17 Flash Memory Registers FCTL1 Flash Memory Control Register 15 14 13 12 14 10 9 8 FRKEY Read as 096h FWKEY Must be written as 0A5h rw 0 FRKEY FWKEY BLKWRT Reserved
257. ical since they cancel in the ratio V Rese Ce Nmeas _ Yoo Nef p XOX ref re V CC Nmeas 2 Rmeas N ref R ref N meas Rmeas Pref X Nur 17 8 Comparator A Comparator A Registers 17 3 Comparator A Registers The Comparator_A registers are listed in Table 17 1 Table 17 1 Comparator A Registers Register Short Form Register Type Address Initial State Comparator A control register 1 CACTL1 Read write 059h Reset with POR Comparator_A control register 2 CACTL2 Read write 05Ah Reset with POR Comparator_A port disable CAPD Read write 05Bh Reset with POR Comparator A 17 9 Comparator A Registers CACTL1 Comparator A Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAEX Bit 7 Comparator_A exchange This bit exchanges the comparator inputs and inverts the comparator output CARSEL Bit 6 Comparator A reference select This bit selects which terminal the VcAREF is applied to When CAEX 0 0 VCAREF is applied to the terminal VCAREF S applied to the terminal When CAEX 1 0 VCAREF is applied to the terminal 1 VCAREF is applied to the terminal CAREF Bits Comparator A reference These bits select the reference voltage VcAREF 5 4 00 Internal reference off An external reference can be applied 01 025 Vcc 10 0 50 Vcc 11 Diode reference is selected CAON Bit 3 Comparator_A on This bit turns on the comparator When the comparator is off it consumes no cu
258. ied with leading zeros Clock Source Select and Divider 13 4 Timer B The timer clock TBCLK can be sourced from ACLK SMCLK or externally via TBCLK or INCLK The clock source is selected with the TBSSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The TBCLK divider is reset when TBCLR is set Timer B Operation 13 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by loading 0 to TBCLO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction from zero 13 2 3 Timer Mode Control The timer has four modes of operation as described in Table 13 1 stop up continuous and up down The operating mode is selected with the bits Table 13 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCLO 10 Continuous The timer repeatedly counts from zero to the value se lected by the TBCNTLx bits 11 Up down The timer repeatedly counts from zero up to the value of TBCLO and then back down to zero Timer B 13 5 Timer B Operation Up Mode The up mode is used ifthe timer period must be different from TBR max
259. ied with storage capacitance across Vngr and Ayss The recommended storage capacitance is a parallel combination of 10 uF and 0 1 uF capacitors From turn on a maximum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required A Note Reference Decoupling Approximately 200 uA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 uF and 0 1 uF capacitors is recommended for any reference used as shown in Figure 19 11 LLTSM External references may be supplied for VR and Vg through pins Vngr Vengr respectively ADC12 Operation 19 2 4 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of the sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following The ADC12SC bit The Timer A Output Unit 1 The Timer B Output Unit 0 The Timer B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit The SAMPCON signal controls the sample period a
260. ifferential amplifier The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits Figure 16 2 shows an example of a two opamp differential amplifier using and 1 The control register settings and are shown in Table 16 2 The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 16 3 The OAx interconnections are shown in Figure 16 3 Table 16 2 Two Opamp Differential Amplifier Control Register Settings Register OAOCTLO OAOCTL1 OA1CTLO OA1CTL1 Settings binary 00 xx xx 00 000 111 0 10 xx Xx x x xxx 1100 x Table 16 3 Two Opamp Differential Amplifier Gain Settings OA1 OAFBRx 000 001 010 011 100 101 110 111 Gain 0 1 3 1 12 3 3 4 1 3 7 15 Figure 16 2 Two Opamp Differential Amplifier V2 V1 V2 VDxR2 Vdiff Rl OA 16 7 Figure 16 3 Two Opamp Differential Amplifier Interconnections OAADCO A13 ext A13 int OAPx 00 OAPMx o1 v2 OAADC1 10 1 int ext OA10 11 9 gt 00 01 OAADC1 10 1 OAFBRx OAPx OATRBOTTOM 01 10 11 OAOOUT 16 8 OA Figure 16 4 shows an example of a three opamp differential amplifier using OA1 and OA2 The control register settings are shown in Table 16 4 The gain for the amplifier is selected by the OAFBRx bits of and OA2 The OAFBRx setti
261. ignal When the comparator output is high while SIFRSON 1 an internal latch is set Otherwise the latch is reset The latch output is written into the selected output bit with the rising edge of the SIFSTOP tsm signal as shown in Figure 22 5 Figure 22 5 Analog Front End Output Timing Comparator Output SIFRSON tsm Internal Latch SIFSTOP tsm SIFxOUT _ SIFTCHxOUT Time 22 10 Scan IF Scan IF Operation Comparator and DAC The analog input signals are converted into digital signals by the comparator and the programmable 10 bit DAC The comparator compares the selected analog signal to a reference voltage generated by the DAC If the voltage is above the reference the comparator output will be high Otherwise it will be low The comparator output can be inverted by setting SIFCAINV The comparator output is stored in the selected output bit and processed by the processing state machine to detect motion and direction The comparator and the DAC are turned on and off by SIFCA tsm signal and the SIFDAC tsm signal when needed by the timing state machine They can also be permanently enabled by setting the SIFCAON and SIFDACON bits During sensitive measurements enabling the comparator and DAC with the SIFCAON and SIFDACON bits may improve resolution Scan IF 22 11 Scan IF Operation For each input there are two DAC registers to set the reference level as listed in
262. igure 5 8 and the following example Figure 5 12 Block Write Flow Disable watchdog gt Setup flash controller P Set BLKWRT WRT 1 Write byte or word Block Border Set BLKWRT 0 Set WRT 0 LOCK 1 re enable WDT 5 12 Flash Memory Controller 11 12 L3 L4 Flash Memory Operation Write one block starting at OFOOOh Must be executed from RAM Assumes Flash is already erased 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV 32 R5 Use as write counter MOV 0F000h R6 Write pointer MOV WDTPW WDTHOLD amp WDTCTL Disable WDT BIT BUSY amp FCTL3 Test BUSY JNZ Li Loop while busy MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY BLKWRT WRT amp FCTL1 Enable block write MOV Write Value 0 R6 Write location BIT WAIT amp FCTL3 Test WAIT JZ L3 Loop while WAIT 0 INCD R6 Point to next word DEC R5 Decrement write counter JNZ L2 End of block MOV FWKEY amp FCTL1 Clear WRT BLKWRT BIT BUSY amp FCTL3 Test BUSY JNZ L4 Loop while busy MOV FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT if needed Flash Memory Controller 5 13 Flash Memory Operation 5 3 4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY 1 the CPU may not read or write to or from any flash location Otherwise an
263. illator Scan IF Registers SIFDACR x Digital To Analog Converter Registers 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw rw 7 6 5 4 3 2 1 0 DAC Data rw rw rw rw rw rw rw rw Unused Bits Unused These bits are always read as zero and when written do not affect 15 10 the DAC output DAC Data Bits 10 bit DAC data 9 0 Scan IF 22 49 Scan IF Registers SIFTSMx Scan IF Timing State Machine Registers 15 rw 0 rw 0 REPEATx SIFACLK SIFSTOP SIFDAC SIFTESTS1 SIFRSON 22 50 14 10 9 8 rw 0 0 rw 0 rw 0 Bits 15 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Scan IF 13 12 11 rw 0 rw 0 rw 0 rw 0 rw 3 1 0 7 6 5 4 2 sensn srcixon siroa rw 0 0 rw 0 rw 0 rw rw 0 rw 0 These bits together with the SIFACLK bit configure the duration of this state SIFREPEATx selects the number of clock cycles for this state The number of clock cycles SIFREPEATx 1 This bit selects the clock source for the TSM 0 The TSM clock source is the high frequency source selected by the SIFCLKEN bit 1 The TSM clock source is ACLK This bit indicates the end of the TSM sequence The duration of this state is always one high frequency clock period regardless of the SIFACLK and SIFREPEATx settings 0 TSM sequence continues with next state 1 End of TSM sequence TSM DAC on This bit turns the DAC on during this state when SIFDACON 0 0 DAC off durin
264. ime the corresponding channel s SD16MEMXx register is read This allows the complete digital filter output result to be read with two read accesses of SD16MEMx Setting or clearing SD16LSBTOG does not change SD16LSBACC until the next SD16MEMx access The positive and negative full scale data range of the digital filter s output depends on the oversampling ratio selected Figure 20 5 Used Bits of Digital Filter Output SD160SRx 256 Digital Filter 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output SD16MEMx MSB LSB SD16LSBACC 0 15 14 13 12 11 109 8 7 6154 3 21 0 SD16MEMx MSB LSB SD16LSBACC 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 501605 128 ae 20 19 18 17 16 15 14 1312 11 7 6 5 4 3 2 1 0 SD16MEMx MSB LSB SD16LSBACC 0 15 14 113 12 11 10 9 8 7 6 5 4 3 2 1 0 SD16MEMx MSB LSB SD16LSBACC 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SD160SRx 64 Digital 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Output SD16MEMx MSB LSB SD16LSBACC 0 15 14 13 12 11 410 9 8 7 6 5 4 3 2 1 0 SD16MEMx MSB LSB SD16LSBACC 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SD160SRx 32 Cae 14 131 12 0 109 8 7 6 5 4 3 2 1 0 SD16ME
265. ing 5016 start conversion 0 No conversion start 1 Start conversion SD16 group Groups SD16 channel with next higher channel Not used for the last channel 0 Not grouped 1 Grouped SD16INCTLx SD16 Channel x Input Control Register 7 5 4 3 2 1 0 rw 0 SD16 INTDLYx SD16GAINx SD16INCHx rw 0 Bits 7 6 Bits 5 3 Bits 2 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt delay generation after conversion start These bits select the delay for the first interrupt after conversion start 00 Fourth sample causes interrupt 01 Third sample causes interrupt 10 Second sample causes interrupt 11 First sample causes interrupt SD16 preamplifier gain 000 x1 001 x2 010 x4 011 x8 100 x16 101 x32 110 Reserved 111 Reserved 5016 channel differential pair input 000 001 A1 010 A2 011 100 A4 101 A5 110 A6 Temperature Sensor 111 A7 Short for PGA offset measurement SD16 20 21 SD16 Registers SD16MEMx SD16 Channel x Conversion Memory Register 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r Conversion Bits Conversion Results The SD16MEMXx register holds the upper or lower Result 15 0 16 bits of the digital filter output depending on the SD16LSBACC bit SD16PREx SD16 Channel x Preload Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16 Bits SD16 digital filter preload value Preload 7 0 Value 20 22 SD16 SD16 Registers SD16IV SD1
266. ing is not dependent on the amount of flash memory present on a device Erase cycle times are equivalent for all MSP430 devices Figure 5 4 Erase Cycle Timing i T E i EACH lt gt eA Erase Operation Active Remove Programming Voltage Programming Voltage a Erase Time Vcc Current Consumption is Increased v BUSY cec tall erase 7 t mass erase S297 ftETG lisegment erase 7 481 9 f FTG A dummy write to an address not in the range to be erased does not start the erase cycle does not affect the flash memory and is not flagged in any way This errant dummy write is ignored Interrupts are automatically disabled before a flash erase cycle After the erase cycle has completed interrupts are automatically re enabled Any interrupt that occurred during the erase cycle will have its associated flag set and will generate an interrupt request when re enabled Flash Memory Controller 5 5 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM When aflash segment erase operation is initiated from within flash memory all timing is controlled by the flash controller and the CPU is held while the erase cycle completes After the erase cycle completes the CPU resumes code execution with the instruction following the dummy write When initiating an erase cycle from within flash memory it is possible to er
267. ing with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh 5 Example MOV EDE R6 MOV 510 R10 L 1 MOV R64 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 3 38 RISC 16 Bit CPU DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Disable general interrupts DINT 0 GIE or OFFF7h AND SR S SR NOT src AND dst dst BIC 8 SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled AAA Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction
268. ingle A single channel is converted repeatedly channel 11 Repeat sequence sequence of channels is converted of channels repeatedly ADC12 Single Channel Sing ADC12 Operation le Conversion Mode A single channel is sampled and converted once The ADC result is written to the ADC12MEMXx defined by the CSTARTADDX bits Figure 19 6 shows the flow of the Single Channel Single Conversion mode When ADC12SC triggers a conversion successive conversions can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 19 6 Single Channel Single Conversion Mode CONSEQx 00 ADC120N 1 x CSTARTADDx Wait for Enable SAMPCON 4 P SAMPCON 1 As Sample Input Channel Defined in ENC ot ADC12MCTLx SAMPCON Y Si 12 x ADC12CLK M ENC ot 1 x ADC12CLK Conversion S Completed Result Stored Into x pointer to ADC12MCTLx TConversion result is unpred ADC12MEMXx ADC12IFG x is Set ictable ADC12 19 11 ADC12 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The ADC results are written to the conversion memories starting with the ADCMEMXx defined by the CSTARTADDx bits The sequence stops after the measurement of the channel with a set EOS bit Figure 19 7 shows the sequence of channels mode When ADC12SC triggers a sequence successive seq
269. inning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented Status Bits N restored from system stack Z restored from system stack C restored from system stack V restored from system stack Mode Bits OSCOFF CPUOFF and GIE are restored from system stack Example Figure 3 13 illustrates the main program interrupt Figure 3 13 Main Program Interrupt PC 6 000 4 Interrupt Request PC 2 d PC Interrupt Accepted Y gt PC 2 PC 2 is Stored PC PGi Onto Stack PC 44 PCi 2 PC 6 PCi 4 PC 8 e v PCi n 4 PCi 2 PCi n RETI y RISC 16 Bit CPU 3 57 Instruction Set RLAL W RLA B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst C lt MSB lt MSB 1 LSB41 LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 3 14 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as
270. into the MSB 1 and the LSB 1 is shifted into the LSB Figure 3 16 Destination Operand Arithmetic Right Shift Status Bits Mode Bits Example Example Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset OSCOFF CPUOFF and GIE are not affected R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 Rb 2 R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 Hold R5 temporarily using stack RRA R5 R5x0 5 R5 ADD SP R5 5 0 5 5 1 5 R5 R5 RRA R5 1 5 x R5 x 0 5 0 75 x R5 R5 The low byte of R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA B R5 R5 2 R5 operation is on low byte only High byte of R5 is reset PUSH B R5 R5x0 5 TOS RRA B SP TOS x0 520 5 x R5 x 0 5 0 25 x R5 TOS ADD B SP R5 R5x0 5 R5x0 25 0 75 x R5 R5 3 60 RISC 16 Bit CPU RRC W RRC B Syntax Operation Description Instruction Set Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C MSB MSB 1 LSB 1 gt LSB C The destination operand is shifted right one position as shown in Figure 3 17 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure 3 17 Destination
271. ion Digital I O 9 3 Digital I O Operation 9 2 4 Function Select Registers PxSEL 9 4 Digital I O Port pins are often multiplexed with other peripheral module functions See the device specific data sheet to determine pin functions Each PxSEL bit is used to select the pin function I O port or peripheral module function Bit 0 I O Function is selected for the pin Bit 1 Peripheral module function is selected for the pin Setting PxSELx 1 does not automatically set the pin direction Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function See the pin schematics in the device specific datasheet Output ACLK on P1 5 on MSP430F41x BIS B 020h amp P1SEL Select ACLK function for pin BIS B 020h amp P1DIR Set direction to output Required ERU a a aes Note P1 and P2 Interrupts Are Disabled When PxSEL 1 When any P1SELx or P2SELx bit is set the corresponding pin s interrupt function is disabled Therefore signals on these pins will not generate P1 or P2 interrupts regardless of the state of the corresponding P1IE or P2IE bit When a port pin is selected as an input to a peripheral the input signal to the peripheral is a latched representation of the signal at the device pin While PxSELx 1 the internal input signal follows the signal at the pin However if the PxSELx 0 the input to the peripheral maintains the value
272. is applied directly to the DAC12 core the DAC12 output updates immediately when new DAC 12 data is written to the DAC12_xDAT register regardless of the state of the DAC12ENC bit When DAC12LSELx 1 DAC12 data is latched and applied to the DAC12 core after new data is written to DAC12 xDAT When DAC12LSELx 2 or 3 data is latched on the rising edge from the Timer A CCR1 output or Timer B CCR 2 output respectively DAC12ENC must be set to latch the new data when DAC12LSELx gt 0 DAC12 21 5 DAC12 Operation 21 2 4 DAC12 xDAT Data Format The DAC12 supports both straight binary and 2 s compliment data formats When using straight binary data format the full scale output value is OFFFh 12 bit mode OFFh in 8 bit mode as shown in Figure 21 2 Figure 21 2 Output Voltage vs DAC12 Data 12 Bit Straight Binary Mode Output Voltage Full Scale Output DAC Data OFFFh When using 2 s compliment data format the range is shifted such that a DAC12_xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and 07FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 21 3 Figure 21 3 Output Voltage vs DAC12 Data 12 Bit 2s Compliment Mode Output Voltage Full Scale Output Mid Scale Output 0 DAC Data 0800h 2048 0 07FFh 2047 21 6 DAC12 DAC12 Operation 21 2 5 DAC12 Output Amplifier Offset Calibration
273. is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal No data are equal continue here Branch to LABEL if R5 is O TST R5 JZ LABEL RISC 16 Bit CPU 3 45 Instruction Set JGE Syntax Operation Description Status Bits Example Jump if greater or equal JGE label If N XOR V 0 then jump to label PC 2 x offset PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are setorreset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 gt R7 compare on signed numbers JGE EDE Yes R6 gt R7 asta No proceed 3 46 RISC 16 Bit CPU JL Syntax Operation Description Status Bits Example Instruction Set Jump if less JL label If N XOR V 1 then jump to label PC 2 x offset PC If N XOR V
274. is used by the slave to enable the transmit and receive operations and is provided by the SPI master When STE is low the slave operates normally When STE is high Any receive operation in progress on SIMO is halted SOMI is set to the input direction A high STE signal does not reset the USART module The STE input signal is not used in 3 pin slave mode 15 6 USART Peripheral Interface SPI Mode USART Operation SPI Mode 15 2 4 SPI Enable The SPI transmit receive enable bit USPIEx enables or disables the USART in SPI mode When USPIEx 0 the USART stops operation after the current transfer completes or immediately if no operation is active A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated Transmit Enable When USPIEx 0 any further write to UXTXBUF does not transmit Data written to UXTXBUF will begin to transmit when USPIEx 1 and the BRCLK source is active Figure 15 4 and Figure 15 5 show the transmit enable state diagrams Figure 15 4 Master Mode Transmit Enable No Data Written to Transfer Buffer USPIEx 0 Not Completed USPIEx 1 Data Written to Transmit Buffer USPIEx 1 Idle State Transmitter Enabled Transmit Disable Handle Interrupt Conditions Transmission Active USPIEx 0 Character Transmitted PUC USPIEx 0 And Last Buffer Entry Is Transmitted Figur
275. isabled 0 Odd parity 1 Even parity SPB Bit 5 Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits CHAR Bit 4 Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI Mode MM Bit 1 Multiprocessor mode select 0 Idle line multiprocessor protocol 1 Address bit multiprocessor protocol SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state 14 22 USART Peripheral Interface UART Mode USART Registers UART Mode UxTCTL USART Transmit Control Register 7 rw 0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 CKPL SSELx TXWAKE rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Clock polarity select 0 UCLKI UCLK 1 UCLKI inverted UCLK Source select These bits select the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled Transmitter wake 0 Next frame transmitted is data 1 Next frame transmitted is an address Unused Transmitter empty flag
276. isabled when SIFSH 1 and SIFTEN 0 1 Excitation transistor enabled when SIFSH 0 and SIFTEN 1 Sampling enabled when SIFSH 1 and SIFTEN 0 LC enable Setting this bit turns the damping transistor off enabling the LC oscillations during this state when SIFTEN 1 0 All SIFCHx channels are internally damped No LC oscillations 1 The selected SIFCHx channel is not internally damped The LC oscillates Input channel select These bits select the input channel to be measured or excited during this state 00 SIFCHO 01 SIFCH1 10 SIFCH2 11 SIFCH3 Scan IF 22 51 Scan IF Registers Processing State Machine Table Entry MSP430 Memory Location 7 5 4 3 2 1 0 Q7 Q7 Q5 Q4 Q3 Q2 Q1 Qo Q7 Bit 7 When Q7 1 SIFIFG6 will be set When SIFQ6EN 1 and SIFQ7EN 1 and Q7 1 the PSM proceeds to the next state immediately regardless of the SIFSTOP tsm signal and Q7 is used in the next state calculation Q6 Bit 6 When Q6 1 SIFIFG5 will be set When SIFQ6EN 1 Q6 will be used in the next state calculation Q5 Bit 5 Bit 5 of the next state Q4 Bit 4 Bit 4 of the next state Q3 Bit 3 Bit 3 of the next state Q2 Bit 2 When Q2 1 SIFCNT1 decrements if SIFCNT1ENM 1 and SIFCNT2 decrements if SIFCNT2EN 1 Q1 Bit 1 When Q1 1 SIFCNT1 increments if SIFCNT1ENP 1 Qo Bit 0 Bit 2 of the next state 22 52 Scan IF
277. ise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two 3 42 RISC 16 Bit CPU INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Instruction Set Invert destination Invert destination INV dst INV B dst NOT dst gt dst XOR OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV ZOOAEh R5 R5 000AEh INV R5 Invert R5 R5 OFF51h INC R5 R5 is now negated R5 OFF52h Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO OAEh INV B LEO Invert LEO MEM LEO 051th INC B LEO MEM LEO is negate
278. ise nested NMI interrupts may occur causing stack overflow and unpredictable operation 2 2 2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval timer mode Each maskable interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disabled by the general interrupt enable GIE bit in the status register SR Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual System Resets Interrupts and Operating Modes 2 9 System Reset and Initialization 2 2 3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set the interrupt service routine is requested Only the individual enable bit must be set for non maskable interrupts to be requested Interrupt Acceptance The interrupt latency is 6 cycles starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt service routine as shown in Figure 2 6 The interrupt logic executes the following 7 Any currently executing instruction is completed The PC which points to the next instruction is pushed onto the stack The SR is pushed onto the stack The interrupt with the highest priority is selected if multiple interrupts occurr
279. it 0 5 4 3 rw 0 rw 0 rw 0 Voltage level detect These bits turn on the SVS and select the nominal SVS threshold voltage level See the device specific datasheet for parameters 0000 SVS is off 0001 1 9V 0010 2 1V 0011 2 2V 0100 2 3V 0101 2 4 V 0110 2 5 V 0111 2 65 V 1000 2 8V 1001 2 9 V 1010 3 05 1011 3 2V 1100 3 35 V 1101 3 5V 1110 3 7V 1111 Compares external input voltage SVSIN to 1 2 V POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is turned on by setting VLDx gt 0 0 SVS is Off 1 SVS is On SVS output This bit reflects the output value of the SVS comparator 0 SVS comparator output is high 1 SVS comparator output is low SVS flag This bit indicates a low voltage condition SVSFG remains set after a low voltage condition until reset by software 0 No low voltage condition occurred 1 A low condition is present or has occurred Supply Voltage Supervisor 6 7 6 8 Supply Voltage Supervisor Chapter 7 Hardware Multiplier This chapter describes the hardware multiplier The hardware multiplier is implemented in MSP430x44x devices Topic Page 7 1 Hardware Multiplier Introduction 7 2 Hardware Multiplier Operation 7 3 Hardware Multiplier lt
280. ith POR Timer B capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer B capture compare control 3 TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read write 019Ah Reset with POR Timer_B capture compare control 5 TBCCTL5 Read write 018Ch Reset with POR Timer_B capture compare 5 TBCCR5 Read write 019Ch Reset with POR Timer B capture compare control 6 TBCCTL6 Read write 018Eh Reset with POR Timer B capture compare 6 TBCCR6 Read write 019Eh Reset with POR Timer B Interrupt Vector TBIV Read only 011Eh Reset with POR 13 20 Timer B Timer B Registers Timer B Control Register TBCTL 15 14 13 12 11 10 9 8 wen mmm ome essex rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bit15 Unused TBCLGRP Bit TBCLx group 14 13 00 Each TBCLx latch loads independently 01 TBCL1 TBCL2 TBCCR1 CLLDx bits control the update TBCL3 TBCL4 TBCCR3 CLLDx bits control the update TBCL5 TBCL6 TBCCR5 CLLDx bits control the update TBCLO independent 10 TBCL1 TBCL2 TBCL3 TBCCR1 CLLDx bits control the update TBCL4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCLO independent 11 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits Counter Len
281. ition is detected When any of these error flags are set RXERR is also set The error conditions are described in Table 14 1 Table 14 1 Receive Error Conditions Error Condition Description A framing error occurs when a low stop bit is detected When two stop bits are used only the first stop bit is checked for framing error When a framing error is detected the FE bit is set A parity error is a mismatch between the number of 1s in a character and the value of the parity bit Parity error When an address bit is included in the character it is included in the parity calculation When a parity error is detected the PE bit is set An overrun error occurs when a character is loaded Receive overrun error into UXRXBUF before the prior character has been read When an overrun occurs the OE bit is set A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit When a Break condition break condition is detected the BRK bit is set A break condition can also set the interrupt flag URXIFGx Framing error When URXEIE 0 and a framing error parity error or break condition is detected no character is received into UxRXBUF When URXEIE 1 characters are received into UXRXBUF and any applicable error bit is set When any of the FE PE OE BRK or RXERR bits is set the bit remains set until user software resets it or UXRXBUF is read 14 8 USART Peripheral Interface UART Mode USART Op
282. l any P1 pin connected to analog signals should be disabled with their associated CAPDx bit Figure 17 3 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer Voc VI ee Vo lcc loc v VI V e 0 Lo e CAPD x 1 Vss 17 2 6 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 17 4 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output selected by the CAIES bit If both the CAIE and the GIE bits are set then the CAIFG flag generates an interrupt request The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software Figure 17 4 Comparator_A Interrupt System 17 6 SET CAIFG Voc CAIE IRQ Interrupt Service Requested IRACC Interrupt Request Accepted Comparator A Comparator A Operation 17 2 7 Comparator A Used to Measure Resistive Elements The Comparator A can be optimized to precisely measure resistive elements using single slope analog to digital conversion For example temperature can be converted into digital data using a thermistor by comparing the thermistor s capacitor discharge time to that of a reference resistor as shown in Figure 17 5 A reference resister Rref is compared to Rmeas Figure 17 5 Temperature Measurement System CAO CCHB Capture I
283. l from the brownout reset circuitry Figure 2 2 Brownout Timing Set Signal for POR circuitry BOR As the V g jT level is significantly above the level of the POR circuit the BOR provides a reset for power failures where Vcc does not fall below V MIN See device specific datasheet for parameters System Resets Interrupts and Operating Modes 2 3 System Reset and Initialization 2 1 2 Device Initial Conditions After System Reset After a POR the initial MSP430 conditions are The RST NMI pin is configured in the reset mode I O pins are switched to input mode as described in the Digital I O chapter Other peripheral modules and registers are initialized as described in their respective chapters in this manual Status register SR is reset L The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location OFFFEh CPU execution begins at that address Software Initialization After a system reset user software must initialize the MSP430 for the application requirements The following must occur Initialize the SP typically to the top of RAM Initialize the watchdog to the requirements of the application Configure peripheral modules to the requirements of the application Additionally the watchdog timer oscillator fault and flash memory flags can be evaluated to determine the
284. le Instruction Set Push word onto stack Push byte onto stack PUSH src or PUSH W src PUSH B SIC SP 2SP src gt SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack a Note The System Stack Pointer The system stack pointer SP is always decremented by two independent of the byte suffix LLLLLSS S X O AO RISC 16 Bit CPU 3 55 Instruction Set RET Return from subroutine Syntax RET Operation SP PC SP 2 SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected 3 56 RISC 16 Bit CPU Instruction Set RETI Return from interrupt Syntax RETI Operation TOS SR 2 SP TOS PC SP 2 SP Description The status register is restored to the value at the beg
285. le Operand Instruction Cycles and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format ll instructions Table 3 15 Format Il Instruction Cycles and Lengths No of Cycles Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL Instruction Example Rn 1 3 4 1 SWPB R5 Rn 3 4 4 1 RRC R9 Rn 3 4 5 1 SWPB R10 N See note 4 5 2 CALL 81H X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH EDE amp EDE 4 5 5 2 SXT amp EDE f 5 a SS OS AA Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SxT with the immediate mode in the destination field Use of these in the immediate mode results in an unpredictable program operation LLLLLLL L L L AM Format lll Jump Instruction Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 3 72 RISC 16 Bit CPU Format l Double Operand Instruction Cycles and Lengths Instruction Set Table 3 16 lists the length and CPU cycles for all addressing modes of format instructions Table 3 16 Format 1 Instruction Cycles and Lengths Addressing Mode Src Rn Rn Rn N x Rn EDE amp EDE Dst Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC TONI x Rm amp TON
286. le only full rotations will be counted on the transition from state 00 to 01 or 10 using a 180 disk with the sensors 90 apart All the possible state transitions can be put into a table and this table can be translated into the corresponding state table entries for the processing state machine as shown in Table 22 8 Table 22 8 Quadrature Decoding PSM Table 22 34 Scan IF Previous Current Movement State Table Entry Quid Q6 Q2 Qi Pair Pair Error 1 1 Current Quad Byte Pair Code 00 00 No Rotation 0 0 0 0 0 000h 00 01 Turns right 1 0 0 1 0 1 003h 00 10 Turns left 1 0 1 0 1 00Ch 00 11 Error 1 0 0 1 1 049h 01 00 Turns left 0 0 0 0 0 000h 01 01 No rotation 0 0 0 0 1 001h 01 10 Error 1 0 0 1 0 048h 01 11 Turns right 0 0 0 1 1 009h 10 00 Turns right 0 0 0 0 0 000h 10 01 Error 1 0 0 0 1 041h 10 10 No rotation 0 0 0 1 0 008h 10 11 Turns left 0 0 0 1 1 009h 11 00 Error 1 0 0 0 0 040h 11 01 Turns left 0 0 0 0 1 001h 11 10 Turns right 0 0 0 1 0 008h 11 11 No rotation 0 0 0 1 1 009h Scan IF Registers 22 3 Scan IF Registers The Scan IF registers are listed in Table 22 9 Table 22 9 Scan IF Registers Register Short Form Register Type Address Initial State Scan IF debug register SIFDEBUG Read write 01BOh Unchanged Scan IF counter 1 and 2 SIFCNT Read write 01B2h Reset with POR Scan IF PSM vector SIFPSMV Read write 01B4h Unchanged Scan IF control 1 SIFCTL1 Read write 01B6h Reset with POR S
287. lexer 19 2 3 Voltage Reference 19 2 4 Sample and Conversion Timing 19 2 5 Conversion 19 2 6 ADC12 Conversion Modes 19 2 7 Using the Integrated Temperature 19 2 8 ADC12 Grounding and Noise Considerations 19 2 9 ADC12 Interrupts 0 ml 19 3 ADC12 Registers siensia animas iiia ind aa Xi Contents 20 SD16 204 5016 Introduction e erbe rne nre e tinere dae dE ob 20 2 SD16 Operation 20 2 1 ADO A eddie UR PR e ae las 20 2 2 Digital Filler edle etd de gae ii oa cce edo cud 20 2 3 Analog Input Range and PGA 20 2 4 Voltage Reference 20 2 5 Conversion Memory Registers SD16MEMx 20 2 Channel Selection es 20 2 7 Conversion Modes csse leer er Rr wens weak E EE S ERA RA 20 2 8 Conversion Operation Using Preload 20 2 9 Using the Integrated Temperature 20 2 10 Interrupt Handling e
288. ll DAC12 modules in a group update simultaneously independent of any interrupt or NMI event On the MSP430FG438x devices DAC12 0 and DAC12 1 are grouped by setting the DAC12GRP bit of DAC12 0 The DAC12GRP bit of DAC12 1 is don t care When DAC12 0 and DAC12 1 are grouped Li The DAC12 1 DAC12LSELx bits select the update trigger for both DACs The DAC12LSELx bits for both DACs must be gt 0 The DAC12ENC bits of both DACs must be set to 1 When DAC12_0 and DAC12_1 are grouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 21 6 shows latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and both DAC12_x DAC12LSELx gt 0 and either DAC12ENC 0 neither DAC12 will update Figure 21 6 DAC 12 Group Update Example Timer Trigger 21 8 DAC12_0 DAC12GRP DAC12_0 DAC12ENC TimerA_OUT1 DAC12 ODAT New Data DAC12 1DAT New Data DAC12 0 Latch Trigger DAC12 0 and DAC12 1 Updated Simultaneously a 12 0 Updated DAC12 DAC12 0 DAC12LSELx 0 AND DAC12 1 DAC12LSELx 2 DAC12 0 DAC12LSELx 2 X A Note DAC12 Settling Time The DMA controller is capable of transferring data to the DAC12 faster than the DAC12 output can settle The
289. ll scale input range for a gain of 1 is 1 2V 2 d 0 6V Refer to the device specific data sheet for full scale input specifications 20 2 4 Voltage Reference Generator The SD16 module has a built in 1 2V reference that can be used for each SD16 channel and is enabled by the SD16REFON bit When using the internal reference an external 100nF capacitor connected from Vref to AVss is recommended to reduce noise The internal reference voltage can be used off chip when SD16VMIDON 1 The buffered output can provide up to 1mA of drive When using the internal reference off chip a 470nF capacitor connected from Vpgr to AVss is required See device specific data sheet for parameters An external voltage reference can be applied to the Vref input when SD16REFON and SD16VMIDON are both reset 20 2 5 Conversion Memory Registers SD16MEMx 20 6 SD16 One SD16MEM x register is associated with each SD16 channel Conversion results for each channel are moved to the corresponding SD16MEM x register with each decimation step of the digital filter The SD16IFG bit for a given channel is set when new data is written to SD16MEMx SD16IFG is automatically cleared when SD16MEMx is read by the CPU or may be cleared with software SD16 Operation Output Data Format The output data format is configurable in two s complement or offset binary as shown in Table 20 1 The data format is selected by the SD16DF bit Table 20 1 Data
290. lly ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF CXXX XXXX PE repeat previous two instructions PET 8 times CCCC CCCC a LSB Serial communication with MSB shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry gt LSB of RECBUF XXXX XXXC ine repeat previous two instructions iss 8 times CCCC CCCC LSB MSB RISC 16 Bit CPU 3 27 Instruction Set BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst PC MOV
291. lock transfer 111 Repeated burst block transfer DMA destination increment This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer When DMADSTBYTE 1 the destination address increments decrements by one When DMADSTBYTE 0 the destination address increments decrements by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments decrements by one When DMASRCBYTE 0 the source address increments decrements by two The DMAXSA is copied into a temporary register and the temporary register is incremented or decremented DMAxSA is not incremented or decremented 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte This bit selects the destination as a byte or word 0 Word 1 Byte Bit 6 source byte This bit selects the source as a byte or word SRCBYTE 0 Word 1 Byte DMA Bit 5 DMA level This bit selects between edge sensitive and level sensitive LEVE
292. ls are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel Using SD16PREx the decimation time of the digital filter is increased by the specified number of fy clock cycles and can range from 0 to 255 Figure 20 8 shows an example using SD16PREx Figure 20 8 Conversion Delay using Preload SD160SRx 32 fM cycles 32 X 40 X 32 gt amp Conversion Delayed Conversion e Conversion Load SD16PREx Delayed Conversion SD16PREx 8 Result Preload gt applied Time The SD16PREx delay is applied to the beginning of the next conversion cycle after being written The delay is used on the first conversion after SD16SC is set and on the conversion cycle following each write to SD16PREx Following conversions are not delayed After modifying SD16PREx the next write to SD16PREx should not occur until the next conversion cycle is completed otherwise the conversion results may be incorrect The accuracy of the result for the delayed conversion cycle using SD16PREx is dependent on the length of the delay and the frequency of the analog signal being sampled For example when measuring a DC signal SD16PREx delay has no effect on the conversion result regardless of the duration The user must determine when the delayed conversion result is useful in their application Figure 20 9 shows the operation of grouped channels 0 and 1 The preload register of channel 1 is loaded with zero resulting in im
293. mediate conversion whereas the conversion cycle of channel 0 is delayed by setting SD16PREO 8 The first channel 0 conversion uses SD16PREx 8 shifting all subsequent conversions by 8 fy clock cycles SD16 20 13 SD16 Operation Figure 20 9 Start of Conversion using Preload SD160SRx 32 fm cycles K 40 x 32 x 32 gt SD16PRE0 8 Delayed Conversion Conversion Conversion 1StSample Cho 32 gt 2 x 32 gt Conversion Conversion Conversion Conversion e SD16PRE1 0 Start of 1StSample Ch1 Time Conversion When channels are grouped care must be taken when a channel or channels operate in single conversion mode or are disabled in software while the master channel remains active Each time channels in the group are re enabled and resynchronize with the master channel the preload delay for that channel will be reintroduced Figure 20 10 shows the resynchronization and preload delays for channels in a group It is recommended that SD16PREx 0 for the master channel to maintain a consistent delay between the master and remaining channels in the group when they are re enabled Figure 20 10 Preload and Channel Synchronization syncronized to master Channel NN PREO Conversion Jom PREO SD16SNGL 0 f SD16GRP 1 SD16SC Set by Ch2 Cleared by swY 4 Set by SW DE EY syncronized to master 0 pre SD16SNGL 1
294. mine if an access violation occurred ACCVIFG must be reset by software The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password When this occurs a PUC is generated immediately resetting the device 5 3 8 Programming Flash Memory Devices There are three options for programming an MSP430 flash device All options support in system programming Program via JTAG _j Program via the Bootstrap Loader Program via a custom solution Flash Memory Controller 5 15 Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port The JTAG interface requires four signals 5 signals on 20 and 28 pin devices ground and optionally and RST NMI The JTAG port is protected with a fuse Blowing the fuse completely disables the JTAG port and is not reversible Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash Based MSP430 Using the JTAG Interface at www ti com sc msp430 Programming Flash Memory via the Bootstrap loader BSL Every MSP430 flash device contains a bootstrap loader The BSL enables users to read or program the flash memory or RAM using a UART serial interface Access to the MSP430 flash memory via the BSL is protected by a 256 bit user defined password For more details see the Application report Features of the MSP430 Bootstrap Loader at www t
295. mode Table 8 1 DMA Transfer Modes DMADTx Transfer Description Mode 000 Single transfer Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made 001 Block transfer complete block is transferred with one trigger DMAEN is automatically cleared at the end of the block transfer 010 011 Burst block CPU activity is interleaved with a block transfer transfer DMAEN is automatically cleared at the end of the burst block transfer 100 Repeated Each transfer requires a trigger DMAEN remains 101 single transfer Repeated block transfer enabled A complete block is transferred with one trigger DMAEN remains enabled EE oe CPU activity is interleaved with a block transfer burst block gt transfer DMAEN remains enabled 8 5 Single Transfer 8 6 In single transfer mode each byte word transfer requires a separate trigger The single transfer state diagram is shown in Figure 8 3 The DMAxSZ register is used to define the number of transfers to be made The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAx
296. n 22 2 6 2 LC Sensor Envelope Test The envelop test measures the decay time of the oscillations after sensor excitation The oscillation envelope is created by the diodes and RC filters The DAC is used to set the reference level for the comparator and the comparator detects if the oscillation envelop is above or below the reference level The comparator and AFE outputs are connected to Timeri A5 and the capture compare registers for Timer A5 are used to time the decay of the oscillation envelope The PSM is not used for the envelope test When the sensors are connected to the individual SIFCIx inputs as shown in Figure 22 16 the comparator reference level can be adjusted for each sensor individually When all sensors are connected to the SIFCI input as shown in Figure 22 17 only one comparator reference level is set for all sensors Figure 22 16 LC Sensor Connections For The Envelope Test SIFCI ANN e SIFCI3 ANN SIFCI2 ANN SIFCI1 ANN SIFCIO SIFCH3 e9 oo eo SIFCH2 9 0 106 SIFCH1 e SIFCHO 4 eee SIFCOM 470 nF SIFVSS gt DVss Power Supply 470 nF AVss Terminals gt DVcc AVcC 22 30 Scan IF Scan IF Operation Figure 22 17 LC Sensor Connections For The Envelope Test AAA e o E
297. n TAIFG Figure 12 9 OFFFFh TACCRO TACCR1 TACCR2 Oh 12 10 Timer_A When changing TACCRO while the timer is running and counting in the down direction the timer continues its descent until it reaches zero The new period takes affect after the counter counts down to zero When the timer is counting in the up direction and the new period is greater thanor equalto the old period or greaterthan the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals See section Timer A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 12 9 the tgeaq is tdead ttimer X TACCR1 TACCR2 With tgead Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TACCRx Content of capture compare register x The TACCRx registers are not buffered They update immediately when written to Therefore any required dead time will not be maintained automatically Output Unit in Up Down Mode gt P Dead Time Output Mode 6 Toggle Set Output M
298. n SD16 has no function and is always 0 When SD16SNGL 1 for a channel in a group single conversion mode is selected A single conversion of that channel will occur synchronously when the master channel SD16SC bit is set The SD16SC bit of all channels in the group will automatically be set and cleared by SD16SC of the master channel SD16SC for each channel can also be cleared in software independently Clearing SD16SC of the master channel before the conversions are completed immediately stops conversions of all channels in the group the channels are powered down and the corresponding digital filters are turned off Values in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMXx be read prior to clearing SD16SC to avoid reading an invalid result SD16 20 11 SD16 Operation Group of Channels Continuous Conversion When SD16SNGL 0 for a channel in a group continuous conversion mode is selected Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set SD16SC bits for all grouped channel will be automatically set and cleared with the master channel s SD16SC bit SD16SC for each channel the group can also be cleared in software independently When SD16SC of a grouped channel is set by software independently of the master conversion of that channel will automatically synchronize to conversions of the master channel This ensures that conve
299. n Select Logic Excitation VSS lt AVCC VMID Gen ANC Es SIFVCC2 L Scan IF 22 7 Scan IF Operation Sample And Hold The sample and hold is used to sample the sensor voltage to be measured The sample and hold circuitry is shown in Figure 22 3 When SIFSH 1 and SIFTEN 0 the sample and hold circuitry is enabled and the excitation circuitry and mid voltage generator are disabled The sample and hold is used for resistive dividers or for other analog signals that should be sampled Up to four resistor dividers can be connected to SIFCHx and SIFCOM AVcc and SIFCOM are the common positive and negative potentials for all connected resistor dividers When SIFEX tsm 1 SIFCOM is connected to SIFVss allowing current to flow through the dividers This charges the capacitors of each sample and hold circuit to the divider voltages All resistor divider channels are sampled simultaneously When SIFEX tsm 0 the sample and hold capacitor is disconnected from the resistor divider and SIFCOM is disconnected from SIFVss After sampling each channel can be measured sequentially using the channel select logic the comparator and the DAC The selected SIFCHx input can be modeled as an RC low pass filter during the sampling time tsampije as shown below in Figure 22 4 An internal MUX on input resistance Ri sipcHx max kQ in series with capacitor CgcH SIFCHx max 7 pF is seen by the resistor
300. n Set Increment destination Increment destination INC dst INC W dst INC B dst dst 1 dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte STATUS of a process is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS 11 STATUS JEQ OVFL RISC 16 Bit CPU 3 41 Instruction Set INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Setif result is negative reset if positive Z Setif dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Setif dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherw
301. n arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10 R5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 OAh 0F6h iau No carry 3 22 RISC 16 Bit CPU ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W srcJdst ADDC B src dst SIC dst C dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven words above the pointer in R13 ADD B R13
302. n operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared MOV BLOCK1 R6 BLOCK start address R6 MOV ZBLOCK2 R7 BLOCK start address in R7 L 1 R6 0 R7 Are Words equal R6 increments JNZ ERROR No branch to ERROR INCD R7 Increment R7 pointer DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the program continues at the label EQUAL CMPB EDE TONI MEM EDE MEM TONI JEQ EQUAL YES JUMP 3 34 RISC 16 Bit CPU DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W
303. n triggered further trigger signals occurring during the block transfer are ignored The block transfer state diagram is shown in Figure 8 4 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set During a block transfer the CPU is halted until the complete block has been transferred The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete CPU execution resumes with its previous state after the block transfer is complete In repeated block transfer mode the DMAEN bit remains set after completion of the block transfer The next trigger after the completion of a repeated block transfer triggers another block transfer Figure 8 4 Block Transfer State Diagram DMAEN 0 DMAEN 0 DMAREQ 0 T Size gt DMAxSZ DMAEN S d DMAxSZ gt T Size 0 od pesi DMAxSA T Sourc
304. n when SIFQ6EN 1 0 Q7 is not used to determine the next PSM state 1 Q7 is used to determine the next PSM state SIFQ6EN Bit10 Q7 enable This bit enables Q6 for the next PSM state calculation 0 Q6 is not used to determine the next PSM state 1 Q6 is used to determine the next PSM state 22 46 Scan IF SIFDIV3Bx SIFDIV3Ax SIFDIV2x SIFDIV1x Scan IF Registers Bits TSM start trigger ACLK divider These bits together with the SIFDIV3Ax bits 9 7 select the ACLK division rate for the TSM start trigger Bits TSM start trigger ACLK divider These bits together with the SIFDIV3Bx bits 6 4 select the ACLK division rate for the TSM start trigger The division rate is SIFDIV3Bx 000 001 010 011 100 101 110 111 000 2 10 14 18 22 26 30 001 6 18 30 42 54 66 78 90 010 10 30 50 70 90 110 130 150 SIFDIV3Ax 011 100 14 18 42 54 70 90 98 126 126 162 154 198 182 234 210 270 101 22 66 110 154 198 242 286 330 110 26 78 130 182 234 286 338 390 111 30 90 150 210 270 330 390 450 Bits TSM ACLK divider These bits select the ACLK division for the TSM 3 2 00 A 01 2 10 4 11 8 Bi 1 0 00 A 01 2 10 4 11 8 Scan IF its TSM SMCLK divider These bits select the SMCLK division for the TSM 22 47 Scan IF Registers SIFCTL5 Scan IF Control Register 5 15 14 13 12 11 10 9 8 rw 0 rw 0 7 6 1 0 0 0 rw 0 rw 1
305. nchanged Scan IF TSM 17 SIFTSM17 Read write 01F2h Unchanged Scan IF TSM 18 SIFTSM18 Read write 01F4h Unchanged Scan IF TSM 19 SIFTSM19 Read write 01F6h Unchanged Scan IF TSM 20 SIFTSM20 Read write 01F8h Unchanged Scan IF TSM 21 SIFTSM21 Read write 01FAh Unchanged Scan IF TSM 22 SIFTSM22 Read write 01FCh Unchanged Scan IF TSM 23 SIFTSM23 Read write 01FEh Unchanged Scan IF 22 35 Scan IF Registers SIFDEBUG Scan IF Debug Register Write Mode 15 14 13 12 11 10 9 8 w WwW Ww Ww Ww 7 6 5 4 3 2 1 0 meu Ww Ww Ww Ww Reserved Bits Reserved Must be written as zero 15 2 SIFDEBUGx Bits SIFDEBUG register mode Writing these bits selects the read mode of the 1 0 SIFDEBUG register SIFDEBUG must be written with Mov instructions only 00 When read SIFDEBUG shows the last address read by the PSM 01 When read SIFDEBUG shows the value of the TSM state pointer and the PSM bits Q7 QO 10 When read SIFDEBUG shows the contents of the current SIFTSMx register 11 Whenread SIFDEBUG shows the currently selected DAC register and its contents SIFDEBUG Scan IF Debug Register Read Mode After 00h Is Written 15 14 13 12 11 10 9 8 Last Address Read by PSM r r r r r r r r 7 6 5 4 3 2 1 0 Last Address Read By PSM r r r r r r r r Last PSM Bits When SIFDEBUG is read after 00 has been written to it SIFDEBUG shows 15 0 the last address read by the PSM 22 36 Scan IF Scan IF Registers SIFDEB
306. nd start of conversion When SAMPCON is high sampling is active The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMPCON is high sampling is active The high to low SAMPCON transition starts the conversion after synchronization with ADC12CLK See Figure 19 3 Figure 19 3 Extended Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete a SHI SAMPCON 13 x ADC12CLK sample gt lt tconvert X synci ADC12 19 7 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP 1 The SHI signal is used to trigger the sampling timer The SHTOx and SHT 1x bits in ADC12CTLO control the interval of the sampling timer that defines the SAMPCON sample period tsample The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample The total sampling time is tsample plus tsync See Figure 19 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHTOx selects the sampling time for ADC12MCTLO to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15 Figure 19
307. ne CALL dst dst tmp dst is evaluated and stored SP 2 SP PC SP PC updated to TOS tmp dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is stored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CALL CALL CALL CALL CALL CALL CALL EXEC Callonlabel EXEC or immediate address e g 0A4h SP 2 2 SP PC 2 SP PC PC EXEC Call on the address contained in EXEC SP 2 SP PC 2 5 SP X PC gt PC Indirect address amp EXEC Call on the address contained in absolute address EXEC SP 2 SP PC 2 5 SP X 0 5 PC Indirect address R5 Call on the address contained in R5 SP 2 5 SP 2 gt SP R5 5 PC Indirect R5 R5 Call on the address contained in the word pointed to by R5 SP 2 SP 2 gt SP R5 gt PC Indirect indirect R5 R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address in a table pointed to by R5 SP 2 2 SP 2 gt SP R5 PC Indirect indirect R5 with autoincrement X R5 Call on the address contained in the address pointed
308. nel is selected The voltage on SVSIN is compared to an internal level of approximately 1 2 V 6 2 2 SVS Comparator Operation A low voltage condition exists when AVcc drops below the selected threshold or when the external voltage drops below its 1 2 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device reset function of the SVS If PORON 1 a POR is generated when SVSFG is set If PORON 0 a low voltage condition sets SVSFG but does not generate a POR The SVSFG bit is latched This allows user software to determine if a low voltage condition occurred previously The SVSFG bit must be reset by user software If the low voltage condition is still present when SVSFG is reset it will be immediately set again by the SVS 6 4 Supply Voltage Supervisor SVS Operation 6 2 3 Changing the VLDx Bits When the VLDx bits are changed two settling delays are implemented to allows the SVS circuitry to settle During each delay the SVS will not set SVSFG The delays tq SvSon and tsettle are shown in Figure 6 2 The ta SVSon delay takes affect when VLDx is changed from zero to any non zero value and is a approximately 50 us The tserje delay takes affect when the VLDx bits change from any non zero value to any other non zero value and is a maximum of 12 us See the device specific datasheet for the delay parameters During the delays the SVS will not flag a low voltage condition or reset t
309. nerator Block Diagram ACLK MCLK SMCLK SMCLK FSSELx Reset Divider 1 64 Flash Timing Generator BUSY WAIT The flash timing generator can be sourced from ACLK SMCLK or MCLK The selected clock source should be divided using the FNx bits to meet the frequency requirements for feq If the fiera frequency deviates from the specification during the write or erase operation the result of the write or erase may be unpredictable or the flash memory may be stressed above the limits of reliable operation 5 4 Flash Memory Controller Flash Memory Operation 5 3 2 Erasing Flash Memory The erased level of a flash memory bit is 1 Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle The smallest amount of flash that can be erased is a segment There are three erase modes selected with the ERASE and MERAS bits listed in Table 5 1 Table 5 1 Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 Erase all flash memory main and information segments Any erase is initiated by a dummy write into the address range to be erased The dummy write starts the flash timing generator and the erase operation Figure 5 4 shows the erase cycle timing The BUSY bitis setimmediately after the dummy write and remains set throughout the erase cycle BUSY MERAS and ERASE are automatically cleared when the cycle completes The erase cycle tim
310. ng to Q1 and Q2 atthe state transition For example if the current state is 05h and Q2 is set and if the next state is calculated to be 05h the transition from state 05h to 05h will decrement SIFCNT2 if SIFCNT2EN 1 Scan IF 22 23 Scan IF Operation Simplest State Machine Figure 22 12 shows the simplest state machine that can be realized with the PSM The following code shows the corresponding state table and the PSM initialization Figure 22 12 Simplest PSM State Diagram 120 amp S2 0 State 00 00000000 51 1 amp S2 0 120 amp S2 1 120 amp S2 0 120 amp S2 0 120 amp S2 0 00000000 51 1 amp S2 1 S1 1 amp S2 0 120 amp S2 1 120 amp S2 1 00000000 S1 1 amp S2 0 S1 1 amp S2 0 S1 1 amp S2 1 S1 1 amp S2 1 00000010 S1 1 amp S2 1 Simplest State Machine Example SIMPLEST_PSM db 000h State 00 State Table Index 0 db 000h State 01 State Table Index 1 db 000h State 10 State Table Index 2 db 002h State 11 State Table Index 3 PSM INIT MOV SIMPLEST PSM amp SIFPSMV MOV HSIFS20 amp SIFCTL3 S1 S2 source MOV HSIFCNTIENP SIFCNTIENM amp SIFCTLA4 Q7 and Q6 disabled for next state calc Increment and decrement of SIFCNT1 enabled Init PSM vector 22 24 Scan IF Scan IF Operation Ifthe PSM is in state 01 of the simplest state machine and the PSM has loaded the corresponding byte at index 01h of the state t
311. ngs for both and OA2 must be equal The gain settings are shown in Table 16 5 The OAx interconnections are shown in Figure 16 5 Table 16 4 Three Opamp Differential Amplifier Control Register Settings Register OAOCTLO OAOCTL1 OA1CTLO OA1CTL1 OA2CTLO OA2CTL1 Settings binary 00 xx xx 00 xxx 001 0 x 00 xx xx 00 000 1110 x 11 11 xx xx xxx 1100 x Table 16 5 Three Opamp Differential Amplifier Gain Settings OAQ0 OA2 OAFBRx Gain 000 001 010 011 100 101 110 111 0 1 3 1 1 2 8 3 4 1 3 7 15 Figure 16 4 Three Opamp Differential Amplifier v2 V1 V2 VDxR2 Ri OA 16 9 Figure 16 5 Three Opamp Differential Amplifier OAx Interconnections OAPx OAADCO A14 ext A14 int OAOOUT OAPMx OAADC1 OAFBRx 1 A5 int ext E 00 01 OAOTAP 10 11 01 OAADC1 10 OAFBRx OAORBOTTOM OA2RBOTTOM 00 ot 10 11 OA1OUT 16 10 OA 16 3 OA Registers Table 16 6 Register Control Register 0 Control Register 1 OA1 Control Register 0 OA1 Control Register 1 OA2 Control Register 0 OA2 Control Register 1 The OA registers are listed in Table 16 6 Short Form OAOCTLO OAOCTL1 OA1CTLO OA1CTL1 OA2CTLO OA2CTL1 Register Type Address Read write Read write Read write Read write Read write Read write 0 1 0C2h OC3h 0C4h
312. nput Of Timer A re 0 25xVCC The MSP430 resources used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor I O set to output high Vcc to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal of the capacitor The terminal is connected to a reference level for example 0 25 x Vcc The output filter should be used to minimize switching noise D DD CAOUT used to gate Timer A CCI1B capturing capacitor discharge time More than one resistive element can be measured Additional elements are connected to CAO with available I O pins and switched to high impedance when not being measured Comparator A 17 7 Comparator A Operation The thermistor measurement is based on a ratiometric conversion principle The ratio of two capacitor discharge times is calculated as shown in Figure 17 6 Figure 17 6 Timing for Temperature Measurement Systems Vc Voc 0 25 x Vec Phase I Phase Il Phase Ill Phase IV t gt Charge Discharge Charge Discharge tref X tmeas The Vcc voltage and the capacitor value should remain constant during the conversion but are not crit
313. nsfer A transfer is triggered when the DAC12 OCTL DAC12IFG flag is set The DAC12_0CTL DAC12IFG flag is automatically cleared when the transfer starts If the DAC12 OCTL DAC12IE bit is set the DAC12 DAC12IFG flag will not trigger a transfer A transfer is triggered by an ADC12IFGx flag When single channel conversions are performed the corresponding ADC12IF Gx is the trigger When sequences are used the ADC12IFGx for the last conversion in the sequence is the trigger A transfer is triggered when the conversion is completed and the ADC12IFGx is set Setting the ADC12IFGx with software will not trigger a transfer All ADC121FGx flags are automatically reset when the associated ADC12MEM x register is accessed by the DMA controller A transfer is triggered when the TACCRO CCIFG flag is set The TACCRO CCIFG flag is automatically reset when the transfer starts If the TACCRO CCIE bit is set the TACCRO CCIFG flag will not trigger transfer A transfer is triggered when the TBCCRO CCIFG flag is set The TBCCRO CCIFG flag is automatically reset when the transfer starts If the TBCCRO CCIE bit is set the TBCCRO CCIFG flag will not trigger transfer A transfer is triggered when the URXIFG1 flag is set URXIFG1 is automatically reset when the transfer starts If URXIE1 is set the URXIFG1 flag will not trigger a transfer A transfer is triggered when the UTXIFG1 flag is set UTXIFG1 is automatically reset when the transfer starts If UTXIE1
314. nt interrupt capability for receive and transmit Figure 15 1 shows the USART when configured for SPI mode 15 2 USART Peripheral Interface SPI Mode USART Introduction SPI Mode Figure 15 1 USART Block Diagram SPI Mode SWRST USPIEx URXEIE URXWIE Receive Control SYNC 1 URXIFGx FE PE OE BRK LISTEN RXERR RXWAKE PENA 1 URXD SSEL1 SSELO SP CHAR UCLKS i UCLKI Baud Rate Generator 0 STE 4 71 SMCLK Prescaler Dvider UxBRx SMCLK Modulator UXMCTL UTXD SP CHAR Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control SWRST USPIEx TXEPT STC ii ds Clock Phase and Polarity Refer to the device specific datasheet for SFR locations PEV PENA TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface SPI Mode 15 3 USART Operation SPI Mode 15 2 USART Operation SPI Mode In SPI mode serial data is transmitted and received by multiple devices using a shared clock provided by the master An additional pin STE is provided as to enable a device to receive and transmit data and is controlled by the master Three or four signals are used for SPI data exchange SIMO Slave in master out Master mode SIMO is the data output line Slave mode SIMO is the data input line SOMI Slave out master in Master mode SOMI is the data input line Slave mode SOMI is the data output line
315. nterrupt vector table is mapped into the the upper 16 words of Flash ROM address space with the highest priority interrupt vector at the highest Flash ROM word address OFFFEh RAM starts at 0200h The end address of RAM depends on the amount of RAM present and varies by device RAM can be used for both code and data Address Space 1 4 3 Peripheral Modules Peripheral modules are mapped into the address space The address space from 0100 to 01FFh is reserved for 16 bit peripheral modules These modules should be accessed with word instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always 0 The address space from 010h to OFFh is reservedfor 8 bit peripheral modules These modules should be accessed with byte instructions Read access of byte modules using word instructions results in unpredictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as shown in Figure 1 3
316. nthe continuous mode the timer repeatedly counts up to OFFFFh and restarts from zero as shown in Figure 12 4 The capture compare register TACCRO works the same way as the other capture compare registers Figure 12 4 Continuous Mode OFFFFh Oh The TAIFG interrupt flag is set when the timer counts from OFFFFh to zero Figure 12 5 shows the flag set cycle Figure 12 5 Continuous Mode Flag Setting Timer y FFFEn X on y 7 Oh Set TAIFG Timer A 12 7 Timer A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TACCRx register in the interrupt service routine Figure 12 6 shows two separate time intervals ty and t4 being added to the capture compare registers In this usage the time interval is controlled by hardware not software without impact from interrupt latency Up to three Timer or five Timer A5 independent time intervals or output frequencies can be generated using capture compare registers Figure 12 6 Continuous Mode Time Intervals 12 8 Timer A OFFFFH M TACCROa TACCR1b TACCR1c TACCROb TROU TACCRia TACCRId Time intervals can be produced with other modes as well where TACCRO is used as the period register Their handling is more complex
317. o the inverting input of the OAx providing a non inverting amplifier configuration with a programmable gain of 1 OAxTAP ratio The OAxTAP ratio is selected by the OAFBRx bits If the OAFBRXx bits 0 the gain is unity The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANx bits are don t care The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits In this mode the output of the OAx is connected to and Rgottom is connected to an analog multiplexer that multiplexes the INON IN1N or the output of one of the remaining OAs selected with the OANx bits The OAxTAP signal is connected to the inverting input of the OAx providing an inverting amplifier with a gain of OAXTAP ratio The OAxTAP ratio is selected by the OAFBRxX bits The non inverting input is selected by the OAPx bits The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTLO bits Differential Amplifier Mode 16 6 OA This mode allows internal routing of the OA signals for a two opamp or three opamp instrumentation amplifier Figure 16 2 shows a two opamp configuration with and OA1 In this mode the output of the OAx is connected to by routing through another in the Inverting PGA mode Rgottom is unconnected providing a unity gain buffer This buffer is combined with one or two remaining OAx to form the d
318. ocess is 1 Set SWRST BIS B SWRST amp UxCTL 2 3 4 5 Initialize all USART registers with SWRST 1 including UxCTL Enable USART module via the MEx SFRs URXEx and or UTXEx Clear SWRST via software BIC B SWRST amp UxCTL Se WH Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx Failure to follow this process may result in unpredictable USART behavior 14 2 2 Character Format The UART character format shown in Figure 14 2 consists of a start bit seven or eight data bits an even odd no parity bit an address bit address bit mode and one or two stop bits The bit period is defined by the selected clock source and setup of the baud rate registers Figure 14 2 Character Format Mark ST DO D6 sp sP 2 Space 2nd Stop Bit SP 1 Parity Bit PENA 1 Address Bit MM 1 8th Data Bit CHAR 1 Optional Bit Condition 14 4 USART Peripheral Interface UART Mode USART Operation UART Mode 14 2 3 Asynchronous Communication Formats When two devices communicate asynchronously the idle line format is used for the protocol When three or more devices communicate the USART supports the idle line and address bit multiprocessor communication formats Idle Line Multiprocessor Format When MM 0 the idle line multiprocessor format is selected Blocks of data are separated by an idle time on the transmit or receive lines as shown in
319. ode 2 Toggle Reset EQUI EQUI EQUI EQUI Interrupt Events EQUO EQUO EQU2 EQU2 EQU2 EQU2 Timer A Operation 12 2 4 Capture Compare Blocks Capture Mode Three or five identical capture compare blocks TACCRx are present in Timer A Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture occurs The timer value is copied into the TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bitto synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 12 10 Figure 12 10 Capture Signal SCS 1 CC
320. of the input signal at the device pin before the PxSELx bit was reset Digital I O Operation 9 2 5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability configured with the PxIFG PxIE and PxIES registers All P1 pins source a single interrupt vector and all P2 pins source a different single interrupt vector The PxIFG register can be tested to determine the source of a P1 or P2 interrupt Interrupt Flag Registers P1IFG P2IFG Each PxIFGx bit is the interrupt flag for its corresponding I O pin and is set when the selected input signal edge occurs at the pin All PxIFGx interrupt flags request an interrupt when their corresponding bit and the GIE bit are set Each PxIFG flag must be reset with software Software can also set each PxIFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is executed the set PxIFGx flag generates another interrupt This ensures that each transition is acknowledged D DEUS Note PxIFG Flags When Changing PxOUT or PxDIR Writing to P1OUT P1DIR P2OUT or P2DIR can result in setting the corresponding 1 or P2IFG flags 1
321. on is always decaying because of energy losses but it decays faster when the damping material on the disk is within the field of the LC sensor as shown in Figure 22 14 The LC oscillations can be measured with the oscillation test or the envelope test Figure 22 14 LC Sensor Oscillations 22 28 Undamped Envelope Scan IF Damped Scan IF Operation 22 2 6 1 LC Sensor Oscillation Test The oscillation test tests if the amplitude of the oscillation after sensor excitation is above a reference level The DAC is used to set the reference level for the comparator and the comparator detects if the LC sensor oscillations are above or below the reference level If the oscillations are above the reference level the comparator will output a pulse train corresponding to the oscillations and the selected AFE output bit will 1 The measurementtiming and reference level depend on the sensors and the system and should be chosen such that the difference between the damped and the un damped amplitude is maximized Figure 22 15 shows the connections for the oscillation test Figure 22 15 LC Sensor Connections For The Oscillation Test SIFCI SIFCI3 SIFCI2 SIFCH SIFCIO SIFCH3 E MAL 96 SIFCH2 E MAL E MAL SIFCH1 SIFCHO SIFCOM 470 nF SIFVSS gt DVss Power Supply 470nF AVss Terminals gt DVoc 22 29 Scan IF Operatio
322. onnections Figure 18 11 4 Mux LCD Example DIGIT15 DIGIT1 Pinout and Connections Display Memory Connections 210 3 2 1 0 490 Pins LCD Pinout B PIN COM0COM1COM2COM3 MAB OgFh a bj c n 30 Digit 16 SO a id le ig 1 OogEh a3 b c h figs 28 Digit 15 S1 4 2 1h 1c 1b 1a 09Dh a b C h f 0 e d 26 Digit 14 lt gt 2f iol 4 i Ph Ps 2a ooch a h fig 24 Digit 13 S4 gt 5 3g 3f ooBn 2 b C h f g e d 22 Digit 12 55 4 6 3h 3c 3b 3a 09Ah a b f g e d 20 Digit 11 bad d e ME NN 5 18 Digit 10 S7 gt 8 4h 4c 4b 4a 099h Ns S8 4 9 5d 5g Of 098h aj b c h fg e d 16 Digit 9 S9 10 5h 5c 5b 5 9097h alb h f g e d 14 Digit8 ace E ja igi 511 12 6h 6c 6 ogeh Es 12 Digit7 S12 4 13 7d 7g 7f doeh a b c h 10 Digit 6 513 4 14 7h 7 7b 7 a b c h fig e d 8 Digit 5 aa ee 092 igi S15 16 8h 8 hT p B Digit4 516 17 9d 9e 9 9 093 cj h fjgielfd 4 Digit 3 S17 lt 18 9h 9 9 o92hfalblctlht tfigitetld 2 Digit 2 S18 19 10d 10e 10g 10f bes S19 20 10h 10c 10b 10a Oihajbjc h fjg 0 Digiti S20 21 ttd tte 119 11 psu eem S21 4 22 iih 1c tib tia Parallel S22 4 23 12d 12e 12g 12 Serial 12a 523 lt 24 12h 12c 12b
323. or BIC W src dst BIC B src dst NOT src AND dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO RISC 16 Bit CPU 3 25 Instruction Set BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Set bits in destination Set bits in destination BIS src dst or BIS W src dst BIS B src dst src OR dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM 3 26 RISC 16 Bit CPU BITLW BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Test bits in destination Test bits in destination BIT src dst or BIT W src dst src AND dst The source and destination operands are logica
324. other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 a a ee ee rw 0 Bits These bits may be used by other modules See device specific datasheet 7 1 WDTIFG Bit 0 Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1 may be used for other modules itis recommended to clear WDTIFG by using BIS BOr BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Watchdog Timer Watchdog Timer 10 9 10 10 Watchdog Timer Watchdog Timer Chapter 11 Basic Timer1 The Basic Timer1 module is two independent cascadable 8 bit timers This chapter describes the Basic Timer1 Basic Timer1 is implemented in all MSP430x4xx devices Topic Page 11 1 Basic Timer1 Introduction 11 2 11 2 Basic Timer1 Operation 11 4 11 3 Basic Timer Registers 11 6 Basic Timer1 Introduction 11 1 Basic Timer1 Introduction 11 2 Basic Timer1 The Basic Timer1 supplies LCD timing and low frequency time intervals The Basic Timer1 is two indep
325. p SIFS1x SIFOOUT 00 SIF1OUT g 01 SIFZOUT m P SIFO1 SIFSOUT m SIFO2 When SIFCS 1 the SIFEX tsm signal and the comparator output can be selected as inputs to different Timert A5 capture compare registers This can be used to measure the time between excitation of a sensor and the last oscillation that passes through the comparator or to perform a slope A D conversion When SIFCS 20 the output bits SIFXOUT can be selected as inputs to Timer1 A5 with the SIFS1x and SIFS2x bits This can be used to measure the duty cycle of SIFXOUT Scan IF 22 13 Scan IF Operation 22 2 2 Scan IF Timing State Machine 22 14 Scan IF The TSM is a sequential state machine that cycles through the SIFTSMx registers and controls the analog front end and sensor excitation automatically with no CPU intervention The states are defined within a 24 x 16 bit memory SIFTSMO to SIFTSM23 The SIFEN bit enables the TSM When SIFEN 0 the ACLK input divider the TSM start flip flop and the TSM outputs are reset and the internal oscillator is stopped The TSM block diagram is shown in Figure 22 8 The TSM begins at SIFTSMO and ends when the TSM encounters a SIFTSMx state with a set SIFTSTOP bit When state with a set SIFSTOP bit is reached the state counter is reset to zero and state processing stops State processing re starts at SIFTSMO with the next start condition when SIFTSMRP 0 or immediately when SIFTSMRP
326. position as shown in Figure 3 15 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 3 15 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example 0 uncus Byte 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5 x 2 C R5 The input P11N 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information gt Carry RLC R5 Carry POin 1 LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C Mem LEO Note RLC and RLC B Substitution The assembler does not recognize the instruction RLC RS5 It must be substituted by ADDC R5 2 R5 RISC 16 Bit CPU 3 59 Instruction Set RRA W RRA B Syntax Operation Description Rotate right arithmetically Rotate right arithmetically RRA dst or RRA W dst RRA B dst MSB MSB MSB MSB 1 LSB 1 LSB LSB gt C The destination operand is shifted right one position as shown in Figure 3 16 The MSB is shifted into the MSB the MSB is shifted
327. process may result in unpredictable USART behavior USART Peripheral Interface SPI Mode USART Operation SPI Mode 15 2 2 Master Mode Figure 15 2 USAHT Master and External Slave MASTER Receive Buffer UXRXBUF Transmit Buffer UXTXBUF Receive Shift Register Data Shift Register DSR LSB SCLK MSP430 USART COMMON SPI Figure 15 2 shows the USART as a master in both 3 pin and 4 pin configurations The USART initiates data transfer when data is moved to the transmit data buffer UXTXBUF The UxTXBUF data is moved to the TX shift register when the TX shift register is empty initiating data transfer on SIMO starting with the most significant bit Data on SOMI is shifted into the receive shift register on the opposite clock edge starting with the most significant bit When the character is received the receive data is moved from the RX shift register to the received data buffer UXRXBUF and the receive interrupt flag URXIFGx is set indicating the RX TX operation is complete A set transmit interrupt flag UTXIFGx indicates that data has moved from UxTXBUF to the TX shift register and UXTXBUF is ready for new data It does not indicate RX TX completion To receive data into the USART in master mode data must be written to UxTXBUF because receive and transmit operations operate concurrently Four Pin SPI Master Mode In 4 pin master mode STE is used to prevent conflicts with another master The master
328. pt can be generated by three sources An edge on the RST NMI pin when configured in NMI mode An oscillator fault occurs An access violation to the flash memory At power up the RST NMI pin is configured in the reset mode The function of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in the reset vector OFFFEh Ifthe RST NMI pin is configured by user software to the NMI function a signal edge selected by the NMIES bit generates an NMI interrupt if the NMIIE bit is set The RST NMI flag NMIFG is also set Note Holding RST NMI Low When configured in the NMI mode a signal generating an NMI event should not hold the RST NMI pin low If a PUC occurs from a different source while the NMI signal is low the device will be held in the reset state because a PUC changes the RST NMI pin to the reset function o M Note Modifying NMIES When NMI mode is selected and the NMIES bit is changed an NMI can be generated depending on the actual level at the RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated LLLLLLL O
329. pt handler for SD16 INT SD16 Enter Interrupt Service Routine 6 ADD amp SD16IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADMO Vector 4 CH 0 SD16IFG 2 JMP ADM1 Vector 6 CH 1 SD16IFG 2 Handler for CH 2 SD16IFG starts here No JMP required ADM2 MOV amp SD16MEM2 xxx Move result flag is reset Other instruction needed JMP INT SD16 Check other int pending 2 i Remaining Handlers 1 MOV amp 5 16 1 Move result flag is reset Other instruction needed RETI Return 5 ADMO MOV amp SD16MEMO xxx Move result flag is reset RETI Return 5 i ADOV s Handle SD16MEMx overflow RETI Return 5 SD16 20 17 SD16 Registers 20 3 SD16 Registers The SD16 registers are listed in Table 20 3 Table 20 3 SD16 Registers Register Short Form Register Type Address Initial State SD16 Control SD16CTL Read write 0100h Reset with PUC 5016 Interrupt Vector SD16IV Read write 0110h Reset with PUC SD16 Channel 0 Control SD16CCTLO Read write 0102h Reset with PUC SD16 Channel 0 Conversion Memory SD16MEMO Read write 0112h Reset with PUC SD16 Channel 0 Input Control SD16INCTLO Read write OBOh Reset with PUC SD16 Channel 0 Preload SD16PREO Read write OB8h Reset with PUC SD16 Channel 1 Control SD16CCTL1 Read write 0104h Reset with PUC 5016 Channel 1 Conversion Memory SD16MEM 1 Read write 0114h Reset with PUC
330. pt service routine will interrupt the routine regardless of the interrupt priorities System Resets Interrupts and Operating Modes 2 11 System Reset and Initialization 2 2 4 Interrupt Vectors The interrupt vectors and the power up starting address are located in the address range OFFFFh OFFEOh as described in Table 2 1 A vector is programmed by the user with the 16 bit address of the corresponding interrupt service routine See the device specific data sheet for the complete interrupt vector list Table 2 1 Interrupt Sources Flags and Vectors INTERRUPT SOURCE Power up external reset watchdog flash password NMI oscillator fault flash memory access violation device specific device specific device specific Watchdog timer device specific device specific device specific device specific device specific device specific device specific device specific device specific device specific INTERRUPT SYSTEM FLAG INTERRUPT WDTIFG KEYV Reset NMIIFG non maskable OFIFG non maskable ACCVIFG non maskable WDTIFG maskable 2 2 5 Special Function Registers SFRs 2 12 Some module enable bits interrupt enable bits and interrupt flags are located in the SFRs The SFRs are located in the lower address range and are WORD ADDRESS OFFFEh OFFFCh OFFFAh OFFF8h OFFF6h OFFF4h OFFF2h OFFFOh OFFEEh OFFECh OFFEAh OFFE8h OFFE6h OFFE4h OFFE2h OFFEOh PRIORITY 15 highest gt
331. r four modes of operation listed in Table 20 2 The SD16SNGL and SD16GRP bits for each channel selects the conversion mode Table 20 2 Conversion Mode Summary SD16SNGL SD16GRPT Mode Operation 1 0 Single channel A single channel is Single conversion converted once 0 0 Single channel A single channel is Continuous conversion converted continuously 1 1 Group of channels A group of channels is Single conversion converted once 0 1 Group of channels A group of channels is Continuous conversion converted continuously t A channel is grouped and is the master channel of the group when SD16GRP 0 if SD16GRP for the prior channel s is set SD16 20 9 SD16 Operation Single Channel Single Conversion Setting the SD16SC bit of a channel initiates one conversion on that channel when SD16SNGL 1 and it is not grouped with any other channels The SD16SC bit will automatically be cleared after conversion completion Clearing SD16SC before the conversion is completed immediately stops conversion of the selected channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMXx be read prior to clearing SD16SC to avoid reading an invalid result Single Channel Continuous Conversion When SD16SNGL 0 continuous conversion mode is selected Conversion of the selected channel will begin when SD16S
332. r output FLL Clock Module 4 9 Buffered Clock Output 4 2 10 FLL Fail Safe Operation The module incorporates oscillator fault fail safe feature This feature detects an oscillator fault for LFXT1 DCO and XT2 as shown in Figure 4 4 The available fault conditions are Low frequency oscillator fault LFOF for LFXT1 in LF mode LJ High frequency oscillator fault XT1OF for LFXT1 HF mode J High frequency oscillator fault XT2OF for XT2 DCO fault flag for the DCO The crystal oscillator fault bits LFOF XT1OF and XT2OF are set if the corresponding crystal oscillator is turned on and not operating properly The fault bits remain set as long as the fault condition exists and automatically cleared if the enabled oscillators function normally During a LFXT1crystal failure no ACLK signal is generated and the continues to count down to zero in an attempt to lock ACLK and MCLK Dx N 1 The DCO tap moves to the lowest position SCFI1 7 to SCF11 3 are cleared and the DCOF is set A DCOF is also generated if the N multiplier value is set too high for the selected DCO frequency range resulting the DCO tap to move to the highest position SCFI1 7 to SCFI1 3 are set The DCOF is cleared automatically if the DCO tap is not in the lowest or the highest positions The OFIFG oscillator fault interrupt flag is set and latched at POR or when an oscillator fault LFOF XT1OF XT2OF or DCOF set is detected When O
333. r the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample input signal 1 SAMPCON signal is sourced from the sampling timer Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC12 clock divider 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 7 8 ADC12 19 23 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx 4 3 00 ADC120SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeat sequence of channels ADC12 Bit 0 ADC12 busy This bit indicates an active sample or conversion operation BUSY 0 No operation is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers E 13 12 11 10 9 8 P m ro rw rw rw rw 7 6 5 4 3 2 amp rw rw rw rw AW n Conversion Bits The 12 bit conversion results are right justified Bit 11 is the MSB Bits 15 12 Results 15 0 are always 0 Writing to the conversion memory registers will corrupt the results 19 24 ADC12 ADC12 Registers ADC12MCTLx ADC12 Conversion Memory Control Registers mE Modifiable only when ENC 0 EOS Bit 7 End of sequence Indicates the last conversion in a sequence 0 Not end of sequence 1 End of sequence SREFx Bits Select reference 6 4 000 VR AVc
334. racter 0 No interrupt pending 1 Interrupt pending Bits These bits may be used by other modules See device specific datasheet 3 0 USART Peripheral Interface UART Mode 14 29 14 30 USART Peripheral Interface UART Mode Chapter 15 USART Peripheral Interface SPI Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode USARTO is implemented on the MSP430x42x and MSP430x43x devices In addition to USARTO the MSP430x44x devices implement second identical USART module USART1 Topic Page 15 1 USART Introduction SPI Mode 15 2 USART Operation SPI Mode 15 3 USART Registers SPI Mode 15 1 USART Introduction SPI Mode 15 1 USART Introduction SPI Mode In synchronous mode the USART connects the MSP430 to an external System via three or four pins SIMO SOMI UCLK and STE SPI mode is selected when the SYNC bit is set and the 12C bit is cleared SPI mode features include 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode L LD L L L Independe
335. re The WDTCNT is controlled and time intervals selected through the watchdog timer control register WDTCTL The WDTONT can be sourced from ACLK or SMCLK The clock source is selected with the WDTSSEL bit 10 2 2 Watchdog Mode After a PUC condition the WDT module is configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC A PUC resets the WDT to its default condition and configures the RST NMI pin to reset mode 10 2 3 Interval Timer Mode 10 4 Setting the WDTTMSEL bitto 1 selects the interval timer mode This mode can be used to provide periodic interrupts In interval timer mode the WDTIFG flag is set at the expiration of the selected time interval A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged When the WDTIE bit and the GIE bit are set the WDTIFG flag requests an interrupt The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced or may be reset by software The interrupt vector address in interval timer mode is different from that in watchdog mode 7 1 Note Modifying the Watch
336. re compare 0 TimerO A3 capture compare 0 Timer A capture compare control 1 TimerO A3 capture compare control 1 Timer A capture compare 1 TimerO A3 capture compare 1 Timer A capture compare control 2 TimerO A3 capture compare control 2 Timer A capture compare 2 TimerO A3 capture compare 2 Timer A interrupt vector TimerO A3 interrupt vector Table 12 4 Timer A5 Registers Register Timer1 A5 control Timer1 A5 counter Timer1 A5 capture compare control 0 Timer1 A5 capture compare 0 Timer1 A5 capture compare control 1 Timer1 A5 capture compare 1 Timer1 A5 capture compare control 2 Timer1 A5 capture compare 2 Timer1 A5 capture compare control 3 Timer1 A5 capture compare 3 Timer1 A5 capture compare control 4 Timer1 A5 capture compare 4 Timer1 A5 Interrupt Vector Short Form TACTL TAOCTL TAR TAOR TACCTLO TAOCCTL TACCRO TAOCCRO TACCTL1 TAOCCTL1 TACCR1 TAOCCR1 TACCTL2 TAOCCTL2 TACCR2 TAOCCR2 TAIV TAOIV Short Form TA1CTL TA1R TA1CCTLO TA1CCRO TA1CCTL1 TA1CCR1 TA1CCTL2 TA1CCR2 TA1CCTL3 TA1CCR3 TA1CCTL4 TA1CCR4 TA1IV Register Type Read write Read write Read write Read write Read write Read write Read write Read write Read only Register Type Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read only Address 0160h 0170h 0162h 0172h 0164h 0174h 0166h
337. red 1 The status bit is set Status Bits V N Z C All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode x RN is used the word that follows contains the address information RISC 16 Bit CPU 3 19 Instruction Set 3 4 8 Jumps Figure 3 11 shows the conditional jump instruction format Figure 3 11 Jump Instruction Format 15 i4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 3 13 lists and describes the jump instructions Table 3 13 Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to 512 words relative to the PC value at the jump instruction The 10 bit program counter offset is treated as a signed 10 bit value that is doubled and added to the program counter PCnew 2 PCoftset x 2 3 20 RISC 16 Bit CPU ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Exampl
338. rflow TAIFG OCh Reserved OEh Reserved Lowest t Timeri A5 only Timer A 12 23 12 24 Timer A Chapter 13 Timer B Timer Bisa 16 bittimer counter with multiple capture compare registers This chapter describes Timer B Timer B3 three capture compare registers is implemented in MSP430x43x devices Timer B7 seven capture compare registers is implemented in MSP430x44x Topic Page 13 1 Timer B Introduction 13 2 Timer B Operation 13 3 Timer B Registers 13 1 Timer B Introduction 13 1 Timer B Introduction Timer B is a 16 bit timer counter with three or seven capture compare registers Timer support multiple capture compares PWM outputs and interval timing Timer B also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer B features include Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Three or seven configurable capture compare registers Configurable outputs with PWM capability Double buffered compare latches with synchronized loading L L Biz L Interrupt vector register for fast decoding of all Timer B interrupts The block diagram of Timer B is shown in Figure 13 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the pro
339. rge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 19 2 Analog Multiplexer R 100 Ohm ADC12MCTLx 0 3 e ESD Protection Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Voc to GND This parasitic current occurs if the input voltage is nearthe transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The P6SELx bits provide the ability to disable the port pin input and output buffers P6 0 and P6 1 configured for analog input BIS B 3h amp P6SEL P6 1 and P6 0 ADC12 function ADC12 19 5 ADC12 Operation 19 2 3 Voltage Reference Generator 19 6 ADC12 The ADC12 module contains a built in voltage reference with two selectable voltage levels 1 5 V and 2 5 V Either of these reference voltages may be used internally and externally on pin VREF Setting REFON 1 enables the internal reference When REF2 5V 1 the internal reference is 2 5 V the reference is 1 5 V when REF2 5V 0 The reference can be turned off to save power when not in use For proper operation the internal voltage reference generator must be suppl
340. rite is unpredictable A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the write completes the CPU resumes code execution with the instruction following the write The byte word write timing is shown in Figure 5 7 Figure 5 7 Byte Word Write Timing VEM 2 EN 4 gt lt Pr gt Generate Programming Operation Active Remove Programming Voltage Programming Voltage Programming Time Vc c Current Consumption is Increased lt BUSY hoseuns Shenr t Word Write 35 f FTG When a byte word write is executed from RAM the CPU continues to execute code from RAM The BUSY bit must be zero before the CPU accesses flash again otherwise an access violation occurs ACCVIFG is set and the write result is unpredictable 5 8 Flash Memory Controller Initiating a Byte Word Write from Within Flash Memory Flash Memory Operation The flow to initiate a byte word write from flash is shown in Figure 5 8 Figure 5 8 Initiating a Byte Word Write from Flash Disable watchdog Setup flash controller and set WRT 1 Write byte or word Set WRT 0 LOCK 1 re enable watchdog Byte word write from flash Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE WDTPW WDTHOLD amp WDTCT
341. rrent The reference circuitry is enabled or disabled independently 0 Off 1 On CAIES Bit 2 Comparator_A interrupt edge select 0 Rising edge 1 Falling edge CAIE Bit 1 Comparator_A interrupt enable 0 Disabled 1 Enabled CAIFG Bit 0 The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending 17 10 Comparator A Comparator A Registers CACTL2 Comparator A Control Register 2 T 6 5 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits 7 4 P2CA1 Bit 3 P2CAO0 Bit 2 CAF Bit 1 CAOUT Bit 0 rw 0 rw 0 Unused Pin to CA1 This bit selects the CA1 pin function 0 The pin is not connected to CA1 1 The pin is connected to CA1 Pin to CAO This bit selects the CAO pin function 0 The pin is not connected to CAO 1 The pin is connected to CAO Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect CAPD Comparator A Port Disable Register rw 0 CAPDx Bits 7 0 CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPDO rw 0 rw 0 rw 0 rw 0 rw 0 Comparator_A port disable These bits individually disable the input buffer for the pins of the port associated with Comparator A For example the CAPDx bits can be used to individually enable or disable each P1 x pin buffer CAPDO disables P1 0 CAPD1 disables P1 1 etc 0 The input buffer is enabled 1 The inpu
342. rrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 0 OFIFG 4 16 Bits 7 2 Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC b instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules See device specific datasheet FLL Clock Module 5 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller Topic Page 5 1 Flash Memory Introduction 5 2 Flash Memory Segmentation 5 3 ElashiMemoryiOperationg 5 4 Flash Memory Registers 5 1 Flash Memory Introduction 5 1 Flash Memory Introduction The MSP430 flash memory is bit byte and word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The controller has three registers a timing generator and a voltage generator to supply program and erase voltages MSP430 flash memory features include Internal programming voltage generation Lj Bit byte or word programmable Ultralow power operation Segment erase and mass erase The block diagram of the flash memory and controller is shown in Figur
343. rsions for grouped channels are always synchronous to the master Clearing SD16SC of the master channel immediately stops conversions of all channels in the group the channels are powered down and the corresponding digital filters are turned off Values in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMXx be read prior to clearing SD16SC to avoid reading an invalid result Figure 20 7 shows grouped channel operation for three SD16 channels Two channels are configured for single conversion mode SD16SNGL 1 and the master channel is operating in continuous conversion mode SD16SNGL 0 Note that conversions of all channels in the group occur synchronously to the master channel regardless of when each SD16SC bit is set using software Figure 20 7 Grouped Channel Operation syncronized to master Channel 0 SD16SNGL 1 SD16GRP 1 SD16SC Set by Ch2 Auto clear 4 Set by SW Auto clear RTT gt syncronized to master Channel 7771 2 Conversion Com Conversion con _____ SD16SNGL 0 SD16GRP 1 SD16SC Setby Ch2 Cleared by SW Set by SW Cleared by Ch2 Tor E a Conversion Conversion Conversion oom SD16SNGL 0 SD16GRP 0 1 SD16SC 4 Set by SW Cleared by SW Y Vor in O Result written to SD16MEMx Time 20 12 SD16 SD16 Operation 20 2 8 Conversion Operation Using Preload When multiple channe
344. rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 rw 0 rw rw rw rw rw mu Modifiable only when DAC12ENC 0 DAC120PS Bit 15 DAC12 SREFx DAC12 RES DAC12 LSELx DAC12 CALON DAC12IR Bits 14 13 Bit 12 Bits 11 10 Bit 9 Bit 8 DAC12 output select This bit selects the pins for the DAC12 x outputs on the MSP430FG43x devices This bit is reserved on all other devices 0 DAC12 0 output on P6 6 DAC12 1 ouput on P6 7 1 DAC12 0 output on VeREF DAC12 1 output on P5 1 DAC12 select reference voltage 00 VREF 01 VREF 10 Vener 11 VeREF DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 load select Selects the load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12latch loads when DAC12 xDAT written DAC12ENC is ignored 01 DAC12 latch loads when DAC12 xDAT written or when grouped when all DAC12 xDAT registers in the group have been written 10 Rising edge of Timer A OUT1 TA1 11 Rising edge of Timer B OUT2 TB2 DAC12 calibration on This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes 0 Calibration is not active 1 Initiate calibration calibration in progress DAC12 input range This bit sets the reference input and voltage output range 0 DAC12 full scale output 3x reference voltage 1 DAC12 full scale output 1x reference voltage
345. s contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Valid only for source operand The substitute for destination operand is O Rd plus second instruction INCD Rd Length One or two words Operation Comment Example MOV R10 0 R11 Before Address Register Space OFF18h OFF16h OFF14h OFF12h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h Address Space Pc Register OFF18h OFF16h OFF14h OFF12h R10 OFA34h 11 010A8h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 3 8 Figure 3 8 Operand Fetch Operation Instruction Address RISC 16 Bit CPU 3 15 Addressing Modes 3 3 7 Immediate Mode The immediate mode is described in Table 3 10 Table 3 10 Immediate Mode Description Assembler Code Content of ROM MOV 45 MOV PC X PC 45 X PC Length Two or three words It is one word less if a constant of CG1 or CG2 can be used Operation Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents
346. segment information to temporary mem Ry 0000 Obch Oagd Oyfe write a g d y f of Digit n LowByte Ry Oagd Oyfe 0000 Obch write b h of Digit n HighByte LCD in 3mux has 9 segments per digit word table required for displayed characters Load segment information to temporary mem Ry 0000 Obch Oagd Oyfe Ry 0000 bchO agd0 yfeo Ry 000b choa gdOy fe00 Ry 00bc h0ag dOyf e000 Ry Obch Oagd Oyfe 0000 write y f e of Digit n 1 LowByte Ry Oyfe 0000 Obch Oagd write b c h a g d of Digit 1 HighByte displays 0 displays 1 displays F LCD Controller Operation 18 2 9 4 Mux Mode In 3 mux mode each MSP430 segment pin drives four LCD segments and all four common lines COMO COM1 COM2 and are used Figure 18 10 shows some example 4 mux waveforms Figure 18 10 Example 4 Mux Waveforms COM3 COMO COM2 fframe V5 arr fon v2 Anm COMO COM2 COM3 V2 V4 SP1 SP2 SP1 SP Segment Pin SP2 Resulting Voltage for Segment e COM1 SP1 Segment Is Off V1 L Resulting Voltage for Segment 1 5 2 OV Segment Is On LCD Controller 18 15 LCD Controller Operation Figure 18 11 shows an example 4 mux LCD pin out LCD to MSP430 connections and the resulting segment mapping This is only an example Segment mapping in a user s application depends on the LCD pin out and on the MSP430 to LCD c
347. since the sum of the old TACCRx data and the new period can be higher than the TACCRO value When the previous TACCRx value plus t is greater than the TACCRO data the TACCRO value must be subtracted to obtain the correct time interval Timer A Operation Up Down Mode The up down mode is used if the timer period must be different from OFFFFh counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare register TACCRO and back down to zero as shown in Figure 12 7 The period is twice the value in TACCRO Figure 12 7 Up Down Mode OFFFFh TACCRO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the TACLK divider In up down mode the TACCRO CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCRO CCIFG interrupt flag is set when the timer counts from TACCRO 1 to TACCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Figure 12 8 shows the flag set cycle Figure 12 8 Up Down Mode Flag Setting Up Down Set TAIFG a Set CCIFG Timer A 12 9 Timer A Operation Changing the Period Register TACCRO Use of the Up Dow
348. smit data buffer clears UTXIFGx The MSB of UxTXBUF is not used for 7 bit data and is reset 14 26 USART Peripheral Interface UART Mode USART Registers UART Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 UTXEO URXEO rw 0 Bit 7 Bit 6 Bits 5 0 USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 UTXE1 URXE1 Bits 7 6 Bit 5 Bit 4 Bits 3 0 rw 0 rw 0 These bits may be used by other modules See device specific datasheet USART1 transmit enable This bit enables the transmitter for USART1 0 Module not enabled 1 Module enabled USART1 receive enable This bit enables the receiver for USART1 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet USART Peripheral Interface UART Mode 14 27 USART Registers UART Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXIEO Bit 7 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEO Bit 6 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled
349. source of the reset 2 4 System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2 3 The nearer a module istothe CPU NMIRS the higher the priority Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously There are three types of interrupts System reset L Non maskable NMI Maskable Figure 2 3 Interrupt Priority Priority High PUC OSCfault Flash ACCV Circuit Reset NMI WDT Security Key Nu Flash Security Key N 7 KZ NZ NA Ne B lt MAB 5LSBs gt System Resets Interrupts and Operating Modes 2 5 System Reset and Initialization 2 21 Non Maskable Interrupts NMI Reset NMI Pin Non maskable NMI interrupts are not masked by the general interrupt enable bit GIE but are enabled by individual interrupt enable bits ACCVIE NMIIE OFIE When a NMI interrupt is accepted all NMI interrupt enable bits are automatically reset Program execution begins at the address stored in the non maskable interrupt vector OFFFCh User software must set the required NMI interrupt enable bits for the interrupt to be re enabled The block diagram for NMI sources is shown in Figure 2 4 A non maskable NMI interru
350. ss tera annene eee 203 SD16 R6glslerS bere ete bee eb bb eot S Ps he ER des 21 DAC12 21 33 DAGCI2 Introd lO i i adus are eodera denos FR ATE 212 DAC12 Operation 21 2 1 DAC 12 COM a taeda eiie S qa Uus tp demde a e qur dieta 21 2 2 DAC12 Reference seeslslls esses 21 2 3 Updating the DAC12 Voltage Output 21 2 4 DAC12 xDAT Data Format 21 2 5 DAC12 Output Amplifier Offset Calibration 21 2 6 Grouping Multiple DAC12 Modules 21 2 7 DAC12 Interrupts siaina ninaa 21 9 DAC12 Registers ne othe denk de es aede ded eda ded 22 Scan lE toca wate Uses uer aD E where 22 4 Scan IF Introduction zerria na aa 22 2 Scan IF Operation 2s oscar Ie ai Tr A 22 2 1 Scan IF Analog Front eee eens 22 2 2 Scan IF Timing State Machine 22 2 3 Scan IF Processing State Machine 22 2 4 Scan IF Debug Register 22 25 ScanlF Interrupts nin
351. ssuring the clock to the WDT cannot be disabled while in watchdog mode This means the low power modes may be affected by the choice for the WDT clock For example if ACLK is the WDT clock source LPM4 will not be available because the WDT will prevent ACLK from being disabled Also if ACLK or SMCLK fail while sourcing the WDT the WDT clock source is automatically switched to MCLK In this case if MCLK is sourced from a crystal and the crystal has failed the fail safe feature will activate the DCO and use it as the source for MCLK When the WDT module is used in interval timer mode there is no fail safe feature for the clock source Watchdog Timer Watchdog Timer 10 5 Watchdog Timer Operation 10 2 6 Operation in Low Power Modes The MSP430 devices have several low power modes Different clock signals are available in different low power modes The requirements of the user s application and the type of clocking used determine how the WDT should be configured For example the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low power mode 3 because SMCLK is not active in LPM3 and the WDT would not function In this case with the WDT SMCLK would remain enabled increasing the current consumption of LPM3 When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT reducing power consumption 10 2 7 Software Examples 10 6 Any write oper
352. st don t care character to UxTXBUF is necessary in order to shift the TXWAKE bit to WUT and generate an idle line condition This data is discarded and does not appear on UTXDx USART Peripheral Interface UART Mode USART Operation UART Mode Address Bit Multiprocessor Format When MM 1 the address bit multiprocessor format is selected Each processed character contains an extra bit used as an address indicator shown in Figure 14 4 The first character in a block of characters carries a set address bit which indicates that the character is an address The USART RXWAKE bit is set when a received character is a valid address character and is transferred to UXRXBUF The URXWIE bit is used to control data reception in the address bit multiprocessor format If URXWIE is set data characters address bit 0 are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated When a character containing a set address bit is received the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIFGx All applicable error status flags are also set If an address is received user software must reset URXWIE to continue receiving data If URXWIE remains set only address characters address bit 1 will be received The URXWIE bit is not modified by the USART hardware automatically Figure 14 4 Address Bit Multiprocessor Format Blocks of Characters M ee T_TT_IL_ LI
353. ster file eliminates working file bottleneck Compact core design reduces power consumption and cost Optimized for modern high level programming B Only 27 core instructions and seven addressing modes B Extensive vectored interrupt capability In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System 1 2 Introduction The clock system is designed specifically for battery powered applications A low frequency auxiliary clock ACLK is driven directly from a common 32 kHz watch crystal The ACLK can be used for a background real time clock self wake up function An integrated high speed digitally controlled oscillator DCO can source the master clock MCLK used by the CPU and high speed peripherals By design the DCO is active and stable in less than 6 us MSP430 based solutions effectively use the high performance 16 bit RISC CPU in very short bursts Low frequency auxiliary clock Ultralow power stand by mode High speed master clock High performance signal processing Embedded Emulation Figure 1 1 MSP430 Architecture ACLK Flash ROM RAM SMCLK TAA MAB 16 Bit RISC CPU 16 Bit JTAG Debug MDB 16 Bit us MDB 8 Bit 3 1 e M 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no
354. t buffer is disabled A 17 11 17 12 Comparator A Chapter 18 LCD Controller The LCD controller drives static 2 mux 3 mux or 4 mux LCDs This chapter describes LCD controller The LCD controller is implemented on all MSP430x4xx devices Topic Page 18 1 LCD Controller Introduction 18 2 LCD Controller 18 4 18 3 LCD Controller Registers 18 18 18 1 LCD Controller Introduction 18 1 LCD Controller Introduction 18 2 The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically The MSP430 LCD controller can support static 2 mux 3 mux and 4 mux LCDs The LCD controller features are Display memory Automatic signal generation Configurable frame frequency Blinking capability L L Support for 4 types of LCDs B Static B 2 mux 1 2 bias B 3 mux 1 3 bias B 4 mux 1 3 bias The LCD controller block diagram is shown in Figure 18 1 F7 1 Note Max LCD Segment Count The maximum number of segment lines available differs with device 41x device SO to S23 42x device 50 to S31 43 device SO to S31 80 pin package or SO to S39 100 pin package 44x device SO to S39 Cd LCD Controller LCD Controller Introduction Figure 18 1 LCD Controller Block Diagram S39
355. t is generated if the corresponding SD16IE bit and the GIE bit are set The SD16 overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read SD16IV Interrupt Vector Generator All SD16 interrupt sources are prioritized and combined to source a single interrupt vector SD16lV is used to determine which enabled SD16 interrupt source requested an interrupt The highest priority SD16 interrupt request that is enabled generates a number in the SD16IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled SD16 interrupts do not affect the SD16IV value Any access read or write of the SD161V register has no effect on the SD16OVIFG or SD16IFG flags The SD16IFG flags are reset by reading the associated SD16MEMx register or by clearing the flags in software SD160OVIFG bits can only be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the SD16OVIFG and one or more SD16IFG interrupts are pending when the interrupt service routine accesses the SD16IV register the SD16OVIFG interrupt condition is serviced first and the corresponding flag s must be cleared in software After the RETI instruction of the interrupt service routine is executed the highest priority SD16IFG pending generates anoth
356. tch is constructed as a T switch to suppress distortion in the signal path n Note Comparator Input Connection When the comparator is on the input terminals should be connected to a signal power or ground Otherwise floating levels may cause unexpected interrupts and increased current consumption Cd The CAEX bit controls the input multiplexer exchanging which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the output signal from the comparator is inverted This allows the user to determine or compensate for the comparator input offset voltage 17 4 Comparator_A 17 2 3 Output Filter Comparator A Operation The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an on chip RC filter Any comparator output oscillates if the voltage difference across the input terminals is small Internal and external parasitic effects and cross coupling on and between signal lines power supply lines and other parts of the system are responsible for this behavior as shown in Figure 17 2 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation
357. tem Interrupts 8 2 8 DMA Controller lt 8 2 9 Using the I2C Module with the DMA Controller 8 2 10 Using ADC12 with the DMA 8 2 11 Using DAC12 With the DMA Controller 8 3 DMA amp lt 9 Digital oce rre deca eos een be ee eee eee eee 9 4 Digital I O Introduction mn 9 2 Digital l O Operation 0 tenet I 9 2 1 Input Register PXIN 00 c ee ees 9 2 2 Output Registers PXOUT 02 cece 9 2 3 Direction Registers PXDIR eee eee 9 2 4 Function Select Registers PXSEL 9 25 2 Interrupts eee eens 9 2 6 Configuring Unused Port Pins 9 33 Digital O Registers 0 cece mn 10 Watchdog Timer Watchdog Timer 10 1 Watchdog Timer Introduction 0 0 cece eee 10 2 Watchdog Timer Operation 0 00 cee n 10 2 1 Watchdog Timer Counter 10 2 2 Watchdog Modo ehe rer RR ERN RUE EIERE 10 2 3 Interval Timer Mode suseeuseeeseeeseeeeee eee 10 2 4
358. the pin regardless of the state of the associated P6SELx and P6DIRx bits 21 4 DAC12 DAC12 Operation 21 2 2 DAC12 Reference The reference for the DAC12 is configured to use either an external reference voltage or the internal 1 5 V 2 5 V reference from the ADC12 module with the DAC12SREFx bits When DAC12SREFx 0 1 the Vngr signal is used as the reference and when DAC12SREFx 2 3 the Vener signalis used as the reference To use the ADC12 internal reference it must be enabled and configured via the applicable ADC12 control bits see the ADC 12 chapter Once the ADC12 reference is configured the reference voltage appears on the Vref signal DAC12 Reference Input and Voltage Output Buffers The reference input and voltage output buffers of the DAC12 can be configured for optimized settling time vs power consumption Eight combinations are selected using the DAC12AMPx bits In the low low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 21 2 3 Updating the DAC12 Voltage Output The DAC12 xDAT register can be connected directly to the DAC12 core or double buffered The trigger for updating the DAC1 2 voltage output is selected with the DAC12LSELx bits When DAC12LSELx 0 the data latch is transparent and the DAC12_xDAT register
359. the receive start edge detection feature The recommended usage of the receive start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low power mode operation The ultra fast turn on of the DCO allows character reception after the start edge detection When URXSE URXIEx and GIE are set and a start edge occurs on URXDx the internal signal URXS will be set When URXS is set a receive interrupt request is generated but URXIFGx is not set User software in the receive interrupt service routine can test URXIFGx to determine the source of the interrupt When URXIFGx 0 a start edge was detected and when URXIFGx 1 a valid character or break was received When the ISR determines the interrupt request was from a start edge user software toggles URXSE and must enable the BRCLK source by returning from the ISR to active mode or to a low power mode where the source is active If the ISR returns to a low power mode where the BRCLK source is inactive the character will not be received Toggling URXSE clears the URXS signal and re enables the start edge detect feature for future characters See chapter System Resets Interrupts and Operating Modes for information on entering and exiting low power modes The now active BRCLK allows the USART to receive the balance of the character After the full character is received and moved to UxRXBUF URXIFGx is set and an interrupt service is again requested Upon ISR entry URX
360. the voltage at R03 reduces the total applied segment voltage decreasing the LCD contrast 18 2 5 LCD Outputs Some LCD segment common and Rxx functions are multiplexed with digital I O functions These pins can function either as digital I O or as LCD functions The pin functions for COMx and Rxx when multiplexed with digital I O are selected using the applicable PxSELx bits as described in the Digital I O chapter The LCD segment functions when multiplexed with digital I O are selected using the LCDPx bits The LCDPx bits selects the LCD function for groups of pins When LCDPx 0 no multiplexed pin is set to LCD function When LCDPx 1 segments SO S15 are selected as LCD function When LCDPx 1 LCD segment functions are selected in groups of four For example when LCDPx 2 segments 50 519 are selected as LCD function E ER ER E EL rr uL Note LCDPx Bits Do Not Affect Dedicated LCD Segment Pins The LCDPx bits only affect pins with multiplexed LCD segment functions and digital I O functions Dedicated LCD segment pins are not affected by the LCDPx bits 0 LCD Controller 18 5 LCD Controller Operation 18 2 6 Static Mode In static mode each MSP430 segment pin drives one LCD segment and one common line COMO is used Figure 18 4 shows some example static waveforms Figure 18 4 Example Static Waveforms V1 COMO E L V5 _ gt trame LE LI EI LI i SP1 VS 7 JL LIE LL V5 Spi
361. tination XOR src dst or XOR W src dst XOR B src dst src XOR dst dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative OSCOFF CPUOFF and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits of byte on the bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B EDEH7 Set different bit to 15 INV B R7 Invert Lowbyte Highbyte is Oh RISC 16 Bit CPU 3 71 Instruction Set 3 4 4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to the MCLK Interrupt and Reset Cycles Table 3 14 lists the CPU cycles for interrupt overhead and reset Table 3 14 Interrupt and Reset Cycles No of Length of Action Cycles Instruction Return from interrupt RETI 5 1 Interrupt accepted 6 WDT reset 4 Reset RST NMI 4 Format ll Sing
362. tinues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE OF016h Dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h O11FEh OFF16h O11FEh OFF14h OF102h OFF14h OF102h OFF12h 04090h PC OFF12h 04090h OFF14h OF018h 0F102h OF018h OF016h OA123h OF016h pEoieh 0A123h OFF16h 01116h Oxxxxh 011FEh 01116h Oxxxxh 01114h 05555h 01114h 0A123h 3 12 RISC 16 Bit CPU 3 3 4 Absolute Mode Addressing Modes The absolute mode is described in Table 3 7 Table 3 7 Absolute Mode Description Assembler Code Content of ROM Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OF016h OF014h 01116h 01114h 01112h MOV amp EDE amp TONI MOV X 0 Y 0 X EDE Y TONI Two or three words Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV amp EDE amp TONI Source address EDE 0F016h dest address TONI 01114h After Address Register Address Register Space Space Oxxxxh PC 01114h OFF16h 01114h OF016h OFF14h OFO16h 04292h PC OFF12h
363. tion TSM Example Figure 22 10 shows an example for a TSM sequence The TSMx register values for the example are shown in Table 22 6 ACLK and SIFCLK are not drawn to scale The TSM sequence starts with SIFTSMO and ends with a set SIFSTOP bit in SIFTSM9 Only the SIFTSM5 to SIFTSMSO states are shown Table 22 6 TSM Example Register Values TSMx Register TSMx Register Contents SIFTSM5 0100Ah SIFTSM6 00402h SIFTSM7 01812h SIFTSM8 00952h SIFTSM9 00200h The example also shows the affects of the clock synchronization when switching between SIFCLK and ACLK In state SIFTSM6 SIFACLK is set whereas in the previous state and the successive state SIFACLK is cleared The waveform shows the duration of SIFTSM6 is less than one ACLK cycle and the duration of state SIFTSM7 is up to one SIFCLK period longer than configured by the SIFREPEATx bits Figure 22 10 Timing State Machine Example SIF SIF SIFCHx tsm 10 10 10 00 SIFEX tsm SIFCA tsm SIFRSON tsm SIFDAC tsm SIFSTOP tsm Scan IF 22 19 Scan IF Operation 22 2 3 Scan IF Processing State Machine 22 20 Scan IF The PSM is a programmable state machine used to determine rotation and direction with its state table stored within MSP430 memory flash ROM or RAM The processing state machine measures rotation and controls interrupt generation based on the inputs from the timing state machine and the analog front en
364. toggled when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value The output is reset when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value Timer A 12 13 Timer A Operation Ouiput Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value and rolls from TACCRO to zero depending on the output mode An example is shown in Figure 12 12 using TACCRO and TACCR1 Figure 12 12 Output Example Timer in Up Mode OFFFFh TACCRO TACCRt Oh Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQUI EQUO EQUI EQUO TAIFG TAIFG TAIFG 12 14 Timer A Timer A Operation Ouiput Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCRO values depending on the output mode An example is shown in Figure 12 13 using TACCRO and TACCR1 Figure 12 13 Output Example Timer in Continuous Mode OFFFFh TACCRO TACCR1 Oh TAIFG EQU1 EQUO TAIFG EQU1 EQUO Interrupt Events Timer A 12 15 Timer A Operation Ouiput Example Timer in Up Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals
365. tor accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels L L LU L O External channel to monitor external voltage The SVS block diagram is shown in Figure 6 1 Note MSP430x41x Voltage Level Detect The MSP430x41x devices implement only one voltage level detect setting When VLDx 0 the SVS is off Any value greater than 0 for VLDx selects a voltage level detect of 1 9V 6 2 Supply Voltage Supervisor Figure 6 1 SVS Block Diagram SVSIN SVS Introduction VCC Brownout Reset ad 1 25V i SVS POR L tReset 50us e SVSOUT Set SVSFG SVSCTL Bits Supply Voltage Supervisor 6 3 SVS Operation 6 2 SVS Operation The SVS detects if the AVcc voltage drops below a selectable level It can be configured to provide a POR or seta flag when a low voltage condition occurs The SVS is disabled after a POR to conserve current consumption 6 2 1 Configuring the SVS The VLDx bits are used to enable disable the SVS and select one of 14 threshold levels V sys for comparison with AVcc The SVS is off when VLDx 0 and on when VLDx gt 0 The SVSON bit does not turn on the SVS Instead it reflects the on off state of the SVS and can be used to determine when the SVS is on When VLDx 1111 the external SVSIN chan
366. tructions are described and shown in Figure 3 5 Figure 3 5 PUSH SP POP SP Sequence PUSH SP POP SP SPoid SP4 SP4 SP2 SP4 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 RISC 16 Bit CPU 3 5 CPU Registers 3 2 3 Status Register SR The status register SR R2 used as a source or destination register can be used the register mode only addressed with word instructions The remain ing combinations of addressing modes are used to support the constant gen erator Figure 3 6 shows the SR bits Figure 3 6 Status Register Bits 15 9 8 T 0 OSC CPU rw 0 Table 3 1 describes the status register bits Table 3 1 Description of Status Register Bits Bit V SCG1 SCGO OSCOFF CPUOFF GIE N 3 6 RISC 16 Bit CPU Description Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range Set when Positive Positive Negative Negative Negative Positive otherwise reset ADD B ADDC B Set when Positive Negative Negative Negative Positive Positive otherwise reset SUB B SUBC B CMP B System clock generator 0 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK System clock generator 1 This bit when set turns off the
367. ts 0 3 SVS Registers unea inate p Elder aa uten ia ec Rte ere ae viii Contents 7 Hardware Multiplier 00 III IRIS 7 1 Hardware Multiplier 7 2 Hardware Multiplier Operation 00 00 cece eee III 7 2 1 Operand Registers lees 7 2 2 Result Registers 7 2 3 Software Examples iringi 7 2 4 Indirect Addressing of RESLO 72 5 Using Interr pts emend RR ee tube LAC be eas 7 3 Hardware Multiplier 5 lt 8 DMA neh ee eee a 81 DMA Introduction 0 0 cc RR re nn 9 2 DMA Operation secos tee ei 8 21 DMA Addressing Modes 8 2 2 DMA Transfer Modes eni hne 8 2 3 Initiating DMA Transfers 8 2 4 Stopping DMA vutaiani eee 8 25 8 2 6 DMA Transfer Cycle 8 2 7 Using DMA with Sys
368. ty vote fails to detect a start bit the USART halts character reception If character reception is halted an active BRCLK is not necessary A time out period longer than the character receive duration can be used by software to indicate that a character was not received in the expected time and the software can disable BRCLK Figure 14 13 Glitch Suppression USART Activated 14 20 Majority Vote Taken USART Peripheral Interface UART Mode USART Registers UART Mode 14 3 USART Registers UART Mode Table 14 3 lists the registers for all devices implementing a USART module Table 14 4 applies only to devices with a second USART module USART1 Table 14 3 USARTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071h 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 1 ME1 Read write 004h 000h with PUC SFR interrupt enable register 1 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC Table 14 4 U
369. ue It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value 011 Set Reset The output is set when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value 100 Toggle The output is toggled when the timer counts to the TBCLx value The output period is double the timer period 101 Reset The output is reset when the timer counts to the TBCLx value It remains reset until another output mode is selected and affects the output 110 Toggle Set The output is toggled when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value 111 Reset Set The output is reset when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value 13 14 Timer B Timer B Operation Ouiput Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value and rolls from TBCLO to zero depending on the output mode An example is shown in Figure 13 12 using TBCLO and TBCL1 Figure 13 12 Output Example Timer Up Mode TBR max TBCLO TBCL1 Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set
370. uences can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 19 7 Sequence of Channels Mode CONSEQx 01 ADC120N 1 ENC 24 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r and ADC12SC Wait for Trigger SAMPCON 47 EOS x 1 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx Ifx lt 15thenx x 1 else x 0 SAMPCON Y MSC 1 and SHP 1 and EOS x 0 Ifx lt 15thenx x 1 else x 0 12 x ADC12CLK 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx 19 12 ADC12 ADC12 Operation Repeat Single Channel Mode A single channel is sampled and converted continuously The ADC results are written to the ADC12MEMx defined by the CSTARTADDxX bits It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion Figure 19 8 shows repeat single channel mode Figure 19 8 Repeat Single Channel Mode CONSEQx 10 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r4 and ADC12SC 5 Wait for Trigger SAMPCON 4 ENC 0 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx SAMPCON Y 12 x ADC12CLK MSC 1 and SHP 1 and ENC
371. ulation Emulation Description Status Bits Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst POP B dst SP gt temp SP 2 SP temp dst MOV SP dst or MOVW SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah Mem R7 low byte of system stack POP SR Last word on stack moved to the SR p BB BB B B B B iil Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix 1 3 54 RISC 16 Bit CPU PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Examp
372. upt enable This bit enables the TAIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TAIFG Bit 0 Timer A interrupt flag 0 No interrupt pending 1 Interrupt pending 12 20 Timer A Timer A Registers TAR Timer A Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits Timer A register The TAR register is the count of Timer A 15 0 Timer A 12 21 Timer A Registers TACCTLx Capture Compare Control Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 r 0 rw 0 7 rw 0 CMx CCISx SCS SCCI Unused OUTMODx 12 22 6 4 3 2 1 0 0 r 0 0 0 rw 0 Bit 15 14 Bit 13 12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7 5 Timer A 5 rw 0 rw rw rw rw Capture mode 00 Nocapture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TACCRx input signal See the device specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vcc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit
373. ust be set to 1 before any conversion can take place Conversion Clock Selection 19 4 ADC12 The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected The ADC12 source clock is selected using the ADC12SSELx bits and can be divided from 1 8 using the ADC12DIVx bits Possible ADC12CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC120SC The ADC12OSO generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific datasheet for the ADC12OSC specification The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC12 Operation 19 2 2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 19 2 The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk The ADC12 uses the cha
374. veforms COM2 COMO 1 V 2 come uei ie era V2 V4 V1 V2 Me e v1 d se TTL LIL LLL SP1 SP3 v5 SP2 V1 P Pi SP Segment Pin aps V5 V1 COMO Resulting Voltage for Segment Is Off Resulting Voltage for Segment d COMO SP2 OV Segment Is On 18 12 LCD Controller Figure 18 9 shows an LCD Controller Operation example 3 mux LCD pin out LCD to MSP430 connections and the resulting segment mapping This is only an example Segment mapping in a user s application depends on the LCD pin out and on the MSP430 to LCD connections Figure 18 9 3 Mux LCD Example DIGIT10 DIGIT1 Pinout and Connections Display Memory Connections 430 Pins LCD Pinout 1312 111013121110 u come osh a Te 4 v iTe S w on 28 pigro St 2 14 d 1 2 So ocni e 2 28 CAP 22 Dig om Mi eg 55 gt 6 2h 2 2 09Ah 4 Digit 7 Se 7 of coon EEEIEE te 57 5 3 16 Digte Pu EE c E e x 97 20 S d A 105 51 4 12 4h 4c 4b 095h Digit 4 52 ep ia Se 5 8 Digit S13 4 gt 14 5d Sa cn to _ sl
375. write 014Eh Unchanged ADC12 memory 8 ADC12MEM8 Read write 0150h Unchanged ADC12 memory 9 ADC12MEM9 Read write 0152h Unchanged ADC12 memory 10 ADC12MEM10 Read write 0154h Unchanged ADC12 memory 11 ADC12MEM 11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTLO Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081 Reset with POR ADC12 memory control 2 ADC12MCTL2 Read write 082h Reset with POR ADC12 memory control 3 ADC12MCTL3 Read write 083h Reset with POR ADC12 memory control 4 ADC12MCTL4 Read write 084h Reset with POR ADC12 memory control 5 ADC12MCTL5 Read write 085h Reset with POR ADC12 memory control 6 ADC12MCTL6 Read write 086h Reset with POR ADC12 memory control 7 ADC12MCTL7 Read write 087h Reset with POR ADC12 memory control 8 ADC12MCTL8 Read write 088h Reset with POR ADC12 memory control 9 ADC12MCTL9 Read write 089h Reset with POR ADC12 memory control 10 ADC12MCTL10 Read write 08Ah Reset with POR ADC12 memory control 11 ADC12MCTL11 Read write 08Bh Reset with POR ADC12 memory control 12 ADC12MCTL12 Read write 08Ch Reset with POR ADC12 memory control 13 ADC12MCTL13 Read write 08Dh Reset with POR ADC12 memory control 14 ADC12MCTL14 Read write 08Eh Reset with POR ADC12 memory control 15 ADC12MCTL15 Rea
376. xtended Time in Low Power Modes The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low power mode periods If the temperature changes significantly the DCO frequency at wake up may be significantly different from when the low power mode was entered and may be out of the specified operating range To avoid this the DCO can be setto it lowest value before entering the low power mode for extended periods of time where temperature can change Enter LPM4 Example with lowest DCO Setting BIC B FN 8 FN 4 FN 3 FN 2 amp SCFIO Lowest Range MOV B 010h amp SCFI1 Select Tap 2 BIS GIE CPUOFF OSCOFF SCG1 SCG0 SR Enter LPM4 A 2s Program stops Interrupt Service Routine BIC CPUOFF OSCOFF SCG1 SCG0 0 SR Exit LPM4 on RETI RETI System Resets Interrupts and Operating Modes 2 15 Principles for Low Power Applications 2 4 Principles for Low Power Applications Often the most important factor for reducing power consumption is using the MSP430 s clock system to maximize the time in LPM3 LPM3 power consumption is less than 2 uA typical with both a real time clock function and all interrupts active A 32 kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO normally off which has a 6 us wake up E E Use interrupts to wake the processor and control program flow Peripherals should be switched on only when needed Use low power integrated perip
377. xxFFh as shown in Figure 5 10 The flash programming voltage remains on for the duration of writing the 64 byte block Figure 5 10 Flash Memory Blocks A block write cannot be initiated from within flash memory The block write must be initiated from RAM only The BUSY bit remains set throughout the duration of the block write The WAIT bit must be checked between writing each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash recovery time given by t end BUSY is cleared following each block write completion indicating the next block can be written Figure 5 11 shows the block write timing Figure 5 11 Block Write Cycle Timing BLKWRT bit Programming Voltage Write to Flash e g MOV 123h amp Flash Y dm 4 1 1 1 EE 4 Generate E Cumulative Programming Time lt 4ms Current Consumption is Increased Programming Operation Active Remove bo pog Programming Voltage B US LL WAIT liblockwrite byteo 30 f FTG L t bytes 1 63 21 t bytes 1 63 21 6 gt Flash Memory Controller 5 11 Flash Memory Operation Block Write Flow and Example A block write flow is shown in F
378. y instruction When setting any of the mode control bits the selected operating mode takes effect immediately Peripherals operating with any disabled clock are disabled until the clock becomes active The peripherals may also be disabled with their individual control register settings All I O port pins and RAM registers unchanged Wake up is possible through all enabled interrupts System Resets Interrupts and Operating Modes 2 13 Operating Modes Figure 2 9 MSP430x4xx Operating Modes For Basic Clock System RST NMI Reset Active WDT Active Time Expired Overflow WDTIFG 1 ici RST NMI is Reset Pin WDTIFG 1 WDT is Active RST NMI NMI Active WDT Active Security Key Violation Active Mode CPU Is Active Peripheral Modules Are Active CPUOFF 1 OSCOFF 1 SCGO 1 SCG1 1 CPUOFF 1 SCGO 0 SCG1 0 LPMO CPU Off FLL On MCLK On ACLK On LPM4 CPU Off FLL Off MCLK Off ACLK Off CPUOFF 1 SCGO 1 SCG1 0 CPUOFF 1 DC Generator Off CPUOFF 1 SCGO 1 SCGO 0 SCG1 1 SCG1 1 LPM3 CPU Off FLL Off MCLK Off ACLK On LPM1 CPU Off FLL Off MCLK On ACLK On LPM2 CPU Off FLL Off MCLK Off ACLK On DC Generator Off SCG1 SCGO OSCOFF CPUOFF Mode CPU and Clocks Status 0 Active CPU is active all enabled clocks are active 1 LPMO CPU MCLK are disa

MSP430x4xx Family User's Guide (Rev. D)

Contents

Download Pdf Manuals

Related Search

Related Contents