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SmartFusion2 High Speed Serial and DDR Interfaces User's Guide

1. Bit Reset Number Name Value Description 15 3 Reserved 2 Transmit test pattern 0x0 When this bit is set to a one pattern testing is enabled on the transmit enabled path 1 b0 Transmit receive test pattern disabled 1 b1 Transmit receive test pattern enabled 1 0 Test pattern select 0x0 The test pattern is used when enabled pattern testing is selected using these bits 2 b00 High frequency test pattern 2 b01 Low frequency test pattern 2 b10 Mixed frequency test pattern 2 b11 Reserved Table 3 19 Depicts Definition of Vendor Specific Reset Low 1 Register Reg12 Vendor Specific Reset Low 1 Bit Reset Number Name Value Description 15 0 Reserved TBD General purpose registers that are connected to the output port XAUI VNDRRESLO 15 0 Typically used for external device control Table 3 20 Depicts Definition of Vendor Specific Reset Low 2 Register Reg13 Vendor Specific Reset Low 2 Bit Reset Number Name Value Description 15 0 Reserved TBD General purpose registers that are connected to the output port XAUI VNDRRESLO 31 16 Typically used for external device control 146 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 21 Depicts Definition of Vendor Specific Reset High 1 Register Reg14 Vendor Specific Reset High 2 Bit Reset Number Name
2. 15 0 REG_PHY_BIST_SHIFT_DQ Ox0 15 0 bits of REG PHY BIST SHIFT DQ Determines whether early shifting is required for a particular DQ bit when REG PHY BIST MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift 320 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_BIST_TEST_SHIFT_PATTERN_2_CR Table 7 106 PHY BIST TEST SHIFT PATTERN 2 CR Bit Reset Number Name Value 31 16 Reserved 0x0 Description Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_SHIFT_DQ 0x0 31 16 bits of REG PHY BIST SHIFT DQ Determines whether early shifting is required for a particular DQ bit when REG_PHY_BIST_MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift PHY_BIST_TEST_SHIFT_PATTERN_3_CR Table 7 107 PHY BIST TEST SHIFT PATTERN 3 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 0 REG PHY BIST SHIFT DQ 0x0 43 32 bits of REG PHY BIST SHIFT DQ Determines whether ea
3. Reg20 CONFIG_PCIE_PM Register 0x2020 Table 1 18 CONFIG PCIE PM Bit Number Reset Name Value Description 3 CFGR TX SWING 0x0 Transmit swing This signal is a per link signal which is generated by each link PCle The PCS logic performs the internal mapping of link to lanes Note This signal is only for PCIe Gen2 controller not for PCIe GENT controller CFGR L2 P2 ENABLE 0x0 L2 P2 enable 1 b1 Enable L2 P2 Default L2P2 Enabled 1 b1 Disable L2 P2 If L2 P2 is enabled cfgr_pm_auxpwr should be enabled too CFGR_PM_AUX_PWR 0x0 Slot auxiliary power This signal specifies whether the device uses the slot auxiliary power source This signal is used only used if the core supports D3 cold 1 b1 Auxiliary power source available default L2P2 Enabled 1 bO Auxiliary power source unavailable CFGR SLOT CONFIG 0x0 Slot clock configuration This signal is used to inform the configuration space if the reference clock of the PHY is same as that of the slot 0 Independent clock 1 Slot clock This signal is synchronous to CLK Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 33 I Microsemi SERDESIF Block Table 1 19 CONFIG PHY MODE 0 Reg24 CONFIG PHY MODE 0 Register 0x2024 Bit Reset Number Name Value Description 15 0 CONFIG PHY MODE 0x0 For each lane this signal selects the protocol d
4. Bit Reset Number Name Value Description 7 0 TX PST RATIO This register defines the TX post cursor ratio for the Gen1 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 A value of 3 5 dB corresponds to 8 d21 encoding Note This register can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated at the end of calibration on entry or exit of TX Electrical Idle or when reg128 is programmed 192 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TX_PRE_RATIO Register Table 5 14 TX PRE RATIO Bit Reset Number Name Value Description 7 0 TX PRE RATIO This register defines the TX pre cursor ratio for the Gen1 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Note This register can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated at the end of calibration on entry or exit of TX electrical idle or when Reg128 is programmed ENDCALIB_MAX Register Table 5 15 ENDCALIB_MAX Bit Reset Number Name Value Description 7
5. Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready RXIDLE_MAX_ERRCNT_THR Register Table 5 5 RXIDLE_MAX_ERRCNT_THR Bit Reset Number Name Value Description 7 4 RXIDLE_MAX This register defines the number of clock cycles required before the activity detected output of the PMA macro and reports either electrical idle or valid input data This register must be set to at least 3 because the activity detected signal is considered as metastable by the PCS logic 3 0 ERRCNT_THR In PCS driven mode the PMA control logic counts the number of errors detected by the PCS logic in order to decide to switch back to frequency lock mode of the CDR PLL This register defines the error counter threshold value after which the CDR PLL switches back to frequency lock Note This register can be reprogrammed any time during operation IMPED_RATIO Register Table 5 6 IMPED_RATIO Bit Reset Number Name Value Description 7 0 IMPED_RATIO This register is used to fine tune the impedance ratio of the PMA macro with a nominal value of 100 ohms corresponding to a multiplication factor of 1 which is encoded 8 d128 A 150 ohm impedance corresponds to 2 3 ratio encoded 8 d85 Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready 190 Revision 1 I Microsem
6. Bit Reset Number Name Value Description 31 26 PM DATA SCALE 2 31 26 Reserved 25 24 PM DATA SCALE 2 25 24 These bits set the register that defines data scale 3 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 23 18 PM DATA SCALE 2 23 18 Reserved 17 16 PM DATA SCALE 2 17 16 These bits set the register that defines data scale 2 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 15 10 PM DATA SCALE 2 15 10 Reserved 9 8 PM DATA SCALE 2 98 These bits set the register that defines data scale 1 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 7 2 PM DATA SCALE 2 7 2 Reserved 1 0 PM DATA SCALE 2 10 These bits set the register that defines data scale 0 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field Revision 1 99 lt gt Microsemi PCI Express PM DATA SCALE 3 Register 07Ch Table 2 47 PM DATA SCALE 3 Bit Reset Number Name Value Description 31 26 PM DATA SCALE 3 31 26 Reserved 25 24 PM DATA
7. This signal is used in PCle mode in order to select the association of lane to link The 4 bits refers to four lanes 132 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 3 describes the settings for the three SERDESIF system registers to force the SERDESIF into XAUI mode Table 3 3 XAUI Mode Settings Using SERDESIF System Register CONFIG_PHY_MODE 15 0 4 bits per lane CONFIG EPCS SEL 3 0 CONFIG_LINKK2LANE 3 0 1 bit per lane 1 bit per lane Mode Lane3 Lane2 Lane1 Lane0 Lane3 Lane2 Lane1 LaneO Lane3 Lane2 Lane1 LaneOd XAUI x4 1 1 1 1 1 1 1 1 0 0 0 0 SERDESIF System Registers Configurations for XAUI Mode The SmartFusion2 SoC FPGA SERDESIF sub system has three regions of configuration and status registers which can be accessed by the 32 bit APB bus e SERDESIF System Registers The SERDESIF system registers control the SERDESIF module for single protocol or multi protocol support implementation e PCle Core Bridge Register Space The PCIE core configuration and status registers occupy 4 kbytes of configuration memory map e SERDES Macro Registers The SERDES macro register map contains control and status information of the SERDES block and lanes In the XAUI mode the PCle core registers are not used Only the SERDESIF system register and the SERDES macro r
8. lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide AXI MASTER WINDOWO 1 Register 104h Table 2 81 AXI MASTER WINDOWO 1 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOWO1 31 12 Size of AXI master window 0 11 1 AXI MASTER WINDOWO1 31 12 Reserved 0 AXI MASTER WINDOWO1 0 Enable bit of AXI master window 0 AXI MASTER WINDOWO 2 Register 108h Table 2 82 AXI MASTER WINDOWO 2 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOWO02 31 12 LSB of base address PCIe window 0 11 5 AXI MASTER WINDOWO2 11 5 Reserved 5 0 AXI MASTER WINDOWO2 5 0 These bits set the BAR To select a BAR set the following values 0x01 BARO 32 bit BAR 0x02 BAR1 32 bit BAR 0x04 BAR2 32 bit BAR 0x08 BAR3 32 bit BAR 0x10 BAR4 32 bit BAR 0x20 BARS 32 bit BAR or BARO 1 64 bit BAR only or BAR2 3 64 bit BAR only or BAR4 5 64 bit BAR only SS 222 oS wo AXI MASTER WINDOWO 3 Register 10Ch Table 2 83 AXI MASTER WINDOWO 3 Bit Reset Number Name Value Description 31 0 AXI MASTER WINDOWO3 31 12 MSB of base address PCle window 0 AXI MASTER WINDOWh1 0 Register 110h Table 2 84 AXI MASTER WINDOW1 0 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW10 31 12 Base address AXI master window 1 11 0 Reserved Reserved AXI MASTER WINDOW1 1 Registe
9. 10 7 REG_PHY_RDC_FIFO_RST_ERR_CNT 0x0 Counter for counting how many times the pointers of read capture FIFO differ when they are reset by DLL_CALIB 6 0 PHY REG RDLVL FIFOWEIN RATIO 0x0 54 48 bits of PHY_REG_RDLVL_FIFOWEIN_RATIO Ratio value generated by read gate training FSM Table 7 1 PHY_MASTER_DLL_SR 93 PHY MASTER DLL SR Bit Number Name Reset Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 3 PHY_REG_STATUS_OF_IN_LOCK_STATE 0x0 Lock status from the output filter module inside the master DLL 2 bits per MDLL PHY has 3 MDLLs Bit 0 Fine delay line lock status 1 Locked 0 Unlocked Bit 1 Coarse delay line lock status 1 Locked 0 Unlocked 2 0 PHY REG STATUS DLL LOCK 0x0 Status signal 1 Master DLL is locked 0 Master DLL is not locked Three bits correspond to three MDLLs 352 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_DLL_SLAVE_VALUE_1_SR Table 7 194 PHY DLL SLAVE VALUE 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compat
10. REG DDRC DIS ACT BYPASS 0x0 Only present in designs supporting activate bypass When 1 disable bypass path for high priority read activates REG_DDRC_DIS_RD_BYPASS 0x0 Only present in designs supporting read bypass When 1 disable bypass path for high priority read page hits REG DDRC DIS PRE BYPASS 0x0 Only present in designs supporting precharge bypass When 1 disable bypass path for high priority precharges 286 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 49 DDRC ADDR MAP COL 3 CR continued Bit Reset Number Name Value Description 1 REG DDRC DIS COLLISION PAGE OPT 0x0 When this is set to 0 auto precharge is disabled for the flushed command in a collision case Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same address with REG_DDRC_DIS_WC bit 1 where same address comparisons exclude the two address bits representing the critical word 0 REG_DDRC_DIS_SCRUB 0x0 This feature is not supported Only the default value works 1 Disable SECDED scrubs 0 Enable SECDED scrubs Valid only when REG_DDRC_ECC_MODE 100 or 101 DDRC_MODE_REG_RD_WR_CR Table 7 50 DDRC_MODE_REG_RD_WR_CR Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on t
11. I Microsemi MSS DDR Subsystem PHY_DYN_BIST_TEST_ERRCLR_2_CR Table 7 103 PHY DYN BIST TEST ERRCLR 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_ERR_CLR 0x0 31 16 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect PHY_DYN_BIST_TEST_ERRCLR_3_CR Table 7 104 PHY DYN BIST TEST ERRCLR 3 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 0 REG_PHY_BIST_ERR_CLR 0x0 43 32 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect PHY_BIST_TEST_SHIFT_PATTERN_1_CR Table 7 105 PHY BIST TEST SHIFT PATTERN 1 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
12. Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_RATIO 0x4010 47 32 bits of REG_PHY_RD_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_RD_DQS_SLAVE_RATIO_4_CR Table 7 142 PHY RD DQS SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_RD_DQS_SLAVE_RATIO 0x0 49 48 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DQ
13. Bit Reset Number Name Value Description 7 0 ATXDRT EI2 15 8 This register defines bit 15 to bit 8 of the transmitted T parameter sent to the PHY for being in electrical idle Il on the transmit driver ATXDRT EI2 20 16 Register Table 5 83 ATXDRT EI2 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRT EI2 20 16 This register defines bit 20 to bit 16 of the transmitted T parameter sent to the PHY for being in electrical idle II on the transmit driver OVERRIDE_CALIB Register Table 5 84 OVERRIDE_CALIB Bit Reset Number Name Value Description 7 5 Unused 4 OVER_TX This register overrides TX driver settings for driving data on the differential line When set to 1 the PMA control logic will use the content of registers Reg85 to Reg93 for the TX parameters loaded into the SERDES 3 OVER_RX This register overrides RX driver settings for specifying RX settings When set the PMA control logic will use the content of Reg84 Reg83 and Reg82 for the RX parameters loaded into the SERDES 2 OVER_RXD This register overrides the RXD calibration result with the content of Reg97 1 OVER RXT This register overrides the RXT calibration result with the content of Reg98 0 OVER_SCH This register overrides the Schmitt trigger calibration result with the content of Reg99 Note This register can be programmed any time but has functional impact on the
14. Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGINS FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden Revision 1 199 I Microsemi Serializer Deserializer TX_AMP_RATIO_MARGIN6_FULL Register Table 5 33 TX AMP RATIO MARGIN6 FULL Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN6 FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN7_FULL Register Table 5 34 TX AMP RATIO MARGIN7 FULL Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN7 FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden Note For Reg32 to Reg35 these registers can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated on entry or exit of TX electrical idle I when Reg128 is programmed or when any of the PIPE TXSwing TXDeemp or TXMargin signals is modified RE_AMP_RATIO_DEEMPO0 Register Table 5 35 RE AMP RATIO DEEMP
15. REG PHY GATELVL NUM OF DQ0 1 3 0 REG PHY WRLVL NUM OF DQ0O 0x0 This register value determines the number of samples for dq0 in for each ratio increment by the write leveling FSM NUM_OF_ITERATION rEG_PHY_GATELVL_NUM_OF_DQ0 1 Revision 1 323 I Microsemi MSS DDR Subsystem Table 7 115 PHY DQ OFFSET 1 CR PHY DQ OFFSET 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_DQ_OFFSET 0x0240 15 0 bits of REG PHY DQ OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG_PHY_USE_WR_LEVEL 1 Table 7 116 PHY DQ OFFSET 2 CR PHY DQ OFFSET 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_DQ_OFFSET 0x4081 31 16 bits of REG PHY DQ OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG PHY USE WR LEVEL 1 Table 7 117 PHY DQ OFFSET 3 CR PHY DQ OFFSET 3 CR Bit Reset
16. Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 12 DDRC_REG_ECC_BANK 0x0 Bank where the SECDED error occurred 11 0 DDRC_REG_ECC_COL 0x0 Column where the SECDED error occurred Col 0 is always set to 0 coming out of the controller This bit is overwritten by the register module and indicates whether the error came from upper or lower lane DDRC_LCB_NUMBER_SR Table 7 93 DDRC LCB NUMBER SR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 0 DDRC_LCB_BIT_NUM 0x0 Indicates the location of the bit that caused a single bit error in SECDED case encoded value If more than one data lane has an error in it the lower data lane is selected This register is 7 bits wide in order to handle 72 bits of the data present in a single lane This does not indicate CORRECTED_BIT_NUM in the case of device correction SECDED The encoding is only present in designs that support SECDED DDRC_LCB_MASK_1_SR Table 7 94 DDRC LCB MASK 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on
17. Reset Value Description 7 4 Unused 3 MESO SYNC MESO LPBK This register is read only and reports whether the mesochronous clock alignment state machine has completed its process having thus aligned the CDR receive clock to the transmit clock When set this register enables mesochronous loopback mode which forces PMA received data to be re transmitted on the PMA TX interface This mode requires that no PPM exists between RX data and TX data thus that both sides of the link use the same reference clock and also performs alignment of the CDR clock to the transmit clock using the PMA CDR PLL skip bit functionality This alignment is automatically performed by a state machine when this loopback register is set PAR LPBK When set this register enables parallel loopback mode which forces the transmitted PIPE 10 bit encoded data to be looped back to the receiver PIPE RX interface PLESIO LPBK When set this register enables plesiochronous loopback mode which forces the PCS to loop back data from RX back to TX after the PCle elastic buffer function It is equivalent to PCle slave loopback except that it is forced by a register instead of controlled by the PCle MAC layer 222 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide GEN1_TX_PLL_CCP Register Table 5 120 GEN1 TX PLL CCP Bit Reset Number Name V
18. Revision 1 EPCS Reset Network 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Figure 4 4 shows the reset network for the EPCS interface x4 lanes implementation All 4 lanes reset inputs EPCS 0 RESET N EPCS_1_RESET_N EPCS 2 RESET N and EPCS 3 RESET N are gated with the power valid signal from the SmartFusion2 SoC FPGA program control and again with SERDES LANEx SOFTRESET x 0 1 2 3 Note The SERDES LANEx SOFTRESET signals are controlled by the SERDESIF System register SERDESIF SOFT RESET active low reset signal for each lane which can be programmed using the APB3 interface EPCS x RESET N and SERDES LANEx SOFTRESET before using the EPCS interface FABRIC EPCS 2 RESET N EPCS 1 RESET N EPCS 3 RESET N EPCS 0 RESET N Power up SERDESIF SERDES_LANEQ_SOFTRESET NOOS JRR SERDES_LANE1_SOFTRESET _ A SERDES LANE SOFTRESET EE BDB SERDES PMA only SERDES LANE3 SOFTRESET Figure 4 4 EPCS Implementation of the SERDESIF Block Revision 1 I O PADS 159 amp Microsemi EPCS Interface EPCS Clock Network Figure 4 5 shows the SERDESIF clock network for EPCS mode The SERDES lanes reference clock aRefClk 3 0 can be sourced from refclk_io0 refclk_io1 fab_ref_clk or ccc_refclk This reference clock can be selected for the SERDES lane using the Libero SoC SERDESI
19. SERDESIF SERDES Block X2 EPCS El Interface I Q PADS SERDES EPCS PMA only X2 EPCS Interface SERDESIF System Register x4 Lane XAUI Extender XGMII Interface A APB Slave Interface FABRIC GIGAbit Ethernet Soft IP Figure 1 5 SERDESIF Configuration for XAUI Protocol Table 1 3 shows the configuration bandwidth for using XAUI in four physical SERDES lanes Refer to the XAUI section on page 129 for details on XAUI protocol implementation in SmartFusion2 SoC FPGA devices Table 1 3 Bandwidth for Implementing XAUI in SERDESIF Block Lane0 Lane1 Lane2 Lane3 Speed Speed Speed Speed bits per bits per bits per bits per XAUI Protocol Protocol second Protocol second Protocol second Protocol second Single Protocol PHY mode XAUI 3 125 G XAUI 3 125 G XAUI 3 125 G XAUI 3 125 G 12 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SGMII Protocol The SGMII protocol can be implemented in Single Multiple Protocol mode using the MAC block in the microcontroller subsystem MSS In Single Protocol mode the SGMII protocol can be implemented using lane3 of the EPCS interface Lane3 of the EPCS interface needs to be connected to the MSS ethernet MAC through the CoreTBItoEPCS IP core block in the FPGA fabric CoreTBItoEPCS appears between TBI Ten Bit Inter
20. lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Revision 1 307 I Microsemi MSS DDR Subsystem Table 7 87 DDRC LCE SYNDROME 2 SR DDRC LCE SYNDROME 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC REG ECC SYNDROMES 0x0 31 16 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it then the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in desig
21. 18 16 MSI5 18 16 These bits set MSI TC 3 of MSI MAP5 15 11 MSI5 15 11 These bits set MSI Offset 2 of MSI MAP5 10 8 MSI5 10 8 These bits set MSI TC 2 of MSI MAP5 7 3 MSI5 7 3 These bits set MSI Offset 1 of MSI MAP5 2 0 MSI5 2 0 These bits set MSI TC 1 of MSI MAP5 MSI 6 Register 098h Table 2 54 MSI 6 Bit Reset Number Name Value Description 31 27 MSI6 31 27 These bits set MSI Offset 3 of MSI MAP6 26 24 MSI6 26 24 These bits set MSI TC 1 of MSI MAP6 23 19 MSI6 23 19 These bits set MSI Offset 3 of MSI MAP6 18 16 MSI6 18 16 These bits set MSI TC 3 of MSI MAP6 15 11 MSI6 15 11 These bits set MSI Offset 2 of MSI MAP6 10 8 MSI6 10 8 These bits set MSI TC 2 of MSI MAP6 7 3 MSI6 7 3 These bits set MSI Offset 1 of MSI MAP6 2 0 MSI6 2 0 These bits set MSI TC 1 of MSI MAP6 102 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MSI 7 Register 09Ch Table 2 55 MSI 7 Bit Reset Number Name Value Description 31 27 MSI7_31_27 These bits set MSI Offset 3 of MSI_MAP7 26 24 MSI7 26 24 These bits set MSI TC 1 of MSI MAP7 23 19 MSI7 23 19 These bits set MSI Offset 3 of MSI MAP7 18 16 MSI7 18 16 These bits set MSI TC 3 of MSI MAP7 15 11 MSI7 15 11 These bits set MSI Offset 2 of MSI MAP7 10 8 MSI7 10 8 These bits set MSI TC 2 of MSI MAP7 7 3 MSI7 7 3 These bits set MSI Offset 1 of MSI MAP7 2 0 MSI7 20 Thes
22. Defines PCle device ID 15 0 PCIE_VENDOR_ID 0x0 Specifies hardwired settings for PCle identification registers Defines PCle vendor ID Reg34 CONFIG_PCIE_1 Register 0x2034 Table 1 23 CONFIG PCIE 1 Bit Reset Number Name Value Description 31 16 PCIE SUB DEVICE ID 0x0 Specifies hardwired settings for PCle identification registers Defines PCle subsystem device ID 15 0 PCIE SUB VENDOR ID 0x0 Specifies hardwired settings for PCle identification registers Defines PCle subsystem vendor ID Reg38 CONFIG PCIE 2 Register 0x2038 Table 1 24 CONFIG PCIE 2 Bit Reset Number Name Value Description 31 16 PCIE CLASS CODE 0x0 Specifies hardwired settings for PCle identification registers Defines PCIe class code 15 0 PCIE REV ID 0x0 Specifies hardwired settings for PCle identification registers Defines PCIe revision ID Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 35 I Microsemi SERDESIF Block Reg3C CONFIG_PCIE_3 Register 0x203C Table 1 25 CONFIG PCIE 3 Bit Number Name Reset Value Description 5 2 K BRIDGE SPEC REV 0x0 These bits set the PCle specification version capability 0000 Core is compliant with PCle Specification 1 0a 0001 Core is compliant with PCle Specification 1 1 0010 Core is compliant with PCle Specification 2 0 1 K_BRIDGE_EMPH 0x0 Selectable de e
23. Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 REG_PHY_DQ_OFFSET 0x0 34 32 bits of REG_PHY_DQ_OFFSET Offset value from DQS to DQ Default value 0x40 for 90 degree shift This is only used when REG_PHY_USE_WR_LEVEL 1 324 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_DIS_CALIB_RST_CR Table 7 118 PHY DIS CALIB RST CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY DIS CALIB RST 0x0 Disables the resetting of the read capture FIFO pointers with DLL CALIB internally generated signal The pointers are reset to ensure that the PHY can recover if the appropriate number of DQS edges is not observed after a read command which can happen when the DQS squelch timing is manually overridden via the debug registers 0 Enable 1 Disable PHY DLL LOCK DIFF CR Table 7 119 PHY DLL LOCK DIFF CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a r
24. PCle Base IP Core The PCle base IP core implements a x4 PCle endpoint link compliant to PCle Rev 2 0 The following sections describe the features of the SmartFusion2 SoC FPGA PCle IP General e x1 x2 x4 PCle core e 64 bit data path e Supports link rate of 2 5 and 5 0 Gbps per lane e Suitable for endpoint e PCle Base Specification Revision 2 0 and Revision 1 1 compliant e One virtual channel VCO e 16 bit PIPE interface for x1 x2 and x4 configuration e Receive transmit user application interface Advanced error reporting AER support End to end cyclic redundancy check ECRC generation check and forward support Data Transfer e Supports all memory configuration and message transactions e Highly optimized application interface for maximum effective throughput Implements type 0 configuration space for endpoint Configuration e Supports 3 64 bit base address registers BARs or 6 32 bit BARs Power Management and Interrupts e Native active state power management LOs and L1 state support Power management event PME message Up to 32 message signaled interrupts MSI mapped to any traffic class TC and interrupt INT message support MSI X capability support The PCle base IP core implements the transaction layer and data link layer described by the PCle Base Specifications Transaction layer The transaction layer TL contains the configuration space which manages communication with the user
25. PORESET N MDDR Configuration register MDDR_ ALIB_CR MDDR librati trol es RW P Register PORESET N MDDR VO Calibration Contro register MSSDDR_PLL_STATUS_LOW_CR Used to control the corresponding RW P Register CC RESET N configuration input of the MPLL MSSDDR PLL STATUS HIGH CR Used to control the corresponding RW P Register CC RESET N configuration input of the MPLL register MSSDDR FACC1 CR MSS DDR Fabric Alignment Clock cor Field CC RESET_N Controller 1 Configuration register MSSDDR_FACC2_CR MSS DDR Fabric Alignment Clock RW P Field CC_RESET_N Controller 2 Configuration register MSSDDR_CLK_CALIB_STATUS F Used to start an FPGA fabric Ar Register SYSRESELN calibration test circuit DDRB CR RW P Register SYSRESET N MSS DDR bridge configuration register MSSDDR PLL STATUS RO MSS DDR PLL Status register MDDR_IO_CALIB_STATUS RO PORESET N DDR I O Calibration Status register MSSDDR CLK CALIB STATUS RO E SYSRESET_N MSS DDR Clock Calibration Status register Revision 1 265 I Microsemi MSS DDR Subsystem DDR Controller Configuration Register Summary Table 7 19 DDR Controller Configuration Register 266 Revision 1 Address Register Reset Register Name Offset Type Source Description DDRC DYN SOFT RESET CR 0x000 RW RO PRESET N DDRC Reset register DDRC DYN REFRESH 1 CR 0x008 RW PRESET NIDDRC
26. SER_INTERRUPT 0x58 SW1C SPLL FPLL lock interrupt SERDESIF_INTR_STATUS 0x5C SW1C Error correction coding ECC interrupt status REFCLK_SEL 0x64 R W LANEO1 REFCLK SEL and LANE23 REFCLK SEL bits are used for the reference clock selection for the four lanes of PMA Revision 1 133 I Microsemi XAUI Table 3 4 e SERDESIF System Registers in EPCS Mode continued Address Register Register Name Offset Type Description PCLK SEL 0x68 R W PIPE_PCLKIN_LANE01_SEL and PIPE_PCLKIN_LANE23_SEL bits are used for PIPE clock input selection for the lanes EPCS_RSTN_SEL Ox6C R W EPCS reset signal selection from fabric DESKEW_CONFIG OxA4 R W PLL REF clock DESKEW register Using the XAUI Protocol Mode This section describes customizing the SERDESIF block and generating the XAUI mode from Libero System on Chip SoC device It describes the clock and reset network when using the XAUI mode It also describes the MDIO interface and running loopback mode Configuring High Speed Serial Generator for XAUI Mode The high speed serial interface generator in Libero SoC allows to configure the SERDESIF block in the XAUI mode and controls the setting of the three SERDESIF system registers Refer to Figure 3 3 for the XAUI mode setting in high speed serial interface generator bs Configuring top_0 SERDES_IF 0 0 517 i Configuration Identfication Location SERDESIF_O X Pre
27. e 460001 XAUI mode Lane3 460010 EPCS SGMII mode Lane3 e 4 b0011 EPCS 2 5 GHz mode Lane3 4 b0100 EPCS 1 25 GHz mode Lane3 e 4 b0101 EPCS undefined mode Lane3 e 4 b1111 SERDES PHY Lane3 is off CONFIG_PHY_MODE 15 12 Defines Lane2 settings 460000 PCIE mode Lane2 e 4 b0001 XAUI mode Lane2 e 4 b0011 EPCS 2 5 GHz mode Lane2 e 460100 EPCS 1 25 GHz mode Lane2 e 4 b0101 EPCS undefined mode Lane2 e 4 b1111 SERDES PHY Lane2 is off CONFIG_PHY_MODE 7 4 Defines Lane settings 460000 PCIE mode Lane 4 b0001 XAUI mode Lane1 e 4 b0011 EPCS 2 5 GHz mode Lane1 e 460100 EPCS 1 25 GHz mode Lane1 e 4 b0101 EPCS undefined mode Lane1 e 4 b1111 SERDES PHY Lane0 is off CONFIG_PHY_MODE 3 0 Defines LaneO settings 460000 PCIE mode LaneO e 4 b0001 XAUI mode LaneO e 4 b0011 EPCS 2 5 GHz mode LaneO e 460100 EPCS 1 25 GHz mode LaneO 4 b0101 EPCS undefined mode LaneO e 4 b1111 SERDES PHY Lane0 is off CONFIG EPCS SEL 3 0 For each lane one bit of this signal defines whether the external PCS interface is used or the PCI express PCS is enabled e Ob PCI express mode e 1b External PCS mode CONFIG_EPCS_SEL 3 External PCS selection associated to Lane3 CONFIG_EPCS_SEL 2 External PCS selection associated to Lane2 CONFIG_EPCS_SEL 1 External PCS selection associated to Lane1 CONFIG_EPCS_SEL 0 External PCS selection associated to LaneO CONFIG_LINKK2LANE 3 0
28. PCIE x TXDP2 floating PCIE x TXDP3 PCIE x TXDNO Output I O Pads Transmit data SERDES differential negative output PCIE x TXDN1 Each SERDESIF consists of 4 TX Signals Here x 0 for SERDESIF 0 and x 1 for SERDESIF 1 If unused can be left PCIE x TXDN2 floating PCIE x TXDN3 PCIE x REXTL Reference I O Pads External reference resistor connection to calibrate TX RX termination value Each SERDESIF consists of 2 REXT signals one for lanes 0 and 1 and another for lanes 2 and 3 Here x 0 for PCIE_x_REXTR SERDESIF 0 and x 1 for SERDESIF 1 If unused can be left floating PCIE_x_REFCLKOP Input I O Pads Reference clock differential positive Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not PCIE_x_REFCLK1P activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating PCIE_x_REFCLKON Input I O Pads Reference clock differential negative Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF 1 If unused can be left floating 230 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 5 141 SmartFusion2 SoC FPGA SERDES Block External PCS Signal Interface EPCS 0 RESET N EPCS_1
29. PCIe 256 SGMII 1 25G PES Reversedmode PCle 25G PCIe 25G SGMII 1256 PCle 5G SGMII 1 25G PCle 5G PCle 5G SGMII 1 25G 14 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide EPCS Protocol By using the EPCS interface any user defined serial protocol can be implemented in the SmartFusion2 SoC FPGA family The SERDESIF block can be configured to bypass the embedded PCS logic in the SERDES block and expose the EPCS interface to the fabric The user defined IP block in the FPGA fabric can be connected to this EPCS interface SERDESIF X2 EPCS VO PADS ak SERDES PMA only X2 EPCS SERDESIF System Register APB Slave EPCS Lane 0 EPCS Lane 2 Interface and Lane 1 and Lane 3 FABRIC Figure 1 7 SERDESIF Configuration for EPCS Protocol Refer to the EPCS Interface section on page 153 for more information on EPCS implementation in SmartFusion2 SoC FPGA families Revision 1 15 lt gt Microsemi SERDESIF Block In summary the four SERDES physical lanes can be configured to run different serial protocols resulting in different modes of operation Table 1 5 summarizes the various modes of operation of the SERDESIF block Table 1 5 Various Serial Protocol Implementation SmartFusion2 SoC FPGA Devices PHY Physical Lanes LaneO0 Lane1 Lane2 Lane3 PHY Serial Protocol M
30. Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 PHY_RESET 0x0 A 1 in this register will bring the PHY out of reset This is dynamic and synchronized internally before giving to PHY Bit Number PHY_LEVELLING_FAILURE_SR Table 7 173 PHY_LEVELLING_FAILURE_SR Name Reset Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 10 PHY_REG_RDLVL_INC_FAIL 0x0 Incremental read leveling fail status flag for each PHY data slice 1 Incremental read leveling test has failed 0 Incremental read leveling test has passed 9 5 PHY_REG_WRLVL_INC_FAIL 0x0 Incremental write leveling fail status flag for each PHY data slice 1 Incremental write leveling test has failed 0 Incremental write leveling test has passed 4 0 PHY_REG_GATELVL_INC_FAIL 0x0 Incremental gate leveling fail status flag for each PHY data slice 1 Incremental gate leveling test has failed 0 Incremental gate leveling test has passed PHY_BIST_ERROR_1_SR Table 7 174 PHY BIST ERROR 1 SR Bit Reset Number Name Value Descriptio
31. Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQS_RATIO 0x0 31 16 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS PHY_WRLVL_DQS_RATIO_3_SR Table 7 179 PHY_WRLVL_DQS_RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQS_RATIO 0x0 47 32 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS PHY_WRLVL_DQS_RATIO_4_SR Table 7 180 PHY WRLVL DQS RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_WRLVL_DQS_RATIO 0x0 49 48 bits of PHY_REG_WRLVL_DQS_RATIO Ratio value generated by the write leveling FSM for write DQS 348 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces Us
32. The PCIe protocol can be run on a maximum of 2 serial physical lanes in Regular and Reverse modes LaneO and lane1 of SERDESIF can be used for PCle Lane2 and lane3 can be used for running user defined protocol through EPCS interface from fabric PCle SGMII The PCIe protocol can be run on a maximum of 2 serial physical lanes in Regular and Reverse modes LaneO and lane1 of SERDESIF can be used for PCle Lane3 can be used for running SGMII In this mode lane2 is not used SmartFusion2 SoC FPGA Serial Protocols Overview The SERDESIF block supports implementing multiple high speed serial protocols Although each of the serial protocols are unique all of them are layered protocol stacks and the implementation can vary greatly from one layer to the next layer Typically the physical layer consists of fixed functionality that is common to multiple packet based protocols while the upper layers tend to be more customizable Revision 1 7 I Microsemi SERDESIF Block Figure 1 2 shows the functional partitioning of the physical and the upper layers of the high speed serial protocols Upper Layer Functionality Aggregation and processing scheduling bridging memory management etc Digital Logic Sub block Encode decode link state machines scrambling alignment CTC PCS Physical Layer gt PMA Electrical Sub block SERDES CDR I O Figure 1 2 Serial Protocol Partitioning Laye
33. These windows are used for address translation Endpoint interrupt registers These registers are used in Endpoint mode to manage interrupts Root port interrupt registers These registers are used in Root Port mode to manage interrupts These registers are not used in SmartFusion2 SoC FPGA PCIe implementation e PCle control and status Registers These read only registers enable the local processor to check useful information related to the PCle interface status This enables the local processor to detect when the bridge s PCle interface is initialized and to monitor PCI link events e Configuration registers These registers are used in Root Port mode only to perform a configuration write or read on the PCle bus Input Output control registers These registers are used in Root Port mode only to perform an I O write or read on the PCle bus These registers are not used in SmartFusion2 SoC FPGA PCle implementation Information Registers The registers listed in Table 2 10 provide device system and bridge identification information Table 2 10 Information Registers Address Register Register Name Offset Type Description VID_DEVID 000h R W or RO Identifies the manufacturer of the device or application See the PCle specification for details CLASS_CODE 008h R W or RO Identifies the manufacturer of the device or application See the PCle specification for details CAPTURED_BUS_DEVICE_NB 03Ch Reports the bus and device n
34. and densities as shown in Table 7 1 and Table 7 2 on page 240 If SECDED mode is enabled it is required to connect a memory module to 36 34 data lines of MDDR according to the width x32 x16 or x8 Table 7 1 Supported Memory Configurations for M25050 M2S080 M2S125 Width Memory Type Memory Density Width in SECDED mode LPDDR1 DDR2 DDR3 128M x32 x36 v v v x16 x18 v v v x8 x9 v v v 256M x32 x36 v v v x16 x18 v V v x8 x9 v v 512M x32 x36 v v v x16 x18 v y v x8 x9 v v v 1G x32 x36 v y v x16 x18 v v v x8 x9 v v v 2G x32 x36 x16 x18 v v v x8 x9 v V v Note The unsupported memories shown can be connected to MDDR and accessed by leaving the additional address lines of DDR SDRAM Revision 1 239 I Microsemi MSS DDR Subsystem Table 7 2 Supported Memory Configurations for M25025 M2S010 M2S005 Width Memory Type Memory Density Width in SECDED mode LPDDR1 DDR2 DDR3 128M x16 x18 v v v PBC a T y Te ay T a A 256M x16 x18 v v v x8 x9 v y v 512M x16 x18 v v v x8 x9 v v v 1G x16 x18 v v v x8 x9 v y v 2G x16 x18 v v v me TS ae Or TE DE 4G x16 x18 x8 x9 v v v Note The unsupported memories shown can be connected to MDDR and accessed by leaving the additional address lines of DDR SDRAM Performance Table 7 3 DDR speeds Data Rate Mbps Memory Type M
35. b0 PCIe mode 1 b1 External PCS mode CONFIG_EPCS_SEL 3 External PCS selection associated with lane3 CONFIG_EPCS_SEL 2 External PCS selection associated with lane2 CONFIG EPCS SEL 1 External PCS selection associated with lane1 CONFIG_EPCS_SEL 0 External PCS selection associated with laneO CONFIG_LINK2LANE 3 0 This signal is used in PCle mode to select the association of lane to link The four bits refer to four lanes Notes 1 XAUI 10 Gbps attachment unit interface 2 EPCS External physical coding sub layer 3 SGMII Serial Gigabit Media Independent Interface 4 Bits not shown here are unused 68 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 2 5 describes the settings to be done for the three SERDESIF system registers to force the SERDESIF into XAUI mode Table 2 5 PCle Mode Settings Using SERDESIF System Register CONFIG_PHY_MODE CONFIG_EPCS_SEL CONFIG_LINK2LANE 4 bits per lane 1 bit per lane 1 bit per lane MODE LaneO lane1 Lane2 Lane3 laneO Lane1 Lane2 Lane3 LaneO Lane1 Lane2 Lane3 PCle only mode x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 PCle only mode x2 0x0 0x0 OxF OxF 0x0 0x0 0x1 0x1 0x1 0x1 0x0 0x0 PCle only mode x1 0x0 OxF OxF OxF 0x0 0x0 0x1 0x1 0x1 0x0 0x0 0x0 PCle only mode with 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Lane rever
36. be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY WR DQS SLAVE RATIO 2 CR Table 7 148 PHY WR DQS SLAVE RATIO 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY WR DQS SLAVE RATIO OxO 31 16 bits of REG PHY WR DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 Revision 1 335 I Microsemi MSS DDR Subsystem PHY_WR_DQS_SLAVE_RATIO_3_CR Table 7 149 PHY_WR_DQS_SLAVE_RATIO_3 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 47 32 bits of REG_
37. continued Address Register Reset Register Name Offset Type Source Description DDRC LUE SYNDROME 5 SR 0x100 RO PRESET_N DDRC last uncorrected error syndrome register DDRC_LUE_ADDRESS_1_SR 0x104 RO PRESET_N DDRC last uncorrected error address register DDRC LUE ADDRESS 2 SR 0x108 RO PRESET_N DDRC last uncorrected error address register DDRC_LCE_SYNDROME_1_SR 0x10C RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 2 SR 0x110 RO PRESET NIDDRC last corrected error syndrome register DDRC_LCE_SYNDROME_3_SR 0x114 RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 4 SR 0x118 RO PRESET NIDDRC last corrected error syndrome register DDRC LCE SYNDROME 5 SR 0x11C RO PRESET_N DDRC last corrected error syndrome register DDRC LCE ADDRESS 1 SR 0x120 RO PRESET_N DDRC last corrected error address register DDRC LCE ADDRESS 2 SR 0x124 RO PRESET NIDDRC last corrected error address register DDRC LCB NUMBER SR 0x128 RO PRESET NIDDRC last corrected bit number register DDRC LCB MASK 1 SR 0x12C RO PRESET NIDDRC last corrected bit mask status register DDRC_LCB_MASK_2_SR 0x130 RO PRESET NIDDRC last corrected bit mask status register DDRC_LCB_MASK_3_SR 0x134 RO PRESET NIDDRC last corrected bit mask status register DDRC_LCB_MASK_4_SR 0x138 RO PRESET NIDDRC last corrected bit mask status register DDRC_ECC_INT_SR 0x13C RO PRESET_N DDR
38. data Revision 1 349 lt gt Microsemi MSS DDR Subsystem PHY_WRLVL_DQ_RATIO_4_SR Table 7 184 PHY_WRLVL_DQ_RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_WRLVL_DQ_RATIO 0x0 49 48 bits of PHY_REG_WRLVL_DQ_RATIO Ratio value generated by the write leveling FSM for write data PHY_RDLVL_DQS_RATIO_1_SR Table 7 185 PHY RDLVL DQS RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_DQS_RATIO 0x0 15 0 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM PHY RDLVL DQS RATIO 2 SR Table 7 186 PHY RDLVL DQS RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY REG RDLVL DQS RATIO 0x0 31 16 bits of PHY REG R
39. gt Microsemi enabled only if the DDR_FIC is configured for AHB mode FPGA fabric FPGA Fabric AHB Master AHB Master Interface 0 Interface 1 SmartFusion2 MSS Cache Controller Write Combining Buffers Arbiter and AHB Bus Matrix Read Buffers MSS DDR Bridge WCB and Read Buffers DDR Bridge DDR_FIC MDDR Subsystem Figure 9 3 MDDR Subsystem DDR Bridge and MSS DDR Bridge Architecture Revision 1 397 lt gt Microsemi DDR Bridge Figure 9 4 FDDR Subsystem DDR Bridge The DDR bridge implemented in the FDDR subsystem provides an interface between user implemented AHB masters in the FPGA fabric as shown in Figure 9 4 The DDR bridge in the FDDR subsystem is enabled only if the DDR_FIC is configured for AHB mode SmartFusion2 FPGA Fabric AHB AHB Master Master Interface 0 Interface 1 WCB and Read Buffers Arbiter DDR Bridge FDDR Subsystem FDDR Subsystem DDR Bridge Architecture Functional Description 398 The DDR bridge consists of two main components read and write combining buffers and an arbiter as shown in Figure 9 4 Master Interface 0 is a read only interface It allows the cache controller D and IC buses to read data from the read buffer through a 32 bit or 128 bit AHB bus Master Interface 1 is a read write port allowing the Cortex M3 Debugger access to external DDR memory and allowi
40. impedance calibrator results aZCompOp 1 impedance calibrator result is greater than nominal and aZCompOp 0 impedance calibrator result is less than nominal signal can be checked for stability after impedance calibration control values aZCalib modification aZCompOp 1 when Impedance calibrator result gt nominal 0 when Impedance calibrator result lt nominal This is used for TX RX and RX equalization calibration Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready POWER DOWN Register Table 5 17 POWER DOWN Bit Number Name Reset Value Description 7 6 RXIDLE_MSB These bits are used as the MSBs of the activity detector logic to specify that no activity has been detected during up to 61 aTXClkp clock cycles These bits are the two MSBs the rxidle_max 3 0 field of Reg02 represents the LSB part 5 FORCE_SIGNAL 4 FORCE_IDLE When this bit is set the PHY disables the Idle detection circuitry and forces signal detection on the receiver This bit is generally always set to disable 0 unless the activity detector logic must be bypassed In that case the PMA control logic will always report activity detected on the link when set to 1 This bit can be used for instance if the activity detector of the SERDES PMA hard macro does not work for the selected protocol as outside range of functionality When this
41. one bit of this signal defines whether the external PCS interface is used or the PCle PCS is enabled 0b PCle mode 1b External PCS mode For instance the mapping associated to a four lane PHY is epcs_sel 0 External PCS selection associated to laneO epcs sel 1 External PCS selection associated to lane1 epcs_sel 2 External PCS selection associated to lane2 epcs sel 3 External PCS selection associated to lane3 34 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg2C CONFIG_PHY_MODE_2 Register 0x202C Table 1 21 CONFIG PHY MODE 2 Bit Reset Number Name Value Description 7 0 CONFIG REXT SEL 0x0 For each lane 2 bits of this signal select whether the Tx Rx and Rx equalization calibration is performed by the PMA control logic of the lane or use the calibration result of adjacent lane upper or lower lanes 00b perform calibration using the lane calibration algorithm which also requires that the Rext resistor is present on board 01b use calibration result of lower lane 10b use calibration result of upper lane 11b reserved Note All the register are 32 bit Bits not shown in the table are reserved Reg30 CONFIG_PCIE_0 Register 0x2030 Table 1 22 CONFIG PCIE 0 Bit Reset Number Name Value Description 31 16 PCIE DEVICE ID 0x0 Specifies hardwired settings for PCle identification registers
42. or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected Revision 1 219 I Microsemi Serializer Deserializer CUSTOM_PATTERN_79_72 Register Table 5 116 CUSTOM PATTERN 79 72 Bit Number Name Reset Value Description 220 7 0 Note RX PWRDN 79 72 This register enables bit 79 to bit 72 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected Revision 1 Table 5 117 CUSTOM PATTERN CTRL I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s
43. same N value is applied to both RX and TX PLL Note This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under reset CNT250NS_MAX Register Table 5 9 CNT250NS MAX Bit Reset Number Name Value Description 7 0 CNT250NS MAX This register defines the base count of a 250 ns event based on the aTXClk clock This counter is used by the CDR PLL in PCS driven mode and also by the PMA control logic for operations such as receiver detect and electrical idle 2 and 3 states In the case of a non integer value the base count should be rounded up Note that this register must be set correctly for all protocols Note This register must only be reprogrammed when the PHY is under reset for proper operation It impacts the PCS driven CDR PLL mode as well as calibration and thus has no effect after calibration is completed PMA is ready or if the PHY CDR PLL is used in PMA driven mode Revision 1 191 I Microsemi Serializer Deserializer RE_AMP_RATIO Register Table 5 10 RE AMP RATIO Bit Reset Number Name Value Description 7 0 RE AMP RATIO This register defines the RX equalization amplitude ratio where the maximum value of 8 d128 corresponds to 100 If RX equalization is not used this register can be set to zero Note This register can be reprogrammed during normal operation but the effect will only appear when the parameters
44. 0 ATXDRP_DYN 15 8 This register defines bit 15 to bit 8 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver ATXDRP_DYN_20_16 Register Table 5 59 ATXDRP DYN 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRP DYN 20 16 This register defines bit 20 to bit 16 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver ATXDRA DYN 7 0 Register Table 5 60 ATXDRA DYN 7 0 Bit Number 7 0 Name ATXDRA DYN 7 0 Reset Value Description This register defines bit 7 to bit 0 of the transmitted A parameter sent to the PHY for driving differential data on the transmit driver Table 5 61 e ATXDRA DYN 15 8 ATXDRA DYN 15 8 Register Bit Reset Number Name Value Description 7 0 ATXDRA DYN 15 8 This register defines bit 15 to bit 8 of the transmitted A parameter sent to the PHY for driving differential data on the transmit driver ATXDRA DYN 20 16 Register Table 5 62 ATXDRA DYN 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRA DYN 20 16 This register defines bit 20 to bit 16 of the transmitted A parameter sent to the PHY for driving differential data on the transmit driver ATXDRT_DYN_7_0 Register Table 5 63 ATXDRT_DYN_7_0 Bit Reset Number Name Value Descriptio
45. 0 ENDCALIB_MAX This register defines the amount of time in microseconds required by the PMA to settle its electrical level after loading electrical idle 1 in the TX driver at the end of calibration Note that all operations are automatically performed by the PMA control logic but that the SERDES transmitter can start driving data on the link immediately after end of calibration By default except if forbidden by protocol a 10 us delay between end of calibration and mission mode is set but any value might work as well Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready Revision 1 193 I Microsemi Serializer Deserializer CALIB_STABILITY_COUNT Register Table 5 16 CALIB STABILITY COUNT Bit Number Name Reset Value Description 7 5 CALIB SETTLE MAX This register defines the amount of time in microseconds required by the PMA to settle its electrical level after loading electrical idle 1 in the TX driver at the end of calibration Note that all operation is automatically performed by the PMA control logic but that the SERDES transmitter can start driving data on the link immediately after end of calibration By default except if forbidden by protocol a 10 us delay between end of calibration and mission mode is set but any value might work as well 4 0 CALIB STABLE MAX This register defines the number of clock cycles before which the
46. 0 This register reports the result of RX impedance calibration RE SWEEP CENTER Register Table 5 54 RE SWEEP CENTER Bit Reset Number Name Value Description 7 RE VAL This register defines whether the PMA has completed the RX equalization calibration signaling and that the result of RX equalization calibration re sweep center 6 0 is valid 6 0 RE SWEEP CENTER 6 0 This register reports the result of RX equalization calibration ATXDRR 7 0 Register Table 5 55 ATXDRR 7 0 Bit Reset Number Name Value Description 7 0 ATXDRR 7 0 This register defines the LSB of the RX impedance and RX equalization computed value to send to the PMA after computation ATXDRR 14 8 Register Table 5 56 ATXDRR 14 8 Bit Reset Number Name Value Description 7 RSVD Reserved 6 0 ATXDRR 14 8 This register defines the MSB of the RX impedance and RX equalization computed value to send to the PMA after computation ATXDRP DYN 7 0 Register Table 5 57 ATXDRP DYN 7 0 Bit Reset Number Name Value Description 7 0 ATXDRP DYN 7 0 This register defines bit 7 to bit 0 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver Revision 1 205 I Microsemi Serializer Deserializer Table 5 58 e ATXDRP_DYN_15_8 ATXDRP_DYN_15_8 Register Bit Reset Number Name Value Description 7
47. 0 next 11 bits are for data slice 1 etc 328 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_GATELVL_INIT_RATIO_2_CR Table 7 130 PHY GATELVL INIT RATIO 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_GATELVL_INIT_RATIO 0x0 31 16 of REG PHY GATELVL INIT RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY GATELVL INIT RATIO 3 CR Table 7 131 PHY GATELVL INIT RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_GATELVL_INIT_RATIO 0x0 47 32 of REG_PHY_GATELVL_INIT_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY_GATELVL_INIT_RATIO_4_CR Table 7 132 PHY GATELVL INIT RATIO 4 CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a re
48. 1 If unused can be left PCIE x RXDN3 PCIE x TXDPO Output I O Pads Transmit data SERDES differential positive output PCIE x TXDP1 Each SERDESIF consists of 4 TX signals Here x 0 for SERDESIF 0 and x 1 for SERDESIF 1 If unused can be left PCIE x TXDP2 floating PCIE x TXDP3 PCIE x TXDNO Output I O Pads Transmit data SERDES differential negative output PCIE x TXDN1 Each SERDESIF consists of 4 TX Signals Here x 0 for Pp SERDESIF_0 and x 1 for SERDESIF 1 If unused can be left PCIE_x_TXDN2 floating PCIE_x_TXDN3 PCIE_x_REXTL Reference I O Pads External reference resistor connection to calibrate TX RX termination value Each SERDESIF consists of 2 REXT signals one for lanes 0 and 1 and another for lanes 2 and 3 Here x 0 for PCIE_x_REXTR SERDESIF_0 and x 1 for SERDESIF 1 If unused can be left floating PCIE_x_REFCLKOP Input I O Pads Reference clock differential positive Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not PCIE_x_REFCLK1P activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF 1 If unused can be left floating PCIE_x_REFCLKON Input I O Pads Reference clock differential negative Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF 1 If u
49. 1 microsecond per switch If the ASPM L1 acceptable latency is lower than the maximum ASPM L1 exit latency then ASPM L1 entry will not be enabled TIMEOUT_COMPLETION 068h R W or RO This signal defines four timeout ranges for the completion timeout mechanism 86 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Address Mapping Registers The registers listed in Table 2 13 provide the address mapping for AXI master and slave windows These windows are used for address translation Table 2 13 Address Mapping Registers es meron O Register Name Offset Type Description RO or There are four register sets that define the address R W mapping for AXI slave window 0 There are four register sets that define the address mapping for AXI slave window 1 There are four register sets that define the address mapping for AXI slave window 2 There are four register sets that define the address mapping for AXI slave window 3 There are four register sets that define the address mapping for AXI master window 0 There are four register sets that define the address mapping for AXI master window 1 RO or There are four register sets that define the address R W mapping for AXI master window 2 Revision 1 87 I Microsemi PCI Express Table 2 13 Address Mapping Registers Address Register Register Name Offset Type Description AXI MASTER WINDOW3 0 130h RO or There
50. 31 6 K CNT CONFIGO 31 6 If k fix 30 1 these bits are hardwired to their default values If k fix 30 0 the bits are reserved 5 2 K CNT CONFIGO 5 2 If k fix 30 1 these bits are hardwired to their default values If k fix 30 0 the bits are defined The configurable power down timeout sets the maximum time in ms allowed for the PHY to acknowledge a power down transition This timeout prevent an LTSSM freeze caused by a missing PHY acknowledge after a power down request The default value of 0 means that no timeout is used 1 0 K_CNT_CONFIGO_1_0 MSBs of the latency setting these bits set the latency for the assertion of the PIPE signal TXELECIDLE after the electrical idle order set EIOS is sent K CNT CONFIG 1 Register 304h Table 2 119 K CNT CONFIG 1 Bit Reset Number Name Value Description 31 30 K CNT CONFIG1 31 30 LSBs of the latency setting These bits set the latency for the assertion of the PIPE signal TXELECIDLE after the electrical idle order set EIOS is sent 29 15 K CNT CONFIG1 29 15 These bits set the timeout value for the replay timer When set to 0 the core defaults to the PCle Specification value 14 0 K CNT CONFIG1 14 0 These bits set the timeout value for the ACK latency timer When set to 0 the core defaults to the PCle Specification value K CNT CONFIG 2 Register 308h Table 2 120 K CNT CONFIG 2
51. 47 40 0X2B8 PRBS_ERR_CYC_FIRST_49_48 0x00 RO PRBS last error cycle counter register bits 49 48 OX2BC Reserved 0X400 188 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDES Block Register Bit Definitions The following tables give bit definitions for the registers present in the SERDES block registers CRO Control Register 0 Table 5 3 CRO Bit Number Name Reset Value Description 7 AUTO_SHIFT Defines whether the electrical idle 1 pattern is automatically shifted in the SERDES macro after loading the drive pattern When set to 1 electrical idle or Drive mode can be entered within a single aTXClkp clock cycle When set to 0 23 clock cycles are required to dynamically switch between electrical idle and Drive mode In general this bit is always set to 1 FORCE_RX_DETECT Forces the result of PCle receiver detect operation to be always detected This register can be used on unreliable results of RX detect operations When set to 1 the result of the PCle receiver detect operation is always positive and thus makes the PHY non compliant to PCle 5 4 CDR_REFERENCE These two bits are used to define the CDR reference PLL mode By default these two bits must be set to 00 when aRefClk is used for the CDR reference clock PMA_DRIVEN_MODE This bit puts the CDR PLL in PMA driven mode When set to 0 the PCS driven mode is
52. 7 85 DDRC LUE ADDRESS 2 SR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 12 DDRC REG ECC BANK 0x0 Bank where the SECDED error occurred Only present in designs that support SECDED 11 0 DDRC REG ECC COL 0x0 Column where the SECDED error occurred Col 0 is always set to 0 coming out of the controller This bit is overwritten by the register module and indicates whether the error came from upper or lower lane Only present in designs that support SECDED DDRC LCE SYNDROME 1 SR Table 7 86 DDRC LCE SYNDROME 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 15 0 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data
53. 8 MDDR SMC AXI M WSTRB Out Indicates which byte lanes to update in memory 4 MDDR SMC AXI M ARID Out Indicates identification tag for the read address group of signals 32 MDDR SMC AXI M ARADDR Out Indicates initial address of a read burst transaction 410 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 10 2 SMC FIC AXI 64 Port List continued Width Port Name Direction Description 4 MDDR_SMC_AXI_M_ARLEN Out Indicates burst length The burst length gives the exact number of transfers in a burst 0000 1 0001 0010 0011 0100 0101 0110 0111 1000 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 OMNAUPRVVN 2 MDDR SMC AXI M ARSIZE Out Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 2 MDDR SMC AXI M ARBURST Out Indicates burst type The burst type coupled with the size information details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved 32 MDDR SMC AXI M AWADDR Out Indicates write address The write address bus gives the address of the first transfer in a write burst transaction 2 MDDR SMC AXI M
54. ACJTAG REG 1 0 PRBS TYP 1 0 This 2 bit register contains the ACJTAG register of the PHY which is loaded when update of the PMA settings is required through a Reg128 transient write operation or any other load request such as initial loading This register defines the type of PRBS pattern which is applied PRBS7 when set to 00 PRBS11 when set to 01 PRBS23 when set to 10 PRBS31 when set to 11 LPBK EN When set the PMA is put in near end loopback serial loopback from TX back to RX PRBS tests can be done using the near end loopback of the PMA some load board or any far end loopback implemented in the opposite component When near end loopback bit is set the idle detector always reports valid data enabling the PCS driven CDR PLL locking logic to lock on input data 0 PRBS_GEN When set this signal starts the PRBS pattern transmission Note This register can be programmed any time but has functional impact because it can configure the SERDES in loopback or generate the PRBS pattern PRBS_ERRCNT Register Table 5 104 PRBS ERRCNT Bit Reset Number Name Value Description 7 0 PRBS ERRCNT 7 0 This test reports the number of PRBS errors detected when the PRBS test is applied This register is automatically cleared when the PRBS EN register is cleared requiring testing the value of this register when the test is running The PRBS error counter saturates at 254 errors the 2
55. AHB master implemented in fabric 1 AXI 64 bit AXI master implemented in fabric 1 CFGR AXI AHB MASTER 0x1 Defines whether AXI AHB master interface is implemented on the master interface to fabric 0 AHB 32 bit AHB slave implemented in fabric 1 AXI 64 bit AXI slave implemented in fabric Table 1 15 CONFIG ECC INTR ENABLE Reg14 CONFIG ECC INTR ENABLE Register 0x2014 Bit Number Name Reset Value Description 7 4 CFGR PCIE ECC INTR EN Ox7 This bit sets ECC interrupt enable for PCle Tx Rx and Rp memories Bit 0 1 Rp ECC interrupt enabled 0 ECC interrupt disabled Bit 1 1 Rx ECC interrupt enabled 0 ECC interrupt disabled Bit 2 1 Tx ECC interrupt enabled 0 ECC interrupt disabled 3 0 CFGR_PCIE_ECC_EN 0x7 This bit sets ECC enable for PCle Tx Rx and Rp memories Bit 0 1 Rp ECC enabled 1 b0 ECC disabled Bit 1 1 b1 Rx ECC enabled 1 b0 ECC disabled Bit 2 1 b1 Tx ECC enabled 1 b0 ECC disabled 32 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg18 Reserved 0x2018 Table 1 16 Reg18 Bit Reset Number Name Value Description 0x0 Note All the register are 32 bit Bits not shown in the table are reserved Reg1C Reserved 0x201C Table 1 17 Reg1C Bit Reset Number Name Value Description 0x0
56. AWSIZE Out Indicates the maximum number of data bytes to transfer in each data transfer within a burst 00 1 01 2 10 4 11 8 2 MDDR SMC AXI M AWLOCK Out Indicates lock type This signal provides additional information about the atomic characteristics of the write transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved Revision 1 411 I Microsemi Soft Memory Controller Fabric Interface Controller Table 10 2 SMC FIC AXI 64 Port List continued Width Port Name Direction Description 2 MDDR SMC AXI M ARLOCK Out Indicates lock type This signal provides additional information about the atomic characteristics of the read transfer 00 Normal access 01 Exclusive access 10 Locked access 11 Reserved 4 MDDR SMC AXI M BID In Indicates response ID The identification tag of the write response The MDDR SMC AXI M BID value must match the MDDR SMC AXI M AWID value of the write transaction to which the slave is responding 4 MDDR SMC AXI M RID In Read ID tag This signal is the ID tag of the read data group of signals The MDDR SMC AXI M RID value is generated by the slave and must match the MDDR SMC AXI M ARID value of the read transaction to which it is responding 2 MDDR SMC AXI M RRESP In Indicates read response This signal indicates the status of the read transfer 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 De
57. Bit Reset Number Name Value Description 7 0 FORCE ATXDRP 7 0 This register defines bit 7 to bit 0 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set FORCE_ATXDRP_15_8 Register Table 5 89 FORCE_ATXDRP_15_8 Bit Reset Number Name Value Description 7 0 FORCE ATXDRP 15 8 This register defines bit 15 to bit 8 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as reg81 bit 0 is not set FORCE ATXDRP 20 16 register Table 5 90 FORCE ATXDRP 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 FORCE ATXDRP 20 16 This register defines bit 20 to bit 16 of the transmitted P parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set Revision 1 211 I Microsemi Serializer Deserializer FORCE ATXDRA 7 0 Register Table 5 91 FORCE ATXDRA 70 Bit Reset Number Name Value Description 7 0 FORCE ATXDRA 7 0 This register defines bit 7 to bit 0 of the transmit
58. Bit Reset Number Name Value Description 31 24 K CNT CONFIG2 31 24 These bits set the flow control timeout check in units of 1 us 23 21 K CNT CONFIG2 23 21 Not used 20 16 K CNT CONFIG2 20 16 These bits set update flow control credit timer in units of 1 us 15 11 K CNT CONFIG2 15 11 These bits set LOs L1 entry latency in units of 256 ns 10 6 K CNT CONFIG2 10 6 These bits set FC init timer in units of 256 ns 5 0 K CNT CONFIG2 5 0 Reserved Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide K_CNT_CONFIG 3 Register 30Ch Table 2 121 K CNT CONFIG 3 Bit Reset Number Name Value Description 31 21 K CNT CONFIG3 31 21 These bits set the SKP OS scheduling counter 20 1 K CNT CONFIG3 210 These bits set the recovery speed counter It counts 1 ms using UCLK when the LTSSM state is Recovery Speed applies to 5 0 Gbps configuration speed only See the PCIe specification for more information 0 K CNT CONFIG3 0 MSB of power down transition delay counter It delays the transition to power down phase when a TXELECIDLE signal is asserted in states where the RXELECIDLE signal is not used such as LOs detect disable and hot reset The recommended value of this counter is 10 K_CNT_CONFIG 4 Register 310h Table 2 122 K CNT CONFIG 4 Bit Reset Number Name Value Description 31 25 K CNT CONFIG4 31 25 LSBs of power dow
59. CDR PLL calibration and the voltage offset cancellation mechanism Figure 5 3 shows a simplified functional block diagram of the PMA macro Each of the PMA macro blocks includes three main sub functions Transmitter TX macro e Receiver RX macro e Clock PLL macro Beacon Driver Beacon Data Far End Rx Detect Amplitude Pre and Post Cursor Settings Transmit Macro TX Data Serializer TX Div TXDN Baud Clk TX Clk aTXCikp ees Tx CIk heap TX PL fg O00 TTTTTTTTTIA IATA TETTE eee Stable REXT Impedance Calibrator L Reference Clock Ref Clk Stable Skip Bit Rx Div H 16 Baud Clk t RX Clk aRXClkp RXDP Reciever with CTLE RXDN Rx Data Activity Detect lt T Schmitt Out Equilization Control AC JTAG Out lt D oO O 2 lt o Figure 5 3 Block Diagram of PMA Macro Block Revision 1 171 I Microsemi Serializer Deserializer 172 TX Macro The TX macro receives 8 bit 16 bit or 20 bit maximum 20 bit dataword synchronous with a TX clock serialized into a single stream of differential transmitted data transmitted to the lane The transmitter supports multi level output drive and multi level transition pre and post cursor emphasis while maintaining proper impedance Refer to the SERDES Block Register section on page 183 for details RX Macro The RX macro receives the serialized data from the lane deserializes this into 10 bit or 20 bit maximum 20 bit digital
60. Capability Structure Table 2 139 illustrates the content of the SSID SSVID capability structure Table 2 139 SSID SSVID Capability Structure Register 31 24 23 16 15 8 7 0 Byte Offset Reserved Next cap PTR Capability ID OCOh SSID SSVID OC4h Virtual Channel Capability Structure Table 2 140 shows the virtual channel capability structure for Function 0 Table 2 140 Virtual Channel Capability Register PCle AER Extended Capability Structure Table 2 141 shows the advanced error reporting AER extended capability structure for Function 0 For Functions 1 7 the byte offset is from 100h to 134h Table 2 141 PCle AER Extended Capability Structure 31 24 23 16 15 8 7 0 Byte Offset Next cap PTR Vers Extended cap ID 100h Port VC cap 1 104h VAT offset VC arbit cap 108h Port VC status Port VC control 10Ch PAT offset 0 31 24 VC resource capability register 0 110h VC resource control register 0 114h VC resource status register 0 Reserved 118h 31 24 23 16 15 8 7 0 Byte Offset PCle enhanced capability header 800h Uncorrectable error status register 804h Uncorrectableerrormaskregister 808h Uncorrectable error severity register 80Ch Correctable error status register 810h Correctable error mask register 814h Advanced error capabilities and control register 818h Header log register 81Ch Root er
61. DDRC DRAM Read Write Precharge Timing register 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 19 DDR Controller Configuration Register continued Address Register Reset Register Name Offset Type Source Description DDRC_DRAM_MR_TIMING_PARAM_CR 0x05C RW PRESET_N DDRC DRAM Mode Register Timing Parameter register DDRC_DRAM_RAS_TIMING_CR 0x060 RW PRESET_N DDRC DRAM RAS Timing Parameter register DDRC DRAM RD WR TRNARND TIME CR 0x064 RW PRESET_N DDRC DRAM Read Write Turn around Timing register DDRC DRAM T PD CR 0x068 RW PRESET N DDRC DRAM Power Down Parameter register DDRC DRAM BANK ACT TIMING CR 0x06C RW PRESET_N DDRC DRAM Bank Activate Timing Parameter register DDRC_ODT_PARAM_1_CR 0x070 RW PRESET_N DDRC ODT Delay Control register DDRC ODT PARAM 2 CR 0x074 RW PRESET_N DDRC ODT Hold Block cycles register DDRC ADDR MAP COL 3 CR 0x078 RW PRESET Nl Upper byte is DDRC Column Address Map register and lower byte controls debug features DDRC MODE REG RD WR CR 0x07C RW PRESET_N DDRC Mode Register Read Write Command register DDRC_MODE_REG_DATA_CR 0x080 RW PRESET_N DDRC Mode Register Write Data Register DDRC_PWR_SAVE_1_CR 0x084 RW PRESET N DDRC Power Save register DDRC PWR SAVE 2 CR 0x088 RW PRESET_N DDRC Power Save register DDRC ZQ LONG TIME CR 0x08C RW PRESET_N DDRC ZQ Long T
62. Feda d kar F Cee de KEEAR GE An Sa REE eee Hee PS 177 SERDES Testing Operation ui o4 ete Pande BA a eke Seven ee bs pee eee ea eee ea eee 179 SERDES Block Register sura ee tie een awed iceae nee Eee eae ke Aa ranere 183 SERDESIF 1 O Signal Int rtace eicere ered ei Sanwa ia PE RA ee OE ie Fae BA 230 GIOSSALY vase bebe eek kjeden hes embede Pee SEE bed eee eee ne ete be 233 Revision 1 3 lt gt Microsemi Table of Contents 6 DDR Controller 41444044 s kb oak can ene a amides ceed ay ea alba dad vie 235 Address Mapping oc eccoci ceci 0022 eee bla erik Seed doe ee eee 235 T MSS DDR SUDSYSIEM vs c4a8 cid seres erter pene ead Sed Eee NEEN RENT ai 237 Introdueti n es rense e D a ea ee eee Et easier ete er Abete 237 MDDR Subsystem Overview c ii cecerssisiiccrsdict idr nents 238 Functional Deserniptibn 2241 23 sees dee dini ee piatat a aie a a a EAEE EEEE EDE E Keke aeaa EO 240 MDDR Configurations eeestis e re ea e se E a E ee E bed ie ork ee eh ceded 243 DDR PHY irer PE De A OEE 250 Memory Initialization eriseeria edd en tiene lade bbe edhe ehh g Pekar been ee 252 Data Flow Paths rocce centope en anara Renna ore Ree AR aete MOEA seed mete a a teen dad ed 253 MDDR Memory M p 20 sone Gin ein se eked ske ee Sa ae ee ee ee a A 259 DDR Memory Device Examples 222 02 0600 00 ee cede kj eee eee eee eRe 262 Register Interlace avstand AR Shen one eeu ete 265 CE EE es edt be n EE E 371 8 Fabric Double Data Rate Subsystem 0 6
63. Guide CREDIT ALLOCATION 1 Register 0B4h Table 2 61 CREDIT ALLOCATION 1 Bit Reset Number Name Value Description 31 28 CREDIT ALLOCATION1 31 28 Reserved 27 16 CREDIT ALLOCATION1 27 16 VCO non posted header data credit npd credO 15 8 CREDIT ALLOCATION1 15 8 Reserved 7 0 CREDIT ALLOCATION1 7 0 VCO non posted header data credit nph credO CREDIT ALLOCATION 2 Register 0B8h Table 2 62 CREDIT ALLOCATION 2 Bit Reset Number Name Value Description 31 0 Reserved Reserved CREDIT ALLOCATION 3 Register OBCh Table 2 63 CREDIT ALLOCATION 3 Bit Reset Number Name Value Description 31 0 Reserved Reserved AXI SLAVE WINDOWO 0 Register 0COh Table 2 64 AXI SLAVE WINDOWO 0 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOWOO 31 12 Base address AXI slave window 0 11 0 Reserved AXI SLAVE WINDOWO 1 Register 0C4h Table 2 65 AXI SLAVE WINDOWO 1 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOWO1 31 12 Size of AXI Slave window 0 11 1 AXI SLAVE WINDOWO1 31 12 Reserved 0 AXI SLAVE WINDOWO1 0 Enable bit of AXI slave window 0 Revision 1 105 lt gt Microsemi PCI Express AXI_SLAVE_WINDOWO 2 Register 0C8h Table 2 66 AXI SLAVE WINDOWO 2 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOWO2 31 12 LSB of base address PCle
64. Guide CUSTOM PATTERN CTRL Register Bit Number Name Reset Value Description 7 RSVD 6 CUST AUTO When this register is set the word alignment is performed automatically by a state machine that checks whether the received pattern is word aligned with the transmitted pattern and automatically use the PMA CDR PLL skip bit function to find the alignment Once the word alignment is detected the custom pattern checker is now word aligned and the custom pattern checker can be enabled for detecting and counting any error over time CUST SKIP CUST CHK This register is used in RX word alignment manual mode The custom pattern requires word alignment in order to be checked by the receiver as opposed to a PRBS pattern which does not require this word alignment function In manual mode read the CUST SYNC register in order to check whether the word is aligned If not in manual mode a one bit skip is to the CDR PLL must be done by writing one then zero in this register and repeat this sequence until the receiver is aligned This register enables the error counter When clear it also resets the error counter Thus the error counter must be checked before clearing this register 3 1 CUST_TYP This register defines whether the custom pattern generated on the link is generated by the custom pattern register or by one of the hard coded patterns 000 Custom pattern register 100 All zero pattern 0
65. Guide DDRC LUE SYNDROME 4 SR Table 7 82 e DDRC LUE SYNDROME 4 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 63 48 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CR is written over by the system Revision 1 305 I Microsemi MSS DDR Subsystem DDRC_LUE_SYNDROME_5_SR Table 7 83 DDRC_LUE_SYNDROME_5_SR Bit Reset Number Name Value Description 16 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi
66. HRESP M_BVALID Input AXI master mode BVALID Fabric M_BREADY Output AXI master mode BREADY Fabric M_ARIDJ 3 0 Output AXI master mode ARID Fabric M ARADDR 31 0 Output AXI master mode ARADDR Fabric M ARLEN 3 0 Output AXI master mode ARLEN Fabric M ARSIZE 1 0 Output AXI master mode ARSIZE Fabric 118 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 2 124 PCle System AXI AHBL Master Interface continued Port Type Description Connected to M ARBURST 1 0 Output AXI master mode ARBURST Fabric M ARVALID Output AXI master mode ARVALID Fabric M ARREADY Input AXI master mode ARREADY Fabric M RID 3 0 Input AXI master mode RID Fabric M RDATA HRDATA 63 0 Input AXI master mode RDATA Fabric AHBL master mode HRDATA M RRESP 1 0 Input AXI master mode RRESP Fabric M_RLAST Input AXI master mode RLAST Fabric M_RVALID Input AXI master mode RVALID Fabric M_RREADY Output AXI master mode RREADY Fabric Table 2 125 PCle System AXI AHBL Slave Interface Port Type Description Connected to S_AWID_HSEL Input AXI slave mode AWID Fabric S_AWADDR_HADDR Input AXI slave mode AWADDR Fabric AHBL slave mode HADDR S_AWLEN_HBURST Input AXI slave mode AWLEN Fabric AHBL slave mode HBURST S_AWSIZE_HSIZE Input AXI slave mode AWSIZE Fabric AHBL
67. High Speed Serial and DDR Interfaces User s Guide In Single protocol mode the x4 EPCS interface is available to the FPGA fabric and in Multi protocol mode the x2 EPCS interface is available to the fabric PMA Hard PMA Lane 3 Macro Control Logic EPCS Interface x2 EPCS INTERFACE PMA Hard PMA Lane 2 Macro Control Logic EPCS Interface PMA Control Common Logic Registers PMA Hard PMA Lane 1 Macro Control Logic x2 EPCS EPCS Interface INTERFACE PMA Hard PMA Lane 0 Macro Control Logic EPCS Interface 32 APB Interface EPCS Implementation of the SERDESIF Block in Single Protocol Mode Figure 4 1 shows the SERDESIF block internal architecture during the EPCS Single protocol mode The SmartFusion2 SoC FPGA EPCS mode facilitates to use 4 lanes of the SERDES exposed to the FPGA fabric with a 20 bit EPCS interface You have full control over the PLL configurations in the SERDES using APB interface to generate the required serial link frequencies This EPCS interface is suitable to run any protocol MAC and PCS in the FPGA fabric and uses the PMA macro for implementing any standard SRIO INTERLAKEN etc or user defined serial protocol SERDESIF System Registers for EPCS Mode Three SERDESIF System registers need to be configured to implement the EPCS interface The three registers that define the mode of operation of the SmartFusion2 SoC FPGA SERDESIF module are 1 CONFIG PHY MODE 2 CONFIG EPCS SEL 3 CONFIG_LINKK2
68. If not lanes are used for any serial protocol Tie it to high APB_S_PRESET_N Input Fabric Asynchronous set signal for APB slave interface EPCS 0 RESET N Input Fabric External EPCS interface mode External PCS EPCS 1 RESET N reset control laneO and lane1 EPCS 0 RX RESET N Output Fabric External EPCS interface mode laneO and EPCS 1 RX RESET N lane1 Clean reset deasserted on rxcik EPCS 0 TX RESET N Output Fabric External EPCS interface mode laneO and EPCS 1 TX RESET N lane1 Clean reset deasserted on txclk PLL SERDESIF RESET Output SPLL SPLL reset output PLL SERDESIF PD Output SPLL SPLL power down enable Table 1 53 SERDESIF Block Clock Interface Connected Port Type To Description CLK BASE Input Fabric Fabric source clock In PCle mode this is the reference clock of the SPLL PLL output clock pll acik is used as AXI AHB bridge clock APB 8 PCLK Input Fabric PCLK for APB slave interface in the SERDESIF REFCLK 100 Input I O Pads Clock input to be used as reference clock of PMA for Tx PLL REFCLK 101 Input I O Pads Clock input to be used as reference clock of PMA for Tx PLL CCC REF CLK Input CCC PMA ref clock source direct from CCC 44 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 53 e SERDESIF Block Clock Interface continued Connected Port Type To Description FAB_REF_CLK Input Fabric PMA ref clock
69. Microsemi PCI Express AXI SLAVE WINDOW3 0 Register OFOh Table 2 76 AXI SLAVE WINDOW3 0 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW30 31 12 Base address AXI slave window 3 11 0 Reserved AXI SLAVE WINDOWB3 1 Register 0F4h Table 2 77 AXI SLAVE WINDOW 3 1 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW31 31 12 Size of AXI slave window 3 11 1 AXI SLAVE WINDOW1 31 12 Reserved 0 AXI SLAVE WINDOW31 0 Enable bit of AXI slave window 3 AXI SLAVE WINDOW3 2 Register OF8h Table 2 78 AXI SLAVE WINDOW3 2 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW32 31 12 LSB of base address PCIe window 3 11 5 AXI SLAVE WINDOW32 11 5 Reserved 4 2 AXI SLAVE WINDOW32 4 2 AXI slave window 0 traffic class TC 1 AXI SLAVE WINDOW32 1 AXI Slave window 0 relaxed ordering RO 0 AXI SLAVE WINDOW32 0 AXI Slave window 0 no snoop NS AXI SLAVE WINDOW3 3 Register 0FCh Table 2 79 AXI SLAVE WINDOW3 3 Bit Reset Number Name Value Description 31 0 AXI SLAVE WINDOW33 31 12 MSB of base address PCle window 0 AXI MASTER WINDOWO 0 Register 100h Table 2 80 AXI MASTER WINDOWO 0 Bit Number 31 12 Name AXI MASTER WINDOWOO 31 12 Reset Value Description Base address AXI master window 0 11 0 Reserved Reserved 108 Revision 1
70. Mode Figure 3 5 shows the reference clock selection in high speed serial Interface generator available in Libero SoC It sets the MUX selection depending on the selected reference clocks 156 25 MHz clock should be fed in as the reference clock to SERDES 4 PMAs in the XAUI mode Protocol 1 Type xau v Protocol 1 Number of Lanes x4 Protocol 1 Speed 3 125 Gbps v Protocol 1 PHY Reference Clock REFCLKO v REFCLK1 Fabric SERDES Reference Clock using High Speed Serial Interface Generator XAUI Mode Clock Network In the XAUI mode data is exchanged from soft IP in the fabric and XAUI extender inside SERDESIF block Figure 3 6 shows in the XAUI clocking scheme The 156 25 MHz reference clock to SERDES PMA for Tx PLL and CDR PLL can be selected as explained in the previous section The PLLs generate 156 25 MHz clocks and send 4 Rx and 4 Tx clocks through the EPCS interface Note The PLL settings are calculated automatically by the Libero SoC device when the XAUI protocol mode is selected The LaneO Tx clock is MUXed and fed into as reference clock of SPLL and XAUI extender block This is done to reduce the skew between the fabric and SmartFusion2 Soc FPGA SERDESIF module The 4 Rx clocks are fed into the XAUI extender block where lane de skewing is done and only one Rx clock is given out to the FPGA fabric The APB clock APB S PCLK is an asynchronous clock used for SERDESIF register access Revision 1 135 I Microsemi
71. Name Value Description 31 12 AXI MASTER WINDOW31 31 12 Size of AXI master window 3 11 1 AXI MASTER WINDOW1 31 12 Reserved 0 AXI MASTER WINDOW31 0 Enable bit of AXI master window 3 Revision 1 111 lt gt Microsemi PCI Express AXI MASTER WINDOW3 2 Register 138h Table 2 94 AXI MASTER WINDOW 3 2 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW32 31 12 LSB of base address PCIe window 3 11 5 AXI MASTER WINDOW32 11 5 Reserved 5 0 AXI MASTER WINDOW32 50 These bits set the BAR To select a BAR set the following values 0x01 BARO 32 bit BAR or BARO 1 64 bit BAR 0x02 BAR1 32 bit BAR only 0x04 BAR2 32 bit BAR or BAR2 3 64 bit BAR 0x08 BAR3 32 bit BAR only 0x10 BAR4 32 bit BAR or BAR4 5 64 bit BAR 0x20 BARS 32 bit BAR only AXI MASTER WINDOW3 3 Register 13Ch Table 2 95 AXI MASTER WINDOW3 3 Bit Reset Number Name Value Description 31 0 AXI MASTER WINDOW33 31 12 MSB of base address PCle window 0 IMASK Register 140h Table 2 96 IMASK Bit Reset Number Name Value Description 31 0 IMASK 310 Reserved ISTATUS Register 144h Table 2 97 ISTATUS Bit Reset Number Name Value Description 31 0 ISTATUS 310 Reserved ICMD Register 148h Table 2 98 ICMD Bit Reset Number Name Value Description 31 0 ICMD 310 Reserved IRTATUS Register 14Ch
72. PHY WR DATA SLAVE FORCE CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_WR_DATA_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for write data slave DLL with the value of the REG PHY WR DATA SLAVE DELAY bus bit 4 is for PHY Data slice 4 bit 3 for PHY Data slice 3 and so on Revision 1 337 I Microsemi MSS DDR Subsystem PHY_WR_DATA_SLAVE_RATIO_1_CR Table 7 155 PHY WR DATA SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY WR DATA SLAVE RATIO 0x0040 15 0 bits of REG PHY WR DATA SLAVE RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 PHY_WR_DATA_SLAVE_RATIO_2_CR Table 7 156 PHY WR DATA
73. PHY control slice DLL slave force register PHY CTRL SLAVE DELAY CR 0x22C RW PRESET NI PHY control slice DLL slave delay register PHY DATA SLICE IN USE CR 0x230 RW PRESET NI PHY control slice in use register PHY LVL NUM OF DQO0 CR 0x234 RW PRESET N PHY receiver on off control register PHY DQ OFFSET 1 CR 0x238 RW PRESET N Selection register of offset value from DQS to DQ PHY DQ OFFSET 2 CR 0x23C RW PRESET NlSelection register of offset value from DQS to DQ PHY DQ OFFSET 3 CR 0x240 RW PRESET_N Selection register of offset value from DQS to DQ PHY DIS CALIB RST CR 0x244 RW PRESET N Calibration reset disabling register PHY DLL LOCK DIFF CR 0x248 RW PRESET N Selects the maximum number of delay line taps PHY FIFO WE IN DELAY 1 CR 0x24C RW PRESET N Delay value for FIFO WE PHY FIFO WE IN DELAY 2 CR 0x250 RW PRESET N Delay value for FIFO WE PHY FIFO WE IN DELAY 3 CR 0x254 RW PRESET N Delay value for FIFO WE PHY FIFO WE IN FORCE CR 0x258 RW PRESET_N Overwriting delay value selection reg for FIFO WE PHY FIFO WE SLAVE RATIO 1 CR 0x25C RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 2 CR 0x260 RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 3 CR 0x264 RW PRESET N Ratio value for FIFO WE slave DLL PHY FIFO WE SLAVE RATIO 4 CR 0x268 RW PRESET N Ratio value for FIFO WE slave DLL PHY GATELVL INIT MODE CR 0x26C RW PRESET_N Init ratio selection registe
74. PRESET N AXI S RMW CORE RESET N CLK BASE DDR FAB PLL LOCK SDRAM SmartFusion2 FER Figure 8 6 e FDDR with AXI interface Configuring from MSS Master 380 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide 2 Single AHB Interface The FDDR subsystem can be used to access DDR SDRAM as shown in Figure 8 7 DDR SDRAM can be DDR2 DDR3 or LPDDR1 depending on the FDDR configuration The FDDR has an APB interface to configure the registers The configuration can be done through the MSS or user logic APB master in the FPGA fabric The read and write transactions are initiated by the AHB master which can be user logic in the FPGA fabric or FIC FPGA Fabric AHB Master APB Master User Logic Logic APB S PCLK APB S PRESET N CORE RESET N CLK BASE FAB PLL LOCK FDDR SmartFusion2 Figure 8 7 FDDR with Single AHB Interface Revision 1 381 I Microsemi Fabric Double Data Rate Subsystem Figure 8 8 3 Dual AHB Interface The FDDR subsystem can be used to access DDR SDRAM memory as shown in Figure 8 8 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the FDDR configuration FDDR has an APB interface to configure the registers The configuration can be done through the MSS or user logic APB master in the FPGA fabric The read and write transactions are initiated by the AHB masters which can be user logic in the FPGA fabric or FIC Both th
75. REG DDRC T ZQ LONG NOP to perform full calibration and the transfer of values The ZQ calibration short ZQCS command is used to perform periodic calibration to account for voltage and temperature variations A shorter timing window is provided to perform calibration and transfer of values as defined by timing parameter tZQCS REG DDRC T ZQ SHORT NOP No other activities are performed by the controller for the duration of tZQinit and tZQCS The quiet time on the DRAM channel helps in accurate calibration of DRAM Ron and ODT All banks are precharged and tRP met before ZQCL or ZQCS commands are issued by the controller Automatic ZQCS by the controller In this case the controller sends ZQCS commands to the DRAM periodically The interval is determined by the REG DDRC T ZQ SHORT INTERVAL X1024 register Explicit Auto Precharge per command Configure REG DDRC DIS COLLISION PAGE OPT to enable or disable auto precharge on a per command basis Revision 1 249 I Microsemi MSS DDR Subsystem ODT Controls The ODT for a specific rank of memory can be enabled or disabled by configuring the DDRC_ODT_PARAM_1_CR and DDRC_ODT_PARAM_2_CR registers These must be configured before taking the controller out of soft reset they are then applied to every read or write issued by the controller DDR PHY 250 The DDR PHY processes read and write requests from the DDR controller and translates them into specific signals within the tim
76. Range 0 to 11 Internal Base 8 for row address bit 2 9 for row address bit 3 10 for row address bit 4 15 for row address bit 9 16 for row address bit 10 17 for row address bit 11 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 3 0 REG_DDRC_ADDRMAP_ROW_B12 0x0 Selects the address bit used as row address bit 12 Valid Range 0 to 11 and 15 Internal Base 18 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 12 is set to 0 276 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_ADDR_MAP_ROW_2_CR Table 7 31 DDRC ADDR MAP ROW 2 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 REG DDRC ADDRMAP ROW B13 0x0 Selects the address bits used as row address bit 13 Valid range 0 to 11 and 15 Internal base 19 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 13 is set to 0 7 4 REG DDRC ADDRMAP ROW B14 0x0 Selects the address bit used as row address bit 14 Valid range 0 to 11 and 15 Internal base 20 The selecte
77. Refresh Control register DDRC DYN REFRESH 2 CR 0x00C RW PRESET_N DDRC Refresh Control register DDRC_DYN_POWERDOWN_CR 0x010 RW PRESET NIDDRC Power Down Control register DDRC DYN DEBUG CR 0x014 RW PRESET_N DDRC Debug register DDRC_MODE_CR 0x018 RW PRESET_N DDRC Mode register DDRC_ADDR_MAP_BANK_CR 0x01C RW PRESET NIDDRC Bank Address Map register DDRC ECC DATA MASK CR 0x020 RW PRESET NIDDRC SECDED Test Data register DDRC ADDR MAP COL 1 CR 0x024 RW PRESET_N DDRC Column Address Map register DDRC ADDR MAP COL 2 CR 0x028 RW PRESET N DDRC Column Address Map register DDRC ADDR MAP ROW 1 CR 0X02C RW PRESET_N DDRC Row Address Map register DDRC_ADDR_MAP_ROW_2_CR 0x030 RW PRESET_N DDRC Row Address Map register DDRC_INIT_1_CR 0x034 RW PRESET_N DDRC Initialization Control register DDRC_CKE_RSTN_CYCLES_1_CR 0x038 RW PRESET_N DDRC Initialization Control register DDRC CKE RSTN CYCLES 2 CR 0x03C RW PRESET_N DDRC Initialization Control register DDRC INIT MR CR 0x040 RW PRESET_N DDRC MR Initialization register DDRC_INIT_EMR_CR 0x044 RW PRESET_N DDRC EMR Initialization register DDRC_INIT_EMR2_CR 0x048 RW PRESET_N DDRC EMR2 Initialization register DDRC_INIT_EMR3_CR 0x04C RW PRESET_N DDRC EMR3 Initialization register DDRC_DRAM_BANK_TIMING_PARAM_CR 0x050 RW PRESET N DDRC DRAM Bank Timing Parameter register DDRC DRAM RD WR LATENCY CR 0x054 RW PRESET N DDRC DRAM Write Latency register DDRC DRAM RD WR PRE CR 0x058 RW PRESET_N
78. Register 050h Table 2 35 AER ECRC CAPABILITY Bit Reset Number Name Value Description 31 3 AER ECRC CAPABILITY 31 3 Reserved 2 AER ECRC CAPABILITY 2 This register defines whether advanced error reporting AER is implemented or not 1 AER ECRC CAPABILITY 1 This register defines ECRC generation 0 AER ECRC CAPABILITY 0 This register defines ECRC check VC1 CAPABILITY Register 054h Table 2 36 VC1 CAPABILITY Bit Reset Number Name Value Description 31 0 Reserved Revision 1 95 lt gt Microsemi PCI Express MAX PAYLOAD SIZE Register 058h Table 2 37 MAX PAYLOAD SIZE Bit Reset Number Name Value Description 31 3 Reserved 2 0 MAX PAYLOAD SIZE 2 0 This register bits sets the payload size Permitted values are 000 128 bytes 001 256 bytes 010 512 bytes 011 1 Kbytes 100 2 Kbytes CLKREQ Register 05Ch Table 2 38 CLKREQ Bit Reset Number Name Value Description 31 1 CLKREQ 31 1 Reserved 0 CLKREQ 0 When set to 1 the ExpressCard CLKREQ is implemented This bit is tied to 0 ASPM_LOS_CAPABILITY Register 05Ch Table 2 39 ASPM LOS CAPABILITY Bit Reset Number Name Value Description 31 ASPM LOS CAPABILITY 31 NFTS COMCLK in common clock mode 23 16 ASPM LOS CAPABILITY 23 16 NFTS SPCLK in separated clock mode 15 10 ASPM LOS CAPABILITY 15 10 Reserved 9 7 ASPM LOS CAPABILITY 9 7 LO
79. Reserved 2 FINE GRAIN COARSE GRAIN In PCS driven mode when this register is set it enables forcing the CDR PLL state machine in fine grain state In this state the CDR PLL locks on receive data making RX data and RX CLOCKP valid on the PMA interface When set this register enables forcing the CDR PLL state machine when used in PCS driven mode see Reg00 bit 3 set to 0 in coarse grain state In this state the CDR PLL performs a coarse grain lock on receive data enabling adjustment of its clock up to 5000 PPM FREQ_LOCK When set this register enables forcing the CDR PLL state machine when used in PCS driven mode see Reg00 bit 3 set to 0 in frequency lock state In this state the CDR PLL does not lock on receive data but on the reference clock 224 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide UPDATE SETTINGS Register Table 5 125 UPDATE SETTINGS Bit Reset Number Name Value Description 7 0 UPDATE SETTINGS 7 0 This register is a transient register read always reports 0 where writing a 1 in bit 0 will trigger a new computation of PMA settings based on the value written in register space registers Note that for PCle Microsemi recommends not using this command register when the link is not transitioning to low power state or changing rate Note This register can be programmed any time except d
80. SCALE 3 25 24 These bits set the register that defines data scale 7 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 23 18 PM DATA SCALE 3 23 18 Reserved 17 16 PM DATA SCALE 3 17 16 These bits set the register that defines data scale 6 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 15 10 PM DATA SCALE 3 15 10 Reserved 9 8 PM DATA SCALE 3 98 These bits set the register that defines data scale 5 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 7 2 PM DATA SCALE 3 7 2 Reserved 1 0 PM DATA SCALE 3 10 These bits set the register that defines data scale 4 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field MSI 0 Register 080h Table 2 48 MSI 0 Bit Reset Number Name Value Description 31 27 MSIO 31 27 These bits set MSI Offset 3 of MSI MAPO 26 24 MSIO 26 24 These bits set MSI TC 1 of MSI MAPO 23 19 MSIO 23 19 These bits set MSI Offset 3 of MSI MAPO 18 16 MSIO 18 16 These bits set MSI TC 3 of MSI MAPO 15 11 MSIO 15 11 These bits set MSI Offset 2 of MSI MAPO 10 8 MSIO 10 8 These bits set
81. SERDES Macro Register i Lane 0 1 KB 0x1000 PCle Core i Bridge Register m 4 KB x Ti i 0x0000 Figure 1 14 SERDESIF Memory Map 26 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Figure 1 15 shows the APB implementation of three region configurations and status registers The APB interface is used to interfaces with FPGA fabric which will allow access to these register region as an APB slave The address decoder block generates the appropriate PSEL and manages the access to these regions of configuration and status registers SERDESIF a APB Se SERDESIF System A Register P B PCle SYSTEM l N T APB 32 gt PCle Core Register Q E og R AG F Q A SERDES C E APB 32 APB to SERDES SERDES Macro Interface Register Figure 1 15 Address Decoder Logic Block Diagram SERDESIF System Register The SERDESIF system register memory map occupies 1 KB of configuration memory map Physical offset location of the SERDESIF system registers is 0x2000 0x23FF from the SERDESIF block memory map Table 1 9 describes the SERDESIF system registers Table 1 9 SERDESIF System Registers Address Register Register Name Offset Type Description SER_PLL_CONFIG_LOW 0x00 R W Sets SERDES PLL configuration bits LSBs SER_PLL_CONFIG_HIGH 0x04 R W Sets SERDES PLL configuration bits MSB
82. Speed Speed Speed bits per bits per bits per bits per PHY MODE Protocol second Protocol second Protocol second Protocol second Single Protocol PCIe 2 5G Pele Link mode PCle 25G PCle 25G z PCle 2 5G PCle 2 5G PCle 25G PCle 256G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G Single Protocol PCle 2 5 G PCle Link Reversed mode 7 PCIe 25G PCle 25G PCle 5G PCle 5G PCle 5G Multi Protocol PCle 2 5G EPCS EPCS FOG mete PCle 25G PCle 25G EPCS EPCS z PCle 5G EPCS EPCS PCle 5G PCle 5G EPCS EPCS Multi Protocol PCle 2 56 EPCS EPCS PCIe Link Reversed mode peje 25G PCle 25G EPCS EPCS z PCle 5G EPCS EPCS PCle 5G PCle 5G EPCS EPCS Note Lane3 EPCS interfaces are available in multi protocol PHY mode and can be used for running SGMII protocols Revision 1 11 I Microsemi SERDESIF Block XAUI Protocol The SERDES block in SERDESIF can be configured to support multiple serial protocols The SERDES block can be configured to bypass the PCS functionality and connect to the XAUI extender block and use the 10 GbE XAUI protocol with a soft IP block in the FPGA Note lanes and it does not support any other protocol When the SERDESIF block is configured to support XAUI it occupies all the four physical serial
83. System Registers in EPCS Mode Register Name Address Offset Register Type Description SER_PLL_CONFIG_HIGH 0x04 R W Bit 11 and bit 16 of the SERDES PLL configuration are used It is recommended to keep the SPLL in reset and power down state as the SPLL is not used in EPCS mode SER_SOFT_RESET CONFIG PHY MODE 0 0x08 0x24 R W R W All 6 bits are used for soft reset Since the PCle and XAUI IPs are not used it is recommended to put them into reset state In EPCS mode each SERDES lane can be put into the reset state depending on the requirement For each lane this signal selects the protocol default settings of the PHY which sets the reset value of the registers space Refer to CONFIG PHY MODE in Table 4 4 on page 156 for further details CONFIG PHY MODE 1 Ox 28 R W Selects PCS mode link to lane settings Refer to CONFIG EPCS SEL in Table 4 4 on page 156 for further details CONFIG PHY MODE 2 REFCLK SEL Ox2C 0x64 R W R W Sets the equalization Calibration is performed by the PMA control logic of the lane or the calibration result of the adjacent lane LANEO1 REFCLK SEL and LANE23_REFCLK_SEL bits are used for the reference clock selection for the four lanes of the PMA PCLK_SEL 0x68 R W PIPE_PCLKIN_LANE01_SEL and PIPE PCLKIN LANE23 SEL bits are used for the PIPE clock input selection for the lanes EPCS_RSTN_SEL Ox6C R W Th
84. TT TT TT UDQS LDQS MDDR DQS N 1 0 PITT TT TT UDQSH LDQS MDDR DQ 15 0 ate eee DQ 15 0 MDDR DM RDQS 3 2 MDDR DQS 3 2 MDDR DQS N 3 2 MDDR DQ 31 16 MT47H64M16 CASN CKE CLK P CLK N CSN ODT RASN WEN ADDR 12 0 BA 2 0 DM UDQS LDQS UDQS LDQS DQ 15 0 Figure 7 10 x16 DDR2 SDRAM Connected to MDDR 262 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Figure 7 11 shows DDR3 SDRAM connected to the MDDR of a SmartFusion2 SoC FPGA device Micron s MT41J512M8RA is a 512 MB density device with x8 data width The MDDR is configured in full bus width mode with SECDED enabled The SDRAM connected to MDDR DQ 36 32 is used to store SECDED bits The total amount of DDR3 memory excluding memory for SECDED connected to MDDR is 2 GB MDDR_PADS MDDR_CAS_N MDDR_CKE MDDR_CLK MDDR_CLK_N MDDR_CS_N MDDR_ODT MDDR_RAS_N MDDR_RESET_N MDDR_WE_N MDDR_ADDR 15 0 MDDR BA 2 0 CASN CKE CLK P CLK N CSN ODT RASN RSTN WEN ADDR 15 0 BA 2 0 MDDR DM RDQS 0 DM DQS DQSH DQ 7 0 Figure 7 11 x8 DDR3 SDRAM Connection to MDDR Revision 1 MT41J512M8RA MT41J512M8RA MT41J512M8RA MT41J512M8RA DQ 3 0 MT41J512M8RA 263 I Microsemi MSS DDR Subsystem Figure 7 12 shows LPDDR1 SDRAM connected to the MDDR of a SmartFusion2 SoC FPGA device The micron s MT46H32M16LF is a 64 MB density device with x16 data width The MDDR is conf
85. User s Guide BAR1 Register 014h Table 2 20 BAR1 Bit Number Name Reset Value Description 31 4 BAR1 31 4 0x000000 The register defines the type and size of BAR1 of the PCle native endpoint 3 BAR1 3 0x0 Identifies the ability of the memory space to be prefetched 2 1 BAR1 2 1 0x00 Set to 00 to indicate anywhere in 32 bit address space 0 BAR1_0 0x0 Memory space indicator BAR2 Register 018h Table 2 21 BAR2 Bit Number Name Reset Value Description 31 4 BAR2_31_4 0x000000 The register defines the type and size of BARO of the PCle native endpoint 3 BAR2_3 Ox1 Identifies the ability of the memory space to be prefetched 2 1 BAR2 2 1 0x10 Set to 00 to indicate anywhere in 32 bit address space 0 BAR2_0 0x0 Memory space indicator BAR3 Register 01Ch Table 2 22 BAR3 Bit Number Name Reset Value Description 31 4 BAR3_31_4 0x000000 The register defines the type and size of BAR1 of the PCIe native endpoint 3 BAR3_3 0x0 Identifies the ability of the memory space to be prefetched 2 1 BAR3 2 1 0x00 Set to 00 to indicate anywhere in 32 bit address space 0 BAR3_0 0x0 Memory space indicator BAR4 Register 020h Table 2 23 BAR4 Bit Number Name Reset Value Description 31 4 BAR4_31_4 0x000000 The register defines the type and size of BARO of the PCle native endpoint 3 BAR4_3 Ox1 Identifies the ability of the memory space to
86. WREADY AHB S HREADYOUT Output Fabric AXI Slave mode WREADY AHBL Slave mode HREADY AXI S BID Output Fabric AXI Slave mode BID AXI S BRESP AHB S HRESP 1 0 Output Fabric AXI Slave mode BRESP AHBL Slave mode HRESP AXI S BVALID Output Fabric AXI Slave mode BVALID AXI S BREADY AHB S HREADY Input Fabric AXI Slave mode BREADY AHBL Slave mode HREADY AXI 8 ARID 3 0 Input Fabric AXI Slave mode ARID AX _S_ARADDR 31 0 Input Fabric AXI Slave mode ARADDR AXI 8 ARLEN 3 0 Input Fabric AXI Slave mode ARLEN AXI 8 ARSIZE 1 0 Input Fabric AXI Slave mode ARSIZE AXI 8 ARBURST 1 0 Input Fabric AXI Slave mode ARBURST AXI S ARVALID Input Fabric AXI Slave mode ARVALID AXI 8 ARLOCK 1 0 Input Fabric AXI Slave mode ARLOCK AXI S ARREADY Output Fabric AXI Slave mode ARREADY AXI 8 RID S 0 Output Fabric AXI Slave mode RID AXI S RDATA AHB S HRDATA 63 0 Output Fabric AXI Slave mode RDATA 63 0 AHBL Slave mode HRDATA 31 0 AXI 8 RRESP 1 0 Output Fabric AXI Slave mode RRESP AXI 8 RLAST Output Fabric AXI Slave mode RLAST AXI 8 RVALID Output Fabric AXI Slave mode RVALID AXI S RREADY Input Fabric AXI Slave mode RREADY Table 1 56 SERDESIF Block APB Slave Interface Connected Port Type To Description APB 8 PCLK Input Fabric APB Slave interface PCLK APB 8 PRESET N In Fabric APB Slave interface PRESETN Async set APB_S_PSEL Input Fabric APB Slave interface PSEL APB_S_PENABLE Input
87. XAUI Note SPLL is used to reduce the skew between the fabric and SmartFusion2 Soc FPGA SERDESIF module However it is required to connect the XAUI_CLK_OUT with XAUI_FDB_CLK signal in the fabric through global network as shown in Figure 3 6 Also it is needed to connect transmit and receive clock to XAUI soft IP RXDP TXDP RXDN TXDN 3 125 Ghz 3 125 Ghz FABRIC SERDES CLK_BASE Reference Clock 156 25 Mhz gt COR TX PLL PLL APB_S_PCLK 156 25 Mhz 156 25 Mhz TxClk x4 Clks RxCIk x4 Clks 156 25 Mhz RxClk x4 Clk ed Seat SERDESIF Extender Y 4to1 Mux 156 25 Mhz TxClk XAUI Soft E PLL_SERDESIF_REF deskew H5 SPLL p PLL_SERDESIF_FB deskew HM GB gt XAUI FDB CL K XAUI CLK OUT PLL ACLK Figure 3 6 e SPLL Clocking in XAUI Mode Figure 3 7 shows SPLL settings in high speed serial interface generator The SERDESIF system register can also be selected to configure and use this PLL PCIe xAUI Fabric SPLL Configuration CLK BASE Frequency MHz 20 Supply Voltage 2 5 y v Lock Delay 32 cycles v Lock Window 64000 ppm z Figure 3 7 SPLL Clocking Configuration Using High Speed Serial Interface Generator 136 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 5 summarizes the various clocks in the XA
88. XAUI TX RESE XAUI RX RESET epcs rstn 3 0 m Reset Glue Logic mdc_reset SERDES M tx_reset mstr_reset XAUI Extender RX_RESET 3 0 epcs ready 3 0 Figure 3 8 XAUI Reset Scheme 137 Revision 1 I Microsemi XAUI MDIO Interface Figure 3 9 shows a system block diagram that describes how the XAUI extender and an MDIO manageable device MMD are connected to a station management entity STA In this case the STA is the A XGMAC X To External Device FABRIC SERDESIF L gt XAUILMMD_MDI_EXT 10 Gig MAC STA XAUI_MMD_MDO hd gt XAUI_MMD_MDI XAUI Extender XAUI_MMD_MDOE_IN e gt XAUI_MMD_MDOE_IN XAUI_MMD_MDI XAUI_MMD_MDO XAUI MMD MDOE Figure 3 9 e MDIO System Block Diagram 138 XAUI Mode Loopback Test Operation The XAUI extender block can be placed in the Loopback mode for testing purpose It can be placed in multiple loopback operations XAUI Near End Loopback Test Bit 14 of Reg00 can be used to enable the Loopback When the Loopback mode is enabled the transmit output is shunted back into the receive input For the Loopback mode to work appropriately the transmit clock is also shunted back into the receive clock inputs The Loopback test data needs to be fed from the XGMII interface available to fabric XAUI Far End Loopback Test In the XAUI far end lo
89. application layer the receive and transmit channels the receive buffer and flow control FC credits e Data link layer The data link layer DLL is responsible for link management including transaction layer packet TLP acknowledgement a retry mechanism in case of a non acknowledged packet flow control across the link transmission and reception power management CRC generation and CRC checking error reporting and logging The PCle IP core also utilizes a clock domain crossing CDC synchronizer between the data link layer and the physical layer that enables the data link and transaction layers to operate at a frequency independent from that of the physical layer Revision 1 63 I Microsemi PCI Express 64 AXI Master Block The AXI master manages read and write transactions from the PCIe link Write Transaction Handling The write transaction is handled in Big Endian order as required by the PC Express Base Specification As PCle transactions can be any size up to the configurable maximum payload size 2 KB and AXI transactions are limited to 128 bytes a received TLP can be cut into several AXI transactions So when the AXI master receives a write transaction it processes the transaction by 128 byte segments aligned on a 128 byte address boundary until all of the segments in the transaction have been processed Read Transaction Handling Read transactions are handled the same way as write transactions except t
90. are four register sets that define the address AXI MASTER WINDOW3 134h R W mapping for AXI master window 3 AXI MASTER WINDOW3 2 138h AXI MASTER WINDOW3 3 13Ch PREFETCH 10 WINDOW 184h RO or This register sets the I O window type When BARs are R W used rather than windows this register is hardwired to 0 Endpoint Interrupt Registers The PCIe IP core can generate interrupts through the input signal This signal may be required by a device in order to interrupt the host processor call its device drivers or report application layer specific events or errors The input signal can be configured for as many as 32 different input interrupt sources The INT BITS parameter of the bridge defines the number of interrupt bits for this signal Table 2 14 Endpoint Interrupt Registers Address Register Register Name Offset Type Description MSI 0 080h RO or This register defines 8 MSI MAPO registers with up to R W 32 possible MSI messages MSI 1 084h RO or This register defines 8 MSI MAP1 registers with up to R W 32 possible MSI messages MSI 2 088h RO or This register defines 8 MSI MAP2 registers with up to R W 32 possible MSI messages MSI 3 08Ch RO or This register defines 8 MSI MAP3 registers with up to R W 32 possible MSI messages MSI 4 090h ROor This register defines 8 MSI_MAP4 registers with up to R W 32 possible MSI messages MSI 5 094h RO or This register defines 8 MSI MAP5 registers with up to R W 3
91. be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 0x0 15 0 bits of PHY_REG_STATUS_WR_DATA_SLA VE_DLL_VALUE Delay value applied to write data slave DLL PHY WR DATA SLAVE DLL VAL 2 SR Table 7 206 PHY WR DATA SLAVE DLL VAL 2 SR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_REG_STATUS_WR_DATA_SL AVE_DLL_VALUE Delay value applied to write data slave DLL PHY_WR_DATA_SLAVE_DLL_VAL_3_SR Table 7 207 PHY_WR_DATA_SLAVE_DLL_VAL_3_SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE 358 Revision 1 0x0 44 32 bits of PHY_REG_STATUS_WR_DATA_SL AVE_DLL_VALUE Delay value applied to write data slave DLL lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_FIFO_WE_SLAVE_DLL_VAL_1_SR Table 7 208 PHY_FIFO_WE
92. between activates to same bank specification 65 ns for DDR2 400 and smaller for faster parts Unit clocks 5 0 REG_DDRC_T_FAW 0x0 tFAW Valid only in burst of 8 mode At most 4 banks must be activated in a rolling window of tFAW cycles Unit clocks 280 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_DRAM_RD_WR_LATENCY_CR Table 7 40 DDRC DRAM RD WR LATENCY CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_DDRC_WRITE_LATENCY 0x0 Number of clocks between the write command to write data enable PHY 4 0 REG_DDRC_READ_LATENCY 0x0 Time from read command to read data on DRAM interface Unit clocks This signal is present for designs supporting LPDDR1 DRAM only It is used to calculate when the DRAM clock may be stopped Table 7 41 DDRC DRAM RD WR PRE CR DDRC DRAM RD WR PRE CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_DDRC_WR2PRE 0x0 Minimum time between write and prec
93. bit is set the PHY disables the Idle detection circuitry and forces electrical Idle detection on the receive side By default this bit is generally cleared and might be set only for very specific conditions or testing such as generating a fake loss of signal to the PCS or MAC layer forcing a retraining of word aligner or any training state machine As long as this bit is set the activity detector logic of the PMA control logic reports that no signal is detected on the receive side If CDR PLL PCS driven mode is selected the CDR PLL will be directed in lock to the reference clock state leading to potential wrong data received by the SERDES because the CDR PLL is not locked to incoming data Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready except for bit 2 which can only be modified under reset condition 194 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 5 17 POWER DOWN continued Bit Reset Number Name Value Description 3 NO FCMP When set this bit disables the frequency comparator logic of the PCS driven CDR PLL control logic When not set the frequency comparator logic is no longer part of the condition for going from fine grain lock state to frequency acquisition 2 PMFF_ALL When set this bit disables the function that waits for every active lane to hav
94. bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_FIFOWEIN_RATIO 0x0 15 0 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM PHY FIFO 2 SR Table 7 190 PHY FIFO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_FIFOWEIN_RATIO 0x0 31 16 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM PHY FIFO 3 SR Table 7 191 PHY FIFO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_RDLVL_FIFOWEIN_RATIO 0x0 47 32 bits of PHY REG RDLVL FIFOWEIN RATIO Ratio value generated by read gate training FSM Revision 1 351 I Microsemi MSS DDR Subsystem PHY FIFO 4 SR Table 7 192 PHY FIFO 4 SR Bit Number Name Reset Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
95. data from the SERDES Output PMA lepcs 3 rxdata 19 0 Fabric EPCS interface Lane3 received data from the SERDES Output PMA lepcs 0 rx val Output Fabric EPCS interface Lane0 receive data valid lepcs 1 rx val Output Fabric EPCS interface Lane1 receive data valid epcs 2 rx val Output Fabric EPCS interface Lane2 receive data valid lepcs 3 rx val Output Fabric EPCS interface Lane3 receive data valid lepcs 0 rx idle Fabric EPCS interface LaneO receive idle needed for SATA Output OOB lepcs 1 rx idle Fabric EPCS interface Lane1 receive idle needed for SATA Output OOB lepcs 2 rx idle Fabric EPCS interface Lane2 receive idle needed for SATA Output OOB lepcs 3 rx idle Fabric EPCS interface Lane3 receive idle needed for SATA Output OOB epcs 0 tx cik stable Output Fabric EPCS interface LaneO clock stable info epos 1 tx cik stable Output Fabric EPCS interface Lane1 clock stable info lepcs 2 tx cik stable Output Fabric EPCS interface Lane2 clock stable info epcs 3 tx cik stable Output Fabric EPCS interface Lane3 clock stable info lepcs 0 Rx RESET N Output Fabric EPCS interface Lane0 clean reset de asserted on EPCS 0 RX CLK lepecs 1 Rx RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS 1 RX CLK epos 2 Rx RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS 2 RX CLK lepecs 3 Rx RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS 3 RX CLK lepcs 0 TX RESET N Output Fabric EPCS interface
96. ekke EDE E aiaa ELE 408 SYSREG Control Register for SMC FIC 1 0 rv ae rare ranerne narr rakner 408 SMC FIC Port Diskuiorta rusker rene AA ka De DEE 409 GISSA makk pan FL kg Fe ted Bite hed eared Sane medeier ST ever bier 414 PESTO Cha ES saase ge TN O bee Bee 415 Be Product SUPPOr ssid aiii iaia i a a dad sal Abd tac diao A lana OG Reh ad Ga e eo a D dd den dd 417 CUSIOMCEN SEIVICE rs creis gree bees ene dte sad ioa Ei Keke Gy dk Roe nee Ed eee ees een bade 417 Customer Technical Support Center 0 0 teeta 417 T chnical Support sess seere bassen ecto heck odd ards aw ive Fae Die heidi g Patina bbe ero ee sae oh age 417 WEDS abt hereto Forres ave hnt BG hee oe sara nr 417 Contacting the Customer Technical Support Center 0 cee teas 417 ITAR Technical Support 2 ee ee ee bee ee ee eee eee 418 4 Revision 1 lt gt Microsemi 4 SERDESIF Block SmartFusion 2 system on chip SoC field programmable gate array FPGA high speed serial interface also known as SERDESIF integrates functionality to support multiple high speed serial protocols The protocols supported in SmartFusion2 SoC FPGA devices are peripheral component interconnect express PCI Express eXtended attachment unit interface XAUI and serial gigabit media independent interface SGMII In addition any user defined high serial protocol implemented in the SmartFusion2 SoC FPGA fabric can access SERDES lanes through the external physical coding sublay
97. even if the request has not been sent because of a lack of credit or a higher priority transaction for example Read Transaction Handling Read transactions are only accepted if at least 128 bytes of buffer space is available in the receive buffer If the read request is accepted the PCle IP generates a PCle tag arbitrates between write requests and completions then checks for available FC credits on the decoded VC An error response is generated if a timeout occurs or if a completion with error status is received PCIe to AXI Window The PCle base IP receives both 32 bit address and 64 bit address PCle requests but only 32 bit address bits are provided to the AXI master The PCle to AXI address windows manage read and write requests from the PCIe link and are used to translate a PCle 32 bit or 64 bit base address to a 32 bit AXI base address transaction AXI to PCle Window The AXI to PCle address windows are used to translate a transaction s 32 bit AXI base address to a PCle 32 bit or 64 bit base address in order to generate a PCle TLP Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PCle Bridge Registers The PCle bridge registers configure all configuration registers and associated functions Refer to the PCle Core Bridge Register Space section on page 83 for more details Most bridge registers are configured to a fixed value during power up whereas the control a
98. for details XAUI Clocking In XAUI only mode the Tx clock is generated from the PMA The laneO Tx clock is used for this purpose The Rx clock for all four lanes is passed to the XGXS receiver block with gating logic in between for low power operation Refer to the XAUI section on page 129 for details Revision 1 23 I Microsemi SERDESIF Block Reset for SERDESIF Block The SERDESIF block has the following RESETs at the top level Table 1 8 lists the reset signals These signals are exposed to fabric based on the protocol implemented in the SERDESIF block Refer to the PCI Express section on page 59 the XAUI section on page 129 and the EPCS Interface section on page 153 for more information on using these reset signals Table 1 8 e SERDESIF Block Reset Signals Protocol Reset signals Direction Description PCle SERDESIF_CORE_RESET_N Input PCle core active low SERDESIF_PHY_RESET_N Input Active low SERDES reset If it is used for any serial the protocol should be tied to 1 b0 APB_S_PRESET_N Input APB slave interface asynchronous preset EPCS EPCS 0 RESET N Input EPCS interface LaneO reset EPCS 1 RESET N Input EPCS interface lane reset EPCS 2 RESET N Input EPCS interface lane2 reset EPCS 3 RESET N Input EPCS interface lane3 reset EPCS 0 RX RESET N Output EPCS interface LaneO reset deasserted onEPCS 0 RX CLK EPCS 1 RX RESET N Output EPCS interface LaneO
99. for the SERDES receiver are updated at the end of calibration or when Reg128 is programmed RE CUT RATIO Register Table 5 11 RE CUT RATIO Bit Reset Number Name Value Description 7 0 RE CUT RATIO This register defines the RX equalization cut frequency ratio used in the computation of Rn 3 0 and Rd 3 0 equalization settings of the PMA macro The encoding of this register is such that Rn Rd RE CUT RATIO 256 W SETTING where W SETTING is the result of RX equalization calibration Note This register can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES receiver are updated at the end of calibration or when Reg128 is programmed TX AMP RATIO Register TX amplitude ratio Table 5 12 TX AMP RATIO Bit Reset Number Name Value Description 7 0 TX AMP RATIO This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden Note that for PCle this register is used for Gen1 speed only Note This register can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated at the end of calibration on entry or exit of TX electrical idle or when Reg128 is programmed X_PST_RATIO Register Table 5 13 TX PST RATIO
100. future products the value of a reserved bit should be preserved across a a read modify write operation 15 12 REG_DDRC_ADDRMAP_COL_B8 0x0 Full bus width mode Selects column address bit 9 Half bus width mode Selects column address bit 11 Quarter bus width mode Selects column address bit 12 Valid range 0 to 7 and 15 Internal base 8 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 Note Per JEDEC DDR2 specification column address bit 10 is reserved for indicating auto precharge and hence no source address bit can be mapped to column address bit 10 11 8 REG DDRC ADDRMAP COL B9 0x0 Full bus width mode Selects column address bit 11 Half bus width mode Selects column address bit 12 Quarter bus width mode Selects column address bit 13 Valid range 0 to 7 and 15 Internal base 9 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 7 4 REG DDRC ADDRMAP COL B10 0x0 Full bus width mode Selects column address bit 12 Half bus width mode Selects column address bit 13 Quarter bus width mode Unused Should be set to 15 Valid range 0 to 7 and 15 Internal base 10 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 10 is set to 0 3
101. in the SERDESIF system block APB S PRDATA 5 1 LTSSM R 4 0 LTSSM state LTSSM state encoding Refer to LTSSM 28 24 register for more info APB S PRDATA 7 6 ERR PHY 1 0 PHY error Physical layer error bit0 Receiver port error bit1 Training error APB_S_PRDATA 12 8 ERR_DLL 4 0 DLL error Data link layer error bit0 TLP error bit1 DLLP error bit2 Replay timer error bit3 Replay counter rollover bit4 DLL protocol error APB S PRDATA 21 13 ERR TRN 8 0 TRN error Transaction layer error bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 Poisoned TLP received ECRC check failed Unsupported request Completion timeout Completer abort Unexpected completion Receiver overflow Flow control protocol error Malformed TLP 56 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 67 Debug Signals Mapping to APB Bus continued APB_PRDAT Signals Debug Signal Description APB_S_PRDATA 22 ERR_DL Error ACK NACK DLLP parameter This signal reports that the received ACK NACK DLLP has a sequence number higher than the sequence number of the last transmitted TLP APB_S_PRDATA 23 TIMEOUT LTSSM timeout This signal serves as a flag which indicates that the LTSSM timeout condition is reached for the current LTSSM state 1b1 Timeout condition reached 1b0 No time condition reached A
102. is invalidated If there is an error response from DDR for the other address reads the read entry is invalidated Figure 9 7 shows the flowchart for read operation Read Request 1 Other master is holding the read transfer Read buffer is empty read request Send read request to arbiter Make AHB Send read request to arbiter with burst Master ready high Initiate single read transfer Read address is size of read buffer size Read data matching with buffer from arbiter Make ready high Send tag expected word to AHB master Make ready high Read data from buffer and send it to master Flow Chart for Read Operation Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide The read buffer is invalidated under the following conditions If the address from the master is outside the TAG region the current data in the read buffer is invalidated TAG mismatch e To ensure proper data coherency every master s write address is tracked If an address matches that of the read buffer TAG the read entry is invalidated Anon bufferable or lock transfer is initiated by any master e An Invalidate command is issued A buffer disable command is issued An error response from DDR for the expected word read Arbiter The DDR bridge arbiter arbitrates read and write requests coming from the read buffers and the WCBs Separate arbitration controllers
103. mask does not indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane DDRC_LCB_MASK_3_SR Table 7 96 DDRC LCB MASK 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 47 32 bits of DDRC LCB MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC REG ECC CORRECTED ERR is High This mask does not indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane Revision 1 313 I Microsemi MSS DDR Subsystem DDRC_LCB_MASK_4_SR Table 7 97 DDRC LCB MASK 4 SR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 61 48 bits of DDR
104. masters can access any external memory through a soft memory controller in the FPGA fabric Cortex M3 Microcontroller S D l DDR lt j SDRAM AXI IDC Cache Transaction MSS DDR Controller Controller Bridge DS PHY Controller S D IC APB Config AHB Bus Matrix 16 Bit APB T 64 Bit AXI APB 2 FIC O FIC 1 ZN Single 32 Bit AHBL Dual 32 Bit AHBL APB AXI AHB Master Master FPGA Fabric Figure 7 1 System Level MDDR Block Diagram 238 The DDR FIC facilitates communication between the FPGA fabric and MDDR subsystem The DDR FIC can be configured to provide either one 64 bit AXI slave interface or two 32 bit AHB Lite AHBL slave interfaces to the FPGA fabric An AXI master or two AHBL masters in the FPGA fabric can access the DDR memories connected to the MDDR using DDR FIC The AXI transaction controller receives read and write requests from AXI masters MSS DDR bridge and DDR FIC and schedules for the DDR controller by translating the requests into DDR controller commands The DDR controller receives the commands from the AXI transaction controller which are initiated by two AXI masters These commands are queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM constraints transaction priorities and dependencies between the transactions The DDR controller in turn issues commands to the PHY module which launches and captures data to and from the DDR SDRAM The DDR PHY conve
105. not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 0 REG_DDRC_DIS_DQ 0x0 When 1 DDRC will not de queue any transactions from the CAM Bypass will also be disabled All transactions are queued in the CAM This is for debug only no reads or writes are issued to DRAM as long as this is asserted This bit is intended to be switched on the fly DDRC_MODE_CR Table 7 25 DDRC_MODE_CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 8 REG_DDRC_DDR3 0x0 1 DDR3 operating mode 0 DDR2 operating mode 7 REG_DDRC_MOBILE 0x0 1 Mobile LPDDR1 DRAM device in use 0 Non mobile DRAM device in use 6 REG_DDRC_SDRAM 0x0 1 SDRAM mode 0 Non SDRAM mode Only present in designs that support SDRAM and or mSDR devices 5 REG_DDRC_TEST_MODE 0x0 1 Controller is in test mode 0 Controller is in normal mode 4 2 REG_DDRC_MODE 0x0 DRAM SECDED mode 000 No SECDED 101 SECDED enabled All other selections are reserved 1 0 REG_DDRC_DATA_BUS_WIDTH 0x0 00 Full DQ bus width to DRAM 01 Half DQ bus width to DRAM 10 Quarter DQ bus width to DRAM 11 Reser
106. of cycles of NOP required after a ZQCS ZQ calibration short command is issued to DRAM Units Clock cycles This is only present for implementations supporting DDR3 devices Revision 1 289 I Microsemi MSS DDR Subsystem DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR Table 7 56 DDRC ZQ SHORT INT REFRESH MARGIN 1 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 4 REG DDRC T ZQ SHORT INTERVAL X1024 OxO 11 0 bits of REG DDRC T ZQ SHORT INTERVAL X1024 Average interval to wait between automatically issuing ZQ calibration short ZQCS commands to DDR3 devices Not considered fREG DDRC DIS AUTO ZQ 1 Units 1 024 clock cycles This is only present for implementations supporting DDR3 devices 3 0 REG DDRC REFRESH MARGIN 0x02 Threshold value in number of clock cycles before the critical refresh or page timer expires A critical refresh is to be issued before this threshold is reached Microsemi recommends using the default value Unit Multiples of 32 clocks DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR Table 7 57 DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR Bit Number Name Reset Value Description 31 8 Res
107. other protocols This signal must be used in conjunction with the CONFIG PHY MODE register which defines the selected protocol characteristics In EPCS mode the PCle PCS dedicated part of the SERDES block is not used only the common PMA macro and PMA control logic are used Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TX PLL and CDR PLL Operation Figure 5 7 This section covers how to configure and use the TX PLL and clock data CDR PLL Powering the TX PLL On and Off Powering on the TX PLL from cold start is done using the aTXPLLRstB signal which is connected to TXPLL RST bit 4 of the PHY RESET OVERRIDE register In PCS driven mode the PCS deasserts aTXPLLRstB after VDD and aRefClk are stable as shown in Figure 5 7 In EPCS mode aTXPLLRstB is deasserted using the APB interface The PLL starts to acquire lock after the deassertion of aTXPLLRstB During TXPLL reset aRefClk is bypassed and produced at the outputs of PLL During bypass mode aTXClk is a divided down version of aRefClk per M N and F settings of the TX PLL Proper values for aRefClk frequency and M N F settings of TX PLL should be supplied to the PLL prior to deassertion of aTXPLLRstB The PCS must initialize these to correct values before coming out of reset The TX PLL OUTPUT IS STABLE WHEN THE ATXCLKSTABLE SIGNAL IS ASSERTED This signal is routed to the fabric in EPCS mode VDD VDDIO VDDPLL aRefCl
108. rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS_ERR_CYC_FIRST_31_24 Register Table 5 136 PRBS ERR CYC FIRST 31 24 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 31 24 PRBS last error cycle counter register bits 31 24 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods 228 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PRBS_ERR_CYC_FIRST_39_32 Register Table 5 137 PRBS ERR CYC FIRST 39 32 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 39 32 PRBS last error cycle counter register bits 39 32 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error coun
109. read data bus is used to transfer data from bus slaves to the bus master during read operations Revision 1 413 I Microsemi Soft Memory Controller Fabric Interface Controller Glossary 414 Acronyms AXI Advanced extensible interface AHB Lite AMBA high performance bus Lite AHBL AMBA high performance bus Lite DDRIO DDR input output ENVMO Embedded nonvolatile memory 0 HPDMA High performance peripheral direct memory access INCR Increment MSIO Multi standard input output MSS Microcontroller subsystem MSSDDR Microcontroller subsystem DDR SMC FIC Soft memory controller fabric interface controller SYSREG System register Revision 1 lt gt Microsemi A List of Changes List of Changes The following table lists critical changes that were made in each revision Date Changes Page 50200330 1 11 12 Updated Fabric Double Data Rate Subsystem section SAR 41901 394 Updated MSS DDR Subsystem section SAR 41901 372 Updated Fabric Double Data Rate Subsystem section SAR 41979 394 Updated Serializer Deserializer section SAR 42156 234 Updated Serializer Deserializer section SAR 42155 234 Updated the user s guide SAR 42443 N A Updated MSS DDR Subsystem section SAR 42751 372 Updated SERDESIF Block section SAR 42912 58 Note The part number is located on the last page of the document The digits following the
110. register 3 CONF AXI SLV WNDW 0 0x94 R W PCle AXI slave window0 configuration register 0 CONF AXI SLV WNDW 1 0x98 R W PCle AXI slave window0 configuration register 1 CONF AXI SLV WNDW 2 Ox9C R W PCle AXI slave window0 configuration register 2 CONF AXI SLV WNDW 3 OxAO R W PCle AXI slave window0 configuration register 4 DESKEW CONFIG OxA4 R W PLL REF clock DESKEW register Note Note R O 0 Read only 28 Refer to the individual register description for the reset value R W Read and write allowed Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg00 SER_PLL_CONFIG_LOW Register 0x2000 Table 1 10 SER PLL CONFIG LOW Bit Reset Number Name Value Description 18 16 PLL OUTPUT DIVISOR Ox1 These bits set SERDES PLL output divider value 000 1 001 2 010 4 011 8 15 6 PLL_FEEDBACK_DIVISOR 0x2 These bits set SERDES PLL feedback divider value SSE 0 binary value 1 0000000000 1 0000000001 2 0000000010 3 1111111111 1 025 5 0 PLL_REF_DIVISOR 0x2 These bits set SERDES PLL reference divider value binary value 1 000000 1 000001 2 000010 3 111111 65 Both REFCK and post divide REFCK must be within the range specified in the PLL datasheet Revision 1 29 I Microsemi SERDESIF Block Table 1 11 SER PLL CONFIG HIGH Reg04 SSER PLL CONFIG HIGH Register 0x2004 Bit Number
111. reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 7 REG_DDRC_T_RFC_MIN 0x23 tRFC min Minimum time from refresh to refresh or activate specification 75 ns to 195 ns Unit clocks 6 REG_DDRC_REFRESH_UPDATE_LEVEL 0x0 Toggle this signal to indicate that the refresh register s have been updated The value is automatically updated when exiting soft reset so it does not need to be toggled initially 5 REG_DDRC_SELFREF_EN 0x0 If 1 then the controller puts the DRAM into self refresh when the transaction store is empty 4 0 REG_DDRC_REFRESH_TO_X32 0x8 Speculative refresh 270 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_DYN_REFRESH_2_CR Table 7 22 e DDRC DYN REFRESH 2 CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 3 REG_DDRC_T_RFC_NOM_X32 0x52 tREFI Average time between refreshes specification 7 8 us Unit multiples of 32 clocks 2 0 REG_DDRC_REFRESH_BURST 0x0 The programmed value plus one is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the ref
112. resource include diagrams illustrations and links to other resources on the website Website You can browse a variety of technical and non technical information on the SoC home page at www microsemi com soc Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website Email You can communicate your technical questions to our email address and receive answers back by email fax or phone Also if you have design problems you can email your design files to receive assistance We constantly monitor the email account throughout the day When sending your request to us please be sure to include your full name company name and your contact information for efficient processing of your request The technical support email address is soc_tech microsemi com Revision 1 417 lt gt Microsemi Product Support My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases Outside the U S Customers needing assistance outside the US time zones can either contact technical support via email soc_tech microsemi com or contact a local sales office Sales office listings can be found at www microsemi com soc company contact default aspx ITAR Technical Support 418 For technical support on RH and RT FPGAs that are regulate
113. slash indicate the month and year of publication Revision 1 415 lt gt Microsemi B Product Support Microsemi SoC Products Group backs its products with various support services including Customer Service Customer Technical Support Center a website electronic mail and worldwide sales offices This appendix contains information about contacting Microsemi SoC Products Group and using these support services Customer Service Contact Customer Service for non technical product support such as product pricing product upgrades update information order status and authorization From North America call 800 262 1060 From the rest of the world call 650 318 4460 Fax from anywhere in the world 408 643 6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware software and design questions about Microsemi SoC Products The Customer Technical Support Center spends a great deal of time creating application notes answers to common design cycle questions documentation of known issues and various FAQs So before you contact us please visit our online resources It is very likely we have already answered your questions Technical Support Visit the Customer Support website www microsemi com soc support search default aspx for more information and support Many answers available on the searchable web
114. source direct from fabric XAUI_FDB_CLK Input Fabric XAUI mode feedback clock for SPLL XAUI CLK OUT Output Fabric XAUI SPLL clock output EPCS RXCLK 1 0 Output Fabric External EPCS interface Rx clock for lane3 and lane2 EPCS TXCLK 1 0 Output Fabric External EPCS interface Tx clock for lane3 and lane2 EPCS 0 TX CLK Output Fabric External EPCS interface Tx clock for laneO EPCS 1 TX CLK Output Fabric External EPCS interface Tx clock for lane1 EPCS 0 RX CLK Output Fabric External EPCS interface Rx clock for laneO EPCS 1 RX CLK Output Fabric External EPCS interface Rx clock for lane1 CLK 25 50MHZ Input RC Osc 25 50MHz RCOSC Oscillator clock Table 1 54 SERDESIF Block AXI AHB Lite Master Interface Connected Port Type To Description AXI M AWID 3 0 Output Fabric AXI Master mode AWID AXI M AWADDR AHB M HADDR 31 0 Output Fabric AXI Master mode AWADDR AHBL Master mode HADDR AXI M AWLEN AHB M HBURST 3 0 Output Fabric AXI Master mode AWLEN AHBL Master mode HBURST AXI M AWSIZE AHB M HSIZE 1 0 Output Fabric AXI Master mode AWSIZE AHBL Master mode HSIZE AXI M AWBURST AHB M HTRANS 1 0 Output Fabric AXI Master mode AWBURST AHBL Master mode HTRANS AXI M AWVALID AHB M HWRITE Output Fabric AXI Master mode AWVALID AHBL Master mode HWRITE AXI M AWREADY Input Fabric AXI Master mode AWREADY AXI M WID 3 0 Output Fabric AXI Master mode WID AXI M WSTRB 7 0 Output F
115. sub layer 3 SGMII Serial Gigabit Media Independent Interface Revision 1 17 I Microsemi SERDESIF Block Table 1 6 PCle Mode Settings Using the SERDESIF System Register continued SERDESIF System APB Registers Description CONFIG_EPCS_SEL 3 0 For each lane one bit of this signal defines whether the external PCS interface is used or the PCle PCS is enabled 0 PCle mode 1 External PCS mode CONFIG_EPCS_SEL 3 External PCS selection associated with lane3 CONFIG_EPCS_SEL 2 External PCS selection associated with lane2 CONFIG_EPCS_SEL 1 External PCS selection associated with lane1 CONFIG_EPCS_SEL 0 External PCS selection associated with laneO CONFIG_LINK2LANE 3 0 This signal is used in PCle mode to select the association of lane to link The four bits refer to four lanes Notes 1 XAUI 10 Gbps attachment unit interface 2 EPCS External physical coding sub layer 3 SGMII Serial Gigabit Media Independent Interface Table 1 7 on page 18 describes the settings for the three SERDESIF system registers to force the SERDESIF block into a specific mode of operation Refer to the Configuration of SERDESIF section on page 25 for the SERDESIF system registers description Table 1 7 Implementing Protocols Using the SERDESIF System Registers CONFIG_PHY_MODE CONFIG_EPCS_SEL CONFIG_LINK2LANE 4 Bits Per Lane 1 Bit Per Lane 1 Bit Per Lane Mode Lane0 Lane1 Lane2 Lane3 Lane0 Lane1 L
116. the MPLL FDDR FACC CLK EN 0x50C RW P PRESETN Enables the clock to the DDR memory controller FDDR_FACC_MUX_CONFIG 0x510 RW P PRESETN Selects the standby glitchless multiplexers within the fabric alignment clock controller FACC FDDR_FACC_DIVISOR_RATIO 0x514 RW P PRESETN Selects the ratio between CLK_A and CLK_DDR_FIC PLL_DELAY_LINE_SEL 0x518 RW P PRESETN Selects the delay values to be added to the FPLL FDDR SOFT RESET 0x51C RW PRESETN Soft reset register for FDDR FDDR_IO_CALIB 0x520 RW PRESETN Configurations register for DDRIO calibration block FDDR_INTERRUPT_ENABLE 0x524 RW PRESETN Interrupt enable register F AXI AHB MODE SEL 0x528 RW PRESETN Selects AXI AHB interface in the fabric PHY SELF REF EN 0x52C RW PRESETN Automatic calibration lock is enabled FDDR_FAB_PLL_CLK_SR 0x530 RO PRESETN Indicates the lock status of the fabric_ PLL FDDR FPLL CLK SR 0x534 RO PRESETN Indicates the lock status of the fabric PLL FDDR INTERRUPT SR 0x53C RO PRESETN Interrupt status register FDDR 10 CALIB SR 0x544 RO PRESETN 1 O calibration status register FDDR FATC RESET 0x548 RW P PRESETN Reset to fabric portion of the fabric alignment test circuit Revision 1 383 I Microsemi Fabric Double Data Rate Subsystem FDDR SYSREG Configuration Register Bit Definitions PLL_CONFIG_LOW_1 Table 8 4 PLL_CONFIG_LOW_1 Bit Reset Num
117. the clock is sent to each PMA single lane macro and skew between lanes is finely controlled Effectively each PMA macro generates a transmit clock TX clock from which is generated the pipe clock generated by one lane used by the PCle controller and also used by PCS logic in all lanes The reference clock signal aRefClk is also sent to the CLK MUX block in order to bypass the transmit clock when this clock is not available This CLK MUX block is a clock multiplexer used for enabling glitchless operation at power up and during speed changes When the link transitions from 2 5 Gbps to 5 Gbps or vice versa the PMA TX PLL and PMA settings are modified by the PCS logic While the TX clock frequency is still 500 MHz the datapath is changed from 5 bit 2 5 Gbps to 10 bit 5 Gbps which might generate glitches on both the TX clock and RX clock provided by the PMA In order to ensure glitchless operation the PCLK provided to the PIPE interface is shut down prior to changing the PMA settings and restarted sometime later when the PLL is stable again this PCLK shut down is done inside the clock divider clkdiv module The TX clock atxclk is a 500 MHz clock in PCle mode and is the clock used by some blocks of the PMA control logic for calibration purposes and PMA hard macro control This clock is used for generating the parallel transmit data TX data as well as other functions such as the TX driver and RX calibration settings idle detection logic and R
118. the suitable change of M N and F settings of the TX PLL Note that a change of mode setting does not instantaneously change the frequencies of aTXCIk and BitClock but will change the frequencies within a few aTXClk cycles depending on the state of the internal PLL registers when mode change is applied The TXPLL design does not guarantee that no runt pulses or glitches occur on the clocks during mode changes So care should be taken when changing the PLL setting during operation mode Revision 1 177 I Microsemi Serializer Deserializer Powering the CDR PLL On and Off The sequence of operations for powering up the CDR PLL from cold start is similar to that of the TX PLL using the aCDRPLLRstB signal connected to RXPLL_RST bits of PHY RESET OVERRIDE register except that proper values for CDR PLL M N and F have to be provided The TX PLL should be up and stable and a bitstream should be present at RXDP and RXDN If the CDR PLL was powered down for deep power savings exit from power down should follow the same sequence of operations as described for powering up from system cold start A bypass operation similar to that of the TX PLL would also result While the CDR PLL is operational and in lock to aRefClk it is possible to shut down the S_CLK and T_CLK trees for intermediate power savings and faster lock to bitstream time by the assertion of RXHF_CLKDN bit 7 of PHY_RESET_OVERRIDE register The RXHF_CLKDN bit when set disables th
119. the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR 0x0 Clear reset for counter RDC_FIFO_RST_ERR_CNT 0 No clear 1 Clear 342 Revision 1 Table 7 166 PHY RDC WE TO RE DELAY CR lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_RDC_WE_TO_RE_DELAY_CR Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 REG_PHY_RDC_WE_TO_RE_DELAY 0x0 Register input specified in number of clock cycles This is valid only if USE_FIXED_RE is High As read capture FIFO depth is limited to 8 entries only the recommended value for this port is less than 8 even though a higher number may work in some cases depending upon memory system design PHY_USE_FIXED_RE_CR Table 7 167 PHY USE FIXED RE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_USE_FIXED_RE 0x0 1 PHY generates FI
120. the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_LCB_MASK 0x0 15 0 bits of DDRC LCB MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High This mask doesn t indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane 312 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_LCB_MASK_2_SR Table 7 95 DDRC LCB MASK 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC LCB MASK 0x0 31 16 bits of DDRC LCB MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC REG ECC CORRECTED ERR is High This
121. to use the SERDES macro for protocols other than PCle through an external PCS interface The PCle PCS is fully configurable in terms of number of lanes and number of links each link configurable from 1 to 4 lanes In addition the multi lane instance can be dissociated at power up to distinguish between lanes used for PCle and lanes used for other protocols through the external PCS interface PMA Macro PMA Control PCle PCS Pm EPCS Block Logic LaneO or XAUI t Extender PMA Macro PMA Control PCle PCS External PCS Block Logic Lane1 Interface PIPE Interface PMA Macro PMA Control PCle PCS Block Logic Lane2 PCle I I I I System 1 I I PMA Macro PMA Control PCle PCS Block Logic Lane3 Power Register Space _ en Aae Management Interface Interface APB bus Auxiliary Power Wake Up Logic Figure 5 1 SERDES Macro Block Diagram The SERDES macro block has 2 major interfaces 1 PIPE interface for PCle protocol maximum 16 bits 2 EPCS interface for implementing any protocol other than PCle maximum 20 bits Revision 1 169 I Microsemi Serializer Deserializer Each lane of SERDES macro can be configured independently at power up in a specific mode using the SERDES macro registers These registers are used to control the multi function SERDES macro parameters to configure the SERDES in a specific mode Refer to the Serial Protocols Setting Using the SERDESIF System Registers section on page 17 in th
122. value of 0 corresponds to 0 Values higher than 128 are forbidden 202 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TX_AMP_RATIO_MARGIN2_HALF Register Table 5 45 TX AMP RATIO MARGIN2 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN2 HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN3_HALF Register Table 5 46 TX AMP RATIO MARGIN3 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN3 HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN4_HALF Register Table 5 47 TX AMP RATIO MARGIN4 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN4 HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN5_HALF Register Table 5 48 TX_AMP_RATIO_MARGIN5_HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGINS HALF This re
123. 0 0xB0000000 0xC0000000 0xD0000000 Modes OxAFFFFFFF OxBFFFFFFF OxCFFFFFFF OxDFFFFFFF 0000 Region 10 Region 11 Region 12 Region 13 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 0011 Region 4 Region 5 Region 6 Region 7 0100 Region 8 Region 9 Region 10 Region 11 0101 Region 12 Region 13 Region 14 Region 15 0110 Region 0 Region 1 Region 2 Region 3 0111 Region 0 Region 1 Region 4 Region 5 1000 Region 0 Region 1 Region 6 Region 7 1001 Region 0 Region 1 Region 8 Region 9 1010 Region 0 Region 1 Region 10 Region 11 1011 Region 0 Region 1 Region 12 Region 13 1100 Region 0 Region 1 Region 14 Region 15 If it connects only 2 GB of DDR memory to MDDR only 8 regions will be available 0 7 Table 7 15 shows the DDR regions available for different address mode settings Table 7 15 Accessed DDR Regions Based on Different Mode Settings for a 2 GB Memory Address DDR Regions Visible at MSS DDR Address Space for Different Modes Space MSS DDR Space 0 MSS DDR Space 1 MSS DDR Space 2 MSS DDR Space 3 Mapping 0xA0000000 0xB0000000 0xC0000000 0xD0000000 Modes OxAFFFFFFF OxBFFFFFFF OxCFFFFFFF OxDFFFFFFF 0000 Region 2 Region 3 Region 4 Region 5 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 0011 Region 4 Region 5 Region 6 Region 7 0110 Region 0 Region 1 Region 2 Region 3 0111 Region 0 Region 1 Region 4 Region 5 1000 Region 0 Regio
124. 0 Read address of math error register 370 Revision 1 CI Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Glossary Acronyms ECC Error correction code FDDR Fabric double data rate FIC Fabric interface controller LPDDR Low power double data rate MDDR MSS double data rate SMC Soft memory controller Revision 1 371 I Microsemi MSS DDR Subsystem List of Changes The following table lists critical changes that were made in each revision be bee re 50200330 1 11 12 Updated 3 Dual AHB Interface from FPGA Fabric section SAR 41901 255 Updated Table 7 7 SAR 41979 24 Updated Features section under Introduction SAR 42751 237 Updated Table 7 3 SAR 42751 240 Note The part number is located on the last page of the document The digits following the slash indicate the month and year of publication 372 Revision 1 lt gt Microsemi 8 Fabric Double Data Rate Subsystem The fabric double data rate FDDR subsystem is a hard ASIC block that simplifies the interfacing of different DDR memory standards to the SmartFusion2 SoC FPGA FPGA fabric The FDDR subsystem is used to access DDR SDRAM for high speed data rates The host slave interface for the FDDR subsystem can be configured to either advanced extensible interface AXI mode or advanced high performance bus AHB mode In AHB mode two AHB masters can access the FDDR subsystem at
125. 0 REG DDRC ADDRMAP COL B11 0x0 Full bus width mode Selects column address bit 13 Half bus width mode Unused To make it unused this should be tied to OxF Quarter bus width mode Unused To make it unused this should be tied to OxF Valid range 0 to 7 and 15 Internal base 11 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 11 is set to 0 Revision 1 275 I Microsemi MSS DDR Subsystem DDRC ADDR MAP ROW 1 CR Table 7 30 DDRC ADDR MAP ROW 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 15 12 IREG DDRC ADDRMAP ROW BO 0x0 Selects the address bits used as row address bit 0 Valid range 0 to 11 Internal base 6 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 11 8 REG_DDRC_ADDRMAP_ROW_B1 0x0 Selects the address bits used as row address bit 1 Valid range 0 to 11 Internal base 7 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field 7 4 REG_DDRC_ADDRMAP_ROW_B2_11 0x0 Selects the address bits used as row address bits 2 to 11 Valid
126. 0 REG_DDRC_EMR 0x0402 Value to be loaded into DRAM EMR registers Bits 9 7 are for OCD and the setting in this register is ignored The controller sets those bits appropriately Revision 1 279 I Microsemi MSS DDR Subsystem DDRC_INIT_EMR2_CR Table 7 37 e DDRC INIT EMR2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_EMR2 0x0 Value to be loaded into DRAM EMR2 registers DDRC_INIT_EMR3_CR Table 7 38 DDRC INIT EMR3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_EMR3 0x0 Value to be loaded into DRAM EMR3 registers DDRC_DRAM_BANK_TIMING_PARAM_CR Table 7 39 DDRC DRAM BANK TIMING PARAM CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 6 REG_DDRC_T_RC 0x0 tRC Minimum time
127. 00 Reg00 TBD R W 04h 05h IXS control 1 register 0x0001 Reg01 TBD R 04h 05h IXS status 1 register Ox 0002 Reg02 TBD R 04h 05h XS device identifier register low 0x0003 Reg03 TBD R 04h 05h XS device identifier register high 0x0004 Reg04 TBD R 04h 05h XS speed ability register 0x0005 Reg05 TBD R 04h 05h XS devices in package register low 0x0006 Reg06 TBD R 04h 05h XS devices in package register high 0x0007 TBD N A 04h 05h Reserved 0x0008 Reg07 TBD R 04h 05h XS status 2 0x0009 to 0x000d TBD N A 04h 05h Reserved 0x000e Reg08 TBD R 04h 05h XS package identifier register low 0x000f Reg09 TBD R 04h 05h XS package identifier register high 0x0010 to 0x0017 TBD N A 04h 05h Reserved 0x0018 Reg10 TBD R 04h 05h 10G XGXS lane status register 0x0019 Reg11 TBD R W 04h 05h 10G XGXS test control register 0x001a to Ox7fff TBD N A 04h 05h Reserved 0x8000 Reg12 TBD R W 04h 05h Vendor specific reset Lo 1 0x8001 Reg13 TBD R W 04h 05h Vendor specific reset Lo 2 0x8002 Reg14 TBD R W 04h 05h Vendor specific reset Hi 1 0x8002 Reg15 TBD R W 04h 05h Vendor specific reset Hi 1 0x8004 to Oxffff TBD N A 04h 05h Reserved Revision 1 141 lt gt Microsemi XAUI Table 3 7 Depicts Definition of XS Control 1 Register Reg00 XS Control 1 Bit Number Name Reset Value Description 15 Reset 0x0 The XAUI extender block is reset when this bit is set to 1 It returns to 0 when the reset is c
128. 000 00 101 All one pattern 1111 11 110 Alternated pattern 1010 10 111 Dual alternated pattern 1100 1100 CUST_SEL When set this signal replaces the PRBS data transmitted on the link by the custom pattern Note that the PRBS_SEL register must also be set for transmitting the custom pattern on the link Note This register can be programmed any time but has functional impact on the SERDES because it can directly activate some part of the SERDES aRXSkipBit changing the current bitstream reception thus creating alignment errors Revision 1 221 I Microsemi Serializer Deserializer CUSTOM PATTERN STATUS Register Table 5 118 CUSTOM PATTERN STATUS Table 5 119 PCS LOOPBBACK CTRL Bit Number Bit Reset Number Name Value Description 7 5 CUST STATE This register reports the current state of the custom pattern word alignment state machine It can be useful for debug purposes Refer verilog code 4 CUST SYNC This register reports that the custom pattern is word aligned 3 0 CUST ERROR 3 0 When the custom pattern checker is enabled this status register reports the number of errors detected by the logic when the custom word aligner is in synchronization it starts counting only after a first matching pattern has been detected The word alignment status can be checked through cust state 3 b101 or CUST_SYNC register asserted PCS LOOPBBACK CTRL Register Name
129. 1 1 0010 Core is compliant with PCle Specification 2 0 PCIE_DEV2SCR Register 230h Table 2 115 PCIE DEV2SCR Bit Reset Number Name Value Description 31 0 PCIE_DEV2SCR_31_0 This register reports the current value of the PCle device control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enabled in the system This register is used when link speed is set to 5 0 Gbps PCIE_LINK2SCR Register 234h Table 2 116 PCIE LINK2SCR Bit Reset Number Name Value Description 31 0 PCIE INK2SCR 310 This register reports the current value of the PCle Link Control and Status register It can be monitored by the local processor when Relaxed Ordering and No Snoop bits are enabled in the system This register is used when link speed is set to 5 0 Gbps ASPM LOS GEN2 Register 260h Table 2 117 ASPM LOS GEN2 Bit Reset Number Name Value Description 31 24 ASPM LOS GEN2 31 24 NFTS COMCLK in common clock mode at 5 0 Gbps 23 16 ASPM LOS GEN2 23 16 NFTS SPCLK in separated clock mode at 5 0 Gbps 15 4 ASPM LOS GEN2 15 4 Reserved 3 0 ASPM LOS GEN2 3 0 Number of electrical idle exit EIE symbols sent before transmitting the first FTS Revision 1 115 lt gt Microsemi PCI Express K_CNT_CONFIG 0 Register 300h Table 2 118 K CNT CONFIG 0 Bit Number Name Reset Value Description
130. 1 5 and 00000 to 4 0 366 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDR_FIC_SW_ERR_ADDR_1_SR Table 7 226 DDR FIC SW ERR ADDR 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR FIC M2 ERR ADD 0x0 Lower 16 bits Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size DDR FIC M2 ERR ADD 31 0 16 bits TAG 0000 32 bits TAG 27 1 00000 DDR FIC SW ERR ADDR 2 SR Table 7 227 DDR FIC SW ERR ADDR 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M2_ERR_ADD 0x0 31 16 bits of DDR FIC M2 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded
131. 1024 0x0 Minimum deep power down time applicable only for LPDDR2 LPDDR exits from deep power down mode immediately after REG_DDRC_DEEPPOWERDOWN_EN is deasserted For LPDDR2 value from the specification is 500 us Units are in 1 024 clock cycles Present only in designs that have mobile support 2 0 REG_DDRC_PAD_PD 0x0 If pads have a power saving mode this is the greater of the time for the pads to enter power down or the time for the pads to exit power down Used only in non DFI designs Unit clocks DDRC_ZQ_LONG _TIME_CR Table 7 54 DDRC ZQ LONG TIME CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG_DDRC_T_ZQ_LONG_NOP 0x0 Number of cycles of NOP required after a ZQCL ZQ calibration long command is issued to DRAM Units Clock cycles This is only present for implementations supporting DDR3 devices DDRC_ZQ_SHORT_TIME_CR Table 7 55 DDRC ZQ SHORT TIME CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG DDRC T ZQ SHORT NOP 0x0 Number
132. 15 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 15 0 bits of REG PHY WR DATA SLAVE DELAY IFREG PHY WR DATA SLAVE FORCE is 1 replace delay tap value for write data slave DLL with this value 336 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_WR_DATA_SLAVE_DELAY_2_CR Table 7 152 PHY WR DATA SLAVE DELAY 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 31 16 bits of REG_PHY_WR_DATA_SLAVE_DELAY If REG_PHY_WR_DATA_SLAVE_FORCE is 1 replace delay tap value for write data slave DLL with this value PHY_WR_DATA_SLAVE_DELAY_3_CR Table 7 153 PHY WR DATA SLAVE DELAY 3 CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_WR_DATA_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_WR_DATA_SLAVE_DELAY If REG_PHY_WR_DATA_SLAVE_FORCE is 1 replace delay tap value for write data slave DLL with this value PHY_WR_DATA_SLAVE_FORCE _CR Table 7 154
133. 2 bit APB interface The physical offset location of the PCle core registers is 0x0000 0x0FFF from the SERDESIF system memory map Refer to the PCI Express section on page 59 for more information about the PCle core register SERDES Macro Register The SERDES macro register map contains control and status information for the SERDES block and lanes Each block uses 256 register bytes However these 256 bytes are mapped to 1 KB to make 32 bit APB output The APB to SERDES programming interface bridge is implemented to convert the system 32 bit APB bus transactions into appropriate 8 bits Since the SmartFusion2 SoC FPGA devices map the 4 SERDES lanes into 1KB blocks the overall register map size is 4 KB The physical offset location of the SERDES macro registers from the SERDESIF system memory map is as follows 0x1000 0x13FF 1 KB SERDES programming interface Lane0 Revision 1 25 I Microsemi SERDESIF Block 0x1400 0x17FF 1 KB SERDES programming interface Lane1 0x1800 0x1BFF 1 KB SERDES programming interface Lane2 0x1C00 0x1FFF 1 KB SERDES programming interface Lane3 Refer to the Serializer Deserializer section on page 169 for the SERDES macro register Ox23FF a SERDESIF System Register i 1 KB 0x2000 SERDES Macro Register i Lane 3 1 KB 0x1C00 i SERDES Macro Register Lane 2 1 KB 0x1800 SERDES Macro Register Lane 1 1 KB 0x1400 i
134. 2 possible MSI messages MSI 6 098h RO or This register defines 8 MSI MAPS registers with up to R W 32 possible MSI messages MSI 7 09Ch ROor This register defines 8 MSI MAP registers with up to R W 32 possible MSI messages MSI_CTRL_STATUS 040h R Wor This register sets MSI control and status All bits are RO RO except the number of MSI requested and the multiple message enable fields which are R W Up to 32 MSI messages can be requested by the device although the PCI software can allocate less than the number of MSI requested This information can be read by the local processor through the multiple message enable field of the register 88 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Root Port Interrupt Registers These registers are not implemented in SmartFusion2 SoC FPGA PCle endpoints PCle Control and Status Registers The following registers are read only registers that enable the local processor to check useful information related to the PCle interface status such as when the PCle interface is initialized and monitoring of PCI link events A complete description of these registers can be found in the PCle specifications Table 2 15 PCle Control and Status Registers Address Register Register Name Offset Type Description CFG_PRMSCR 004h RO The command and status register of PCI configuration space PCIE_DEVSCR 030h This register reports the
135. 5 68 ATXDRP EM 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRP EI11 20 16 This register defines bit 20 to bit 16 of the transmitted P parameter sent to the PHY for being in electrical idle I on the transmit driver ATXDRA EI1 7 0 Register Table 5 69 ATXDRA EI1 7 0 Bit Reset Number Name Value Description 7 0 ATXDRA EI1 7 0 This register defines bit 7 to bit 0 of the transmitted A parameter sent to the PHY for being in electrical idle I on the transmit driver Revision 1 207 I Microsemi Serializer Deserializer Table 5 70 ATXDRA_EI1_15_8 ATXDRA_EI1_15_8 Register Bit Reset Number Name Value Description 7 0 ATXDRA_EI1 15 8 This register defines bit 15 to bit 8 of the transmitted A parameter sent to the PHY for being in electrical idle on the transmit driver ATXDRA EI1 20 16 Register Table 5 71 ATXDRA EI1 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRA EI1 20 16 This register defines bit 20 to bit 16 of the transmitted A parameter sent to the PHY for being in electrical idle I on the transmit driver ATXDRT EI1 7 0 Register Table 5 72 ATXDRT EI1 7 0 Bit Number 7 0 Name ATXDRT E11 7 0 Reset Value Description This register defines bit 7 to bit 0 of the Transmitted T parameter sent to the PHY for being in ele
136. 55 count value corresponding to an error code where the CDR PLL is not locked to incoming data When such an error code is detected the PRBS test must wait for a longer time for the CDR PLL to synchronize on input data before enabling the PRBS checker or simply timeout reporting that no data has been received at all Note that the PRBS error counter logic also counts errors when the PRBS invariant all zero value is obtained considering input data as error data Revision 1 215 lt gt Microsemi Serializer Deserializer PHY_RESET_OVERRIDE Register Table 5 105 PHY RESET OVERRIDE Bit Reset Number Name Value Description 7 RXHF CLKDN When set this signal disables the RX PLL VCO settings by applying a static zero to the PMA aRXHfClkDnb signal 6 TXHF_CLKDN When set this signal disables the TX PLL VCO by applying a static zero to the PMA aTXHfClkDnb signal 5 RXPLL_RST When set this signal resets the RX PLL settings by applying a static zero to the PMA aCadrPIlRstb signal 4 TXPLL_RST When set this signal initializes the TX PLL settings by applying a static zero to the PMA aTXPIIRstb signal 3 RXPLL_INIT When set this signal resets the RX PLL settings by applying a static zero to the PMA aCadrPIlRstb signal 2 TXPLL_INIT When set this signal initializes the TX PLL settings by applying a static one to the PMA aTXPIlDivInit signal 1 RX_HIZ When set this signal forces the RX drive
137. 6 c eee ee tee es 373 FDDR Subsystem Overview 0 00 tte 373 FDDR Configuration scoici ees circe bebe ie bee see ee eee DE debe ee ee eee 378 USE Case Scenaro iiia e a boda eadlbed dad s Jake bier 6 Aa g obit by d EAE saben deep raaa 378 Register Interface 2 2 6 sn arsakarese dea e ke aka Sdn AE sea bate ee rahe EAE S E dee 382 GOSS na ee eae de ae EAA 393 9 DDR Bdge vas skerhvdsae VEKK Ge oe DES heed WHET eee a R eee SG l SG 395 Feature Sinsen eo aeneon Saker kalkrik et PA Sk acerca te LAY bk Meek ee A 395 DDR Bridges in SmartFusion2 SoC FPGA Devices 0 00 ccc nr rare rakne 396 Funetional DeEsenption icsi oerien kt stener Aae ened ee Mae LAT Th ee ee GER 398 MSS DDR Bridge Configurations aaauvvrn arna rar renner nen rn inii E narr nakne 404 MDDR FDDR DDR Bridge Configuration Steps 0 6 nere rare rever rakke 404 SYSREG Control Registers 2020 92 ses iakes da pee oe Pee eee ee Pane vee yew dae ee Pee eee eee 405 DDR Bridge Control Registers in MDDR and FDDR 0 0 eects 406 EET sci ch et epee bebe piren bea Re bb eae eee eG baw bee boobed done be 406 10 Soft Memory Controller Fabric Interface Controller 000 200 ee eee 407 Intfoduetion vusrsansrussorrnl wits DEE ar Ale Sareea ANE seeks EAH ow Cane Gahn 407 Functional Block Diagram 2 220020 ecc ee nee smerte Sb edd dee eae ea bee eed Pb bebe deeds 407 Functional Desenptibn s s sa sets pira Gikk a ieie aine a eens Gh a nE Glare
138. 8 3 FPGA Fabric AXI Master AWREADY WREADY BID BRESP BVALID ARREADY RID RRESP RDATA RLAST RVALID AWID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWVALID WID WDATA WSTRB WLAST WVALID BREADY ARID ARADDR ARLEN ARSIZE ARBURST ARLOCK ARVALID APB Master PENABLE PSELx PWRITE PADDR PWDATA PREADY PSLVERR PRDATA AX _S_AWREADY AX _S_WREADY AXI S BID 3 0 AXI S BRESP 1 0 AXI S BVALID AXI S ARREADY AXI 8 RID 3 0 AXI S RRESPI1 0 AXI S RDATA 63 0 AXI S RLAST AXI S RVALID AXI S AWID 3 AXI S AWADDRIJ31 0 AXI S AWLEN 3 0 AXI 8 AWSIZE 1 0 AXI S AWBURST 1 0 AXI S AWLOCK 1 0 AXI S AWVALID AXI 8 WID 3 0 AXI S WDATA 63 0 AXI S WSTRB 7 0 AXI S WLAST AXI S WVALID AXI S BREADY AXI 8 ARID 3 0 AXI 8 ARADDR 31 0 AXI S ARLEN 3 0 AXI S ARSIZE 1 0 AXI S ARBURST 1 0 AXI S ARLOCK 1 0 AXI S ARVALID APB S PENABLE APB S PSELX APB S PWRITE APB S PADDR 10 2 APB S PWDATA 15 0 APB S PREADY APB S PSLVERR APB S PRDATA 15 0 Figure 8 3 FDDR Subsystem Block Diagram FDDR PLL LOCK INT PLL LOCKLOST INT ECC INT IO CALIB INT FIC INT DDR SDRAM FDDR CAS N CASN FDDR CKE CKE FDDR CLK CLK P FDDR CLK N CLK N FDDR_CS_N CSN FDDR_ODT ODT FDDR_RAS_N RASN FDDR_RESET_N RSTN FDDR_WE_N WEN FDDR ADDR 15 0 ADDR 15 0 FDDR BA 2 0 BA 2 0 FDDR DM RDQS 4 0 DM 4 0 FDDR DQ 4 0 DQS P 4 0 FDDR DQS N 4 0 DQS N 4 0 FDDR DQ 35 0 DQ 35 0 FDDR FIFO
139. 9 for more information on the SERDES block e PCle system This block implements the x1 x2 x4 lane PCle endpoint Regular and Reverse mode with an AXI AHB interface to the fabric The SmartFusion2 SoC FPGA PCle is compliant with the PCle Base Specification 1 1 for Gen1 and PCle Base Specification 2 0 for Gen1 or Gen2 Refer to the PCI Express section on page 59 for more information on the PCle system block e XAUI Extender This block is an XGMII extender to support the XAUI protocol through a soft IP core in the SmartFusion2 SoC FPGA fabric Refer to the XAUI section on page 129 for more information e SERDESIF system register The SERDESIF system registers control the SERDESIF module for single protocol or multi protocol support implementation These registers can be accessed through the 32 bit APB interface and the default values of these registers can be configured using Libero System on Chip SoC software Using the SERDESIF blocks SmartFusion2 SoC FPGA devices allow to implement the following high speed protocols e PCle e XAUI protocol 10 GbE e SGMIl e User defined high speed protocols Table 1 1 on page 7 lists the single protocol and multi protocol implementations in the SERDESIF block also known as PHY modes of operation Revision 1 5 I Microsemi SERDESIF Block SERDESIF SERDES Block X2 EPCS I 0 PADS SERDES XAUI _ PMA PCIE Extender PCS X2 EPCS Interface XGMII Interface SERDESIF PCle Syste
140. AIN 0x0 1 Read Data Eye training mode has been enabled as part of the initialization sequence 4 REG_DDRC_DFI_RD_DQS_GATE_LEVEL 0x0 1 Read DQS Gate Leveling mode has been enabled as part of the initialization sequence Only present in designs that support DDR3 devices 3 0 REG_DDRC_DFI_RDLVL_MAX_X1024 0x0 12 8 bits Read leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY_DFI_RDLVL_RESP to a read leveling enable signal DDRC DFI RDLVL EN or DDRC DFI RDLVL GATE EN Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units 1 024 clocks 298 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC DFI CTRLUPD TIME INTERVAL CR Table 7 73 DDRC DFI CTRLUPD TIME INTERVAL CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG DDRC DFI T CTRLUPD INTERVAL MIN X1024 0x10 This is the minimum amount of time between controller initiated DFI update requests which will be executed whenever the controller is idle Set this number higher to reduce the frequency of update requests which can h
141. AM external flash and external SRAM The SMC_FIC can be accessed by different masters in the MSS and is configured by the Libero SoC MSS MDDR configuration GUI The SMC FIC implements an AXI master to AXI master AHB Lite master protocol translator The MSS DDR subsystem MDDR controller is not available to the user application if SMC FIC mode is enabled In SMC FIC mode the 2 5 V DDRIOs normally available to the MDDR controller are available for interfacing to external devices Functional Block Diagram SmartFusion2 ARM Cortex M3 Microcontroller Microcontroller Subsystem MSS MSS DDR Bridge AXI 64 Output MM2 MM1 MMO MM6 MM3 AHB Bus Matrix SMC_FIC AXI 64 or AHB Lite nput to Fabri Soft Memory FPGA Fabric Controller External Bulk Memory Figure 10 1 SMC FIC Mode Revision 1 407 I Microsemi Soft Memory Controller Fabric Interface Controller Functional Description The input side of the SMC FIC accepts 64 bit AXI master transactions from the MSS DDR bridge and converts the transactions into 64 bit AXI or 32 bit AHB Lite master output transactions for consumption in the FPGA fabric The AXI and AHB Lite slave ports are mutually exclusive only one type is available at any given time The type of interface can be configured by setting the F AXI AHB MODE bit in the MDDR_CR register in the SYSREG block Setting the SDR_MODE bit in the MDDR_CR register in the SYSREG block enables SMC_FIC mode The SMC
142. ARGIN6 FULL 0x48 RW ITX amplitude ratio TXMargin 6 full swing OX07C TX AMP RATIO MARGIN7 FULL 0x40 RW ITX amplitude ratio TXMargin 7 full swing 0X080 RE AMP RATIO DEEMPO 0x00 RW RX equalization amplitude ratio TXDeemp 0 0X084 RE_CUT_RATIO_DEEMPO 0x00 RW RX equalization cut frequency TXDeemp 0 0X088 RE AMP RATIO DEEMP1 0x00 RW RX equalization amplitude ratio TXDeemp 1 Ox08C RE CUT RATIO DEEMP1 0x00 RW RX equalization cut frequency TXDeemp 1 0X090 TX PST RATIO DEEMPO HALF 0x15 RW ITX post cursor ratio with TXDeemp 0 half swing 0X094 TX PRE RATIO DEEMPO HALF 0x00 RW ITX pre cursor ratio TXDeemp 0 half swing 0X098 TX PST RATIO DEEMP1 HALF 0x20 RW ITX post cursor ratio with TXDeemp 1 half swing OX09C TX PRE RATIO DEEMP1 HALF 0x00 RW ITX pre cursor ratio TXDeemp 1 half swing 0X090 TX AMP RATIO MARGINO HALF 0x50 RW ITX amplitude ratio TXMargin 0 half swing OXOA4 TX AMP RATIO MARGIN1 HALF 0x58 RW ITX amplitude ratio TXMargin 1 half swing OXOA8 TX AMP RATIO MARGIN2 HALF 0x48 RW ITX amplitude ratio TXMargin 2 half swing OXOAC TX AMP RATIO MARGIN3 HALF 0x40 RW ITX amplitude ratio TXMargin 3 half swing OXOAO TX AMP RATIO MARGIN4 HALF 0x38 RW ITX amplitude ratio TXMargin 4 half swing 0X0B4 TX AMP RATIO MARGINS HALF 0x30 RW ITX Amplitude ratio TXMargin 5 Half swing 0X0B8 TX AMP RATIO MARGIN6 HALF 0x28 RW ITX amplitude ratio TXMargin 6 half swing OXOBC TX AMP RATIO MARGIN7
143. ATIO DEEMP1 HALF Bit Reset Number Name Value Description 7 0 TX PST RATIO DEEMP1 HALF This register defines the TX post cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 value of 3 5 dB corresponds to 8 d21 encoding TX_PRE_RATIO_DEEMP1_HALF Register Table 5 42 TX PRE RATIO DEEMP1 HALF Bit Reset Number Name Value Description 7 0 TX_PRE_RATIO_DEEMP1_HALF This register defines the TX pre cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 TX_AMP_RATIO_MARGINO_HALF Register Table 5 43 TX AMP RATIO MARGINO HALF Bit Name Reset Description Number Value P 7 0 TX_AMP_RATIO_MARGINO_HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN1_HALF Register Table 5 44 TX AMP RATIO MARGIN1 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN1 HALF This register implements the TX amplitude ratio used by the TX driver value of 128 corresponds to 100 full voltage a
144. ATXDRP 7 0 0x00 RW Force transmitter P shift loader parameter 0 0X158 FORCE ATXDRP 15 8 0x00 RW Force transmitter P shift loader parameter 1 OX15C FORCE ATXDRP 20 16 0x00 RW Force transmitter P shift loader parameter 2 0X160 FORCE ATXDRA 7 0 0x00 RW Force transmitter A shift loader parameter 0 0X164 FORCE ATXDRA 15 8 0x00 RW Force transmitter A shift loader parameter 1 0X168 FORCE ATXDRA 20 16 0x00 RW Force transmitter A shift loader parameter 2 OX16C FORCE ATXDRT 7 0 0x00 RO Force transmitter T shift loader parameter 0 0X170 FORCE ATXDRT 15 8 0x00 RO Force transmitter T shift loader parameter 1 0X174 FORCE ATXDRT 20 16 0x00 RO Force transmitter T shift loader parameter 2 0X178 RXD OFFSET CALIB RESULT 0x00 RO RXD offset calibration result 186 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 5 2 e SERDES Macro Registers continued Offset Reset Hex Register Name Value Type Description OX17C RXT OFFSET CALIB RESULT 0x00 RO RXT offset calibration result 0X180 SCHMITT TRIG CALIB RESULT 0x00 RO Schmitt trigger calibration result 0X184 FORCE RXD OFFSET CALIB 0x00 RW Force RXD offset calibration settings 0X188 FORCE RXT OFFSET CALIB 0x00 RW Force RXT offset calibration settings 0X18C FORCE SCHMITT TRIG CALIB 0x00 RW Force Schmitt trigger calibration s
145. ATXDRP EI2 20 16 This register defines bit 20 to bit 16 of the transmitted P parameter sent to the PHY for being in electrical idle Il on the transmit driver ATXDRA EI2 7 0 Register Table 5 78 ATXDRA EI2 7 0 Bit Reset Number Name Value Description 7 0 ATXDRA EI2 7 0 This register defines bit 7 to bit 0 of the transmitted A parameter sent to the PHY for being in electrical idle Il on the transmit driver ATXDRA EI2 15 8 Register Table 5 79 ATXDRA EI2 15 8 Bit Reset Number Name Value Description 7 0 ATXDRA_EI2 15 8 This register defines bit 15 to bit 8 of the transmitted A parameter sent to the PHY for being in electrical idle Il on the transmit driver ATXDRA EI2 20 16 Register Table 5 80 ATXDRA EI2 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRA_EI2 20 16 This register defines bit 20 to bit 16 of the transmitted A parameter sent to the PHY for being in electrical idle Il on the transmit driver ATXDRT EI2 7 0 Register Table 5 81 ATXDRT EI2 7 0 Bit Reset Number Name Value Description 7 0 ATXDRT EI2 7 0 This register defines bit 7 to bit 0 of the transmitted T parameter sent to the PHY for being in electrical idle Il on the transmit driver Revision 1 209 I Microsemi Serializer Deserializer ATXDRT EI2 15 8 Register Table 5 82 ATXDRT EI2 15 8
146. AX164 AXI64 Slave Slave AHB32 Slave Interface Interface interfaca AXI to AXI FPGA Fabric Figure 2 5 e AHBL AXI to AXI Bridge Block Diagram The AHBL AXI to AXI bridge can be configured using two SERDESIF system registers as shown in Table 2 3 for appropriate slave implementation in the fabric These two one bit registers are programmable but Libero SoC should be used to configure these bridges according to their requirement Refer to the SERDESIF system registers in the SERDESIF Block section on page 5 for details Table 2 3 Configuration Inputs for Configuring AHBL AXI to AXI Bridge F AXI AHB SLAVE Specifies whether there is an AXI AHBL slave implemented in the fabric 1 AXI slave implemented in fabric default value 0 AHB slave implemented in fabric AHB_DATA_WIDTH Specifies whether there is a 32 bit or 64 bit AHB slave in the fabric Applies only when F AXI AHB SLAVE is programmed to 0 1 64 bit AHB slave implemented in the fabric default value 0 32 bit AHB slave implemented in the fabric 66 The AXI interface has following limitations 1 Supports only INCR types of bursts 2 Supports only 64 bit read write transactions on the AXI slave interface Glue Logic Blocks The PCle system block has several small logic blocks for PCle subsystem functionality PCle PHY reset Controller This block controls the assertion and deassertion of reset to the PCIe core SERDES macro and other
147. BIST generation and checker logic when this port is set High Setting this port as 0 will stop the BIST generator checker In order to run BIST tests this port must be set along with REG_PHY_LOOPBACK 2 1 REG_PHY_BIST_MODE 0x0 The mode bits select the pattern type generated by the BIST generator All the patterns are transmitted continuously once enabled 00 Constant pattern 0 repeated on each DQ bit 01 Low frequency pattern 00001111 repeated on each DQ bit 10 PRBS pattern 2 7 1 PRBS pattern repeated on each DQ bit Each DQ bit always has same data value except when early shifting in PRBS mode is requested 0 REG_PHY_BIST_FORCE_ERR 0x0 _ This register bit is used to check that the BIST checker is not giving a false pass When this port is set to 1 the data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error PHY_DYN_BIST_TEST_ERRCLR_1_CR Table 7 102 PHY DYN BIST TEST ERRCLR 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_BIST_ERR_CLR 0x0 15 0 bits of REG_PHY_BIST_ERR_CLR Clear the mismatch error flag from the BIST checker 1 Sticky error flag is cleared 0 No effect Revision 1 319
148. BL master interface Active EPCS interface of lane0 and lane1 for SRIO EPCS AXI AHBL slave interface Inactive APB interface 32 bit Active Inactive EPCS interface lane2 and lane3 Active I O pad Interface Active Miscellaneous interface Active Revision 1 53 I Microsemi SERDESIF Block Figure 1 18 shows the SERDESIF I O signals in Fabric mode2 SERDES APB_S_PRESET_N PADs OUTEI APB_S_PCLK TXDO_P APB_SLAVE TXDO_N EIPADs_IN TXD1_P FO PADs OUT REFCLKO P TXD1N REFCLKO N TXD2_P RXDO P TXD2 N RXDO N TXD3 P RXD1 P TXD3_N RXD1_N EPCS 0 OUTE RXD2 P EPCS 0 READY RXD2 N EPCS 0 RX DATA 19 0 RXD3 P EPCS 0 RX VAL RXD3_N EPCS 0 RX IDLE EIEPCS 0 IN EPCS 0 TX C K ST BLE EPCS 0 TX DATA 19 0 EPOS 0 RX RESET N EPCS 0 PWRCN EPCS 0 TX RESET N EPCS 0 TX VAL EPCS 0 RX_CLK EPCS 0 TX 00B EPCS 0 TX CLK EPCS_0_RX_ERR EPCS 1 OUTE EJEPGS 1 OUT EPCS 0 RESET N EPCS 1 READY EJEPCS 1 IN EPCS 1 RX DATA 19 0 EPCS 1 TX DATA 19 0 EPCS 1 RX VAL EPCS 1 PWRCN EPCS 1 RX IDLE EPCS 1 TX VAL EPCS 1 TX CLK ST BLE EPCS 1 TX 00B EPCS 1 RX RESET N EPCS 1 RX ERR EPCS 1 TX RESET N EPCS 1 RESET N EPCS 1 RX C K EJEPCS 2 IN EPCS 1 TX CLK EPCS 2 TX DATA 19 0 EPCS 2 OUT HEPCS 2 OUT EPCS 2 PWRCN EPCS 2 READY EPCS 2 TX VAL EPCS 2 RX DATA 19 0 EPCS 2 TX 00B EPCS 2 RX VAL EPCS 2 RX ERR EPCS 2 RX IDLE EPCS 2 RESET N EPCS 2 TX C K ST BLE EPCS 3
149. Bus Width M2S125 M2S080 and M2S050 M2S025 M2S010 and M2S005 Full bus width v Half bus width v v Quarter bus width v v Burst Mode Burst mode can be selected as sequential or interleaving by configuring DDRC_BURST_MODE to 1 or 0 Burst length can be selected as 4 8 or 16 by configuring REG_DDRC_BURST_RDWR Supported burst modes for various DDR SDRAM types and PHY widths are given in Table 7 6 and Table 7 7 on page 244 Microsemi recommends sequential burst mode and a burst length of 8 Burst Modes for M2S050 Table 7 6 Supported Burst Modes for M2S050 Sequential Interleaving Bus width Memory Type 8 16 32 LPDDR1 SISIA DDR2 DDR3 16 LPDDR1 DDR2 SISISISINIS DDR3 Burst Modes for M2S010 Table 7 7 Supported Burst Modes for M2S010 Sequential Interleaving Bus width Memory Type 16 16 LPDDR1 DDR2 DDR3 8 LPDDR1 DDR2 DDR3 SISISISISISI S 244 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Clocking The MDDR subsystem operates on MDDR_CLK which comes from MSS_CCC This clock value can be configured through the MSS_CCC configurator in Libero SoC 1 Maximum frequency of MDDR_CLK is 333 MHz 2 The MSS DDR bridge design within the MSS requires M3_CLK to run at the same speed or slower than MDDR_CLK with the ratio being any integer betw
150. C SECDED interrupt status register DDRC_ECC_INT_CLR_REG 0x140 RW PRESET_N DDRC SECDED interrupt clear register Revision 1 269 I Microsemi MSS DDR Subsystem DDR Controller Configuration Register Bit Definitions DDRC_DYN_SOFT_RESET_CR Table 7 20 DDRC_DYN_SOFT_RESET_CR Bit Name Reset Description Number Value 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 AXIRESET 0x1 Set when main AXI reset signal is asserted Reads and writes to the dynamic registers should not be carried out This is a read only bit 1 RESET_APB_REG 0x0 Full soft reset If this bit is set when the soft reset bit is written as 1 all APB registers reset to the power up state 0 REG_DDRC_SOFT_RSTB 0x0 This is a soft reset 0 Puts the controller into reset 1 Takes the controller out of reset The controller should be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APB configuration registers Once the soft reset bit is asserted the APB register should be modified as required DDRC_DYN_REFRESH_1_CR Table 7 21 DDRC DYN REFRESH 1 CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a
151. CALIB RESULT Bit Reset Number Name Value Description 7 5 Unused 4 ARXTDIR This register reports the sign of voltage applied to aRXD settings for RX offset calibration 3 0 ARXTNUL 3 0 This register reports the voltage applied to aRXD settings for RX offset calibration SCHMITT_TRIG_CALIB_RESULT Register Table 5 99 SCHMITT TRIG CALIB RESULT Bit Reset Number Name Value Description 7 5 Unused 4 ASCHDIR This register reports the sign of voltage applied for Schmitt trigger offset calibration 3 0 ASCHNULJ 3 0 This register reports the voltage applied for Schmitt trigger offset calibration Revision 1 213 lt gt Microsemi Serializer Deserializer FORCE_RXD_OFFSET_CALIB Register Table 5 100 FORCE RXD OFFSET CALIB Bit Reset Number Name Value Description 7 5 Unused 4 F ARXDDIR This register forces the voltage to apply to aRXD settings for RX offset calibration 3 0 F_ARXDNUL 3 0 This register forces the voltage to apply to aRXD settings for RX offset calibration Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 2 is not set When Reg81 bit 2 is set the RXD offset calibration obtained during calibration is replaced by the content of this register FORCE_RXT_OFFSET_CALIB Register Table 5 101 FORCE RXT OFFSET CALIB Bit Reset Num
152. CEX is set to 1 PHY FIFO WE IN DELAY 3 CR Table 7 122 PHY FIFO WE IN DELAY 3 CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_FIFO_WE_IN_DELAY Ox0 44 32 bits of REG PHY FIFO WE IN DELAY Delay value to be used when REG PHY FIFO WE IN FORCEX is set to 1 PHY FIFO WE IN FORCE CR Table 7 123 PHY FIFO WE IN FORCE CR Bit Reset Number Name Value Description 7 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG PHY FIFO WE IN FORCE 0x0 1 Overwrite the delay tap value for the FIFO_WE slave DLL with the value of the REG_PHY_FIFO_WE_IN_DELAY bus 326 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_FIFO_WE_SLAVE_RATIO_1_CR Table 7 124 PHY_FIFO_WE_SLAVE_RATIO_1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pre
153. CH XAUT MMD MD p XAUT MMO MOT EXT PR PAU MMD MDOE IN gt XAUT_MMD_PRTAD 4 0 gt i XAUT MMD DEMD 4 01 XAU OOPBACK IN XAUI RX R KAO TXDIGSOLp XAUI MMD MDC XAUI_MMD_MDI XAULMMD_MDI_EXT XAUI MMD MDOE IN XAUI MMD PRTAD 4 0 XAUI MMD DEMD 4 0 XAUI LOOPBACK IN XAUI MDC RESET XAUI TX RESET XAUI RX RESET XAUI TXD 63 0 EIPADs IN REFCLKO_P REFCLKO_N RXDO_P RXDO_N RXD1_P RXD1_N RXD2 P RXD2 N RXD3_P 2 y 4 ERT pT oo oom em SN SERDES IF 0 XAUI RXD 63 0 XAUI RXD 63 0 XAUT RXC 7 0 gt ff XAUT_RX_CLK 4 XAUT_RX_CTR XAUI_VNDRESLO 31 0 gt _4 XAUT VNDR XAUI_VNDRESHII31 0 gt XAUI_VNDRESHI ST 0 gt XAUT_MIMD_MDO XAUT MMD MDOE XAUI LOWPOWER XAU OOPBA XAUI MMD MDO XAUI MMD MDOE XAUI LOWPOWER XAUI LOOPBACK OUT XAUI MDC RESET OUT XAUI TX RESET OUT XAUI RX RESET OUT 3 0 XAUI OUT CLK PLL LOCK INT PLL LOCKLOST INT pF pr l gt b PAUR RESET OUTS gt 4 XAUI_OUT_CLK b PPL OCK INT SPL TOCRTOST NT s POK ou am 4 re zz 4 SPLL LOCK O PADs_OUTE SEIPADs OUT TXDO P gt TXDO_P TXDO_N STXDO N TXD1 P XDT P TXD1_N gt XD1_N TXD2_P TXD2_N gt IXDZN TXD3_P gt IXD3 P TXD3_N gt IXDS N IP Figure 1 19 SERDESIF I O Signals in Fabric Mode3 Re
154. CLK SEL Bit Reset Number Name Value Description 0 RC OSC REFCLK SEL Ox1 This bit sets RC OSC as reference clock selection for SPLL Revision 1 41 lt gt Microsemi SERDESIF Block Reg80 SPREAD_SPECTRUM_CLK Register 0x2080 Table 1 42 SPREAD SPECTRUM CLK Bit Reset Number Name Value Description 7 3 PLL_SERDESIF_SSMF 0x0 Spread spectrum clocking configuration register for feedback divider 2 1 PLL_SERDESIF_SSMD 0x0 Spread spectrum clocking configuration register for reference divider 0 PLL_SERDESIF_SSE 0x0 Spread spectrum clocking configuration register Reg84 CONF AXI MSTR WNDW 0 Register 0x2084 Table 1 43 CONF AXI MSTR WNDW 0 Bit Reset Number Name Value Description 31 0 CONF AXI MSTR WNDW 0 0x0 PCle AXI master Window0 configuration register 0 Note All the register are 32 bit Bits not shown in the table are reserved Reg88 CONF AXI MSTR WNDW 1 Register 0x2088 Table 1 44 CONF AXI MSTR WNDW 1 Bit Reset Number Name Value Description 31 0 CONF AXI MSTR WNDW 1 0x0 PCle AXI master Window0 configuration register 1 Reg8C CONF AXI MSTR WNDW 2 Register 0x208C Table 1 45 CONF AXI MSTR WNDW 2 Bit Reset Number Name Value Description 31 0 CONF AXI MSTR WNDW 2 0x0 PCle AXI master Window0 configuration register 2 Reg90 CONF AXI MSTR WNDW 3 Register 0x2090
155. CS interface is used or the PCI Express PCS is enabled e Ob PCI Express mode e 1b External PCS mode CONFIG EPCS SEL 3 External PCS selection associated to Lane3 CONFIG EPCS SEL 2 External PCS selection associated to Lane2 CONFIG EPCS SEL 1 External PCS selection associated to Lane1 CONFIG EPCS SEL 0 External PCS selection associated to LaneO CONFIG_LINKK2LANE 3 0 156 This signal is used in PCle mode in order to select the association of lane to link The 4 bits refer to 4 lanes Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Note 1 EPCS 2 5 GHz mode is a subset of the EPCS Interface mode where the SERDES registers are configured for 2 5 GHz link speed with a 20 bit interface at the EPCS 2 EPCS 1 25 GHz mode is a subset of the EPCS Interface mode where the SERDES registers are configured for 1 25 GHz link speed with a 10 bit interface at the EPCS 3 EPCS undefined mode is also a subset of the EPCS interface where the SERDES registers default values are programmed to 32 d0 An APB interface is needed or programming the link speed and EPCS bit width 4 EPCS SGMII mode Lane3 is also a subset of the EPCS interface where only SERDES Lane3 is used for the SGMII protocol purposes No other lanes are active in this mode This feature enables to quickly configure the SERDES into the Single protocol SERDES SGMII mode Table 4 5 describes the se
156. C_LCB_MASK Indicates the mask of the corrected data 1 On any bit indicates that the bit has been corrected by the DRAM SECDED logic 0 On any bit indicates that the bit has NOT been corrected by the DRAM SECDED logic Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High This mask does not indicate any correction that has been made in the SECDED check bits If there are errors in multiple lanes this signal will have the mask for the lowest lane Table 7 98 DDRC ECC INT SR DDRC ECC INT SR Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 DDRC ECC STATUS SR 0x0 Bit 0 1 Indicates the SECDED interrupt is due to a single error Bit 1 1 Indicates the SECDED interrupt is due to a double error Bit 3 Always 1 DDRC_ECC_INT_CLR_REG Table 7 99 DDRC ECC INT CLR REG Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDRC_ECC_INT_CLR_REG 0x0 _ This register should be written by the processor when it has read the SECDED error status infor
157. C_M2_WBEMPTY 0x0 1 Write buffer of AHBL master2 does not have valid data 0 Default DDR_FIC_SW_HPB_LOCKOUT_SR Table 7 229 DDR FIC SW HPB LOCKOUT SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide 7 5 3 1 compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_LCKTOUT 0x0 Indicates lock counter in arbiter reached its maximum value Lock counter 20 bit starts counting when a locked request gets access to a bus and will be cleared when the lock signal becomes logic 0 6 DDR_FIC_M2_WDSBL_DN 0x0 High indicates AHBL master2 write buffer is disabled 4 DDR_FIC_M2_RDSBL_DN 0x0 High indicates AHBL master2 read buffer is disabled 2 DDR_FIC_M1_WDSBL_DN 0x0 High indicates AHBL master1 read buffer is disabled 0 DDR_FIC_M1_RDSBL_DN 0x0 High indicates AHBL master1 write buffer is disabled DDR_FIC_SW_HPD_WERR_SR Table 7 230 DDR FIC SW HPD WERR SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_M1_WR_ERR 0x0 Status bit 368 Goes High when error response is received for buff
158. C_MUX_CONFIG Table 8 8 FDDR FACC MUX CONFIG Bit Number Name Reset Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation FACC_FAB_REF_SEL 0x0 Selects the source of the reference clock to be supplied to the FPLL 0 25 50 MHz RC oscillator selected as the reference clock for the FPLL 1 Fabric clock CLK_BASE selected as the reference clock for the FPLL FACC_GLMUX_SEL 0x1 Selects the four glitchless multiplexers within the FACC which are related to the aligned clocks All four of these multiplexers are switched by one signal Allowed values 0 M3_CLK PCLKO PCLK1 CLK_DDR_FIC all driven from stage 2 dividers from CLK_SRC 1 M3_CLK PCLKO PCLK1 CLK_DDR_ FIC all driven from CLK_STANDBY FACC_PRE_SRC_SEL 0x0 Selects whether clk_1mhz or ccc2asic is to be fed into the source glitchless multiplexer 0 clk_1mhz is fed into the source glitchless multiplexer 1 ccc2asic is fed into the source glitchless multiplexer 5 3 FACC_SRC_SEL 0x0 Selects the source multiplexer within the FACC This is used to allow one of four possible clocks to proceed through the FACC dividers for generation of normal functional run time FDDR subsystem clocks There are three individual 2 to 1 glitchless multiple
159. Ch Table 2 51 MSI 3 Bit Reset Number Name Value Description 31 27 MSI3 31 27 These bits set MSI Offset 3 of MSI MAP3 26 24 Msi3 26 24 These bits set MSI_TC 1 of MSI _MAP3 1 23 19 MSI3 23 19 These bits set MSI Offset 3 of MSI MAP3 18 16 MSI3 18 16 These bits set MSI TC 3 of MSI MAP3 15 11 MSI3 15 11 These bits set MSI Offset 2 of MSI MAP3 10 8 MSI3 10 8 These bits set MSI TC 2 of MSI MAP3 7 3 MSI3 7 3 These bits set MSI Offset 1 of MSI MAP3 20 mst20 These bits set MSI_TC 1 of MSI _MAP3 Revision 1 101 lt gt Microsemi PCI Express MSI 4 Register 090h Table 2 52 MSI 4 Bit Reset Number Name Value Description 31 27 MSI4 31 27 These bits set MSI Offset 3 of MSI MAP4 26 24 MSI4 26 24 These bits set MSI TC 1 of MSI MAP4 23 19 MSI4 23 19 These bits set MSI Offset 3 of MSI MAP4 18 16 MSI4 18 16 These bits set MSI TC 3 of MSI MAP4 15 11 MSI4 15 11 These bits set MSI Offset 2 of MSI MAP4 10 8 MSI4 10 8 These bits set MSI TC 2 of MSI MAP4 7 3 MSI4 7 3 These bits set MSI Offset 1 of MSI MAP4 2 0 MSI4 2 0 These bits set MSI TC 1 of MSI MAP4 MSI 5 Register 094h Table 2 53 MSI 5 Bit Reset Number Name Value Description 31 27 MSI5 31 27 These bits set MSI Offset 3 of MSI MAP5 26 24 MSI5 26 24 These bits set MSI TC 1 of MSI MAP5 23 19 MSI5 23 19 These bits set MSI Offset 3 of MSI MAP5
160. Configure the timeout value for each write buffer using the DDR FIC LOCK TIMEOUTVAL CR1 and DDR FIC LOCK TIMEOUTVAL CR2 registers Set the timeout value to maximum or a non Zero value Enable the write and read buffers of the DDR bridge using the DDR FIC HPD SW RW EN CR register The configuration registers for the MDDR DDR bridge and FDDR DDR bridge are listed under the DDR FIC registers section in the MDDR and FDDR chapters Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SYSREG Control Registers Table 9 2 lists MSS DDR bridge Control registers in the SYSREG block Refer to the System Register Map chapter of the ARM Cortex M3 Processor and Subsystem for SmartFusion2 SoC FPGA Devices User s Guide for a detailed description of each register and bit Table 9 2 e SYSREG Control Registers Register Flash Write Register Name Type Protect Reset Source Description DDRB_BUF_TIMER_CR RW P Register SYSRESET_N Uses a 10 bit timer interface to configure the timeout register in the write buffer module DDRB_NB_ADDR_CR RW P Register SYSRESET_N Indicates the base address of the non bufferable address region DDRB_NB_SIZE_CR RW P Register SYSRESET_N Indicates the size of the non bufferable address region DDRB_CR RW P Register SYSRESET_N MSS DDR bridge configuration register MSS_IRQ_ENABLE_CR RW P Register SYSRESET_N Configures
161. DATA slave DLL status register PHY WR DATA SLAVE DLL VAL 2 SR 0x3A8 RO PRESET N Write DATA slave DLL status register PHY WR DATA SLAVE DLL VAL 3 SR Ox3AC RO PRESET N Write DATA slave DLL status register PHY FIFO WE SLAVE DLL VAL 1 SR 0x3B0 RO PRESET N FIFO WE slave DLL status register PHY FIFO WE SLAVE DLL VAL 2 SR 0x3B4 RO PRESET N FIFO WE slave DLL status register PHY FIFO WE SLAVE DLL VAL 3 SR 0x3B8 RO PRESET N FIFO WE slave DLL status register PHY WR DQS SLAVE DLL VAL 1 SR 0x3BC RO PRESET N Write DQS slave DLL status register PHY WR DQS SLAVE DLL VAL 2 SR 0x3C0 RO PRESET N Write DQS slave DLL status register PHY WR DQS SLAVE DLL VAL 2 SR 0x3C4 RO PRESET N Write DQS slave DLL status register PHY CTRL SLAVE DLL VAL SR 0x3C8 RO PRESET NIDLL controller status register 318 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY Configuration Register Bit Definitions PHY_DYN_BIST_TEST_CR Table 7 101 PHY_DYN_BIST_TEST_CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 REG_PHY_AT_SPD_ATPG 0x0 1 Test with full clock speed but lower coverage 0 Test with lower clock speed but higher coverage 3 REG_PHY_BIST_ENABLE 0x0 Enable the internal
162. DDR1 in half quarter bus mode may boost performance For systems that tend to do many single cycle random transactions a burst length of 4 may slightly improve system performance 12 Reserved 0x0 This bit must always be set to zero 11 5 REG_DDRC_RDWR_IDLE_GAP 0x04 When the preferred transaction store is empty for this many clock cycles switch to the alternate transaction store if it is non empty The read transaction store both high and low priority is the default preferred transaction store and the write transaction store is the alternate store When Prefer write over read is set this is reversed 4 REG_DDRC_PAGECLOSE 0x0 1 Bank is closed and kept closed if no transactions are available for it This is different from auto precharge a Explicit precharge commands are used and not read write with auto precharge and b Page is not closed after a read write if there is another read write pending to the same page 0 Bank remains open until there is a need to close it to open a different page or for page timeout or refresh timeout This does not apply when auto refresh is used 3 Reserved This bit must always be set to zero 2 0 REG_DDRC_LPR_NUM_ENTRIES 0x03 Number of entries in the low priority transaction store is this value plus 1 READ_CAM_DEPTH REG_DDRC_LPR_NUM_ENTRIES 1 is the number of entries available for the high priority transaction store READ_CAM_DEPTH Depth o
163. DDRC ECC DATA MASK CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 8 1 CO_WU_RXDATA_INT_ECC 0x0 Internal SECDED This contains the SECDED associated with the data bus Data on this bus is presented to the Internal SECDED decode logic 0 CO_WU_RXDATA_MASK_INT_ECC 0x0 Mask to be used during production test Revision 1 273 I Microsemi MSS DDR Subsystem DDRC_ADDR_MAP_COL_1_CR Table 7 28 DDRC ADDR MAP COL 1 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 15 12 REG DDRC ADDRMAP COL B2 0x0 Full bus width mode Selects column address bit 3 Half bus width mode Selects column address bit 4 Quarter bus width mode Selects column address bit 5 Valid range 0 to 7 Internal base 2 The selected address bit is determined by adding the internal base to the value of this field 11 8 REG_DDRC_ADDRMAP_COL_B3 0x0 Full bus width mode Selects column address bit 4 Half bus width mode Selects column address bit 5 Quarter bus width mode Sel
164. DESIF System Registers continued CONFIG_PHY_MODE CONFIG_EPCS_SEL CONFIG_LINK2LANE 4 Bits Per Lane 1 Bit Per Lane 1 Bit Per Lane Mode Lane0 Lane1 Lane2 Lane3 Lane0 Lane1 Lane2 Lane3 LaneO Lane1 Lane2 Lane3 M11 PCle mode x2 and OxO 0x0 OxF OxF Ox0 0x0 Ox1 0x1 0x1 0x1 OxO 0x0 EPCS x2 nr pcie x2 epcs M12 PCle mode x1 and OxO OxF OxF OxF Ox0 0x1 Ox1 0x1 0x1 0x0 0x0 0 EPCS x2 nr pcie x1 epcs M13 PCle mode x2 with OxO 0x0 OxF OxF Ox0 0x0 Ox1 0x1 0x1 1 0x0 0x1 lane reverse and EPCS x2 r pcie x2 epcs M14 PCle mode x1 with OxF 0x0 OxF OxF 0x1 OxO 0x1 0x1 0x0 0x1 OxO 0x0 lane reverse and EPCS x2 r pcie x1 epcs Revision 1 19 I Microsemi SERDESIF Block Using the SERDESIF Macro in Libero SoC The high speed serial interface generator available in Libero SoC allows generation of the SERDESIF block with various protocol modes It allows to create single and multi protocol modes Figure 1 8 displays the main screen for the high speed serial interface generator for single protocol mode and Figure 1 9 on page 21 displays the main screen for high speed serial interface generator for multi protocol mode Single protocol Mode PCle Single protocol Mode XAUI gt Single protocol Mode EPCS Single protocol Mode SGMII Figure 1 8 SERDESIF Configurati
165. DEVID Bit Number Name Reset Value Description 31 16 Device ID Ox110A Identifies the manufacturer of the device or application The values are assigned by PCI SIG The default value 110A is the Vendor ID for Microsemi 15 0 Vendor ID 0x1556 The field Identifies the manufacturer of the device or application The values are assigned by PCI SIG The default value 1556 is the Vendor ID for Microsemi Table 2 17 CFG PRMSCR CFG_PRMSCR Register 004h Bit Number Name Reset Value Description 31 0 Class Code 0x00100000 The command and status register of PCI configuration space Table 2 18 CLASS CODE CLASS_CODE Register 008h EE Name Reset Value Description 31 16 CLASS CODE 0x0000 Identifies the manufacturer of the device or application The values are assigned by PCI SIG 15 0 RESERVEDO 0x0000 Identifies the manufacturer of the device or application The values are assigned by PCI SIG BARO Register 010h Table 2 19 BARO Bit Number Name Reset Value Description 31 4 BARO 31 4 0x000000 Defines the type and size of BARO of the PCIe native endpoint 3 BARO 3 Ox1 Identifies the ability of the memory space to be prefetched 2 1 BARO 2 1 0x10 Set to 00 to indicate anywhere in 32 bit address space 0 BARO 0 0x0 Memory space indicator 90 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces
166. DLVL DQS RATIO Ratio value generated by read data eye training FSM Table 7 187 PHY RDLVL DQS RATIO 3 SR PHY RDLVL DQS RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_RDLVL_DQS_RATIO 0x0 47 32 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM 350 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_RDLVL_DQS_RATIO_4_SR Table 7 188 PHY RDLVL DQS RATIO 4 SR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 PHY_REG_RDLVL_DQS_RATIO Ox0 49 48 bits of PHY REG RDLVL DQS RATIO Ratio value generated by read data eye training FSM PHY_FIFO_1_SR Table 7 189 PHY FIFO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved
167. DR3 LPDDR1 memories to the SmartFusion2 SoC FPGA family of devices The MDDR subsystem can be used to access DDR memories for high speed data transfers and code execution The MDDR subsystem includes the DDR memory controller and DDR PHY along with arbitration logic to support two different masters The DDR memories interfaced to the MDDR subsystem can be accessed by the MSS masters and master logic implemented in the FPGA fabric The MSS masters communicate with the MDDR subsystem through an MSS DDR bridge present in the MSS The MSS DDR Bridge provides an efficient access path between the MSS masters and MDDR subsystem Refer to the DDR Bridge section on page 395 for more information on the features provided by the MSS DDR Bridge The MDDR subsystem can also be connected to various bus masters resident in the FPGA fabric using AXI or AHB interfaces The following sections explain the features functionality and use models of the MDDR subsystem Features e Integrated on chip DDR memory controller and PHY e Configurable to support LPDDR1 DDR2 and DDR3 memory devices Up to 667 Mbps 333 MHz DDR performance e Supports memory densities up to 4 GB e Supports 8 16 32 bit DDR standard dynamic random access memory SDRAM data bus width modes e Supports a maximum of 8 memory banks Supports a single rank of memories e SECDED enable disable feature e Supports DRAM burst lengths of 4 8 or 16 depending on configured bus width mode an
168. DRAM address While configuring the registers ensure that no two DDR SDRAM address bits are determined by the same source address bit Each DRAM address bit has an associated register vector to determine its source The source address bit number is determined by adding the internal base of a given register to the programmed value for that register as described in EQ 1 Internal base register value source address bit number EQ 1 For example reading the description for REG DDRC ADDRMAP COL B3 the internal base is 3 so when the full data bus is in use the column bit 4 is determined by 3 register value If this register is programmed to 2 then the source address bit is 3 2 5 Notes 1 All of the column bits shift up 1 bit when only half of the data bus is in use In this case it is required to look at REG_DDRC_ADDRMAP_COL_B2 instead to determine the value of column address bit 4 2 Some registers map multiple source address bits REG DDRC ADDRMAP ROW BO 11 The address mapping registers are listed below DDRC_ADDR_MAP_BANK_CR DDRC_ADDR_MAP_COL_1_CR DDRC_ADDR_MAP_COL_2_CR DDRC_ADDR_MAP_COL_3_CR DDRC_ADDR_MAP_ROW_1_CR DDRC ADDR MAP ROW 2 CR DARREN gt Revision 1 235 lt gt Microsemi 7 MSS DDR Subsystem Introduction The microcontroller subsystem MSS double data rate DDR subsystem MDDR is an ASIC block available as a part of the SmartFusion2 SoC FPGA MSS for interfacing of DDR2 D
169. EG_DDRC_SOFT_RSTB 0x0 This is a soft reset 0 Puts the controller into reset 1 Takes the controller out of reset The controller should be taken out of reset only when all other registers have been programmed Asserting this bit does NOT reset all the APB configuration registers Once the soft reset bit is asserted the APB register should be modified as required DDRC_AXI_FABRIC_PRI_ID_CR Table 7 75 DDRC_AXI_FABRIC_PRI_ID_CR Bit Number Name Reset Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 4 PRIORITY_ENABLE_BIT 0x0 This is to set the priority of the fabric master ID 01 Indicates that the ID is higher priority but still lower than the ICache and DSG bus 10 11 Indicates that the ID has the highest priority even higher than ICache and DSG bus to be used for isochronous traffic display applications only This only affects the reads Writes would still have the priority lower than Cache DSG 00 None of the master IDs from the fabric have a higher priority 3 0 PRIORITY ID 0x0 If the Priority Enable bit is 1 this ID will have a higher priority over other IDs 300 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interf
170. ERDESIF 0 and x 1 for SERDESIF 1 If unused can be left floating PCIE_x_TXDN3 PCIE_x_REXTL Reference I O Pads External reference resistor connection to calibrate TX RX termination value Each SERDESIF consists of 2 REXT signals one for lanes 0 land 1 and another for lanes 2 and 3 Here x 0 for SERDESIF_0 and x PCIE_x_REXTR 1 for SERDESIF 1 If unused can be left floating PCIE_x_REFCLKOP Input I O Pads Reference clock differential positive Each SERDESIF consists of two signals REFCLKO_P REFCLK1 P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not PCIE X REFGLKIP activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating PCIE_x_REFCLKON Input I O Pads Reference clock differential negative Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be used for MSIOD fabric if SERDESIF is not activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating Port Type Description Connected to PCIE_INTERRUPT 3 0 Input PCle system interrupt inputs Fabric PCIE_SYSTEM_INT Output PCle system interrupt output Fabric PCIE_P 35 0 Input PC bits from fabric Fabric WAKE_REQ Input L2 P2 implementation 12 request from G4M fabric Fabric WAKE_N Output L2 P2 implementation 12 exit request to RP Fabric Revision 1 121 I Microsemi PC
171. ERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods Revision 1 227 I Microsemi Serializer Deserializer PRBS_ERR_CYC_FIRST_15_8 Register Table 5 134 PRBS ERR CYC FIRST 15 8 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 15 8 PRBS last error cycle counter register bits 15 8 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS ERR CYC FIRST 23 16 Register Table 5 135 PRBS ERR CYC FIRST 23 16 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 23 16 PRBS last error cycle counter register bits 23 16 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error
172. ES block on the other side The PCle system block interface signals to fabric are shown below 1 AXI AHBL master interface AXI AHBL slave interface APB interface 32 bit PCle system clock interface af ON PCle system reset Interface 6 PCle interrupt and power management interface Table 2 124 PCle System AXI AHBL Master Interface Port Type Description Connected to M AWID 3 0 Output AXI master mode AWID Fabric M AWADDR HADDR 31 0 Output AXI master mode AWADDR Fabric AHBL master mode HADDR M_AWLEN_HBURST 3 0 Output AXI master mode AWLEN Fabric AHBL master mode HBURST M_AWSIZE_HSIZE 1 0 Output AXI master mode AWSIZE 1 Fabric AHBL master mode HSIZE M_AWBURST_HTRANS 1 0 Output AXI master mode AWBURST Fabric AHBL master mode HTRANS M_AWVALID_HWRITE Output AXI master mode AWVALID Fabric AHBL master mode HWRITE M_AWREADY Input AXI master mode AWREADY Fabric M WID 3 0 Output AXI master mode WID Fabric M WSTRB 7 0 Output AXI master mode WSTRB Fabric IMWLAST Output AxImastermode WLAST 1 Fabric M WVALID Output AXI master mode WVALID Fabric M WDATA HWDATA Output AXI master mode WDATA Fabric AHBL master mode HWDATA M WREADY HREADY Input AXI master mode WREADY Fabric AHBL master mode HREADY M BID 3 0 Input AXI master mode BID Fabric M BRESP HRESP 1 0 Input AXI master mode BRESP Fabric AHBL master mode
173. F configurator as shown in Figure 4 6 refclk_io0 ee APB_S PCLK Trapt refelk io1 ccc ref cik aREFCLK 1 0 Fabric epcs rxcik 1 epcs rxcik 0 lane01 refcik sel epcs rxcik 3 0 epcs rxcik 1 aREFCLK 3 2 epcs rxcik 0 lane23 refcik sel epcs txcik 3 0 epcs txcik 1 epcs txcik 0 SERDES Figure 4 5 EPCS Clock Network S Configuring SERDES IF 0 SERDES IF 0 0 500 Protocol 1 Type EPCS v Protocol 2 Type Protocol 1 Number of Lanes x4 VW Protocol 2 Number of Lanes Protocol 1 Speed 2 5 Gbps v Protocol 2 Speed Protocol 1 PHY Reference Clock 1 O Porto 7 Protocol 2 PHY Reference Clock _ YO Port1 Lane Assignment ord i Protocol for Lane 0 Jepcs X Protocol For Lane 1 Ecs 7 Protocol For Lane 2 FP z Protocol for Lane 3 Ecs p Figure 4 6 e SERDES Reference Clock Selection Using SERDESIF Configurator 160 In EPCS mode it is needed to configure and control the SERDES block to implement the user defined protocol This can be done using the SERDES registers which are accessed by the APB bus The APB bus interface clock APB S PCLK is used for this purpose Refer to the Serializer Deserializer section on page 169 for the details regarding the SERDES register detail Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide EPCS SERDES Calibrati
174. FO read enable after fixed number of clock cycles as defined by REG PHY RDC WE TO RE DELAY 3 0 0 PHY uses the NOT EMPTY method to do the read enable generation Note This port must be set High during the training leveling process when DDRC DFI WRLVL EN DDRC DFI RDLVL EN DDRC DFI RDLVL GATE EN PORT is set High Revision 1 343 I Microsemi MSS DDR Subsystem PHY USE RANKO DELAYS CR Table 7 168 PHY USE RANKO DELAYS CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY USE RANKO DELAYS 0x0 Delay selection This applies to multi rank designs only 1 Rank 0 delays are used for all ranks 0 Each rank uses its own delay This port must be set High when write latency lt 5 PHY USE LVL TRNG LEVEL CTRL CR Table 7 169 PHY USE LVL TRNG LEVEL CTRL CR Bit Number Name Reset Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 REG_PHY_USE_WR_LEVEL 0x0 Write leveling training control 0 Use register programmed ratio values 1 Use ra
175. FO_WE_SLAV E_DLL_VALUE Delay value applied to FIFO WE slave DLL Revision 1 359 lt gt Microsemi MSS DDR Subsystem PHY_WR_DQS_SLAVE_DLL_VAL_1_SR Table 7 211 PHY WR DQS SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE 0x0 15 0 bits of PHY_REG_STATUS_WR_DQS_SLAV E DLL VALUE Delay value applied to write DQS slave DLL PHY_WR_DQS_SLAVE_DLL_VAL_2_SR Table 7 212 PHY WR DQS SLAVE DLL VAL 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_REG_STATUS_WR_DQS_SL AVE_DLL_VALUE Delay value applied to write DQS slave DLL PHY_WR_DQS_SLAVE_DLL_VAL_3_SR Table 7 213 PHY WR DQS SLAVE DLL VAL 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved
176. FPGA Logic The following sections briefly describe each of these serial protocols and their implementation in SmartFusion2 SoC FPGA devices using the SERDESIF block Revision 1 9 I Microsemi SERDESIF Block PCle Endpoint The SmartFusion2 SoC FPGA family supports PCle endpoints The PCle endpoint supports PCle Base Specification 1 1 for Gen1 and PCle Base Specification 2 0 for Gen1 2 5 bps or Gen2 5 0 bps protocol with width of x1 x2 or x4 The application interface to the PCle link is available through the FPGA and can be programmed to AXI or AHB master and slave interfaces SERDESIF Block SERDES SERDES PMA PCle PCS lege SERDESIF System PCle Register System IP Y PCle L2 P2 AXI AHB AXI AHB APB Slave Control Master Slave Interface Interface Interface FABRIC Figure 1 4 e SERDESIF Configuration for PCle Protocol 10 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 2 shows the possible options for implementing the PCle link on four physical SERDES lanes Refer to the PCI Express section on page 59 for details on PCle protocol implementation in SmartFusion2 SoC FPGA devices Table 1 2 Physical Interface Options for PCle Endpoint in the SERDESIF Block PHYSICAL SERDES LANES LOGICAL LANES Mapping Lane0 Lane1 Lane2 Lane3 Speed
177. Fabric APB Slave interface PENABLE APB S PWRITE Input Fabric APB Slave interface PWRITE APB S PADDR 13 0 Input Fabric APB Slave interface PADDR APB S PWDATA 31 0 Input Fabric APB Slave interface PWDATA APB 8 PREADY Output Fabric APB Slave interface PREADY Revision 1 47 lt gt Microsemi SERDESIF Block Table 1 56 e SERDESIF Block APB Slave Interface continued Connected Port Type To Description APB_S_PRDATA 31 0 Output Fabric APB Slave interface PRDATA APB_S_PSLVERR Output Fabric APB Slave interface PSLVERR Table 1 57 e SERDESIF Block EPCS Interface Lane2 and Lane3 EPCS 3 TX CLK STABLE Connected Port Type To Description EPCS 2 PWRDN Input Fabric EPCS interface lane2and lane3 Power down EPCS 3 PWRDN mode of the PMA EPCS_3_TX_DATA 19 0 Input Fabric EPCS interface lane2 and lane3 Signal EPCS 3 TX DATA 19 0 detected 1 b0 needed for SATA EPCS 2 TX VAL Input Fabric EPCS interface lane2 and lane3 Transmit data EPCS 3 TX VAL valid EPCS 2 TX OOB Input Fabric EPCS interface lane2 and lane3 Transmit idle EPCS 3 TX OOB needed for SATA OOB EPCS 2 RX ERR Input Fabric EPCS interface lane2 and lane3 Receiver EPCS 3 RX ERR error detected EPCS 2 READY Output Fabric EPCS interface lane2 and lane3 PHY training EPCS 3 READY completed EPCS 2 RXDATA 19 0 Output Fabric EPCS interface lane2 and lane3 Received EPCS 3
178. GA devices implement three DDR bridges in the MSS MDDR and FDDR subsystems Table 9 1 explains the master interfaces in SmartFusion2 SoC FPGA subsystems Table 9 1 DDR Bridges in SmartFusion2 SoC FPGA Devices DDR Bridge Sub Master Interface 0 Master a 1 Master aie 2 Master eo 3 Seon Read Only Slave Interface MSS Cache controller IDC controller IDC Cache controller DS controller DS AHB bus matrix bus matrix HPDMA DMA MDDR MDDR subsystem me Ee PS re bes mt interface ee ioi interface DDR E subsystem FDDR AHB master interface AHB master interface FDDR subsystem 0 1 Note If the AXI bus is selected as the interface between the FPGA fabric and the DDR controller in the MDDR and FDDR subsystem the DDR bridge in those subsystems is not used MSS DDR Bridge The DDR bridge implemented in the MSS provides an interface between AHB masters within the MSS and the MDDR subsystem as shown in Figure 9 2 SmartFusion2 MSS ARM Cortex M3 Controller Write Combining Buffers Arbiter MDDR AHB Bus and Subsystem Matrix Read Buffers MSS DDR Bridge Figure 9 2 e MSS DDR Bridge Architecture 396 Revision 1 SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MDDR Subsystem DDR Bridge The DDR bridge implemented in the MDDR subsystem provides an interface between user implemented AHB masters in the FPGA fabric as shown in Figure 9 3 The DDR bridge in the MDDR subsystem is lt
179. HALF 0x20 RW ITX amplitude ratio TXMargin 7 half swing OXOCO PMA STATUS 0x00 RO PMA status OX0C4 TX SWEEP CENTER 0x00 RO TX sweep center Ox0C8 RX_SWEEP_CENTER 0x00 RO RX sweep center OXOCC RE SWEEP CENTER 0x00 RO RX equalization sweep center OX0DO ATXDRR 7 0 0x00 RO Receiver shift loader parameter 0 0X0D4 ATXDRR 14 8 0x00 RO Receiver shift loader parameter 1 0X0D8 ATXDRP_DYN_7_0 0x00 RO Transmitter P shift loader parameter 0 0 OXODC ATXDRP DYN 158 0x00 RO Transmitter P shift loader parameter 0 1 OXOEO ATXDRP_DYN_20_16 0x00 RO Transmitter P shift loader parameter 0 2 OX0E4 ATXDRA_DYN_7_0 0x00 RO Transmitter A shift loader parameter 0 0 OXOE8 ATXDRA_DYN_15_8 0x00 RO Transmitter A shift loader parameter 0 1 OXOEC ATXDRA_DYN_20_16 0x00 RO Transmitter A shift loader parameter 0 2 Revision 1 185 I Microsemi Serializer Deserializer Table 5 2 e SERDES Macro Registers continued Offset Reset Hex Register Name Value Type Description OXOFO ATXDRT DYN 7 0 0x00 RO Transmitter T shift loader parameter 0 0 OX0F4 ATXDRT_DYN_15_8 0x00 RO Transmitter T shift loader parameter 0 1 OXOF8 ATXDRT DYN 20 16 0x00 RO Transmitter T shift loader parameter 0 2 OXOFC ATXDRP_EI1_7_0 0x00 RO Transmitter P shift loader parameter 1 0 0X100 ATXDRP_EI1_15_8 0x00 RO Transmitter P shift l
180. Hz mode lane3 4 b0100 EPCS 1 25 GHz mode lane3 4 b0101 EPCS undefined mode lane3 4 b1111 SERDES PHY lane3 is off CONFIG PHY MODE 11 8 CONFIG PHY MODE 11 8 Defines lane2 settings 4 b0000 PCIe mode lane2 4 b0001 XAUI mode lane2 4 b0011 EPCS 2 5 GHz mode lane2 4 b0100 EPCS 1 25 GHz mode lane2 4 b0101 EPCS undefined mode lane2 4 b1111 SERDES PHY lane2 is off CONFIG PHY MODE 7 4 CONFIG PHY MODE 7 4 Defines lane1 settings 4 b0000 PCIe mode lane1 4 b0001 XAUI mode lane1 4 b0011 EPCS 2 5 GHz mode lane1 4 b0100 EPCS 1 25 GHz mode lane1 4 b0101 EPCS undefined mode lane1 4 b1111 SERDES PHY lane is off Notes 1 XAUI 10 Gbps attachment unit interface 2 EPCS External physical coding sub layer 3 SGMII Serial Gigabit Media Independent Interface 4 Bits not shown here are unused Revision 1 67 I Microsemi PCI Express Table 2 4 PCle Mode Settings Using the SERDESIF System Register continued SERDESIF System APB Registers Description CONFIG PHY MODE S 0 CONFIG PHY MODE 3 0 Defines lane0 settings 4 b0000 PCIe mode lane0 4 b0001 XAUI mode laneO 4 b0011 EPCS 2 5 GHz mode lane0 4 b0100 EPCS 1 25 GHz mode lane0 4 b0101 EPCS undefined mode lane0 4 b1111 SERDES PHY lane0 is off CONFIG EPCS SEL 3 0 For each lane one bit of this signal defines whether the external PCS interface is used or the PCle PCS is enabled 1
181. I Express Appendix A PCle Configuration Space Figure 2 21 PCle Configuration Space 122 Revision 1 The PCle base IP core transaction layer TL contains the 4 KB configuration space The configuration space implements all configuration registers and associated functions It manages BAR and window decoding interrupt MSI message generation power management negotiation and error handling For upstream ports the configuration space is accessed through the PCIe link using Type 0 requests Type 1 requests are forwarded to the application layer For downstream ports the configuration space is accessed through the application interface using Type 0 requests Type 1 requests are forwarded to the PCIe link The first 256 bytes of the configuration space are the function s configuration space and the remaining configuration space is PCle extended configuration space see Figure 2 21 FFFh PCI Express Extended Extended Configuration Configuration Space Space t for PCI Express not visible on parameters and legacy operating capabilities not systems available on legacy operating systems PCI Express OFFh Capability Structure Capabioity needed by BIOS or by driver software on PCI Configuration non PCI Express Space available on aware operatin legacy operating z eae 9 systems through y legacy PCI mechanisms 03Fh PCI 3 0 Compatible Configuration Space Header 000h lt gt Microsemi SmartFusion2 SoC FPGA High Speed
182. I O pad Interface Active Miscellaneous interface Active PLL control and status interface Active 52 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Figure 1 17 shows the SERDESIF I O signals in Fabric mode SERDES_IF_0 CORE_RESET_N PCIE_SYSTEM_INT JCORE_RESET_N PCIE INTERRUPT 3 0 PCIE EV 1US AHB MASTER REFCLKO P REFCLKO N TXD2_P RXDO_P TXD2_N RXDO_N TXD3_P RXD1_P TXD3_N RXD1_N RXD2_P RXD2_N RXD3_P RXD3_N Figure 1 17 SERDESIF I O Signals in Fabric Mode1 Fabric Signals for Fabric Mode2 In Fabric mode2 overlaid EPCS interfaces for laneO and lane1 are exposed to fabric Non overlaid EPCS interface for lane2 and lane3 are exposed directly to fabric and is active interface The SERDESIF can be configured to support only single protocol in Fabric mode2 The application interface to the SERDESIF for EPCS protocol s is EPCS interface maximum x4 lane The EPCS interface for laneO and lane1 are overlaid on AXI master and slave interface The EPCS interface for lane2 and lane3 are non overlaid interface and are directly connected to the fabric EPCS protocols can be run with x1 x2 x4 lane support Table 1 64 lists the SERDESIF signals and behavior in Fabric mode2 Table 1 64 e SERDESIF Signals in Fabric Mode2 SERDESIF Signal Interface Interface Behavior Clock and reset interface Active AXI AH
183. IC ERR INT ENABLE Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 SYR_SW_WR_ERR OxO Status bit Goes High when error response is received for bufferable write request Goes Low when processor serves interrupt and makes clear bit for AHBL master1 0 SYR_HPD_WR_ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes Low when processor serves the interrupt Revision 1 365 I Microsemi MSS DDR Subsystem DDR_FIC_NUM_AHB_MASTERS_CR Table 7 223 DDR FIC NUM AHB MASTERS CR Bit Number Name Value Reset Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation CFG_NUM_AHB_MASTERS 0x0 Defines whether one or two AHBL 32 bit masters are implemented in the fabric 0 One 32 bit AHB master implemented in fabric 1 Two 32 bit AHB masters implemented in fabric 3 0 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pre
184. ING EIEPCS 3 IN T EPCS 2 RX RESET N EPCS 3 TX DATA 19 0 EPCS_2 IX RESET_N eres a EPES REN EPCS 3 OUTE TIEPCS 3 OUT EPCS 3 RESET N EPCS 3 RX DATA 19 0 EPCS 3 RX VAL EPCS 3 RX IDLE EPCS 3 TX CLK ST BLE EPCS_3 RX RESET N EPCS 3 TX RESET N EPCS 3 RX CLK EPC8 3 TX CLK Figure 1 18 SERDESIF I O Signals in Fabric Mode2 Fabric Signal MUXing for Fabric Mode3 In Fabric mode3 overlaid XGMII interfaces for XAUI protocol is exposed to the SmartFusion2 SoC FPGA fabric The XGMII interface is overlaid on AXI master and slave interface The SERDESIF can be configured to support only XAUI protocol in Fabric mode3 The application interface to the SERDESIF for XAUI protocol is XGMII interface x4 lane Table 1 65 on page 55 lists the SERDESIF signals and behavior in Fabric mode3 54 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 65 SERDESIF Signals in Fabric Mode3 SERDESIF Signal Interface Interface Behavior Clock and reset interface Active AXI AHBL master interface Active XGMII interface for XAUI protocol AXI AHBL slave interface Active XGMII interface for XAUI protocol APB interface 32 bit Active Inactive EPCS interface lane2 and lane3 Inactive IO pad interface Active Miscellaneous interface Active Figure 1 19 shows the SERDESIF I O signals in Fabric mode3 KAU MMD MO
185. ITE Fabric APB_S_PADDR 13 0 Input APB Slave interface PADDR Fabric APB S PWDATA 31 0 Input APB Slave interface PWDATA Fabric APB S PREADY Output APB Slave interface PREADY Fabric APB 8 PRDATA 31 0 Output APB Slave interface PRDATA Fabric APB 8 PSLVERR Output APB Slave interface PSLVERR Fabric Revision 1 167 I Microsemi EPCS Interface Glossary EPCS External Physical Coding Sublayer FPGA Field programmable gate array PCle Peripheral component interconnect express SERDES Serialize and de serializer SGMII Serial gigabit media independent interface XAUI eXtended attachment unit interface 168 Revision 1 lt gt Microsemi 5 Serializer Deserializer I O I O SmartFusion2 SoC FPGA family has two hard high speed serial interface blocks SERDESIFO and SERDESIF1 Each SERDESIF block has a serializer deserializer SERDES macro block that fully implements physical media attachment PMA and the PCI Express PCle physical coding sublayer PCS PMA includes the SERDES TX and RX buffers clock generator and clock recovery circuitry The PCS contains the 8b 10b encoder decoder RX detection and elastic buffer for the PCI Express physical coding sublayer Figure 5 1 shows the SERDES macro block diagram The PCS layer interface is compliant to the Intel PHY Interface for the PCI Express Architecture v2 00 specification PIPE The PCle PCS functionality can be bypassed completely in order
186. IT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM 340 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_WRLVL_INIT_RATIO_3_CR Table 7 162 PHY WRLVL INIT RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 47 32 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM PHY_WRLVL_INIT_RATIO_4_CR Table 7 163 PHY WRLVL INIT RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WRLVL_INIT_MODE 0x0 49 48 bits of REG_PHY_WRLVL_INIT_MODE The user programmable init ratio used by the write levelin
187. J Protocol 1 Number of Lanes v Protocol 2 Number of Lanes pm Protocol 1 Speed GEN 2 5 0 Gbps vi Protocol 2 Speed a Protocol 1 PHY Reference Clock 1 0 Porto nd Protocol 2 PHY Reference Clock a Lane Assignment Protocol For Lane 0 Pcie z Protocol for Lane 1 Jpcte p Protocol For Lane 2 P z Protocol for Lane 3 fce Figure 2 6 PCle Single Protocol Mode Setting in High Speed Serial Interface Generator Protocol Selection Protocol 1 Type Pcie v Protocol 2 Type Jercs v Protocol 1 Number of Lanes x2 v Protocol 2 Number of Lanes x2 v Protocol 1 Speed GEN 2 5 0 Gbps 7 Protocol 2 Speed 2 5 Gbps v Protocol 1 PHY Reference Clock 1 0 Porta Protocol 2 PHY Reference Clock I O Porti v Lane Assignment Protocol for Lane 0 Pcie x Protocol for Lane 1 Pcie z Protocol for Lane 2 JePcs z Protocol for Lane 3 Eres z Figure 2 7 PCle Multi Protocol Mode Setting in High Speed Serial Interface Generator 70 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Lane Reversal The SmartFusion2 SoC FPGA PCle system supports lane reversal capabilities and therefore provides flexibility in the design of the board It is possible for any user to choose to lay out the board with reversed lane numbers and the PCle endpoint will continue to link train successfully and operate normally The high speed serial interface gen
188. LANE Revision 1 155 I Microsemi EPCS Interface Table 4 4 EPCS Mode Settings Using The SERDESIF System Register SERDESIF System APB Registers Description CONFIG PHY MODE 15 0 For each lane this signal selects the protocol default settings which sets the reset value of the registers space CONFIG PHY MODE 15 12 Defines Lane3 settings e 460000 PCIE mode Lane3 460001 XAUI mode Lane3 e 460010 EPCS SGMII mode Lane3 e 4b0011 EPCS 2 5 GHz mode Lane3 e 4 b0100 EPCS 1 25 GHz mode Lane3 e 4 b0101 EPCS undefined mode Lane3 e 4 b1111 SERDES PHY Lane3 is off CONFIG_PHY_MODE 11 8 Defines Lane2 settings e 460000 PCIE mode Lane2 460001 XAUI mode Lane2 e 4b0011 EPCS 2 5 GHz mode Lane2 e 4 b0100 EPCS 1 25 GHz mode Lane2 e 4 b0101 EPCS undefined mode Lane2 e 4 b1111 SERDES PHY Lane2 is off CONFIG_PHY_MODE 7 4 Defines Lane1 settings e 460000 PCIE mode Lane1 e 4 b0001 XAUI mode Lane1 e 4b0011 EPCS 2 5 GHz mode Lane1 e 460100 EPCS 1 25 GHz mode Lane1 e 4b0101 EPCS undefined mode Lane1 e 4b1111 SERDES PHY Lane1 is off CONFIG_PHY_MODE 3 0 Defines LaneO settings 460000 PCIE mode LaneO e 4 b0001 XAUI mode LaneO e 4 b0011 EPCS 2 5 GHz mode LaneO e 4 b0100 EPCS 1 25 GHz mode LaneO e 4 b0101 EPCS undefined mode LaneO e 4 b1111 SERDES PHY Lane0 is off CONFIG EPCS SEL 3 0 For each lane one bit of this signal defines whether the external P
189. LAVE_DLL_VALUE 0x0 15 0 bits of PHY_STATUS_RD_DQS_SLAVE _DLL_VALUE Delay value applied to read DQS slave DLL PHY_RD_DQS_SLAVE_DLL_VAL_2_SR Table 7 203 PHY RD DQS SLAVE DLL VAL 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_RD_DQS_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_STATUS_RD_DQS_SLAVE_D LL_VALUE Delay value applied to read DQS slave DLL PHY_RD_DQS_SLAVE_DLL_VAL_3_SR Table 7 204 PHY RD DQS SLAVE DLL VAL 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_RD_DQS SLAVE DLL VALUE 0x0 44 32 bits of PHY STATUS RD DQS SLAVE DLL VALUE Delay value applied to read DQS slave DLL Revision 1 357 lt gt Microsemi MSS DDR Subsystem PHY_WR_DATA_SLAVE_DLL_VAL_1_SR Table 7 205 PHY WR DATA SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should
190. LCE SYNDROME 4 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 63 48 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CRis written over by the system 310 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC LCE SYNDROME 5 SR Table 7 90 DDRC LCE SYNDROME 5 SR Bit Reset Number Name Value Description 16 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a re
191. LEVEL 0x0 This port determines whether the delay line clock stalls at High or Low level The expected input is a very slow clock to avoid asymmetric aging in delay lines This port is implementation specific and may not be available in all PHYs 1 REG_PHY_CMD_LATENCY 0x0 Extra command latency 1 Command bus has 1 extra cycle of latency 0 Default This port is available only when MEMP_CMD_PIPELINE is defined PHY_RD_WR_GATE_LVL_CR Table 7 171 PHY RD WR GATE LVL CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 10 REG_PHY_GATELVL_INC_MODE 0x0 Incremental read DQS gate training mode One bit for each data slice 1 Incremental read gate training 0 Normal read gate training 9 5 REG_PHY_WRLVL_INC_MODE 0x0 Incremental write leveling mode One bit for each data slice 1 Incremental write leveling 0 Normal write leveling 4 0 REG_PHY_RDLVL_INC_MODE 0x0 Incremental read data eye training mode One bit for each data slice 1 Incremental read data eye training Revision 1 345 I Microsemi MSS DDR Subsystem PHY_DYN_RESET_CR Table 7 172 PHY DYN RESET CR Bit Reset Number Name Value Description 31 1
192. LaneO clean reset de asserted on EPCS 0 TX CLK lepcs 1 TX RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS_1_TX_CLK lepcs 2 Tx RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS 2 TX CLK lepcs 3 TX RESET N Output Fabric EPCS interface LaneO clean reset de asserted on EPCS 3 TX CLK epcs 0 TX CLK Output Fabric EPCS interface LaneO Tx Clock epcs 1 TX CLK Output Fabric EPCS interface Lane1 Tx Clock epcs 2 TX CLK Output Fabric EPCS interface Lane2 Tx Clock epcs_3_TX_CLK Output Fabric EPCS interface Lane3 Tx Clock epcs_0_Rx_CLK Output Fabric EPCS interface LaneO Rx Clock epcs_1_Rx_CLK Output Fabric EPCS interface Lane1 Rx Clock epcs_2_Rx_CLK Output Fabric EPCS interface Lane2 Rx Clock 166 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 4 8 e SERDESIF Block EPCS Interface continued Port Type Connected to Description fepcs_3_Rx_CLK Output Fabric EPCS interface Lane3 Rx Clock Table 4 9 SERDESIF Block APB Slave Interface Port Type Description Connected to APB S PCLK Input APB Slave interface PCLK Fabric APB_S_PRESET_N Input APB Slave interface PRESETN Async Set Fabric APB_S_PSEL Input APB Slave interface PSEL Fabric APB_S_PENABLE Input APB Slave interface PENABLE Fabric APB S PWRITE Input APB Slave interface PWR
193. M 17 This bit sets master loopback R W 16 LTSSM 16 This bit disables scrambling R W 15 2 LTSSM 15 2 Reserved 1 LTSSM 1 This bit indicates if PME TURN OFF was received RO 0 LTSSM 0 This bit acknowledges PME TURN OFF RW 94 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide POWER_MGT_CAPABILITY Register 048h Table 2 33 POWER MGT CAPABILITY Bit Reset Number Name Value Description 31 27 POWER MGT CAPABILITY 31 27 These bits set PME support 26 POWER MGT CAPABILITY 26 This bit sets D2 support If this field is cleared PME SUPPORT bit 29 must also be cleared 25 POWER MGT CAPABILITY 25 This bit sets D1 support If this field is cleared PME SUPPORT bit 28 must also be cleared 24 22 POWER MGT CAPABILITY 24 22 These bits set maximum current required 21 POWER MGT CAPABILITY 21 This bit sets device specification initialization 20 19 POWER MGT CAPABILITY 20 19 Reserved 18 POWER MGT CAPABILITY 18 This bit sets PCI power management interface specification version hardwired to 011b PCle Spec v1 1 17 0 POWER MGT CAPABILITY 17 0 Reserved CFG PMSCR Register 04Ch Table 2 34 CFG PMSCR Bit Reset Number Name Value Description 31 0 CFG PMSCR This register reports the current values of the PCIe IP core s power management control Status register AER ECRC CAPABILITY
194. MSI TC 2 of MSI MAPO 7 3 MSIO 7 3 These bits set MSI Offset 1 of MSI MAPO 2 0 MSI0 2 0 These bits set MSI TC 1 of MSI MAPO 100 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MSI 1 Register 084h Table 2 49 MSI 1 Bit Reset Number Name Value Description 31 27 MSI1 31 27 These bits set MSI Offset 3 of MSI MAP1 26 24 MSI1 26 24 These bits set MSI TC 1 of MSI MAP1 23 19 MSI1 23 19 These bits set MSI Offset 3 of MSI MAP1 18 16 Msn 1816 These bits set MSI_TC 3 of MSI_MAP4 1 15 11 MSI1 15 11 These bits set MSI Offset 2 of MSI MAP1 10 8 MSI1 10 8 These bits set MSI TC 2 of MSI MAP1 7 3 MSI1 7 3 These bits set MSI Offset 1 of MSI MAP1 2 0 MSI1 20 These bits set MSI TC 1 of MSI MAP1 MSI 2 Register 088h Table 2 50 MSI 2 Bit Reset Number Name Value Description 31 27 MSI2 31 27 These bits set MSI Offset 3 of MSI MAP2 26 24 MSI2 26 24 These bits set MSI TC 1 of MSI MAP2 23 19 MSI2 23 19 These bits set MSI Offset 3 of MSI MAP2 18 16 MSI2 18 16 These bits set MSI TC 3 of MSI MAP2 15 11 MSI2 15 11 These bits set MSI Offset 2 of MSI MAP2 1108 Mmsi2108 ThesebitssetMSI TC 2JofMsLMAP2 7 3 MSI2 7 3 These bits set MSI Offset 1 of MSI MAP2 2 0 MSI2 2 0 These bits set MSI TC 1 of MSI MAP2 MSI 3 Register 08
195. Memory Controller Fabric Interface Controller Table 10 2 SMC FIC AXI 64 Port List continued Width Port Name Direction Description 1 MDDR SMC AXI M RLAST In Indicates the last transfer in a read burst 1 MDDR_SMC_AXI_M_RVALID In Indicates whether the required read data is available and the read transfer can complete 1 Read data available 0 Read data not available 4 MDDR_SMC_AXI_M_AWLEN Out Indicates burst length The burst length gives the exact number of transfers in a burst This information determines the number of data transfers associated with the address 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 2 MDDR_SMC_AXI_M_AWBURST Out Indicates burst type The burst type coupled with the size information details how the address for each transfer within the burst is calculated 00 FIXED Fixed address burst FIFO type 01 INCR Incrementing address burst normal sequential memory 10 WRAP Incrementing address burst that wraps to a lower address at the wrap boundary 11 Reserved 4 MDDR_SMC_AXI_M_AWID Out Indicates identification tag for the write address group of signals 64 MDDR_SMC_AXI_M_WDATA Out Indicates write data 4 MDDR_SMC_AXI_M_WID Out Indicates ID tag of the write data transfer The SMC_AXI64_WID value must match the SMC_AXI64_AWID value of the write transaction
196. Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 8 Depicts Definition of XS Status 1 Register continued Reg01 M XGXS PHY DTE XS Status 1 Bit Reset Number Name Value Description 2 PHY DTE 0x0 When read as a one the receive link is up transmit receive link 1 b0 Link down SAG 1 b1 Link up The receive link status bit is implemented with latching low behavior 1 Low power ability 0x1 When read as a one it indicates that the Low power feature in supported 1 b10 Low power not supported 1 b1 Low power is supported 0 Reserved 0x0 Table 3 9 Depicts Definition of XS Device Identifier Low Register Reg02 M XGXS PHY DTE XS ID Low Bit Reset Number Name Value Description 15 0 Organizationally unique 0x0 Reg02 and Reg03 provide a 32 bit value which may constitute a identifier OUI unique identifier for a particular type of SERDES The identifier shall be composed of the 3rd through 24th bits of the OUI assigned to the device manufacturer by the IEEE a 6 bit model number and a 4 bit revision number This Reg02 sets bits 3 18 of the OUI Bit 3 of the OUI is located in bit 15 unique identifier of the register and bit 18 of the OUI is located in bit 0 of the register Table 3 10 Definition of XS Device Identifier High Register Reg03 M XGXS PHY DTE XS ID High Bit Reset Number Name Value Descripti
197. Minimum time from an activate command to a READ or WRITE command to the same bank REG_DDRC_WR2PRE tWR Write Command Minimum time from a WRITE command to a Period precharge command to the same bank REG_DDRC_RD2PRE al bl 2 Read to Precharge Minimum time from a READ command to a Delay precharge command to the same bank Set this to the current value of additive latency plus half of the burst length Revision 1 245 lt gt Microsemi MSS DDR Subsystem Dynamic DRAM Rank Constraints One rank constraints block enforces all of the following constraints for each rank supported by the system Using the rank constraints blocks the scheduler dynamically obeys all of the following constraints on a per rank basis when scheduling transactions Table 7 9 Table 7 9 Dynamically Enforced Bank Constraints Constraint Constraint Control Signal Abbreviation Name Constraint Meaning REG DDRC T RFC NOM X32 tRFC nom or Nominal Refresh Average time between refreshes for a given tREFI Cycle Time rank The actual time between any 2 refresh commands may be larger or smaller than this this represents the maximum time allowed between refresh commands to a given rank when averaged over a large period of time REG DDRC T RFC MIN tRFC min Minimum Refresh Minimum time from refresh to refresh or Cycle Time activate REG DDRC T RRD tRRD RAS to RAS Minimum time between activates from bank Delay a to ban
198. N_CR Table 7 66 DDRC DFI RDDATA EN CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_DDRC_DFI_T_RDDATA_EN 0x0 Time from the assertion of a READ command on the DFI interface to the assertion of the DDRC DFI RDDATA EN signal Program this to RL 1 where RL is the read latency of the DRAM For LPDDR1 this should be set to RL Units Clocks DDRC DFI MIN CTRLUPD TIMING CR Table 7 67 DDRC DFI MIN CTRLUPD TIMING CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG DDRC DFI T CTRLUP MIN 0x03 Specifies the minimum number of clock cycles that the DDRC DFI CTRLUPD REQ signal must be asserted Lowest value to assign to this variable is 0x3 Units Clocks DDRC DFI MAX CTRLUPD TIMING CR Table 7 68 DDRC DFI MAX CTRLUPD TIMING CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pre
199. Name Reset Value Description 16 PLL PD 0x0 A power down PD signal is provided for lowest quiescent current When PD is asserted the PLL powers down and outputs are low PD has precedence over all other functions 15 PLL_FSE 0x0 This signal chooses between internal and external input paths 0 Feedback FB pin input 1 Internal feedback FB should be tied off High or Low and not left floating when FSE is High FB should connect directly or through the clock tree to PLLOUT when FSE is low SSE is ineffective when FSE 0 If the FACC source multiplexer is configured to select a clock other than the PLL output clock then the fddr_pll_fse signal must be set to 1 when the PLL is powered up 14 PLL_MODE_3V3 0x1 Analog voltage selection 1 3 3 V 0 2 5V Selects between 2 5 V and 3 3 V analog voltage Operation mode wrong selection may cause PLL not to function but will not damage the PLL 13 12 PLL_MODE_1V2 PLL_BYPASS Ox1 Ox1 Core voltage selection 1 12 V 0 1 0 V Selects between 1 0 V and 1 2 V core voltage Operation mode wrong selection may cause PLL not to function but will not damage the PLL A Bypass signal is provided which both powers down the PLL core and bypasses it as that PLLOUT tracks REFCK Bypass has precedence over Reset Microsemi recommends that either Bypass or Reset are asserted until all configuration controls are set in the desired working v
200. Name Value Description 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_invalid_M2 0x0 1 Invalidate read buffer for AHBL master2 0 Default DDR FIC SW WR ERCLR CR Table 7 221 DDR FIC SW WR ERCLR CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_LTO_CLR 0x0 Clear signal to lock timeout interrupt 7 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M2_WR_ERCLR 0x0 Clear bit for error status of AHBL master2 write buffer Once it goes High error status is cleared 3 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M1_WR_ERCLR 0x0 Clear bit for error status posted by AHBL master1 write buffer Once it goes High error status is cleared DDR_FIC_ERR_INT_ENABLE Table 7 222 DDR F
201. Name Value Description 31 24 MSI CTRL STATUS 31 24 These bits are hardwired to 00000000 23 MSI CTRL STATUS 23 This bit is hardwired to 1 22 20 MSI CTRL STATUS 22 20 Multiple message enable 19 17 MSI CTRL STATUS 19 17 Number of MSI requested 16 MSI CTRL STATUS 16 MSI is enabled 15 0 MSI CTRL STATUS 15 0 This bits are hardwired to 0x7805 Revision 1 93 I Microsemi PCI Express LTSSM Register 044h Table 2 32 LTSSM Bit Reset Number Name Value Description 31 29 LTSSM 31 29 Reserved 28 24 LTSSM 28 24 These bits set LTSSM state encoding RO 00000 Detect quiet 00001 Detect Active 00010 Polling Active 00011 Polling Compliance 00100 Polling Configuration 00101 Reserved ex polling Speed 00110 Configuration Linkwidth Start 00111 Configuration Linkwidth Accept 01000 Configuration Lanenum Accept 01001 Configuration Lanenum Wait 01010 Configuration Complete 01011 Configuration Idle 01100 Recovery RevrLock 01101 Recovery RcvrCfg 01110 Recovery Idle 01111 LO 10000 Disabled 10001 Loopback Entry 10010 Loopback Active 10011 Loopback Exit 10100 Hot Reset 10101 LOs transmit 10110 L1 entry 10111 L1 Idle 11000 L2 idle 11001 L2 TransmitWake 11010 Recovery Speed 11011 11111 Reserved 23 20 LTSSM 23 20 Reserved 19 LTSSM 19 This bit forces compliance pattern R W 18 LTSSM 18 This bit fully disables power management R W 17 LTSS
202. O Bit Reset Number Name Value Description 7 0 RE AMP RATIO DEEMPO This register defines the RX Equalization amplitude ratio where the maximum value is 8 d128 corresponding to 100 If RX equalization is not used this register can be set to zero RE CUT RATIO DEEMPO Register Table 5 36 RE CUT RATIO DEEMPO Bit Reset Number Name Value Description 7 0 RE CUT RATIO DEEMPO This register defines the RX equalization cut frequency ratio used in the computation of Rn 3 0 and Rd 3 0 equalization settings of the PMA macro The encoding of this register is such that Rn Rd RE CUT RATIOY256 W SETTING W_SETTING being the result of the RX equalization calibration 200 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide RE AMP RATIO DEEMP1 Register Table 5 37 RE AMP RATIO DEEMP1 Bit Name Reset Description Number Value P 7 0 RE_AMP_RATIO_DEEMP1 This register defines the RX equalization amplitude ratio where the maximum value is 8 d128 corresponding to 100 If RX equalization is not used this register can be set to zero RE CUT RATIO DEEMP1 Register Table 5 38 RE CUT RATIO DEEMP1 Bit Reset Number Name Value Description 7 0 RE CUT RATIO DEEMP1 This register defines the RX equalization cut frequency ratio used in the computation of Rn 3 0 and Rd 3 0 equalization setting
203. O pads I O PortO and I O Port1 There are two additional reference clocks fab_ref_clk and ccc_ref_clk coming from the fabric and clock conditioning circuitry block CCC For maximum flexibility the reference clock to the four lanes can come from either refclk_io0 or refclk_io1 I O pads or from the internal fab_ref_clk or ccc_ref_clk signal Figure 1 10 shows the reference clock selection The SERDES has four lanes but the two adjacent SERDES lanes share the same reference clock LaneO and lane1 share the same reference clock input Similarly lane3 and lane 4 share the same reference clock refcik io0 refclk_io1 ccc_ref_clk aREFCLK 1 0 fab_ref_clk SERDES LANE01_REFCLK_SEL 1 0 aREFCLK 3 2 LANE23_REFCLK_SEL 1 0 Figure 1 10 SERDES Reference Clock Revision 1 21 I Microsemi SERDESIF Block Figure 1 11 shows the reference clock selection in high speed serial interface generator available in Libero SoC It sets the MUX selection depending on the selected reference clocks Protocol 1 PHY Reference Clock 1 0 PortO I O Port1 Fabric Figure 1 11 e SERDES Reference Clock Using High Speed Serial Interface Generator The multiplexer select bits can be set for reference clocks come from the SERDESIF system registers Table 1 35 on page 40 shows the two registers LANE01 REFCLK SEL and LANE23_REFCLK_SELLANE23_REFCLK_SEL that define the clock selection for SERDES lanes SPLL Clocking The SERDESIF incl
204. PB S PRDATA 24 CRCERR Received TLP with LCRC error This signal reports that a TLP is received that contains an LCRC error APB S PRDATA 25 CRCINV Received nullified TLP This signal indicates that a nullified TLP is received APB S PRDATA 26 RX ERR DLLP Received DLLP with LCRC error This signal reports that a DLLP APB_S_PRDATA 27 ERR_DLLPROT has been received that contains an LCRC error DLL protocol error at data link layer This signal reports a DLL protocol error APB S PRDATA 28 RX ERR FRAME DLL framing error detected This signal indicates that received data cannot be considered as a DLLP or TLP in which case a receive port error is generated and link retraining is initiated APB 8 PRDATA 29 L2 EXIT 12 exit information signal APB 8 PRDATA 30 DLUP EXIT dlup exit information signal APB S PRDATA S1 HOTRST EXIT hotrst exit information signal Revision 1 57 I Microsemi SERDESIF Block Glossary Acronyms PCI Express Peripheral component interconnect express PCle PCI Express PCS Physical coding sublayer SERDESIF Serializer deserializer interface SGMII serial gigabit media independent interface XAUI Extended attachment unit interface List of Changes The following table lists critical changes that were made in each revision bm mme re 50200330 1 11 12 Updated Figure 1 14 SAR 42912 Note The part number is located on the last page of the
205. PHY_CTRL slave DLL 1 0 Fine value 8 2 Coarse value PHY_CTRL_OUTPUT_FILTER_SR Table 7 201 PHY CTRL OUTPUT FILTER SR Bit Number Reset Name Value Description 31 11 10 9 Reserved PHY REG STATUS PHY CTRL OF IN LOCK STATE 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 Lock status from the output filter module inside the PHY_CTRL Master DLL Bit 9 Fine delay line lock status 1 Locked 0 Unlocked Bit 10 Coarse delay line lock status 1 Locked 0 Unlocked 8 0 PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE 0x0 The coarse and fine values going into the output filter in the PHY_CTRL master DLL 1 0 Fine value 8 2 Coarse value 356 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_RD_DQS_SLAVE_DLL_VAL_1_SR Table 7 202 PHY RD DQS SLAVE DLL VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_STATUS_RD_DQS_S
206. PHY_WRLVL_INIT_MODE 0x0 The user programmable init ratio selection mode 1 Selects a starting ratio value based on REG_PHY_WRLVL_INIT_RATIO PORT 0 Selects a starting ratio value based on write leveling of previous data slice PHY_WRLVL_INIT_RATIO_CR Table 7 160 PHY WRLVL INIT RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 15 0 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_INIT_MODE port is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM PHY_WRLVL_INIT_RATIO_2_CR Table 7 161 PHY WRLVL INIT RATIO 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WRLVL_INIT_MODE 0x0 31 16 bits of REG_PHY_WRLVL_INIT_MODE The user programmable initialization ratio used by the write leveling FSM when the REG_PHY_WRLVL_IN
207. PHY_WR_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DQS_SLAVE_RATIO_4_CR Table 7 150 PHY WR DQS SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 49 48 bits of REG_PHY_WR_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY_WR_DATA_SLAVE_DELAY_1_CR Table 7 151 PHY WR DATA SLAVE DELAY 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
208. PLL_LOCKLOST_INT_ENABLE 0x0 Masking bit to enable FAB PLL LOCK LOST interrupt 2 FABRIC_PLL_LOCK_INT_ENABLE 0x0 Masking bit to enable FAB_PLL_LOCK interrupt 1 FPLL_LOCKLOST_INT_ENABLE 0x0 Masking bit to enable FPLL_LOCK_LOST interrupt 0 FPLL_LOCK_INT_ENABLE 0x0 Masking bit to enable FPLL LOCK interrupt 390 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide F_AXI_AHB_MODE_SEL Table 8 14 F AXI AHB MODE SEL Bit Name Reset Description Number Value 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 F AXI AHB MODE 0x0 1 AXI interface in the fabric will be selected 0 AHB interface in the fabric will be selected PHY SELF REF EN Table 8 15 PHY SELF REF EN Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 PHY_SELF_REF_EN 0x0 If 1 automatic calibration lock is enabled FDDR_FAB_PLL_CLK_SR Table 8 16 FDDR FAB PLL CLK SR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should n
209. PRESET N Training mode selection register PHY DYN RESET CR 0x31C RW PRESET NIThis register will bring the PHY out of reset PHY LEVELLING FAILURE SR 0x320 RO PRESET N Leveling failure status register PHY BIST ERROR 1 SR 0x324 RO PRESET NIBIST error status register PHY BIST ERROR 2 SR 0x328 RO PRESET_N BIST error status register PHY BIST ERROR 3 SR 0x32C RO PRESET NIBIST error status register PHY WRLVL DQS RATIO 1 SR 0x330 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 2 SR 0x334 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 3 SR 0x338 RO PRESET N Write level DQS ratio status register PHY WRLVL DQS RATIO 4 SR 0x33C RO PRESET N Write level DQS ratio status register PHY WRLVL DQ RATIO 1 SR 0x340 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 2 SR 0x344 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 3 SR 0x348 RO PRESET N Write level DQ ratio status register PHY WRLVL DQ RATIO 4 SR 0x34C RO PRESET N Write level DQ ratio status register PHY RDLVL DQS RATIO 1 SR 0x350 RO PRESET_N Read level DQS ratio status register PHY RDLVL DQS RATIO 2 SR 0x354 RO PRESET N Read level DQS ratio status register PHY RDLVL DQS RATIO 3 SR 0x358 RO PRESET N Read level DQS ratio status register PHY RDLVL DQS RATIO 4 SR 0x35C RO PRESET_N Read level DQS ratio status register Revision 1 317 amp Microsemi MSS DDR Su
210. R FIC BUF TIMER CR 0x408 RW PRESET N 10 bit timer interface used to configure the timeout register DDR FIC HPD SW RW EN CR Ox40C RW PRESET N Enable write buffer and read buffer register for AHB Lite AHBL master1 and master2 DDR FIC HPD SW RW INVAL CR 0x410 RW PRESET N l Invalidates write buffer and read buffer for AHBL master1 and master2 DDR LOCK TIMEOUTVAL 1 CR 0x440 RW PRESET N Indicates maximum number of cycles a master can hold the bus for a locked transfer DDR LOCK TIMEOUTVAL 2 CR 0x444 RW PRESET N Indicates maximum number of cycles a master can hold the bus for a locked transfer Glossary DDR Double data rate Flush Operation Writing the data in the Write combining buffer into DDR memory Non bufferable Address The address is within the range of defined non bufferable region RAC Read access controller SEU Single event upsets TAG Region It is the range of bufferable data for write read transactions from the address of initial transaction WAC Write access controller WCB Write combining buffer 406 Revision 1 lt gt Microsemi 10 Soft Memory Controller Fabric Interface Controller Introduction The SmartFusion2 SoC FPGA soft memory controller fabric interface controller SMC_FIC is used to access external bulk memories other than DDR via the FPGA fabric The SMC_FIC can be used with a soft memory controller to interface the MSS to memories such as SDR
211. R Interfaces User s Guide PLL_CONFIG_HIGH Table 8 6 PLL_CONFIG_HIGH Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 PLL_PD 0x0 When PD is asserted the PLL will power down and outputs will be Low PD has precedence over all other functions 14 PLL_FSE 0x0 Chooses between internal and external input paths 0 FB pin input 1 Internal feedback FB should be tied off High or Low and not left floating when FSE is High FB should connect directly or through the clock tree to PLLOUT when FSE is Low SSE is ineffective when FSE 0 13 PLL_MODE_3V3 0x1 Analog voltage selection 1 3 3V 0 25 V 12 PLL_MODE_1V2 0x1 Core voltage selection 1 1 2V 0 1 0V The wrong selection when operating at 1 V the jitter is not within the required limit for operation of DDR may cause the PLL not to function but will not damage the PLL 11 PLL_BYPASS 0x1 If 1 powers down the PLL core and bypasses it such that PLLOUT tracks REFCK BYPASS has precedence over RESET Microsemi recommends that either BYPASS or RESET are asserted until all configuration controls are set in the desired working value and the power supply and reference clock are stable within operating range 10 7 PLL_LOCKCNT OxF Configured to contro
212. RC_DRAM_RAS_TIMING_CR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 5 REG_DDRC_T_RAS_MAX 0x0 tRAS max Maximum time between activate and precharge to same bank Maximum time that a page can be kept open specification 70 us Minimum value of this register is 1 Zero is invalid Unit Multiples of 1 024 clocks 4 0 REG_DDRC_T_RAS_MIN 0x0 tRAS min Minimum time between activate and precharge to the same bank specification 45 ns Unit clocks 282 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_DRAM_RD_WR_TRNARND_TIME_CR Table 7 44 DDRC_DRAM_RD_WR_TRNARND_TIME_CR Bit Number Name Reset Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_DDRC_RD2WR 0x0 RL BL 2 2 WL Minimum time from READ command to WRITE command Include time for bus turnaround and all per bank per rank and global constraints Unit clocks where WL Write latency BL Burst length This must match the val
213. RO PRESET NlIError response register for bufferable write request DDR LOCK TIMEOUTVAL 1 CR 0x440 RW PRESET NlIndicates maximum number of cycles a master can hold the bus for locked transfer DDR LOCK TIMEOUTVAL 2 CR 0x444 RW PRESET NlIndicates maximum number of cycles a master can hold the bus for locked transfer DDR FIC LOCK TIMEOUT EN CR 0x448 RW PRESET Nl Lock timeout feature enable register DDR FIC RDWR ERR SR 0x44C RO PRESET NlIndicates read address of math error register DDR FIC Configuration Register Bit Definitions DDR FIC NB ADDR CR Table 7 216 DDR FIC NB ADDR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR FIC NB ADD 0x0 This indicates the base address of the non bufferable address region DDR FIC NBRWB SIZE CR Table 7 217 DDR FIC NBRWB SIZE CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 DDR_FIC_WCB_SZ 0x0 Configures write buffer and read buffer size as per DDR burst size This port is common for al
214. RXDATAL 19 0 data from the PMA EPCS 2 RX VAL Output Fabric EPCS interface lane2 and lane3 Receive data EPCS 3 RX VAL valid if needed EPCS 2 RX IDLE Output Fabric EPCS interface lane2 and lane3 Receive idle EPCS 3 RX IDLE needed for SATA OOB EPCS 2 TX CLK STABLE Output Fabric EPCS interface lane2 and lane3 Clock stable info 48 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 58 e SERDESIF Block I O PAD Interface Connected Port Name Type to Description PCIE_x_RXDPO Input I O Pads Receive data SERDES differential positive PCIE x RXDP1 input each SERDESIF consists of 4 RX signals Here x 0 for SERDESIF 0 and x 1 for PCIE x RXDP2 SERDESIF 1 If unused can be left floating PCIE x RXDP3 PCIE x RXDNO Input I O Pads Receive data SERDES differential negative PCIE x RXDN1 input Each SERDESIF consists of 4 RX signals Bele RD Here x 0 for SERDESIF 0 and x 1 for PCIE x RXDN3 SERDESIF 1 If unused can be left floating PCIE x TXDPO Output I O Pads Transmit data SERDES differential positive PCIE x TXDP1 output Each SERDESIF consists of 4 TX signals POE AE Here x 0 for SERDESIF 0 and x 1 for PCIE x TXDP3 SERDESIF 1 If unused can be left floating PCIE x TXDNO Output I O Pads Transmit data SERDES differential negative PCIE x TXDN1 output Each SERDESIF consists of 4
215. S 4 0 In out DRAM data mask from bidirectional pads MDDR DQS 4 0 In out DRAM single ended data strobe output for bidirectional pads MDDR_DQS_N 4 0 In out DRAM single ended data strobe output for bidirectional pads MDDR DQ 35 0 In out DRAM data input output for bidirectional pads MDDR FIFO WE IN 2 0 In FIFO in signal DQS enable input for timing match between DQS and system clock For simulations to be tied to DRAM FIFO WE OUT MDDR FIFO WE OUT 2 0 Output FIFO out signal DQS enable output for timing match between DQS and system clock For simulations to be tied to DRAM FIFO WE IN Revision 1 251 amp Microsemi MSS DDR Subsystem Memory Initialization After power up the DDR controller initializes memories through different sequences of steps 252 DDR2 For DDR2 the initialization state machine executes the following initialization sequence 1 Issues NOP Deselect for the duration specified by REG DDRC PRE CKE X1024 specification requires at least 200 us with stable power and clock Asserts CKE and issues NOP Deselect for REG DDRC POST CKE X1024 specification requires at least 400 ns Issues PRECHARGE ALL followed by NOP Deselect for REG DDRC T RP cycles Programs EMR2 to the REG DDRC EMR2 value and issues NOP Deselect for REG DDRC T MRD cycles Programs EMR3 to the REG DDRC EMR3 value and issues NOP Deselect for REG DDRC T MRD cycles Enables DLL by programming EMR to
216. S rising edge aligns with the beginning and end transitions of the associated DQ data eye By identifying these delays the system can calculate the midpoint between the delays and accurately center the read DQS within the DQ data eye The DDRC drives subsequent read transactions for every read to read delay specified by REG_DDRC_RDLVL_RR until the PHY drives the response signal High The DDR controller performs the below steps 1 Sets up the DRAM for read leveling mode by sending the appropriate MR3 command which forces the SDRAM to respond to read commands with a 1 0 1 0 1 pattern 2 Sets the relevant read leveling enable bit and sends out periodically timed read commands on the SDRAM command interface 3 Once the PHY completes its measurements it sets the read level response bits which then signal the DDRC to stop the leveling process and lower read leveling enable bit Table 7 12 MDDR Subsystem Interface Signals Signal Name Type Description MDDR_CAS_N Out DRAM CASN MDDR_CKE Out DRAM CKE MDDR_CLK Out DRAM single ended clock for differential pads MDDR_CLK_N Out DRAM single ended clock for differential pads MDDR_CS_N Out DRAM CSN MDDR_ODT Out DRAM ODT 0 Termination Off 1 Termination On MDDR_RAS_N Out DRAM RASN MDDR_RESET_N Out DRAM Reset for DDR3 MDDR_WE_N Out DRAM WEN MDDR ADDR 15 0 Out Dram address bits MDDR BA 2 0 Out Dram bank address MDDR DM RDQ
217. SERDES behavior because it forces the SERDES to different calibration settings than those computed by calibration function FORCE_ATXDRR_7_0 Register Table 5 85 FORCE_ATXDRR_7_0 Bt Name Reset Description Number Value P 7 0 FORCE ATXDRR 7 0 This register defines bit 7 to bit 0 of the RX impedance and RX equalization fields used when the override RX settings register is set Note This register can be programmed any time and has no functional impact on the SERDES 210 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FORCE ATXDRR 15 8 Register Table 5 86 FORCE ATXDRR 15 8 Bit Reset Number Name Value Description 7 0 This register defines bit 15 to bit 8 of the RX impedance and RX FORCE ADRESS equalization fields used when the override RX settings register is set Note This register can be programmed any time and has no functional impact on the SERDES FORCE_ATXDRR_20_16 Register Table 5 87 FORCE_ATXDRR_20_16 Bit Reset Number Name Value Description 7 5 Unused 4 0 FORCE_ATXDRR 20 16 This register defines bit 20 to bit 16 of the RX impedance and RX equalization fields used when the override RX settings register is set Note This register can be programmed any time and has no functional impact on the SERDES FORCE_ATXDRP_7_0 Register Table 5 88 FORCE_ATXDRP_7_0
218. SLAVE RATIO 2 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0401 31 16 bits of REG_PHY_WR_DATA_SLAVE_RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 338 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_WR_DATA_SLAVE_RATIO_3_CR Table 7 157 PHY WR DATA SLAVE RATIO 3 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0401 47 32 bits of REG PHY WR DATA SLAVE RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applie
219. S_SLAVE_DELAY_1_CR Table 7 143 PHY WR DQS SLAVE DELAY 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 15 0 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG_PHY_WR_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value Revision 1 333 I Microsemi MSS DDR Subsystem PHY WR DQS SLAVE DELAY 2 CR Table 7 144 PHY WR DQS SLAVE DELAY 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 31 16 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG_PHY_WR_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY WR DQS SLAVE DELAY 3 CR Table 7 145 PHY WR DQS SLAVE DELAY 3 CR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read mo
220. Serial and DDR Interfaces User s Guide Common Configuration Space Header Table 2 131 shows the common configuration space header SmartFusion2 SoC FPGA PCIe common configuration space includes the following registers Type 0 configuration settings e MSI capability structure e MSI X capability structure Power management capability structure e PCle capability structure For comprehensive information about these registers refer to PCle Base Specification Revision 1 0a 1 1 or 2 0 specifications Table 2 131 Configuration Inputs for AHBL AXI to AXI Bridge 31 24 23 16 15 8 7 0 Byte Offset TYPE 0 configuration registers 000h 03Ch Reserved 040h PLDA CSR 044h Reserved 048h 04Ch MSI capability structure optional 050 05Ch Reserved 060h 064h MSI X capability structure optional 68h 70h Power management capability structure 078 07Ch PCI Express capability structure 080h 0BCh SSID SSVID capability structure optional OCOh 0C4h Reserved OC8h OFCh PCle Extended Capability Structure Table 2 132 shows the PCle extended capability structure SmartFusion2 SoC FPGA PCIe common configuration space includes the following registers e Virtual channel capability structure e PCle advanced error reporting AER extended capability structure Table 2 132 PCle Extended Capability Structure Function 0 31 24 23 16 15 8 7 0 Byte Offset Virtual c
221. SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide lt gt Microsemi lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table of Contents 1 SERDESIP Block rss EP HOGER RE SESE TRE RE DERE TAS 5 Functional Deseriptibn seri sara herad besre eed ete eh ee eee PR sees oe ee 5 SmartFusion2 SoC FPGA Serial Protocols Overview 0 00 7 Clocking and Reset sa cs0h2ee0he hee nP eben nemes bog bee ferd wee eee ee be eee eee eee 21 Configuration of SERDESIF 0 0 tte 25 I O Signal Interface of SERDESIF a sann anarki bk mm ee ee ee 44 SERDESIF Debug Interface s kekka sms eee anke kg Ene ske deal pea a EEDE 56 GIOSSARY vader kr okie od eve ga pur wane Poe ST RE 58 2 PEIES S erea Ascot SEa ee NE 59 Fully compliant physical layer device PHY physical coding sub layer PCS 2 00 00 eee eee 59 PCIE Endpoint miair e e Mech kit dol Peds BE ok bape hice hae ee en Eee en eh eee es 59 PCIGSYSIOM csiosrpsencgsi restene Sue tee aa 96 ee Ak ad ket de ye ee eels wee aA a EE i E 61 SERDESIF System Registers for PCle Mode 0 cece ett 67 Using the PCle System eeri ass sense See era fe keene gue ead Gea ke new ed Sewn eee dee ee 70 SmartFusion2 SoC FPGA PCle Power Management 0 e tte eae 79 PCle Core Bridge Register Space icca nc bes eee eee ee te eee eee ba eee ee 83 PCle System I O Signal Interface 0 0 ett 118 Append
222. SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MSI X Capability Structure Table 2 136 illustrates the content of the MSI X capability structure Table 2 136 MSI X Capability Structure Register 31 24 23 16 15 8 7 3 2 0 Byte Offset Message control Next pointer Capability ID 068h Table offset Table BIR 06Ch PBA offset PBA BIR 070h Power Management Capability Structure Table 2 137 illustrates the content of the power management capability structure Table 2 137 Power Management Capability Structure 31 24 23 16 15 8 7 0 Byte Offset Capabilities register Next cap PTR Cap ID 078h Data PM control status Power management status and control 07Ch bridge extensions PCle Capability Structure Table 2 138 illustrates the content of the PCle capability structure Table 2 138 PCle Capability Structure Register 31 24 23 16 15 8 7 0 Byte Offset Capabilities register Next cap PTR cap ID 080h Device capabilities 084h Device status Device control 088h Link capabilities 08Ch Link status Link control 090h Slot capabilities 094h Slot status Slot control 098h Root control 09Ch Root status OAOh Device capabilities 2 OA4h Device status 2 Device control 2 OA8h Link capabilities 2 OACh Link status 2 Link control 2 OBOh Revision 1 125 I Microsemi PCI Express SSID SSVID
223. SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide AXI_SLAVE_WINDOW1 3 Register ODCh Table 2 71 AXI SLAVE WINDOW1 3 Bit Reset Number Name Value Description 31 0 AXI SLAVE WINDOW13 31 12 MSB of base address PCIe window 1 AXI SLAVE WINDOW2 0 Register OEOh Table 2 72 AXI SLAVE WINDOW2 0 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW20 31 12 Base address AXI slave window 2 11 0 Reserved AXI SLAVE WINDOWO 1 Register OE4h Table 2 73 AXI SLAVE WINDOW2 1 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW21 31 12 Size of AXI slave window 2 11 1 AXI SLAVE WINDOW 22 31 12 Reserved 0 AXI SLAVE WINDOW 21 0 Enable bit of AXI slave window 2 AXI SLAVE WINDOWO 2 Register OE8h Table 2 74 AXI SLAVE WINDOW2 2 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW 22 31 12 LSB of base address PCIe window 2 11 5 AXI_SLAVE_WINDOW22_11_5 Reserved 4 2 AXI SLAVE WINDOW 22 4 2 AXI slave window 0 traffic class TC 1 AXI SLAVE WINDOW 22 1 AXI slave window 0 relaxed ordering RO 0 AXI SLAVE WINDOW22 0 AXI slave window 0 no snoop NS AXI SLAVE WINDOW3 3 Register 0ECh Table 2 75 AXI SLAVE WINDOW2 3 Bit Reset Number Name Value Description 31 0 AXI SLAVE WINDOW 23 31 12 MSB of base address PCle window 3 Revision 1 107 lt gt
224. TX Signals FE Here x 0 for SERDESIF 0 and x 1 for PCIE x TXDN3 SERDESIF 1 If unused can be left floating PCIE x REXTL Referenc I O Pads External reference resistor connection to e calibrate TX RX termination value Each SERDESIF consists of 2 REXT signals one for PCIE x REXTR lanes 0 and 1 and another for lanes 2 and 3 77 Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating PCIE_x_REFCLKOP Input I O Pads Reference clock differential positive Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual PCIE x REFCLK1P purpose I Os t these lines can be used for MSIOD fabric if SERDESIF is not activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating PCIE_x_REFCLKON Input I O Pads Reference clock differential negative Each SERDESIF consists of two signals REFCLKO_P REFCLK1_P These are dual purpose I Os these lines can be for MSIOD fabric if SERDESIF is not activated Here x 0 for SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left floating Revision 1 49 lt gt Microsemi SERDESIF Block Table 1 59 SERDESIF Block PLL Control and Status Interface Connected Port Type To Description SPLL_LOCK Output Fabric SPLL control status information PLL_LOCK_INT Output Fabric SPLL control status information PLL_LOCKLOST_INT Output Fabric SPLL control status information FAB PLL LOCK I
225. T_STATUS_SR Bit Reset Number Name Value Description 31 0 DDRC_SINGLE_ERR_CNT_STATUS_REG 0x0 Single error count status If the count reaches OxFFFF it is held and only cleared after DDRC ECC ERR READ DONE _CR is written over by the system Revision 1 301 I Microsemi MSS DDR Subsystem DDRC_DOUBLE_ERR_CNT_STATUS_SR Table 7 78 DDRC DOUBLE ERR CNT STATUS SR Bit Reset Number Name Value Description 31 0 DDRC DOUBLE ERR CNT STATUS REG 0x0 Double error count status If the count reaches OxFFFF then it is held and only cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system DDRC_LUE_SYNDROME_1_SR Table 7 79 DDRC_LUE_SYNDROME_1_SR Bit Number 31 16 Name Reserved Reset Value 0x0 Description Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC REG ECC SYNDROMES 0x0 15 0 bits of DDRC_REG_ECC_SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower da
226. Table 1 46 CONF AXI MSTR WNDW 3 Bit Reset Number Name Value Description 3 0 CONF AXI MSTR WNDW 3 0x0 PCle AXI master Window0 configuration register 3 42 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg94 CONF AXI SLV WNDW 0 Register 0x2094 Table 1 47 CONF AXI SLV WNDW 0 Bit Reset Number Name Value Description 31 0 CONF AXI SLV WNDW 0 0x0 PCle AXI slave Window0 configuration register 0 Reg98 CONF AXI SLV WNDW 1 Register 0x2098 Table 1 48 CONF AXI SLV WNDW 1 Bit Reset Number Name Value Description 31 0 CONF AXI SLV WNDW 1 0x0 PCle AXI slave Window0 configuration register 1 Reg9C CONF AXI SLV WNDW 2 Register 0x209C Table 1 49 CONF AXI SLV WNDW 2 Bit Reset Number Name Value Description 31 0 CONF AXI SLV WNDW 2 0x0 PCle AXI slave Window0 configuration register 2 RegA0 CONF AXI SLV WNDW 3 Register 0x20A0 Table 1 50 CONF AXI SLV WNDW 3 Bit Reset Number Name Value Description 3 0 CONF AXI SLV WNDW 3 0x0 PCle AXI slave Window0 configuration register 3 Note All the register are 32 bit Bits not shown in the table are reserved RegA4 DESKEW_CONFIG Register 0x20A4 Table 1 51 DESKEW_CONFIG Bit Reset Number Name Value Description 3 2 DESKEW_PLL_FDB_CLK Ox0 These bits set the PLL FEEDBACK
227. Table 2 99 IRTATUS Bit Reset Number Name Value Description 31 0 IRTATUS 310 Reserved 112 Revision 1 MSIADDR Register 150h Table 2 100 IMSIADDR lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Bit Reset Number Name Value Description 31 0 IMSIADDR_31_0 Reserved SLOTCAP Register 154h Table 2 101 SLOTCAP Bit Reset Number Name Value Description 31 0 SLOTCAP_31_0 Reserved SLOTCSR Register 158h Table 2 102 SLOTCSR Bit Reset Number Name Value Description 31 0 SLOTCSR 310 Reserved ROOTCSR Register 15Ch Table 2 103 ROOTCSR Bit Reset Number Name Value Description 31 0 ROOTCSR 310 Reserved CFG_CONTROL Register 160h Table 2 104 CFG CONTROL Bit Reset Number Name Value Description 31 0 CFG_CONTROL_31_0 Reserved CFG_WRITE_DATA Register 164h Table 2 105 CFG WRITE DATA Bit Reset Number Name Value Description 31 0 CFG WRITE DATA 31 0 Reserved CFG READ DATA Register 168h Table 2 106 CFG READ DATA Bit Reset Number Name Value Description 31 0 CFG READ DATA 31 0 Reserved Revision 1 113 lt gt Microsemi PCI Express INFO Register 016Ch Table 2 107 INFO Bit Reset Number Name Value Description 31 12 INFO_31_12 Bridge version 11 0 INFO_11_0 Reserve
228. The SmartFusion2 SoC FPGA SERDESIF block I2_p2_ctrl logic in L2 state detects WAKE_REQ and the SmartFusion2 SoC FPGA SERDESIF configured as an EP can request exit from the L2 state by asserting the WAKE_N WAKE output signal 10 Once WAKE WAKE_N is asserted alDDQ is deasserted and fundamental reset is applied to the PCle IP Core and PHY SERDES and released Link training starts again L2 Exit Sequence Initiated by RP 1 When the RP switch needs to wake the EP it asserts the PERST PERST_N side band signal 2 Once the PERST signals is asserted alDDQ is deasserted and fundamental reset is asserted to the PCle core and SERDES The link starts training in a normal way This case of exit is valid only in the case of the PCle connector using the PERST side band signal PERST is the PERST_N input signal on the SmartFusion2 SoC FPGA SERDESIF active low signal No L2 Exit Request from RC EP PCle Link in Active State L2 Figure 2 20 L2 Exit Flow Diagram Initiated by RC SW 82 L2 Exit Request from EP WAKE_REQ 1 from Fabric PCle link is in L2 P2 state L2 P2 CTRL FSM is in L2 state On WAKE REQ L2 P2 CTRL FSM exits L2 state and asserts PCle Core and SERDES reset for one clock cycle and alDDQ is deasserted WAKE Nis asserted Revision 1 L2 Exit Request from RC PCIe link is in L2 P2 state L2 P2 CTRL FSM is in L2 state On PERST_N deassertion L2 P2 CTRL FSM exits L2 state and as
229. This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected CUSTOM PATTERN 39 32 Register Table 5 111 CUSTOM PATTERN 39 32 Bit Reset Number Name Value 7 0 RX PWRDN 39 32 Description This register enables bit 39 to bit 32 to program a custom pattern instead of the implemented PRBS generator checker PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected CUSTOM_PATTERN_47_40 Register Table 5 112 CUSTOM PATTERN 47 40 Bit Reset Number Name Value 7 0 RX PWRDNJ 47 40 Description This register enables bit 47 to bit 40 to program a custom pattern instead of the implemented PRBS generator checker PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It c
230. To facilitate the configuration a GUI in Libero SoC is provided Table 1 6 PCle Mode Settings Using the SERDESIF System Register SERDESIF System APB Registers Description CONFIG PHY MODE 15 12 For each lane this signal selects the protocol default settings which will set the reset value of the register space CONFIG PHY MODE 15 12 Defines lanelane3 settings 0000 PCIe mode lane3 0001 XAUI mode lane3 0010 EPCS SGMII9 mode lane3 0011 EPCS 2 5 GHz mode lane3 0100 EPCS 1 25 GHz mode lane3 0101 EPCS undefined mode lane3 1111 SERDES PHY lane3 is off CONFIG PHY MODE 11 8 CONFIG PHY MODE 11 8 Defines lane2 settings 0000 PCIe mode lane2 0001 XAUI mode lane2 0011 EPCS 2 5 GHz mode lane2 0100 EPCS 1 25 GHz mode lane2 0101 EPCS undefined mode lane2 1111 SERDES PHY lane2 is off CONFIG PHY MODE 7 4 CONFIG PHY MODE 7 4 Defines lane1 settings 0000 PCIe mode lane1 0001 XAUI mode lane1 0011 EPCS 2 5 GHz mode lane1 0100 EPCS 1 25 GHz mode lane1 0101 EPCS undefined mode lane1 1111 SERDES PHY lanet is off CONFIG PHY MODE 3 0 CONFIG PHY MODE 3 0 Defines lane0 settings 0000 PCIe mode lane0 0001 XAUI mode laneO 0011 EPCS 2 5 GHz mode lane0 0100 EPCS 1 25 GHz mode lane0 0101 EPCS undefined mode laneO 1111 SERDES PHY lane0 is off Notes 1 XAUI 10 Gbps attachment unit interface 2 EPCS External physical coding
231. UI mode Table 3 5 Clock Signals in the XAUI Mode Clock Signal Description REFCLK 100 Reference clock for SERDES PMA PLLs REFCLK 101 Reference clock for SERDES PMA PLLs CCC_REF_CLK Reference clock for SERDES PMA PLLs Do not use this clock as reference clock FAB_REF_CLK Reference clock for SERDES PMA PLLs Do not use this clock as reference clock PLL_SERDESIF_REF Reference clock for SPLL EPCS TXCLK 0 LaneO EPCS Tx clock is fed as reference clock in XAUI mode PLL_SERDESIF_FB Feed through of XAUI_IN_CLK as feedback clock to SPLL PLL_ACLK SPLL clock output SPLL to G4M SERDESIF XAUI OUT CLK SPLL clock output PLL ACLK XAUI IN CLK Feedback clock for SPLL Fabric to G4M SERDESIF MMD MDC MDIO clock EPCS RXCLK XAUI XGMII interface receive clock for XAUI MAC four lanes Rx data is phase aligned to this clock XAUI Mode Reset When the SmartFusion2 SoC FPGA SERDESIF is configured in the XAUI mode it has multiple reset inputs Figure 3 8 shows the reset signals and how they are connected internally The CORE RESET N input is the external asynchronous reset input XAUI extender block XAUlI MDC RESET input asynchronously resets all the MDIO registers XAUI_TX_RESET input resets the TX block register and XAUI_RX_RESET input resets the RX block register Refer to Table 3 26 for detail CORE_RESET_N Power up XAUI MDC RESET FABRIC
232. VE_RATIO_CR Table 7 110 PHY CTRL SLAVE RATIO CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 0 REG PHY CTRL SLAVE RATIO 0x0 Ratio value for address command launches timing in PHY CTRL macro This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line PHY_CTRL_SLAVE_FORCE_CR Table 7 111 PHY CTRL SLAVE FORCE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_CTRL_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for address command timing slave DLL with the value of the REG_PHY_RD_DQS_SLAVE_DELAY bus 322 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_CTRL_SLAVE_DELAY_CR Table 7 112 PHY CTRL SLAVE DELAY CR Bit Reset Number Name Value Desc
233. Value Description 15 0 Reserved TBD General purpose registers that are connected to the output port XAUI_VNDRRESL 15 0 Typically used for external device control Table 3 22 Depicts Definition of Vendor Specific Reset High 2 Register Reg15 Vendor Specific Reset High 2 Bit Reset Number Name Value Description 15 0 Reserved TBD General purpose registers that are connected to the output port XAUI_VNDRRESLI 31 16 Typically used for external device control SmartFusion2 SoC FPGA XAUI I O Signal Interface The SmartFusion2 SoC FPGA SERDESIF in XAUI mode interfaces with the fabric and differential I O pads The SmartFusion2 SoC FPGA SERDESIF I Os can be grouped into a number of interfaces by functional protocol implemented PHY mode and easy representation point of view Following is the list of XAUI mode I O interface signals e MDIO interface signals e XGMII transmit interface signals e XGMII receive interface signals e Reset signals e SPLL clocking signals e I O PAD interface e Miscellaneous control signal Table 3 23 SmartFusion2 SoC FPGA XAUI Extender Block MDIO Interface Port Type Description XAUI_MMD_MDC Input MDIO I F clock 40 MHZ or less XAUI_MMD_MDI Input MDIO data input from bidirectional pad XAUI_MMD_MDI_ EXT Input Serial data output of another block that is responding to a host read transaction XAUI_MMD_MDO Output MDIO data output to bidirectional
234. W PRESET NIDDRC DFI Controller Update Max Time register DDRC DFI WR LVL CONTROL 1 CR 0x0C8 RW PRESET_N DDRC DFI Write Levelling Control register DDRC DFI WR LVL CONTROL 2 CR OxOCC RW PRESET_N DDRC DFI Write Levelling Control register DDRC DFI RD LVL CONTROL 1 CR 0x0D0 RW PRESET NIDDRC DFI Read Levelling Control register DDRC DFI RD LVL CONTROL 2 CR 0x0D4 RW PRESET NIDDRC DFI Read Levelling Control register DDRC DFI CTRLUPD TIME INTERVAL CR 0x0D8 RW PRESET_N DDRC DFI Controller Update Time Interval register DDRC DYN SOFT RESET 2 CR 0x0DC RW PRESET_N DDRC reset register DDRC_AXI_FABRIC_PRI_ID_CR Ox0E0 RW PRESET_N DDRC AXI Interface Fabric Priority ID Register DDRC SR Ox0E4 RO PRESET NIDDRC Status register SECDED Registers DDRC SINGLE ERR CNT STATUS SR 0x0E8 RO PRESET NIDDRC single error count Status register DDRC DOUBLE ERR CNT STATUS SR Ox0EC RO PRESET_N DDRC double error count status register DDRC_LUE_SYNDROME_1_SR Ox0FO RO PRESET_N DDRC last uncorrected error syndrome register DDRC_LUE_SYNDROME_2_SR Ox0F4 RO PRESET_N DDRC last uncorrected error syndrome register DDRC_LUE_SYNDROME_3_SR Ox0F8 RO PRESET_N DDRC last uncorrected error syndrome register DDRC LUE SYNDROME 4 SR Ox0FC RO PRESET_N DDRC last uncorrected error syndrome register 268 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 19 DDR Controller Configuration Register
235. WE IN 2 0 FDDR FIFO WE OUT 2 0 APB S CLK APB S PRESET_N CORE RESET N CLK BASE AXI S RMW CLK BASE PLL LOCK FPLL LOCK FATC RESET N Revision 1 375 lt gt Microsemi Fabric Double Data Rate Subsystem FDDR Subsystem Interface Signals The FDDR subsystem top level interface signals are listed in Table 8 1 Table 8 1 FDDR Subsystem Interface Signals Signal Name Type Description APB_S_PCLK In APB clock This clock drives all the registers of the APB interface APB_S_PRESET_N In APB reset signal This is an active low signal This drives the APB interface which uses this signal to generate the soft reset for the DDR controller as well CORE_RESET_N In Global reset This resets the DDR FIC DDRC PHY DDRAXI logic CLK_BASE In Fabric interface clock This drives the AXI AHB clock inside FIC 64 AX _S_RMW In AXI mode only Indicates whether all bytes of a 64 bit lane are valid for all beats of an AXI transfer 0 Indicates that all bytes in all beats are valid in the burst and the controller should default to write commands 1 Indicates that some bytes are invalid and the controller should default to RMW commands This is classed as an AXI write address channel sideband signal and is valid with the AWVALID signal Only used when error correcting code ECC is enabled CLK BASE PLL LOCK In Fabric PLL LOCK input FPLL LOCK Out PLL lock stat
236. X offset cancellation logic This clock is generated and used inside each lane as a multiple SERDES The clkdiv module is used to generate PIPE clock for the PCle controller which must also be fed back to each lane on pipe_pclkin signal In order to generate a 125 MHz 250 MHz or 500 MHz clock from the 500 MHz aTXClk this block implements a divider by 1 2 or 4 which depends on the PHY settings and current rate On top of clock division this block also shuts down the clock The PIPE_PCLKOUT signal is the output signal of the PCS and is generated on a per lane basis Revision 1 175 I Microsemi Serializer Deserializer RXDP RXDN The phase matching FIFO is used to recapture the transmitted data generated on the PCLK clock domain back to the aTXCIk domain considering the two clocks are fully independent asynchronous The TX data MUX performs the multiplexing between data coming from the PCle PCS and the external PCS Depending on the settings of the clock divider logic this block also serializes the PCS valid data bus width into the PMA expected data width The 8b 10b encoder implements an 8 bit to 10 bit encoder that encodes 8 bit data or control characters into 10 bit symbols The 8b 10b decoder uses two lookup tables the D and K tables to decode the 10 bit symbol stream into 8 bit data D or control K characters plus the D K signal Receiver Block The Receiver block consists of receive capture logic word alignment logic
237. XI Master mode RLAST AXI M RVALID Input Fabric AXI Master mode RVALID AXI M RREADY Output Fabric AXI Master mode RREADY Table 1 55 e SERDESIF Block AXI AHB Lite Slave Interface Connected Port Type To Description AXI S AWID HSEL Input Fabric AXI Slave mode AWID AHBL Slave mode HSEL AXI_S_AWADDR_AHB_S_HADDRJ 31 0 Input Fabric AXI Slave mode AWADDR AHBL Slave mode HADDR AXI_S_AWLEN_AHB_S_HBURST 1 0 Input Fabric AXI Slave mode AWLEN AHBL Slave mode HBURST AXI_S_AWSIZE_AHB_S_HSIZE 1 0 Input Fabric AXI Slave mode AWSIZE AHBL Slave mode HSIZE AXI S AWBURST AHB S HTRANS 1 0 Input Fabric AXI Slave mode AWBURST AHBL Slave mode HTRANS AXI S AWVALID AHB S HWRITE Input Fabric AXI Slave mode AWVALID AHBL Slave mode HWRITE AXI S AWREADY Output Fabric AXI Slave mode AWREADY AXI 8 AWLOCK Input Fabric AXI Slave mode AWLOCK AXI 8 WID Input Fabric AXI Slave mode WID AXI S WSTRB Input Fabric AXI Slave mode WSTRB AXI S WLAST Input Fabric AXI Slave mode WLAST AXI 8 WVALID Input Fabric AXI Slave mode WVALID 46 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 55 e SERDESIF Block AXI AHB Lite Slave Interface continued Connected Port Type To Description AXI S WDATA AHB S HWDATA 63 0 Input Fabric AXI Slave mode WDATA 63 0 AHBL Slave mode HWDATA 31 0 AXI S
238. Y Output AXI slave mode ARREADY Fabric S RID Output AXI slave mode RID Fabric S RDATA HRDATA Output AXI slave mode RDATA Fabric S RRESP Output AXI slave mode RRESP Fabric S RLAST Output AXI slave mode RLAST Fabric IS RVALID Output AXIslavemode RVALID gt Fabric S RREADY Input AXI slave mode RREADY Fabric Table 2 126 PCle System APB Slave Interface Port Type Description Connected to APB PSEL Input APB slave interface PSEL Fabric APB PENABLE Input APB slave interface PENABLE Fabric APB PWRITE Input APB slave interface PWRITE Fabric APB PADDR 13 0 Input APB slave interface PADDR Fabric APB PWDATA 31 0 Input APB slave interface PWDATA Fabric APB PREADY Output APB slave interface PREADY Fabric APB PRDATA 31 0 Output APB slave interface PRDATA Fabric APB PSLVERR Output APB slave interface PSLVERR Fabric Table 2 127 PCle System Clock Signals Port Type Description Connected to CLK BASE Input Fabric source clock In PCle mode this is the reference clock of the SPLL The PLL output clock PLL ACLK is used as the AXI AHB bridge clock APB CLK Input PCLK for APB slave interface in SERDESIF Fabric SPLL LOCK Output SPLL control status information Fabric PLL LOCK INT Output SPLL control status information Fabric PLL LOCKLOST INT Output SPLL control status information Fabric Table 2 128 PCle System Reset Signals Ports Type Description Connected to CORE_RESET_N In PLDA PCle core active low Fabr
239. _FIC is overlaid on the DDR_FIC fabric interface they share the same fabric interface signals Therefore the MDDR is not available in SMC_FIC mode However the I Os associated with the MDDR are available to user logic in the fabric Figure 10 1 on page 407 shows a soft memory controller implemented within the fabric for interfacing with external bulk memory Microsemi provides CoreSDR AHB and CoreSDR AXI soft memory controller IPs for interfacing with external SDRAM A custom soft memory controller can be implemented in the FPGA fabric to support the external bulk memories connected to the fabric MSS masters connected to the AHB bus matrix can communicate with the soft memory controller in SDR mode for interfacing with external bulk memory via the fabric For example the HPDMA can be used to perform data transfers from external bulk memory connected to the fabric The Cortex M3 processor boots from the internal eNVM or eSRAM in debug mode Application code except vector tables can execute from external bulk memories such as external flash or a preloaded SDRAM which are connected via FPGA fabric in SMC_FIC mode To configure the SMC FIC with the Libero Soc MSS MDDR configuration GUI select the application access to single data rate memory from MSS option and specify either the AXI 64 or AHB Lite interface The SMC FIC AXI 64 interface in the fabric supports INCR burst transactions of any length for read and write channels It supports WRAP bur
240. _RESET_N EPCS 2 RESET_N EPCS 3 RESET_N EPCS 0 READY EPCS 1 READY EPCS 2 READY EPCS 3 READY EPCS 0 PWRDN EPCS 1 PWRDN EPCS 2 PWRDN EPCS 3 PWRDN EPCS 0 TX 00B EPCS 1 TX 008 EPCS 2 TX 00B EPCS 3 TX 00B EPCS 0 TX VAL EPCS 1 TX VAL EPCS 2 TX VAL EPCS 3 TX VAL PHY reset When the power up signal from program control is asserted this signal is used to reset the complete SERDES macro as well as the associated PMA control logic PHY ready This signal is asserted when the PHY has completed the calibration sequence for each specific lane This signal can be used to release the reset for the external PCS and controller start transmitting data to the PMA or any other purpose PHY power down This signal is used to put the PMA in power down state where RX CDR PLL is bypassed and other low power features are applied to the PMA When exiting power down no calibration is required and the link can be operational much faster than when using the EPCS X TX OOB or EPCS X RESET N signals PHY transmit out of band OOB This signal is used to load electrical idle III in the TX driver of the PMA macro It can be used for serial advanced technology attachment SATA as part of the sequencing for transmitting very short OOB signaling PHY transmit valid This signal is used to transmit valid data If deasserted the PMA macro is put in electrical idle 1 It can be used for protocols requiring electrical idle SATA and must also be deasserted a
241. _SLAVE_DLL_VAL_1_SR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 15 0 bits of PHY_REG_STATUS_FIFO_WE_SLA VE_DLL_VALUE Delay value applied to FIFO WE slave DLL PHY_FIFO_WE_SLAVE_DLL_VAL_2_SR Table 7 209 PHY_FIFO_WE_SLAVE_DLL_VAL_2_SR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 31 16 bits of PHY_REG_STATUS_FIFO_WE_SLAV E_DLL_VALUE Delay value applied to FIFO WE slave DLL PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR Table 7 210 PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE 0x0 44 32 bits of PHY_REG_STATUS_FI
242. a time The FDDR subsystem has a 16 bit APB configuration bus which is used to initialize the internal registers within the FDDR subsystem after reset The functionality of the FDDR sub blocks DDR controller DDR PHY and the fabric interface is the same as that of the MDDR block The main difference between the MSS DDR subsystem MDDR and FDDR is that the MDDR controller has an additional AXI slave interface directly connected to the MSS through the MSS DDR bridge and uses the MSS system configuration registers Refer to the MSS DDR Subsystem section on page 237 for more information on the functionality of the FDDR sub blocks This chapter gives an overview of the FDDR subsystem use cases FDDR configuration details and FDDR control registers FDDR Subsystem Overview Block Diagram Figure 8 1 shows a system level block diagram of the FDDR subsystem DDR SDRAM can be DDR2 DDR3 or LPDDR1 depending on the FDDR configuration FPGA Fabric APB DDRAIG Config Reg CLK_BASE AXI DDR fre PER DDR SDRAM FDDR SYSREG DDR PHY FDDR SmartFusion2 Figure 8 1 System Level FDDR Block Diagram Revision 1 373 I Microsemi Fabric Double Data Rate Subsystem Major blocks in the FDDR subsystem e DDR_FIC AXI transaction controller e DDR controller DDR PHY The DDR FIC is an AHB Lite to AXI or AXI to AXI bridge between the FPGA fabric and AXI Transaction controller On the input interface DDR FIC impleme
243. abled and selected CUSTOM_PATTERN_63_56 Register Table 5 114 CUSTOM PATTERN 63 56 Bit Reset Number Name Value Description 7 0 RX PWRDNI 63 56 This register enables bit 63 to bit 56 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected CUSTOM_PATTERN_71_64 Register Table 5 115 CUSTOM PATTERN 71 64 Bit Reset Number Name Value Description 7 0 RX PWRDN 7 1 64 This register enables bit 71 to bit 64 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check
244. abric AXI Master mode WSTRB AXI M WLAST Output Fabric AXI Master mode WLAST AXI M WVALID Output Fabric AXI Master mode WVALID AXI M WDATA AHB M HWDATA 63 0 Output Fabric AXI Master mode WDATA 63 0 AHBL Master mode HWDATA 31 0 AXI M WREADY AHB M HREADY Input Fabric AXI Master mode WREADY AHBL Master mode HREADY AXI M BID 3 0 Input Fabric AXI Master mode BID AXI M BRESP HRESP 1 0 Input Fabric AXI Master mode BRESP Revision 1 AHBL Master mode HRESP 45 lt gt Microsemi SERDESIF Block Table 1 54 e SERDESIF Block AXI AHB Lite Master Interface continued Connected Port Type To Description AXI M BVALID Input Fabric AXI Master mode BVALID AXI M BREADY Output Fabric AXI Master mode BREADY AXI M ARID 3 0 Output Fabric AXI Master mode ARID AXI M ARADDR 31 0 Output Fabric AXI Master mode ARADDR AXI M ARLEN 3 0 Output Fabric AXI Master mode ARLEN AXI M ARSIZE 1 0 Output Fabric AXI Master mode ARSIZE AXI M ARBURST 1 0 Output Fabric AXI Master mode ARBURST AXI M ARVALID Output Fabric AXI Master mode ARVALID AXI M ARREADY Input Fabric AXI Master mode ARREADY AXI M RID 3 0 Input Fabric AXI Master mode RID AXI M RDATA AHB M HRDATA 63 0 Input Fabric AXI Master mode RDATA 63 0 AHBL Master mode HRDATA 31 0 AXI M RRESP 1 0 Input Fabric AXI Master mode RRESP AXI M RLAST Input Fabric A
245. aces User s Guide DDRC_SR Table 7 76 DDRC SR Bit Number Name Reset Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 3 DDRC_CORE_REG_OPERATING_MODE 0x0 Operating mode This is 3 bits wide in designs with mobile support and 2 bits in all other designs Non mobile designs 000 Init 001 Normal 010 Power down 011 Self Refresh Mobile designs 000 Init 001 Normal 010 Power down 011 Self refresh 1XX Deep power down DDRC_REG_TRDLVL_MAX_ERROR 0x0 Single pulse output 1 indicates the RDRLVL_MAX timer has timed out DDRC_REG_TWRLVL_MAX_ERROR 0x0 Single pulse output 1 indicates the WRLVL_MAX timer has timed out DDRC_REG_MR_WR_BUSY 0x0 1 Indicates that a mode register write operation is in progress 0 Indicates that the core can initiate a mode register write operation Core must initiate an MR write operation only if this signal is Low This signal goes High in the clock after the controller accepts the write request It goes Low when the MR write command is issued to the DRAM Any MR write command that is received when DDRC_REG_MR_WR_BUSY is High is not accepted Table 7 77 DDRC_SINGLE_ERR_CNT_STATUS_SR DDRC_SINGLE_ERR_CN
246. across a read modify write operation 12 0 PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE Ox0 44 32 bits of PHY_REG_STATUS_WR_DQS_SL AVE_DLL_VALUE Delay value applied to write DQS slave DLL 360 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_CTRL_SLAVE_DLL_VAL_SR Table 7 214 PHY CTRL SLAVE DLL VAL SR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 0 PHY_REG_STATUS_PHY_CTRL_SLAVE_DLL_VALUE 0x0 _ Delay value applied to write DQS slave DLL DDR_FIC Configuration Registers Summary Table 7 215 DDR FIC Configuration Register Summary Address Reset Register Name Offset R W Source Description DDR FIC NB ADDR CR 0x400 RW PRESET Nl Indicates the base address of the non bufferable address region DDR FIC NBRWB SIZE CR 0x404 RW PRESET NlIndicates the size of the non bufferable address region DDR FIC BUF TIMER CR 0x408 RW PRESET Nl 10 bit timer interface used to configure the timeout register DDR FIC HPD SW RW EN CR 0x40C RW PRESET_NjEnable write buffer and read buffer register for AHBL master1 and master2 DDR FIC HPD SW RW INVAL CR 0x410 RW PRESET_N Invalidate
247. across a read modify write operation 9 0 DDR_FIC_TIMER 0x0 10 bit timer interface used to configure timeout register Once timer reaches the timeout value a flush request is generated by the flush controller in the DDR_FIC This port is common for all buffers Revision 1 363 I Microsemi MSS DDR Subsystem DDR_FIC_HPD_SW_RW_EN_CR Table 7 219 DDR FIC HPD SW RW EN CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_M1_REN 0x0 1 Enable read buffer for AHBL master1 0 Disable read buffer for AHBL master 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M1_WEN 0x0 1 Enable write buffer for AHBL master 1 0 Disable write buffer for AHBL master 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_M2_REN 0x0 1 Enable read buffer for AHBL master2 0 Disable read buffer for AHBL master2 1 Reserved 0x0 Software should not rely on the
248. alue the power supply and reference clocks are stable within operating range and the feedback path is functional Either Bypass or Reset may be used for power down IDDQ testing 11 PLL_RESET 0x1 PLL reset signal asserted high 10 7 PLL_LOCKCNT OxF These bits contain lock counter value 24 binary value 5 0000 32 0001 64 1111 1048576 The above mentioned lock counter values represent the number of reference cycles present before the lock is asserted or detected 30 Note All the registers are 32 bit Bits which are not shown in the table are reserved Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 11 SER PLL CONFIG HIGH continued Bit Reset Number Name Value Description 6 4 PLL LOCKWIN 0x0 These bits contain phase error window for lock assertion as a fraction of divided reference period 000 500ppm 100 8000ppm 001 1000ppm 101 16000ppm 010 2000ppm 110 32000ppm 011 4000ppm 111 64000ppm Values are at typical process voltage and temperature PVT only and are not PVT compensated 3 0 PLL FILTER RANGE 0x9 These bits contain PLL filter range 0000 BYPASS 0111 18 29 MHz 0001 1 1 6 MHz 1000 29 46 MHz 0010 1 6 2 6 MHz 1001 46 75 MHz 0011 2 6 4 2 MHz 1010 75 120 MHz 0100 4 2 6 8 MHz 1011 120 200 MHz 0101 6 8 11 MHz 0110 11 18 MHz Note All the registers
249. alue Description 7 4 Reserved 2 0 ATXICP_RATEO 2 0 This register defines the TX PLL charge pump current when the PMA is running in PCle Gen1 speed or in any other protocol This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion Note This register can be programmed when the PHY is under reset GEN1 RX PLL CCP Register Table 5 121 GEN1 RX PLL CCP Bit Reset Number Name Value Description 7 Reserved 6 4 ARXCDRICP_RATEO 2 0 This register defines the RX PLL charge pump current when the PMA is frequency locked and running in PCIe Gen1 speed or in any other protocol This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion 3 Reserved 2 0 ARXICP_RATEO 2 0 This register defines the RX PLL charge pump current when the PMA is CDR locked and running in PCle Gen1 speed or in any other protocol This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion Note This register can be programmed when the PHY is under reset GEN2_TX_PLL_CCP Register PCle Gen2 protocol only Table 5 122 GEN2 TX PLL CCP Bit Reset Number Name Value Description 7 Reserved 6 4 ATXICP RATE1 2 0 This register defin
250. ample in Figure 2 16 four BARS are enabled in the bridge two 64 bit BARS BARO1 and BAR23 and two 32 bit BARS BAR4 and BARS All AXI master windows are utilized BARO1 is connected to AXI master window 0 AXI Master window 1 is mapped to the lower 64 bytes of BAR23 and AXI master window 2 is mapped to the upper 64 bytes of BAR23 AXI master window 3 is connected to BAR4 BARS is not mapped to an AXI window its offset is passed directly to the AXI master and translation is not performed To configure AXI MASTER WINDOW 0 for example APB write operations are performed e First APB write APB_PADDr 100h APBPWDATA FFFO 0000 Second APB write APB_PADDR 104h APBPWDATA FFFO 0001 Third APB write APB_PADDR 108h APBPWDATA 0000 0001 Fourth APB write APB_PADDR 10Ch APBPWDATA 0000 0000 Host Processor Address Space Local Device Address Space 0000 0000 PCle Full Address PCle Offset Address r AXI Full Address BARS Direct ME G 0000 OFFC me CDAO 0000 0001 8000 CDAO OFFC PAUSE 0001 FFFC 0005 0000 RENE 0005 7FFFC AAAA AAAA 0000 0000 a C000 0000 Window3 AAAA AAAA 0000 FFFC C000 OFFC BBBB BBBB 0000 0000 me Fr FFFO 0000 gest FFFO FFFC BBBB BBBB 0000 FFFC me Figure 2 16 16 PCle to AXI Master Address Translation If window size is not enabled or if the PCle offset address is located in a BAR but not in any of the windows address translation is not performed In this case the PCle base address is removed to
251. an be used for instance for single lane PCle compliance pattern generation for purpose of eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected 218 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide CUSTOM_PATTERN_55_48 Register Table 5 113 CUSTOM PATTERN 55 48 Bit Reset Number Name Value Description 7 0 RX PWRDN 55 48 This register enables bit 55 to bit 48 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not en
252. and control signals should be source centered on rx cik In the SmartFusion2 SoC FPGA devices the XAUI extender will be interfaced with a soft 10G MAC in the fabric within the same device eliminating the need to source center the data All four lanes of data are synchronous with the common clock rx_clk XAUI RX CLK Figure 3 11 Receive XGMII Interface Timing Diagram MMD Read Timing Figure 3 12 shows the timing diagram for an XS MDIO Registers read The MMD MDO may be a tristate signal in which the tristate buffer is controlled by mmd_mdoe lt read read inc gt lt Z gt lt 0 gt XAUI MMD MDC JU LU TT XAUI MMD MDOE fr Figure 3 12 MMD Internal Interface Read to TA Timing 140 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MMD Write Timing Figure 3 13 shows the timing diagram for an XS MDIO Registers write By design mmd_mdoe must not be asserted during a write operation Refer to the IEEE 802 3ae specification clause 45 for a complete definition lt idle gt lt 0 gt lt 0 gt XAUI MMD MDC XAUI MMD MDI er XAUI MMD MDOE Figure 3 13 MMD Internal Interface Start Interface MDIO Register Map Table 3 6 shows the description of MDIO registers Table 3 6 MDIO Registers Register Reset Read Device Register Address Name Value Writable Address Description 0x00
253. ane2 Lane3 LaneO0 Lane1 Lane2 Lane3 MO PCle only mode x4 0x0 0x0 OxO Ox0 OxO 0x0 OxO OxO 0x01 Ox1 0x1 0x1 nr pcie x4 M1 PCle only mode x2 OxO 0x0 OxF OxF Ox0 0x0 0x1 0x1 0x1 0x1 OxO 0x0 nr pcie x2 M2 PCle only mode x1 OxO OxF OxF OxF Ox0 0x0 Ox1 0x1 0x1 OxO OxO 0x0 nr pcie x1 M3 PCle only mode with OxO 0x0 OxO OxO OxO OxO OxO OxO OxO OxO OxO 0x0 lane reverse x4 r pcie x4 M4 PCle only mode with OxF OxF OxO Ox0 0x1 0x1 OxO 0x0 OxO 0x0 Ox1 0x1 Lane reverse x2 r pcie x2 M5 PCle only mode with OxF OxF OxF Ox0 0x1 0x1 0x1 OxO OxO 0x0 0x0 0x1 Lane reverse x1 r pcie x1 M6 PCle only mode with 0x0 0x0 OxF OxF 0x0 0x0 0x1 0x1 0x1 0x1 0x0 0x0 Lane reverse x2 r pcie x2 M7 PCle only mode with OxF 0x0 OxF OxF 0x1 OxO 0x1 0x1 0x0 0x1 OxO 0x0 Lane reverse x1 r pcie x1 M8 XAUI only mode 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 OxO 0x0 0x0 x4 xaui x4 M9 XAUI only mode 0x3 0x3 0x3 0x3 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 x4 SRIO x4 M10 EPCS only mode OxF OxF OxF OxF Ox1 0x1 0x1 0x1 0x0 OxO OxO 0x0 x4 EPCS mode x4 18 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 7 Implementing Protocols Using the SER
254. are 32 bit Bits which are not shown in the table are reserved Reg08 SER SOFT RESET Register 0x2008 Table 1 12 SER SOFT RESET Bit Reset Number Name Value Description 0 PCIE CTLR SOFTRESET 0x1 PCle controller soft Reset 1 XAUI CTLR SOFTRESET Ox1 XAUI controller soft Reset 2 SERDES LANEO SOFTRESET 0x1 SERDES lane0 soft Reset 3 SERDES_LANE1_SOFTRESET 0x1 SERDES lane1 soft Reset 4 SERDES_LANE2_ SOFTRESET 0x1 SERDES lane2 soft Reset 5 SERDES LANE3 SOFTRESET 0x1 SERDES lane3 soft Reset Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 31 lt gt Microsemi SERDESIF Block Reg0C SER INTERRUPT ENABLE Register 0x200C Table 1 13 SER INTERRUPT ENABLE Bit Reset Number Name Value Description 3 FPLL LOCKLOST INT ENABLE 0x0 This bit sets FPLL lock lost interrupt output enable 2 FPLL LOCK INT ENABLE 0x0 This bit sets FPLL lock interrupt output enable 1 SPLL LOCKLOST INT ENABLE 0x0 This bit sets SERDES PLL lock lost interrupt output enable 0 SPLL LOCK INT ENABLE 0x0 This bit sets SERDES PLL lock interrupt output enable Reg10 CONFIG AXI AHB BRIDGE Register 0x2010 Table 1 14 CONFIG AXI AHB BRIDGE Bit Reset Number Name Value Description 0 CFGR AXI AHB SLAVE 0x1 Defines whether AXI AHB slave interface is implemented on the slave interface to fabric 0 AHB 32 bit
255. are used for read and write requests so that two masters can access read and write channels simultaneously The DDR bridge arbiter has an AXI master interface to the DDR controller AXI Write Access Controller WAC The WAC arbitrates write requests from the WCBs and grants access to one of the requesting masters based on its priority Combinations of fixed and round robin priorities are assigned to the masters below e Master Interface 1 Fixed 1st priority Master Interface 0 is read only e Round robin between Master Interface 2 and Master Interface 3 for 2nd and 3rd priorities When a master is granted access to the bus its address and data is placed on the bus and is 64 bit aligned All transactions from a single master have a dedicated master ID Once a burst transaction is initiated to the external DDR memory then the transaction will be completed without an interruption No other master even a high priority master can interrupt this process Subsequent write requests from the same master are held until the previous write transactions are completed to the external DDR memory Subsequent write requests from other masters can be accepted and allowed to write into WCB but the DDR bridge will not flush out this data until the previous write transactions are completed to the external DDR memory AXI Read Access Controller RAC The RAC arbitrates read requests from read buffers and gives access to one of the requesting masters for transf
256. as well as the write data payload from the AXI slave The size of the TX buffer depends on the number of outstanding read write transactions In general the transmit size is required to be greater than two times MAX_PAYLOAD_ SIZE 512 bytes The SmartFusion2 SoC FPGA PCIe system has a transmit buffer size of 1 KB each which is four times MAX_PAYLOAD_ SIZE Receive Buffer The receive buffer is located in the transaction layer and accepts incoming TLPs from the link and then sends them to the application layer for processing Receive buffer resources are either implemented per VC or per link The receive buffer stores TLPs based on the type of transaction not the TC of a transaction Types of transactions include posted transactions non posted transactions and completion transactions A transaction always has a header but does not necessarily have data The receive buffer accounts for this distinction maintaining separate resources for the header and data of each type of transaction To summarize distinct buffer resources are maintained per an initialized VC for each of the following elements e Posted transactions header PH e Posted transactions data PD e Non posted transactions header NPH e Non posted transactions data NPD e Completion transactions header CPLH e Completion transactions data CPLD TLPs are stored in the RX buffer in 64 bit addressing format with each AXI slave read outstanding request consuming 16 cr
257. ation results from its own calibration circuitry 00b from one of the upper lanes 10b or from one of the lower lanes 01b Thus several consecutive lanes can be configured to take the calibration result from the lower or upper lane These lanes can be enabled for instance for a 4 lane implementation to have a single external resistor for 4 lanes or 1 external resistor 1 for each group of 2 lanes Also the external resistor is not expected to be located on functional LaneQ it can be located on any lane of the multi lane link Even if using the calibration results of another lane each lane can still be finely tuned independently with the other lanes in term of Tx pre emphasis and Rx equalization Revision 1 161 I Microsemi EPCS Interface SmartFusion2 SoC FPGA EPCS Interface Timing Diagram The Tx clock aTXclk and Rx clock aRXCIk of SERDES are directly provided to the external PCS interface through the EPCS_x_TX_CLK x 0 1 2 3 and EPCS x RX CLK x 0 1 2 3 output signals These signals must be used as transmit clock and receive clock by the external PCS logic and thus a clock tree is required to be implemented on each of these signals The transmit data EPCS_X_TXDATA x 0 1 2 3 must be generated using rising edge of the EPCS_x_TX_CLK and captured back by the SERDES block as shown in Figure 4 7 1 Delay introduced by the clock tree on a TxClkp 2 Clock to out delay and routing delay Figure 4 7 EPCS Transm
258. ator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected Revision 1 217 I Microsemi Serializer Deserializer CUSTOM_PATTERN_31_24 Register Table 5 110 CUSTOM PATTERN 31 24 Bit Reset Number Name Value 7 0 RX PWRDN 31 24 Description This register enables bit 31 to bit 24 to program a custom pattern instead of the implemented PRBS generator checker PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform word alignment function Note
259. ave a small impact on the latency of the first read request when the controller is idle Units 1 024 clocks 7 0 REG DDRC DFI T CTRLUPD INTERVAL MAX X1024 0x16 This is the maximum amount of time between controller initiated DFI update requests This timer resets with each update request when the timer expires traffic is blocked for a few cycles PHY can use this idle time to recalibrate the delay lines to the DLLs The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors Updates are required to maintain calibration over PVT but frequent updates may impact performance Units 1 024 clocks DDRC_DYN_SOFT_RESET_2_CR Table 7 74 DDRC DYN SOFT RESET 2 CR Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 AXIRESET 0x1 Set when main AXI reset signal is asserted Reads and writes to the dynamic registers should not be carried out This is a read only bit Revision 1 299 I Microsemi MSS DDR Subsystem Table 7 74 e DDRC DYN SOFT RESET 2 CR continued Bit Reset Number Name Value Description 1 RESET APB REG 0x0 Full soft reset If this bit is set when the soft reset bit is written as 1 all APB registers reset to the power up state 0 R
260. be higher and side effect can be observed on the link 3 2 ARXD_ERR 1 0 This register defines whether RX offset D calibration has reached a min bitO max bit1 value If any min max value is detected the calibration logic will apply the min max value but the offset can be higher and side effect can be observed on the link 1 0 ARXT_ERR 1 0 This register defines whether RX offset T calibration has reached a min bitO max bit1 value If any min max value is detected the calibration logic will apply the min max value but the offset can be higher and side effect can be observed on the link TX_SWEEP_CENTER Register Table 5 52 TX SWEEP CENTER Bt Name Roset Description Number Value P 7 TX VAL This register defines whether PMA has completed the TX impedance calibration signaling and that the result of TX impedance calibration tx sweep center 6 0 is valid 6 0 TX SWEEP CENTER 6 0 This register reports the result of TX impedance calibration 204 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide RX_SWEEP_CENTER Register Table 5 53 RX SWEEP CENTER Bit Reset Number Name Value Description 7 RX_VAL This register defines whether the PMA has completed the RX impedance calibration signaling and that the result of RX impedance calibration rx sweep center 6 0 is valid 6 0 RX SWEEP CENTER 6
261. be prefetched 2 1 BAR4 2 1 0x10 Set to 00 to indicate anywhere in 32 bit address space 0 BAR4_0 0x0 Memory space indicator Revision 1 91 lt gt Microsemi PCI Express BAR5 Register 024h Table 2 24 BAR5 Bit Number Name Reset Value Description 31 4 BARS_31_4 0x000000 The register defines the type and size of BAR1 of the PCIe native endpoint 3 BAR5 3 0x0 Identifies the ability of the memory space to be prefetched 2 1 BAR5 2 1 0x00 Set to 00 to indicate anywhere in 32 bit address space 0 BAR5 0 0x0 Memory space indicator Reserved 028h Table 2 25 Reserved 028h Bit Number Name Reset Value Description Reserved 0x00000000 Reserved SUBSYSTEM_ID Register 02Ch Table 2 26 e SUBSYSTEM ID Bit Reset Number Name Value Description 31 16 SUBSYSTEM ID Ox110A This field further qualifies the manufacturer of the device or application This value is typically the same as the Device ID 15 0 SUBSYSTEM VENDOR ID 0x1556 This field further qualifies the manufacturer of the device or application PCIE_DEVSCR Register 030h Table 2 27 PCIE_DEVSCR Bit Reset Number Name Value Description 31 0 PCIE_DEVSCR 0x00000000 Device control and status This register reports the current value of the PCle device control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enab
262. ber Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 6 PLL_FEEDBACK_DIVISOR 0x2 Can be configured to control the corresponding configuration input of the MPLL Feedback divider value SSE 0 binary value 1 00000000 1 1111111111 1 024 Feedback divider value SSE 1 binary value 1 0000000 1 1111111 128 5 0 PLL_REF_DIVISOR 0x1 Can be configured to control the corresponding configuration input of the MPLL Reference divider value binary value 1 000000 1 PLL_CONFIG_LOW_2 Table 8 5 PLL_CONFIG_LOW_2 Bit Reset Number Name Value Description 31 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 PLL_OUTPUT_DIVISOR 0x2 Configures the amount of division to be performed on the internal multiplied PLL clock in order to generate the DDR clock Output divider value 000 1 001 2 010 4 011 8 100 16 101 32 It is possible to configure the PLL output divider as 1 this setting must not be used when the DDR is operational 384 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DD
263. ber Name Value Description 7 5 Unused 4 F ARXTDIR This register forces the voltage to apply to aRXD settings for RX offset calibration 3 0 F_ARXTNUL 3 0 This register forces the voltage to apply to aRXD settings for RX offset calibration Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 2 is not set FORCE_SCHMITT_TRIG_CALIB Register Table 5 102 FORCE SCHMITT TRIG CALIB Bit Reset Number Name Value Description 7 5 Unused 4 F ASCHDIR This register forces the voltage to apply for Schmitt trigger offset calibration 3 0 F_ASCHNUL 3 0 This register forces the voltage to apply for Schmitt trigger offset calibration Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 4 is not set 214 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PRBS_CTRL Register Table 5 103 PRBS_CTRL Bit Number Name Reset Value Description 7 Unused 6 PRBS_CHK When set this signal starts the PRBS pattern checker It can be set at the same time as the PRBS generator while the PRBS checker logic waits for 256 clock cycles and CDR being in lock state to enable the PRBS pattern comparison allowing a total latency of 256 cycles to loop back the transmitted data 5 4 3 2
264. block and is controlled either at boot time by the MSS APB master connected via Fabric routing resources or under user control via an APB master implemented in the FPGA fabric a GJFDDR_PADS Figure 8 4 FDDR Block Use Case Scenario 378 1 AXI Interface The FDDR subsystem can be used to access DDR SDRAM memory as shown in Figure 8 5 FDDR has an APB interface to configure the registers The configuration can be done through user logic APB master in the FPGA fabric The APB master can be selected by configuring the APB configuration IF in Libero SoC The read write and read modify write transactions are initiated by the AXI master to read or write data into the memory Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FPGA Fabric AXI Master User Logic APB S PCLK APB S PRESET N AXI_S_RMW CORE_RESET_N CLK_BASE FAB_PLL_LOCK FDDR SmartFusion2 Figure 8 5 FDDR with AXI Interface Revision 1 379 3 Microsemi Fabric Double Data Rate Subsystem The FDDR can be configured from the MSS through APB configuration interface refer to the APB Configuration Interface chapter in the ARM Cortex M3 Processor and Subsystem in SmartFusion2 SoC FPGA Devices User s Guide as shown in Figure 8 6 Cortex M3 Microcontroller FIC_2_APB_M_PCLK AHB Bus Matrix FIC 2 APB M PRESET_N FPGA Fabric AXI Master User Logic I i APB S PCLK APB S
265. bsystem Table 7 100 PHY Configuration Register Summary continued Reset Register Name Offset Type Source Description PHY FIFO 1 SR 0x360 RO PRESET Nl FIFO status register PHY FIFO 2 SR 0x364 RO PRESET N FIFO status register PHY FIFO 3 SR 0x368 RO PRESET Nl FIFO status register PHY FIFO 4 SR 0x36C RO PRESET_N FIFO status register PHY MASTER DLL SR 0x370 RO PRESET N Master DLL status register PHY DLL SLAVE VALUE 1 SR 0x374 RO PRESET NlJSlave DLL status register PHY DLL SLAVE VALUE 2 SR 0x378 RO PRESET N Slave DLL status register PHY STATUS OF IN DELAY VAL 1 SR 0x37C RO PRESET NIIN delay status register PHY STATUS OF IN DELAY VAL 2 SR 0x380 RO PRESET NIIN delay status register PHY STATUS OF OUT DELAY VAL 1 SR 0x384 RO PRESET N OUT delay status register PHY STATUS OF OUT DELAY VAL 2 SR 0x388 RO PRESET N OUT delay status register PHY DLL LOCK AND SLAVE VAL SR 0x38C RO PRESET NIDLL lock status register PHY CTRL OUTPUT FILTER SR 0x390 RO PRESET Nl Control output filter status register PHY RD DQS SLAVE DLL VAL 1 SR 0x398 RO PRESET_N Read DQS slave DLL status register PHY RD DQS SLAVE DLL VAL 2 SR 0x39C RO PRESET N Read DQS slave DLL status register PHY RD DQS SLAVE DLL VAL 3 SR Ox3A0 RO PRESET_N Read DQS slave DLL status register PHY WR DATA SLAVE DLL VAL 1 SR 0x3A4 RO PRESET N Write
266. ce Revision 1 73 I Microsemi PCI Express PCle Reset Network The SmartFusion2 SoC FPGA SERDESIF when configured in PCle mode has three reset inputs Figure 2 13 shows a simplified view of the reset signal in PCle mode FPGA Fabric CORE_RESET_N PHY_RESET_N APB S PCLK APB S PRESET N PHY CLK PCle PHY Reset Controller SERDES PCle IP Block SERDESIF Figure 2 13 Reset Signals in PCle Mode Table 2 7 shows the reset signals to use Table 2 7 Reset Signals in PCle Mode Signal Direction Description CORE_RESETN In Top level fundamental asynchronous RESET to the PCle system It is tied to GND when PCle protocol mode is not used Fundamental reset to the PCle IP block It affects only those SERDES lanes which are in PCle mode Lanes associated with the PCle link should have one reset for all lanes PHY_RESETN In Top level fundamental asynchronous RESET to the SERDES block Any 1 2 4 lanes used for any serial protocol should be tied to 1 APB_RESETN In APB asynchronous reset to all APB registers Base Address Registers The high speed serial interface generator in Libero SoC allows the base address register BAR for the endpoint configuration SmartFusion2 SoC FPGA PCle implementation supports up to six 32 bit BARs or three 64 bit BARs The BARs can be one of two sizes 32 bit BARs The address space can be as small as 16 bytes or as large as 2 gigabytes Used for memory
267. ce of bit error rate testing BERT Note The first error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS ERR CYC FIRST 49 48 Register Table 5 132 PRBS ERR CYC FIRST 49 48 Bt Name pesei Description Number Value p 7 2 Reserved 1 0 PRBS_ERR_CYC_FIRST 49 48 PRBS last error cycle counter register bits 49 48 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS_ERR_CYC_FIRST_7_0 Register Table 5 133 PRBS ERR CYC FIRST 7 0 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 7 0 PRBS last error cycle counter register bits 7 0 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing B
268. chip bring up On the application side it has one master interface and one slave interface The master interface can be a 64 bit AXI master or 32 bit advanced high performance bus AHB master The slave interface can be a 64 bit AXI slave or 32 bit AHB slave interface The PCIe link initiates transactions to SmartFusion2 SoC FPGA fabric through the AXI master or AHB master SmartFusion2 SoC FPGA fabric initiates transactions towards the PCIe link through the AXI slave or AHB slave interface There is an APB interface that has access to the PCle bridge configuration registers In addition the APB interface has access to the configuration register for the AXI to AXI AHBL bridge and AXI AHBL to AXI bridge which are defined in the SERDESIF system registers Figure 2 3 shows the architecture of the PCle IP block PCIe to AXI WindowO PCIe to AXI Window1 PCIe to AXI Window3 PCIe to AXI Window3 PCle Base lt SERDES IP core x4 Link AXI to PCle Window0 AXI AXI to PCle Window 1 AXI Slave AXI to PCle Window2 AXI to PCle Window3 APB APB Slave 4 gt PCle Bridge Registers Figure 2 3 PCIe IP Block Diagram The main sub blocks for the PCle IP block include PCle base IP core AXI master block AXI slave block PCle to AXI window AXI to PCIe window PCIe bridge registers N O WOR ON gt APB slave interface 62 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide
269. cket based point to point low pin count serial interconnect bus SmartFusion2 SoC FPGA has a fully hardened PCle implementation The PCle system sub block inside the SERDESIF block implements the PCle transaction layer and data link layer The SERDES sub block inside the SERDESIF block implements the physical layer This section describes the PCle system and its various sub blocks Figure 2 2 shows the SmartFusion2 SoC FPGA PCle system block diagram The main sub blocks for PCle system include 1 PCle IP block with AXI interface AXI to AXI AHB Lite AHBL bridge AXI AHBL to AXI bridge PCIe bridge registers aREN Glue logic blocks SERDESIF PCle System IP FPGA Fabric CORE_RESET_N Reset lt PHY_CLK Controller MUX PHY_RESET_N E PHY_CLK AXI64 AXI64 Slave ee AXI to AXI AHBL Bridge ALES Slave PM ad BCS 74 PIPE PCle IP with AXI interface 16 Bit Pad Signals AXI64 AXI64 Master AHBL AXI to AXI Bridge AHB32 Master Interface PCle Bridge Interface Registers L2 P2 Control Logic Lane to Lane Calibration Logic SERDESIF System Registers APB Interface APB APB32 Master Decoder Interface Figure 2 2 PCle System Block Diagram Revision 1 61 I Microsemi PCI Express PCIe IP Block with AXI Interface The PCle IP block in SmartFusion2 SoC FPGA implements an x1 x2 or x4 PCle interface that can be configured in Endpoint mode It is configured in Endpoint mode during the initialization phase or
270. clock DESKEW register Delay cells addition in the path of FEEDBACK clock to PLL 00 Bypass delay cells 01 Add 1 cells 10 Add 2 cells 11 Add 3 cells 1 0 DESKEW_PLL_REF_CLK 0x0 These bits set the PLL REF clock DESKEW register Delay cells addition in the path of REFERENCE clock to PLL 00 Bypass delay cells 01 Add 1 cells 10 Add 2 cells 11 Add 3 cells Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 43 I Microsemi SERDESIF Block I O Signal Interface of SERDESIF The SERDESIF block interfaces with the FPGA fabric and SERDES differential I O pad The SERDESIF I Os can be grouped into a number of interfaces from functional protocol The SERDESIF I O signals interface are listed below Reset interface Clock reset interface e AXI AHB Lite AHBL master interface AXI AHBL slave interface APB interface 32 bit e External PCS interface lane2 and lane3 e 1 0 pad interface SPLL control and status Interface e PCle interrupt and power management interface These interface signals are multiplexed to support different serial protocols at any point of time Table 1 52 SERDESIF Block Reset Interface Connected Port Type To Description CORE_RESET_N Input Fabric PCle or XAUI mode Active reset for PCle and XAUI fundamental core PHY_RESET_N Input Fabric SERDES PHY Active low reset
271. clock is passed on to DRAM Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology This effectively delays the CLK to the DRAM device by half a cycle providing a CLK edge that DQS can align to during leveling PHY_RD_DQS_SLAVE_DELAY_1_CR Table 7 135 PHY RD DQS SLAVE DELAY 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_DELAY Ox0 15 0 bits of REG_PHY_RD_DQS_SLAVE_DELAY If REG_PHY_RD_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value 330 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_RD_DQS_SLAVE_DELAY_2_CR Table 7 136 PHY RD DQS SLAVE DELAY 2 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_DELAY 0x0 31 16 bits of REG_PHY_RD_DQS_SLAVE_DELAY If REG_PHY_RD_DQS_SLAVE_FORCE is 1 replace delay tap value f
272. code error 2 MDDR SMC AXI M BRESP In Indicates write response This signal indicates the status of the write transaction 00 Normal access okay 01 Exclusive access okay 10 Slave error 11 Decode error 64 MDDR SMC AXI M RDATA In Indicates read data 412 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 10 3 SMC FIC AHB Lite Port List Width Port Name Direction Description 1 MDDR_SMC_AHB_M_HMASTLOCK Out Indicates that the current master is performing a locked sequence of transfers 1 MDDR_SMC_AHB_M_HWRITE Out Indicates write control signal When High this signal indicates a write transfer and when Low a read transfer 1 MDDR_SMC_AHB_M_HRESP In The transfer response Indicates the status of transfer 1 MDDR_SMC_AHB_M_HREADY In When High the signal indicates that a transfer has finished on the bus This signal may be driven Low to extend a transfer 2 MDDR_SMC_AHB_M_HBURST Out Indicates burst type 2 MDDR_SMC_AHB_M_HTRANS Out Indicates the type of the current transfer 00 Idle 01 Busy 10 Non Sequential 11 Sequential 2 MDDR_SMC_AHB_M_HSIZE Out Indicates the size of the transfer 00 Byte 01 Half word 10 Word 32 MDDR_SMC_AHB_M_HWDATA Out The write data bus is used to transfer data during write operations 32 MDDR_SMC_AHB_M_HADDR Out Indicates address bus 32 MDDR_SMC_AHB_M_HRDATA In The
273. create the AXI address and for BARs larger than 4 KB MSBs are ignored 76 Revision 1 0x00000000 0x40000000 0x80000000 0xC0000000 OxFFFFFFFF amp Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide AXI Slave Interface Address Translation The bridge can be configured up to 4 AXI slave address windows to handle address translation on read write requests initiated by the AXI The AXI slave address windows are used to translate a transaction s 32 bit AXI base address to a PCle 32 bit or 64 bit base address in order to generate a PCle TLP The slave address windows can also be used to generate the following PCle parameters e TC selection Indicates the PCle traffic class in the PCle packet header RO bit selection Generates the PCle TLP using a selectable relaxed ordering bit No snoop bit selection Generates the PCle TLP using a selectable no snoop bit The following example shows address translation when AXI slave address windows 0 and 2 target two different region of the host memory and AXI slave address window 1 targets a PCle memory mapped device enabling peer to peer transactions Window 3 is not used in this example Local Device Address Space Host Processor Address Space 0x00000000 PCleFull Address Host Memory I PN Memory Mapped I I PCle to AXI Bridge I OxFFO0Q0Q0 OxFFFFFFFF Figure 2 17 AXI Slave to PCle Address Translation If AXI sla
274. cription 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 FATC_RESET 0x1 Reset to the fabric portion of the fabric alignment test circuit 1 Reset active 392 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Glossary Acronyms ECC Error correction code FDDR Fabric double data rate FIC Fabric interface controller LPDDR Low power double data rate MDDR MSS double data rate SMC Soft memory controller Revision 1 393 I Microsemi Fabric Double Data Rate Subsystem List of Changes The following table lists critical changes that were made in each revision pie omme re 50200330 1 11 12 Updated 3 Dual AHB Interface section SAR 41901 382 Note The part number is located on the last page of the document The digits following the slash indicate the month and year of publication 394 Revision 1 lt gt Microsemi 9 DDR Bridge The DDR bridge is a data bridge between four AHB bus masters and a single AXI bus slave It accumulates AHB writes into write combining buffers prior to bursting out to external DDR memory It also includes read combining buffers allowing AHB masters to efficiently read data from the external DDR memory from a local buffer The DDR bridge optim
275. ct byte location based on the offset address of the data The WCB tag is updated when the Flush Controller section on page 400 completes a flush operation The WCB has four different modes of operation e DISABLE Default state after reset WCB is in DISABLE mode IDLE Once buffer is enabled it enters IDLE mode WRITE COMBINE On the first write into the WCB it enters WRITE COMBINE mode e FLUSH If a flush request is generated from the flush controller the WCB enters FLUSH mode Once a flush operation is completed and if the write buffer disable command is received from the processor the WCB enters DISABLE mode Before entering DISABLE mode the WCB checks whether a bufferable write is pending or not If a bufferable write is pending the WCB enters IDLE mode after the flush operation and updates the tag After updating the tag register it goes to WRITE COMBINING mode The flush controller sees that the buffer is in write combining mode and a disable command has been received from the processor so it enters FLUSH mode After exiting from FLUSH mode since the disable command is high the WCB enters DISABLE mode Data is written to the WCB on any of the following conditions 1 Address received for the write is in a bufferable region the WCB is not disabled and the transfer is not a locked transfer 2 The WCB is in IDLE mode and the write request is received from an AHB Master 3 The WCB is in write combining mode and the ad
276. ctrical idle I on the transmit driver Table 5 73 ATXDRT EN 15 8 ATXDRT EI1 15 8 Register Bit Reset Number Name Value Description 7 0 ATXDRT EI1 15 8 This register defines bit 15 to bit 8 of the transmitted T parameter sent to the PHY for being in electrical idle I on the transmit driver Table 5 74 e ATXDRT EI 20 16 ATXDRT EI1 20 16 Register Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRT EI1 20 16 This register defines bit 20 to bit 16 of the transmitted T parameter sent to the PHY for being in electrical idle I on the transmit driver ATXDRP EI2 7 0 Register Table 5 75 ATXDRP EI2 7 0 Bit Reset Number Name Value Description 7 0 ATXDRP EI2 7 0 This register defines bit 7 to bit 0 of the transmitted P parameter sent to the PHY for being in electrical idle Il on the transmit driver 208 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide ATXDRP EI2 15 8 Register Table 5 76 ATXDRP EI2 15 8 Bit Reset Number Name Value Description 7 0 ATXDRP_EI2 15 8 This register defines bit 15 to bit 8 of the transmitted P parameter sent to the PHY for being in electrical idle II on the transmit driver ATXDRP EI2 20 16 Register Table 5 77 ATXDRP EI2 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0
277. current value of the PCle device control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enabled in the system PCIE_DEV2SCR 230h This register reports the current value of the PCle device control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enabled in the system This register is used when link speed is set to 5 0 Gbps bi status register It can be monitored by the local processor when CFG PMSCR 04Ch This register reports the current values of the XpressRich2 core s power management control status register PCIE_LINKSCR 034h This register reports the current value of the PCle link control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enabled in the system relaxed ordering and no snoop bits are enabled in the system This Configuration Registers PCIE_LINK2SCR 234h This register reports the current value of the PCle link control and register is used when link speed is set to 5 0 Gbps These registers are not implemented in SmartFusion2 SoC FPGA PCle endpoints Input Output Control Registers These registers are not implemented in SmartFusion2 SoC FPGA PCle endpoints Revision 1 89 I Microsemi PCI Express PCle Bridge Registers The following section describes all the PCle bridge registers in detail VID_DEVID Register 000h Table 2 16 VID
278. d IO CONTROL Register 170h Table 2 108 10 CONTROL Bit Reset Number Name Value Description 31 0 IO_CONTROL_31_0 Reserved IO ADDR Register 174h Table 2 109 10 ADDR Bit Reset Number Name Value Description 31 0 IO ADDR 31 0 Reserved IO WRITE DATA Register 178h Table 2 110 10 WRITE DATA Bit Reset Number Name Value Description 31 0 IO WRITE DATA 31 0 Reserved IO READ DATA Register 17Ch Table 2 111 10 READ DATA Bit Reset Number Name Value Description CFG FBE Register 180h Table 2 112 CFG FBE Bit Reset Number Name Value Description 31 0 CFG FBE 310 Reserved PREFETCH IO WINDOW Register 184h Table 2 113 PREFETCH IO WINDOW Bit Reset Number Name Value Description 31 0 PREFETCH IO WINDOW 31 0 Reserved 114 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PCIE_CONFIG Register 204h Table 2 114 PCIE CONFIG Bit Reset Number Name Value Description 31 5 PCIE_CONFIG_31_5 Reserved 4 PCIE_CONFIG_4 Selects the level of de emphasis for an upstream component when the link speed is 5 0 Gbps 3 0 PCIE_CONFIG_3_0 Sets PCle Specification version capability 0000 Core is compliant with PCle Specification 1 0a or 1 1 0001 Core is compliant with PCle Specification 1 0a or
279. d out of order for a single AXI transaction The tags returned from the DDR controller are used to reorder the data by the read slave interface port The reorder buffer is implemented as a standard register bank of 20x65 bits 64 bits are for the data and 1 bit stores the read error response This size allows enough storage for up to 5 read transactions each with 5 cycles of read data on both the AXI channels If the DDR transactions are of partial reads 2 cycles of data it can store the data for up to 7 read transactions DDR Controller Refer to the DDR Controller section on page 235 Configurations Memory Type The MDDR subsystem can be configured to use DDR2 DDR3 or LPDDR1 SDRAM using the SmartFusion2 SoC FPGA MSS configurator in Libero SoC Refer to the MDDR Configurator User s Guide for more details Bus Width Configurations The controller can be programmed to work in full half or quarter bus width mode by configuring DDRC_MODE_CR when the controller is in soft reset 1 In full bus width mode the PHY size is 32 The PHY size is 36 if SECDED is enabled 2 In half bus width mode the PHY size is 16 The PHY size is 18 if SECDED is enabled 3 In quarter bus width mode the PHY size 8 The PHY size is 9 if SECDED is enabled Revision 1 243 lt gt Microsemi MSS DDR Subsystem Supported bus widths in SmartFusion2 SoC FPGA devices are listed in Table 7 5 Table 7 5 Supported Bus Widths
280. d DDR type e Support for sequential and interleaved burst ordering e For DDR3 configurations programmable internal control for ZQ short calibration cycles e Supports dynamic scheduling to optimize bandwidth and latency e Support for self refresh entry and exit on software command e Support for dynamically changing clock frequency while in self refresh Support for deep power down entry and exit on software command Support for per command auto precharge e Flexible address mapper logic to allow application specific mapping of row column bank and rank bits e Configurable support for 1T or 2T timing on the DDR SDRAM control signals Supports autonomous DRAM power down entry and exit caused by lack of transaction arrival for programmable time Advanced power saving design includes no unnecessary toggling of command address and data pins Revision 1 237 I Microsemi MSS DDR Subsystem MDDR Subsystem Overview The MDDR subsystem is a part of the SmartFusion2 SoC FPGA MSS that interfaces with high speed DDR memories The system level block diagram of the MDDR subsystem is shown in Figure 7 1 The MDDR subsystem includes blocks such as the DDR fabric interface controller DDR FIC AXI transaction handler DDR memory controller and DDR PHY The MDDR has a special mode called soft memory controller fabric interface controller SMC_FIC Soft Memory Controller Fabric Interface Controller section on page 407 in which the MSS
281. d address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 14 is set to 0 3 0 REG DDRC ADDRMAP ROW B15 0x0 Selects the address bit used as row address bit 15 Valid range 0 to 11 and 15 Internal base 21 The selected address bit is determined by adding the internal base to the value of this field If set to 15 row address bit 15 is set to 0 Revision 1 277 I Microsemi MSS DDR Subsystem DDRC_INIT_1_CR Table 7 32 e DDRC_INIT_1_CR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 7 1 REG_DDRC_PRE_OCD_X32 REG_DDRC_FINAL_WAIT_X32 0x0 0x0 Wait period before driving the OCD Complete command to DRAM Units are in counts of a global timer that pulses every 32 clock cycles There is no known specific requirement for this It may be set to zero Cycles to wait after completing the DRAM initialization sequence before starting the dynamic scheduler Units are in counts of a global timer that pulses every 32 clock cycles There is known specific requirement for this it may be set to zero REG_DDRC_SKIP_OCD 0x1 This register must be kept at 1 1 Indicates the con
282. d be preserved across a read modify write operation 10 0 REG_DDRC_HPR_MAX_STARVE_X32 0x0 11 1 bits of REG_DDRC_LPR_MAX_STARVE_X32 Number of clocks that the HPR queue can be starved before it goes critical Unit 32 clocks DDRC_LPR_QUEUE_PARAM_1_CR Table 7 61 DDRC LPR QUEUE PARAM 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 REG_DDRC_LPR_MAX_STARVE_X32 0x0 Lower 1 bit of REG_DDRC_LPR_MAX_STARVE_X32 Number of clocks that the LPR queue can be starved before it goes critical Unit 32 clocks 292 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 61 DDRC LPR QUEUE PARAM 1 CR continued Bit Reset Number Name Value Description 14 4 REG DDRC LPR MIN NON CRITICAL 0x0 Number of clocks that the LPR queue is guaranteed to be non critical Unit 32 clocks 3 0 REG_DDRC_LPR_XACT_RUN_LENGTH 0x0 Number of transactions that are serviced once the LPR queue goes critical is the smaller of this value and number of transactions available Units Transactions DDRC_LPR_QUEUE_PARAM_2_CR Table 7 62 DDRC LPR QUEUE PARAM 2 CR Bit Reset Number Name Value D
283. d by International Traffic in Arms Regulations ITAR contact us via soc_tech_itar microsemi com Alternatively within My Cases select Yes in the ITAR drop down list For a complete list of ITAR regulated Microsemi FPGAs visit the ITAR web page Revision 1 Microsemi Corporation NASDAQ MSCC offers a comprehensive portfolio of semiconductor solutions for aerospace defense and security enterprise and communications and industrial and alternative energy markets Products include high performance high reliability analog and RF devices mixed signal and RF integrated circuits customizable SoCs FPGAs and complete subsystems Microsemi is headquartered in Aliso Viejo Calif Learn more at Microsemi www microsemi com Microsemi Corporate Headquarters ee beeper tert ag USA 2012 Microsemi Corporation All rights reserved Microsemi and the Microsemi logo are trademarks of ithin the i i i i i i i Sales 1 949 380 6136 Microsemi Corporation All other trademarks and service marks are the property of their respective owners Fax 1 949 215 4996 50200330 1 11 12
284. d to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG PHY USE WR LEVEL 0 PHY WR DATA SLAVE RATIO 4 CR Table 7 158 PHY WR DATA SLAVE RATIO 4 CR Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 0 REG_PHY_WR_DATA_SLAVE_RATIO 0x0 49 48 bits of REG_PHY_WR_DATA_SLAVE_RATIO Ratio value for write data slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the write DQ MUXes in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line This is only used when REG_PHY_USE_WR_LEVEL 0 Revision 1 339 I Microsemi MSS DDR Subsystem PHY_WRLVL_INIT_MODE_CR Table 7 159 PHY_WRLVL_INIT_MODE_CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_
285. dataword RX data and provides the deserialized data synchronous to the recovered link clock RX clock Note The TX clock and RX clock do not need to be identical in frequency The receiver also incorporates programmable continuous time linear equalization while maintaining proper input impedance Refer to the SERDES Block Register section on page 183 for details Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Clock Macro The clock macro in the PMA contains one transmit PLL TX PLL and one clock data recovery PLL CDR PLL which allow the TX and RX data paths to operate in asynchronous frequencies using different reference clock inputs Figure 5 4 shows the overview of the clock macro with some associated signals For applications where the TX and RX data paths operate in the same line rate range the RX PLL can be shared between the TX and RX data paths and the TX PLL can be powered down to conserve power Refer to TX PLL and CDR PLL Operation on page 177 TX Data 0 TX Data 10 TX Div Baud Clk 16 ath EE Reference Clock Loop Near End 7 K77 aRefClk RX Div Baud Clk RX Clk RX Data 19 RX Data 0 Figure 5 4 TX PLL and CDR PLL in PMA Revision 1 173 lt gt Microsemi Serializer Deserializer 174 Each of the PLLs TX PLL and CDR PLL contains the necessary dividers and output high BitClk S_Clk T_Clk and low frequenc
286. defines the F setting for the TX PLL and CDR PLL of the PMA macro for the PCle Gen2 protocol Note reset This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under PLL M N 5GBPS Register PCle Gen2 protocol only Table 5 20 PLL M N 5GBPS Bit Reset Number Name Value Description 7 CNT250NS MAX 5G This defines bit 7 and bit 6 of the cnt250ns max counter mentioned in BPS 8 Reg18 6 5 M This register defines the TX PLL M values and CDR PLL M value settings of the PMA macro for the PCle Gen2 protocol 4 0 N This register defines the TX PLL N values and CDR PLL N value settings of the PMA macro for the PCle Gen2 protocol Note This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under reset 196 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide CNT250NS_MAX_5GBPS Register PCle Gen2 protocol only Table 5 21 CNT250NS MAX 5GBPS Bit Reset Number Name Value Description 7 0 CNT250NS MAX 5GBPS 7 0 This register defines the base count of a 250 ns event based on the aTXClk clock This counter is used by the CDR PLL in PCS driven mode Note This register must only be reprogrammed when PHY is under reset for proper operation It impacts the PCS driven CDR PLL mode as well as calibration and thus
287. details Table 2 2 Configuration Inputs for Configuring the AXI to AXI AHBL Bridge F_AXI_AHB_SLAVE Specifies whether there is an AXI AHBL slave implemented in the fabric 1 AXI slave implemented in fabric default value 0 AHB slave implemented in the fabric AHB_DATA_WIDTH Specifies whether there is a 32 bit or 64 bit AHB slave in fabric Applies only when F_AXI_AHB_SLAVE is programmed to 0 1 64 bit AHB slave implemented in the fabric default value 0 32 bit AHB slave implemented in the fabric The AXI interface has the following limitations 1 Supports only INCR types of bursts 2 Supports only 64 bit read write transactions on the AXI slave interface Revision 1 65 lt gt Microsemi PCI Express AHBL AXI to AXI Bridge AHB AXI TOP The AHBL AXI to AXI bridge module implements an AHBL AXI master to AXI master protocol translator The bridge appears as a 64 bit AXI slave or 32 bit AHBL slave to the fabric 64 bit AXI master or 32 bit AHBL master on the input side The appearance on the output side is as 64 bit AXI master to the 64 bit PCle AXI slave on the PCle side So the input side of the bridge accepts 32 bit AHBL master transactions or 64 bit AXI master transactions and converts the transactions into 64 bit AXI master output transactions Figure 2 5 shows the block diagram of the AHBL AXI to AXI bridge AXI AHB TOP AX164 Master AHB32 Master Interface PCle 4 gt AHB to AXI AXI64
288. devices Units Clocks DDRC DFI WR LVL CONTROL 2 CR Table 7 70 DDRC DFI WR LVL CONTROL 2 CR Bit Number Name Reset Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 5 REG_DDRC_DFI_T_WLMRD 0x0 First DQS DQS rising edge after write leveling mode is programmed Only present in designs that support DDR3 devices Units Clocks REG DDRC DFI WR LEVEL EN 0x0 1 Write leveling mode has been enabled as part of the initialization sequence Only present in designs that support DDR3 devices 3 0 296 REG_DDRC_DFI_WRLVL_MAX_X1024 0x0 Revision 1 11 8 bits of REG DDRC DFI WRLVL MAX X1024 Write leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI WRLVL RESP to a write leveling enable signal DDRC DFI WRLVL EN Only applicable when connecting to PHYs operating in PHY write leveling evaluation mode Units 1 024 clocks Only present in designs that support DDR3 devices lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_DFI_RD_LVL_CONTROL_1_CR Table 7 71 DDRC_DFI_RD_LVL_CONTROL_1_CR Bit Reset Number Name Value Descrip
289. dify write operation 12 0 REG_PHY_WR_DQS_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_WR_DQS_SLAVE_DELAY If REG_PHY_WR_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY_WR_DQS_SLAVE_FORCE_CR Table 7 146 PHY WR DQS SLAVE FORCE CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_WR_DQS_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for read DQS slave DLL with the value of the REG_PHY_WR_DQS_SLAVE_DELAY bus bit 4 is for PHY Data slice 4 bit 3 for PHY Data slice 3 and so on 334 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_WR_DQS_SLAVE_RATIO_1_CR Table 7 147 PHY_WR_DQS_SLAVE_RATIO_1_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_WR_DQS_SLAVE_RATIO 0x0 15 0 bits of REG PHY WR DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to
290. document The digits following the slash indicate the month and year of publication 58 Revision 1 lt gt Microsemi 2 PCI Express The SmartFusion2 SoC FPGA family supports two hard high speed serial interface blocks SERDESIFO and SERDESIF1 Each SERDESIF block contains a PCI Express system block also known as a PCIe system The PCle system interfaces to the FPGA fabric and the serialization deserialization SERDES block The PCle system IP block and SERDES block in SERDESIF implements PCle Base Specification Rev 2 0 for Gen1 or Gen2 The main features of PCI Express implemented in SmartFusion2 SoC FPGA are as follows x1 x2 x4 lane support Implements native endpoint e PCle Base Specification Revision 2 0 and 1 1 compliant e 1 virtual channel VC e 1 to 3 64 bit base address registers e Receive transmit and retry buffer using Dual port RAM implementation Fully compliant physical layer device PHY physical coding sub layer PCS PCle Endpoint The SmartFusion2 SoC FPGA supports implementing PCle endpoint Figure 2 1 shows the PCle implementation in SERDESIF SERDESIF Block SERDES PMA and PCle PCS SERDES I O Pads SERDESIF PCle System Register System IP PCle L2 P2 AXI AHB AXI AHB APB Slave Control Master Slave Interface FPGA Fabric Interface Interface Figure 2 1 e SERDESIF Configuration for PCle Single Protocol Mode Revision 1 59 lt gt Microsemi PCI Express Table 2 1 shows th
291. dress received for the write transfer from an AHB Master matches the WCB Tag If the data is not combined it is directly bypassed to the AXI bus arbiter Each buffer has a 10 bit timer down counter which starts when the first bufferable write data is loaded into the WCB The timer starts decrementing its value at every positive edge of the AHB clock and when it reaches zero a timeout event is generated and a flush request is generated to the flush controller The Revision 1 399 3 Microsemi DDR Bridge timer restarts once the next bufferable write is detected Figure 9 5 shows the flowchart for WCB operation WCB in DISABLE mode Write buffer enable 1 NO YES WCB in IDLE mode rite Request 1 NO YES lt Y Write data is buffered for next write requests based on WCB tag Flush request from Flush Controller Any pending bufferable write request Figure 9 5 Flow Chart for WCB Operation Flush Controller The flush controller flushes writes the WCB to external memory It sends a flush request to the arbiter for flush operation It communicates with other WCBs and the read buffer on master Interface 0 and broadcasts internal signals to maintain data coherency The flush controller checks whether any other master that has initiated a read to the same address for which data is already present in a write buffer or for which a flush operation is ongoing If the addr
292. e SERDESIF Block chapter for details about setting serial protocols The SERDES macro register allows control of the parameters corresponding to PLL frequency baud rate output voltage de emphasis RX equalization and parallel data path width for the PCS logic These registers can be modified after power up through the register space interface signals on a per lane basis or all lanes together These registers can be accessed through the APB interface and load the SERDES parameters after power up or simply change the output voltage amplitude or de emphasis due to a high bit error rate seen on a specific lane SERDES Functional Blocks The following section briefly describes the various sub blocks of the SERDES block in one lane Figure 5 2 shows the simplified SERDES block diagram for single lane implementation The SERDES block in each lane includes the following PMA macro block PCle PCS block Transmit TX Phase 8b 10b Serializer Matching Encoder TXDP FIFO TXDN PMA Impedance 5 i and Offset segs te Calibration Ru PCI Express PMA PCS Block Macro Block RX PLL RXDP RXDN RX Deserializer 8b 10b Decoder Receive Word Elastic Capture Alignment Buffer Logic Figure 5 2 e SERDES Macro for Single Lane Implementation 170 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PMA Macro Block The PMA macro contains all high speed analog logic as well as TX PLL and
293. e valid data to transmit before generating a global read enable This bit is intended to be used in case of any issue with this function When set each lane might start transmitting data with one 500 MHz clock uncertainty corresponding to 5 or 10 bits time depending on the speed of the link Even if violating the protocol requirement the PCle standard is strong enough to support this non compliance 1 CDR_ERR When set this register disables the error counter internally of the CDR PLL state machine which switches back the CDR PLL to frequency mode acquisition when the number of errors counted is higher than the predefined error threshold This bit is intended for disabling this function in the case of any issue with the PHY 0 CDR P1 This register defines the state of the CDR PLL when the PHY is in P1 low power mode When set to zero the CDR PLL is put in reset and low power enabling maximum power savings When the opposite component sends the TS1 ordered set to drive the link in recovery only the PIPE RXELECIDLE signal is deasserted at the PIPE interface and the PHY waits for the controller to change the pipe powerdown 1 0 signal back to PO before retraining the CDR PLL 6 us and sending received data to the controller When set to 1 the CDR PLL is kept alive in frequency lock mode in the P1 state which enables a faster recovery time from the P1 state but which also consumes more power all RX logic is kept alive and consumes power in
294. e AHB masters have a round robin arbitration scheme For using dual AHB interface of FDDR the CFG_NUM_AHB MASTERS bit in the DDR FIC NUM AHB MASTERS CR register must be set to 1 FPGA FABRIC AHB Measter AHB Master APB Master User Logic User Logic Logic APB S PCLK APB S PRESET N CORE RESET N CLK BASE FAB PLL LOCK FDDR SmartFusion2 FDDR with Dual AHB Interface Register Interface Table 8 2 lists the registers visible on the DDR APB interface Table 8 2 Address Table for Register Interfaces Registers Address Offset Space DDR Controller Configuration Register 0x000 0x1FC PHY Configuration Register Summary 0x200 0x3FC DDR FIC Configuration Register Summary 0x400 0x4FC FDDR SYSREG 0x500 0x5FC Reserved 0x600 0x7FC 382 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FDDR SYSREG Configuration Register Summary Table 8 3 FDDR SYSREG Address Register Reset Register Name Offset Type Flash Source Description PLL CONFIG LOW 1 0x500 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of the MPLL PLL CONFIG LOW 2 0x504 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of the MPLL PLL CONFIG HIGH 0x508 RW P PRESETN Comes from SYSREG Controls the corresponding configuration input of
295. e Bridge Registers section on page 65 for more information PCle Power Management PCle active state power management ASPM defines link power management states that a PCle physical link is permitted to enter in response to software driven D state transitions or active state link power management activities The PCle protocol defines the following low power link states Table 2 9 PCle Low Power States Low Power State Description LOs Autonomous electrical idle This state reduces power during short intervals of idle Devices must transition to LOs independently on each direction of the link L1 Directed electrical idle The L1 state reduces power when the downstream port directs the upstream ports This state saves power in two ways e Shutting down the transceiver circuitry and associated PLL e Significantly decreasing the number of internal core transitions L2 In this state a beacon or WAKE signal is required to reinitialize the Link Auxiliary power is still available however L2 L3 ready This state prepares the PCle link for the removal of main power and the reference clock 80 SmartFusion L2_P2 Entry Exit Traditionally the PCle specification states to implement two power domains if L2 P2 state support is implemented in the PCle link Vaux and Vmain The root complex power management logic supplies controls the power through the connector to the whole PCle fabric SmartFusion2 SoC FPGA Implementa
296. e Cortex M3 processor The interrupt can be cleared by setting the DDR_LOCKOUT bit in the MSS_EXTERNAL_SR from SYSREG block If the interrupt is cleared and the lock signal is still asserted the counter will start counting again Revision 1 403 I Microsemi DDR Bridge The error routine should be stored in eSRAM so that the processor can fetch the ISR without going through the DDR Bridge As part of the ISR the CM3 will read the SYSREG registers to identify the master and take appropriate action to release the arbiter in DDR Bridge from dead lock MSS DDR Bridge Configurations The DDR bridge configurator in Libero SoC allows configuration of the MSS DDR bridge Configurable parameters are listed below Buffer size 1b 32 bytes Ob 16 bytes Non bufferable address and Non bufferable size Timeout value for each write buffer Set timeout value to maximum or non zero value Enable or disable respective buffer allocated for each master MDDR FDDR DDR Bridge Configuration Steps 404 Configure the clock ratios using DDR_FIC_DIVISOR bits in the MSSDDR_FACC1_CR register for MDDR and the lt FDDR_FACC_DIVISOR_RATIO gt register for FDDR The ratios are set during power up and cannot be changed after that Configure buffer size to 32 bytes or 16 bytes using the DDR FIC NBRWB SIZE CR register Configure the non bufferable address using the DDR FIC NB ADD register Configure the non bufferable size using the DDR FIC NBRWB SIZE CR register
297. e EPCS resets signal selection from the FPGA fabric Revision 1 163 I Microsemi EPCS Interface SmartFusion2 SoC FPGA EPCS Mode I O Signal Interface The SmartFsuion2 SERDESIF EPCS interface can be configured for Single protocol Multi protocol mode In Single protocol mode all the x4 SERDES lanes of the EPCS interface are exposed to the FPGA fabric In Multi protocol mode only two SERDES lanes Lane2 and Lane3 of the EPCS interface are exposed to the FPGA fabric Because of this configuration the EPCS interface for Lane2 and Lane3 is directly connected to the FPGA fabric and the EPCS interface for LaneO and Lane are overlaid on the AXI Master and slave interface Refer to the Serializer Deserializer section on page 169 for further details Table 4 7 Table 4 8 on page 165 and Table 4 9 on page 167 show the list of EPCS mode I O signals interface Table 4 7 EPCS Mode I O PAD Interface Connecte Port Name Type d to Description PCIE_x_RXDPO Input I O Pads Receive data SERDES differential positive input each SERDESIF consists of 4 RX signals Here x 0 for SERDESIF_0 and x 1 PEE a RaDP i for SERDESIF 1 If unused can be left floating PCIE_x_RXDP2 PCIE_x_RXDP3 PCIE_x_RXDNO Input I O Pads Receive data SERDES differential negative input PCIE x RXDN1 Each SERDESIF consists of 4 RX signals Here x 0 for SERDESIF_0 and x 1 for SERDESIF
298. e RX PLL VCO settings by applying a static zero to the PMA aRXHfClkDnb signal The aRXClk signal will still be functional in this case but within specified bounds of accuracy linked to Refclk Note that since S_Clk and T_Clk are not operational bitstream lock cannot be achieved and the PCS will park the CDR PLL in frequency acquisition mode which locks to aRefClk Acquiring Bit Lock for CDR PLL There are two modes of lock where the CDR PLL can be trained to the incoming bitstream PCS driven mode e PMA driven mode The steps for acquiring bit lock are similar in both modes Bit 3 of the CRO register PMA driven mode puts the CDR PLL in PMA driven mode or PCS driven mode In PMA driven mode CDR_PLL_MANUAL_CR CDR PLL manual control register controls the bit lock steps Both modes of lock require two steps for training the CDR PLL to the incoming bitstream for the lock 1 Frequency lock The frequency lock FL operation whereby the CDR PLL locks to the reference clock The sampling clock at the receiver is not aligned to the center of the data eye during this step 2 Phase lock The phase lock PL operation whereby CDR PLL acquires phase and small frequency deviation lock to the bitstream The sampling clock at the receiver will be aligned to the center of the data eye after this step It is imperative that the bitstream be valid upon entering phase lock There are two further steps for phase lock Coarse phase lock which has a highe
299. e SERDES behavior as long as Reg81 bit 0 is not set FORCE ATXDRT 15 8 Register Table 5 95 FORCE ATXDRT 15 8 Bit Reset Number Name Value Description 7 0 FORCE ATXDRT 15 8 This register defines bit 15 to bit 8 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set 212 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FORCE_ATXDRT_20_16 Register Table 5 96 FORCE ATXDRT 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 FORCE ATXDRT 20 16 This register defines bit 20 to bit 16 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set RXD OFFSET CALIB RESULT Register Table 5 97 RXD OFFSET CALIB RESULT Bit Reset Number Name Value Description 7 5 Unused 4 ARXDDIR This register reports the sign of voltage applied to aRXD settings for RX offset calibration 3 0 ARXDNULJ 3 0 This register reports the voltage applied to aRXD settings for RX offset calibration RXT OFFSET CALIB RESULT Register Table 5 98 RXT OFFSET
300. e bits set MSI TC 1 of MSI MAP7 ERROR COUNTER 0 Register 0A0h Table 2 56 ERROR COUNTER 0 Bit Reset Number Name Value Description 31 14 ERROR COUNTERO 31 24 Eight bit counter that reports the following error source A3 DLLP error 23 16 ERROR COUNTERO 23 16 Eight bit counter that reports the following error source A2 TLP error 15 8 ERROR COUNTERO 15 8 Eight bit counter that reports the following error source A1 Training error not supported 7 0 ERROR COUNTERO 7 0 Eight bit counter that reports the following error source AO Receiver port error ERROR COUNTER 1 Register 0A4h Table 2 57 ERROR_COUNTER 1 Bit Reset Number Name Value Description 31 14 ERROR COUNTER1 31 24 Eight bit counter that reports the following error source AT Poisoned TLP received error 23 16 ERROR COUNTER1 23 16 Eight bit counter that reports the following error source A6 Data link layer protocol error 15 8 ERROR COUNTER1 15 8 Eight bit counter that reports the following error source A5 Replay number rollover error 7 0 ERROR_COUNTER1_7_0 Eight bit counter that reports the following error source A4 Replay time error Revision 1 103 lt gt Microsemi PCI Express ERROR COUNTER 2 Register 0A8h Table 2 58 ERROR COUNTER 2 Bit Reset Number Name Value Description 31 14 ERROR COUNTER2 31 24 Eight bit counter t
301. e clock 40 Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg6C EPCS_RSTN_SEL Register 0x206C Table 1 37 EPCS RSTN SEL Bit Reset Number Name Value Description 3 0 FABRIC EPCS RSTN SEL 0x0 EPCS reset signal selection from FABRIC Reg70 CHIP_ENABLES Register 0x2070 Table 1 38 CHIP ENABLES Bit Reset Number Name Value Description 0 GEN2 SUPPORTED Ox1 GEN2 enable for PCIe 1 GEN2 enabled 0 GEN2 disabled All the register are 32 bit Bits not shown in the table are reserved Reg 74 SERDES TEST OUT Register 0x2074 Table 1 39 SERDES TEST OUT Bit Reset Number Name Value Description 31 0 SERDES TEST OUT 0x0 Status TESTOUT output of PCle PHY SERDES TEST OUT 31 24 Debug signal for lane3 SERDES TEST OUT 23 16 Debug signal for lane2 SERDES_TEST_OUT 15 80 Debug signal for lane1 SERDES TEST OUT 7 0 Debug signal for laneO Bit 0 Tx PLL reset Bit 1 Rx PLL reset Bit 2 Activity detected Bit 3 CDR PLL locked on data Bit 4 Tx PLL locked Bit 5 Rx PLL locked Bit 7 6 reserved Reg78 Reserved 0x2078 Table 1 40 Reg78 Bit Reset Number Name Value Description Reg7C RC_OSC_SPLL_REFCLK_SEL Register 0x207C Table 1 41 RC OSC SPLL REF
302. e custom pattern Note that the PRBS SEL register must also be set for transmitting the custom pattern on the link CUST TYP CUSTOM PATTERN CTRL 3 1 This signal defines whether the custom pattern generated on the link is generated by the custom pattern register or by one of the hard coded patterns 000b Custom pattern register 100b All zero pattern 0000 00 101b All one pattern 1111 11 110b Alternated pattern 1010 10 111b Dual alternated pattern 1100 1100 CUST CHK CUSTOM PATTERN CTRL 4 This bit enables the error counter CUST SKIP CUSTOM PATTERN CTRL 5 This register is used in RX word alignment manual mode CUST AUTO CUSTOM PATTERN CTRL 6 This allows the word alignment to be performed automatically by a state machine that checks whether the received pattern is word aligned with the transmitted pattern and to automatically use the PMA CDR PLL skip bit function to find the alignment CUST ERROR CUSTOM PATTERN CTRL 3 0 When the custom pattern checker is enabled this status register reports the number of errors detected by the logic when the custom word aligner is in synchronization It starts counting only after a first matching pattern has been detected CUST_SYNC CUSTOM PATTERN CTRL 4 This bit reports that the custom pattern is word aligned CUST STATE CUSTOM PATTERN CTRL 7 5 This register reports the current state of the custom pattern word alignment state machine R
303. e high speed serial interface generator available in Libero SoC It sets the MUX selection depending on the reference clocks selected A 100 MHz clock should be fed in as reference clock to SERDES 4 PMAs in XAUI mode Protocol 1 PHY Reference Clock 1 0 PortO v I O Port1 Fabric SERDES Reference Clock Using High Speed Serial Interface Generator PCIe Clock Network Figure 2 11 shows the PCle clocking architecture in SmartFusion2 SoC FPGA The 100 MHz reference clock to SERDES PMA for TX PLL and CDR PLL can be selected as explained in SERDES Reference Clocks for PCle Mode section on page 71 The PLLs generate 250 MHz or 125 MHz clocks depending on protocol settings and passed to PCle System IP block Also the PLL settings are calculated automatically by Libero SoC software when PCle protocol mode is selected The SPLL allows reducing the skew between the fabric and SmartFusion2 SoC FPGA SERDESIF module The APB clock APB_S_PCLK is an asynchronous clock used for SERDESIF register access RXDP TXDP RXDN TXDN Gen1 2 5 GHz 5 GHz FPGA Fabric Reference Clock 100 MHz TxClk x4clks RxCLK x4clks PCle PCS APB S PCLK CLK BASE 250 125 MHz SERDESIF Figure 2 11 72 TxClk x4clks 4to1 MUX 250 125 MHz TxClk PLL_SERDESIF_REF Deskew l PLL_SERDESIF_FB Deskew PLL_ACLK SPLL Clocking in PCle Mode Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User
304. e identification registers CONFIG_PCIE_2 0x38 R W Defines PCle subsystem revision ID and class code CONFIG_PCIE_3 Ox3C R W Sets PCIe link speed CONFIG BAR SIZE 0 1 0x40 R W Sets BARO and BAR1 of PCIe core register map CONFIG BAR SIZE 2 3 0x44 R W Sets BAR2 and BAR3 of PCle core register map CONFIG BAR SIZE 4 5 0x48 R W Sets BAR4 and BARS of PCIe core register map SER CLK STATUS Ox4C R O This register describes SERDES PLL lock information Reserved 0x50 R O Reserved 0x54 R O SER_INTERRUPT 0x58 SW1C SPLL FPLL lock interrupt SERDESIF_INTR_STATUS Ox5C SW1C SECDED interrupt status for PCle memories Reserved 0x60 REFCLK SEL 0x64 R W Reference clock selection for the four lanes of PMA PCLK_SEL 0x68 R W PCle core clock selection EPCS RSTN SEL Ox6C R W EPCS reset signal selection from fabric CHIP ENABLES 0x70 R O GEN2 enable for PCle SERDES TEST OUT 0x74 R O Status Test out output of PCle PHY SERDES FATC RESET 0x78 R W Fabric alignment test circuit reset input RC OSC SPLL REFCLK SEL Ox7C R W Reference clock selection for SPLL SPREAD SPECTRUM CLK 0x80 R W Spread spectrum clocking configuration CONF AXI MSTR WNDW 0 0x84 R W PCle AXI master window0 configuration register 0 CONF AXI MSTR WNDW 1 0x88 R W PCle AXI master window0 configuration register 2 CONF AXI MSTR WNDW 2 Ox8C R W PCle AXI master window0 configuration register 2 CONF AXI MSTR WNDW 3 0x90 R W PCle AXI master window0 configuration
305. e of the BAR5 memory For example 32 bit BAR CONFIG_BAR_SIZE_5 5 d25 translates to BAR5 32MB 1111 1110 0000 0000 0000 0000 0000 CONFIG BAR C ONTROL 5 12 9 8 4 CONFIG BAR CONTROL 5 CONFIG BAR SIZE 4 0x0 0x0 3 0 LSB bits of BAR 5 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable non prefetchable memory These bits set the size of the BAR4 memory For example 32 bit BAR CONFIG BAR SIZE 4 5 d24 translates to BAR4 16MB 4111 1111 0000 0000 0000 0000 0000 CONFIG BAR C ONTROL 4 3 0 CONFIG BAR CONTROL 4 0x0 3 0 LSB bits of BAR 4 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable non prefetchable memory Note All the register are 32 bit Bits not shown in the table are reserved Reg4C SER_CLK_STATUS Register 0x204C Table 1 29 SER CLK STATUS Bit Number Name Reset Value Description 17 13 FAB PLL LOCK 0x0 Fabric PLL lock information 12 9 PLL_LOCK 0x0 SPLL lock information Reg50 Reserved 0x2050 Table 1 30 Reg50 HER Name Reset Value Description 0x0 Reg54 Reserved 0x2050 Table 1 31 Reg54 Bit Number Name Reset Value Description 0x0 38 Revision 1 lt
306. e products the value of a reserved bit should be preserved across a read modify write operation 14 CALIB_TRIM 0x0 Indicates override of the calibration value from the pc code programmed code values in the DDRIO calibration block 13 CALIB_LOCK 0x0 Used in the DDRIO calibration block as an override to lock the codes during intermediate runs When the firmware receives CALIB_INTRPT it may choose to assert this signal by prior knowledge of the traffic without going through the process of putting the DDR into self refresh 12 CALIB_START 0x0 Indicates that rerun of the calibration state machine is required in the DDRIO calibration block 11 6 NCODE 0x0 Indicates the DPC override NCODE from flash in DDRIO calibration This can also be overwritten from the firmware 5 0 PCODE 0x0 Indicates the PC override PCODE from flash in the DDRIO calibration block This is also be overwritten from the firmware FDDR_INTERRUPT_ENABLE Table 8 13 FDDR INTERRUPT ENABLE Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_INT_ENABLE 0x0 Masking bit to enable DDR FIC interrupt 5 IO CALIB INT ENABLE 0x0 Masking bit to enable DDR 1 O calibration interrupt 4 FDDR_ECC_INT_ENABLE 0x0 Masking bit to enable ECC error interrupt 3 FABRIC_
307. e various options for implementing a PCle link on four physical SERDES lanes Table 2 1 Options for Implementing PCle in SERDESIF Block Physical SERDES Lanes Logical Lanes Mapping LaneO0 Lane1 Lane2 Lane3 Speed Speed Speed Speed bits per bits per bits per bits per PHY Mode Protocol second Protocol second Protocol second Protocol second Single Protocol PCIe 2 5G PCle Link Mode PCle 2 5G PCle 2 5G PCle 2 5G PCle 2 5G PCle 2 5G PCle 2 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G Single Protocol PCle 2 5G PCle Link Reversed PCle 2 5G PCle 2 5G Mode PCle 2 5G PCle 2 5G PCle 2 5G PCle 2 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G PCle 5G Multi Protocol PCle 2 5G EPCS EPCS PCIe Link Mode PCIe 2 5G PCIe 2 5G EPCS EPCS PCle 5G EPCS EPCS PCle 5G PCle 5G EPCS EPCS Multi Protocol PCIe 2 5G EPCS EPCS as Reversed PCle 2 5G PCIe 2 5G EPCS EPCS PCIe 5G EPCS EPCS PCle 5G PCle 5G EPCS EPCS Note 60 Revision 1 Lane3 EPCS interfaces are available in multi protocol PHY mode can be used for running SGMII protocol I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PCle System PCle is a high speed pa
308. ected to the rx_reset input XAUI_RX_RESET Input Resets the XAUI extender block These pins are connected to set reset ports of all flops in the corresponding rx_clkiX X 01 2 3 clock domain Refer to the XAUI Mode Reset section on page 137 section for detail Table 3 27 SmartFusion2 SoC FPGA XAUI Extender Block Clocking Signal Port Type Description XAUI_OUT_CLK Output XAUI mode feedback clock from for SPLL XAUI_FB_CLK Input XAUI mode fabric clock this clock is driven by SPLL output clock in the XAUI mode Table 3 28 SmartFusion2 SoC FPGA XAUI Mode I O PAD Interface Port Type Description RXDO_P RXD1_P Input SERDES differential positive input for each lane Rx RXD2 P RXD3_P RXDO N RXD1_N Input SERDES differential negative input for each lane Rx RXD2 N RXD3_N TXDO P TXD1_P Output SERDES differential positive output for each lane Tx TXD2 P TXD3 P TXDO_N TXD1_N Output SERDES differential negative output for each lane Tx TXD2_N TXD3_N REXT 3 0 Input Common external resistance VDDPLL 3 0 Input Power Supply PLL PLL REF RETURN 3 0 Input PLL Reference return PLL VDDIO 3 0 Input Power Supply Vmain VSSIO 3 0 Input Power Supply Vss VAUX 3 0 Input Power Supply Vaux 150 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 29 SmartFusion2 SoC FPGA XAUI Ex
309. ects column address bit 6 Valid range 0 to 7 Internal base 3 The selected address bit is determined by adding the internal base to the value of this field 7 4 REG DDRC ADDRMAP COL B4 0x0 Full bus width mode Selects column address bit 5 Half bus width mode Selects column address bit 6 Quarter bus width mode Selects column address bit 7 Valid Range 0 to 7 Internal base 4 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field 3 0 REG DDRC ADDRMAP COL B7 0x0 Full bus width mode Selects column address bit 8 Half bus width mode Selects column address bit 9 Quarter bus width mode Selects column address bit 11 Valid range 0 to 7 and 15 Internal base 7 The selected address bit is determined by adding the internal base to the value of this field If set to 15 column address bit 9 is set to 0 Note Per JEDEC DDR2 specification column address bit 10 is reserved for indicating auto precharge and hence no source address bit can be mapped to column address bit 10 274 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_ADDR_MAP_COL_2_CR Table 7 29 DDRC ADDR MAP COL 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with
310. ed Range A 50 us to 10 ms Range B 10 ms to 250 ms Range C 250 ms to 4 s Range D 4s to 64s PCIE_LINK_CAPABILITIES Register 06Ch Table 2 42 PCIE_LINK_CAPABILITIES Bit Reset Number Name Value Description 31 0 Reserved PCIE_LINK_STATUS_CTRL Register 070h Table 2 43 PCIE LINK STATUS CTRL Bit Reset ae Number Name Value Description 31 0 Reserved Revision 1 97 I Microsemi PCI Express PM DATA SCALE 0 Register 070h Table 2 44 PM DATA SCALE 0 Bit Number Name Reset Value Description 31 24 PM DATA SCALE 0 31 24 These bits set the register that defines Data3 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 23 16 PM DATA SCALE 0 23 16 These bits set the register that defines Data2 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 15 8 PM DATA SCALE 0 15 8 These bits set the register that defines Data1 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 7 0 PM DATA SCALE 07 0 These bits set the register that defines DataO of the PM data value of the device fo
311. ed bit should be preserved across a read modify write operation 13 10 REG_DDRC_T_RCD 0x0 tRCD Minimum time from activate to READ or WRITE command to same bank specification 15 ns for DDR2 400 and lower for faster devices Unit clocks 9 7 REG_DDRC_T_CCD 0x0 tCCD Minimum time between two reads or two writes from bank A to bank B specification 2 cycles is this value 1 Unit clocks 6 4 REG_DDRC_T_RRD 0x0 tRRD Minimum time between activates from bank A to bank B specification 10 ns or less Unit clocks 3 0 REG_DDRC_T_RP 0x0 tRP Minimum time from precharge to activate of same bank Unit clocks DDRC_ODT_PARAM_1_CR Table 7 47 DDRC ODT PARAM 1 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 8 REG_DDRC_RD_ODT_DELAY 0x0 The delay in clock cycles from issuing a READ command to setting ODT values associated with that command Recommended value for DDR2 is CL 4 7 4 REG_DDRC_WR_ODT_DELAY 0x0 The delay in clock cycles from issuing a WRITE command to setting ODT values associated with that command The recommended value for DDR2 is CL 5 Where CL is CAS latency DDR ODT has a 2 cycle on time delay and a 2 5 cycle off time delay ODT setti
312. ed into read port and write port The read port queues read AXI transactions and it can hold up to four read transactions The read port assembles the data from the reorder buffer and puts it out on the read channel The write port stores the write transactions and generates the handshaking signals on the AXI channel The write port handles only one write instruction at a time 2 Priority Block The priority block prioritizes among the various instructions on the AXI channel and provides control to the transaction handler It also combines similar instructions read write for maximum performance The master from the FPGA fabric can be programmed to have a higher priority by configuring the DDRC_AXI_FABRIC_PRI_ID_CR register The priority level is also programmable it is required to specify whether the priority is even higher than Il cache DSG master requests The default priority scheme is in the following order Reads from the slave port of the MSS DDR bridge Reads from the slave port of the FPGA fabric Writes from the slave port of the MSS DDR bridge Writes from the slave port of the FPGA Fabric Po NS Revision 1 MDDR I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide After each access the priority block also checks whether the instruction from read slave port 0 contains pending instructions from the cache DSG bus If so the priority block switches back to read slave port 0 to execute t
313. edits 128 bytes plus headers and data credits consuming 1 credit each 16 bytes For example a core with four outstanding AXI slave read requests 1 VC and a maximum payload size of 256 bytes will have the RX buffer minimum memory requirements shown in Table 2 8 Table 2 8 Credit Calculation Type of Credit Memory Required VCO VC1 completion data payload 1 KB 4 x 128 bytes VCO posted header 16 credits 16 x 16 bytes VCO posted data payload 64 credits 64 x 16 bytes VCO non posted header 16 credits 16 x 16 bytes 78 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Receive Buffer Calculations The receive buffer levels on one side of a link have no relation to the receive buffer levels on the other side of a link The size of the receive buffer has a significant impact on system performance The receive buffer size calculation depends on the AXI interface cumulative MAX_PAYLOAD_SIZE in one transfer maximum length of AXI of 64 bit 16x8 and default credit settings The size of the receive buffer should be equal to or more than the RHS credit buffer requirement Receive buffer CPLD completion data PDVCO pd_cred0 PHVCO ph_cred0 NPHVCO nph credO EQ 1 For example A core with 4 outstanding read requests needs 128 x 4 512 bytes of space in the RX buffer to accommodate incoming completion packets 1 KByte One header credit each for posted and non
314. een 1 and 8 The possible MDDR_CLK M3 CLK ratios that meet the MSS DDR bridge requirements are 1 1 2 1 3 1 4 1 6 1 or 8 1 Configuring Dynamic DRAM Constraints Dynamic DRAM constraints may be subdivided into three basic categories Bank constraints affect the transactions that may be scheduled to a given bank e Rank constraints affect the transactions that may be scheduled to a given rank e Global constraints affect all transactions Dynamic DRAM Bank Constraints Bank state machines track the state of each bank and enforce the bank constraints There is one bank state machine for each bank supported by the system Using the bank state machines the scheduler dynamically obeys all of the following constraints on a per bank basis when scheduling transactions Table 7 8 Table 7 8 Dynamically Enforced Bank Constraints Constraint Control bit Abbreviation Constraint Name Constraint Meaning REG_DDRC_T_RC tRC Row Cycle time Minimum time between two successive activates to a given bank REG_DDRC_T_RP tRP Row Precharge Minimum time from a precharge command to the Command Period next command affecting that bank REG_DDRC_T_RAS_MIN tRAS min Min Bank Active Minimum time from an activate command to a Time precharge command to the same bank REG_DDRC_T_RAS_MAX tRAS max Max Bank Active Maximum time from an activate command to a Time precharge command to the same bank REG_DDRC_T_RCD tRCD RAS to CAS Delay
315. efault settings of the PHY which sets the reset value of the registers space For instance the following mapping is associated to a four lane PHY phy mode 3 0 Mode associated to laneO phy mode 7 4 Mode associated to lane1 phy_mode 11 8 Mode associated to lane2 phy_mode 15 12 Mode associated to lane3 PHY_MODE settings 4 b0000 PCIEe mode 4 b0001 XAUI mode 4 b0010 EPCS SGMII mode 4 b0011 EPCS 2 5 Ghz mode 4 b0100 EPCS 1 25 Ghz mode 4 b0101 EPCS undefined mode 4 b1111 SERDES PHY lane is off Reg28 CONFIG PHY MODE 1 Register 0x2028 Table 1 20 CONFIG PHY MODE 1 Bit Number Name Reset Value Description 11 8 CONFIG REG LANE SEL OxF Lane select This signal defines which lanes are accessed and must be one hot encoded for read transaction For write transaction one or several lanes can be written in the same time when several bits are asserted 7 4 CONFIG_LINKK2LANE OxF This signal is used in PCle mode in order to select the association of lane to link and must be one hot encoded each lane can be associated only to one link For example a four lane PHY which can be configured in 1 or 2 link might have e pipe Ik2In 3 0 lane associated to link 0 e pipe Ik2In 7 4 lane associated to link 1 Note It is mandatory that this signal is static at power up or Stable before reset de assertion 3 0 CONFIG_EPCS_SEL 0x0 For each lane
316. egister are used for the XAUI mode Table 3 4 shows the SERDESIF system registers which need to be configured for XAUI mode of operation Refer to the SERDESIF Block section on page 5 for detailed description of the register Table 3 4 e SERDESIF System Registers in EPCS Mode Address Register Register Name Offset Type Description SER_PLL_CONFIG_LOW 0x00 R W Sets SERDESIF PLL configuration bits LSBs SER_PLL_CONFIG_HIGH 0x04 R W Sets SERDESIF PLL configuration bits MSBs SER_SOFT_RESET 0x08 R W _ AIl 6 bits are used for soft reset Since PCIe IP is not used it is recommended to put IP into Reset state In the XAUI mode each SERDES lane needs to be put into Non Reset state as all four lanes are used in the XAUI mode SER INTERRUPT ENABLE 0x0C R W SERDES PLL lock interrupt enable CONFIG PHY MODE 0 0x24 R W For each lane this signal selects the protocol default settings of the PHY which will set the reset value of the registers space Refer to the CONFIG PHY MODE in Table 3 2 on page 132 for more information CONFIG PHY MODE 1 Ox 28 R W Selects PCS mode link to lane settings Refer to the CONFIG EPCS SEL in Table 3 2 on page 132 for detail CONFIG PHY MODE 2 0x2C R W Sets the equalization calibration It is performed by the PMA control logic of the lane or use the calibration result of adjacent lane SER_CLK_STATUS Ox4C R O This register describes the SERDES PLL and fabric PLL lock information
317. elastic buffer and an 8b 10b decoder as shown in Figure 5 6 i To T PCle CLK i Elastic Buffer aRXDo 19 0 Capture Word Register Aligner 20108 gt st CDR Clock Domain PCLK Clock Domain Figure 5 6 Receive Clock and Receive Datapath 176 The CLK Down block shuts down the receive clock when it is not stable and glitch free The CLK divider function on the RX path is very similar to the one on the transmit side The capture register is clocked directly by RXCLK output of clock divider rising edge which is a divide by and delayed version of the RX clock from the PMA hard macro The elastic buffers also known as elasticity buffers synchronization buffers and elastic stores are used to ensure data integrity when bridging two different clock domains Each receiver lane incorporates a 10b 8b Decoder which is fed from the Elastic Buffer The 8b 10b Decoder uses two lookup tables the D and K tables to decode the 10 bit symbol stream into 8 bit Data D or Control K characters plus the D K signal SERDES in External PCS Mode The SERDES block can be used in other modes other than PCIe For this purpose the SERDES block includes an external PCS ECPS interface that enables it to assign each implemented PHY lane to a different protocol The selection between the EPCS and the PCle PCS is performed by the CONFIG EPCS SEL register in the SERDESIF block enabling it to assign each implemented lane independently to PCle and
318. er s Guide PHY_WRLVL_DQ_RATIO_1_SR Table 7 181 PHY WRLVL DQ RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 15 0 bits of PHY_REG_WRLVL_DQ_RATIO Ratio value generated by the write leveling FSM for write data PHY_WRLVL_DQ_RATIO_2_SR Table 7 182 PHY WRLVL DQ RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 31 16 bits of PHY REG WRLVL DQ RATIO Ratio value generated by the write leveling FSM for write data PHY WRLVL DQ RATIO 3 SR Table 7 183 PHY WRLVL DQ RATIO 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQ_RATIO 0x0 47 32 bits of PHY_REG_WRLVL_DQ_RATIO Ratio value generated by the write leveling FSM for write
319. er EPCS interface The SERDESIF block can be configured to support single or multiple serial protocol modes of operation In multiple serial protocol mode two protocols can be implemented on the four physical lanes of the SERDESIF block The SERDESIF block is connected to the FPGA fabric through an AXI AHBL interface or EPCS interface Functional Description SmartFusion2 SoC FPGA devices have two hard high speed serial interface blocks SERDESIFO and SERDESIF1 These SERDESIF blocks interface with fabric program control and four SERDES differential I O pads The program control interface can not be accessed so it is not described in this chapter Figure 1 1 on page 6 shows the simplified view of the SmartFusion2 SoC FPGA SERDESIF block Depending on the protocol implemented the SERDESIF blocks allow AXI AHB APB EPCS interface to the fabric Each of these SERDESIF blocks instantiate the following blocks e SERDES This block implements the physical media attachment layer PMA and physical coding sub layer PCS of PCle protocols This PCS layer interface is compliant to the Intel PIPE 2 0 specification It also implements the PMA calibration and control logic The PCle PCS functionality can be bypassed completely in order to use the SERDES lanes for protocols other than PCle This allows to use the PMA in various PHY modes and implement various protocols in the SmartFusion2 SoC FPGA device Refer to the Serializer Deserializer section on page 16
320. er Name Value Description 31 12 AXI MASTER WINDOW21 31 12 Size of AXI master window 2 11 1 AXI MASTER WINDOW22 31 12 Reserved 0 AXI MASTER WINDOW 21 0 Enable bit of AXI master window 2 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide AXI MASTER WINDOWO 2 Register 128h Table 2 90 AXI MASTER WINDOW2 2 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW 22 31 12 LSB of base address PCle window 2 11 5 AXI MASTER WINDOW22 11 5 Reserved 5 0 AXI MASTER WINDOW 22 50 These bits set the BAR To select a BAR set the following values 0x01 BARO 32 bit BAR 0x02 BAR1 32 bit BAR 0x04 BAR2 32 bit BAR 0x08 BAR3 32 bit BAR 0x10 BAR4 32 bit BAR only only SI 22 oe wo or BARO 1 64 bit BAR or BAR2 3 64 bit BAR or BAR4 5 64 bit BAR 0x20 BARS 32 bit BAR only AXI_MASTER_WINDOW3 3 Register 12Ch Table 2 91 AXI MASTER WINDOW2 3 Bit Reset Number Name Value Description 31 0 AXI MASTER WINDOW23 31 12 MSB of base address PCle window 3 AXI MASTER WINDOW3 0 Register 130h Table 2 92 AXI MASTER WINDOW3 0 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW30 31 12 Base address AXI master window 3 11 0 Reserved Reserved AXI MASTER WINDOW3 1 Register 134h Table 2 93 AXI MASTER WINDOW 3 1 Bit Reset Number
321. erable write request Goes Low when the processor serves an interrupt and makes a clear bit for AHBL master Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 230 DDR FIC SW HPD WERR SR continued Bit Reset Number Name Value Description 7 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M2_WR_ERR 0x0 Status bit Goes High when error response is received for bufferable write request Goes Low when processor serves the interrupt DDR_LOCK_TIMEOUTVAL_1_CR Table 7 231 DDR LOCK TIMEOUTVAL 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 CFGR_LOCK_TIMEOUT_REG 0x0 15 0 bits of CFGR LOCK TIMEOUT REG Lock timeout 20 bit register Indicates maximum number of cycles a master can hold the bus for locked transfer If master holds the bus for locked transfer more than the required cycles an interrupt is generated DDR LOCK TIMEOUTVAL 2 CR Table 7 232 DDR LOCK TIMEOUTVAL 2 CR Bit Reset Number Name Val
322. erator in Libero SoC allows configuration of the SERDESIF block in reverse PCle mode Refer to Figure 2 8 Configuration Protocol Selection Protocol 1 Type Protocol 2 Type fire J Protocol 1 Number of Lanes x4 vi Protocol 2 Number of Lanes rl Protocol 1 Speed GEN 2 5 0 Gbps v Protocol 2 Speed Protocol 1 PHY Reference Clock 1 0 Port1 sd Protocol 2 PHY Reference Clock z Lane Assignment Protocol for Lane 0 Pae z Protocol for Lane 1 Pae z Protocol for Lane 2 P z Protocol for Lane 3 Pae z Figure 2 8 PCle Protocol Mode Setting in Reverse Lane Mode PCle Clocking Architecture The SmartFusion2 SoC FPGA SERDESIF when configured in PCle mode has multiple clock inputs and outputs This section describes the PCle clocking architecture SERDES Reference Clocks for PCle Mode The PMA in the SERDES block needs a reference clock on each of its lanes for TX and RX clock generation through PLLs For maximum flexibility the reference clock to the four lanes can come from REFCLK 100 or REFCLK 101 I O pads or from the internal FAB REF CLK or CCC_REF_CLK signals These two reference clocks REFCLK 100 and REFCLK 101 are connected to I O pads Figure 2 9 shows the reference clock selection aREFCLK 1 0 SERDES LANE23_REFCLK_SEL 1 0 Figure 2 9 e SERDES Reference Clock for PCle Mode Revision 1 71 I Microsemi PCI Express Figure 2 10 Figure 2 10 shows the reference clock selection in th
323. erring the requested read address to the DDR slave depending on its priority Combinations of fixed and round robin priorities are assigned to the masters as below e Master Interface 0 and Master Interface 1 have fixed 1st and 2nd priority Round robin between Master Interface 2 and Master Interface 3 for 2nd and 3rd priorities Re arbitration is performed at the end of every read address transaction The RAC also routes the read data from the slave MDDR or FDDR to the corresponding master based on the Read data ID A master requesting locked transactions is granted read and write access until the locked transfer is complete Locked Transactions Locked transactions are initiated only after all the posted write and read transactions receive the correct responses from the DDR slave Once a master requesting a locked transfer is granted the bus read and write access is granted until the locked transaction is completed After the last lock transfer a dummy write with all data strobes deasserted is initiated on the AXI bus to unlock the DDR slave from the master by completing the locked transaction The AXI controller resume normal operation after receiving the correct response from the DDR slave for dummy write transfer The arbiter has a 20 bit up counter for detecting a lock timeout condition The counter starts counting when a locked transaction is initiated on the bus When the counter reaches its maximum value an interrupt is generated to th
324. errors that occur while the controller is processing another scrub RMW When the controller detects an uncorrectable error it does the following e Generates an interrupt signal which can be monitored by reading the interrupt status register DDRC ECC INT SR The ECCINT interrupt is mapped to the groupO interrupt signal MSS_INT_M2F 12 of the fabric interface interrupt controller FIIC e Sends the data with error to the read requested MSS FPGA fabric master as part of the read data Send the SECDED error information to the DDRC_LUE_SYNDROME_1_SR register Monitoring SECDED Status 1 DDRC LUE ADDRESS 1 SR and DDRC LUE ADDRESS 2 SR give the row bank column information of the SECDED unrecoverable error 2 DDRC_LCE_ADDRESS_1_SR and DDRC_LCE_ADDRESS_2_SR give the row bank column information of the SECDED error correction 3 DDRC_LCB_NUMBER_SR indicates the location of the bit that caused the single bit error in the SECDED case encoded value 4 DDRC_ECC_INT_SR indicates whether the SECDED interrupt is because of a single bit error or double bit error The interrupt can be cleared by writing zeros to DDRC_ECC_INT_CLR_REG Restriction on Data Mask When SECDED Is Used Each SECDED lane in the DDR controller is 64 bits 8 bytes wide If SECDED is enabled the MSS master or FPGA fabric master can do a write operation if the write is 8 byte aligned If the granularity of the write is smaller than 8 bytes the controller issues a read modify
325. erved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 0 REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024 0x0 19 12 bits of REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024 Average interval to wait between automatically issuing ZQ calibration short ZQCS commands to DDR3 devices Not considered if REG_DDRC_DIS_AUTO_ZQ 1 Units 1 024 clock cycles This is only present for implementations supporting DDR3 devices 290 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_PERF_PARAM_1_CR Table 7 58 DDRC PERF PARAM 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 13 REG_DDRC_BURST_RDWR 0x0 1001 Burst length of 4 010 Burst length of 8 100 Burst length of 16 All other values are reserved This controls the burst size used to access the DRAM This must match the BL mode register setting in the DRAM The DDRC and AXI controllers are optimized for a burst length of 8 The recommended setting is 8 A burst length of 16 is only supported for LPDDR1 Setting to 16 when using LP
326. es the TX PLL charge pump current when the PMA is running in PCle Gen2 speed This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion Note This register can be programmed when the PHY is under reset and is implemented only if PCle Gen2 is supported by the PHY Revision 1 223 I Microsemi Serializer Deserializer GEN2_RX_PLL_CCP Register PCle Gen2 protocol only Table 5 123 GEN2 RX PLL CCP Bit Reset Number Name Value Description 7 Reserved 6 4 ARXCDRICP RATE1 2 0 This register defines the RX PLL charge pump current when the PMA is frequency locked and running in PCle Gen2 speed This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion 3 Reserved 2 0 ARXICP RATE1 2 0 This register defines the RX PLL charge pump current when the PMA is CDR locked and running in PCle Gen2 speed This register is R W in order to enable changing the default value by register programming which is expected to be performed before reset deassertion Note This register can be programmed when supported by the PHY CDR PLL MANUAL CR Register Table 5 124 CDR PLL MANUAL CR the PHY is under reset and is implemented only if PCle Gen2 is Bit Number Name Reset Value Description 7 3
327. escription 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 REG DDRC LPR MAX STARVE X32 0x0 11 1 bits of REG DDRC HPR MAX STARVE X32 Number of clocks that the LPR queue can be starved before it goes critical Unit 32 clocks DDRC WR QUEUE PARAM CR Table 7 63 DDRC WR QUEUE PARAM CR Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 4 REG_DDRC_W_MIN_NON_CRITICAL 0x0 Number of clocks that the write queue is guaranteed to be non critical Unit 32 clocks 3 0 REG_DDRC_W_XACT_RUN_LENGTH 0x0 Number of transactions that are serviced once the WR queue goes critical is the smaller of this value and number of transactions available Units Transactions Revision 1 293 I Microsemi MSS DDR Subsystem DDRC_PERF_PARAM_2_CR Table 7 64 DDRC PERF PARAM 2 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reser
328. eserved Reg44 CONFIG_BAR_SIZE_2_3 Register 0x2044 36 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 27 CONFIG BAR SIZE 2 3 Bit Number Name Reset Value Description 17 13 CONFIG BAR SIZE 3 0x0 These bits set the size of the BAR3 memory For example 32 bit BAR CONFIG_BAR_SIZE_3 5 d23 translates to BAR3 8MB 1111_1111_1000_0000_0000_0000_0000 CONFIG_BAR_CONTROL_3 12 9 CONFIG BAR CONTROL 3 0x0 3 0 LSB bits of BAR 3 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable non prefetchable memory 8 4 CONFIG BAR SIZE 2 0x0 These bits set the size of the BAR2 memory For example 32 bit BAR CONFIG_BAR_SIZE_2 5 d22 translates to BARO 4MB 1111_1111_1100_0000_0000_0000_0000_CONFIG_BAR_ CONTROL_2 3 0 CONFIG_BAR_CONTROL_2 0x0 3 0 LSB bits of BAR 2 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable Non prefetchable memory Revision 1 37 lt gt Microsemi SERDESIF Block Reg48 CONFIG_BAR_SIZE_4_5 Register 0x2048 Table 1 28 CONFIG BAR SIZE 4 5 Bit Number Name Reset Value Description 17 13 CONFIG BAR SIZE 5 0x0 These bits set the siz
329. eserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_DLL_LOCK_DIFF 0x0 The maximum number of delay line taps variations allowed while maintaining the master DLL lock This is calculated as total jitter delay line tap size Where total jitter is half of incoming clock jitter pp delay line jitter pp PHY_FIFO_WE_IN_DELAY_1_CR Table 7 120 PHY_FIFO_WE_IN_DELAY_1_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY FIFO WE IN DELAY 0x0 15 0 bits of REG PHY FIFO WE IN DELAY Delay value to be used when REG PHY FIFO WE IN FORCEX is set to 1 Revision 1 325 I Microsemi MSS DDR Subsystem PHY FIFO WE IN DELAY 2 CR Table 7 121 PHY FIFO WE IN DELAY 2 CR Bit Name Reset Description Number Value 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE_IN_DELAY 0x0 31 16 bits of REG_PHY_FIFO_WE_IN_DELAY Delay value to be used when REG PHY FIFO WE IN FOR
330. eserved bit should be preserved across a read modify write operation 11 3 REG_DDRC_POST_CKE_X1024 0x0 Cycles to wait after driving CKE High to start the DRAM initialization sequence Units 1 024 clocks DDR Typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds SDR Typically requires this to be programmed for a delay of 100 us to 200 us 1 0 REG_DDRC_PRE_CKE_X1024 0x0 9 0 bits of REG_DDRC_PRE_CKE_X1024 Cycles to wait after reset before driving CKE High to start the DRAM initialization sequence Units 1 024 clock cycles DDR2 specifications typically require this to be programmed for a delay of gt 200 us DDRC_INIT_MR_CR Table 7 35 DDRC INIT MR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_MR 0x095A Value to be loaded into the DRAM Mode register Bit 8 is for the DLL and the setting here is ignored The controller sets appropriately DDRC_INIT_EMR_CR Table 7 36 DDRC INIT EMR CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15
331. ess for a read request matches the flush address or the write buffer tag the read request is held until the buffer is flushed out completely to the AXI slave A flush request is generated on the following conditions 1 The WCB is full All bytes of the write buffer are valid The WCB times out The WCB is in write combining mode and the address received does not match the address tag A LOCK request is detected for a write read transfer from its own or other Master A read address match is found from its own or any other read buffers oa kw RN A non bufferable address is received from its own AHB master or from any other master 400 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide 7 AFlush command is issued 8 A DISABLE command is issued Once a Flush request is generated the WCB enters flush mode and writes to the write buffer are blocked Once a WCB exits flush mode it will start write combining data even though response is not received for the posted write request but it will not place the next write request until it receives the response for the posted write request To maintain data coherency the WCB compares every read access from all other masters to ensure whether they are held in the write buffer If an address match is found the read accesses are held until the write buffer is flushed out to the slave When any master initiates a non bufferable or a lock transfer a
332. ettings 0X190 PRBS_CTRL 0x00 RW PRBS control register 0X194 PRBS_ERRCNT 0x00 RO PRBS error counter register 0X198 PHY RESET OVERRIDE 0x00 RW PHY reset override register OX19C PHY_POWER_OVERRIDE 0x00 RW PHY power override register 0X190 CUSTOM PATTERN 7 0 0x00 RW Custom pattern byte 0 OX1A4 CUSTOM PATTERN 15 8 0x00 RW Custom pattern byte 1 OX1A8 CUSTOM_PATTERN_23_16 0x00 RW Custom pattern byte 2 OX1AC CUSTOM PATTERN 31 24 0x00 RW Custom pattern byte 3 OX1A0 CUSTOM PATTERN 39 32 0x00 RW Custom pattern byte 4 0X1B4 CUSTOM PATTERN 47 40 0x00 RW Custom pattern byte 6 0X1B8 CUSTOM PATTERN 55 48 0x00 RW Custom pattern byte 6 OX1BC CUSTOM_PATTERN_63_56 0x00 RW Custom pattern byte 7 OX1C0 CUSTOM PATTERN 71 64 0x00 RW Custom pattern byte 8 0X1C4 CUSTOM PATTERN 79 72 0x00 RW Custom pattern byte 9 0X1C8 CUSTOM PATTERN CTRL 0x00 RW Custom pattern control OX1CC CUSTOM PATTERN STATUS 0x00 RO Custom pattern status register 0X1D0 PCS_LOOPBBACK_CTRL 0x00 RW IPCS loopback control 0X1D4 GEN1 TX PLL CCP 0x00 RW Gen1 transmit PLL current charge pump 0X1D8 GEN1_RX_PLL_CCP 0x00 RW Gen1 receive PLL current charge pump OX1DC GEN2 TX PLL CCP 0x00 RW Gen2 receive PLL current charge pump OX1E0 GEN2_RX_PLL_CCP 0x00 RW Gen2 receive PLL current charge pump OX1E4 CDR PLL MANUAL CR 0x00 RW CDR PLL manual control Ox1E8 Reserved Ox1FC 0X200 UPDATE SETTINGS 0x00 WO Update settings command register 0X200 Reser
333. evision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDES Block Register The SERDES block registers are part of the SERDESIF register space There are three regions of configuration and status registers in the SERDESIF block Configuration of the top level functionality of the PCle core XAUI block and SERDES macro is also done through these registers These three regions of registers are as follows SERDESIF System Registers e PCle Core Bridge Register Space e SERDES Macro Registers The SERDES macro register contains the control and status information of SERDES for each lane Each SmartFusion2 SoC FPGA SERDES block has four SERDES lanes The location of SERDES macro registers in the SERDESIF system memory map are as follows e 0x1000 0x13FF 1 Kbyte SERDES macro register laneO e 0x1400 0x17FF 1 Kbyte SERDES macro register lane1 e 0x1800 0x1BFF 1 Kbyte SERDES macro register lane2 e 0x1C00 0x1FFF 1 Kbyte SERDES macro register lane3 The 1 Kbyte register space can be divided between the protocol specific read write register and generic purpose register e Configuration PHY registers offset 0x000 to 0x03C These 16 registers are protocol specific with a reset value depending on the selected protocol according to CONFIG_PHY_MODE register settings For example PLL_F_PCLK_RATIO register may have different reset values for PCle and XAUI mode Also note that for PCle Ge
334. f a reserved bit should be preserved across a read modify write operation 12 6 REG DDRC POST SELFREF GAP X32 0x10 Minimum time to wait after coming out of self refresh before doing anything This must be larger than all the constraints that exist specifications maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks Unit Multiples of 32 clocks 5 1 REG DDRC POWERDOWN TO X32 0x06 After this many clocks of NOP or DESELECT the controller puts the DRAM into power down This must be enabled in the Master Control register Unit Multiples of 32 clocks 0 REG_DDRC_CLOCK_STOP_EN 0x0 1 Stops the clock to the PHY whenever a clock is not required by LPDDR1 0 Clock will never be stopped This is only present for implementations supporting mobile LPDDR1 devices DDRC_PWR_SAVE_2_CR Table 7 53 DDRC PWR SAVE 2 CR Bit Reset Number Name Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 11 REG_DDRC_DIS_PAD_PD 0x0 1 Disable the pad power down feature 0 Enable the pad power down feature Used only in non DFI designs 288 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 53 DDRC_PWR_SAVE_2_CR continued Bit Reset Number Name Value Description 10 3 REG_DDRC_DEEPPOWERDOWN_TO_X
335. f the read transaction store Setting this to maximum value allocates all entries to low priority transaction store Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store Revision 1 291 I Microsemi MSS DDR Subsystem DDRC_HPR_QUEUE_PARAM_1_CR Table 7 59 DDRC HPR QUEUE PARAM 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 REG_DDRC_HPR_MAX_STARVE_X32 0x0 Lower 1 bit of REG_DDRC_HPR_MAX_STARVE_X32 Number of clocks that the HPR queue can be starved before it goes critical Unit 32 clocks 14 4 REG_DDRC_HPR_MIN_NON_CRITICAL 0x0 Number of clocks that the HPR queue is guaranteed to be non critical Unit 32 clocks 3 0 REG_DDRC_HPR_XACT_RUN_LENGTH 0x0 Number of transactions that are serviced once the HPR queue goes critical is the smaller of this value and number of transactions available Units Transactions DDRC_HPR_QUEUE_PARAM_2_CR Table 7 60 DDRC HPR QUEUE PARAM 2 CR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit shoul
336. face and EPCS External PCS It has a Ten Bit transmit receive interface on TBI side and 20 bit transmit receive interface on EPCS side It will receive TBI data from MAC block and transmit it towards the EPCS It will also receive EPCS data and transmit it towards TBI In Multi protocol mode laneO and lane1 of the SERDESIF block can be used for the PCle protocol Table 1 4 shows the various options available for implementing SGMII in the SERDESIF block SERDESIF SERDES Block V O PADS SERDES X2 EPCS Interface PMA only SERDESIF System Register EPCS Lane 3 only APB Slave Interface CoreTBItoEPCS FABRIC Ethernet MAC with TBI Interface Figure 1 6 SERDESIF Configuration for SGMII Protocol Revision 1 13 I Microsemi SERDESIF Block Table 1 4 shows the various options for implementing SGMII protocol Table 1 4 Various Options for Implementing SGMII in the SERDESIF Block LaneOd Lane1 Lane2 Lane3 Speed Speed Speed Speed bits per bits per bits per bits per SGMII Protocol Protocol second Protocol second Protocol second Protocol second Single Protocol PHY mode SGMII 1 25G Multi Protocol PHY mode PCle 256 SGMII 1 25G PCIe Link Non Reversed mode pe 25G Pele 256 sGMII 1256 PCIe 5G SGMII 1 25G PCle 5G PCle 5G SGMII 1 25G Multi Protocol PHY mode
337. face asynchronous preset Note 1 b0 means logic 0 Configuration of SERDESIF The SERDESIF block has three regions of configuration and status registers Configuration of the SERDESIF is done through these registers Configuration of top level functionality of the PCle core XAUI block and SERDES macro is also done through these registers Figure 1 14 on page 26 shows the memory map for the SERDESIF block The three regions of configuration and status registers are described below SERDESIF System Register The SERDESIF system register controls the SERDESIF module for single protocol or multi protocol support implementation It occupies 1 KB of the configuration memory map The physical offset location of the SERDESIF system register is 0x2000 0x23FF from the SERDESIF subsystem memory map These registers can be accessed through the 32 bit APB interface and the default values of these registers can be configured using Libero SoC These registers are set while configuring the high speed serial interface generator in Libero SoC However the SERDESIF system registers can be updated through the 32 bit APB interface if required PCle Core Bridge Register The PCle core bridge registers occupy 4 KB of the configuration memory map These registers set the PCle configuration and status These registers are set while configuring the high speed serial interface generator in Libero SoC These registers can also be accessed through the 3
338. g FSM when the REG_PHY_WRLVL_INIT_MODE PORT is set to 1 The recommended setting of REG_PHY_WRLVL_INIT_RATIO is a half cycle less than the total skew between CLK and DQS at the DRAM Revision 1 341 I Microsemi MSS DDR Subsystem PHY_WR_RD_RL_CR Table 7 164 PHY_WR_RD_RL_CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 _ Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG_PHY_WR_RL_DELAY 0x0 _ This delay determines when to select the active rank s ratio logic delay for write data and write DQS slave delay lines after PHY receives a write command at the control interface This is only used for multi rank designs when REG PHY USE RANKO DELAYS 0 This must be programmed as Write Latency 4 with a minimum value of 1 4 0 REG_PHY_RD_RL_DELAY 0x0 This delay determines when to select the active rank s ratio logic delay for FIFO_WE and read DQS slave delay lines after PHY receives a read command at the control interface This is only used for multi rank designs when REG PHY USE RANKO DELAYS 0 PHY DYN RDC FIFO RST ERR CNT CLR CR Table 7 165 PHY DYN RDC FIFO RST ERR CNT CLR CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on
339. g sequence is given below 1 Write leveling 2 Read leveling DQS gate training Data eye training Read leveling and write leveling apply only for DDR3 memories Write Leveling The write leveling process locates the delay at which the write DQS rising edge aligns with the rising edge of the memory clock By identifying this delay the system can accurately align the write DQS within the memory clock The DDRC drives subsequent write strobes for every write to write delay specified by REG DDRC WRLVL WW until the PHY drives the response signal High The DDR controller performs the below steps Sets up the SDRAM in write leveling mode by sending the appropriate MR1 command 2 Sets the write leveling enable bit for the PHY and sends out periodically timed write level strobes to the PHY while sending out DEVSEL commands on the SDDRAM command interface 3 Once the PHY completes its measurements it sets the write level response bits which then signal the DDRC to stop the leveling process and lower the write leveling enable bit Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Read Leveling There are two read leveling modes 1 DQS gate training The purpose of gate training is to locate the optimum delay that can be applied to the DQS gate such that it functions properly 2 Data eye training The goal of data eye training is to identify the delay at which the read DQ
340. g10 10G PHY DTE XGXS Lane Status Bit Reset Number Name Value Description 15 13 Reserved 12 PHY DTE XGXS lane 0x0 1 b0 Lanes not aligned alignment status 1 b1 Lanes aligned 11 Pattern testing ability Ox1 1 b0 PHY DTE XS is unable to generate test patterns 1 b1 PHY DTE XS is able to generate test patterns 10 PHY XGXS loopback Ox1 1 b0 PHY XGXS does not has the ability to perform a loopback ability 1 b1 PHY XGXS has the ability to perform a loopback 9 4 Reserved 3 Lane3 synced 0x0 When read as a one this register indicates that the receive Lane3 is synchronized 1 b0 Lane3 is not synced 1 b1 Lane3 is synced 2 Lane2 synced 0x0 When read as a one this register indicates that the receive Lane2 is synchronized 1 b0 Lane2 is not synced 1 b1 Lane2 is synced Revision 1 145 lt gt Microsemi XAUI Table 3 17 Depicts Definition of XGXS Lane Status Register Reg10 10G PHY DTE XGXS Lane Status Bit Reset Number Name Value Description 1 Lane1 synced 0x0 When read as a one this register indicates that the receive Lane1 is synchronized 1 b0 Lane1 is not synced 1 b1 Lane1 is synced 0 LaneO synced 0x0 When read as a one this register indicates that the receive Lane is synchronized 1 b0 LaneO is not synced 1 b1 LaneO is synced Table 3 18 Depicts Definition of XGXS Test Control Register Reg11 10G PHY DTE XGXS Test Control
341. ge must perform a write transaction any value to the register Power Management Registers The registers listed in Table 2 11 enable to configure the power management capabilities of the bridge Table 2 12 Bridge Configuration Registers Byte Register Offset Description LTSSM 044h R W or RO This register can be used to monitor the core state or to select a specific test mode on bits 31 16 and to control L2 entry on bits 15 0 POWER MGT CAPABILITY 010h R W or RO The power management capability register enables the local processor to configure power management capability PM DATA SCALE 0 070h R W or RO There are four PM data and scale registers that define the PM data value of the device for each possible power state EM DATA SOALEN AN RTR defined by the PCI power management specification used in PM DATA SCALE 2 078h R W or RO conjunction with the PM scale field PM DATA SCALE 3 07Ch R W or RO Revision 1 85 I Microsemi PCI Express Table 2 12 Bridge Configuration Registers continued Byte Register Offset Description ASPM_LOS_CAPABILITY 060h R W or RO This register defines the endpoint LOs acceptable latency and the number of fast training sequences FTS required by the SERDES to resynchronize its receiver on incoming data depending on clock mode configuration separated clock or common clock The number of FTS required in separated clock mode must be higher than that required in common clock m
342. gister implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX AMP RATIO MARGIN6 HALF Register Table 5 49 TX AMP RATIO MARGIN6 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN6 HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden Revision 1 203 I Microsemi Serializer Deserializer TX_AMP_RATIO_MARGIN7_HALF Register Table 5 50 TX AMP RATIO MARGIN7 HALF Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN7 HALF This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden PMA STATUS Register Table 5 51 PMA STATUS Bit Reset Number Name Value Description 7 PMA RDY This register defines whether the PMA has completed its internal calibration sequence after power up and PHY reset deassertion 5 4 ASCH ERR 1 0 This register defines whether Schmitt offset calibration has reached a min bit0 max bit1 value If any min max value is detected the calibration logic will apply the min max value but the offset can
343. glue logic L2 P2 control Logic This block controls logic to implement the L2 P2 state The PCle System supports the following features and limitations e Supports 4 master read requests and 4 write requests Supports 4 outstanding slave read requests and 4 write requests e Supports optional ERC generation and checking Supports all memory configuration and message transactions e Supports no write data interleaving for AXI interface e No support for I O or locked transactions e Supports only incremental address bursts for the AXI slave and burst Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDESIF System Registers for PCle Mode Three SERDESIF system registers must be configured to implement PCle mode The three registers that define the mode of operation of the SmartFusion2 SoC FPGA SERDESIF module are as follows 1 CONFIG PHY MODE 2 CONFIG EPCS SEL 3 CONFIG_LINKK2LANE Table 2 4 gives the settings for the SERDESIF registers in PCle mode Table 2 4 PCle Mode Settings Using the SERDESIF System Register SERDESIF System APB Registers Description CONFIG PHY MODE 15 12 For each lane this signal selects the protocol default settings which will set the reset value of the register space CONFIG PHY MODE 15 12 Defines lanelane3 settings 4 b0000 PCIe mode lane3 4 b0001 XAUI mode lane3 400010 EPCS SGMII5 mode lane3 4 b0011 EPCS 2 5 G
344. gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Reg58 SER_INTERRUPT Register 0x2058 Table 1 32 SER INTERRUPT Bit Number Name Reset Value Description 1 PLL_LOCK_INT 0x0 SPLL FPLL lock interrupt output 0 PLL_LOCKLOST_INT 0x0 SPLL FPLL lock lost interrupt output Reg5C SERDESIF_INTR_STATUS Register 0x205C Table 1 33 SERDESIF INTR STATUS Bit Number Name Reset Value Description 2 0 SERDESIF INTR STATUS 0x0 ECC interrupt status for PCle memories Reg60 Reserved 0x2060 Table 1 34 Reg60 Bit Number Name Reset Value Description 0x0 Note All the register are 32 bit Bits not shown in the table are reserved Revision 1 39 I Microsemi SERDESIF Block Reg64 REFCLK_SEL Register 0x2064 Table 1 35 REFCLK SEL Bit Reset Number Name Value Description 3 2 LANE23 REFCLK SEL 0x0 Reference clock selection for lane2 and lane3 of PMA 00 Selects refcik io0 clock for laneO and lane1 as reference clock 01 Selects refclk_io1 clock for laneO and lane1 as reference clock 10 Selects ccc_ref_clk clock for laneO and lane1 as reference clock 11 Selects fab_ref_clk clock for laneO and lane as reference clock 1 0 LANE01_REFCLK_SEL 0x0 Reference clock selection for laneO and lane1 of PMA 00 Selects refcik io0 clock for laneO and lane1 as reference clock 01 Selects refclk_io1 clock fo
345. h a 64 bit width E Configuring SERDES_IF_0 SERDES_IF 0 0 501 PCIe Base Address Registers a BARO Width 32bit Size 4Ke x Type Memory v Prefetchable F N BAR 1 Width em see wef Prefetchable I BAR 2 Width None v see ef J Prefetchable 7 BAR 3 Width None v sef we z Prefetchable I BAR 4 Width None v Size Type 3 Prefetchable I BARS Width None v Size O H Type 3 Prefetchable I Figure 2 15 BAR Settings in High Speed Serial Interface Generator Revision 1 75 I Microsemi PCI Express Address Translation on the AXI Master Interface The address space for PCle is different from the AXI address space To access one address space from another address space requires an address translation process The PCle IP can receive both 32 bit address and 64 bit address PCle requests but only 32 bit address bits are provided to the AXI master In order to manage address translation the PCle IP can implement up to 4 AXI master address windows which can be mapped to 3 BARs in the main PCle IP core Each AXI master address window implemented can be mapped to a BAR and several address windows can be mapped to the same BAR When transferring PCle receive requests to the AXI Master the PCle IP automatically removes the decoded BAR base address then performs a windows match using the PCle offset address If a match is found the bridge then maps the corresponding AXI base address For ex
346. hannel capability structure 100h 16Ch Reserved 170h 17Ch VC arbitration table 180h 1FCh Port VCO arbitration table reserved 200h 23Ch Reserved 400h 7FCh AER 800h 834h Revision 1 123 I Microsemi PCI Express Type 0 Configuration Settings Table 2 133 shows the type 0 configuration settings Table 2 133 Type 0 Configuration Register 31 24 23 16 15 8 7 0 Byte Offset Device ID Vendor ID 000h Status Command 004h Class Code Revision ID 008h BIST Header Type Latency Timer Cache Line Size 00Ch Base address 0 010h Base address 1 014h Base address 2 018h Base address 3 01Ch Base address 4 020h Base address 5 024h 028h Subsystem ID Subsystem Vendor ID 02Ch Expansion ROM base address 030h Capabilities PTR 034h 038h Int pin Int line 03Ch IP Core Status Register Table 2 134 illustrates the content of the IP Core Status Register Table 2 134 IP Core Status Register 31 28 27 16 15 4 3 0 Reserved Core version PLDA signature Reserved MSI Capability Structure Table 2 135 illustrates the content of the MSI capability structure Table 2 135 MSI Capability Structure Register 31 24 23 16 15 8 7 0 Byte Offset Message control Next pointer Cap ID 050h Message address 054h Message upper address 058h 0001 Message data osch 124 Revision 1 lt gt Microsemi
347. harge to same bank specifications WL BL 2 tWR approximately 8 cycles 15 ns 14 clocks 400 MHz and less for lower frequencies Unit Clocks where WL Write latency BL Burst length This must match the value programmed in the BL bit of the mode register to the DRAM tWR Write recovery time This comes directly from the DRAM specs 4 0 REG_DDRC_RD2PRE 0x0 tRTP Minimum time from read to precharge of same bank specification tRTP for BL 4 and tRTP 2 for BL 8 tRTP 7 5 ns Unit clocks Revision 1 281 I Microsemi MSS DDR Subsystem Table 7 42 e DDRC DRAM MR TIMING PARAM CR DDRC DRAM MR TIMING PARAM CR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 3 REG_DDRC_T_MOD 0x0 Present for DDR3 only replaces REG_DDRC_T_MRD functionality when used with DDR3 devices The mode register set command updates delay in number of clock cycles This is required to be programmed even when a design that supports DDR3 is running in DDR2 mode minimum is the larger of 12 clock cycles or 15 ns 2 0 REG_DDRC_T_MRD 0x0 tMRD Cycles between load mode commands Not used in DDR3 mode Table 7 43 DDRC_DRAM_RAS_TIMING_CR DD
348. has no effect after calibration is completed PMA is ready or if the PHY CDR PLL is used in PMA driven mode Reg19 Register Table 5 22 Reg19 Bit Reset Number Name Value Description 7 0 Reserved 7 0 This register is reserved for future use Note For Reg20 to Reg31 These registers can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated on entry or exit of TX electrical idle I or when Reg128 is programmed or when any of the PIPE TXSwing TXDeemp or TXMargin signals is modified X PST RATIO DEEMPO FULL Register Table 5 23 TX PST RATIO DEEMPO FULL Bit Reset Number Name Value Description 7 0 TX PST RATIO DEEMPO FULL This register defines the TX post cursor ratio for Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 A value of 3 5dB corresponds to 8 d21 encoding TX PRE RATIO DEEMPO FULL Register Table 5 24 TX PRE RATIO DEEMPO FULL Bit Reset Number Name Value Description 7 0 TX PRE RATIO DEEMPO FULL This register defines the TX pre cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Revision 1 197 I Microsemi Ser
349. hat before transferring the transaction to the AXI master read channel the PCle IP checks for available space on the transmit buffer If there is not sufficient space in the transmit buffer to store PCle completions the PCle IP does not transfer the read transaction The number of outstanding AXI master read transactions is therefore limited by the size of the TX buffer This is configurable in the core between 2 512 B TX buffer 4 1 KB TX buffer and 8 2 KB TX buffer outstanding requests The AXI master read channel can receive transactions in any order and data can be completely interleaved However the PCle IP generates completions in the order they are initiated on the link AXI Slave Block The AXI slave interface forwards AXI read and write requests to the PCIe link Write Transaction Handling Write transactions are only accepted if at least 128 bytes of buffer space is available in the transmit buffer Because AXI does not support write data interleaving the PCIe IP stores all write requests inside the transmit buffer to avoid the insertion of wait states before initiating PCle transactions Wait states are only asserted for write requests if no additional outstanding requests can be stored in the buffer The PCle IP then waits for the last data phase before arbitrating between read requests and completions and checking for FC credits availability on the decoded VC Write responses are generated as soon as the last data phase occurs
350. hat reports the following error source AB Completer abort error 23 16 ERROR COUNTER2 23 16 Eight bit counter that reports the following error source AA Completion timeout error 115 8 ERROR COUNTER2 15 8 Eight bit counter that reports the following error source A9 Unsupported request error 7 0 ERROR COUNTER2 7 0 Eight bit counter that reports the following error source A8 ECRC error ERROR COUNTER 3 Register 0ACh Table 2 59 ERROR COUNTER 3 Bit Reset Number Name Value Description 31 14 ERROR COUNTER3 31 24 Eight bit counter that reports the following error source AF Malformed TLP error 23 16 ERROR COUNTER3 23 16 Eight bit counter that reports the following error source AE Flow control protocol error 15 8 ERROR COUNTER3 15 8 Eight bit counter that reports the following error source AD Receiver overflow error 7 0 ERROR_COUNTER3_7_0 Eight bit counter that reports the following error source AC Unexpected completion error REDIT ALLOCATION 0 Register Table 2 60 CREDIT ALLOCATION 0 Bit Reset Number Name Value Description 31 28 CREDIT ALLOCATIONO 31 28 Reserved 27 16 CREDIT ALLOCATIONO 27 16 VCO posted header data credit pd credO 15 8 CREDIT ALLOCATIONO 15 8 Reserved 7 0 CREDIT ALLOCATIONO 7 0 VCO posted header data credit ph credO 104 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s
351. he MSS DDR bridge to read or write the data into the memory ARM Cortex M3 Microcontroller SD l Cache Transaction Controller Controller AHB Bus Matrix AHB to APB Bridge SPI x 2 MMUART x 2 FPGA Fabric Figure 7 9 Accessing MDDR from AHB Bus Matrix 258 Register Configuration Path The MDDR subsystem registers can be configured through the MSS master or the FPGA fabric master The selection of APB master can be done by configuring APB 2 in Libero SoC For more details about APB 2 refer to the APB Configuration Interface chapter in the ARM Cortex M3 Processor and Subsystem in SmartFusion2 SoC FPGA Devices User s Guide Refer to the APB Configuration Interface Configurator User s Guide to be released for information on configuring the registers for the MSS master or FPGA fabric master Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide MDDR Memory Map The address map for MDDR is OxA0000000 0xDFFFFFFF The MDDR can support up to 4 GB of memory but only 1 GB of this memory is accessible at a time from the Cortex M3 or MSS masters via the AHB bus matrix The HPDMA and DDR FIC can access all 4 GB of memory at default settings The 4 GB address space 0x00000000 0xFFFFFFFF of DDR memory is divided into sixteen DDR regions 0 15 as shown in Table 7 13 In order to make a particular region of DDR visible to Cortex M3 firmware or another non HPDMA MSS ma
352. he value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 REG_DDRC_MR_WR 0x0 When 1 is written and DDRC_REG_MR_WR_BUSY is Low a mode register read or write operation is started There is no need for the CPU to set this back to zero This bit always reads as zero Controller accepts this command if this signal is detected High and DDRC_REG_MR_WR_BUSY is detected Low 2 1 REG_DDRC_MR_ADDR 0x0 Address of the Mode register that is to be written to 00 MRO 01 MR1 10 MR2 11 MR3 0 REG_DDRC_MR_TYPE 0x0 Indicates whether the Mode register operation is read or write 1 Read 0 Write DDRC_MODE_REG_DATA_CR Table 7 51 DDRC_MODE_REG_DATA_CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_DDRC_MR_DATA 0x0 Mode register write data Revision 1 287 I Microsemi MSS DDR Subsystem DDRC_PWR_SAVE_1_CR Table 7 52 e DDRC PWR SAVE 1 CR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value o
353. hese instructions The priority transactions are ordered as follows 1 cache Highest priority 2 DSG master Second highest priority 3 Fabric master Third highest priority if PRIORITY_ID 0 3 Transaction Handler The transaction handler converts AXI transactions into appropriate transactions for the DDR controller It will convert one AXI transaction into multiple DDR controller transactions depending on the size of the AXI transaction The transaction handler works on one transaction at a time from the read write port queue that is selected by the priority block The transaction handler has a write command controller and read command controller for write and read transactions The write command controller fetches the command from the AXI slave write port and sends RMW or a pure write instruction to the DDR controller depending on the write command If SECDED is enabled the write command controller converts each partial write transaction less than 64 bits to a read modified write transaction The read command controller generates appropriately sized read transactions for the DDR controller The number of transactions associated with each command is computed and dispatched to the DDR controller The priority block gives control to the read command controller if any read requests are available 4 Reorder Buffer The reorder buffer receives data from the DDR controller and reorders it because data could be returne
354. his block XAUI Extender Block This section describes the functionality and interfaces of the XAUI extender sub block in SERDESIF for the XGMII This block implements e IEEE 802 3ae clauses 47and 48 mandatory and optional features This function is located between the reconciliation sublayer RS and the PCS IEEE 802 3ae clause 45 to provide control and status through the MDIO interface The main features of the module are e Full compliance with IEEE 802 3 IEEE 802 3ae clause 45 MDIO interface IEEE 802 3ae clause 48 state machines e IEEE 802 3ae annex 48A jitter test pattern support IEEE 802 3 clause 36 8B 10B encoding compliance IEEE 802 3 PICs compliance matrix e Pseudorandom idle insertion PRBS Polynomial XT X34 1 e Clock frequency of 156 25 MHz e Double width single data rate SDR XGMII interface 156 25 MHz Low power mode PHY XS and DTE XS loopback Tolerance of lane skew up to 16ns 50 Ul XAUI Extender Block Functional Overview Figure 3 2 on page 131 shows the XAUI extender sub block This module is connected to the SERDES PMA block through two x2 EPCS interface 2 twox2 EPCS interface x4 EPCS interface blocks and to the FPGA fabric via an XGMII interface There are three major blocks e Transmit block This block is responsible for encoding the XGMII data using 8B 10B The output to the transmit block is an 80 bit interface 20 bits per lane The PMA in the SERDES receive
355. i SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PLL_F_PCLK_RATIO Table 5 7 PLL F PCLK RATIO Bit Reset Number Name Value Description 7 6 Reserved 5 4 DIV MODEO This register defines the ratio between PCLK and aTXClk PCLK is used by the PCle PCS logic as well as by the majority of the PMA control logic and thus is also useful for other protocols in order to reduce the amount of logic requiring a high aTXClk frequency In non PCle mode this register is only useful if pipe_pclkout is used by any logic A value of 00 is used for divide by 1 10 for divide by 2 and 11 for divide by 4 3 0 F This register defines the aRXF 3 0 and aTXF 3 0 settings of the PMA macro The same F value is applied to both RX and TX PLL Note This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under reset PLL_M_N Register Table 5 8 PLL M N Bit Reset Number Name Value Description 7 CNT250NS_MAX 8 This bit is concatenated to the Reg06 register as an MSB to define the 250 ns base time 5 4 M 1 0 This register defines the TX PLL M values and CDR PLL M value settings of the PMA macro For PCIe it corresponds to the Gen1 settings The same M value is applied to both RX and TX PLL 3 0 N 4 0 This register defines the TX PLL N values and CDR PLL N value settings of the PMA macro For PCle it corresponds to the Gen1 settings The
356. ializer Deserializer TX_PST_RATIO_DEEMP1_FULL Register Table 5 25 TX PST RATIO DEEMP1 FULL Bit Reset Number Name Value Description 7 0 TX PST RATIO DEEMP1 FULL This register defines the TX post cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 A value of 3 5dB corresponds to 8 d21 encoding TX_PRE_RATIO_DEEMP1_FULL Register Table 5 26 TX PRE RATIO DEEMP1 FULL Bit Reset Number Name Value Description 7 0 TX PRE RATIO DEEMP1 FULL This register defines the TX pre cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 TX AMP RATIO MARGINO FULL Register Table 5 27 TX AMP RATIO MARGINO FULL Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGINO FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN1_FULL Register Table 5 28 TX AMP RATIO MARGIN1 FULL Bit Reset Number Name Value Description 7 0 TX AMP RATIO MARGIN1 FULL This register implements the TX amplitude ratio used by the TX dri
357. ibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_DLL_SLAVE_VALUE 0x0 15 0 bits of PHY_REG_STATUS_DLL_SLAVE_VALUE Shows the current coarse and fine delay values measured for a full cycle shift by each master DLL This is a 27 bit register 9 bits for each DLL 1 0 Fine value 8 2 Coarse value PHY_DLL_SLAVE_VALUE_2_SR Table 7 195 PHY DLL SLAVE VALUE 2 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_DLL_SLAVE_VALUE 0x0 26 16 bits of PHY_REG_STATUS_DLL_SLAVE_VALUE Shows the current coarse and fine delay values measured for a full cycle shift by each master DLL This is a 27 bit register 9 bits for each DLL 1 0 Fine value 8 2 Coarse value Revision 1 353 I Microsemi MSS DDR Subsystem Table 7 196 PHY_STATUS_OF_IN_DELAY_VAL_1_SR PHY_STATUS_OF_IN_DELAY_VAL_1_SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operati
358. ic PHY_RESET_N In Active low SERDES reset Fabric If not used for any serial protocol should be tied 0 APB S PRESET N In APB slave interface PRESETN Async set Fabric 120 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 2 129 SmartFusion2 SoC FPGA PCIe I O PAD Interface Table 2 130 PCle Interrupt and Power Management Interface Connecte Port Name Type d to Description PCIE x RXDPO Input I O Pads Receive data SERDES differential positive input each SERDESIF PCIE x RXDP1 consists of 4 RX signals Here x 0 for SERDESIF 0 and x 1 for PCIE x RXDP2 SERDESIF 1 If unused can be left floating PCIE x RXDP3 PCIE x RXDNO Input I O Pads Receive data SERDES differential negative input PCIE x RXDN1 Each SERDESIF consists of 4 RX signals Here x 0 for PCIE x RXDN2 SERDESIF 9 and x 1 for SERDESIF 1 If unused can be left floating PCIE x RXDN3 PCIE x TXDPO Output I O Pads Transmit data SERDES differential positive output PCIE x TXDP1 Each SERDESIF consists of 4 TX signals Here x 0 for PCIE x TXDP2 SERDESIF_0 and x 1 for SERDESIF_1 If unused can be left LU 77 floating PCIE x TXDP3 PCIE x TXDNO Output I O Pads Transmit data SERDES differential negative output PCIE x TXDN1 Each SERDESIF consists of 4 TX Signals Here x 0 for PCIE x TXDN2 S
359. igned to the bitstream if all of the following are true e Reference clock is initially present and at the correct frequency M N and F are correctly set TX PLL is on at correct frequency and TX clock is present PMA controlled mode Serial bitstream is present and valid e Deserializer circuitry is on e Receivers are on Refer to the TX PLL and CDR PLL Operation section on page 177 for more information on using the TX and CDR PLL Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Physical Coding Sublayer Block The PCS block implements 8b 10b encoder decoder RX detection and elastic buffer for the PCle protocol It has transmitter and receiver blocks Transmitter Block The Transmitter block consists of an 8b 10b encoder and a phase matching first in first out FIFO as shown in Figure 5 5 The transmitter block passes the input data in the PCLK domain PIPE clock domain to the PMA hard macro in the TX clock domain PIPE Interface To PCle PIPE_PCLKOUT System CLK Divider CLK MUX i aTXClkp aTXClk TXDP PIPE_PCLKIN TXDN i Phase I Matching aRefClk FIFO 8b 10b i TX Clock Domain PCLK Clock Domain Txdata0 TxdatakO Figure 5 5 Transmit Clock and Transmit Datapath The reference clock aRefClk is the per lane PCle reference clock which is generally the PCle 100 MHz reference clock During multiple lane implementations
360. igured in full bus width mode with SECDED enabled The SDRAM connected to MDDR DQ 33 32 is used to store SECDED bits The total amount of LPDDR1 memory excluding memory for SECDED connected to MDDR is 64 MB MDDR_PADS MT46H32M16LF ee pies MDDR_CKE CKE HEG ae MDDR CLK CLK_N CSN ODT RASN WEN MDDR ADDR 12 0 ADDR 12 0 MDDR BALTO Lu TT BA 2 0 MDDR DM RDQS 1 0 PITT TTT TN UDM LDM MDDR DQS 0 Eee Je LDQS MDDR DQS 1 eee MDDR DQ 15 0 MDDR DM RDQS 1 MDDR DQS 2 MDDR DQ 33 32 Figure 7 12 x16 LPDR1SDRAM Connection to MDDR 264 Revision 1 DYRE UDQS i ss MT46H32M16LF CASN CKE CLK P CLK_N CSN ODT RASN WEN ADDR 12 0 BA 2 0 LDM LDQS DQ 1 0 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Register Interface Table 7 17 lists the registers visible on the DDR APB interface The base address is 0x40020000 Table 7 17 Address Table for Register Interfaces Registers DDR Controller Configuration Register Address Offset Space 0x000 0x1FC PHY Configuration Register Summary 0x200 0x3FC DDR_FIC Configuration Register Summary 0x400 0x4FC Reserved 0x500 0x7FC SYSREG Configuration Register Summary Table 7 18 e SYSREG Configuration Register Summary Register Flash er Register Name ae Reset Source Description MDDR_CR RW P Register
361. ime Calibration register DDRC_ZQ_SHORT_TIME_CR 0x090 RW PRESET_N DDRC ZQ Short Time Calibration register DDRC ZQ SHORT INT REFRESH MARGIN 1 CR 0x094 RW PRESET_N DDRC ZQ Short Time Calibration register DDRC ZQ SHORT INT REFRESH MARGIN 2 CR 0x098 RW PRESET_N DDRC ZQ Short Time Calibration register DDRC PERF PARAM 1 CR 0x09C RW PRESET_N DDRC Performance Parameter register DDRC HPR QUEUE PARAM 1 CR OxOAO RW PRESET_N DDRC Performance Parameter register DDRC HPR QUEUE PARAM 2 CR Ox0A4 RW PRESET_N DDRC Performance Parameter register DDRC_LPR_QUEUE_PARAM_1_CR 0x0A8 RW PRESET_N DDRC Performance Parameter register Revision 1 267 I Microsemi MSS DDR Subsystem Table 7 19 DDR Controller Configuration Register continued Address Register Reset Register Name Offset Type Source Description DDRC LPR QUEUE PARAM 2 CR OxOAC RW PRESET_N DDRC Performance Parameter register DDRC WR QUEUE PARAM CR 0x0BO RW PRESET_N DDRC Performance Parameter register DDRC_PERF_PARAM_2_CR 0x0B4 RW PRESET_N DDRC Performance Parameter register DDRC PERF PARAM 3 CR 0x0B8 RW PRESET_N DDRC Performance Parameter register DDRC DFI RDDATA EN CR Ox0BC RW PRESET NIDDRC DFI Read Command Timing register DDRC DFI MIN CTRLUPD TIMING CR OxOCO RW PRESET NIDDRC DFI Controller Update Min Time register DDRC DFI MAX CTRLUPD TIMING CR 0x0C4 R
362. in arbitration schemes For using dual AHB interface of MDDR the CFG_NUM_AHB_MASTERS bit in the DDR FIC NUM AHB MASTERS CR register must be set to 1 MSS Ai MSS DDR MSS DDR DDR Transaction Bridge Masters SDRAM Controller Controller AHB Lite AHB Lite FPGA Fabric Figure 7 6 MDDR with Dual AHB Interface Revision 1 255 I Microsemi MSS DDR Subsystem DDR SDRAM MSS to MDDR through MSS DDR bridge The MSS DDR bridge is a data bridge between four MSS AHB bus masters IDC DSG HPDMA and AHB bus matrix and the MDDR subsystem The MSS DDR bridge accumulates AHB writes into write combining buffers prior to bursting out to external DDR memory The MSS DDR bridge also includes read combining buffers allowing AHB masters to efficiently read data from the external DDR memory from a local buffer The MSS DDR bridge optimizes reads and writes from multiple masters to a single external DDR memory For more details refer to the DDR Bridge chapter 1 Cortex M3 Processor to DDR SDRAM The Cortex M3 processor can access the DDR SDRAM connected to the MDDR subsystem through the MSS DDR bridge as shown in Figure 7 7 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS The read write and read modify write transactions are initiated by the MSS DDR bridge to read or write the data into the mem
363. ing constraints of the target DDR memory The DDR PHY is composed of functional units including PHY control master DLL and read write leveling logic There are two kinds of DLLs the master DLL and the slave DLL The DLLs are responsible for creating the precise timing windows required by the DDR memories to read and write data The master DLL measures the cycle period in terms of a number of taps and passes this number through the ratio logic to the slave DLLs The slave DLLs can be separated on the target die to minimize skew and delay and to account for process temperature and voltage variations Write leveling and read leveling functions determine delay timings required to align data to the optimal window for reliable data capture The DDR PHY top level signals to interface with DDR SDRAM are listed in Table 7 12 PHY Training The PHY is responsible for determining the correct delay programming for the read data DQS read DQS gate and write DQS signals The PHY adjusts the delays and evaluates the results to locate the appropriate edges The DDR controller DDRC assists by enabling and disabling the leveling logic in the DRAMs and the PHY by generating the necessary read commands or write strobes The PHY informs the DDR controller when it has completed training which triggers the DDRC to stop generating commands and to return to normal operation DDR controller performs the PHY training after powering up the device The order of trainin
364. inimum Maximum LPDDR1 266 Mbps 133 MHz 400 Mbps 200 MHz DDR2 400 Mbps 200 MHz 667 Mbps 333 MHz DDR3 667 Mbps 333 MHz 667 Mbps 333 MHz Functional Description 240 The MDDR subsystem accepts requests from the AXI AHB interfaces with system addresses and associated data for writes For writes the data is written to DDR SDRAM through the DDR PHY for reads the associated data is returned to the AXI AHB interface The MDDR subsystem performs address mapping from system addresses to DDR SDRAM addresses rank bank row and column and prioritizes requests to minimize the latency of writes and reads and maximize page hits Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide The functional block diagram of the MDDR subsystem is shown in Figure 7 2 64 Bit AXI Bus from MSS DDR Bridge ee Bi Transaction DDR Controller Single ANBL j DDR_FIC Controller Dual AHBL Bus from FPGA Fabric 16 Bit APB Configuration Registers Configuration Bus Figure 7 2 MDDR Subsystem Functional Block Diagram DDR_FIC The MDDR subsystem has DDR FIC at the input side which provides an interface for the AXI or AHB master logic in the FPGA fabric The MDDR subsystem can be configured for AXI 64 or single AHB 32 or dual AHB 32 bit interfaces to connect with the FPGA fabric These options can be configured with the help of the MDDR configurator in Libero SoC For more details
365. interrupts to the Cortex M3 processor DDRB_DS_ERR_ADR_SR RO SYSRESET N MSS DDR bridge DS master error address status register DDRB HPD ERR ADR SR RO SYSRESET N MSS DDR bridge high performance DMA master error address status register DDRB SW ERR ADR SR RO SYSRESET N MSS DDR bridge switch error address status register DDRB BUF EMPTY SR RO SYSRESET N MSS DDR bridge buffer empty status register DDRB DSBL DN SR RO SYSRESET N MSS DDR bridge disable buffer status register DDRB STATUS RO SYSRESET N Indicates MSS DDR bridge status MSS EXTERNAL SR SW1C SYSRESET N MSS external status register MSSDDR FACC1 CR RW P Field CC RESET N MSS DDR fabric alignment clock controller 1 configuration register Revision 1 405 I Microsemi DDR Bridge DDR Bridge Control Registers in MDDR and FDDR Table 9 3 lists MSS DDR bridge control registers in the MDDR and FDDR Refer to the MSS DDR Subsystem section on page 237 and the Fabric Double Data Rate Subsystem section on page 373 for a detailed description of each register and bit Table 9 3 DDR Bridge Control Registers in MDDR and FDDR Address Reset Register Name Offset R W Source Description DDR_FIC_NB_ADDR_CR 0x400 RW PRESET N Indicates the base address of the non bufferable address region DDR_FIC_NBRWB_SIZE_CR 0x404 RW PRESET N l Indicates the size of the non bufferable address region DD
366. ion XAUI_TX_CLK Input Transmit clock source centered with txd The clock that drives the XAUI extender transmit block provided by the XGMII interface The active edge is source centered on the XGMII transmit data and control Refer to the IEEE 802 3ae clause 46 for a complete definition XAUI TXD 63 0 Input Transmit data input from the XGMII The signal has the following lane definitions LaneO row0 txd 7 0 Lane1 row0 txd 15 8 Lane2 row0 txd 23 16 Lane3 row0 txd 31 24 LaneO row1 txd 39 32 Lane1 row1 txd 47 40 Lane2 row1 txd 55 48 Lane3 row1 txd 63 56 The row0 lanes are leading the row1 lanes in time Refer to the IEEE 802 3ae clause 46 for a complete definition XAUI TXC 7 0 Input Transmit data lane control signals The signal has the following lane definitions LaneO row0 txc 0 Lane1 row0 txc 1 Lane2 row0 txc 2 Lane3 row0 txc 3 LaneO row1 txc 4 Lane1 row1 txc 5 Lane2 row1 txc 6 Lane3 row1 txc 7 The row0 lanes are leading the row1 lanes in time Refer to the IEEE 802 3ae clause 46 for a complete definition 148 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 25 SmartFusion2 SoC FPGA XAUI Extender Block XGMII Receive Interface Signal Port Type Description XAUI_RX_CLK Output Receive clock synchronous with Rxd clock synchronous with the ou
367. it Interface Timing Diagram The EPCS_X_RXDATA x 0 1 2 3 is captured using the rising edge of EPCS x RX CLK x 0 1 2 3 as shown in Figure 4 8 epcs rxcik EPCS X RXDATA 19 0 lt Valid Data Window Figure 4 8 EPCS Receive Interface Timing Diagram All other external PCS signals are considered asynchronous with respect to the epcs_rxclk or epcs_txclk clocks 162 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDESIF System Registers Configurations for EPCS Mode The SmartFusion2 SoC FPGA SERDESIF subsystem has 3 regions of configuration and status registers which can be accessed by the 32 bit APB bus e SERDESIF System Registers The SERDESIF System registers control the SERDESIF module for single protocol or multi protocol support implementation e PCle Core Bridge Register Space The PCle core configuration and status registers occupy 4 KBytes of configuration memory map e SERDES Macro Registers The SERDES macro register map contains control and status information of the SERDES block and lanes During EPCS mode the PCle core registers are not used Only the SERDESIF System registers and the SERDES macro register are used for EPCS mode Table 4 6 shows the SERDESIF system registers which need to be configured for EPCS mode of operation Refer to the SERDESIF Block section on page 5 for a detailed description of the register Table 4 6 e SERDESIF
368. ix A PCle Configuration Space 1 0 cnt nt ene 122 GIOSSAlY s i ee eats Aaa ae aie ees ee Ries Ee Roe ew Rha Dh ee Pee ee ete 127 3 KAW sees aesiad deat eed douegt teed Ganeae eed deeke aed Crees Tedd sera E ed veaea ak 129 SERDESIF System Registers Configurations for XAUI Mode 000 0c cece eee eee 133 Using the XAUI Protocol Mode 0 0 cient eae 134 SmartFusion2 SoC FPGA XAUI Timing Diagram 0 teas 139 MDIO Register Map sx c2 ccceg deere nr Sed eee GRE EEE RE ee Pe ee A eR eee a ee 141 SmartFusion2 SoC FPGA XAUI I O Signal Interface 1 0 eee eee 147 GOSSA 2 2 2524 2 ied a heed a Nia a ete dwar he eile ee Gon oie bab ESO Dee Gee eee ee ecb 152 A EPCSIMEWACC cso ke dra r e CeCe Dated eger bek Ob ooee ieee neh eae dee eh si 153 Using EPCS Protocol Mode 0 rapeaa oa aie a a EG EE aE EEn REED d E teas 158 SmartFusion2 SoC FPGA EPCS Interface Timing Diagram 1 0 eee 162 SERDESIF System Registers Configurations for EPCS Mode 0 eee 163 SmartFusion2 SoC FPGA EPCS Mode I O Signal Interface avuvvanaarnanve rar eee 164 GOSS ae ccs ere ia eae Gaye ea these eves eat ve a ative alg es Eaa E EN ee OE ens a ai 168 5 Serializer DeSenialiZer cvias 440d ceded seeativwetaewaa hawan deed k ae eee de Aa saa da 169 SERDES Functional BIOCks as ssaursar kjendeiekhe Rita ke thee hoy ohn eek oa Sagres sekk Ge 170 TX PLL nd CDR PLL Operation xcccet Oveantagg oven d
369. izes reads and writes from multiple masters to a single external DDR memory Data coherency rules between the four masters and the external DDR memory are implemented in the hardware The DDR bridge contains three write combining Read buffers and 1 read buffer as shown in Figure 9 1 All buffers within the DDR bridge are implemented with latches and are not subject to the single event upsets SEUs that SRAM exhibits SmartFusion2 SoC FPGA devices implement three DDR bridges in MSS FDDR and MDDR subsystems i Read Buffer Master Interface 1 WCB and Write Access Read Buffer Control Master Interface 0 To AXI Slave Master Interface 2 WCB and Read Buffer Read Access Control Master Interface 3 WCB and Read Buffer DE Figure 9 1 DDR Bridge Functional Block Diagram Features The DDR bridge has the following features Single 64 bit AXI master interface e Four slave interfaces 1 Read only 32 128 bits AHB bus Fixed read buffer size of 32 Bytes to match cache line fill size 3 Read Write 32 bit AHB bus Configurable read buffer size of 16 or 32 Bytes Configurable write buffer size of 16 or 32 Bytes Arbitration scheme Two level arbitration with Master Interface O having the highest priority followed by Master Interface 1 and the remaining Master Interfaces in round robin fashion Revision 1 395 3 Microsemi DDR Bridge DDR Bridges in SmartFusion2 SoC FPGA Devices SmartFusion2 SoC FP
370. k Unstable Stable aTxPLLRstB Transmit Clock and Transmit Datapath Powering off the TX PLL is done using the aTXPLLRstB signal which is connected to the TXPLL RST bit4 of PHY RESET OVERRIDE register If the TX PLL was powered down by asserting aTXPLLRstB for deep power savings exit from power down should follow the same procedure as described for powering on the TX PLL Note that TXPLL is bypassed in this mode and if aRefClk was present while aTXPLLRstB was asserted the outputs of the PLL will toggle with aRefClk but at a divided down frequency While the TX PLL is operational and in lock it is possible to shut down both the BitClk tree and aTXClk for intermediate power savings and faster bring up time by the assertion of TXHF_CLKDN bit6 of PHY_RESET_OVERRIDE register The TXHF_CLKDN signal when set disables the TX PLL VCO by applying a static zero to the PMA aTXHfClkDnB signal The aTXHfCIKDNB signal functions to inhibit the output buffers of the PLL without interfering with the loop hence not affecting lock It is also important to note that the output driver has to be brought to an idle condition before shutting down BitClk shutting down BitClk could result in a static High or Low at the TXDP TXDN pins if the driver is not brought to idle which would cause undesirable DC shifts on an AC coupled transmission line Changing the TX PLL Mode of Operation Once the TX PLL has acquired lock any change of mode setting is accomplished by
371. k b REG DDRC T CCD tCCD RAS to CAS Minimum time between two reads or two Delay writes from bank A to bank B REG DDRC T FAW tFAW Four Active Wi Sliding time window in which a maximum of tWorkndow 4 bank activates are allowed in a 8 bank design In a 4 bank design set this register to 0x1 Dynamic DRAM Global Constraints These are primarily related to gaining access to the data bus while avoiding bus contention A global constraints block enforces each of these constraints Using the global constraints block the scheduler dynamically obeys all of the following constraints when scheduling transactions Table 7 10 Table 7 10 Dynamic DRAM Global Constraints Control Signal REG_DDRC_RD2WR Constraint Name Read to Write turnaround time Minimum time to and issuing any WRITE command Constraint Meaning allow between issuing any READ command REG_DDRC_WR2RD Write to Read Turnaround Time Minimum time to command and is allow between issuing any WRITE suing any READ command REG_DDRC_WRITE_LATENCY Write Latency Time after a WR driven to DRAM ITE command that write data should be 246 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Single Error Correction and Double Error Detection SECDED The SECDED system can be enabled by setting REG_DDRC_MODE of DDRC_MODE_CR to 101 When SECDED is enabled the DDRC adds 8 bi
372. l buffers Buffers can be configured to 16 byte or 32 byte size 0 Buffer size is configured to 16 bytes 1 Buffer size is configured to 32 bytes 362 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 217 DDR FIC NBRWB SIZE CR continued Bit Reset Number Name Value Description 7 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 DDR_FIC_NUBF_SZ 0x0 This signal indicates the size of the non bufferable address region The region sizes are as follows 0000 Reserved default 0001 64 KB bufferable region 0010 128 KB bufferable region 0011 256 KB bufferable region 0100 512 KB bufferable region 0101 1 MB bufferable region 0110 2 MB bufferable region 0111 4 MB bufferable region 1000 8 MB bufferable region 1001 16 MB bufferable region 1010 32 MB bufferable region 1011 64 MB bufferable region 1100 128 MB bufferable region 1101 256 MB bufferable region 1110 512 MB bufferable region 1111 1 GB bufferable region DDR_FIC_BUF_TIMER_CR Table 7 218 DDR FIC BUF TIMER CR Bit Reset Number Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved
373. l number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods Revision 1 225 I Microsemi Serializer Deserializer PRBS ERR CYC FIRST 23 16 Register Table 5 128 PRBS ERR CYC FIRST 23 16 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC FIRST 23 16 PRBS last error cycle counter register bits 23 16 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS_ERR_CYC_FIRST_31_24 Register Table 5 129 PRBS ERR CYC FIRST 31 24 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC FIRST 31 24 PRBS last error cycle counter register bits 31 24 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter infor
374. l the corresponding configuration input of the MPLL LOCK counter Value 2 binary value 5 0000 32 1111 1048576 For the number of reference cycles before LOCK is asserted from LOCK being detected Revision 1 385 I Microsemi Fabric Double Data Rate Subsystem Table 8 6 PLL_CONFIG_HIGH continued Bit Reset Number Name Value Description 6 4 PLL_LOCKWIN 0x0 000 500 ppm 100 8000 ppm 001 1000 ppm 101 16000 ppm 010 2000 ppm 110 32000 ppm 011 4000 ppm 111 64000 ppm Phase error window for LOCK assertion as a fraction of divided reference period Values are at typical PVT only and are not PVT compensated 3 0 PLL FILTER RANGE Ox9 PLL filter range 0000 BYPASS 0111 18 29 MHz 0001 1 1 6 MHz 1000 29 46 MHz 0010 1 6 2 6 MHz 1001 46 75 MHz 0011 2 6 4 2 MHz 1010 75 120 MHz 0100 4 2 6 8 MHz 1011 120 200 MHz 0101 6 8 11 MHz 0110 11 18 MHz FDDR_FACC_CLK_EN Table 8 7 FDDR FACC CLK EN Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_CLK_EN Ox1 Enables the clock to the DDR memory controller 386 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FDDR_FAC
375. ld not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 5 BASE_DIVISOR 0x0 Selects the ratio between CLK_A and the regenerated version of CLK_BASE called CLK_BASE_REGEN Allowed values 000 clk_a clk_base_regen ratio is 1 1 001 clk_a clk_base_regen ratio is 2 1 010 clk_a clk_base_regen ratio is 4 1 100 clk_a clk_base_regen ratio is 8 1 101 clk_a clk_base_regen ratio is 16 1 110 clk_a clk_base_regen ratio is 32 1 Other values Reserved 4 3 DIVISOR_A 0x0 Selects the ratio between CLK_SRC and CLK_A which is an intermediate clock within the FACC 00 clk_src clk_a ratio is 1 1 01 clk_src clk_a ratio is 2 1 10 clk_src clk_a ratio is 3 1 11 Reserved 2 0 DDR_FIC_DIVISOR 0x0 Selects the ratio between CLK_A and CLK_DDR_FIC 000 clk_a clk_DDR_FIC ratio is 1 1 001 clk_a clk_DDR_FIC ratio is 2 1 010 clk_a clk_DDR_FIC ratio is 4 1 100 clk_a clk_DDR_FIC ratio is 8 1 101 clk_a clk_DDR_FIC ratio is 16 1 110 clk_a clk_DDR_FIC ratio is 32 1 Other values Reserved 388 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PLL_DELAY_LINE_SEL Table 8 10 PLL DELAY LINE SEL Bit Reset Number Name Value Description 31 4 Reserved 0
376. le 3 1 XAUI Implementation in SmartFusion2 SoC FPGA LaneOd Lane1 Lane2 Lane3 XAUI Protocol Protocol Speed Protocol Speed Protocol Speed Protocol Speed Single Protocol PHY mode XAUI 3 125G XAUI 3 125G XAUI 3 125G XAUI 3 125G Revision 1 129 I Microsemi XAUI 130 XAUI Overview XAUI is a standard for extending the 10 Gb media independent interface XGMII between the media access control MAC and PHY layer of 10Gb Ethernet 10 GbE The XGMII extender which is composed of an XGMII extender sublayer XGXS at the MAC end an XGXS at the PHY end and an XAUI between them is to extend the operational distance of the XGMII and to reduce the number of interface signals XAUI is a four lane serial interface and each lane is a differential pair and the data on each lane is 8B 10B encoded before the transmission XAUI has the following features e Simple signal mapping to the XGMII Independent transmit and receive data paths Four lanes conveying the XGMII 64 bit data and control e Differential signaling with low voltage swing 1600 mV p p Self timed interface allowing jitter control to the physical coding sublayer PCS e Shared technology with other 10 Gb s interfaces Shared functionality with other 10 Gb s Ethernet blocks e Utilization of 8b 10b encoding This chapter introduces the XAUI extender block inside SERDESIF block and provides detailed information on using t
377. led in the system PCIE_LINKSCR Register 034h Table 2 28 PCIE_LINKSCR Bit Reset Number Name Value Description 31 0 PCIE_LINKSCR 0x00000050 This register reports the current value of the PCle link control and status register It can be monitored by the local processor when relaxed ordering and no snoop bits are enabled in the system 92 Re vision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TC_VC_MAPPING Register 038h Table 2 29 TC VC MAPPING Bit Reset Number Name Value Description 31 24 TC VC MAPPING 31 24 0x0 Reserved 23 21 TC VC MAPPING 23 21 0x0 Mapping for TC7 20 18 TC_VC_MAPPING_20_18 0x0 Mapping for TC6 17 15 TC VC MAPPING 17 15 0x0 Mapping for TC5 14 12 TC_VC_MAPPING_14_12 0x0 Mapping for TC4 11 9 TC_VC_MAPPING_11_9 0x0 Mapping for TC3 8 6 TC VC MAPPING 8 6 0x0 Mapping for TC2 5 3 TC VC MAPPING 5 3 0x0 Mapping for TC1 2 0 TC VC MAPPING 2 0 0x0 Mapping for TCO always 0 CAPTURED_BUS_DEVICE_NB Register 03Ch Table 2 30 CAPTURED BUS DEVICE NB Bit Reset Number Name Value Description 31 0 CAPTURED BUS DEVICE NB This register reports the bus and device number of the endpoint device for each configuration write TLP received MSI CTRL STATUS Register 03Ch Table 2 31 MSI CTRL STATUS Bit Reset Number
378. looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected CUSTOM_PATTERN_15_8 Register Table 5 108 CUSTOM_PATTERN_15_8 Bit Reset Number Name Value Description 7 0 RX_PWRDN 15 8 This register enables bit 15 to bit 8 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be looped back to the receiver to check if any error is detected on the line In the latter case the PMA hard macro function is used to perform a word alignment function Note This register can be programmed any time but has no functional impact as long as the custom pattern generation is not enabled and selected CUSTOM_PATTERN_23_16 Register Table 5 109 CUSTOM PATTERN 23 16 Bit Reset Number Name Value Description 7 0 RX PWRDN 23 16 This register enables bit 23 to bit 16 to program a custom pattern instead of the implemented PRBS gener
379. m System IP Register EPCS Lane 0 and Lane 1 XGMII Interface PCle L2 P2 AXI AHB AXI AHB APB Slave Control Master Slave Interface Interface Interface m oO C oO a ne E oO N q oO a N Lane 2 and Lane 3 EPCS XGMII Lane 0 and Interface Lane 1 FABRIC XGMII Interface Figure 1 1 SmartFusion2 SoC FPGA SERDESIF Block 6 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 1 e SERDESIF Block usages in Single Mode and Multi Modes Protocols Single Multi Protocol Protocol Description Single protocol PCle SERDESIF is configured to use PCle x4 x2 and x1 link mode The PCle link can be configured in Regular or Reversed modes In PCle only mode unused lanes are forced to RESET state and the Extender XAUI block is put in RESET state XAUI SERDESIF is configured to use all four lanes In XAUI mode all the lanes are used and the PCle System is put in RESET state SGMII SERDESIF is configured to use lane3 only for SGMII purposes In SGMIl only mode lane0 lane1 and lane2 are not used and are forced to the RESET state The PCle System and XAUI blocks are put in the RESET state EPCS SERDESIF is configured to use all four lanes In EPCS only mode any serial protocol can be run though the EPCS interface to fabric using the EPCS interface The PCle System and XAUI blocks are put in the RESET state Multi protocol PCle EPCS
380. master to read or write the data into the memory AXI MSS DDR DDR Transaction Controller Controller me ea FPGA Fabric Figure 7 4 MDDR with AXI Interface Revision 1 253 I Microsemi MSS DDR Subsystem 2 Single AHB Interface from FPGA Fabric The MDDR subsystem can be used to access DDR SDRAM memory as shown in Figure 7 5 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS or user logic APB master in the FPGA fabric The read and write transactions initiated by the AHB master are converted to AXI transactions by DDR FIC MSS AXI MSS DDR MoS DDR DDR Transaction Bridge Masters SDRAM Controller Controller AHB Lite FPGA Fabric Figure 7 5 MDDR with Single AHB Interface 254 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide 3 Dual AHB Interface from FPGA Fabric The MDDR subsystem can be used to access DDR SDRAM memory as shown in Figure 7 6 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS or user logic APB master in the FPGA Fabric The read and write transactions initiated by AHB masters are converted to AXI transactions by DDR FIC Both the AHB masters have round rob
381. mation This helps to clear all the SECDED status information such as error counters and other SECDED registers The read value of this register is always 0 314 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY Configuration Register Summary Table 7 100 PHY Configuration Register Summary Reset Register Name Offset Type Source Description PHY_DYN_BIST_TEST_CR 0x200 RW PRESET N PHY BIST test configuration register PHY DYN BIST TEST ERRCLR 1 CR 0x204 RW PRESET N PHY BIST test error clear register PHY DYN BIST TEST ERRCLR 2 CR 0x208 RW PRESET N PHY BIST test error clear register PHY DYN BIST TEST ERRCLR 3 CR 0x20C RW PRESET_N PHY BIST test error clear register PHY BIST TEST SHIFT PATTERN 1 CR 0x210 RW PRESET N PHY BIST test shift pattern register PHY BIST TEST SHIFT PATTERN 2 CR 0x214 RW PRESET N PHY BIST test shift pattern register PHY BIST TEST SHIFT PATTERN 3 CR 0x218 RW PRESET N PHY BIST test shift pattern register PHY DYN LOOPBACK CR 0x21C RW PRESET N PHY loopback test configuration register PHY BOARD LOOPBACK CR 0x220 RW PRESET N PHY Board loopback test configuration register PHY CTRL SLAVE RATIO CR 0x224 RW PRESET N PHY control slice DLL slave ratio register PHY CTRL SLAVE FORCE CR 0x228 RW PRESET N
382. mation complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS ERR CYC FIRST 39 32 Register Table 5 130 PRBS ERR CYC FIRST 39 32 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC FIRST 39 32 PRBS last error cycle counter register bits 39 32 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter information complementing the total number errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods 226 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PRBS_ERR_CYC_FIRST_47_40 Register Table 5 131 PRBS_ERR_CYC_FIRST_47_40 Bit Reset Number Name Value Description 7 2 Reserved 1 0 PRBS_ERR_CYC_FIRST 47 40 PRBS last error cycle counter register bits 47 40 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performan
383. me Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 54 48 bits of REG_PHY_FIFO_WE_SLAVE_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY GATELVL INIT MODE CR Table 7 128 PHY GATELVL INIT MODE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_GATELVL_INIT_MODE 0x0 The user programmable init ratio selection mode 1 Selects a starting ratio value based on REG_PHY_GATELVL_INIT_RATIO port 0 Selects a starting ratio value based on write leveling of the same data slice PHY_GATELVL_INIT_RATIO_1_CR Table 7 129 PHY GATELVL INIT RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG PHY GATELVL INIT RATIO Ox0 15 0 of REG PHY GATELVL INIT RATIO Lowest 11 bits are from data slice
384. mi Serializer Deserializer Table 5 2 e SERDES Macro Registers continued 184 Revision 1 Offset Reset Hex Register Name Value Type Description 0X010 PLL F PCLK RATIO 0x24 RW PLLF settings and PCLK ratio 0x34 Reset value for PCle mode or 0x09 0x24 16 bit pipe interface and 250 MHz PCLK 0x34 16 bit pipe interface and other PCLK 0x24 8 bit pipe interface Reset value for other modes 0x00 0X014 PLL_M_N 0x04 RW PLL M and N settings 0x13 Reset value for PCle mode 0x04 OrURDA Reset value for XAUI mode 0x13 Reset value for EPCS mode 0x69 0X018 CNT250NS_MAX 0x7C RW 250 ns timer base count 0x27 Reset value for PCle mode 0x7C OLUWE Reset value for XAUI mode 0x27 Reset value for EPCS mode 0x1F 0X01C RE_AMP_RATIO 0x00 RW IRX equalization amplitude ratio 0X020 RE CUT RATIO 0x00 RW RX equalization cut frequency 0X024 TTX_AMP_RATIO 0x80 RW ITX amplitude ratio 0X028 TX PST RATIO 0x15 RW ITX post cursor ratio or 0x00 Reset value for PCle mode 0x15 Reset value for XAUI mode 0x15 Reset value for EPCS mode 0x00 0X02C TX_PRE_RATIO 0x00 RW ITX pre cursor ratio 0X030 ENDCALIB_MAX 0x10 RW End of calibration counter 0X034 CALIB STABILITY COUNT 0x38 RW Calibration stability counter 0X038 POWER DOWN 0x00 RW Power down feature 0X03C RX_OFFSET_COUNT 0x70 RW IRX offset counter 0X040 PLL F PCLK RATIO 5GBPS 0x24 RW PLL F settings a
385. mode I O PAD interface Active MISCELLENOUS interface Active PLL control and status interface Active Revision 1 51 I Microsemi SERDESIF Block All SERDESIF signals are mapped one to one and there is no overlaying of signals Figure 1 16 shows the SERDESIF I O signals in Fabric mode0 SERDES IF 0 CORE RESET N PCIE SYSTEM INT PLL LOCK INT V 1U PPIE EV US AEO N PCIE_EV_1US PCIE_WAKE_REQ AXI MASTER PERST_N PADs_OUTE REFCLKO P TXD1_N REFCLKO_N TXD2_P RXDO_P TXD2_N Figure 1 16 e SERDESIF I O Signals in Fabric Mode0 Fabric Signals for Fabric Mode1 In Fabric mode1 overlaid AHB lite master and slave interfaces are exposed to the fabric Overlaid interface EPCS interface for laneO and lane1 is not exposed to fabric The SERDESIF block can be configured to support single or multi protocol in Fabric mode1 that is different PHY modes can be supported in Fabric mode Note The application interface to SERDESIF for PCle protocol is AHB master and AHB slave interface Table 1 63 lists the SERDESIF signals and behavior in Fabric model Table 1 63 e SERDESIF Signals in Fabric Mode1 SERDESIF Signal Interface Interface Behavior Clock and reset interface Active AXI AHBL master interface Active PCle in AHBL Mode AXI AHBL slave interface Active PCle in AHBL Mode APB interface 32 bit Active Inactive EPCS interface lane2 and lane3 Inactive
386. mphasis This bit selects the level of de emphasis for an upstream component when the link is operating at 5 0 gbps speed support 0 Indicates de emphasis of 6 dB 1 Indicates de emphasis of 3 5 dB 0 K_BRIDGE_SPEED 0x0 PCle link speed support 0 Implements link speed support for 2 5 gbps 1 Implements link speed support for 2 5 and 5 0 gbps Reg40 CONFIG_BAR_SIZE_0_1 Register 0x2040 Table 1 26 CONFIG_BAR_SIZE_0_1 Bit Reset Number Name Value Description 17 13 CONFIG_BAR_SIZE_1 0x0 These bits set the size of the BAR1 memory For example 32 bit BAR CONFIG_BAR_SIZE_1 5 d21 translates to BARO 2MB 1111 1111 1110 0000 0000 0000 0000 CONFIG BAR C ONTROL 1 12 9 CONFIG BAR CONTROL 1 0x0 LSB bits of BAR1 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable non prefetchable memory 8 4 CONFIG_BAR_SIZE_0 0x0 These bits set the size of the BARO memory For example 32 bit BAR CONFIG_BAR_SIZE_0 5 d20 translates to BARO 1MB 1111 1111 1111 0000 0000 0000 0000 CONFIG BAR C ONTROL 0 3 0 CONFIG BAR CONTROL 0 0x0 LSB bits of BAR 0 register in PCle core register map BitO Memory IO type indicator Bit2 1 Size of memory 00 32 bit memory 10 64 bit memory Bit3 Prefetchable non prefetchable memory Note All the register are 32 bit Bits not shown in the table are r
387. n 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY REG BIST ERR 0x0 15 0 bits of PHY REG BIST ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG PHY BIST ERR CLR must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bits 346 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_BIST_ERROR_2_SR Table 7 175 PHY_BIST_ERROR_2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_BIST_ERR 0x0 31 16 bits of PHY REG BIST ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG_PHY_BIST_ERR_CLR port must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bit
388. n 7 0 ATXDRT DYN 7 0 This register defines bit 7 to bit 0 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver 206 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide ATXDRT_DYN_15_8 Register Table 5 64 ATXDRT_DYN_15_8 Bit Reset Number Name Value Description 7 0 ATXDRT DYN 15 8 This register defines bit 15 to bit 8 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver ATXDRT DYN 20 16 Register Table 5 65 e ATXDRT DYN 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 ATXDRT DYN 20 16 This register defines bit 20 to bit 16 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver ATXDRP EI1 7 0 Register Table 5 66 ATXDRP EI 7 0 Bit Reset Number Name Value Description 7 0 ATXDRP EI1 7 0 This register defines bit 7 to bit 0 of the transmitted P parameter sent to the PHY for being in electrical idle on the transmit driver ATXDRP EI1 15 8 Register Table 5 67 ATXDRP EI1 15 8 Bit Reset Number Name Value Description 7 0 ATXDRP EI1 15 8 This register defines bit 15 to bit 8 of the transmitted P parameter sent to the PHY for being in electrical idle I on the transmit driver ATXDRP EI1 20 16 Register Table
389. n 1 Region 6 Region 7 260 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide If it connects only 2 GB of DDR memory to MDDR only 4 regions will be available 0 4 Table 7 16 shows the DDR regions available for different address mode settings Table 7 16 Accessed DDR Regions Based on Different Mode Settings for a 2 GB Memory DDR Regions Visible at MSS DDR Address Space for Different Modes Address Space MSS DDR Space 0 MSS DDR Space 1 MSS DDR Space 2 MSS DDR Space 3 Mapping 0xA0000000 0xB0000000 0xC0000000 0xD0000000 Modes OxAFFFFFFF OxBFFFFFFF OxCFFFFFFF OxDFFFFFFF 0000 Region 2 Region 3 Region 0 Region 1 0001 Region 0 Region 1 Region 2 Region 3 0010 Region 0 Region 1 Region 2 Region 3 Revision 1 261 I Microsemi MSS DDR Subsystem DDR Memory Device Examples Figure 7 10 shows DDR2 SDRAM connected to the MDDR of a SmartFusion2 SoC FPGA device Micron s MT47H64M16 is a 128 MB density device with x16 data width The MDDR is configured in full bus width mode and without SECDED The total amount of DDR2 memory connected to MDDR is 256 MB MDDR_PADS MT47H64M16 MDDR_CAS_N MDDR CKE __ O MDDR eak y moor cik h S MDDR 68 nh ST EERE MDDR ODT Ceo MDDR WE NL MDDR ADDR 12 0 OE VEE FA OE ADDR 12 0 MDDR BA2 0 Lu TT TT BA 2 0 MDDR DM RDQS 1 0 PIT TT TT DM MDDR DQS 1 0 TT
390. n of XS Package ID Low Register Reg08 M XGXS PHY DTE XS Package ID Low Bit Reset Number Name Value Description 15 0 OUI 0x0 Reg08 and Reg 09 provide a 32 bit value which may constitute a unique identifier for a particular type of package that the SERDES is instantiated within The identifier shall be composed of the 3rd through 24th bits of the OUI assigned to the package manufacturer by the IEEE plus a 6 bit model number and a 4 bit revision number Reg08 sets bits 3 18 of the OUI Bit 3 of the OUI is located in bit 15 unique identifier of the register and bit 18 of the OUI is located in bit 0 of the register Table 3 16 Depicts Definition of XS Package ID High Register Reg09 M XGXS PHY DTE XS Package ID High Bit Reset Number Name Value Description 15 10 OUI 0x0 Bits 19 24 of the OUI Bit 19 of the OUI is located in bit 15 of the register and bit 24 of the OUI is located in bit 10 of the register 9 4 Manufacturer model Ox0 Bits 5 0 of the manufacturer model number Bit 5 of the model number number is located in bit 9 of the register and bit 0 of the model number is located in bit 4 of the register 3 0 Revision number 0x0 Bits 3 0 of the manufacturer model number Bit 3 of the revision number is located in bit 3 of the register and bit 0 of the revision number is located in bit 0 of the register Table 3 17 Depicts Definition of XGXS Lane Status Register Re
391. n transition delay counter It delays the transition to power down phase when a TXELECIDLE signal is asserted in states where the RXELECIDLE signal is not used such as LOs detect disable and hot reset The recommended value of this counter is 10 24 21 K CNT CONFIG4 24 21 These bits are used for stopping dummy insertion at the CDC transmit FIFO when the Almost Full condition is reached Used when a user clock is implemented and CDC compensates for plesiochronous relation When set to 0000 the core defaults to 1011 20 K CNT CONFIG4 20 Reserved 19 12 K CNT CONFIG4 19 12 These bits set number of clock cycles for inferring electrical idle exit when core RX lanes are in the LOs state 11 8 K CNT CONFIG4 11 8 These bits set the RX CDC Almost Full condition which indicates when the CDC receive FIFO is almost full When set to 0000 the core defaults to 1011 7 4 K CNT CONFIG4 7 4 These bits set the TX CDC Almost Full condition which indicates when the CDC transmit FIFO is almost full When set to 0000 the core defaults to 1011 3 0 K CNT CONFIG4 3 0 Reserved K CNT CONFIGJ 5 Register 314h Table 2 123 K CNT CONFIG 5 Bit Reset Number Name Value Description 31 0 K CNT CONFIG5S 31 0 Reserved Revision 1 117 I Microsemi PCI Express PCle System I O Signal Interface The SmartFusion2 SoC FPGA PCle system block interfaces with the FPGA fabric on one side and SERD
392. n1 features are configured using these 16 8 bit registers e PCle 5 Gbps PHY registers offset 0x040 to OXOBC These 32 registers are specific to the PCle protocol when running at 5 Gbps e SERDES Electrical Parameter registers offset OXOCO to 0X18C These 48 registers are internally reported values of parameters programmed inside the SERDES block e SERDES Testing registers offset 0X190 to Ox1FC These registers are used for testing the SERDES block e SERDES Recompute register offset 0x200 This register is a command register that requires PMA control logic to recompute the SERDES parameter based on the new set of register values programmed e SERDES PRBS Error Counter registers offset 0x204 to 0x400 There are 14 registers that are used for bit error rate testing These registers are for Lane0 1 2 or 3 and the only difference between Lane0 1 2 or 3 is the base address specifying which lane it is for The rest of the register spaces are unused Table 5 2 e SERDES Macro Registers Offset Reset Hex Register Name Value Type Description 0X000 CRO 0x80 RW Control register 0 0X004 ERRCNT DEC 0x20 RW Clock count for error counter decrement 0X008 RXIDLE MAX ERRCNT THR 0x48 RW Error counter threshold RXO idle detect maximum or OxF8 latency Reset value for PCle mode 0x48 Reset value for other mode OxF8 OX00C IMPED RATIO 0x80 RW ITX impedance ratio Revision 1 183 lt gt Microse
393. nd PCLK ratio in PCle 5 Gbps or 0x04 speed 0x24 16 bit pipe 0x04 8 bit pipe 0X044 PLL M N 5GBPS 0x09 RW PLL M and N settings in PCle 5 Gbps speed 0X048 CNT250NS MAX 5GBPS Ox7C RW 1250 ns timer base count in PCle 5 Gbps speed 0X04C Reserved 0X050 TX PST RATIO DEEMPO FULL 0x15 RW ITX Post Cursor ratio with TXDeemp 0 Full swing 0X054 TX PRE RATIO DEEMPO FULL 0x00 RW ITX pre cursor ratio TXDeemp 0 full swing 0X058 TX PST RATIO DEEMP1 FULL 0x20 RW ITX post cursor ratio with TXDeemp 1 Full swing OX05C TX_PRE_RATIO_DEEMP1_FULL 0x00 RW TX pre cursor ratio TXDeemp 1 full swing 0x060 TX_AMP_RATIO_MARGINO_FULL 0x80 RW TX amplitude ratio TXMargin 0 full swing I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 5 2 e SERDES Macro Registers continued Offset Reset Hex Register Name Value Type Description 0X064 TX AMP RATIO MARGIN1 FULL 0x78 RW ITX amplitude ratio TXMargin 1 full swing 0X068 TX AMP RATIO MARGIN2 FULL 0x68 RW ITX amplitude ratio TXMargin 2 full swing 0X06C TX AMP RATIO MARGIN3 FULL 0x60 RW ITX amplitude ratio TXMargin 3 full swing 0X070 TX AMP RATIO MARGIN4 FULL 0x58 RW ITX amplitude ratio TXMargin 4 full swing 0X074 TX AMP RATIO MARGINS FULL 0x50 RW ITX amplitude ratio TXMargin 5 full swing 0X078 TX AMP RATIO M
394. nd if data is present in a write buffer these transfers will occur after flushing the write buffer Figure 9 6 shows the flowchart for flush controller operation Any read buffe tag WCB tag Hold the read request All eight A lush operation are YES NO Generate flush request to the Arbiter Release the read request after Flush operation Figure 9 6 Flow Chart for Flush Controller Operation Revision 1 401 3 Microsemi DDR Bridge Figure 9 7 402 Read Buffer The DDR bridge has a read buffer for each master to hold the fetched DDR burst data One read buffer is maintained for each master with a configurable burst size of 16 or 32 bytes in alignment with the DDR burst capability For Master Interface 0 the buffer length is fixed to 32 bytes e The read buffer is associated with one specific master for reading it does not check the read addresses of other masters to determine whether that data can be read from the read buffer there is no cross buffer read access If the subsequent access from the same master is to a region that is outside the TAG region the current data in the read buffer is invalidated The read buffer will initiate a DDR burst size request for reads in the bufferable region regardless of the size of request from the master e If there is an error response from DDR for the critical first word read the error is propagated to the master and the read entry
395. nd status registers are used via the APB interface Note that most of the PCle bridge registers are actually used for the PCle configuration space register and it takes two clock cycles for PCle configuration space registers to get updated after the PCle bridge registers are updated APB Slave The APB slave interface provide APB interface to configuration PCle Bridge Registers Refer to the PCle Bridge Registers section on page 90 for details AXI to AXI AHBL Bridge AXI AHB Top The AXI to AXI AHBL top bridge module implements an AXI master to AXI master AHBL master protocol translator This bridge appears as a 64 bit AXI slave to the PCle 64 bit AXI master on the input side and as a 64 bit AXI master or 32 bit 64 bit AHB master to the AHBL slave on the output towards the fabric So the bridge accepts 64 bit AXI master transactions and converts the transactions into 64 bit AXI or 32 bit AHBL master output transactions for the fabric Figure 2 4 shows the block diagram of the AXI AHB top bridge AXI AHB TOP AXI64 Slave Pee AXI64 HAD i AXI64 Master ME ive AHB32 Master merage Master Interface Interface iA Interface FPGA Fabric Figure 2 4 AXI to AXI AHBL Bridge Block Diagram The AXI to AXI AHBL bridge are configured using the two SERDESIF system registers as shown in Figure 2 2 on page 61 for appropriate slave implementations in the fabric Refer to the SERDESIF system registers in the SERDESIF Block section on page 5 for
396. ndicates whether valid write data and strobes are available 1 Write data and strobes available 0 Write data and strobes not available 1 MDDR_SMC_AXI_M_BREADY Out Indicates whether the master can accept the response information 1 Master ready 0 Master not ready 1 MDDR_SMC_AXI_M_AWVALID Out Indicates whether valid write address and control information are available 1 Address and control information available 0 Address and control information not available 1 MDDR_SMC_AXI_M_ARVALID Out Indicates the validity of read address and control information 1 Address and control information valid 0 Address and control information not valid 1 MDDR_SMC_AXI_M_RREADY Out Indicates whether the master can accept the read data and response information 1 Master ready 0 Master not ready 1 MDDR_SMC_AXI_M_AWREADY In Indicates that the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready 1 MDDR_SMC_AXI_M_WREADY In Indicates whether the slave can accept the write data 1 Slave ready 0 Slave not ready 1 MDDR_SMC_AXI_M_BVALID In Indicates whether a valid write response is available 1 Write response available 0 Write response not available 1 MDDR_SMC_AXI_M_ARREADY In Indicates whether the slave is ready to accept an address and associated control signals 1 Slave ready 0 Slave not ready Revision 1 409 3 Microsemi Soft
397. ng read and write access to DDR memory through the Cortex M3 S bus through the cache controller Master interfaces 0 and 1 are used only within the MSS The DDR bridges resident in the MDDR subsystem and FDDR subsystem do not use these two interfaces Master Interfaces 1 2 and 3 are identical in that they allow read and write access from the connected master Arbitration among the four Master interfaces is handled as follows fixed priority between Master Interfaces 0 and 1 with 0 having the highest priority and round robin arbitration between interfaces 2 and 3 The external DDR memory regions can be defined to be non bufferable If a master interface requests a write to a non bufferable region the DDR bridge is essentially bypassed no write combining occurs The size of the non bufferable address space can also be defined Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Write Combining Buffer WCB For efficient use of DDR memory bandwidth the WCB combines single cycle access from each master into a single DDR memory burst The WCB has a user configurable burst size of 16 or 32 bytes and is typically set at design time Each WCB maintains an address tag that stores the base address of the data to be combined in the buffer For every write transfer the address is compared with the WCB tag If the address matches the tag data is combined into the buffer The WCB writes to the corre
398. ng should remain constant for the entire time that DQS is driven by the controller 3 2 REG DDRC RANKO WR ODT 0x0 10 Indicates which remote ODTs should be turned on during a write to rank 0 Each rank has a remote ODT in the DRAM which can be turned on by setting the appropriate bit here Set this bit to 1 to enable its ODT 1 Uppermost bit is unused 1 0 REG DDRC RANKO RD ODT 0x0 10 Indicates which remote ODTs should be turned on during a read to rank 0 Each rank has a remote ODT in the DRAM which can be turned on by setting the appropriate bit here Set this bit to 1 to enable its ODT 1 Uppermost bit is unused 284 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC ODT PARAM 2 CR Table 7 48 DDRC ODT PARAM 2 CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 6 REG_DDRC_RD_ODT_HOLD 0x0 Cycles to hold ODT for a READ command 0 ODT signal is ON for 1 cycle 1 ODT signal is ON for 2 cycles and so on 5 2 REG_DDRC_WR_ODT_HOLD 0x0 Cycles to hold ODT for a WRITE command 0 ODT signal is ON for 1 cycle 1 ODT signal is ON for 2 cycles and so on 1 0 REG_DDRC_WR_ODT_BLOCK 0x0 00 Block read write scheduling for 1 cycle when write re
399. nput Fabric Fabric PLL LOCK output Table 1 60 SERDESIF Block PCI Express Interrupt and Power Management Interface Connected Port Type To Description PCIE_INTERRUPT 3 0 Input Fabric PCle system interrupt inputs PCIE_SYSTEM_INT Output Fabric PCle system interrupt output PCIE_WAKE_REQ Input Fabric PCle L2 P2 request from fabric PCIE_WAKE_N Output Fabric PCle L2 P2 exit request 50 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDESIF I O Signals For Various Protocol Modes The SERDESIF block supports implementing multiple high speed serial protocols and allows different modes of operation Depending on the protocol implemented some of the interface signals become active or inactive The term Fabric mode is used to describe the fabric interface to SERDESIF during various modes Fabric mode is divided into four modes 1 Fabric modeO PCle mode of operation with AXI master and AXI slave interface 2 Fabric mode1 PCle mode of operation with AHBL master and AHBL slave 3 Fabric mode2 EPCS mode of operation 4 Fabric mode3 XAUI mode of operation Table 1 61 shows the link between various Protocol mode and Fabric mode Table 1 61 Link Between Various Protocol Mode and Fabric Mode Mode of Operation Description Fabric Mode PCle only mode SERDESIF with AXI master and slave interface Fabric mode0 SERDESIF wi
400. ns that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 308 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC LCE SYNDROME 3 SR Table 7 88 DDRC LCE SYNDROME 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC REG ECC SYNDROMES 0x0 _ 47 32 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Revision 1 309 I Microsemi MSS DDR Subsystem DDRC LCE SYNDROME 4 SR Table 7 89 DDRC
401. nsmitted TX link should have enough credits to transfer TLP DLLPs after L2 exit EP supports L2 EP should have transmitted PM_REQUEST_ACK to RP Condition True PCle link transitions into L2 State alDDQ is asserted Figure 2 19 L2 Entry Flow Diagram Initiated by RC SW 5 The EP transmitting PM_REQUEST_ACK DLLPs and SERDES transitions into the L2 state and the status is reflected on the PIPE interface PowerDown 1 0 and PhyStatus outputs from the SERDES which indicate whether the SERDES transitioned into L2 state 6 The PCle system waits for PowerDown 1 0 on the PIPE interface to go to L2 state 11 and PhyStatus to be asserted asynchronously 7 Once the two conditions are met the EP is ready to go into L2 state and alDDQ which forces all analog circuitry to switch off for power saving is asserted Before transmitting PM_REQUEST_ACK DLLP the EP should meet all protocol requirements This is taken care of by the PCle IP core NonewTLPs or DLLPs should be pending for transmission e The TX link should have enough credits to transfer TLPs DLLPs after L2 exit The EP supports L2 The EP should have transmitted PM_REQUEST_ACK to the RP Revision 1 81 I Microsemi PCI Express SmartFusion2 SoC FPGA L2 Exit Sequence L2 Exit Sequence Initiated by EP 8 When the EP needs to exit L2 the application layer fabric asserts WAKE_REQ active high signal to the SmartFusion2 SoC FPGA SERDESIF block 9
402. nter enabling performance of bit error rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods Revision 1 229 I Microsemi Serializer Deserializer SERDESIF I O Signal Interface The SmartFusion2 SoC FPGA SERDES block interfaces with differential I O pads the PCle system and the FPGA The following section describes these signals Table 5 140 SERDESIF Block I O PAD Interface PCIE_x_REFCLK1N Connecte Port Name Type dto Description PCIE_x_RXDPO Input I O Pads Receive data SERDES differential positive input each SERDESIF consists of 4 RX signals Here x 0 for SERDESIF_0 and x 1 PAF XERADPI for SERDESIF_1 If unused can be left floating PCIE_x_RXDP2 PCIE_x_RXDP3 PCIE_x_RXDNO Input I O Pads Receive data SERDES differential negative input PCIE x RXDN1 Each SERDESIF consists of 4 RX signals Here x 0 for SERDESIF 0 and x 1 for SERDESIF 1 If unused can be left PCIE x RXDN3 PCIE x TXDPO Output I O Pads Transmit data SERDES differential positive output PCIE x TXDP1 Each SERDESIF consists of 4 TX signals Here x 0 for SERDESIF 0 and x 1 for SERDESIF 1 If unused can be left
403. nterface for the SERDES Register programming SERDESIF Protocol Mode with EPCS Interface SERDESIF with the EPCS interface can be configured as Single protocol mode or Multi protocol mode Table 4 1 Table 4 2 on page 154 and Table 4 3 on page 154 show a detailed description of the EPCS interface usage in Single protocol and Multi protocol mode Table 4 1 EPCS Interface Usage in Single protocol and Multi protocol Mode Single Multi Protocol Description Single protocol EPCS Protocol mode only Configured to use maximum 4 lanes In EPCS mode the user defined serial protocol can be run though the EPCS interface to the fabric using the EPCS interface The XGMII Extender Sublayer XGXS core and PCle core are put in RESET state Multi protocol PCle Protocol mode and Configured to use x2 and x1 lane PCle mode laneO and EPCS Protocol mode lane1 are used for the PCle link Any user defined other serial protocol can be run though the EPCS interface Lane2 and lane3 can be used for this purpose Revision 1 153 I Microsemi EPCS Interface Table 4 2 EPCS Interface and SERDES Lane Mapping in Multi protocol Mode PHYSICAL SERDES LANES LOGICAL LANES Mapping PHY MODE LaneOd Lane1 Lane2 Lane3 PCIe Protocol Protocol Speed Protocol Speed Protocol Speed Protocol Speed Multi protocol PCIe 2 5G EPCS EPCS PHY mode PCIe 2 5G PCIe 2 5G EPCS EPCS PCle link N
404. ntroller Entering Deep power down involves the following steps 1 Precharging closing all open pages Pages are closed one at a time in no specified order 2 Waiting for the tRP row precharge idle period 3 Issuing the command to enter deep power down For multi rank systems all chip selects will be asserted so that all ranks will enter deep power down simultaneously If the controller receives a read or write request from the core logic during steps 1 and 2 above deep power down is immediately aborted The same is true if REG_DDRC_DEEPPOWERDOWN_EN is driven to 0 during steps 1 or 2 Once the deep power down entry command has been issued proper deep power down exit is required Exit Once the controller has put the DDR SDRAM device in deep power down mode the controller automatically exits deep power down and reruns the initialization sequence when REG_DDRC_DEEPPOWERDOWN_EN is reset to 0 The contents of DDR SDRAM may be lost upon entry into deep power down mode ZQ Calibration This is a DDR3 only feature The ZQ calibration command is used to calibrate DRAM output drivers Ron and on die termination ODT values DDR3 SDRAM needs a longer time to calibrate Roy and ODT at initialization and a relatively smaller time to perform periodic calibrations The ZQ calibration long ZQCL command is used to perform initial calibration during the power up initialization sequence This command is allowed a timing period of tZQinit
405. nts an AHB Lite or AXI slave interface to connect to any AHB Lite or AXI master in the FPGA fabric On the output interface the DDR FIC bridge AXI master connects to the AXI slave interface of the AXI Transaction controller The AXI transaction controller receives read and write requests from DDR FIC and schedules to the DDR controller by translating the requests into the DDR controller commands The DDR controller DDRC receives the commands from the AXI transaction controller These commands are queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM constraints transaction priorities and dependencies between the transactions The DDRC in turn issues commands to the PHY module which launches and captures data to and from the DDR SDRAM DDR PHY converts the DDR controller instructions into the actual timing relationships and DDR signaling necessary to communicate with the memory device For more details about each block refer to the MSS DDR Subsystem section on page 237 The functional block diagram of the FDDR subsystem is shown in Figure 8 2 64 Bit AXI AHB Bus from FPGA AXI Fabric DDR Controller SRAM 16 Bit APB Configuration Bus Configuration Registers Figure 8 2 e FDDR Subsystem Functional Block Diagram 374 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide FDDR Port Descriptions The FDDR subsystem ports are shown in Figure
406. nused can be left floating 164 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 4 8 SERDESIF Block EPCS Interface Port Type Connected to Description fepcs_O_pwrdn Input Fabric EPCS interface Power down mode of the SERDES PMA LaneO lepcs 1 pwrdn Input Fabric EPCS interface Power down mode of the SERDES PMA Lane1 lepcs 2 pwrdn Input Fabric EPCS interface Power down mode of the SERDES PMA Lane2 lepcs 3 pwrdn Input Fabric EPCS interface Power down mode of the SERDES PMA Lane3 lepcs 0 tx data 19 0 Input Fabric EPCS interface transmit data from SERDES PMA LaneO epcs_1_tx_data 19 0 Input Fabric EPCS interface transmit data from SERDES PMA Lane epcs_2_tx_data 19 0 Input Fabric EPCS interface transmit data from SERDES PMA Lane2 epcs_3_tx_data 19 0 Input Fabric EPCS interface transmit data from SERDES PMA Lane3 epcs 0 tx val Input Fabric EPCS interface transmit data valid from LaneO lepcs 1 tx val Input Fabric EPCS interface transmit data valid from Lane1 lepcs 2 tx val Input Fabric EPCS interface transmit data valid from Lane2 lepcs 3 tx val Input Fabric EPCS interface transmit data valid from Lane3 lepcs 0 tx oob Input Fabric EPCS interface LaneO transmit idle needed for SATA OOB lepcs 1 tx oob Input Fabric EPCS interface Lane1 transmit idle needed fo
407. oader parameter 1 0 0X104 ATXDRP_EI1_20_16 0x00 RO Transmitter P shift loader parameter 1 2 0X108 ATXDRA_EI1_7_0 0x00 RO Transmitter A shift loader parameter 1 0 OX10C ATXDRA_EI1_15_8 0x00 RO Transmitter A shift loader parameter 1 1 0X110 ATXDRA_EI1_20_16 0x00 RO Transmitter A shift loader parameter 1 2 0X114 ATXDRT EI 70 0x00 RO Transmitter T shift loader parameter 1 0 0X118 ATXDRT EI1 158 0x00 RO Transmitter T shift loader parameter 1 1 OX11C ATXDRT_EI1_20 16 0x00 RO Transmitter T shift loader parameter 1 2 0X120 ATXDRP EI2 7 0 0x00 RO Transmitter P shift loader parameter 2 0 0X124 ATXDRP_EI2_15 8 0x00 RO Transmitter P shift loader parameter 2 1 0X128 ATXDRP EI2 20 16 0x00 RO Transmitter P shift loader parameter 2 2 OX12C ATXDRA_EI2_7_0 0x00 RO Transmitter A shift loader parameter 2 0 0X130 ATXDRA EI2 15 8 0x00 RO Transmitter A shift loader parameter 2 1 0X134 ATXDRA EI2 20 16 0x00 RO Transmitter A shift loader parameter 2 2 0X138 ATXDRT EI2 7 0 0x00 RO Transmitter T shift loader parameter 2 0 OX13C ATXDRT EI2 158 0x00 RO Transmitter T shift loader parameter 2 1 0X140 ATXDRT_EI2_20 16 0x00 RO Transmitter T shift loader parameter 2 2 0X144 OVERRIDE CALIB 0x00 RW Override calibration register 0X148 FORCE ATXDRR 7 0 0x00 RW Force receiver shift loader parameter 0 OX14C FORCE_ATXDRR_15_ 8 0x00 RW Force receiver shift loader parameter 1 0X150 FORCE ATXDRR 20 16 0x00 RW Force receiver shift loader parameter 2 0X154 FORCE
408. ock and reset network when using EPCS mode It describes the SERDES external register calibration in EPCS mode Configuring High Speed Serial Generator for EPCS Mode The high speed serial interface generator in the Libero SoC allows to configure the SERDESIF block in EPCS mode to control the setting of the three SERDESIF System registers Refer to Figure 4 2 and Figure 4 3 for EPCS mode setting in the high speed serial interface generator Protocol Selection Protocol 1 Type M Protocol 2 Type fe Protocol 1 Number of Lanes x4 Protocol 2 Number of Lanes 4 Protocol 1 Speed faser zl Protocol 2 Speed 4 Protocol 1 PHY Reference Clock 1 0 Porta v Protocol 2 PHY Reference Clock a Lane Assignment Protocol for Lane 0 EPCS z Protocol for Lane 1 za z Protocol for Lane 2 FG z Protocol for Lane 3 EPCS z Figure 4 2 EPCS Single Protocol Mode Setting in High Speed Serial Interface Generator Protocol Selection Protocol 1 Type fa 3 Protocol 2 Type es gt Protocol 1 Number of Lanes x2 X Protocol 2 Number of Lanes x2 v Protocol 1 Speed GEN 25 0 Gbps v Protocol 2 Speed f2 5cbps x Protocol 1 PHY Reference Clock 1 0 Porto ad Protocol 2 PHY Reference Clock 1 0 Port Lane Assignment Protocol for Lane 0 fa z Protocol for Lane 1 fa Y Protocol for Lane 2 z Protocol for Lane 3 z z Figure 4 3 e EPCS Multi Protocol Mode Setting in High Speed Serial Interface Generator 158
409. ode The bridge automatically computes the ASPM LOs exit latency based on these two register values and on the maximum payload size of the control register The selected NFTS field is that transmitted by the link training and status state machine LTSSM to the opposite component in order to define the number of FTS that the opposite component must send to be sure that the device receiver has re locked onto incoming data ASPM_LOS_GEN2 260h This register defines the endpoint LOs acceptable latency and the number of FTS required by the SERDES to resynchronize its receiver on incoming data depending on clock mode configuration separate clock or common clock at 5 0 Gbps The number of FTS required in separated clock mode must be higher than that required in common clock mode The bridge automatically computes the ASPM LOs exit latency based on these two register values and the maximum payload size of the control register The selected NFTS field is that transmitted by the LTSSM to the opposite component in order to define the number of FTS that the opposite component must send to be sure that the device receiver has re locked onto incoming data ASPM_L1_CAPABILITY 064h R W or RO This register defines the endpoint L1 acceptable latency and the number of FTS required The endpoint L1 acceptable latency is used to enable or disable ASPM L1 entry by comparing its value to the maximum ASPM L1 exit latency of all components in the hierarchy plus
410. odes PHY Logical Lanes Vs Logical Lanes Mode PCle protocol only mode PCle x4 PCle PCle PCle PCle MO LaneO Lane1 Lane2 Lane3 PCle x2 PCle PCle M1 LaneO Lane1 PCle x1 PCle 1 z M2 LaneO PCle Reversed mode x4 PCle PCle PCle PCle M3 Lane3 Lane2 Lane1 LaneO PCle Reversed mode x2 PCle PCle M4 Lane1 LaneO PCle Reversed mode x1 PCle 0 M5 PCle Reversed mode x2 PCle PCle M6 Lane01 LaneO PCle Reversed mode x1 PCle M7 LaneO XAUI only XAUI x4 lane XAUI 0 XAUI 1 XAUI 2 XAUI 3 M8 SGMII only SGMII M9 EPCS only All lanes are used for user EPCS EPCS EPCS EPCS M10 defined protocol Multi Protocol PCle and EPCS PCle x2 PCle PCle EPCS EPCS M11 SGMII or EPCS can be LaneO Lane01 supported on lane2 and lane3 ple x1 PCle A EPCS EPCS M12 LaneO PCle Reversed mode x2 PCle PCle EPCS EPCS M13 Lane01 LaneO PCle Reversed mode x1 PCIe EPCS EPCS M14 LaneO Notes 1 Lane Tx clk is used for laneO for PCIe protocol purposes 2 In multi protocol mode EPCS is available only on lane and lane3 16 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Serial Protocols Setting Using the SERDESIF System Registers The SERDESIF is configured to support various modes of operation This configuration of the protocols is through the SERDESIF system registers These registers are configured using the APB interface
411. of supporting multiple high speed serial protocols such as peripheral component interconnect express PCle 2 0 eXtended attachment unit interface XAUI and serial gigabit media independent interface SGMII In addition the SmartFusion2 SoC FPGA SERDESIF block is available as a standalone serialize and de serializer SERDES with the external physical coding sublayer interface EPCS interface available to the fabric to implement PCS logic in the fabric This allows any user defined high speed serial protocol to be implemented through the SmartFusion2 SoC FPGA field programmable gate array FPGA fabric The EPCS interface is available to the FPGA fabric and this has 20 bit transmit and 20 bit receive signals Any standard protocol or user defined serial protocol can be chosen to implement The SERDESIF block can be configured Single protocol mode where the EPCS interface can be configured as x4 lane or x2 The SERDESIF block can also be configured in Single protocol mode where only Lane2 and Lane3 are available for the EPCS interface and Lane1 and Lane2 are used for the PCle protocol link implementation Following are the main features of the EPCS interface in SmartFusion2 SoC FPGA 1 The SERDES lanes EPCS interface can be available to FPGA fabric to allow any serial protocol up to 4 lanes in the fabric 2 Each lane has 20 bit Rx Tx External PCS Interface 3 SERDES Tx PLL and Rx PLLs can be programmed 4 32 bit Advanced Peripheral Bus APB i
412. omplete self clearing 1 b1 Block reset 1 b0 Normal operation 14 Loopback 0x0 The XAUI extender block loops the transmit signal back into the receiver 1 b0 Disable loopback 1 b1 Enable loopback 13 Speed selection Ox1 This bit is speed selection bits and is set to 1 b1 in order to make compatible with clause 22 1 b0 Unspecified 1 b1 10 Gbs and above Any write to this bit will be ignored 12 Reserved 0x0 11 Low power mode 0x0 When set to 1 the SERDES block is placed in a Low power mode Set to 0 to return to normal operation 1 b0 Normal operation 1 b1 Low power mode 10 7 Reserved 0x0 Speed selection 0x1 This bit is set to 1 b1 in order to make compatible with clause 22 1 b0 Unspecified 1 b1 10 Gbs and above 5 2 Speed selection 0x0 The speed of the PMA PMD may be selected using bits 5 through 2 1 x x x Reserved x 1x x Reserved x x 1 x Reserved 000 1 Reserved 0000 10 Gb s Any write to this bit will be ignored 1 0 Reserved 0x0 Table 3 8 Depicts Definition of XS Status 1 Register Reg01 M XGXS PHY DTE XS Status 1 Bit Reset Number Name Value Description 15 8 Reserved 0x0 7 Fault 0x0 This bitis set if either the Tx or Rx fault bit is set in status register 2 03 07 1 b0 No fault detected 1 b1 Fault detected 6 3 Reserved 0x0 142 Revision 1 lt gt
413. on 15 0 PHY_REG_STATUS_OF_IN_DELAY_VALUE 0x0 15 0 bits of PHY REG STATUS OF IN DELAY VALUE The coarse and fine values going into the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 Table 7 197 PHY STATUS OF IN DELAY VAL 2 SR PHY STATUS OF IN DELAY VAL 2 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_OF_IN_DELAY_VALUE 0x0 26 16 bits of PHY_REG_STATUS_OF_IN_DELAY_VALUE The coarse and fine values going into the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 354 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_STATUS_OF_OUT_DELAY_VAL_1_SR Table 7 198 PHY STATUS OF OUT DELAY VAL 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_STATUS_OF_OUT_DELAY_VALUE 0x0 15 0 bits of PHY REG STATUS OF OUT DELA Y VALUE The coa
414. on 15 10 OUI 0x0 I Bits 19 24 of the OUI Bit 19 of the OUI is located in bit 15 of the register and bit 24 of the OUI is located in bit 10 of the register 9 4 Manufacturer model 0x0 Bits 5 0 of the manufacturer model number Bit 5 of the model number number is located in bit 9 of the register and bit 0 of the model number is located in bit 4 of the register 3 0 Revision number 0x0 Bits 3 0 of the manufacturer model number Bit 3 of the revision number is located in bit 3 of the register and bit 0 of the revision number is located in bit 0 of the register Table 3 11 Depicts Definition of XS Speed Ability Register Reg04 M XGXS PHY DTE XS Speed Ability Bit Reset Number Name Value Description 15 10 Reserved 0x0 9 4 10g capable 0x1 1 b0 Not 10g capable 1 b0 10g capable Revision 1 143 lt gt Microsemi XAUI Table 3 12 Depicts Definition of XS Devices in Package Low Register Reg05 M XGXS PHY DTE XS Devices in Package Low Bit Reset Number Name Value Description 15 6 Reserved 0x0 5 DTE XS present 0x1 1 b0 DTE XS not present in the package 1 b1 DTE XS present in the package 4 PHY XS present 0x0 1 00 PHY XS not present in the package 1 b1 PHY XS present in the package 3 PCS present Ox0 1 b0 PCS not present in the package 1 b1 PCS present in the package 2 WIS present Ox0 1 b0 WIS not present in the package 1 b1 WIS present in the
415. on PCIe 5G ig EPCS EPCS reversed mode PCle 5G PCle 5G EPCS EPCS B Multi protocol PCIe 2 5G EPCS EPCS PHY mode PCIe 2 5G PCIe 2 5G EPCS EPCS PCle link reversed PCle 5G EPCS EPCS mode PCle 5G PCle 5G EPCS EPCS Table 4 3 describes the EPCS interface usage in Single protocol mode Table 4 3 EPCS Interface and SERDES Lane Mapping in Single protocol Mode Single Protocol Lane0 Lane1 Lane2 Lane3 EPCS Mode EPCS _ 2 EPCS EPCS EPCS EPCS EPCS EPCS EPCS EPCS EPCS Note The link speed when configured as the EPCS interface is user defined Appropriate phase locked loop PLL settings define the link speed Refer to the Serializer Deserializer section on page 169 for setting the TX PLL and the RX PLL EPCS Implementation in SERDESIF Block The SmartFusion2 SoC FPGA SERDESIF block includes SERDES PCle system XAUI extender APB decoder and several glue logic blocks x2 EPCS INTERFACE PCle L2 P2 control etc The SERDES sub block includes the physical medium attachment PMA macro and physical coding sublayer PCS logic for PCle For further details refer to the Serializer Deserializer section on page 169 During the EPCS implementation the SERDES PCS logic is bypassed and the PMA interface is passed to the fabric via the x2 EPCS interface blocks 154 Revision 1 Figure 4 1 lt gt Microsemi SmartFusion2 SoC FPGA
416. on and External Resistor Configuration An external resistor is required for the PMA hard macro in order to perform an impedance calibration transmit receive and receiver equalization The external resistor input signal needs to be connected to the Rext input signal of the physical layer PHY This calibration is automatically performed by the PMA control logic after the reset de assertion and generally takes less than 100 us At the end of the calibration the PHY logic computes all the calibration logic parameters and applies the corresponding settings and automatically drives Electrical Idle 1 also called El1 on the transmit driver It requires another 100 us to physically establish the Electrical Idle condition The driving data on the link can only be performed when the initial calibration is completed and whatever the protocol the PMA hard macro is in El1 Tx driver state when this calibration is completed The end of the calibration is signaled by the PMA macro through the EPCS READY signal The SERDESIF System Register CONFIG REXT SEL register is used to select whether the calibration is performed by the PMA control logic at the lane or use the calibration result from the adjacent lane The SmartFusion2 SoC FPGA SERDESIF has 2 external resistors connected to LaneO and Lane2 Lane1 and Lane3 need to get calibrated using the register from adjacent lane Using this register each lane can be independently configured to use the calibr
417. on for Single Protocol Mode Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Protocol Selection Protocol 1 Type PCIe bd Protocol 2 Type EPCS p Multi protocol Mode PCle and EPCS gt Protocol 1 Number ofLanes 12 3 Protocol ber flanes e or Protocol 1 Speed GEN 2 5 0Gbps F Protocol 2 Speed 2 5 Gbps Protocol 1 PHY Reference Clock 1 0 Porto p Protocol 2 PHY Reference Clock 1 O Port v Lane Assignment ProtocolforLaneO PCIe z Protocol for Lane 1 Pcie z Protocol for Lane 2 EPCS z Protocol for Lane 3 JEPCS z Figure 1 9 e SERDESIF Configuration for Multi Protocol Mode Clocking and Reset This section describes the clocking and reset scheme for the SERDESIF block Clocking System for SERDESIF The clocking system in the SERDESIF block includes e SERDES reference clocks e Serial PLL SPLL clocking e PCle system block clocking e XAUI block clocking SERDES Reference Clocks The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock generation through PLLs Refer to the Serializer Deserializer section on page 169 for more information on Tx and Rx clock generation through PLLs In order to reduce the number of chip level I O pads there are only two reference clocks refcik io0 and refclk_io1 in the SmartFusion2 SoC FPGA devices coming from I O pads The two reference clocks refcik io0 and refclk_io1 are connected to I
418. opback test the transmit interface of the XAUI extender block is connected to the EPCS interface of the SERDES block In this case the SERDES block is put in the Loopback mode where serial data from transmit side is fed into the serial receive interface Apart from covering the transmit and receive block of XAUI extender it also tests the PMA data path validity The XAUI LOOPBACK_IN signal is used for this Loopback mode Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SmartFusion2 SoC FPGA XAUI Timing Diagram The following sections show the timing relations between clock and data for the three interfaces of the XAUI extender Each section discusses an interface in detail Refer to the SmartFusion2 SoC FPGA datasheet for the detail timing number Transmit Interface Figure 3 10 shows the XGMII transmit timing diagram The transmit data and control signals are source centered on the transmit clock per requirements of IEEE 802 3ae clause 46 Furthermore all four lanes of data are synchronous with a common clock xue TT TT TL TL XAUI TXD XAUI TXC XAUI TXD XAUI TXC Figure 3 10 Transmit XGMII Interface Timing Diagram Revision 1 139 I Microsemi XAUI Receive Interface Figure 3 11 shows the XGMII receive timing diagram The receive data and control signals are edge aligned with the receive clock rx cik To be fully compliant with IEEE 802 3ae the data
419. or read DQS slave DLL with this value PHY_RD_DQS_SLAVE_DELAY_3_CR Table 7 137 PHY RD DQS SLAVE DELAY 3 CR Bit Number Name Reset Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 REG_PHY_RD_DQS_SLAVE_DELAY 0x0 44 32 bits of REG_PHY_RD_DQS_SLAVE_DELAY If REG_PHY_RD_DQS_SLAVE_FORCE is 1 replace delay tap value for read DQS slave DLL with this value PHY_RD_DQS_SLAVE_FORCE_CR Table 7 138 PHY RD DQS SLAVE FORCE CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_RD_DQS_SLAVE_FORCE 0x0 1 Overwrite the delay tap value for read DQS slave DLL with the value of PHY_RD_DQS_SLAVE_DELAY Revision 1 331 I Microsemi MSS DDR Subsystem PHY_RD_DQS_SLAVE_RATIO_1_CR Table 7 139 PHY RD DQS SLAVE RATIO 1 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi
420. ory ARM Cortex M3 Microcontroller SD l AX Cache DDR Mea MBridge pr Controller Controller Controller lt p sa 5 A AHB Bus Matrix Figure 7 7 Accessing MDDR from Cortex M3 Processor 256 Revision 1 2 HPDMA to DDR SDRAM lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide HPDMA can access the DDR SDRAM connected to the MDDR subsystem through the MSS DDR bridge as shown in Figure 7 8 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS The read write and RMW transactions are initiated by the MSS DDR Bridge to read or write the data into the memory DDR SDRAM Controller Figure 7 8 Accessing MDDR from HPDMA Transaction Controller Revision 1 HPDMA 4 gt ARM Cortex M3 Microcontroller SD l Cache Controller S D IC AHB Bus Matrix 257 I Microsemi MSS DDR Subsystem 3 MSS Peripherals to DDR SDRAM The MSS peripherals which are connected to the AHB bus matrix can access the DDR SDRAM connected to the MDDR subsystem through the MSS DDR bridge as shown in Figure 7 9 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS The read write and RMW transactions are initiated by t
421. ot rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 FAB_PLL_LOCK 0x0 Indicates the lock status of the FPLL FDDR_FPLL_CLK_SR Table 8 17 FDDR FPLL CLK SR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 FPLL_LOCK 0x0 Indicates the lock status of the fabric PLL Revision 1 391 I Microsemi Fabric Double Data Rate Subsystem FDDR_INTERRUPT_SR Table 8 18 FDDR INTERRUPT SR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation DDR_FIC_INT 0x0 Indicates interrupt from DDR_FIC 3 IO CALIB INT 0x0 The interrupt is generated when the calibration is finished For the calibration after reset this typically would be followed by locking the codes directly For in between runs during functional operation of DDR the assertion of an interrupt does not guarantee lock because the state machine would wait for the ideal time DRAM self refresh for locking This can be used by firmwa
422. package 1 PMD PMA present Ox0 1 1 b0 PMD PMA not present in the package 1 b1 PMD PMA present in the package 0 Clause 22 register 0x0 1 b0 Clause 22 registers not present in the package present 1 b1 Clause 22 registers present in the package Table 3 13 Depicts Definition of XS Devices in Package High Register Reg06 M XGXS PHY DTE XS Devices in Package High Bit Reset Number Name Value Description 15 Vendor specific device2 0x0 1 b0 Vendor specific device 2 not present present 1 b1 Vendor specific device 2 present 14 Vendor specific device Ox0 1 1 b0 Vendor specific device 1 not present present 1 b1 Vendor specific device 1 present 13 0 Reserved 0x0 Table 3 14 Depicts Definition of XS Status 2 Register Reg07 M XGXS PHY DTE XS Status 2 Bit Reset Number Name Value Description 15 14 Device present 0x0 2 b10 Device responding at this address 2 b11 No device responding at this address 2 b01 No device responding at this address 2 b00 No device responding at this address 13 12 Reserved 0x0 11 Transmit fault 0x0 1 b0 No transmit fault 1 b1 Transmit fault Latched high clear on read 10 Receive fault 0x0 1 b0 No receive fault 1 b1 Receive fault Latched high clear on read 9 0 Reserved 0x0 144 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 3 15 Depicts Definitio
423. pad XAUI_MMD_ MDOE Output MDIO data output enable Used to control bidirectional pad It is active high XAUI MMD MDOE IN Input MDIO data output enable input Used to force mmd_mdi high in an idle state It is active high XAUI MMD PRTAD 4 0 Input Static signal that defines the port address of the XAUI extender block instantiated Access to the MDIO registers is granted only if the port address specified in the mdi stream matches this input XAUI MMD DEVID 4 0 Input Static signal that defines the device ID of the XAUI extender block instantiated Access to the MDIO registers is granted only if the device id DEVID specified in the mmd m i stream matches this input For the PHY XS this value should be 04h For the DTE XS this value should be 05h Revision 1 147 I Microsemi XAUI Table 3 23 SmartFusion2 SoC FPGA XAUI Extender Block MDIO Interface continued Port Type Description XAUI VNDRRESLO 31 0 Output General purpose register for vendor use reset low The output of two 16 bit registers address 0x8000 and 0x8001 that are set low on reset for general purpose use XAUI_VNDRRESHI 31 0 Output General purpose register for vendor use reset high The output of two 16 bit registers address 0x8002 and 0x8003 that are set high on reset for general purpose use Table 3 24 SmartFusion2 SoC FPGA XAUI Extender Block XGMII Transmit Interface Signal Port Type Descript
424. posted header requests that are received 256 256 bytes e Posted data credit of 64 credits with 16 bytes for each credit 512 bytes The total is 128 x 4 completion data 256 posted header 256 non posted header 512 posted data to get the receive buffer size Note that this is less than 2 KBytes SmartFusion2 SoC FPGA PCIe Power Management This section describes the power management scheme in SmartFusion2 SoC FPGA PCIe implementation Power Domain Implementation In SmartFusion2 SoC FPGA devices the FPGA and PCle link including PMA PCS and PCle controller are combined in a single chip so they have a separate power supplies Figure 2 18 shows the SmartFusion2 SoC FPGA power rails PCIExVDD PCIExVDDIO a PCle PCS PCle System FPGA Fabric Logic LaneO MA Pcie Pes Logic Lane0 ge Signals Logic PMA PMA Macro Control ney Block Logic PMA PMA Macro Control hie ao Block Logic Figure 2 18 SmartFusion2 SoC FPGA Power Supply to the PCle Link implementation Revision 1 79 lt gt Microsemi PCI Express Legacy Power Management The PCle bridge register space defines the capabilities of the PCle bridge in term of legacy power management PME support auxiliary current requirement etc In addition the Power Management Control and Status register displays the current power management state The PM data and PM scale value array can define the power consumed in each power state Refer to the PCl
425. quires changing ODT settings 01 Block read write scheduling for 2 cycles when write requires changing ODT settings 10 Block read write scheduling for 3 cycles when write requires changing ODT settings 11 Reserved Revision 1 285 I Microsemi MSS DDR Subsystem Bit Number DDRC_ADDR_MAP_COL_3_CR Table 7 49 DDRC_ADDR_MAP_COL_3_CR Name Reset Value Description 31 16 7 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 12 11 8 REG DDRC ADDRMAP COL B5 REG DDRC ADDRMAP COL B6 0x0 0x0 Full bus width mode Selects column address bit 6 Half bus width mode Selects column address bit 7 Quarter bus width mode Selects column address bit 8 Valid range 0 to 7 Internal base 5 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field Full bus width mode Selects column address bit 7 Half bus width mode Selects column address bit 8 Quarter bus width mode Selects column address bit 9 Valid range 0 to 7 Internal base 6 The selected address bit for each of the column address bits is determined by adding the internal base to the value of this field REG DDRC DIS WC 0x0 When 1 disable write combine
426. r Revision 1 315 I Microsemi MSS DDR Subsystem Table 7 100 PHY Configuration Register Summary continued Reset Register Name Offset Type Source Description PHY_GATELVL_INIT_RATIO_1_CR 0x270 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 2 CR 0x274 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 3 CR 0x278 RW PRESET NlInit ratio value configuration register PHY GATELVL INIT RATIO 4 CR 0x27C RW PRESET NIlInit ratio value configuration register PHY LOCAL ODT CR 0x280 RW PRESET N PHY ODT control register PHY INVERT CLKOUT CR 0x284 RW PRESET N PHY DRAM clock polarity change register PHY RD DQS SLAVE DELAY 1 CR 0x288 RW PRESET N Delay value for read DQS PHY RD DQS SLAVE DELAY 2 CR 0x28C RW PRESET N Delay value for read DQS PHY RD DQS SLAVE DELAY 3 CR 0x290 RW PRESET N Delay value for read DQS PHY RD DQS SLAVE FORCE CR 0x294 RW PRESET Nl Overwriting delay value selection reg for read DQS PHY RD DQS SLAVE RATIO 1 CR 0x298 RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 2 CR 0x29C RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 3 CR Ox2A0 RW PRESET N Ratio value for read DQS slave DLL PHY RD DQS SLAVE RATIO 4 CR 0x2A4 RW PRESET N Ratio value for read DQS sla
427. r Table 5 141 SmartFusion2 SoC FPGA SERDES Block External PCS Signal Interface continued EPCS 0 RX VAL Output PHY receive valid This signal is used to signal receive valid data It corresponds EPCS 1 RX VAL to the two conditions completed by the PMA control logic EPCS 2 RX VAL e Receiver detects incoming data not in electrical idle EPCS 3 RX VAL e CDR PLL is locked to the input bitstream in fine grain state EPCS 0 RX IDLE Output PHY Receive Idle This signal is used to signal an electrical idle condition EPCS 1 RX IDLE detected by the PMA control logic Note that this signal is generated on EPCS 2 RX IDLE EPCS X TX CLK of the selected lane EPCS 3 RX IDLE EPCS 3 RXDATA 19 0 Output PHY receive data This signal is always 20 bits per lane and the external PCS EPCS 1 RXDATA 19 0 can use any number of these bits for its application based on the aRXN 4 0 EPCS 2 RXDATA 19 0 feature of the PMA macro see register space for more details EPCS 3 RXDATA 19 0 Note X 0 1 23 232 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Glossary CDR Clock data recovery PCS Physical coding sublayer PHY Physical interface PIPE PHY interface for the PCI Express architecture v2 00 specification PMA Physical media attachment PRBS Pseudo random bit sequence SERDES Serializer deserializer SERDESIF Serializer deserializer interface Revi
428. r 114h Table 2 85 AXI MASTER WINDOW1 1 Bit Name bea Description Number Value 31 12 AXI MASTER WINDOW11 31 12 Size of AXI master window 1 11 1 AXI MASTER WINDOW11 31 12 Reserved 0 AXI MASTER WINDOW11 0 Enable bit of AXI master window 1 Revision 1 lt gt Microsemi PCI Express AXI_MASTER_WINDOW1 2 Register 118h Table 2 86 AXI MASTER WINDOW1 2 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW12 31 12 LSB of base address PCle window 1 11 5 AXI MASTER WINDOW12 11 5 Reserved 5 0 AXI MASTER WINDOW12 50 These bits set the BAR To select a BAR set the following values 0x01 BARO 32 bit BAR or BARO 1 64 bit BAR 0x02 BAR1 32 bit BAR only 0x04 BAR2 32 bit BAR or BAR2 3 64 bit BAR 0x08 BAR3 32 bit BAR only 0x10 BAR4 32 bit BAR or BAR4 5 64 bit BAR 0x20 BARS 32 bit BAR only AXI_MASTER_WINDOW1 3 Register 11Ch Table 2 87 AXI MASTER WINDOW1 3 Bit Reset Number Name Value Description 31 0 AXI MASTER WINDOW13 31 12 MSB of base address PCIe window 1 AXI MASTER WINDOW2 0 Register 120h Table 2 88 AXI MASTER WINDOW2 0 Bit Reset Number Name Value Description 31 12 AXI MASTER WINDOW20 31 12 Base address AXI master window 2 11 0 Reserved Reserved AXI MASTER WINDOWO 1 Register 124h Table 2 89 AXI MASTER WINDOW2 1 Bit Reset Numb
429. r upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system Revision 1 303 I Microsemi MSS DDR Subsystem DDRC_LUE_SYNDROME_3_SR Table 7 81 DDRC LUE SYNDROME 3 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC REG ECC SYNDROMES 0x0 47 32 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CR is written over by the system 304 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s
430. r SATA OOB lepcs 2 tx oob Input Fabric EPCS interface Lane2 transmit idle needed for SATA OOB lepcs 3 tx oob Input Fabric EPCS interface Lane3 transmit idle needed for SATA OOB lepcs 0 rx err Input Fabric EPCS interface Lane0 receiver error detected lepcs 1 rx err Input Fabric EPCS interface Lane1 receiver error detected lepcs 2 rx ert Input Fabric EPCS interface Lane2 receiver error detected lepcs 3 rx err Input Fabric EPCS interface Lane3 receiver error detected lepcs 0 rESET N Input Fabric EPCS interface LaneO reset epos 1 rESET N Input Fabric EPCS interface Lane1 reset epos 2 rESET N Input Fabric EPCS interface Lane2 reset lepcs 3 rESET N Input Fabric EPCS interface Lane3 reset lepcs 0 ready Output Fabric EPCS interface LaneO PHY training completed lepcs 1 ready Output Fabric EPCS Interface Lane1 PHY training completed lepcs 2 ready Output Fabric EPCS interface Lane2 PHY training completed lepcs 3 ready Output Fabric EPCS interface Lane3 PHY training completed lepcs 0 rxdata 19 0 Output Fabric EPCS interface LaneO received data from the SERDES PMA lepcs 1 rxdata 19 0 Output Fabric EPCS interface Lane1 received data from the SERDES PMA Revision 1 165 lt gt Microsemi EPCS Interface Table 4 8 e SERDESIF Block EPCS Interface continued Port Type Connected to Description lepcs 2 rxdata 19 0 Fabric EPCS interface Lane2 received
431. r each possible power state defined by the PCI power management specification used in conjunction with the PM scale field PM DATA SCALE 1 Register 074h Table 2 45 PM DATA SCALE 1 Bit Number Name Reset Value Description 31 24 PM DATA SCALE 1 31 24 These bits set the register that defines Data7 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 23 16 PM DATA SCALE 1 23 16 These bits set the register that defines Data6 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 15 8 PM DATA SCALE 1 15 8 These bits set the register that defines Data5 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 7 0 PM DATA SCALE 170 These bits set the register that defines Data4 of the PM data value of the device for each possible power state defined by the PCI power management specification used in conjunction with the PM scale field 98 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PM_DATA_SCALE 2 Register 078h Table 2 46 PM DATA SCALE 2
432. r laneO and lane1 as reference clock 10 Selects ccc_ref_clk clock for laneO and lane1 as reference clock 11 Selects fab_ref_clk clock for laneO and lane as reference clock Reg68 PCLK_SEL Register 0x2068 Table 1 36 PCLK_SEL Bit Number Name Reset Value Description 5 4 PIPE_PCLKIN_LANE23_SEL 0x0 PIPE clock input selection for lane2 and lane3 can be selected from one of pipeclk_out 3 0 00 Selects pipeclk_out 0 clock as pipeclk_in for lane2 and lane3 01 Selects pipeclk_out 1 clock as pipeclk_in for lane2 and lane3 10 Selects pipeclk_out 2 clock as pipeclk_in for lane2 and lane3 11 Selects pipeclk_out 3 clock as pipecik in for lane2 and lane3 3 2 PIPE PCLKIN LANEO1 SEL 0x0 PIPE clock input selection for lane0 and lane1 can be selected from one of pipeclk_out 3 0 00 Selects pipeclk_out 0 clock as pipeclk_in for laneO and lane1 01 Selects pipeclk_out 1 clock as pipeclk_in for laneO and lane1 10 Selects pipeclk_out 2 clock as pipeclk_in for laneO and lane1 11 Selects pipeclk_out 3 clock as pipecik in for laneO and lane1 1 0 PCIE_CORECLK_SEL 0x0 PCle core clock selection PCle core clock can be selected from one of pipecik out 3 0 00 Selects pipecik out 0 clock as PCle core clock 01 Selects pipecik out 1 clock as PCle core clock 10 Selects pipeclk_out 2 clock as PCle core clock 11 Selects pipeclk_out 3 clock as PCle cor
433. r range of frequency acquisition 5000 ppm of static frequency difference This step is always a transient step before embarking on fine phase lock Fine phase lock which has a lower range of frequency acquisition 300 ppm static frequency difference Figure 5 8 shows CDR locking CDRPLL in Lock if Frequency Lock Phase Lock coarse Phase Lock fine Serial Data Present 5 us i 0 5 us i 0 25 us i x ae YY a i Oi from cold start reset aCDRDiaglIn 0 aCDRDiaglin 1 aCDRDiaglin 1 aCDRDiagln 1 aRxFDIp 1 0 i aRxFDIp 1 0 aRxFDIp 1 1 i aRxFDIp 1 1 gt r i 0 5 us Start Frequency from FD prompt Detection If and when frequency difference exceeds preset threshold go back to frequency acquisition Figure 5 8 CDR Bit Locking 178 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Bit 3 of the SERDES_TEST_OUT register in the SERDESIF block also known as CDR PLL locked on data aCDRDiagOut indicates the current state of the internal frequency detector Bit 5 of the SERDES TEST OUT register in the SERDESIF block also known as CDR PLL locked aRXCIkStable indicates when CDR is locked However note that the non assertion of aCDRDiagOut or the assertion of aRXClkStable do not indicate lock to the bitstream They indicate that the CDR PLL frequency is not grossly o
434. r to hiZ applying a static one to the PMA aForceRXHiZ signal 0 TX_HIZ When set this signal forces the TX driver to hiZ applying a static one to the PMA aForceTXHiZ signal Note This register can be programmed any time but has functional impact on the SERDES because it can put the PLL under reset or place part of the SERDES in low power mode bypassing the functional mode PHY_POWER_OVERRIDE Register Table 5 106 PHY POWER OVERRIDE Bit Reset Number Name Value Description 7 1 Unused 0 RX PWRDN This register when set forces the RX PMA logic to be in power down mode Note This register can be programmed any time but has functional impact on the SERDES because it can power down the receiver part of the SERDES bypassing the functional mode 216 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide CUSTOM_PATTERN_7_0 Register Table 5 107 CUSTOM PATTERN 70 Bit Reset Number Name Value Description 7 0 RX PWRDN 7 0 This register enables bit 7 to bit 0 to program a custom pattern instead of the implemented PRBS generator checker The PRBS mode must still be selected to transmit this custom pattern on the transmit line but this mode enables the generation of any repeated sequence of data It can be used for instance for single lane PCle compliance pattern generation for the purpose of an eye diagram compliance check or can even be
435. re to insert the ideal time and provides an indication that locked codes are available 2 FDDR_ECC_INT 0x0 Indicates when the ECC interrupt from the FDDR subsystem is asserted 1 PLL_LOCKLOST_INT 0x0 This bit indicates that a falling edge event occurred on the MPLL_LOCK signal This indicates that the MPLL lost lock 0 PLL_LOCK_INT 0x0 This bit indicates that a rising edge event occurred on the MPLL_LOCK signal This indicates that the MPLL came into lock Table 8 19 FDDR_IO_CALIB_SR FDDR_IO_CALIB_SR Bit Reset Number Name Value Description 31 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 14 CALIB_PCOMP 0x01 The state of the P analog comparator 13 CALIB_NCOMP 0x01 The state of the N analog comparator 12 7 CALIB_PCODE Ox3F The current PCODE value set on the FDDR DDR I O bank 6 1 CALIB NCODE Ox3F The current NCODE value set on the FDDR DDR I O bank 0 CALIB_STATUS 0x0 This is 1 when the codes are actually locked For the first run after reset this would be asserted 1 cycle after calib_intrpt For in between runs this would be asserted only when the DRAM is put into self refresh or there is an override from the firmware calib_lock Table 8 20 FDDR_FATC_RESET FDDR_FATC_RESET Bit Reset Number Name Value Des
436. refer to the MDDR Configurator User s Guide DDR_FIC converts the single dual 32 bit AHBL master transactions from the FPGA fabric to 64 bit AXI transactions towards the AXI Transaction controller When single or dual AHB interfaces to the FPGA fabric is selected the DDR bridge embedded as part of the DDR_FIC is enabled Refer to the DDR Bridge section on page 395 for a detailed description If the AXI interfaces to the FPGA fabric is selected the DDR FIC acts as an AXI to AXI synchronous bridge to synchronize the transactions from master to FDDR The DDR_FIC input interface is clocked by the FPGA fabric clock and MDDR is clocked by MDDR_CLK from the MSS clock conditioning circuit CCC Configuration inputs DIVISOR_A 1 0 and DDR FIC DIVISOR 2 0 from the SYSREG block are combined to select a clock ratio between the fabric clock and AXI DDR clock Clock ratios supported are shown in Table 7 4 Table 7 4 e MDDR CLK to FPGA Fabric Clock Ratios DIVISOR_A 1 0 DDR_FIC_DIVISOR 2 0 MDDR_CLK FPGA FABRIC Clock Ratio 0x0 1 1 0x1 2 1 0x2 4 1 0x4 8 1 0x5 16 1 0x8 2 1 0x9 4 1 OxA 8 1 OxC 16 1 0x18 3 1 0x19 6 1 Ox1A 12 1 Default 1 1 Revision 1 241 I Microsemi MSS DDR Subsystem 64 Bit AXI Bus from MSS DDR Bridge 64 Bit AXI Bus from DDR_FIC AXI Transaction Controller The AXI transaction controller block is responsible for receiving AXI transactions from various mas
437. reset deasserted on EPCS_1_RX_CLK EPCS 2 RX RESET N Output EPCS interface LaneO reset deasserted on EPCS 2 RX CLK EPCS 3 RX RESET N Output EPCS interface LaneO reset deasserted on EPCS 3 RX CLK EPCS 0 TX RESET N Output EPCS interface LaneO reset deasserted on EPCS_0_TX_CLK EPCS_1_TX_RESET_N Output EPCS interface LaneO reset deasserted on EPCS_1_TX_CLK EPCS 2 TX RESET N Output EPCS interface LaneO reset deasserted on EPCS 2 TX CLK EPCS 3 TX RESET N Output EPCS interface LaneO reset deasserted on EPCS 3 TX CLK APB S PRESET N Input APB slave interface PRESETN Async set 24 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 1 8 e SERDESIF Block Reset Signals continued Protocol Reset signals Direction Description XAUI SERDESIF_PHY_RESET_N Input PHY RESET N CORE RESET N Input External asynchronous global hard XAUI MDC RESET OUT Output Management data controller MDC synchronous reset XAUI MDC RESET Input jAsynchronously resets all the MDIO registers to their default values XAUI TX RESET OUT Output Software generated reset register 0 15 synchronized with tx_clk XAUI_TX_RESET Input Resets the tx_core block XAUI_RX_RESET_ OUT 3 0 Output Software generated resets register 0 15 synchronized with the rx_clkiX X 01 2 3 clocks XAUI RX RESET 3 0 Input Resets the XAUI extender block APB_S_PRESET_N Input APB slave inter
438. resh cycle is required to any rank in the system e The controller receives a new request from the core logic REG DDRC POWERDOWN EN is set to 0 To exit precharge power down the controller does the following 1 Inserts any NOP Deselect commands required to satisfy the tCKE requirement after entering precharge power down 2 Issues the power down exit command NOP Deselect with CKE 1 For multi rank systems all chip selects are asserted so that all ranks will exit precharge power down simultaneously 3 Issues NOP Deselect for the period defined by tXP Self Refresh The controller keeps the DDR SDRAM device s in self refresh mode whenever the REG DDRC SELFREF EN bit is set and no reads or writes are pending in the controller The controller can be programmed to issue single refreshes at a time REG DDRC REFRESH BURST 0 to minimize the worst case impact of a forced refresh cycle It can be programmed to burst the maximum number of refreshes allowed for DDR2 REFRESH BURST 7 for performing 8 refreshes at a time to minimize the bandwidth lost to closing the pages for refresh Entering self refresh mode involves the following steps 1 Precharging closing all open pages Pages are closed one at a time in no specified order 2 Waiting for the tRP row precharge idle period 3 Issuing the command to enter self refresh mode asserting RAS and CAS with CKE 0 For multi rank systems all chip selects are asserted so tha
439. reshes are forced to execute Closing pages to perform a refresh is a one time penalty that must be paid for each group of refreshes therefore performing refreshes in a burst reduces the per refresh penalty of these page closings Higher numbers for burst_of_N_refresh slightly increases utilization lower numbers decreases the worst case latency associated with refreshes 0x0 Single refresh 0x1 Burst of 2 0x7 Burst of 8 refresh DDRC_DYN_POWERDOWN_CR Table 7 23 DDRC DYN POWERDOWN CR Bit Number Reset Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation REG_DDRC_POWERDOWN_EN 0x1 If true the controller goes into power down after a programmable number of cycles REG DDRC POWERDOWN TO X32 This register bit may be reprogrammed during the course of normal operation REG DDRC DEEPPOWERDOWN EN 0x0 1 Controller puts the DRAM into deep power down mode when the transaction store is empty 0 Brings controller out of deep power down mode Present only in designs that have mobile support Revision 1 271 I Microsemi MSS DDR Subsystem DDRC_DYN_DEBUG_CR Table 7 24 DDRC DYN DEBUG CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should
440. ridge Configuration Registers continued Byte Register Offset Description K CNT CONFIG 0 300h RO or R W This register enables the configuration of default control settings K CNT CONFIG 1 304h RO or R W This register enables the configuration of default control settings K CNT CONFIG 2 308h RO or R W This register enables the configuration of default control settings K CNT CONFIG 3 30Ch RO or R W This register enables the configuration of default control settings K CNT CONFIG 4 310h RO or R W This register enables the configuration of default control settings K CNT CONFIG 5 314h RO or R W This register enables the configuration of default control settings ERROR COUNTER 0 OAOh RO or R W This register has four 8 bit counters for the four error sources To clear the register content the bridge must perform a write transaction any value to the register ERROR_COUNTER 1 OA4h RO or R W This register has four 8 bit counters for the four error sources To clear the register content the bridge must perform a write transaction any value to the register ERROR_COUNTER 2 OA8h RO or R W This register has four 8 bit counters for the four error sources To clear the register content the bridge must perform a write transaction any value to the register ERROR COUNTER 3 OACh RO or R W This register has four 8 bit counters for the four error sources To clear the register content the brid
441. ription 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 0 REG_PHY_CTRL_SLAVE_DELAY 0x0 If REG_PHY_RD_DQS_SLAVE_FORCE is 1 replace delay tap value for address command timing slave DLL with this value PHY_DATA_SLICE_IN_USE_CR Table 7 113 PHY DATA SLICE IN USE CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 REG_PHY_DATA_SLICE_IN_USE 0x0 Data bus width selection for read FIFO RE generation One bit for each data slice 1 Data slice is valid 0 Read data responses are ignored Note The PHY data slice 0 must always be enabled PHY_LVL_NUM_OF_DQ0_CR Table 7 114 PHY_LVL_NUM_OF_DQ0_CR Bit Reset Number Name Value Description 31 8 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 4 REG_PHY_GATELVL_NUM_OF_DQO 0x0 This register value determines the number of samples for dq0 in for each ratio increment by the gate training FSM NUM_OF_ITERATION
442. rly shifting is required for a particular DQ bit when REG PHY BIST MODE is 10 1 PRBS pattern shifted early by 1 bit 0 PRBS pattern without any shift PHY LOOPBACK TEST CR Table 7 108 PHY DYN LOOPBACK CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG PHY LOOPBACK 0x0 Loopback testing 1 Enable 0 Disable Revision 1 321 I Microsemi MSS DDR Subsystem PHY_BOARD_LOOPBACK_CR Table 7 109 PHY BOARD LOOPBACK CR Bit Reset Number Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 9 5 REG PHY BOARD LPBK TX 0x0 External board loopback testing 1 This slice behaves as a transmitter for board loopback 0 Default This port must always be set to 0 except when in external board level loopback test mode 4 0 REG_PHY_BOARD_LPBK_RX 0x0 External board loopback testing 1 This slice behaves as a receiver for board loopback 0 Disable This port must always be set to 0 except when in external board level loopback test mode PHY_CTRL_SLA
443. ror command 82Ch Root error status 830h Error source identification register Correctable error source ID register 834h 126 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Glossary Acronyms AXI Advanced extensible interface EP Endpoint PCI Express Peripheral component interconnect express PCle PCI Express SERDES Serializer deserializer SERDESIF Serializer deserializer interface XAUI Extended attachment unit interface Revision 1 127 lt gt Microsemi 3 XAUI The SERDESIF block can be configured to support the 10 Gigabit attachment unit interface XAUI protocol Figure 3 1 shows the XAUI implementation in SmartFusion2 SoC FPGA devices The SERDESIF block provides the XGXS functionality The XAUI extender block connects a 10Gb Ethernet MAC to SERDES physical medium attachment PMA logic In addition the XAUI extender block has a management data input output MDIO interface allowing MDIO manageable device to program the MDIO registers SERDES O PADS SERDES PMA only SERDESIF Block X2 EPCS Interface X2 EPCS Interface EPCS En Be x4 Lane SERDESIF System Register APB Slave Interface FABRIC Figure 3 1 XAUI Implementation in SmartFusion2 SoC FPGA XAUI Extender XGMII Interface MDIO Master Interface Table 3 1 shows the options for implementing XAUI on 4 physical SERDES lanes Tab
444. rs 8 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide The advantage of being able to connect the FPGA logic and the SERDESIF blocks is that it allows multiple serial protocols in the SmartFusion2 SoC FPGA devices Figure 1 3 shows implementation of PCIe XAUI and SGMII protocols using the SERDESIF block and FPGA fabric Application Layer lt lt Transaction Layer MAC Layer Transaction Layer MAC and Control MAC and Control Data Link Layer CRC Control DLLP Reconciliation z oO gt oO se fy eee eee Framing n ee XAUI State Machine Link Width and Lane AKR Translation Negotiation MAC Layer Reconciliation CRC Generation and Checking Link Training and Status Clock Tolerance Compensation GbE State Machine Auto Negotiation Physical Coding Sublayer PCS Scrambling 5 Descrambling KE Q gt Channel Alignment Clock Tolerance aI DA Compensation Clock Tolerance 9 Compensation 3 om 2 2 a S n Channel Alignment gt xa 8b 10b 8b 10b 8b 10b Word Alignment Word Alignment Link Sync Link Sync Word Alignment Link Sync Ea Ex 25 32 ge HS PMA SERDES PMA SERDES amp PMA SERDES 2 87 Be gg 2S o 2s aa ag MDI MDI PCle Express XAUI SGMII Figure 1 3 Serial Protocol Using SERDESIF and
445. rse and fine values coming out of the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 PHY_STATUS_OF_OUT_DELAY_VAL_2_SR Table 7 199 PHY STATUS OF OUT DELAY VAL 2 SR Bit Reset Number Name Value Description 31 11 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 10 0 PHY_REG_STATUS_OF_OUT_DELAY_VALUE Ox0 26 16 bits of PHY REG STATUS OF OUT DELAY VALUE The coarse and fine values coming out of the output filter in the master DLL This is a 27 bit register 9 bits for each DLL coarse 6 0 fine 1 0 Revision 1 355 I Microsemi MSS DDR Subsystem PHY_DLL_LOCK_AND_SLAVE_VAL_SR Table 7 200 PHY_DLL_LOCK_AND_SLAVE_VAL_SR Bit Number Reset Name Value Description 31 10 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PHY_REG_STATUS_PHY_CTRL_DLL_LOCK 0x0 PHY_CTRL Master DLL Status bits 1 Master DLL is locked 0 Master DLL is not locked 8 0 PHY_REG_STATUS_PHY_CTRL_DLL_SLAVE_VALUE 0x0 Shows the current coarse and fine delay value going to the
446. rts the DDR controller instructions into the actual timing relationships and DDR signaling necessary to communicate with the memory device Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide The read write transactions to the DDR memories connected to the MDDR subsystem can be done through four different paths 1 The Cortex M3 processor can access the DDR memories connected to the MDDR subsystem through the MSS DDR Bridge for data and code execution 2 High performance direct memory access HPDMA can perform the high speed data transactions between the MDDR memories and a memory region within the MSS via the MSS DDR bridge 3 The connection between the MSS DDR bridge and AHB bus matrix facilitates the MSS masters in accessing DDR memory 4 The MDDR subsystem can be connected to AXI or AHBL masters in the FPGA fabric through the DDR_FIC If the MDDR subsystem is configured in SMC_FIC mode to connect a soft memory controller in the FPGA fabric to the MSS DDR bridge then the connection between MDDR and the MSS DDR bridge will not exist The MSS masters can access the external memory connected to the soft memory controller through the MSS DDR Bridge For more details about SMC_FIC mode refer to the Soft Memory Controller Fabric Interface Controller section on page 407 Memory Configurations The SmartFusion2 SoC FPGA MDDR subsystem supports a wide range of common memory types configurations
447. s PHY BIST ERROR 3 SR Table 7 176 PHY BIST ERROR 3 SR Bit Reset Number Name Value Description 31 13 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 12 0 PHY REG BIST ERR 0x0 44 32 bits of PHY_REG_BIST_ERR Mismatch error flag from the BIST checker 1 Pattern mismatch error 0 All patterns matched This is a sticky flag In order to clear this bit the REG_PHY_BIST_ERR_CLR port must be set High The bits 8 0 are used for Slice 0 bits 17 9 for slice 1 and so on The MSB in each slice is used for Mask Bit and lower bits are for DQ bits PHY_WRLVL_DQS_RATIO_1_SR Table 7 177 PHY WRLVL DQS RATIO 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 PHY_REG_WRLVL_DQS_RATIO 0x0 15 0 bits of PHY REG WRLVL DQS RATIO Ratio value generated by the write leveling FSM for write DQS Revision 1 347 I Microsemi MSS DDR Subsystem PHY_WRLVL_DQS_RATIO_2_SR Table 7 178 PHY WRLVL DQS RATIO 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0
448. s SER_SOFT_RESET 0x08 R W PCle controller XAUI and SERDES lanes soft RESET SER_INTERRUPT_ENABLE 0x0C R W SERDES PLL lock interrupt enable CONFIG AXI AHB BRIDGE 0x10 R W Defines whether AXI AHB master interface is implemented on the master interface to fabric CONFIG_ECC_INTR_ENABLE 0x14 R W Sets ECC enable and ECC interrupt enable for PCle memories Reserved 0x18 R W Reserved Reserved Ox1C R W Reserved CONFIG PCIE PM Ox 20 R W Used to inform the configuration space the slot power PHY reference clock Power mode etc Note Refer to the individual register description for the reset value Note R W Read and write allowed R O 0 Read only Revision 1 27 I Microsemi SERDESIF Block Table 1 9 e SERDESIF System Registers continued Address Register Register Name Offset Type Description CONFIG PHY MODE 0 0x24 R W Selects the protocol default settings of the PHY CONFIG_PHY_MODE_1 Ox 28 R W Selects PCS mode link to lane settings CONFIG_PHY_MODE_2 Ox2C R W Sets the equalization calibration performed by the PMA control logic of the lane or use the calibration result of adjacent lane CONFIG PCIE 0 0x30 R W Defines PCle vendor ID and device ID for PCle identification registers CONFIG PCIE 1 0x34 R W Defines PCle subsystem vendor ID and subsystem device ID for PCl
449. s Guide Figure 2 12 shows SPLL settings in the high speed serial interface generator The SPLL configuration fields are described below e CLK_BASE Frequency MHz The valid range for the PCle protocol is 20 to 200 MHz Supply Voltage it is to specify the SPLL core supply voltage to be either 2 5 V or 3 3 V This selection does not impact the SPLL frequency range See the Microsemi SmartFusion2 SoC FPGA Datasheet for more details on the PLL power supply requirement Lock Delay The number of REFCLK clock cycles can be set by which the lock is delayed after the SPLL has reached the lock condition PCIe XAUI Fabric SPLL Configuration CLK_BASE Frequency MHz 166 Supply Voltage 2 5v Lock Delay 32 cycles z Lock Window 64000 ppm v Figure 2 12 e SPLL Clocking Configuration Using High Speed Serial Interface Generator The SERDESIF system register can also be used to configure and to use this PLL Figure 2 6 summarizes the various clocks in PCle mode Table 2 6 Clock Signals in PCle Mode Clock Signal Description REFCLK 100 Reference clock for SERDES PMA REFCLK 101 Reference clock for SERDES PMA CCC REF CLK Reference clock for SERDES PMA FAB REF CLK Reference clock for SERDES PMA CLK BASE Fabric source clock This is the reference clock for the SPLL PLL ACLK PLL output clock used as the AXI AHB bridge clock PLL SERDESIF REF Reference clock for the SPLL APB_S_PCLK PCLK for APB interfa
450. s exit latency for separate clock 6 4 ASPM LOS CAPABILITY 64 LOs exit latency for common clock 3 1 ASPM LOS CAPABILITY 3 1 Endpoint LOs acceptable latency 0 ASPM LOS CAPABILITY 0 Reserved ASPM L1 CAPABILITY Register 064h Table 2 40 ASPM L1 CAPABILITY Bit Reset Number Name Value Description 31 24 ASPM L1 CAPABILITY 31 24 NFTS COMCLK in common clock mode at 5 0 Gbps 23 16 ASPM L1 CAPABILITY 23 16 NFTS_SPCLK in separated clock mode at 5 0 Gbps 15 4 ASPM L1 CAPABILITY 15 4 Reserved 3 0 ASPM L1 CAPABILITY 3 0 Number of electrical idle exit EIE symbols sent before transmitting the first FTS 96 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TIMEOUT_COMPLETION Register 068Ch Table 2 41 TIMEOUT COMPLETION Bit Reset Number Name Value Description 31 4 TIMEOUT COMPLETION 31 4 Reserved 3 0 TIMEOUT COMPLETION 3 0 This register defines four timeout ranges for the completion timeout mechanism Bits are set as given below to show timeout value ranges supported 0000 Completion timeout programming not supported the function must implement a timeout value in the range 50 us to 50 ms 0001 Range A 0010 Range B 0011 Ranges A and B 0110 Ranges B and C 0111 Ranges A B and C 1110 Ranges B C and D 1111 Ranges A B C and D All other values are reserved Completion timeout range support
451. s long as EPCS_X_READY is not asserted This signal is must be generated one clock cycle earlier than corresponding EPCS_TXDATA signals EPCS 2 TX DATA 19 0 aTXN 4 0 feature of the PMA macro EPCS 3 TX DATA 19 0 EPCS 0 TX CLK EPCS 1 TX CLK EPCS 2 TX CLK EPCS 3 TX CLK EPCS 0 TX RESET N EPCS 1 TX RESET N EPCS 2 TX RESET N EPCS 3 TX RESET N EPCS 0 RX CLK EPCS 1 RX CLK EPCS 2 RX CLK EPCS 3 RX CLK EPCS 0 RX RESET N EPCS 1 RX RESET N EPCS 2 RX RESET N EPCS 3 RX RESET N Note X 0 1 23 EPCS 0 TX DATA 19 0 Input PHY transmit data This signal is used to transmit data This signal is always 20 EPCS 1 TX DATA 19 0 bits per lane but the PMA macro will use only the number of bits defined by the EPCS X TX DATA Output PHY transmit clock This signal is the aTXCIk signal generated by the PMA macro and must be used by the external PCS logic to provide data on Output PHY clean active low reset on the TX clock This signal is a clean version of the EPCS X RESET N signal which has a clean deassertion timing versus EPCS TXCLK Output PHY receive clock This signal is the aTXCIk signal generated by the PMA macro and must be used by the external PCS logic to provide data on EPCS_X_TX_DATA clean deassertion timing versus EPCS_X_RX_CLK Output PHY clean active low reset on EPCS_X_RX_CLK This signal is a clean version of the EPCS X RESET N signal which has a Revision 1 231 I Microsemi Serializer Deserialize
452. s of the PMA macro The encoding of this register is such that Rn Rd RE CUT RATIOY 256 W SETTING W SETTING being the result of RX equalization calibration Note For Reg36 to Reg47 these registers can be reprogrammed during normal operation but the effect will only appear when the parameters for the SERDES transmitter are updated on entry or exit of TX electrical idle I when Reg128 is programmed or when any of the PIPE TXSwing TXDeemp or TXMargin signals is modified TX PST RATIO DEEMPO HALF Register Table 5 39 TX PST RATIO DEEMPO HALF Bit Reset Number Name Value Description 7 0 TX PST RATIO DEEMPO HALF TX PRE RATIO DEEMPO HALF Register Table 5 40 TX PRE RATIO DEEMPO HALF This register defines the TX post cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 A value of 3 5dB corresponds to 8 d21 encoding Bit Reset Number Name Value Description 7 0 TX PRE RATIO DEEMPO HALF This register defines the TX pre cursor ratio for the Gen2 speed used for selecting the de emphasis of the switching bit versus non switching bit A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Revision 1 201 I Microsemi Serializer Deserializer TX_PST_RATIO_DEEMP1_HALF Register Table 5 41 TX PST R
453. s this 80 bit data and transmit it onto the XAUI bus e Receive block This block receives 8B 10B encoded data and four recovered clocks from an external XAUI SERDES PMA The receive block performs the comma alignment on the data phase aligns the four lanes of data and performs the 8B 10B decode function Revision 1 amp Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide e Management block The management block is the MDIO interface to the design registers The transmit and receive frequencies are set at 156 25 MHz XAUI Extender Transmit Block X2 EPCS SERDES Interf FABRIC lt gt Management Block dd PMA only X2 EPCS Mode Interface Receive Block Figure 3 2 e XAUI Extender Block Diagram SERDESIF System Registers for XAUI Mode Three SERDESIF system registers need to be configured to implement XAUI mode The three registers that define the mode of operation of SmartFusion2 SoC FPGA SERDESIF module are e CONFIG_PHY_MODE 15 0 e CONFIG EPCS SEL 3 0 e CONFIG_LINKK2LANE 3 0 Revision 1 131 I Microsemi XAUI Table 3 2 XAUI Mode Settings using SERDESIF System Register SERDESIF System APB Registers CONFIG PHY MODE 15 0 Description For each lane this signal selects the protocol default settings which will set the reset value of the registers space CONFIG PHY MODE 15 12 Defines Lane3 settings 460000 PCIE mode Lane3
454. s write buffer and read buffer for AHBL master1 and master2 DDR FIC SW WR ERCLR CR 0x414 RW PRESET_N Clear bit for error status by AHBL master1 and master2 write buffer DDR FIC ERR INT ENABLE 0x418 RW PRESET_N Used for Interrupt generation DDR FIC NUM AHB MASTERS CR 0x41C RW PRESET N Defines whether one or two AHBL 32 bit masters are implemented in fabric DDR FIC HPB ERR ADDR 1 SR 0x420 RO PRESET_N Tag of write buffer for which error response is received is placed in this register DDR FIC HPB ERR ADDR 2 SR 0x424 RO PRESET_N Tag of write buffer for which error response is received is placed in this register DDR_FIC_SW_ERR_ADDR_1_SR 0x428 RO PRESET N Tag of write buffer for which error response is received is placed in this register DDR FIC SW ERR ADDR 2 SR 0x42C RO PRESET N Tag of write buffer for which error response is received is placed in this register DDR FIC HPD SW WRB EMPTY SR 0x430 RO PRESET_N Indicates valid data in read and write buffer for AHBL master1 and master2 DDR FIC SW HPB LOCKOUT SR 0x434 RO PRESET_N Write and read buffer status register for AHBL master1 and master2 Revision 1 361 I Microsemi MSS DDR Subsystem Table 7 215 DDR FIC Configuration Register Summary continued Address Reset Register Name Offset R W Source Description DDR FIC SW HPD WERR SR 0x438
455. se x4 PCle only mode with OxF OxF 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x0 0x1 0x1 Lane reverse x2 PCle only mode with OxF OxF OxF 0x0 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x1 Lane reverse x1 PCle only mode with 0x0 0x0 OxF OxF 0x0 0x0 0x1 0x1 0x1 0x1 0x0 0x0 Lane reverse x2 PCle only mode with OxF 0x0 OxF OxF 0x1 0x0 0x1 0x1 0x0 0x1 0x0 0x0 Lane reverse x1 PCle mode x2 and 0x0 0x0 OxF OxF 0x0 0x0 0x1 0x1 0x1 0x1 0x0 0x0 EPCS x2 PCle mode x1 and 0x0 OxF OxF OxF 0x0 0x1 0x1 0x1 0x1 0x0 0x0 0x0 EPCS x2 PCle mode x2 with 0x0 0x0 OxF OxF 0x0 0x0 0x1 0x1 0x1 0x1 0x0 0x1 Lane reverse and EPCS x2 PCle mode x1 with OxF 0x0 OxF OxF Ox1 0x0 0x1 0x1 0x0 0x1 0x0 0x0 Lane reverse and EPCS x2 Revision 1 69 I Microsemi PCI Express Using the PCle System This section describes generating and configuring the SERDESIF block for PCle mode using Libero SoC software It also describes various topics about clocking and resetting scheme for implementing PCle in SmartFusion2 SoC FPGA Configuring the High Speed Serial Generator for PCle mode The high speed serial interface generator in Libero SoC allows to configure the SERDESIF block in PCle mode and thus control the setting of the three SERDESIF system registers Refer to Figure 2 6 and Figure 2 7 for PCle mode setting in the high speed serial interface generator Protocol Selection Protocol 1 Type pa Protocol 2 Type fine
456. select for a duration of T MOD Starts counting of T ZQ LONG NOP and issues ZQCL command to start ZQ calibration Waits for T ZQ LONG NOP counting to finish Ensures wait from step 7 is larger than tDLLK DDR3 SRAM is now ready for normal operation Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide LPDDR1 When used with LPDDR1 SDRAM the initialization state machine executes the following initialization sequence 1 Asserts and holds CKE 2 Issues NOP Deselect for duration specified by REG_DDRC_PRE_CKE_X1024 specification requires at least 200 us with stable power and clock Issues PRECHARGE ALL command Issues REFRESH command 8 times JEDEC specification requires only 2 refreshes during initialization 5 Loads Mode register 6 Loads Extended Mode register 7 Issues ACTIVE command 8 Issues NOP Deselect for REG DDRC FINAL WAIT X32 cycles no specification requirement 9 Begins normal operation Data Flow Paths FPGA Fabric to MDDR Through DDR FIC 1 AXI interface from FPGA Fabric The MDDR subsystem can be used to access DDR SDRAM memory as shown in Figure 7 4 DDR SDRAM memory can be DDR2 DDR3 or LPDDR1 depending on the MDDR configuration MDDR has an APB interface for configuring the registers The configuration can be done through the MSS or user logic APB master in the FPGA fabric The read write and read modify write transactions are initiated by the AXI
457. selected for locking the SERDES CDR circuitry and when set to 1 the PMA driven mode is used CDR_PLL_DELTA This register defines the frequency comparator threshold value to switch from fine grain locking to frequency lock and thus control the input signal of the PMA macro when CDR is configured in PMA driven mode and the equivalent function when the PMA is configured in PCS driven mode When set to 0 the RX clock and TX clock must be in a 0 4 difference range 0 8 when set to 1 SIGNAL_DETECT_THRESHOLD This register defines the Schmitt trigger signal detection threshold used to detect electrical idle on RX When set to 0 threshold is 125 mV 440 and when set to 1 threshold is 180 mV 33 TX_SELECT_RX_FEEDBACK This register must be set to 0 when aRefclk is used for TX PLL Set to 1 when the CDR PLL is used as TX PLL reference clock Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready Revision 1 189 I Microsemi Serializer Deserializer ERRCNT_DEC Register Table 5 4 ERRCNT DEC Bit Reset Number Name Value Description 7 0 ERRCNT DEC In PCS driven mode the PMA control logic counts the number of errors detected by the PCS logic in order to decide to switch back to frequency lock mode of the CDR PLL This counter is used to decrement the error counter every 16 errcnt_dec 7 0 aTXClk clock cycles
458. serts PCle Core and SERDES reset for one clock cycle and alDDQ is deasserted lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PCle Core Bridge Register Space The PCle core bridge register space is used to configure PCle core settings at power up These registers are 32 bits wide and accessed via the APB bus from the SmartFusion2 SoC FPGA fabric The PCle system block registers consist of the following e Read only registers that report configuration space control and status registers to the AXI side through the APB bus e Read write registers that report PCle configuration space capability that must be configured at power up Bridge settings that must be configured at power up such as local interrupt mapping to MSI and test mode e Control status registers that can be used by the AXI bus to control bridge behavior during an operation Most bridge registers are hardwired to a fixed value These registers are described in the next section according to their function e Information registers These registers provide device system and bridge identification information e Bridge configuration registers These registers enable configuration of bridge functionality Power management registers These registers enable configuration of the power management capabilities of the bridge Address mapping registers These registers provide address mapping for AXI master and slave windows
459. served across a read modify write operation 15 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 15 0 bits of REG PHY FIFO WE SLAVE RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY FIFO WE SLAVE RATIO 2 CR Table 7 125 PHY FIFO WE SLAVE RATIO 2 CR Bit Name Reset Description Number Value 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 31 16 bits of REG PHY FIFO WE SLAVE RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc PHY FIFO WE SLAVE RATIO 3 CR Table 7 126 PHY FIFO WE SLAVE RATIO 3 CR Bit Reset Number Name Value Description 31 15 Reserved Ox0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_FIFO_WE_SLAVE_RATIO 0x0 47 32 bits of REG_PHY_FIFO_WE_SLAVE_RATIO Lowest 11 bits are from data slice 0 next 11 bits are for data slice 1 etc Revision 1 327 I Microsemi MSS DDR Subsystem PHY_FIFO_WE_SLAVE_RATIO_4_CR Table 7 127 PHY FIFO WE SLAVE RATIO 4 CR Bit Reset Number Na
460. served across a read modify write operation 9 0 REG DDRC DFI T CTRLUP MAX 0x40 Specifies the maximum number of clock cycles that the DDRC DFI CTRLUPD REQ signal can assert Lowest value to assign to this variable is 0x40 Units Clocks Revision 1 295 I Microsemi MSS DDR Subsystem DDRC DFI WR LVL CONTROL 1 CR Table 7 69 DDRC DFI WR LVL CONTROL 1 CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG_DDRC_DFI_WRLVL_MAX_X1024 0x0 7 0 bits of REG_DDRC_DFI_WRLVL_MAX_X1024 Write leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI WRLVL RESP to a write leveling enable signal DDRC DFI WRLVL EN Only applicable when connecting to PHY s operating in PHY WrLvi Evaluation mode Units 1 024 clocks Only present in designs that support DDR3 devices 7 0 REG DDRC WRLVL WW 0x0 Write leveling write to write delay Specifies the minimum number of clock cycles from the assertion of a DDRC_DFI_WRLVL_STROBE signal to the next DDRC_DFI_WRLVL_STROBE signal Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3
461. served across a read modify write operation DDR_FIC_HPB_ERR_ADDR_1_SR Table 7 224 DDR FIC HPB ERR ADDR 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M1_ERR_ADD 0x0 15 0 bits of DDR FIC M1 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded to 31 5 and 00000 to 4 0 DDR FIC HPB ERR ADDR 2 SR Table 7 225 DDR FIC HPB ERR ADDR 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDR_FIC_M1_ERR_ADD 0x0 31 16 bits of DDR FIC M1 ERR ADD Tag of write buffer for which error response is received is placed in this register The following values are updated in this register as per buffer size Buffer size 16 bytes 28 bit TAG value is loaded to 31 4 and 0000 to 3 0 32 bytes upper 27 bits of TAG is loaded to 3
462. served bit should be preserved across a read modify write operation 6 0 REG_PHY_GATELVL_INIT_RATIO 0x0 54 48 of REG PHY GATELVL INIT RATIO Lowest 11 R bits are from data slice 0 next 11 R bits are for data slice 1 etc Revision 1 329 I Microsemi MSS DDR Subsystem PHY_LOCAL_ODT_CR Table 7 133 PHY LOCAL ODT CR Bit Reset Number Name Value Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 2 REG_PHY_IDLE_LOCAL_ODT 0x0 The user programmable initialization ratio selection mode 01 Selects a starting ratio value based on the REG_PHY_GATELVL_INIT_RATIO port 00 Selects a starting ratio value based on write leveling of the same data slice 1 REG_PHY_WR_LOCAL_ODT 0x0 Tied to 0 0 REG_PHY_RD_LOCAL_ODT 0x0 _ Tied to 0 PHY_INVERT_CLKOUT_CR Table 7 134 PHY INVERT CLKOUT CR Bit Name Reset Description Number Value 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_PHY_INVERT_CLKOUT 0x0 Inverts the polarity of the DRAM clock 0 Core clock is passed on to DRAM Most common usage mode 1 Inverted core
463. served bit should be preserved across a read modify write operation 7 0 DDRC REG ECC SYNDROMES 0x0 71 64 bits of DDRC REG ECC SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system DDRC_LCE_ADDRESS_1_SR Table 7 91 DDRC LCE ADDRESS 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_ROW 0x0 Row where the SECDED error occurred Revision 1 311 I Microsemi MSS DDR Subsystem DDRC_LCE_ADDRESS_2_SR Table 7 92 e DDRC LCE ADDRESS 2 SR Bit Reset Number Name Value Description 31 15
464. sion 1 233 I Microsemi Serializer Deserializer List of Changes The following table lists critical changes that were made in each revision bm amme re 50200330 1 11 12 Updated Table 5 121 and Table 5 123 SAR 42156 223 and 224 Updated Table 5 25 SAR 42155 The part number is located on the last page of the document The digits following the slash indicate the month and year of publication Note 234 Revision 1 lt gt Microsemi 6 DDR Controller The DDR controller receives requests from the AXI transaction controller performs the address mapping from system addresses to DRAM addresses rank bank row and column and prioritizes requests to minimize the latency of reads especially high priority reads and maximize page hits It also ensures that DRAM is properly initialized all requests are made to DRAM legally accounting for associated DRAM constraints refreshes are inserted as required and the DRAM enters and exits various power saving modes appropriately Address Mapping Read and write requests are provided to the controller with a system address The controller is responsible for mapping this system address with rank bank row and column address to DRAM The address mapper maps linear request addresses to DRAM addresses by selecting the source bit that maps to each and every applicable DRAM address bit The address map interface registers can be configured to map source address bits to
465. slave mode HSIZE S AWBURST HTRANS Input AXI slave mode AWBURST Fabric AHBL slave mode HTRANS S AWVALID HWRITE Input AXI slave mode AWVALID Fabric AHBL slave mode HWRITE S AWREADY Output AXI slave mode AWREADY Fabric S AWLOCK Input AXI slave mode AWLOCK Fabric S WID Input AXI slave mode WID Fabric S WSTRB Input AXI slave mode WSTRB Fabric S WLAST Input AXI slave mode WLAST Fabric S WVALID Input AXI slave mode WVALID Fabric S WDATA HWDATA Input AXI slave mode WDATA Fabric AHBL slave mode HWDATA S WREADY HREADYOUT Output AXI slave mode WREADY Fabric AHBL slave mode HREADY S BID Output AXI slave mode BID Fabric S BRESP HRESP Output AXI slave mode BRESP Fabric AHBL slave mode HRESP S BVALID Output AXI slave mode BVALID Fabric S BREADY HREADY Input AXI slave mode BREADY Fabric AHBL slave mode HREADY S ARID Input AXI slave mode ARID Fabric Revision 1 119 lt gt Microsemi PCI Express Table 2 125 PCle System AXI AHBL Slave Interface S_ARADDR Input AXI slave mode ARADDR Fabric S ARLEN Input AXI slave mode ARLEN Fabric S ARSIZE Input AXI slave mode ARSIZE Fabric S ARBURST Input AXIslavemode ARBURST 1 Fabric S ARVALID Input AXI slave mode ARVALID Fabric S ARLOCK Input AXI slave mode ARLOCK Fabric S ARREAD
466. st for read write transactions for burst lengths 2 and 4 only The SMC_FIC AHB Lite interface in the fabric supports INCR burst transactions of any length for read and write It supports WRAP for read write transactions for burst lengths 4 and 8 only SYSREG Control Register for SMC_FIC Complete descriptions of each register and bit are located in the System Register Map chapter in the ARM Cortex M3 Processor and Subsystem for SmartFusion2 SoC FPGA Devices User s Guide and are listed here for clarity Table 10 1 MDDR CR Register Register Name Register Type Flash Write Protect Reset Source Description MDDR CR RW P Register PORESET N MDDR configuration register 408 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SMC FIC Port List Table 10 2 and Table 10 3 on page 413 give the AXI 64 and AHB Lite port list details toward the fabric interface AHB Lite signals are overlaid on AXI 64 signals toward the fabric interface F AXI AHB MODE configuration input from the SYSREG block is used to select the AXI 64 or AHB Lite interface toward the fabric Note For smaller SmartFusion2 SoC FPGA devices only the AHB Lite interface for SMC FIC is available Table 10 2 SMC FIC AXI 64 Port List Width Port Name Direction Description 1 MDDR_SMC_AXI_M_WLAST Out Indicates the last transfer in a write burst 1 MDDR_SMC_AXI_M_WVALID Out I
467. ster it is necessary to configure the DDRB_CR register in SYSREG The DDRB CR register has four 4 bit fields DDR IDC MAP DDR SW MAP DDR HPD MAP DDR DS MAP that can be configured to select the DDR address space mapping modes from 0 to 12 The MSS masters can access any of four regions at a time depending on the address space mapping mode configured for that particular master using the DDRB CR register The address mapping modes for a 4 GB memory are shown in Table 7 14 on page 260 Table 7 13 DDR Memory Regions DDR Region DDR Memory Space 0 0x00000000 0x0FFFFFFF 0x10000000 0x1FFFFFFF 0x20000000 0x2FFFFFFF 0x30000000 0x3FFFFFFF 0x40000000 0x4FFFFFFF 0x50000000 0x5FFFFFFF 0x60000000 0x6FFFFFFF 0x70000000 0x7FFFFFFF 0x80000000 0x8FFFFFFF ol oln ol al al wlpr 0x90000000 0x9FFFFFFF oO OxA0000000 0xAFFFFFFF 0xB0000000 0xBFFFFFFF QIN 0xC0000000 0xCFFFFFFF 0xD0000000 0xDFFFFFFF A 0xE0000000 0xEFFFFFFF o 0xF0000000 0xFFFFFFFF Revision 1 a lt gt Microsemi MSS DDR Subsystem Table 7 14 Accessed DDR Regions Based on Different Mode Settings for a 4 GB Memory PN DDR Regions Visible at MSS DDR Address Space for Different Modes Space MSS DDR Space 0 MSS DDR Space 1 MSS DDR Space 2 MSS DDR Space 3 Mapping 0xA000000
468. sters define the type and size of BAR4 of the PCIe native endpoint This register combines with BAR5 for defining the type and size of BAR45 of the PCle native endpoint BARS 010h R W or RO The BARS size registers define the type and size of BARS of the PCle native endpoint This register combines with BAR4 for defining the type and size of BAR45 of the PCle native endpoint TC_VC_MAPPING 038h This register reports the TC to VC mapping configured for each PCle traffic channel AER_ECRC_CAPABILITY 050h R W or RO This register defines whether the bridge supports AER and ECRC generation check and whether AER ECRC is implemented ECRC generation and check bits can only be set if AER is implemented MAX PAYLOAD SIZE 058h RO This register sets the payload size a _ ALLOCATION 0 OBOh These registers enable the posted credit distribution of the RX buffer at device power up Credit allocation is balanced between posted and non posted requests Non posted data credits minimum value is 1 CREDIT ALLOCATION 1 OBOh E These registers enable the non posted credit distribution of the RX buffer at device power up Credit allocation is balanced between posted and non posted requests Non posted data credits minimum value is 1 credit but Microsemi recommends setting it to the same value as the non posted header credit 84 Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 2 11 B
469. stry standard PRBS patterns mentioned in the Pseudo Random Bit Sequences Pattern Generator section The PRBS_CTRL register and PRBS_ERRCNT register allow pattern checking e LPBK_EN The LPBK_EN signal bit 1 of the PRBS_CTRL register puts the PMA macro block in near end loopback serial loopback from TX back to RX PRBS tests can be done using the near end loopback of the PMA macro or using any far end loopback implemented in the opposite component e PRBS_CHK The PRBS_CHK signal bit 6 of the PRBS_CTRL register starts the PRBS pattern checker Refer to the PRBS_CTRL register for more information e PRBS_ERRCNT The PRBS ERRCNT register reports the number of PRBS errors detected when the PRBS test is applied Refer to PRBS_ERRCNT register for more information Revision 1 181 I Microsemi Serializer Deserializer 182 Custom Pattern Generator and Checking The SERDES block allows generation of a user defined pattern and checking the pattern using far end loopback mode The SERDES block allows pattern generation using PRBS related registers The following bits describe the custom pattern generation feature CUSTOM PATTERN 79 0 The custom pattern registers register offset 0X190 to OX1CC enables to program a custom pattern Refer to the custom pattern registers starting with CUSTOM PATTERN 7 0 on page 217 for more information CUST SEL CUSTOM PATTERN CTRL 0 This signal replaces the PRBS data transmitted on the link by th
470. synchronously deasserted with the mmd_mdc clock Typically this output is connected to the mdc_reset input It is active high XAUI_MDC_RESET Input Asynchronously resets all the MDIO registers to their default values This pin is connected directly to set reset ports of all flops in the mmd_mdc clock domain Typically this input is connected to the mdc_reset_out signal XAUI_TX_RESET_OUT Output Software generated reset register 0 15 synchronized with tx_clk This signal will be held high whenever low power mode is enabled This signal is asynchronously asserted by the software generated reset and synchronously deasserted with tx_clk It is active high Typically this output is connected to the tx_reset input Revision 1 149 I Microsemi XAUI Table 3 26 SmartFusion2 SoC FPGA XAUI Extender Block Reset Signals continued Port Type Description XAUI TX RESET Input Resets the tx core block This pin is connected directly to set reset ports of all flops in the tx_clk clock domain It is active high Typically this is connected to the tx_reset_out signal XAUI_RX_RESET_ Output Software generated resets register 0 15 synchronized with the rx_clkix OUT 3 0 X 01 2 3 clocks These signals will be held high whenever low power mode is enabled These signals are asynchronously asserted by the software generated reset and synchronously deasserted with the rx_clkix It is active high Typically this output is conn
471. t DRAM data mask from bidirectional pads FDDR DQS 4 0 In out DRAM single ended data strobe output for bidirectional pads FDDR DQS N 4 0 In out DRAM single ended data strobe output for bidirectional pads FDDR DQ 35 0 In out DRAM data input output for bidirectional pads FDDR FIFO WE IN 2 0 In FIFO in signal DQS enable input for timing match between DQS and system clock For simulations to be tied to DRAM FIFO WE OUT FDDR FIFO WE OUT 2 0 Output FIFO out signal DQS enable output for timing match between DQS and system clock For simulations to be tied to DRAM FIFO WE IN Note AXI or AHB interface depending on configuration Revision 1 377 I Microsemi Fabric Double Data Rate Subsystem FDDR Configuration Figure 8 4 shows the FDDR as seen in Libero SoC FDDR can be instantiated from the catalog of Libero SoC For configuration details refer to the FDDR Configurator User s Guide The configurable options are as follows DDR memory type DDR2 DDR3 or LPDDR1 e Interface AXI single AHB or dual AHB FDDR CLK frequency e Clock ratio between CLK_FDDR and CLK BASE e Fabric PLL FPLL configuration e Enable disable interrupts The FDDR block can be configured by using the configuration wizard This action generates register settings that are used to configure the FDDR control registers after power up of the device This can be accomplished through the APB slave interface on the FDDR
472. t all ranks will enter self refresh simultaneously The controller takes the DDR SDRAM out of self refresh mode whenever the REG_DDRC_SELFREF_EN input is deasserted or new commands are received by the controller To exit self refresh the controller typically does the following 1 Inserts any NOP Deselect commands required to satisfy the tCKE requirement after entering precharge power down 2 Issues the self refresh exit command refresh with CKE 1 3 Issues NOP Deselect for the period defined by tXP Revision 1 amp Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide When burst refresh is enabled REFRESH_BURST gt 0 there is a feature called speculative refresh Burst refresh is done by counting the number of times tREFI expires and issuing a group of refreshes when that number reaches the refresh burst number If the tREFI has expired at least once but it has not expired REFRESH_BURST number of times yet then the controller may perform speculative refreshes This is done by automatically inserting refreshes when the controller is idle The REG_DDRC_REFRESH_TO_X32 bits determine how long the controller must be idle before considering inserting these speculative refreshes Deep Power Down This is supported only for LPDDR1 Entry The controller puts the DDR SDRAM device s in deep power down mode whenever the REG_DDRC_DEEPPOWERDOWN_EN bit is set and no reads or writes are pending in the co
473. t should be preserved across a read modify write operation 15 0 REG PHY RD DQS SLAVE RATIO 0x0040 15 0 bits of REG PHY RD DQS SLAVE RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 PHY RD DQS SLAVE RATIO 2 Table 7 140 PHY RD DQS SLAVE RATIO 2 CR CR Bit Number Reset Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 REG_PHY_RD_DQS_SLAVE_RATIO 0x0401 31 16 bits of REG_PHY_RD_DQS_SLAVE_RATIO Ratio value for read DQS slave DLL This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths In other words the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line Default value 0x40 332 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_RD_DQS_SLAVE_RATIO_3_CR Table 7 141 PHY RD DQS SLAVE RATIO 3 CR
474. t should be preserved across a read modify write operation 7 0 DDRC_REG_ECC_SYNDROME 0x0 71 64 bits of DDRC REG ECC SYNDROMES S First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC ECC ERR READ DONE CR is written over by the system DDRC LUE ADDRESS 1 SR Table 7 84 DDRC LUE ADDRESS 1 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_ROW 0x0 Row where the SECDED error occurred Only present in designs that support SECDED 306 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_LUE_ADDRESS_2_SR Table
475. ta lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable error upper lane Only present in designs that support SECDED This is cleared after DDRC_ECC_ERR_READ_DONE_CR is written over by the system 302 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_LUE_SYNDROME_2_SR Table 7 80 DDRC LUE SYNDROME 2 SR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 DDRC_REG_ECC_SYNDROMES 0x0 31 16 bits of DDRC_REG_ECC_SYNDROMES First data which has SECDED error in it 72 bits consists of the following SECDED 71 64 SECDED 63 00 Data In the same clock cycle if one lane has a correctable error and the other lane has an uncorrectable error the syndrome for the uncorrectable error is sent on this bus If more than one data lane has an error in it the lower data lane is selected The priority applied when there are multiple errors in the same cycle is as follows Uncorrectable error lower lane Uncorrectable error upper lane Correctable error lower lane Correctable erro
476. ted A parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set FORCE ATXDRA 15 8 Register Table 5 92 FORCE ATXDRA 15 8 Bit Reset Number Name Value Description 7 0 FORCE ATXDRA 15 8 This register defines bit 15 to bit 8 of the transmitted A parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set FORCE ATXDRA 20 16 Register Table 5 93 FORCE ATXDRA 20 16 Bit Reset Number Name Value Description 7 5 Unused 4 0 FORCE ATXDRA 20 16 This register defines bit 20 to bit 16 of the transmitted A parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on the SERDES behavior as long as Reg81 bit 0 is not set FORCE ATXDRT 7 0 Register Table 5 94 FORCE ATXDRT 70 Bit Reset Number Name Value Description 7 0 FORCE ATXDRT 7 0 This register defines bit 7 to bit 0 of the transmitted T parameter sent to the PHY for driving differential data on the transmit driver Note This register can be programmed any time and has no functional impact on th
477. tender Block Miscellaneous Control Signal Port Type Description XAUI LOOPBACK OUT Output Loopback mode enable out This signal is asserted when the XAUI extender block is placed in loopback Typically this signal is shunted back into the input XAUL_LOOPBACK_IN port in which case loopback is implemented in the XAUI extender block However this signal can be used to control the loopback function on a PMA in the SERDES block in place of the mxgxs loopback function XAUI_LOOPBACK_IN Input Loopback mode enable in When asserted the XAUI PMA output data signals are shunted back into the input signals For loopback to function appropriately the XGMII transmit clock tx_clk must be shunted back into the PMA recovered clock inputs XAUI_LOWPOWER Output SERDES low power status When set to 1 the SERDES block is placed in a low power state Revision 1 151 I Microsemi XAUI Glossary 152 Revision 1 Acronyms MAC Media access control MDIO Management data input output PCS Physical coding sublayer PHY Physical layer PMA Physical medium attachment PRBS Pseudo random bit sequence RS Reconciliation sublayer SERDESIF Serializer deserializer interface XAUI Extended attachment unit interface XGMII 10 Gb media independent interface lt gt Microsemi 4 EPCS Interface The SmartFusion2 SoC FPGA SERDESIF block integrates the functionality
478. ter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS ERR CYC FIRST 47 40 Register Table 5 138 PRBS ERR CYC FIRST 47 40 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC LAST 47 40 PRBS last error cycle counter register bits 47 40 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The last error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS ERR CYC FIRST 49 48 Register Table 5 139 PRBS ERR CYC FIRST 49 48 Bit Reset Number Name Value Description 7 2 Reserved 1 0 PRBS_ERR_CYC_LAST 49 48 PRBS last error cycle counter register bits 49 48 This read only register reports on which clock cycle the error counter has last been incremented after the PRBS error counter is enabled It is a 50 bit cou
479. tern generation using the PRBS_CTRL register This pattern can be looped back in the PMA and verified as explained in the Pseudo Random Bit Sequences Pattern Checker section The following bits describe the PRBS pattern generation feature e PRBS_GEN This signal starts the PRBS pattern transmission e PRBS_TYP 1 0 This signal defines the type of PRBS pattern which is applied PRBS7 when set to 00b PRBS11 when set to 01b PRBS23 when set to 10b and PRBS31 when set to 11b Table 5 1 ERDES Macro PRBS Patterns Length of Polynomial Sequence Descriptions PRBS 7 1 X6 X7 27 1 bits Used to test channels with 8b 10b PRBS 15 1 X14 X15 215 1 bits ITU T Recommendation 0 150 Section 5 3 PRBS 15 is often used for jitter measurement because it is the longest pattern the Agilent DCA J sampling scope can handle PRBS 23 1 X18 X23 223 1 bits ITU T Recommendation 0 150 Section 5 6 PRBS 23 is often used for non 8B 10B encoding scheme One of the recommended test patterns in the SONET specification PRBS 31 1 X28 X31 231 1 bits ITU T Recommendation 0 150 Section 5 8 PRBS 31 is often used for non 8b 10b encoding schemes A recommended PRBS test pattern for 10 Gigabit Ethernet See IEEE 802 3ae 2002 Pseudo Random Bit Sequences Pattern Checker The SERDES block includes a built in PRBS checker to test the signal integrity of the channel Using the internal PMA loopback this pattern checker allows SERDES to check the four indu
480. ters MSS DDR bridge fabric and translating them into DDR controller transactions Figure 7 3 shows a block diagram of the AXI transaction controller along with the DDR controller The AXI transaction controller receives read and write requests from an AXI interconnect and schedules them to the DDR controller which in turn drives the DDR SDRAM The interface supports four outstanding transactions in accordance with the standard AXI protocol AXI Transaction Controller AXI Slave Interface 0 Transaction Handler Priority Block DDR PHY Controller AXI Slave Interface 1 Re Order Buffer Figure 7 3 AXI Interface with DDR Controller Block Diagram 242 The AXI transaction controller consists of four major blocks 1 AXI slave interface 2 Priority block 3 Transaction handler 4 Reorder buffer 1 AXI Slave Interfaces There are two AXI slave ports coming into the AXI transaction controller one from the MSS DDR bridge and the other from the FPGA fabric Each of the AXI slave ports is 64 bits wide and is in compliance with the standard AXI protocol Each transaction has an ID related to the master interface Transactions with the same ID are completed in order while the transactions with different read IDs can be completed in any order depending on when the instruction is executed by the DDR controller If a master requires ordering between transactions the same ID should be used The AXI slave interface is further subdivid
481. th AHB master and slave interface Fabric mode1 EPCS only mode SERDESIF with EPCS interface with maximum four lanes Fabric mode2 SGMII only or EPCS only mode XAUI mode SERDESIF with XAUI mode Fabric mode3 PCle and EPCS mode SERDESIF with PCle AXI master and slave on lane0 and lane1 Fabric modeO SERDESIF with PCle AHBL master and slave on laneO and Fabric mode1 lane1 SERDESIF with EPCS interface for lane2 and lane3 only EPCS Not applicable laneO and lane1 signals are over laid Fabric Signals for Fabric ModeO In Fabric modeO AXI master and AXI slave interfaces are exposed to the SmartFusion2 Soc FPGA fabric The overlaid interface EPCS interface for laneO and lane1 are not exposed to the SmartFusion2 SoC FPGA fabric The SERDESIF can be configured to support the single or multi protocol in Fabric moded0 that is PCle only or PCle and EPCS protocol mode Note The application interface to SERDESIF for PCle protocol is AXI master and AXI slave interface Table 1 62 lists the SERDESIF signals and behavior in Fabric modeO Table 1 62 e SERDESIF Signals in Fabric ModeO0 SERDESIF Non overlaid Interface Interface Behavior Clock and reset interface Active AXI AHBL master interface Active PCle in AXI mode AXI AHBL slave interface Active PCle in AXI mode APB interface 32 bit Active Inactive EPCS interface lane2 and lane3 Inactive in PCle only protocol PHY MODE Active in multi protocol PHY
482. the P1 state Note that this register must not be set for applications which remove the reference clock in P1 mode generally associated with the CLKREGH signal express card application and more generally power sensitive application Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready except for bit 2 which can only be modified under reset condition Revision 1 195 I Microsemi Serializer Deserializer Table 5 18 RX OFFSET COUNT RX OFFSET COUNT Register Bit Reset Number Name Value Description 7 5 RXOFF SETTLE MAX This register defines the number of clock cycles before which the aRXDNullDat signal can be checked for stability after aRXDNull 3 0 modification This is used also for aRXD aRXT and Schmitt trigger calibration The value of this register expresses a number of 2 N 1 PCLK clock cycles 4 0 RXOFF_STABLE_MAX This register defines the number of clock cycles where the aRXDNullDat signal is checked for stability Note This register can be reprogrammed when the PHY is under reset or when calibration has completed PMA is ready PLL F PCLK RATIO 5GBPS Register PCle Gen2 protocol only Table 5 19 PLL F PCLK RATIO 5GBPS Bit Reset Number Name Value Description 7 6 Reserved 5 4 DIV MODE1 This register defines the ratio between PCLK and aTXClk for the PCle Gen2 protocol 3 0 F This register
483. the REG DDRC EMR value and issues NOP deselect for REG DDRC T MRD cycles Issues DLL reset by programming MR to the REG DDRC MR value and issues NOP Deselect for REG DDRC T MRD cycles 8 Issues PRECHARGE ALL and issues NOP Deselect for REG DDRC T RP 1 cycles 9 Issues Refresh and issues NOP Deselect for REG DDRC T RFC MIN cycles Repeats 9 times 10 Programs MR without resetting the DLL by setting MR to REG DDRC MR value with bit 8 set to 1 11 Issues NOP Deselect for the duration specified by REG DDRC PRE OCD X32 no specification requirement 12 Issues OCD complete command indicating that no on chip driver calibration will be performed 13 Issues NOP Deselect for REG DDRC FINAL WAIT X32 cycles 14 Begins normal operation DDR3 For DDR3 the initialization state machine executes the following initialization sequence 1 Issues NOP Deselect for the duration specified by REG DDRC PRE CKE X1024 specification requires at least 200 us with stable power and clock Asserts CKE and issues NOP Deselect for POST CKE X1024 specification requires at least 500 us Issues MRS command to load MR2 with EMR2 value followed by NOP Deselect for a duration of REG_DDRC_T_MRD Issues MRS command to load MR3 with EMR3 followed by NOP Deselect for a duration of T_MRD Issues MRS command to load MR1 with EMR followed by NOP Deselect for a duration of T_MRD Issues MRS command to load MRO with MR followed by NOP De
484. tio for delay line calculated by write leveling Note This port must be set to 0 when PHY is not working in DDR3 mode 1 REG_PHY_USE_RD_DQS_GATE_LEVEL 0x0 Read DQS gate training control 0 Use register programmed ratio values 1 Use ratio for delay line calculated by DQS gate leveling This can be used in DDR2 mode also Note This port must be set to 0 when PHY is not working in DDR2 DDR3 mode 0 REG_PHY_USE_RD_DATA_EYE_LEVEL 0x0 Read data eye training control 0 Use register programmed ratio values 1 Use ratio for delay line calculated by data eye leveling Note This port must be set to 0 when PHY is not working in DDR3 mode 344 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide PHY_DYN_CONFIG_CR Table 7 170 PHY DYN CONFIG CR Bit Reset Number Name Value Description 31 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 REG PHY DIS PHY CTRL RSTN 0x0 Disable the PHY control macro reset 1 PHY control macro does not get reset 0 PHY control macro gets reset default 3 REG PHY LPDDR1 0x0 If the PHY is operating in LPDDR1 mode 2 REG PHY BL2 0x0 Burst length control 1 Burst length 2 0 Other burst length 1 REG_PHY_CLK_STALL_
485. tion 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG DDRC DFI RDLVL MAX X1024 0x0 7 0 bits Read leveling maximum time Specifies the maximum number of clock cycles that the controller will wait for a response PHY DFI RDLVL RESP to a read leveling enable signal DDRC_DFI_RDLVL_EN or DDRC DFI RDLVL GATE EN Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units 1 024 clocks 7 0 REG_DDRC_RDLVL_RR 0x0 Only present in designs that support DDR3 devices Read leveling read to read delay Specifies the minimum number of clock cycles from the assertion of a read command to the next read command Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode Only present in designs that support DDR3 devices Units Clocks Revision 1 297 I Microsemi MSS DDR Subsystem DDRC_DFI_RD_LVL_CONTROL_2_CR Table 7 72 DDRC DFI RD LVL CONTROL 2 CR Bit Reset Number Name Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 REG DDRC DFI RD DATA EYE TR
486. tion of L2 P2 State SmartFusion2 SoC FPGA devices have a single power domain Vmain and achieve pseudo L2 state Vmain is derived from the SmartFusion2 SoC FPGA chip supply itself L2 entry follows the PCle specification The L2 exit is implemented differently but complies to the PCle specification requirements Revision 1 3 Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SmartFusion2 SoC FPGA L2 Entry Sequence L2 entry on the downstream component can be initiated upstream through the switch root port RP L2 Entry Initiated by Upstream Component RP Switch 1 The root complex RC switch broadcasts PM_TURN_OFF data link layer packets DLLPs to part whole of the downstream components 2 The endpoint EP can accept reject PM_TURN_OFF DLLP transmitting PM_REQUEST_ACK Nak DLLPs accordingly 3 The EP can delay transmitting PM_Request_Ack DLLPs by disabling the PM ENABLE bit on power up By default the PM_ENABLE bit is 1 4 Delaying L2 entry On power up the local processor must disable the PM_ENABLE bit 0 Once the L2 entry request L2 Req is received an interrupt is generated to the local processor which can complete pending tasks and re enable the PM_ENABLE bit to generate the PM_REQUEST_ACK DLLP No L2 Entry Request from RC Switch PCle Link in Active State LO L2 Entry Request from RC SW Condition False Condition No new TLP DLLPs should be pending to be tra
487. to 31 5 and 00000 to 4 0 DDR_FIC_HPD_SW_WRB_EMPTY_SR Table 7 228 DDR FIC HPD SW WRB EMPTY SR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR_FIC_M1_RBEMPTY 0x0 1 Read buffer of AHBL master1 does not have valid data 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_M1_WBEMPTY 0x0 1 Write buffer of AHBL master1 does not have valid data 0 Default Revision 1 367 lt gt Microsemi MSS DDR Subsystem Table 7 228 DDR_FIC_HPD_SW_WRB_EMPTY_SR continued Bit Reset Number Name Value Description 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_M2_RBEMPTY 0x0 1 Read buffer of AHBL master2 does not have valid data 0 Default 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FI
488. to I O 64 bit BARs The address space can be as small as 128 bytes or as large as 8 exabytes Used for memory only 74 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide The PCle bridge register defines the BAR setting Each BAR register is 32 bits but BARs can be combined to make a 64 bit BAR For example BARO address offset 010h and BAR1 address offset 014h define the type and size of BARO1 of the PCle native endpoint BARO1 can be memory mapped prefetchable 64 bit BAR or non prefetchable 32 bit BAR 32 Bit Memory BAR wena Ka om I 0 Non Prefetchable 00 4 GB Space Memory 1 Prefetchable Indicator 64 Bit Memory BAR Upper 32 Bits Base Address LP Type o ep 0 Non Prefetchable 10 16 GB Space Memory 1 Prefetchable Indicator Figure 2 14 BAR Settings in High Speed Serial Interface Generator Libero SoC can also be used to configure the individual fields of the 6 BARs Refer to Figure 2 15 The BAR registers share the options below e Width The width on even registers can be 32 bits or 64 bits If an even register is selected to be 64 bits wide the subsequent odd register serves as the upper half Otherwise the width on odd registers is restricted to 32 bits e Size The size setting can range from 4 KB to 2 GB Type The type can toggle between memory and I O e Prefetchable This option is enabled only on even registers wit
489. tocol Selection Proteco 1 Type AL Protocol 2 Type ime 7 e Protocol 1 Number of Lanes x4 Y Prctozol 2 Number of Lanes 7 Protocol 1 Speed E 125 Gbps 7 Pretoco 2 Speed 7 Protocol 1 PHY Reference Clock REFCLKO hd Protocol Z PHY Reference Clock z Lane Assicnment Lane fo ALI Lane i XAUI Lane E 4 XALI Lane F Figure 3 3 e XAUI Mode Setting in High Speed Serial Interface Generator XAUI Mode Clocking When the SmartFusion2 SoC FPGA SERDESIF is configured in the XAUI mode it has multiple clock inputs and outputs This section describes the XAUI clocking scheme 134 Revision 1 Figure 3 4 Figure 3 5 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide SERDES Reference Clocks for the XAUI Mode The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock generation through PLLs For maximum flexibility the reference clock to the four lanes can come from either REFCLK 100 or REFCLK 101 I O pads or from internal fab_ref_clk or ccc_ref_clk signal These two reference clocks REFCLK 100 and REFCLK 101 are connected to I O pad I O PortO and I O Port1 Figure 3 4 shows the reference clock selection refcik io0 PAD refcik io1 ccc ref cik aREFCLK 1 0 fab ref cik SERDES LANEO1 REFCLK SEL 1 0 aREFCLK 3 2 Y LANE23_REFCLK_SEL 1 0 SERDES Reference Clock for XAUI
490. tput XGMII data Rxd Equal to the input recovered clock rx_clki0 Refer to the IEEE 802 3ae clause 46 for a complete definition XAUI_RXD 63 0 Output Receive data output to the XGMII The signal has the following lane definitions LaneO row0 rxd 7 0 Lane1 row0 rxd 15 8 Lane2 row0 rxd 23 16 Lane3 row0 rxd 31 24 LaneO row1 rxd 39 32 Lane1 row1 rxd 47 40 Lane2 row1 rxd 55 48 Lane3 row1 rxd 63 56 The row0 lanes are leading the row1 lanes in time Refer to the IEEE 802 3ae clause 46 for a complete definition XAUI RXC 7 0 Output Receive lane data control signals The signal has the following lane definitions LaneO row0 rxc 0 Lane1 row0 rxc 1 Lane2 row0 rxc 2 Lane3 row0 rxc 3 LaneO row1 rxc 4 Lane1 row1 rxc 5 Lane2 row1 rxc 6 Lane3 row1 rxc 7 The row0 lanes are leading the row1 lanes in time Refer to the IEEE 802 3ae clause 46 for a complete definition Table 3 26 SmartFusion2 SoC FPGA XAUI Extender Block Reset Signals Port Type Description CORE_RESET_N Input External asynchronous reset input Must be asserted for at least two clock cycles of the host clock mmd_mdc for a full reset of the XAUI extender to occur It is active high PHY_RESET_N Input Active low SERDES reset If this port is not used for any serial protocol it should be tied 1 b0 XAUI_MDC_RESET_ Output MDC synchronous reset This reset is asynchronously asserted by OUT mstr_reset and
491. troller is to skip the OCD adjustment step during DDR2 initialization OCD_Default and OCD_Exit is performed instead 0 Not supported DDRC_CKE_RSTN_CYCLES_1_ Table 7 33 DDRC CKE RSTN CYCLES 1 CR CR Bit Number Name Reset Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 8 REG_DDRC_PRE_CKE_X1024 0x0 7 0 bits of REG_DDRC_PRE_CKE_X1024 Cycles to wait after reset before driving CKE High to start the DRAM initialization sequence Units 1 024 clock cycles DDR2 specifications typically require this to be programmed for a delay of gt 200 us 7 0 REG_DDRC_DRAM_RSTN_X1024 0x0 Number of cycles to assert DRAM reset signal during initialization sequence This is only present for implementations supporting DDR3 devices 278 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC CKE RSTN CYCLES 2 CR Table 7 34 DDRC CKE RSTN CYCLES 2 CR Bit Reset Number Name Value Description 31 16 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a r
492. ts of SECDED data to every 64 bits of data supporting one bit error correction and two bit error detection When SECDED is enabled a write operation computes and stores a SECDED code along with the data and a read operation reads and checks the data against the stored SECDED code It is therefore possible to receive error correcting code ECC errors when reading uninitialized memory locations To avoid this all memory locations must be written before being read The SECDED bits are interlaced with the data bits and unused bits as shown in Table 7 11 Table 7 11 SECDED DQ Lines at DDR SECDED Data Pins SECDED Data Pins Mode M2S050 M2S080 and M2S120 M25005 M25010 and M2S025 Full bus width mode DQ 35 32 NA Half bus width mode DQ 33 32 DQ 18 17 Quarter bus width mode DQ 33 DQ 17 Controller Behavior During SECDED Errors When the controller detects a correctable SECDED error it does the following Sends the corrected data to the read requested MSS FPGA fabric master as part of the read data Sends the SECDED error information to the DDRC LCE SYNDROVE 1 SR register Performs a read modify write operation to correct the data present in the DRAM The controller has automatic data scrubbing of correctable errors the SECDED scrubbing is enabled automatically Only one scrub read modify write RMW command can be outstanding in the controller at any time No scrub is performed on single bit SECDED
493. ttings to be done for the three SERDESIF System registers to force the SERDESIF into EPCS mode Table 4 5 EPCS Mode Settings Using SERDESIF System Register CONFIG_PHY_MODE CONFIG_EPCS_SEL CONFIG_LINKK2LANE SERDESIF 4 bits per lane 1 bit per lane 1 bit per lane MODE Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane 0 1 2 3 0 1 2 3 0 1 2 3 EPCS Single mode only Non reversed mode EPCS x4 3 4 5 3 4 5 3 4 5 3 4 5 1 1 1 1 0 0 0 0 EPCS x2 3 4 5 3 4 5 F F 1 1 1 1 0 0 0 0 EPCS x1 3 4 5 F F F 1 1 1 1 0 0 0 0 EPCS Single mode only Reversed mode EPCS x4 3 4 5 3 4 5 3 4 5 3 4 5 1 1 1 1 0 0 0 0 EPCS x2 F F 3 4 5 3 4 5 1 1 1 1 0 0 0 0 EPCS x1 F F F 3 4 5 1 1 1 1 0 0 0 0 Multi mode PCle Non reversed mode nr pcie x2 EPCS 0 0 3 4 5 3 4 5 0 0 1 1 1 1 0 0 nr pcie x1 epcs 0 F 3 4 5 3 4 5 0 1 1 1 1 0 0 0 Multi mode PCle Reversed mode r pcie x2 epcs 0 0 3 4 5 3 4 5 0 0 1 1 1 1 0 0 r pcie x1 epcs 0 0 3 4 5 3 4 5 1 0 1 1 0 1 0 0 Note The register values are Hex Revision 1 157 I Microsemi EPCS Interface Using EPCS Protocol Mode This section describes the customizing and generating the EPCS from the Libero System on Chip SoC software It also describes the cl
494. udes an embedded PLL which is to be used by the SERDESIF block exclusively This SERDES PLL is called the SPLL It is used to reduce the skew between the Fabric and SERDESIF module This clocking scheme is used for PCle and XAUI protocol modes Refer to the PCI Express section on page 59 and the XAUI section on page 129 for more information SERDESIF PMA Lane 0 et XAUI Soft i IP deskew XAUI FDB PCle System XAUI CLK OUT AXI AHB Design for XAUI PCle Extender SPLL GB FABRIC A Global Clock Buffer PCle XAUI Figure 1 12 SPLL Clocking 22 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Figure 1 13 shows SPLL settings in the high speed serial interface generator The SERDESIF system register can be used to configure and can also be used this PLL PCIe XAUT Fabric SPUL Configuration CLK BASE Frequency MHz 166 Supply Voltage 2 5 9 LodkDelay 32 cydes v Lock Window 64000 ppm Figure 1 13 SPLL Clocking Configuration using High Speed Serial Interface Generator PCle System Block Clocking The PCle system is a multi clock system The clock domains of the PCle system are the SERDES reference clock bridge interface clock APB interface clock and PHY clock The SERDESIF block handles the entire clock domain crossing Refer to the PCI Express section on page 59
495. ue Description 31 4 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 CFGR LOCK TIMEOUT REG 0x0 1 19 16 bits of CFGR LOCK TIMEOUT REG Lock timeout 20 bit register Indicates maximum number of cycles a master can hold the bus for locked transfer If master holds the bus for locked transfer more than the required cycles an interrupt is generated Revision 1 369 I Microsemi MSS DDR Subsystem DDR_FIC_LOCK_TIMEOUT_EN_CR Table 7 233 DDR FIC LOCK TIMEOUT EN CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 CFGR LOCK TIMEOUT EN 0x0 1 Lock timeout feature is enabled and interrupt is generated 0 Lock timeout feature is disabled and interrupt is not generated DDR_FIC_RDWR_ERR_SR Table 7 234 DDR FIC RDWR ERR SR Bit Reset Number Name Value Description 31 6 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 0 DDR_FIC_CFG_RDWR_ERR_SR 0x
496. ue programmed in the BL bit of the mode register to the DRAM RL Read latency CAS latency 4 0 REG_DDRC_WR2RD 0x0 WL tWTR BL 2 Minimum time from WRITE command to READ command Includes time for bus turnaround and recovery times and all per bank per rank and global constraints Unit clocks where WL Write latency BL Burst length This should match the value programmed in the BL bit of the mode register to the DRAM tWTR Internal WRITE to READ command delay This comes directly from the DRAM specifications Table 7 45 DDRC_DRAM_T_PD_CR DDRC_DRAM_T_PD_CR Bit Reset Number Name Value Description 31 9 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 8 4 REG_DDRC_T_XP 0x0 tXP Minimum time after power down exit to any operation Units clocks 3 0 REG_DDRC_T_CKE 0x0 Minimum number of cycles of CKE High Low during power down and self refresh Unit clocks Revision 1 283 I Microsemi MSS DDR Subsystem DDRC_DRAM_BANK_ACT_TIMING_CR Table 7 46 DDRC DRAM BANK ACT TIMING CR Bit Reset Number Name Value Description 31 14 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserv
497. umber of the endpoint device for each configuration write TLP received SUBSYSTEM_ID 02Ch R W or RO Identifies the manufacturer of the device or application See the PCle specification for details INFO 16Ch RO This register reports the bridge version Revision 1 83 I Microsemi PCI Express Bridge Configuration Registers The registers listed in Table 2 11 enable to configure bridge functionality Table 2 11 Bridge Configuration Registers Byte Register Offset Description PCIE_CONFIG 204h R W or RO This register sets the PCle Configuration BARO 010h R W or RO The BARO size registers define the type and size of BARO of the PCle native endpoint This register combines with BAR1 for defining the type and size of BARO1 of the PCle native endpoint BAR1 010h R W or RO The BAR1 size registers define the type and size of BAR1 of the PCle native endpoint This register combines with BARO for defining the type and size of BARO1 of the PCle native endpoint BAR2 010h R W or RO The BAR2 size registers define the type and size of BAR2 of the PCle native endpoint This register combines with BAR3 for defining the type and size of BARO1 of the PCle native endpoint BAR3 010h R W or RO The BAR3 size registers define the type and size of BAR3 of the PCle native endpoint This register combines with BAR2 for defining the type and size of BAR23 of the PCle native endpoint BAR4 010h R W or RO The BAR4 size regi
498. urce Typically a specific traffic pattern is transmitted and then compared to check for errors Loopback test modes fall into two broad categories e Near end serial loopback mode The SERDES block provides support for near end serial loopback for test purposes When the LPBK_EN bit bit1 of the PRBS_CTRL register is set the serial data is fed back to the CDR block and the CDR block extracts clock and data generated by the PCS as shown in Figure 9 Loopback may be operated in full frequency mode PLLs active or bypass mode PLLs bypassed e Far end serial loopback mode The SERDES block can also be configured in far end serial loopback mode In this mode the transmit data is looped back to received data at the far end of the link as shown by green line in Figure 5 9 on page 180 Loopback testing can be used either during development or in deployed equipment for fault isolation The traffic patterns used can be application traffic patterns or specialized pseudo random patterns Revision 1 179 I Microsemi Serializer Deserializer TX Data 0 TX Data 19 CDR PLL Loop Near End RX Data 19 RX Data 0 Figure 5 9 Serial Loopback 180 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Pseudo Random Bit Sequences Pattern Generator Pseudo random bit sequences PRBS are commonly used to test the signal integrity of SERDES The SERDES block allows pat
499. uring calibration and triggers the RX TX shift load logic to load new programmed settings into the SERDES Thus it must be written only after a coherent set of register programming has been programmed PRBS_ERR_CYC_FIRST_7_0 Register PRBS first error cycle counter register Table 5 126 PRBS ERR CYC FIRST 7 0 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC FIRST 7 0 PRBS last error cycle counter register bits 7 0 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter information complementing the total number of errors detected might give information about bursts of errors or distributed errors but statistics might also be required The test can be rerun several times with different test periods PRBS_ERR_CYC_FIRST_15_8 Register Table 5 127 PRBS ERR CYC FIRST 15 8 Bit Reset Number Name Value Description 7 0 PRBS ERR CYC FIRST 15 8 PRBS last error cycle counter register bits 15 8 This read only register reports on which clock cycle the error counter has first been incremented after the PRBS error counter is enabled It is a 50 bit counter enabling performance of bit error rate testing BERT Note The first error cycle counter information complementing the tota
500. us of DDR PLL FATC RESET N Out Reset output to fabric portion of fabric alignment test circuit Interrupts PLL LOCK INT Out PLL lock interrupt PLL_LOCKLOST_INT Out PLL lock lost interrupt ECC_INT Out Sticky interrupt on APB clock Generated on ECC errors from the DDR controller IO CALIB INT Out Sticky Interrupt on APB clock Generated on code lock from the I O calibration block FIC INT Out Sticky interrupt on APB clock Generated on error conditions from the DDR FIC Bus Interfaces AXI SLAVE Bus AXI slave interface 1 0 bus AHBO SLAVE Bus AHBO slave interface 3 0 bus AHB1_SLAVE Bus AHB1 slave interface 3 0 bus APB SLAVE Bus APB slave interface 3 0 bus T DRAM Interface FDDR CAS N Out DRAM CASN FDDR CKE Out DRAM CKE FDDR CLK Out DRAM single ended Clock for differential pads Note AXI or AHB interface depending on configuration 376 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 8 1 e FDDR Subsystem Interface Signals continued Signal Name Type Description FDDR_CLK_N Out DRAM Single Ended Clock for differential pads FDDR_CS_N Out DRAM CSN FDDR_ODT Out DRAM ODT 0 Termination OFF 1 Termination ON FDDR_RAS_N Out DRAM RASN FDDR_RESET_N Out DRAM Reset for DDR3 FDDR_WE_N Out DRAM WEN FDDR ADDR 15 0 Out DRAM address bits FDDR BA 2 0 Out Dram bank address FDDR DM RDQS 4 0 In ou
501. ut of range of the bitstream frequency The only indicator for correct lock to the bitstream is detection of no errors in the decoded stream Changing CDR PLL Mode of Operation speed Once the CDR PLL has acquired lock any change of mode settings is accomplished by the suitable change of CDR PLL M N and F settings Note that a valid bitstream has to have been present for the CDR PLL to correctly bit lock If a change of mode setting is desired with no change in VCO frequency a certain amount of time will be required for the CDR PLL to reacquire bit lock This kind of change of mode setting does not disturb the PLL frequency lock significantly but due to phase re acquisition the jitter specifications of the PLL may be violated for a few transient bit periods with associated loss of received bits If a change of mode setting is desired resulting in a change in VCO frequency it must be noted that the CDR PLL will have to go through the entire acquisition process including frequency lock The CDR PLL design does not guarantee that no runt pulses or glitches occur on the clocks during mode changes So care should be taken when changing the PLL setting during operation mode SERDES Testing Operation This section covers how to configure the SERDES in loopback to test the signal integrity of the SERDES block Serial Loopback Serial loopback modes are specialized configurations of the SERDES datapath where the datastream is folded back to the so
502. value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 DDR_FIC_M2_WEN 0x0 1 Enable write buffer for AHBL master2 0 Disable write buffer for AHBL master2 DDR_FIC_HPD_SW_RW_INVAL_CR Table 7 220 DDR FIC HPD SW RW INVAL CR Bit Reset Number Name Value Description 31 7 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 6 DDR FIC fishM1 0x0 1 Flush read buffer for AHBL master1 0 Default 5 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 DDR_FIC_invalid_M1 0x0 1 Invalidate write buffer for AHBL master1 0 Default 3 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 DDR_FIC_flshM2 0x0 1 Flush write buffer for AHBL master2 0 Default 364 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 220 DDR FIC HPD SW RW INVAL CR continued Bit Reset Number
503. ve DLL PHY WR DQS SLAVE DELAY 1 CR 0x2A8 RW PRESET N Delay value for write DQS PHY WR DQS SLAVE DELAY 2 CR Ox2AC RW PRESET_N Delay value for write DQS PHY WR DQS SLAVE DELAY 3 CR 0x2B0 RW PRESET N Delay value for write DQS PHY WR DQS SLAVE FORCE CR 0x2B4 RW PRESET Nl Overwriting delay value selection reg for write DQS PHY WR DQS SLAVE RATIO 1 CR 0x2B8 RW PRESET N Ratio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 2 CR 0x2BC RW PRESET NlRatio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 3 CR 0x2C0 RW PRESET N Ratio value for write DQS slave DLL PHY WR DQS SLAVE RATIO 4 CR 0x2C4 RW PRESET N Ratio value for write DQS slave DLL PHY WR DATA SLAVE DELAY 1 CR 0x2C8 RW PRESET N Delay value for write DATA PHY WR DATA SLAVE DELAY 2 CR 0x2CC RW PRESET_N Delay value for write DATA PHY WR DATA SLAVE DELAY 3 CR 0x2D0 RW PRESET N Delay value for write DATA PHY WR DATA SLAVE FORCE CR 0x2D4 RW PRESET Nl Overwriting delay value selection reg for write DATA PHY WR DATA SLAVE RATIO 1 CR 0x2D8 RW PRESET_N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 2 CR 0x2DC RW PRESET N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 3 CR 0x2E0 RW PRESET N Ratio value for write DATA slave DLL PHY WR DATA SLAVE RATIO 4 CR 0x2E4 RW PRESET N Ratio value for write DATA slave DLL PHY WRILVL INIT MODE CR 0x2E8 RW PRESET_N IInitialization ratio selection register used by write leveling 316 Re
504. ve windows are not enabled address translation is not performed and AXI slave requests are transferred to the PCle IP core with defaults of TC 0 RO 0 and NS 0 PCle System Credit Settings The SmartFusion2 SoC FPGA PCle system has 2 KB of receive buffer RAM and 1 KB of transmit and replay buffer RAM The following sections describe credit setting and flow control Maximum Payload Size TLP size is restricted by the capabilities of both link partners After the link is trained the root complex sets the MAX_PAYLOAD_SIZE value in the device control register The PCle system MAX PAYLOAD SIZE Maximum Payload Size register is 256 Bytes with a 64 bit AXI interface Revision 1 77 I Microsemi PCI Express Replay Buffer The replay buffer located in the data link layer and common to all VCs stores a copy of a transmitted TLP until the transmitted packet is acknowledged by the receiving side of the link Each stored TLP includes the header an optional data payload of which the maximum size is determined by the maximum payload size parameter an optional ECRC the sequence number and the link cyclic redundancy check LCRC field In general the replay size is required to be greater than two times MAX_PAYLOAD_SIZE 512 bytes The SmartFusion2 SoC FPGA PCle system has a replay buffer size of 1 KB each which is four times MAX PAYLOAD SIZE Transmit Buffer The transmit buffer TX buffer stores the read data payload from the AXI master
505. ved Note that the half bus width modes are only supported when the DRAM bus width is a multiple of 16 272 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_ADDR_MAP_BANK_CR Table 7 26 DDRC ADDR MAP BANK CR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a a read modify write operation 11 8 7 4 REG DDRC ADDRMAP BANK BO REG DDRC ADDRMAP BANK B1 0x0 0x0 Selects the address bits used as bank address bit 0 Valid Range 0 to 14 Internal Base 2 The selected address bit for each of the bank address bits is determined by adding the internal base to the value of this field Selects the address bits used as bank address bit 1 Valid Range 0 to 14 Internal Base 3 The selected address bit for each of the bank address bits is determined by adding the internal base to the value of this field 3 0 REG DDRC ADDRMAP BANK B2 0x0 Selects the address bits used as bank address bit 2 Valid Range 0 to 14 and 15 Internal Base 4 The selected address bit is determined by adding the internal base to the value of this field If set to 15 bank address bit 2 is set to 0 DDRC_ECC_DATA_MASK_CR Table 7 27
506. ved 0x27C 0X280 PRBS_ERR_CYC_FIRST_7_0 0x00 RO PRBS first error cycle counter register bits 7 0 0X284 PRBS_ERR_CYC_FIRST_15_8 0x00 RO PRBS first error cycle counter register bits 15 8 0X288 PRBS_ERR_CYC_FIRST_23_16 0x00 RO PRBS first error cycle counter register bits 23 16 0X28C PRBS_ERR_CYC_FIRST_31_24 0x00 RO PRBS first error cycle counter register bits 31 24 Revision 1 187 I Microsemi Serializer Deserializer Table 5 2 e SERDES Macro Registers continued Offset Reset Hex Register Name Value Type Description 0X290 PRBS_ERR_CYC_FIRST_39_32 0x00 RO PRBS first error cycle counter register bits 39 32 0X294 PRBS_ERR_CYC_FIRST_47_40 0x00 RO PRBS first error cycle counter register bits 47 40 0X298 PRBS ERR CYC FIRST 49 48 0x00 RO PRBS first error cycle counter register bits 49 48 OX29C Reserved Ox2A0 OX2A0 PRBS ERR CYC FIRST 7 0 0x00 RO PRBS last error cycle counter register bits 7 0 OX2A4 PRBS ERR CYC FIRST 15 8 0x00 RO PRBS last error cycle counter register bits 15 8 OX2A8 PRBS_ERR_CYC_FIRST_23 16 0x00 RO PRBS last error cycle counter register bits 23 16 OX2AC PRBS ERR CYC FIRST 31 24 0x00 RO PRBS last error cycle counter register bits 31 24 0X2B0 PRBS ERR CYC FIRST 39 32 0x00 RO PRBS last error cycle counter register bits 39 32 0X2B4 PRBS ERR CYC FIRST 47 40 0x00 RO PRBS last error cycle counter register bits
507. ved bit should be preserved across a read modify write operation 11 REG_DDRC_BURSTCHOP 0x0 Not supported in this version of the DDRC controller always reads as zero 10 REG_DDRC_BURST_MODE 0x0 1 Interleaved burst mode 0 Sequential burst mode The burst mode programmed in the DRAM mode register and the order of the input data to the controller should both match the value programmed in the REG_DDRC_BURST_MODE register 9 2 REG DDRC GO2CRITICAL HYSTER 0x0 Indicates the number of cycles that ESIS CO_GS_GO2CRITICAL_RD or CO_GS_GO2CRITICAL_WR must be asserted before the corresponding queue moves to the critical state in the DDRC 1 REG_DDRC_PREFER_WRITE 0x0 If set the bank selector prefers writes over reads 0 REG_DDRC_FORCE_LOW_PRI_N 0x0 Active Low signal When asserted 0 all incoming transactions are forced to low priority Forcing the incoming transactions to low priority implicitly turns off bypass DDRC PERF PARAM 3 CR Table 7 65 DDRC PERF PARAM 3 CR Bit Reset Number Name Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 REG_DDRC_EN_2T_TIMING_MODE 0x0 1 DDRC uses 2T timing 0 DDRC uses 1T timing 294 Revision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide DDRC_DFI_RDDATA_E
508. ver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden 198 Revision 1 I Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide TX_AMP_RATIO_MARGIN2_FULL Register Table 5 29 TX AMP RATIO MARGIN2 FULL Bit Number Name Reset Value Description 7 0 TX AMP RATIO MARGIN2 FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN3_FULL Register Table 5 30 TX AMP RATIO MARGIN3 FULL Bit Number Name Reset Value Description 7 0 TX AMP RATIO MARGIN3 FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN4_FULL Register Table 5 31 TX AMP RATIO MARGIN4 FULL Bit Number Name Reset Value Description 7 0 TX AMP RATIO MARGIN4 FULL This register implements the TX amplitude ratio used by the TX driver A value of 128 corresponds to 100 full voltage a value of 0 corresponds to 0 Values higher than 128 are forbidden TX_AMP_RATIO_MARGIN5_FULL Register Table 5 32 TX_AMP_RATIO_MARGIN5_FULL
509. vision 1 lt gt Microsemi SmartFusion2 SoC FPGA High Speed Serial and DDR Interfaces User s Guide Table 7 100 PHY Configuration Register Summary continued Reset Register Name Offset Type Source Description PHY_WRLVL_INIT_RATIO_1_CR Ox2EC RW PRESET_N Configuring register for initialization ratio used by write leveling PHY_WRLVL_INIT_RATIO_2_CR 0x2F0 RW PRESET_N Configuring register for initialization ratio used by write leveling PHY_WRLVL_INIT_RATIO_3_CR 0x2F4 RW PRESET_N Configuring register for initialization ratio used by write leveling PHY_WRLVL_INIT_RATIO_4_CR 0x2F8 RW PRESET_N Configuring register for initialization ratio used by write leveling PHY_WR_RD_RL_CR 0x2FC RW PRESET_N Configurable register for delays to read and write PHY_DYN_RDC_FIFO_RST_ERR_CNT_CLR_CR 0x300 RW PRESET_N Reset register for counter PHY_RDC_WE_TO_RE_DELAY_CR 0x304 RW PRESET_N Configurable register for delay between WE and RE PHY_USE_FIXED_RE_CR 0x308 RW PRESET_N Selection register for generating read enable to FIFO PHY USE RANKO DELAYS CR 0x30C RW PRESET N Delay selection This applies to multi rank designs only PHY USE LVL TRNG LEVEL CTRL CR 0x310 RW PRESET N Training control register PHY DYN CONFIG CR 0x314 RW PRESET N PHY dynamically controlled register PHY RD WR GATE LVL CR 0x318 RW
510. vision 1 55 I Microsemi SERDESIF Block SERDESIF Debug Interface SERDESIF has a Debug mode mostly for debugging PCle link A number of internal status error signals are available to the fabric to be used for end to end system debug function In order to keep the number of signals interfacing between the fabric and SERDESIF block to a minimum these debug signals are multiplexed on PRDATA signals of the APB bus Debug mode is enabled only when DEBUG KEY 8 b1010_0101 is written to DEBUG MODE KEY APB system register offset address A8 Table 1 66 on page 56 shows the condition when debug information is available and Table 1 67 on page 56 shows the debug signals that are mapped to APB PRDATA bus Table 1 66 Debug Information Available Conditions Table 1 67 Debug Signa Is Mapping to APB Bus Debug Mode APB Bus Operation APB PRDATA Bus Behavior Enabled Write Debug information Enabled Read APB read data Enabled Idle Debug information Disabled Do not care APB read data APB PRDAT Signals Debug Signal Description APB S PRDATA 0 PHY LOCK STATUS SERDES PHY related status signals Combined status of PHY Tx CDR PLL lock status Only PHY lanes which are used are considered for this phy lock status signal generation When any used PLL s PHY lanes are locked then phy lock status is 1 b1 else it is 1 bO0 Note Individual PHY lane s PLL information is available in SERDES_TEST_OUT register
511. window 0 11 5 AXI SLAVE WINDOWO2 11 5 Reserved 4 2 AXI SLAVE WINDOWO2 4 2 AXI slave window 0 traffic class TC 1 AXI SLAVE WINDOWO2 1 AXI Slave window 0 relaxed ordering RO 0 AXI SLAVE WINDOWO2 0 AXI Slave window 0 no snoop NS AXI SLAVE WINDOWO 3 Register O0CCh Table 2 67 AXI SLAVE WINDOWO 3 Bit Reset Number Name Value Description 31 0 AXI SLAVE WINDOWO3 31 12 MSB of base address PCle window 0 AXI SLAVE WINDOW1 0 Register 0DOh Table 2 68 AXI SLAVE WINDOW1 0 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW10 31 12 Base address AXI slave window 1 11 0 Reserved Reserved AXI SLAVE WINDOW1 1 Register 0D4h Table 2 69 AXI SLAVE WINDOW1 1 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW11 31 12 Size of AXI slave window 1 11 1 AXI SLAVE WINDOW11 31 12 Reserved 0 AXI SLAVE WINDOW11 0 Enable bit of AXI slave window 1 AXI SLAVE WINDOW1 2 Register 0D8h Table 2 70 AXI SLAVE WINDOW1 2 Bit Reset Number Name Value Description 31 12 AXI SLAVE WINDOW12 31 12 LSB of base address PCIe window 1 11 5 AXI SLAVE WINDOW12 11 5 Reserved 4 2 AXI SLAVE WINDOW12 4 2 AXI slave window 0 traffic class TC 1 AXI SLAVE WINDOW12 1 AXI slave window 0 relaxed ordering RO 0 AXI SLAVE WINDOW12 0 AXI slave window 0 no snoop NS 106 Revision 1 lt gt Microsemi
512. write command In this case the controller will first fetch the read data from the DRAM and merge it with the write data from the master then do a write with no bytes masked Revision 1 247 lt gt Microsemi MSS DDR Subsystem 248 Precharge Power Down Entry If REG_DDRC_POWERDOWN_EN 1 the controller automatically enters precharge power down when the period specified by REG_DDRC_POWERDOWN_TO_X32 has passed while the controller is idle except for issuing refreshes Entering precharge power down involves the following steps 1 Precharging closing all open pages Pages are closed one at a time in no specified order 2 Waiting for the tRP row precharge idle period 3 Issuing the command to enter precharge power down NOP Deselect with CKE 0 For multi rank systems all chip selects will be asserted so that all ranks will enter precharge power down simultaneously If the controller receives a read or write request from the core logic during steps 1 and 2 above the power down entry will be immediately aborted The same is true if REG_DDRC_POWERDOWN_EN is driven to 0 during steps 1 or 2 Once the power down entry command has been issued proper power down exit is required as described in the following section Exit Once the controller has put the DDR SDRAM device s in precharge power down mode the controller automatically performs the precharge power down exit sequence for any of the following reasons A ref
513. x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 2 PLL_FB_DEL_SEL 0x0 Selects the delay values that are added to the FPLL feedback clock before being output to the FPLL 00 No buffer delay 01 One buffer delay 10 Two buffers delay 11 Three buffers delay 1 0 PLL_REF_DEL_SEL 0x0 Selects the delay values that are added to the FPLL reference clock before being output to the FPLL 00 No buffer delay 01 One buffer delay 10 Two buffers delay 11 Three buffers delay FDDR_SOFT_RESET Table 8 11 FDDR SOFT RESET Bit Reset Number Name Value Description 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 FDDR_DDR_FIC_SOFTRESET 0x1 When 1 holds the DDR FIC AXI AHB interface controller in reset 0 FDDR CTLR SOFTRESET Ox1 When 1 holds the FDDR subsystem in reset Revision 1 389 I Microsemi Fabric Double Data Rate Subsystem FDDR_IO_CALIB Table 8 12 FDDR 1O CALIB Bit Reset Number Name Value Description 31 15 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with futur
514. xers in the 4 to 1 source glitchless multiplexer FACC_SRC_SEL 0 is used to select the lower source MUX 0 clk_src driven from clk_25_50mhz 1 clk_src driven from clk_xtal FACC_SRC_SEL 1 is used to select the upper source MUX 0 clk_src driven from output of pre_src_mux either clk_1mhz or ccc2asic 1 clk_src driven from mssddr_pll_out_clk FACC SRC SEL 2 is used to select output source MUX 0 clk_src driven from output of lower source MUX 1 clk_src driven from output of upper source MUX 2 0 FACC_STANDBY_SEL 0x0 Selects the standby glitchless multiplexers within the FACC This is used to allow one of four possible clocks to proceed through to the FDDR subsystem during FACC PLL initialization time before the MPLL comes into lock facc_standby_sel 0 is used to select the lower standby MUX 0 clk_standby driven from clk_25_50mhz 1 clk_standby driven from clk_xtal FACC STANDBY SEL 1 is used to select upper standby MUX 0 clk_standby driven from clk_1mhz 1 clk_standby driven from ccc2asic FACC_STANDBY_SEL 2 is used to select the output standby MUX 0 clk_standby driven from output of lower standby MUX 1 clk_standby driven from output of upper standby MUX Revision 1 387 I Microsemi Fabric Double Data Rate Subsystem FDDR_FACC_DIVISOR_RATIO Table 8 9 FDDR FACC DIVISOR RATIO Bit Number Name Reset Value Description 31 8 Reserved 0x0 Software shou
515. y aTXClk aRXCIk clocks The TX clock aTXclk and RX clock aRXClk are divided down and pipelined versions of the high frequency clocks BitClk and S_Clk The TX divider baud clock and RX divider baud clock are divided by 16 versions of the high frequency clocks BitClk and S_Clk The TX clock and RX clock are complementary The exact frequencies of the clocks are determined by the reference clock aRefClk and divide ratio settings M N and F The divide ratio settings M N and F can be programmed from the APB interface on the SERDESIF block Refer to the SmartFusion2 SoC FPGA Datasheet for the aRefClk BitClk S_Clk and T_Clk operating ranges The relationships between FREF FBaudClock FBusClock and bus width are as shown in EQ 1 through EQ 4 FVCO FREF M N F EQ 1 FBaudClock FVCO M FREF N F EQ2 FBusClock FBaud clock N FREF F EQ 3 Bus width FBaud clock FBus clock N EQ4 Note FBaudClock in TX PLL is the EPCS_TX_CLK for EPCS mode FBaudClock in CDR PLL is the EPCS_RX_CLK for EPCS mode and bus width is the EPCS bus width TX clock will only be present and at the correct frequency if all the following are true e Reference clock is present and at correct frequency M N and F are correctly set TX PLL is on e TX clock trees are on Power down mode is off and initialization is done The RX clock will only be present and at the correct frequency with high frequency internal S and T clocks al

SmartFusion2 High Speed Serial and DDR Interfaces User's Guide

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