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Triple-Speed Ethernet MegaCore Function User Guide

1. Sharing PLLs in Devices with LVDS Soft CDR I O For designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft CDR I O you can optimize resource utilization by sharing the PLLs ref_clk tbi tx ck 4 port MAC rx dk1 d tbi rx dk1 ams mo Pe COMPONENT pll clka p Port 1 PCS 1 A m tx dk1 e e AIDS TX e COMPONENT 31 e ndo fu ind ATDS RK e COMPONENT 4 e Lp Port 2 PCS 2 tx dk2 ALTLVDS_TX_ e COMPONENT 4 e rx_clk3 doe ALTLVDS_RX_ 9 COMPONENT e Port 3 PCS 3 tx clk3 e o AIDS TX e COMPONENT 4 e n did M UM Avos RC 4 0 COMPONENT e Port 4 PCS 4 aid ALTLVDS_TX_ A COMPONENT lq The Quartus II software merges the PLLs for these instances if you implement the following items in your design e Connect the reference clock of each instance to the same source e Place the LVDS I O pins on the same side of the FPGA Altera Corporation Design Considerations C Send Feedback UG 01008 2015 06 15 Sharing PLLs in Devices with GIGE PHY
2. ref ck e e tbi tx ck 4 port e MAC lg tx ck en1 i v rx dk 1 Ix dk1 bonc dk ES pll clk1 k1 i I band c gt Port 1 tx dki l tx dk1 gt PCS 1 PLL a diem e ams T e COMPONENT 9 tx dk en2 4 T i Log Donc dio ALTLVDS _RX_ e IX Cl IX Cl dk2 Port 2 COMPONENT d gt tx dk2 tx dk2 la xC Pa p PCS 2 Ix dk en2 lt q ALTLVDS TX COMPONENT qe tx_clk_en3 Lg Phe WEE m dk3 rx dk3 qe dk3 Port 3 9 p gt la tx dk3 tx dk3 gt PCS 3 Ix dk en3 o ALTLVDS TX 4 9 mM COMPONENT 4 o tx dk en4 tbi rx dk4 ALTLVDS _RX_ e6 a 4 COMPONENT g la x dk4 e tks dk4 gt Port 4 dd waka PG 4 ue x AUS TX SES COMPONENT Design Considerations Altera Corporation LJ Send Feedback 8 6 Sharing PLLs in Devices with LVDS Soft CDR I O UG 01008 2015 06 15 Figure 8 4 Clock Distribution in MAC and 1000BASE X PCS with LVDS Configuration Optimal Case Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the MAC 1000BASE X PCS and LVDS Soft CDR I O dk1 dk2 dk3 clk4
3. Note to Figure 8 2 1 The PMA layer in devices with GX transceivers uses ALTGX megafunctions MAC and PCS With LVDS Soft CDR I O 4 port MAC e n dki tbi rx dk1 det x Port 1 PCS 1 tx dk lt lt Y Quad 2 e Transceivers tx ALTGX GIGEMode tbi rx dk2 IX dk2 Lean E ls Port 2 PCS 2 ALTGX GIGEMode tbi ix dk e tbi nx dia ALTGX 3 rx dk3 GIGEMode zi i Port 3 PCS 3 E tx dk3 e ALTGX e GIGEMode 2 vv Lun dk4 rx dk4 dk4 Port 4 tx dk4 PCS 4 9 In configurations that contain the MAC PCS and LVDS Soft CDR I O you have the following options in optimizing clock resources Altera Corporation Design Considerations C Send Feedback UG 01008 2015 06 15 MAC and PCS With LVDS Soft CDR I O 8 5 e Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance e Utilize the same clock source to drive the reference clock FIFO transmit and receive clocks and system clocks if these clocks run at the same frequency Figure 8 3 Clock Distribution in MAC and SGMII PCS with LVDS Configuration Optimal Case Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the MAC SGMII PCS and LVDS Soft CDR I O
4. PMA CDR amp Deserializer PHY Loopback Serializer 1 25 Gbps Serial Receive 1 25 Gbps Serial Transmit Status LEDs mE M MAC Side 1000BASE X SGMII PCS with PMA 1000 Base X PCS Receive Control SGMII MIVGMII lt i Receive poses e gt De encapsulation 8b 10b Synchronization Decoder i AutoNegotiation 1000 Base X PCS Transmit Control _SGMII MIVGMII Transmit gt Transmit Converter Encapsulation ER 8b 10b Encoder Configuration i Avalon MM Interface Transmit Operation The transmit operation includes frame encapsulation and encoding Frame Encapsulation The PCS function replaces the first preamble byte in the MAC frame with the start of frame S symbol Then the PCS function encodes the rest of the bytes in the MAC frame with standard 8B 10B encoded characters After the last FCS byte the PCS function inserts the end of frame sequence T R R or T R depending on the number of character transmitted Between frames the PCS function transmits I symbols If the PCS function receives a frame from the MAC function with an error gm_tx_err asserted during frame transmission the PCS function encodes the error by inserting a V character 8b 10b Encoding The 8B 10B encoder maps 8 bit
5. Note to Figure 8 1 1 The PMA layer in devices with GX transceivers uses ALTGX megafunctions ref ck e e 4 port MAC ref_clk tx_ck_en1 vy lt k ik tbi rx dk1 Quad la rx di rx dk1 e e Transceivers dk1 tx dki PCS 1 gt Port 00 e a tbi tx dii le IX dk eni Te ALTGX k B GIGEMode t Z la tx dk en2 bi k2 rx dk2 rx dk2 DUE AS d R la e GIGEMode Port 2 tx dk2 tx di2 e PG 2 tbi tx clk2 Ix dk en2 lt ALTGX GIGEMode tx dk en3 tbi rx clk3 Ix dk3 Ix dk3 dk3 b Ik M Ik3 PCS 3 tx dk3 vale T Port 3 la e tbi tx dk3 ALTGX la IX dk en3 GIGEMode a eo tx dk en tbi rx dk4 E lid lid E di X c ELS PCS 4 la tx dk4 tx dk4 gt tbi tx dk4 Ei Ix dk en1 E x vv In addition to the aforementioned optimization options the TBI transmit and receive clocks can be used to drive the MAC transmit and receive clocks respectively Design Considerations LJ Send Feedback Altera Corporation 8 4 MAC and PCS With LVDS Soft CDR I O UG 01008 2015 06 15 Figure 8 2 Clock Distribution in MAC and 1000BASE X PCS with GXB Configuration Optimal Case Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the 10 100 1000 Ethernet MAC 1000Base X PCS and GX transceivers ref ck
6. IX ck rx_control rgmii in 3 0 0 y LLL Ls 15 V 130040000300 A frame received on the RGMII interface with a PHY error indication is subsequently transferred on the Avalon ST interface with the error signal rx_err 0 asserted Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 MII Transmit 7 47 Figure 7 21 RGMII Receive with Error in Gigabit Mode wma 9X We NE The current implementation of the RGMII receive interface expects a positive delay rx_c1k relative to the receive data the clock comes after the data MII Transmit On transmit all data transfers are synchronous to the rising edge of tx_c1k The MII data enable signal m_tx_en is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m_tx_d 3 0 bus Between frames m_tx_en remains deasserted If a frame is received on the FIFO interface with an error tx err asserted the frame is subsequently transmitted with the MII error signal m tx err for one clock cycle at any time during the frame transfer MII Receive On receive all signals are sampled on the rising edge of rx_cik The MII data enable signal m xx en is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m rx d 3 0 bus Between frames m xx en remains deasserted If the PHY
7. tx dk i tx control j Uu rgmii out 3 0 0 y ee S un rA a E eels ee E Ne gt lt p jo Interface Signals Altera Corporation C Send Feedback UG 01008 7 46 RGMII Receive 2015 06 15 Figure 7 17 RGMII Transmit in Gigabit Mode ma LPL LULU UL e eee ee 1 i 1 tx control i i i i i I I i L D I I I l lj V L rgmii_out 3 0 5 If a frame is received on the Avalon ST interface with an error tx err asserted with tx eop the frame is subsequently transmitted with the RGMII tx contxo1 error signal at the falling edge of cx c1x at any time during the frame transfer Figure 7 18 RGMII Transmit with Error in 1000 Mbps mig o Y Wk Aso RC exeo RGMII Receive On receive all signals are sampled on both edges of rx_c1k The RGMII control signal xx control is asserted by the PHY to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on rgmii_in 3 0 bus Between frames xx contro1 remains deasserted Figure 7 19 RGMII Receive in 10 100 Mbps IX ck M rx control d Un nmi io oJ Figure 7 20 RGMII Receive in 1000 Mbps
8. 5 ff rx data 31 0 00000000 00000000 X 00000001 X 00000002 00000003 0000004 00000005 00000000 ff rx sop ff_rx_eop ff rx rdy ff rx dval ff 1x dsav J rx_frm_type 3 0 0 Y 1 M y 0 rx_err_stat 17 0 00000 Y 004 X 00000 Ix err 5 0 00 ff_rx_mod 1 0 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 Avalon ST Receive Interface 7 43 Figure 7 11 Receive Operation MAC Without Internal FIFO Buffers mac rx dk 0 data rx data 0 7 0 00 o3 Xos jos 06 m os fos X10 X10 X10 J 10 Yoo data_rx_sop_0 data_rx_eop_0 7 r data rx error 0 4 0 00 J data_rx_valid_0 i pkt dass data 0 4 0 0 y 10 f j j j data rx ready 0 f Y j pkt dass valid 0 Figure 7 12 Invalid Length Error During Receive Operation MAC With Internal FIFO Buffer wx LI LD LELEL S LU LIU ff_rx_data 31 0 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 ff_rx_sop FOX ff rx eop ff rx dval ff 1x dsav rx_frm_type 3 0 0 1 y 0 rx_err_stat 17 0 00000 Y 005DD y 00000 rx_err 5 0 00 03 00 ff_rx_mod 1 0 0 W i 3 0 je M MV M j
9. tx egress timestamp request valid y tx_egress_timestamp_request_data N 0 Fingerprint JJ K 2 step Timestamp Return Output tx egress timestamp 96b valid D A tx egress timestamp 96b fingerprint N 0 W Y Fingerprint Y tx egress timestamp 96b data 95 0 W 96b Egress Timestamp tx egress timestamp 64b valid tx egress timestamp 64b fingerprint N 0 f Y Fingerprint J tx egress timestamp 64b data 63 0 A Y 64b Egress Timestamp 1 step Timestamp Insert Input tx etstamp ins ctrl timestamp insert tx_etstamp_ins_ctrl_timestamp_format Don t care W Don t care 1 step Residence Time Update Input tx etstamp ins ctrl residence time update tx_etstamp_ins_ctrl_ingress_timestamp_96b 95 0 Don t care W Don t care tx etstamp ins ctrl ingress timestamp 64b 63 0 Don t care W Don t care tx etstamp ins ctrl residence time calc format Don t care W Don t care 1 step IPv4 and IPv6 Checksum Input tx etstamp ins ctr checksum zero Don t care W Don t care tx etstamp ins ctrl checksum correct Don t care W Don t care 1 step Location Offset Input tx etstamp ins ctrl offset timestamp 15 0 Don t care W Don t care tx etstamp ins ctrl offset correction field 15 0 Don t care W Don t care tx etstamp ins ctrl offset checksum field 15 0 Don t care Y Don t care tx etstamp ins ctrl offset checksum comectionl5 0 Dontae WS Don t car
10. 4 27 Altera FPGA Osc 25MHz gt 25MHz 25 2 5 MHz clk_inkxtali E Clock Driver tx dk tx dk gtx clk mtx 0 0 txd7 0 a mter fora gm tx 7 0 X erre gm tx en gm tx err Optional tie to 0 th mod 10 10 1000 ifnotued egg 1100 1000 PHY gt set 10 Ethernet Unused en 10 MAC n ck 125 25 2 5 MHz gt l nx clk m_rx_d 3 0 p m Ix en p m IX err rxd 7 0 gt gm rx d 7 0 rx dv ot gt gm rx dv IX eir e Qm rx err Figure 4 13 10 100 1000 PHY Interface via RGMII Reference Clock 125 MHz L Altera FPGA Clock ena 10 dk in tali Divider eth mode gx dk 4 gt tx ck txen le tx_control txd 3 0 rgmii out 3 0 Optional tie to 0 i bos 1 A erne noonoo fme etg iem ee set 10 rx_clk Ix ck Ix dv y Ix control rxd 3 0 gt rgmii in 3 0 Functional Description LJ Send Feedback Altera Corporation UG 01008 4 28 1000BASE X SGMII PCS With Optional Embedded PMA 2015 06 15 1000BASE X SGMII PCS With Optional Embedded PMA The Altera 1000BASE X SGMII PCS function implements the functionality specified by IEEE 802 3 Clause 36 The PCS function is accessible via MII SGMII or GMII 1000BASE X SGMII The PCS function interfaces to an on or off chip SERDES component via the industry standard ten bit interface TBI You can co
11. The components Master TOD clock domain consists of three interfaces clk_master reset_master and tod master data Slave TOD clock domain consists of five interfaces c1k slave reset slave tod slave valid tod slave data and Start tod sync Sampling clock PLL consists of the c1k domain interface The Tod synchronizer module synchronizes the master ToD clock domain with the slave ToD clock domain The dual clock FIFO in the Tod synchronizer block takes in the time of day from the master ToD clock domain and transfers it to the slave ToD clock domain The slave ToD then will load the synchron ized time of day into its own internal counter which then increments based on the new value As the ToD transfer is in progress the master ToD domain keeps incrementing When the ToD reaches the slave ToD clock domain and is ready to be loaded it is much slower than the master ToD To achieve high accuracy synchronization the latency caused by the transfer must be reflected in the synchronized ToD The sampling clock PLL c1k sampling samples the FIFO fill level and calculates the latency through the FIFO For better accuracy the sampling clock must be derived from the master clk_master or slave clk slave clock domain using a PLL If you use the recommended sampling clock frequency the Tod synchronizer module takes 64 clock cycles of sampling clock for every newly synchronized ToDto be valid at the output port A
12. 7 45 RGMII Transmit msasani eh et e HERE EUER HERE RE EUER RS RO IEEE ER 7 45 hend 7 46 MIU Lransmit uae iit tas ai ord iere re e D re ERU Cet Hd ert Perkins Fee Rate 7 47 MID RECOIV 7 47 IEEE 1588v2 Timestamp tienen tereti ea co tee te te debeat Ld nra a feda 7 47 Design Consider ating M RR 8 1 Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 8 1 MAC aud PCS With GX ST aTiS COT VES iissscsssistssadenssabannveabastansonaiannsedsussace iaaiiai sa saasina at 8 2 MAC and PCS With LVDS Soft CDR Veo reeertt tope ves tr entia rite ette v E meen 8 4 Sharing PLLs in Devices with LVDS Soft CDR I O acoge estie M ed pxet kot Ri ER IE MOI Ec TERI REA 8 6 Sharing PLLs in Devices with GIGB PHY aae cietteti HE EIN dad OR dise ei eim NM 8 7 Sharing Transceiver cr D aea 8 7 Migrating From Old to New User Interface For Existing Designs sse 8 7 Exposed Ports in the New User Iuteriace oer tkt pei MN etd ica odd qe ite a 8 7 Timing Constraints mme 9 1 Creating Clock Constraints aucune testen iid ca ron NERONE RR scale an ADRENAL REVENE 9 1 Recommended Glock Erequetiey seonsnaedpedivasete eii rue qqivbdns Vac p htec ceva ehe pev ep Leti E Med 9 3 Altera Corporation TOC 5 E UISQdM TP UU UU UT 10 1 Triple Speed Ethernet Testoench Architecture 2a
13. MAC only Avalon ST GMII MII RGMII Avalon ST Frame Avalon ST Frame Generator Monitor MAC with PCS Avalon ST TBI Avalon ST Frame Avalon ST Frame Generator Monitor MAC with PCS Avalon ST 1 25 Gbps Avalon ST Frame Avalon ST Frame and embedded Generator Monitor PMA PCS only GMII MII TBI GMII MII Frame GMII MII Frame Generator Monitor PCS with GMII MII 1 25 Gbps GMII MII Frame GMII MII Frame embedded Generator Monitor PMA Testbench Verification The testbench is self checking and determines the success of a simulation by verifying the frames received It also checks for any errors detected by the frame monitors The testbench does not verify the IEEE statistics generated by the MAC layer Simulation fails only if the testbench is not able to detect deliberately inserted errors At the end of a simulation the testbench displays messages in the simulator console indicating its results Altera Corporation Testbench G send Feedback UG 01008 2015 06 15 Testbench Configuration 10 3 The testbench verifies the following functionality e Transmit and receive datapaths are functionally correct Ethernet frames generated by the frame generator are received by the frame monitor e Additional checks for configurations that contain the MAC function Correct CRC 32 is inserted Short frames are padded up to at least 64 bytes in length Untagged received frames of size greater than the maxim
14. Altera Corporation Time of Day ToD Clock C Send Feedback UG 01008 2015 06 15 ToD Clock Interface Signals Figure C 1 Time of Day Clock Interface Signals Avalon MM Control Interface Signals Avalon ST Transmit Interface ToD Clock Interface Signals C 3 ToD Clock P cr address p csr read P cer write csr writedata dk ntn period_clk time_of_day_96b_load_valid time of day 96b load data csr readdata time of day 96 96 Signals x 64 time of day 64b load valid time of day 64 y Gr readdata gt time of day 64b load data a ToD Clock Avalon MM Control Interface Signals Table C 4 Avalon MM Control Interface Signals for ToD Clock a INIM NN NN NN csr address Input Use this bus to specify the register address you want to read from or write to csr read Input Assert this signal to request a read csr readdata Output Carries the data read from the specified register csr write Input Assert this signal to request a write csr writedata Input Carries the data to be written to the specified register clk Input Register access reference clock rst_n Input Assert this active low signal to reset the ToD clock Time of Day ToD Clock LJ Send Feedback Altera Corporation C4 ToD Clock Avalon ST Transmit Interface Signals UG 01008 2015 06 15 ToD Clock A
15. rx clkena O Receive clock enabler In SGMII mode this signal enables xx cik Interface Signals Altera Corporation C Send Feedback UG 01008 J GMII 2015 06 15 tx_clkena O Transmit clock enabler In SGMII mode this signal enables t x_ Lis Figure 7 8 Clock Enabler Signal Behavior mua LILI LIL UU UU UU LT LE LT UE LFU LE LE LT LT LT U 25 MHz Clock Enable J J Input Data OxEE ouput ata aoa ue C GMII Table 7 39 GMII Signals GMII Transmit Interface gmii tx d 7 0 I GMII transmit data bus gmii tx en I Assert this signal to indicate that the data on gmii tx d 7 0 is valid gmii tx err I Assert this signal to indicate to the PHY device that the current frame sent is invalid GMII Receive Interface gmii rx d 7 0 O GMII receive data bus gmii_rx_dv O Asserted to indicate that the data on gmii_rx_d 7 0 is valid Stays asserted during frame reception from the first preamble byte until the last byte in the CRC field is received gmii rx err O Asserted by the PHY to indicate that the current frame contains errors MII Table 7 40 MII Signals MII Transmit Interface mii tx d 3 0 I MII transmit data bus mii tx en I Assert this signal to indicate that the data on mii tx d 3 0 is valid Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 SGMII Status Signals 7 39 mii tx err I Ass
16. 64 Use this bus to carry the time of day from external ToD module to 64 bit MAC RX clock Consists of 48 bit nanoseconds field and 16 bit fractional nanoseconds field Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 IEEE 1588v2 PCS Phase Measurement Clock Signal 7 35 IEEE 1588v2 PCS Phase Measurement Clock Signal Table 7 34 IEEE 1588v2 PCS Phase Measurement Clock Signal ee INNEN NN pcs phase measure clk Sampling clock to measure the latency through the PCS FIFO buffer The recommended frequency is 80 MHz IEEE 1588v2 PHY Path Delay Interface Signals Table 7 35 IEEE 1588v2 PHY Path Delay Interface Signals a NI INNEN NN tx path delay data Use this bus to carry the path delay on the transmit datapath The delay is measured between the physical network and MII GMII to adjust the egress timestamp Bits 0 to 9 Fractional number of clock cycles Bits 10 to 21 Number of clock cycles rx path delay data I 22 Use this bus to carry the path delay on the receive datapath The delay is measured between the physical network and MII GMII to adjust the ingress timestamp Bits 0 to 9 Fractional number of clock cycles Bits 10 to 21 Number of clock cycles Interface Signals Altera Corporation C Send Feedback x UG 01008 7 36 1000BASE X SGMII PCS Signals 2015 06 15 1000BASE X SGMII PCS Signals Figure 7 7 1000BASE X SGMII PCS
17. Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 PHY Management Signals 7 11 m rx d 3 0 I MII receive data bus m rx en I Assert this signal to indicate that the data on the MII receive data bus is valid Keep this signal asserted during frame reception from the first preamble byte until the last byte of the CRC field is received m rx err I The PHY asserts this signal to Indicate that the receive frame contains errors MII PHY Status m rx col I Collision detection The PHY asserts this signal to indicate a collision during frame transmission This signal is not used in full duplex or gigabit mode m rx crs I Carrier sense detection The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line This signal is not used in full duplex or gigabit mode PHY Management Signals Table 7 11 PHY Management Interface Signals mdio in I Management data input mdio out O Management data output mdio_oen O An active low signal that enables n io in or mdio_out For more information about the MDIO connection refer to MDIO Connection on page 4 23 mdc O Management data clock Generated from the Avalon MM interface clock signal c1x Specify the division factor using the Host clock divisor parameter such that the frequency of this clock does not exceed 2 5 MHz For more information about the parameters refer to Ethe
18. This option is always turned on in devices other than Arria GX and Stratix II GX When this option is turned on the MegaCore function includes the dynamic reconfiguration signals For designs targeting devices other than Arria V Cyclone V Stratix V and Arria 10 Altera recommends that you instantiate the ALTGX_RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation For Arria V Cyclone V and Stratix V designs Altera recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation The transceivers in the Arria V Cyclone V and Stratix V designs are configured with Altera Custom PHY IP core The Custom PHY IP core require two reconfiguration interfaces for external reconfiguration controller For more information on the reconfiguration interfaces required refer to the Altera Transceiver PHY IP Core User Guide and the respective device handbook For more information about quad sharing considera tions refer to Sharing PLLs in Devices with GIGE PHY on page 8 7 Altera Corporation Parameter Settings C Send Feedback UG 01008 2015 06 15 PCS Transceiver Options 3 7 Starting channel 0 284 Specifies the channel number for the GXB transceiver number block In a multiport MAC this parameter specifies the c
19. ANU amp RYA 101 Innovation Drive San Jose CA 95134 n UG 01008 11 2 Directory Structure 2015 06 15 Directory Structure Structure of the altera triple speed ethernet directory Figure 11 2 Directory Structure altera triple speed ethernet inc triple speed ethernet h altera avalon tse h altera avalon tse system info h altera avalon tse c altera avalon tse system info c triple speed ethernet regs h UCOSII inc Lf iniche ins tse mach m triple speed ethernet iniche h 7 iniche Ins tse macc PHY Definition By default the software driver only supports the following PHYs e National DP83848C 10 100 Mbps e National DP83865 10 100 1000 Mbps e Marvell 88E1111 10 100 1000 Mbps e Marvell 88E1145 Quad PHY 10 100 1000 Mbps You can extend the software driver to support other PHYs by defining the PHY profile using the structure alt tse phy profile and adding it to the system using the function a1t tse phy add profile For each PHY instance use the structure alt tse system phy struct to define it and the function alt tse system add sys to add the instance to the system The software driver automatically detects the PHY s operating mode and speed if the PHY conforms to the following specifications e One bit to specify duplex and two consecutive bits the higher bit being the most significant bit to specify the speed in the same extended PHY specific register The
20. variation name testbench directory Note Generating a design example can increase processing time You can now integrate your custom IP core instance in your design simulate and compile While integrating your IP core instance into your design you must make appropriate pin assignments You can create a virtual pin to avoid making specific pin assignments for top level signals while you are simulating and not ready to map the design to hardware Related Information e Testbench More information about the MegaCore function simulation model Quartus II Help More information about the Quartus II software including virtual pins Simulate the System During system generation Qsys generates a functional simulation model or design example that includes a testbench which you can use to simulate your system in any Altera supported simulation tool Related Information e Quartus II Software Release Notes More information about the latest Altera supported simulation tools e Simulating Altera Designs More information in volume 3 of the Quartus II Handbook about simulating Altera IP cores e System Design with Qsys More information in volume 1 of the Quartus II Handbook about simulating Osys systems Compiling the Triple Speed Ethernet MegaCore Function Design Before you begin Refer to Design Considerations on page 8 1 chapter before compiling the Triple Speed Ethernet MegaCore function design Altera Corporation Getting Sta
21. Additional Information C Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet IP Core Document Revision History F 5 ELE NN E CON May 2013 13 0 Updated the MegaWizard Plug In Manager flow in Getting Started with Altera IP Cores Added information about generating a design example and simulation testbench in Generating a Design Example or Simulation Model on page 2 2 Updated the list of Quartus II generated files Added information about the recommended pin assignments in Design Constraint File No Longer Generated on page 2 4 Updated the MegaCore parameter names and description in Parameter Settings Updated the IEEE 1588v2 feature list in Functional Description Updated the SGMII auto negotiation description in Functional Description Added information about the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay on page 6 17 Updated the Multiport Ethernet MAC with IEEE 1588v2 1000BASE X SGMII PCS and Embedded PMA Signals Updated the IEEE 1588v2 timestamp signal names Added timing diagrams for IEEE 1588v2 timestamp signals Added a section about migrating existing design to the Quartus II software new MegaCore user interface in Design Considerations Updated Timing Constraints chapter to describe the new timing constraint files and the recommended clock input frequency for each MegaCore Function variant Added information about the simulation model files generated using IEEE simulation encrypti
22. Prototype alt tse system add sys alt tse system mac psys mac alt tse System sgdma psys sgdma alt tse system desc mem psys mem alt tse system shared fifo psys shared fifo alt tse system phy psys phy Thread safe No Available from No ISR Include system h system h altera avalon tse system info h altera avalon tse h altera avalon tse system info h altera avalon tse system info h altera avalon tse system info h Description Theait tse system add sys function defines the TSE system s components MAC scatter gather DMA memory FIFO and PHY This needs to be done for each port in the system Parameter psys mac A pointer to the MAC structure psys_sgdma A pointer to the scatter gather DMA structure psys_mem A pointer to the memory structure psys_shared_fifo A pointer to the FIFO structure psys_phy A pointer to the PHY structure Return SUCCESS if the operation is successful succgss if the operation is successful ALTERA_TSE_MALLOC_FAILED if the operation fails ALTERA TSE SYSTEM DEF ERROR if one or more of the definitions are incorrect or empty triple_speed_ethernet_init Prototype error_t triple_speed_ethernet_init alt_niche_dev p_dev Thread safe No Available from No ISR Include lt triple_speed_ethernet_iniche h gt Software Programming Interface CJ
23. SGMII mode with PHY mode Similar to 1e an and auto negotiation dev ability 15 led crs When asserted this signal indicates some activities on the transmit and receive paths When deasserted it indicates no traffic on the paths led col When asserted this signal indicates that a collision was detected during frame transmission This signal is always deasserted when the PCS function operates in standard 1000BASE X mode or in full duplex mode when SGMII is enabled led an Auto negotiation status The PCS function asserts this signal when an auto negotiation completes led char err 10 bit character error Asserted for one tbi rx clk cycle when an erroneous 10 bit character is detected Interface Signals CJ Send Feedback Altera Corporation UG 01008 7 20 SERDES Control Signals 2015 06 15 led disp err O 10 bit running disparity error Asserted for one tbi rx clk cycle when a disparity error is detected A running disparity error indicates that more than the previous and perhaps the current received group had an error SERDES Control Signals Table 7 21 SERDES Control Signal powerdown O Power down enable Asserted when the PCS function is in power down mode deasserted when the PCS function is operating in normal mode This signal is implemented only when an external SERDES is used sd loopback O SERDES Loopback Control Asserted when the
24. For transceiver quad sharing between Triple Speed Ethernet IP core and other IP cores that target these devices reset signal for all the cores must be from the same source Refer to the respective device handbook for more information on dynamic reconfiguration signals in Altera devices Migrating From Old to New User Interface For Existing Designs In Quartus II software ACDS 13 0 release the old Triple Speed Ethernet MegaCore function user interface is deprecated Existing Triple Speed Ethernet designs generated prior to the ACDS 13 0 release can still load properly in ACDS 13 0 However starting from ACDS 13 1 release the old Triple Speed Ethernet interface and the design generated using the old interface will not be supported You need to manually migrate your design to the new user interface Reopening and saving the existing design created with the old user interface will not automatically convert the design to the new user interface To migrate your design to the new user interface launch the Quartus II software ACDS 13 0 or higher create a new project and specify the parameters as described in Design Walkthrough on page 2 1 Exposed Ports in the New User Interface In the new user interface in Qsys for a design that has a MAC function you have to manually connect the exposed ports or terminate them In MAC variation with internal FIFO buffers the ready latency is two in both standalone and Qsys flow The Qsys system inserts
25. Stratix V Arria V and Cyclone V devices with GX transceivers 1 25 Gbps Serial Interface If the variant includes an embedded PMA the PMA provides a 1 25 GHz serial interface Table 7 25 1 25 Gbps MDI Interface Signals ref clk I 125 MHz local reference clock oscillator rx p I Serial Differential Receive Interface tx p O Serial Differential Transmit Interface Transceiver Native PHY Signal Table 7 26 Transceiver Native PHY Signal a a NNNM cdr ref clk n Port to connect the RX PLL reference clock with a frequency of 125 MHz when you enable SyncE support SERDES Control Signals These signals apply only to PMA blocks implemented in devices with GX transceivers Table 7 27 SERDES Control Signal rx recovclkout O Recovered clock from the PMA block pcs pwrdn out O Power down status Asserted when the PCS function is in power down mode deasserted when the PCS function is operating in normal mode This signal is implemented only when an internal SERDES is used with the option to export the power down signal This signal is not present in PMA blocks implemented in Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers gxb pwrdn in I Power down enable Assert this signal to power down the transceiver quad block This signal is implemented only when an internal SERDES is used with the option to export the power down signal This signal is not present in PMA blocks implemented in Arria
26. This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers You must turn on this option if you intend to use the Triple Speed Ethernet MegaCore function with the Interniche TCP IP protocol stack Parameter Settings LJ Send Feedback Altera Corporation 3 4 FIFO Options UG 01008 2015 06 15 A KNEE 7 HN Enable full duplex On Off Turn on this option to include the logic for full duplex flow control flow control that includes pause frames generation and termination Enable VLAN On Off Turn on this option to include the logic for VLAN and detection stacked VLAN frame detection When turned off the MAC does not detect VLAN and staked VLAN frames The MAC forwards these frames to the user applica tion without processing them Enable magic On Off Turn on this option to include logic for magic packet packet detection detection Wake on LAN MDIO Module Include MDIO On Off Turn on this option if you want to access external PHY module MDC devices connected to the MAC function When turned MDIO off the core does not include the logic or signals associated with the MDIO interface Host clock divisor Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface The default value is 40 For example if the MAC control interface clock frequency is 100 MHz and the des
27. When software reset is triggered the MAC function completes the current transmission or reception and subsequently disables the transmit and receive logic flushes the receive FIFO buffer and resets the statistics counters 14 MHASH SEL RW Hash code mode selection for multicast address resolution e Set this bit to 0 to generate the hash code from the full 48 bit destination address e Set this bit to 1 to generate the hash code from the lower 24 bits of the destination MAC address 15 LOOP ENA RW Local loopback enable Set this bit to 1 to enable local loopback on the RGMII GMII MII of the MAC The MAC function sends transmit frames back to the receive path This bit is not available in the small MAC variation 18 16 TX ADDR SEL 2 0 RW Source MAC address selection on transmit If you set the TX ADDR INS bit to 1 the value of these bits determines the MAC address the MAC function selects to overwrite the source MAC address in frames received from the user application e 000 primary address configured in the nac 0 and mac 1 registers e 100 supplementary address configured in the smac_0_ 0 and smac 0 1 registers e 101 supplementary address configured in the smac 1 0 and smac 1 1 registers e 110 supplementary address configured in the smac_2_ 0 and smac 2 1 registers e 111 supplementary address configured in the smac 3 0 and smac 3 1 registers Co
28. eS INNEN NN tx egress timestamp request valid n I Assert this signal when a user defined tx egress timestamp is required for a transmit frame Assert this signal in the same clock cycle as the start of packet avalon_ St tx startofpacket Of avalon st tx startofpacket nis asserted tx egress timestamp request fingerprint Use this bus to specify fingerprint for the user defined tx egress timestamp The fingerprint is used to identify the user defined timestamp The signal width is determined by the TSTAMP FP WIDTH parameter default parameter value is 4 The value of this signal is mapped to user fingerprint This signal is only valid when you assert tx egress timestamp request valid IEEE 1588v2 TX Insert Control Timestamp Signals Table 7 32 IEEE 1588v2 TX Insert Control Timestamp Interface Signals EE CENE NCC NEN NN tx etstamp ins ctrl timestamp insert n Assert this signal to insert egress timestamp into the associated frame Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted Interface Signals C Send Feedback Altera Corporation 7 32 IEEE 1588v2 TX Insert Control Timestamp Signals UG 01008 2015 06 15 a NN NN tx etstamp ins ctrl timestamp format Timestamp format of the frame which the timestamp inserts 0 1588v2 format 48 bits second field 32 bits nanosecond fie
29. generation of a pause frame with a pause quanta configured in the pause quant register The MAC function generates the pause frame independent of the status of the receive FIFO buffer This signal is not in use in the following conditions P Ignored if the xo gen bit in the command con ig register is set to 1 e Absent when the Enable full duplex flow control option is turned off Assert this active low signal to put the node into a power down state If magic packets are supported the macrc_kEna bit in the command config register is set to 1 the receiver logic stops writing data to the receive FIFO buffer and the magic packet detection logic is enabled Setting this signal to 1 restores the normal frame reception mode This signal is present only if the Enable magic packet detection option is turned on magic wakeup If the MAC function is in the power down state the MAC function asserts this signal to indicate that a magic packet has been detected and the node is requested to restore its normal frame reception mode This signal is present only if the Enable magic packet detection option is turned on Interface Signals LJ Send Feedback Altera Corporation UG 01008 7 10 MII GMII RGMII Signals 2015 06 15 MII GMII RGMII Signals Table 7 10 GMII RGMII MII Signals GMII Transmit gmetad 7 80 GMII transmit data bus gm tx en Asserted to indicate that the data on the GMII transmi
30. lt variation_name gt run_ lt variation_name gt _tb tcl testbench_vhdl lt variation_name gt A signal tracing macro script used with the ModelSim lt variation_name gt _wave do or simulation software to display testbench signals testbench_verilog lt variation_name gt lt variation_name gt _wave do testbench_vhdl models or A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench_verilog models testbench Design Constraint File No Longer Generated For a new Triple Speed Ethernet MegaCore function created using the Quartus II software ACDS 13 0 or later the Quartus II software no longer generate the lt variation_name gt _constraints tcl file that contains the necessary constraints for the compilation of your MegaCore Function variation Table 2 2 lists the recommended Quartus II pin assignments that you can set in your design Table 2 2 Recommended Quartus II Pin Assignments Quartus II Pin Assignment Description Design Pin Assignment WELT FAST_ To optimize I O timing for MII MIL GMII RGMII TBI input INPUT GMII and TBI interface pins REGISTER FAST ON To optimize I O timing for MII MII GMII RGMII TBI output OUTPUT GMII and TBI interface pins REGISTER IO 1 4 V PCML I O standard for GXB serial input GXB transceiver serial input and STANDARD jor 1 5 V and output pins output pins PCML IO LVDS I O standard for
31. rc RE on the rising edge of xx c1x connection tx clkena I Clock enable from the PHY IP When you turn on the Use clock enable for MAC parameter this signal is used together with t x_ clk and rx_clk to generate 125 MHz 25 MHz and 2 5 MHz clocks rx clkena I Clock enable from the PHY IP When you turn on the Use clock enable for MAC parameter this signal is used together with t x_ clk and rx_clk to generate 125 MHz 25 MHz and 2 5 MHz clocks 9 Table 7 2 Reset Signal reset I Assert this signal to reset all logic in the MAC and PCS control interface The signal must be asserted for at least three clock cycles MAC Control Interface Signals The MAC control interface is an Avalon MM slave port that provides access to the register space Table 7 3 MAC Control Interface Signals Avalon MM Description Signal Type Register access reference clock Set the signal to a value less than or equal to 125 MHz reg_wr write I Register write enable reg_rd read I Register read enable reg_addr 7 0 address I 32 bit word aligned register address reg data in 31 0 writedata I Register write data Bit 0 is the least signifi cant bit For configurations without internal FIFO this signal is called tx cikena n 99 For configurations without internal FIFO this signal is called rx_clkena_ lt n gt Interface Signals Altera Corporation C Send Feedback MAC Status Signals
32. 1 10 100 1000 Ethernet MAC With Internal FIFO Buffers Systeme 10 100 1000 Ethernet MAC with Internal FIFO Buffers nem Local Receiver Control Loopback MACReceive 1 MIIGMILRGMII Interface gt FIO Buffer Pause Receive Avalon ST CRC Check Frame Termination neten i Transmitter Control ransmit F H Interface 17 gt ae m Pause Transmit Avalon ST i Frame oana Generation Generation mn i Magic Packet Configuration and PHY Detection g Statistics gt MDIO Master t Management Interface mu cum Avalon The FIFO buffers which you can configure to 8 or 32 bits wide store the transmit and receive data The buffer width determines the data width on the Avalon ST receive and transmit interfaces You can configure the FIFO buffers to operate in cut through or store and forward mode using the rx section fullandtx section full registers Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 MAC Interfaces 4 3 Figure 4 2 Multiport MAC Without Internal FIFO Buffers System Side Multiport MAC Without Internal FIFO Buffers Ethernet Side Avalon ST Port Loopback MII GMII RGMII Receiver Control p Rehek
33. 32 ESSO startofpacket O Receive start of packet Asserted when the first byte or word of a frame is driven on _rx_ data DATAWIDTH 1 0 ff_rx_eop endofpacket O Receive end of packet Asserted when the last byte or word of frame data is driven on ff_ rx data DATAWIDTH 1 0 Ibis Ges egy ready I Receive application ready Assert this signal on the rising edge of xx c1k when the user application is ready to receive data from the MAC function rx err 5 0 error O Receive error Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame See Table 7 7 for the bit description Component Specific Signals ff_rx_dsav O Receive frame available When asserted this signal indicates that the internal receive FIFO buffer contains some data to be read but not necessarily a complete frame The user application may want to start reading from the FIFO buffer This signal remains deasserted in the store and forward mode Interface Signals LJ Send Feedback Altera Corporation UG 01008 MAC Receive Interface Signals 2015 06 15 Avalon ST Description Signal Type rx frm type 3 0 Frame type See Table 7 6 for the bit descrip tion ff rx a full O Asserted when the FIFO buffer reaches the almost full threshold ff_rx_a_empty O Asserted when the FIFO buffer goes below the almost empty threshold rx_er
34. 3201 3977 8 0 3620 10 100 supported 1000 Mbps 2048x32 3345 4425 12 1 3364 Ethernet MII GMII 2048x32 3125 3994 12 1 2084 MAC All MAC options enabled RGMII 2048x32 3133 4021 12 1 2084 All MAC options enabled 12 port 10 27215 34372 0 0 25008 100 1000 Mbps Ethernet MAC MII GMII 24 port 10 All MAC options enabled 54123 68404 0 0 50016 100 1000 Mbps Ethernet MAC 1000BASE X 624 661 0 0 0 1000BASE X 808 986 2 0 0 SGMII bridge enabled 1000BASE 1990BASE X B 819 1057 2 0 0 X SGMII sGMiI bridge enabled PCS PMA block LVDS IO 1000BASE X 1189 1212 1 0 160 SGMII bridge enabled PMA block GXB 10 100 All MAC options enabled 2048x32 3971 4950 14 1 2084 1000 Mbps SGMII bridge enabled Ethernet MAC and 1000BASE X SGMII PCS About This MegaCore Function LJ Send Feedback Altera Corporation UG 01008 1 10 2015 06 15 Performance and Resource Utilization Table 1 4 Cyclone IV GX Performance and Resource Utilization The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Cyclone IV device family The estimates are obtained by compiling the Triple Speed Ethernet MegaCore function using the Quartus II software targeting a Cyclone IV GX EP4CGX150DF27C7 device with speed grade 7 MegaCore Function FIFO Buffer Size Bits Logic Elements Logic Registers Memory M9K Blocks Mi44K Blocks MLAB Bits 1000 Mbps
35. 4 5 Receive FIFO Thresholds Network The remaining Frame Buffer n unwritten entries in the FIFO buffer Frame Buffer n 1 before it is full Almost full Section Empty T An early indication Frame Buffer k that the FIFO buffer is getting full Section full Almost empty Secon Sufficient unread The remaining entries in the FIFO unread entries in Frame Buffer 2 buffer for the user the FIFO buffer application to start before it is empty Frame Buffer 1 reading from it Switch Fabric Table 4 6 Receive Thresholds Almost empty rx_almost_empty The number of unread entries in the FIFO buffer before the buffer is empty When the level of the FIFO buffer reaches this threshold the MAC function asserts the xx a empty signal The MAC function stops reading from the FIFO buffer and subsequently stops transferring data to the user application to avoid buffer underflow When the MAC function detects an EOP it transfers all data to the user application even if the number of unread entries is below this threshold Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Receive Thresholds 4 15 Almost full rx almost full The number of unwritten entries in the FIFO buffer before the buffer is full When the level of the FIFO buffer reaches this threshold the MAC function asserts the rx full signal If the user application is not ready to receive data rx
36. 42 waitrequest PSU Signals TBI Interface Signals If the core variation does not include an embedded PMA the PCS block provides a 125 MHz ten bit interface TBI to an external SERDES chip Table 7 19 TBI Interface Signals for External SERDES Chip tbi tx d 9 0 O TBI transmit data The PCS function transmits data on this bus synchronous to tbi tx clk Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 Status LED Control Signals 7 19 tbi tx clk I 125 MHz TBI transmit clock from external SERDES typically sourced by the local reference clock oscillator tbi rx clk I 125 MHz TBI receive clock from external SERDES typically sourced by the line clock recovered from the encoded line stream tbi rx d 9 0 I TBI receive data This bus carries the data from the external SERDES Synchronize the bus with tbi rx cix The data can be arbitrary aligned Status LED Control Signals Table 7 20 Status LED Interface Signals led link O When asserted this signal indicates a successful link synchroni zation led panel link O When asserted this signal indicates the following behavior 1000 Base X without auto Similar to 1ed link negotiation SGMII mode without auto Similar to led_link negotiation 1000 Base X with auto negotia Similar to 1ea an tion SGMII mode with MAC mode Similar to 1ed_an and auto negotiation partner ability 15
37. 6 ms abpajwouypy uM D 9Anmoasuo e Send I Idle sequence is 3 Data For more information refer to CISCO Serial GMII Specifications Ten bit Interface In PCS variations with embedded PMA the PCS function implements a TBI to an external SERDES On transmit the SERDES must serialize tbi tx a 0 the least significant bit of the TBI output bus first and tbi tx d 9 the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly as figure below illustrates Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 PHY Loopback 4 37 Figure 4 19 SERDES Serialization Overview tbi tx d 9 0 serialization 1 25Gbps Serial Stream On receive the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last as figure below illustrates Figure 4 20 SERDES De Serialization Overview tbi rx d 9 0 de serialization 1 25Gbps Serial Stream PHY Loopback In PCS variations with embedded PMA targeting devices with GX transceivers you can enable loopback on the serial interface to test the PCS and embedded PMA functions in isolation of the PMD To enable loopback set the s 1oopback bit in the PCS control register to 1 The serial loopback option is not supported in Cyclone IV devices with GX transceiver Functional Description Altera Corporation LJ Send Feedback UG 01008 4 38 PHY Po
38. Avalon ST frame data e FIFO Insert Control the ingress control input bus that includes the signals required for decoding logics and signals to the MAC that is required to be aligned with SOP e FIFO Request Control contains decoded data such as control signals to inserter and timestamp field locations e Decoding Decodes packet types of incoming PTP packets and returns the decoded data to be stored in the FIFO request control block 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for product
39. Classifier decodes the packet type of incoming PTP packets and returns the decoded information to the Triple Speed Ethernet MAC e Ethernet ToD Clock provides 64 bits and or 96 bits time of day to TX and RX of Triple Speed Ethernet MAC e Pulse Per Second Module returns pulse per second pps to user e Avalon MM Master Translator provides access to the registers of the following components through the Avalon MM interface e Triple Speed Ethernet MAC e Transceiver Reconfiguration Controller e ToD Clock Base Addresses Table below lists the design example components that you can reconfigure to suit your verification objectives To reconfigure the components write to their registers using the base addresses listed in the table and the register offsets described in the components user guides Table 5 1 Base Addresses of Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Components Triple Speed Ethernet 0x0000 Time of Day Clock 0x1000 Transceiver Reconfiguration Controller 0x2000 Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Files Figure 5 2 Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Folders fm ip library ethernet altera eth tse design example o tse jeee1588 SER testbench Triple Speed Ethernet with IEEE 1588v2 Design Example Altera Corporation C Send Feedback UG 01008 5 4 Creating a New Triple Speed Ethern
40. Counters Dword Offset 0x18 0x38 2015 06 15 Dword Description Offset Ox1F aOctetsReceivedo RO The number of data and padding octets that are successfully K received The lower 32 bits of the aoctet sReceivedox counter The upper 32 bits of this statistics counter reside at the dword offset 0x3D 0x20 aTxPAUSEMACCtrlF RO The number of pause frames transmitted rames 0x21 aRxPAUSEMACCtrlF RO The number received pause frames received rames 0x22 ifInErrors RO The number of errored frames received 0x23 ifOutErrors RO The number of transmit frames with one the following errors e FIFO overflow error e FIFO underflow error e Errors defined by the user application 0x24 ifInUcastPkts RO The number of valid unicast frames received 0x25 ifInMulticastPkt RO The number of valid multicast frames received The count s does not include pause frames 0x26 ifInBroadcastPkt RO The number of valid broadcast frames received S 0x27 ifOutDiscards This statistics counter is not in use The MAC function does not discard frames that are written to the FIFO buffer by the user application 0x28 ifOutUcastPkts RO The number of valid unicast frames transmitted 0x29 ifOutMulticastPk RO The number of valid multicast frames transmitted excluding ts pause frames 0x2A ifOutBroadcastPk RO The number of valid broadcast frames transmitted ts Ox2B etherStatsDropEv RO The number of frames that are dropped due to MAC internal ents errors when FIFO buffer overf
41. Fause Frame Transmit Receive gt i To From Interfaces TISUBRCRU External PHY gt CRC Generation Pause Frame y Y gl Miet orgaga E A e conhada Porin Receiver Control Loopback CRCCheck Pause Frame Transmit Receive 4 teint To From Interfaces Y Transmitter Control External PHY CRC Generation Pause Frame Y yo i i d MDIO Mast Medi Conga Py mores A Avalon MM Interface In a multiport MAC the instances share the MDIO master and some configuration registers You can use the Avalon ST Multi Channel Shared Memory FIFO core in Qsys to store the transmit and receive data Related Information MAC Configuration Register Space on page 6 1 MAC Interfaces The MAC function implements the following interfaces Functional Description Altera Corporation LJ Send Feedback UG 01008 4 4 MAC Transmit Datapath 2015 06 15 e Avalon ST on the system side e Avalon ST sink port on transmit with the following properties e Fixed data width 8 bits in MAC variations without internal FIFO buffers configurable data width 8 or 32 bits in MAC variations with internal FIFO buffers e Packet support using start of packet SOP and end of packet EOP signals and partial final packet signals e Error reporting e Variable length ready latency specified by the tx aimost fu11 register e Avalon ST source port on receive with the following properties e F
42. LVDS IO serial LVDS IO transceiver serial input STANDARD input and output pins and output pins Altera Corporation Getting Started with Altera IP Cores C Send Feedback UG 01008 2015 06 15 Design Constraint File No Longer Generated Quartus II Pin Assignment Description Design Pin Assignment Value GLOBAL_ Global clock To assign clock signals to use the ref clk for MAC and PCS SIGNAL global clock network Use this setting with LVDS IO with internal to guide the Quartus II in the fitter FIFO process for better timing closure clkand reset pins for MAC only without internal FIFO clkand ref_clk input pins for MAC and PCS with transceiver without internal FIFO GLOBAL_ Regional To assign clock signals to use the See edi E E eS SIGNAL clock regional clock network Use this input pins for M AC only using setting to guide the Quartus II in the MII GMII interface without fitter process for better timing internal FIFO closure e rx clk n input pin for MAC only using RGMII interface without internal FIFO GLOBAL OFF To prevent a signal to be used asa Signals for Arria V devices SIGNAL global signal e reset ff wr and reset ff rd e altera tse reset synchronizer chain out Getting Started with Altera IP Cores CJ Send Feedback Altera Corporation 2015 06 15 UG 01008 GX subscribe send Feedback Parameter Settings Parameter Settings You customize the Triple Speed Ethernet M
43. The state machine decodes sequences other than I I Idle or I S Start of Frame as wrong carrier During frame reception the de encapsulation state machine checks for invalid characters When the state machine detects invalid characters it indicates an error to the MAC function Synchronization The link synchronization constantly monitors the decoded data stream and determines if the underlying receive channel is ready for operation The link synchronization state machine acquires link synchronization if the state machine receives three code groups with comma consecutively without error When link synchronization is acquired the link synchronization state machine counts the number of invalid characters received The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character The internal error counter is decremented when four consecutive valid characters are received When the counter reaches 4 the link synchronization is lost The PCS function drives the 1e 1ink signal to 1 when link synchronization is acquired This signal can be used as a common visual activity check using a board LED The PCS function drives the 1e panei link signal to 1 when link synchronization is acquired for the PCS operating in 1000 Base X without auto negotiation and SGMII mode without auto negotiation Carrier Sense The carrier sense state machine detects an activity when the l
44. ToD Clock Device Family Support Table C 1 Device Family Support Arria V GX GT GZ SoC Preliminary Cyclone V GX GT SoC Preliminary Stratix V GX GT Preliminary Other device families No support ToD Clock Performance and Resource Utilization Table C 2 provides the estimated resource utilization and performance of the ToD clock for the Stratix V device family The estimates are obtained by compiling the Triple Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX 55GXMA7N3F45C23 device with speed grade 3 O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest
45. X PCS with Embedded PMA Example application using the Triple Speed Ethernet MegaCore function with 1000BASE X and PMA The PMA block connects to an off the shelf GBIC or SFP module to communicate directly over the optical link Altera Device Triple Speed Ethernet MegaCore Function bp 1000BASE X GBIC SFP Ethernet MAC PCS Module Figure 1 8 10 100 1000 Mbps Ethernet MAC and SGMII PCS with Embedded PMA GMII MII to 1 25 Gbps Serial Bridge Mode Example application using the Triple Speed Ethernet MegaCore function with 1000BASE X and PMA in which the PCS function is configured to operate in SGMII mode and acts as a GMII to SGMII bridge In this case the transceiver I O connects to an off the shelf Ethernet PHY that supports SGMII 10BASE T 100BASE T or 1000BASE T Ethernet PHY Altera Device Triple Speed Ethernet MegaCore Function 10 100 um 1000 Mbps SGMII PCS bol no pp Ethernet MAC MegaCore Verification For each release Altera verifies the Triple Speed Ethernet MegaCore function through extensive simulation and internal hardware verification in various Altera device families The University of New Hampshire UNH InterOperability Lab also successfully verified the MegaCore function prior to its release Altera Corporation About This MegaCore Function C Send Feedback UG 01008 2015 06 15 Optical Platform 1 7 Altera used a highly parameterizeable transaction based testbench to test the following aspects of th
46. and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 16 OxOB rx almost empty RW RO Variable length almost empty threshold of the receive FIFO buffer Use the depth of your FIFO buffer to determine this threshold Due to internal pipeline latency you must set this threshold to a value greater than 3 This threshold is typically set to 8 In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 8 0x0C rx_almost_full RW RO Variable length almost full threshold of the receive FIFO buffer Use the depth of your FIFO buffer to determine this threshold Due to internal pipeline latency you must set this threshold to a value greater than 3 This threshold is typically set to 8 In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 8 0x0D tx_almost_ empty RW RO Variable length almost empty threshold of the transmit FIFO buffer Use the depth of your FIFO buffer to determine this threshold Due to internal pipeline latency you must set this threshold to a value greater than 3 This threshold is typically set to 8 In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 8 Configuration Register Space C Send Feedback Altera Corporation Base Configuration Regis
47. calculation is optional for the UDP IPv4 protocol The 1588v2 Tx logic should set the checksum to zero Altera Corporation Functional Description C Send Feedback UG 01008 m 2015 06 15 PTP Frame over UDP IPv6 45 Figure 4 28 PTP Frame over UDP IPv4 6 Octets Destination Address zu 6 Octets Source Address MAC Header 2 Octets Length Type 0x0800 1 H 1 Octet Version Internet Header Length 1 Octet Differentiated Services 2 Octets Total Length 2 Octets Identification 2 Octets Flags Fragment Offsets 1 Octet TimeTo Live IP Header 1 Octet Protocol 0x11 2 Octets Header Checksum 4 Octets Source IP Address 4 Octets Destination IP Address 0 Octet Options Padding 2 Octets Source Port 2 Octets Destination Port 319 320 UDP Header 2 Octets Length 2 Octets Checksum 1 Octet transportSpecific messageType Trj 1 Octet reserved versionPTP 2 Octets messageLength 1 Octet domainNumber 1 Octet reserved 2 Octets flagField PTP Header 8 Octets correctionField 4 Octets reserved 10 Octets SourcePortldentify 2 Octets sequenceld 1 Octet controlField 1 Octet logMessagelnterval 10 Octets TimeStamp 0 1500 9600 Octets o Payload LE 4 Octets CRC Note to Figure 4 28 1 For frames with VLAN or Stacked VLAN tag add 4 or 8 octets offsets before the length type field PTP Frame over UDP IPv6 Checksum cal
48. checksum_correct packet checksum by updating the checksum correction specified by ie GIES sins Citiell_ Owe offset_checksum_correction tx_etstamp_ins_ctrl_out Output The timestamp format of the frame timestamp_format where the timestamp is inserted Altera Corporation Packet Classifier C Send Feedback UG 01008 2015 06 15 Packet Classifier Timestamp Field Location Signals E 5 EE CENE IET NEN NN tx etstamp ins ctrl out Output Assert this signal to insert timestamp timestamp insert into the associated frame tx etstamp ins ctrl out Output 1 Assert this signal to add the residence time updat residence time into the correction field of the PTP frame Packet Classifier Timestamp Field Location Signals These signals must be aligned to the start of a packet Table E 6 Timestamp Field Location Signals for the Packet Classifier a 27 G2 NEN NN NN tx etstamp ins ct offset Output Indicates the location of the timestamp timestamp field tx etstamp ins ctrl out offset Output 16 Indicates the location of the correction field correction field tx etstamp ins ctrl out offset Output 16 Indicates the location of the checksum field checksum field tx etstamp ins ctrl out offset Output 16 Indicates the location of the checksum correction checksum corrector field Packet Classifier Altera Corporation LJ Send Feedback Additional Information 201
49. command config register to disable the RX datapath Parameter iface The index of the MAC interface This argument is reserved for configurations that contain multiple MAC instances Return SUCCESS if the close operations are successful An error code if de registration of SGDMA RX from the operating system failed See also triple speed ethernet init Altera Corporation Software Programming Interface C Send Feedback UG 01008 2015 06 15 tse mac raw send 11 9 tse mac raw send Prototype int tse mac raw send NET net char data unsigned data bytes Thread safe No Available from ISR No Include lt triple_speed_ethernet_iniche h gt Description The tse mac raw send function sends Ethernet frames data to the MAC function It validates the arguments to ensure the data length is greater than the ethernet header size specified by ALTERA TSE MIN MrU szizk The function also ensures the SGDMA TX engine is not busy prior to constructing the descriptor for the current transmit operation Upon successful validations this function calls the internal API tse mac sTxWrite to initiate the synchronous SGDMA transmit operation on the current data buffer Parameter net The NET structure of the Triple Speed Ethernet MAC instance data A data pointer to the base of the Ethernet frame data including the header to be transmitted to the MAC The data pointer is assu
50. data n 0 data tx sop n data tx eop n data tx error n data tx valid n data tx ready n tx ac fwdn tx ff uflow n data rx data n 0 data rx sop n data rx eop n data rx error n 4 0 data rx ready n data rx valid n pkt dass valid n pkt dass data n 4 0 rx afull channel CHANNEL WIDTH 1 0 rx afull data 1 0 rx afull valid rx afull clk Xon gen n xoff gen n magic sleep n n magic wakeup n clk reg addr log2 MAX_CHANNELS 7 0 7 0 reg wr reg rd reg data in 31 0 reg data out 31 0 reg busy reset 4 tbi rx dk n tbi rx d n 9 0 qe tbi tx dk n 10 tbi tx d n 9 0 led an n led cs n led col n led char err n e led link n amp led panel link n led disp ert n mdioin 4 md mdio oen mdio out sd loopback n PEE powerdown n pcs eccstatus 1 0 e UG 01008 2015 06 15 Reset Signal Ten Bit Interface Signals Status LED Signals HY Management Signals SERDES Control Signals ECC Status Signd Clock and reset signals Clock and Reset Signal on page 7 2 MAC control interface MAC Control Interface Signals on page 7 3 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS Signals 7 23 MAC transmit interface MAC Trans
51. dee OR ERE EE ARR SERE RR eoseadectnag eeeanasser eases 4 40 IEBE 15882 Supported Configurations aue ea ceperat rtt Ure deb peer or eie eb RdS 4 40 TEBE nHAATunCc M R S 4 41 IEEE 138392 ZXCIWIGUUREE ere reves Deren vtm o remind ict t a 4 42 IEEE J58892 Tr smit ata pati cusccadudbqpase np teo ERA ta AVR ER xc eden A RR 4 42 IEEE 1588v2 Receive Datapath eee tete ne EE NAR RHET AR testes e Seen 4 43 IEEE E588v2 Frame Format nette erret nre eb ree depo roi taceo 4 43 Triple Speed Ethernet with IEEE 1588v2 Design Example 5 1 Software Bequitefnottte cse oO MERERI HER DNE REN QNUM it RN OHNE 5 Triple Speed Ethernet with IEEE 1588v2 Design Example Componennts sss 5 2 or niu c e c 5 3 Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Files 5 3 Creating a New Triple Speed Ethernet MAC with IEEE 1588v2 Design sse 5 4 Triple Speed Ethernet with IEEE 1588v2 Testbenchi auae idees ertt nore b ober Pu Pine ginda 5 4 Triple Speed Ethernet with IEEE 1588y2 Testbench Files ernannt abrite tnra 5 5 Triple Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow 5 6 Simulating Triple Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Nilo RM 5 7 Configuration Register Space ee
52. derart p PRI A RUE HAURIRE UR PEE LE 10 1 STE Sle UC CS nT 0 ceca preste acess ssa uie cee a RR ERO eens S s a alta NU pd E S 10 2 Testbench Verification cccccccsscccsssssscscsssssscscsssssscscsssssscsesssscsesesssscscssscsescsessceesescsececsesesececsesesececseseseceenees 10 2 je oae 10 3 Test EloWdaucad ntis niae iere tee eiie ete tie die EO ERR 10 3 Simulation Model ao oen eee on eteeteredaten nim eti rie coire eei codvechas sasidvasaiuevizs pvc in 10 4 Generate the Simulation Modlel sees eene tht ntn tnat nenas th then 10 4 Simulate the TP COE iiti consect retro a ru Ue HL FCR Eon e NE 10 4 Simulation Model Files cccccsescssssessssesscscssescssesecsesecsessesessesecsesecsessesecsesecsessesessesecsesessessesees 10 5 Software Programming Interface orto t EIER ERE PER PEE ELS R P ei EPIS SURE QUUS 11 1 Driver Architectures TREE ne a 11 1 DIFECLORY dian E M M 11 2 IER RETE 11 2 Using Multiple SG DMA Desi pin gs uadit aadtinte iai ane cas ineo ta diarias RO 11 4 Using Jumbo PEIDesoauceio inen atocnarerb ende PAR oases Cd iari erai raa a EE e pra dol da eq 11 4 API bunctiols s aereo aceite eatem dere wakes daisies Boe atn ne rite ber ED IE cd 11 5 alt tse mac get common SPEEUU eco imet aetate irit esei Losivigviuiri aiv up Rete put 11 5 alt tse mac set common speed i e erret tee n Et pe ox Eee ere Ren
53. described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 D 2 ToD Synchronizer Block UG 01008 2015 06 15 ToD Synchronizer Block Figure D 1 Connection between ToD Synchronizer Master ToD Slave ToD and Sampling Clock PLL ToD Synchronizer Master ToD Slave ToD Tbi P start tod sync ynchronization valid m tod_slave_valid time of day 96b load valid time of day 96b Master ToD tod master data Synchronization ToD tod slave data time of day 96b load data Master clock P reset master reset slave 4 3 period rst n p gt dk master ck slave period clk Master reset M period rst n P period clk Slave reset Slave dock p PLL Sampling clock clk_sampling
54. dio oen MDIO Interface 10 100 1000 Ethernet MAC MDIO Frame Generation and Decoding Avalon MM Control Interface The MDIO master communicates with the slave PHY device using MDIO frames A complete frame is 64 bits long and consists of 32 bit preamble 14 bit command 2 bit bus direction change and 16 bit data Each bit is transferred on the rising edge of the MDIO clock mac Functional Description LJ Send Feedback Altera Corporation UG 01008 4 24 Connecting MAC to External PHYs 2015 06 15 Table 4 9 MDIO Frame Formats Read Write Field settings for MDIO transactions Addr1 Addr2 Data MSB MSB LSB MSB LSB MSB LSB Read 1 vox Z0 noooononoooor Write ee 01 01 XXXXX XXXXX 10 XXXXXXXXXXXXXXXX Z Table 4 10 MDIO Frame Field Descriptions PRE Preamble 32 bits of logical 1 sent prior to every transaction ST Start indication Standard MDIO Clause 22 0b01 OP Opcode Defines the transaction type Addr1 The PHY device address PHYAD Up to 32 devices can be addressed For PHY device 0 the Addr1 field is set to the value configured in the mdio_addr0 register For PHY device 1 the Addr1 field is set to the value configured in the mdio addr1 register Addr2 Register Address Each PHY can have up to 32 registers TA Turnaround time Two bit times are reserved for read operations to switch the data bus from write to read for r
55. discards frames with CRC 32 error if the Rx ERR Drsc bit in the command config register is set to 1 Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Length Checking 4 11 The MAC function forwards the CRC 32 field to the user application if the cRc Fwp and Pap Eu bits in the command config register are 1 and 0 respectively Otherwise the CRC 32 field is removed from the frame Length Checking The MAC function checks the frame and payload lengths of basic VLAN tagged and stacked VLAN tagged frames The frame length must be at least 64 0x40 bytes and not exceed the following maximum value for the different frame types e Basic frames the value specified in the frm_length register e VLAN tagged frames the value specified in the frm_length register plus four e Stacked VLAN tagged frames the value specified in the frm_length register plus eight To prevent FIFO buffer overflow the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length For frames of a valid length the MAC function continues to check the payload length if the NO_LGTH_CHECK bit in the command_config register is set to 0 The MAC function keeps track of the payload length as it receives a frame and checks the length against the length type field in basic MAC frames or the client length type field in VLAN tagged frames The payload length is valid if it satisfies the followin
56. dk rxd 7 0 IX dv IX err Altera FPGA AAAA Programmable 10 100 Ethernet Connect 10 100 Ethernet PHYs to the MAC function via MII On the receive path connect the 25 MHz 100 Mbps or 2 5 MHz 10 Mbps clock provided by the PHY device to the MAC clock x cix On the transmit path connect the 25 MHz 100 Mbps or a 2 5 MHz 10 Mbps clock provided by the PHY to the MAC clock tx cik Functional Description LJ Send Feedback tx ck gm tx d 7 0 qm tx en qm tx err m tx d3 0 mixen mtx err ena TO eth mode set 1000 set 10 m rx d 3 0 mrx en m rx err 10 100 1000 Ethernet MAC Ik gx d gmrx dv gm err Altera Corporation 4 26 Programmable 10 100 1000 Ethernet Operation Figure 4 11 10 100 PHY Interface UG 01008 2015 06 15 Reference Clock 25Mhz Altera FPGA clk_inktali tx ck tx clk txd 3 0 ke m tx d 3 0 txen m tx en tx err bq m tx err gm tx d 7 0 3 gm tx en S gmtxerr 5 a ena 10 oprana neto D lt eth mode 10 100 1000 10100 2 2 set 10 Ethernet PHY set 1000 gm rx d 0 MAC gm rx dv gm rx err rx dk D dk rxd 3 0 m_rx_d 3 0 rx dv gt mrxen IX eir m x err m rx col m rx col m Ix crs mix s Programmable 10 100 1000 Ethernet Operation Typically 10 100 1000 Ethernet PHY devices impl
57. e Bits 15 0 16 bit maximum frame length in bytes The MegaCore function checks the length of receive frames against this value Typical value is 1518 In 10 100 and 1000 Small MAC core variations this register is RO and the maximum frame length is fixed to 1518 e Bits 31 16 unused 1518 Configuration Register Space C Send Feedback Altera Corporation 6 4 Base Configuration Registers Dword Offset 0x00 0x17 Dword Offset 0x06 pause_quant empty full rx_section_ rx_section_ Description e Bits 15 0 16 bit pause quanta Use this register to specify the pause quanta to be sent to remote devices when the local device is congested The MegaCore function sets the pause quanta P1 P2 field in pause frames to the value of this register 10 100 and 1000 Small MAC core variations do not support flow control e Bits 31 16 unused to FIFO Depth 16 Set this threshold to a value that is below the rx_ almost full threshold and above the xx section full or rx almost empty threshold In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of FIFO Depth 16 determine this threshold For cut through mode this threshold is typically set to 16 Set this threshold to a value that is above the rx_ almost empty threshold For store and forward mode set this threshold to 0 In 10 100 and 1000 Small MAC core variat
58. e to filter unicast frames when the promiscuous mode is disabled refer to Command Config Register Dword Offset 0x02 on page 6 7 for the description of the PROMIS_EN bit e to replace the source address in transmit frames received from the user application when address insertion is enabled refer to Command Config Register Dword Offset 0x02 on page 6 7 for the description of the Tx_ADDR_INS and TX ADDR SEL bits If you do not require the use of supplementary addresses configure them to the primary address Configuration Register Space Altera Corporation LJ Send Feedback 6 16 IEEE 1588v2 Feature Dword Offset OxDO OxD6 IEEE 1588v2 Feature Dword Offset OxDO OxD6 Table 6 7 IEEE 1588v2 MAC Registers UG 01008 2015 06 15 Dword Description Offset OxDO tx period Clock period for timestamp adjustment on the transmit datapath The period register is multiplied by the number of stages separating actual timestamp and the GMII bus e Bits 0 to 15 Period in fractional nanoseconds Tx PERIOD FNS e Bits 16 to 24 Period in nanoseconds Tx PERIOD NS e Bits 25 to 31 Not used The default value for the period is 0 For 125 MHz clock set this register to 8 ns OxDI1 ioc eeur deine RW Static timing adjustment in fractional nanoseconds for outbound timestamps on the transmit datapath e Bits 0 to 15 Timing adjustment in fractional nanosec onds e Bits 16
59. gt RX Descriptor E RXFIFO Q gre MII GMII Ra Seti zm RXSGDMA Notes to Figure 11 1 1 The first n bytes are reserved for SGDMA descriptors where n Total number of descriptors 3 x 32 Applications must not use this memory region 2 For MAC variations without internal FIFO buffers the transmit and receive FIFOs are external to the MAC function 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services
60. in the current version March 2007 7 0 Updated signal names and description Additional Information LJ Send Feedback Altera Corporation F 8 How to Contact Altera UG 01008 2015 06 15 ELENCO NN December 6 1 2006 e Global terminology changes 1000BASE X PCS SGMII to 1000BASE X SGMII PCS host side or client side to internal system side HD to half duplex e Initial release of document on Web December 6 1 2006 Initial release of document on DVD How to Contact Altera Table F 1 Altera Contact Information Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature General Email nacomp altera com Nontechnical support Software Email apgcs altera com licensing Related Information e www altera com support e www altera com training e www altera com literature 9 You can also contact your local Altera sales office or sales representative Altera Corporation Additional Information C Send Feedback
61. maintains a typical minimum IPG value of 12 bytes between packets although a read back to the register reflects the invalid value written In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 12 Bits 31 5 unused Set to read only value 0 Note to Table 6 2 1 Register is not available in 10 100 and 1000 Small MAC variations Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Command Config Register Dword Offset 0x02 6 7 Command Config Register Dword Offset 0x02 Figure 6 1 Command Config Register Fields 31 30 27 26 25 24 23 22 21 20 19 18 16 15 14 13 1211 10 9 8 7 6 5 43 2 1 0 E lt Lu 2 A Nia LLI lt x Lu 4 a zo wuj duo e em sas 2 a Se nla S e lt ele H o Z ala e a MET MALS Iz ux uo ou bu 1 mw Lu cc 1 ye cu Fo ic ealw Ii cc m c mj lalol S T Iuda ut al R a uu a A Sz zia 2 olz le ujo R2 e2 lt olz gt lt gt lt gt Lu 2 22 o x Slza Zjv E Aale ae Q S m 2E a lt FEA Ra TES ce rw a m At the minimum you must configure the Tx ENA and Rx_ENa bits to 1 to start the MAC operations When configuring the command_config register Altera recommends that you configure the Tx_ENA and Rx ENA bits the last because the MAC function immediately starts its o
62. map params pkg sv A SystemVerilog HDL package that maps addresses to the Avalon MM control registers ptp timestamp sv A SystemVerilog HDL class that defines the timestamp in the testbench tb testcase sv A System Verilog HDL testbench file that controls the flow of the testbench tb top sv The top level testbench file This file includes the customized Triple Speed Ethernet MAC which is the device under test DUT a client packet generator and a client packet monitor along with other logic blocks wave do A signal tracing macro script for use with the ModelSim simulation software to display testbench signals Triple Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow Upon a simulated power on reset each testbench performs the following operations 1 Ww Altera Corporation Initializes the DUT by configuring the following options through the Avalon MM interface e Configures the MAC In the MAC sets the transmit primary MAC address to EE CC 88 CC AA EE sets the speed to 1000 Mbps enables TX and RX MAC enables pad removal at receive sets IPG to 12 and sets maximum packet size to 1518 e Configures PCS and SGMII interface to 1000BASE X e Configures Timestamp Unit in the MAC by setting periods and path delay adjustments of the clocks e Configures ToD clock by loading a predefined time value e Configures clock mode of Packet Classifier to Ordinary Clock mode Starts packet tr
63. modes supported 8 port 10 100 MII GMII 20201 22292 32 0 14624 1000 Mbps All MAC options enabled Eien eS Full and half duplex modes supported 1000BASE X 624 661 0 0 0 1000BASE X 1000BASE X 1191 1214 1 0 160 SGMII PCS SGMII bridge enabled PMA block GXB Table 1 3 Stratix IV Performance and Resource Utilization The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Stratix IV device family The estimates are obtained by compiling the Triple Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix IV GX EP4SGX530NF45C4 device with speed grade 4 MegaCore FIFO Buffer Combina Logic Memory Function Size Bits seed Registers M9K Blocks M144K Blocks MLAB Bits MII 2048x32 1410 2127 12 1 1408 10 100 Full and half duplex modes Mbps Small supported MAC MII 2048x32 1157 1894 12 1 128 All MAC options enabled GMII 2048x32 1160 1827 12 1 176 1000 Mbps All MAC options enabled Small MAC RGMII 2048x32 1170 1861 12 1 176 All MAC options enabled Altera Corporation About This MegaCore Function C Send Feedback UG 01008 2015 06 15 Performance and Resource Utilization 1 9 MegaCore FIFO Buffer Combina Logic Memory Function Size Bits a Registers M9K Blocks 2 M144K Blocks MLAB Bits MII GMII 2721 3395 0 0 3364 Full and half duplex modes 2048x8
64. notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 10 2 Testbench Components UG 01008 2015 06 15 Testbench Components The testbench comprises the following modules Device under test DUT Your custom MegaCore function variation Avalon ST Ethernet frame generator Simulates a user application connected to the MAC system side interface It generates frames on the Avalon ST transmit interface Avalon ST Ethernet frame monitor Simulates a user application receiving frames from the MAC system side interface It monitors the Avalon ST receive interface and decodes all data received MII RGMII GMII Ethernet frame generator Simulates a MAC function that sends frames to the PCS function MII RGMII GMII Ethernet frame monitor Simulates a MAC function that receives frames from the PCS function and decodes them MDIO slaves Simulates a PHY management interface It responds to an MDIO master transactor Clock and reset generator Table 10 1 Testbench Components Configuration System Side Ethernet Side Frame Generator Frame Monitor Interface Interface
65. on the Avalon ST transmit interface Related Information Ethernet Frame Format on page 12 1 IP Payload Re alignment If you turn the Align packet headers to 32 bit boundaries option the MAC function removes the additional two bytes from the beginning of Ethernet frames Related Information IP Payload Alignment on page 4 11 Address Insertion By default the MAC function retains the source address received from the user application You can configure the MAC function to replace the source address with the primary MAC address or any of the supplementary addresses by setting the TX AppR ius bit in the command config register to 1 The TX ADDR SEL bits in the command con ig register determines the address selection Related Information Command Config Register Dword Offset 0x02 on page 6 7 Frame Payload Padding The MAC function inserts padding bytes 0x00 when the payload length does not meet the minimum length required e 46 bytes for basic frames e 42 bytes for VLAN tagged frames e 38 bytes for stacked VLAN tagged frames CRC 32 Generation To turn on CRC 32 generation you must set the o 1T cnc bit in the tx cma stat register to 0 and send the frame to the MAC function with the tx crc fwd signal deasserted The following equation shows the CRC polynomial as specified in the IEEE 802 3 standard FCS X X 9 X 26 X 23 4X 2 X 16 X Pax H X 4K 84K 74K594K 44K 24K 141 The 32 bit CRC value occupies the FCS fi
66. or Simulation Model sss 2 2 Sim late the ril RR 2 2 Compiling the Triple Speed Ethernet MegaCore Function Design ss 2 2 Programming n FPGA D vICe ice Ine o OH IER OR EGER ERI UNE E ke gate 2 3 Generat d Piles T I 2 3 Design Constraint Pile No Longer Genetated u eee tucot eritis ribera orae 2 4 Parameter SCC GS e 3 1 hone Iac M 3 1 Cote Cans a Of aer coe basa mti d pin ci d rre pd HR pe a Fun pinea M E UR es dag pd ES HR Ea EES ed 3 1 Ethernet MAC ODtIOnS no re Re e RR RT ERE BAI ERE I ERNIE RENE IHRER de 3 2 BEIEO OptiOnS ioni t mie iei hee ee i eite dubia en detdlasels ee coe cai 3 4 Timestamp OPUOMS ss cssssccesssivs taas 3 5 PGS Transceiver OPUOnse sass etii re o e Pe tree ete tecta ENT e di MAR e Yet Ede eI REOR i ARN 3 5 Functional DescrIpHOB niens vede icono dvluE Fa udin da eer Ipsi WEE DARE RR 4 1 10 100 1000 Ethernet MA QC aet tetro te eere bete pae aM REESE nde 4 1 MAC vnius o M 4 2 MAC TINT C SS T 4 3 MAC Transmit Datapath eR RR a R R E 4 4 MAC Receive Datapathi reete ttem ee eot ies tir dale d i eese um dessins diea 4 7 MAC Transmit and Receive LIIeHclesu oce pend pap ia FAX en Mie MO
67. pcs pwrdwn out gxb pwrdn in reconfig clk and reconfig_busy are not present in variations targeting Stratix V devices with GX transceivers Interface Signals LJ Send Feedback Reset Signals 1000BASE X SGMII PCS and PMA Signals 7 41 1 25 Gbps Serial Signals Status LED Signals SERDES Control Signals PCS Control Interface Signals Altera Corporation 7 42 Timing Table 7 43 References UG 01008 2015 06 15 Reset signals PCS Reset Signals on page 7 37 MII GMII clocks and clock enablers MII GMII Clocks and Clock Enablers on page 7 37 PCS control interface PCS Control Interface Signals on page 7 37 GMII signals GMII on page 7 38 MII signals MII on page 7 38 SGMII status signals SGMII Status Signals on page 7 39 1 25 Gbps Serial Signals 1 25 Gbps Serial Interface on page 7 25 Status LED signals Status LED Control Signals on page 7 19 SERDES control signals SERDES Control Signals on page 7 20 Transceiver Native PHY signal Transceiver Native PHY Signal on page 7 25 Timing This section shows the timing on the Triple Speed Ethernet transmit and receive interfaces as well as the timestamp signals for the IEEE 1588v2 feature Related Information Avalon Interface Specifications More information on Avalon MM control interface timing Avalon ST Receive Interface Figure 7 10 Receive Operation MAC With Internal FIFO Buffers ff rx dk
68. reference clock rx_cdr_refclk Related Information Arria 10 Transceiver PHY User Guide More information about Gigabit Ethernet GbE and GbE with 1588 the connection guidelines for a PHY design and how to implement GbE GbE with 1588 in Arria 10 Transceivers ECC Status Signals Table 7 23 ECC Status Signals pcs eccstatus 1 0 O Indicates the ECC status This signal is synchronized to the reg_ clk clock domain 11 An uncorrectable error occurred and the error data appears at the output 10 A correctable error occurred and the error has been corrected at the output However the memory array has not been updated 01 Not valid 00 No error For more information on the signals refer to the respective sections shown in Table 7 18 Interface Signals Altera Corporation C Send Feedback 7 22 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS Signals 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS Signals Figure 7 4 10 100 1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with 1000BASE X SGMII PCS Signals Clock Signals MAC Transmit Interface Signals MAC Receive Interface Signals MAC Packet Classification Signals MAC FIFO Status Signals Pause and Magic Packet Signals MAC Control Interface Signals MM LHITLL HEAT TH TH LILLIE LL Table 7 24 References Multi Port MAC with 1000BASE X SGMII PCS mac tx ck n mac rx ck n data tx
69. specific eur 3 2 mony Cite up tse mac Inach p Pointer to the function that reads and returns 32 bit link status Possible status cull cduples oit ONT EST S oie 0 ODEPT TEIG EO EIER oirt 1 1 Software Programming Interface Altera Corporation CJ Send Feedback 11 4 UG 01008 Using Multiple SG DMA Descriptors 2015 06 15 100Mbps bit 2 1 10Mbps bit 3 1 invalid speed bit 16 1 alt_u32 link_status_read np_tse_mac pmac alr tee phy TeuseEaLlle Example of PHY Instance Structure typedef struct alt tse system phy struct PHY instance PHY s MDIO address alt 32tse phy mdio address fo PEY initialization function pointer instance specific alt 32 tse phy cfg np tse mac pmac alt tse system phy Using Multiple SG DMA Descriptors To successfully use multiple SG DMA descriptors in your application make the following modifications e Set the value of the constant ALTERA TSE SGDMA RX DESC CHAIN SIZE in altera avalon tse h to the number of descriptors optimal for your application The default value is 1 and the maximum value is determined by the constant NuUMB1GBUFFS For TCP applications Altera recommends that you use the default value e Increase the amount of memory allocated for the Interniche stack The memory space for the Interniche stack is allocated using the Interniche function pk alloc Although user applicat
70. speed bits are set according to the convention shown in Table 11 1 Altera Corporation Software Programming Interface GJ Send Feedback UG 01008 2015 06 15 PHY Definition 11 3 Table 11 1 PHY Speed Bit Values PHY Speed Bits Speed Mbps 1000 1 0 100 0 1 10 0 0 For PHYs that do not conform to the aforementioned specifications you can write a function to retrieve the PHY s operating mode and speed and set the field 1ink status readin the PHY data structure to your function s address You can also execute a function to initialize a PHY profile or a PHY instance by setting the function pointer phy_cfg and tse phy cfc in the respective structures to the function s address Example of PHY Profile Structure typedef struct alt_tse phy profile eU PHY profile 7 The name of the PHY char name 80 Organizationally Unique Identififier alrt u92 oui PHY model number alt u8 model number PHY revision number alt u8 revision number The location of the PHY Specific Status Register alt u8 status reg location The location of the Speed Status bit in the PHY Specific Status Register alt u8 speed lsb location The location of the Duplex Status bit in the PHY Status Specific Register alrt ue chiolex bit locacion The location of the Link Status bit in PHY Status Specific Register eli ug limk oboir location PHY initialization function pointer profile
71. standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01008 2 2 Generating a Design Example or Simulation Model 2015 06 15 5 In the New Project Wizard Family amp Device Settings page select the device family and specific device you want to target for compilation Click Next 6 In the EDA Tool Settings page select the EDA tools you want to use with the Quartus II software to develop your project 7 Thelast page in the New Project Wizard window shows the summary of your chosen settings Click Finish to complete the Quartus II project creation Generating a Design Example or Simulation Model After you have parameterized the MegaCore function you can also generate a design example in addition to generating the MegaCore component files In the parameter editor click Example Design to create a functional simulation model design example that includes a testbench The testbench and the automated script are located in the
72. the frame All multicast frames are accepted if all entries in the hash table are one Frame Type Validation The MAC function checks the length type field to determine the frame type Functional Description Altera Corporation LJ Send Feedback UG 01008 4 10 Payload Pad Removal 2015 06 15 e Length type lt 0x600 the field represents the payload length of a basic Ethernet frame The MAC function continues to check the frame and payload lengths e Length type gt 0x600 the field represents the frame type e Length type 0x8100 VLAN or stacked VLAN tagged frames The MAC function continues to check the frame and payload lengths and asserts the following signals e for VLAN frames rx err stat 16 in MAC variations with internal FIFO buffers or pkt class data 1 in MAC variations without internal FIFO buffers e for stacked VLAN frames rx err stat 17 in MAC variations with internal FIFO buffers or pkt class data 0 in MAC variations without internal FIFO buffers e Length type 0x8088 control frames The next two bytes the Opcode field indicate the type of control frame e For pause frames Opcode 0x0001 the MAC function continues to check the frame and payload lengths For valid pause frames the MAC function proceeds with pause frame processing The MAC function forwards pause frames to the user application only when the PAUSE FWD bit in the command config register is set to 1 e For other types of control f
73. tion about these registers see Transmit and Receive Command x cA UCM E Registers Dword Offset 0x3A 0x3B on page 6 13 Ox3C _ Extended Statistics Upper 32 bits of selected statistics counters These registers are used if Ox3E Counters you turn on the option to use extended statistics counters For more information about these counters refer to Statistics Counters Dword Offset 0x18 0x38 on page 6 11 Ox3F Reserved Unused 0x40 Multicast Hash Table 64 entry write only hash table to resolve multicast addresses Only bit Ox7F 0 in each entry is significant When you write a 1 to a dword offset in the hash table the MAC accepts all multicast MAC addresses that hash to the value of the address bits 5 0 Otherwise the MAC rejects the multicast address This table is cleared during reset Hashing is not supported in 10 100 and 1000 Mbps Small MAC core variations 0x80 MDIO Space 0 MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the Ox9F PCS Functi PHY devices whose addresses are configured in the mdio_addr0 and a amp es n mdio addr1 registers respectively For example register 0 of PHY SB TOME device 0 maps to dword offset 0x80 register 1 maps to dword offset OxA0 MDIO Space 1 0x81 and so forth OxBF Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register Only bits 15 0 of each register are significant Write 0 to bits 31 16
74. version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE AN UG 01008 C 2 ToD Clock Parameter Setting 2015 06 15 Table C 2 Stratix V Performance and Resource Utilization MegaCore Function FIFO Buffer Combina Logic Memory Size Bits tional ALUTs Registers M20K Blocks MLAB Bits TOD Clock Default 0 378 1 120 0 0 ToD Clock Parameter Setting The ToD Clock is part of the reference design components in the Quartus II software You can enable this module from the IP Catalog and in Qsys Interface Protocols gt Ethernet gt Reference Design Components Table C 3 ToD Clock Configuration Parameters e KNEES 7 ON NN DEFAULT NSEC Between 0 and 0x000F 4 bit value that defines the reset value for PERIOD PERIOD ns For Triple Speed Ethernet MegaCore function set the value to 0x0008 The default value is 0x0006 DEFAULT FNSEC Between 0 and OxFFFF 16 bit value that defines the reset value for PERIOD PERIOD ENS For Triple Speed Ethernet MegaCore function set the value to 0x0000 The default value is 0x6666 DEFAULT NSEC Between 0 and 0x000F 4 bit value that defines the reset value for ADJPERIOD ADJPERIOD NS The default value is 0x0006 DEFAULT FNSEC Between 0 and OxFFFF 16 bit value that defines the reset value for PERIOD ADJPERIOD FNS The default value is 0x6666
75. 0 reg data out 31 0 reg busy PRED TUL TREE TE EE TL LLL ed 10 100 1000 Ethernet MAC reset Ix dk tx dk rx_clkena tx_clkena gm n dU 0 gm rx dv gm rx err gm tx d 7 0 gm tx en gm tx err rgmii_in 3 0 rx control rgmii_out 3 0 tx_control m_rx_d 3 0 m rx en m Ix err m rx col m Ix qs m tx d 3 0 m tx en m tx err mdio in mdc mdio oen mdio out mac eccstatus 1 0 set 10 n set 1000 n ena 10 n eth mode n i Reset Signal Clock Signals GMII Signals RGMII Signals MII Signals PHY UG 01008 2015 06 15 Management Signals ECC Status Signal MAC Status Signals Data transfers on the MAC Ethernet side interface are synchronous to the receive and transmit clocks Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 MAC Control Interface Signals 7 3 Table 7 1 GMII RGMII MII Clock Signal tx clk I GMII RGMII MII transmit clock Provides the timing reference for all GMII MII transmit signals The values of gm tx d 7 0 In Qsys pcs_ mac_tx_clock_ connection gm_tx_en gm_tx_err and of m_tx_d 3 0 m tx en m tx err are valid on the rising edge of cx cix Ix x In Qsys DES GMII RGMII MII receive clock Provides the timing reference for all rx related signals The values of gm_rx_d 7 0 gm xx v gm rx err and of um sex qs sese sexe Gua du sexe quere are valid lock gu
76. 0x00 R W Description e Bits 15 0 Set to the current version of the MegaCore function e Bits 31 16 Customer specific revision specified by the cusr VERSION parameter defined in the top level file generated for the instance of the MegaCore function These bits are set to 0 during the configura tion of the MegaCore function lt IP version number gt 0x01 scratch l RW Scratch register Provides a memory location for you to test the device memory operation 0x02 0x03 0x04 0x05 command_config RW mac 0 mac 1 frm length MAC configuration register Use this register to control and configure the MAC function The MAC function starts operation as soon as the transmit and receive enable bits in this register are turned on Altera therefore recommends that you configure this register last See Command Config Register Dword Offset 0x02 on page 6 7 for the bit description 6 byte MAC primary address The first four most significant bytes of the MAC address occupy mac 0 in reverse order The last two bytes of the MAC address occupy the two least significant bytes of mac 1 in reverse order For example if the MAC address is 00 1C 23 17 4A CB the following assignments are made mac 0 0x17231c00 mac 1 0x0000CB4a Ensure that you configure these registers with a valid MAC address if you disable the promiscuous mode PROMIS EN bit in command config 0
77. 1 2008 Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA UG 01008 B 2 Functionality Configuration Parameters 2015 06 15 ee TB_MDIO_ADDRO Sets the mdio_addr0 register See Base Configuration Registers 0 Dword Offset 0x00 0x17 on page 6 3 TB_MDIO_ADDR1 Sets the mdio_addr1 register See Base Configuration Registers 1 Dword Offset 0x00 0x17 on page 6 3 X FIFO AE Sets the tx almost empty register See Base Configuration Registers 8 Dword Offset 0x00 0x17 on page 6 3 TX FIFO AF Sets the tx almost u11 register See Base Configuration Registers 10 Dword Offset 0x00 0x17 on page 6 3 RX FIFO AE Sets the xx almost empty register See Base Configuration Registers 8 Dword Offset 0x00 0x17 on page 6 3 RX FIFO AF Sets the xx almost fu11 register See Base Configuration Registers 8 Dword Offset 0x00 0x17 on page 6 3 TX FIFO Sets the tx section empty register See Base Configuration 16 SECTION EMPTY Registers Dword Offset 0x00 0x17 on page 6 3 TX_FIFO_ Sets the tx section full register See Base Configuration R
78. 10 Stratix V Arria V and Cyclone V devices with GX transceivers Interface Signals Altera Corporation LJ Send Feedback 7 26 SERDES Control Signals UG 01008 2015 06 15 peter Joule ellie Calibration block clock for the ALT2GXB module SERDES This clock is typically tied to the 125 MHz re cix Only implemented when an internal SERDES is used This signal is not present in PMA blocks implemented in Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers reconfig_clk Reference clock for the dynamic reconfiguration controller If you use a dynamic reconfiguration controller in your design to dynamically control the transceiver both the reconfiguration controller and the MegaCore function require this clock This clock must operate between 37 5 50 MHz Tie this clock low if you are not using an external reconfiguration controller This signal is not present in PMA blocks implemented in Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers reconfig togxb n 0 Driven from an external dynamic reconfiguration controller Supports the selection of multiple transceiver channels for dynamic reconfiguration For PMA blocks implemented in Stratix V devices with GX transceivers the bus width is 139 0 For more information about the bus width for PMA blocks implemented in each device refer to the Dynamic Reconfiguration chapter of the respective device handbook reconfi
79. 10 100 Mbps connections support Enable local On Off Turn on this option to enable local loopback on the loopback on MII MAC s MIL GMII or RGMII interface If you turn on GMII RGMII this option the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register Enable On Off Turn on this option to include support for supplemen supplemental tary destination MAC unicast addresses for fast MAC unicast hardware based received frame filtering addresses Include statistics On Off Turn on this option to include support for simple counters network monitoring protocol SNMP management information base MIB and remote monitoring RMON statistics counter registers for incoming and outgoing Ethernet packets By default the width of all statistics counters are 32 bits Enable 64 bit On Off Turn on this option to extend the width of selected statistics byte statistics counters aoctetsTransmittedOK counters aOctetsReceivedOk and etherStatsOctets to 64 bits Include multicast On Off Turn on this option to implement a hash table a fast hashtable hardware based mechanism to detect and filter multicast destination MAC address in received Ethernet packets Align packet On Off Turn on this option to include logic that aligns all headers to 32 bit packet headers to a 32 bit boundary This helps reduce boundary software overhead processing in realignment of data buffers
80. 1000 Mbps Ethernet MAC Avalon ST Transmit and Receive Avalon MM Management and Control Figure 1 2 Multi port MAC Avalon MM Management and Control Avalon ST Transmit and Receive Avalon ST Transmit and Receive 10 100 1000 Mbps Er Ethernet MAC Network Side Client Side Multi Port MAC 10 100 1000 Mbps Ethernet MAC Client Side 10 100 1000 Mbps Ethernet MAC Network Side lt gt MII GMII RGMII MII GMII RGMII MII GMII RGMII Figure 1 3 10 100 1000 Ethernet MAC and 1000BASE X SGMII PCS with Optional PMA Avalon MM MAC and PCS with Optional Embedded PMA Management and Control Avalon ST Client Side 10 100 1000 Mbps Mi Ethernet MAC MII TBI 1000BASE X SGMII e y PCS PMA Optional Network Side Transmit and Receive Figure 1 4 1000BASE X SGMII PCS with Optional PMA MII GMII v V2 r e Altera Corporation PCS with Optional Embedded PMA TBI 1000BASE X SGMII e y PCS PMA Optional Network Side 1 25 Gbps Serial About This MegaCore Function C Send Feedback 1 25 Gbps Serial UG 01008 2015 06 15 Example Applications 1 5 Figure 1 5 Stand Alone 10 100 1000 Mbps Ethernet MAC issu Triple Speed Ethernet MegaCore Function z E Gigabit or Fast Copper EG Ainii ily 10 100 1000 Mbps o Ether
81. 16 h0 ToD Synchronizer Signals ToD Synchronizer Common Clock and Reset Signals Table D 3 Clock and Reset Signals for the ToD Synchronizer a INI N NEN CN NN Clk master Input Clock from master ToD domain reset master Input 1 Reset signal that is synchronized to the master ToD clock domain Altera Corporation ToD Synchronizer C Send Feedback UG 01008 2015 06 15 as JN E NNNM NN ToD Synchronizer Interface Signals D 5 Clk slave Input Clock from slave ToD domain reset slave Input 1 Reset signal that is synchronized to the slave ToD clock domain clk_sampling Input 1 Sampling clock to measure the latency across ToD Synchronizer Interface Signals Table D 4 Interface Signals for the ToD Synchronizer es 18 E NN NN start tod sync Input the ToD Synchronizer Assert this signal to start the ToD synchroni zation process When this signal is asserted the synchronization process continues and the time of day from the master ToD clock domain will be repeatedly synchronized with the slave ToD clock domain tod master data Input This signal carries the 64 bit or 96 bit format data for the time of day from the master ToD The width of this signal is determined by the TOD MODE parameter tod slave valid This signal indicates that the tod_data_ slave signal is valid and ready to be loaded into the slave ToD clock in the following cycle T
82. 2 Features 2015 06 15 Features Altera Corporation Complete triple speed Ethernet IP 10 100 1000 Mbps Ethernet MAC 1000BASE X SGMII PCS and embedded PMA Successful validation from the University of New Hampshire UNH InterOperability Lab 10 100 1000 Mbps Ethernet MAC features e Multiple variations 10 100 1000 Mbps Ethernet MAC in full duplex 10 100 Mbps Ethernet MAC in half duplex 10 100 Mbps or 1000 Mbps small MAC resource efficient variant and multiport MAC that supports up to 24 ports e Support for basic VLAN stacked VLAN and jumbo Ethernet frames Also supports control frames including pause frames e Optional internal FIFO buffers depth from 64 bytes to 256 Kbytes e Optional statistics counters 1000BASE X SGMII PCS features e Compliance with Clause 36 of the IEEE standard 802 3 e Optional embedded PMA implemented with serial transceiver or LVDS I O and soft CDR in Altera devices that support this interface at 1 25 Gbps data rate e Support for auto negotiation as defined in Clause 37 e Support for connection to 1000BASE X PHYs Support for IOBASE T 100BASE T and 1000BASE T PHYs if the PHYs support SGMII MAC interfaces e Client side 8 bit or 32 bit Avalon Streaming Avalon ST e Network side medium independent interface MIT gigabit medium independent interface GMIT or reduced gigabit medium independent interface RGMII on the network side Optional loopback on these interfaces e Option
83. 5 06 15 UG 01008 GX subscribe C Send Feedback Additional information about the document and Altera O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01008 F 2 Triple Speed Ethernet IP Core Document Revision History 2015 06 15 Triple Speed Ethernet IP Core Document Revision History e een aaae June 2015 2015 06 15 e Added a new parameter Use clock enable for MAC in the Core Configuration Parameter
84. 6 7 TB MACFWD CRC Sets the cRc_Fwn bit in the command con ig register See 0 Command Config Register Dword Offset 0x02 on page 6 7 TB MACINSERT Sets the ADDR_INS bit in the command con ig register See 0 ADDR Command Config Register Dword Offset 0x02 on page 6 7 TB PROMIS ENA Sets the PRoMIS_EN bit in the command con ig register See 1 Command_Config Register Dword Offset 0x02 on page 6 7 TB_MACPADEN Sets the PAD_EN bit in the command_config register See 1 Command_Config Register Dword Offset 0x02 on page 6 7 B MACLENMAX Maximum frame length 1518 TB IPG LENGTH Sets the tx ipg length register See Base Configuration Registers 12 Dword Offset 0x00 0x17 on page 6 3 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information ISO 900
85. 8 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA UG 01008 2015 06 15 ENLCNNEEEN KRNNN NE 7 KH NN Interface MII Determines the Ethernet side interface of the MAC GMI block e RGMII e MII The only option available for 10 100 Mb e MII GMII Small MAC core variations e GMII Available only for 1000 Mb Small MAC core variations e RGMII Available for 10 100 1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations e MII GMII Available only for 10 100 1000 Mb Ethernet MAC core variations If this is selected media independent interface MII is used for the 10 100 interface and gigabit media independent interface GMII for the gigabit interface 3 2 Ethernet MAC Options Use clock enable On Off Turn on this option to include clock enable signals for for MAC the MAC This option is only applicable for 10 100 1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations Use internal FIFO On Off Turn on this option to include internal FIFO buffers in the core You can only include i
86. 8 7 Sharing PLLs in Devices with GIGE PHY For Cyclone V designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with GIGE PHY you can share the PLLs by placing the associated signals tx p rx p and re c1k to the same I O block of transceiver bank through pin assignment Additionally the xx xecovcikout clock must be buffered by two levels of inverter in the top level module so that it can be fitted to the general I O pins Sharing Transceiver Quads For designs that contain multiple PMA blocks targeting Altera device families with GX transceivers you can combine the transceiver channels in the same quad To share the same transceiver quad the transceiver channels must have the same dynamic reconfiguration setting In other words you must turn on dynamic reconfiguration capabilities in all channels in a quad even though you only intend to use these capabilities in some of the channels The dynamic reconfiguration is always turned on in devices other than Arria GX and Stratix II GX When the dynamic reconfiguration is turned on in designs targeting devices other than Arria 10 Stratix V Arria V and Cyclone V Altera recommends that you connect the dynamic reconfiguration signals to the ALTGX RECONFIG megafunction In Stratix V Arria V and Cyclone V devices Altera recommends that you connect the dynamic reconfi guration signals to the Transceiver Reconfiguration Controller megafunction
87. 8000 ALTERA TSEMAC CMD TX ADDR SEL OFST 16 Configures the TX ADDR SEL ALTERA TSEMAC CMD TX ADDR SEL MSK 0x70000 bits bits 16 18 ALTERA TSEMAC CMD MAGIC ENA OFST 19 Configures the MAGIC_ENA bit ALTERA TSEMAC CMD MAGIC ENA MSK 0x80000 ALTERA TSEMAC CMD SLEEP OFST 20 ALTERA TSEMAC CMD SLEEP MSK 0x10000 Configures the s1 EE bit 0 ALTERA TSEMAC CMD WAKEUP OFST 21 ALTERA TSEMAC CMD WAKEUP MSK 0x20000 Configures the wAKEUP bit 0 ALTERA TSEMAC CMD XOFF GEN OFST 22 ALTERA TSEMAC CMD XOFF GEN MSK Ox40000 Configures the xorr ck bit 0 ALTERA TSEMAC CMD CNTL FRM ENA OFST 23 Configures the CNTL_FRM_ENA ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK 0x80000 bit 0 ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST 24 Configures the NO_LENGTH_ ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK 0x10000 CHECK bit 00 ALTERA_TSEMAC_CMD_ENA_10_OFST 25 ALTERA TSEMAC CMD ENA 10 MSK 0x20000 Configures the ENA 10 bit 00 Altera Corporation Software Programming Interface C Send Feedback UG 01008 2015 06 15 Constants 11 13 Constant Description ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST 26 Configures the RX_ERR_DISC ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK 0x40000 bit 00 ALTERA_TSEMAC_CMD_CNT_RESET_OFST 31 ALTERA_TSEMAC_CMD_CNT_RESET_MSK 0x80000 Configures the cNT_RESET bit 000 Tx Cmd Stat Register Transmit and Receive Command Registers Dword Offse
88. 96b data contains valid timestamp For all receive frame the MAC asserts this signal in the same clock cycle it receives the start of packet avalon_ st_rx_startofpacket is asserted rx_ingress_timestamp_64b_data 64 Carries the ingress timestamp on the receive datapath Consists of 48 bit nanoseconds field and 16 bit fractional nanoseconds field The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress_timestamp_64b_valid rx_ingress_timestamp_64b_ valid When asserted this signal indicates that rx_ingress_timestamp_64b_ data contains valid timestamp For all receive frame the MAC asserts this signal in the same clock cycle it receives the start of packet avalon_ st_rx_startofpacket is asserted IEEE 1588v2 TX Timestamp Signals Table 7 30 IEEE 1588v2 TX Timestamp Interface Signals mesi e ee ER tx egress timestamp 96b data n A transmit interface signal This signal requests timestamp of frames on the TX path The timestamp is used to calculate the residence time Consists of 48 bit seconds field 32 bit nanoseconds field and 16 bit fractional nanoseconds field Interface Signals CJ Send Feedback Altera Corporation 7 30 IEEE 1588v2 TX Timestamp Signals UG 01008 2015 06 15 memi ee TER tx egress timestamp 96b valid A transmit interface signal Assert this signal to indicate that a
89. AX FRAME LENGTH 8196 1 software lib HAL inc altera_avalon_tse h lt BSP project directory gt ifndef BIGBUFSIZE iniche src h nios2 ipport h define BIGBUFSIZE 1536 endif Note to Table 11 2 1 The maximum value for ALTERA_TSE_MAC_MAX_FRAME_LENGTH is defined by the frm_length register API Functions This section describes each provided API function in alphabetical order alt_tse_mac_get_common_speed Prototype alt_tse_mac_get_common_speed np_tse_mac pmac Thread safe No Available from No ISR Include lt altera_avalon_tse h gt Description The alt_tse_mac_get_common_speed obtains the common speed supported by the PHYs connected to a multiport MAC and remote link partners Parameter pmac A pointer to the base of the MAC control interface Return SE PHY SPEED 1000 if the PHYs common speed is 1000 Mbps SE PHY SPEED 100 if the PHYs common speed is 100 Mbps TSE PHY SPEED 10 if the PHYs common speed is 10 Mbps SE PHY SPEED NO COMMON if there isn t a common speed among the PHYs See also alt 32 alt tse mac set common speed Software Programming Interface LJ Send Feedback Altera Corporation 11 6 alt tse mac set common speed UG 01008 2015 06 15 alt tse mac set common speed Prototype alt tse mac set common spee
90. Avalon MM BFM to access the Avalon MM interfaces of the design example components Packet monitors monitors the transmit and receive datapaths and displays the frames in the simulator console Triple Speed Ethernet with IEEE 1588v2 Testbench Files The ip library ethernet altera eth tse design example tse ieee1588 testbench directory contains the testbench files Table 5 3 Triple Speed Ethernet with IEEE 1588v2 Testbench Files avalon bfm wrapper sv A wrapper for the Avalon BFMs that the avalon driver sv file uses avalon driver sv A System Verilog HDL driver that utilizes the BFMs to exercise the transmit and receive path and access the Avalon MM interface Triple Speed Ethernet with IEEE 1588v2 Design Example C Send Feedback Altera Corporation UG 01008 5 6 Triple Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow 2015 06 15 avalon if params pkg sv A SystemVerilog HDL testbench that contains parameters to configure the BFMs Because the configuration is specific to the DUT you must not change the contents of this file avalon_st_eth_packet_monitor sv A SystemVerilog HDL testbench that monitors the Avalon ST transmit and receive interfaces default_test_params_pkg sv A SystemVerilog HDL package that contains the default parameter settings of the testbench eth_mac_frame sv A SystemVerilog HDL class that defines the Ethernet frames The avalon_driver sv file uses this class eth register
91. Count RW Bits 0 to 19 The number of AdjustPeriod clock cycles 0x06 used during offset adjustment Bits 20 to 31 Not used Time of Day ToD Clock C Send Feedback Altera Corporation UG 01008 Using ToD Clock SecondsH SecondsL and NanoSec Registers 2015 06 15 Dword Description Offset 0x07 DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space e Bits 0 to 15 Adjustment value in fractional nanosecond DRIFT_ADJUST_FNS This value is added into the current ToD during the adjustment The default value is 0 e Bits 16 to 19 Adjustment value in nanosecond DRIFT_ADJUST_NS This value is added into the current ToD during the adjustment The default value is 0 e Bits 20 to 32 Not used 0x08 DriftAdjustRate RW The count of clock cycles for each ToD s drift adjustment 0x0 to take effect e Bits 0 to 15 The number of clock cycles ADJUST_ RATE The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space e Bits 16 to 32 Not used Using ToD Clock SecondsH SecondsL and NanoSec Registers To avoid data integrity issue follow these sequence to read from or write to the SecondsH Seconds and NanoSec registers e Read Read from NanoSec then Secondst and followed by seconds e Write Write to SecondsH then Secondst and followed by NanoSec Adjusting T
92. Date June 2015 Ordering Code IP TRIETHERNET Product ID s OOBD Triple Speed Ethernet MegaCore function 0104 IEEE 1588v2 Vendor ID s 6AF7 Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release Related Information MegaCore IP Library Release Notes and Errata Altera Corporation About This MegaCore Function C Send Feedback Getting Started with Altera IP Cores 2015 06 15 UG 01008 GX subscribe C Send Feedback Design Walkthrough 2 This walkthrough explains how to create a Triple Speed Ethernet MegaCore function design using Qsys in the Quartus II software After you generate a custom variation of the Triple Speed Ethernet MegaCore function you can incorporate it into your overall project This walkthrough includes the following steps Creating a New Quartus II Project on page 2 1 Generating a Design Example or Simulation Model on page 2 2 Simulate the System on page 2 2 Compiling the Triple Speed Ethernet MegaCore Function Design on page 2 2 Programming an FPGA Device on page 2 3 dU amc i Creating a New Quartus II Project You need to create a new Quartus II project with the New Project Wizard which specifies the working directory for the project
93. Detection 2015 06 15 Magic Packet Detection Magic packet detection wakes up a node that was put to sleep The MAC function detects magic packets with any of the following destination addresses e Any multicast address e A broadcast address The primary MAC address configured in the mac 0 and mac 1 registers e Any of the supplementary MAC addresses configured in the following registers if they are enabled smac O0 0 smac 0 1 smac 1 0 smac 1 1 smac 2 0 smac 2 1 smac_3 0 and smac 3 1 When the MAC function detects a magic packet the wakeup bit in the command con ig register is set to 1 and the etherStatsPkts and etherStatsOctets statistics registers are incremented Magic packet detection is disabled when the sLEep bit in the command_config register is set to 0 Setting the SLEEP bit to 0 also resets the wakeup bit to 0 and resumes the transmit and receive operations MAC Local Loopback You can enable local loopback on the MII GMII RGMII of the MAC function to exercise the transmit and receive paths If you enable local loopback use the same clock source for both the transmit and receive clocks If you use different clock sources ensure that the difference between the transmit and receive clocks is less than 100 ppm To enable local loopback 1 Initiate software reset by setting the sw RESET bit in command config register to 1 Software reset disables the transmit
94. Family Support For new additions and enhancements to the latest Quartus II software and Altera IP refer to the What s New for Altera IP page of the Altera website For a list of IP support for all device families refer to the All Intellectual Property page of the Altera website Related Information Altera Triple Speed Ethernet MegaCore Function O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 Iso 9001 2008 Registered JA DTE RYA UG 01008 1
95. Feedback Altera Corporation E 4 Packet Classifier Control Insert Signals UG 01008 2015 06 15 EE RENE CO INNEN NN Pisemwiktinmciac Input Indicates whether or not a packet contains CRC e 1 Packet contains CRC e 0 Packet does not contain CRC tx_etstamp_ins_ctrl_in_ residence_time_updat Input Indicates the update for residence time e 1 Allows update for residence time based on decoded results e 0 Prevents update for residence time When this signal is deasserted tx_etstamp_ins_ ctrl_out_residence_time_ update also gets deasserted ex _ SEStamMo ams Ceil aim residence_time_calc_format Input Format of the timestamp to be used for calculating residence time This signal must be aligned to the start of an incoming packet e 1 64 bit timestamp format e 0 96 bit timestamp format tx_etstamp_ins_ctrl_out residence_time_calc_format Output Format of the timestamp to be used for calculating residence time This signal must be aligned to the start of an outgoing packet e 1 64 bit timestamp format e 0 96 bit timestamp format Packet Classifier Control Insert Signals These signals must be aligned to the start of a packet Table E 5 Control Insert Signals for the Packet Classifier I mme tx_etstamp_ins_ctrl_out Output Assert this signal to set the checksum checksum_zero field tx_etstamp_ins_ctrl_out Output Assert this signal to correct the
96. For more information on the frame length refer to Length Checking on page 4 11 Interface Signals C Send Feedback UG 01008 2015 06 15 MAC Transmit Interface Signals 7 7 E ee 0 Receive frame error Indicates that an error has occurred It is the logical OR of rx_ err 5 1 Note to Table 7 7 1 Bits 1 and 2 are not mutually exclusive Ignore CRC error xx err 2 signal if it is asserted at the same time as the invalid length error rx_err 1 signal MAC Transmit Interface Signals Table 7 8 MAC Transmit Interface Signals Avalon ST Signal 1 0 Description Type Avalon ST Signals PE ex elk clk I Transmit clock All transmit signals are To A synchronized on the rising edge of this clock Serano mie clock_connection Set this clock to the required frequency to get the desired bandwidth on the Avalon ST transmit interface This clock can be completely independent from tx_c1k ff_tx_wren valid I Transmit data write enable Assert this signal to indicate that the data on the following signals are valid ff_tx_data DATAWIDTH 1 0 ff tx sop and ff tx eop In cut through mode keep this signal asserted throughout the frame transmission Otherwise the frame is truncated and forwarded to the Ethernet side interface with an error i tz data data I Transmit data DATAWIDTH can be either 8 or DATAWIDTH 1 0 32 depending on the FIFO data width configured When DATAWIDTH is 32 the first byte tr
97. Function Signals 1000 BASE X SGMII PCS Function reset_rx_clk 4 T gmii tx d 0 on Reset gmiitx en reset bc ck Signals GMI e gmiitxem reset_reg_clk 4 Signals e gmii nc d 7 0 tbi nc dk 4 omid tbim d 0 eo Tenbit 4 4 gmiirx err tbi fx dk 10 sana tbi tx d 9 0 md ar md mii tx d 3 0 led an gt mii tx en led cs mii tx err led col Lan MII mii rx d 0 led char err l Signals 43 mid led ink 70 lt _ mii rx err led panel link mii col led disp err mii crs SERDES sd_loopback Control powerdown gt Signals E Bg IX dkena reg clk Signals tx clkena reg_addr 4 0 reg wr PCS d Control reg td Interface teh rx ck reg data in 15 0 Signals Signals tx dk reg data out 15 0 Ly reg_busy EOR set 10 tx serial clk Bal set 100 rx edr refclk Signals lt _ set 1000 tx_analogreset 4 hd ena tx digitalreset 4 rx analogreset 4 Arria 10 rx digitalreset Transceiver tx cal busy Native PHY Signals IX cal busy rx set locktodata 4 rx set locktoref rx is locktodata rx is locktoref Note to Figure 7 7 1 The clock enabler signals are present only in SGMII mode Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 PCS Control Interface Signals 7 37 PCS C
98. ID 32bit Configures the PHY ID of the PCS block Enable SGMII On Off Turn on this option to add the SGMII clock and rate bridge adaptation logic to the PCS block This option allows you to configure the PCS either in SGMII mode or 1000Base X mode If your application only requires 1000BASE X PCS turning off this option reduces resource usage In Cyclone IV GX devices REFCLK 0 1 and REFCLK 4 5 cannot connect directly to the GCLK network If you enable the SGMII bridge you must connect ref clk to an alternative dedicated clock input pin Transceiver Options apply only to variations that include GXB transceiver blocks Parameter Settings LJ Send Feedback Altera Corporation 3 6 PCS Transceiver Options UG 01008 2015 06 15 Export transceiver powerdown signal On Off This option is not supported in Stratix V Arria V Arria V GZ and Cyclone V devices Turn on this option to export the powerdown signal of the GX transceiver to the top level of your design Powerdown is shared among the transceivers in a quad Therefore turning on this option in multiport Ethernet configurations maximizes efficient use of transceivers within the quad Turn off this option to connect the powerdown signal internally to the PCS control register interface This connection allows the host processor to control the transceiver powerdown in your system Enable transceiver dynamic reconfi guration On Off
99. MAC function such as a processor can request the remote device to stop data transmission Related Information MAC Configuration Register Space on page 6 1 Remote Device Congestion When the MAC function receives an XOFF pause frame and the PAUSE_IGNoRE bit in the command config register is set to 0 the MAC function completes the transfer of the current frame and stops transmission for the amount of time specified by the pause quanta in 512 bit times increments Transmission resumes when the timer expires or when the MAC function receives an XON frame You can configure the MAC function to ignore pause frames by setting the PAUsE rcNomk bit in the command config register is set to 1 Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Receive FIFO Buffer and Local Device Congestion 4 19 Receive FIFO Buffer and Local Device Congestion Pause frames generated are compliant to the IEEE Standard 802 3 annex 31A amp B The MAC function generates pause frames when the level of the receive FIFO buffer hits a level that can potentially cause an overflow or at the request of the user application The user application can trigger the generation of an XOFF pause frame by setting the xorr cEN bit in the command con ig register to 1 or asserting the xoff gen signal For MAC variations with internal FIFO buffers the MAC function generates an XOFF pause frame when the level of the FIFO buffer
100. NA and nx Eua bits in the command config register to 0 to disable the transmit and receive paths However the transmit and receive paths are only disabled when the current frame transmission and reception complete To trigger a hardware reset assert the reset signal To trigger a software reset set the sw RESET bit in the command config register to 1 The sw RESET bit is cleared automatically when the software reset ends Functional Description LJ Send Feedback Altera Corporation UG 01008 4 22 PHY Management MDIO 2015 06 15 Altera recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode full half duplex If you want to change the operating speed or mode without changing other configurations preserve the command config register before performing the software reset and restore the register after the changing the MAC operating speed or mode Figure 4 8 Software Reset Sequence START SW RESET 1 RX ENA 0 TX ENA 0 ram Reception 465 pleted No Receive Frames Transmit Frames Clear Statistics Counters Flush FIFO v y Note Ifthe sw_RESET bit is 1 when the line clocks are not available for example cable is disconnected the statistics registers may not be clear
101. Negotiation Activity Simplified Link Partner PCS i i I Link I 4 Synchronization Acquired C with 0x00 ability al z i i 3 I l i C with dev ability register and i i ACK bit set to 0 2 i i 3 Link Timer 2 3 10 ms i C with dev ability register and zo i ACK bit set to 1 ES v I I Se i z 3 Send I Idle sequence 5 Once auto negotiation completes successfully the ability advertised by the link partner device is available in the partner_ability register and the AUTO_NEGOTIATION_COMPLETE bit in the status register is set to l The PCS function restarts auto negotiation when link synchronization is lost and reacquired or when you set the RESTART_AUTO_NEGOTIATION bit in the PCS control register to 1 SGMII Auto Negotiation In SGMII mode the capabilities of the PHY device are advertised and exchanged with a link partner PHY device Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 SGMII Auto Negotiation 4 35 Possible application of SGMII auto negotiation in MAC mode and PHY mode Figure 4 17 SGMII Auto Negotiation in MAC Mode and PHY Mode Altera Device Triple Speed Ethernet Link Partner Ability MegaCore Function SGMII PCS MAC Mode Device Ability I SGMII Link 4 Altera Device Triple Speed Ethernet Me
102. ORE_MSK 0x100 bit ALTERA TSEMAC CMD TX ADDR INS OFST 9 Configures the Tx ADDR INS ALTERA TSEMAC CMD TX ADDR INS MSK 0x200 bit Software Programming Interface CJ Send Feedback Altera Corporation 11 12 Constants UG 01008 2015 06 15 ALTERA TSEMAC CMD HD ENA OFST 10 f Configures the HD_ENA bit ALTERA_TSEMAC_CMD_HD_ENA_MSK 0x400 ALTERA_TSEMAC_CMD_EXCESS_COL_OFST 11 Configures the ExcESS cor bit ALTERA TSEMAC CMD EXCESS COL MSK 0x800 ALTERA TSEMAC CMD LATE COL OFST 12 Configures the LATE_COL bit ALTERA TSEMAC CMD LATE COL MSK 0x1000 ALTERA TSEMAC CMD SW RESET OFS 13 Configures the sw RESET bit ALTERA TSEMAC CMD SW RESET MSK 0x2000 ALTERA TSEMAC CMD MHASH SEL OFST 14 Configures the MHASH SEL bit ALTERA_TSEMAC_CMD_MHASH_SEL_MSK 0x4000 ALTERA_TSEMAC_CMD_LOOPBACK_OFST 15 Configures the Loop_Ena bit ALTERA TSEMAC CMD LOOPBACK MSK 0x
103. PCS and GX transceivers you have the following options in optimizing clock resources e Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance e Utilize the same reference clock for all PMA quads e Utilize the same clock source to drive the reference clock FIFO transmit and receive clocks and system clocks if these clocks run at the same frequency The Quartus II software automatically optimizes the TBI transmit clocks Only one clock source drives the TBI transmit clocks from each PMA quad The calibration clock gxb_cal_blk_clk calibrates the termination resistors in all transceiver channels in a device As there is only one calibration circuit in each device one clock source suffices Note If you do not constrain the PLL inputs and outputs in your design add aerive p11 clocks in the timing constraint file to ensure that the TimeQuest timing analyzer automatically creates derived clocks for the PLL outputs Altera Corporation Design Considerations C Send Feedback UG 01008 2015 06 15 MAC and PCS With GX Transceivers 8 3 Figure 8 1 Clock Distribution in MAC and SGMII PCS with GXB Configuration Optimal Case Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the 10 100 1000 Ethernet MAC SGMII PCS and GX transceivers
104. PCS function operates in loopback mode You can use this signal to configure an external SERDES device to operate in loopback mode Arria 10 Transceiver Native PHY Signals Table 7 22 Arria 10 Transceiver Native PHY Signals aie tx_serial_clk I Serial clock input from the transceiver PLL The frequency of this clock depends on the data rate and clock division factor rx_cdr_refclk I Reference clock input to the receive clock data recovery CDR circuitry tx_analogreset I Resets the analog transmit portion of the transceiver PHY tx_digitalreset I Resets the digital transmit portion of the transceiver PHY rx_analogreset I Resets the analog receive portion of the transceiver PHY rx_digitalreset I Resets the digital receive portion of the transceiver PHY tx_cal_busy O When asserted this signal indicates that the transmit channel is being calibrated rx_cal_busy O When asserted this signal indicates that the receive channel is being calibrated rx set locktodata I Force the receiver CDR to lock to the incoming data rx set locktoref I Force the receiver CDR to lock to the phase and frequency of the input reference clock rx is lockedtodata O When asserted this signal indicates that the CDR PLL is locked to the incoming data rx serial data Altera Corporation Interface Signals C Send Feedback UG 01008 WT 2015 06 15 ECC Status Signals 3 rx is lockedtoref O When asserted this signal indicates that the CDR PLL is locked to the incoming
105. RGMII The 0 value must always be set to 0 B TXFRAMES Specifies the number of frames to be generated by the Avalon ST 5 Ethernet frame generator TB RXIPG IPG on the receive path 12 B ENA VAR IPG 0 A constant IPG TB_RXIPG is used by the GMII RGMII MII 0 Ethernet frame generator 1 Enables variable IPG on the receive path TB LENSTART Specifies the payload length of the first frame generated by the frame 100 generators The payload length of each subsequent frame is incremented by the value of TB_LENSTEP B LENSTEP Specifies the payload length increment 1 B_LENMAX Specifies the maximum payload length generated by the frame 1500 generators If the payload length exceeds this value it wraps around to TB_LENSTART This parameter can be used to test frame length error by setting it to a value larger than the value of TB_MACLENMAX TB_ENA_PADDING 0 Disables padding 1 If the length of frames generated by the GMII RGMII MII Ethernet frame generator is less than the minimum frame length 64 bytes the generator inserts padding bytes to the frames to make up the minimum length TB ENA VLAN 0 Only basic frames are generated 1 Enables VLAN frames generation This value specifies the number of basic frames generated before a VLAN frame is generated followed by a stacked VLAN frame TB STOPREAD Specifies the number of packets to be read from the receive FIFO before reading is suspend
106. RGMII 2048x32 2161 1699 24 0 0 Small MAC Only full duplex mode supported 10 100 MII GMII 2048x32 5614 3666 31 0 0 1000 Mbps Full and half duplex modes Ethernet supported MAC 4 port 10 MII GMII 17017 10612 36 0 0 100 All MAC options enabled TUCO MBPS ss lland half duplex modes Ethernet MAC supported 1000BASE X 1149 661 0 0 0 1000BASE X SGMII l000BASE X 2001 1127 2 0 0 PCS SGMII bridge enabled PMA block GXB Table 1 5 Stratix V Performance and Resource Utilization The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Stratix V device family The estimates are obtained by compiling the Triple Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX SSGXMA7N3F45C3 device with speed grade 3 MegaCore FIFO Buffer Combina Logic Memory Function Size Bits s Registers M20K Blocks MLAB Bits MII 2048x32 1261 2018 11 0 10 100 Full and half duplex modes Mbps Small supported MAC MII 2048x32 1261 2018 11 0 All MAC options enabled GMI 2048x32 1227 1959 10 128 1000 Mbps All MAC options enabled Small MAC RGMII 2048x32 1237 1984 10 128 All MAC options enabled About This MegaCore Function C Send Feedback Altera Corporation UG 01008 2015 06 15 Performance and Resource Utilization 1 11 MegaCore FIFO Buffer Combina Logic M
107. Send Feedback Altera Corporation UG 01008 11 8 tse mac close 2015 06 15 Description Thetriple speed ethernet init function opens and initializes the Triple Speed Ethernet driver Initialization involves the following operations e Set up the NET structure of the MAC device instance e Configure the MAC PHY Address e Register and open the SGDMA RX and TX Module of the MAC device instance e Enable the SGDMA RX interrupt and register it to the Operating System e Register the SGDMA RX callback function e Obtains the PHY Speed of the MAC e Setup the Ethernet MAC Register settings for the Triple Speed Ethernet driver operation e Setup the initial descriptor chain to start the SGDMA RX operation Parameter p_dev A pointer to the Triple Speed Ethernet device instance Return SUCCESS if the Triple Speed Ethernet driver is successfully initialized See also tse mac close tse mac close Prototype int tse mac close int iface Thread safe No Available from No ISR Include triple speed ethernet iniche h Description The tse mac close closes the Triple Speed Ethernet driver by performing the following operations e Configure the admin and operation status of the NET structure of the Triple Speed Ethernet driver instance to ALTERA TSE ADMIN STATUS DOWN e De register the SGDMA RX interrupt from the operating system e Clear the RX ENA bit in the
108. TX and RX path is disable Wait Command_config Register 0x00802220 MAC FIFO Configuration Tx_section_empty Max FIFO size 16 Tx_almost_full 3 Tx_almost_empty 8 Rx_section_empty Max FIFO size 16 Rx_almost_full 8 Rx_almost_empty 8 Configuration Register Space C Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet System with MII GMII or RGMII 6 29 Cut Throught Mode Set this Threshold to 0 to enable Store and Forward Mode Tx section full 16 Cut Throught Mode Set this Threshold to 0 to enable Store and Forward Mode Rx section full 16 MAC Address Configuration MAC address is 00 1C 23 17 4A CB mac 0 0x17231C00 mac 1 0x0000CB4A MAC Function Configuration Maximum Frame Length is 1518 bytes Frm length 1518 Minimum Inter Packet Gap is 12 bytes Tx ipg length 12 Maximum Pause Quanta Value for Flow Control Pause quant OxFFFF Set the MAC with the following option 100Mbps User can get this information from the PHY status PCS status Full Duplex User can get this information from the PHY status PCS status Padding Removal on Receive CRC Removal TX MAC Address Insertion on Transmit Packet Select mac 0 and mac 1 as the source MAC Address Command config Register 0x00800220 Reset MAC Altera recommends that you perform a software reset when there is a change in the MAC speed or duplex The MAC software reset bit self clears when the software r
109. Table 6 8 IEEE 1588v2 Feature PMA Delay Hardware Timing Adjustment Delay Device Stratix V or Arria V GZ 53 UI 26 UI Digital Arria V GX Arria V GT or Arria V SoC 52 UI 34 UI Cyclone V GX or Cyclone V SoC 32 UI 44 UI Stratix V 1 1 ns 1 75 ns Analog Arria V 1 1 ns 1 75 ns Cyclone V 1 1 ns 1 75 ns Table 6 9 IEEE 1588v2 Feature LVDS I O Delay Hardware Timing Adjustment Delay Device Stratix V or Arria V GZ Arria V GX Arria V GT or Arria V SoC PMA digital and analog delay of simulation model for the IEEE 1588v2 feature and the register timing adjustment Digital Table 6 10 IEEE 1588v2 Feature PMA Delay Simulation Model Timing Adjustment Delay Device Stratix V or Arria V GZ 11 UI 33 5 UI Arria V GX Arria V GT or Arria V SoC 10 UI 23 5 UI Digital Arria 10 32 UI 23 5 UI Cyclone V GX or Cyclone V SoC 10 UI 23 5 UI Configuration Register Space Altera Corporation C Send Feedback UG 01008 6 18 PCS Configuration Register Space 2015 06 15 Table 6 11 IEEE 1588v2 Feature LVDS I O Delay Simulation Model Timing Adjustment Delay Device Stratix V or Arria V GZ 19 5 UI 26 UI Arria V GX Arria V GT or Arria V SoC 19 5 UI 26 UI Digital Arria 10 19 5 UI 24 5 UI Cyclone V GX or Cyclone V SoC 19 5 UI 26 UI PCS Configuration Register Space This section describes the PCS registers Use the registers to configure the PCS func
110. The sequence is sent for a time specified in the PCS 1ink timer register mapped in the PCS register space When the 1ink timer time expires the PCS ev ability register is advertised with the acx bit set to 0 for the link partner The auto negotiation state machine checks for three consecutive C sequences received from the link partner The auto negotiation state machine then sets the acx bit to 1 in the advertised aev ability register and checks if three consecutive C sequences are received from the link partner with the acx bit set to 1 Auto negotiation waits for the value configured in the 1ink timer register to ensure no more consecu tive C sequences are received from the link partner The auto negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires After auto negotiation completes successfully the user software reads both the dev_ability and partner ability register and proceed to resolve priority for duplex mode and pause mode If the design contains a MAC and PCS the user software configures the MAC with a proper resolved pause mode by setting the PAUSE IGNORE bit in command config register To disable pause frame generation based on the receive FIFO buffer level you should set the xx section empty register accordingly Functional Description Altera Corporation LJ Send Feedback UG 01008 4 34 SGMII Auto Negotiation 2015 06 15 Figure 4 16 Auto
111. Transceiver ATX PLL with an output clock frequency of 1250 0 MHz instead of applying the default value of 625 MHz when using the Arria 10 Transceiver Native PHY with the Triple Speed Ethernet IP core Refer to the respective device handbook for more information on dynamic reconfiguration in Altera devices Related Information Arria 10 Transceiver PHY User Guide More information about the Arria 10 Transceiver ATX PLL Parameter Settings LJ Send Feedback Altera Corporation Functional Description 4 2015 06 15 UG 01008 GX subscribe Send Feedback The Triple Speed Ethernet MegaCore function includes the following functions e 10 100 1000 Ethernet MAC e 1000BASE X SGMII PCS With Optional Embedded PMA e Altera IEEE 1588v2 10 100 1000 Ethernet MAC The Altera 10 100 1000 Ethernet MAC function handles the flow of data between user applications and Ethernet network through an internal or external Ethernet PHY Altera offers the following MAC variations e Variations with internal FIFO buffers supports only single port e Variations without internal FIFO buffers supports up to 24 ports and the ports can operate at different speeds e Small MAC provides basic functionalities of a MAC function using minimal resources Refer to 10 100 1000 Ethernet MAC Versus Small MAC on page 1 3 for a feature comparison between the 10 100 1000 Ethernet MAC and small MAC The MAC function supports the following Ethernet fram
112. Triple Speed Ethernet MegaCore Function User Guide Last updated for Altera Complete Design Suite 15 0 X subscribe UG 01008 2015 06 15 C Send Feedback 101 Innovation Drive LJ San Jose CA 95134 N DTE BJAN www altera com TOC 2 Contents About This MeoaU ore PUnCLOD aoro RErt t ERE PR EET EPEPAAR UE PEREE EP U IEEE UE 1 1 About This MegaCore PunclOB ien sbn ved HAT tesa ERO OR ERR DA FIpIOD rcr ND MU I QI IDA Opa RIVE 1 1 ibis edidere Nr 1 1 hn I 1 2 10 100 1000 Ethernet MAC Versus Small NDAG ud iue ieatniecut eiae inb tenent ey te RES ERA Rz 1 3 High Level Block DIaptatns isasensosetsttn nip mieh ped peior diarias made puniat tiet 1 3 Exaimple Applicatlonis eoe orn ebd a e Re IR TER RA Eh Besten qe eR UI RIS 1 5 Megatcore Veriliedloibuneozenion PRO RH MADRE RUM RD gp qM DRM i DEM DN RN 1 6 Optical Plat OBL eoo poU RR REA NI NUR B pit hid toV M rd RUE 1 7 Copper Platformers M 1 7 Performance and Resource Wa OI eoe sit ra Ur rtis atepa croit dedi rsen redit bcosu bns 1 7 Release UN IO NEN 1 12 Getting Started with Altera IP Cores ssessoeesoeesseessoessoessoseseesssesssoesseesseessses 2 1 Design VY AMM Ue cys otes occas se vache ast inv ansionssnanan bape acon oynervednoasdnnepatannaiinana M s riait 2 1 Creating a New Quartus II Projects te oia e die ed vie 2 1 Generating a Design Example
113. UG 01008 2015 06 15 Avalon MM Description Signal Type reg data out 31 0 readdata Register read data Bit 0 is the least significant bit reg busy waitrequest Register interface busy Asserted during register read or register write access deasserted when the current register access completes MAC Status Signals The MAC status signals which allow you to set the transfer mode of the Ethernet side interface Table 7 4 MAC Status Signals O Ethernet mode This signal is set to 1 when the MAC function is eth mode configured to operate at 1000 Mbps set to 0 when it is configured to operate at 10 100 Mbps ena 10 O 10 Mbps enable This signal is set to 1 to indicate that the PHY interface should operate at 10 Mbps Valid only when the et h_ mode signal is set to 0 set 1000 I Gigabit mode selection Can be driven to 1 by an external device for example a PHY device to set the MAC function to operate in gigabit When set to 0 the MAC is set to operate in 10 100 Mbps This signal is ignored when the ETH_SPEED bit in the command config register is set to 1 set 10 10 Mbps selection Can be driven to 1 by an external device for example a PHY device to indicate that the MAC function is connected to a 10 Mbps PHY device When set to 0 the MAC function is set to operate in 100 Mbps or gigabit mode This signal is ignored when the ETH_SPEED or ENA 10 bit in the command co
114. USE NS RN EDS UE 4 12 FIFO Buffer Threshold cau desse opta D DRE e RUINA OUO BAN ARE ADU aN aaa d ed Pid a rk 4 13 Gong stion and Flow GCOBIOL agens to qnae i Ran cip eim dert p darn rt RE 4 18 Altera Corporation DVN AIG PAC I P 4 19 MAC Local Loopback ritsevos atia as aiti a ode au cha OM UR BERNER 4 20 MAG Error Correction COGO sese sic tta api p PM rera Y LU IH I REL FE ra sd brUr e erst 4 20 Du You 4 21 PHY Maugeenentt NIDMO quoubsssespxmmipres diss b redi eno iaiia E SE pena ia 4 22 Contiecting MAC fo External PELYS ai oudisce qtasdanctes La dd a pia Oe to Ia RU vrbe a 4 24 1000BASE X SGMII PCS With Optional Embedded PMA serene 4 28 IO0OBASE X SGMII PCS Architecture assinar ii 4 29 Transmit Opetation nter dee e eret in SY PEEN KSE EE cree el e oL e ES dd db ca e eee aan 4 30 Receive Operation nacti teet o Re qe e dd Lee ea e eta ad Che Re Ex 4 3 Transmit arid Receive Latenctes aseo t erre etti pb reip ari pend oi a beata Rd SE 4 32 EIEI u m E 4 32 Auto NEG OU ATOM a oe rere EEA e n SI EA E E E EE 4 33 Te bit Int rfa e sisseseade 4 36 PHY Loopback n E E R E EE 4 37 Jd bdo 22b 4 38 IOQUBASE X SGMLIL PCS ROSE oie edo pu mea divi rip Rd in i t n Re M p uibs Reste bs cpu 4 39 Altera IEEE 1588v2 Feature ete ane
115. You can get the value for the dev ability register from the system level where the Triple Speed Ethernet IP core is integrated If the IP core is integrated in the system level with another IP that resolves the copper speed and duplex information use these values to set the dev ability register Table 6 17 Dev Ability Register Bits Description in SGMII PHY Mode a KENN Reserved Always set bit 0 to 1 and bits1 9 to 0 11 10 sPEED 1 0 RW Link partner interface speed e 00 copper interface speed is 10 Mbps e Ol copper interface speed is 100 Mbps e 10 copper interface speed is 1 gigabit e 11 reserved 12 COPPER_DUPLEX_ RW Link partner duplex capability VEO e 1 copper interface is capable of operating in full duplex mode e 0 copper interface is capable of operating in half duplex mode e 1 Gbps speed does not support half duplex mode 13 Reserved Always set this bit to 0 14 ACK RO Acknowledge Value as specified in the IEEE 802 3z standard 15 COPPER LINK STATUS RW Copper link partner status e 1 copper interface link is up e 0 copper interface link is down Configuration Register Space Altera Corporation LJ Send Feedback UG 01008 6 26 An Expansion Register Word Offset 0x06 2015 06 15 An Expansion Register Word Offset 0x06 Table 6 18 An Expansion Register Description a i e EHE NK PARTNER AUTO A value of 1 indicates that the link par
116. a timing adapter to change the ready latency to zero Design Considerations Altera Corporation LJ Send Feedback UG 01008 8 8 Exposed Ports in the New User Interface 2015 06 15 Table 8 2 Exposed Ports and Recommended Termination Value for MAC Variation With Internal FIFO Buffers WEIS xon_gen I 1 1 b0 xoff_gen I 1 1 b0 magic_wakeup O 1 Left open magic_sleep_n I 1 1 b1 ff tx crc fwd I 1 1 b0 ff tx septy O 1 Left open tx_ff_uflow O 1 Left open ar tx e full O 1 Left open ff_tx_a_empty O 1 Left open pg err stat O 18 Left open rx_frm_type O 4 Left open ff rx dsav O 1 Left open ff rx a full O 1 Left open ff rx a empty O 1 Left open Table 8 3 lists the following ports that are exposed in the Qsys system for a design that has MAC variation without internal FIFO buffers Table 8 3 Exposed Ports and Recommended Termination Value for MAC Variation Without Internal FIFO Buffers Port Name VK Width Recommended Termination Value xon_gen_ lt n gt I 1 1 b0 xoff_gen_ lt n gt I 1 1 b0 magic_wakeup_ lt n gt O 1 Left open magic_sleep_n_ lt n gt I 1 l bl ff tx crc fwd n I 1 1 b0 Altera Corporation Design Considerations C Send Feedback Timing Constraints 2015 06 15 UG 01008 GX subscribe C Send Feedback Altera provides timing constraint files sdc to ensure that the Triple Speed Ethernet MegaCore function meets the design timing requirements in Altera d
117. al management data I O MDIO master interface for PHY device management PCS interfaces e Client side MII or GMII e Network side ten bit interface TBI for PCS without PMA 1 25 Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I O and soft CDR in Altera devices that support this interface at 1 25 Gbps data rate Programmable features via 32 bit configuration registers e FIFO buffer thresholds e Pause quanta for flow control e Source and destination MAC addresses e Address filtering on receive up to 5 unicast and 64 multicast MAC addresses e Promiscuous mode receive frame filtering is disabled in this mode e Frame length in MAC only variation up to 64 Kbytes including jumbo frames In all variants containing 1000BASE X SGMII PCS the frame length is up to 10 Kbytes e Optional auto negotiation for the 1000BASE X SGMII PCS Error correction code protection feature for internal memory blocks Optional IEEE 1588v2 feature for 10 100 1000 Mbps Ethernet MAC with SGMII PCS and embedded serial PMA variation operating without internal FIFO buffer in full duplex mode 10 100 1000 Mbps MAC with SGMII PCS and embedded LVDS I O or MAC only variation operating without internal FIFO buffer in full duplex mode These features are supported in Arria V Arria 10 Cyclone V MAX 10 and Stratix V device families About This MegaCore Function C Send Feedback UG 01008 1 2015 06 15 10 100 1000 E
118. ames against the length type field in receive frames e Set this bit to 1 to omit length checking This bit is not available in the small MAC variation 25 ENA_10 RW 10 Mbps interface enable Set this bit to 1 to enable the 10 Mbps interface The MAC function asserts the ena_10 signal when you enable the 10 Mbps interface You can also enable the 10 Mbps interface by asserting the set_10 signal 26 RX ERR DISC RW Erroneous frames processing on receive e Set this bit to 1 to discard erroneous frames received This applies only when you enable store and forward operation in the receive FIFO buffer by setting the rx_ section full register to 0 e Set this bit to 0 to forward erroneous frames to the user application with rx_err 0 asserted Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Statistics Counters Dword Offset 0x18 0x38 6 11 DISABLE READ Set this bit to 1 to disable MAC configuration register read TIMEOUT timeout 28 Reserved 30 31 CNT RESET RW Statistics counters reset Set this bit to 1 to clear the statistics counters The MAC function clears this bit when the reset sequence completes Statistics Counters Dword Offset 0x18 0x38 Table 6 4 describes the read only registers that collect the statistics on the transmit and receive datapaths A hardware reset clears these registe
119. and embedded LVDS I O without FIFO buffer in full duplex mode e 10 100 1000 Mbps MAC without FIFO buffer in full duplex mode Functional Description C Send Feedback Altera Corporation UG 01008 2015 06 15 IEEE 1588v2 Features 4 41 IEEE 1588v2 Features Supports 4 types of PTP clock on the transmit datapath e Master and slave ordinary clock e Master and slave boundary clock e End to end E2E transparent clock e Peer to peer P2P transparent clock Supports PTP message types PTP event messages Sync Delay Req Pdelay Req and Pdelay Resp e PTP general messages Follow Up Delay Resp Pdelay Resp Follow Up Announce Management and Signaling Supports simultaneous 1 step and 2 step clock synchronizations on the transmit datapath e 1 step clock synchronization The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time e 2 step clock synchronization The MAC function provides accurate timestamp and the related fingerprint for all PTP message Supports the following PHY operating speed accuracy e random error e 10Mbps NA e 100Mbps timestamp accuracy of 5 ns e 1000Mbps timestamp accuracy of 2 ns e static error timestamp accuracy of 3 ns Supports IEEE 802 3 UDP IPv4 and UDP IPv6 transfer protocols for the PTP frames Supports untagged VLAN tagged Stacked VLAN Tagged PTP frames and any number of MPLS labels Supports configu
120. and ignore them on reads If your variation does not include the PCS function you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices If your MAC variation includes the PCS function the PCS function is always device 0 and its configuration registers PCS Configuration Register Space on page 6 18 occupy MDIO Space 0 You can use MDIO Space 1 to map to a PHY device OxCO Supplementary Supplementary unicast addresses For more information about these 0xC7 Address addresses refer to Supplementary Address Dword Offset 0xCO 0xC7 on page 6 15 0xC8 Reserved 1 Unused OxCF OxD0 IEEE 1588v2 Feature Registers to configure the IEEE 1588v2 feature For more information 0xD6 about these registers refer to IEEE 1588v2 Feature Dword Offset 0xD0 0xD6 on page 6 16 OxD7 Reserved 1 Unused OxFF Note to Table 6 1 1 Altera recommends that you set all bits in the reserved registers to 0 and ignore them on reads Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Base Configuration Registers Dword Offset 0x00 0x17 6 3 Base Configuration Registers Dword Offset 0x00 0x17 Table 6 2 lists the base registers you can use to configure the MAC function A software reset does not reset these registers except the first two bits Tx ENA and Rx ENA 0 in the command con ig register Table 6 2 Base Configuration Register Map Dword Offset
121. and receive operations flushes the internal FIFOs and clears the statistics counters The sw RESET bit is automatically cleared upon completion 2 When software reset is complete enable local loopback on the MAC s MII GMII RGMII by setting the LOOP_ENA bit in command config register to 1 3 Enable transmit and receive operations by setting the Tx ENA and Rx Ewa bits in command con ig register to 1 4 Initiate frame transmission 5 Compare the statistics counters aFramesTransmittedOK and aFramesReceivedoOk to verify that the transmit and receive frame counts are equal 6 Check the statistics counters ifinErrors and ifOutErrors to determine the number of packets transmitted and received with errors 7 To disable loopback initiate a software reset and set the LOOP_ENA bit in command config register to 0 MAC Error Correction Code The error correction code feature is implemented to the memory instances in the MegaCore function This feature is capable of detecting single and double bit errors and can fix single bit errors in the corrupted data Note This feature is only applicable for Stratix V and Arria 10 devices Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 MAC Reset 4 21 Table 4 8 Core Variation and ECC Protection Support 10 100 1000 Mb Ethernet MAC Protects the following options transmit and receive FIFO buffer Retransmit buffer if half du
122. ansmission with different clock mode The testbench sends a total of three packets e l step PTP Sync message over Ethernet e l step PTP Sync message over UDP IPv4 with VLAN tag e 2 step PTP Sync message over UDP IPv6 with stacked VLAN tag Configures clock mode of Packet Classifier to End to end Transparent Clock mode Starts packet transmission The testbench sends a total of three packets e l step PTP Sync message over Ethernet e l step PTP Sync message over UDP IPv4 with VLAN tag e 2 step PTP Sync message over UDP IPv6 with stacked VLAN tag Ends transmission Triple Speed Ethernet with IEEE 1588v2 Design Example m Send Feedback UG 01008 2015 06 15 Simulating Triple Speed Ethernet with IEEE 1588v2 Testbench with 5 7 Simulating Triple Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Simulator To use the ModelSim simulator to simulate the testbench design 1 Copy the respective design example directory to your preferred project directory tse ieee1588 from ip library ethernet altera eth tse design example 2 Launch Qsys from the Tools menu and open the tse 1588 qsys file 3 On the Generation tab select either a Verilog HDL or VHDL simulation model 4 Click Generate to generate the simulation and synthesis files 5 Run the following command to set up the required libraries to compile the generated IP Functional simulation model and to exercise the simulation model with the provided testbench do tb run
123. ansmitted is tx data 31 24 followed by tx data 23 16 and so forth Interface Signals Altera Corporation LJ Send Feedback 7 8 MAC Transmit Interface Signals Avalon ST Signal Description Type ff tx mod 1 0 empty UG 01008 2015 06 15 Transmit data modulo Indicates invalid bytes in the final frame word e ll tx data 23 0 is not valid e 10 tx data 15 0 is not valid e Ol tx data 7 0 is not valid e 00 tx data 31 0 is valid This signal applies only when DATAWIDTH is set to 32 ibit jo SOO startofpacket Transmit start of packet Assert this signal when the first byte in the frame the first byte of the destination address is driven on tx data ff tx eop endofpacket Transmit end of packet Assert this signal when the last byte in the frame the last byte of the FCS field is driven on tx data ff tx err Sree Transmit frame error Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid The MAC function forwards the invalid frame to the GMII with an error ff tx rdy ready MAC ready When asserted the MAC function is ready to accept data from the user application Component Specific Signals ff tx crc fwa oer WOE ILOW ff_tx_septy Transmit CRC insertion Set this signal to 0 when ff_tx_eop is set to 1 to instruct the MAC function to compute a CRC and insert it i
124. assigns the project name and designates the name of the top level design entity To create a new project follow these steps 1 From the Windows Start menu select Programs gt Altera gt Quartus II version to launch the Quartus II software Alternatively you can use the Quartus II Web Edition software 2 On the File menu click New Project Wizard 3 In the New Project Wizard Directory Name Top Level Entity page specify the working directory project name and top level design entity name Click Next 4 In the New Project Wizard Add Files page select the existing design files if any you want to include in the project Click Next To include existing files you must specify the directory path to where you installed the MegaCore function You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s
125. at holds data so that the output can align with the start of an incoming packet tx etstamp ins ctrl in ingress Input 64 64 bit format of ingress timestamp timestamp 64b that holds data so that the output can align with the start of an incoming packet tx etstamp ins ctrl out Output 96 96 bit format of ingress timestamp ingress timestamp 96b that holds data so that the output can align with the start of an outgoing packet tx etstamp ins ctrl out Output 64 64 bit format of ingress timestamp ingress_timestamp_64b that holds data so that the output can align with the start of an outgoing packet tx egress timestamp request in Input 1 Assert this signal when timestamp is valid required for the particular frame This signal must be aligned to the start of an incoming packet tx egress timestamp request in Input 4 A width configurable fingerprint fingerprint that correlates timestamps for incoming packets tx egress timestamp request Output 1 Assert this signal when timestamp is out valid required for the particular frame This signal must be aligned to the start of an outgoing packet tx egress timestamp request Output 4 A width configurable fingerprint out fingerprint that correlates timestamps for outgoing packets clock mode Input 2 Determines the clock mode e 00 Ordinary clock e 01 Boundary clock e 10 End to end transparent clock e 11 Peer to peer transparent clock Packet Classifier J send
126. atus LED Signals Pause and Magic Packet Signals PHY Management Signals SERDES Control Signals IEEE 1588v2 Signals ECC Status Signal 1 The SERDES control signals are present in variations targeting devices with GX transceivers For Stratix II GX and Arria GX devices the reconfiguration signals reconfig clk reconfig togxb and reconfig fromgxb are included only when the Enable transceiver dynamic reconfiguration option is turned on The reconfiguration signals gxb cal blk clk pcs pwrdwn out gxb pwrdn in Interface Signals LJ Send Feedback Altera Corporation IEEE 1588v2 RX Timestamp Signals UG 01008 2015 06 15 reconfig_clk and reconfig_busy are not present in variations targeting Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers Table 7 28 References Clock and reset signals Clock and Reset Signal on page 7 2 MAC control interface MAC Control Interface Signals on page 7 3 MAC transmit interface MAC Transmit Interface Signals on page 7 7 MAC receive interface MAC Receive Interface Signals on page 7 4 MAC packet classification signals Multiport MAC Packet Classification Signals on page 7 15 MAC FIFO status signals Multiport MAC FIFO Status Signals on page 7 16 Pause and magic packet signals Pause and Magic Packet Signals on page 7 9 PHY management signals PHY Management Signals on page 7 11 1 25 Gbps Serial Signa
127. be used for residence time calculation 0 96 bits 96 bits egress timestamp 96 bits ingress timestamp 1 64 bits 64 bits egress timestamp 64 bits ingress timestamp Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins ctrl checksum zero Assert this signal to set the checksum field of UDP IPv4 to zero Required offset location of checksum field Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins ctrl checksum COPPOCL Assert this signal to correct UDP IPv6 packet checksum by updating the checksum correction which is specified by checksum correction offset Required offset location of checksum correction Assert this signal in the same clock cycle as the start of packet avalon_st_ tx startofpacket is asserted tx etstamp ins ctrl offset timestamp The location of the timestamp field relative to the first byte of the packet Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins ctrl offset correction field 16 The location of the correction field relative to the first byte of the packet Assert this signal in the same clock cycle as the start of packet avalon_st_ tx startofpacket is asserted Interface Signals J send Feedback Al
128. bench design To use the ModelSim simulation software to simulate the testbench design follow these steps 1 For Verilog testbench design Altera Corporation Testbench C Send Feedback UG 01008 2015 06 15 Simulation Model Files 10 5 a Browse to the following project directory variation name testbench testbench verilog variation name b Run the following command to set up the required libraries to compile the generated IP Functional simulation model and to exercise the simulation model with the provided testbench run variation name tb tcl 2 For VHDL testbench design a Browse to the following project directory variation name testbench testbench vhdl variation name b Run the following command to set up the required libraries to compile the generated IP Functional simulation model and to exercise the simulation model with the provided testbench run variation name tb tcl For more information about simulating Altera IP cores refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook Note Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Simulation Model Files Previously the Triple Speed Ethernet MegaCore function generates a variation name vho or variation name vo file for VHDL or Verilog HDL IP functional simulation model For the new Tripl
129. cate such errors The user application should subsequently discard these frames by setting the Rx ERR Dz15c bit in the command config register to 1 Magic Packets A magic packet can be a unicast multicast or broadcast packet which carries a defined sequence in the payload section Magic packets are received and acted upon only under specific conditions typically in power down mode The defined sequence is a stream of six consecutive OxFF bytes followed by a sequence of 16 consecutive unicast MAC addresses The unicast address is the address of the node to be awakened The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header optional padding and CRC Sleep Mode You can only put a node to sleep set SLEEP bit in the command con ig register to 1 and deassert the magic sleep n signal if magic packet detection is enabled set the mAG1Cc Ewa bit in the command config register to 1 Altera recommends that you do not put a node to sleep if you disable magic packet detection Network transmission is disabled when a node is put to sleep The receiver remains enabled but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node In the sleep mode only etherStatsPkts and etherStatsOctets count the traffic statistics Functional Description Altera Corporation LJ Send Feedback UG 01008 4 20 Magic Packet
130. cation Signals Avalon ST Description Signal Type pkt_class_valid_n valid When asserted this signal indicates that classifi cation data is valid Interface Signals C Send Feedback Altera Corporation Multiport MAC FIFO Status Signals UG 01008 2015 06 15 Avalon ST Description Signal Type pkt_class_data_ n 4 0 data Classification presented at the beginning of each packet Bit 4 Set to 1 for unicast frames Bit 3 Set to 1 for broadcast frames Bit 2 Set to 1 for multicast frames Bit 1 Set to 1 for VLAN frames Bit 0 Set to 1 for stacked VLAN frames Multiport MAC FIFO Status Signals The MAC FIFO status interface is an Avalon ST sink port which streams in information on the fill level of the external FIFO buffer to the MAC function Table 7 17 MAC FIFO Status Signals Signal Name Avalon ST Description Signal Type rx_afull_valid_n valid Assert this signal to indicate that the fill level of the external FIFO buffer rx_afull_data_ n 1 0 is valid rx afull data n 1 0 rx afull channel CHANNEL WIDTH 1 0 data channel Carries the fill level of the external FIFO buffer rx afull data n 1 Set to 1 if the external receive FIFO buffer reaches the initial warning level indicating that it is almost full Upon detecting this the MAC function generates pause frames rx afull data n 0 Set to 1 if the external receive FIFO buffer reac
131. ch the parameter editor Specify the required parameters in the parameter editor Click Finish On the Generation tab select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on 8 Click Generate to generate the simulation and synthesis files NAU A Triple Speed Ethernet with IEEE 1588v2 Testbench Altera provides a testbench for you to verify the Triple Speed Ethernet with IEFE 1588v2 design example The following sections describe the testbench its components and use The testbench operates in loopback mode Figure 5 3 shows the flow of the packets in the design example Altera Corporation Triple Speed Ethernet with IEEE 1588v2 Design Example m Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet with IEEE 1588v2 Testbench Files 5 5 Figure 5 3 Testbench Block Diagram Testbench Ethernet Packet Avalon MM Monitor Control Register Avalon ST Transmit Frame Generator Avalon ST DUT Loopback on serial interface Avalon ST Receive Frame Avalon ST Monitor avalon bfm wrapper sv Ethernet Packet Avalon Driver Monitor The testbenches comprise the following modules e Device under test DUT the design example Avalon driver uses Avalon ST master bus functional models BFMs to exercise the transmit and receive paths The driver also uses the master
132. cifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 A 2 VLAN and Stacked VLAN Frame Format VLAN and Stacked VLAN Frame Format The extension of a basic MAC frame is a virtual local area network VLAN tagged frame which contains an additional 4 byte field for the VLAN tag and information between the source address and length type fields VLAN tagging is defined by the IEEE Standard 802 1Q VLAN tagging can identify and separate many groups network traffic from each other in enterprise and metro networks Each VLAN group can consist of many users with varied MAC address in different geographical locations of a network VLAN tagging increases and scales the network performance and add privacy and safety to various groups and customers network traffic UG 01008 2015 06 15 VLAN tagged frames have a maximum length of 1522 bytes excluding the preamble and the SFD fields Figure A 2 VLAN Tagged MAC Frame Format 7 octets PREAMBLE 1 octet SFD 6 octets DESTINATION ADDRESS 6 octets SOURCE ADDRESS 2 octets LENGTH TYPE VLAN Tag 0x8100 2 octets VLAN info Frame length lt gt octets CLIENT LENGTH TYPE 0 1500 9600 octets PAY LOAD DATA 0 42 octets PAD 4 octets FRAME CHECK SEQUENCE EXTENSION half duplex only In metro Ethernet applications which require more scalabil
133. conds ToD Synchronizer LJ Send Feedback Altera Corporation D 4 ToD Synchronizer Signals UG 01008 2015 06 15 LS NENNEN 7 ON SYNC MODE Between 0 and 6 Value that defines types of synchronization The default value is 1 e 0 Master clock frequency is 125MHz 1G while slave is 156 25MHz 10G e 1 Master clock frequency is 156 25MHz 10G while slave is 125MHz 1G e 2 Master and slave are same in the same frequency can be in different ppm or phase When you select this mode specify the period of master and slave through the PERIOD_ NSEC and PERIOD FNSEC parameters e 3 Master clock frequency is 156 25MHz 10G while slave is 312 5MHz 10G e 4 Master clock frequency is 312 5MHz 10G while slave is 156 25MHz 10G e 5 Master clock frequency is 125MHz 1G while slave is 312 5MHz 10G e 6 Master clock frequency is 312 5MHz 10G while slave is 125MHz 1G PERIOD NSEC Between 0 and 4 hF A 4 bit value that defines the reset value for a nanosecond of period The default value is 4 h6 to capture 6 4ns for 156 25 MHz frequency For 125 MHz frequency 1G set this parameter to A h8 PERIOD FNSEC Between 0 and 16 hFFFF A 4 bit value that defines the reset value for a fractional nanosecond of period The default value is 16 h6666 to capture 0 4ns of 6 4ns for 156 25 MHz frequency For 125 MHz frequency 1G set this parameter to
134. culation is mandatory for the UDP IPv6 protocol You must extend 2 bytes at the end of the UDP payload of the PTP frame The MAC function modifies the extended bytes to ensure that the UDP checksum remains uncompromised Functional Description Altera Corporation LJ Send Feedback 4 46 PTP Frame over UDP IPv6 Figure 4 29 PTP Frame over UDP IPv6 6 Octets 6 Octets 2 Octets 4 Octet 2 Octets 1 Octet 1 Octet 16 Octets 16 Octets 2 Octets 2 Octets 2 Octets 2 Octets 1 Octet 1 Octet 2 Octets 1 Octet 1 Octet 2 Octets 8 Octets 4 Octets 10 Octets 2 Octets 1 Octet 1 Octet 10 Octets 0 1500 9600 Octets 2 Octets 4 Octets Note to Figure 4 29 Destination Address Source Address Length Type 0x86DD 1 Version Traffic Class Flow Label Payload Length Next Header 0x11 Hop Limit Source IP Address Destination IP Address Source Port Destination Port 319 320 Length Checksum transportSpecific messagelype reserved versionPTP messageLength domainNumber reserved flagField correctionField reserved SourcePortldentify sequenceld controlField logMessagelnterval TimeStamp extended bytes CRC UG 01008 2015 06 15 MAC Header IP Header UDP Header PTP Header 1 For frames with VLAN or Stacked VLAN tag add 4 or 8 octets offsets before the length type field Altera Corporation Functional Descri
135. d Ethernet MegaCore function to exercise your custom MegaCore function variation The testbench includes the following features e Easy to use simulation environment for any standard HDL simulator e Simulation of all basic Ethernet packet transactions e Open source Verilog HDL and VHDL testbench files The provided testbench applies only to custom MegaCore function variations created using Osys Triple Speed Ethernet Testbench Architecture Figure 10 1 Triple Speed Ethernet Testbench Architecture System Device Under Test Ethemet Frame l Generator i Port 0 Pie Port 1 Ns Port 2 Frame id LP Monitor 777 love Slave 0 t io Testbench Control Simulation Configuration Parameters 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any a visus egistere products and services at any time without
136. d np tse mac pmac alt 32 common speed Thread safe No Available from No ISR Include lt altera_avalon_tse h gt Description Thealt tse mac set common speed sets the speed of a multiport MAC and the PHYs connected to it Parameter pmac A pointer to the base of the MAC control interface common speed The speed to set Return SE PHY SPEED 1000 if the PHYs common speed is 1000 Mbps SE PHY SPEED 100 if the PHYs common speed is 100 Mbps SE PHY SPEED 10 if the PHYs common speed is 10 Mbps SE PHY SPEED NO COMMON if there isn t a common speed among the PHYs The current speed of the MAC and PHYs is not changed See also alt 32 alt tse mac get common speed alt tse phy add profile Prototype alt tse phy add profile alt tse phy profile phy Thread safe No Available from No ISR Include altera avalon tse h Description The ait tse phy add profile function adds a new PHY to the PHY profile Use this function if you want to use PHYs other than Marvell 88E1111 Marvell Quad PHY 88E1145 National DP83865 and National DP83848C Parameter phy A pointer to the PHY structure Return ALTERA TSE MALLOC FAILED ifthe operation is not successful Otherwise the index of the newly added PHY is returned alt tse system add sys Altera Corporation Software Programming Interface C Send Feedback UG 01008 2015 06 15 triple speed ethernet init 11 7
137. data enable signal gm tx enis asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on gm tx d 7 0 bus Between frames gm tx en remains deasserted If a frame is received on the Avalon ST interface with an error asserted with tx eop the frame is subsequently transmitted with the GMII gm tx err error signal at any time during the frame transfer GMII Receive On receive all signals are sampled on the rising edge of xx cix The GMII data enable signal gm xx v is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on the gm xx 7 0 bus Between frames gm rx v remains deasserted If the PHY detects an error on the frame received from the line the PHY asserts the GMII error signal gm rx err for at least one clock cycle at any time during the frame transfer A frame received on the GMII interface with a PHY error indication is subsequently transferred on the Avalon ST interface with the error signal rx_err 0 asserted RGMII Transmit On transmit all data transfers are synchronous to both edges of cx cix The RGMII control signal tx control is asserted to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on the xgmii out 3 0 bus Between frames tx controlremains deasserted Figure 7 16 RGMII Transmit in 10 100 Mbps
138. detects an error on the frame received from the line the PHY asserts the MII error signal m rx err for at least one clock cycle at any time during the frame transfer A frame received on the MII interface with a PHY error indication is subsequently transferred on the FIFO interface with the error signal xx err 0 asserted IEEE 1588v2 Timestamp The following timing diagrams show the timestamp of frames observed on TX path for the IEEE 1588v2 feature Figure below shows the TX timestamp signals for the IEEE 1588v2 feature in a 1 step operation In a I step operation a TX egress timestamp is inserted into timestamp field of the PTP frame in the MAC You need to drive the 1 step related signal appropriately so that the timestamp can be inserted into the correct location of the packet The input signals related to the 2 step operation are not important and can be driven low or ignored Interface Signals Altera Corporation LJ Send Feedback 7 48 IEEE 1588v2 Timestamp UG 01008 2015 06 15 Figure 7 22 Egress Timestamp Insert for IEEE 1588v2 PTP Packet Encapsulated in IEEE 802 3 Egress Timestamp Insert IEEE 1588v2 PTP Packet 2 step Timestamp Request Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data N 0 2 step Timestamp Return Output tx_egress_timestamp_96b_valid tx_egress_timestamp_96b_fingerprint N 0 tx_egress_timestamp_96b_data 95 0 tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_fingerprin
139. e Interface Signals C Send Feedback Altera Corporation Design Considerations 2015 06 15 UG 01008 GX subscribe send Feedback Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA The following factors determine the total number of global and regional clock resources required by your system e Configuration of the Triple Speed Ethernet MegaCore function and the blocks it contains e PCS operating mode SGMII or 1000BASE X e PMA technology implemented in the target device Number of clocks that can share a single source Number of PMAs required in the design ALTGX megafunction operating mode You can use the same clock source to drive clocks that are visible at the top level design thus reducing the total number of clock sources required by the entire design Table 8 1 Clock Signals Visible at Top Level Design Clock and reset signals that are visible at the top level design for each possible configuration Configurations Clocks eer eee MAC Only MAC and PCS MAC and PCS with PMA Yes rx_recovclkout ref clk Yes clk Yes Yes Yes ee dps eik Yes Yes Yes ff_rx_clk Yes Yes Yes tx_clk Yes No No rx_clk Yes No No woa iz gll Yes No tbi_tx_clk Yes No gxb cal blk clk 2 Yes 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are t
140. e MegaCore function e Register access e MDIO access e Frame transmission and error handling e Frame reception and error handling e Ethernet frame MAC address filtering e Flow control e Retransmission in half duplex Altera has also validated the Triple Speed Ethernet MegaCore function in both optical and copper platforms using the following development kits e Altera Nios II Development Kit Cyclone II Edition 2C35 e Altera Stratix III FPGA Development Kit e Altera Stratix IV FPGA Development Kit Quad 10 100 1000 Marvell PHY e MorethanIP 10 100 and 10 100 1000 Ethernet PHY Daughtercards Optical Platform In the optical platform the 10 100 1000 Mbps Ethernet MAC 1000BASE X SGMII PCS and PMA functions are instantiated The FPGA application implements the Ethernet MAC the 1000BASE X PCS and an internal system using Ethernet connectivity This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields thus implementing a loopback A direct connection to an optical module is provided through an external SFP optical module Certified 1 25 GBaud optical SFP transceivers are Finisar 1000BASE SX FTLF8519P2BNL Finisar 1000BASE LX FTRJ 1319 3 and Avago Technologies AFBR 5710Z Copper Platform In the copper platform Altera tested the Triple Speed Ethernet MegaCore function with an external 1000BASE T PHY devices The MegaCore function is connected t
141. e 11 6 alt tse phy add profile aciaueco dai eod USA RAN M VIR EEG CA M EU EUER RUM 11 6 WCG AC AA 65 P MO 11 6 triple speed ethernet init rere neret er eei e ie Reb Pe e ce este 11 7 tse mac close aceon eerste eaea E a E rta ELM een IN DU EU 11 8 tse mac raw send eene etae dri terret oit dte te e ne oi ere re ree eee tes 11 9 tse mae SetG MIT mode eerte terna epe dvsdasvee v suacach eV erbe ve bae Pra eene uin 11 9 tse mac setMIImode eese eene teen nennen netten tee tntnne tete tse testes tne te ene se ne 11 10 tse mac SwReSet ie idu devi tete endet tite deret ve iae ote ie HG 11 10 Constants 3iiiin ire ORUWRRRWH I RIVE RR En NOR EHE ERREUR 11 10 Ethernet Frame EOFPIIAL co eter oiu leva ven EVE y vU Udo ovx d Noe V BeYE QU SU e RO tad GYx CXV Cx N UE NU HEN A 1 Basic Frame Format iie dn ERE E E E ERU WT RRR A 1 VLAN and Stacked VLAN Frame Format ccccccccsccscsssssssscsssesssscsssssssscsscesssscsessssseccesessssssesesssasseseesees A 2 Pause Frame Fottm t aedes ee e E A E T E ue EEE aE iatis A 3 Pause Frame Generations vsscsesccsscosdcccssscdeddsssevasscssdecdesdsencoviesancscivcnveecsvbassasoaisseveeliedesavioiacesascieeisees A 4 Simulation Parameter s eessseseseesseseesccoeecooecososoosssoossssssssesssesssessseessesseseeeseeeoe B 1 Functionality Configuration Paratielelsespeas e iderendn ira een db uri e pi rA Bex inen eR E e Kan B 1 Test Configuration Patar
142. e Speed Ethernet MegaCore function created in Quartus II ACDS 13 0 the simulation model will be generated using the industrial standard IEEE simulation encryption Table 10 2 lists the scripts available for you to compile the simulation model files in a standalone flow Table 10 2 Simulation Model Files variation name sim mentor Contains a ModelSim script msim setup tcl to set up and run a simulation variation name sim synopsys vcs Contains a shell script vcs setup sh to set up and run a vcs simulation lt variation_name gt _sim synopsys vcsmx Contains a shell script vesmx_setup sh and synopsys_sim setup to set up and run a VCS MX simulation variation name sim mentor cadence Contains a shell script ncsim setup sh and other setup files to set up and run an NCSIM simulation Testbench LJ Send Feedback Altera Corporation Software Programming Interface 2015 06 15 UG 01008 GX subscribe C Send Feedback Driver Architecture Figure 11 1 Triple Speed Ethernet Software Driver Architecture Avalon MM Interface TSE MAC gt gt TXSGDMA pe Control Interface ue Nios II CPU E es j dE Descriptor Memory 1 TXEIFO 2 E S MII GMII TX Path ms gt TX Descriptor Client Interniche TSE Driver Apps Descriptors
143. e maximum frame length register frm_length is configured to 1518 For a single channel MAC with internal FIFO buffers the transmit FIFO buffer is set to start data transmission as soon as its level reaches tx section fu11 The receive FIFO buffer is set to begin forwarding Ethernet frames to the Avalon ST receive interface when its level reaches rx section full e Default setting for the PCS function The if mode register is set to 0x0000 Auto negotiation between the local PHY and remote link PHY is bypassed Test Flow The testbench performs the following operations upon a simulated power on reset Testbench Altera Corporation LJ Send Feedback UG 01008 2015 06 15 10 4 Simulation Model Initializes the DUT registers e Starts transmission For a single channel MAC with internal FIFO buffers clears the FIFOs e Ends transmission and checks the following elements to determine that the simulation is successful e No Ethernet protocol errors detected e Ethernet frames generated and transmitted are received by the frame monitor Simulation Model This section describes the step by step instructions for generating the simulation model and simulating your design using the ModelSim simulator or other simulators Generate the Simulation Model The generated design example includes both Verilog HDL and VHDL testbench files for the device under test DUT your custom MegaCore function variation To generate a Verilog functio
144. e section on Timing Constraint to a new chapter Added information about how to customize the SDC file in Chapter 8 Added Pause Frame Generation section November 2011 Added support for Arria V Revised the Device Family Support section in Chapter 1 Added disable_read_timeout and read_timeout registers at address 0x15 and 0x16 June 2011 11 0 Updated support for Cyclone IV GX Cyclone III LS Aria II GZ HardCopy IV GX E and HardCopy III E devices Revised Performance and Resource Utilization section in Chapter 1 Updated Chapter 3 to include Qsys System Integration Tool Design Flow Added Transmit and Receive Latencies section in Chapter 4 Updated all MAC register address to dbyte addressing December 2010 Altera Corporation Added support for Arria II GZ Added a new parameter Starting Channel Number Streamlined the contents and document organization Additional Information C Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet IP Core Document Revision History F 7 ELENCO E CK NN August2010 10 0 e Added support for Stratix V e Revised the nomenclature of device support types e Added chapter 5 Design Considerations Moved the Clock Distribution section to this chapter and renamed it to Optimizing Clock Resources in Multiport MAC and PCS with Embedded PMA Added sections on PLL Sharing and Transceiver Quad Sharing e Updated the description of Enable transceiv
145. ead operations The PHY device presents its register contents in the data phase and drives the bus from the 2 bit of the turnaround phase Data 16 bit data written to or read from the PHY device Idle Between frames the MDIO data signal is tri stated Connecting MAC to External PHYs The MAC function implements a flexible network interface MII for 10 100 Mbps interfaces RGMII or GMII for 1000 Mbps interfaces that you can use in multiple applications This section provides the guidelines for implementing the following network applications e Gigabit Ethernet operation e Programmable 10 100 Ethernet operation e Programmable 10 100 1000 Ethernet operation Gigabit Ethernet You can connect gigabit Ethernet PHYs to the MAC function via GMII or RGMII On the receive path connect the 125 MHz clock provided by the PHY device to the MAC clock x cix On transmit drive a 125 MHz clock to the PHY GMII or RGMII Connect a 125 MHz clock source to the MAC transmit clock tx_clk Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Programmable 10 100 Ethernet 4 25 A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC The clock driver can be a PLL a delay line or a DDR flip flop Figure 4 10 Gigabit PHY to MAC via GMII Reference Clock 125MHz Y ck in xtali Gigabit PHY gtx ck txd 7 0 tx en tx eir rx
146. ed The read timeout register is then set to 1 to indicate that the statistics registers were not cleared PHY Management MDIO This module implements the standard MDIO specification IEEE 803 2 standard Clause 22 to access the PHY device management registers and supports up to 32 PHY devices To access each PHY device write the PHY address to the MDIO register mdio_addr0 1 followed by the transaction data MDIO Space 0 1 For faster access the MAC function allows up to two PHY devices to be mapped in its register space at any one time Subsequent transactions to the same PHYs do not require Functional Description C Send Feedback Altera Corporation UG 01008 2015 06 15 MDIO Connection 4 23 writing the PHY addresses to the register space thus reducing the transaction overhead You can access the MDIO registers via the Avalon MM interface For more information about the registers of a PHY device refer to the specification provided with the device For more information about the MDIO registers refer to MAC Configuration Register Space on page 6 l MDIO Connection Figure 4 9 MDIO Interface PHY Management Registers MDIO Frame Generation amp Decoding PHY Management Registers MDIO Frame Generation amp Decoding 4 mdc MDIO Frame Format mdio in imdio out
147. ed You can use this parameter to test FIFO overflow and flow control Simulation Parameters C Send Feedback Altera Corporation B 4 Test Configuration Parameters UG 01008 2015 06 15 A ON D TB HOLDREAD Specifies the number of clock cycles before the Avalon ST monitor 1000 stops reading from the receive FIFO B TX FF ERR 0 Normal behavior 0 1 Drives the Avalon ST error signal high to simulate erroneous frames transmission B TRIGGERXOFF Specifies the number of clock cycles from the start of simulation 0 before the xo gen signal is driven B TRIGGERXON Specifies the number of clock cycles from the start of simulation 0 before the xon gen signal is driven high RX COL FRM Specifies which frame is received with collision Valid in fast Ethernet 0 and half duplex mode only RX COL GEN Specifies which nibble within the frame collision occurs 0 TX COL FR Specifies which frame is transmitted with a collision Valid in fast 0 Ethernet and half duplex mode only X COL GEN Specifies which nibble within the frame collision occurs on the 0 transmit path mx Oon ING Specifies the number of consecutive collisions during retransmission 0 TX_COL_DELAY Specifies the delay in nibbles between collision and retransmission 0 B_PAUSECONTROL 0 GMII frame generator does not respond to pause frames 1 1 Enables flow control in the GMII fra
148. ed Ethernet with IEEE 1588v2 Design Example Components UG 01008 2015 06 15 Triple Speed Ethernet with IEEE 1588v2 Design Example Components Figure 5 1 Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Block Diagram Altera Corporation Altera FPGA Client Application Configuration Status amp Statistics 32 Bit Avalon MM Client Application Avalon MM Master Translator Transceiver Reconfiguration Bundle Pulse Per 64 Bit Timestamp amp Second Avalon ST Fingerprint Design Example uS Second Module Time of Day Time of Ethernet Day Packet Clock Classifier Time 64 Bit of Day Avalon ST 32 Bit Avalon MM Triple Speed Ethernet Reconfiguration Serial Signal External PHY Triple Speed Ethernet with IEEE 1588v2 Design Example C Send Feedback UG 01008 2015 06 15 Base Addresses 5 3 The Triple Speed Ethernet with IEEE 1588v2 design example comprises the following components e Triple Speed Ethernet design that has the following parameter settings e 10 100 1000 Mbps Ethernet MAC with 1000BASE X SGMII PCS e SGMII bridge enabled e Used GXB transceiver block e Number of port 1 e Timestamping enabled e PTP I step clock enabled e Timestamp fingerprint width 4 e Internal FIFO not used e Transceiver Reconfiguration Controller dynamically calibrates and reconfigures the features of the PHY IP cores e Ethernet Packet
149. egaCore function by specifying parameters using the Triple Speed Ethernet parameter editor launched from Qsys in the Quartus II software The customization enables specific core features during synthesis and generation This chapter describes the parameters and how they affect the behavior of the MegaCore function Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface Core Configuration Table 3 1 Core Configuration Parameters ne CKENGN NE 7 CON Core Variation 10 100 1000 Mb Ethernet MAC 10 100 1000 Mb Ethernet MAC with 1000BASE X SGMII PCS 1000BASE X SGMII PCS only 1000 Mb Small MAC 10 100 Mb Small MAC Determines the primary blocks to include in the variation Enable ECC On Off protection Turn on this option to enable ECC protection for internal memory blocks 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any ISO 9001 200
150. egisters 16 SECTION FULL Dword Offset 0x00 0x17 on page 6 3 RX FIFO Sets the xx section empty register See Base Configuration 0 SECTION EMPTY Registers Dword Offset 0x00 0x17 on page 6 3 RX_FIFO_ Sets the xx section full register See Base Configuration Registers 16 SECTION FULL Dword Offset 0x00 0x17 on page 6 3 MCAST_TABLEN Specifies the first n addresses from MCAST_ADDRESSLIST from which 9 multicast address is selected MCAST ADDRESS Alistof multicast addresses 0x887654332 LIST 211 0x886644352 611 OxABCDEFO 12313 0x92456545 ABI15 0x432680010 217 OxADB5892 15439 OxFFEACFE 3434B OxFFCCDD AA3123 OxADB3584 15439 Supported in configurations that contain the 1000BASE X SGMII PCS TB SGMII ENA Sets the scM11 ENA bit in the i mode register See If Mode Register 0 Word Offset 0x14 on page 6 26 Altera Corporation Simulation Parameters C Send Feedback UG 01008 2015 06 15 Test Configuration Parameters B 3 A IO E75 Sets the usE cMrr aN bit in the i mode register See If Mode Register Word Offset 0x14 on page 6 26 TB SGMII AUTO CONF Test Configuration Parameters You can use these parameters to create custom test scenarios Table B 2 Test Configuration Parameters A ONE 75M Supported in configurations that contain the 10 100 1000 Ethernet MAC B RXFRAMES Enables local loopback on the Ethernet side GMII MII
151. eiver block For designs targeting devices other than Stratix V you can export the power down signals to implement your own power down logic to efficiently use the transceivers within a particular transceiver quad Turn on the Export transceiver powerdown signal parameter to export the signals Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 1000BASE X SGMII PCS Reset 4 39 Figure 4 23 Power Down with Export Transceiver Power Down Signal 1000BASE X Pcs PG pwrdn oup POWERDOWN CONTROL PMA gxb pwrdn in 1000BASE X SGMII PCS Reset A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only resets the PCS state machines comma detection function and 8B10B encoder and decoder To trigger a hardware reset on the PCS assert the respective reset signals reset reg clk reset tx clk and reset rx clk To trigger a software reset set the RESET bit in the cont rol register to 1 In PCS variations with embedded PMA assert the respective reset signals or the power down signal to trigger a hardware reset You must assert the reset signal subsequent to asserting the reset_rx_clk reset tx clk Orgbx pwrdn in signal The reset sequence is also initiated when the active low rx freglocked signal goes low Figure 4 24 Reset Distribution in PCS with Embedded PMA reset gbx_pwrdn_in reset_rx_clk reset
152. eld with x31 in the least significant bit of the first byte The CRC bits are thus transmitted in the following order x31 x30 x1 x0 Interpacket Gap Insertion In full duplex mode the MAC function maintains the minimum number of IPG configured in the tx_ipg_length register between transmissions You can configure the minimum IPG to any value Functional Description Altera Corporation LJ Send Feedback UG 01008 4 6 Collision Detection in Half Duplex Mode 2015 06 15 between 64 and 216 bit times where 64 bit times is the time it takes to transmit 64 bits of raw data on the medium In half duplex mode the MAC function constantly monitors the line Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied In accordance with the standard the MAC function begins to measure the IPG when the m xx ccs signal is deasserted Collision Detection in Half Duplex Mode Collision occurs only in a half duplex network It occurs when two or more nodes transmit concurrently The PHY device asserts the m xx co1 signal to indicate collision When the MAC function detects collision during transmission it stops the transmission and sends a 32 bit jam pattern instead A jam pattern is a fixed pattern 0x6485324A6 and is not compared to the CRC of the frame The probability of a jam pattern to be identical to the CRC is very low 0 53296 If the MAC function detects coll
153. eleb usen edades ep E CORR MAG IME GU AR RU CU RLR Up Taf ER UNA B 3 Time of Day ToD ClO c C 1 ToD Clock Featutes 2 ient intr erret eit ite i ete ive p Us C 1 ToD Glock Device Family Suppott uistaen eic eiiis qr ku i nose sted dover epu ven perte ba an C 1 ToD Clock Performance and Resource Utilization eene C 1 Altera Corporation TOC 6 ToD Clock Parameter Setting D C 2 TODD COC Interface ruri T C 3 ToD Clock Avalon MM Control Interface Signals enne ertet esatto ente ater C 3 ToD Clock Avalon ST Transmit Interface Sigmals sissasssessoccssssnssossassasnnsssosssctocnssnansssssnsspsaen C 4 ToD Clock Configuration Register Space ores qucreeteeir etin ninos tela bates con Pedes ior otc ua C 5 Using ToD Clock SecondsH SecondsL and NanoSec Registers sss C 6 Adjusting ToD Clock DEHL as ee na e PH DIRE RERO an NI EHE EIER dE C 6 ToD arret Dp CP UN D 1 ToD Synchronizer BLO Ce M M D 2 ToD Synchronizer Parameter BettInps ise eso tb a M eg d pes Dd lanus EM MEE D 3 EbE S hiinias uiri RN D 4 ToD Synchronizer Common Clock and Reset Signals to tates enne ere tron bp ns D 4 ToD Synchronizer Interface Sig 1a eue usate ito quen utr bc UR vardbaseenestaueataiaatiategens D 5 De gx oci e Y E 1 Packer Classifier ol PN E 1 Packet C
154. ement a shared interface that you connect to a 10 100 Mbps MAC via MII RGMII or to a gigabit MAC via GMII RGMII On the receive path connect the clock provided by the PHY device 2 5 MHz 25 MHz or 125 MHz to the MAC clock xx cik The PHY interface is connected to both the MII active PHY signals and GMII of the MAC function On the transmit path standard programmable PHY devices operating in 10 100 mode generate a 2 5 MHz 10 Mbps or a 25 MHz 100 Mbps clock In gigabit mode the PHY device expects a 125 MHz clock from the MAC function Because the MAC function does not generate a clock output an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices In 10 100 mode the clock generated by the MAC to the PHY can be tri stated During transmission the MAC control signal etn moae selects either MII or GMII The MAC function asserts the eth mode signal when the MAC function operates in gigabit mode which subsequently drives the MAC GMII to the PHY interface The eth moae signal is deasserted when the MAC function operates in 10 100 mode In this mode the MAC MII is driven to the PHY interface Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Programmable 10 100 1000 Ethernet Operation Figure 4 12 10 100 1000 PHY Interface via MII GMII
155. emory Function Size Bits e Registers M20K Blocks MLAB Bits MII GMII 3137 4298 5 2048 Full and half duplex modes 2048x8 3627 4971 10 2048 10 100 supported 1000 Mbps 2048x32 3777 5145 16 2048 Ethernet MII GMII 2048x32 3454 4928 16 768 MAC All MAC options enabled RGMII 2048x32 3466 4933 16 768 All MAC options enabled 12 port 10 35303 48365 60 24576 100 1000 Mbps Ethernet MAC MII GMII 24 port 10 All MAC options enabled 70079 96092 120 49152 100 1000 Mbps Ethernet MAC 1000BASE X 614 786 0 0 1000BASE X 839 1160 0 480 SGMII bridge enabled 1000BASE X 857 1250 0 480 SGMII bridge enabled PMA block LVDS_IO 1000BASE X 2203 1991 5 2208 1000BASE SGMII bridge enabled X SGMII PMA block GXB PCS reconfig controller has been compiled together with 1000BASE X SGMII bridge enabled PMA block GXB Combinational ALUTs 1441 Logic Registers 903 and Memory M20K Block MLAB Bits 4 2048 10 100 All MAC options enabled 2048x32 4306 6132 16 1248 1000 Mbps SGMII bridge enabled Ethernet Default MAC option 0 5062 5318 4 1536 MAC and SGMII bridge enabled 1OOOBASE TEEE 1588v2 feat bled X SGMII v2 feature enable PCS About This MegaCore Function LJ Send Feedback Altera Corporation 1 12 Release Information Release Information UG 01008 2015 06 15 Table 1 6 Triple Speed Ethernet MegaCore Function Release Information EE KNEE ON Version 15 0 Release
156. er defined instance The top level input clocks consist of p11 inclk ext clk and xcvr ref clk e user instance v The user defined instance that instantiates the Triple Speed Ethernet MegaCore function e tse variation A Triple Speed Ethernet MegaCore function variation This example uses a 10 100 1000 Mbps Ethernet MAC with an internal FIFO buffer a 1000BASE X SGMII PCS and an embedded PMA The frequency for the PLL clock input inc1k0 is 100 MHz and the frequency for the PLL clock output c0 is 110 MHz The Triple Speed Ethernet MAC Avalon ST clocks tx clkand rx clk use c0 as the clock source The input clock frequency for the transceiver reference clock xcvr_ref_clk is 125 MHz Example of the Triple Speed Ethernet MegaCore function timing constraint file PLL clock input create clock nam ext clk 50 MHz create clock nam xcvr ref clk Fee OO MME e LI suae pxeseanexel 10 000 Iger ports Ioil ineliki e ext clk persecl 20 000 let porcs Toll ext elik PZ Oe ME create clock nam zevi iSite I Derive PLL gene plesesiye j9JLIL euliexelss Altera Corporation e eue ref Clk period 5000 rated output clocks get ports Timing Constraints C Send Feedback UG 01008 2015 06 15 Recommended Clock Frequency Recommended Clock Frequency 9 3 Table 9 1 Recommended Clock Input Frequency For Each MegaCore Function Variant MegaCore Function Var
157. er during the auto negotiation process Table 6 16 Partner Ability Register Bits Description in SGMII MAC Mode LIBE RENE a NEN NN Reserved 11 10 COPPER_SPEED 1 0 RO Link partner interface speed e 00 copper interface speed is 10 Mbps e 01 copper interface speed is 100 Mbps e 10 copper interface speed is 1 gigabit e 11 reserved 12 COPPER_DUPLEX_ RO Link partner duplex capability prem e 1 copper interface is capable of operating in full duplex mode e 0 copper interface is capable of operating in half duplex mode 15 Reserved Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 SGMII PHY Mode Auto Negotiation 6 25 er NENNEN Acknowledge A value of 1 indicates that the link partner has received 3 consecutive matching ability values from the device 15 COPPER LINK STATUS RO Copper link partner status e 1 copper interface link is up e 0 copper interface link is down SGMII PHY Mode Auto Negotiation When the SGMII mode and the SGMII PHY mode auto negotiation is enabled set the aev ability register before the auto negotiation process so that the link partner can identify the copper speed duplex status and link status When the auto negotiation is complete Triple Speed Ethernet IP core speed and the duplex mode will be resolved based on the value that you set in the dev ability register
158. er dynamic reconfigura tion November 91 e Added support for Cyclone IV Hardcopy III and Hardcopy IV 2009 and updated support for Hardcopy II to full e Updated chapter 1 to include a feature comparison between 10 100 1000 Ethernet MAC and small MAC e Updated chapter 4 to revise the 10 100 1000 Ethernet MAC description Length checking Reset and Control Interface sections March 2009 9 0 e Added support for Arria II GX e Updated chapter 3 to include a new parameter that enables wider statistics counters e Updated chapter 4 to reflect support for different speed in multiport MACs and gated clocks elimination e Updated chapter 6 to reflect enhancements made on the device drivers November 8 1 e Updated Chapters 3 and 4 to add description on dynamic reconfi 2008 guration Updated Chapter 6 to include a procedure to add unsupported PHYs May 2008 8 0 e Revised the performance tables and device support e Updated Chapters 3 and 4 to include information on MAC with multi ports and without internal FIFOs e Revised the clock distribution section in Chapter 4 e Reorganized Chapter 5 to remove redundant information and to include the new testbench architecture e Updated Chapter 6 to include new public APIs October 2007 7 2 e Updated Chapter 1 to reflect new device support e Updated Chapters 3 and 4 to include information on Small MAC May 2007 7 1 e Added Chapters 2 3 5 and 6 e Updated contents to reflect changes and enhancements
159. era Corporation Input Clock for the ToD clock The clock must be in the same clock domain as tx time of day and rx time of day in the MAC function Time of Day ToD Clock C Send Feedback UG 01008 2015 06 15 ToD Clock Configuration Register Space C 5 es 18 E NNNM NN period rst n Input Assert this signal to reset period_c1k to the same clock domain as tx time of day and rx time of day in the MAC function ToD Clock Configuration Register Space Table C 6 ToD Clock Registers Dword R W Description Offset 0x00 SecondsH RW e Bits 0 to 15 High order 16 bit second field 0x0 e Bits 16 to 31 Not used 0x01 SecondsL RW Bits 0 to 32 Low order 32 bit second field 0x0 0x02 NanoSec RW Bits 0 to 32 32 bit nanosecond field 0x0 0x03 Reserved Reserved for future use 0x04 Period RW The period for the frequency adjustment n e Bits 0 to 15 Period in fractional nanosecond PERIOD_ FNS e Bits 16 to 24 Period in nanosecond PERIOD ws e Bits 25 to 31 Not used The default value for the period depends on the fmax of the MAC function For example if fmax 125 MHz the period is 8 ns PER10D Ns 0x0008 and PERIOD_FNS 0x0000 0x05 AdjustPeriod RW The period for the offset adjustment 0x0 e Bits 0 to 15 Period in fractional nanosecond ADJPERIOD_FNS e Bits 16 to 24 Period in nanosecond ADJPERIOD_NS e Bits 25 to 31 Not used 0x06 Adjust
160. eriving the latencies Latency Clock Cycles MAC Configuration Transmit Receive MAC with Internal FIFO Buffers 2 GMII in cut through mode 32 110 MII in cut through mode 41 218 RGMII in gigabit and cut through mode 33 113 RGMII in 10 100 Mbps and cut through mode 42 221 MAC without Internal FIFO Buffers 3 GMII 11 37 MII p 77 RGMII in gigabit mode 12 40 RGMII in10 100 Mbps 23 80 Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 FIFO Buffer Thresholds 4 13 Latency Clock Cycles MAC Configuration Transmit Receive Notes to Table 4 5 1 The clocks in all domains are running at the same frequency 2 The data width is set to 32 bits 3 The data width is set to 8 bits Related Information Base Configuration Registers Dword Offset 0x00 0x17 on page 6 3 FIFO Buffer Thresholds For MAC variations with internal FIFO buffers you can change the operations of the FIFO buffers and manage potential FIFO buffer overflow or underflow by configuring the following thresholds e Almost empty e Almost full e Section empty e Section full These thresholds are defined in bytes for 8 bit wide FIFO buffers and in words for 32 bit wide FIFO buffers The FIFO buffer thresholds are configured via the registers Functional Description Altera Corporation LJ Send Feedback UG 01008 4 14 Receive Thresholds 2015 06 15 Receive Thresholds Figure
161. ernet System with MII GMII or RGMII on page 6 27 Triple Speed Ethernet System with SGMII on page 6 30 Triple Speed Ethernet System with 1000BASE X Interface on page 6 31 Triple Speed Ethernet System with MII GMII or RGMII Configuration Register Space Altera Corporation C Send Feedback UG 01008 6 28 Triple Speed Ethernet System with MII GMII or RGMII 2015 06 15 Figure 6 2 Triple Speed Ethernet System with MII GMII or RGMII with Register Initialization Recommendation MII GMII RGMII Interface 10 100 1000 Mbps MAC External PHY Avalon ST TX Avalon ST RX 4 Copper Fiber PHY Interface hs Register Register Space Avalon MM lt gt MDIO Space 0 MDIO Space 1 Use the following recommended initialization sequences for the example in Figure 6 2 1 External PHY Initialization using MDIO Assume the External PHY Address is 0x0A Altera Corporation mdio_addr0 0x0A External PHY Register will Map to MDIO Space 0 Read write to MDIO space 0 dword offset 0x80 Ox9F Read write to PHY Register 0 to 31 a MAC Configuration Register Initialization Disable MAC Transmit and Receive DatapathDisable the MAC transmit and receive datapath before performing any changes to configuration Set TX_ENA and RX_ENA bit to 0 in Command Config Register Command_config Register 0x00802220 Read the TX_ENA and RX_ENA bit is set 0 to ensure
162. ert this signal to indicate to the PHY device that the frame sent is invalid MII Receive Interface mii rx d 3 0 O MII receive data bus mii_rx_dv O Asserted to indicate that the data on mii_rx_d 3 0 is valid The signal stays asserted during frame reception from the first preamble byte until the last byte of the CRC field is received mii_rx_err O Asserted by the PHY to indicate that the current frame contains errors mii_col Out Collision detection Asserted by the PCS function to indicate that a collision was detected during frame transmission mii crs Out Carrier sense detection Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line SGMII Status Signals The SGMII status signals provide status information to the PCS block When the PCS is instantiated standalone these signals are inputs to the MAC and serve as interface control signals for that block Table 7 41 SGMII Status Signals set_1000 O Gigabit mode enabled In 1000BASE X this signal is always set to 1 In SGMII this signal is set to 1 if one of the following conditions is met the USE_SGMI1_aN bit is set to 1 and a gigabit link is established with the link partner as decoded from the partner_ability register the USE_SGMI1_AN bit is set to 0 and the SGMII_SPEED bit is set to 10 set_100 Interface Signals CJ Send Feedback 100 Mbps mode enabled In 1000BASE X this si
163. es basic VLAN and stacked VLAN jumbo and control frames For more information about these frame formats refer to Ethernet Frame Format on page 12 1 O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01008 4 2 MAC Architecture 2015 06 15 MAC Architecture Figure 4
164. es between 2to10230ctets the length of 512 and 1023 bytes 0x35 etherStatsPkts10 RO The number of received good and errored frames between 24tol5180ctets the length of 1024 and 1518 bytes 0x36 etherStatsPkts15 RO The number of received good and errored frames between 19toXOctets the length of 1519 and the maximum frame length configured in the frm_length register 0x37 etherStatsJabber RO Too long frames with CRC error S 0x38 etherStatsFragme RO Too short frames with CRC error nts 0x39 Reserved Unused Extended Statistics Counters 0x3C Ox3E 0x3C msb aOctetsTransmitt edOK RO 0x3D msb_ aOctetsReceivedO K RO Ox3E msb etherStatsOctets RO Upper 32 bits of the respective statistics counters By default all statistics counters are 32 bits wide These statistics counters can be extended to 64 bits by turning on the Enable 64 bit byte counters parameter To read the counter read the lower 32 bits first then followed by the extended statistic counter bits Transmit and Receive Command Registers Dword Offset 0x3A Ox3B Table 6 5 describes the registers that determine how the MAC function processes transmit and receive frames A software reset does not change the values in these registers Configuration Register Space C Send Feedback Altera Corporation UG 01008 6 14 Transmit and Receive Command Registers Dword Offset 0x3A 0x3B 2015 06 15 Table 6 5 Tra
165. eset is complete Set SW RESET bit to 1 Command config Register 0x00802220 Wait Command config Register 0x00800220 Enable MAC Transmit and Receive Datapath Set TX ENA and RX ENA to 1 in Command Config Register Command config Register 0x00800223 Read the TX ENA and RX ENA bit is set 1 to ensure TX and RX path is enable Wait Command config Register 0x00800223 Configuration Register Space Altera Corporation C Send Feedback UG 01008 6 30 Triple Speed Ethernet System with SGMII 2015 06 15 Triple Speed Ethernet System with SGMII Figure 6 3 Triple Speed Ethernet System with SGMII with Register Initialization Recommendation SGMII Interface 1 25 Gbps 10 100 1000 Mbps MAC 1000BASE X External PHY Avalon ST TX SGMII PCS Avalon ST RX 4 A a gt Copper Fiber PHY Interface MAC Register Register Space PCS Space Avalon MM lt gt MDIO Space 0 Register Space MDIO Space 1 amp Host Slave MDIO Use the following recommended initialization sequences for the example in Figure 6 4 1 External PHY Initialization using MDIO Altera Corporation Refer to step 1 in Triple Speed Ethernet System with MII GMII or RGMII on page 6 27 a PCS Configuration Register Initialization Set Auto Negotiation Link Timer Set Link timer to 1 6ms for SGMII link_timer address offset 0x12 0x0D40 Link_timer address of
166. et MAC with IEEE 1588v2 Design 2015 06 15 Table 5 2 Triple Speed Ethernet MAC with IEEE 1588v2 Design Example Files These files are located in the tse_ieee1588 directory File Name Description tse_1588_top v The top level entity file of the design example for verification in hardware tse_1588_top sdc The Quartus II SDC constraint file for use with the TimeQuest timing analyzer tse_1588 qsys A Qsys file for the Triple Speed Ethernet design example with IEEE 1588v2 option enabled tb_run_simulation tcl Tcl script to run testbench simulation Creating a New Triple Speed Ethernet MAC with IEEE 1588v2 Design You can use the Quartus II software to create a new Triple Speed Ethernet MAC with IEEE 1588v2 design Altera provides a Qsys design example file that you can customize to facilitate the development of your Triple Speed Ethernet MAC with IEEE 1588v2 design 1 Launch the Quartus II software and open the tse_1588 top v file from the project directory 2 Launch Qsys from the Tools menu and open the tse_1588 qsys file By default the design example targets the Stratix V device family To change the target family click on the Project Settings tab and select the desired device from the Device family list 3 Turn off the additional module under the Use column if your design does not require it This action disconnects the module from the Triple Speed Ethernet MAC with IEEE 1588v2 system Double click on triple_speed_ethernet_0 to laun
167. evices The files constraints the false paths and multi cycle paths in the Triple Speed Ethernet Megacore function The timing constraints files are specified in the variation name qip file and is automatically included in the Quartus II project files You may need to add timing constraints that are external to the MegaCore function The following sections describe the procedure to create the timing constraint file Creating Clock Constraints After you generate and integrate the Triple Speed Ethernet MegaCore function into the system you need to create a timing constraints file to specify the clock constraint requirement You can specify the clock requirement in the timing constraint file using the following command create clock For example for a new clock named reg_c1k with a 50 MHz clock targeted to the top level input port clk enter the following command line create clock name reg clk period 50 MHz get ports clk Figure below shows an example of how you can create a timing constraint file to constrain the Triple Speed Ethernet MegaCore function clocks O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holde
168. fset 0x13 0x03 Configure SGMII Enable SGMII Interface and Enable SGMII Auto Negotiation SGMITI_ENA 1 USE SGMII AN 1 if mode 0x0003 Enable Auto Negotiation Enable Auto Negotiation AUTO_NEGOTIATION_ENA 1 Bit 6 8 13 can be ignore PCS Control Register 0x1140 PCS Reset PCS Software reset is recommended where there any configuration changed RESET 1 Configuration Register Space C Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet System with 1000BASE X Interface 6 31 PCS Control Register 0x9140 Wait PCS Control Register RESET bit is clear 3 MAC Configuration Register Initialization Refer to step 2 in Triple Speed Ethernet System with MII GMII or RGMII on page 6 27 Note If 1000BASE X SGMII PCS is initialized set the ETH_SPEED bit 3 and ENA 10 bit 25 in command config register to 0 If half duplex is reported in the PHY PCS status register set the HD ENA bit 10 to 1 in command config register Triple Speed Ethernet System with 1000BASE X Interface Figure 6 4 Triple Speed Ethernet System with 1000BASE X Interface with Register Initialization Recommendation 1000BASE X Interface 1 25 Gbps 1000BASE X Optical Tranceiver SFP 1000BASE X SGMII PCS 10 100 1000 Mbps MAC Avalon ST TX gt Fiber Interface Avalon ST RX MAC Register Space Avalon MM lt gt MDIO Space 0 MDIO Space 1 PCS Registe
169. g conditions e The actual payload length matches the value in the length type or client length type field e Basic frames the payload length is between 46 0x2E and 1536 0x0600 bytes excluding 1536 e VLAN tagged frames the payload length is between 42 0x2A and 1536 0x0600 excluding 1536 e Stacked VLAN tagged frames the payload length is between 38 0x26 and 1536 0x0600 excluding 1536 If the frame or payload length is not valid the MAC function asserts one of the following signals to indicate length error e rx err 1 in MACs with internal FIFO buffers e data rx error 0 in MACs without internal FIFO buffers Frame Writing The MegaCore function removes the preamble and SFD fields from the frame The CRC field and padding bytes may be removed depending on the configuration For MAC variations with internal FIFO buffers the MAC function writes the frame to the internal receive FIFO buffers For MAC variations without internal FIFO buffers it forwards the frame to the Avalon ST receive interface MAC variations without internal FIFO buffers do not support backpressure on the Avalon ST receive interface In this variation if the receiving component is not ready to receive data from the MAC function the frame gets truncated with error and subsequent frames are also dropped with error IP Payload Alignment The network stack makes frequent use of the IP addresses stored in Ethernet frames When you turn on the Alig
170. g fromgxb n 0 Connects to an external dynamic reconfiguration controller The bus identifies the transceiver channel whose settings are being transmitted to the reconfiguration controller Leave this bus disconnected if you are not using an external reconfigura tion controller For more information about the bus width for PMA blocks implemented in each device refer to the Dynamic Reconfigura tion chapter of the respective device handbook reconfig busy Driven from an external dynamic reconfiguration controller This signal will indicate the busy status of the dynamic reconfi guration controller during offset cancellation Tie this signal to 1 b0 if you are not using an external reconfiguration controller This signal is not present in PMA blocks implemented in Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers For more information on the signals refer to the respective sections shown in Table 7 24 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS and 7 27 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA Figure 7 6 10 100 1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with IEEE 1588v2 1000BASE X SGMII PCS and Embedded PMA Signals Clock Signals MAC Transmit Interface Signals MAC Receive Interface Signals MAC Packet Classificat
171. gaCore Function SGMII PCS with PMA PHY Mode Device Ability iiaa Rb Link Partner Abilit 10 100 1000BASE T PHY Device Ability Link Partner Mig Medium Twisted Copper Pai 10 100 1000BASE T PHY Link Partner Device Ability lA Link Partner Abilit If the SGMII_ENA and USE SGMII A bits in the i mode register are 1 the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto negotiation completes If the scmz1_ SGMII S If the SGMII ENA bit is 1 and the us E SGMII AN bit is 0 the PCS function can be configured with the PEED and SGMII DUPLEX bits in the if mode register ENA bitis 1 and the scw1i aw wopz bit is 1 SGMII PHY Mode auto negotiation is enabled the speed and duplex mode resolution will be resolved based on the value that you set in the aev ability register once auto negotiation is done You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner Functional Description LJ Send Feedback Altera Corporation UG 01008 4 36 Ten bit Interface 2015 06 15 Figure 4 18 SGMII Auto Negotiation Activity PHY SGMII PCS Link lt lt Synchronization Acquired C with 0x00 ability Il C with 0x0001 C with dev ability en e s Link Timer S 1
172. gnal is always set to 0 In SGMII this signal is set to 1 if one of the following conditions is met the USE_SGMI1_AN bit is set to 1 and a 100Mbps link is established with the link partner as decoded from the partner_ ability register the USE_SGMII_AN bit is set to 0 and the SGMII_SPEED bit is set to 01 Altera Corporation 7 40 SGMII Status Signals UG 01008 2015 06 15 set 10 O 10 Mbps mode enabled In 1000BASE X this signal is always set to 0 In SGMII this signal is set to 1 if one of the following conditions is met the USE_SGMII_AN bit is set to 1 and a 10Mbps link is established with the link partner as decoded from the partner_ability register the USE_SGMI1_AN bit is set to 0 and the SGMII_SPEED bit is set to 00 hd_ena Half duplex mode enabled In 1000BASE X this signal is always set to 0 In SGMII this signal is set to 1 if one of the following conditions is met the usE scMiri AN bit is set to 1 and a half duplex link is established with the link partner as decoded from the partner_ ability register the USE_SGMI1_AN bit is set to 0 and the SGMII_DUPLEX bit is set tol Table 7 42 References Ten bit interface TBI Interface Signals on page 7 18 Status LED signals Status LED Control Signals on page 7 19 SERDES control signals SERDES Control Signals on page 7 20 Arria 10 Transceiver Native PHY signals Arria 10 Transcei
173. hannel number for the first port Subsequent channel numbers are in four increments In designs with multiple instances of GXB transceiver block multiple instances of Triple Speed Ethernet IP core with GXB transceiver block or a combination of Triple Speed Ethernet IP core and other IP cores Altera recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad This option is not supported in Arria V Cyclone V Stratix V and Arria 10 devices For these devices the channel numbers depends on the dynamic reconfigu ration controller Series V GXB Transceiver Options TX PLLs type e CMU This option is only available for variations that include ATX the PCS block for Stratix V and Arria V GZ devices Specifies the TX phase locked loops PLLs type CMU or ATX in the GXB transceiver for Series V devices Enable SyncE On Off Turn on this option to enable SyncE support by Support separating the TX PLL and RX PLL reference clock TX PLL clock s xl This option is only available for variations that include network xN the PCS block for Arria V and Cyclone V devices Specifies the TX PLL clock network type Arria 10 GXB Transceiver Options Enable Arria 10 On Off Turn on this option for the MegaCore function to transceiver include the dynamic reconfiguration signals dynamic reconfi guration Note You must configure the Arria 10
174. hes the critical level before it overflows The FIFO buffer can be considered overflow if this bit is set to 1 in the middle of a packet transfer The port number the status applies to ioe quelli eui clk The clock that drives the MAC FIFO status interface Table 7 18 References Clock and Reset Signal on page 7 2 Clock and reset signals MAC control interface MAC Control Interface Signals on page 7 3 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 Multiport MAC FIFO Status Signals 7 17 MAC transmit interface MAC Transmit Interface Signals on page 7 7 MAC receive interface MAC Receive Interface Signals on page 7 4 Status signals MAC Status Signals on page 7 4 Pause and magic packet Pause and Magic Packet Signals on page 7 9 signals MII GMII RGMII MII GMIUI RGMII Signals on page 7 10 interface PHY management signals PHY Management Signals on page 7 11 ECC status signals ECC Status Signals on page 7 12 Interface Signals C Send Feedback Altera Corporation 7 18 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS Signals 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS Signals Figure 7 3 10 100 1000 Ethernet MAC Function with Internal FIFO Buffers with 1000BASE X SGMII UG 01008 2015 06 15 PCS Signals 10 100 1000 Ethernet MAC with 1000 Base X PCS SGMII gt ff tx dk reset le sere gt ff_t
175. his signal will only be high for 1 cycle every time a new time of day is successfully synchronized to the slave clock domain tod slave data n 1 ToD Synchronizer CJ Send Feedback Input This signal carries the 64 bit or 96 bit format synchronized time of day that is ready to be loaded into the slave clock domain The width of this signal is determined by the top_ MODE parameter The synchronized time of day will be 1 slave clock period bigger than the master ToD because it takes 1 slave clock cycle to load this data into the slave ToD Altera Corporation Packet Classifier 2015 06 15 UG 01008 GX subscribe Send Feedback The Packet Classifier decodes the packet types of incoming PTP packets and returns the decoded information aligned with SOP to the Triple Speed Ethernet MAC with IEEE 1588v2 feature Packet Classifier Block Figure E 1 Packet Classifier Block Diagram Packet Classifier Avalon STDataln Data Pipeline FIFO Packets Avalon ST DataOut Sink Source Control Signals to Decoding FIFO Request inserter Control Timestamp Field Location Ingress Control FIFO Insert Ingress Control Input Signals Control Output Signals The components e Data Pipeline holds the data frame up to a specified number of cycles The number of cycles is determined by the largest length type field e FIFO Packets holds the
176. iant Recommended Frequency MHz CLK 50 100 TX CIK 125 10 100 1000 Mbps Ethernet MAC with Internal mmm 125 FIFO buffers FF_TX_CLK 100 FF_RX_CLK 100 CLK 50 100 10 100 1000 Mbps Ethernet MAC without Internal CLE lt N gt 125 FIFO buffers RX_CLK lt N gt 125 RX_AFULL_CLK 100 CLK 50 100 FF_TX_CLK 100 FF_RX_CLK 100 10 100 1000 Mbps Ethernet MAC with 1000BASE TB1_TX_CLK 125 X SGMII PCS with Internal FIFO buffers TBI_RX_CLK 125 REF CLK 125 RECONFIG_CLK 37 5 50 GXB CAL BLK CLK 125 CLK 50 100 RX AFULL CLK 100 WE EXC Cuk epe 125 10 100 1000 Mbps Ethernet MAC with 1000BASE Fe eee 125 X SGMII PCS without Internal FIFO buffers ait REF_CLK 125 RECONFIG CLK lt N gt 37 5 50 GXB CAL BLK CLK 125 9 This signal is only applicable to all device family prior to the 28 nm devices which consists of the Stratix V Arria V Arria V GZ and Cyclone V devices Timing Constraints LJ Send Feedback Altera Corporation 9 4 Recommended Clock Frequency UG 01008 2015 06 15 MegaCore Function Variant Recommended Frequency MHz 1000BASE X SGMII PCS only CLK 50 100 REF CLK 125 TBI TX CLK 125 TBI RX CLK 125 Altera Corporation Timing Constraints C Send Feedback Testbench 2015 06 15 UG 01008 GX subscribe Send Feedback You can use the testbench provided with the Triple Spee
177. ink synchronization is acquired and when the transmit and receive encapsulation or de encapsulation state machines are not in the idle or error states The carrier sense state machine drives the nii rx crs and led_crs signals to 1 when it detects an activity The 1ed crs signal can be used as a common visual activity check using a board LED Functional Description Altera Corporation LJ Send Feedback UG 01008 4 32 Collision Detection 2015 06 15 Collision Detection A collision happens when non idle frames are received from the PHY and transmitted to the PHY simultaneously Collisions can be detected only in SGMII and half duplex mode When a collision happens the collision detection state machine drives the mii rx co1and 1ed coi signals to 1 You can use the 1ed co1 signal as a visual check using a board LED Transmit and Receive Latencies Altera uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA e Transmit latency is the time the PCS function takes to transmit the first bit on the PMA PCS interface after the bit was first available on the MAC side interface MII GMII e Receive latency is the time the PCS function takes to present the first bit on the MAC side interface MII GMII after the bit was received on the PMA PCS interface Table 4 11 PCS Transmit and Receive Latency These latencies are derived from a simulation For transceiver latency refer to the transcei
178. ion Signal Type Avalon ST Signals data tx valid n valid Transmit data valid Assert this signal to indicate that the data on the following signals are valid data tx data n data tx sop n data tx eop n and data tx error n data tx data n 7 0 data Transmit data data tx sop nh startofpacket Transmit start of packet Assert this signal when the first byte in the frame is driven on darote datann data_tx_eop_n endofpacket Transmit end of packet Assert this signal when the last byte in the frame the last byte of the FCS field is driven on data_tx_data_n daroie C105 D EE Que Transmit frame error Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid The MAC function then forwards the frame to the GMII with error data tx ready n ready MAC ready When asserted this signal indicates that the MAC function is ready to accept data from the user application Component Specific Signal tx crc fwd n Transmit CRC insertion Assert this active low signal when data tx eop n is asserted for the MAC function to compute the CRC and insert it into the frame Otherwise the user applica tion is expected to provide the CRC Multiport MAC Packet Classification Signals The MAC packet classification interface is an Avalon ST source port which streams out receive packet classifications Table 7 16 MAC Packet Classifi
179. ion Signals MAC FIFO Status Signals MAC Control Interface Signals Transceiver Native PHY Signal Note to Figure 7 6 Multi Port MAC and 1000BASE X SGMII PCS with Embedded PMA reset mac tx dk n mac rx dk n ref ck n data tx data n 7 0 xpn data tx sop n pon data tx eop n data tx error n led an n data tx valid n led cs n data tx ready n led col n tx ec fwdn led char err n tx ff uflow n led link n led panel link n data rx data n 7 0 led disp err n data rx sop n data Ix eop n Xon gen n data rx error n 4 0 xoff gen n magic sleep n n magic wakeup n data rx ready n data rx valid n mdio in pkt dass valid n pkt dass data n 4 0 mdc mdio oen rx_afull_channel CHANNEL_WIDTH 1 0 mdio out rx afull data 1 0 rx afull valid gxb cal blk clk nx afull clk pcs pwrdn out dk gxb pwrdn in n reg addr log2 MAX CHANNELS 7 0 reconfig clk n reg Wr reconfig togxb n reg rd reconfig_fromgxb_n reg_data_in 31 0 rx recovclkout reg data out 31 0 reconfig_busy reg busy tx egress timestamp 96b n tx egress timestamp 64b n cdr ref ck n IX ingress timestamp 96b n IX ingress timestamp 64b n tX egress timestamp request n tx etstamp ins ctrl n tx time of day 96b n tx time of day 64b n IX time of day 96b n IX time of day 64b n pcs phase measure ck pcs eccstatus 1 0 l I qe gt le L Reset Signal 1 25 Gbps Serial Signals St
180. ion Configuration Register Space C Send Feedback Interface Signals 7 2015 06 15 UG 01008 GX subscribe C Send Feedback Interface Signals The following sections describe the Triple Speed Ethernet MegaCore function interface signals e 10 100 1000 Ethernet MAC Signals on page 7 2 e 10 100 1000 Multiport Ethernet MAC Signals on page 7 13 e 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS Signals on page 7 18 e 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS Signals on page 7 22 e 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA Signals on page 7 24 e 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA on page 7 27 e 1000BASE X SGMII PCS Signals on page 7 36 e 1000BASE X SGMII PCS and PMA Signals on page 7 41 Note To view all the interface signal names turn on Show Signals in the Block Diagram tab in the Triple Speed Ethernet parameter editor interface Otherwise only the connection signal names are shown 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semic
181. ion Configuration Register Space C Send Feedback UG 01008 2015 06 15 Register Initialization 6 27 a NENNEN SGMII DUPLE SGMII half duplex mode Setting this bit to 1 enables half duplex for 10 100 Mbps speed This bit is ignored when SGMII_ENA is 0 or USE_SGMII_ an is 1 These bits are only valid if you only enable the SGMII mode and not the auto negotiation mode SGMII AN MODE RW SGMII auto negotiation mode e l enable SGMII PHY mode e 0 enable SGMII MAC mode This bit resets to 0 which defaults to SGMII MAC mode 15 6 Reserved Register Initialization The Triple Speed Ethernet MegaCore function supports various types of interface commonly used by the following Ethernet solutions e MII GMII e RGMII e 10 bit Interface e SGMII e 1000BASE X Management Data Input Output MDIO for external PHY register configuration When using the Triple Speed Ethernet MegaCore function with an external interface you must understand the requirements and initialize the registers Register initialization mainly performed in the following configurations e External PHY Initialization using MDIO Optional e PCS Configuration Register Initialization e MAC Configuration Register Initialization This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences Triple Speed Eth
182. ions this register is RO and the register is set to a fixed value of 16 Variable length section empty threshold of the receive FIFO buffer Use the depth of your FIFO buffer to determine this threshold This threshold is typically set Variable length section full threshold of the receive FIFO buffer Use the depth of your FIFO buffer to UG 01008 2015 06 15 0x09 tx_section_ empty Variable length section empty threshold of the transmit FIFO buffer Use the depth of your FIFO buffer to determine this threshold This threshold is typically set to FIFO Depth 16 Set this threshold to a value below the xx aimost full threshold and above the xx section fullorrx almost empty threshold In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of FIFO Depth 16 Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Dword Offset 0x0A tx section full sal RW RO Base Configuration Registers Dword Offset 0x00 0x17 6 5 Description Variable length section full threshold of the transmit FIFO buffer Use the depth of your FIFO buffer to determine this threshold For cut through mode this threshold is typically set to 16 Set this threshold to a value above the tx_almost_ empty threshold For store and forward mode set this threshold to 0 In 10 100
183. ions and other network interfaces such as LAN91C111 can share the memory space Altera recommends that you use this memory space for only one purpose that is storing unprocessed packets for the Triple Speed Ethernet MegaCore function Each SG DMA descriptor used by the device driver consumes a buffer size of 1536 bytes defined by the constant BIGBUFSIZE in the memory space To achieve reasonable performance and to avoid memory exhaustion add a new constant named NuMBIGBUFS to your application and set its value using the following guideline NUMBIGBUFS current value number of SG DMA descriptors gt By default the constant NUMBIGBUFS is set to 30 in ipport h If you changed the default value in the previous release of the MegaCore function to optimize performance and resource usage use the modified value to compute the new value of NUMBIGBUFS Using Jumbo Frames To use jumbo frames set the frm_length register to 9600 and edit the files and definitions Altera Corporation Software Programming Interface GJ Send Feedback UG 01008 2015 06 15 API Functions 11 5 Table 11 2 Jumbo Frames Definitions m ON ip altera ethernet altera_eth_tse src define ALTERA_TSE_PKT_INIT_LEN 8206 software lib UCOSII inc iniche altera_ eth_tse_iniche h define ALTERA TSE MAX MTU SIZE 8192 define ALTERA TSE MIN MTU SIZE 14 ip altera ethernet altera_eth_tse src define ALTERA TSE MAC M
184. ired MDC clock frequency is 2 5 MHz a host clock divisor of 40 should be specified Altera recommends that the division factor is defined such that the MDC frequency does not exceed 2 5 MHz FIFO Options The FIFO options are enabled only for MAC variations that include internal FIFO buffers Table 3 3 FIFO Options Parameters Width Width 8 Bits and 32 Bits Determines the data width in bits of the transmit and receive FIFO buffers Depth Transmit umm Between 64 and 64K Determines the depth of the internal FIFO buffers eceive Altera Corporation Parameter Settings C Send Feedback UG 01008 2015 06 15 Timestamp Options Table 3 4 Timestamp Options Parameters Timestamp Options 3 5 Timestamp Enable timestamping On Off Turn on this parameter to enable time stamping on the transmitted and received frames Enable PTP 1 step On Off Turn on this parameter to insert timestamp on PTP clock messages for 1 step clock based on the TX Timestamp Insert Control interface This parameter is disabled if you do not turn on Enable timestamping Timestamp Use this parameter to set the width in bits for the fingerprint width timestamp fingerprint on the TX path The default value is 4 bits PCS Transceiver Options The PCS Transceiver options are enabled only if your core variation includes the PCS function Table 3 5 PCS Transceiver Options Parameters PCS Options PHY
185. ision while transmitting the preamble or SFD field it sends the jam pattern only after transmitting the SFD field which subsequently results in a minimum of 96 bit fragment If the MAC function detects collision while transmitting the first 64 bytes including the preamble and SFD fields the MAC function waits for an interval equal to the backoff period and then retransmits the frame The frame is stored in a 64 byte retransmit buffer The backoff period is generated from a pseudo random process truncated binary exponential backoff Figure 4 3 Frame Retransmission MAC Transmit LFSR Backoff gt Period Col PHY Control Retransmission Block x Retransmit Rd en MAC Transmit Buffer bs Control Control WAddr RAddr 64x8 L Retransmit Frame gt Buffer Discard 4 MAC Transmit Avalon ST j Datapath PHY Interface Interface Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 MAC Receive Datapath 4 7 The backoff time is a multiple of slot times One slot is equal to a 512 bit times period The number of the delay slot times before the Nth retransmission attempt is chosen as a uniformly distributed random integer in the following range 0 lt r lt 2k k min n N where n is the number of retransmissions and N 10 For example after the firs
186. ity and security due to the sharing of an Ethernet link by many service providers MAC frames can be tagged with two consecutive VLAN tags stacked VLAN Stacked VLAN frames contain an additional 8 byte field between the source address and client length type fields as illustrated Altera Corporation Ethernet Frame Format C Send Feedback UG 01008 2015 06 15 Pause Frame Format A 3 Figure A 3 Stacked VLAN Tagged MAC Frame Format Frame length 4 Stacked VLANs 7 octets PREAMBLE 1 octet SFD 6 octets DESTINATION ADDRESS 6 octets SOURCE ADDRESS 2 octets LENGTH TYPE VLAN Tag 0x8100 2 octets VLAN info 2 octets LENGTH TYPE VLAN Tag 0x8100 2 octets VLAN info 2 octets CLIENT LENGTH TYPE 0 1500 9600 octets PAY LOAD DATA 0 38 octets PAD 4 octets FRAME CHECK SEQUENCE EXTENSION half duplex only Pause Frame Format A pause frame is generated by the receiving device to indicate congestion to the emitting device If flow control is supported the emitting device should stop sending data upon receiving pause frames The length type field has a fixed value of 0x8808 followed by a 2 octet opcode field of 0x0001 A 2 octet pause quanta is defined in the second and third bytes of the frame payload P1 and P2 The pause quanta P1 is the most significant byte A pause frame has no payload length field and is always padded with 42 bytes of 0x00 Figure A 4 Pau
187. ixed data width of 8 bits in MAC variations without internal FIFO buffers configurable data width 8 or 32 bits in MAC variations with internal FIFO buffers e Backpressure is supported only in MAC variations with internal FIFO buffers Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds e Packet support using SOP and EOP signals and partial final packet signals e Error reporting e Ready latency is zero in MAC variations without internal FIFO buffers In MAC variations with internal FIFO buffers the ready latency is two e Media independent interfaces on the network side select MII GMII or RGMII by setting the Interface option on the Core Configuration page or the ETH_SPEED bit in the command_config register e Control interface an Avalon MM slave port that provides access to 256 32 bit configuration and status registers and statistics counters This interface supports the use of wait request to stall the interconnect fabric for as many cycles as required e PHY management interface implements the standard MDIO specification IEEE 803 2 standard Clause 22 to access the PHY device management registers This interface supports up to 32 PHY devices MAC variations without internal FIFO buffers implement the following additional interfaces e FIFO status interface an Avalon ST sink port that streams in the fill level of an external FIFO buffer Only MAC variations without i
188. j Fy j Interface Signals Altera Corporation LJ Send Feedback UG 01008 7 44 Avalon ST Transmit Interface 2015 06 15 Figure 7 13 Invalid Length Error During Receive Operation MAC Without Internal FIFO Buffers mcn deo PSL LI data m data 0 7 0 00 o3 Wo Yos Yos Yos Yor Yos Yos Yoo Yos Yos Yos Yoo data m sop f dip ae data mx ready 0 N data n error 040 Woo 01 datanvaido WW f Wtasda o oY Wo pkt dass valid 0 fJ W Avalon ST Transmit Interface Figure 7 14 Transmit Operation MAC With Internal FIFO Buffers com LJ LJ LI Wt LI LI LI ff_tx_data 31 0 00000001 00000002 00000003 00 30004 00000005 00000006 fft sp M ftx eop ho XE fimy Wo ftw ju ff tx ac fwd j j fh ben UE ff tx septy W tx ff uflow j Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 GMII Transmit 7 45 Figure 7 15 Transmit Operation MAC Without Internal FIFO Buffers mac t dk 0 U 18 L data t data 070 00 A01 f 01 Ao f o jo 04 o5 06 jo fos Jj 09 data sopo data_tx_eop_0 J t data tx ready 0 W b data tx err 0 data tx valid 0 GMII Transmit On transmit all data transfers are synchronous to the rising edge of tx cix The GMII
189. lassifier Siptidls iuioe uvis eti bride aee bd e RAV RR tuer ir out dor Uf be vH qu i ri Na dde E 2 Packet Classifier Common Clock and Reset Sipn lss 22e tectis d ner Fr R RU KR inae E 2 Packet Classifier Avalon ST Interface Signals jciacatsacavescsvencessaveentounsecsanveadvcctsdespranissaesstnendasnemavens E 2 Packet Classifier Ingress Control ode3 6 uostri Lotte AERA EUAR EV UA EN RE Aant E3 Packet Classifier Control Insert Signals seis ccsdicannniiainartiinnaniuiausddeanaudiae E 4 Packet Classifier Timestamp Field Location Sigmals c scsssssssssssasossovesansonssnasdeshoonsssnsesosvsensonenssst E 5 Additional Informatio Miss sisscsscsssisessscsseacenscanddesvessaesoeatestoaieeasbisanbecsanecouesansneas teow F 1 Triple Speed Ethernet IP Core Document Revision History eese F 2 Howto Contact i lc F 8 Altera Corporation About This MegaCore Function 2015 06 15 UG 01008 GX subscribe C Send Feedback About This MegaCore Function The Altera Triple Speed Ethernet MegaCore function is a configurable intellectual property IP core that complies with the IEEE 802 3 standard The IP core was tested and successfully validated by the University of New Hampshire UNH interoperability lab It combines the features of a 10 100 1000 Mbps Ethernet media access controller MAC and 1000BASE X SGMII physical coding sublayer PCS with an optional physical medium attachment PMA Device
190. ld 16 bits correction field for fractional nanosecond Required offset location of timestamp and correction field 1 1588v1 format 32 bits second field 32 bits nanosecond field Required offset location of timestamp Assert this signal in the same clock cycle as the start of packet avalon_st_ tx startofpacket is asserted tx etstamp ins ctrl residence I time update Assert this signal to add residence time egress timestamp ingress timestamp into correction field of PTP frame Required offset location of correction field Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins Ctrl ingress I timestamp 96b 96 96 bit format of ingress timestamp 48 bits second 32 bits nanosecond 16 bits fractional nanosecond Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins ctrl ingress I timestamp 64b 64 64 bit format of ingress timestamp 48 bits nanosecond 16 bits fractional nanosecond Assert this signal in the same clock cycle as the start of packet avalon_st_ tx_startofpacket is asserted Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 IEEE 1588v2 TX Insert Control Timestamp Signals 7 33 a ANN tx etstamp ins ctrl residence time calc format Format of timestamp to
191. low persists 0x2C etherStatsOctets RO The total number of octets received This count includes both good and errored frames This register is the lower 32 bits of etherstatsoctets The upper 32 bits of this statistics counter reside at the dword offset Ox3E Ox2D etherStatsPkts RO The total number of good and errored frames received Ox2E etherStatsUnders RO The number of frames received with length less than 64 izePkts bytes This count does not include errored frames Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Transmit and Receive Command Registers Dword Offset 0x3A Ox3B 6 13 Dword Description Offset Ox2F etherStatsOversi RO The number of frames received that are longer than the value zePkts configured in the frm_length register This count does not include errored frames 0x30 etherStatsPkts64 RO The number of 64 byte frames received This count includes Octets good and errored frames 0x31 etherStatsPkts65 RO The number of received good and errored frames between tol270ctets the length of 65 and 127 bytes 0x32 etherStatsPkts12 RO The number of received good and errored frames between 8to2550ctets the length of 128 and 255 bytes 0x33 etherStatsPkts25 RO The number of received good and errored frames between 6to5110ctets the length of 256 and 511 bytes 0x34 etherStatsPkts51 RO The number of received good and errored fram
192. ls 1 25 Gbps Serial Interface on page 7 25 Status LED signals Status LED Control Signals on page 7 19 SERDES control signals SERDES Control Signals on page 7 20 Transceiver Native PHY signal IEEE 1588v2 RX Timestamp Signals Transceiver Native PHY Signal on page 7 25 IEEE 1588v2 RX Timestamp Signals on page 7 28 IEEE 1588v2 TX Timestamp Signals IEEE 1588v2 TX Timestamp Signals on page 7 29 IEEE 1588v2 TX Timestamp Request Signals IEEE 1588v2 TX Timestamp Request Signals on page 7 31 IEEE 1588v2 TX Insert Control Timestamp Signals IEEE 1588v2 TX Insert Control Timestamp Signals on page 7 31 IEEE 1588v2 ToD Clock Interface Signals IEEE 1588v2 Time of Day ToD Clock Interface Signals on page 7 34 IEEE 1588v2 RX Timestamp Signals Table 7 29 IEEE 1588v2 RX Timestamp Interface Signals m mir E m TEE Carries the ingress timestamp on the receive datapath Consists of 48 bit seconds field 32 bit nanoseconds field and 16 bit fractional nanoseconds field rx ingress timestamp 96b data n The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress timestamp 96b valid Interface Signals G send Feedback Altera Corporation UG 01008 2015 06 15 IEEE 1588v2 TX Timestamp Signals 7 29 Ce NN rx ingress timestamp 96b valid When asserted this signal indicates that zx ingress timestamp
193. ltera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Dev Ability and Partner Ability Registers Word Offset 0x04 0x05 6 23 EINEN HEN NENNEN RN 100BASET2 HALF DUPLEX 10 100BASET2 FULL DUPLEX 11 10MBPS_HALF_ DUPLEX 12 10MBPS FULL DUPLEX 13 100BASE X HALF DUPLEX 14 100BASE X FULL DUPLEX 15 100BASE T4 RO The PCS function does not support 100Base T2 10 Mbps 100BASE X and 100Base T4 operation Always set to 0 Dev Ability and Partner Ability Registers Word Offset 0x04 0x05 The definition of each field in the partner ability registers depends on the mode in which the PCS function operates In this mode the definition of the fields in the dev_ability register are the same as the fields in the partner ability register The contents of these registers are valid only when the auto negotiation AUTO NEGOTIATION COMPLETE bit in the status register 1 completes 1000BASE X Table 6 15 Dev Ability and Partner Ability Registers Bits Description in 1000BASE X A NE CR NN 0 4 Reserved Always set these bits to 0 5 FD Full duplex mode enable A value of 1 indicates support for full duplex 6 HD Half duplex mode enable A value of 1 indicates RW RO 1 2 support for half duplex Pause support PS1 0 ps2 0 Pause is not supported e PS1 0 Ps2 1 Asy
194. ltera recommends that you use the following sampling clock frequencies Altera Corporation 1G master and slave 64 63 125 MHz 10G master and slave 64 63 156 25 MHz 1G master and 10G slave 16 63 125 MHz or 64 315 156 25 MHz 10G master and 1G slave 16 63 125 MHz or 64 315 156 25 MHz ToD Synchronizer C Send Feedback UG 01008 2015 06 15 ToD Synchronizer Parameter Settings D 3 e 10G 312 5 Mhz master and slave 64 63 312 5 MHz e 1G master and 10G 312 5 Mhz slave 32 63 125 MHz or 64 315 312 5 MHz e 10G 156 25 MHz master and 10G 312 5 Mhz slave 64 63 156 25 MHz or 32 63 312 5 MHz Table D 1 Settings to Achieve The Recommended Factors for Stratix V PLL Settings 64 63 16 63 64 315 32 63 64 16 64 32 M Counter N Counter 21 03 21 03 C Counter 03 21 15 21 ToD Synchronizer Parameter Settings The ToD Synchronizer is part of the reference design components in the Quartus II software You can enable this module from the IP Catalog and in Qsys Interface Protocols Ethernet Reference Design Components Table D 2 ToD Synchronizer Configuration Parameters ENCENEN CENE CRX NE TOD MODE Between 0 and 1 Value that defines the time of day format that this block is synchronizing The default value is 1 e 1 96 bits format 32 bits seconds 48 bits nanosecond and 16 bits fractional nanosecond e 0 64 bits format 48 bits nanosecond and 16 bits fractional nanose
195. me generator TB_MDIO_ Enable Disable MDIO simulation 0 SIMULATION Supported in configurations that contain the 1000BASE X SGMII PCS TB SGMII HD 0 Disables half duplex mode 0 1 Enables half duplex mode TB SGMII 1000 0 Disables gigabit operation 1 1 Enables gigabit operation TB SGMII 100 0 Disables 100 Mbps operation 0 1 Enables 100 Mbps operation TB SGMII 10 0 Disables 10 Mbps operation 0 1 Enables 10 Mbps operation Altera Corporation Simulation Parameters C Send Feedback UG 01008 2015 06 15 Test Configuration Parameters B 5 TB TX ERR 0 Disables error generation 0 1 Enables error generation Simulation Parameters Altera Corporation C Send Feedback 2015 06 15 Time of Day ToD Clock UG 01008 CX subscribe GC Send Feedback The Time of Day ToD clock provides a stream of timestamps for the IEEE 1588v2 feature ToD Clock Features e Provides a stream of 64 bit and 96 bit timestamps e The 64 bit timestamp has 48 bit nanosecond field and 16 bit fractional nanosecond field e The 96 bit timestamp has 48 bit second field 32 bit nanosecond field and 16 bit fractional nanosecond field e Runs at 125 MHz for the Triple Speed Ethernet MegaCore function e Supports coarse adjustment and fine adjustments through clean frequency adjustment e Supports period adjustment for frequency control using the Period register e Supports offset adjustment using the AdjustPeriod register
196. med to be word aligned data bytes The total number of bytes in the Ethernet frame including the additional padding bytes as specified by ETHHDR BIAS Return SUCCESS if the current data buffer is successfully transmitted SEND DROPPED if the number of data bytes is less than the Ethernet header size ENP RESOURCE if the SGDMA TX engine is busy tse mac setGMII mode Prototype int tse mac setGMIImode np tse mac pmac Thread safe No Available from No ISR Include triple speed ethernet iniche h Description The tse mac setGM1Imode function sets the MAC function operation mode to Gigabit GMII The settings of the command con ig register are restored at the end of the function Parameter pmac A pointer to the MAC control interface base address Return SUCCESS Software Programming Interface CJ Send Feedback Altera Corporation 11 10 tse mac setMlImode See also tse mac setMIImode tse mac setMIImode Prototype int tse mac setMIImode np tse mac pmac Thread safe No Available from No ISR Include triple speed ethernet iniche h Description The tse mac setMIImode function sets the MAC function operation mode to MII 10 100 The settings of the command con ig register are restored at the end of the function Parameter pmac A pointer to the MAC control interface base address Re
197. mit Interface Signals on page 7 7 MAC receive interface MAC Receive Interface Signals on page 7 4 MAC packet classification signals Multiport MAC Packet Classification Signals on page 7 15 MAC FIFO status signals Multiport MAC FIFO Status Signals on page 7 16 Pause and magic packet signals Pause and Magic Packet Signals on page 7 9 PHY management signals PHY Management Signals on page 7 11 Ten bit interface TBI Interface Signals on page 7 18 Status LED signals Status LED Control Signals on page 7 19 SERDES control signals SERDES Control Signals on page 7 20 Interface Signals Altera Corporation C Send Feedback 7 24 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA UG 01008 2015 06 15 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA Signals Figure 7 5 10 100 1000 Ethernet MAC Function with Internal FIFO Buffers and 1000BASE X SGMII PCS With Embedded PMA Signals 10 100 1000 Ethernet MAC and 1000BASE X SGMII PCS ff tx dk with Embedded PMA MAC Transmit Interface Signals MAC Receive Interface Signals Pause and Magic Packet Signals MAC Control Interface Signals Note to Figure 7 5 PLIST TULL TTT REET TET Ish ff_tx_data DATAWIDTH 1 0 ff tx mod 1 0 ff tx sop ff tx eop ff tx err ff tx wren ff tx ac fwd tx ff uflow ff tx rdy ff tx septy ff tx a full ff tx a empty ff rx dk ff rx rdy ff rx data DATAWIDTH 1 0 ff rx mod 1 0 ff rx sop ff rx eop r
198. mit converter transmits each byte from the PCS function once to the MAC function In 100 Mbps mode the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function In 10 Mbps the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function Auto Negotiation Auto negotiation is an optional function that can be started when link synchronization is acquired during system start up To start auto negotiation automatically set the AUTO NEGOTIATION ENABLE bit in the PCS control register to 1 During auto negotiation the PCS function advertises its device features and exchanges them with a link partner device If the scurr ENA bit in the i mode register is set to 0 the PCS function operates in 1000BASE X Otherwise the operating mode is SGMII The following sections describe the auto negotiation process for each operating mode When simulating your design you can disable auto negotiation to reduce the simulation time If you enable auto negotiation in your design set the 1ink timer time to a smaller value to reduce the auto negotiation link timer in the simulation Related Information PCS Configuration Register Space on page 6 18 1000BASE X Auto Negotiation When link synchronization is acquired the PCS function starts sending a C sequence configuration sequence to the link partner device with the advertised register set to 0x00
199. mmetric pause toward link partner e psi 1 ps2 0 Symmetric pause e PS1 l Ps2 Pause is supported on transmit and receive Reserved Always set these bits to 0 Configuration Register Space C Send Feedback Altera Corporation 6 24 SGMII MAC Mode Auto Negotiation UG 01008 2015 06 15 a NENNEN NN 13 RF2 RW RO 1 2 Remote fault condition e RF1 0 RF2 0 No error link is valid reset condition RF1 0 RF2 1 Offline e RF1 1 RF2 0 Failure condition e RF1 l RF2 l Auto negotiation error 14 ACK RO Acknowledge A value of 1 indicates that the device has received three consecutive matching ability values from its link partner RW RO 1 2 Next page In dev_ability register this bit is always set to 0 Notes to Table 6 15 1 All bits in the dev_ability register have RW access 2 All bits in the partner_ability register are read only SGMII MAC Mode Auto Negotiation When the SGMII mode and the SGMII MAC mode auto negotiation are enabled the Triple Speed Ethernet IP core ignores the value in the aev ability register and automatically sets the value to 16 h4001 as specified in the SGMII specification for SGMII auto negotiation When the auto negotiation is complete the Triple Speed Ethernet IP core speed and the duplex mode will be resolved based on the value in the partner ability register The partner ability register is received from the link partn
200. mode the MAC function receives all frames without address filtering PAD EF RW Padding removal on receive Set this bit to 1 to remove padding from receive frames before the MAC function forwards the frames to the user application This bit has no effect on transmit frames This bit is not available in the small MAC variation CRC FWD RW CRC forwarding on receive e Set this bit to 1 to forward the CRC field to the user application e Set this bit to 0 to remove the CRC field from receive frames before the MAC function forwards the frame to the user application The MAC function ignores this bit when it receives a padded frame and the Pap rw bit is 1 In this case the MAC function checks the CRC field and removes the checksum and padding from the frame before forwarding the frame to the user application PAUSE FWD RW Pause frame forwarding on receive e Set this bit to 1 to forward receive pause frames to the user application e Set this bit to 0 to terminate and discard receive pause frames PAU SE_IGNORE RW Pause frame processing on receive e Set this bit to 1 to ignore receive pause frames e Set this bit to 0 to process receive pause frames The MAC function suspends transmission for an amount of time specified by the pause quanta TX_ADDR_INS RW MAC address on transmit e Set this bit to 1 to overwrite the source MAC address in transmit frame
201. n packet headers to 32 bit boundaries option the MAC function aligns the IP payload on a 32 Functional Description Altera Corporation LJ Send Feedback i UG 01008 4 12 MAC Transmit and Receive Latencies 2015 06 15 bit boundary by adding two bytes to the beginning of Ethernet frames The padding of Ethernet frames are determined by the registers tx_cmd_stat and rx_cmd_stat on transmit and receive respectively Table 4 3 32 Bit Interface Data Structure Non IP Aligned Ethernet Frame 31 24 23 16 15 8 7 0 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Table 4 4 32 Bit Interface Data Structure IP Aligned Ethernet Frame 31 24 23 16 15 8 7 0 padded with zeros MAC Transmit and Receive Latencies Altera uses the following definitions for the transmit and receive latencies e Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network side interface MII GMII RGMII after the bit was first available on the Avalon ST interface e Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon ST interface after the bit was received on the network side interface MII GMII RGMII Table 4 5 Transmit and Receive Nominal Latency The transmit and receive nominal latencies in various modes The FIFO buffer thresholds are set to the typical values specified in this user guide when d
202. nal simulation model use the command prompt and run the quartus sh t generate sim verilog tcl file Alternatively perform the following steps 1 Launch the Quartus II software and browse to the variation name testbench directory 2 Open the generate sim qpf file from the project directory 3 On the Tools menu select Tcl Scripts and select the generate sim verilog tcl file 4 Click Run To generate a VHDL functional simulation model you can use the command prompt and run the quartus sh t generate sim vhdl tcl file Alternatively perform the following steps 1 Launch the Quartus II software and browse to the variation name testbench directory 2 Open the generate sim qpf file from the project directory 3 On the Tools menu select Tcl Scripts and browse to the generate sim vhdl tcl file 4 Click Run Simulate the IP Core You can simulate your IP core variation with the functional simulation model and the testbench or design example generated with your IP core The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts provided with the testbench in Simulation Model Files on page 10 5 Before you begin Generate the simulation model as shown in Generate the Simulation Model on page 10 4 before simulating the test
203. nals e 1000BASE X SGMII PCS Function Signals e 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS Signals e 10 100 1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with IEEE 1588v2 1000BASE X SGMII PCS and Embedded PMA Signals Added IEEE 1588v2 feature PHY path delay interface signals in IEEE 1588v2 PHY Path Delay Interface Signals on page 7 35 Updated the Period and AdjustPeriod register bits in ToD Clock Configuration Register Space on page 14 5 Added two new conditions that the ToD synchronizer module supports in ToD Synchronizer chapter Added three new recommended sampling clock frequencies in ToD Synchronizer chapter Added a new setting of 32 63 in ToD Synchronizer Block on page 15 2 Updated the sync_MopE parameter value and description in ToD Synchronizer Parameter Settings on page 15 3 Altera Corporation UG 01008 F 4 Triple Speed Ethernet IP Core Document Revision History 2015 06 15 ELENCO CORN December 2013 Altera Corporation 13 1 Added support for Arria 10 device Added device family support list for IEEE 1588v2 variant Updated the PCS Transceiver options parameters in PCS Transceiver Options on page 3 5 Updated the bit order in Table F 16 Table F 17 and Table F 19 Added information on how to view all the signal names when implementing the IP in Qsys in Interface Signals Added a section about exposed ports in the new user interface in Design Considerations
204. ndsL and NanoSec Registers on page 14 6 Altera Corporation Additional Information C Send Feedback UG 01008 2015 06 15 Triple Speed Ethernet IP Core Document Revision History F 3 ELENCO E CON June 2014 Additional Information LJ Send Feedback 14 0 Added a link to the Altera website that provides the latest device support information for Altera IP Added a note in PCS Transceiver Options on page 3 5 You must configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250 0 MHz when using the Arria 10 Transceiver Native PHY with the Triple Speed Ethernet IP core Added MAC Error Correction Code on page 4 20 section Added new support configuration for IEEE 1588v2 feature Updated the tx periodand rx period register bits in IEEE 1588v2 Feature Dword Offset 0xD0 0xD6 on page 6 16 Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay on page 6 17 Revised the control interface signal names to reg xd reg data in reg wr reg busy and reg addr in MAC Control Interface Signals on page 7 3 Added ECC status signals in ECC Status Signals on page 7 12 and ECC Status Signals on page 7 21 Added Arria 10 Transceiver Native PHY signals in Arria 10 Transceiver Native PHY Signals on page 7 20 Added Transceiver Native PHY signal in Transceiver Native PHY Signal on page 7 25 Updated the following the signal diagrams e 10 100 1000 Ethernet MAC Sig
205. net PHY ge Ethernet MAC Device usn a gt gt Host Interface MDIO Master Example Applications This section shows example applications of different variations of the Triple Speed Ethernet MegaCore function The 10 100 1000 Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices Figure 1 6 Stand Alone 10 100 1000 Mbps Ethernet MAC Example application using this variation for a copper network Gigabit or Fast Ethernet PHY Device Copper Altera Device Triple Speed Ethernet MegaCore Function z User 2 10 100 1000 Mbps at tL 5 y Application Ethernet MAC LM Hostinterface MDIO Master When configured to include the 1000BASE X SGMII PCS function the MegaCore function can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI Alternatively when the 1000BASE X SGMII PCS function is configured to include an embedded PMA the MegaCore function can connect directly to a gigabit interface converter GBIC small form factor pluggable SFP module or an SGMII PHY About This MegaCore Function LJ Send Feedback Altera Corporation pay sais UG 01008 1 6 MegaCore Verification 2015 06 15 Figure 1 7 10 100 1000 Mbps Ethernet MAC and 1000BASE
206. nfig register is set to 1 The ENA 10 bit has a higher priority than this signal MAC Receive Interface Signals Table 7 5 MAC Receive Interface Signals Avalon ST 1 0 Description Signal Type Avalon ST Signals iie aes Ek In Qsys receive_ clock connect ion clk Receive clock All signals on the Avalon ST receive interface are synchronized on the rising edge of this clock Set this clock to the frequency required to get the desired bandwidth on this interface This clock can be completely independent from rx_c1k Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 MAC Receive Interface Signals 7 5 Avalon ST Description Signal Type ff_rx_dval valid Receive data valid When asserted this signal indicates that the data on the following signals are valid xx data DATAWIDTH 1 0 ff rx sop ff rx eop rx err 5 0 rx ls and rx err stat 17 0 frm type 3 0 ibit ese volente data O DATAWIDTH 1 0 Receive data When DATAWIDTH is 32 the first byte received is _rx_data 31 24 followed by rx data 23 16 and so forth ff rx mod 1 0 empty O Receive data modulo Indicates invalid bytes in the final frame word e ll ff_rx_data 23 0 is not valid e 10 rx data 15 0 is not valid e Ol rx data 7 0 is not valid e 00 rx data 31 0 is valid This signal applies only when DATAWIDTH is set to
207. nfiguration Register Space C Send Feedback Altera Corporation 6 10 UG 01008 Command Config Register Dword Offset 0x02 2015 06 15 Ls RN MAGIC ENA Magic packet detection Set this bit to 1 to enable magic packet detection This bit is not available in the small MAC variation 20 SLEF RW Sleep mode enable When the vac1c rwa bit is 1 set this bit to 1 to put the MAC function to sleep and enable magic packet detection This bit is not available in the small MAC variation 2l WAKI EUP RO Node wake up request Valid only when the macic_zna bit is 1 e The MAC function sets this bit to 1 when a magic packet is detected e The MAC function clears this bit when the stp bit is set to 0 22 XOFF GEN RW Pause frame generation Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer The MAC function sets the pause quanta field in the pause frame to the value configured in the pause quant register 23 CNTL FRM ENA RW MAC control frame enable on receive e Set this bit to 1 to accept control frames other than pause frames opcode 0x0001 and forward them to the user application e Set this bit to 0 to discard control frames other than pause frames 24 NO_LGTH_CHECK RW Payload length check on receive e Set this bit to 0 to check the actual payload length of receive fr
208. nfigure the PCS function to include an embedded physical medium attachment PMA with a a serial transceiver or LVDS I O and soft CDR The PMA interoperates with an external physical medium dependent PMD device which drives the external copper or fiber network The interconnect between Altera and PMD devices can be TBI or 1 25 Gbps serial The PCS function supports the following external PHYs e 1000 BASE X PHYs as is e IOBASE T 100BASE T and 1000BASE T PHYs if the PHYs support SGMII Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 MAC Side MIIGMII 4 Receive MIIGMII Transmit 1000BASE X SGMII PCS Architecture 4 29 1000BASE X SGMII PCS Architecture Figure 4 14 1000BASE X SGMII PCS 1000 BASE X SGMII PCS Ethernet Side 1000 Base X PCS Receive Control SGMI lt gt eceive j i Converte De enrapsiation 8b 10b TBI mA bi Synchronization Decoder 1 AutoNegotiation 1000 Base X PCS Transmit Control E M TBI ransmit gt t j Converter Encapsulation 9b l0b Tarn Encoder e Configuration 3 ae 1 Functional Description CJ Send Feedback Y AvalonMM Interface Altera Corporation 4 30 Transmit Operation Figure 4 15 1000BASE X SGMII PCS with Embedded PMA UG 01008 2015 06 15 Ethernet Side
209. ns_ctrl_residenc egress and ingress timestamps For PTP frames encapsulated using the UDP IPv6 protocol the MAC function performs UDP checksum correction using extended bytes in the PTP frame The MAC function re computes and re inserts CRC 32 into the PTP frames after each timestamp or correction field insertion For 2 step clock synchronization the MAC function returns the timestamp and the associated fingerprint for all transmit frames when the client asserts tx egress timestamp request valid Functional Description C Send Feedback UG 01008 2015 06 15 Table 4 12 Timestamp and Correction Insertion for 1 Step Clock Synchronization IEEE 1588v2 Receive Datapath 4 43 This table summarizes the timestamp and correction field insertions for various PTP messages in different PTP clocks Ordinary Clock Boundary Clock E2E Transparent Clock P2P Transparent Clock PTP Message Insert Insert Insert Insert Insert Insert Insert Correction Time Correction Time Correction Time Correction stamp stamp stamp Sync Yes 1 No Yes 1 No No Yes 2 No Yes 2 Delay Req No No No No No Yes 2 No Yes 2 Pdelay No No No No No Yes 2 No No Req Pdelay No Yes 1 2 No Yes 1 2 No Yes 2 No Yes 1 Resp 2 Delay_ No No No No No No No No Resp Follow No No No No No No No No Up Pdelay No No No No No No No No Resp_ Follow_ Up Announce No No No No No No No No Signaling No No No No No No No No Managem No No No No N
210. nsmit and Receive Command Registers Dword Description Offset Ox3A tx cmd stat Specifies how the MAC function processes transmit frames When you turn on the Align packet headers to 32 bit boundaries option this register resets to 0x00040000 upon a hardware reset Otherwise it resets to 0x00 e Bits 0 to 16 unused e Bit 17 ourT cRC Set this bit to 1 to omit CRC calcula tion and insertion on the transmit path The user applica tion is therefore responsible for providing the correct data and CRC This bit when set to 1 always takes precedence over the f _tx_crc_fwa signal e Bit 18 rx suirT16 Set this bit to 1 if the frames from the user application are aligned on 32 bit boundary For more information refer to IP Payload Re alignment on page 4 5 This setting applies only when you turn on the Align packet headers to 32 bit boundary option and in MAC variations with 32 bit internal FIFO buffers Otherwise reading this bit always return a 0 In MAC variations without internal FIFO buffers this bit is a read only bit and takes the value of the Align packet headers to 32 bit boundary option e Bits 19 to 31 unused Ox3B rx cmd stat RW Specifies how the MAC function processes receive frames When you turn on the Align packet headers to 32 bit boundaries option this register resets to 0x02000000 upon a hardware reset Otherwise it resets to 0x00 e Bits 0 to 24 unused e Bit 25 Rx suirT16 Set this bi
211. nternal FIFO buffers in single port MACs Number of ports 1 4 8 12 16 20 and 24 Specifies the number of Ethernet ports supported by the IP core This parameter is enabled if the parameter Use internal FIFO is turned off A multiport MAC does not support internal FIFO buffers Transceiver type None This option is only available for variations that include LVDSI O the PCS block e GXB e None the PCS block does not include an integrated transceiver module The PCS block implements a ten bit interface TBI to an external SERDES chip e LVDSI O or GXB the MegaCore function includes an integrated transceiver module to implement a 1 25 Gbps transceiver Respective GXB module is included for target devices with GX transceivers For target devices with LVDS I O including Soft CDR such as Stratix III the ALTLVDS module is included Ethernet MAC Options These options are enabled when your variation includes the MAC function In small MACs only the following options are available Altera Corporation Parameter Settings C Send Feedback Ethernet MAC Options 3 3 e Enable MAC 10 100 half duplex support 10 100 Small MAC variations e Align packet headers to 32 bit boundary 10 100 and 1000 Small MAC variations Table 3 2 MAC Options Parameters r 7 KH NN Ethernet MAC Options Enable MAC10 On Off Turn on this option to include support for half duplex 100 half duplex operation on
212. nternal buffers implement this interface e Packet classification interface an Avalon ST source port that streams out receive packet classification information Only MAC variations without internal buffers implement this interface Related Information Transmit Thresholds on page 4 16 e Interface Signals on page 7 1 MAC Configuration Register Space on page 6 1 e Avalon Interface Specifications More information about the Avalon interfaces MAC Transmit Datapath On the transmit path the MAC function accepts frames from a user application and constructs Ethernet frames before forwarding them to the PHY Depending on the MAC configuration the MAC function could perform the following tasks realigns the payload modifies the source address calculates and appends the CRC 32 field and inserts interpacket gap IPG bytes In half duplex mode the MAC Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 IP Payload Re alignment 4 5 function also detects collision and attempts to retransmit frames when a collision occurs The following conditions trigger transmission e In MAC variations with internal FIFO buffers e Cut through mode transmission starts when the level of the FIFO level hits the transmit section full threshold e Store and forward mode transmission starts when a full packet is received e In MAC variations without internal FIFO buffers transmission starts as soon as data is available
213. nto the frame If this signal is set to 1 the user application is expected to provide the CRC Asserted when an underflow occurs on the transmit FIFO buffer Deasserted when the FIFO buffer is filled to or above the section empty threshold defined in the tx_section_empty register User applications can use this signal to indicate when to stop writing to the FIFO buffer and initiate backpressure ibis es e se GUL aL Asserted when the transmit FIFO buffer reaches the almost full threshold Altera Corporation Interface Signals J send Feedback UG 01008 2015 06 15 Pause and Magic Packet Signals 7 9 Avalon ST Signal Description Type Asserted when the transmit FIFO buffer goes below the almost empty threshold ff tx a empty Pause and Magic Packet Signals The pause and magic packet signals are component specific signals Table 7 9 Pause and Magic Packet Signals xon gen I Assert this signal for atleast 1 tx c1k clock cycle to trigger the generation of a pause frame with a 0 pause quanta The MAC function generates the pause frame independent of the status of the receive FIFO buffer This signal is not in use in the following conditions e Ignored when the xon gen bit in the command con ig register is set to 1 e Absent when the Enable full duplex flow control option is turned off xoff gen magic sleep n Assert this signal for at least one tx c1k clock cycle to trigger the
214. o No No No ent Notes to Table 4 12 1 Applicable only when 2 step flag in flagField ofthe PTP frame is 0 2 Applicable when you assert tx ingress timestamp request valid IEEE 1588v2 Receive Datapath In the receive datapath the IEEE 1588v2 feature provides a timestamp for all receive frames The timestamp is aligned with the avalon st rx startofpacket signal IEEE 1588v2 Frame Format The MAC function with the IEEE 1588v2 feature supports PTP frame transfer for the following transport protocols e IEEE 802 3 e UDP IPv4 e UDP IPv6 Functional Description LJ Send Feedback Altera Corporation 4 44 PTP Frame in IEEE 802 3 PTP Frame in IEEE 802 3 Figure 4 27 PTP Frame in IEEE 8002 3 6 Octets Destination Address 6 Octets Source Address 2 Octets Length Type 0x88F7 1 1 Octet transportSpecific messageType 1 Octet reserved versionPTP 2 Octets messageLength 1 Octet domainNumber 1 Octet reserved 2 Octets flagField 8 Octets correctionField 4 Octets reserved 10 Octets SourcePortldentify 2 Octets sequenceld 1 Octet controlField 1 Octet logMessagelnterval 10 Octets TimeStamp 0 1500 9600 Octets Payload 4 Octets CRC Note to Figure 4 27 UG 01008 2015 06 15 MAC Header PTP Header 1 For frames with VLAN or Stacked VLAN tag add 4 or 8 octets offsets before the length type field PTP Frame over UDP IPv4 Checksum
215. o avoid FIFO underflow Almost full tx almost full The number of unwritten entries in the FIFO buffer before the buffer is full When the level of the FIFO buffer reaches this threshold the MAC function asserts the tx full signal The MAC function deasserts the tx rdy signal to backpressure the Avalon ST transmit interface Section empty tx section empty An early indication that the FIFO buffer is getting full When the level of the FIFO buffer reaches this threshold the MAC function deasserts the tx septy signal This threshold can serve as a warning about potential FIFO buffer congestion Section full ie exexonEal oye SCIL This threshold indicates that there are sufficient entries in the FIFO buffer to start frame transmission Set this threshold to 0 to enable store and forward on the transmit path When you enable the store and forward mode the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer Transmit FIFO Buffer Underflow If the transmit FIFO buffer hits the almost empty threshold during transmission and the FIFO buffer does not contain the end of packet indication the MAC function stops reading data from the FIFO buffer and initiates the following actions 1 The MAC function asserts the RGMII GMII MII error signals tx control gm tx err m tx err to indicate that the fragment transferred is not valid 2 The MAC functi
216. o the external PHY device using MII GMII RGMII and SGMII in conjunction with the 1000BASE X SGMII PCS and PMA functions A 10 100 1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields thus implementing a loopback A direct connection to an Ethernet link is provided through a combined MII to an external PHY module Certified 1 25 GBaud copper SFP transceivers are Finisar FCMJ 8521 3 Methode DM7041 and Avago Technologies ABCU 5700RZ Performance and Resource Utilization In the following tables the fmax of the configurations is more than 125 MHz About This MegaCore Function Altera Corporation LJ Send Feedback UG 01008 1 8 Performance and Resource Utilization 2015 06 15 Table 1 2 Arria Il GX Performance and Resource Utilization The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Arria II GX device family The estimates are obtained by compiling the Triple Speed Ethernet MegaCore function using the Quartus II software targeting an Arria II GX EP2AGX260EF2913 device with speed grade 3 MegaCore Function FIFO Buffer Combina Logic Memory Size Bits Ks Registers M9K Blocks M144K Blocks MLAB Bits 10 100 1000 Mbps RGMII 2048x32 3357 3947 26 0 1828 Biber All MAC options enabled Full and half duplex
217. oD Clock Drift You can use the DriftAdjust and DriftAdjustRate registers to correct any drift in the ToD clock In the case ofa ToD for 10G with period of 6 4ns the nanosecond field is converted directly to PERIOD_NS while the fractional nanosecond need to be multiplied with 216 or 65536 in order to convert to PERIOD FNS This results in 0x6 PERIOD NS and 0x6666 4 PERIOD FNS PERIOD NS only accepts 0x6666 and ignores 0x0000 4 which in turn would cause some inaccuracy in the configured period This inaccuracy causes the ToD to drift from the actual time as much as 953 67 ns after a period of 1 second You would notice that after every 5 cycles 0x0000 4 accumulates to 0x0002 If the TOD is able to add 0x0002 of fractional nanosecond into the ToD once after every period of 5 cycles then it will correct the drift Therefore for the 10G case DR1FT ADJUST NS is now configured to 0x0 pR1FT ADJUST FNS is configured to 0x0002 and ADJUST_RATE is configured to 0x5 Altera Corporation Time of Day ToD Clock G send Feedback ToD Synchronizer 2015 06 15 UG 01008 GX subscribe C Send Feedback The ToD Synchronizer provides a high accuracy synchronization of time of day from a master ToD clock to a slave ToD clock This synchronizer provides more user flexibility for your design The IEEE 1588v2 specifies multiple type of PTP devices which include the following clocks e ordinary clock boundary clock e transparent cl
218. ock e peer to peer transparent clock Some of these PTP devices boundary clock for example consists of multiple ports that act as master or slave in the IEEE 1588v2 system All these ports may share a common system clock or have its own individual clock If every port has an individual ToD running on its own clock then you must implement a method to instantiate one ToD clock as the master and the rest of the ToD clocks synchronized to this master ToD clock For this purpose Altera provides the ToD synchronizer module This module synchronizes a master ToD and a slave ToD in the following conditions e Master and slave ToD clock are in the same frequency within 125 MHz to 312 5 MHz but different phase e Master and slave ToD clock are in the same frequency within 125 MHz to 312 5 MHz but different PPM e Master and slave ToD clock are in different frequencies of either 125 MHz or 156 25 MHz e Master and slave ToD clock are in different frequencies of either 125 MHz or 312 5 MHz e Master and slave ToD clock are in different frequencies of either 156 25 MHz or 312 5 MHz O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as
219. on deasserts the RGMII GMII MII transmit enable signals tx control gm tx en m tx en to terminate the frame transmission 3 After the underflow the user application completes the frame transmission aN The transmitter control discards any new data in the FIFO buffer until the end of frame is reached 5 The MAC function starts to transfer data on the RGMII GMII MII when the user application sends a new frame with an SOP Functional Description LJ Send Feedback Altera Corporation UG 01008 4 18 Congestion and Flow Control 2015 06 15 Figure 4 7 Transmit FIFO Buffer Underflow Figure illustrates the FIFO buffer underflow protection algorithm for gigabit Ethernet system Transmit FIFO 3 4 ff tx data ff tx sop ff tx eop ff tx rdy ff tx wren ff tx ac fwd ff tx err ff tx septy ff tx uflow ff tx a full ff tx a empty GMII Transmit gm tx en gm tx d gm tx err Congestion and Flow Control In full duplex mode the MAC function implements flow control to manage the following types of congestion e Remote device congestion the receiving device experiences congestion and requests the MAC function to stop sending data e Receive FIFO buffer congestion when the receive FIFO buffer is almost full the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data e Local device congestion any device connected to the
220. on in Simulation Model Files on page 10 5 Updated the jumbo frames file directory in Using Jumbo Frames on page 11 4 Updated the ToD configuration parameters in ToD Clock Parameter Setting on page 14 2 and ToD interface signals in ToD Clock Interface Signals ToD Clock Avalon ST Transmit Interface Signals on page 14 4 and ToD Clock Avalon MM Control Interface Signals on page 14 3 Added information to describe the ToD s drift adjustment in Adjusting ToD Clock Drift on page 14 6 Added ToD Synchronizer and Packet Classifier chapters Removed SOPC Builder information Additional Information LJ Send Feedback Altera Corporation UG 01008 F 6 Triple Speed Ethernet IP Core Document Revision History 2015 06 15 oae RN January 2013 June 2012 12 1 12 0 Added Altera IEEE 1588v2 Feature section in Chapter 4 Added information for the following GUI parameters Enable timestamping Enable PTP 1 step clock and Timestamp fingerprint width in Timestamp Options Added MAC registers with IEEE 1588v2 feature Added IEEE 1588v2 feature signals tables Added Triple Speed Ethernet with IEEE 1588v2 Design Example section Added Time of Day Clock section Added support for Cyclone V Updated the Congestion and Flow Control section in Chapter 4 Added Register Initialization section in Chapter 5 Added noi1doff quant register description Added uNIDIRECTIONAL_ENABLE bit description Revised and moved th
221. onductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 7 2 10 100 1000 Ethernet MAC Signals 10 100 1000 Ethernet MAC Signals Figure 7 1 10 100 1000 Ethernet MAC Function with Internal FIFO Buffers Signals Clock and Reset Signal MACTransmit Interface Signals MAC Receive Interface Signals Pause and Magic Packet Signals MAC Control Interface Signals P ff tx dk ff tx data DATAWIDTH 1 0 ff tx mod 1 0 ff tx sop ff tx eop ff tx err ff tx wren ff tx ac fwd tx ff uflow ff tx rdy ff tx septy ff tx a full ff tx a empty ff rx dk ff rx rdy ff rx data DATAWIDTH 1 0 ff rx mod 1 0 ff rx sop ff rx eop rx err 5 0 Ix err stat 17 0 rx frm type 3 0 ff rx dsav ff rx dval ff rx a full ff rx a empty xon gen xoff gen magic sleep n magic _wakeup dk reg addr 7 0 reg Wr reg rd reg data in 31
222. ontrol Interface Signals Table 7 36 Register Interface Signals Avalon MM Description Signal Type reg clk Register access reference clock Set the signal to a value less than or equal to 125 MHz reset reg clk reset I Active high reset signal for reg_c1k clock domain reg wr write I Register write enable reg rd read I Register read enable reg addr 4 0 address I 16 bit word aligned register address reg data in 15 0 writedata I Register write data Bit 0 is the least significant bit reg data out 15 0 readdata O Register read data Bit 0 is the least significant bit reg_busy waitrequest O Register interface busy Asserted during register read or register write A value of 0 indicates that the read or write is complete PCS Reset Signals Table 7 37 Reset Signals reset_rx_clk I Active high reset signal for PCS rx_c1k clock domain Assert this signal to reset the logic synchronized by xx cix Pesetctx lk I Active high reset signal for PCS tx_c1k clock domain Assert this signal to reset the logic synchronized by tx cix MII GMII Clocks and Clock Enablers Data transfers on the MII GMII interface are synchronous to the receive and transmit clocks Table 7 38 MAC Clock Signals rx clk O Receive clock This clock is derived from the TBI clock tpi rx clk andsetto 125 MHz tx clk O Transmit clock This clock is derived from the TBI clock toi tx clk and set to 125 MHz
223. perations once these bits are set to 1 Table 6 3 Command Config Register Field Descriptions ENA Transmit enable Set this bit to 1 to enable the transmit datapath The MAC function clears this bit following a hardware or software reset See the sw RESET bit descrip tion 1 RX ENA RW Receive enable Set this bit to 1 to enable the receive datapath The MAC function clears this bit following a hardware or software reset See the sw RESET bit descrip tion 2 XON GEN RW Pause frame generation When you set this bit to 1 the MAC function generates a pause frame with a pause quanta of 0 independent of the status of the receive FIFO buffer 3 ETH SPEED RW Ethernet speed control e Set this bit to 1 to enable gigabit Ethernet operation The set_1000 signal is masked and does not affect the operation e Ifyou set this bit to 0 gigabit Ethernet operation is enabled only if the sec 1000 signal is asserted Otherwise the MAC function operates in 10 100 Mbps Ethernet mode When the MAC operates in gigabit mode the et h_mode signal is asserted This bit is not available in the small MAC variation Configuration Register Space Altera Corporation C Send Feedback 6 8 UG 01008 Command Config Register Dword Offset 0x02 2015 06 15 LINE ENIMS NN PROMIS Promiscuous enable Set this bit to 1 to enable promiscuous mode In this
224. plex is enabled Statistic counters if enabled Multicast hashtable if enabled 10 100 1000 Mb Ethernet MAC with 1000BASE X SGMII PCS Protects the following options transmit and receive FIFO buffer Retransmit buffer if half duplex is enabled Statistic counters if enabled Multicast hashtable if enabled SGMII bridge if enabled 1000BASE X SGMII PCS only 1000 Mb Small MAC Protects the SGMII bridge if enabled Protects the transmit and receive FIFO buffer 10 100 Mb Small MAC Protects the following options transmit and receive FIFO buffer Retransmit buffer if half duplex is enabled When you enable this feature the following output ports are added for 10 100 1000 Mb Ethernet MAC and 1000BASE X SGMII PCS variants to provide ECC status of all the memory instances in the MegaCore function e Single channel core configuration eccstatus 1 0 output ports e Multi channel core configuration eccstatus n 1 0 output ports where eccstatus_0 1 0 is for channel 0 eccstatus 1 1 0 for channel 1 and so on MAC Reset A hardware reset resets all logic A software reset only disables the transmit and receive paths clears all statistics registers and flushes the receive FIFO buffer The values of configuration registers such as the MAC address and thresholds of the FIFO buffers are preserved during a software reset When you trigger a software reset the MAC function sets the 7x E
225. poration Interface Signals C Send Feedback UG 01008 g 2015 06 15 IEEE 1588v2 Timestamp 7 49 Figure 7 23 Type 1 Egress Correction Field Update Type 1 Egress Correction Field Update 96b IPV4 2 step Timestamp Request Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data N 0 Don t care 2 step Timestamp Return Output tx egress timestamp 96b valid tx egress timestamp 96b fingerprint N 0 Don t care tx egress timestamp 96b data 95 0 Don t care tx egress timestamp 64b valid tx egress timestamp 64b fingerprint N 0 Don t care tx egress timestamp 64b data 63 0 Don t care 1 step Timestamp Insert Input tx etstamp ins ctrl timestamp insert tx etstamp ins ctrl timestamp format Don t care 1 step Residence Time Update Input tx etstamp ins ctrl residence time update 0d ll A o o x etstamp ins ctrl ingress timestamp 96b 95 0 Ingress Timestamp _ Y X_etstamp_ins_ctrl_ingress_timestamp_64b 63 0 Don t care tx etstamp ins ctrl residence time calc format 1 step IPv4 and IPv6 Checksum Input tx etstamp ins ctrl checksum zero NEEDS IIEEML MENS tx etstamp ins ctl checksum correct 1 step Location Offset Input tx etstamp ins ctrl offset timestamp 15 0 Don t care tx etstamp ins ctrl offset correction field 15 0 l Offset 1 tx_etstamp_ins_ctrl_offset_checksum_field 15 0 ss Wa xtstamp ins ct
226. primary address configured in the registers mac_0 and mac_1 e The supplementary addresses configured in the following registers smac 0 0 smac 0 1 smac 1 0 smac 1 1 smac 2 0 smac 2 1and smac 3 0 smac 3 1 Otherwise the MAC function discards the frame Multicast Address Resolution You can use either a software program running on the host processor or a hardware multicast address resolution engine to resolve multicast addresses Address resolution using a software program can affect the system performance especially in gigabit mode The MAC function uses a 64 entry hash table in the register space multicast hash table to implement the hardware multicast address resolution engine as shown in figure below The host processor must build the hash table according to the specified algorithm A 6 bit code is generated from each multicast address by xoning the address bits as shown in table below This code represents the address of an entry in the hash table Write one to the most significant bit in the table entry All multicast addresses that hash to the address of this entry are valid and accepted You can choose to generate the 6 bit code from all 48 bits of the destination address by setting the MHASH SEL bit in the command con ig register to 0 or from the lower 24 bits by setting the mHAsH_sEt bit to 1 The latter option is provided if you want to omit the manufacturer s code which typically resides in the upper 24 bits of the des
227. ption C Send Feedback Triple Speed Ethernet with IEEE 1588v2 Design Example 2015 06 15 UG 01008 GX subscribe C Send Feedback Software Requirements Altera uses the following software to test the Triple Speed Ethernet with IEEE 1588v2 design example and testbench e Altera Complete Design Suite 14 0 e ModelSim SE 10 0b or higher O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 5 2 Triple Spe
228. r Space Use the following recommended initialization sequences for the example in Figure 6 5 1 External PHY Initialization using MDIO Refer to step 1 in Triple Speed Ethernet System with MII GMII or RGMII on page 6 27 2 PCS Configuration Register Initialization a Set Auto Negotiation Link Timer Set Link timer to 10ms for 1000BASE X link timer address offset 0x12 0x12D0 link timer address offset 0x13 0x13 b Configure SGMII 1000BASE X SGMII PCS is default in 1000BASE X Mode SGMII_ENA 0 USE SGMII AN 0 if mode 0x0000 c Enable Auto Negotiation Enable Auto Negotiation Configuration Register Space Altera Corporation C Send Feedback UG 01008 6 32 Triple Speed Ethernet System with 1000BASE X Interface 2015 06 15 AUTO NEGOTIATION ENA 1 Bit 6 8 13 is Read Only PCS Control Register 0x1140 d PCS Reset PCS Software reset is recommended where there any configuration changed RESET 1 PCS Control Register 0x9140 Wait PCS Control Register RESET bit is clear 3 MAC Configuration Register Initialization Refer to step 2 in Triple Speed Ethernet System with MII GMII or RGMII on page 6 27 Note If 1000BASE X SGMII PCS is initialized set the ETH_SPEED bit 3 and ENA_10 bit 25 in command_config register to 0 If half duplex is reported in the PHY PCS status register set the HD_ENA bit 10 to 1 in command_config register Altera Corporat
229. r_stat 17 0 O rx_err_stat 17 One indicates that the receive frame is a stacked VLAN frame rx_err_stat 16 One indicates that the receive frame is either a VLAN or stacked VLAN frame rx_err_stat 15 0 The value of the length type field of the receive frame Table 7 6 rx_frm_type Bit Description S CIONNNNNNNN 3 Indicates VLAN frames Asserted with _rx_sop and remains asserted until the end of the frame 2 Indicates broadcast frames Asserted with rx sop and remains asserted until the end of the frame 1 Indicates multicast frames Asserted with rx sop and remains asserted until the end of the frame 0 Indicates unicast frames Asserted with rx sop and remains asserted until the end of the frame Table 7 7 rx err Bit Description ELEME 5 Collision error Asserted when the frame was received with a collision 4 Corrupted receive frame caused by PHY or PCS error Asserted when the error is detected on the MII GMII RGMII 3 Truncated receive frame Asserted when the receive frame is truncated due to an overflow in the receive FIFO buffer 2 1 CRC error Asserted when the frame is received with a CRC 32 error This error bit applies only to frames with a valid length Refer to Length Checking on page 4 11 1 1 Invalid length error Asserted when the receive frame has an invalid length as defined Altera Corporation by the IEEE Standard 802 3
230. rable register for timestamp correction on both transmit and receive datapaths Supports Time of Day ToD clock that provides a stream of 64 bit and 96 bit timestamps Functional Description Altera Corporation LJ Send Feedback 4 42 UG 01008 2015 06 15 IEEE 1588v2 Architecture IEEE 1588v2 Architecture Figure 4 26 Overview of the IEEE 1588v2 Feature This figure shows only the datapaths related to the IEEE 1588v2 feature tx path delay Timestamp amp Y User Fingerprint IEEE 1588v2 gt PHY i Tx Logic Tx Prstne paes 1 n A A Stack ingress P i Correction MAC PHY tx time of day Time of Day rx_time_of_day Time of Day Clock IEEE 1588v2 PHY Timestamp Aligned to Rx Logic Rx Receive Frame A rx_path_delay IEEE 1588v2 Transmit Datapath The IEEE 1588v2 feature supports 1 step and 2 step clock synchronizations on the transmit datapath Altera Corporation For 1 step clock synchronization Timestamp insertion depends on the PTP device and message type The MAC function inserts a timestamp in the Sync PTP message if the PTP clock operates as ordinary or boundary clock Depending on the PTP device and message type the MAC function updates the residence time in the correction field of the PTP frame when the client asserts _time_update The residence time is the difference between the tx_etstamp_i
231. rademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any E inis egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of p AN 101 Innovation Drive San Jose CA 95134 UG 01008 8 2 MAC and PCS With GX Transceivers 2015 06 15 Configurations MAC Only MAC and PCS MAC and PCS with PMA Yes Clocks reconfig_clk Notes to Table 8 1 1 Yes indicates that the clock is visible at the top level design No indicates that the clock is not visible at the top level design indicates that the clock is not applicable for the given configuration 2 Applies to GX transceiver MAC and PCS With GX Transceivers In configurations that contain the MAC
232. rames the MAC function accepts the frames and forwards them to the user application only when the cNTL_FRM_ENa bit in the command con ig register is set to 1 For other field values the MAC function forwards the receive frame to the user application Related Information Remote Device Congestion on page 4 18 Payload Pad Removal You can turn on padding removal by setting the PAp EN bit in the command con ig register to 1 The MAC function removes the padding prior to forwarding the frames to the user application when the payload length is less than the following values for the different frame types e 46 bytes for basic MAC frames e 42 bytes for VLAN tagged frames e 38 bytes for stacked VLAN tagged frames When padding removal is turned off complete frames including the padding are forwarded to the Avalon ST receive interface CRC Checking The following equation shows the CRC polynomial as specified in the IEEE 802 3 standard FCS X X 9 X 6 X P X 2 X 16 X D AX HX 10 X 8 X7 X 4X44X 4X14 The 32 bit CRC value occupies the FCS field with x31 in the least significant bit of the first byte The CRC bits are thus received in the following order x31 x30 x1 x0 If the MAC function detects CRC 32 error it marks the frame invalid by asserting the following signals e rx err 2 in MAC variations with internal FIFO buffers e data rx error 1 in MAC variations without internal FIFO buffers The MAC function
233. rames are continu ously generated and sent to the MII GMII TX interface until the XON GEN bit is cleared 1 1 This event is not recommended as it will produce non determin istic result Note to Table A 1 1 Set the XON and XOFF registers to 0 when you use the I O pin to generate the pause frame and vice versa Altera Corporation Ethernet Frame Format C Send Feedback 2015 06 15 Simulation Parameters UG 01008 GX subscribe send Feedback Functionality Configuration Parameters You can use these parameters to enable or disable specific functionality in the MAC and PCS Table B 1 MegaCore Functionality Configuration Parameters A IN NE 73M Supported in configurations that contain the 10 100 1000 Ethernet MAC ETH MODE 10 Enables MII 1000 100 Enables MII 1000 Enables GMII HD ENA Sets the HD_ENa bit in the command con ig register See 0 Command Config Register Dword Offset 0x02 on page 6 7 TB MACPAUSEQ Sets the pause quant register See Base Configuration Registers 15 Dword Offset 0x00 0x17 on page 6 3 TB MACIGNORE Sets the PAUSE IGNORE bit in the command config register See 0 PAUSE Command Config Register Dword Offset 0x02 on page 6 7 TB MACFWD PAUSE SetsthePausE rwp bit in the command config register See 0 Command Config Register Dword Offset 0x02 on page
234. rated by an interpacket gap IPG of at least 96 bit times The MAC function however can accept frames with an IPG ofless than 96 bit times at least 8 bytes and 6 bytes in RGMII GMII 1000 Mbps operation and RGMII MII 10 100 Mbps operation respectively The MAC function removes the preamble and SFD fields from valid frames Collision Detection in Half Duplex Mode In half duplex mode the MAC function checks for collisions during frame reception When collision is detected during the reception of the first 64 bytes the MAC function discards the frame if the RX ERR DISC bitis set to 1 Otherwise the MAC function forwards the frame to the user application with error Address Checking The MAC function can accept frames with the following address types Functional Description Altera Corporation LJ Send Feedback UG 01008 4 8 Unicast Address Checking 2015 06 15 e Unicast address bit 0 of the destination address is 0 e Multicast address bit 0 of the destination address is 1 e Broadcast address all 48 bits of the destination address are 1 The MAC function always accepts broadcast frames If promiscuous mode is enabled PRomIsS_EN bit in the command_config register 1 the MAC function omits address filtering and accepts all frames Unicast Address Checking When promiscuous mode is disabled the MAC function only accepts unicast frames if the destination address matches any of the following addresses The
235. rdy 0 the MAC function performs the following operations e Stops writing data to the FIFO buffer e Truncates received frames to avoid FIFO buffer overflow e Asserts the xx err 0 signal when the rx eop signal is asserted e Marks the truncated frame invalid by setting the xx err 3 signal to 1 If the Rx_ERR_DISC bit in the command_config register is set to 1 and the section full xx section full threshold is set to 0 the MAC function discards frames with error received on the Avalon ST interface Section empty rx section empty An early indication that the FIFO buffer is getting full When the level of the FIFO buffer hits this threshold the MAC function generates an XOFF pause frame to indicate FIFO congestion to the remote Ethernet device When the FIFO level goes below this threshold the MAC function generates an XON pause frame to indicate its readiness to receive new frames To avoid data loss you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost full threshold The MAC function truncates receive frames when the buffer level hits the almost full threshold Functional Description LJ Send Feedback Altera Corporation UG 01008 2015 06 15 Section full rx section full The section full threshold indicates that there are sufficient entries in the FIFO buffer for the user applica
236. reaches the section empty threshold xx section empty Iftransmission is in progress the MAC function waits for the transmission to complete before generating the pause frame The fill level of an external FIFO buffer is obtained via the Avalon ST receive FIFO status interface When generating a pause frame the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause quant register The source address is set to the primary MAC address configured in the mac 0 and mac 1 registers and the destination address is set to a fixed multicast address 01 80 C2 00 00 01 0x010000c28001 The MAC function automatically generates an XON pause frame when the FIFO buffer section empty flag is deasserted and the current frame transmission is completed The user application can trigger the generation of an XON pause frame by clearing the xorrF ceu bit and signal and subsequently setting the XON GEN bit to 1 or asserting the xon_GEN signal When generating an XON pause frame the MAC function fills the pause quanta payload bytes P1 and P2 with 0x0000 zero quanta The source address is set to the primary MAC address configured in the mac 0 and mac 1 registers and the destination address is set to a fixed multicast address 01 80 C2 00 00 01 0x010000c28001 In addition to the flow control mechanism the MAC function prevents an overflow by truncating excess frames The status bit rx_err 3 is set to 1 to indi
237. rl offset checksum correction 15 0 Don t care Figure 7 24 shows the TX timestamp signals for the second type of egress correction field update where the 64 bit ingress timestamp has been pre subtracted from the correction field at the ingress port At the egress port the 64 bit egress timestamp is added into the correction field and the correct residence time is updated in the correction field This is the example of PTP frame encapsulated over UPD IPV6 The tx etstamp ins ctrl residence time calc format signal is driven high to indicate that this is a 64b residence time calculation The tx etstamp ins ctrl checksum correct signal is driven high to correct the packet UPD IPV6 checksum by updating the checksum correction field Interface Signals Altera Corporation LJ Send Feedback ET UG 01008 IEEE 1588v2 Timestamp 2015 06 15 Figure 7 24 Type 2 Egress Correction Field Update Type 2 Egress Correction Field Update 64b IPV6 2 step Timestamp Request Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data N 0 Don t care 2 step Timestamp Return Output tx egress timestamp 96b valid tx egress timestamp 96b fingerprint N 0 Don t care tx egress timestamp 96b data 95 0 Don t care tx egress timestamp 64b valid tx egress timestamp 64b fingerprint N 0 Don t care tx egress timestamp 64b data 63 0 Don t care 1 step Timestamp Insert Input tx etstamp ins ctrl timestamp insert
238. rnet MAC Options on page 3 2 A data bit is shifted in out on each rising edge of this clock AII fields are shifted in and out starting from the most significant bit Interface Signals LJ Send Feedback Altera Corporation UG 01008 7 12 ECC Status Signals 2015 06 15 ECC Status Signals Table 7 12 ECC Status Signals mac eccstatus 1 0 O Indicates the ECC status This signal is synchronized to the reg_ clk clock domain e ll An uncorrectable error occurred and the error data appears at the output e 10 A correctable error occurred and the error has been corrected at the output However the memory array has not been updated e 01 Not valid e 00 No error Interface Signals C Send Feedback Altera Corporation UG 01008 2015 06 15 10 100 1000 Multiport Ethernet MAC Signals 10 100 1000 Multiport Ethernet MAC Signals Figure 7 2 10 100 1000 Multiport Ethernet MAC Function without Internal FIFO Buffers Signals Clock Signals MAC Transmit Interface Signals MAC Receive Interface Signals MAC Packet Classification Signals MAC FIFO Status Signals Pause and Magic Packet Signals MAC Control Interface Signals Interface Signals CJ Send Feedback MLS TEU A I ttt TIS Multi Port MAC mac tx dk n mac rx ck n data tx data n 7 0 data tx sop n data tx eop n data tx error n data tx valid n data tx ready n tx cc fwd n tx ff uflow n data rx data n 7 0 data r
239. rs a software reset also clears these registers except aMacip The statistics counters roll up when the counter is full The register description uses the following definitions Good frame error free frames with valid frame length e Error frame frames that contain errors or whose length is invalid e Invalid frame frames that are not addressed to the MAC function The MAC function drops this frame Table 6 4 Statistics Counters Dword Description Offset Ox18 aMacID RO 0x19 The MAC address This register is wired to the primary MAC address in the mac 0 and mac 1 registers OxlA aFramesTransmitt RO The number of frames that are successfully transmitted edOK including the pause frames Ox1B aFramesReceivedo RO The number of frames that are successfully received K including the pause frames OxIC aFrameCheck RO The number of receive frames with CRC error SequenceErrors Ox1D aAlignmentErrors RO The number of receive frames with alignment error OxlE aOctetsTransmitt RO edOK The number of data and padding octets that are successfully transmitted This register contains the lower 32 bits of the aOctetsTransmittedOK counter The upper 32 bits of this statistics counter reside at the dword offset OxOF Configuration Register Space Altera Corporation C Send Feedback UG 01008 6 12 Statistics
240. rs as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 9 2 Creating Clock Constraints Figure 9 1 Triple Speed Ethernet Timing Constraint Example UG 01008 2015 06 15 The reconfig_clk signal is not shown in this example Constrain the xecon ig clk based on your design implementation TOv pll_inclk ext_clk i 100 Mhz 50 Mhz incik l Altera PLL Mwerintaxev 4o c c0 i tse variation v dk 110 Mhz 10 100 1000 Mbps Ethernet MAC with 1000BASE X SGMII i PCS and PMA i F i ff tx dk with internal FIFO RE xer rei dk LL ff rx dk 125 Mhz Pm eke as eh Neth ce ee NEIN NE The example above consists of the following Verilog modules e TOP v The top level design module which contains an Altera PLL and a us
241. rted with Altera IP Cores C Send Feedback UG 01008 2015 06 15 Programming an FPGA Device 2 3 To compile your design click Start Compilation on the Processing menu in the Quartus II software You can use the generated qip file to include relevant files into your project Related Information Quartus II Help More information about compilation in Quartus II software Programming an FPGA Device After successfully compiling your design program the targeted Altera device with the Quartus II Programmer and verify the design in hardware For instructions on programming the FPGA device refer to the Device Programming section in volume 3 of the Quartus II Handbook Related Information Device Programming Generated Files The type of files generated in your project directory and their names may vary depending on the custom variation of the MegaCore function you created Table 2 1 Generated Files variation name v or variation name vhd A MegaCore function variation file which defines a VHDL or Verilog HDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside your design Include this file when compiling your design in the Quartus II software variation name bsf Quartus II symbol file for the MegaCore function variation You can use this file in the Quartus II block diagram editor variation name qip and variation name sip Contains Quartu
242. s II project information for your MegaCore function variations variation name cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore variation name spd Simulation Package Descriptor file Specifies the files required for simulation Testbench Files in variation name testbench folder README txt Read me file for the testbench design generate sim qpf and generate sim qsf Dummy Quartus II project and project setting file Use this to start the Quartus II in the correct directory to launch the generate sim verilog tcl and generate sim vhdl tcl files generate sim verilog tcl and generate sim vhdl tcl A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench Getting Started with Altera IP Cores LJ Send Feedback Altera Corporation UG 01008 2 4 Design Constraint File No Longer Generated 2015 06 15 ENEENLI REN NE 7 ON testbench_vhdl lt variation_name gt VHDL or Verilog HDL testbench that exercises your MegaCore lt variation_name gt _tb vhd or function variation in a third party simulator testbench_verilog lt variation_name gt lt variation_name gt _tb v testbench_vhdl lt variation_name gt A Tcl script for use with the ModelSim simulation software run_ lt variation_name gt _tb tcl or testbench_verilog
243. s collecting traffic statistics For more information about the 0x38 statistics counters refer to Statistics Counters Dword Offset 0x18 0x38 on page 6 11 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of p AN 101 Innovation Drive San Jose CA 95134 6 2 MAC Configuration Register Space UG 01008 2015 06 15 0x3A Transmit Command __ Transmit and receive datapaths control register For more informa 0x3B Receive C d
244. s or services ANU S RYA 101 Innovation Drive San Jose CA 95134 UG 01008 E 2 Packet Classifier Signals 2015 06 15 Packet Classifier Signals Packet Classifier Common Clock and Reset Signals Table E 1 Clock and Reset Signals for the Packet Classifier I ea NN Input 1 156 25 MHz register access reference clock reset Input 1 Assert this signal to reset the clock Packet Classifier Avalon ST Interface Signals Table E 2 Avalon ST Dataln Interface Signals for the Packet Classifier I GNE 7 NN data sink sop Input data sink eop Input 1 data_sink_valid Input 1 data_sink_ready Output 1 The Avalon ST input frames data_sink_data Input 64 data_sink_empty Input 3 data_sink_error Input 1 Table E 3 Avalon ST DataOut Source Interface Signals for the Packet Classifier EE EET TI GNE 7 A NN data src sop Input data src eop Input 1 data_src_valid Input 1 data_src_ready Output 1 The Avalon ST output frames data_src_data Input 64 data src empty Input 3 data src error Input 1 Altera Corporation Packet Classifier C Send Feedback UG 01008 2015 06 15 Packet Classifier Ingress Control Signals Table E 4 Ingress Control Signals for the Packet Classifier Packet Classifier Ingress Control Signals E 3 a T2 IN NN tx etstamp ins ctrl in ingress Input 96 bit format of ingress timestamp timestamp 96b th
245. s received from the user application with the MAC primary or supplementary address configured in the registers The TX ADDR SEL bit determines the address selection e Set this bit to 0 to retain the source MAC address in transmit frames received from the user application 10 HD Altera Corporation ENA RW Half duplex enable e Set this bit to 1 to enable half duplex e Set this bit to 0 to enable full duplex The MAC function ignores this bit if you set the ETH_ SPEED bit to 1 Configuration Register Space C Send Feedback UG 01008 2015 06 15 Command Config Register Dword Offset 0x02 6 9 Ls d RN ESS COL Excessive collision condition e The MAC function sets this bit to 1 when it discards a frame after detecting a collision on 16 consecutive frame retransmissions e The MAC function clears this bit following a hardware or software reset See the sw RESET bit description 12 LATE COL RO Late collision condition The MAC function sets this bit to 1 when it detects a collision after transmitting 64 bytes and discards the frame e The MAC function clears this bit following a hardware or software reset See the sw RESET bit description 13 SW RESET RW Software reset Set this bit to 1 to trigger a software reset The MAC function clears this bit when it completes the software reset sequence
246. s table e Added description for new signals tx_clkena rx clkena and led panel link e Added Qsys equivalent signal names for the following signals e control port clock connection clk e pcs mac tx clock connection tx clk e pcs mac rx clock connection rx clk e receive clock connection ff rx clk e transmit clock connection ff tx clk e Revised the Command con ig register field descriptions for bits 0 1 and 13 e Corrected the Command con ig register setting for Enable MAC Transmit and Receive Datapath register initialization sequence from 0x00802223 to 0x00800223 e Corrected the bit width for pkt_class_data signal in the following timing diagrams e Receive Operation MAC Without Internal FIFO Buffers e Invalid Length Error During Receive Operation MAC Without Internal FIFO Buffers e Updated the following sections to indicate that the reconfiguration signals are not present in variations targeting Arria 10 Stratix V Arria V and Cyclone V devices with GX transceivers e notein Figure F 5 e SERDES control signals description in Table F 27 e notein Figure F 6 e Sharing Transceiver Quads on page 8 7 e Updated the description for Extended Statistics Counters 0x3C Ox3E to state the specific order for reading counters e Removed 10 100 1000 Mbps MAC with 1000BASE X SGMII PCS configuration from the list of supported configurations in IEEE 1588v2 feature e Added a new topic Using ToD Clock SecondsH Seco
247. se Frame Format 7octets PREAMBLE 1 octet SFD 6 octets DESTINATION ADDRESS 6 octets SOURCE ADDRESS 2 octets TYPE 0x8808 2 octets OPCODE 0X0001 2 octets PAUSE QUANTA P1 P2 42 octets PAD 4 octets CRC Ethernet Frame Format CJ Send Feedback Payload Altera Corporation i UG 01008 A 4 Pause Frame Generation 2015 06 15 Pause Frame Generation When you turn on the Enable full duplex flow control option pause frame generation is triggered by the following events e RX FIFO fill level hits the xx section empty threshold e XOFF register write XON register write e XOFF I O pin xo gen assertion e XONI O pin xon gen assertion If the RX FIFO buffer is almost full the MAC function triggers the pause frame generation to the remote Ethernet device If the local Ethernet device needs to generate pause frame via XOFF or XON register write or I O pin assertion it is recommended to set the xx section empty register to a larger value to avoid non deterministic result Table A 1 summarizes the pause frame generation based on the above events Table A 1 Pause Frame Generation Register Write or I O Pin Assertion Description XOFF GEN XON GEN E 0 If the xorr cEu bit is set to 1 the XOFF pause frames are continu ously generated and sent to the MII GMII TX interface until the XOFF GEN bit is cleared 0 1 If the xow GEN bit is set to 1 the XON pause f
248. se riii erv aede teet ev vua x deii un Rv EE HE SE UR E 6 1 MAC Contsurati n Registet SDIQeunsiudenski sir ned ipi cerokidesiib secet tussi do onto quib iex paga 6 1 Base Configuration Registers Dword Offset 0x00 0x17 teens 6 3 Statistics Counters Dword Offset 0X18 0x38 tnnt tette tn ennt 6 11 Transmit and Receive Command Registers Dword Offset 0x3A 0x3B 6 13 Supplementary Address Dword Offset 0XCO 0xC7 sese 6 15 IEEE 1588v2 Feature Dword Offset OxDO OXD6 ccccccsessesssesesessssesesesssssscsessssesesececsesees 6 16 IEEE 158892 Feature PMA Delay uuesconcistis Qe dti FOREN UR MEER EM R HELM 6 17 PCS Configuration Register Space aso reps i tod i Sere ERRARE UNE REIHE SEENR ERN ERAN RENE PRU QE 6 18 Control Register d WOPEOLDSSEDXOUD isset dotado uaa d id cel eeds optic 6 20 Altera Corporation TOC 4 Status Register Word OUSEEOX D cissescssnsciseds tine reme b tonii ceascenssnsubasvengnvincaeacennstinvenndueahees 6 22 Dev Ability and Partner Ability Registers Word Offset 0x04 0x05 6 23 An Expansion Register Ward Offset Ux tta erret secs aatenssdeaaeoassaiocviaitsvend 6 26 IE Mode Register Word OHSBEDSDD e unio tiara bti tea a abduahsn MO DER Ua 6 26 Register Initialization PH M 6 27 Triple Speed Ethernet System with MII GMII or RGMII eee 6 27 Triple Speed Ethernet System with SGMIL ae iscetiae
249. set to 1 and 0 respectively This combination of values represent the gigabit mode Bit 6 13 e 00 10 Mbps 01 100 Mbps e 10 1 Gigabit e 11 Reserved COLLI SION TEST RO The PCS function does not support half duplex mode This bit is always set to 0 EX MODE RO The PCS function only supports full duplex mode This bit is always set to 1 Z EGOT EO TARTEAUIOS IATION RW Set this bit to 1 to restart the auto negotiation sequence For normal operation set this bit to 0 reset value 10 ISOLATE RW Set this bit to 1 to isolate the PCS function from the MAC layer device For normal operation set this bit to 0 reset value 11 POWERDOWN RW Set this bit to 1 to power down the transceiver quad The PCS function then asserts the powerdown signal to indicate the state it is in 12 AUTO NEGOTIATION ENABLE RW Set this bit to 1 reset value to enable auto negotiation Configuration Register Space GJ send Feedback Altera Corporation 6 22 Status Register Word Offset 0x01 LIRE REEL NENNEN NENNEN LOOPBACK UG 01008 2015 06 15 PHY loopback Set this bit to 1 to implement loopback in the GX transceiver For normal operation set this bit to 0 reset value This bit is ignored if reduced ten bit interface RTBI is implemented This feature is supported in all device families except
250. t 0x3A 0x3B on page 6 13 ALTERA TSEMAC TX CMD STAT OMITCRC OFST 17 Configures the OMIT_CRC bit ALTERA TSEMAC TX CMD STAT OMITCRC MSK 0x20000 ALTERA TSEMAC TX CMD STA XSHIFT16 OFST 18 Configures the Tx_SHIFT16 bit ALTERA TSEMAC TX CMD STAT TXSHIFT16 MSK 0x40000 Rx Cmd Stat Register Transmit and Receive Command Registers Dword Offset 0x3A 0x3B on page 6 13 ALTERA TSEMAC RX CMD STAT RXSHIFT16 OFST 25 ALTERA TSEMAC RX CMD STAT RXSHIFT16 MSK 0x20000 Configures the Rx_SHIFT16 bit 00 Software Programming Interface Altera Corporation CJ Send Feedback Ethernet Frame Format A 2015 06 15 UG 01008 GX subscribe Send Feedback Basic Frame Format Figure A 1 MAC Frame Format 7 octets PREAMBLE 1 octet SFD 6 octets DESTINATION ADDRESS 6 octets SOURCE ADDRESS 2 octets LENGTH TYPE Frame length 9 4500 8600 octets PAYLOAD DATA 0 46 octets PAD 4 octets FRAME CHECK SEQUENCE EXTENSION half duplex only A basic Ethernet frame comprises the following fields e Preamble a maximum of 7 octet fixed value of 0x55 e Start frame delimiter SFD a 1 octet fixed value of 0xD5 which marks the beginning of a frame e Destination and source addresses 6 octets each The least significant byte is transmitted first e Leng
251. t N 0 tx_egress_timestamp_64b_data 63 0 1 step Timestamp Insert Input tx_etstamp_ins_ctrl_timestamp_insert tx_etstamp_ins_ctrl_timestamp_format 1 step Residence Time Update Input tx_etstamp_ins_ctrl_residence_time_update tx_etstamp_ins_ctrl_ingress_timestamp_96b 95 0 tx_etstamp_ins_ctrl_ingress_timestamp_64b 63 0 tx_etstamp_ins_ctrl_residence_time_calc_format 1 step IPv4 and IPv6 Checksum nput tx etstamp ins ctrl checksum zero tx etstamp ins ctrl checksum correct 1 step Location Offset Input tx etstamp ins ctrl offset timestamp 15 0 tx etstamp ins ctrl offset correction field 15 0 tx etstamp ins ctrl offset checksum field 15 0 tx etstamp ins ctrl offset checksum correction 15 0 Don t care Don t care Don t care Don t care Don t care Don t care Don t care Don t care Offset 1 Offset 2 y Don t care Don t care Figure 7 23 shows the TX timestamp signals for the first type of egress correction field update where the residence time is calculated by subtracting 96 bit ingress timestamp from 96 bit egress timestamp The result is updated in the correction field of the PTP frame encapsulated over UDP IPv4 The tx etstamp ins ctrl residence time calc format signal is driven low to indicate that this is a 96b residence time calculation The tx etstamp ins ctrl checksum zero signal is driven high to clear the UDP IPv4 checksum field to all 0 Altera Cor
252. t collision the backoff period in slot time is 0 or 1 If a collision occurs during the first retransmission the backoff period in slot time is 0 1 2 or 3 The maximum backoff time in 512 bit times slots is limited by N set to 10 as specified in the IEEE Standard 802 3 If collision occurs after 16 consecutive retransmissions the MAC function reports an excessive collision condition by setting the EXCESS_COL bit in the command_config register to 1 and discards the current frame from the transmit FIFO buffer In networks that violate standard requirements collision may occur after the transmission of the first 64 bytes If this happens the MAC function stops transmitting the current frame discards the rest of the frame from the transmit FIFO buffer and resumes transmitting the next available frame You can check the LATE_COL register command config 12 to verify if the MAC has discarded any frame due to collision MAC Receive Datapath The MAC function receives Ethernet frames from the network via a PHY and forwards the payload with relevant frame fields to the user application after performing checks filtering invalid frames and removing the preamble and SFD Preamble Processing The MAC function uses the SFD 0xp5 to identify the last byte of the preamble If an SFD is not found after the seventh byte the MAC function rejects the frame and discards it The IEEE standard specifies that frames must be sepa
253. t data bus is valid an tx ere Asserted to indicate to the PHY that the frame sent is invalid GMII Receive tpa sese el lt 7 8191 GMII receive data bus gm rx dv Assert this signal to indicate that the data on the GMII receive data bus is valid Keep this signal asserted during frame reception from the first preamble byte until the last byte of the CRC field is received gm rx err The PHY asserts this signal to indicate that the receive frame contains errors RGMII Transmit GML Cwmie 3 80 RGMII transmit data bus Drives gm tx a 3 0 on the positive edge of tx c1k and gm tx d 7 4 on the negative edge of tx_ bliss tx control Control output signal Drives gm tx en on the positive edge of tx clk anda logical derivative of gm tx en XOR gm tx err on the negative edge of tx c1x RGMII Receive rgmii in 3 0 RGMII receive data bus Expects gm_rx_d 3 0 on the positive edge of xx cik and gm_rx_d 7 4 on the negative edge of rx_ clk Ie cer com ters co RGMII control input signal Expects gm xx v on the positive edge of xx c1k and a logical derivative of gm xx dv XOR gm rx err on the negative edge of xx c1x MII Transmit m tx d 3 0 MII transmit data bus m tx en Asserted to indicate that the data on the MII transmit data bus is valid m tx err Asserted to indicate to the PHY device that the frame sent is invalid MII Receive
254. t to 1 to instruct the MAC function to align receive frames on 32 bit boundary For more information on frame alignment refer to IP Payload Alignment on page 4 11 This setting applies only when you turn on the Align packet headers to 32 bit boundary option and in MAC variations with 32 bit internal FIFO buffers Otherwise reading this bit always return a 0 In MAC variations without internal FIFO buffers this bit is a read only bit and takes the value of the Align packet headers to 32 bit boundary option e Bits 26 to 31 unused Altera Corporation Configuration Register Space G send Feedback UG 01008 2015 06 15 Supplementary Address Dword Offset OxCO 0xC7 6 15 Supplementary Address Dword Offset OxCO OxC7 A software reset has no impact on these registers MAC supplementary addresses are not available in 10 100 and 1000 Small MAC variations Table 6 6 Supplementary Address Registers Dword R W Description Offset OxCO smac 0 0 You can specify up to four 6 byte supplementary OxC1 smac 0 1 addresses e smac O 0 1 OxC2 1_0 x smac 1 e smac 1 0 1 0xC3 smac 1 1 m smac_2_0 1 OxC4 smac 2 0 e smac 3 0 1 OxC5 smac 21 Map the supplementary addresses to the respective registers in the same manner as the primary MAC 0xC6 smac 3 0 address Refer to the description of mac 0 and mac 1 OxC7 smac 3 1 The MAC function uses the supplementary addresses for the following operations RW 0
255. tcl Triple Speed Ethernet with IEEE 1588v2 Design Example Altera Corporation LJ Send Feedback Configuration Register Space 2015 06 15 UG 01008 GX subscribe send Feedback MAC Configuration Register Space Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters In multiport MACs a contiguous register space is allocated for all ports and accessed via the Avalon MM control interface For example if the register space base address for the first port is 0x00 the base address for the next port is 0x100 and so forth The registers that are shared among the instances occupy the register space of the first port Updating these registers in the register space of other ports has no effect on the configuration Table 6 1 Overview of MAC Register Space 0x00 Base Configuration Base registers to configure the MAC function At the minimum you 0x17 must configure the following functions e Primary MAC address mac_0 mac_1 e Enable transmit and receive paths Tx ENa and Rx wa bits in the command config register The following registers are shared among all instances of a multiport MAC e rev scratch frm length pause quant e mdio addrO and mdio addr1 e tx ipg length For more information about the base configuration registers refer to Base Configuration Registers Dword Offset 0x00 0x17 on page 6 3 0x18 Statistics Counters Counter
256. tera Corporation 7 34 IEEE 1588v2 Time of Day ToD Clock Interface Signals me i e EE tx etstamp ins ctrl offset checksum field UG 01008 2015 06 15 The location of the checksum field relative to the first byte of the packet Assert this signal in the same clock cycle as the start of packet ava1on st tx startofpacket is asserted tx etstamp ins ctrl offset checksum correction 16 The location of the checksum correction field relative to the first byte of the packet Assert this signal in the same clock cycle as the start of packet avalon_st_ tx startofpacket is asserted IEEE 1588v2 Time of Day ToD Clock Interface Signals Table 7 33 IEEE 1588v2 ToD Clock Interface Signals eC NN tx time of day 96b data n rx time of day 96b data 96 Use this bus to carry the time of day from external ToD module to 96 bit MAC TX clock Consists of 48 bits seconds field 32 bits nanoseconds field and 16 bits fractional nanoseconds field Use this bus to carry the time of day from external ToD module to 96 bit MAC RX clock Consists of 48 bits seconds field 32 bits nanoseconds field and 16 bits fractional nanoseconds field tx_time_of_day 64b_data 64 Use this bus to carry the time of day from external ToD module to 64 bit MAC TX clock Consists of 48 bit nanoseconds field and 16 bit fractional nanoseconds field rx_time_of_day 64b_data
257. teret c has HARE NE H HER RE RR ER REN HER EP EIER 6 30 Triple Speed Ethernet System with LOOOBASE X Inter face cccsscssorsecossesssssossssensensorscess 6 31 Interface Siptialls P 7 1 liirssCi ETAT T O R 7 1 10 100 1000 Ethernet MAC Stati als issesssissancsnuidenhvvasocyisoebsoncusvaedonensntanisasicnassiselvnsdesasdedssserssnesuaitss 7 2 10 1 00 1000 Multiport Ethernet MAC Signal s c5sissspdosscssoseasviassansartsoresioracspuseracsresenaniienny 7 13 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS Signals 7 18 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS Signals 7 22 10 100 1000 Ethernet MAC with 1000BASE X SGMII PCS and Embedded PMA III M 7 24 10 100 1000 Multiport Ethernet MAC with 1000BASE X SGMII PCS and Embedded s T 7 27 1000BASE X SGMI PES Signals rst stints pr oiei otra itai i oderam cde tr eranak 7 36 1000BASE X SGMII PCS and PMA Sippals aiuieesesereitisrtate penc hori tto Qe r to ere br 7 41 jii 7 42 Avalon ST Recelye Interface cu sies acucase s nisu ob eri Ra Rb HH ertt brune ru uH vb e 7 42 Avalon ST Eranennt Interface siseses eisereen So nist eniin ul bae RR ei eR 7 44 GMIT Trans mil nno tonii Ieri EU t E a Oe eria EIS E dE Ren ERN aive 7 45 GMI Cg c
258. ters Dword Offset 0x00 0x17 UG 01008 2015 06 15 Dword Description Offset OxOE tx almost full RW Variable length almost full threshold of the transmit FIFO buffer Use the depth of your FIFO buffer to determine this threshold You must set this register to a value greater than or equal to 3 A value of 3 indicates 0 ready latency a value of 4 indicates 1 ready latency and so forth Because the maximum ready latency on the Avalon ST interface is 8 you can only set this register to a maximum value of 11 This threshold is typically set to 3 In 10 100 and 1000 Small MAC core variations this register is RO and the register is set to a fixed value of 3 OxOF mdio addrO 0x10 mdio_addrl e Bits 4 0 5 bit PHY address Set these registers to the addresses of any connected PHY devices you want to access The mdio addr0 and mdio_addr1 registers contain the addresses of the PHY whose registers are mapped to MDIO Space 0 and MDIO Space 1 respectively e Bits 31 5 unused Set to read only value of 0 0x11 holdoff_quant Bit 15 0 16 bit holdoff quanta When you enable the flow control use this register to specify the gap between consecutive XOFF requests e Bits 31 16 unused OxFFFF 0x12 0x16 0x17 Reserved tx_ipg_length e Bits 4 0 minimum IPG Valid values are between 8 and 26 byte times If this register is set to an invalid value the MAC still
259. th or type a 2 octet value equal to or greater than 1536 0x600 indicates a type field Otherwise this field contains the length of the payload data The most significant byte of this field is transmitted first e Payload Data and Pad variable length data and padding e Frame check sequence FCS a 4 octet cyclic redundancy check CRC value for detecting frame errors during transmission e An extension field Required only for gigabit Ethernet operating in half duplex mode The MAC function does not support this implementation O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any ee egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device spe
260. the Cyclone IV GX device families 15 RE RW Self clearing reset bit Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS function state machines comma detection function and 8b 10b encoder and decoder For normal operation set this bit to 0 asynchronous reset value Status Register Word Offset 0x01 Table 6 14 Status Register Bit Descriptions NNNM RENE RR NEN NENNNN ED CAPABILITY A value of 1 indicates that the PCS function supports extended registers 1 JABBER DETECT Unused Always set to 0 2 LINK STATUS RO A value of 1 indicates that a valid link is established A value of 0 indicates an invalid link If the link synchronization is lost a 0 is latched 3 AUTO NEGOTIATION RO A value of 1 indicates that the PCS function ABILITY supports auto negotiation 4 REMOTE FAULT Unused Always set to 0 5 AUTO NEGOTIATION RO A value of 1 indicates the following status COMPLETE i The auto negotiation process is completed The auto negotiation control registers are valid 6 MF PREAMBLE Unused Always set to 0 SUPPRESSION 7 UNIDIRECTIONAL_ RO A value of 1 indicates that the PCS is able to ABILITY transmit from MII GMII regardless of whether the PCS has established a valid link 8 EXTENDED_STATUS Unused Always set to 0 A
261. thernet MAC Versus Small MAC 3 10 100 1000 Ethernet MAC Versus Small MAC Table 1 1 Feature Comparison between 10 100 1000 Ethernet MAC and Small MAC Feature 10 100 1000 Ethernet MAC Small MAC Speed Triple speed 10 100 1000 Mbps 10 100 Mbps or 1000 Mbps External MII GMII or RGMII MII only for 10 100 Mbps small MAC GMII or interfaces RGMII for 1000 Mbps small MAC Control Fully programmable Limited programmable options The following interface options are fixed registers Maximum frame length is fixed to 1518 Jumbo frames are not supported e FIFO buffer thresholds are set to fixed values e Store and forward option is not available e Interpacket gap is set to 12 e Flow control is not supported pause quanta is not in use Checking of payload length is disabled e Supplementary MAC addresses are disabled e Padding removal is disabled e Sleep mode and magic packet detection is not supported Synthesis Fully configurable Limited configurable options The following options options are NOT available e Flow control e VLAN e Statistics counters e Multicast hash table e Loopback e TBI and 1 25 Gbps serial interface e 8 bit wide FIFO buffers High Level Block Diagrams High level block diagrams of different variations of the Triple Speed Ethernet MegaCore function About This MegaCore Function Altera Corporation J send Feedback 1 4 High Level Block Diagrams Figure 1 1 10 100
262. timestamp is obtained and a timestamp request is valid for the particular frame Assert this signal in the same clock cycle as the start of packet avalon_ st tx startofpacket is asserted tx egress timestamp 96b fingerprint Configurable width fingerprint that returns with correlated timestamps The signal width is determined by the TSTAMP FP WIDTH parameter default parameter value is 4 tx egress timestamp 64b data 64 A transmit interface signal This signal requests timestamp of frames on the TX path The timestamp is used to calculate the residence time Consists of 48 bit nanoseconds field and 16 bit fractional nanoseconds field tx egress timestamp 64b valid A transmit interface signal Assert this signal to indicate that a timestamp is obtained and a timestamp request is valid for the particular frame Assert this signal in the same clock cycle as the start of packet avalon_ st tx startofpacket Of avalon st tx startofpacket nis asserted tx egress timestamp 64b fingerprint Configurable width fingerprint that returns with correlated timestamps The signal width is determined by the TSTAMP FP WIDTH parameter default parameter value is 4 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 IEEE 1588v2 TX Timestamp Request Signals Table 7 31 IEEE 1588v2 TX Timestamp Request Signals IEEE 1588v2 TX Timestamp Request Signals 7 31
263. tination address when generating the 6 bit code Figure 4 4 Hardware Multicast Address Resolution Engine multicastnatch read add 5 0 Hash frame d stination x I Generate Look Up Table 64x1DPRAM di EEEZ Z age EE cS writeport Dep Functional Description C Send Feedback UG 01008 2015 06 15 Frame Type Validation 4 9 Table 4 1 Hash Code Generation Full Destination Address Algorithm for generating the 6 bit code from the entire destination address Hash Code Bit VELG xor multicast MAC address bits 7 0 xor multicast MAC address bits 15 8 xor multicast MAC address bits 23 16 xor multicast MAC address bits 31 24 xor multicast MAC address bits 39 32 xor multicast MAC address bits 47 40 gaj AeA Ol tt Table 4 2 Hash Code Generation Lower 24 Bits of Destination Address Algorithm for generating the 6 bit code from the lower 24 bits of the destination address Hash Code Bit Value 0 xor multicast MAC address bits 3 0 xor multicast MAC address bits 7 4 m xor multicast MAC address bits 11 8 xor multicast MAC address bits 15 12 xor multicast MAC address bits 19 16 xor multicast MAC address bits 23 20 a A N The MAC function checks each multicast address received against the hash table which serves as a fast matching engine and a match is returned within one clock cycle If there is no match the MAC function discards
264. tion or retrieve its status Note In MAC and PCS variations the PCS registers occupy the MAC register space and you access these registers via the MAC 32 bit Avalon MM control interface PCS registers are 16 bits wide they therefore occupy only the lower 16 bits and the upper 16 bits are set to 0 The offset of the first PCS register in this variation is mapped to dword offset 0x80 If you instantiate the IP core using the MegaWizard Plug in Manager flow use word addressing to access the register spaces When you instantiate MAC and PCS variations map the PCS registers to the respective dword offsets in the MAC register space by adding the PCS word offset to the offset of the first PCS For example e In PCS only variation you can access the i mode register at word offset 0x14 e In MAC and PCS variations map the i mode register to the MAC register space Offset of the first PCS register 0x80 e if mode word offset 0x14 e if mode dword offset 0x80 0x14 0x94 If you instantiate the MAC and PCS variation using the Qsys system access the register spaces using byte addressing Convert the dword offsets to byte offsets by multiplying the dword offsets by 4 For example e For MAC registers e comand config dword offset 0x02 e comand config byte Offset 2 0x02 x 4 2 0x08 e For PCS registers map the registers to the dword offsets in the MAC register space before you convert the dword offsets to byte offsets e if mode
265. tion to start reading from it The MAC function asserts the xx dsav signal when the buffer level hits this threshold Set this threshold to 0 to enable store and forward on the receive datapath In the store and forward mode the xx dsav signal remains deasserted The MAC function asserts the f rx dvalsignalas soon as a complete frame is written to the FIFO buffer 4 16 Transmit Thresholds Transmit Thresholds Figure 4 6 Transmit FIFO Thresholds Switch Fabric The remaining Frame Buffer n unwritten entries in the FIFO buffer Frame Buffer n 1 before it is full Almost full 7 Section Empty HN An early indication Frame Buffer k that the FIFO ee buffer is getting full Section full Almost empty gt Sufficient unread The remaining entries in the FIFO unread entries in Frame Buffer 2 buffer for the the FIFO buffer transmitter to start before it is empty Frame Buffer 1 transmission Network Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Table 4 7 Transmit Thresholds Almost empty tx almost empty Transmit FIFO Buffer Underflow 4 17 The number of unread entries in the FIFO buffer before the buffer is empty When the level of the FIFO buffer reaches this threshold the MAC function asserts the tx empty signal The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII MII RGMII error t
266. tner NEGOTIATION ABLE supports auto negotiation The reset value is 0 1 PAGE RECEIVE RO A value of 1 indicates that a new page is received with new partner ability available in the register partner ability The bit is set to 0 reset value when the system management agent performs a read access 2 NEXT PAGE ABLE Unused Always set to 0 15 3 Reserved If Mode Register Word Offset Ox14 Table 6 19 IF Mode Register Description SGMII ENA Determines the PCS function operating mode Setting this bit to 1 enables SGMII mode Setting this bit to 0 enables 1000BASE X gigabit mode 1 USE_SGMII_AN RW This bit applies only to SGMII mode Setting this bit to 1 causes the PCS function to be configured with the link partner abilities advertised during auto negotiation If this bit is set to 0 it is recommended for the PCS function to be configured with the se rr sPEED and SGMII_ DUPLEX bits 3 2 SGMII_SPEED 1 0 RW SGMII speed When the PCS function operates in SGMII mode scmr1_ENA 1 and programed not to be automatically configured USE_SGMII_AN 0 set the speed as follows e 00 10 Mbps e 01 100 Mbps e 10 1 Gigabit e 11 Reserved These bits are ignored when SGMIT_ENA is 0 or USE SGMII ANis 1 These bits are only valid if you only enable the SGMII mode and not the auto negotiation mode Altera Corporat
267. to 31 Not used 0x0 OxD2 tx adjust ns RW Static timing adjustment in nanoseconds for outbound timestamps on the transmit datapath e Bits 0 to 15 Timing adjustment in nanoseconds e Bits 16 to 23 Not used 0x0 0xD3 rx period RW Clock period for timestamp adjustment on the receive datapath The period register is multiplied by the number of stages separating actual timestamp and the GMII bus e Bits 0 to 15 Period in fractional nanoseconds Rx PERIOD FNS e Bits 16 to 24 Period in nanoseconds Rx PERIOD NS e Bits 25 to 31 Not used The default value for the period is 0 For 125 MHz clock set this register to 8 ns 0x0 0xD4 rx adjust fns RW Static timing adjustment in fractional nanoseconds for outbound timestamps on the receive datapath e Bits 0 to 15 Timing adjustment in fractional nanosec onds e Bits 16 to 31 Not used 0x0 Altera Corporation Configuration Register Space G send Feedback UG 01008 2015 06 15 IEEE 1588v2 Feature PMA Delay Dword Description HW Reset Offset rx_adjust_ns Static timing adjustment in nanoseconds for outbound 0x0 timestamps on the receive datapath e Bits 0 to 15 Timing adjustment in nanoseconds e Bits 16 to 23 Not used IEEE 1588v2 Feature PMA Delay PMA digital and analog delay of hardware for the IEEE 1588v2 feature and the register timing adjustment 1 UI is equivalent to 800 ps
268. turn SUCCESS See also tse mac setGMIImode tse mac SwReset Prototype int tse mac SwReset np tse mac pmac Thread safe No Available from No ISR Include triple speed ethernet iniche h Description The tse mac SwReset performs a software reset on the MAC function A software reset occurs with some latency as specified by ALTERA TSE SW RESET TIME OUT CNT The settings of the command con ig register are restored at the end of the function Parameter pmac A pointer to the MAC control interface base address Return SUCCESS Constants UG 01008 2015 06 15 Table 11 3 lists all constants defined for the MAC registers manipulation and provides links to detailed descriptions of the registers It also list the constants that define the MAC operating mode and timeout values Altera Corporation Software Programming Interface C Send Feedback UG 01008 2015 06 15 Table 11 3 Constants Mapping ALTERA S DUPLEX ODE DEFAULT Constants 11 11 1 0 Half duplex 1 Full duplex MAC_SP ED DEFAULT 0 0 10 Mbps 1 100 Mbps 2 1000 Mbps ALTERA TS SGDMA RX DESC CHAIN SIZI Lu 1 The number of SG DMA descriptors required for the current operating mode ALTERA_CH ECKLINK_TIMEOUT_THRESHOLD 1000000 The timeout val
269. tx ck Reset Synchronizer PCS PMA Reset Reset im Synchronizer Sequencer rx freglocked For more information about the rx_freqlocked signal and transceiver reset refer to the transceiver handbook of the respective device family Assert the reset or gxb pwrdn in signals to perform a hardware reset on MAC with PCS and embedded PMA variation Note You must assert the reset signal for at least three clock cycles Functional Description Altera Corporation LJ Send Feedback 4 40 Altera IEEE 1588v2 Feature see Figure 4 25 Reset Distribution in MAC with PCS and Embedded PMA reset gbx_pwrdwn Reset Reset Synchronizer Synchronizer Reset Sequencer Altera IEEE 1588v2 Feature The Altera IEEE 1588v2 feature provides timestamp for receive and transmit frames in the Triple Speed Ethernet MegaCore function designs The feature consists of Precision Time Protocol PTP PTP is a layer 3 protocol that accurately synchronizes all real time of day clocks in a network to a master clock This feature is supported in Arria V Arria 10 Cyclone V MAX10 and Stratix V device families IEEE 1588v2 Supported Configurations The Triple Speed Ethernet MegaCore functions support the IEEE 1588v2 feature only in the following configurations e 10 100 1000 Mbps MAC with 1000BASE X SGMII PCS and embedded serial PMA without FIFO buffer in full duplex mode e 10 100 1000 Mbps MAC with 1000BASE X SGMII PCS
270. tx etstamp ins ctl timestamp format Don t care 1 step Residence Time Update Input tx etstamp ins ctrl residence time update S es CN tx etstamp ins ctrl ingress timestamp 96b 95 0 Don t care tx etstamp ins ctr ingress timestamp 64b 6 0 ab tx etstamp ins ctrl residence time calc foomat t i O oO 1 step IPv4 and IPv6 Checksum Input tx etstamp ins ctrl checksum zero tx etstamp ins ctl checksum correct i 1 step Location Offset Input tx etstamp ins ctrl offset timestamp 15 0 Don t care tx etstamp ins ctrl offset correction fieldl ea i s S S tx etstamp ins ctrl offset checksum field 15 0 Don t care tx etstamp ins ctrl offset checksum correction 15 0 y Offset 2 i Figure 7 25 shows the TX timestamp signals for the IEEE 1588v2 feature in a two step operation When the tx egress timestamp request valid signal is driven high with a unique fingerprint the MAC returns an egress timestamp associated with that unique fingerprint The signals related to the 1 step operation can be driven low or ignored There is no modification to the packet content Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 IEEE 1588v2 Timestamp 7 51 Figure 7 25 Egress 2 Step Operation Egress Two Step Operation IEEE 1588v2 PTP Packet 2 step Timestamp Request Input
271. ue when the MAC tries to establish a link with a PHY ALTERA_AUTON EG TIMEOUT THRESHOLD 250000 The auto negotiation timeout value Command Config Register Command Config Register Dword Offset 0x02 on page 6 7 ALTERA TSEMAC CMD TX ENA OFS 0 Configures the Tx ENA bit ALTERA TSEMAC CMD TX ENA MSK 0x1 ENA_OFS Configures the Rx Ewa bit ENA MSK ALTERA TSEMAC CMD XON GEN OFST 2 Configures the xo GEN bit ALTERA TSEMAC CMD XON GEN MSK 0x4 ALTERA TSEMAC CMD ETH SPEED OFST 3 Configures the ETH_SPEED bit ALTERA TSEMAC CMD ETH SPEED MSK 0x8 ALTERA TSEMAC CMD PROMIS EN OFST 4 Configures the PROMIS EN bit ALTERA TSEMAC CMD PROMIS EN MSK 0x10 ALTERA_TSEMAC_CMD_PAD_EN_OFST 5 Configures the PAD EN bit ALTERA TSEMAC CMD PAD EN MSK 0x20 ALTERA TSEMAC CMD CRC FWD OFST 6 Configures the cnc Fwp bit ALTERA TSEMAC CMD CRC FWD MSK 0x40 Configures the Paus E E_FWD_MSK ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST 8 Configures the PAUSE_IGNORE ALTERA_TSEMAC_CMD_PAUSE_IGN
272. um frame length are truncated to the maximum frame length with additional bytes up to 12 CRC 32 is optionally discarded before the frames are received by the traffic monitor e Additional checks for configurations that contain the PCS function with optional embedded PMA Transmit frames generated by the frame generator are correctly encapsulated Received frames are de encapsulated before they are forwarded to the frame monitor Testbench Configuration The testbench is configured by default to operate in loopback mode Frames sent through the transmit path are looped back into the receive path Separate data paths can be configured for single channel MAC with internal FIFO buffers In this configuration the MII GMII Ethernet frame generator is enabled and the testbench control block simulates independent yet complete receive and transmit datapaths You can also customize other aspects of the testbench using the testbench simulation parameters The device under test is configured with the following default settings e Link speed is set to Gigabit except for configurations that contain Small MAC For Small MACs the default speed is 100 Mbps e Five Ethernet frames of payload length 100 101 102 103 and 104 bytes are transmitted to the system side interface and looped back on the ethernet side interface e Default settings for the MAC function The command con ig register is set to 0x0408003B Promiscuous mode is enabled Th
273. valon ST Description Signal Type data_rx_valid_n valid Receive data valid When asserted this signal indicates that the data on the following signals are valid data rx data n data rx sop n data rx eop n and data rx error n data rx data nh 7 0 data Receive data data rx sop nh data rx eop nh startofpacket endofpacket Receive start of packet Asserted when the first byte or word of a frame is driven on data rx data D Receive end of packet Asserted when the last byte or word of frame data is driven on data_ rx data n data rx ready n ready Receive application ready Assert this signal on the rising edge of data rx clk n when the user application is ready to receive data from the MAC function If the user application is not ready to receive data the packet is dropped or truncated with an error data rx error n 4 0 Susie Receive error Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame For the description of each bit refer to the description of bits 5 to 1 in MAC Receive Interface Signals on page 7 4 Bit 4 of this signal maps to bit 5 in the table and so forth Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 Multiport MAC Transmit Interface Signals Table 7 15 MAC Transmit Interface Signals Multiport MAC Transmit Interface Signals 7 15 Avalon ST 1 0 Descript
274. valon ST Transmit Interface Signals Table C 5 Avalon ST Transmit Interface Signals for ToD Clock es IR RN NN C NN time of day 64b Output Timestamp from the ToD clock e Bits 0 to 15 16 bit fractional nanosecond field e Bits 16 to 63 48 bit nanosecond field time_of_day_96b Output Timestamp from the ToD clock e Bits 0 to 15 16 bit fractional nanosecond field e Bits 16 to 47 32 bit nanosecond field e Bits 48 to 95 48 bit second field time_of_day_96b_load_valid Input Indicates that the synchronized ToD is valid Every time you assert this signal the synchronized ToD is loaded into the ToD clock Assert this signal for only one clock cycle time of day 96b load data time of day 64b load valid Input Input 96 Loads 96 bit synchronized ToD from master ToD clock to slave ToD clock within 1 clock cycle e Bits 0 to 15 16 bit fractional nanosecond field e Bits 16 to 63 32 bit nanosecond field e Bits 64 to 95 48 bit second field Indicates that the synchronized ToD is valid Every time you assert this signal the synchronized ToD is loaded into the ToD clock Assert this signal for only one clock cycle time of day 64b load data Input 64 Loads 64 bit synchronized ToD from master ToD clock to slave ToD clock within 1 clock cycle e Bits 0 to 15 16 bit fractional nanosecond field e Bits 16 to 63 48 bit nanosecond field period_clk Alt
275. ver Native PHY Signals on page 7 20 Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 1000BASE X SGMII PCS and PMA Signals Figure 7 9 1000BASE X SGMII PCS Function and PMA Signals GMII Signals MII Signals Clock Enabler Signals MII GMII Clock Signals SGMII Status Signals PN 1000BASE X SGMII PCS Function With Embedded PMA gmii tx d 7 0 gmii tx en gmii tx em gmii rx d 7 0 gmii rx dv gmii rx eim mii tx d 3 0 mii tx en mii tx etr mii rx d 3 0 mii nx dv mii rx eir mii col mii cs Ix dkena tx dkena x dk tx dk set 10 t set 100 set 1000 hd ena reset rx ck reset tx ck reset ref ck p tx p led an led cs led col led char er led link led panel link led disp em gxb cal blk dk pcs pwrdn out gxb pwrdn in reconfig_clk reconfig_togxb reconfig_fromgxb rx_recovclkout reconfig_busy dk address 4 0 write read writedata 15 0 readdda 15 0 waitrequet Notes to Figure 7 9 1 The clock enabler signals are present only in SGMII mode 2 The SERDES control signals are present in variations targeting devices with GX transceivers For Stratix II GX and Arria GX devices the reconfiguration signals reconfig_clk reconfig togxb and reconfig fromgxb are included only when the option Enable transceiver dynamic reconfigu ration is turned on The reconfiguration signals 9gxb cal blk clk
276. ver handbook of the respective device family Latency ns PCS Configuration PCS with GX transceivers 10 Mbps SGMII 3368 2489 100 Mbps SGMII 488 335 1000 Mbps SGMII 184 135 1000BASE X 24 40 PCS with LVDS Soft CDR I O 10 Mbps SGMII 3600 2344 100 Mbps SGMII 440 344 1000 Mbps SGMII 192 184 1000BASE X 40 104 SGMII Converter You can enable the SGMII converter by setting the SGMII_ENA bit in the i mode register to 1 When enabled and the usz_scm11_an bit in the i mode register is set to 1 the SGMII converter is automatically configured with the capabilities advertised by the PHY Otherwise Altera recommends that you configure the SGMII converter with the SGMII_SPEED bits in the i mode register In 1000BASE X mode the PCS function always operates in gigabit mode and data duplication is disabled Transmit In gigabit mode the PCS and MAC functions must operate at the same rate The transmit converter transmits each byte from the MAC function once to the PCS function Altera Corporation Functional Description G send Feedback UG 01008 2015 06 15 Receive 4 33 In 100 Mbps mode the transmit converter replicates each byte received by the PCS function 10 times In 10 Mbps the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times Receive In gigabit mode the PCS and MAC functions must operate at the same rate The trans
277. wer Down 2015 06 15 Figure 4 21 Serial Loopback 1000BASE X PCS j SERDES i PCS Transmit i SERDES Tod P serial Transmit i Transmit gt SERDES PCS Receive q Receive I Serial Receive Control i m sd loopback i MDIO Slave Ten bit nterface PHY Power Down Power down is controlled by the PowzRDowN bit in the PCS cont rol register When the system management agent enables power down the PCS function drives the powerdown signal which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity When the PHY is in power down state the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored The management interface remains active and responds to management transactions from the MAC layer device Figure 4 22 Power Down 1000BASE X PCS Powerdown Control Technology Spedific Conti powerdown 4 DIO ave Power Down in PCS Variations with Embedded PMA In PCS variations with embedded PMA targeting devices with GX transceivers the power down signal is internally connected to the power down of the GX transceiver In these devices the power down functionality is shared across quad port transceiver blocks Ethernet designs must share a common gbx_pwrdn_in signal to use the same quad port transc
278. word offset 0x14 e if mode dword offset 0x80 0x14 0x94 e if mode byte offset 0x94 x 4 0x250 Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Table 6 12 PCS Configuration Registers 6 19 PCS Configuration Register Space Word Register Name R W Description Offset 0x00 control RW PCS control register Use this register to control and configure the PCS function For the bit description see Control Register Word Offset 0x00 on page 6 20 0x01 status RO Status register Provides information on the operation of the PCS function 0x02 32 bit PHY identification register This register is set to EE cO RO the value of the PHY ID parameter Bits 31 16 are zum eee written to word offset 0x02 Bits 15 0 are written to word offset 0x03 0x04 dev ability RW Use this register to advertise the device abilities to a link partner during auto negotiation In SGMII MAC mode the PHY does not use this register during auto negotia tion For the register bits description in 1000BASE X and SGMII mode see 1000BASE X on page 6 23 and SGMII PHY Mode Auto Negotiation on page 6 25 0x05 partner ability RO Contains the device abilities advertised by the link partner during auto negotiation For the register bits description in 1000BASE X and SGMII mode refer to 1000BASE X on page 6 23 and SGMII PHY Mode Auto Negotiation on page 6 25 respectively 0x06 an e
279. words to 10 bit symbols to generate a DC balance and ensure disparity of the stream with a maximum run length of 5 Altera Corporation Functional Description C Send Feedback UG 01008 2015 06 15 Receive Operation 4 31 Receive Operation The receive operation includes comma detection decoding de encapsulation synchronization and carrier sense Comma Detection The comma detection function searches for the 10 bit encoded comma character K28 1 K28 5 K28 7 in consecutive samples received from PMA devices When the K28 1 K28 5 K28 7 comma code group is detected the PCS function realigns the data stream on a valid 10 bit character boundary A standard 8b 10b decoder can subsequently decodes the aligned stream The comma detection function restarts the search for a valid comma character if the receive synchroniza tion state machine loses the link synchronization 8b 10b Decoding The 8b 10b decoder performs the disparity checking to ensure DC balancing and produces a decoded 8 bit stream of data for the frame de encapsulation function Frame De encapsulation The frame de encapsulation state machine detects the start of frame when the I S sequence is received and replaces the S with a preamble byte 0x55 It continues decoding the frame bytes and transmits them to the MAC function The T R R or the T R sequence is decoded as an end of frame A V character is decoded and sent to the MAC function as frame error
280. x err 5 0 rx err stat 17 0 rx frm type 0 ff rx dsav ff rx dval ff tx a full ff tx a empty Xon gen xoff gen magic sleep n magic wakeup clk reg_addr 7 0 reg wr reg rd reg data in 31 0 reg data out 31 0 reg busy reset 4 ref clk 4 xp txp ledan led crs led col gt led char err led link led panel link led disp err mdio in md mdio oen mdio out cdr_ref_clk_n mac eccstatus 1 0 rx recovclkout xb cal blk clk pcs pwrdn out gxb pwrdn in reconfig clk reconfig_togxb reconfig_fromgxb Reset Signal 1 25 Gbps Serial Signals Status LED Signals PHY Sauter Signals Transceiver Native PHY Signal ECC Status Signal SERDES Control Signals 1 The SERDES control signals are present in variations targeting devices with GX transceivers For Stratix II GX and Arria GX devices the reconfiguration signals reconfig_clk reconfig togxb and reconfig fromgxb are included only when the option Enable transceiver dynamic reconfigu ration is turned on The reconfiguration signals gxb cal blk clk pcs pwrdwn out Altera Corporation Interface Signals C Send Feedback UG 01008 2015 06 15 1 25 Gbps Serial Interface 7 25 gxb pwrdn in reconfig_clk and reconfig_busy are not present in variations targeting Arria 10
281. x sop n data rx eop n data rx error n 4 0 data rx ready n data rx valid n pkt dass valid n pkt dass data n 4 0 rx afull channel CHANNEL WIDTH 1 0 rx afull data 1 0 rx afull valid rx afull clk Xon gen n xoff gen n magic sleep n n magic wakeup n clk reg addi 0 reg wr reg rd reg data in 31 0 reg data out 31 0 reg busy reset rx ck n tx dk n IX dkena n tx dkena n gm rx d n 7 0 gm rx dv n gm rx err n gm tx d n 7 0 gm tx en n gm tx err n rgmii in n 3 0 rx control n rgmii out n 3 0 tx control n Tx d n 3 0 mmrxdvn m rx er n m col n m cs n m tx d n 3 0 mtxenn m tx err n mdio in mdc mdio oen mdio out set 10 n set 1000 n ena 10 n eth mode n mac eccstatus 1 0 PUT TIT TATA RB TAT Reset Signal Clock Signals GMII Signals RGMII Signals MII Signals PHY Management Signals MAC Status Signals ECC Status Signal Altera Corporation 7 14 Multiport MAC Clock and Reset Signals Multiport MAC Clock and Reset Signals Table 7 13 Clock Signals UG 01008 2015 06 15 Avalon ST Description Signal Type mac_rx_clk Receive MAC clock 2 5 25 125 MHz for the Avalon ST receive data and receive packet classification interfaces mac tx clk elik Transmit MAC clock 2 5 25 125 MHz for the Avalon ST transmit data interface Multiport MAC Receive Interface Signals Table 7 14 MAC Receive Interface Signals A
282. x15 disable read timeout RW Bit 0 Set this bit to 1 to disable PCS register read timeout Bits 31 1 unused Set to read only value 0 0x16 read_timeout RO Bit 0 PCS register read timeout indication Valid only when disable read timeout is set to 0 This bit is cleared after it is read The PCS function sets this bit to 0 when the register read ends normally and sets this bit to 1 when the register read ends with a timeout Bits 31 1 unused 0x17 OxlF Reserved Control Register Word Offset 0x00 Table 6 13 PCS Control Register Bit Descriptions A NN 0 4 Reserved Altera Corporation Configuration Register Space C Send Feedback UG 01008 2015 06 15 Control Register Word Offset 0x00 6 21 Eel eem TERT UNIDIR ECTIONAL_ ENABLE Enables the unidirectional function This bit depends on bit 12 When bit 12 is one this bit is ignored When bit 12 is zero bit 5 indicates the unidirectional function e A value of 1 enables transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established e A value of 0 enables transmit from media independent interface only when the PHY has determined that a valid link has been established The reset value of this bit is zero SPEED SELECTION RO Indicates the operating mode of the PCS function Bits 6 and 13 are
283. x_data DATAWIDTH 1 0 m gt fitcomodi o fftxsop tbi rx clk 4 i Ten Bit CAE tbir d Interface i fftxer tbi tx dk C Signal MAC Transmit Ignats Interface Signals ffx wren tbi tx d 9 0 n P ff tx crc fwd tx ff uflow z fftxrdy ledan 5 ff tx septy led_crs T 4 ff tx a full led col gt a 4 fftx a empty led char err gt Signals led_link gt ffrx dk led panel link 4 ffnordy led disp er ff_rx_data DATAWIDTH 1 0 mdio in T ii mdc Mas ement PESE ios mdio oen gt Signals i LT eop mdio out MAC Receive Interface Signals 7 er 5 0 lt n err stat 17 0 p 18 rx frm type 3 0 tx serial clk 4 ff rx dsav l rxcdr_refcdk 4 i ff rx dval tx analogreset 4 4 ff nx a full tx digitalreset lt _ ffrx a empty nanalogreset Arria 10 m 7 rx_digitalreset e Transceiver Native PHY xon gen tx cal busy Signals Pause and Magic gt xoff gen rx cal busy gt Packet Signals magic sleep n IX set locktodata 4 magic wakeup rx set locktoref E rx is locktodata 9 dk rx is locktoref gt 7 address 7 0 mE FCC MAC Control write pcs_eccstatus 1 0 gt Status Interface gt read Signal Signals gt writedatq31 0 sd loopback SERDES readdata 31 0 D sidoin ontro
284. xpansion RO Auto negotiation expansion register Contains the PCS function capability and auto negotiation status 0x07 device next pag 0x08 partner_next_page The PCS function does not support these features RO These registers are always set to 0x0000 and any write 0x09 master slave cntl access to the registers is ignored Ox0A master slave stat 0x0B Reserved OxOE OxOF extended status RO The PCS function does not implement extended status registers Specific Extended Registers 0x10 scratch RW Scratch register Provides a memory location to test register read and write operations Oxll rev RO The PCS function revision Always set to the current version of the MegaCore function Configuration Register Space C Send Feedback Altera Corporation 20 Control Register Word Offset 0x00 UG 01008 2015 06 15 Word Register Name Description Offset 0x12 0x13 0x14 link timer if mode RW RW 21 bit auto negotiation link timer Set the link timer value from 0 to 16 ms in 8 ns steps 125 MHz clock periods The reset value sets the link timer to 10 ms Bits 15 0 are written to word offset 0x12 Bit 0 of word offset 0x12 is always set to 0 thus any value written to it is ignored Bits 20 16 are written to word offset 0x13 The remaining bits are reserved and always set to 0 Interface mode Use this register to specify the operating mode of the PCS function 1000BASE X or SGMII 0

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