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RIC User's Manual

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1. Table 2 7 Miscellaneous Signals Signal Name Internal Signal Pin I O Driver Description Name Count SBUS_CLK isbus_clk 1 I BINO4T 25 Mhz input clock SBUS RST L isbus_rst_ 1 I PINC10T SBus Reset from U2S ENET_CLK ienet_clk 1 I BIN10T 10 Mhz clk for reset counter 2 8 RIC Pin Count Table 2 8 RIC Pin Count Subblock In Out Total Reset 3 3 6 Interrupt 41 7 48 Scan 15 20 35 Clock Control 12 3 15 PAL Block 11 6 17 Misc 3 0 3 Subtotal 85 39 124 Vec VDD Gnd 36 Total 160 Sun Microelectronics 13 RIC User s Manual Sun Microelectronics 14 LA II RIC Functional Description 3 1 RIC Overview This chapter contains the functional description of the RIC chip at the top level Overall features of the chip functional description of each major sub block are discussed RIC chip contains five major modules The five modules are Reset Interrupt Concentrator Scan Control Clock Control PAL block There are no major data paths between any of these blocks Sun Microelectronics 15 RIC User s Manual 3 2 Detailed Internal Block Diagram CHIP BOUNDARY interrupts sbus_clk 6 int num 5 0 s Interrupt Concentrator sbus_rst_ slavio rst jtag controls Scan Control tms 8 1 4 JTAG Interface tdi 8 1 m ziek tdil 15 Internal Scan Ring Logic scan por xir
2. power_ok_ POR CES butt por p button scan por button POR oporout butt xir H x button button scan xir XIR Figure 4 2 Reset Block 4 1 3 Reset Logic Gate Count Estimates The current gate equivalent for the reset block is approximately 600 gate equiva lents Sun Microelectronics 21 RIC User s Manual 4 2 Signal Descriptions The reset block diagram looks as follows clk ibutt_por_ ibutt_xir_ ipower_ok_ oporout_ scan_por_ scan xir H gt op_button_ H gt osys_por_ H gt ox_button_ RIC_Reset Figure 4 3 RIC_Reset Table 4 1 Input Output Signals of Reset Logic Signal Name Signals I O Description ipower_ok_ 1 I Signal asserted during power on ibutt_por_ 1 I Signal asserted by push button switch scan_por 1 I Signal asserted by Scan Controller oporout_ 1 I Signal asserted by PAL block ibutt_xir_ 1 I Signal asserted by push button switch scan_xir 1 I Signal asserted by Scan controller ienet clk 1 I 10 mhz clock OSyS por 1 Signal to SC during power on reset op button 1 Signal to SC asserted during push button power reset ox button 1 O Signal to SC asserted during push button XIR Sun Microelectronics 22 4 Reset Block 4 3 Reset Logic Functional Description The following sections give a detailed description of all the sub blocks associated with reset generation logic 4 3 1 POR Description
3. SLAVIO RIC Chip System Block Diagram SBus_0 SBus_1 SBus_2 SBus_3 UPA Graphics 2 UPA Graphics 1 Sun Microelectronics 3 RIC User s Manual 1 4 RIC Chip Overview The RIC Chip includes five major functional modules The five modules are Re sets Interrupt Scan Clock Control and the PAL block The five modules are completely independent of each other and can be imple mented in separate chips 1 4 1 Resets The reset logic generates an asynchronous power on reset signal to the system controller SC from the power ok signal from the power supply It also generates the p_button_ reset to SC when a signal is received from a power on reset button or scan_por_ signal from scan logic A x_button_ reset is generated to SC if the XIR_ reset button is pressed or a scan_xir_ signal is received from the scan logic 1 4 2 Interrupt This interrupt module collects all the interrupts from SBus devices EBus devices and UPA expansion devices It will send the interrupt number binary encoded to U2S on a round robin basis The best case latency from detecting an interrupt and sending it to U2S is five Sbusl clocks 1 4 3 Scan The scan module directs the flow of the serial scan chains at the system level It receives the scan chain identification from the service controller and directs the corresponding scan input to the scan output It also implements a separate scan chain t
4. sys por power ok p button button por Resets x button button xir opor out Ebus Signals Hu a PAL Block Chip Selects cpu pda clk_sel Clock Control Figure 3 1 RIC Chip Block Diagram Sun Microelectronics 16 3 RIC Functional Description 3 3 Block Overviews The following chapters describe each functional block in detail These chapters are organized as follows 3 3 1 Resets This block is responsible for generating resets to the System Controller It gener ates three different resets Power On Reset Button POR and Button XIR The as sertion and de assertion of all the resets are asynchronous to the system clock This block can receive resets from external power detect logic on AC power on POR and XIR resets from external switch button and from the internal Scan Con troller block 3 3 2 Interrupt Concentrator The function of the Interrupt Concentrator block is to detect any active interrupt coming from any of the sbus slots SLAVIO or UPA expansion ports generate the interrupt source number and deliver it to the U2S This block does not communi cate with any other blocks in the chip 3 3 3 Scan Controller The function of the Scan Controller is to act as an interface between a remote ser vice processor and the Unit under test UUT It supports the JTAG Bus proto col It controls the scan rings for all the
5. button_por_ Mr p button scan por oporout_ e D B J ES enet_clk gt Figure 4 6 Button_POR Detailed Block 4 3 2 3 Button POR State Descriptions The button por signal coming from the switch will go through a debouncer cir cuit and combinatorial logic before it goes into a flip flop So when scan por or button por are asserted the flip flop will assert the p button for at least 1 clock cycle 4 8 2 4 Button POR Timine Diagram enet_clk button por p button Figure 4 7 Button POR Timing Sun Microelectronics 25 RIC User s Manual 4 3 3 Button_XIR Description 4 3 3 1 Overview The Button_XIR block is responsible for generating a reset when it gets a signal from lab console button xir reset switch or a SCAN_XIR command from Scan controller 4 3 3 2 Button_XIR Block Diagram debouncer button xir x button ee scan_xir sbus_clk Figure 4 8 Button_XIR Detailed Block 4 3 3 3 Button_XIR State Descriptions The button_xir_ signal coming from the switch will go through a debouncer cir cuit and combinatorial logic before it goes into a flip flop So when scan_xir or button_por_ are asserted the flip flop will assert the p_button_ for at least one clock cycle Sun Microelectronics 26 4 3 3 4 Button_XIR Timing Diagram enet clk button xir
6. oxorout 1 O Xor Output Not Shown above Sun Microelectronics 68 8 PAL Block 8 2 PAL Block Function Descriptions 8 2 1 PAL Logic The PAL logic decodes the Ebus signals coming in to provide access to the SC address and data resgister Lab Console address and data registers see Note the frequency margining Motorola MC12429 amp MC12439 chips and address range to write to the Flash PROM Slavio only provides read access Note It was decided not to implement the Lab Console in the UltraSPARC systems although the support exists in the RIC PAL Block The Address map for the PAL logic is shown in the table below Table 8 2 PAL logic Addess Map Address Range Description 0x0 0000 SC Address Register 0x0 0004 SC Data Register 0x0 2000 Lab Console Address Register Not Used 0x0 2001 Lab Console Data Register Not Used 0x0 4000 Freq Margining Serial Load and Reset 0x0 4001 Freq Margining serial load 0x0 4002 Freq Margining serial data in 0x8 0000 OXF FFFF Prom write address 8 2 2 XOR gate Addtionally the RIC chip make an xor gate available to select between the POST and OBP parts of the PROM Sun Microelectronics 69 UltraSPARC User s Manual Sun Microelectronics 70 Index A console accesses 65 address map 68 CPU Speed 63 Address Register 54 D Addresses 2 data register 55 AG Internal Scan Ring 55 De assertio 2 Assertion 2 Decode 65 B Dispatcher 29 39
7. Sun Microelectronics Contents 1 A O RT 1 IN AA tete ee tee er bietet 1 1 2 D finition of Terms eerte ti dere tee deett BEA eret 2 1 9 Partition Overview cedi e tee t ie ete tete ete 3 14 RIC Chip Overview nnen ensen eren nennen ran nr nr nn rananannnn tenete tenent 4 Pin Descriptions uoo cnet alias 7 Zl I O Driver Specifications nes eee Intendente 7A 22 Resets Interface Signalga irna ea hired ANR eaea 8 2 3 Interrupt Concentrator Interface Signals EE 9 24 Scan Interface Signalga isea etie ie bete teet caca 10 25 Clock Controller Interface Signals enee 11 2 67 PAL Block Signals so deese ii 12 2 7 Miscellaneous Signals ee 13 2 97 RIC Pin Count rennend etensbak 13 RIC Functional Description sees eee eee eee nennen 15 31 RIC OVERVIEW egene 15 3 2 Detailed Internal Block Diagramm 16 3 3 BlOck Overviews coins ii desatar 17 Reset Block ico arte 19 KENE Wi ete dio e ai debe p i edit en iu deret d 19 4 2 Signal DesriptonS eserini eeo e tenente nennen nnne 22 4 3 Reset Logic Functional Description nana ene nennen senen ensenensenenenenenenseneneneneesen 23 Sun Microelectronics iii RIC User s Manual 5 Interrupt Concentrator ENEE b COVOeEVIe WC oes a t tet e tea n Ck lies PALS el oe 5 27 Signal Descriptions ee ee hee E iones EEE OR 5 3 Interrupt Concentrator Functional Description sss Scan Controller eee raro A ata pe ierit ice diesen iterat 6 1 e eee nee atte rie ere repeti
8. int en 20 done6 1 TRANSITIONS DDI If int_prel DDI2 If int_pre2 DDI3 If int_pre3 DDI4 if int_pre4 DDI5 if int_pre5 DIDI default 5 Interrupt Concentrator 5 3 2 6 Dispatcher Timing Diagram sbus clk int prel int pre4 wpe A 3 3 X amp 3 93 pon 4 5 state didl ddil X did2 Y m X did5 X ddi2 AS did3 X int_sel Y 001 Y E X 100 Y Y 010 Y Ee Y donel i j j done A i r E Wo nan EN int ena int out DI YN mmm mu X 001000 Figure 5 9 Dispatcher Timing Sun Microelectronics 45 RIC User s Manual Sun Microelectronics 46 Scan Controller 6 6 1 Overview The scan controller is used for controlling the scan rings on the system mother boards The major goal is to provide an efficient debug and test tool that could be used by both engineering and manufacturing personnel 6 1 1 Scan Controller Overview The Scan Controller has two major blocks associated with it JTAG Interface and JTAG Internal Scan Ring Clock Interrupt Control Concentrator Resets Scan porscan xir OSys por jtag controls new_tdo tdo_o stck Scan ED Controller EED BLS osys_por_ tck tck_o Figure 6 1 Scan Controller System Block Sun Microelectronics 47 RIC User s Manual new stdo istas e oe e JTAG ISFESt el
9. 6 3 2 3 JTAG Scan Ring Register Scan Ring Register Table 6 4 JTAG Scan Ring Data Instruction Register Field Bits Description R W N A 07 03 Not Used RW Reserved 02 Reserved for future use RW POR 01 Scan Power On Reset RW XIR 00 Scan XIR reset RW The JTAG Scan Ring Register provides data to be loaded into the clock counter and control bits to generate resets 6 3 2 4 JTAG FSM State Description Table 6 5 Jtag state machine State Description Test reset Logic Test logic disabled Run Test Idle Controller State between scan operations Select DR Scan Test data selected by the current inst retains their previ ous state Capture DR Data may be parallel loaded into test data registers Shift DR Data register shifts data one stage Exit DR Terminates scanning process Pause DR Allows shifting of test data register Exit2 DR Scanning process terminates Update DR Data register will be provided with latched parallel out put Sun Microelectronics 56 6 Scan Controller 6 3 2 5 JTAG FSM State Diagram TMS 1 Dummy State TMS 1 Select DR S r Run test Idle A N Gi Se TMS TMS 1 Y Ges TE Capture DR TMS 0 Shift DR YO ou Z TMS 0 TMS 1 LU Exitl DR TMS 1 TMS 0 ar Y Exit2 DR TMS 1 Update DR TMS 1 TMS 0 Figure 6 8 JTAG State Machine S
10. Interface gt tek ist n amp new tms 8 1 smp_ Control new tdo tdi 8 1 SA tdi 15 tms 15 Y Y E JTAG Internal Scan Ring ro E A ga L m scan xir stclk Figure 6 2 Scan Controller Block Diagram 6 1 2 Scan Controller Gate Count Estimates The current gate count for the scan controller is 500 gate equivalents Sun Microelectronics 48 6 2 Signal Descriptions 6 Scan Controller The block diagram for the scan controller can be shown as follows ismp DA isrest_ gt istas 4 istdi 5 pok tap gt H po 4 stelk ESA idi 8 1 9 Figure 6 3 Scan Control int trst new stdo new tdo nem tms 8 1 scan por scan Xir tdo 0 ml 0 trst Scan Control Sun Microelectronics 49 RIC User s Manual 6 3 Scan Controller Functional Description Table 6 1 Scan Controller Signals Signal Name Signals I O Description ismp_ 1 I Service Processor Present signal isrest_ 1 I Test Reset for Scan from Service Processor istas_ 1 I Test Address Strobe from Service Processor istdi 1 I Test data in for Scan from Service Processor istms 1 I Test Mode Select for Scan from Service processor pok_tap_ 1 I Power Ok tap same signal as ipower_ok_ por_ 1 I Power On Reset from reset block same signal as osys por stclk 1 I Test Clock for Scan from Service processor tdi 8 1 8 I Test Data from ASICS
11. Microelectronics 66 8 1 2 Signal Descriptions The Block diagram for the PAL Block can be shown as follows notEBusChipSelect natPrenChipSelectIn clock eBusAddress 14 H1 gt clockednotLabConsoleBoerdSelect gt ec lockednotSCChipSelect gt clockednoteBusReady elockednotporOut natERusilrite clockedserialClock clackedseriallaad reset notPranChipSelectOut risc_pal Figure 8 2 RIC_PAL These signals connect from the PAL Block to the IO cells 8 PAL Block Table 8 1 PAL Block signal descriptions Signal Name Signals I O Description clock 1 I Sbus Clock eBusAddess 5 I Ebus Address 19 14 13 1 0 notEbusChipSelect 1 I Ebus Chip Select notEbusWrite 1 1 EbusWrite norPromSelectIn 1 1 PROM Chip Select In reset 1 1 SBus reset ClockednotLabConsoleBoardSelect 1 O Lab Console Board Select clockednotSCChipSelect 1 O SC ChipSelect clockednotEbusReady 1 O Ebus Ready clockednotporOut 1 O Reset signal oporout_ to reset block clockedserialClock 1 O Serial Clock out for Freq chip clockedserialLoad 1 O Serial Load out for Freq chip Sun Microelectronics 67 UltraSPARC User s Manual Table 8 1 PAL Block signal descriptions Signal Name Signals I O Description notPromChipSlectOut 1 O PROM Chip Select Out ixorin1 1 I Xor Input 1 Not Shown above ixorin2 1 I Xor Input 2 Not Shown above
12. PAL Signals 12 Partition 3 POR 2 19 23 55 POR State 24 POR Timing 24 Power on Reset 2 PRO 5 PROM 65 68 R Reset Block 19 21 reset block 21 22 Reset Circuit 20 Reset Logic 19 reset logic 19 Resets 4 8 16 17 RIC 1 2 8 9 10 15 19 29 51 59 RIC Gate Counts 18 Ric Intcon 31 RIC_Clogen 62 RIC_PAL 66 RIC_Reset 22 S SC 2 SC chip 65 Scan 4 Scan Controller 17 47 Scan Controller Signals 50 Scan Controller Timing 58 Scan Interface Signals 10 scan rings 47 Scan service processor 10 Scan Control 49 Signal Descriptions 31 49 state machine 33 state machines 39 sub blocks 23 X system clock frequency 61 System clock select 63 System Controller 2 system controller 19 T TAS signal 59 TMS 51 58 TMS lines 59 TMS ring 58 U U2S 2 19 29 Uniform Port Architectur 2 Unselected Rings 58 UPA 2 W word 2 X XIR 2 55 XOR gate 5 68 Xor Gate 65 Index Sun Microelectronics 73 RIC User s Manual Sun Microelectronics 74
13. before any encoding is done This has to de done to simplify the encoding logic Each subgroup is comprised of a state machine and some combinatorial logic to do the arbitration The state machine uses round robin arbitration scheme to service an interrupt Once the interrupt source has been determined the interrupt number will be loaded into a register associated with that particular sub group Also an interrupt valid signal is asserted to inform the dispacher second stage state machine Sun Microelectronics 33 RIC User s Manual 5 3 1 2 Encoder Block Diagram donel interrupt 6 0 done2 interrupt 13 7 done3 interrupt 20 14 done4 interrupt 27 21 done5 interrupt 34 28 done6 interrupt 40 35 Figure 5 4 Sun Microelectronics 34 enl fsm pre st1 3 0 int_prel logic int num1 5 0 en2 fsm pre st2 3 0 int pre2 logic int num2 5 0 en3 fsm pre st3 3 0 int pre3 logic int num3 5 0 en4 fsm pre st4 3 0 int pre4 logic int num4 5 0 en5_fsm pre_st5 3 0 int_pre5 logic int num5 5 0 en6_fsm Encoder Block int pre6 pre st6 3 0 logic m int num6 5 0 5 Interrupt Concentrator 5 3 1 3 EN1_FSM State Descriptions The state machine cou
14. high to allow the clock controller to function correctly even though only two or three processor modules are connected Interrupt Scan Reset Block Control Control Clock clk_sel Controller x Figure 7 1 Clock Controller System Block Sun Microelectronics 61 RIC User s Manual 7 1 1 Clock Controller Gate Count Estimates The current gate count for the Clock controller is fifty gate equivalents 7 1 2 Signal Descriptions The block diagram for the clock controller can be shown as follows Figure 7 2 cpu_spl 2 cpu_sp2 2 cpu_sp3 2 cpu_sp4 2 RIC_Clogen clk sell2 01 These signals connect from the clock controller to the IO cells Table 7 1 Clock Controller signal descriptions Signal Name Signals I O Description icpu spl 3 I Speed Inputs from CPU module 1 icpu sp2 3 I Speed Inputs from CPU module 2 icpu sp3 3 I Speed Inputs from CPU module 4 icpu sp4 3 I Speed Inputs from CPU module 4 clk sel 3 O Selection Code to the Clock chip Sun Microelectronics 62 7 2 Clock Controller Function Descriptions 7 2 1 CPU Speed Selection 7 Clock Controller Each CPU module sends three signals to the clock generator chip to state what is the speed of the CPU Based on that information from all the CPUs the CPU speed selection determines the system speed by selecting the slowest CPU speed It then sends the th
15. int num 1 int pre2 E Z _ en2 f m ES int num 2 a dispatch E int pre3 y S 7 sm _ en3 I fsm l log int_num 3 S int pre4 7 en4 T y om log int num 4 int pre5 Reg en5 g E 7 Bl fan log int_num 5 Y R 1 MUX 7 in int pre int num 6 7 fsm lo g Y sbus clk int_num 5 0 Figure 5 2 Interrupt Concentrator Block 5 1 3 Interrupt Concentrator Gate Count Estimates Current gate count is approximately 1800 gate equivalents Sun Microelectronics 30 5 2 Signal Descriptions The Interrupt controller block can be shown as follows clk iaudio intl ieth int iflop int igra intl igra int2 ikey int ipar int ipfail int isbusO 6 0 isbus1 6 0 isbus2 6 0 isbus3 6 0 iscsi int iskey int ismou int ispare int gt isser_int Figure 5 3 Ric Intcon RIC Intcon oint_num 5 0 osiavio_rst_ 5 Interrupt Concentrator Sun Microelectronics 31 RIC User s Manual Table 5 1 Interrupt Signals Signal name Signals I O Description isbus clk 1 I 25 Mhz input clock jaudio int 1 I interrupt from audio device ieth_int_ 1 I interrupt from ethernet iflop_int 1 I interrupt from a floppy device igra_intl_ 1 I interrupt from on board graphics igra_int2_ 1 I interrupt from graphics mod ikey_int 1 I interrupt form key board ipar_int_ 1 I interrupt from parallel port ipfail_int_ 1 I interrupt from power supply isbusO int 6 0 7 I interrupts from sb
16. int numl1 5 TRANSITIONS EID7 go to EID7 state and wait for the next interrupt If done go to EID7 EDI6 default EDIT First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1 int numl1 6 TRANSITIONS EIDS go to EID3 state and wait for the next interrupt If done go to EID1 EDI7 default Sun Microelectronics 38 5 Interrupt Concentrator 5 3 1 6 Encoder Timing Diagrams sbus_clk intl int5 xxx X eidl state X int prel donel ld ena int num 000000 x 000101 Figure 5 6 Encoder 1 Timing 5 3 2 Dispatcher Description 5 3 2 1 Overview The dispatcher state machine basically dispatches the active interrupt to the U2S chip As with the enoder state machine this state machine also uses round robin algorithm to select an active interrupt to be serviced Potentially there could be six interrupts active from the stage one encoder state machines Once the dis patcher selects the interrupt source it loads its interrupt register with the inter rupt number from the appropriate sub group On the next clock cycle the interrupt number is driven on the bus for U2S to service Also the dispatcher gen erates a done signal for the first stage so that the encoder state machine first stage can continue with its arbitration This
17. on UUT int trst 1 O Internal trst for the internal tap ring 15 new_stdo 1 O Test data out for Scan to Service Processor new_tdo 1 O Test data out to all ASICS on brd new_tms 8 1 8 O Test Mode select for ASICS scan_por_ 1 O scan power on reset scan xir 1 O scan xir reset tdo_o 1 O Test Data out same as new_tdo tm1_0 1 O Extra Test mode select 1 same as new_tms 1 trst_ 1 O Test mode Reset The JTAG bus interface of the scan controller is used for communicating be tween the board under test and Service Processor It supports two protocols First it supports the Standard Test Access Port and Boundary Scan Architecture Specification from the IEEE 1149 1 This is known as JTAG Second it supports a special address protocol that was developed by Sundragon Project group This special protocol will allow selection of up to 16 boards and up to 16 rings on that selected board To support this protocol two signals istas ismp_ were added to the JTAG interface The Standard JTAG interface will be used to access the JTAG boundary and internal scan paths All of this communication is done through the Sun Microelectronics 50 6 Scan Controller TDI_n TDO TMS_n and TCK signals For further information on JTAG please refer to Standard Test Access Port and Boundary Scan Architecture Specifica tion from the IEEE 1149 1 6 3 1 JTAG Interface Description 6 3 1 1 Overview When the istas_ is asserted from
18. tede rete t tt ed 6 2 Signal Descriptions eene nnne tenen nennen 6 3 Scan Controller Functional Description sse 6 4 Scan Controller Timing Diagrams 6 5 Scan Block Bugs and Solutions EE Clock Controller A p den eripe ertet eret As Z3 EE 7 2 Clock Controller Function Description PAL Block aede ent ect reet iret Ert EAS Gell e 82 PAL Block Function Descriptions En Sun Microelectronics iv 29 29 31 32 47 47 49 50 58 58 61 61 63 65 65 68 List of Figures RIC Chip System Block Diagram EE RIG Chip Logical Blocker rte e Dota betae edem 6 RIC Chip Block Diagram EE 16 RIG Chip Block sour gen ete emen endete etre e ge ee stele 20 Reset Block e aine p ipaa teen hd 21 RIERA eese YAN we ee e a cd Stace 22 POR Detailed Block 23 POR Timing Diagram cns petu ee bee get reat ee ed eee tei 24 Button POR Detailed Block aaneen ensen nennen nnne nennen nennt 25 Button IEN Ken 25 Button_XIR Detailed Block 26 Dutton XIR TIAS ii et Nr e adan 27 Interrupt Concentrator System Block Diagram eee 29 Interrupt Concentrator Block EE 30 Rie NICON pus yon da sin does ek kaa ini die an ia fa bade ea yok andan dende van 31 Encoder BIOCK aci iii e rante 34 State Diagram of the First Stage encode EE 36 Encoder 1 Timing ee ao ak abo took ond payo padan d anko qt ete eicere te tii eie dt sede 39 Dispatcher Block retire reete pipe eee 40 Dispatcher State Machine EE 42 Dispatc
19. 1 I PINC10T interrupt from audio device PFAIL_INT_L ipfail_int 1 I PINC10T interrupt from power supply GRA2_INT_L igra_int2 1 I PINC10T interrupt from graphics module KEY_INT ikey_int 1 I PINY10T interrupt form key board mouse serial ports FLOP_INT iflop_int 1 I PINY10T interrupt from a floppy device SPARE_INT_L ispare_int 1 I PINC10T interrupt from a spare device ETH_INT_L ieth_int 1 I PINC10T interrupt from ethernet SKEY_INT_L iskey_int 1 I PINC10T Key board int for future use SMOU_INT_L ismou_int 1 I PINC10T Mouse Int for future use SSER_INT_L isser_int 1 I PINC10T Serial Int for future use INT_NUMJ 5 0 oint_num 6 BOT6T interrupt number to U2S SLAVIO_RST_L oslavio_rst_ 1 BOM4T sbus reset to slavio Sun Microelectronics 9 RIC User s Manual 2 4 Scan Interface Signals These signals connect from the RIC chip to the Scan service processor and scan rings on the system board Table 2 4 Scan Interface Signals Signal Name Internal Sig Pin I O Driver Description nal Name Count SP TAS is tas 1 I BIN10T Test Address Strobe from Service Pro cessor SP TDI is tdi 1 I BIN10T Test data out for Scan from Service Pro cessor SP TCLK is tclk 1 I BINOAT Test Clock for Scan from Service pro cessor SP TMS is tms 1 I PINC10T Test Mode Select for Scan from Service processor SP_REST_L is_rest 1 I PINC10T Te
20. 4 3 1 1 Overview The POR logic is responsible for generating power on reset signal and keeping it low for a minimum of 2ms 4 3 1 2 POR Block Diagram power_ok_ enet_clk lA OA N Or l enet_clk 10 MHz V d w Sys por power ok O ihrd_rst_flag RIC_ rst_cnt_done_ counter clr_ gt Figure 4 4 POR Detailed Block Sun Microelectronics 23 RIC User s Manual 4 3 1 3 POR State Descriptions The sys_por_ will be asserted asynchronously when it detects the power_ok_ sig nal from the power supply Once the power_ok_ gets de asserted the counter starts counting When the counter reaches full count the rst cnt done will de as sert the ihrd_rst_flag which in turn will de assert sys_por_ It will be asynchro nous to the SC chip which runs on the system clock frequency 4 3 1 4 POR Timing Diagram enet_clk power ok 100 usec l Sys por ud i j l i i 2msec Figure 4 5 POR Timing Diagram 4 3 2 Button POR description 4 3 2 1 Overview The Button POR block is responsible for generating a reset when it gets a signal from button por reset switch on the lab console board a porout signal from the PAL block or a scan por command from Scan controller Sun Microelectronics 24 4 3 2 2 Button_POR Block Diagram 4 Reset Block debouncer
21. ASICs and the processor Modules It can also generate POR and XIR resets The Scan Controller has two subblocks JTAG Interface block and Internal Scan Ring block The JTAG interface block interfaces to the external service processor to receive send scan data and control signals It also interfaces to the system board and controls all the scan chains It can receive up to 8 different scan chains and selects one of the chain to pass it along to the service processor TDI15 scan ring chain is from the Internal scan ring block The internal scan ring uses TMS 15 and TDO signals from the JTAG interface block to set up its data 3 3 4 Clock Control The function of the Clock Control block is to select the clock speed based on the input from processor modules The clock select signals will be used by the clock chip to generate the system clock Sun Microelectronics 17 RIC User s Manual 3 3 5 PAL Block The function of the PAL Block is to prvide decode logic for the SC and Lab Con sole address and data registers Freq Margining chip support and PROM write address decode Additionally it also provides an XOR gate 3 3 6 RIC Gate Counts Table 3 1 RIC Gate Count estimates Subblock Gate Count Reset 600 Interrupt 1800 Scan 500 Clock Control 50 PAL 250 Total 3200 Sun Microelectronics 18 Reset Block 4 4 1 Overview The reset logic on the UltraSPARC system boards is divided among the RIC chip s
22. Block 17 Dispatcher Block 40 bus interface signals 12 Dispatcher State 41 42 Button PO 19 Dispatcher Timing 45 Button XIR 19 E Button_POR 24 25 Ebus signals 68 Button_XIR 26 27 EN FSMI 37 byte stream 2 Bytes 2 C clock 17 Clock Contro 16 Clock Control 4 17 Clock Controller 11 61 63 clock controller 61 62 Clock Controller Signals 11 Clock Controller System 61 clock generator 65 clock select signals 17 EN FSMI State 36 EN1_FSM State 35 Encoder 29 33 encoder 39 Encoder 1 Timing 39 Encoder Block 34 Encoder Timing 39 External interrupt Reset 2 F frequency margining chip 5 G Gate Count 21 30 48 62 66 Sun Microelectronics 71 RIC User s Manual gate level fix 58 H halfword 2 I Instruction Register 56 instruction register 55 Interface Signal 8 11 Interface Signals 9 internal logics 13 Internal Scan Ring 17 Interrupt 4 Interrupt Concentrator 9 16 17 29 Interrupt Signals 32 J JTAG 50 58 JTAG controller 59 JTAG FSM State 53 56 57 JTAG Internal Scan Ring 47 48 55 JTAG ring 55 JTAG Scan controller 19 JTAG Scan Ring Register 56 Jtag state machine 56 JTAG 50 JTAG Bus protocol 17 JTAG FSM 53 JTAG Interface 47 48 JTAG Interface Block 52 JTAG Registers 54 JTAG Timing 54 L Lab Console 68 Lab Console LC 5 Logical Block 6 M MUX 51 P PAL Block 5 16 18 65 66 68 PAL Block Signals 12 Sun Microelectronics 72 PAL Logic 68 PAL Logic Address Map 68
23. MSs and Stop_clock Ld Clock Contoller PAL Resets Frequency code chip selects PAL Block to the clock chip SC LC Prom chip selects Figure 1 2 Sun Microelectronics 6 RIC Chip Logical Block Pin Descriptions No II This chapter describes the pinout for the RIC chip 2 1 I O Driver Specifications The following drivers are used in the RIC Table 2 1 Driver Descriptions Driver Name Buffer Type Strength Notes LO IO PINC10T Input 1 44 mW BIN10T with 100K pull up PINY10T Input 1 44 mW BIN10T with 50K pull down BIN10T Input 1 44 mW Noninverting TTL input buffer BINO4T input 6 17 mW Noninverting TTL input buffer PIMCO6F INV Input Inverting 5 Volt tolerant PIMCO6F input driver BOM4T Output 4mA Noninverting MOS 3state output BOT6T Output 6mA Noninverting TTL 3 state output BOT10T Oupput 10 mA Noninverting TTL 3state output BON6T Output 6mA Noninverting TTL output BOM6F_TRD Output 6mA 5 Volt tolerant BOM6F output driver BON6F TRD Ouput 6mA 5 Volt tolerant BON6F output driver DONS TRD Ouput 8mA 5 Volt tolerant BONS8F output driver BON10F_TRD Ouput 12 mA 5 Volt tolerant BON10F output driver BONI2F TRD Ouput 12mA 5 Volt tolerant BON12F output driver Sun Microelectronics 7 RIC User s Manual 2 2 Resets Interface Signals These signals connect from the RIC chip to the SC power sup
24. P3 2 0 icpu_sp4 3 I PIMCO6F INV Speed Inputs from CPUs CLK SEL 2 0 oclk sel 3 O BOM6F TRD Selection Code to the Clock chip Sun Microelectronics 11 RIC User s Manual 2 6 PAL Block Signals These are the Ebus interface signals to the internal logics Table 2 6 Ebus and PAL Signals Signal Name Internal Sig Pin I O Driver Description nal Name Count EB ADR 0 ieb adr 0 1 I BIN10T Ebus Address 0 input EB ADR 1 ieb adr 1 1 I BIN10T Ebus Address 0 input EB ADR 13 ieb adr 2 1 I BIN10T Ebus Address 0 input EB ADR 14 ieb adr 3 1 I BIN10T Ebus Address 0 input EB ADR 19 ieb adr 4 1 I BIN10T Ebus Address 0 input EB WR L ieb wr 1 I PINC10T Ebus Write bit EB_CS_L ieb_cs_ 1 I PINC10T Ebus Chip Select EB_RDY_L oeb_rdy_ 1 I BOT10T Ebus Ready line PR_CSIN_L ipr_csin_ 1 I PINC10T Prom Chip Select In PR_CSOUT_L opr_csout_ 1 BOT6T Prom Chip Select Out S_LOAD os load 1 BOM6F_TRD Freq Margining chip load S_CLOCK os_clock 1 O BOM6F_TRD Freq Margining chip clock SC CSL OSC CS 1 BOT6T SC Chip Select LC BS L olc_bs_ 1 BOT6T LC Chip Select XOR INI ixor inl 1 I PINC10T Xor Input 1 XOR IN2 ixor in2 1 I PINC10T Xor Input 2 XOROUT oxorout 1 O BOT6T Xor output Sun Microelectronics 12 2 7 Miscellaneous Signals These are the clock input reset and other signals to the internal logics 2 Pin Descriptions
25. RIC User s Manual Sun Microelectronics RIC User s Manual 1997 Sun Microsystems Inc All rights reserved THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED AS IS WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES IN ADDITION SUN MICROSYSTEMS INC DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WAR RANTIES INCLUDING ANY WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS This document contains proprietary information of Sun Microsystems Inc or under license from third parties No part of this doc ument may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems Inc Sun Sun Microsystems and the Sun Logo are trademarks or registered trademarks of Sun Microsystems Inc in the United States and other countries All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC Interna tional Inc in the United States and other countries Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems Inc The information contained in this document is not designed or intended for use in on line control of aircraft air traffic aircraft nav igation or aircraft communications or in the design construction operation or maintenance of any nuclear facility Sun disclaims any express or implied warranty of fitness for such uses
26. atched ENC4 interrupt go to DIDS state or DDI5 state ddi5 dispatch ENCS interrupt go to DID6 state or DDI6 state ddi6 dispatch ENC6 interrupt go to DIDI state or DDII state Sun Microelectronics 41 RIC User s Manual 5 3 2 4 Dispatcher State Machine Diagram done6 Figure 5 8 Dispatcher State Machine Sun Microelectronics 42 5 Interrupt Concentrator 5 3 2 5 Dispatcher State Machine description DDIl1 DDI1 DDI2 Goes to this state on reset or whenever a when a transition is com pleted in state ddi5 SYNC OUTPUTS Everything is inactive in DID TRANSITIONS DDI1 interrupt from ENCI is being serviced If int_prel then go to state DDI1 DDI2 interrupt number 2 is being serviced If lint_prel amp int pre2 then go to DDI2 DDI3 interrupt number3 is being serviced If lint_prel amp lint_pre2 amp int pre3 then go to DDI3 DDI4 interrupt number 4 is being serviced If lint_prel amp int_pre2 amp lint pre3 amp int pre4 then go to DDI4 DDI5 interrupt number 5 is being serviced If lint_prel r lint_pre2 amp lint pre3 amp lintPre4 amp intPre5 then go to DDI5 DDI6 interrupt number6 is being serviced If int prel amp int pre2 amp int pre3 amp lintPre4 amp i intPre5 amp int pre6 then go to DDI6 First stage of interrupt dispatch cycle SYNC OUTPUTS load the int register int sel 2 0 1 int en 20 do
27. e highest bit number Least significant bit is the bit with the lowest bit number Byte 8 bits Halfword 16 bit Word 32 bit Doubleword 64 bit Addresses are byte address In a byte stream if byte n is located at address a byte n 1 is located at address a 1 The same is true for the other data types Bytes halfwords words and doubleword datums are located at byte halfword word and doubleword addresses respectively A halfword address is evenly divisible by 2 a word address is evenly divisible by 4 and a doubleword address is evenly divisible by 8 In a halfword most significant byte is at the lower address In a word most significant byte or halfword is at the lowest address In a doubleword the most significant byte halfword or doubleword is at the lowest address Assertion True 1 and De assertion Negative False 0 All descriptions and state diagrams are logical They are completely independent of the electrical value unless explicitly called out as high or low uon Negative true signals are suffixed with an Sun Microelectronics 2 1 3 Partition Overview 1 Overview The RIC chip interfaces with the power on circuits interrupts sources scan log ics and the system clock chip 1 3 1 Partition Block Diagram Power Supply Figure 1 1 Partition Overview RIC Chip Reset Block Interrupt Concentrator Scan Controller Clock Controller PAL Block
28. eigo tre Re eiae e deti re E i ie aids 56 Clock Controller signal descriptions sse 62 System clock select nee tend ed pin da da panse ki os daou on eb tes 63 PAL Block signal descriptions EE 67 PAL Logic Address Map EE 68 Sun Microelectronics vii Sun Microelectronics viii Overview 1 1 1 Introduction The RIC chip STP2210QFP supports the system resets system interrupts sys tem scan system clock control as well as other functions for the UltraSPARC sys tem boards Features Supports resets from power supply reset buttons and scan Delivers system power on reset button power on reset and the external button resets to the system controller SC Concentrates all the interrupts and sends interrupt numbers to the system I O U2S Directs SCAN inputs and outputs through the scan chains Provides scan power on reset and scan external interrupt resets through an internal scan chain Determines the system speed from the CPU speed inputs Provides decoding for SC Lab Console address and data registers Frequency Margining chip and PROM write address space Sun Microelectronics 1 RIC User s Manual 1 2 Definition of Terms 1 2 1 Frequently Used Terms RIC Reset Interrupt Scan and Clock Control U2S I O Controller SC System Controller POR Power on Reset XIR External interrupt Reset UPA Uniform Port Architecture 1 2 2 Conventions Most significant bit is the bit with th
29. ers Address Register Table 6 3 JTAG Scan Address Register Field Bits Description R W Board ID 7 4 Board Address not used by RIC RW Ring Number 3 0 Selects one of the 8 scan rings or ring 15 RW inter RIC tap The most significant four bits of the address register specify particular board to be selected Board addressing is not supported in the RIC chip use address 0 for the UltraSPARC system motherboards and the least significant four bits specify the particular scan ring on the board Sun Microelectronics 54 6 3 2 JTAG Internal Scan Ring Description 6 3 2 1 Overview 6 Scan Controller The internal Scan ring ring 15 is used for generating POR and XIR resets This JTAG ring will only support the data register DR portion of the JTAG state dia gram The instruction register IR portion is not used or not needed Instead a dummy path was added in place of the IR path to meet the JTAG specifica tions The JTAG Internal Scan Ring is 8 bit long register Out of the bits currently only two are defined Two bits are used for generating power on and xir resets 6 3 2 2 JTAG Internal Scan Ring Block Diagram tck tms 15 JTAG t FSM Osys por d 8 bit shift register gt tdi 15 m Scan xir Scan por Figure 6 7 JTAG Internal Scan Ring Block Sun Microelectronics 55 RIC User s Manual
30. g the same ring resets the ring While the TAS signal is active TMS 8 2 are driven to a high value this causes the rings connected to TMS 8 2 to be reset TMS 1 is a special case and is not reset when TAS is active The same solution as above will also fix this problem 6 5 3 Selecting non existent rings gives inconsistent behavior Since the register in the JTAG controller has four bits for the ring address and only eight TMS lines it is possible to select non existent rings in this case the JTAG controller should consisently return all one s however selecting non exis tent rings causes the JTAG controller in the RIC to default to ring 0 and give in consistent behavior The solution to this problem would be to better qualify the tms enable 0 signal so that rather then default to tms enable 0 we would only drive tms enable 0 high after reset This solution needs further investigation and verification Sun Microelectronics 59 RIC User s Manual Sun Microelectronics 60 Clock Controller 7 7 1 Overview This chapter describes how the clock controller of the RIC chip sets the system and CPU speeds The clock controller in the RIC chip provides a magintude comparator for multi ple up to four CPU clock speeds and determines the slowest cpu speed This in formation is then used to set the CPU speed for all cpu modules in the system and the system clock frequency Unconnected speed select inputs are internally pulled
31. her Timings dct pret He bs te realem eite ite 45 Scan Controller System Block sss eee 47 Scan Controller Block Diagram EE 48 Scari ConDttol nto esae Ge ee be pleb s et HER eie 49 JTAG Interface Detailed Block 52 JTAG ESM State Machine nee eee Ree Se ation 53 JTAG Interface Timing Diagram En 54 Sun Microelectronics H JTAG Internal Scan Ring Block EEN 55 MAG State Machine i ce e tue 57 JT AG Scan Ring Timing Diagram EE 58 Clock Controller System Block een 61 RIC CIO SO iet de dada betae e UD e p RE n deste 62 EE EE 66 RIC BAT in EE 66 Sun Microelectronics vi Listof Tables Driver Descriptions ENEE nennt ve 7 Resets Interface Signals 155 nternet ien neden dete eis 8 Interrupt Concentrator Interface Signals En 9 Scan Interface Signals onte ete a endete trea de e e e en 10 Clock Controller Signals n puse reete eterne 11 Ebus and PAL Signals ree tere erede te n degeret ene dede 12 Miscellaneous Signals nee 13 RICE Pin Count toca ene HE RESI Se t Da tuu o diede SH 13 RIC Gate Count estimates EE 18 Input Output Signals of Reset Logic 22 Interrupt Signals iet Siena e ene ene e eed ee s 32 enl fem State Description ione aee e teile Hs 35 State Table descrrptiOri o e ete n e diete i et eet 41 Scan Controller Signals 5 rentem pede es a oe dee td aed 50 JLAG FSM Sha te TT M 53 JTAG Scan Address Register een 54 JT AG Scan Ring Data Instruction Register En 56 Jtag state machine 5
32. ld be in any one of the 16 different states when an interrupt occurs There are seven idle states and seven dispatch states corresponding to each of the eight interrupts coming in Each idle state waits in that state until an interrupt occurs Once it detects an interrupt it goes to the dispatch state of that interrupt which is being serviced In that state it does two things It drives an int pre signal to the second stage which is the dispatch state machine Also it drives control signals to some combo logic which enables the right interrupt number get loaded into the register on the following clock edge Then it waits in that state until it sees a done signal from the dispatcher state machine from the second stage Once it sees the done signal it goes to the idle state of the next higher interrupt from the one being serviced Table 5 2 enl fsm State Description State Description eid1 waiting for an interrupt 1 has the highest pri eid2 waiting for an interrupt 2 has the highest pri eid3 waiting for an interrupt 3 has the highest pri eid4 waiting for an interrupt 4 has the highest pri eid5 waiting for an interrupt 5 has the highest pri eid6 waiting for an interrupt 6 has the highest pri eid7 waiting for an interrupt 7 has the highest pri edil send out int number 1 goes to eid 2 on done edi2 send out int number 2 goes to eid3 on done edi3 send out int number 3 goes to eid4 o
33. n done edi4 send out int number 4 goes to eid5 on done edi5 send out int number 5 goes to eid6 on done edi6 send out int number 6 goes to eid7 on done edi7 send out int number 7 goes to eid8 on done Sun Microelectronics 35 RIC User s Manual 5 3 1 4 EN FSMI State diagram done done Figure 5 5 State Diagram of the First Stage encode Sun Microelectronics 36 5 Interrupt Concentrator 5 3 1 5 EN FSMI State Machine Description EID1 Goes to this state on reset or whenever a when a transition is com pleted in state edi8 SYNC OUTPUTS Everything is inactive in EID TRANSITIONS EDI1 EDIT EDI2 EDI2 EDI EDI4 EDI5 EDI6 EDIT interrupt number 1 is being serviced If int1 then go to state EDI interrupt number 2 is being serviced If lint1 amp int2 then go to EDI2 interrupt number3 is being serviced If lint1 amp lint2 amp int3 then go to EDI3 interrupt number 4 is being serviced If lint1 amp lint2 amp lint3 amp int4 then go to EDI4 interrupt number 5 is being serviced If int1 amp lint2 amp lint3 amp lint4 amp int5 then go to EDI5 interrupt number 6 is being serviced If int1 amp lint2 amp lint3 amp lint4 amp lint5 amp int then go to EDI6 interrupt number 7is being serviced If lint1 amp int2 amp lint3 amp lint4 amp lint5 amp lint6 amp int7
34. nel 1 TRANSITIONS DDI2 If int_pre2 DDI3 If int_pre3 DDI4 If int_pre4 DDI5 if int_pre5 DDI6 if int_pre6 DID2 default First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int sel 2 0 2 int en 20 done2 1 TRANSITIONS DDI3 If int pre3 DDIA If int pre4 DDI5 if int pre5 DDI6 if int pre6 DDII If int prel DID3 default Sun Microelectronics 43 RIC User s Manual DDI3 DDI4 DDI5 DDI6 Sun Microelectronics 44 First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int sel 2 0 3 int en 20 done3 1 TRANSITIONS DDIA If int pre4 DDI5 if int pre5 DDI6 if int pre6 DDI If int_prel DDI2 If int_pre2 DID4 default First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int sel 2 0 4 int en 20 done4 1 TRANSITIONS DDI5 if int pre5 DDI6 if int pre6 DDI If int_prel DDI2 If int_pre2 DDI3 If int_pre3 DID5 default First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int sel 2 0 5 int en 20 done5 1 TRANSITIONS DDI6 if int pre6 DDI If int_prel DDI2 If int_pre2 DDI3 If int_pre3 DDI4 if int_pre4 DID6 default First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int sel 2 0 6
35. o initiate the XIR and POR resets to system controller SC 1 If the RIC chip is used in a PCI based system all references to SBus can be replaced with PCI bus Equally replace all references to 25MHz Sbus clock with 33MHz PCI clock When the RIC chip is used in a PCI based system the RIC chip meets the necessary timing requirements for the 33MHz PCIbus Note that this manual also has relevance for PCI based system designs Sun Microelectronics 4 1 Overview 1 4 4 Clock Control The clock control module receives speed inputs from all the CPU modules Based on the slowest CPU speed it determines the system frequency and sends clock se lect signals to select the system frequency 1 4 5 PAL Block The PAL Block module implements decode logic for the system controller SC address and data register Lab Console LC address and data register support for the frequency margining chip and a decode for the PROM write address space Also the PAL block provides an XOR gate Sun Microelectronics 5 RIC User s Manual Resets from the power supply and switch buttons Interrups from SBus devices and UPA expan sion slots SBus Clock sbus_rst_ TDIs from scan chains JTAG controls from service processor CPU speed inputs Ebus signals RIC Chip om Y Interrupt Concentrator Scan Controller A Resets to SC Interrupt numbers to the U2S Lg Scan Resets TDO T
36. ply and switch but tons Table 2 2 Resets Interface Signals Signal Name Internal Signal Pin I O Driver Description Name Count POWER OK L ipower ok 1 I PINY10T Signal asserted during power on BUTTON_POR_L ibutt_por_ 1 I PINC10T Signal asserted by push button switch BUTTON_XIR_L ibutt_xir_ 1 I PINC10T Signal asserted by push button switch SYS_POR_L osys_por_ 1 O BOM6F_TRD Signal to SC during pow on reset P_BUTTON_RESET_L op_button_ 1 O BOM6F_TRD Signal to SC asserted dur ing push button power reset X_BUTTON_RESET_L ox_button_ 1 O BOM6F_TRD Signal to SC asserted dur ing push button XIR Sun Microelectronics 8 2 3 Interrupt Concentrator Interface Signals These signals connect from the RIC chip to the interrupting devices and U2S 2 Pin Descriptions Table 2 3 Interrupt Concentrator Interface Signals Signal Name Internal Signal Pin I O Driver Description Name Count SB IRQO L 7 1 isbus0 7 I PINC10T interrupts from sbus slot 0 SB_IRQ1_L 7 1 isbus1 7 I PINC10T interrupts from sbus slot 1 SB IRQ2 L 7 1 isbus2 7 I PINCIOT interrupts from sbus slot 2 SB_IRQ3_L 7 1 isbus3 7 I PINC10T interrupts from sbus slot 3 SCSI INT L iscsi int 1 I PINC10T interrupt from scsi PP_INT_L ipar_int 1 I PINC10T interrupt from parallel port GRA1_INT_L igra_intl 1 I PINC10T interrupt from on board graphics AUDIO_INT_L laudio_int
37. possible fix Sun Microelectronics 51 RIC User s Manual 6 3 1 2 JTAG Interface Block Diagram istms stms o nr istdi stdi E ido new tdo stclk stelk O gt MUX istdi tms_en 0 A tms_en 1 stelk ok stclk d gt tms en 2 8 15 UN tms 15 8 2 Ring Address S eina 9 istdi stas shift register 8 bit 4 8 gt tms en 15 8 1 a o default tens endo tdi15 tdi 8 1 new mido stclk dd tdi 1 tms en 15 8 1 tms en 0 i Figure 6 4 JTAG Interface Detailed Block Sun Microelectronics 52 6 Scan Controller 6 3 1 3 JTAG FSM State Descriptions The JTAG state machine can be in two different states On power up or on reset it will be in idle state when s tas is asserted by the service processor state ma chine in scan ring state In this state it will enable the address register to be scanned in with the board and ring addresses Table 6 2 JTAG FSM State State Description waiting for s tas enable address register for shifting scan ring 6 3 1 4 JIAG FSM State Diagram Figure 6 5 JTAG FSM State Machine Sun Microelectronics 53 RIC User s Manual 6 3 1 5 JLAG Timing Diagram Figure 6 6 JTAG Interface Timing Diagram 6 3 1 6 JTAG Regist
38. process continues until there are no interrupts pending When all interrupts have been serviced the dispatcher will send idle interrupt number all 1 s to U2S Sun Microelectronics 39 RIC User s Manual 5 3 2 2 Dispatcher Block Diagram Dispatcher State Machine done 6 1 int_num 1 5 0 y int_num 2 5 0 int_num 6 5 0 int num sel int ena sbus clk int num 5 0 register Figure 5 7 Dispatcher Block Sun Microelectronics 40 5 3 2 3 Dispatcher State Description 5 Interrupt Concentrator The dispatcher state machine is comprised of twelve different states Based on its present state the next higher interrupt will be selected to be passed onto the U2S There are six idle states and six dispatch states The following table explains the different states Table 5 3 State Table description State Description didi Wait for interrupt Enc1 output has highest pri did2 Wait for interrupt Enc2output has highest pri did3 Wait for interrupt Enc3 output has highest pri did4 Wait for interrupt Enc4 output has highest pri did5 Wait for interrupt Enc5 output has highest pri did6 Wait for interrupt Enc6 output has highest pri ddil dispatch ENC1 interrupt go to DID2 state or DDI2 state ddi2 dispatch ENC2 interrupt go to DID3 state or DDIS state ddi3 dispatch ENC3 interrupt go to DIDA state or DDIA state ddi4 disp
39. ree bit code associated with the slowest CPU speed to the out put The slowest CPU speed and the corresponding output is shown in the table below Table 7 2 System clock select Slowest CPU Speed Code Output Speed Select 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 Sun Microelectronics 63 RIC User s Manual Sun Microelectronics 64 PAL Block 8 8 1 Overview This chapter describes how the PAL block of the RIC chip works The PAL block was added late in the RIC development to provide misc decode logic services that did not fit anywhere else on the system The PAL block implements the following five functions T 2 3 4 5 Decode for the SC chip Decode for lab console accesses Decode and sequencing for clock generator parts Decode for PROM writeable space Xor Gate Sun Microelectronics 65 UltraSPARC User s Manual Figure 8 1 Ebus Addres PAL Block Diagram Interrupt Block Scan Control Clock Control Reset Control 5 5 oporout_ Ebus Chip Select Ebus Write PROM Chip Select In PAL Block Lab Console Board Sel SC Chip Select Ebus Ready Serial Clock Serial Load PROM Chip Select Qut 8 1 1 PAL Block Gate Count Estimates The current gate count for the PAL Block is 250 gate equivalents Sun
40. st Reset for Scan from Service Pro cessor SP_MP_L is_mp_ 1 I PINC10T Service processor present TDI 8 1 itdi 8 I PIMCO6F INV Test Data from ASICS on UUT TCLK tclk 1 I BINO4T Scan Input Clk SP_TDO os_tdo 1 O BON6T Test data out to Scan processor TDO_A otdo 1 O BON6F_TRD Test data out to all ASICS on board TDO_B otdo_o 1 O BON6F_TRD Test data out to asics same as tdo TCLK_1 is_tclk 1 O BON12F_TRD Test Clock Out to all ASICS TCLK_2 is tclk 1 O BON12F_TRD Test Clock out same as tclk TCLK_3 is tclk 1 O BON12F_TRD Test Clock out same as tclk TCLK_4 is tclk 1 O BON12F_TRD Test Clock out same as tclk TCLK_5 is tclk 1 O BON12F_TRD Test Clock out same as tclk TCLK_6 is tclk 1 O BON12F_TRD Test Clock out same as tclk TRST_L otrst_ 1 O BON12F_TRD Reset for spitfire clock logic TMS 8 1 otms 8 O BON8F_TRD Test Mode select for ASICS TMS1_B otms1_o 1 O BON6T Test mode select same as tms1 TRST_5V_L 1 O BONI1OF TRD 5V Reset for tap controller Sun Microelectronics 10 2 5 Clock Controller Interface Signals These signals connect from the RIC chip to the CPU modules and the clock gen eration chip 2 Pin Descriptions Table 2 5 Clock Controller Signals Signal Name Internal Signal Pin I O Driver Description Name Count CPU SP4 2 0 icpu spl 3 I PIMCO6F INV Speed Inputs from CPUs CPU SP1 2 0 icpu_sp2 3 I PIMCO6F INV Speed Inputs from CPUs CPU SP2 2 0 icpu_sp3 3 I PIMCO6F INV Speed Inputs from CPUs CPU S
41. the service processor the jtag fsm state ma chine enables the 8 bit shift register The board and the ring addresses are fed se rially into this address register though s_tdi signal The s_tas will stay active for 8 clocks of s_tck In this implementation of the scan controller the least signifi cant four bits of the address register will be used to send s_tms signal to the right scan chain All the other tms lines for the remaining scan rings will be kept high see Note below The scan bits are also used as input to a MUX to select the right tdi signal to be scanned back to the service processor Since ATE in manufacturing does not support multiple rings the RIC chip on power up will default to scan chain 1 So all the ASICS which have to be tested on the ATE must be on a single scan chain Also the normal operation of the scan control logic in the RIC chip has a two clock delay associated with all the test sig nals which ATE can not account for To work around this problem the tms1 and tdo signals are bypassed inside the RIC chip when the default ring is selected for example at power up This is illustrated in the Figure 6 4 JTAG Interface De tailed Block Note Keeping the TMS lines high on a scan chain ring will reset the unselected rings in five test clock cycles or less This also prevents the RIC chip for being used for inter ring testing To allow inter ring testing see Section 6 5 Scan Block Bugs and Solutions for a
42. then go to EDI7 First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1 int num1 0 TRANSITIONS EID2 go to EID2 state and wait for the next interrupt If done go to EID2 EDI default First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1 int numl 1 TRANSITIONS EID3 go to EID3 state and wait for the next interrupt If done go to EID3 EDI2 default Sun Microelectronics 37 RIC User s Manual EDI3 First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1 int numl 2 TRANSITIONS EID4 go to EID3 state and wait for the next interrupt If done go to EID4 EDI3 default EDIA First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1 int numl 3 TRANSITIONS EID5 go to EID5 state and wait for the next interrupt If done go to EID5 EDI4 default EDI5 First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int_prel 1 int_numl 4 TRANSITIONS EID6 go to EID6 state and wait for the next interrupt If done go to EID6 EDI5 default EDI6 First stage of interrupt dispatch cycle SYNC OUTPUTS dispatch int valid and load the int register int prel 1
43. un Microelectronics 57 RIC User s Manual 6 4 Scan Controller Timing Diagrams tck istas tdi0 istdo istms isrest istdi tdo0 tms0 Figure 6 9 JTAG Scan Ring Timing Diagram 6 5 Scan Block Bugs and Solutions The JTag implementation in the RIC has three known problems these are dis cussed in detail below 6 5 1 Unselected Rings Reset Automatically All unselected TMS ring lines are driven high this was done intentionally to make sure that all unused TMS lines were driven to a known state Unfortunately driving TMS line high causes JTAG to reset after five clocks Thus when attempt ing to do inter ring testing it is not possible to setup one ring and then load the second ring as the first ring will have reset when you come back The solution to this problem is to do a gate level fix and tie the tms enable line on the nand gates that are used to drive the TMS signals to VCC this will leave the TMS lines always enable and thus low when switching between rings See Figure Figure 6 4 JTAG Interface Detailed Block Sun Microelectronics 58 6 Scan Controller 6 5 2 Selectin
44. us slot 0 isbus1 int 6 0 7 I interrupts from sbus slot 1 isbus2 int 6 0 7 I interrupts from sbus slot 2 isbus3 int 6 0 7 I interrupts from sbus slot 3 iscsi_int_ 1 I interrupt from scsi iskey_int_ 1 I spare int for keyboard ismou_int_ 1 I spare int for mouse ispare_int_ 1 I interrupt from a spare device isser_int 1 I spare int for serial port isbus_rst_ 1 I sbus reset oint num 5 0 6 interrupt number to U2S oslavio rst 1 Registered sbus reset to slavio 5 3 Interrupt Concentrator Functional Description The encoder receives interrupts from SBUS slots SLAVIO and the UPA expan sion slots There are a total of 41 interrupts The encoder constantly monitors for an active interrupt and generates a interrupt number associated with the device It will signal the interrupt dispatcher state machine that there is a valid interrupt Sun Microelectronics 32 5 Interrupt Concentrator present There is a three clock cycle latency after the interrupt is detected before it is sent out to the U2S Since all the interrupts coming are asynchronous it will be double clocked and stored in a register before any encoding takes place The outputs of this six sub groups are fed into the second stage of decoding Af ter the arbitration is complete at second stage the interrupt vector is sent to the U2S on the next clock edge 5 3 1 Encoder Description 5 3 1 1 Overview The incoming interrupts are divided into seven sub groups
45. x button Figure 4 9 4 Reset Block Button XIR Timing Sun Microelectronics 27 RIC User s Manual Sun Microelectronics 28 Interrupt Concentrator D 5 1 Overview The function of the interrupt concentrator is to detect all the active interrupts and provide the U2S with interrupt numbers The major goal of designing this logic inside the RIC chip is to support the large number of interrupt sources and re duce the pin count of the U2S chip 5 1 1 Interrupt Concentrator Overview The interrupt concentrator is basically a two level round robin priority encoder There are two major blocks in the Interrupt Concentrator Encoder and Dispatch er Clock Scan Reset Control Control Control sbus_rst_ Interrupt Concentrator int num 5 0 Interrupts 41 sbus clk slavio rst Lazi Figure 5 1 Interrupt Concentrator System Block Diagram Sun Microelectronics 29 RIC User s Manual 5 1 2 Interrupt Concentrator Detailed Block Diagram interrupts 41 ENCODER DISPATCHER int prel 7 enl R a log
46. ystem controller SC U2S and discrete components The RIC chip generates three different reset signals to the system controller SC chip Based on these re sets the SC will generate resets to the rest of the system RIC uses six different sources POR button POR PAL Block POR SCAN_POR button XIR and SCAN_XIR to generate the three resets Each of these three resets are handled differently by SC 4 1 1 Reset Logic The reset logic is divided into three different blocks POR Button POR Button XIR The POR block generates a reset SYS_POR_L on AC power on The Button POR block generates a reset P BUTTON RESET L when it gets a signal from the POR press button switch on the lab console board POR signal from the PAL block or SCAN POR command from the JTAG Scan controller The Button XIR block generates a reset X BUTTON RESET L when it gets a signal from the XIR press button switch from the lab console board or SCAN XIR command from the JTAG Scan controller Sun Microelectronics 19 RIC User s Manual Scan Interrupt Clock PAL Block Control Concentrator Control Scan por oporout scan xir enet clk power ok Sys por Reset p button Circuit button por x button button xir Figure 4 1 RIC Chip Block Sun Microelectronics 20 4 Reset Block 4 1 2 Reset Logic Detailed Block Diagram

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