Drigmorn4 User Manual Issue – 2.0
Contents
1. 111311 s We ging xm um a 2 7 L3 ET E 222 A 20 09 LE 2 I 00 Location of Expansion headers measured to holes for locating pegs The heights of the components measured from the lower surface of the board are as follows Upper surface of LCD display 12 5mm Ethernet connector 15 3mm USB connector 5 5mm PS2 connectors 14 7mm Micro SD card holder measured from top surface of PCB to bottom of SD card holder 2 6mm The is 1 6mm thick O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 49 Medical and Safety Critical Use Drigmorn4 boards are not authorised for the use in or use in the design of medical or other safety critical systems without the express written person of the Board of Enterpoint If such use is allowed the said use will be entirely the responsibility of the user Enterpoint Ltd will accepts no liability for any failure or defect of the Drigmorn4 board or its design when it is used in any medical or safety critical application Warranty Drigmorn4 comes with a 90 day return to base warranty Do not attempt to solder connections to the Drigmorn4 Enterpoint reserves the right not honour a warranty if the failure is due to soldering or other maltreatment of the Drigmorn4 board Outside warranty Enterpoint offers a fixed price repair or replacement service We reserve the right not to o2. Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 5 LED6 TN LEDS 94 WE LED13 l Q LED3 i 40 LED12 LED4 1778 1415 LED10 LED2 oo t 89 1 1 LEDI 09 LED9 LED oo co 760 oo w 00 400 ioo LED7 Drigmorn4 has 13 LEDs There is a single red LED in the lower half of the board just below the Real Time Clock device and 12 LEDs arranged into 4 blocks of three one of each block being red orange and green This is to enable users to simulate a traffic light sequence The LEDS may turn on dimly when power is applied to the unconfigured board The relevant IO pin for an LED needs to be asserted low to ensure the specified LED turns on The exception to this is LED7 for which the relevant IO pin should be asserted high Users may wish to visit out TechiTips section of the Enterpoint engineering website for tutorial and lab materials using Traffic Light LEDs Our Techitips are located at http www enterpoint co uk techitips techitips html Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 23 LEDS connected to the FPGA as indicated below LED FPGA PIN COLOUR 1 20 RED 2 21 ORANGE 3 B22 GREEN 4 F16 GREEN 5 F17 ORANGE 6 C19 RED 7 K7 RED SINGLE 8 P17 RED 9 V20 ORANGE 10 U19 GREEN 11 W22 GREEN 12 W20 ORANGE 13 T20 RED Enterpoint Ltd Drigmorn4 Ma
3. point d ASIC Design Drigmorn4 User Manual Issue 2 0 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 Kit Contents You should receive the following items with your Drigmorn4 development kit 1 Drigmorn4 Board 2 Programming Cable Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR DRIGMORN4 BOARD PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL Trademarks Spartan 6 ISE Webpack EDK COREGEN Xilinx are the registered trademarks of Xilinx Inc San Jose California US Drigmorn4 is a trademark of Enterpoint Ltd O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 2 Contents Kit Contents 2 Foreword 2 Trademarks 2 Drigmorn4 Board 4 Introduction 5 Getting Started 6 fpga 9 SPI FLASH 10 DDR3 MEMORY 12 DIL HEADERS 14 USB 16 ETHERNET 18 MAC ADDRESS DEVICES 19 TOP IDC HEADER 20 LCD DISPLAY 21 LEDS 23 REAL TIME CLOCK 25 POWER MONITOR MASTER RESET 27 OSCILLATOR 28 SWITCHES 29 SERIAL EEPROM 30 MICRO SD CARD HOLDER 31 ACCELEROMETER 32 PS2 33 INPUT POWER CONNECTIONS 35 POWER REGULATORS 37 CLOCK GENERATOR 39 EXPANSION HEADERS 41 PROGRAMMING DRIGMORN4 45 MECHANICAL 48 Medical and Safety Critical Use 50 Warranty 50 Support 50 O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 Driemo
4. NOTE E B27 5V FEED 2 NOTE E B28 5 FEED 2 NOTE E A29 EXP P34 U6 IO L63P 2 B29 5 FEED 2 NOTE E A30 EXP N34 V5 IO L63N 2 B30 5 FEED2 NOTE E AVAILABLE ON LX150 LX100 LX45 LX25 LO AVAILABLE ON LX150 LX100 LX45 AVAILABLE ON LX150 LX45 LX25 AVAILABLE ON LX150 LX45 AVAILABLE ON ALL DEVICES NOTES A This pin is connected to the main suspend pin of the Spartan6 and is intended for use where the FPGA needs to be shut down from an external device e g for power saving Leaving this pin unconnected allows the FPGA to function Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 normally Asserting the pin HIGH 3v3 will shut the FPGA down There is 100ohm resistor connected between this pin and DGND B EXP SCP connects to 4 resistor sites R204 to R207 which connect to the top 4 Left hand side DIL Header pins This is to allow an external device connected to J100 to connect with a user s module plugged into the DIL Headers Drigmorn4 boards are normally shipped with these resistors not fitted If customer requires any of these resistors to be fitted it is advised that they specify which are required so that they can be fitted before the board is shipped Enterpoint Ltd cannot be responsible for damage to the Drigmorn4 board by poor soldering C There are 6 connections between the expansion headers and the Clock Generator This is to allow an external device connected to the expansion header
5. TWO PS2 PORTS l4mm 13mm The Drigmorn4 has two PS2 ports which connect to the FPGA through bus switches and hence are 5V tolerant These can be used to connect to a keyboard and mouse or for other user defined functions Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 The connections to FPGA shown below Connector 1 1s defined as the connector on the left PS2 FPGA PIN CONNECTORI PIN 1 LEFT G4 CONNECTORI PIN 2 G3 CONNECTOR PIN 3 Wired to 0V CONNECTORI PIN 5 Wired to 5V CONNECTORI PIN 6 G7 CONNECTORI PIN 8 F2 CONNECTOR PIN 1 RIGHT H5 CONNECTOR PIN 2 H4 CONNECTOR 2 PIN 3 Wired to 0V CONNECTOR2 PIN 5 Wired to 5V CONNECTOR PIN 6 H6 CONNECTOR PIN 8 G6 O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 34 POWER CONNECTIONS 2 1 JACK CONNECTOR ROW OF 20 OV FOR 5V CONNECTIONS ON IDC SUPPLY HEADER a gt 3034 TT 189 nm z 00 00 7 ce 56 oo MINI USB CONNECTOR COLUMN OF 20 OV COLUMN OF 20 3 3V CONNECTIONS ON CONNECTIONS ON LHS DILHEADER RHS DILHEADER Drigmorn4 is powered principally from the 2 1mm Jack socket A limited supply can be provided using the USB connector but since the current available from a USB port can be as low as 100mA this should be av
6. This powers the FPGA general I O DIL Header and other devices such the Ethernet controller and Real Time Clock O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 37 A Micrel MIC22600 regulator supplies 1 2V with a maximum current available of 6A This is used for the core voltage of the FPGA An EP5388QI regulator supplies 1 5V with a maximum current of 600mA for the DDR3 and related FPGA I O A National Semiconductor LP2996 push pull regulator produces up to 1 5A at 0 75V This supply is used as reference and termination voltage for the DDR3 memory and related FPGA I O There is a small Standby Switch near the Jack socket which disables the voltage regulators A small residual current into the board may be seen when the switch is in the off position and the 5V supply to the board will still be active O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 38 CLOCK GENERATOR ee ee eS EELS TT EET Ye YS 7 Ls eo o0 3 va oo oo oo oo oo JAN 2 0000000000000 e 9000000000000 CLOCK GENERATOR Drigmorn4 has an IDT5V19EE901NLGI clock generator capable of generating four single ended clocks and one differential clock which are all connected to FPGA It can be used to generate clock frequencies in the range 4 9KHz to 500MHz The clock generator is controlled by an
7. oo El oo PUSH 48 3 DIP SW BITO BUTTON SWITCH SW 160 oo oo oo 00 A DIP SW BIT3 oo The Drigmorn4 has two push button switches and one 4 way switch To use these switches it is necessary to set the IO pins connected to the switches to have a pull up resistor in the FPGA This is set in FPGA constraints file Any switches pressed or made will then give a LOW signal at the FPGA otherwise a HIGH is seen The two push button switches are connected to the following IO pins The four DIP switch bits are connected to the following IO pins 16 1 15 M4 B3 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 29 16k SERIAL LESITIPITILIITILI E Lj 16 SERIAL EEPROM The Drigmorn4 has an Atmel AT24C16 EEPROM device which use a simple Parallel address and single serial data line and clock There is also a write protect line which can be used to electronically safeguard the information contained in the device This serial memory has 2048 words of 8 bits and employs a byte or page programming system It can run at speeds up to 400 KHz The EEPROM has the following connections to the FPGA SDA HI SCL H2 WP Gl The address pins on this device are wired to DGND OV O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 30 MICRO SD CARD HOLDER SD CARD HOLDER Further access to data can be achieved using
8. I2C serial interface and has an internal EEPROM for storage of configuration data Information and configuration software for this device are available from www idt com Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 39 The connections between the Clock Generator and the FPGA shown below IDT5V19EE901 Function IDT5V19EE901 Pin FPGA Pin CLK C 24 K5 P CLK Differential Clock ve 11 14 P CLK Differential Clock ve 10 K3 CLKB 8 M3 CLKA 7 LA SDAT 18 WA SCLK 19 UA SEL2 SUSPEND 26 AB3 SHUTDOWN OE 29 U3 CLK X 30 J3 Signals shown in yellow are routed via a 4 bit multiplexer which enables these signals if required to be controlled from the USB device In order for this to happen the signal on BCBUS4 must be asserted low or a jumper should be fitted to J7 default The legend on the PCB shows the positions for the jumper marked FPGA if the FPGA is to control the clock generator right side of J7 or USB if the control is from the FT2232H device left side of J7 When USB control is selected the signals will be routed as follows CLOCK GENERATOR SIGNAL FT2232 PIN USB SIGNAL SHUTDOWN OE 48 BCBUSO SEL2 SUSPEND 52 BCBUSI SCLK 53 BCBUS2 SDAT 54 BCBUS3 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 40 EXPANSION HEADERS 4 22010 nt Ltd ay VW enter point U TES PIN AI PIN B1 PIN
9. IDC 15 14 11 IDC 6 AB9 3l IDC 16 14 13 7 D9 33 IDC 17 Y13 15 IDC 8 C8 35 IDC 18 AB13 17 IDC 9 C9 37 IDC 19 W12 19 IDC_10 9 39 20 12 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 20 LCD DISPLAY LCD DISPLAY 100 LI 00 TE 200 too 00 The standard Drigmorn 4 LCD display is an LCM S01602DTR M display which is 16x2 alpha numerical display with a Hitachi HD44780 compatible chipset More information on this at http www lumex com specs LCM S01602DTR 20M pdf For OEM applications this LCD can be replaced by a 2x17 IDC header allowing remote location of the LCD or even reuse of the interface for other I O functions For these applications the 8 data signals are passed through bus switches giving 5V tolerance The remaining signals of this interface are not protected for 5V operation and should only be used with voltages less than 3 3V For OEM applications we can offer other display solutions with graphic colour LCD and OLED options Contact us for specific requirements Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 21 The IO pins used for the display are shown in the table below FUNCTION FPGA PIN Backlight ON VII RS 14 R W C13 EN 11 DO CI D1 17 D2 D17 D3 E16 D4 A15 D5 C15 D6 D15 D7 D14
10. near J11 3 If using an external power brick switch on your power source O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 8 A CPAS 1 y SPARTAN6 FPGA rit oc 00 oo oo oo 09 00 00 00 1 1 ioo ic 00 Drigmorn4 supports Spartan 6 devices the FGG484 package Drigmorn4 is normally available with commercial grade 2 speed devices fitted in the XC6SLX150 or XC6SLX75 size Should you have an application that needs industrial parts or faster speed grades please contact sales for a quote at boardsales enterpoint co uk O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 9 SPI FLASH MEMORY ES ETERS TT ELT Fe FF MEMORY 3 2 22 oo N o0 E 83 F 8 F oo 20 see 00 1 oo 00 SPIFLASH 06 oo 2 1 el 25 128 SPI flash memory device configures the FPGA when it is powered providing a suitable bitstream is programmed into the device The M25P128 has a capacity of 128Mbits with a single configuration bitstream for Drigmorn4 taking 4 1Mbits LX150 Any remaining space can be used for alternative configurations code and data storage After configu
11. the Micro SD Card Socket which is situated on the back of the Drigmorn 4 board To use this socket in a design you may need to obtain a license from the SD Association at http www sdcard org home The connections between the Micro SD Card Socket and the FPGA are shown below SDCARD SOCKET FPGA PIN DATA 0 Y2 DATA 1 W3 DATA 2 VI DATA 3 v2 CMD WI CLK POWER ON N MI The POWER ON N pin must be set LOW for power to be supplied to the SDCARD Reader Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 31 ACCELEROMETER 0000000000000 t ACCELEROMETER The Drigmorn 4 has an MMA7455L 3 axis accelerometer which has 3 sensitivity ranges 526 4g and 8g Typical applications for this device are tilt and motion sensing freefall detection and shock and vibration detection and these types of devices are used in cell phones anti theft equipment pedometers e compasses and for 3d gaming The datasheet for this accelerometer can be obtained from www freescale com This device has both SPI and I2C interfaces The connections between the accelerometer and the FPGA are shown below 7 INTI DRDY 8 J6 INT2 9 17 SDO 12 SDA SDI SDO 15 K2 SLC SPC 14 K6 IADDRO 4 FIXED 0V Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 52 0000000000000 0000000000000
12. 50 LX100 AVAILABLE ON LX150 LX100 LX75 LX25 AVAILABLE ON LX150 LX100 LX25 NSW AVAILABLE ON LX150 LX100 LX75 LX45 AVAILABLE ON LX150 LX100 LX45 LX25 1777777 AVAILABLE ON LX150 LX100 LX45 AVAILABLE ON LX150 LX45 LX25 EN AVAILABLE ON LX150 LX45 AVAILABLE ON ALL DEVICES Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 42 DGND B2 EXP P17 W18 IO L6P 2 B3 EXP NI7 Y18 L6N 2 B4 DGND B5 DGND A8 EXP N20 L20N 2 B8 DGND A9 EXP P18 V13 IO LI8P 2 B9 DGND AIO EXP 8 10 1183 2 BIO EXP P38 U14 IO LI4P 2 All P32 T7 IO L60P 2 EXP N38 IO 2 12 EXP N32 R7 IO L60N 2 2 EXP CLK SEL NOTE C 1 EXP CLK SEL NOTE C 0 Bl4 EXP P37 AAIO IO LAIP 2 AIS EXP P23 R11 IO LA40P 2 B15 EXP N37 ABIO IO LAIN 2 A16 EXP N23 IO 2 Bl6 EXP CLOCK S NOTE C RC SEL 17 EXP P24 W10 IO LAMP 2 B17 EXP CLOCK NOTE C 18 EXP N24 Y10 L44N 2 B18 5 NOTE E 19 EXP P25 W9 IO 2 B19 A20 EXP 5 Y9 IO LA7N 2 B20 5 NOTE E A21 EXP P26 WS IO L46P 2 B21 5 NOTE E A22 EXP N26 V7 IO L46N 2 B22 V5 NOTE E B23 5 FEED 1 NOTE E B24 5 FEED 1 NOTE E A25 EXP P28 Y7 IO_L48P_2 25 5V_FEED_1 NOTE E 26 EXP N28 AB7 IO LA8N 2 B26 5 FEED 1
13. BI d 51042 2 IM 5 44 PIN AI TER i b ren TOLLIT sm ddk S K pibus a EXPANSION EXPANSION HEADER 01 HEADER J100 PIN B30 PIN A30 PIN A30 On the reverse side of Drigmorn4 two CLP 130 02 L D A connectors which provide access to up to 38 LVDS pairs 76 single ended IO on the FPGA These connections are not available for all FPGA sizes but they are all connected for the XC6SLX150 device The connections between these expansion headers and the FPGA are shown below The suffix of the IO function denotes the FPGA Bank into which it connects Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 41 IO 1 7 0 A7 EXP N7 F15 IO LA7N 0 B7 EXP P6 Fl4 IO 1481 B8 EXP 6 4 1483 0 B9 EXP P8 H13 IO 146 0 BIO EXP IO L46N 0 B11 E12 IO L43P 0 B12 EXP D12 IO L43N 0 B17 XP_P9 13 IO_L45P_0 A18 EXP CLOCKI NOTE C B18 XP N9 13 IO 145 0 P A19 EXP CLOCKI NOTE C 20 EXP SUSPEN N15 NOTE A D A21 5 NOTE B 21 P33 22 Y4 B22 XP_N33 A23 2 F7 A24 REGI EN NOTE D A25 2 EN NOTE D A26 DGND A27 DGND 27 XP 1 9 O L50P 2 A28 DGND 28 XP N31 V9 O L50N 2 A29 DGND A30 DGND AVAILABLE ON LX1
14. LX75 device or smaller it is supported by the free ISE Webpack 11 1 SP4 or later available from Xilinx providing all the tools to enter and build a design Using this tool in conjunction with O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 7 your supplied programming cable you will also be able to program the Spartan 6 and the supporting SPI Flash that are on Drigmorn4 If your Drigmornd is fitted with an LX100 or LX150 device it will require the full Xilinx toolset to build a design ISE Webpack can be obtained directly from the Xilinx website at http www xilinx com ise Registration will be necessary to complete the download The full ISE toolset can also be purchased from the Xilinx website Once you have obtained your ISE tools 1 Connect your programming cable to the board and your PC hosting the Xilinx software 2 Connect the Drigmorn4 board to either a USB connector of a PC a USB power supply or a 5V source plugged into the 2 1mm Jack socket Note that some Laptops and desktop computer USB ports have a current limit of 100mA Drigmorn4 can exceed this in some circumstances and should you have a problem a powered USB hub or external mains to USB adaptor are recommended solutions Check that the 5V input selection jumper on J11 situated adjacent to the 5V jack socket is set to the correct position left for power from USB right for power into Jack socket Switch the power ON using the small standby switch
15. Programming Drigmorn4 0000000000000 8 o 0 6 o 0000000 HEADER The programming of the FPGA and SPI Flash parts on Drigmorn4 is achieved using the JTAG interface Principally it is anticipated that a JTAG connection will be used in conjunction with Xilinx ISE software although other alternatives do exist including self re programming The Spartan 6 series needs to be programmed using ISE 11 or higher Versions of ISE prior to 11 do not support Spartan 6 The full version of the Xilinx tools is required to program the XC6SLX150 2FGG484C The free Webpack version of ISE is sufficient to support the smaller versions of the FPGA There is a single JTAG chain on Drigmorn4 The JTAG chain allows the programming of the Spartan 6 and SPI Flash device The JTAG connector has a layout as follows top view GND GND GND TDI NC NC O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 45 Using iMPACT Boundary Scan the JTAG chain appears like this 150 bypass 1 Programming the FPGA directly Direct JTAG programming of the Spartan 6 FPGA is volatile and the FPGA will lose its configuration every time the board power 18 cycled For sustained use of an FPGA design programming the design into the Flash memory is recommended see 2 and 3 below Direct JTAG programming using bit files is useful for fast tempo
16. before programming are chosen Otherwise all defaults can be accepted The programming operation will take some time at least 3 or 4 minutes Depending upon the settings used when generating the bitfile using ISE it will take up to 20 seconds for the XC6L X150 to configure upon power up In order to decrease this time the following process can be followed 1 In the main ISE menu right click Generate Programming file Choose Properties 2 On the left hand side of the Process Properties Dialogue box choose Configuration Options 3 The first item on the menu which appears on the right hand side of the dialogue box is Configuration Rate The default setting is 2 Increase this number The maximum value we suggest is 22 Choose and OK 4 Generate the program file as normal O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 47 MECHANICAL ARRANGEMENT The Dimensions on the drawings below are millimetres mm sizes quoted are subject to manufacturing tolerances and should only be used as a general guide 54mm 5 TT a zo s 5 E d e o 04 40 64mm 71 65mm Locations of mounting holes and headers The socket pins on the DIL headers are arranged 2 45mm 0 1linch pitch Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 48 LLE uS ie sd
17. es enhancing the capabilities of your Drigmorn4 board Enterpoint has a wide range of modules suitable for the DIL Header Details at http www enterpoint co uk moelbryn modules modules html We can also offer custom design modules should our standard range not cover your requirement The DIL Headers will also support the use of crude prototype circuits using stripboard or other prototype materials The DIL Header connectors are arranged on a standard 0 linch 2 54mm pitch The horizontal pitch of the DIL Headers is 1 6 inches between the outer rows of the headers The inner pins of the header form continuous power strips allowing a range of modules to be used together in one header subject to sufficient pins being available The right hand side header has an inner column of 3 3V pins The LHS header has an inner column of DGND OV Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 15 USB ee re M ann Ls LE J 2219 121 FT2232H DEVICE MINI B USB SOCKET The USB interface on the Drigmorn 4 is achieved using an FT2232H USB 2 0 High Speed 480Mb s to UART FIFO device which can operate as a USB to dual serial parallel ports with a variety of configurations The datasheet and drivers for this device are available from http www ftdichip com When appropriate drivers are installed the Drigmorn4 USB port should be detected as a serial port Alter
18. ffer this service where a Drigmorn4 has been maltreated or otherwise deliberately damaged Please contact support if you need to use this service Other specialised warranty programs can be offered to users of multiple Enterpoint products Please contact sales on boardsales enterpoint co uk if you are interested in these types of warranty Support Please check our FAQ page for this product first before contacting support FAQ is located at http www enterpoint co uk drigmorn Drigmorn4 faq html Telephone and email support is offered during normal United Kingdom working hours GMT or GMT 1 9 00am to 5 00pm Telephone 44 0 121 288 3945 Email support enterpoint co uk O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 50
19. inated using suitable arrangements of resistors A timing loop has been implemented on the and connected to the between pins R19 and 18 to facilitate compensation for temperature and timing delays where necessary Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 13 DIL HEADERS OUTER PINS INNER RIGHT COLUMNS INNER OUTER PINS FUNCTION S6 PIN PINS PINS FUNCTION S6 PIN IO L65P 0 18 OV 3 3V 2 0 AA21 IO L65N 0 A18 OV 3 3V IO L2N 0 AB2I IO L63P 0 16 OV 3 3V IO L5P 0 Y19 IO L63N 0 16 OV 3 3V IO L5N 0 ABI9 IO L50P 0 14 OV 3 3V IO_L14P_0 AAI8 IO L50N 0 14 OV 3 3V IO LI4N 0 18 IO L37P 0 B12 OV 3 3V IO L15P 0 17 IO L37N 0 A12 OV 3 3V IO LI5N 0 ABI7 IO L35N 0 11 OV 3 3V IO L19P 0 16 IO L35P 0 11 OV 3 3V IO L19N 0 16 IO L34P 0 10 OV 3 3V IO L31P 0 AAI2 IO L34N 0 10 OV 3 3V IO 0 AB12 IO L6P 0 B8 OV 3 3V IO L45P 0 8 IO L6N 0 8 OV 3 3V IO 45 0 AB8 IO LAP 3 B6 OV 3 3V IO L49P 0 AB6 IO LAN 3 A6 OV 3 3V IO L49N 0 6 10 L5P 3 C7 OV 3 3V IO L57P 0 AAA IO L5N 3 7 OV 3 3V IO L57N 0 4 IO L32P 3 D7 OV 3 3V IO L64P 0 AA2 IO L32N 3 D8 OV 3 3V IO L64N 0 AB2 oo J ON Qi The DIL Headers provide a simple mechanical and electrical interface for add on modules There are twe
20. ique identity numbers The device used is a MAXIM DS2502 E48 of which further details can be found on http ww maxim ic com There are two sites on the Drigmorn4 for DS2502 E48 devices is a 6 pin TSOC6 site the other is a 3 pin TO 92 site The 6 pin device is defined as Mac Address 1 and the 3 pin device is defined as Mac Address 2 It should be straightforward to determine which of these 2 devices is fitted on your board The connections to the FPGA are shown below The table below shows the location of the MAC address devices on the Drigmorn 4 MAC ADDRESS DEVICE FPGA PIN 6 PIN TSOC6 DEVICE MAC ADDRESS 1 H3 3 PIN TO 92 DEVICE MAC ADDRESS 2 E6 O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 19 TOP IDC HEADER IDC HEADER At the top of the Drigmornd there is a 40 way IDC connector This has 20 IO connections to the FPGA and 20 DGND OV connections The IOs are wired directly to the Spartan 6 FPGA so signal voltage to these pins should not exceed 3 3V The connections between the IDC connector and the FPGA are shown below Pin 1 of the IDC header is defined as the pin on the left of the lower row of pins as viewed from the front of the board The odd numbered pins occupy the lower row of connections on the IDC header 1 IDC 1 C5 21 11 D10 3 IDC 2 A5 23 IDC 12 C10 5 IDC_3 D6 25 IDC 13 15 7 IDC 4 C6 27 IDC 14 ABI5 9 IDC 5 9 29
21. ise 00000000000000000000 o KSZ8851 ETHERNET DEVICE Y 0000000000000000001 RJ45 CONNECTOR E E imi Drigmorn4 Ethernet connector showing dimensions The Drigmorn4 Ethernet interface uses a Micrel KSZ8851SNL device The KSZ8851 incorporates a Fast Ethernet MAC PHY with an 8 16 32 bit generic host processor interface and SPI interface All datasheets and support documentation can be found on Micrel s website www micrel com Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 18 The connections between 578851 and the as shown below 578851 578851 DRIGMORN4 SIGNAL PIN PIN SIGNAL PME 2 D5 PME INTRN 3 D3 ETH INT N SI 31 DI SD IN SO 27 1 ETH SD OUT CSN 26 H8 CSN ETH SCLK 28 C3 SCLK RSTN 19 D2 RST N ETH X1 20 ES CLOCK ETHERNET Pin X1 of the KSZ8851SNL has been routed to the FPGA so that the Ethernet Clock frequency 25 2 can be provided by the FPGA You will need to implement this in any designs for the Ethernet to work The 578851 has been provided with an AT93C46E EEPROM as required by the specification It communicates to the outside world via an RJ45 connector Pulse J3006G21D which has green and yellow LEDs which indicate whether a connection to an Ethernet hub is present MAC ADDRESS DEVICES The Drigmorn4 has two MAC address devices fitted which assign the boards un
22. native data optimised drivers are also available from FTDI The FT2232H is connected to the Spartan 6 and has the capability of being configured in a variety of industry standard serial or parallel interfaces It is supported by an AT93C46E 1Kbit serial EEPROM which is used for configuration data Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 16 FT2232H device is also connected into the JTAG chain for the so that reconfiguration of the FPGA over USB is possible Jumper J14 will need to be set to the right position between pins 2 and 3 for this to be possible The connections between the USB device and the FPGA are shown below SIGNAL FT2232H FPGA PIN PIN ADBUSO 16 M7 ADBUSI 17 N7 ADBUS2 18 NI ADBUS3 19 N4 ADBUS4 21 N3 ADBUSS 22 P7 ADBUS6 23 P6 ADBUS7 24 P4 ACBUSO 26 5 ACBUSI 21 ACBUS2 28 R3 ACBUS3 29 RA ACBUSA 30 ACBUSS 32 T2 ACBUS6 33 T4 ACBUS7 34 Ul BDBUSO 38 TCK BDBUSI 39 TDI BDBUS2 40 TDO BDBUS3 41 TMS BDBUS4 43 P3 BDBUS5 44 P2 BDBUS6 45 BDBUS7 46 P8 BCBUSO 48 N6 BCBUSI 52 2 BCBUS2 53 5 BCBUS3 54 M6 BCBUS4 55 M8 BCBUSS 57 L3 BCBUS6 58 Ll BCBUS7 30 L6 PWREN 60 K4 SUSPEND 36 T3 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 17 ETHERNET A V
23. nents O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 3 Getting Started POWER SWITCH 2 1MM JACK 20 IO s on IDC FOR 5V HEADER SUPPLY 2X16 LCD DISPLAY was 4 4 4 13 LEDs 9 5 eo IGBIT DDR3 ow 52 MEMORY SPARTAN T 29 oo TU 2 PUSH BUTTON oo SWITCHES ETHERNET oo INTERFACE gt 4 en DIL HEADERS T WITH FORTY 5V td 00 TOLERANT 10 60 USB oo INTERFACE REAL TIME CLOCK MICRO SDCARD DN1306EN HOLDER ON BACK OF BOARD lt 4 16 CLOCK GENERATOR CONNECTOR BATTERY HOLDER FOR REAL TIME CLOCK ON ACCELEROMETER BACK RJ45 CONNECTOR ME X MINI USB FLASH TWO PS2 CONNECTOR MEMORY PORTS D Drigmorn4 front View O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 6 uma c 2010 Enterpoint Ltd iaa WW enter Point CO UK 35 45 44 4 24 49 NO EXPANSION HEADER EXPANSION HEADER BATTERY HOLDER FOR REAL TIME CLOCK MICRO SDCARD HOLDER Drigmorn4 Back View Your Drigmorn4 will be supplied un programmed Unless you have bought an OEM product your board will be supplied with either a Prog2 parallel port programming cable or a Prog3 USB port programming cable The Xilinx toolset required to program the Drigmorn4 depends upon the Spartan6 device fitted to the board If your Drigmorn4 is fitted with an
24. nty I O on each side of the DIL Header giving a total of 40 I O available Each of these I O pins is protected by bus switch technology to facilitate 5V tolerance on all of these pins Bus switch technology has a minimal effect on I O timing with propagation times of less than 250ps through these devices There are sites on the reverse side of the Drigmorn4 where pull up resistors to 5v may be fitted Drigmorn4 is normally shipped with these resistors not fitted If customers require any of these resistors to be fitted it is advised that they specify which are required so that they can be fitted before the board is shipped Enterpoint Ltd cannot be responsible for damage to the Drigmorn4 board by poor soldering The DIL Headers can also support up 20 pairs of LVDS signalling when not used for add on modules The Spartan 6 FPGA can terminate any of these pairs LVDS termination on individual signal pairs is a programmable option that can be set in build constraints for the FPGA when using the ISE toolset The LVDS pairs are shown in the table above along with Spartan 6 pin numbers O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 14 e a 7 w 1 2 T ve ru 14 4 00000000 ve 00 000000000000 00000 LEFT DIL HEADER RIGHT DIL HEADER The DIL Headers support the use of add on modul
25. nual Issue 2 0 16 02 2011 24 REAL TIME CLOCK 4 c 2010 Enterpoint Ltd a a WW enter POINT UK M N N c REAL TIME TE CLOCK oe Esa HOLDER FOR 96 REAL TIME v CLOCK The Drigmorn4 has a Maxim DS1306EN Serial Alarm Real time clock device with a 32 768KHz crystal Further information and datasheets for this device can be found On http ww maxim ic com The DS1306EN can provide a 32 768KHz clock timed interrupts and data storage features Please consult the device datasheet for more details The DS1306EN is supported by a battery holder that can take CR1220 1225 battery types We do not normally supply the battery to avoid shipping issues with batteries Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 25 The connections between the Real Time Clock device and FPGA shown below SIGNAL DS1306EN PIN FPGA PIN 9 FI SDI 15 DI INTI 8 F5 INTO 7 F3 32KHZ 18 El SDO 16 E3 SCLK 14 C4 CE 12 O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 POWER MONITOR AND MASTER RESET The Drigmorn4 has a voltage monitor which monitors the 3 3V 1 2V and 0 75V supplies within the board If any of these voltages are missing the reset signal is held active Connector J2 found at the very top left of the board provides a manual reset facility Placing a jumper between the cen
26. oided unless you know that your design does not consume more current than this A powered USB hub or a USB power supply can also be used Whatever power supply is used care should be taken not to exceed 5 5V input as this can cause damage to the Drigmorn4 The O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 35 power from the jack connector is limited by a 2 6 resettable fuse and the power from the USB connector is limited by a 1 1A resettable fuse and 3 3V are available on the DIL headers to power add on modules or the user s hardware The maximum current available from the 3 3v regulator is 6 amps however the actual maximum current available will be limited by the fuse on the 5v supply O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 36 POWER REGULATORS 0 75V ee REGULATOR 32 12 Got REGULATOR 99 13 31 LSV 55 REGULATOR E 00 279 00 m A oo 171 AT T1 06 00 100 3 3V 8 2 REGULATOR 60 t i oo oo Drigmorn4 has four regulators supplying 3 3V 1 5V 1 2 and 0 75V power rails WARNING REGULATORS CAN BECOME HOT IN NORMAL OPERATION ALONG WITH THE BOARDS THERMAL RELIEF PLEASE DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE DRIGMORN4 BOARD IS IN OPERATION A Micrel MIC22600 regulator supplies 3 3V with a maximum current available of 6A
27. rary programming during development of FPGA programs Right click the icon representing the Spartan 6 FPGA and choose Assign New Configuration File Navigate to your bit file and choose OPEN The next dialogue box will offer to add a flash memory and you should decline Right click the icon representing the Spartan 6 and choose Program On the next dialogue box ensure that the Verify box is not checked If it is you should uncheck it failure to do this will result in error messages being displayed Click OK The Spartan 6 will program This process is very quick typically one second 2 Programming the SPI flash memory using Boundary Scan Once the SPI Flash memory has been programmed the Spartan 6 device will automatically load from the Flash memory at power up Generation of suitable Flash memory files mcs can be achieved using ISE iMPACT s Prom File Formatter Right click on the icon representing the Spartan 6 and choose Add SPI BPI Flash Navigate to your programming file mcs and click OPEN Use the next dialogue box to select SPI flash and M25P128 Data width should be set to 1 The flash memory should appear as shown below TDI 150 bypass O Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 46 Right click on the icon representing the flash memory and choose Program to load your program into the device It is recommended that options to Verify and Erase
28. ration the SPI Flash can be accessed via the following pins of the FPGA Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 10 CCLK Y21 MOSI AB20 WRITE 15 DIN AA20 CSO B T5 The HOLD pin of this memory device is permanently connected to 3 3V The flash memory can be programmed using direct SPI programming from the 7x2 programming connector J8 To achieve this the jumper J14 must be connected between pins 1 and 2 left position Otherwise the jumper J14 should be connected between pins 2 and 3 right position so that normal JTAG programming can be achieved The connections to the SPI flash can also be accessed via the USB interface This option requires the jumper J14 to be connected between pins 2 and 3 left position The connections between the USB interface and the SPI flash memory are shown below BDBUSO 38 MOSI BDBUSI 39 DIN BDBUS2 40 CSO B BDBUS3 41 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 11 DDR3 MEMORY 113 28 eus PT ooa t V 3 on IGBIT DDR3 20000 6 y Q Le o o E o no 11 io Drigmorn4 has IGBIT DDR3 Micron MT41J64MI16LA device as standard This device is organised as 8 Meg x 16 x 8 banks This device is supported by the hard co
29. re memory controller that is in the Spartan 6 FPGA To add this core to your design the COREGEN tool part of the ISE suite will generate implementation templates in VHDL or Verilog for the configuration that you want to use More details on the memory controller can be found in the user guide http www xilinx com support documentation user_guides ug388 pdf Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 12 The DDR3 has 12 address lines and 16 data lines to address all the available memory which can be accessed at speeds of 1 87ns More details of the DDR3 can be found in http download micron com pdf datasheets dram ddr3 1Gb_DDR3_SDRAM pdf For OEM applications we can fit bigger DDR3 parts subject to limitations of the memory controller The DDR3 site has the following connections to the FPGA DDR3 FUNCTION DDR3FUNCTION FPGA PIN 21 DDR DQ3 M22 F22 DDR DQ4 J20 E22 DDR 05 J22 G20 DDR DQ6 21 20 DDR DQ7 22 20 DDR DQS P21 K19 DDR DQ9 P22 E20 DDR _DQ10 R20 C20 DDR R22 C22 DDR DQI2 U20 G19 DDR_DQ13 U22 F19 DDR_DQ14 V21 D22 DDR_DQ15 V22 D19 DDR_LDM L19 D20 DDR_LDQS L20 B21 DDR_LDQS_N 122 J17 DDR UDM M20 K17 DDR UDQS 121 18 DDR 0008 N 195 DDR CS N 20 G22 H2 H22 HI9 DDR RESET N F18 DDR DQO N20 D21 DDR DQI N22 J19 DDR DQ2 M21 H20 The signals shown shaded in yellow are term
30. rn 4 e ee a 4 c a hd 3 1 9000000000000000000 0000000000000000000 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 Introduction Welcome to your Drigmorn4 board Drigmorn4 is a Spartan 6 based FPGA development board offering a highly powerful flexible and low cost approach to prototyping FPGA and System designs The aim of this manual is to assist in using the main features of Drigmorn4 There are features that are beyond the scope of the manual Should you need to use these features then please email support Genterpoint co uk for detailed instructions Drigmorn4 currently comes with XC6SLX150 2FGG484C or XC6SLX75 2FGG484C Spartan 6 Other variants may be offered at a later date or as an OEM product Please contact out us on boardsales enterpoint co uk should you need further information Drigmorn4 is supported by a wide range of add on modules Some examples of these include ADC 7927 MODULE LED DOT MATRIX MODULE BUTTONS SWITCHES SATA MEMORY MODULE RS232 AND RS485 HEADER MODULES DP83816 ETHERNET MODULE SD CARD MODULE DDR2 MODULE IDE 5V TOLERANT CPLD MODULE USB MODULE D A CONVERTER MODULE ADV70202 MODULE We can also offer custom DIL Header modules should you require a function not covered by our current range of modules Typical turn around for this service is 6 8 weeks depending upon quantity ordered and availability of compo
31. s to provide an alternative clock source to the 25MHz oscillator provided on Drigmorn4 to select the clock source and to access clock signals from the Clock Generator The connections between the Expansion headers and the Clock Generator are shown below SIGNAL NAME EXPANSION HEADER CLOCK GENERATOR PIN PIN EXP CLOCK 17 5 EXP CLOCK SRC SEL B16 20 EXP CLOCK SELO B13 28 EXP CLOCK SELI B12 27 EXP_CLK1_P 18 14 19 15 D There are two signals the expansion header which allow the main regulators on the DNA to be shut down for purposes of power saving REGI EN controls the 1 2V regulator and REG2 EN controls the 3 3V regulator These signals should be asserted LOW to shut down a regulator leaving them unconnected allows the regulators to function normally E There is a choice of power sources for the expansion header 5v supply The supply on pins 18 22 of J101 is either from the Jack socket on Drigmorn4 J13 or from the USB connection to Drigmorn4 depending upon the setting of jumper J11 Pins B23 to B26 could if required be used to supply 5v from the expansion headers to power the Drigmorn4 Pins B27 to B30 could be used for a second alternative power supply e g a solar panel or a battery The Supply voltage should not exceed 5 5V as this would cause irreparable damage to the Voltage Regulators on Drigmornd Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 44
32. tre pin of J2 and the leftmost pin pin 1 will cause an active reset signal This header can also be used for an external system reset with a remote switch or relay wired across the pins The signal from the voltage monitor is connected to pin C12 of the FPGA a Da aa VOLTAGE MONITOR 00 00 71 18 00 00 00 Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 27 OSCILLATOR The main oscillator on the Drigmorn4 is an ASEM 50MHz oscillator The oscillator is situated as shown in and is connected to the on PIN 11 The Drigmorn 4 also has a Clock Generator see below fitted with 25MHz oscillator The Spartan 6 has PLLs and DCMs to produce multiples divisions and phases of the clock for specific application requirements Please consult the Spartan 6 datasheet available from the Xilinx website at http www xilinx com if multiple clock signals are required SAARBRAABZAAALAAA PAS ET eve OSCILLATOR rt oo oo 00 oo oo oo oo 1 2 i 85 c d uU Sdi d E EE a 4 is Enterpoint Ltd Drigmorn4 Manual Issue 2 0 16 02 2011 28 SWITCHES PUSH 43 32 23 BUTTON 00 SWITCH SW3 00 5 oo
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