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Arria 10 Transceiver PHY User Guide

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1. Transmitter PMA Transmitter Standard PCS FPGA Fabric ER Z g z 3 D D wo io n a5 5 ES i L 2 3 z oxi 5 i J PRBS Generator tx_coreclkin tx_clkout Jl I 4 12 14 tx_pma_div_clkout par Receiver PMA Receiver Standard PCS e gt 2 z i S g 5 fo O 8 a a n si g gt a Ler o 2s a z m e zj Ss 7 ele S N a 2 a a S 2 i o S rx_coreclkin Parallel Clock Recovered rx_clkout gt tx_clkout if Parallel Clock E 1214 rx_clkout or From Clock PRBS tx_clkout Divider Verifier t _pma_div_clkout Clock Generation Block CGB ATX PLL Clock Divider lt CMU PLL fPLL Parallel Clock Serial Clock Serial Clock Parallel and Serial Clock Parallel and Serial Clock Transmitter Datapath TX FIFO Shared with Enhanced PCS and PCle Gen3 PCS The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of data and status signals It compensates for the phase difference between the FPGA fabric clock and tx_clkout the low speed parallel clock The TX FIFO operates in low latency mode and registe
2. Partner A Parter B Encode 3 dmi Handshake q Change 4 5 Change Eq dmi Handshake q Decode e Parter C Data Transmission Pe Decod Adaptation Feedback gt ecode a q Feedback Handshake via Management Change Eq Ack Change dmo omi Handshake o moe M Data transmission proceeds clockwise from link partner A to B to C TX equalization includes the following steps which are identified in the figure 1 The receiving partner B calculates the BER for data received from transmitting partner A 2 The receiving partner B sends updates for TX link partner C 3 The receiving link partner C transmits an update to the transmitting link partner A 4 Transmit partner A updates its equalization settings 5 Transmit partner A acknowledges the change This procedure is repeated for the other two link partners Auto Negotiation The Auto Negotiation module in the 10GBASE KR PHY IP implements Clause 73 of the IEEE 802 3 Standard 2008 This module currently supports auto negotiation between 1GbE and 10GBASE R data rates Auto negotiation with XAUI is not supported Auto negotiation runs at power up or if the sequencer module is reset Reconfiguration Block The Reconfiguration Block performs the Avalon MM writes to the PHY for both PCS and
3. 9 Simulate your design to verify its functionality Figure 2 23 24 Lanes Bonded Interlaken Link TX Direction Reset PLL and CGB Reset gt PLLIP Controller TX RX Analog Digital Reset TX Clocks a TX FIFO Status Control and Status TX Soft Bonding TX FIFO Control Pattern Generator TX Data Stream Arria 10 Transceiver q PX FIFO Status Neder shy RX Control and Status Deskew RX FIFO Control _ gt Pattern Verifier p RX Data Stream To show more details three different time segments are shown with the same zoom level Pre Fill Completed Send Data tx_ready Pre Fill Assert burst_en for Based on Asserted Stage All Lanes FIFO Flags pll_locked 5 tx_analogreset 241000000 3 247000000 J 24000000 ockout o UL UUUU UU UL LIU _clkout i tx_digitalreset 24 h0d0000 i S 24n000000 A 247000000 t tx_readyf0 5 i tx_ready 24 2ahtffff Ys hittttt Q 2a hififit tx_enh_data_valid 0 i i tx_enh_data_valid 24h000000 24 hifffff p 27 247000000 G 24h000000 ae hit 24000000 tx_enh_fifo_full 24 hooo000 Jaane Sy 2a hettt O24 hit _24 ho00000 tx_enh_frame 0 Gv tx_enh_frame 247000000 Jee hoo0000 Y 27h00 24h000000 YT 27h000000 tx_enh_frame_burst_en 0 5 tx_enh_frame_burst_en 24hfffff 24 ho00000
4. tx_pma_div_clkout tx clkout Receiver PMA Receiver Standard PCS gt pe 2 o oO wo P F a z S P 16 2 o 8 a 2 2 w day sie y gt gt gt S rer o zs a gt lo N 2 Ir gt 8 2 g 2 3 S g a E s rx_coreclkin Parallel Clock J Recovered AI rx_clkout I gt l 125 MHz 1 ix okout ied t 62 Mid 1 Parallel Clock 12 rx_clkout or From Clock PRBS tx_clkout Divider Verifier rx_pma_div_clkout Clock Generation Block CGB ATX PLL Clock Divider lt CMU PLL fPLL Parallel Clock Serial Clock Serial Clock Parallel and Serial Clock Parallel and Serial Clock Notes 1 The parallel clock tx_clkout or rx_clkout is calculated as data rate PCS PMA interface width 1250 10 125 MHz When the Byte Serializer is set to Serialize x2 mode tx_clkout and rx_clkout become 1250 20 62 5 MHz 2 The serial clock is calculated as data rate 2 The PMA runs on a dual data rate clock 3 This block is only enabled when using the Basic with Rate Match transceiver configuration rule In low latency mode much of the Standard PCS is bypassed which allows more design control in the FPGA fabric Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Word Aligner Manual Mode 2 233 Figure 2 101 Transceiver Channel Datapath and Clocking for Basic Configuration with Low Latency Enabled The
5. rx_digital_reset _ rx_digital_reset rx_clkout gt rx_clkout rx_coreclkin rx_coreclkin gt CDR rx_parallel_data 127 0 gt rx_parallel_data 127 0 gt rx_control 19 0 gt rx_control 19 0 A refclk Note For GT transceiver channels all the individual functional blocks within the enhanced PCS are not enabled and are bypassed to provide the lowest latency PCS from the PMA rx_control and tx_control ports are not used 4 Open the MegaWizard Plug In Manager and select ATX PLL IP Refer to Instantiating ATX PLL on page 3 5 for detailed steps 5 Configure the ATX PLL IP using the MegaWizard Plug In Manager e Select the GT clock output buffer e Enable the PLL GT clock output port e Set the PLL output clock frequency to the Native PHY IP recommended frequency Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 How to Implement Designs for Data Rates Above 17 4 Gbps Using Enhanced PCS in Low Latency Mode 2 255 Figure 2 133 ATX PLL IP with GT Clock Lines Enabled Arria 10 Transceiver ATX PLL ATXPLL Tk Arria 10 Transceiver ATX PLL Megetore altera_xcvr_atx_pll_a10 Presets for ATXPLL xa Block Diagram PLL Master Clock Generation Block Dynamic Reconfiguration Generation Op Show signals 4 Bene Project Message level for
6. Arria 10 Transceiver PHY Overview CJ Send Feedback GX 115 RF40 Si in GXBL1H Transceiver GX 090 RF40 Transceiver GXBR4J Bank Bank Then GXBL1G Transceiver Transceiver GXBR4I Bank Bank GXBL1F mo PCle PCle D i GXBR4H Gen1 Gen3 Gen1 Gen3 Hard IP Hard IP GXBL1E Transceiver Transceiver GXBR4G Bank Bank GXBL1D Transceiver Transceiver GXBR4F Bank Mole Bank Gent Gen3 Hard IP with CvP GXBL1C Transceiver Transceiver GXBR4E 1 Bank Bank 2 Notes 1 Nomenclature of left column bottom transceiver banks always begins with C 2 Nomenclature of right column bottom transceiver banks may begin with C D or E Legend PCle Gent Gen3 Hard IP blocks with CvP capabilities PCle Geni Gen3 Hard IP blocks without CvP capabilities Altera Corporation 7 z UG A10XCVR 1 6 Arria 10 GX Device Transceiver Layout 2013 12 02 Figure 1 5 Arria 10 GX Devices with 48 36 and 24 Transceiver Channels and Two PCle Hard IP Blocks CH5 CH4 aA Transceiver CH3 Transceiver CH2 Bank CH1 CHO Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank PCle Gen1 Gen3 Hard IP with CvP Transceiver Bank Note 1 These devices ha
7. RX word aligner mode Synchronous state machine RX word aligner pattern length 7 10 RX word aligner pattern hex a A A et a Number of word alignment patterns to achieve sync 3 Number of invalid data words to lose sync 3 Number of valid data words to decrement error count 3 Enable rx_std_wa_patternalign port Off Enable rx_std_wa_ala2size port Off Enable rx_std_bitslipboundarysel port Off Enable rx_bitslip port Off Enable TX bit reversal Off Enable TX byte reversal Off Enable TX polarity inversion On Off Enable tx_polinv port On Off Enable RX bit reversal Off Enable rx_std_bitrev_ena port Off Enable RX byte reversal Off Enable rx_std_byterev_ena port Off Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 92 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC UG A10XCVR 2013 12 02 Parameters VELTS Enable RX polarity inversion On Off Enable rx_polinv port On Off Enable rx_std_signaldetect port On Off All options under PCIe Ports off 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC Arria 10 transceivers can implement the 10GBASE R 10GBASE R with 1588 and 10GBASE R with FEC protocols using the 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC Transceiver Configuration Rules respectively 10GBASE R is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in clause 49 of the
8. 0 63 4 z y encoded 10 1e 000000 00000000 10 78D D D D D D D 01 D D D D D D D D 10 b4 D D D 00000000 data oO 65 Enhanced PCS Pattern Generators The Enhanced PCS supports pseudo random bit sequence PRBS pattern and square wave pattern generators The pattern generators or verifiers in the Enhanced PCS are enabled by writing to the respective register bits of the Transceiver and PLL Address Map Refer to the Transceiver and PLL Address Map for configuration details PRBS Generator The PRBS generator block generates PRBS patterns and square wave patterns PRBS test patterns may be considered equivalent to noise Use these pattern generators to test the transceiver link with a noisy signal using the test patterns listed below by placing the transceiver in loopback mode The PRBS generator supports a 64 bit PCS PMA interface PRBS9 supports 64 bit and 10 bit PCS PMA interface widths to allow testing at lower data rates The following PRBS test patterns are supported e PRBS9 x x 41 e PRBS15 x gt x4 41 e PRBS23 x x 1 e PRBS31 x x 1 Enable the PRBS generator and select a test pattern through the reconfiguration interface Use PRBS9 to test transceiver links with linear impairments and with 8B 10B Use PRBS15 for jitter evaluation Use PRBS23 or PRBS31 for jitter evaluation data dependent jitter of non 8B 10B links su
9. rx_syncstatus rx_patterndetect rx_disperr rx_errdetect rx_ready tx_ready Related Information Word Aligner on page 5 37 Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 84 8B 10B Decoding for GbE GbE with 1588 2013 12 02 8B 10B Decoding for GbE GbE with 1588 The general functionality for the 8B 10B decoder is to take a 10 bit encoded value as input and produce an 8 bit data value and 1 bit control value as output The following figure shows Dx y 8d Dx y a4 K28 5 bc Dx y 50 received at rx_parallel_data K28 5 is set as the word alignment pattern rx_patterndetect goes high whenever it detects K28 5 bc rx_datak is high when bc is received indicating that the decoded word is a control word Otherwise rx_datak is low rx_runningdisp is high for 8d indicating that the decoded word has negative disparity and a4 has positive disparity Figure 2 30 Decoding for GbE rx_datak rx_parallel_data 8d X a4 x be X 50 8d X a4 X bc X 50X 8d X ad X be X 50X ad X ad X bc 4 50 rx_patterndetect tx_disperr rx_errdetect rx_runningdisp Related Information 8B 10B Decoder on page 5 42 Rate Match FIFO for GbE The rate match FIFO is capable of compensating for up to 100 ppm 200
10. Transceiver PHY Architecture Overview A link is defined as a single entity communication port A link can have one or more transceiver channels A transceiver channel is synonymous with a transceiver lane For example a 1OGBASE R link has one transceiver channel or lane with a data rate of 10 3125 Gbps A 40GBASE R link has four transceiver channels Each transceiver channel operates at a lane data rate of 10 3125 Gbps Four transceiver channels give a total collective link bandwidth of 41 25 Gbps 40 Gbps before and after 64B 66B PCS encoding and decoding Transceiver Bank Architecture The transceiver bank is the fundamental unit that contains all the functional blocks related to the device s high speed serial transceivers Each transceiver bank includes six transceiver channels in all devices except for the devices with 66 transceiver channels These devices with 66 transceiver channels have both six channel and three channel transceiver banks The uppermost transceiver bank on the left and the right side of these devices is a three channel transceiver bank All other devices contain six channel transceiver banks The figures below show the transceiver bank architecture with the phase locked loop PLL and clock generation block CGB resources available in each bank 11 12 13 14 15 Package U19 19mm x 19mm package 484 pins Package F27 27mm x 27mm package 672 pins Package F29 29mm x 29mm
11. ei GT 115 SF45 ransceiver Transceiver GXBR4H cae Bank GT 090 SF45 Bank XBL1 _ Transceiver Transceiver XBRAG G G Bank Bank G GXBL1F laa PCle PCle patil GXBRAF Geni Gen3 Geni Gen3 Hard IP Hard IP GXBL1E Transceiver Transceiver GXBR4E Bank Bank i i XBR4D GXBL1D oe PCle PCle en G Geni Gen3 Geni Gen3 Hard IP Hard IP with CvP GXBLIC Transceiver Transceiver GXBR4C 1 Bank Bank 2 1 Nomenclature of left column bottom transceiver banks always begins with C 2 Nomenclature of right column bottom transceiver banks may begin with C D or E Legend a GT transceiver channels channel 0 1 3 and 4 PCle Geni Gen3 Hard IP blocks with CvP capabilities PCle Geni Gen3 Hard IP blocks without CvP capabilities m Transceiver channels that cannot be used channel 2 and 5 when all four GT channels in the bank are used Arria 10 Transceiver PHY Overview GJ Send Feedback Altera Corporation z UG A10XCVR 1 10 Arria 10 GT Device Transceiver Layout 2013 12 02 Figure 1 10 Arria 10 GT Devices with 48 Transceiver Channels and Two PCle Hard IP Blocks GT 115
12. The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the Transmit PLL The Transceiver PHY Reset Controller IP core receives status from the Transceiver PHY and the Transmit PLL Based on the status signals or the reset input it generates TX and RX reset signals to the Transceiver PHY and TX PLL Thetx_ready signal indicates whether the TX PMA exits the reset state and if the TX PCS is ready to transmit data The rx_ready signal indicates whether the RX PMA exits the reset state and if the RX PCS is ready to receive data You must monitor these signals to determine when the transmitter and receiver are out of the reset sequence Altera Corporation CJ Send Feedback UG A10XCVR 4 10 Parameterizing the Transceiver PHY Reset Controller IP 2013 12 02 Parameterizing the Transceiver PHY Reset Controller IP This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the MegaWizard Plug In Manager You can customize the following Transceiver PHY Reset Controller parameters for different modes of operation by clicking Tools gt MegaWizard Plug In Manager To parameterize and instantiate the Transceiver PHY Reset Controller IP core 1 2 3 For Which device family will you be using select your target device from the list Click Installed Plug Ins gt Interfaces gt Transceiver PHY gt Transceiver PHY Reset Controller lt version gt Select the options required for your des
13. ATX PLLO Notes 1 The figure shown is just one possible combination for the PCle Gen1 Gen2 x1 mode 2 Geni Gen2 x1 mode uses the ATX PLL or fPLL 3 Gen1 Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled 4 Use the pll_pcie_clk from either the ATX PLL or fPLL This is the hclk required by the PIPE interface Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 192 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode Figure 2 78 Use ATX PLL or fPLL for Gen1 Gen2 x4 Mode Altera Corporation fPLL1 ATX PLL1 Notes OnorwWNnr Connections Done via X1 Network Master CGB X6 Network y Chs5 CGB CDR Ch4 CGB CDR Ch3 CGB CDR Ch2 CGB CDR CGB Chi CDR Cho CGB j CDR The figure shown is just one possible combination for the PCle Gen1 Gen2 x4 mode The x6 and xN clock networks are used for channel bonding applications Each master CGB drives one set of x6 clock lines Gen1 Gen2 x4 mode use the ATX PLL or fPLL Use the pll_pcie_clk from either the ATX or fPLL This is the hclk required by the PIPE interface
14. TX channel bonding mode Non bonded TX local clock division factor 1 2 4 8 Number of TX PLL clock inputs per 1 2 3 4 channel Initial TX PLL clock input selection 0 Table 2 74 RX PMA Parameters Number of CDR reference clocks 1to5 Selected CDR reference clock 0to4 Selected CDR reference clock frequency 322 265625 and 644 53125 MHz PPM detector threshold 62 5 100 125 200 250 300 500 1000 Decision feedback equalization mode disabled Table 2 75 Enhanced PCS Parameters Enhanced PCS PMA interface width 32 40 64 Note 1O0GBASE R with KR FEC allows 64 only FPGA fabric Enhanced PCS interface 66 width Enable RX TX FIFO double width mode Off Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR m 2013 12 02 Native PHY IP Parameter Settings for 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC 2 101 TX FIFO mode e Phase Compensation 10GBASE R and 10GBASE R with KR FEC e Register 10GBASE R with 1588 TX FIFO partially full threshold 11 TX FIFO partially empty threshold 2 RX FIFO mode 10GBASE R 10GBASE R and 10GBASE R with KR FEC e Register 10GBASE R with 1588 RX FIFO partially full threshold 23 RX FIFO partially empty threshold 2 Table 2 76 64B 66B Encoder and Decoder Parameters Enable TX 64B 66B encoder On Enable RX 64B 66B decoder On Enable TX sync
15. Ordered Set y m Y na K na X Ica X Related Information 8B 10B Encoder on page 5 33 Reset Condition for 8B 10B Encoder in GbE GbE with 1588 After deassertion of tx_digitalreset the transmitters automatically transmit at least three K28 5 comma code groups before transmitting user data on the tx_parallel_data port This could affect the synchronization state machine behavior at the receiver Depending on when you start transmitting the synchronization sequence there could be an even or odd number of Dx y code groups transmitted between the last of the three automatically sent K28 5 code groups and the first K28 5 code group of the synchronization sequence If there is an even number of Dx y code groups received between these two K28 5 code groups the first K28 5 code group of the synchronization sequence begins at an odd code group boundary The synchronization state machine treats this as an error condition and goes into the loss of sync state Figure 2 28 Reset Condition clock tx_digitalreset Automatically ensinei 1K28 5 User tran e synchronization sequence User transmitted data Altera Corporation Implementing Protocols in Arria 10 Transceivers C Send Feedback UG A10XCVR 2013 12 02 Word Alignment for GbE GbE with 1588 2 83 Word Alignment for GbE GbE with 1588 The word aligner for the GbE and GbE wi
16. fbclk Lines C M and CGB Outputs To support PLL feedback compensation bonding and PLL cascading the following connections are present 1 The divided clock output the C counter output for PLL or M counter output for ATX PLL of all PLLs drives the feedback and cascading clock network 2 The feedback and cascading clock network drives the feedback clock input of all PLLs 3 The feedback and cascading clock network drives the reference clock input of all PLLs 4 The master CGB s parallel clock output drives the feedback and cascading clock network For PLL cascading connections 1 and 3 are used to connect the output of one PLL to the reference clock input of another PLL Arria 10 transceivers support only fPLL to fPLL or fPLL to ATX PLL cascading PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 40 Using PLLs and Clock Networks 2013 12 02 For PLL feedback compensation bonding connections 2 and 4 are used to connect the master CGB s parallel clock output to the PLL feedback clock input port PLL feedback compensation bonding can be used instead of xN bonding The primary difference between PLL feedback compensation and xN bonding configurations is for PLL feedback compensation the bonded interface is broken down into smaller groups of 6 bonded channels within a transceiver bank A PLL within each transceiver bank ATX PLL or fPLL is used as a transmit PLL All the transmit PLLs
17. tx_pma_clkout Output Clock This is the parallel clock from the TX PMA It is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP GUI tx_pma_div_clkout Output Clock This is a divided version of the recovered parallel clock It is available when you turn on Enable tx_pma_div_ clkout port in the Transceiver Native PHY IP GUI You can divide the parallel clock by 1 or 2 You can divide the serial clock by 33 40 or 66 tx_pma_ Input Asynchronous When asserted this signal forces the transmitter to lecidle lt n gt 1 0 electrical idle This port has no effect when you configure the transceiver for the PCI Express protocol tx_pma_ Input Asynchronous This port is available if you turn on Enable tx_pma_ api punmono EO qpipullup port QPI in the Transceiver Native PHY IP GUL It is only used for Quick Path Interconnect QPI applications tx_pma_ Input Asynchronous This port is available if you turn on Enable tx_pma_ qpipulldn lt n gt 1 0 qpipulldn port QPI in the Transceiver Native PHY IP GUL It is only used for Quick Path Interconnect QPI applications tx_pma_ Input Asynchronous This port is available if you turn on Enable tx_pma_ txdetectrx lt n gt txdetectrx port QPI in the Transceiver Native PHY 130 IP GUI When asserted the receiver detect block in TX PMA detects the presence of a transmitter at the other end of the channel After receiving tx_pma_ txdet
18. Configure the Native PHY IP using the MegaWizard Plug In Manager Set the Native PHY IP TX Channel bonding mode to Non Bonded Connectivity e Connect the PLL IP to Native PHY IP e Connect the tx_serial_clk output port ofthe PLL to IP to the corresponding tx_serial_clk0 input port of the Native PHY IP This port represents the input to the local CGB of the channel The tx_serial_clk for the PLL represents the high speed serial clock generated by the PLL Multi Channel x1 Non Bonded Configuration This configuration is an extension of the x1 non bonded case In the following example 10 channels are connected to two instances of the PLL IP Two PLL instances are required because PLLs using the x1 clock network can only span the 6 channels within the same transceiver bank A second PLL instance is required to provide the clock to the remaining 4 channels Because 10 channels are not bonded and are unrelated you can use a different PLL type for the second PLL instance It is also possible to use more than two PLL IPs and have different PLLs driving different channels If some channels are running at different data rates then you need different PLLs driving different channels PLLs and Clock Networks Altera Corporation GJ Send Feedback UG A10XCVR 3 42 Multi Channel x1 Non Bonded Configuration 2013 12 02 Figure 3 18 PHY IP and PLL IP Connection for Multi Channel x1 Non Bonded Configuration Transc
19. In this case the Master PCS channel is logical channel 3 physical channel 4 UG A10XCVR 2013 12 02 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode 2 193 Figure 2 79 Use ATX PLL or fPLL for Gen1 Gen2 x8 Mode e Chs5 CGB J4 CDR 6 6 6 A Y Cha CGB CDR Master 6 CGB Ch3 CGB CDR One HSSI Ch2 Tile Connections Done CGB via X1 Network PLL i CDR Use Any One PLL Ch1 ATX PLL1 t i CDR cho CGB e CDR Ch5 4 CGB CDR One Chi HSSI Tile 4x6 CGB Master CGB CDR Notes 1 Figure shown is just one possible combination for the PCle Gen1 Gen2 x8 mode 2 The x6 and xN clock networks are used for channel bonding applications 3 Each master CGB drives one set of x6 clock lines The x6 lines further drive the xN lines 4 Gen1 Gen2 x8 mode use the ATX PLL or fPLL 5 Use the pll_pcie_clk from either the ATX or fPLL This is the hclk required by the PIPE interface 6 In this case the Master PCS channel is logical channel 4 Ch 1 in the top bank Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR
20. N AJ Oy RO Rx_DATA_READY When set to 1 indicates the PHY is ready to receive data PMA Registers The PMA registers allow you to reset the PMA customize the TX and RX serial data interface and provide status information E 0x422 lt p gt 1 0 pma_tx_pll_is__ Indicates that the TX PLL is locked to the input locked reference clock lt p gt is the number of PLLs 0x444 1 RW reset_tx_digital Writinga 1 causes the internal TX digital reset signal to be asserted You must write a 0 to clear the reset condition 2 RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted You must write a 0 to clear the reset condition RW reset_rx_digital Writing a 1 causes the internal RX digital reset signal to be asserted You must write a 0 to clear the reset condition 0x461 31 0 RW phy_serial_ Writing a 1 puts the channel in serial loopback loopback mode 0x464 31 0 RW pma_rx_set_ When set programs the RX CDR PLL to lock to the locktodata incoming data 0x465 31 0 RW pma_rx_set_ When set programs the RX clock data recovery locktoref CDR PLL to lock to the reference clock 0x466 31 0 RO pma_rx_is_ When asserted indicates that the RX CDR PLL is lockedtodata locked to the RX data and that the RX CDR has changed from LTR to LTD mode 0x467 31 0 RO pma_rx_is_ When asserted indicates that the RX CDR PLL is lockedtoref locked t
21. 1G Ref CLK CMU PLL 10G Ref CLK ATX PLL Reset Contro Reset Contro Reset Contro Reset Contro Test Harness THO_ADDR OxFnnn Test Harness TH1_ADDR 0xEnnn XGMI Source XGMIl Sink XGMI GEN XGMIl CHK KR PHY IP NF Reconfiguration Re Aval gisters CSR lon MM S 1588 Soft FIFOs Sequencer GMIl RS Auto Neg cls 73 Link Training cls 72 Native Hard TX PMA Divide q _ _ Divide Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Simulation Support 2 149 Related Information e Arria 10 Transceiver PHY Design Examples e Ethernet MAC MegaCore Function User Guide For more information about this design example Simulation Support The 1G 10GbE and 10GBASE KR PHY IP Core supports ModelSim Verilog and ModelSim VHDL VCS Verilog and VCS VHDL simulation Arria 10 devices also support NCSIM Verilog and NCSIM VHDL simulation The MegaWizard Plug In Manager generates an IP functional simulation model when you press the Finish button TimeQuest Timing Co
22. Altera Corporation input N A 2 bit PCle rate switch control input PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 CMU PLL 3 19 pcie_sw_done output 2 bit PCIe rate switch status output pll_cascade_clk output N A fPLL to fPLL cascading clock output port atx_pll_cascade_clk activeclk output output N A fPLL to ATX PLL cascading clock output port Creates an output signal that indicates the input clock being used by the PLL A logic Low on this signal indicates refc1k0 is being used and a logic High indicates refclk1 is being used Related Information Avalon Interface Specifications The ports related to reconfiguration are compliant with the Avalon Specification Refer to the Avalon Specification for more details about these ports CMU PLL The clock multiplier unit CMU PLL channel PLL CDR resides locally within each transceiver channel The channel PLL s primary function is to recover the receiver clock and data in the transceiver channel In this case the PLL is used in clock and data recovery CDR mode When the channel PLL of channel 1 and 4 is configured in the CMU mode the channel PLL can drive the local clock generation block CGB of its own channel However when the channel PLL is used as a CMU PLL the channel can only be used as a transmitter channel as the CDR block is not available to recover the received
23. Auto Speed Negotiation PIPE Gen3 mode enables ASN between Gen1 2 5 Gbps Gen2 5 0 Gbps and Gen3 8 0 Gbps signaling data rates The signaling rate switch is accomplished through frequency scaling and configuration of the PMA and PCS blocks using a fixed 32 bit wide PIPE 3 0 based Interface The PMA switches clocks between Gen1 Gen2 and Gen3 data rates For a non bonded x1 channel an ASN module facilitates speed negotiation in that channel For bonded x2 x4 and x8 channels the ASN module selects the master channel to control the rate switch The master channel distributes the speed change request to the other PMA and PCS channels The PCIe Gen3 speed negotiation process is initiated by a rate change requested from Hard IP or FPGA FABRIC The ASN then places the PCS in reset and dynamically shuts down the clock paths to disengage the current active state PCS either Standard PCS or Gen3 PCS If a switch to or from Gen3 is requested Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 188 Rate Switch 2013 12 02 the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers The ASN block then sends a request to the PMA block to switch the data rate and waits for a rate change done signal for confirmation When the PMA completes the rate change and sends confirmation to the ASN block the ASN enables the clock paths to engage the new PCS block and
24. Enable PCIe clock output port On Off Exposes the p1l_pcie_clk port used for PCI Express PLL output frequency Specify the target output frequency for the PLL PLL reference clock frequency 100 MHz to 800 Selects the input reference clock frequency for the MHz PLL Effective M Counter Read only Displays the effective M counter value Divide factor N Counter Read only Displays the effective N counter value Divide factor L Counter Read only Displays the effective L counter value Table 3 3 ATX PLL Master Clock Generation Block Parameters and Settings Include Master Clock Generation On Off When enabled includes a master CGB as a part of the Block ATX PLL IP The PLL output drives the Master CGB This is used for x6 xN bonded and non bonded modes Clock division factor 1 2 4 8 Divides the master CGB clock input before generating bonding clocks Enable x6 xN non bonded high On Off Enables the master CGB serial clock output port used speed clock output port for x6 xN non bonded modes Enable PCIe clock switch On Off Enables the control signals for the PCIe clock switch interface circuitry Used for PCle clock rate switching Number of auxiliary MCGB 0 1 Auxiliary input is used for PCIe Gen3 clock input ports MCGB input clock frequency Read only Displays the master CGB s required input clock frequency MCGB output data rate Read only Displays the master CGB s output data rate 8 You
25. Enable rx_divclk port On Off When you turn this option on the rx_divclk port is enabled Refer to clock and reset signals section for more information about his port Enable tx_clkout port On Off When you turn this option on the tx_clkout port is enabled Refer to clock and reset signals section for more information about his port Enable rx_clkout port On Off When you turn this option on the rx_clkout port is enabled Refer to clock and reset signals section for more information about his port 10GBASE R Parameters The 1OGBASE R parameters specify basic features of the 1OGBASE R PCS The FEC options also allow you to specify the FEC ability Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Table 2 108 10GBASE R Parameters 10M 100M 1Gb Ethernet Parameters 2 157 a opon T Deto Reference clock frequency 644 53125 MHz 322 265625 Specifies the input reference clock frequency The default is 322 265625MHz Enable additional control and status pins On Off When you turn this option on the core includes the rx_block_lock and rx_hi_ber ports Table 2 109 FEC Options A T Deptan Include FEC sublayer On Off When you turn this option on the core includes logic to implement FEC and a soft 10GBASE R PCS Set FEC_ability biton power On Off When you turn this option on the core sets the up and reset Assert KR FEC Abili
26. 3 Receiver PMA Receiver Enhanced PCS B rx_pma _div_clkout gt 64 bits Ej i 5 data S i xX o 6 g no cs N x N ge 2 se co g 3 bits 3 x N x Pi Se E Se ge m A control S cj 40 g 45 a 5 S 0 5 oo zD 8 gt i 2E p sl p tem S e fa e ie B i 5 2 Lai Ze p pa gg lad ai ER 5 i A Z a a i EO x n a a x a oO ui 186 97 MHz to 312 5MHz r Div 40 P Parallel Clock 312 5 MHz rx_clkout Clock Generation Block CGB 6 25 GHz Data rate 2 ATX PLL ad Clock Divider z PLL CMU PLL Parallel Clock petal clerk Parallel and Serial Clocks Senalcioes Parallel and Serial Clocks Input Reference Clock Related Information e Interlaken Protocol Definition v1 2 e Interlaken Look Aside Protocol Definition v1 1 Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 64 Metaframe Format and Framing Layer Control Word 2013 12 02 Metaframe Format and Framing Layer Control Word The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words However for stability and performance Altera recommends you set the frame length to no less than 128 words In simulation use a smaller metaframe length to reduce simulation times The payload of a metaframe could be pure payload and Burst Idle control word from MAC layer Figure 2 10 Framing Layer Metaframe Format Metaframe Length Se Control and Data Words Diagnostic Synchronizati
27. A PMA is the transceiver s electrical interface to the physical medium The transceiver PMA consists of standard blocks such as e serializer deserializer SERDES e clock and data recovery PLL e analog front end transmit drivers e analog front end receive buffers The PCS can be bypassed with a PCS Direct configuration Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs In PCS Direct configuration the data flow is through the PCS block but all the internal PCS blocks are bypassed In this mode the PCS functionality is implemented in the FPGA fabric The GX Transceiver Channel Figure 1 17 GX Transceiver Channel in Full Duplex Mode Transmitter PMA Transmitter PCS FPGA Fabric Standard PCS ial g POle Gens PCs lg 2 Sot PIPE HiP SH Serializer 5 Optional Optional A Q 2 lt 4 4 Receiver PMA k Receiver PCS Standard PCS KR FEC I gt CDR p Deserializer Notes 1 PCS Direct support will be available in a future release of the Quartus lI software 2 The FPGA Fabric PCS and PCS PMA interface widths are configurable Arria 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between of 611 Mbps to 17 4 Gbps Table 1 6 PCS Types Supported b
28. CGB 1 z CDR Cho CGB 1 0 CDR Note 1 The local CGB is bypassed by the clock input ports in bonded mode Related Information xN Clock Lines on page 3 29 Information on xN Clock Network Span Altera Corporation PLLs and Clock Networks J Send Feedback pooner R PLL Feedback Compensation Bonding Mode 3 47 PLL Feedback Compensation Bonding Mode In this bonding mode the data rate limitations of xN bonding mode are removed This is achieved by dividing all channels into multiple bonding groups Each bonding group is driven by its own set of high speed serial and low speed parallel clocks Each bonding group has its own PLL and master CGB The PLL and the master CGB for different groups share the same reference clock in order to maintain the same phase relationship The following steps explain the PLL feedback compensation bonding process 1 The same input reference clock drives the local PLL in each triplet or a 6 channel transceiver bank 2 The local PLL for the bonding group drives the master CGB 3 The master CGB feeds the x6 clock line Master CGB drives the transceiver channels in the bonding group via the x6 clock network 4 The parallel output of the master CGB is the feedback input to the PLL 5 All channels are phase aligned to the same input reference clock Figure 3 23 PHY IP and PLL IP Connection for PLL Feedback Compensation Bonding Transceive
29. CJ Send Feedback UG A10XCVR 2013 12 02 Arria 10 GT Channel Usage 2 251 Arria 10 GT Channel Usage All Arria 10 GT devices have a total of 16 GT transceiver channels that can support data rates up to 28 1 Gbps In Arria 10 GT devices each transceiver bank supports up to 4 GT channels that can operate as a duplex channel TX only or RX only channel Transceiver banks GXBLIE GXBL1F GXBL1G and GXBL1H each contain four GT transceiver channels 0 1 3 and 4 Channels 2 and 5 can only be configured as GX transceiver channels Table 2 153 Valid Permutations for GT and GX Channel Configuration in Transceiver Banks GXBL1E GXBL1F GXBL1G and GXBL1H for Channels 0 1 and 2 GT Configuration A Configuration B Configuration C Configuration D Configuration E Configuration F Transceiver Channel Ch2 Unusable Unusable Unusable GX GX GX Chl Gi GT GX Unusable cr GX Cho GT GX GT GT Unusable GX Notes e Ifboth the channels 0 and 1 are used with either one of them configured as a GT channel and the other one as GT or GX then channel 2 is unusable For all other configurations of channels 0 and 1 channel 2 can only be configured as a GX channel e Ifeither channel 0 or 1 is used as a GT channel then the ATX PLL adjacent to channel 0 and 1 needs to be reserved for GT channel configurations Table 2 154 Valid Permutations for GT and GX Channel Configuration in Transceiver Banks GXBL1E GXBL1F GXBL1G an
30. Gen3 HIP blocks with CvP capabilities D Arria 10 GX device with 6 transceiver channels and one PCle Hard IP block Arria 10 GT Device Transceiver Layout The largest GT device has 96 transceiver channels and four PCI Express Hard IP blocks All GT devices have a total of 16 GT transceiver channels that can support data rates up to 28 1 Gbps In GT devices transceiver banks GXBL1E GXBL1F GXBL1G and GXBL1H each contain four GT transceiver channels These are channels 0 1 3 and 4 The channels 2 and 5 are GX transceiver channels Arria 10 Transceiver PHY Overview Altera Corporation GJ Send Feedback z UG A10XCVR 1 8 Arria 10 GT Device Transceiver Layout 2013 12 02 Figure 1 8 Arria 10 GT Devices with 96 Transceiver Channels and Four PCle Hard IP Blocks GT 115 UF45 ge channa GXBL1J Transceiver GT 090 UF45 Transceiver GXBR4J Capable of Short Bank Bank Reach 28 1 Gbps GX or Restricted GT or GX Transceiver Transceiver GXBR4I GTOrGE Transceiver K
31. Rand Interlaken Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Table 2 39 Bitslip Enhanced PCS and PMA Ports 2 51 cx_bitslip lt n gt 1 0 Input Asynchronous rx_clkout The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input The maximum shift is lt pcswidth 1 gt bits so that if the PCS is 64 bits wide you can shift 0 63 bits tx enna oicsliol lt sn 1 0 Input Asynchronous T COUE The value of this signal controls the number of cbit locations to slip the tx_parallel_ data before passing to the PMA Related Information e ATX PLL IP on page 3 6 e CMU PLL IP on page 3 21 e fPLL IP on page 3 13 e Ports and Parameters on page 6 1 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 52 Standard PCS and PMA Ports 2013 12 02 e Transceiver PHY Reset Controller Interfaces on page 4 12 This section describes the top level signals for the Transceiver PHY Reset Controller IP core Standard PCS and PMA Ports The following figure illustrates the transceiver channel using the Standard PCS If you enable both the Standard PCS and Enhanced PCS your top level HDL file includes all the ports for both datapaths Arria 10 Transceiver Native PHY tx_cal_busy lt Nios Hard Reconfiguration a rx_cal busy lt
32. The following table specifies the control and status registers that you can access over the Avalon MM PHY management interface A single address space provides access to all registers Note Unless otherwise indicated the default value of all registers is 0 Note Writing to reserved or undefined register addresses may have undefined side effects Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Table 2 119 10GBASE KR Register Definitions Register Definitions 2 169 Word Bit R W Description Addr Offset Reset SEQ When set to 1 resets the LOGBASE KR sequencer initiates a PCS reconfiguration and may restart Auto Negotiation Link Training or both if AN and LT are enabled LOGBASE KR mode SEQ Force Mode 2 0 forces these modes This reset self clears 1 RW Disable AN Timer Auto Negotiation disable timer If disabled Disable AN Timer 1 ANmaygetstuckand require software support to remove the ABILITY_DETECT capability ifthe link partner does not include this feature In addition software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state To enable this timer set Disable AN Timer 0 2 RW Disable LF When set to 1 disables the Link Fault timer When set to 0 the Timer Link Fault timer is enabled 6 4 RW SEQ Force Forces the sequencer to a specific protocol Must write the Mode 2 0
33. UG A10XCVR 2 226 Using the Basic and Basic with KR FEC Configurations of Enhanced PCS 2013 12 02 Figure 2 95 Transceiver Channel Datapath and Clocking for Basic Enhanced PCS Configuration Transmitter PMA Transmitter Enhanced PCS FPGA Fabric 32 bit data See e a 10 3125 Gbps tx_serial_data LI Serializer A TX Gearbox Enhanced PCS TX FIFO N is 22 ao go 85 go REJ v oie Parallel Clock 322 265625 MHz i tx_pma_div_clkout Receiver PMA Receiver Enhanced PCS rx_pma _div_clkout m gt 3 z i 3 T 5 O 32 bit gS N oO a x 32 x le N 20 a4 a 2 8 Se ral 1 ot data H gt me 5 o gt E 4 85 gt or Fi S 3 X g Dg Le p L p S x sh fal o E sr x S wn wW N is zz Pa 28 z Le 2E j RE rn S rx_cikout Parallel Clock 322 265625 MHz Clock Generation Block CGB 5156 25 MHz ata rate 2 a aii ATX PLL Jt Clock Divider f fPLL ad f io CMU PLL Parallel Clock Serie Clock Parallel and Serial Clocks Seer h Parallel and Serial Clocks Input Reference Clock Notes 1 Can be enabled or disabled based on the gearbox ratio selected 2 Depends on the value of the clock division factor chosen Altera Corporation Implem
34. UG A10XCVR 2013 12 02 pipe_rate 1 0 In N A The 2 bit encodings defined in the following list 2 b00 Gen rate 2 5 Gbps 2 b01 Gen2 rate 5 0 Gbps 2 b1x Gen3 8 0 Gbps pipe_sw_done In N A Signal from the Master clock generation buffer indicating that the rate switch has completed Use this signal for bonding mode only For non bonded applications this signal is internally connected to the local CGB pipe_tx_data_valid In tx_pma_clk For Gen3 this signal is de asserted by the MAC to instruct the PHY to ignore tx_parallel_data for one clock cycle A value of 1 b1 indicates the PHY should use the data A value of 0 indicates the PHY should not use the data Active High rx_parallel_data 31 0 1520 oe L730 PIPE Output to PHY MAC Layer Out ise joel CJLie The RX parallel data driven to the MAC For Gen this can be 8 or 16 bits For Gen2 this is 16 bits only For Gen3 this is 32 bits rx_datak 3 0 1 0 or 0 Out tx_pma_clk The data and control indicator For Gen1 when 0 indicates that tx_parallel_data is data when 1 indicates that tx_parallel_data is control For Gen3 Bit 0 corresponds to pipe_ txdata 7 0 Bit 1 corresponds to pipe_ txdata 15 8 and soon Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Ports for PCI Express 2 211 pipenn _sy
35. Unlike in the 1G 10GbE PHY IP Core for Stratix V devices for Arria 10 devices the Reconfiguration Block is included 1G 10bE PHY This Reconfiguration Block provides the Avalon MM interface that you can use to read and write to PHY registers All read and write operations must be adhere to Avalon specification Instantiate a reset controller using the Transceiver Reset Controller Megafunction in the MegaWizard Plug In Manager Connect the power and reset signals between the 1G 10GbE PHY and the reset controller Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2013 12 02 3 Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate Connect the high speed serial clock and PLL lock signals between 1G 10GbE PHY and TX PLLs You can use any combination of fPLLs ATX or CMU PLLs 4 Use the tx_pma_divclk from 1G 10GbE PHY or generate a fPLL to create the 156 25 MHz XGMII clock from the 10G reference clock Unlike in the 1G 10GbE PHY IP Core for Stratix V devices no Memory Initialization Files mif are required for the 1G 10GbE design in Arria 10 devices 5 Complete the design by creating a top level module to connect all the IP 1G 10GbE PHY IP PLL IP and Reset Controller blocks 2 176 Design Guidelines Related Information e fPLL on page 3 11 e CMU PLL on page 3 19 e ATX PLL on page 3 3 e Using the Altera Transceiver PHY Reset Controller on page 4 8
36. Word Aligner in Deterministic Latency Mode for CPRI The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process It automatically synchronizes and aligns the word boundary by slipping a clock cycle in the deserializer Incoming data to the word aligner is aligned to the boundary of the word alignment pattern K28 5 Figure 2 90 Deterministic Latency State Machine in the Word Aligner Clock Slip Control Parallel lt lt 4 Clock From RX CDR Deserializer gt Deterministic Latency To 8B 10B Decoder Synchronization State Machine When using deterministic latency state machine mode reassert rx_std_wa_patternalign to initiate the pattern alignment after the initial alignment following the deassertion of reset Figure 2 91 Word Aligner in Deterministic Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data fledb6e4 b9dbf1db 915d061d e13f913f _ 7a4ae24a bbae9b10 bcbcbcbe 95cd3c50 91c295cd_ rx_errdetect 1101 0000 1010 2000 0010 1010 i rx_disperr 1101 0000 1010 1000 0000 1010 I rX_patterndetect 0000 1111 0000 rx_syncstatus 0000 1 Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback
37. _ __ Calibration IP Registers 7 reconfig_c lt reconfig_avmm TX PMA TX Standard PCS Serial Data lt 7 lt gt Parallel Data Control Clocks Clocks lt QPI gt Serializer re PCle lt gt 8B 10B Encoder Decoder Optional Ports lt gt lt gt PCle A tx_serial_clkO Clock from TX PLL Generation tx_analog_reset Block 1 rx_analog_reset RX PMA it RX Standard PCS Vv Serial Data p Parallel Data Control Clocks Optional Ports lt __ lt lt RX FIFO CDR Control lt CDR Deserializer lt gt QPI lt lt Rate Match FIFO Clocks lt lt Word Aligner amp Bitslip PRBS lt gt lt t _ PCle Bit amp Byte Reversal lt Polarity Inversion In the following tables the variables represent these parameters e lt n gt The number of lanes e lt w gt The width of the interface e lt d gt The serialization factor e lt s gt The symbol size e lt p gt The number of PLLs Table 2 40 TX Standard PCS Data Control and Clocks tx_parallel_data lt n gt Input tx_clkout TX parallel data input from the FPGA fabric to 128 1 0 the TX PCS For each 128 bit word the data input bits correspond to tx_parallel_ data 7 0 Altera Corporation Implementing P
38. namaak e e wren ae al aa wo 10GBASE R of ee a BER Checker oa 5 Ba os g peel ple E H Bg Egg gs gg ga ro E8 a g E amp KRFEC d tx_serial_clkO Clock Generation Block CGB 6156 25 MHz 4 Data rate 2 ATX PLL Clock Divider g PLL 4 oa CMU PLL Parallel Clock Serial Glode Parallel and Serial Clocks Stal clpsr J Parallel and Serial Clocks Input Reference Clock Notes 1 Value is based on the clock division factor chosen 2 Value is calculated as data rate on parallel interface FPGA fabric PCS interface width 3 Value is calculated as data rate on serial interface PCS PMA interface width How to Implement the Basic Enhanced PCS and Basic with KR FEC Transceiver Configuration Rules in Arria 10 Transceivers Before you begin You should be familiar with the Basic Enhanced PCS and PMA architecture PLL architecture and the reset controller before implementing the Basic Enhanced PCS or Basic with KR FEC Transceiver Configuration Rule 1 Open the MegaWizard Plug In Manager and select the Arria 10 Transceiver Native PHY IP Refer to Select and Instantiate PHY IP on page 2 2 for more details 2 Select Basic Enhanced PCS Basic with KR FEC from the Transceiver Configuration Rule list located under Datapath Options 3 Use the parameter values in the tables in Native PHY IP Parameter Settings for Basic Enhanced PCS and Basic with KR FEC as a starting point Or you
39. pin CMU PLL CDR 2 or fPLL Fractional PLL RX pin 2 fPLL fee i 6 RX pin 1L_ gt a RX pin 0L_ gt a 1 1 y Note 1 You can choose only one of the three RX pins to be used as an input reference clock source Any RX pin on the same side of the device can be used as an input reference clock 2 Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network Reference clock network can then drive the CMU PLL 3 The output of another PLL can be used as an input reference clock source during PLL cascading Note In Arria 10 devices the FPGA fabric core clock network can be used as an input reference source for fPLLs Dedicated Reference Clock Pins To minimize the jitter the advanced transmit ATX PLL and the fractional PLL fPLL can source the input reference clock directly from the reference clock buffer without passing through the reference clock network The input reference clock is also fed into the reference clock network PLLs and Clock Networks Altera Corporation GJ Send Feedback 3 26 Receiver Input Pins Figure 3 6 Dedicated Reference Clock Pins UG A10XCVR 2013 12 02 There are two dedicated reference clock refclk pins available in each transceiver bank The bottom refclk pin feeds the bottom ATX PLL and fPLL and the top refclk pin feeds the top ATX PLL and fPLL fPLL1 Reference Clock Network From PL
40. CJ Send Feedback 2 98 How to Implement 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC in Arria 10 Transceivers UG A10XCVR 2013 12 02 Figure 2 42 Signals and Ports of Native PHY IP for the 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC Arria 10 Transceiver Native PHY tx_cal_busy lt Nios Hard Reconfiguration gt a ena rx_cal_bus Calibration IP Registers re rs cal BUSY lt 4 g lt gt reconfig_avmm TX PMA TX Enhanced PCS q tx_digital_reset tx_control 17 0 lt xgmii_tx_c 7 0 2 tx_parallel_data 127 0 lt lt xgmii_tx_d 63 0 2 tx_serial_data lt 4 Serializer lt gt t_coreclkin 4 xgmii_tx_clk tx_clkout gt A tx_enh_data_valid lt 1 b1 1 tx_fifo_flags gt Clock tx_serial_clkO from TX PLL P Generation tx_analog_reset Block rx_analog_reset RX PMA il RX Enhanced PCS la x digital reset y rx_clkout gt rx_serial_data 7 gt rx_coreclkin q xgmii_rx_clk rx_cdr_refcik0 CDR Deserializer KH gt Peon DIK lock gt rx_is lockedtodata lt fx_enh_highber gt rx_is_lockedtoref lt rx_fifo_flags rx_parallel_data 127 0 gt rx_control 19 0 gt Notes 1 For 10GBASE R with 1588 configurations this signal is user controlled 2 For 1OGBASE R
41. Errors can only occur once per word Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS and PMA Ports 2 47 rx_prbs_err_ clr lt n gt 1 0 Input Soe When asserted clears the PRBS pattern and deasserts the rx_prbs_done signal rx joe _Clkowe Output Clock This is the recovered parallel clock from the RX CDR circuitry rx_pma_div_ clkout Output Clock This is a divided version the recovered RX parallel clock For the parallel clock you can divide rx_pma_clkout by 1 or 2 For the serial clock you can divide by 33 40 50 or 66 This clock drives rx_coreclkin for different gear box ratios rx_pma_clkslip Input Clock A rising edge on this signal causes the RX deserializer to slip the serial data by one clock cycle 2 UI Table 2 34 Enhanced PCS TX FIFO tx_enh_data_ valid lt n gt 1 0 Input Assertion of this signal indicates that the TX data coreclkin _ is valid Connect this signal to 1 b1 for 1OGBASE R without 1588 For Enhanced Basic and 10GBASE R with 1588 you must control this signal based on the gearbox ratio For Interlaken you need to control this port based on TX FIFO flags so that the FIFO won t underflow or overflow tz enn FLO ELL amns O Output tx_ Active high Assertion of this signal indicates the coreclkin TX FIFO is full tx_enh_fifo_ pfull l
42. HSSTI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE 1 hO INTERFACE _PLDIF_DATAWIDTH_MODE_ADDR_FIELD_OFST ll e INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_HIGH 7 INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_SIZE II bh Ne INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_BITMASK INTERFACE _PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALMASK The System Verilog configuration files are separated into two parts that represent the same data using two formats The first part of the configuration file consists of a data array of 26 bit hexadecimal values and the second part consists of parameter values For the data array each 26 bit hexadecimal value contains an associated comment describing the various bit positions Table 6 5 26 bit Value of Typical SystemVerilog Configuration File Line Bit Description Position 25 16 The channel or PLL offset 15 8 The channel or PLL bit mask The bit mask exposes the bits that are configured by either the Transceiver Native PHY or the transmit PLL IP cores 7 0 Feature bit values Multiple features may reside at the same offset or span multiple offsets Using the value of 26 h008FF04 the offset value is 0x008 and the bit mask is OxFF The four features that reside at offset 0x008 are e hssi_tx_pcs_pma_interface_
43. PLLs Table 3 1 Transmit PLLs in Arria 10 Devices PLL Type Data Rate Range Characteristics Advanced Transmit ATX PLL 1 0 Gbps to 28 1 Gbps e Best jitter performance e LC Tank based voltage controlled oscillator VCO e Supports fractional synthesis mode e Used for both bonded and non bonded channel configurations Fractional PLL fPLL 0 611 Gbps to 12 5 Gbps e Ring oscillator based VCO e Supports fractional synthesis mode e Used for both bonded and non bonded channel configurations CMU Clock Multiplier Unit PLL 0 611 Gbps to 17 4 Gbps Ring oscillator based VCO Channel PLL e Used as an additional clock source for non bonded applications Note For best overall performance use the ATX PLL first followed by the fPLL The channel PLL can be used as a transmit PLL if additional PLLs are required Related Information Clock Networks ATX PLL The ATX PLL contains three LC Tank based voltage controlled oscillators VCOs These three LC VCOs have different frequency ranges to support continuous range of operation It supports both integral and fractional frequency synthesis The transceiver banks with six channels have two ATX PLLs each one located at the top and the other at the bottom of the bank The transceiver banks with three channels have only one ATX PLL 5 Data rates depend on characterization and may change after characterization report is available The CMU PLL Channel PLL of channe
44. Phase Frequency Detector PFD The reference clock refclk signal at the output of the N counter block and the feedback clock flbc1k signal at the output of the M counter block is supplied as an input to the PFD The PFD output is proportional to the phase difference between the two inputs It aligns the input reference clock refc1k to the feedback clock fbc1k The PFD generates an Up signal when the reference clock s falling edge occurs before the feedback clock s falling edge Conversely the PFD generates a Down signal when feedback clock s falling edge occurs before the reference clock s falling edge Charge Pump and Loop Filter CP LF The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO The charge pump translates the Up Down pulses from the PFD into current pulses The current pulses are filtered through a low pass filter into a control voltage which drives the VCO frequency Voltage Controlled Oscillator VCO The CMU PLL has a ring oscillator based VCO The fundamental VCO frequency range is from 4 GHz to 14 GHz Lower frequencies can be generated using the PFD and M counter settings L Counter The L counter divides the differential clocks generated by the CMU PLL The division factors supported are 1 2 4 and 8 Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 M Counter Instantiating CMU PLL IP 3 21 The M counter is
45. RX FIFO Shared with Enhanced PCS and PCle Gen3 PCS The RX FIFO interfaces between the PCS on the receiver side and the FPGA fabric and ensures reliable transfer of data and status signals It compensates for the phase difference between the FPGA fabric and the PCS on the receiver side It operates in register FIFO and low latency Figure 5 49 RX FIFO Block Diagram RX Datapath from F Byte Deserializer 8B L0B Decoder gt FIFO li een Fabric Rate Match FIFO or Deserializer wr_clk rd_clk Parallel clock rx_clkout rx_coreclkin recovered 9 from clock divider RX FIFO Low Latency Mode The low latency mode incurs two to three cycles of latency when connecting it with the FPGA fabric The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases which in turn decreases the latency RX FIFO Register Mode The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements This is accomplished by tying the read clock of the FIFO with its write clock The register mode incurs only one clock cycle of latency when interfacing to the FPGA fabric Arria 10 PCI Express Gen3 PCS Architecture Arria 10 architecture supports the PCIe Gen3 specification Altera provides two options to implement the PCI Express solution e You can use the Altera Hard IP solution This complete
46. Related Information e CMU PLL on page 3 19 For more information on CMU PLL e CMU PLL IP on page 3 21 For information on implementing CMU PLL IP Clock Generation Block CGB In Arria 10 devices there are two types of clock generation blocks CGBs e Master CGB e Local CGB Transceiver banks with six transceiver channels have two master CGBs Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank Transceiver banks with three channels have only one master CGB The master CGB divides and distributes bonded clocks to a bonded channel group It also distributes non bonded clocks to non bonded channels across the x6 xN clock network Each transceiver channel has a local CGB The local CGB is used for dividing and distributing non bonded clocks to its own PCS and PMA blocks Related Information Clock Generation Block on page 3 32 For more information on clock generation block Arria 10 Transceiver PHY Overview Altera Corporation CJ Send Feedback Implementing Protocols in Arria 10 Transceivers 2013 12 02 UG A10XCVR S subscribe QO Send Feedback Transceiver Design IP Blocks Figure 2 1 Arria 10 Transceiver Design Fundamental Building Blocks Reset controller is used for resetting the transceiver channels Analog and Digital Reset Bus Transceiver PLL IP provides a clock soucrce to clock networks that drive the transceiver channels In Arria 10
47. Reset SEQ bit to 1 for the Force to take effect The following 0x4B0 encodings are defined e 3 b000 No force 3 b001 GigE e 3 b010 Reserved e 3 b011 Reserved e 3 b100 1OGBASE R e 3 b101 1OGBASE KR e Others Reserved 16 RW Assert KR FEC Ability When set to 1 indicates that the FEC ability is supported This bit defaults to 1 if the Set FEC_ability bit on power up reset bit is on For more information refer to the FEC variable FEC_ Enable as defined in Clause 74 8 2 and 10GBASE KR PMD control register bit 1 171 0 IEEE 802 3ap 2007 18 RW Assert KR FEC Request When set to 1 indicates that the core is requesting the FEC ability When this bit changes you must assert the Reset SEQ bit 0x4B0 0 to renegotiate with the new value Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 170 Register Definitions UG A10XCVR 2013 12 02 Word Bit R W Description Addr Offset SEQ Link Ready When asserted the sequencer is indicating that the link is ready SEQ AN timeout When asserted the sequencer has had an Auto Negotiation timeout This bit is latched and is reset when the sequencer restarts Auto Negotiation SEQ LT timeout When set indicates that the Sequencer has had a timeout 0x4B1 SEQ Reconfig Mode 5 0 Specifies the Sequencer mode for PCS reconfiguration The following modes are defined e Bit 8 mode 0 AN
48. The receiver buffer has on chip biasing circuitry to establish the required Vy at the receiver input The Quartus II software automatically chooses the optimal setting for RX Vcy Note On chip biasing circuitry is available only if you select OCT If you select external termination you must implement off chip biasing circuitry to establish the Vy at the receiver input buffer Programmable Differential On Chip Termination OCT Receiver buffers include programmable on chip differential termination of 850 100Q or OFF You can disable OCT and use external termination If you select external termination the receiver common mode is tri stated Common mode is based on the external termination connection You will also need to implement off chip biasing circuitry to establish the Vy at the receiver buffer Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 6 Signal Detector 2013 12 02 Signal Detector You can enable the optional signal threshold detection circuitry If enabled this option senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage that you specified in the assignment editor in Quartus II Continuous Time Linear Equalization CTLE Each receiver buffer has independently programmable equalization circuits that amplify the high frequency component of the incoming signal compensating for the low pass characteristics of the physica
49. When set to 1 The local device TX coefficients are set to a state where equalization is turned off Preset coefficients are used When set to 0 the local device operates normally The function and values of the preset bit is defined in 72 6 10 2 3 1 The function and values of the initialize bit are defined in Clause 72 6 10 2 3 2 For more information refer to bit 10G BASE KR LP coefficient update register bits 1 152 13 in Clause 45 2 1 78 3 of IEEE 802 3ap 2007 29 24 Altera Corporation RO LP coefficient status 5 0 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Word R W Addr 10GBASE KR PHY Register Definitions 2 139 Description Status report register reflects the contents of the second 16 bit word of the training frame most recently received from the control channel The following fields are defined e 5 4 Coefficient 1 e 2 bll Maximum e 2 b0l Minimum e 2 b10 Updated e 2 b00 Not updated e 3 2 Coefficient 0 same encoding as 5 4 e n 1 0 Coefficient 1 same encoding as 5 4 For more information refer to bit 10G BASE KR LP status report register bits 1 153 5 0 in Clause 45 2 1 79 of IEEE 802 3ap 2007 30 RO LP Receiver ready When set to 1 the link partner receiver has determined that training is complete and is prepared to receive data When set to 0 the link partner receiver is requesting that training contin
50. When t x_datak is low the 8 bit data is encoded as a data word Dx y Depending upon the PCS PMA interface width the width of tx_datak is either 1 bit or 2 bits When the PCS PMA interface width is 10 bits tx_dat ak is a 1 bit word When the PCS PMA interface width is 20 bits tx_datak is a 2 bit word The LSB of tx_datak corresponds to the LSByte of the input data sent to the 8B 10B encoder and the MSB corresponds to the MSByte of the input data sent to the 8B 10B encoder Related Information Refer to Specifications amp Additional Information for more information about 8B 10B encoder codes Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 8B 10B Encoder Reset Condition 5 35 8B 10B Encoder Reset Condition tx_digitalreset resets the 8B 10B encoder During the reset condition the 8B 10B encoder outputs K28 5 continuously until tx_digitalreset goes low 8B 10B Encoder Idle Character Replacement Feature The idle character replacement feature is used in protocols such as Gigabit Ethernet which requires the running disparity to be maintained during idle sequences During these idle sequences the running disparity has to be maintained such that the first byte of the next packet always starts when the running disparity of the current packet is negative When an ordered set which consists of two code groups is received by the 8B 10B encoder the second code group will be converted into
51. coefficients generation protocol When set the software changes the local TX equalizer coefficients When set to 0 uses the update command received from the link partner to determine local device coefficients Used with 0x4D1 bit 8 and 0x4D4 bits 23 16 The default value is 1 Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY Register Definitions 2 135 Word R W Description Addr Restart Link training When set to 1 resets the LOGBASE KR start up protocol When set to 0 continues normal operation This bit self clears For more information refer to the state variable mr_restart_training as defined in Clause 72 6 10 3 1 and 1OGBASE KR PMD control register bit 1 150 0 IEEE 802 3ap 2007 0x4D1 RW Updated TX Coef new When sent to 1 there are new link partner coefficients available to send The LT logic starts sending the new values set in 0x4D4 bits 7 0 to the remote device When set to 0 continues normal operation This bit self clears Must enable this override in 0x4D0 bit16 RW Updated RX coef new Receiver status Link Trained When set to 1 new local device coefficients are available The LT logic changes the local TX equalizer coefficients as specified in 0x4D4 bits 23 16 When set to 0 continues normal operation This bit self clears Must enable the override in 0x4D0 bit17 When set
52. e 0 Sync Header high indicates a control word low indicates a data word Bit 0 is mutually exclusive with bit 1 Altera Corporation 2 40 Enhanced PCS and PMA Ports UG A10XCVR 2013 12 02 Description e lOGBASE R e 8 Active high synchronous error insertion control bit e 7 XGMII control signal for tx_parallel_ data 63 56 e 6 XGMII control signal fort x_parallel_ data 55 48 e 5 XGMII control signal fortx_parallel_ data 47 40 e 4 XGMII control signal for tx_parallel_ data 39 32 e 3 XGMII control signal for tx_parallel_ data 31 24 e 2 XGMII control signal fortx_parallel_ data 23 16 e 1 XGMII control signal for tx_parallel_ data 15 8 e 0 XGMII control signal fort x_parallel_ data 7 0 e 10GBASE R KR FEC and Basic KRFEC e 9 Active high status signal that indicates when KRFEC Block Lock is achieved e 8 Active high status signal that indicates the beginning of a received KRFEC frame boundary e Basic mode 64 bit data including sync header e 8 2 Unused Ground e 1 Sync Header 1 indicates a control word e 0 Sync Header 1 indicates a data word e Basic 64 bit data excluding sync header e 8 0 Unused Ground e Basic mode 128 bit data including sync header e 17 11 Unused Ground e 10 Sync Header 1 indicates a control word e 9 Sync Header 1 indicates a data word e Basic mode 128 bit da
53. oO go gx XG mM eu a tx_pma_div_clkout Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout z b 5 5 RX s i 5 E F v Bs g 8 if a g cg eg 8 Data amp 5 Kis Ba FH on 5 E J aa K ax 2 vy BE cma ss _ gt O E SE o ze He o iL 5 3 a ie zap Bp BE sgm SEs x 1 fa gt ES a r oe 0 cX x a a g i i a 3 O fr T 4 z k 5 Verte PRP Ces N gt verifier Le Parallel Clock T jj 4 Tx _clkout 10GBASE R o 3 x a BER Checker ga lee les joel jes Lt Ol pit sips pli sie es es ea el led sa B g Q E o E a Clock Generation Block CGB ya ATX PLL nee Clock Divider lq re PLL a CMUPLL e Parallel and Serial Clocks Serial Clock Input Reference Clock Related Information Implementing Protocols in Arria 10 Transceivers on page 2 1 Transmitter Datapath Enhanced PCS TX FIFO Shared with Standard PCS and PCle Gen3 PCS The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS and the FPGA fabric The TX FIFO can operate for phase compensation between the channel PCS and FPGA fabric You Arria 10 Transceiver PHY Architecture Altera Corporation GJ Send Feedback g UG A10XCVR 5 16 Phase Compensation Mode 2013 12 02 can also use the TX FIFO as an elastic buffer to control the input data flow using tx_enh_data_valid The TX FIFO also allows channel bonding The TX FIFO has a width of 73 bits and a depth of 16 words The TX FIFO pa
54. other configuration rules PMA Parameters You can specify values for the following types of PMA parameters e TX Bonding Options e TX PLL Options e TX PMA Optional Ports e RX CDR Options e RX PMA Optional Ports Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 18 PMA Parameters 2013 12 02 Table 2 4 TX PMA Bonding Options TX channel Not bonded Selects the bonding mode to be used for the channels specified bonding mode PMA bonding Bonded clocks use a single TX PLL to generate a clock that drives multiple channels reducing channel to channel skew The PMA PCS bonding following options are available Non bonded In a non bonded configuration only the high speed serial clock is routed from the transmitter PLL to the transmitter channel The low speed parallel clock is generated by the local clock generation block CGB present in the transceiver channel For non bonded configurations because the channels are not related to each other and the feedback path is local to the PLL the skew between channels cannot be calculated PMA bonding In a PMA bonded configuration the high speed serial clock is routed from the same transmitter PLL to all the transmitter channels that require bonding The master CGB generates both the high and slow speed clocks PMA PCS bonding In a PMA PCS bonded configuration both the high speed serial and low speed parallel clocks are route
55. to your project 5 Click OK to close the Settings dialog box Related Information e Preparing for EDA Simulation e Altera Simulation Models How to Generate Scripts When you compile your design the Quartus II software and Qsys automatically generate simulation scripts for the supported third party simulation tools You can also use the ip make simscript utility to generate scripts for multiple IP cores or a Qsys system Custom Simulation Scripts You can automate simulations by creating customized scripts You can generate scripts manually In addition you can use NativeLink to generate a simulation script as a template and then make the necessary changes The following table shows a list of script directories NativeLink generates Table 2 157 NativeLink Generated Scripts for Third Party RTL Simulation Mentor Graphics ModelSim or _ simulation modelsim modelsim_ Source directly with your QuestaSim setup do simulator Aldec Riviera Pro simulation aldec rivierapro_ Source directly with your setup tcl simulator Synopsys VCS simulation synopsys vcs vcs_ Add your testbench file name to setup sh this options file to pass the file to VCS using the file option If you specify a testbench file for NativeLink and do not choose to simulate NativeLink generates an script that runs VCS Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Qsys Simulati
56. 0x7 or offset 0x8 to enable the type of PRBS or square wave pattern a Perform a read modify write to offset 0x7 by writing a 1 b1 to either bit 7 bit 6 or bit 5 to enable PRBS9 PRBS15 or PRBS23 respectively Write other bits with 1 b0 b Perform a read modify write to offset 0x8 by writing to bit 3 0 or bit 4 to enable the square wave or PRBS31 respectively Write bit 6 5 with the type pattern generator 3 Perform a read modify write to offset 0x110 with the specified width This data width is either 64 bit or 10 bit 4 Perform a reset To disable the PRBS or square wave generator write the original values back into the read modify write offsets in Table 6 12 Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration J Send Feedback UG A10XCVR 2013 12 02 Enabling the PRBS and Square Wave Data Generator 6 15 Table 6 13 PRBS Generator and Square Wave Offsets Reconfigura Reconfig Attribute Other Attribute Encoding Bit Encoding Description tion uration NET Address Bit HEX prbs_pat 3 b100 Enable PRBS generator 2 0 a 0x8 ata_se sq_wave_pat 3 b101 Enable square wave generator prbs9_10b 1 b1 Enable PRBS9 in 10 bit mode 3 prbs9_dwidth prbs9_64b 1 b0 Enable PRBS9 in 64 bit mode 0x6 prbs_clk_dis 1 b0 Disable PRBS clock 6 prbs_clken prbs_clk_en 1 b1 Enable PRBS clock sqwgen_clk_dis 1 b0 Disable
57. 1 1 Clocks Selected CDR reference clock 0 0 0 Selected CDR reference clock frequency 100 MHz 125 MHz 100 MHz 125 MHz 100 MHz 125 MHz PPM detector threshold 300 300 300 Decision Feedback Equalization DFE Decision feedback equalization mode Off Off Off RX PMA Optional Ports Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 200 Native PHY IP Parameter Settings for PCI Express 2013 12 02 Enable rx_pma_clkout port Optional Optional Optional a ee OUI CEE fel Sorel Optional Optional Optional tx_pma_div_clkout r 3 division factor Optional Optional Optional Enable rx_pma_clkslip port Optional Optional Optional Enable rx_pma_qpipulldn port QPI Off Off Off Enable rx_is_lockedto Sika nd Optional Optional Optional Enablerx_is_lockedtoref Optional Optional Optional port port Enable rx_set_locktodata and rx_set_locktoref Optional Optional Optional ports g Ta seriallpiken Optional Optional Optional Enable PRBS Verifier Control oat SHINO WOKE Optional Optional Optional Table 2 129 Parameterizing Arria 10 Native PHY IP in PIPE Gen1 Gen2 Gen3 Modes Standard PCS Standard PCS configurations Standard PCS PMA interface 10 10 10 width FPGA Fabric Standard TX PCS 8 16 16 32 interface width FPGA Fabric Standard
58. 100G via OTL4 4 Native PHY IP PCS Direct Basic Enhanced User created CEI 25G 28G VSR SR Enhanced PCS PCS low latency mode OTU 4 100G via OTL4 10 Native PHY IP Enhanced SFI S User created OIF SFI S OTU 3 40G via OTL3 4 Native PHY IP Enhanced SFI S User created OIF SFI 5 2 SFI 5 1 OTU 2 10G via SFP SFF Native PHY IP Enhanced Basic Enhanced User created 8431 CEI 11G PCS OTU 2 10G via OIF SFI Native PHY IP Enhanced SFI S User created 5 1s OTU 1 2 7G Native PHY IP Standard Basic Custom User created Standard PCS SONET SDH STS 768 STM Native PHY IP Enhanced SFI S User created 256 40G via OIF SFI 5 2 STL256 4 SONET SDH STS 768 STM Native PHY IP Enhanced SFI S User created 256 40G via OIF SFI 5 1 17 PHY IP on page 2 12 18 2 12 19 PCI Express Hard IP is also available as a MegaCore function For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page CO The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed negotiation and sequencer functions 21 22 23 4 X AUI PHY IP will be available in a future release of the Quartus II software GJ Send Feedback Implementing Protocols in Arria 10 Transceivers Needs a user created Soft IP for link training auto speed
59. 10GBASE KR PHY Register Definitions 2 129 Word R W Description Addr SEQ Link Ready When asserted the sequencer is indicating that the link is ready 1 SEQ AN timeout When asserted the sequencer has had an Auto Negotiation timeout This bit is latched and is reset when the sequencer restarts Auto Negotiation 2 SEQ LT timeout When set indicates that the Sequencer has had a timeout 13 8 SEQ Reconfig Specifies the Sequencer mode for PCS reconfiguration The Mode 5 0 following modes are defined e Bit 8 mode 0 AN mode e Bit 9 mode 1 LT Mode Ox4B1 e Bit 10 mode 2 10G data mode e Bit 11 mode 3 Gige data mode e Bit 12 mode 4 Reserved for XAUI e Bit13 mode 5 10G FEC mode 16 KR FEC ability When set to 1 indicates that the 1OGBASE KR PHY supports FEC For more information refer to Clause 45 2 1 84 of IEEE 302 3ap 2007 17 KR FEC err ind Whenset to 1 indicates that the 1OGBASE KR PHY is capable ability of reporting FEC decoding errors to the PCS For more information refer to Clause 74 8 3 of IEEE 302 3ap 2007 0 10 Reserved 11 FEC TX Error Writing a 1 inserts 1 error pulse into the TX FEC depending 0x4B2 Insert on the Transcoder and Burst error settings 31 15 Reserved 0 AN enable When set to 1 enables Auto Negotiation function The default value is 1 For additional information refer to bit 7 0 12 in Clause 73 8 Management Register Requirements of IEEE
60. 10Gb Fthernet variant When you select the Backplane KR variant the Link Training LT and Auto Negotiation AN tabs appear The 1Gb 10Gb Ethernet variant 1G 10GbE does not implement the LT and AN functions Complete the following steps to parameterize the 10GBASE KR PHY IP core in the MegaWizard Plug In Manager YSN a So For Which device family will you be using select Arria 10 from the list Click Installed Plug Ins gt Interfaces gt Ethernet gt Arria 10 1G1OGbE and LOBASE KR PHY Select 1OGBASE KR PHY version from the IP variant list in MegaWizard Plug In Manager Use the tabs on the MegaWizard Plug In Manager to select the options required for the protocol Refer to the topics listed as Related Links to understand and specify 1G 10GbE parameters Click Finish to generate your parameterized 1OGBASE KR PHY IP Core Related Information 10GBASE R Parameters on page 2 111 10M 100M 1Gb Ethernet Parameters on page 2 112 Speed Detection Parameters on page 2 113 10GBASE KR Auto Negotiation Parameters on page 2 114 1GbE Parameters 10GBASE KR Link Training Parameters Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 General Options 2 111 General Options The General Options allow you to specify options common to 1GbE and 10GbE modes Table 2 85 General Options Parameters A Peton Initial datapath 10G 1G Specifies the data rate need after reset or power up I
61. 12 02 Transmitter Datapath 5 15 The Enhanced PCS provides the following functions e Performs functions common to most serial data industry standards such as word alignment encoding decoding and framing before data is sent or received off chip through the PMA e Handles data transfer to and from the FPGA fabric e Internally handles data transfer to and from the PMA e Provides frequency compensation e Performs channel bonding for multi channel low skew applications Figure 5 20 Enhanced PCS Datapath Diagram Parallel Clock Serial Clock Parallel and Serial Clocks Transmitter PMA Transmitter Enhanced PCS FPGA Fabric 5 w E S 5 Q TX s co R T O T x oc s gz co c 20 Data amp 2 SE n o rt 2 ies 5 S FES Control z g ae HA E Paris RE Fom 2x t 3 8 5 5 gz ER v ge ia a ae o Se ra x 2 a 4 a wi i a 3 O c S ates PRP a 8 anara Generator S ba p3 i Parallel Clock I Jl l I I j tx_clkout f Os 3 og Qs us 98 C pge Egga 2g a
62. 156 25 MHz for the TX PCS and PMA datapath for 10G mode rx_data_ready Output Synchronous to rx_ When asserted indicates that the MAC can begin clkout sending data to the PHY Dynamic Reconfiguration Interface You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G data rates Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Avalon MM Register Interface 2 167 Table 2 117 Dynamic Reconfiguration Interface Signals mode_lg_ Input Synchronous to This signal indicates the requested mode for the 10gbar mgmt_clk channel A 1 indicates 1G mode and a 0 indicates 10G mode re busy Output Synchronous to When asserted indicates that reconfiguration is in mgmt_clk progress Synchronous to the mgmt __c1lk This signal is only exposed under the following conditions e Turn off Enable automatic speed detection e Turn on Enable internal PCS reconfiguration logic e Turn on Enable 1Gb Ethernet protocol start_pcs_ Input Synchronous to When asserted initiates reconfiguration of the PCS reconfig mgmt_clk Sampled with the mgmt __c1k This signal is only exposed under the following conditions e Turn off Enable automatic speed detection Turn on Enable internal PCS reconfiguration logic e Turn on Enable 1Gb Ethernet protocol Avalon MM Register Interface The Avalon MM slave interface signals provi
63. 25 MHz TX GMII MIl Data 125 MHz RX GMII Data TX XGMIl Data RX XGMII Data Altera Device with 10 3125 Gbps Serial Transceivers 1G 10Gb Ethernet PHY MegaCore Function Optional Re a er ee Coron To From Modules in the PHY MegaCore Native PHY Hard IP 257 8 MHz TX Serial Data 1G 10 Gb Ethernet gt Ethernet Hard PCS Network w FEC RX lt Interface Serial 1Gb Data Ethernet Standard Hard PCS d 322 265625 MHz or 644 53125 MHz Reference Clock 125 MHz Reference Clock Legend EI sore Red With FEC Option An Avalon MM slave interface provides access to the 1G 10GbE PHY IP Core registers These registers control many of the functions of the other blocks Many of these bits are defined in Clause 45 of IEEE Std 802 3ap 2008 Related Information e IEEE Std 802 3ap 2008 Standard e Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems 1G 10GbE PHY Release Information This topic provides information about this release of the 1G 10GbE PHY IP Core Table 2 104 1G 10GbE Release Information Se i n ne Version 13 1 Release Date November 2013 Ordering Codes IP 1G10GBASER PHY primary Product ID 0106 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR amay 2013 12 02 1G 10GbE PHY Performance and Re
64. 32 Calculation gt Calculated CRC 32 Value Inserted in the 32 Bits of Diagnostic Word The 66 bit encoded data contains two overhead sync header bits that the receiver PCS uses for block synchronization and bit error rate BER monitoring The sync header is 01 for data blocks and 10 for control blocks Sync headers are not scrambled and are used for block synchronization The sync headers 00 and 11 are not used and generate an error if seen The remainder of the block contains the payload The payload is scrambled and the sync header bypasses the scrambler The encoder block also has a state machine TX SM designed in accordance with the IEEE802 3 2008 specification The TX SM ensures valid packet construction on data sent from the MAC layer It also performs functions such as transmitting local faults under reset as well as transmitting error codes when the 1OGBASE R PCS rules are violated Note The 64B 66B encoder is available to implement the 1OGBASE R protocol Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback Enhanced PCS Pattern Generators 5 19 Figure 5 23 Example Data Pattern for 64B 66B Encoding TXC lt 0 3 gt TXD lt 0 31 gt XGMII XGMII B 07070707 f07070707 8fbD D D 0D D D D 0D D D D 0D D D D 1D D D fd 107070707 Data C C C C C C C C D D D D D D D D D D D D D D D D D D T C C C C Onli daai aa ad ial Taar A Oils aae a aak a a A Oleic a i a a L i Ae a ah aiaa
65. 32 Checker The Interlaken CRC 32 checker verifies that the data transmitted has not been corrupted between the transmit PCS and the receive PCS The CRC 32 checker calculates the 32 bit CRC for the received data and compares it against the CRC value that is transmitted within the diagnostic word rx_enh_crce32_err CRC error signal is sent to the FPGA fabric Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS RX FIFO 5 27 Enhanced PCS RX FIFO The Enhanced PCS RX FIFO is designed to compensate for the phase and or clock difference between the receiver channel PCS and the FPGA fabric It can operate as a phase compensation clock compensation elastic buffer or a deskew FIFO in Interlaken mode The RX FIFO has a width of 74 bits and a depth of 32 words for all protocols The RX FIFO supports the following modes e Phase Compensation mode e Register mode e Interlaken mode deskew FIFO e l10GBASE R mode clock compensation FIFO e Basic mode elastic buffer FIFO Phase Compensation Mode The RX FIFO compensates for the phase difference between the read clock and write clocks rx_clkout RX parallel low speed clock clocks the write side of the RX FIFO rx_coreclkin FPGA fabric clock or rx_clkout clocks the read side of the RX FIFO When phase compensation is used in double width mode the FPGA data width is doubled to allow the FPGA fabric clock to run at half rate s
66. 34 bit input data to 32 bit data During the next 3 clock cycles the gearbox will merge bits from adjacent cycles to form the 32 bit data In order for the gearbox to work correctly a gap must be provided in the data for every 16 shifts as each shift is 2 bits for converting the initial 34 bit to 32 bit in the gearbox After 16 Shifts the gearbox will have an extra 32 bit data that was transmitted out and thus a gap is required in the input data stream This gap is achieved by driving data valid low for one cycle after every 16 blocks of data Related Information Gearbox on page 2 190 Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 48 Receiver Datapath 2013 12 02 Receiver Datapath This section describes the Block Synchronizer Rate Match FIFO and RX FIFO of the Gen3 PCS receiver Block Synchronizer PMA parallelization occurs at arbitrary word boundaries Consequently the parallel data from the RX PMA CDR must be realigned to meaningful character boundaries The PCI Express 3 0 base specification outlines that the data is formed using 130 bit blocks with the exception of SKP blocks The SKP Ordered Set can be 66 98 130 162 or 194 bits long The block sync module searches for the Electrical Idle Exit Sequence Ordered Set or the last number of fast training sequences NFTS Ordered Set or skip SKP Ordered Set to identify the correct boundary for the incoming stream and to achieve the block
67. Available As this figure illustrates the 1G 10GbE Ethernet PHY IP Core is built using the Native PHY It includes the following modules Standard and Enhanced PCS Datapaths The Standard PCS supports the 1G protocol The Enhanced PCS supports 1OGBASE R Refer to the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support 1G 10G protocols and FEC Sequencer The Sequencer controls the start up sequence of the PHY IP including reset and power on It selects which PCS 1G or 10G and PMA interface is active The Sequencer interfaces to the reconfiguration block to request a reconfigurations to change from one data rate to the other data rate GigE PCS The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII functionality Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Clock and Reset Interfaces 2 153 1588 FIFO The 1588 FIFO has an XGMII like interface for both input and outputs The 1588 FIFO includes the latency adjust information that the 1588 logic in the MAC requires Reconfiguration Block The Reconfiguration Block performs the Avalon MM writes to the PHY for both PCS and PMA reconfigu ration The following figure shows reconfiguration blocks details The Avalon MM master accepts requests from the PMA or PCS controller It performs the Read Modify Write or Write commands using the Aval
68. DO lt q Transmitter Buffer The transmitter buffer includes the following circuitry to improve signal integrity e programmable differential output voltage Vop e main tap e programmable four tap pre emphasis circuitry e two pre cursor taps e two post cursor taps e internal termination circuitry e receiver detect capability to support PCI Express and Quick Path Interconnect QPI configurations Figure 5 3 Transmitter Buffer gt o o C gt To Serial Data p L gt Output Pins Programmable tx_serial_data Pre Emphasis and Vy On Chip 850 1000 OFF Receiver Termination Detect Programmable Output Differential Voltage You can program the differential output voltage to handle different channel losses and receiver requirements There are 32 differential V op settings up to 1000 mV The step size is 31 25 mV Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2 5 3 2013 12 02 Programmable Pre Emphasis Figure 5 4 Vop Differential Signal Level Differential Waveform 0 V Differential Vo Differential V V Programmable Pre Emphasis Pre emphasis can maximize the eye at the far end receiver The programmable pre emphasis module in each transmit buffer amplifies high frequencies in the transmit data signal to compensate for attenuation in the transmission media The pre tap de emphasizes the bit before the transiti
69. Decoder in Single Width and Double Width Mode Single Width Mode Double Width Mode datain 19 10 gt rx dataout 15 8 8B 10B Decoder gt datak 1 MSB Byte B rx errdetect 1 P rx disperr 1 datain 9 0 p gt gt x_dataout 0 8B 10B Decoder rx_datak recovered clock or LSB Byte p gt 1x errdetect tx_clkout 0 Current Running Disparity rx disperr ail datain 9 0 p gt L 1x_dataout 7 0 recovered clock or 8B 10B Decoder B gt rx_datak tx_clkout 0 LSB Byte gt rx _errdetect m rx disperr recovered clock or tx_clkout 0 When the PCS PMA interface width is 10 bits only one 8B 10B decoder is used to perform the conversion When the PCS PMA interface width is 20 bits two cascaded 8B 10B decoders are used The 10 bit LSByte of the received 20 bit encoded data is decoded first and the ending running disparity is forwarded to the 8B 10B decoder responsible for decoding the 10 bit MSByte The cascaded 8B 10B decoder decodes the 20 Altera Corporation Arria 10 Transceiver PHY Architecture J Send Feedback UG A10XCVR 2013 12 02 8B 10B Decoder Control Code Encoding 5 43 bit encoded data into 16 bit data 2 bit control identifier The MSB and LSB of the 2 bit control identifier correspond to the MSByte and LSByte of the 16 bit decoded data code group The decoded data is fed to the byte deserializer or the RX FIFO 8B 10B Decoder Control Code Encoding
70. FIFO write enable by monitoring the TX FIFO flags tx_e nh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 68 TX FIFO Soft Bonding 2013 12 02 tx_enh_fifo_cnt and so forth On the TX FIFO read side a read enable is controlled by the frame generator If tx_enh_frame_burst_en is asserted high the frame generator reads data from the TX FIFO A TXFIFO pre fill stage must be implemented to perform the TX channel soft bonding The following figure shows the state of the pre fill process Figure 2 16 TX Soft Bonding Flow Exit from tx_digitalreset gt y Deassert all lanes tx_enh_frame_burst_en Assert all lanes tx_enh_data_valid qo yes y Deassert all lanes tx_enh_data_valid gt Any lane send new frame tx_enh_frame asserted yes y Wait for extra 16 tx_coreclkin cycles All lanes full yes AA TX FIFO pre fill completed The following figure shows that after the deassertion of tx_digitalreset TX soft bonding logic starts filling the TX FIFO until all lanes are full Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 RX Multi lane FIFO Deskew State Machine 2 69 Figure 2 17 TX FIFO Pre fill p Deasse
71. Figure 5 47 8B 10B Decoder in Control Code Group Detection When the PCS PMA Interface Width is 10 Bits bx clkout eee detaingo0 D3 4 i D24 3 N D28 5 y K28 5 eee D15 0 K D0 0 i D31 5 X rx_datak dataout 7 0 eee l 83 X 78 BC l BC T OF 00 BF y When the PCS PMA Interface Width is 20 Bits tx_clkou datain 19 10 D3 4 i D28 5 D15 0 Y D3 4 datain 9 0 D24 3 D28 5 Y D15 0 Y D3 4 rx_datak 1 0 l 00 01 N 00 l dataout 15 0 16 h8378 y 16 hBCBC y 16 h0F0OF i 16 h8383 The 8B 10B decoder indicates whether the decoded 8 bit code group is a data or control code group on rx_datak Ifthe received 10 bit code group is one of the 12 control code groups Kx y specified in the IEEE 802 3 specification rx_datak is driven high If the received 10 bit code group is a data code group Dx y rx_datak is driven low 8B 10B Decoder Running Disparity Checker Feature Running disparity checker resides in 8B 10B decoder module This checker checks the current running disparity value and error based on the rate match output rx_runningdisp and rx_disperr indicate positive or negative disparity and disparity errors respectively Pseudo Random Binary Sequence PRBS Verifier The PRBS verifier checks the pseudo random patterns generated by the PRBS generator An error flag is asserted when an
72. Generxion Options 3 TX Bording Options PMA PCS Reconfiguration s TX channel bording mode Notbonded Dice Latency Standard PCS ii i annei bonding ma gt e PCle APE Ger2x1 and generation options ee ee ee Daet Geia Actual PCS TX channd bonding master o Pcie le on i F TX PLL Options P Cie APE Corde TX local clock division factor 7 Number of TX PLL clock inputs per channet i oN Note The external TX PLL P must be configured with an output clock frequency af 5 LLITETETITETTETETEETETETEETETETETTTTETETTETETETETTTTETETTTTETETETTITETETTTTETETTETTTETET ETT Z TX PMA Optional Ports Enatie tx pma Pout port Enable tx pma_div cikou port U pma_div cout dhision factor tential T gt MUL clock input selection Viel EIR 15 33 w Protocol or custom iannnnnnennnsdhat ate li tiriririiiiiiiiiiiiiiiitiiiiiii gy Enatte tx_prma_qripulup port QP Enatte tx_prma_aripulidr port QPD Enatte ty pena_tedetectre port OPH Enatie tx pma_nxfound port QP preset settings ro TOT o Note The Quartus II software version 13 1 does not perform legality checks for PCS to FPGA fabric speeds Although the Quartus II software version 13 1 checks the Transceiver data rate the PCS to FPGA fabric may be set too high if the PCS PMA interface width is too small for high data rates Later versions of the Quartus II software perform PCS interface legality checking Related Information e Configure the PHY I
73. IP will be available in a future release of the Quartus II software Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Needs a user created Soft IP for link training auto speed negotiation and sequencer functions PCS Direct support will be available in a future release of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software Altera Corporation UG A10XCVR 2 12 Using the Arria 10 Transceiver Native PHY IP 2013 12 02 Protocol Transceiver IP PCS Support Transceiver Protocol Preset Configuration Rule ASI Native PHY IP Standard Basic Custom User created Standard PCS SPI 5 100G SPI 5 50G Native PHY IP Enhanced SFI S User created Custom and other procols Native PHY IP Standard and Basis Custom User created Enhanced Standard PCS Basic Enhanced PCS Basic Custom with Rate Match Standard PCS Using the Arria 10 Transceiver Native PHY IP 17 18 19 20 21 22 23 24 This section describes use of the Altera provided Arria 10 Transceiver Native PHY IP core This IP core provides direct access to Arria 10 transceiver features You can enable the Standard and or Enhanced PCS datapaths If you enable both the Standard and Enhanced PCS datapaths you can use the Reconfiguration Interface to switch between them without device power down You can enable Gen3 PCS by selecting the Gen3 P
74. In daisy chained configu rations the local update coefficients substitute for the coefficients that would be set using Link Training dmo_lcl_coefh 1 0 Output Local update high bits 13 12 In daisy chained configurations the local update coefficients substitute for the coefficients that would be set using Link Training dmo_lcl_upd_new Output When asserted indicates a local update has occurred dmo_rx_trained Output When asserted indicates that the state machine has Altera Corporation finished local training Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Embedded Processor Interface Signals 2 125 Embedded Processor Interface Signals The optional embedded processor interface signals allow you to use the embedded processor mode of Link Training This mode overrides the TX adaptation algorithm and allows an embedded processor to initialize the link Table 2 98 Embedded Processor Interface Signals upi_mode_en Input When asserted enables embedded processor mode pt acj itso Input Selects the active tap The following encodings are defined e 2 b01 Main tap e 2 b10 Post tap e 2 b11 Pre tap upi_inc Input When asserted sends the increment command upi_dec Input When asserted sends the decrement command upi_pre Input When asserted sends the preset command upi init Input When asserted sends the initialize command upi_st_bert
75. Input When asserted starts the BER timer upi train ert Input When asserted indicates a training error upi_rx_trained Input When asserted the local RX interface is trained upo_enable Output When asserted indicates that the 10GBASE KR PHY IP Core is ready to receive commands from the embedded processor upo_frame_lock Output When asserted indicates the receiver has achieved training frame lock upo_cm_done Output When asserted indicates the master state machine handshake is complete upo_bert_done Output When asserted indicates the BER timer is at its maximum count uoe ber cnt lt w gt 1 0 Output Records the BER count upo_ber_max Output When asserted the BER counter has rolled over Output When asserted indicates that the remote coefficients are at their maximum or minimum values upo_coef_max Dynamic Reconfiguration Interface You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G data rates Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback 2 126 Table 2 99 Dynamic Reconfiguration Interface Signals Avalon MM Register Interface UG A10XCVR 2013 12 02 mode_lg_ Input Synchronous to This signal indicates the requested mode for the 10gbar mgmt_clk channel A 1 indicates 1G mode and a 0 indicates 10G mode re busy Output Synchronous to When asserted indicates that reconfiguration is in mgmt_clk progress Sy
76. KR FEC descrambler block descrambles received data to regenerate unscrambled data using the x x 1 polynomial Before the block boundary in the KR FEC sync block is detected the data at the input of the descrambler is sent directly to the KR FEC decoder When the boundary is detected the aligned word from the KR FEC sync block is descrambled with the Psuedo Noise PN sequence and then sent to the KR FEC decoder KR FEC Decoder The KR FEC decoder block performs the FEC 2112 2080 decoding function by analyzing the received 32 65 bit blocks for errors It can correct burst errors of 11 bits or less per FEC block KR FEC RX Gearbox The KR FEC RX gearbox block adapts the PMA data width to the larger bus width of the PCS channel It supports a 64 65 ratio Transcode Decoder The transcode decoder block performs the 65 bit to 64B 66B reconstruction function by regenerating the 64B 66B synchronization header Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Arria 10 Standard PCS Architecture 5 31 Arria 10 Standard PCS Architecture The standard PCS can operate at a data rate up to 12 5 Gbps Protocols such as PCI Express CPRI 4 2 GigE IEEE 1588 are supported in Hard PCS while the other protocols can be implemented using Basic Custom Standard PCS transceiver configuration rules Figure 5 38 Standard PCS Datapath Diagram
77. L fPLL Serial Clock Parallel Clock Serial Clock Parallel and Serial Clock Parallel and Serial Clock All configurations that use the standard PCS channel must have a 0 ppm phase difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO Figure 3 15 Receiver Enhanced PCS and PMA Clocking Receiver PMA Receiver Enhanced PCS FPGA rx_pma_div_clkout gt Fabric z 5 FS s e 5 amp Bs 5 n o O 2 O 5 a E 52 2 ib r 282i js8i Ee tad oO oS i oU PH i e G f pele e zoi ja g gt 5 8 5 2 Ee 8 aad Es eg EG BE x a a a g ses a oO oO wW E PRBS eRe 8 ll 5 venner gt Verifier L_ T K if T I T I T ji rx_clkout 10GBASE R 8 a x a P BER Checker Ors os OG ax U5 MEA we os Oa ou Lp tot EL E Si G ee S gs Par gs zo E8 a a 3 a g EG Parallel Clock Serial Clock Parallel and Serial Clock The receiver PCS forwards the following clocks to the FPGA fabric e rx_clkout for each receiver channel in a non bonded configuration when the rate matcher is not used e tx_clkout for each receiver ch
78. Local Device LT Link training in backplane Ethernet Clause 72 for 1OGBASE KR and 40GBASE KR4 LP Link partner to which the LD is connected MAC Media Access Control MII Media independent interface OSI Open System Interconnection PCS Physical Coding Sublayer PHY Physical Layer in OSI 7 layer architecture also in Altera device scope is PCS PMA PMA Physical Medium Attachment PMD Physical Medium Dependent SGMII Serial Gigabit Media Independent Interface WAN Wide Area Network XAUI 10 Gigabit Attachment Unit Interface PCI Express Arria 10 transceivers can be used to implement a complete PCIe solution for Gen1 Gen2 and Gen3 at data rates of 2 5 5 0 and 8 Gbps You can configure the transceivers for PCIe functionality using one of the following methods Arria 10 Hard IP for PCI Express This is a complete PCI Express solution that includes the Transaction Data Link and PHY MAC layers The Hard IP solution contains dedicated hard logic which is connected to the transceiver PHY interface Note For more information refer to the Arria 10 Hard IP for PCI Express User Guide Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 180 PCI Express 2013 12 02 e Native PHY IP in PIPE Gen1 Gen2 Gen3 Transceiver Configuration Rules Native PHY can be used to configure the transceiver in PCIe mode giving access to the PIPE interface commonly called PIPE mode i
79. PCS In serialize x4 mode the byte serializer serializes 32 bit data into 8 bit data As the parallel data width from the TX FIFO is divided four times the clock rate is quadrupled After byte serialization the byte serializer forwards the least significant word first followed by the most significant word For example if the FPGA fabric to PCS Interface width is 32 the byte serializer forwards tx_parallel_data 15 0 first followed by tx_parallel_data 31 16 Related Information PCI Express on page 2 179 For more information about using the Serialize x4 mode in the PCle protocol 8B 10B Encoder The 8B 10B encoder takes in 8 bit data and 1 bit control as input and converts them into a 10 bit output The 8B 10B encoder automatically performs running disparity check for the 10 bit output Additionally the 8B 10B encoder can control the running disparity manually using the tx_forcedisp and tx_dispval ports Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 34 8B 10B Encoder Control Code Encoding 2013 12 02 Figure 5 41 8B 10B Encoder Block Diagrams When the PCS PMA Interface Width is 10 bits When the PCS PMA Interface Width is 20 bits To the Serializer From the Byte Serializer oar ai datain 7 0 To the Serializer 8B 10B Encoder From the Byte Serializer q datain 15 8 lt tx_datak dataout 9 0 lt lt 8B 10B Encoder oe msg x _datak 1 lt M d
80. PHY Interface for PCI Express PIPE Architecture for more information Active High pipe_rx_polarity In N A When 1 b1 instructs the PHY layer to invert the polarity on the received data Active High pipe_powerdown 1 0 In tx_pma_clk Requests the PHY to change its power state to the specified state The Power States are encoded as follows 2 b00 PO Normal operation 2 b01 POs Low recovery time power saving state 2 b10 P1 Longer recovery time lower power state 2 b11 P2 Lowest power state Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 208 Native PHY IP Ports for PCI Express pees Transmit Vop margin selection The PHY MAC sets the value for this signal based on the value from the Link Control 2 Register The following encodings are defined 3 b000 Normal operating range 3 b001 Full swing 800 1200 mV Half swing 400 700 mV 3 b010 3 b011 Reserved 3 b100 3 b111 full swing 200 400mV half swing 100 200 mV else reserved pipe_tx_margin 2 0 In tx_pma_clk Indicates whether the transceiver is using full or low swing voltages as defined pipe_tx_swing In tx_pma_clk by the pipe_tx_margin 1 b0 Full swing 1 b1 Low swing Transmit de emphasis selection In PCI Express Gen2 5 Gbps mode it selects the pipe_tx_deemph In tx_pma_clk transmitter de emphasis 1 b0 6 dB 1 b1 3 5 dB Al
81. Reference clock input to the RX clock data recovery CDR circuitry Optional Ports rx_cdr_refclk1 Inputs Clock Reference clock input to the RX clock data recovery CDR i _eClic_ circuitry retelki rx_pma_ Input Asynchronous This port is only used for Quick Path Interconnect QPI qpipullup lt n gt applications 1 0 tise Output Asynchronous When asserted indicates that the CDR PLL is locked to the lockedtoref lt n gt incoming data rx_serial_ data 1L3 rx_is_ Output Asynchronous When asserted indicates that the CDR PLL is locked to the lockedtoref lt n gt incoming data rx_serial_data 130 rz set Input Asynchronous This port provides manual control of the RX CDR circuitry LoOekecico CaAica lt iaS i1 2 O rx_set_ Input Asynchronous This port provides manual control of the RX CDR circuitry lockedtoref lt n gt 1 0 rx_seriallp Input Asynchronous When asserted enables the TX to RX serial loopback path bken lt n gt 1 0 in the transceiver rx_prbs_ Output rx_ When asserted indicates the verifier has aligned and captured done lt n gt 1 0 coreclkin consecutive PRBS patterns and the first pass through a polynomial is complete The generator has restarted the polynomial rx_prbs_err lt n gt Output rx_ When asserted indicates an error only after the rx_prbs_ 130 coreclkin done signal has been asserted This signal pulses for every error that occurs
82. TX and RX serial data interface and provide status information a 0x422 lt p gt 1 0 pma_tx_pll_is__ Indicates that the TX PLL is locked to the input locked reference clock lt p gt is the number of PLLs 0x444 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted You must write a 0 to clear the reset condition 2 RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted You must write a 0 to clear the reset condition 3 RW reset_rx_digital Writing a 1 causes the internal RX digital reset signal to be asserted You must write a 0 to clear the reset condition 0x461 31 0 RW phy_serial_ Writing a 1 puts the channel in serial loopback loopback mode 0x464 31 0 RW pma_rx_set_ When set programs the RX CDR PLL to lock to the locktodata incoming data 0x465 31 0 RW pma_rx_set_ When set programs the RX clock data recovery locktoref CDR PLL to lock to the reference clock Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Creating a 1G 10GbE Design 2 175 m 0x466 31 0 pma_rx_is_ When asserted indicates that the RX CDR PLL is lockedtodata locked to the RX data and that the RX CDR has changed from LTR to LTD mode 0x467 31 0 RO pma_rx_is_ When asserted indicates that the RX CDR PLL is lockedtoref
83. The following figure shows a way of clock generation and distribution in Arria 10 devices for 1OGBASE R with KR FEC protocol Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR Figure 2 40 Clock Generation and Distribution for 10GBASE R with KR FEC 10GBASE R Hard IP Transceiver Channel TX 64 Bit Data 8 Bit Control 64 10 3125 Gbps Serial TX PCS TXPMA 3 pll_ref_clk 644 53125 MHz TLM LX PLLA T RX 64 Bit Data 8 Bit Control 64 10 3125 Gbps RX PCS RX PMA poca 156 25 MHz 161 13 MHz lt T P rx_coreclkin fPLL hq 8 33 Clocking in 10GBASE R and 10GBASE R with 1588 The XGMI interface defines the 32 bit data and 4 bit wide control character clocked between the MAC RS and the PCS at both the positive and negative edge double data rate DDR of the 156 25 MHz interface clock The transceivers do not support the XGMII interface to the MAC RS as defined in the IEEE 802 3 2008 specification Instead they support a 64 bit data and 8 bit control single data rate SDR interface between the MAC RS and the PCS Figure 2 41 XGMII Interface DDR and Transceiver Interface SDR for 10GBASE R Configurations XGMII Transfer DDR Interface Clock 156 25 MHz TXD RXD 31 0 X DO D1 D2 KA EA Kale TX
84. This feature swaps the LSByte with the MSByte and vice versa For example when the PCS PMA interface width is 16 bits 7 0 bits LSByte gets swapped with 15 8 bits MSByte and 15 8 bits MSByte gets swapped with 7 0 bits LSByte As a result the 16 bit bus becomes MSB to LSB bits 7 0 to bits 15 8 Polarity Inversion Feature The polarity inversion feature is used in situations where the positive and the negative signals of a serial differential link are erroneously swapped during board layout The polarity inversion feature inverts the value of each bit of the input data For example if the input data is 00101001 then the data gets changed to 11010110 after polarity inversion Pseudo Random Binary Sequence PRBS Generator The PRBS generator block generates PRBS patterns and square wave patterns PRBS test patterns may be considered equivalent to noise Use these pattern generators to test the transceiver link with a noisy signal using the test patterns listed below by placing the transceiver in loopback mode Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 36 TX Bit Slip 2013 12 02 The PRBS generator supports a 64 bit PCS PMA interface PRBS9 supports 64 bit and 10 bit PCS PMA interface widths to allow testing at lower data rates The following PRBS test patterns are supported e PRBS9 x x 1 e PRBSI5 x x 441 e PRBS23 x 4x 41 e PRBS31 x x 1 Enable the P
85. Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 64B 66B Decoder and Receiver State Machine 5 25 received the frame synchronizer loses frame lock In addition the frame synchronizer provides rx_enh_frame_lock receiver metaframe lock status to the FPGA fabric Note The Interlaken frame synchronizer is available to implement the Interlaken protocol 64B 66B Decoder and Receiver State Machine The 64B 66B decoder reverses the 64B 66B encoding process The decoder block also contains a state machine RX SM designed in accordance with the IEEE802 3 2008 specification The RX SM checks for a valid packet structure in the data sent from the remote side It also performs functions such as sending local faults to the Media Access Control MAC Reconciliation Sublayer RS under reset and substituting error codes when the 1OGBASE R and 10GBASE KR PCS rules are violated Note The 64B 66B decoder is available to implement the 1OGBASE R protocol PRBS Verifier The pseudo random bit stream PRBS block verifies the pattern generated by the PRBS generator The verifier supports the 64 bit PCS PMA interface PRBS9 also supports 10 bit PMA data width to allow testing at a lower data rate The following PRBS verifiers are supported e PRBS9 x x 1 e PRBSI5 x gt x4 1 e PRBS23 x x 1 e PRBS31 x x 1 Figure 5 32 PRBS9 Verify Serial Implementation PRBS datain Y e gt SO S1 gt gt s4 g
86. Transceiver PHY Reset Controller Interfaces 2013 12 02 rx_is_lockedto Input Provides the rx_is_lockedtodata status data lt n gt 1 0 from each RX CDR When asserted indicates that a particular RX CDR is ready to receive input data If you do not choose separate controls for the RX channels these inputs are ANDed together internally to provide a single status signal tx_manual lt n gt Input Asynchronous This optional signal places tx_digitalreset 130 controller under automatic or manual control When asserted the associated tx_digital reset controller logic does not automatically respond to deassertion of the pl 1_locked signal However the initial tx_digitalreset sequence still requires a one time rising edge on pll_locked before proceeding When deasserted the associated tx_digitalreset controller automatically begins its reset sequence whenever the selected p11_locked signal is deasserted rx_manual lt n gt Input Asynchronous This optional signal places rx_digitalreset 1 0 logic controller under automatic or manual control In manual mode the rx_digital reset controller does not respond to the assertion or deassertion of the rx_is_ lockedtodata signal The rx_digital reset controller asserts rx_ready when the pll_locked signal is asserted clock Input N A A free running system clock input to the Transceiver PHY Reset Controller from which all internal logic is driven Ifa free running clo
87. UG A10XCVR 2013 12 02 Transmitter and Receiver Latency 2 219 Related Information Word Aligner on page 5 37 Transmitter and Receiver Latency The latency variation from the link synchronization function in the word aligner block is deterministic with the rx_bitslipboundaryselectout port In additional you can optionally fix the round trip transceiver latency for port implementation in the remote radio head to compensate for latency variation in the word aligner block with the tx_bitslipboundaryselect port Thetx_bitslipboundary select port is available to control the amount of bits to be slipped in the transmitter serial data stream You can optionally use the tx_bitslipboundaryselect port to round the round trip latency to a whole number of cycles To use the byte deserializer create additional logic in the FPGA fabric to determine if the comma byte is received in the lower or upper byte of the word The delay is dependent on the word in which the comma byte appears The total transmitter and receiver channel datapath latencies are computed as follows e The total transmitter channel datapath latency is equal to the transmitter fixed latency and tx_bitslipboundaryselect delay e The total receiver channel datapath latency is equal to the receiver fixed latency rx_std_bitslip boundarysel delay and byte deserializer delay Note Latency numbers are pending device characterization Word Aligner in Manual Mode for CPRI When confi
88. When asserted this signal forces the transmitter 130 to electrical idle This port has no effect when you configure the transceiver for the PCI Express protocol Related Information e ATX PLL IP on page 3 6 e CMU PLL IP on page 3 21 e fPLL IP on page 3 13 e Ports and Parameters on page 6 1 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Preset Configuration Options 2 61 e Transceiver PHY Reset Controller Interfaces on page 4 12 This section describes the top level signals for the Transceiver PHY Reset Controller IP core Preset Configuration Options You can select preset settings for the Transceiver Native PHY IP defined for each protocol Use presets as a starting point to specify parameters for your specific protocol or application To apply a preset to the Transceiver Native PHY IP double click on the preset name When you apply a preset all relevant options and parameters are set in the current instance of the Transceiver Native PHY IP For example selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires The preset does not validate ports or parameters after the preset has been applied Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design Any changes that you make are validated by the design rules for the Transceiver configuration rules you specified not the
89. Yes supported through the Gearbox Scrambler Descrambler N A N A Yes implemented in FPGA fabric Power state management Yes Yes Yes Receiver PIPE status encoding pipe_rxstatus 2 0 Yes Yes Yes Dynamic switching between 2 5 Gbps and 5 Gbps N A Yes N A signaling rate Dynamic switching between 2 5 Gbps 5 Gbps and 8 Gbps N A N A Yes signaling rate Dynamic transmitter margining for differential output N A Yes Yes voltage control Dynamic transmitter buffer de emphasis of 3 5 dB and N A Yes Yes 6 dB Dynamic Gen3 transceiver pre emphasis de emphasis N A N A Yes and equalization PCS PMA interface width Genl 10 Gen2 10 Gen3 32 Related Information Intel PHY Interface for the PCI Express PIPE Architecture PCI Express 2 0 e Intel PHY Interface for the PCI Express PIPE Architecture PCI Express 3 0 e Arria 10 Standard PCS Architecture on page 5 31 For more information about PIPE Gen1 and Gen2 e PCIe Gen3 PCS Architecture For more information about PIPE Gen3 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Gen1 Gen2 Features 2 183 Gen1 Gen2 Features In a PIPE configuration each channel has a PIPE interface block that transfers data control and status signals between the PHY MAC layer and the transceiver channel PCS and PMA blocks The PIPE configu ration is based on PIPE 2 0 specification If you use a PIPE configuration you must implement the PHY MAC lay
90. _read Input Synchronous to Read signal Active high mgmt_clk Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY Register Definitions 2 127 mgmt _ Output Synchronous to When asserted indicates that the Avalon MM slave waitrequest mgmt_clk interface is unable to respond to a read or write request When asserted control signals to the Avalon MM slave interface must remain constant Related Information Avalon Interface Specifications 10GBASE KR PHY Register Definitions The Avalon MM slave interface signals provide access to the control and status registers The following table specifies the control and status registers that you can access over the Avalon MM PHY management interface A single address space provides access to all registers Note Unless otherwise indicated the default value of all registers is 0 Note Writing to reserved or undefined register addresses may have undefined side effects Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 128 10GBASE KR PHY Register Definitions Table 2 101 10GBASE KR Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr Reset SEQ When set to 1 resets the 10GBASE KR sequencer auto rate detect logic initiates a PCS reconfiguration and may restart Auto Negotiation Link Training or both if AN and LT are enabled 10GBAS
91. and values Table 3 12 fPLL IP Ports pll_powerdown input Asynchronous Resets the PLL when asserted high pll refelko input N A Reference clock input port 0 There are five reference clock input ports The number of reference clock ports available depends on the Number of PLL reference clocks parameter pll_refclk1 input N A Reference clock input port 1 plil _refelk input N A Reference clock input port 2 pll_refclk3 input N A Reference clock input port 3 pll_refclk4 input N A Reference clock input port 4 tx_serial_clk output N A High speed serial clock output port for GX channels Represents the x1 clock network tx serial clk n output N A Thisistx_serial_clk with 180 degree phase shift pll_locked output Asynchronous Active high status signal which indicates if PLL is locked pll_pcie_clk output N A Used for PCIe reconfig_clk0 input N A Optional Avalon interface clock Used for PLL reconfiguration reconfig_reset0O input reconfig_clk0O Used to reset the Avalon interface reconfig_write0 input reconfig_clk0 Active high write enable signal reconfig_read0 input reconfig_clk0 Active high read enable signal reconfig_address0 9 0 input reconfig_clk0O 10 bit address bus used to specify address to be accessed for both read and write operations PLLs and Clock Networks CJ Send Feedback Altera Corporation 3 18 fPLL IP UG A10XCVR 2013 12 02 CECCON
92. asserted a few input clock clock cycles after the deassertion of rx_ digitalreset Some protocol implementa tions may require you to monitor this signal prior to sending data The width of this signal depends on the number of channels pll_ Output Synchronous to the Asserted to power down a transceiver PLL circuit powerdown lt p gt Transceiver PHY When asserted the selected TX PLL is reset 150 Reset Controller input clock Transceiver PHY Reset Controller Resource Utilization This section describes the estimated device resource utilization for two configurations of the transceiver PHY reset controller The exact resource count varies by Quartus II version number as well as by optimization options Table 4 5 Reset Controller Resource Utilization Configuration Combination ALUTs Logic Registers Single transceiver channel approximately 50 approximately 50 4 Transceiver channels shared TX approximately 100 approximately 150 reset separate RX resets Using a User Coded Reset Controller You can choose to design your own user coded reset controller rather than using Altera s Transceiver PHY Reset Controller IP core Your user coded reset controller must provide the following functionality for the recommended reset sequence e A clock signal input for your reset logic e Holds the transceiver channels in reset by asserting the appropriate reset control signals e Checks the PLL status for exam
93. be enabled in low latency basic and basic rate match mode whereas the word aligner is available in any mode This feature is parameter based and creates no additional ports If there is more than one channel in the design all channels have TX bit reversal To enable this feature select the Enable TX bit reversal option You can verify this feature by monitoring rx_parallel_data Figure 2 127 TX Bit Reversal tx_parallel_data 11111100001110111100 rx_parallel_data 00000 00111101110000111111 TX Byte Reversal The TX byte reversal feature can be enabled in low latency basic and basic rate match mode whereas the word aligner is available in any mode This feature is parameter based and creates no additional ports If there is more than one channel in the design all channels have TX byte reversal To enable this feature select the Enable TX byte reversal option You can verify this feature by monitoring rx_parallel_data Figure 2 128 TX Byte Reversal tx_parallel_data 11111100001110111100 rx_parallel_data 00000000 11101111001111110000 How to Implement the Basic Basic with Rate Match Transceiver Configuration Rules in Arria 10 Transceivers Before you begin You should be familiar with the Standard PCS and PMA architecture PLL architecture and the reset controller before implementing your Basic protocol IP 1 Open the MegaWizard Plug In Manager and select the PHY IP Altera Corpora
94. between the receiver input reference clock and the upstream transmitter reference clock The rx_is_lockedtodata signal toggles until the CDR sees valid data therefore you should hold receiver PCS logic in reset cx_digitalreset for a minimum of 4 us after rx_is_lockedtodata remains continuously asserted Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 12 CDR Lock Modes 2013 12 02 CDR Lock Modes You can configure the CDR in either automatic lock mode or manual lock mode By default the Quartus II software configures the CDR in automatic lock mode Automatic Lock Mode In automatic lock mode the CDR initially locks to the input reference clock LTR mode After the CDR locks to the input reference clock the CDR locks to the incoming serial data LTD mode when the following conditions are met e The signal threshold detection circuitry indicates the presence of valid signal levels at the receiver input buffer when rx_std_signaldetect is enabled e The CDR output clock is within the configured ppm frequency threshold setting with respect to the input reference clock frequency locked e The CDR output clock and the input reference clock are phase matched within approximately 0 08 unit interval UI phase locked If the CDR does not stay locked to data because of frequency drift or severe amplitude attenuation the CDR switches back to LTR mode Manual Lock Mode The PPM detector
95. between deassertion of each channel s FIFO reset N To calculate the channel skew the following five scenarios are considered 1 Non bonded In this case both the PMA and PCS are non bonded Skew ranges from 0 UI to S 1 N S UI 2 PMA bonding using x6 xN clock network In this case the PCS is non bonded Skew ranges from 0 to N S UI x6 xN clock skew 3 PMA bonding using the PLL feedback compensation clock network In this case the PCS is non bonded Skew ranges from 0 to N S UI reference clock skew x6 clock skew 4 PMA and PCS bonding using the x6 xN clock network Skew x6 xN clock skew 5 PMA and PCS bonding using PLL feedback compensation clock network Skew reference clock skew x6 clock skew PLL Feedback and Cascading Clock Network The PLL feedback and cascading clock network spans the entire side of the device and is used for PLL feedback compensation bonding and PLL cascading Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 PLL Feedback and Cascading Clock Network 3 39 Figure 3 16 PLL Feedback and Cascading Clock Network Transceiver Bank PLL Feedback and Cascading Clock Network Master CBG1 l Bidirectional l y gt Y i y Tristate Buffer Master CBG0 Bidirectional l l X Tristate Buffer Legend refclk Lines
96. can use the protocol presets described in Preset Configuration Options You can then modify the settings to meet your specific requirements 4 Click Finish to generate the Native PHY IP this is your RTL file Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 228 Transceivers How to Implement the Basic Enhanced PCS and Basic with KR FEC Transceiver Configuration Rules in Arria 10 UG A10XCVR 2013 12 02 Figure 2 97 Signals and Ports of Native PHY IP for Basic Enhanced PCS Basic with KR FEC Configurations tx_cal_busy lt rx_cal_busy lt 4 NIOS Hard Calibration IP TX PMA tx_serial_data lt tx_serial_clkO from TX PLL Serializer A Clock _ Generation 4 reconfig_reset Reconfiguration la reconfig_cik Registers gt reconfig_avmm TX Enhanced PCS tx_digital_reset lt 7 tx_digital_reset tx_control 17 0 tx_control 17 0 tx_parallel_data 127 0 tx_parallel_data 127 0 tx_coreclkin _ tx_coreclkin tx_clkout gt tx_clkout tx_enh_data_valid tx_enh_data_valid Block tx_analog_reset RX PMA Deserializer _ rx_serial_data rx_cdr_refclkO rx_is_lockedtodata lt rx_is_lockedtoref lt RX Enhanced PCS rx_digital_rese
97. clock inputs per channel 1 2 4 8 Initial TX PLL clock input selection 0 Enable tx_pma_clkout port On Off Enable tx_pma_div_clkout port On Off tx_pma_div_clkout division factor Disabled 1 2 33 40 66 Enable tx_pma_elecidle port On Off Enable tx_pma_qpipullup port QPI On Off Enable tx_pma_qpipulldn port QPI On Off Enable tx_pma_txdetectrx port QPI On Off Enable tx_pma_rxfound port QPI On Off Table 2 70 RX PMA Parameters Parameter Value Number of CDR reference Clocks 1to5 Selected CDR reference clock 0to4 Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 90 Native PHY IP Parameter Settings for GbE and GbE with 1588 UG A10XCVR 2013 12 02 Parameter Value Selected CDR reference clock frequency Select legal range defined by the Quartus II software PPM detector threshold 62 5 100 125 200 250 300 500 1000 Decision feedback equalization mode Disabled Enable rx_pma_clkout port On Off Enable rx_pma_div_clkout port On Off rx_pma_div_clkout division factor Disabled 1 2 33 40 50 66 Enable rx_pma_clkslip port On Off Enable rx_pma_qpipulldn port QPI On Off Enable rx_is_lockedtodata port On Off Enable rx_is_lockedtoref port On Off Enable rx_set_locktodata and rx_set_locktoref ports On Off Enable rx_seriallpbken port On Off Enable PRBS verifier control and status ports On Off Table 2 71 Standard PCS Parameters
98. data for every 16 shifts as each shift is 2 bits for converting the initial 34 bit to 32 bit in the gearbox After 16 shifts the gearbox has an extra 32 bits of data that were transmitted out thus requiring a gap in the input data stream This is achieved by driving pipe_t x_data_valid low for one cycle after every 16 blocks of data Figure 2 76 Gen3 Data Transmission tx_clkout pipe tx sync_hdr 10 10 10 pipe_tx_blk_start pipe_tx_data_valid Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode 2 191 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode Figure 2 77 Use ATX PLL or fPLL for Gen1 Gen2 x1 Mode X1 Network 6 Ch5 eoeeee gt CGB gt fPLL1 gt Be Law CDR ATX PLL1 _____ gt 6 an Ch 4 eeecece gt CGB gt Master 4 lt 2 SBR cop E7 mana Cha e220 08 piccel pl gt Path for Clocking in Gen1 Gen2 x1 Mode Path for Clocking in Gen1 Gen2 x1 Mode
99. data includes only the bits required for the configu ration you specify Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 38 Enhanced PCS and PMA Ports UG A10XCVR 2013 12 02 Description When FPGA fabric PCS interface data width is 64 bits you must ground data 127 64 The following bits are active for narrower interfaces e 32 bit FPGA fabric IF width tx_parallel_data 31 0 Ground 63 32 e 40 bit FPGA fabric IF width tx_parallel_data 39 0 Ground 63 40 e 64 bit FPGA fabric IF width tx_parallel_data 63 0 When the FPGA fabric PCS interface data width is 128 bits double width mode the following bits are active for narrower double width configurations e 32 bit FPGA fabric IF width data 95 64 Ground 127 96 e 40 bit FPGA fabric IF width data 103 64 Ground 127 104 e 64 bit FPGA fabric IF width data 127 64 Note You cannot select the Enable simplified interface if you plan to dynamically reconfigure between multiple protocols unused_tx_ parallel_data tx_control lt n gt lt 3 gt Input S elkout EX This signal specifies the unused data when you turn on Enable simplified data interface Connect all of these bits to 0 Indicates whether the tx_parallel_data bus is 1 0 or tx_control lt n gt lt 18 gt 1 0 Altera Corporation Input coreclkin control or data If you select Enable simplified interfac
100. device characterization Currently GT channel bonding is not supported Reset Controller Each GT channel instantiated will have independent analog and digital reset ports Refer to the Resetting Transceiver Channels chapter for more details on designing a reset controller to reset these ports Related Information Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details How to Implement Designs for Data Rates Above 17 4 Gbps Using Enhanced PCS in Low Latency Mode Before you begin You should be familiar with the Enhanced PCS and PMA architecture PLL architecture and the reset controller 1 Open the MegaWizard Plug In Manager and select the Native PHY IP Refer to Select and Instantiate PHY IP on page 2 2 for detailed steps 2 Select Basic Enhanced PCS from the Transceiver configuration rules list located under Datapath Options 3 Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Basic Enhanced PCS Transceiver Configuration Rule for each input of the Arria 10 Transceiver Native PHY MegaWizard as a starting point Or you can use the protocol presets described in Preset Configuration Options You can then modify the settings to meet your specific requirements Ensure that the data rate is between 17400 and 28100 Mbps Select a CDR reference clock to match your data rate Set the Enhanced PCS PMA interface width to 64 bits Set the FPGA Fabri
101. e 1G 10GbE PHY Functional Description on page 2 152 Design Guidelines Consider the following guidelines while designing with 1G 10GbE PHY Using the 1G 10GbE PHY without the Sequencer The sequencer brings up channel based initial datapath and performs parallel detection To use the 1G 10GbE PHY without the sequencer turn off the Enable automatic speed detection parameter Turning off the sequencer results in the following additional ports e rc_busy e start_pcs_reconfig e mode_lg_l0gbar These ports perform manual reconfiguration The following figure shows how these ports are used for 1G and 10G configuration Figure 2 64 Timing for Reconfiguration without the Sequencer mgmt_clk rc_busy start_pcs_reconfig mode_1g_10bar Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR siis 2013 12 02 Channel Placement Guidelines 2 177 Channel Placement Guidelines The channels of multi channel 1G 10G designs do not need to be placed contiguously However channels instantiated in different transceiver banks require PLLs in the same bank Currently the Quartus II software version 13 1 for Arria 10 devices does not support PMA bonding for 10GBASE KR PHY IP Design Example Altera provides a design example to assist you in integrating your Ethernet PHY IP into your complete design The MAC and PHY design e
102. for the parallel and serial clocks Number of TX 1 2 3 Specifies the number of clock inputs per PLL channel Use this PLL clock inputs parameter when you plan to dynamically switch between TX PLL per channel clock sources Up to 4 input sources are possible InitialTX PLL 0 lt no of TX PLL Specifies the initially selected TX PLL clock input This parameter clock input clock inputs gt 1 is necessary when you plan to switch between multiple TX PLL selection clock inputs Table 2 6 TX PMA Optional Ports Enable tx_pma_ On Off Enables the optional t x_pma_clkout output clock This is the clkout port low speed parallel clock from the TX PMA The source of this clock is the deserializer It is driven by the PCS PMA interface block Enable tx_pma_ On Off Enables the optional t x_pma_div_clkout output clock This div_clkout port clock is generated by the serializer You can use this to drive core logic to drive the PCS to fabric or both If you specify a tx_pma_div_clkout division factor of 1 or 2 this clock output is derived from the PMA parallel clock If you specify a tx_pma_div_clkout division factor of 33 40 or 66 this clock is derived from the PMA serial clock This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency such as 66 40 applications tx_pma_div_ Disabled 1 2 33 40 Specifies the division factor for the tx_pm
103. gt rx_cal_busy tx_digital_reset gt TX Standard PCS TX PMA tx_datak tx_datak tx_parallel_data 7 0 gt tx_parallel_data 7 0 w tx_coreclkin P tx_coreclkin A Serializer gt tx_serial_data tx_clkout lt lt tx_clkout A pipe_rx_elecidle lt PIPE Interface gt pipe_hclk_out from TX PLL pipe_phy_status lt e pipe_hclk_in from TX PLL pipe_rate lt pipe_g3_tx_deemph oi pipe_g3_rxpresethint i pipe_sw_done pipe_rx_valid pipe_rx_polarity gt pipe_rx_status pipe_elecidle gt gt pipe_sw pipe_tx_detectrx_loopback gt pipe_m_sync_hdr pipe_powerdown Local pipe_rx_eidleinfersel Clock dt tx serial_clk0 from TX PLL pipe_tx_sync_hdr Divider tx_analog_reset lt rx_analog_reset lt lt 1 1x digital_reset pl RX Standard PCS i RX PMA rx_datak lt lt rx_datak y rx_parallel_data 7 0 4 rx_parallel_data 7 0 rx serial_data rx_clkout lt lt rx_clkout 10 ma rx cdr_refclk0 rx_coreclkin rx_coreclkin 7 Deserializer GDR rx_is_lockedtodata rx_syncstatus lt q rx_syncstatus p gt rx_is_lockedtoref 4 Geni Gen2 Gen3 Black Gen2 Gen3 Red Gen3 Blue Table 2 131 Ports for Arria 10 Transceiver Native PHY in PIPE Mode Clocks The 100 125 MHz input rz edi refelko In N A reference clock source for the PHY s TX and RX PLL The high speed serial clock tx_serial_clk0 generated by
104. i rx digital reset gt RX Standard PCS RX PMA rx_datak lt rx_datak y rx_parallel_data 7 0 4 rx parallel_data 7 0 4 1x serial_data rx_clkout lt lt rx_clkout 10 rx cdr_refclko Le rx_coreclkin Desenalizer CDR rx_is_lockedtodata rx_errdetect lt rx_errdetect p gt rx_is_lockedtoref rx_disperr lt lt rx_disperr rx_runningdisp 4 rx_runningdisp rx_patterndetect lt j rx_patterndetect rx_syncstatus lt lt rx_syncstatus rx_rmfifostatus 1 lt rx_rmfifostatus 1 Note 1 Only applies when using the Basic with Rate Match transceiver configuration rule 5 Instantiate and configure your PLL 6 Create a transceiver reset controller 7 Connect the Native PHY IP to the PLL IP and the reset controller Use the information in Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations to connect the ports Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 246 Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations 2013 12 02 Figure 2 130 Connection Guidelines for a Basic Custom Design tx_parallel_data tx_datak tx_clkout tx_digital_reset tx_analog_reset rx_digital_reset tx_serial_data pll_ref_clk rx_serial_data pll_locked pll_powerdown tx_ready rx_is_lockedtoref rx_is_lockedtodata tx_parallel_data tx_datak tx_cl
105. in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for Interlaken 2 77 Parameter Value Enable rx_enh_fifo_rd_en port On Interlaken Enable rx_enh_fifo_align_val port On Off Interlaken Enable rx_enh_fifo_align_clr port On Interlaken Table 2 55 Interlaken Frame Generator Parameters Parameter Value Enable Interlaken frame generator On Frame generator metaframe length 5 to 8192 Enable frame burst On Enable tx_enh_frame port On Enable tx_enh_frame_diag_status port On Enable tx_enh_frame_burst_en port On Table 2 56 Interlaken Frame Synchronizer Parameters Parameter Value Enable Interlaken frame synchronizer On Frame synchronizer metaframe length 5 to 8192 Enable rx_enh_frame port On Enable rx_enh_frame_lock port On Off Enable rx_enh_frame_diag_status port On Off Table 2 57 Interlaken CRC 32 Generator and Checker Parameters Parameter WALI Enable Interlaken TX CRC 32 generator On Enable TX CRC 32 generator error insertion On Off Enable Interlaken RX CRC 32 checker On Enable rx_enh_crc32_err port On Off Implementing Protocols in Arria 10 Transceivers J Send Feedback Altera Corporation UG A10XCVR 2 78 Native PHY IP Parameter Settings for Interlaken 2013 12 02 Table 2 58 64B 66B Encoder and Decoder Parameters Parameter Value
106. is set to OK The legal range is 500 510 ms For more information refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Std 802 3ap 2007 Link fail inhibit time for 1Gb Ethernet Altera Corporation 40 50 ms Specifies the time before link_status is set to FAIL or OK A link fails if the link_fail_inhibit_ time has expired before Link_status is set to OK The legal range is 40 50 ms For more information refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Std 802 3ap 2007 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 PHY Analog Parameters PHY Analog Parameters 2 159 You can specify analog parameters using the Quartus II Assignment Editor the Pin Planner or through the Quartus II Settings File qsf Refer to the appropriate link for a description of analog parameters 1G 10GbE PHY Interfaces Figure 2 63 1G 10GbE PHY Top Level Signals XGMII GMIl MII Interfaces Avalon MM PHY Management Interface Clocks and Reset Interface 1G 10GbE Top Level Signals xgmii_tx_dc 71 0 xgmii_tx_clk xgmii_rx_de 71 0 xgmii_rx_clk gmii_tx_d 7 0 gmii_rx_d 7 0 gmii_tx_en gmii_tx_err gmii_rx_err gmii_rx_dv mii_tx_d 3 0 mii_tx_en mii_tx_err mii_tx_clkena mii_tx_clkena_half_rate mii_rx_d 3 0 mii_rx_en t mii_rx_err mii_rx_clkena mii_rx_clkena_half_rate mgmt_clk mgmt_clk_reset mgmt_address 10 0 mgm
107. locked to the reference clock 0 RW tx_invpolarity Whenset to 1 the TX interface inverts the polarity of the TX data Inverted TX data is input to the 8B 10B encoder 1 RW rx_invpolarity Whenset to 1 the RX channels inverts the polarity of the received data Inverted RX data is input to the 8B 10B decoder Ores 2 RW rx_bitreversal_ When set to 1 enables bit reversal on the RX enable interface The RX data is input to the word aligner 3 RW rx_bytereversal_ When set enables byte reversal on the RX interface enable The RX data is input to the byte deserializer 4 RW force_ When set to 1 forces the TX outputs to electrical electrical_idle idle 0 R rx_syncstatus When set to 1 indicates that the word aligner is synchronized to incoming data 1 R rx_patterndetect When set to 1 indicates the 1G word aligner has detected a comma 2 R rx riv When set to 1 indicates a run length violation 3 R rx_rmfifodatain When set to 1 indicates the rate match FIFO 0x4A9 serted inserted code group 4 R rx_ When set to 1 indicates that rate match FIFO rmfifodatadeleted deleted code group 5 R rx_disperr When set to 1 indicates an RX 8B 10B disparity error 6 R rx_errdetect When set to 1 indicates an RX 8B 10B error detected Creating a 1G 10GbE Design Here are the steps you must take to create a 1G 10GbE design using the 1G 10GbE PHY IP 1 Generate the 1G 10GbE PHY with the required parameterization
108. mode e Bit 9 mode 1 LT Mode e Bit 10 mode 2 10G data mode e Bit 11 mode 3 Gige data mode e Bit 12 mode 4 Reserved for XAUI e Bit13 mode 5 10G FEC mode KR FEC Ability Indicates whether or not the 1OGBASE KR PHY supports FEC For more information refer to the FEC variable FEC_Enable as defined in Clause 74 8 2 and 1OGBASE KR PMD control register bit 1 171 0 IEEE 802 3ap 2007 Reserved 0x4B2 RWSC FEC TX Error Insert Writing a 1 inserts 1 error pulse into the TX FEC depending on the Transcoder and Burst error settings Software clears this register 31 15 RWSC Reserved 0x0DC Qx0DD Ox0DE OxODF RSC FEC Corrected Blocks Counts the number of corrected FEC blocks Resets to 0 when read Otherwise it holds at the maximum count and does not roll over Refer to Clause 74 8 4 1 of IEEE 802 3ap 2000 for details The low order byte of each register maps to the following bits of the 32 bit counter e 0x0DC 7 0 7 0 e Ox0DD 7 0 15 8 e Ox0DE 7 0 23 16 e Ox0DF 7 0 31 24 0x0E0 Ox0E1 Ox0E2 0x0E3 Altera Corporation RSC FEC Uncorrected Blocks Counts the number of uncorrectable FEC blocks Resets to 0 when read Otherwise it holds at the maximum count and does not roll over Refer to Clause 74 8 4 1 of IEEE 802 3ap 2000 for details The low order byte of each register maps to the following bits of the 32 bit counter e 0x0E0 7 0 7 0 e
109. mode the byte serializer is bypassed The data from the TX FIFO is directly transmitted to the 8B 10B encoder TX Bitslip or Serializer depending on whether or not the 8B 10B encoder and TX Bitslip are enabled Disabled mode is used in low speed applications such as GigE where the FPGA fabric and the TX standard PCS can operate at the same clock rate Byte Serializer Serialize x2 Mode The serialize x2 mode is used in high speed applications such as the PCIe Gen1 or Gen2 protocol implementation where the FPGA fabric cannot operate as fast as the TX PCS In serialize x2 mode the byte serializer serializes 16 bit 20 bit when 8B 10B encoder is not enabled 32 bit and 40 bit when 8B 10B encoder is not enabled input data into 8 bit 10 bit 16 bit and 20 bit data respectively As the parallel data width from the TX FIFO is halved the clock rate is doubled After byte serialization the byte serializer forwards the least significant word first followed by the most significant word For example if the FPGA fabric to PCS Interface width is 32 the byte serializer forwards tx_parallel_data 15 0 first followed by tx_parallel_data 31 16 Related Information PCI Express on page 2 179 For more information about using the Serialize x2 mode in the PCle protocol Byte Serializer Serialize x4 Mode The serialize x4 mode is used in high speed applications such as the PCIe Gen3 protocol mode where the FPGA fabric cannot operate as fast as the TX
110. noooo00 rx_enh _fifo_align_clr 24000000 G 24000000 24 htfittt Se4h000000 rx_enh_fifo_align_val 24h000000 24h00 24 h000001 i 27h00 pa nit rx_enh_fifi_rd_en 24 h000000 4 24 h000000 Wrnooo000 2a ntti 24 h00 24 nett rx_enh_data_valid 24h000000 G24h000000 W27 h000000 aa het 2r hoo 2a nett rx_parallel_data _1536 h0100009c0100 1536 h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000 1536 h01000 T Jasaehie rx_control 240h0441104411044 Y240 h044110441104404411044110441104411044110441104411044110441104411 240h044110 240h90a 240h826 Assert align_clr Start Reading Data to Re Align Based on FIFO Flags Related Information e Arria 10 Enhanced PCS Architecture on page 5 14 For more information about Enhanced PCS architecture e Arria 10 PMA Architecture on page 5 1 For more information about PMA architecture e Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks e PLLs on page 3 3 PLL architecture and implementation details e Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details e Enhanced PCS and PMA Ports on page 2 37 For detailed information about the available ports in the Interlaken protocol Design Example Altera provides a PHY layer only design example to help you integrate an Interlaken PHY into your complete design The TX soft bonding logic and RX multi lane deskew st
111. package provides both the MAC Layer and the physical PHY layer functionality e You can implement the MAC in the FPGA core and connect this MAC to the transceiver PHY through the PIPE interface This section will focus on the basic blocks of PIPE 3 0 based Gen3 PCS architecture The PIPE 3 0 based Gen3 PCS uses a 128b 130b block encoding decoding scheme which is different from the 8B 10B scheme Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback 5 46 Arria 10 PCI Express Gen3 PCS Architecture ries Mi used in Gen1 and Gen2 The 130 bit block contains a 2 bit sync header and a 128 bit data payload For this reason Arria 10 devices include a separate Gen3 PCS that supports functionality at Gen3 speeds This PIPE interface supports the seamless switching of Data and Clock between the Gen1 Gen2 and Gen3 data rates and provides support for PIPE 3 0 features The PCIe Gen3 PCS will support the PIPE interface with the Hard IP enabled as well as with the Hard IP bypassed Note For more information about Hard IP based implementation refer to the Altera Hard IP for PCIe Users Guide Figure 5 50 Gen3 PCS Block Diagram TX PCle Gen3 PCS Standard FPGA PCS i 9 o 32 Fabric Q te BEE 32 Q nu OD rox 58 S
112. parallel data source interface This clock frequency is 125 MHz in 1G mode and 257 81 MHz in 10G Mode and 161 13 MHz with FEC enabled Tz ClkoOut Output XGMII GMII RX clock for the RX parallel data source interface This clock frequency is 125 MHz in 1G mode and 257 81 in 10G Mode and 161 13 MHz with FEC enabled tx_pma_div_clkout Output This is the divided 33 clock from the TX serializer You can use this clock for the for xgmii_tx_clk or xgmii_rx_clk This clock frequency is 125 MHz for 1G and 156 25 MHz for 10G The frequencies are the same if you enable 1588 or FEC Ex pma div Clkowet Output This is the divided 33 clock from CDR recovered clock This clock frequency is 125 MHz for 1G and 156 25 MHz for 10G The frequencies are the same if you enable 1588 or FEC This clock is not used for clock the 10G RX datapath If PHY is reconfigured to 1G mode this clock frequency changes to 125 MHz tx_analogreset Input Resets the analog TX portion of the transceiver PHY tx_digitalreset Input Resets the digital TX portion of the transceiver PHY rx_analogreset Input Resets the analog RX portion of the transceiver PHY Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Data Interfaces 2 161 rx_digitalreset Input Resets the digital RX portion of the transceiver PHY usr_seq_reset Input Resets the sequencer Initiates a PCS reconfiguration and may
113. read modify write to bit 4 with a value of 1 b1 to offset OxA Table 6 16 PRBS Pattern Inversion Offsets Reconfiguration Address HEX Bit Encoding Bit 1 b0 Disables static polarity tx_static_ inversion 0x7 2 polarity_ i inversion 1 b1 Enables static polarity inversion 1 b0 Disables static polarity pe inversion OxA 4 polarity_ inversion 1 b1 Enables static polarity inversion Note Disable the inversion bit on the TX and RX to prevent normal data traffic from being inverted while entering or leaving the PCS Unsupported Features The following features are not supported by either the Transceiver Native PHY IP or the PLL IP reconfiguration interface Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration GJ Send Feedback UG A10XCVR 2013 12 02 Transceiver and PLL Address Map 6 21 Reconfiguration from bonded configuration to a non bonded configuration or vice versa Reconfiguration from bonded protocol to another bonded protocol Reconfiguration from PCIe with Hard IP to PCIe without Hard IP or non PCIE bonded protocol switching Switching between bonding schemes such as xN to FB compensation Connecting the Transceiver Native PHY IP to any other transceiver IP Master CGB reconfiguration Switching between two master CGBs Data rate switching by reconfiguring the CGB local divider Serialization factor changes on bonded channels TX PLL switching on bonde
114. releases the PCS reset Successful completion of this process is indicated by assertion of the pipe_phy_status signal by the ASN block Note In Native PHY IP PIPE configuration you must set pipe_rate 1 0 to initiate the transceiver datarate switch sequence Rate Switch This section provides an overview of auto rate change between PIPE Gen1 2 5 Gbps Gen2 2 5 Gbps and Gen3 8 0 Gbps mode The switches among Gen1 Gen2 and Gen3 rates involve reconfiguration of PMA and PCS settings PMA needs to re lock and provide a TX PLL clock and its CDR will also lock at a new incoming data rate PIPE interface clock rate is also adjusted to match the data throughput In Arria 10 devices there is only one common ASN block located in the PMA PCS interface handling all PIPE speed change Figure 2 73 Rate Switch Change The block level diagram below shows a high level connectivity between ASN and 8G PCS and Gen3 PCS Control Plane Bonding Up 8G PCS PCS PMA INF Gen3 PCS PMA Interface ii Gen3 ASN pipe_sw rate 1 0 gt Gent 2 3 from FPGA Fabric pipe_sw_done PHYSTATUS a GEN 4 I PHYSTATUS GEN Phase pipe_phy_status lt Comp lt q _ FIFO pll_fixed_clk lt Control Plane Bonding Down The sequence of speed change between Gen1 Gen2 and Gen3 occurs as follows 1 The PHY MAC layer implemented in FPGA Fabric reque
115. reset signals section for more information about his port 10GBASE R Parameters The 1OGBASE R parameters specify basic features of the 1OGBASE R PCS The FEC options also allow you to specify the FEC ability Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 112 10M 100M 1Gb Ethernet Parameters 2013 12 02 Table 2 86 10GBASE R Parameters a opten T Detorn Reference clock frequency 644 53125 MHz Specifies the input reference clock frequency The 322 265625 default is 322 265625MHz Enable additional control and On Off When you turn this option on the core includes status pins the rx_block_lock and rx_hi_ber ports Table 2 87 FEC Options A T oons Deaton Include FEC sublayer On Off When you turn this option on the core includes logic to implement FEC and a soft 10GBASE R PCS Set FEC_ability biton power On Off When you turn this option on the core sets the up and reset Assert KR FEC Ability bit 0xBO 16 FEC ability bit during power up and reset causing the core to advertise the FEC ability This option is required for FEC functionality Set FEC_Enab1e bit on power up On Off When you turn this option On the core sets the and reset KR FEC Request bit 0xBO 18 during power up and reset causing the core to request the FEC ability during Auto Negotiation This option is required for FEC functionality 10M 100M 1Gb Ethernet
116. restart AN LT or both if these modes are enabled Related Information e Input Reference Clock Sources on page 3 24 e PLLs on page 3 3 Data Interfaces The following table describes the signals in the XGMII GMII and MII interfaces The MAC drives the TX XGMII GMII and MII signals to the 1G 10GbE PHY The 1G 10GbE PHY drives the RX XGMII GMI or MII signals to the MAC Table 2 113 SGMII and GMII Signals 1G 10GbE XGMII Data Interface xgmii tx Input Synchronous to XGMII data and control for 8 lanes Each lane consists de Pils Oj we of 8 bits of data and 1 bit of control Cpa a_i CL xgmii_tx_clk Input Clock signal Clock for single data rate SDR XGMII TX interface to the MAC It should connect to xgmii_rx_clk This clock can be connected to the tx_div_ clkout however Altera recommends that you connect it to a PLI for use with the Triple Speed Ethernet MegaCore Function The frequency is 125 MHz for 1G and 156 25 MHz for 10G This clock is driven from the MAC The frequencies are the same if you enable 1588 or FEC xgmii_rx_ Output Synchronous to RX XGMII data and control for 8 lanes Each lane de Wis O consists of 8 bits of data and 1 bit of control Gm r elk xgmii_rx_clk Input Clock signal Clock for SDR XGMII RX interface to the MAC This clock can be connected to the tx_div_clkout however Altera recommends that you connect it to a PLI for use with the Triple Speed Ethernet MegaCore Functi
117. selected preset IP Core File Locations When you generate your Transceiver Native PHY IP the Quartus II software generates the HDL files that define your instance of the IP In addition the Quartus II software generates an example Tcl script to compile and simulate your design in the ModelSim simulator Figure 2 8 Directory Structure for Generated Files C lt project_dir gt lt instance_name gt v or vhd the parameterized transceiver PHY IP lt instance_name gt qip lists all files used in the transceiver PHY IP design lt instance_name gt bsf a block symbol file for you transceiver PHY IP lt project_dir gt lt instance_name gt includes PHY IP Verilog HDL and SystemVerilog design files for synthesis a lt instance_name gt _simlaltera_xcvr lt PHY_IP_name gt includes plain text files that describe all necessary files required for a successful simulation The plain text files contain the names of all required files and the correct order for reading these files into your simulation tool lt instance_name gt _simlaldec Simulation files for Riviera PRO simulation tools lt instance_name gt _simlcadence Simulation files for Cadence simulation tools lt instance_name gt _sim mentor Simulation files for Mentor simulation tools lt instance_name gt _simlsynopsys Simulation files for Synopsys simulation tools The following table describes the director
118. share the same input reference clock In xN bonding configurations one PLL is used for each bonded group Based on the number of channels in a bonded group there are speed limitations for xN bonding In PLL feedback compensation one PLL is used for each transceiver bank that the bonded group spans However there are no speed limitations in PLL feedback compensation bonding other than the natural speed limitations of the transceiver channel and the PLL For feedback compensation bonding the low speed parallel clock must be the same frequency as the reference clock for the PLL Using PLLs and Clock Networks In Arria 10 devices PLLs are not integrated in the Native PHY IP You must instantiated by the user through a separate PLL IP PLL merging is no longer performed by Quartus II software This gives you more control transparency and flexibility in the design process You can specify the channel configuration and PLL usage Related Information Clock Networks Non bonded configurations In a non bonded configuration only the high speed serial clock is routed from the transmitter PLL to the transmitter channel The low speed parallel clock is generated by the local clock generation block CGB present in the transceiver channel For non bonded configurations because the channels are not related to each other and the feedback path is local to the PLL the skew between channels cannot be calculated Also the skew introduced by the clock
119. source interface This clock frequency is 125 MHz in 1G mode and 257 81 in 10G Mode and 161 13 MHz with FEC enabled tx_pma_div_clkout Output This is the divided 33 clock from the TX serializer You can use this clock for the for xgmii_tx_clk or xgmii_rx_clk This clock frequency is 125 MHz for 1G and 156 25 MHz for 10G The frequencies are the same if you enable 1588 or FEC rx_pma_div_clkout Output This is the divided 33 clock from CDR recovered clock This clock frequency is 125 MHz for 1G and 156 25 MHz for 10G The frequencies are the same if you enable 1588 or FEC This clock is not used for clock the 10G RX datapath If PHY is reconfigured to 1G mode this clock frequency changes to 125 MHz Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 118 Data Interfaces 2013 12 02 D somaname recon Despi tx_analogreset Input Resets the analog TX portion of the transceiver PHY tx_digitalreset Input Resets the digital TX portion of the transceiver PHY rx_analogreset Input Resets the analog RX portion of the transceiver PHY rx_digitalreset Input Resets the digital RX portion of the transceiver PHY usr_seq_reset Input Resets the sequencer Initiates a PCS reconfiguration and may restart AN LT or both if these modes are enabled Related Information e Input Reference Clock Sources on page 3 24 e PLLs on page 3 3 Data Interfaces The f
120. square wave clock 7 sqwgen_clken sqwgen_clk_en 1 b1 Enable square wave clock prbs_15 3 b010 Enable PRBS15 in 64 bit mode prbs_23 3 b100 Enable PRBS23 in 64 bit mode 0x7 7 5 prbs_gen_pat 0x8 prbs_31 3 b000 Enable PRBS31 in 64 bit mode prbs_9 3 b001 Enable PRBS9 in 64 bit mode prbs_dis 3 b000 Disable PRBS in 64 bit mode sq_wave_1l 4 b0001 Enable square wave One L followed by one 0 sq_wave_4 4 b0100 Enable square wave Four 3 0 PW aye L followed by four 0 i num sq_wave_8 4 b1000 Enable square wave Eight 1 followed by eight 0 sq_wave_default 4 b0100 0x8 prbs_15 1 b0 Enable PRBS15 in 64 bit mode prbs_23 1 b0 Enable PRBS23 in 64 bit mode 4 prbs_gen_pat 0x7 prbs_31 1 b1 Enable PRBS31 in 64 bit mode prbs_9 1 b0 Enable PRBS9 in 64 bit mode prbs_dis 1 b0 Disable PRBS in 64 bit mode prbs_pat 2 b00 Enable PRBS generator 6 5 EPM 0x6 data_se sq_wave_pat 2 b00 Enable square wave generator q P q S sixty_four_bit 3 b011 64 bit mode 0x110 2 0 ser_mode ten_bit 3 b100 10 bit mode Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation GJ Send Feedback UG A10XCVR 6 16 Enabling the PRBS Data Checker 2013 12 02 Enabling the PRBS Data Checker You must perform a sequence of read modify writes to the Transceiver Native PHY reconfiguration interface to enable the PRBS checker You must perform read modify writes to offsets 0xA 0xB 0xC and 0x13F To enable the PRBS checker follow these steps 1 Perform a
121. stored in the CRC32 field of the diagnostic word CRC 32 provides a diagnostic tool for each lane This helps to trace the errors on the interface back to an individual lane The CRC 32 calculation covers most of the metaframe including the diagnostic word except the following e Bits 66 64 of each word e 58 bit scrambler state within the scrambler state word e 32 bit CRC 32 field within the diagnostic word Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback 5 18 64B 66B Encoder and Transmitter State Machine Figure 5 22 Interlaken CRC 32 Generator UG A10XCVR The Interlaken CRC 32 generator is available to implement the Interlaken protocol From the Interlaken Frame Generator lt __ Metaframe gt Interlaken CRC 32 Generator Sy SB SK Payload Di Sy SB SK 67 067 067 66 0 Total Data for CRC 32 Calculation gt 64B 66B Encoder and Transmitter State Machine The 64B 66B encoder is used to achieve DC balance and sufficient data transitions for clock recovery It encodes 64 bit XGMII data and 8 bit XGMII control into 1OGBASE R 66 bit control or data blocks in accordance with Clause 49 of the IEEE802 3 2008 specification 2013 12 02 Metaframes with Embedded a CRC 32 Code to Scrambler Di _ oF Sy SB SK Payload Sy SB SK 66 31 0 Total Data for CRC
122. switches from lock to reference to lock to data RX channel How Do Reset You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the PCS and PMA blocks You can save time by using the Altera provided Transceiver PHY Reset Controller IP core or you can implement your own reset controller that follows the recommended reset sequence You can design your own reset controller if you require individual control of each signal for reset or need additional control or status signals as part of the reset functionality Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 Recommended Reset Sequence 4 3 Recommended Reset Sequence Figure 4 2 Transmitter and Receiver Reset Sequence Transmit or Receive y FPGA Device Power Up Operation y Ensure Calibration Inactive y PLL TX RX Analog Reset Deasserted y Associated PLL CDR Locked y Release TX RX Digital Reset y TX RX Reset Completed Resetting the Transmitter After Device Power Up The FPGA automatically calibrates the PLL at every power up before entering user mode Perform a reset sequence after the device enters user mode Your User Coded Reset Controller must comply with the reset sequence below to ensure a reliable transmitter initialization after the initial power up calibration The following steps detail the t
123. that reads and writes to PHY registers Instantiate a reset controller using the Transceiver Reset Controller Megafunction in the MegaWizard Plug In Manager Connect the power and reset signals between the 1OGBASE KR PHY and the reset controller Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate Connect the high speed serial clock and PLL lock signals between 1OGBASE KR PHY and TX PLLs For the 1G data rate you can use either fPLL or ATX or CMU PLL For the 10G data rate you can use ATX PLL or CMU PLL Generate a fractional PLL to create the 156 25 MHz XGMII clock from the 10G reference clock Use the tx_pma_divclk from the l10GBASE KR PHY or generate a fPLL to create the 156 25 MHz XGMII clock from the 10G reference clock Unlike in the 1OGBASE KR PHY IP core for Stratix V devices no Memory Initialization Files mif are required for the 1OGBASE KR design in Arria 10 devices Complete the design by creating a top level module to connect all the IP 1OGBASE KR PHY IP PLL IP and Reset Controller blocks Related Information fPLL on page 3 11 CMU PLL on page 3 19 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR Pee 2013 12 02 Design Guidelines 2 147 e ATX PLL on page 3 3 e Using the Altera Transceiver PHY Reset Controller on page 4 8 e 10GBASE KR Functional Description on page 2 106 Design Guidelines Consider the following gu
124. the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL When Off the TX PLL reset control is disabled pll_powerdown duration 1 999999999 Specifies the duration of the PLL powerdown period in ns The value is rounded up to the nearest clock cycle The default value is 1000 ns Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 Transceiver PHY Reset Controller Parameters 4 11 a Synchronize reset input for PLL powerdown On Off When On the Transceiver PHY Reset Controller synchronizes the PLL powerdown reset with the Transceiver PHY Reset Controller input clock When Off the PLL powerdown reset is not synchronized TX Channel Enable TX channel reset control On Off When On the Transceiver PHY Reset Controller enables the control logic and associated status signals for TX reset When Off disables TX reset control and status signals Use separate TX reset per channel On Off When On each TX channel has a separate reset When Off the Transceiver PHY Reset Controller uses a shared TX reset controller for all channels TX digital reset mode Auto Manual Specifies the Transceiver PHY Reset Controller Expose Port behavior when the p11_locked signal is deasserted The following modes are available e Auto Theassociated tx_digital_reset controller automatically resets whenever the pll_locked signal is deasse
125. the addresses offset and bit values that must change to switch from one configuration to another Some features span multiple addresses in the configuration file Therefore enabling or disabling a single feature can result in multiple address reads and writes to the reconfiguration interface Step 3 Perform Read Modify Writes After programming the device with the base configuration you can reconfigure the transceiver with the modified configuration You must issue a read modify write to the reconfiguration interface for each address and bit difference between the base and modified Transceiver Native PHY or PLL Write both the address and bit differences to the reconfiguration interface Step 4 Reset Transceiver Channels After performing all read modify write operations you must implement the required reset sequence Refer to the required reset sequence to determine which blocks require reset Using Configuration Files You can save the parameters you specify for the Transceiver Native PHY and transmit PLL IP instances as configuration files The configuration files store offsets along with the data values required for a particular transceiver instance You can use the configuration files as part of dynamic reconfiguration flow Specify the file type of the configuration file on the Dynamic Reconfiguration tab of either the Transceiver Native PHY or transmit PLL parameter GUI Select one or more of System Verilog package file C header f
126. this to drive core logic to drive the RX PCS to fabric interface or both If you specify a rx_pma_div_clkout division factor of 1 or 2 this clock output is derived from the PMA parallel clock If you specify arx_pma_div_clkout division factor of 33 40 or 66 this clock is derived from the PMA serial clock This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock frequency such as 66 40 applications rx_pma_div_ Disabled 1 2 33 40 Specifies the division factor for the rx_pma_div_clkout clkout division 66 output clock when this port is enabled factor Enable rx_pma_ On Off Specifies the division factor for the rx_pma_div_clkout clock div_clkout signal This parameter is disabled when you turn Off the Enable division factor rx_pma_div_clkout port Enable rx_pma_ On Off Enables the optional rx_pma_clkslip control input port A clkslip port rising edge on this signal causes the RX serializer to slip the serial data by one clock cycle or 2 unit intervals UI Enable rx_pma_ On Off Enables the rx_pma_qpipulldn control input port Use this qpipulldn port port only for QPI applications QPI Enable rx_is_ On Off Enables the optional rx_is_lockedtodata status output lockedtodata port port This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream This is an as
127. to rx_ Clause 37 Auto negotiation status The PCS function elkout asserts this signal when auto negotiation completes rx_block_lock Output Synchronous to rx_ Asserted to indicate that the block synchronizer has clkout established synchronization rx_hi_ber Output Synchronous to rx_ Asserted by the BER monitor block to indicate a Sync clkout Header high bit error rate greater than 10 8 8 rx_is_ Output Asynchronous signal When asserted indicates the RX channel is locked to lockedtodata input data tx_cal_busy Output Synchronous to When asserted indicates that the TX channel is being mgmt_clk calibrated Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2013 12 02 2 166 Dynamic Reconfiguration Interface rx_cal_busy Output Synchronous to When asserted indicates that the RX channel is being mgmt_clk calibrated calc_clk_lg Input Clock signal This clock is used to calculate the latency of the soft 1G PCS block This clock is only required for when you enable 1588 in 1G mode Its frequency is 80 MHz This clock should have the same PPM as the p11_ ref_clk_lginput rx_sync_ Output Synchronous to rx_ When asserted indicates the word aligner has aligned status clkout to in incoming word alignment pattern tx petito Output Synchronous to tx_ When asserted indicates that the Standard PCS TX error ilg elkout
128. transceiver and clock signals from the transceiver into the FPGA fabric These clock signals use the global GCLK regional RCLK and periphery PCLK clock networks in the FPGA core The transmitter channel forwards a parallel output clock tx_clkout to the FPGA fabric to clock the transmitter data and control signals The receiver channel forwards a parallel output clock to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric Based on the receiver channel configuration the parallel output clock is recovered from either the receiver serial data or therx_clkout clock in configurations without the rate matcher or the tx_clkout clock in configu rations with the rate matcher The divided versions of the tx_clkout and rx_clkout are available as tx_pma_div_clkout and rx_pma_div_clkout respectively The output frequency of tx_pma_div_clkout and rx_pma_div_clkout canbe one of the following e A divided down version of the tx_clkout or rx_clkout respective where divide by 1 and divide by 2 ratios are available e A divided down version of the serializer clock where divide by 33 40 and 66 ratios are available The tx_pma_div_clkout and rx_pma_div_clkout can be used as tx_coreclkin or rx_coreclkin and provide additional flexibility These clocks can be used to meet core timing by operating the TX and RX FIFO in double width mode as this halves the required clock frequency at the PCS to FPGA interfa
129. used in the PFD s feedback path The output of the L counter is connected to the M counter The combined division ratios of the L counter and the M counter determine the overall division factor in the PFD s feedback path The division factors supported are 8 9 10 12 15 16 18 20 24 25 30 32 36 40 48 50 60 64 72 80 96 100 120 128 160 and 200 Lock Detector LD The lock detector indicates when the CMU PLL is locked to the desired output s phase and frequency The lock detector XORs the Up Down pulses and indicates when the M counter s output and N counter s output are phase aligned The reference clock refclk and feedback clock fbc1k are sent to the PCS ppm detector block There is a pre divider to lower the frequency in case the frequency is too high Instantiating CMU PLL IP The CMU PLL IP for Arria 10 transceivers provides access to the CMU PLLs in hardware One instance of the PLL IP represents one CMU PLL in hardware Open the Quartus II software Select the Arria 10 device family A aE No design and enter a filename Click Next Click Tools gt MegaWizard Plug In Manager Select PLL in the Installed Plug Ins tree Choose Arria 10 Transceiver CMU PLL In What name do you want for the output file browse to the location where you want to save your The CMU PLL IP MegaWizard Plug In Manager window opens CMU PLL IP The CMU PLL configuration options and parameters are listed in the fo
130. you must route any signal that you want to observe to the top level of your design 5 To monitor additional signals highlight the desired instances or nodes in Instance and right click Add wave 6 Select Simulate and then Run Specify the simulation duration 8 Complete the following steps to restart the simulation N a On the ModelSim Altera Simulate menu select restart then click ok Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Use NativeLink to Specify Third Party RTL Simulators 2 259 This action clears the existing waves b Highlight run and select the appropriate options to run the simulation Related Information Simulating the Transceiver Native PHY IP Core on page 2 256 How to Use NativeLink to Specify Third Party RTL Simulators The following figure illustrates the high level steps for NativeLink with Third Party EDA RTL Simulations Figure 2 135 Using NativeLink with Third Party Simulators Specify EDA Simulator amp Simulator Directory _ y Perform Functional Simulation Simulation Give Expected Results No gt Debug Design amp Make RTL Changes y Run Quartus II Analysis and Elaboration y Start Simulator Compile Design and Testbench y Load Design amp Run Simulation Simulation Give Expected Results Simulation Complete Comp
131. you want to create Which megafunction would you like to customize Select a megafunction from the list below Q x C AHDL Gates Fy H Gyo C VHDL J Interfaces Verilog HDL ASI Ma CPRI What name do you want for the output file DisplayPort data nikshah Demo1 TransceiverPHY a J Ethernet 1OGBASE R PHY v13 1 1G 10GbE and 10GBASE KR PHY v13 1 4 Arria 10 1G 10GbE and 10GBASE KR PHY v13 1 Ethernet 10G MAC v13 1 A Low Latency Ethernet 10G MAC v13 1 A Triple Speed Ethernet v13 1 XAUI PHY v13 1 J External Memory I Return to this page for another create operation Note To compile a project successfully in the Quartus II software your design files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu or a library specified in the Libraries page of the Settings dialog box Assignments menu Your current user library directories are J Interlaken G PCI J PCI Express 3 Rapidio SDI J SerialLite Transceiver PHY A Arria 10 Transceiver Native PHY v13 1 Arria V GZ Transceiver Native PHY v13 1 Arria V GZ Transceiver PLL v13 1 Ban i a z HOH A T Cancel lt Back Next gt Finish Related Information Arria 10 Transceiver Protocols and PHY IP Support on page 2 7 Configure the PHY IP Configure the PHY IP by selecting the valid parameters for your design The valid parameter settings are different f
132. 0 pll refelks Represents logical refclk3 0x116 7 0 pll_refclk4 Represents logical refc1k4 0x117 7 0 N A ATX Refclk selection MUX 0x112 7 0 Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 fPLL Reference Clock Switching 6 11 When performing a reference clock switch you must specify the logical reference clock and respective offset and bits of the replacement clock After determining the ATX PLL follow this procedure to switch to the selected reference clock 1 Read from the logical reference clock offset and save the required 8 bit pattern For example switching to logical re fc1k2 requires use of bits 7 0 of offset 0x115 2 Perform a read modify write to bits 7 0 of offset 0x112 using the 8 bit value obtained from the logical refclk offset 3 Complete the required reset sequence fPLL Reference Clock Switching You can use the reconfiguration interface on the fPLL instance to specify which reference clock source drives the fPLL The fPLL supports clocking by up to five different reference clock sources Independent of the number of transmitter PLLs specified the flow to select between the different reference clock sources remain the same Before initiating a reference clock switch ensure that your f PLL instance defines more than one reference clock source Specify the Number of PLL reference clocks parameter on the PLL tab during fPLL parameterizatio
133. 0 Transceiver Native PHY tx_cal busy lt 1 Nios Hard Reconfiguration 4 ei et rx_cal_busy Calibration IP Registers bE eon lt reconfig_avmm TX PMA TX Enhanced PCS Serial Data lt Clocks lt gt TX Parallel Data Control Clocks QPI lt ial Optional Ports lt Serializer j gt lt gt Enhanced PCS TX FIFO lt Interlaken Frame Generator A tx_serial_clk0 Clock from TX PLL Generation tx_analog_reset Block rx_analog_reset RX PMA l RX Enhanced PCS y Serial Data _ lt RX Parallel Data Control Clocks Optional Ports lt gt Enhanced PCS RX FIFO ializer gt CDR it CPR Deserializer lt Interlaken Frame Synchronizer Clocks lt gt 10GBASE R BER Checker PRBS A lt _ Bitslip Bitslip lt gt In the following tables the variables represent these parameters e lt n gt The number of lanes e lt d gt The serialization factor e lt s gt The symbol size e lt p gt The number of PLLs Table 2 32 Enhanced TX PCS Parallel Data Control and Clocks tx_paralle Input tx_ TX parallel data inputs from the FPGA fabric to the data lt n gt 12 1 0 coreclkin TX PCS If you select Enable simplified interface in the Transceiver Native PHY IP GUI tx_parallel_
134. 0XCVR 2013 12 02 me e T Petan Specifies the Transceiver PHY Reset Controller behavior when the PLL lock signal is deasserted The following modes are available Auto The associated rx_digital_reset controller automatically resets whenever the rx_is_lockedtodata signalis deasserted Manual The associated rx_digital_ reset controller is not reset when the rx_ is_lockedtodata signal is deasserted allowing you to choose corrective action Expose Port The rx_manua signal is a top level signal of the IP Core If the core includes separate reset control for each RX channel each RX channel uses its respective rx_is_ lockedtodata signal for automatic reset control otherwise the inputs are ANDed to provide internal status for the shared reset controller rx_analogreset duration 1 99999 8989 Specifies the time in ns to continue to assert the rx_analogreset after the reset input and all other gating conditions are removed The value is rounded up to the nearest clock cycle The default value is 40 ns rx_digitalreset duration 1 99999999 9 Transceiver PHY Reset Controller Interfaces This section describes the top level signals for the Transceiver PHY Reset Controller IP core The following figure illustrates the top level signals of the Transceiver PHY Reset Controller IP core Many Specifies the time in ns to continue to assert the rx_digitalreset after the reset input and all other gating conditions are remov
135. 0x0E0 7 0 15 8 e 0x0E0 7 0 23 16 e 0x0E0 7 0 31 24 Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Related Information Hard Transceiver PHY Registers 2 171 Reconfiguration Interface and Dynamic Reconfiguration on page 6 1 Hard Transceiver PHY Registers Table 2 120 Hard Transceiver PHY Registers PE A Taes name T Peton All registers in the PCS and PMA that you can dynamically reconfigure are in this address space Refer to reconfiguration chapter for further information RW Access to HSSI registers 0x000 0x3FF 9 0 Enhanced PCS Registers These registers provide Enhanced PCS status information Table 2 121 PCS Registers A 0x480 31 0 Indirect_addr Because the PHY implements a single channel this register must remain at the default value of 0 to specify logical channel 0 2 RW RCLR_ERRBLK_CNT Error Block Counter clear register When set to 1 clears the RCLR_ERRBLK_CNT register When set to 0 normal operation continues 0x481 3 RW RCLR_BER_COUNT BER Counter clear register When set to 1 clears the RCLR_ BER_COUNT register When set to 0 normal operation continues 1 RO HI_BER High BER status When set to 1 the PCS is reporting a high BER When set to 0 the PCS is not reporting a high BER 2 RO BLOCK_LOCK Block lock status When set to 1 the PCS is locked to received blocks When set to 0 t
136. 1 13 Arria 10 SX Device with Six Transceiver Channels and One Hard IP Block ti a Transceiver Note PCle Hard IP Transceiver 1 These devices have transceivers only on the left side of the device Legend PCle Geni Gen3 HIP blocks with CvP capabilities E Arria 10 SX device with 6 transceiver channels and 1 PCle Hard IP block Arria 10 SX Device Package Details The following tables list package sizes available transceiver channels and PCI Express Hard IP blocks for Arria 10 SX devices Altera Corporation Arria 10 Transceiver PHY Overview GJ Send Feedback UG A10XCVR f mpre 2013 12 02 Transceiver PHY Architecture Overview Table 1 5 Package Details for SX Devices with Transceivers and HIP Blocks Located on the Left Side Periphery of the Device Fer RS ee ee GRE E Transceiver Transceiver Transceiver Transceiver Transceiver Transceiver Transceiver Count PCle Count PCle Count PCle Count PCle Count PCle Count PCle Count PCle Hard IP Hard IP Hard IP Hard IP Hard IP Hard IP Hard IP Block Block Count Block Count Block Count Block Count Block Count Block Count Count SX 016 6 1 12 1 12 1 SX 022 6 1 12 1 12 1 SX 027 12 1 12 1 24 2 24 2 SX 032 12 1 12 1 24 2 24 2 SX 048 12 1 24 2 36 2 SX 057 24 2 36 2 36 2 48 2 SX 066 24 2 36 2 36 2 48 2
137. 10 Gbps ATX PLL x cop 4 s Legend m TX channels placed in the same transceiver bank a TX channels placed in the adjacent transceiver bank Bonded configurations In a bonded configuration both the high speed serial and low speed parallel clocks are routed from the transmitter PLL to the transmitter channel In this case the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network In bonded configurations the transceiver clock skew between the channels is minimum Bonded configura tions are used for channel bonding in protocols such as PCIe and XAUI There are two methods for channel bonding in Arria 10 devices e x6 xN bonding e PLL feedback compensation Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 x6 xN Bonding Mode 3 45 x6 xN Bonding Mode In x6 xN bonding mode the same PLL drives multiple channels spanning more than one transceiver bank The steps below explain the x6 xN bonding process 1 5 The ATX PLL or the fPLL generates a high speed serial clock 2 The PLL drives the high speed serial clock to the Master CGB via the x1 clock network 3 4 The x6 clock network feeds the TX clock mux for the transceiver channels within the same transceiver The Master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network ban
138. 10 Transceivers CJ Send Feedback High order 5 bits of the 21 bit auto negotiation link timer Altera Corporation 2 146 Creating a 10GBASE KR Design UG A10XCVR 2013 12 02 Ee 0x4A4 Determines the PCS function operating mode Setting this bit to 1b l enables SGMII mode Setting this bit to 1b 0 enables 1000BASE X gigabit mode 1 RW USE_SGMII_AN In SGMII mode setting this bit to 1b l causes the PCS to be configured with the link partner abilities advertised during auto negotiation If this bit is set to 1b 0 the PCS function should be configured with the SGMII_SPEED and SGMII_DUPLEX bits 3 2 RW SGMII_SPEED SGMII speed When the PCS operates in SGMII mode SGMII_ENA 1 and is not programmed for automatic configuration USE_SGMII_AN 0 the following encodings specify the speed e 2 b00 10 Mbps e 2 b01 100 Mbps e 2 b10 Gigabit e 2 b11 Reserved These bits are not used when SGMII_ENA Oor USE_SGMII_AN 1 Creating a 10GBASE KR Design Here are the steps you must take to create a 1OGBASE KR design using the Backplane Ethernet PHY IP 1 Generate the 1OGBASE KR PHY with the required parameterization Unlike in the 1OGBASE KR PHY IP Core for Stratix V devices for Arria 10 devices the Reconfiguration Block is included 1OGBASE KR PHY This Reconfiguration Block provides the Avalon MM master
139. 10 bit data is 1111100000 the polarity inversion feature inverts it to 0000011111 Rate Match FIFO The rate match FIFO compensates for the frequency differences between the local clock and the recovered clock up to 300 ppm by inserting and deleting skip idle characters in the data stream The rate match FIFO has several different protocol specific modes of operation All of the protocol specific modes depend upon the following parameters e Rate match deletion occurs when the distance between the write and read pointers exceeds a certain value due to write clock having a higher frequency than the read clock e Rate match insertion occurs when the distance between the write and the read pointers becomes less than a certain value due to the read clock having a higher frequency than the write clock e Rate match full occurs when the write pointer wraps around and catches up to the slower advancing read pointer e Rate match empty occurs when the read pointer catches up to the slower advancing write pointer Rate match FIFO operates in six modes e Basic single width e Basic double width e GigE e PIPE e PIPEO ppm e PCIe Related Information Howto Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver Native PHY IP Core For more information about implementing rate match FIFO for each mode e Rate Match FIFO in Basic Single Width Mode on page 2 238 For more information about implementing rate match FIF
140. 10GBASE R with KR FEC Transmitter PMA Transmitter Enhanced PCS FPGA Fabric TX a 5 n Data amp 5 R 64 5 8 A a g a Control s4 ee Hay veh 2 a 8 n cs 2 E 64 8 a 3 mi A 3 156 25 MH tx hf cik mia Fe B lito xen 15625 mHz 2 L e tx pma cik tx krfee clk ie E Saak ee tx_clkout bs os 28 5 i US he TEM Eg Me 2a gx eB jeu E H DAOC LOR eT ERLE ET BECS tx_pma_div_cikout gt Receiver PMA Receiver Enhanced PCS rx_pma_div_clkout gt g m RX E m 5 3 m Data amp g E amp 64 2 xi a A ae 9 g Control 3 tape Bett F PEIDA J fe gt Z a Fj 8 lt f Ss lt lt E 64 8 S a A F 156 25 MHz PRP m i rx_Tevd_clk Verter eA L 5 from XGMII l m pma ck ee a a ee e a Pepo 3 J l I i R 10GBASE R g 5 _ x v BER Checker iL gal eel esl os las Py PL S pls hme jH a S es jeg jes Jed a x E Clock Generation Block CGB ES 2 p 4 gt Data rate 2 ATX PLL Clock Divider lt PLL L fg CMU PLL _t Parallel Clock Soek Parallel and Serial Clocks eS h Parallel and Serial Clocks Input Reference Clock Notes 1 Value is based on the clock division factor chosen 2 Value is calculated as data rate FPGA fabric PCS interface width 3 Value is calculated as data rate PCS PMA interface width 4 For 1OGBASE R with KR FEC TX FIFO is in phase compensation mode 5 For 1OGBASE R with KR FEC RX FIFO is in 10GBASE R mode The CMU PLL or the ATX PLLs generate the TX high speed serial clock
141. 12 02 XN Clock Lines 3 29 Figure 3 8 x6 Clock Lines x6 Network Master CGB Master CGB XN Clock Lines The xN clock lines route the transceiver clocks across multiple transceiver banks The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock lines There are two xN clock lines xN Up and xN Down xN Up clock lines route the clocks to transceiver banks located above the master CGB and xN Down clock lines route the clocks to transceiver banks located below the master CGB The xN clock lines can be used in both bonded and non bonded configurations For bonded configurations the low speed parallel clock output of the master CGB is used and the local CGB within each channel is bypassed For non bonded configurations the master CGB provides a high speed serial clock output to each channel PLLs and Clock Networks Altera Corporation CJ Send Feedback 3 30 XN Clock Lines Figure 3 9 xN Clock Network x6 Bottom Ch5 Master CGB1 Ch3 Master CGBO Chi Cho UG A10XCVR 2013 12 02 The maxi
142. 12 5 Gbps Interlaken with a bonded group of 10 channels e Set the Interlaken 10x12 5 Gbps preset from the Arria 10 Transceiver Native PHY IP GUI e Refer to Interlaken on page 2 62 for more details Custom multi data rate 1 25G 9 8G 10 3125 Gbps non bonded group of four channels e Set the Number of data channels to 4 e Set TX channel bonding to Not Bonded e Under the TX PMA tab set the Number of TX PLL clock inputs per channel to 3 e Under the RX PMA tab set the Number of CDR reference clocks to 3 1 25 Gbps Gigabit Ethernet with a non bonded group of two channels e Set the GIGE 1 25Gbps preset from the Arria 10 Transceiver Native PHY IP GUI e Change the Number of data channels to 2 PCIe Gen3 with a bonded group of 8 channels e Set the PCIe PIPE Gen3x8 preset from the Arria 10 Transceiver Native PHY IP GUI e Under TX Bonding options set the PCS TX channel bonding master to channel 5 Note The PCS TX channel bonding master must be physically placed in channel 1 or channel 4 within a transceiver bank In this example the 5th channel of the bonded group is physically placed at channel 1 in the transceiver bank e Refer to PCI Express on page 2 179 for more details 10 3125 Gbps 1OGBASE KR non bonded group of 4 channels e Instantiate the Arria 10 1G 10GbE and 10GBASE KR PHY IP four times with one instance for each channel e Refer to 1OGBASE KR PHY IP with FEC Option on page 2 103 for more details PLLs and Clock Networks A
143. 124 Daisy Chain Interface Signals UG A10XCVR 2013 12 02 rx_data_ready Output Synchronous to rx_ When asserted indicates that the MAC can begin Daisy Chain Interface Signals clkout sending data to the PHY The optional daisy chain interface signals connect link partners using a daisy chain topology Table 2 97 Daisy Chain Interface Signals dmi_mode_en Input When asserted enable Daisy Chain mode dmi_frame_lock Input When asserted the daisy chain state machine has locked to the training frames dmi_rmt_rx_ready Input Corresponds to bit 15 of Status report field When asserted the remote receiver cmi lel coefliSs0 Input Local update low bits 5 0 In daisy chained configu rations the local update coefficients substitute for the coefficients that would be set using Link Training dmi_lcl_coefh 1 0 Input Local update high bits 13 12 In daisy chained configurations the local update coefficients substitute for the coefficients that would be set using Link Training dmi_lcl_upd_new Input When asserted indicates a local update has occurred dmi_rx_trained Input When asserted indicates that the state machine has finished local training dmo_frame_lock Output When asserted indicates that the state machine has locked to the training frames dmo_rmt_rx_ready Output Corresponds to the link partner s remote receiver ready bit emo lel coctl 5 0 Output Local update low bits 5 0
144. 15 0 RO LP base page low The AN RX state machine received these bits from the link partner The following bits are defined e 15 Next page bit e 14 ACK which is controlled by the state machine e 13 RF bit e 12 10 Pause bits e 9 5 Echoed Nonce which are set by the state machine e 4 0 Selector Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY Register Definitions 2 133 Word R W Description Addr 0x4C8 31 0 LP base page high The AN RX state machine received these bits from the link partner The following bits are defined e 31 30 Reserved e 29 5 Correspond to page bits 45 21 which are the technology ability e 4 0 Correspond to bits 20 16 which are TX Nonce bits 0x4C9 15 0 RO LP Next page low The AN RX state machine receives these bits from the link partner The following bits are defined e 15 Next page bit e 14 ACK which is controlled by the state machine 13 MP bit e 12 ACK2 bit e 11 Toggle bit For more information refer to Clause 73 7 7 1 Next Page encodings of IEEE 802 3ap 2007 Ox4CA 31 0 RO LP Next page high The AN RX state machine receives these bits from the link partner Bits 31 0 correspond to page bits 47 16 24 0 0x4CB RO AN LP ADV Tech_A 24 0 Received technology ability field bits of Clause 73 Auto Neg
145. 2 194 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode 2013 12 02 Figure 2 80 Use ATX PLL or fPLL for Gen1 Gen2 Gen3 x1 Mode Altera Corporation X1 Network 6 ch5 opoo gt CGB fPLL1 P CDR ATX PLLL p 6 ch4 eeceee gt CGB 4 CDR Master 4 lt 4 CGB1 7 oeoo oet p CGB p sg 4 L CDR Ch2 CGB p J fPLLO CDR Chi ccBl_p gt ATX PLLO CDR a Cho CGB p CDR Notes ORWNE The figure shown is just one possible combination for the PCle Gen1 Gen2 Gen3 x1 mode Gent Gen2 mode use the fPLL ONLY Gen3 mode uses the ATX PLL ONLY Use the pll_pcie_clk from the fPLL configured as Gen1 Gen2 This is the hclk required by the PIPE interface Select the number of TX PLLs 2 in the Native PHY wizard Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Connections Done fPLL1 ATX PLL1 Notes OonrWNnNr Master CGB Implementing Protocols in Arria 10 Transceivers GJ Send Feedback How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode XN Network va va Figure 2 81 Use ATX PLL o
146. 2 20 KR FEC Parameters Enable RX KF On Off When you turn this option on the decoder asserts both sync bits REC error 2 b11 when it detects an uncorrectable error This feature marking increases the latency through the KR FEC decoder Enable tx_enh_ On Off Enables the tx_enh_frame port frame port Enable rx_enh__ On Off Enables the rx_enh_frame port frame port Enable rx_enh_ On Off Eables the rx_enh_frame_diag_status port frame_diag_ status port Related Information e Arria 10 Enhanced PCS Architecture on page 5 14 e Using the Basic and Basic with KR FEC Configurations of Enhanced PCS on page 2 225 e Interlaken on page 2 62 e 10GBASE R and 10GBASE R 1588 e 10GBASE KR PHY IP with FEC Option on page 2 103 e Enhanced PCS and PMA Ports on page 2 37 Standard PCS Parameters This section provides descriptions of the parameters that you can specify to customize the Standard PCS The Standard PCS provides Transceiver configuration rules for the following supported protocols e Basic e Basic with Rate Match e CPRI e GbE e GbE 1588 For specific information about configuring the Standard PCS for these protocols refer to the sections of this user guide that describe support for these protocols Table 2 21 Standard PCS Parameters Note For detailed descriptions of the optional ports that you can enable or disable refer to the Standard PCS and PMA Ports on page 2 52 Standard PCS 8 10 16 20 Spec
147. 2 49 OS Word Deletion This figure shows the deletion of Ordered set word in the receiver data stream Before Deletion AAAAAAAAAAAAAAAAh rx_parallel data FD000000000004AEh X DDDDDD9CDDDDDD9Ch K 00000000000000FBh After Deletion 00000000AAAAAAAAh rx_parallel_data lt FD000000000004AEh lt 000000FBDDDDDDICh RAAAAAAA00000000h sume OS Deleted 10GBASE KR PHY IP with FEC Option The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates The 1G 10GbE and 10GBASE KR PHY IP Core enables Ethernet connectivity at 1 Gbps and 10 Gbps over backplanes The 1OGBASE KR PHY IP is also known as the Backplane Ethernet PHY IP It includes link training and auto negotiation to support the IEEE Backplane Ethernet standard Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 104 10GBASE KR PHY IP with FEC Option a The 10GBASE KR Ethernet PHY IP MegaCore function supports the following features of Ethernet standards e 10GBASE KR Ethernet protocol with link training as defined in Clause 72 of the IEEE 802 3 2008 Standard In addition to the link partner TX tuning as defined in Clause 72 this PHY also automatically configures the local device RX interface for the lowest bit error rate BER e Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802 3 2008 Standard The 10GBASE KR Ethernet PHY MegaCore F
148. 2 Pal _ Phase Down Detector Up rx_serial_data a gt PD F Charge Pump hie d L amp H ontrol e Divider e al i Oscillator zi Loop Filter 1 7 Up VCO refclk gt Divider gt _ Phase 1 Frequency Detector Down Lock f PFD a Detect rx_is_lockedtoref M Divider 9 D Note 1 The Quartus II software automatically chooses the optimal values Lock to Reference Mode In LTR mode the phase frequency detector PFD in the CDR tracks the receiver input reference clock The PFD controls the charge pump that tunes the VCO in the CDR The rx_is_lockedtoref status signal is asserted active high to indicate that the CDR has locked to the phase and frequency of the receiver input reference clock Note The phase detector PD is inactive in LTR mode Lock to Data Mode During normal operation the CDR must be in LTD mode to recover the clock from the incoming serial data In LTD mode the PD in the CDR tracks the incoming serial data at the receiver input Depending on the phase difference between the incoming data and the CDR output clock the PD controls the CDR charge pump that tunes the VCO Note The PFD is inactive in LTD mode The rx_is_lockedtoref status signal toggles randomly and is not significant in LTD mode After switching to LTD mode the rx_is_lockedtodata status signal is asserted The actual lock time depends on the transition density of the incoming data and the parts per million ppm difference
149. 2 b10 511 Oxb 7 5 prbs_ver OxC prbs_15 3 b010 Enable PRBS15 in 64 bit mode prbs_23 3 b100 Enable PRBS23 in 64 bit mode prbs_31 3 b000 Enable PRBS31 in 64 bit mode prbs_9 prbs_off 3 b001 3 b000 Enable PRBS9 in 64 bit mode Disable PRBS in 64 bit mode Reconfiguration Interface and Dynamic Reconfiguration GJ Send Feedback Altera Corporation UG A10XCVR 6 1 Enabling Pseudo Random Pattern Test Mode 2013 12 02 Reconfiguration Reconfiguration Attribute Other Offsets Attribute Bit Encoding Description Address HEX Bit Name Encoding prbs_15 Enable PRBS15in 64 bit mode prbs_23 1 b0 Enable PRBS23 in 64 bit mode prbs_31 1 b1 Enable PRBS31 in 64 bit mode prbs_9 1 b0 Enable PRBS9 in 64 bit mode 0 prbs_ver 0xB OxC prbs_off 1 b0 Disable PRBS in 64 bit mode force_sig_ok 1 b1 unforce_sig_ok 1 b0 2 rx_signalok_ signaldet_sel sel_sig_ok 1 b1 prbs9_10b 1 b1 PRBS9 10 bit prbs9_64b 1 b0 PRBS9 64 bit 10 4 b0001 10 bit mode 64 4 b1110 64 bit mode prbs9_ dwidth 3 deser_factor Enabling Pseudo Random Pattern Test Mode Pseudo Random Pattern is a test mode of the scrambler You can select two seeds of the Pseudo Random Pattern The seed produces the pattern in the scrambler and the r_tx_data_pat_seljisthe data pattern
150. 2 support Related Information e Arria 10 Hard IP for PCI Express User Guide e Intel PHY Interface for the PCI Express PIPE Architecture PCI Express 2 0 e Intel PHY Interface for the PCI Express PIPE Architecture PCI Express 3 0 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Transceiver Channel Datapath for PIPE Figure 2 66 Transceiver Channel Datapath for PCle Gen1 Gen2 Configuration with Gen3 Disabled Transceiver Channel Datapath for PIPE 2 181 The following figure shows the Arria 10 transmitter and receiver channel datapath for PIPE Genl Gen2 configurations when using PIPE configuration with Gen3 disabled In this configuration the transceiver connects to a PIPE interface Transmitter PMA Transmitter Standard PCS FPGA Fabric a g 3 2o 2 a D D a 8 S g 2 Receiver PMA Receiver Standard PCS eseyaql adid di prey ssaidxq 19d vep euas xy Jezijeuasaq aug 4apooaq 401 88 vr i aao Jazijeuasag Jaubly plo Old ye IPY oe Figure 2 67 Transceiver Channel Datapath for PCle Gen1 Gen2 Gen3 Configurations The following figure shows the Arria 10 transmitter and receiver channel datapath for PCIe Gen1 Gen2 Gen3 configurations with a 32 bit PIPE 3 0 based
151. 24000000 EY 2a hittttt tx_parallel_data 1536 h0123456789abcdef01234567 1536 h0123456789abcdef01234567 G 1536 h0123456789abcdef01234567 1 OOOO 1536 baat tx_control 72 h249249249249249249 72 h249249249249249249 72 h249249249249249249 tx_enh_fifo_empty 24 hfffff 24 h000000 24000000 G 24n000000 tx_enh_fifo_pempty 24 hfffff 24h000000 24000000 24000000 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 74 Design Example Figure 2 24 24 Lanes Bonded Interlaken Link RX Direction UG A10XCVR 2013 12 02 To show more details three different time segments are shown with different zoom level Some Lanes pfull Signal Is Asserted All Lanes pfull Low and All Altera Corporation rx_ready before All Lanes pempty is Deasserted Lanes pempty Deasserted Asserted RX Deskew Fails Need to Realign RX Deskew Complete 0 I OOOO LI rx_digitalreset 24 hffff 2100 24 h000000 pa h000000__ rx_ready 24 h000000 2s nti h 24 httftt 3 Spa ttt rx_enh_blk_lock 24h000000 2a nett Qa hitit rx_enh_frame_lock 24 ho00000 24ho 24 h000001 Qo ittttt rx_enh_fifo_pfullf0 S rx_enh_fifo_pfull 241000000 247000000 24 h000000 24004 24 hoo0000 rx_enh _fifo_pempty _24 nfttff QO oa hitttit 2s hfffffe 2a niitit Sentit J24 noooo00 2a
152. 29 Dynamic Reconfiguration Enable dynamic On Off When you turn this option on the dynamic reconfiguration reconfiguration interface is enabled Share reconfigura On Off When you turn this option on the Transceiver Native PHY IP tion interface presents a single Avalon MM slave interface for dynamic reconfiguration for all channels In this configuration the upper 1 10 address bits of the reconfiguration address bus specify the channel The channel numbers are binary encoded Address bits 9 0 provide the register offset address within the reconfiguration space for a channel Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 36 Dynamic Reconfiguration Parameters 2013 12 02 Enable embedded On Off When you turn this option on the Transceiver Native PHY IP JTAG Avalon includes an embedded JTAG Avalon MM master that connects MM master to the Avalon MM slave interface for dynamic reconfiguration The JTAG Avalon MM master can access the reconfiguration space of the transceiver It can perform certain test and debug functions via JTAG using the System Console This option requires you to enable the Share reconfiguration interface option Table 2 30 Configuration Files Configuration lt prefix gt When you turn this option on it specifies the file prefix to use for file prefix generated configuration files Each variant of the Transceiver Native P
153. 5 control pattern in the LSByte and K28 0 skip pattern in the MSByte of a clock cycle followed by one K28 0 skip pattern in the LSByte of the next clock cycle The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle The second skip cluster has a K28 5 control pattern in the MSByte of a clock cycle followed by two pairs of K28 0 skip patterns in the next two cycles The rate match FIFO deletes both pairs of K28 0 skip patterns for a total of four skip patterns deleted from the second skip cluster to meet the three skip pattern deletion requirement The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running The 10 bit skip pattern can appear on the MSByte the LSByte or both of the 20 bit word 2 119 Rate Match FIFO Deletion with Four Skip Patterns Required for Insertion First Skip Cluster Second Skip Cluster K28 0 Dx y 1 K28 5 i K28 0 X K28 0 K28 5 _data 19 10 1 Dx y llel_data 9 0 X Dx y data 19 0 l Dxy K28 0 K28 0 I K28 0 X K28 0 X K28 0 K28 5 lt lt lt ee w f e T ee ee lel_data 9 0 y Dxy In this example K28 5 is the control pattern and neutral disparity K28 0 is the skip pattern The first skip cluster has a K28 5 control pattern in the LSByte and K28 0 skip pattern in the MSByte of a clock cycle follo
154. 802 3ap 2007 1 AN base pages When setto 1 the user base pages are enabled You can send ctrl any arbitrary data via the user base page low high bits When set to 0 the user base pages are disabled and the state machine 0x4C0 generates the base pages to send 2 RW AN next pages When setto 1 the user next pages are enabled You can send eter any arbitrary data via the user next page low high bits When set to 0 the user next pages are disabled The state machine generates the null message to send as next pages 3 R Local device When set to 1 the local device signals Remote Faults in the remote fault Auto Negotiation pages When set to 0 a fault has not occurred Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 130 10GBASE KR PHY Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr Reset AN When set to 1 resets all the 10GBASE KR Auto Negotiation state machines This bit is self clearing 0x4C1 RW Restart AN TX SM When set to 1 restarts the 10GBASE KR TX state machine This bit self clears This bit is active only when the TX state machine is in the AN state For more information refer to bit 7 0 9 in Clause 73 8 Management Register Requirements of IEEE 802 3ap 2007 Altera Corporation RW AN Next Page When asserted new next page info is ready to send The data is in the XNP TX registers When 0 the TX in
155. 88h X 1122324455667788hX112233405566F788h 1122334455667788h rx_control 00h tx_parallel_data 1122334455667788h tx_control 00h rx_enh_highber oh x th Figure 2 46 Block Lock Assertion This figure shows the assertion on rx_enh_b1lk_lock signal when the Receiver detects the block delineation rx_parallel_data 0100009C0100009Ch X0707070707070707h rx_control 11h XFFh tx_parallel_data 0707070707070707h tx_control FFh rx_enh_highber oh X 1h rx_ready rx_enh_block_lock oh X ih Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 The following figures show Idle insertion and deletion Figure 2 47 IDLE Word Insertion This figure shows the insertion of IDLE words in the receiver data stream Before Insertion 10GBASE KR PHY IP with FEC Option 2 103 rx parallel data FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh NK AAAAAAAAAAAAAAAAR After Insertion rx_parallel data FD000000000004AEh BBBBBB9CDDDDDD9Ch lt 0707070707070707h lt 00000000000000FBh Figure 2 48 IDLE Word Deletion This figure shows the deletion of IDLE words from the receiver data stream Before Deletion Idle Inserted 000000FB07070707h rx_parallel_data lt 00000000000004ADh 00000000000004AEh After Deletion rx_parallel_data lt 00000000000004ADh 00000000000004AEh ee 2 Idle Deleted Figure
156. Arria 10 Transceiver PHY User Guide S subscribe eR es Be eee i G Send Feedback eles an Jose 5 7 www altera com TOC 2 Arria 10 Transceiver PHY User Guide Contents Arria 10 Transceiver PHY Overview ccccccsccccccsccscccsccscccccceccecccsccssccsssessee Lo Device Transceiver Layoutt scsscscssiisitititscasiciisitiacensabss tbeaeesdebenctics E E E RAE 1 2 Arria 10 GX Device Transceiver Lay ut sassssecaxisicssissassbssoosasseoisscinatsswedsbisarsasseaaaspasassisecaascsesianasann 1 3 Arria 10 GT Device Transceiver Layout ccccccesssscscseesessssscsssssssssesscesssssssssssssssssesssssssassanees 1 7 Arria 10 GX and GT Device Package Details ucsncunsaitessncassenanvcsnspsdsastbinsvansetinsboupsensvegecnseages 1 11 Arria 10 SX Device Transceiver Layout sss sssessssessrstssssessstessstenstsensssesnieesniesnressnresnressseense 1 12 Arria 10 SX Device Packape Detailssssrnisnunronsynpecnnnsieienaa aaa 1 14 Transceiver PHY Architecture OvervieW s ssseseseseesesesessesssessresssresstessntrsnteesrtresrresrrresrteesrteesreesnreestes 1 15 Transceiver Bank Arc iio ae scsiacexettis chai covssvcsaraivnneabncnsadasdiagnassacenedrabedhsiscsaisnacarpeanasswuasdauess 1 15 PHY Layer Transceiver COMPpPOnents icscesscscsssnsssssisnetarsseestsnersensiesesbuotuesy sbsvsbuvaseeu sbsnssasssavesseddoes 1 17 Transceiver Phase Locked LO Opi sivsastans csssutuasateavaraesbavsnndenanedeahcandovanatacraratiadesaaiuheatoniosvbeednsspaihas 1 20 Clo
157. B disparity control On Off Enable RX 8B 10B decoder On Off Disabled e Basic single width for Basic with Rate RX rate match FIFO mode Match e Basic double width for Basic with Rate Match RX rate match insert delete ve pattern hex User defined value RX rate match insert delete ve pattern hex User defined value Enable rx_std_rmfifo_full port On Off Enable rx_std_rmfifo_empty port On Off Enable TX bit slip On Off Enable tx_std_bitslipboundarysel port On Off RX word aligner mode e bitslip manual PLD controlled e synchronous state machine RX word aligner pattern length 7 8 10 16 20 32 40 RX word aligner pattern hex User defined value Number of word alignment patterns to achieve sync 0 255 Number of invalid data words to lose sync 0 63 Number of valid data words to decrement error count 0 255 Enable rx_std_wa_patternalign port On Off Enable rx_std_wa_ala2size port On Off Enable rx_std_bitslipboundarysel port On Off Enable rx_bitslip port On Off Enable TX bit reversal On Off Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 250 UG A10XCVR Design Considerations for Data Rates Above 17 4 Gbps Using Arria 10 GT Channels 2013 12 02 Enable TX byte reversal On Off Enable TX polarity inversion On Off Enable tx_polinv port On Off Enable RX bit reversal
158. BR4J Bank Bank J GXBL1I Transceiver Transceiver GXBR4I Bank Bank ie GXBL1H Transceiver Transceiver GXBR4H Bank Bank GXBL1G Transceiver Transceiver GXBR4G Bank Bank GXBL1F I S PCle PCle en GXBR4F Gen1 Gen3 Gen1 Gen3 Hard IP Hard IP GXBL1E Transceiver Transceiver GXBR4E Bank Bank GXBL1D Transceiver Transceiver GXBR4D Bank PCle Pee Bank Gen1 Gen3 Gen1 Gen3 Hard IP Hard IP with CvP GXBL1C Transceiver Transceiver GXBR4C 1 Bank Bank 2 Notes 1 Nomenclature of left column bottom transceiver banks always begins with C 2 Nomenclature of right column bottom transceiver banks may begin with C D or E Legend PCle Gen1 Gen3 Hard IP blocks with CvP capabilities PCle Gen1 Gen3 Hard IP blocks without CvP capabilities Altera Corporation 1 4 Arria 10 GX Device Transceiver Layout UG A10XCVR 2013 12 02 Figure 1 3 Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCle Hard IP Blocks Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Notes 1 Nomenclature of left column bottom transceiver banks always begins with C PCle Gent Gen3 Hard IP PCle Gent Gen3 Hard IP with CvP PCle Gent Gen3 Hard IP PCle Gent Gen3 Hard IP Transceiver Ban
159. Bank Bank GX or Restricted Bank gt GT or GX GT or GX i GXBL1H Transceiver Transceiver GXBR4H ieee Bank Bank GXBL1G Transceiver Transceiver GXBR4G Bank Bank GXBLIF Teren PCle PCle Lai GXBR4F Geni Gen3 Geni Gen3 Hard IP Hard IP Transceiver Transceiver GXBR4E GXBLIE Bank Bank XBL1D Transceiver Transceiver GXBR4D G Bank PCle PCle Bank Geni Gen3 Geni Gen3 Hard IP Hard IP with CvP GXBL1C Transceiver Transceiver GXBR4C 1 Bank Bank 2 Notes 1 Nomenclature of left column bottom transceiver banks always begins with C 2 Nomenclature of right column bottom transceiver banks may begin with C D or E Legend i GT transceiver channels channel 0 1 3 and 4 o Transceiver channels that cannot be used channel 2 and 5 when all four GT channels are used PCle Gen1 Gen3 Hard IP blocks with CvP capabilities PCle Gen1 Gen3 Hard IP blocks without CvP capabilities Altera Corporation Arria 10 Transceiver PHY Overview J Send Feedback UG A10XCVR 2013 12 02 Figure 1 9 Arria 10 GT Devices with 72 Transceiver Channels and Four PCle Hard IP Blocks Arria 10 GT Device Transceiver Layout 1 9 Notes CHS WAE CH4 IKOLE cH3 aio Transceiver CH2 WAREN Bank CH1 WIKL CHO IKLAN GT Channels Capable of Short Reach 28 1 Gbps
160. CIRXC 3 0 K co Transceiver Interface SDR Interface Clock 156 25 MHz TXD RXD 63 0 x D1 DO X D3 D2 X D5 D4 TXCIRXC 7 0 C1 CO ne C3 C2 x C5 C4 Note Clause 46 of the IEEE 802 3 2008 specification defines the XGMII interface between the 10GBASE R PCS and the Ethernet MAC RS Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 TX FIFO and RX FIFO 2 97 The transceiver PLL supports a reference clock frequency of 322 265625 MHz and 644 53125 MHz for the 10GBASE R and 10GBASE R with 1588 Transceiver Configuration Rules For 1OGBASE R to ensure proper functioning of the PCS the maximum ppm difference between the TX PLL reference clock and XGMII interface clock on the transmit side is 0 ppm The RX FIFO can compensate 100 ppm between the RX low speed parallel clock and XGMIH interface clock on the receive side Note Channel bonding should be disabled when using the 1OGBASE R and 10GBASE R with 1588 Transceiver Configuration Rules TX FIFO and RX FIFO In 1OGBASE R configuration the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO In 1OGBASE R with 1588 configuration both the TX FIFO and the RX FIFO are used in register mode In 1OGBASE R with KR FEC configuration the TX FIFO is used in phase compensation mode and the RX FIFO behaves as a clock compensa
161. CMU PLL cannot drive the master CGB only the ATX PLL or fPLL can be used for this example e If ATX PLL is used set the following configuration settings e Under the PLL Tab e Set the PLL Feedback type to External e Turn ON Enable external feedback input port 3 48 PLL cascading e Under the Master Clock Generation Block Tab e Enable Include Master Clock Generation Block e Turn ON Enable Bonding Clock output ports e Turn ON Enable feedback compensation bonding e IffPLL is used set the following configuration settings e Under the PLL Tab e Set the PLL Feedback type to Normal e Under the Master Clock Generation Block Tab e Turn ON Enable Bonding Clock output ports 3 Configure the Native PHY IP using the MegaWizard Plug In Manager e Set the Native PHY IP TX Channel bonding mode to either PMA bonding or PMA PCS bonding 4 Connectivity e Create a top level wrapper to connect the PLL IP to Native PHY IP e In this case the PLL IP has tx_bonding_clocks output bus with width 5 0 e The Native PHY IP has tx_bonding_clocks input bus with width 5 0 multiplied by the number of channels in a transceiver bank six channels in the transceiver bank e Unlike the x6 xN bonding mode for this mode the PLL should be instantiated multiple times 1 PLL is required for each transceiver bank that is a part of the bonded group Instantiate a PLL for each transceiver bank used e Connect the tx_bonding_clocks output from each PLL to
162. CTLE mode of operation through the Avalon Memory Mapped Avalon MM registers Related Information e Arria 10 Register Map e Arria 10 Device Datasheet Variable Gain Amplifier VGA Arria 10 channels have a variable gain amplifier to optimize the signal amplitude prior to the CDR sampling The VGA operates both in fixed and adaptive modes Adaptive VGA is controlled by the Adaptive Parametric Tuning Engine Decision Feedback Equalization DFE DFE amplifies the high frequency components ofa signal without amplifying the noise content It compensates for inter symbol interference ISI DFE minimizes post cursor ISI by adding or subtracting weighted versions of the previously received bits from the current bit DFE can work in synchronization with the TX pre emphasis and downstream RX CTLE to enable the RX CDR to receive the correct data that was transmitted through a lossy and noisy backplane An advantage of DFE over CTLE is improved Signal to Noise Ratio SNR That is DFE amplifies the power of the high frequency components without amplifying the noise power Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 8 Decision Feedback Equalization DFE 2013 12 02 Figure 5 10 Signal ISI ISI Precursor Cursor Postcursor Notes An ideal pulse response is a single data point at the cursor e Real world pulse response is non zero before the cursor precursor and after the cursor postc
163. Clock Clock j agnostic loopbac Generation Transmitter nput Serial Block PLL M lt Reference Clock Clock Receiver PMA a n Parallel Parallel Receiver gt Deseriali Data Receiver Data FPGA Buffer Sai ey Deseraizer PCS Fabric Serial Clock Parallel Clock Figure 5 19 Reverse Loopback Path The reverse loopback path sets the transmitter buffer to transmit data fed directly from the CDR recovered data Data from the serializer is ignored by the transmitter buffer Transmitter PMA Transmitter of Parallel Parallel Bao i i Data Serial Differential Output Transmitter Serializer lag Data Transmitter FPGA Buffer PCS Fabric Data lt A Parallel Clock Clock i Generation Transmitter nput Reverse loopback Serial Block PLL lt Reference Clock Clock Receiver PMA Oriel becaiver Data Parallel Parallel 5 Receiver oor Data Receiver Data FPGA Serial Input Buffer Serial CDR p Deserializer gt gt pcs gt gt Fabric Data 1 Data Serial Clock Parallel Clock Arria 10 Enhanced PCS Architecture You can use the Enhanced PCS to implement multiple protocols that operate at around 10 Gbps or higher line rates Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013
164. E KR mode SEQ Force Mode 2 0 forces these modes This reset self clears RW Disable AN Timer Auto Negotiation disable timer If disabled Disable AN Timer 1 AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature In addition software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state To enable this timer set Disable AN Timer 0 RW Disable LF Timer When set to 1 disables the Link Fault timer When set to 0 the Link Fault timer is enabled 6 4 0x4B0 RW SEQ Force Mode 2 0 Forces the sequencer to a specific protocol Must write the Reset SEQ bit to 1 for the Force to take effect The following encodings are defined e 3 b000 No force e 3 b001 GigE e 3 b010 Reserved e 3 b011 Reserved e 3 b100 1OGBASE R e 3 b101 1OGBASE KR e Others Reserved 16 RW FEC ability When set to 1 indicates that the FEC ability is supported When the FEC ability changes you must assert the Reset SEQ bit 0x4B0 0 to renegotiate with the new value 18 RW FEC request When set to 1 indicates that FEC block is enabled When this bit changes you must assert the Reset SEQ bit 0x4B0 0 to renegotiate with the new value Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02
165. Enable TX 64B 66B encoder Off Enable RX 64B 66B decoder off Enable TX sync header error insertion Off Table 2 59 Scrambler and Descrambler Parameters Parameter Value Enable TX scrambler 1OGBASE R On Interlaken TX scrambler seed 1OGBASE R 0x1 to 0x3 FFFFFFFFFFFFFF Interlaken Enable RX descrambler 1OGBASE R On Interlaken Table 2 60 Interlaken Disparity Generator and Checker Parameters Parameter Value Enable Interlaken TX disparity On generator Enable Interlaken RX disparity checker On Table 2 61 Block Synchronizer Parameters Parameter Value Enable RX block synchronizer On Enable rx_enh_blk_lock port On Off Table 2 62 Gearbox Parameters Parameter Value Enable TX data bitslip On Off Enable TX data polarity inversion On Off Enable RX data bitslip On Off Enable RX data polarity inversion On Off Enable tx_enh_bitslip port On Off Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Ethernet 2 79 Enable rx_bitslip port On Off Table 2 63 Dynamic Reconfiguration Parameters Parameter Value Enable dynamic reconfiguration On Off Share reconfiguration interface On Off Enable embedded JTAG AVMM master On Off Table 2 64 Configuration Files Parameters Parameter Value Configuration file prefix Generate SystemVerilog package file O
166. Enhanced PCS Datapaths The Standard PCS supports the 1G protocol The Enhanced PCS supports 1OGBASE R Refer to the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support 1G 10G protocols and FEC Sequencer The Sequencer controls the start up sequence of the PHY IP including reset and power on It selects which PCS 1G or 10G and PMA interface is active The Sequencer interfaces to the reconfiguration block to request a reconfigurations to change from one data rate to the other data rate Gigabit Ethernet GbE PCS The GbE PCS includes the GMI interface and Clause 37 auto negotiation and SGMII functionality Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 108 10GBASE KR Functional Description 2013 12 02 1588 FIFO The 1588 FIFO has an XGMII like interface for both input and outputs The 1588 FIFO includes the latency adjust information that the 1588 logic in the MAC requires Link Training LT Clause 72 This module performs link training as defined in Clause 72 The module facilitates two features e Daisy chain mode for non standard link configurations where the TX and RX interfaces connect to different link partners instead of in a spoke and hub or switch topology e An embedded processor mode to override the state machine based training algorithm This mode allows an embedded processor to establish link data rates instead of establish
167. FIFO FPGA Fabric Interface rx_enh_fifo_align_clr UG A10XCVR 2013 12 02 10GBASE R Mode rx_enh_fifo_rd_en i rx_enh_fifo_pempty rx_enh_fifo_pfull RX FIFO In 1OGBASE R mode the RX FIFO operates as a clock compensation FIFO When the block synchronizer achieves block lock data is sent through the FIFO Idles Ordered Sets OS are deleted and Idles are inserted to compensate for the clock difference between the RX low speed parallel clock and the FPGA fabric clock 100 ppm for a maximum packet length of 64 000 bytes Idle OS Deletion Deletion of Idles occurs in groups of four OS when there are two consecutive OS until the rx_enh_fifo_rd_pempty flag deasserts Every word consisting of a lower word LW and an upper word UW is checked for whether it can be deleted by looking at both the current and previous words For example the current LW can be deleted if it is Idle and the previous UW is not a Terminate Table 5 4 Conditions Under Which a Word Can be Deleted In this table X don t care T Terminate I Idle and OS order set UW IT X i IT X LW X I X X Lower Word UW OS X OS X LW X OS X X i UW X I X X LW X IT X IT Upper Word 2 UW X OS X X LW X OS X OS If only one word is deleted data shifting is necessary because the datapath is two words wide After two words have been deleted the FIFO stops writing for one cycle and a synchro
168. FO in Phase Compensation Mode Datapath to Byte Serializer TX Datapath from FPGA Fabric 8B 10B Encoder lt FIFO lt q or PIPE Interface or Serializer rd_clk wr_clk tx_coreclkin tx_clkot Concerning TX FIFO modes PIPE Gen1 Gen2 and Gen3 only allow TX FIFO in Low Latency mode The Low Latency mode incurs 3 4 cycles of latency when connecting with the FPGA Fabric The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases which decreases the latency Related Information Arria 10 Standard PCS Architecture on page 5 31 For more information about TX FIFO Gearbox The PCIe 3 0 base specification specifies a block size of 130 bits with the exception of the SKP Ordered Sets which can be of variable length An implementation of a 130 bit data path takes significant resources so the PCIe Gen3 PCS data path is implemented as 32 bits wide Because the TX PMA data width is fixed to 32 bits and the block size is 130 bits with variations a gearbox is needed to convert 130 bits to 32 bits The gearbox module in the TX PCS converts the 130 bit block to the 32 bit data required by the TX PMA as the data path implementation is 32 bits to reduce usage of resources The 130 bit block is received as follows in the 32 bit data path 34 32 2 bit sync header 32 32 32 34 32 2 bit sync header During the first cycle the gearbox converts the
169. G A10XCVR 2013 12 02 Arria 10 GX Device Transceiver Layout The largest Arria 10 GX device includes 96 transceiver channels A column array of eight transceiver banks on the left and the right side periphery of the device is shown in the following figure Each transceiver bank has six transceiver channels Some devices have transceiver banks with only three channels The transceiver banks with only three channels are the uppermost transceiver banks Arria 10 devices also include PCI Express Hard IP blocks Arria 10 GX Device Transceiver Layout 1 3 The figures below illustrate different transceiver bank layouts for Arria 10 GX device variants Figure 1 2 Arria 10 GX Devices with 96 Transceiver Channels and Four PCle Hard IP Blocks Transceiver Bank CH5 CH4 CH3 CH2 CH1 CHO Arria 10 Transceiver PHY Overview GJ Send Feedback GX 115 UF45 et GXBL1J Transceiver GX 090 UF45 Transceiver GX
170. GA fabric width specified You must understand the mapping of data and control signals within the interface When you turn on this option the Transceiver Native PHY IP presents a simplified data and control interface between the FPGA fabric and transceiver Only the sub set of the 128 bits that are active for a particular FPGA fabric width are ports The default value is Off Table 2 3 Transceiver Configuration Rule Parameters Basic Custom Standard PCS Basic Custom w Rate Match Enforces a standard set of rules within the Standard PCS Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules Enforces a standard set of rules including rules for the Rate Match FIFO Standard PCS within the Standard PCS Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules CPRI Auto Enforces rules required by the CPRI protocol The receiver word aligner mode is set to Auto In Auto mode the word aligner is set to deterministic latency CPRI Manual Enforces rules required by CPRI protocol The receiver word aligner mode is set to Manual In Manual mode logic in the FPGA fabric controls the word aligner GbE Enforces rules that the 1 Gbps Ethernet 1 GbE protocol requires GbE 1588 Enforces rules for the 1 GbE protocol with support fo
171. HY IP NE Registers CSR CLK FPLL Reconfiguration Avalon MM Slave 1G Ref CLK 1588 Soft Native Hard CMU PLL FIFOs gt TX PMA 10G Ref CLK ATX PLL Sequencer m gt Reset gt Contro Reset Contro Reset Contro Reset Contro Divide lt __ Divide Related Information Arria 10 Transceiver PHY Design Examples Simulation Support The 1G 10GbE and 10GBASE KR PHY IP Core supports ModelSim Verilog and ModelSim VHDL VCS Verilog and VCS VHDL simulation Arria 10 devices also support NCSIM Verilog and NCSIM VHDL simulation The MegaWizard Plug In Manager generates an IP functional simulation model when you press the Finish button TimeQuest Timing Constraints To pass timing analysis you must decouple the clocks in different time domains The necessary Synopsys Design Constraints File sdc timing constraints for the are included in the top level wrapper file Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Acronyms Acronyms 2 179 This table defines some commonly used Ethernet acronyms Table 2 122 Ethernet Acronyms AN Auto Negotiation in Ethernet as described in Clause 73 or of IEEE 802 3ap 2007 BER Bit Error Rate DME Differential Manchester Encoding FEC Forward error correction GMII Gigabit Media Independent Interface KR Short hand notation for Backplane Ethernet with 64b 66b encoding LD
172. HY IP should use a unique prefix for configuration files Generate On Off When you turn this option on the Transceiver Native PHY IP System Verilog generates a SystemVerilog package file _reconifg_parameters sv package file containing parameters defined with the attribute values required for reconfiguration Generate C On Off When you turn this option on the Transceiver Native PHY IP header file generates a C header file _reconifg_parameters h containing macros defined with the attribute values required for reconfigura tion Generate MIF On Off When you turn this option on the Transceiver Native PHY IP Memory Initial generates a MIF reconifg_parameters mif containing the ization File attribute values required for reconfiguration in a data format Table 2 31 Generation Options Generate On Off When you turn this option on generation produces a Comma parameter Separated Value File csv with descriptions of the Transceiver documentation Native PHY IP parameters file Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS and PMA Ports 2 37 Enhanced PCS and PMA Ports Figure 2 7 Enhanced PCS Interfaces If you enable both the Enhanced PCS and Standard PCS your top level HDL file includes all the ports for both datapaths The labeled inputs and outputs to the PMA and PCS modules represent buses not individual signals Arria 1
173. I writedata0 31 0 input reconfig_cl 32 bit data bus Carries the write data to the specified address reconfig_ readdata0 31 0 output reconfig_cl1k0 32 bit data bus Carries the read data from the specified address reconfig_waitrequest0 output reconfig_clk0 Indicates when the Avalon interface signal is busy When asserted all inputs must be held constant pll_cal_busy output Asynchronous Status signal which is asserted high when PLL calibration is in progress OR this signal with the t x_ cal_busy port on the reset controller IP MEGO PST input N A Master CGB reset control If pll feedback compensation bonding mode is used deassert this reset at the same time as pll_powerdown If pll feedback compensation bonding is not being used then this port can be deasserted after pll_powerdown is deasserted but before t x_ analogreset is de asserted Alternatively this port can be deasserted at the same time as pll_powerdown mcgb_aux_c1k0 input N A Used for PCIe to switch between fPLL ATX PLL during link speed negotiation tx_bonding_clocks 5 0 Output N A Optional 6 bit bus which carries the low speed parallel clock outputs from the Master CGB Used for channel bonding and represents the x6 xN clock network mcgb_serial_clk Output N A High speed serial clock output for x6 xN non bonded configu rations pcie_sw 1 0
174. I1 or I2 so that the final running disparity of the data code group is negative The first code group is K28 5 and the second code group is a data code group other than D21 5 or D2 2 I1 K28 5 D5 6 is used to flip the running disparity and 12 K28 5 D16 2 is used to preserve the running disparity 8B 10B Encoder Current Running Disparity Control Feature The 8B 10B encoder performs a running disparity check on the 10 bit output data The running disparity can also be controlled using tx_forcedisp and tx_dispval When the PCS PMA interface width is 10 bits tx_forcedisp and tx_dispval are one bit each When the PCS PMA interface width is 20 bits tx_forcedispandtx_dispval are two bits each The LSB of tx_forcedispandtx_dispval corresponds to the LSByte of the input data and the MSB corresponds to the MSByte of the input data 8B 10B Encoder Bit Reversal Feature The bit reversal feature reverses the order of the bits of the input data Bit reversal is performed at the output of the 8B 10B Encoder and is available even when the 8B 10B Encoder is disabled For example if the input data is 20 bits wide bit reversal switches bit 0 with bit 19 bit 1 with bit 18 and so on 8B 10B Encoder Byte Reversal Feature The byte reversal feature is available only when the PCS PMA interface width is 16 bits or 20 bits Byte reversal is performed at the output of the 8B 10B Encoder and is available even when the 8B 10B Encoder is disabled
175. IEEE 802 3 2008 specification The 10GBASE R protocol is used in optical module LAN applications such as optical routers servers and switches It uses the XGMII interface to connect to the IEEE802 3 media access control MAC and reconciliation sub layers RS It delivers serialized data at a line rate of 10 3125 gigabits per second Gbps Each channel operates independently in a multi channel implementation Figure 2 37 10GBASE R PHY Connection to IEEE802 3 MAC and RS OSI Reference Model Layers LAN CSMA CD LAYERS Higher Layers Logical Link Control LLC or other MAC Client MAC Control Optional Media Access Control MAC Application Reconciliation Presentation XGMI l gt Session 1OGBASE R PCS Transport Pa ee 10GBASE R FEC Optional Network PHY PMA Data Link PMD Physical MDI E To 10GBASE R PHY medum Point to Point Link 10GBASE R PCS FEC PMA PMD Legend MDI Medium Dependent Interface PCS Physical Coding Sublayer PHY Physical Layer Device PMA Physical Medium Attachment PMD Physical Medium Dependent FEC Forwarad Error Correction XGMII 10 GB Media Independent Interface Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC 2 93 You can configure the tran
176. IPE block clock Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 190 CDR Control 2013 12 02 Figure 2 75 P1 to PO Transition The figure below shows the transition from P1 to PO with completion provided by pipe_phy_status tx_clkout Il pipe_powerdown P1 PO pipe_phy_status CDR Control The CDR control block controls the PMA CDR to obtain bit and symbol alignment and deskew within the allocated time and generates status signals for other PCS blocks The PCle base specification requires that the receiver LOs power state exit time be a maximum of 4 ms for Gen1 2 ms for Gen2 and 4 ms for Gen3 signaling rates The transceivers have an improved CDR control block to accommodate fast lock times when the CDR must relock to the new multiplier divider settings when entering or exiting Gen3 speeds Gearbox As per PIPE 3 0 spec for every 128 bits that are moved across the Gen3 PCS the PHY must transmit 130 bits of data Altera uses the pipe_tx_data_valid signal every 16 blocks of data to transmit the built up backlog of 32 bits of data The 130 bit block is received as follows in the 32 bit data path 34 32 2bit sync header 32 32 32 During the first cycle the gearbox converts the 34 bit input data to 32 bit data During the next 3 clock cycles the gearbox merges bits from adjacent cycles In order for the gearbox to work correctly a gap must be provided in the
177. IPE transceiver configuration rule in standard PCS Similarly you can customize the Transceiver Native PHY IP by specifying various IP parameters For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native PHY IP on page 2 12 For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page 2 12 PCI Express Hard IP is also available as a MegaCore function The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed negotiation and sequencer functions Needs a user created Soft IP for link training auto speed negotiation and sequencer functions PCS Direct support will be available in a future release of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software XAUI PHY IP will be available in a future release of the Quartus II software Altera Corporation Implementing Protocols in Arria 10 Transceivers GI Send Feedback UG A10XCVR 2013 12 02 Using the Arria 10 Transceiver Native PHY IP 2 13 Figure 2 5 Transceiver Native PHY IP Top Level Interfaces and Functional Blocks Transmit Parallel Data Receive Parallel Data Reconfiguration Interface gt Reset Signals Transmit and Receive Clocks Pa lt q gt Transmit Enhanced PCS Sua Standard PCS Receive PMA PCle Ge
178. In this mode the RX FIFO acts as an elastic buffer The gearbox data valid flag controls the FIFO read enable You can monitor the rx_enh_fifo_pfull and rx_enh_fifo_ empty flags to determine whether or not to read from the FIFO RX FIFO 0 31 Specifies the partially full threshold for the Enhanced PCS RX partially full FIFO The default value is 23 threshold RX FIFO 0 31 Specifies the partially empty threshold for the Enhanced PCS RX partially empty FIFO The default value is 2 threshold Enable RX FIFO On Off When you turn this option on all alignment words sync words alignment word including the first sync word are removed after frame synchro deletion nization is achieved If you enable this option you must also enable Interlaken control word deletion Enable RX FIFO On Off When you turn this option on Interlaken control word removal control word is enabled When the Enhanced PCS RX FIFO is configured in deletion Interlaken mode enabling this option removes all control words Interlaken after frame synchronization is achieved Enabling this option requires that you also enable alignment word deletion Enable rx enh_ On Off Enables the rx_enh_data_valid port data_valid port Enable rx_enh_ On Off Enables the rx_enh_fifo_full port fifo_full port Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS Parameters 2 25 Enable r
179. Installed Plug Ins a LJ Arithmetic C VHDL J Communications Verilog HDL LJ DSP z Gates What name do you want for the output file 7 Vo data nikshah Demol et J Interfaces LJ JTAG accessible Extensions J Memory Compiler F Return to this page for another create operation j PLL A i Note To compile a project successfully in the Quartus II software your design files aap aii aaa must be in the project directory in a library specified in the Libraries page of the ae PLL v13 1 Options dialog box Tools menu or a library specified in the Libraries page of the Armia 10 FPL vi3 1 Settings dialog box Assignments menu N Arria 10 Transceiver ATX PLL v13 1 oe Arria 10 Transceiver CMU PLL v13 1 J Click to Open IP MegaStore Your current user library directories are Cancel lt Back Next gt Finish Related Information PLLs on page 3 3 Configure PLL IP Understand the available PLLs clock networks and the supported clocking configurations Configure the PLL IP to achieve adequate data rate for your design Related Information e ATX PLL IP on page 3 6 e fPLL IP on page 3 13 e CMU PLL IP on page 3 21 e Using PLLs and Clock Networks on page 3 40 Generate PLL IP After configuring the PLL IP click the Finish button in the MegaWizard Plug In Manager window This generates the PLL IP The Quartus II software generates a lt pll ip instance name gt folder lt pll ip instance name gt
180. Interface Width is 20 Bits tx_parallel_data 20 h3FC3BC and the word aligner pattern 0x3BC rx_std_wa_patternalign tx_parallel_data fe3be rx_parallel_data 0000 fe3be rx_patterndetect 00 Yor rx_syncstatus 00 I 11 u 11 rx_std_wa_patternalign tx_parallel_data fc3bc rx_parallel_data fc3bc rx_patterndetect 01 rx_syncstatus 11 o0 u Word Aligner Synchronous State Machine Mode To use this mode e Select the Enable TX 8B 10B encoder option e Select the Enable RX 8B 10B decoder option The 8B 10B encoder and decoder add the following additional ports e tx _datak e rx _datak e rx_errdetect e rx_disperr e rx_runningdisp 1 Set the RX word aligner mode to synchronous state machine 2 Set the RX word aligner pattern length option according to the PCS PMA interface width 3 Enter a hexadecimal value in the RX word aligner pattern hex field Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 236 RX Bit Slip 2013 12 02 The RX word aligner pattern is the 8B 10B encoded version of the data pattern You can also specify the number of word alignment patterns to achieve synchronization the number of invalid data words to lose synchronization and the number of valid data words to decrement error count This mode adds two additional ports rx_patterndetect and rx_syncstatus Note e rx_pat
181. L Feedback and Cascading Clock Network pana Reference Clock Network ATX PLL1 N From PLL Feedback and Cascading Clock fPLLO Tristate Capable Bidirectional Buffer Network From PLL Feedback and Cascading Clock Network Reference Clack Network ATX PLLO lt q Reick Input Reference Clock to the PLLs Can Come from Either the Reference Clock Network or the PLL Feedback and Cascading Clock Network From PLL Feedback and Cascading Clock Tristate Capable Bidirectional Buffer Network Receiver Input Pins Receiver input pins can be used as an input reference clock source lt q Refck ATX and fPLL Can Receive the Input Reference Clock from a Dedicated refclk Pin The receiver input pin drives the reference clock network which can then feed any number of transmitter PLLs on the same side of the device When a receiver input pin is used as an input reference clock source the clock data recovery CDR block of that channel is not available As indicated in Figure 3 5 only one RX differential pin pair per three channels can be used as an input reference clock source at any given time PLL Cascading as a Input Reference Clock Source In PLL cascading PLL outp
182. L option Configure the number of clocks desired and the desired output clock parameters A message appears indicating which output clock port should be used as the cascading source Generate the ATX PLL IP the second PLL in the design 6 Configure the ATX PLL IP for the desired data rate and the reference clock frequency Ensure that the reference clock frequency for the ATX PLL matches the output of the fPLL ron nn Note No special configuration is required for the Native PHY instance Connectivity 1 Instantiate both the fPLL and the ATX PLL 2 The fPLL has an output port at x_p1l1_cascade_clk Connect this port to the ATX PLL s pll_refclk0 port 3 For p11_powerdown both the PLLs can share the same p11_powerdown or use independent power down sources 4 OR the p11_powerdown of ATX PLL with p11_1lock signal of the first PLL This ensures that the second PLL downstream PLL is powered down until the first PLL has successfully locked to the input reference clock This prevents the second PLL from trying to lock until the output of the first PLL is stable Note The procedure for PLL to fPLL cascading is similar to the one described here fPLL to ATX PLL cascading Mix and Match Example The Arria 10 transceiver architecture and Native PHY IP PLL IP scheme allows great flexibility It is easy to share PLLs and reconfigure data rates The following design example illustrates PLL sharing and both bonded and non bonde
183. LL IP Arria 10 devices have three types of PLL IPs e Advanced Transmit ATX PLL IP e Fractional PLL fPLL IP e Channel PLL Clock Multiplier Unit CMU PLL IP Select the appropriate PLL IP for your design Refer to the PLLs and Clock Networks chapter for detailed information on available PLLs and clock networks To instantiate a PLL IP Open the Quartus II software Click Tools gt MegaWizard Plug In Manager Select Create a new custom megafunction variation then click Next Select Arria 10 device family Select PLL in the Installed Plug Ins tree Choose the PLL IP Arria 10 Transceiver ATX PLL Arria 10 fPLL or Arria 10 Transceiver CMU PLL you want to instantiate in your design 6 Under Which type of output file do you want to create select Verilog or VHDL as the hardware description language 7 In What name do you want for the output file browse to the location where you want to save your design and enter a filename aA bk WON 8 Click Next The PLL IP GUI window opens Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Configure PLL IP 2 5 Figure 2 4 Arria 10 Transceiver PLL Types F MegaWizard Plug In Manager page 2a x Which megafunction would you like to customize Which device family will you be using Arria 10 gt Select a megafunction from the list below x Which type of output file do you want to create Q C AHDL 5 5
184. MAX ovrd Enable When set to 1 enables the override value for the VUAXRULE parameter stored in the LT VODMAX ovrd register field RW LT VODMin ovrd Override value for the VODMINRULE parameter When enabled this value substitutes for the VMINRULE to allow channel by channel override of the device settings This override only effects the local device TX output for this channel The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation 14 0x4D6 RW LT VODMin ovrd Enable When set to 1 enables the override value for the VODMINRULE parameter storedinthe LT VODMin ovrd register field 20 16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter When enabled this value substitutes for the VPOSTRULE to allow channel by channel override of the device settings This override only effects the local device TX output for this channel The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation 21 RW LT VPOST ovrd Enable When set to 1 enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd register field 27 24 RW LT VPre ovrd Override value for the VPRERULE parameter When enabled this value substitutes for the VPOSTRULE to allow channel by channel override of the device settings This override only effects the local device TX output for
185. NF40 GT Channels GXBL1J Transceiver GT 090 NF40 Capable of Short Bank Reach 28 1 Gbps GX or Restricted ie GT or GX GXBL1i Transceiver GT or GX Transceiver Pa Pank GX or Restricted Bank E GT or GX es GT or GX T f ransceiver GXBLIH Bank cts Transceiver Bank GXBL1F ie PCle Geni Gen3 Hard IP GXBL1E Transceiver Bank GXBL1D T i sca PCle Gen1 Gen3 Hard IP with CvP GXBL1C Transceiver 1 Bank Notes 1 Nomenclature of left column bottom transceiver banks always begins with C 2 These devices have transceivers only on left hand side of the device Legend a GT transceiver channels channel 0 1 3 and 4 M Transceiver channels that cannot be used channel 2 and 5 when all four GT channels in the bank are used PCle Gen3 HIP blocks with CvP capabilities PCle Gen3 HIP blocks without CvP capabilities The largest GT device has 96 transceiver channels which include 16 GT transceiver channels supporting data rates greater than 17 4 Gbps If all 16 GT transceiver channels are used then there will be 72 GX transceiver channels that can drive backplanes at data rates up to 17 4 Gbps and 8 GX channels that are unusable In contrast the GX transceiver channels in SX and GX device variants can drive backplanes at data rates up to 16 0 Gbps In GT devices that have transceivers on both sides of the device the GX transceiver channels on right sid
186. O in basic single width mode Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 42 8B 10B Decoder 2013 12 02 e Rate Match FIFO Basic Double Width Mode on page 2 240 For more information about implementing rate match FIFO in basic double width mode e Howto Implement GbE GbE 1588 in Arria 10 Transceivers on page 2 86 For more information about implementing rate match FIFO in GigE mode e PCI Express on page 2 179 For more information about implementing rate match FIFO in PCIe mode e Howto Implement PCI Express in Arria 10 Transceivers on page 2 197 For more information about implementing rate match FIFO in PIPE mode 8B 10B Decoder The general functionality for the 8B 10B decoder is to take a 10 bit encoded value as input and produce an 8 bit data value and a 1 bit control value as output In configurations with the rate match FIFO enabled the 8B 10B decoder receives data from the rate match FIFO In configurations with the rate match FIFO disabled the 8B 10B decoder receives data from the word aligner The 8B 10B decoder operates in two conditions e When the PCS PMA interface width is 10 bits and FGPA fabric PCS interface width is 8 bits e When the PCS PMA interface width is 20 bits and FPGA fabric PCS interface width is 16 bits The 8B 10B decoder supports the following features e PCle PIPE polarity inversion e Running disparity checker e 8B 10B decoder bypass Figure 5 46 8B 10B
187. OGBASE KR PHY to automatically configure the link partner TX PMDs for the lowest Bit Error Rate BER LT is defined in Clause 72 of IEEE Std 802 3ap 2007 e Auto negotiation AN The 10OGBASE KR PHY IP can auto negotiate between 1000BASE KX 1GbE and 10GBASE KR 10GbE PHY types The AN function is mandatory for Backplane Ethernet It is defined in Clause 73 of the IEEE Std 802 3ap 2007 e Forward Error Correction Forward Error Correction FEC function is an optional feature defined in Clause 74 of IEEE 802 3ap 2007 It provides an error detection and correction mechanism allowing noisy channels to achieve the Ethernet mandated Bit Error Rate BER of 101 Related Information e IEEE Std 802 3ap 2008 Standard e Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Implementing Protocols in Arria 10 Transceivers Altera Corporation os Send Feedback F UG A10XCVR 2 106 10GBASE KR PHY Release Information 2013 12 02 10GBASE KR PHY Release Information Table 2 83 10GBASE KR PHY Release Information a Version 13 1 Release Date November 2013 Ordering Codes IP 10GBASEKR PHY primary Product ID 0106 Vendor ID 6AF7 10GBASE KR PHY Performance and Resource Utilization This topic provides performance and resource utilization for the IP The following table shows the typical expected resource utilization for selected configurations using the Quartus II software
188. On Off Enable rx_std_bitrev_ena port On Off Enable RX byte reversal On Off Enable rx_std_byterev_ena port On Off Enable RX polarity inversion On Off Enable rx_polinv port On Off Enable rx_std_signaldetect port On Off Enable PCIe dynamic datarate switch ports Off Enable PCIe pipe_hclk_in and pipe_hclk_out ports Off Enable PCIe Gen3 analog control ports Off Enable PCIe electrical idle control and status ports Off Enable PCIe pipe_rx_polarity port Off Table 2 151 Dynamic Reconfiguration Parameters Enable dynamic reconfiguration On Off Share reconfiguration interface On Off Enable embedded JTAG AVMM master On Off Table 2 152 Generation Options Parameters Generate parameter documentation file On Off Design Considerations for Data Rates Above 17 4 Gbps Using Arria 10 GT Channels This section provides information on using the Arria 10 GT transceiver channels to achieve data rates from 17 4 to 28 1 Gbps Arria 10 GT transceiver channels are used to implement data rates above 17 4 Gbps GT channels can be used in Enhanced PCS Low Latency mode to support data rates from 17 4 Gbps to 28 1 Gbps GT channels can also operate in PCS Direct configuration for data rates up to 28 1 Gbps When GT channels are used in PCS Direct configuration the PCS blocks are bypassed The serializer deserializer in GT channels supports 64 bit and 128 bit serialization factors Altera Corporation Implementing Protocols in Arria 10 Transceivers
189. P on page 2 3 Interlaken on page 2 62 Gigabit Ethernet GbE and GbE with 1588 on page 2 80 10GBASE R 10GBASE R with 1588 and 1OGBASE R with KR FEC on page 2 92 10GBASE KR PHY IP with FEC Option on page 2 103 1G 10 Gbps Ethernet PHY IP Core on page 2 149 PCI Express on page 2 179 CPRI on page 2 216 Using the Basic and Basic with KR FEC Configurations of Enhanced PCS on page 2 225 Using the Basic Custom Basic Custom with Rate Match Configurations of Standard PCS on page 2 232 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 General and Datapath Parameters General and Datapath Parameters 2 15 Design Considerations for Data Rates Above 17 4 Gbps Using Arria 10 GT Channels on page 2 250 PMA Parameters on page 2 17 You can customize your instance of the Transceiver Native PHY IP by specifying parameter values The GUI organizes the parameters into the following sections for each functional block and feature Table 2 2 General and Datapath Options TX PMA RX PMA Enhanced PCS Standard PCS Dynamic Reconfiguration General and Datapath Options Device speed fastest grade Specifies the required speed grade This information is used for data rate validation Message level for error rule violations message Specifies the messaging level for parameter rule violations Selecting error causes all rule violations to prevent IP generation
190. P provides access to the ATX PLLs in hardware One instance of the PLL IP represents one ATX PLL in hardware 1 Open the Quartus II software 2 Click Tools gt MegaWizard Plug In Manager 3 Select the Arria 10 device family 4 Select PLL in the Installed Plug Ins tree Choose Arria 10 Transceiver ATX PLL 5 In What name do you want for the output file browse to the location where you want to save your design and enter a filename Click Next The ATX PLL IP MegaWizard Plug In Manager window opens PLLs and Clock Networks Altera Corporation CJ Send Feedback 3 6 ATX PLL IP ATX PLL IP UG A10XCVR 2013 12 02 The ATX PLL configuration options and parameters are listed in the following tables Table 3 2 ATX PLL Parameters and Settings Message level for rule violations Error Specifies the messaging level to use for parameter rule A violations Warning e Error Causes all rule violations to prevent IP generation e Warning Displays all rule violations as warnings and will allow IP generation in spite of violations Device speed grade fastest Specifies the desired device speed grade This information is used for PLL frequency validation Protocol mode Basic Governs the internal setting rules for the VCO PCIe Genl This parameter is not a preset You must set all other PCle Gen _ Parameters for your protocol PCIe Gen3 Bandwidth Low Specifies the VCO bandwidth Medium Higher bandwidth reduces PLL lock time at
191. PGA fabric through the Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Gen3 Features 2 187 rx_parallel_data port This loopback mode is based on PCle specification 2 0 Arria 10 devices provide an input signal to enable this loopback mode Note This is the only loopback option supported in PIPE configurations Figure 2 72 PCle Reverse Parallel Loopback Mode Datapath Wep euas xy Lep euas x1 Transmitter PMA Transmitter Standard PCS FPGA Fabric i a Reverse Parallel i Loopback Path PCI Express Hard IP Receiver PMA i Receiver Standard PCS LL PIPE Interface i gt aao Jazijeuasaq Jaubly plo Old YIN IPY 49p098q 401 88 Jazijeueseq aikg Odld Xd y Related Information Intel PHY Interface for the PCI Express PIPE Architecture PCI Express 2 0 Arria 10 Standard PCS Architecture on page 5 31 Gen3 Features The following sub section explains how the various PIPE features are supported by the Arria 10 transceiver block The PCS supports PIPE 3 0 base specification The PIPE interface has been expanded to a 32 bit wide PIPE 3 0 based interface The PIPE interface controls PHY functions such as transmission of electrical idle receiver detection and speed negotiation and control
192. PHY IP PCS Direct Basic Enhanced User created Enhanced low ey latency mode FDR FDR 10 Infiniband x1 Native PHY IP Enhanced Basic Enhanced User created x4 x12 PCS SDR DDR QDR Infiniband Native PHY IP Standard Basic Custom User created x1 x4 x12 Standard PCS CPRI 6 0 10 1376 Gbps Native PHY IP Enhanced 10GBASE R 1588 10GBASE R 1588 CPRI 4 2 OBSAI RP3 v4 2 Native PHY IP Standard CPRI Auto CPRI9 8Gbps Auto Mode SERUM arina CPRI 9 8 Gbps Manual Mode SRIO 2 2 1 3 Native PHY IP Standard Basic Custom User created Standard PCS SAS 3 0 Native PHY IP Enhanced Basic Enhanced User created PCS SATA 3 0 2 0 1 0 and SAS Native PHY IP Standard Basic Custom User created 2 0 1 0 Standard PCS HiGig HiGig HiGig2 Native PHY IP Standard Basic Custom User created HiGig2 Standard PCS JESD204B Native PHY IP Enhanced Basic Enhanced User created PCS JESD204A Native PHY IP Standard Basic Custom User created Standard PCS 17 PHY IP on page 2 12 18 2 12 19 PCI Express Hard IP is also available as a MegaCore function For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page CO The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed negotiation and sequencer functions 21 22 23 4 X AUI PHY
193. PLLs and master clock generation blocks CGBs The transceiver banks with three transceiver channels have one master CGB ATX PLL and fPLL The Arria 10 transceiver clocking architecture supports both bonded and non bonded transceiver channel configurations Channel bonding is used to minimize the clock skew between multiple transceiver channels within the same interface For Arria 10 transceivers the term bonding can refer to PMA bonding as well as PMA and PCS bonding Refer to the Channel Bonding section for more details 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any pu
194. PLLs and Clock Networks CGJ Send Feedback UG A10XCVR 2013 12 02 fPLL IP 3 15 Table 3 8 fPLL Master Clock Generation Block Parameters and Settings Include Master Clock Generation On Off When enabled includes a master CGB as a part of the Block fPLL IP The PLL output drives the master CGB This is used for x6 xN bonded and non bonded modes Clock division factor 1 2 4 8 Divides the master CGB clock input before generating bonding clocks Enable x6 xN non bonded high On Off Enables the master CGB serial clock output port used speed clock output port for x6 xN non bonded modes Enable PCIe clock switch On Off Enables the control signals used for PCle clock switch interface circuitry Number of auxiliary MCGB Auxiliary input is intended for PCIe Gen3 clock input ports MCGB input clock frequency Read only Displays the master CGB s required input clock frequency You cannot set this parameter MCGB output data rate Read only Displays the master CGB s output data rate You cannot set this parameter This value is calculated based on MCGB input clock frequency and MCGB clock division factor Enable bonding clock output On Off Enables the tx_bonding_clocks output ports ports of the Master CGB used for channel bonding You must enable this for bonded designs Enable feedback compensation On Off Enables the feedback output path of the master CGB bonding used for feedback compensation bonding
195. PMA gt i qz oO x A tx_clkout tx_clkout E gt 14 gt CDR Auto Speed Negotiation PIPE Interface Gen3 x1 x2 x4 x8 y RX PCle Gen3 PCS g poj pel So ae ng 32 a3 os gt gg RX z s F x K PMA I AA eos 5 a 3 5 x S rx_clkout N tx_clkout Clock Generation Block CGB En 4 ATX PLL Clock Divider je PLL Serial Clock l Parallel Clock Serial Clock Parallel and Serial Clocks Parallel and Serial Clocks helk for ASN Block Input Reference Clock Related Information Altera Hard IP for PCIe Users Guide PCI Express on page 2 179 For more information about PCIe Gen1 Gen2 and Gen3 implementation and configuration refer to Supported PIPE Features Altera Corporation Arria 10 Transceiver PHY Architecture I Send Feedback UG A10XCVR 2013 12 02 Transmitter Datapath 5 47 Transmitter Datapath This section describes the TX FIFO and the Gearbox of the Gen3 PCS transmitter TX FIFO Shared with Standard and Enhanced PCS The TX FIFO in each channel ensures a reliable transfer of data and status signals between the PCS channel and the FPGA fabric The TX FIFO compensates for the phase difference between the low speed parallel PCS clock and the FPGA fabric clock The RX and TX FIFOs are shared with standard and enhanced PCS In Hard IP mode the TX FIFO works in register mode In PIPE mode the TX FIFO works in low latency mode Figure 5 51 TX FI
196. PMA reconfigu ration The following figure shows the reconfiguration block details The Avalon MM master accepts requests from the PMA or PCS controller It performs the Read Modify Write or Write commands using the Avalon MM interface The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read Modify Write or Write commands to the PMA and PCS Eight compile time configuration modes are supported These include the enumerated combination of reference clock 644 MHz or 322 MHz including the 1588 mode and the FEC sublayer Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 110 Parameterizing the 10GBASE KR PHY UG A10XCVR 2013 12 02 Figure 2 54 Reconfiguration Block Details mgmt_clk rcfg_data e e e address data 1 PCS mp rcfg data PCS Reconfiguration I F lt gt esti control v R Daek 4 gt PMA and PCS PMA Reconfiguration Controller busy Requests PMA Reconfiguration I F lt gt e Note Based on the control signal the data is streamed to the AVMM master Related Information Arria 10 Enhanced PCS Architecture on page 5 14 Arria 10 Standard PCS Architecture on page 5 31 Parameterizing the 10GBASE KR PHY The Arria 10 1G 10GbE and 10GBASE KR PHY IP core allows you to select either the Backplane KR or 1Gb
197. PON EPON Native PHY IP Standard Basic Custom User created Standard PCS 16G 10G Fibre Channel Native PHY IP Enhanced Basic Enhanced User created PCS 17 PHY IP on page 2 12 18 2 12 19 PCI Express Hard IP is also available as a MegaCore function For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page CO The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed negotiation and sequencer functions 21 22 23 4 X AUI PHY IP will be available in a future release of the Quartus II software Altera Corporation Implementing Protocols in Arria 10 Transceivers Needs a user created Soft IP for link training auto speed negotiation and sequencer functions PCS Direct support will be available in a future release of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software GI Send Feedback UG A10XCVR 2013 12 02 Protocol Transceiver IP Arria 10 Transceiver Protocols and PHY IP Support PCS Support Transceiver Configuration Rule 2 11 18 Protocol Prese 8G 4G 2G 1G Fibre Native PHY IP Standard Basic Custom User created Channel Standard PCS EDR Infiniband x1 x4 x12 Native
198. Parameters The 10M 100M 1GbE parameters allow you to specify options for the MII interface and the 1GbE data rate Table 2 88 10M 100M 1Gb Ethernet a opon T Deto Enable 1Gb Ethernet protocol On Off When you turn this option on the core includes the GMII interface and related logic Enable 10M 100Mb Ethernet On Off When you turn this option on the core includes functionality the MII PCS It also supports 4 speed mode to implement a 10M 100M interface to the MAC for the GbE line rate Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Speed Detection Parameters 2 113 A peton PHY ID 32 bits 32 bit value An optional 32 bit value that serves as a unique identifier for a particular type of PCS The identifier includes the following components e Bits 3 24 of the Organizationally Unique Identifier OUI assigned by the IEEE e 6 bit model number e 4 bit revision number If unused do not change the default value which is 0x00000000 PHY Core version 16 bits 16 bit value This is an optional 16 bit value identifies the PHY core version Speed Detection Parameters By selecting the Enable automatic speed detection option in the MegaWizard Plug In Manager the PHY IP includes the sequencer module which implements the Parallel Detect function as described in the Ethernet specification Selecting the speed detection option gives th
199. Parameters VEIG Standard PCS PMA interface width 10 FPGA fabric Standard TX PCS interface width 10 FPGA fabric Standard RX PCS interface width 10 low latency for GbE TX FIFO mode register_fifo for GbE with 1588 low latency for GbE RX FIFO Mode register_fifo for GbE with 1588 Enable Standard PCS low latency mode off Enable tx_std_pcfifo_full port On Off Enable tx_std_pcfifo_empty port On Off Enable rx_std_pcfifo_full On Off Enable rx_std_pcfifo_empty port On Off TX byte serializer mode RX byte deserializer mode Disabled Serialize x2 Disabled Deserialize x2 Enable TX 8B 10B encoder On Off Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for GbE and GbE with 1588 2 91 Parameters VELTS Enable TX 8B 10B disparity control On Off Enable RX 8B 10B decoder On Off gige for GbE RX rate match FIFO mode disabled for GbE with 1588 RX rate match insert delete ve pattern hex 0x000ab683 for GbE 0x00000000 for GbE with 1588 RX rate match insert delete ve pattern hex 0x000a257c for GbE 0x00000000 for GbE with 1588 Enable rx_std_rmfifo_full port On Off Enable rx_std_rmfifo_empty port On Off PCI Express Gen3 rate match FIFO mode Bypass Enable TX bit slip Off Enable tx_std_bitslipboundarysel port On Off
200. RBS generator and select a test pattern through the reconfiguration interface Use PRBS9 to test transceiver links with linear impairments and with 8B 10B Use PRBS15 for jitter evaluation Use PRBS23 or PRBS31 for jitter evaluation data dependent jitter of non 8B 10B links such as SDH SONET OTN jitter testers Most 40G 100G and 10G applications use PRBS31 for link evaluation Figure 5 43 PRBS Generator for Serial Implementation of PRBS9 Pattern So gt S1 G gt S4 e S5 S S8 Y v PRBS Output Note All supported PRBS generators are similar to the PRBS9 generator The square wave generator supports 64 bit PCS PMA interface widths It has a programmable n number of consecutive serial bit 1s and Os where n is 4 6 or 8 n defaults to 4 Figure 5 44 Generator for Square Wave Pattern Ld Program the value of n through the Transceiver and PLL Address Map TX Bit Slip The TX bit slip allows the word boundary to be controlled by tx_std_bitslipboundarysel The TX bit slip feature is used in applications such as CPRI which has a data rate greater than 6 Gbps The maximum number of the supported bit slips is PCS data width 1 and the slip direction is from MSB to LSB and from current to previous word Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Receiver Datapath 5 37 Receiver Datapat
201. RX PCS 8 16 16 32 interface width Enable Standard PCS low latency off off off mode Phase Compensation FIFO TX FIFO mode low_latency low_latency low_latency Enable fast TX FPGA Fabric interface Off Off Off RX FIFO Mode low_latency low_latency low_latency Enable tx_std_pcfifo_ 3 i Bai aid Optional Optional Optional Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for PCI Express 2 201 Enable tx_std_pcfifo_ Optional Optional Optional empty port eth oes Soe pee ee Optional Optional Optional WIL IL Enable rx_std_pcefifo_ Optional Optional Optional empty port Byte Serializer and Deserializer TX byte serializer mode Disabled Serialize x2 Serialize x2 Serialize x4 RX byte deserializer mode Disabled Serialize x2 Serialize x2 Serialize x4 8B 10B Encoder and Decoder Enable TX 8B 10B encoder Enabled Enabled Enabled Enable TX 8B 10B disparity On On On control Enable RX 8B 10B decoder Enabled Enabled Enabled Rate Match FIFO Rate Match FIFO mode PIPE PIPE PIPE a mat inser eelte Ve 0x0002f17 0x0002f17c 0x0002f17 pattern hex P Se 0x000d0e83 0x000d0e83 0x000d0e83 pattern hex Enable rx_std_rmfifo_ y f Fuld port Optional Optional Optional TEDE Saa eae Optional Optional Optional empty port Word Aligner and Bit Slip Enable TX bit slip off off off Enable tx_st
202. RX byte deserializer mode list Ensure that RX rate match FIFO mode is disabled Set the RX word aligner mode to bitslip Set the RX word aligner pattern length to 7 or 16 Note TX bitslip RX bitslip bit reversal and polarity inversion modes are supported TX Bit Slip To use the TX bit slip select the Enable TX bitslip and Enable tx_std_bitslipboundarysel port options This adds the tx_std_bitslipboundarysel input port The TX PCS automatically slips the number of bits specified by tx_std_bitslipboundarysel There is no port for TX bit slip If there is more than one channel in the design tx_std_bitslipboundarysel port becomes a bus in which each bit corresponds to one channel You can verify this feature by monitoring the rx_parallel_data port Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR s 2013 12 02 TX Polarity Inversion 2 243 The RX bit slip feature is optional and may or may not be enabled Figure 2 122 TX Bit Slip in 8 bit Mode tx_parallel_data 8 hbc tx_std_bitslipboundarysel 5 b00001 bit slip by 1 bit tx_std_bitslipboundarysel 00001 tx_parallel_data bc rx_parallel_data 5e Figure 2 123 TX Bit Slip in 10 bit Mode tx_parallel_data 10 h3bc tx_std_bitslipboundarysel 5 b00011 bit slip by 3 bits tx_std_bitslipboundarysel 00011 tx_parallel_data 3bc m_parallel_data 1e7 Figure 2 124 TX Bit Slip in 16
203. Reset Controller handles all transceiver reset sequencing and supports the following options e Separate or shared reset controls per channel in response to PLL lock activity e Separate controls for the TX and RX channels and PLLs e Synchronization of the reset inputs e Hysteresis for PLL locked status inputs e Configurable reset timing e Automatic or manual reset recovery mode in response to loss of PLL lock You should create your own reset controller if the Transceiver PHY Reset Controller IP does not meet your requirements especially when you require independent transceiver channel reset The following figure illustrates the typical use of the Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the transmit PLL Figure 4 8 Altera Transceiver PHY Reset Controller System Diagram Resetting Transceiver Channels Status Signals i ready Fix ready Transceiver PHY Instance tx_analogreset teat tx_digitalreset Transmitter Transmitter ese Controller rx_analogreset PCS PMA clock y IP Core rx_digitalreset e reset p rx_cal_busy Receiver Receiver rx_is_lockedtodata PCS PMA ll_tx_cal_bus CDR a _X_Cal_DuSy tx_cal_busy O asoj H E z sil ca bie You can logical OR the pil_cal_busy a and tx_cal_busy signals LI 2 pll_tx_cal_busy connects to the y controller s tx_cal_busy input port Transmit PLL
204. S Registers This topic describes the GMII PCS registers M 0x490 RESTART_ AUTO_ NEGOTIATION Set this bit to 1 to restart the Clause 37 Auto Negotiation sequence For normal operation set this bit to 0 which is the default value This bit is self clearing 12 RW AUTO_ Set this bit to 1 to enable Clause 37 Auto Negotiation NEGOTIATION_ The default value is 1 ENABLE 15 RW Reset Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines comma detection function and the 8B 10B encoder and decoder For normal operation set this bit to 0 This bit self clears Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 144 Arria 10 GMII PCS Registers UG A10XCVR 2013 12 02 LL LINK_STATUS A value of 1 indicates that a valid link is operating A value of 0 indicates an invalid link If link synchroniza tion is lost this bit is 0 3 R AUTO_ A value of 1 indicates that the PCS function supports NEGOTIATION_ Clause 37 Auto Negotiation 0x491 ABILITY 5 R AUTO_ A value of 1 indicates the following status NEGOTIATION_ fee 9 COMPLETE e The Auto Negotiation process is complete e The Auto Negotiation control registers are valid Full duplex mode enable for the local device Set to 1 for full duplex support 0x494 6 RW HD Half duplex mode enable fo
205. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations Transceiver mode TX RX Duplex TX Simplex RX Simplex Specifies the operational mode of the transceiver e TX RX Duplex Specifies a single channel that supports both transmit and receive capabilities e TX Simplex Specifies a single channel that supports only transmission e RX Simplex Specifies a single channel that supports only reception The default is TX RX Duplex Number of data 1 lt n gt Specifies the number of transceiver channels to be implemented The maximum number of channels available lt n gt depends on the package you select The default value is 1 Specifies the data rate in megabits per second Mbps channels Data rate lt valid Arria 10 Transceiver data rate gt The default value is 1250 Mbps Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 16 General and Datapath Parameters UG A10XCVR 2013 12 02 Enable reconfigu On Off ration between Standard and Enhanced PCSs When you turn this option on you can preconfigure both the Standard and Enhanced PCS datapaths and dynamically reconfigure between them The default value is Off Enable simplified On Off data interface By default all 128 bits are ports for the tx_parallel_data and rx_parallel_data buses regardless of the FP
206. Send Feedback UG A10XCVR 2013 12 02 How to Use NativeLink to Run a ModelSim Altera RTL Simulation 2 257 Table 2 155 Simulator Path Mentor Graphics ModelSim lt drive gt lt simulator install path gt win32aloem Windows Altera lt simulator install path gt bin Linux On Assignments menu click Settings 4 In the Category list under EDA Tool Settings select Simulation N In the Tool name list select your simulator Note ModelSim refers to ModelSim SE PE and DE These simulators use the same commands as QuestaSim ModelSim Altera refers to ModelSim Altera Starter Edition and ModelSim Altera Subscription Edition In the Output directory browse to the directory for your output files To map illegal HDL characters turn on Map illegal HDL characters To filter netlist glitches turn on Enable glitch filtering This option is not available for Arria 10 devices in the Beta release Complete the following steps to specify additional options for NativeLink automation a Turn on Compile testbench b Click Test Benches The Test Benches dialog box appears c Click New d Under Create new test bench settings for Test bench name type the testbench name For Top level module in the testbench type the top level module name These names should match the actual testbench module names e Under the Simulation period turn on Run simulation until all vector stimiuli are used f Click OK H
207. Specification Performing a Read to the Reconfiguration Interface Reading to the reconfiguration interface prompts the Avalon master to determine the current value at a specific address The read operation involves the following steps 1 Place a 10 bit feature address on the reconfig_address bus 2 Assert the reconfig_read signal After the reconfig_read signal asserts the reconfig_waitrequest signal always asserts for a numberof reconfig_clock cycles then deasserts This deassertion indicates the reconfig_readdata bus contains valid data Figure 6 1 Read Operation reconfig_clk reconfig_reset reconfig_address 119 reconfig_read reconfig_readdata XXXX y VALID Y XXXX reconfig_waitrequest reconfig_write reconfig_writedata XXXX Performing a Write to the Reconfiguration Interface Writing to the reconfiguration interface of either the Transceiver Native PHY or TX PLL allows an Avalon master to change the value at a specific address All writes performed with the reconfiguration interface must be a read modified write because two or more features may share the same reconfiguration address When two or more features share the same reconfiguration address one feature s data bits are interleaved with another feature s data bits Therefore you must always use read modified write and the correct address and data bits Alter
208. TX PLL CH3 6 Pack CH2 fPLL CH1 Master ATX cob PLL CHO CH5 fPLL CH4 Master ATX L CH3 6 Pack CH2 CH1 CHO Physical Channel For x8 configurations Altera recommends you choose a master channel that is a maximum of four channels away from the farthest slave channel Altera Corporation Logical Channel CH5 fPLL CH4 pes ATX PLL CH3 CH2 fPLL Physical Channel 6 Pack Master CGB 6 Pack Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Design Example 2 215 Figure 2 88 x4 Alternate Configuration The figure below shows an alternate way of placing 4 bonded channels In this case the logical PCS master channel number must be specified as 2 CH5 fPLL CH4 yey ATX PLE CH3 6 Pack CH2 TPL Master CH1 CGB ATX PLL CHO CHS 2 CH4 1 CH3 6 Pack CH2 fPLL CH1 Master ATX oe PLL CHO Logical Physical Channel Channel As indicated in the figures above the fitter picks either physical CH1 or CH4 as the PCS master in bonded configurations for PIPE Design Example The PIPE Design Example located on the Arria 10 Transceiver PHY Design Examples Wiki page demonstrates the connectivity between several IPs that form a complete PCIe design The example contains the following components e PHY Native PHY IP configured for PIPE Gen3 x8 mode e ATX PLL PLL us
209. TX PLL Clock Divider lt CMU PLL fPLL Serial Clock Parallel Clock Serial Clock Parallel and Serial Clock Parallel and Serial Clock Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Table 2 132 Channel Width Options for Supported Serial Data Rates TX PLL Selection for CPRI 2 217 Channel Width FPGA PCS Fabric Serial Data Rate 8 10 Bit Width 16 20 Bit Width Mbps Ses Sie ee aie N A 614 4 Yes N A N A 1228 8 Yes Yes Yes Yes 2457 6 N A Yes Yes Yes 3072 N A Yes Yes Yes 4915 2 N A N A N A Yes 6144 N A N A N A Yes 9830 4 N A N A N A Yes TX PLL Selection for CPRI Choose a transmitter PLL that fits your required data rate Table 2 133 TX PLL Supported Data Rates TX PLLs Supported Data Rate Mbps ATX 1228 8 2457 6 3072 4915 2 6144 9830 4 fPLL 1228 8 2457 6 3072 4915 2 6144 CMU 1228 8 2457 6 3072 4915 2 6144 Auto Negotiation When auto negotiation is required the channels initialize at the highest supported frequency and switch to successively lower data rates if frame synchronization is not achieved If your design requires auto negotiation choose a base data rate that minimizes the number of PLLs required to generate the clocks required for data transmission By selecting an appropriate base data rate you can change data rates by changing the lo
210. Third 12 Ordered Set bg datain T Dx y K K28 5 x D162 Y K28 5 Xx D16 2 x Dx y X daout X Dx y X K28 5 x D16 2 X Dx y X The following figure shows an example of rate match FIFO insertion in the case where one symbol must be inserted Because the rate match FIFO can only insert 12 ordered sets it inserts one I2 ordered set two symbols inserted Figure 2 32 Rate Match FIFO Insertion First 12 Ordered Set First 12 Ordered Set Second 12 Ordered Set rc dataout X Dx y xX K28 5 x D16 2 X K28 5 X D16 2 Xx datain x Dx y X K28 5 X D16 2 X K28 5 pis2 YD K285 X D16 2 Dx y x rx_std_rmfifo_full and rx_std_rmfifo_empty are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions The rate match FIFO does not delete code groups to overcome a FIFO full condition It asserts the rx_std_rmfifo_ful flag for at least two recovered clock cycles to indicate rate match FIFO full The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer Figure 2 33 Rate Match FIFO Full Condition tx_parallel_data 2D x 2E x 2F x X X X X rx_parallel_data 03 04 x 05 X X l X X rx_std_rmfifo_full oo The rx_std_rmfifo_full status flag indicates that the FIFO is full at this time The rate match FIFO does not insert code groups to overcome the FIFO empty condition It asserts the rx_std_rmfifo_empty flag for at least tw
211. When enabled the feedback connections are automatically handled by the PLL IP PMA interface width 8 10 16 20 32 Specifies PMA PCS interface width 40 64 Proper value must be selected for generating bonding clocks for Native PHY IP This value should match the PMA interface width selected for the Native PHY IP Table 3 9 fPLL Dynamic Reconfiguration Parameters and Settings Enable reconfiguration On Off Enables the PLL reconfiguration interface Configuration file prefix Enter the prefix name for the configuration files to be generated PLLs and Clock Networks Altera Corporation CJ Send Feedback fPLL IP UG A10XCVR 2013 12 02 Generate SystemVerilog package On Off Generates a SystemVerilog package file containing all file relevant parameters used by the PLL Generate C header file On Off Generates a C header file containing all relevant parameters used by the PLL Generate MIF Memory Initialize On Off Generates a MIF file that contains the current File configuration Use this option for reconfiguration purposes in order to switch between different PLL configurations Table 3 10 fPLL Clock Switch over Parameters and Settings Create a second input clock On Off Turn on this parameter to have a secondary clock pll_refclk1 attached to your fPLL that can switch with your original reference clock Second Reference Clock Specifies the 2nd reference clock frequency
212. When this parameter is not selected the ports are set to OFF internally reconfig_reset0 input reconfig__ Used to reset the Avalon interface clk0 reconfig_write0 input reconfig__ Active high write enable signal cl1k0 reconfig_read0 input reconfig__ Active high read enable signal eLO reconfig_address0 9 0 input reconfig_ 10 bit address bus used to specify clk0 address to be accessed for both read and write operations reconfig_ input reconfig__ 32 bit data bus Carries the write writedata0 31 0 c1k0 data to the specified address PLLs and Clock Networks Altera Corporation CJ Send Feedback 3 10 ATX PLL IP UG A10XCVR 2013 12 02 reconfig_ readdata0 31 0 output reco nfig_ cl1k0 32 bit data bus Carries the read data from the specified address reconfig_waitrequest0 output rece MELE clk0 Indicates when the Avalon interface signal is busy When asserted all inputs must be held constant pll_cal_busy output Asynchronous Status signal which is asserted high when PLL calibration is in progress OR this signal with tx_cal busy port before connecting to the reset controller IP mcegb_rst input Asynchronous Master CGB reset control If pll feedback compensation bonding mode is used deassert this reset at the same time as pll_powerdown If pll feedback compensation bonding is not being used then this port can be deasserted after p
213. X Standard PCS Data Control Status and Clocks rx_parallel_data lt n gt 128 170 Output Ex rx_clkout or coreclkin RX parallel data from the RX PCS to the FPGA fabric For each 128 bit word of rx_ parallel_data the data bits correspond to rx_parallel_data 7 0 when 8B 10B decoder is enabled and rx_parallel_ data 9 0 when 8B 10B decoder is disabled unused_rx_parallel_ Output data isc rx_clkout or coreclkin This signal specifies the unused data when you turn on Enable simplified data interface Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 56 Standard PCS and PMA Ports 2013 12 02 rx_clkout Output Clock FPGA fabric transceiver clock This clock times rx_parallel_data from the RX PCS to the FPGA fabric x_coreclkin Input Clock RX parallel clock that drives the read side clock of the RX FIFO Table 2 44 TX and RX FIFO tx_std_pcfifo_ Output tx_clkout or Indicates when the standard TX FIFO reaches full lt n gt 1 0 tx_ the full threshold coreclkin tx ste petito Output tx_clkout or Indicates when the standard TX FIFO reaches empty lt n gt 1 0 tx the empty threshold coreclkin rx_std_pcfifo_ Output rx_clkout or Indicates when the standard RX FIFO reaches full lt n gt 1 0 EX the full threshold coreclkin rz ste petilo Output rx_clkout or Indicates when the standard TX FIFO re
214. You cannot enable the PRP and PRBS generators at the same time Refer to the Transceiver and PLL Address Map for configuration details Scrambler The scrambler randomizes data to create transitions to DC balance the signal and help CDR circuits The scrambler uses a x x 1 polynomial and supports both synchronous scrambling used for Interlaken and asynchronous also called self synchronized scrambling used for the 1OGBASE R protocol The asynchronous self synchronizing mode does not require an initialization seed Except for the two sync header bits in each 66 bit data block the entire 64 bit payload is scrambled by feeding it into a linear feedback shift register LFSR continuously to generate scrambled data while the sync header bits bypass the scrambler The initial seed is set to all 1s You can change the seed for the 1OGBASE R protocol using the Native PHY IP MegaWizard Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR ae 2013 12 02 Interlaken Disparity Generator 5 21 Figure 5 26 Asynchronous Scrambler in Serial Implementation IN 3 e SO gt S1 S2 S38 e S39 S S56 S57 v OUT In synchronous mode the scrambler is initially reset to different programmable seeds on each lane The scrambler then runs by itself Its current state is XOR d with the data to gene
215. _ Lane 4 data data 39 32 xgmii_rx_dc 44 xgmii_sdr_ctrl1 4 Lane4 control xgmii_rx_dc 52 45 xgmii_sdr_ Lane 5 data data 47 40 RGM rz dels xgmii_sdr_ctrl 5 Lane 5 control xgmii_rx_dc 61 54 xgmii_sdr_ Lane 6 data data 55 48 xgmii_rx_dc 62 xgmii_sdr_ctrl 6 Lane6 control xgmii_rx_dc 70 63 xgmii_sdr_ Lane 7 data data 63 56 zomi ex devi xgmii_sdr_ctrl 7 Lane7 control Serial Data Interface This topic describes the serial data interface rx_serial_data Input RX serial input data tx_serial_data Output TX serial output data Control and Status Interfaces The XGMII and GMII interface signals drive data to and from PHY Table 2 96 Control and Status Signals led_char_err Output Synchronous to rx_ 10 bit character error Asserted for one rx_clkout_lg clkout cycle when an erroneous 10 bit character is detected led link Output Synchronous to rx_ When asserted indicates successful link synchroniza clkout tion led_disp_err Output Synchronous to rx_ Disparity error signal indicating a 10 bit running clkout disparity error Asserted for one rx_clkout_lg cycle when a disparity error is detected A running disparity error indicates that more than the previous and perhaps the current received group had an error led_an Output Synchronous to rx_ Clause 37 Auto negotiation status The PCS function elkout asserts this signal when auto negotiation completes Altera Corporation Implem
216. _enh_frame status output port frame port Enable tx_enh_ On Off Enables the tx_enh_frame_diag_status 2 bit input port frame_diag_ status port Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 26 Enhanced PCS Parameters 2013 12 02 Enable tx_enh_ On Off Enables the tx_enh_frame_burst_en input port frame_burst_en port Table 2 12 Interlaken Frame Synchronizer Parameters Enable Interlaken On Off When you turn this option on the Enhanced PCS frame frame synchro synchronizer is enabled nizer Frame synchro 5 8192 Specifies the metaframe length of the frame synchronizer nizer metaframe length Enable rx_enh_ On Off Enables the rx_enh_frame status output port frame port Enable rx_enh_ On Off Enables the rx_enh_frame_lock output port frame_lock port Enable rx_enh__ On Off Enables the rx_enh_frame_diag_status port frame_diag_ status port Table 2 13 Interlaken CRC32 Generator and Checker Parameters Enable Interlaken On Off When you turn this option on the TX Enhanced PCS datapath TX CRC 32 enables the CRC32 generator function Generator Enable Interlaken On Off When you turn this option on the error insertion of the interlaken RX CRC 32 CRC 32 generator is enabled Error insertion is cycle accurate generator error When this feature is enabled the assertion of tx_cont rol 8 insertion or tx_err_ins signal causes the CRC cal
217. _rx_d clkout MII Data Interface mili etx Al3O0 Input Synchronousto TX data to be encoded and sent to the link partner Synchronized to the tx_pma_clkout clock Cepam clkout mii_tx_en Input Synchronousto When asserted indicates the start of a new frame t mii_tx_enshould remain asserted until the last zpra nibble of data on the frame is present on mii_tx_ clkout d 3 0 mii_tx_err Input Synchronousto When asserted it indicates an error in the frame mii_tx_en should also be asserted for PHY to e transmit invalid data clkout mii_tx_clkena Output Clock signal MII TX clock enable This clock frequency has the following frequencies e 25 MHz For an effective rate of 100 Mbps e 2 5 MHz For an effective rate of 10 Mbps mii_tx_clkena__ Output Clock signal MII RX clock enable when the FPGA fabric runs at half_rate half the PCS frequency This clock frequency has the following frequencies e 12 5 MHz For an effective rate of 100 Mbps e 1 25 MHz For an effective rate of 10 Mbps Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 XGMII Mapping to Standard SDR XGMII Data 2 163 mii_rx_d Output Synchronous to rx_pma_ clkout RX Data received from link partner Synchronized to the rx_pma_clkout clock maL ise en Output Synchronous to When asserted indicates that data onmii_rx_ d 3 0 is valid rx_pma_ clkou
218. _seed_a 55 48 Seed A value bit 55 48 r_tx_seed_a 57 56 Seed A value bit 57 56 0x7A r_tx_seed_b 7 0 Seed B value bit 7 0 0x7B r_tx_seed_b 15 8 Seed B value bit 15 8 0x7C r_tx_seed_b 23 16 Seed B value bit 23 16 0x7D r_tx_seed_b 31 24 Seed B value bit 31 24 0x7E r_tx_seed_b 39 32 Seed B value bit 39 32 0x7F r_tx_seed_b 47 40 Seed B value bit 47 40 0x80 r_tx_seed_b 55 48 Seed B value bit 55 48 0x81 r_tx_seed_b 57 56 Seed B value bit 57 56 2 local faults r_tx_data_pat_sel O s 0x82 Pseudo Random r_tx_test_pat_sel Square Wave r_tx_test_en 0x97 r_rx_test_en 0xAC r_rx_test_pat_sel eee Square wave Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback Altera Corporation UG A10XCVR 6 2 Enabling PRBS Pattern Inversion 2013 12 02 Reconfiguration Reconfiguration Attribute Name Bit Encoding Description Address HEX Bit random_ err_cnt 7 0 Error count o Enabling PRBS Pattern Inversion You can enable pattern inversion for PRBS data leaving or entering the PRBS data pattern generator and checker respectively The following table shows the offsets to invert the either the generator or checker To invert the PRBS pattern leaving the PRBS generator or checker follow these steps e To invert the PRBS pattern leaving the PRBS generator perform a read modify write to bit 2 with a value of 1 b1 to offset 0x7 e To invert the PRBS pattern leaving the PRBS checker perform a
219. _sim folder lt pll ip instance name gt qip file and lt pll ip instance name gt v file The lt pll ip instance Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 6 Reset Controller 2013 12 02 name gt file is the top level design file for the PLL IP and the folders contain lower level design files used for simulation and compilation Reset Controller There are two methods to reset the transceivers in Arria 10 devices e Using the Altera Transceiver PHY Reset Controller IP Core e Using your own User Coded Reset Controller Related Information Resetting Transceiver Channels on page 4 1 Create Reconfiguration Logic Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLLs settings during device operation You need to create an Avalon master in order to access the dynamic reconfiguration registers using the Avalon interface The Avalon MM master enables PCS dynamic switching PLL and channel reconfiguration All the PMA parameters such as VOD differential output voltage swing and pre emphasis can be dynamically adjusted through the Avalon MM reconfiguration registers by the user generated Avalon MM master Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for details on dynamic reconfiguration Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 6 1 Connect PHY IP to PLL IP and Reset Cont
220. a Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 Reconfiguring Channel and PLL Blocks 6 5 Read modify write operation involves the following steps 1 Place a 10 bit feature address onthe reconfig_address bus 2 Assert the reconfig_read signal and storing the read value Wait for reconfig_waitrequest to transition from 1 to 0 before reading the value on the reconfig_readdata bus 3 From the read value modify only the necessary bits by masking out the non relevant bits Store this new value internally using the additional steps below Wait for the high to low transition on the waitrequest signal to indicate valid data is on the readdata bus 4 Place the same 10 bit feature address from step 1 on the reconfig_address bus and place the new 32 bit value on the reconfig_writedata bus 5 Assert the reconfig_write signal 6 Reset the transceiver channel as appropriate Figure 6 2 Write Operation reconfig_clk reconfig_reset reconfig_waitrequest reconfig_address x 119 reconfig_read reconfig_readdata 00000000 reconfig_write reconfig_writedata x 00000000c Reconfiguring Channel and PLL Blocks Certain systems may require that your transceiver channels or PLLs take on a different data rate or protocol specification For example the 8b 10b encoder may be enabled under one mode of operat
221. a D 6q 64 8 A x 3 f a 8 E 156 25 MHz p 156 25 MHz ke from XGMIL Parallel Clack i 257 8125 MHz 3 D ONGA 10GBASE R BER Checker Clock Generation Block CGB ATX PLL Clock Divider 4 PLL L a CMU PLL Parallel Clock Serial Clock paiaal and Sonar closes Serial Clock Parallel and Serial Clocks Input Reference Clock Notes 1 Value based on the the clock division factor chosen 2 Value calculated as data rate FPGA fabric PCS interface width 3 Value calculated as data rate PCS PMA interface width 4 This block is in Phase Compensation mode for the 10GBASE R configuration and register mode for the 1OGBASE R with 1588 configuration 5 This block is in 10GBASE R mode for the LOGBASE R configuration and register mode for the 10GBASE R with 1588 configuration Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC 2 95 2013 12 02 Figure 2 39 Transceiver Channel Datapath and Clocking for
222. a read access Low order 16 bits of the 21 bit auto negotiation link timer Each timer step corresponds to 8ns assuming a 125 MHz clock The total timer corresponds to 16 ms The reset value sets the timer to 10 ms for hardware mode and 10 us for simulation mode 0x4A3 4 0 AN link timer 4 0 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback High order 5 bits of the 21 bit auto negotiation link timer Altera Corporation 2 174 PMA Registers UG A10XCVR 2013 12 02 a 0x4A4 IT_ENA Determines the PCS function operating mode Setting this bit to 1b l enables SGMII mode Setting this bit to 1b 0 enables 1000BASE X gigabit mode RW USE_SGMII_AN In SGMII mode setting this bit to 1b l causes the PCS to be configured with the link partner abilities advertised during auto negotiation If this bit is set to 1b 0 the PCS function should be configured with the SGMII_SPEED and SGMII_DUPLExX bits 3 2 RW SGMII_ SPEED SGMII speed When the PCS operates in SGMII mode SGMII_ENA 1 and is not programmed for automatic configuration USE_SGMII_AN 0 the following encodings specify the speed e 2 b00 10 Mbps e 2 b01 100 Mbps e 2 b10 Gigabit e 2 b11 Reserved These bits are not used when SGM USE_SGM Oor _ENA _AN 1 PMA Registers The PMA registers allow you to reset the PMA customize the
223. a source interface The frequency is 125 MHz rx_clkout_1g Output GMII RX clock for the 1G RX parallel data source interface The frequency is 125 MHz rz Coreclkin ig Input Clock to drive the read side of the RX phase compensation FIFO in the Standard PCS The frequency is 125 MHz tx_coreclkin_1g Input Clock to drive the write side of the TX phase compensation FIFO in the Standard PCS The frequency is 125 MHz Li weir _ellk_ig Input Reference clock for the PMA block for the 1G mode Its frequency is 125 or 62 5 MHz pll_ref_clk_10g Input Reference clock for the PMA block in 10G mode Its frequency is 644 53125 or 322 265625 MHz pll_powerdown_lg Input Resets the 1Gb TX PLLs Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Parameterizing the 1G 10GbE PHY 2 155 pll_powerdown_10g Input Resets the 10Gb TX PLLs tx_analogreset Input Resets the analog TX portion of the transceiver PHY tx_digitalreset Input Resets the digital TX portion of the transceiver PHY rx_analogreset Input Resets the analog RX portion of the transceiver PHY rx_digitalreset Input Resets the digital RX portion of the transceiver PHY usr_an_lt_reset Input Resets only the AN and LT logic This signal is only available for the LOGBASE KR variants usr_seq_reset Input Resets the sequencer Initiates a PCS reconfigu
224. a0 31 0 clk0 data from the specified address reconfig_waitrequest0 output reconfig__ Indicates when the Avalon c1k0 interface signal is busy When asserted all inputs must be held constant pll_cal_busy output Asynchronous _ Status signal that is asserted high when PLL calibration is in progress Connect this port by OR ing it with tx_cal_busy port on the reset controller IP Related Information Avalon Interface Specifications The ports related to reconfiguration are compliant with the Avalon Specification Refer to the Avalon Specification for more details about these ports Input Reference Clock Sources The transmitter PLL and the clock data recovery CDR block need an input reference clock source to generate the clocks required for transceiver operation The input reference clock must be stable and free running at device power up for proper PLL operation Arria 10 transceiver PLLs have four possible input reference clock sources e Dedicated reference clock pins e Receiver input pins e The output of another PLL with PLL cascading e Reference clock network Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Dedicated Reference Clock Pins 3 25 Figure 3 5 Input Reference Clock Sources Reference Clock Network A Input Reference Dedicated Clock ATX PLL refclk m lt d Channel PLL Serial Clock i m
225. a10_reconfig_parameters sv all options required for the base configuration such contains all transceiver addresses as data rate PCS options and PMA options and their bit value for that Reconfiguring between Standard PCS and Enhanced transceiver configuration PCS requires Enable reconfiguration between Or Standard and Enhanced PCS datapaths be enabled The Transceiver configuration rules define the initial e lt PLL Modified Instance Name gt mode of the PHY instance reconfig altera_xcvr_ lt type gt _pll e Enable all ports to be used by the modified configura a10_reconfig_parameters sv tion contains all PLL addresses and e Onthe Dynamic Reconfiguration tab turnonEnable their bit value for that PLL dynamic reconfiguration and specify the same configuration Configuration Options as the base instance Note You can generate the base and modified instance files in the same or different folders If you use the same folder then each configuration instance name must be unique Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 Step 2 Determine Address Offsets and Differences 6 7 Related Information Using Configuration Files on page 6 7 Step 2 Determine Address Offsets and Differences Use a text editor to compare the differences between the base and modified Transceiver Native PHY or PLL instance files The differences between these two files indicate
226. aWizard Plug In Manager GUI lists the available choices Use the following data rates and configuration settings for PLL IPs e Transceiver PLL Instance 0 ATX PLL with output clock frequency of 6 25 GHz e Enable the Master CGB and bonding output clocks e Transceiver PLL instance 1 ATX PLL with output clock frequency of 5 1625 GHz e Transceiver PLL instance 2 ATX PLL with output clock frequency of 5 1625 GHz e Transceiver PLL instance 3 ATX PLL with output clock frequency of 4 9 GHz Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Mix and Match Example 3 51 Transceiver PLL instance 4 PLL with output clock frequency of 0 625 GHz e Select the Use as Transceiver PLL option Transceiver PLL instance 5 PLL with output clock frequency of 2 5 GHz e Select Enable PCIe clock output port option e Select Use as Transceiver PLL option e Set Protocol Mode to PCIe Gen2 e Select the Use as Core PLL option e Set the Desired frequency to 500 MHz with a phase shift of 0 ps Transceiver PLL instance 6 ATX PLL with output clock frequency of 4 GHz e Enable Master CGB and bonding output clocks e Select Enable PCIe clock switch interface option e Set Number of Auxiliary MCGB Clock Input ports to 1 Native PHY IP Instances In this example four Transceiver Native PHY IP instances and four 1OGBASE KR PHY IP instances are used Use the following data rates and configuration settings for the PHY IPs
227. a_div_clkout clkout division 66 output clock when this port is enabled factor tx_pma_elecidle On Off Enables the tx_pma_elecidle port When you assert this port port the transmitter is forced into an electrical idle condition This port has no effect when the transceiver is configured for PCI Express Enable tx_pma_ On Off Enables the tx_pma_qpipullup control input port Use this qpipullup port port only for Quick Path Interconnect QPI applications QPI Enable tx_pma_ On Off Enables the tx_pma_qpipulldn control input port Use this qpipulldn port port only for QPI applications QPI Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 20 PMA Parameters UG A10XCVR 2013 12 02 Enable tx_pma_ On Off Enables the tx_pma_t xdetectrx control input port The txdetectrx port receiver detect block in TX PMA detects the presence of a receiver QPI at the other end of the channel After receiving tx_pma_ txdetectrx request the receiver detect block initiates the detection process Use this port only in QPI applications Enable tx_pma_ On Off Enables the t x_rxfound status output port The receiver detect rxfound port QPI block in TX PMA detects the presence of a receiver at the other end by using tx_pma_txdetectrx input The tx_pma_ rxfound reports the status of the detection operation Use this port only in QPI applications Table 2 7 RX PMA Parameters N
228. aches empty lt n gt 1 0 EX the empty threshold Gore cules Table 2 45 Rate Match FIFO rx_std_rmfifo_full lt n gt Output Asynchronous Rate match FIFO full flag When asserted the 1 0 rate match FIFO is full You must synchronize this signal This port is only used for GigE mode rx_std_rmfifo_empty lt n gt Output Asynchronous Rate match FIFO empty flag When asserted 120 match FIFO is full You must synchronize this signal This port is only used for GigE mode Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS and PMA Ports 2 57 rx_rmfifostatus lt n gt 1 0 Output Asynchronous Indicates FIFO status The following encodings are defined e 2 b00 Normal operation e 2 b01 Deletion rx_std_rmfifo_full 1 e 2 b10 Insertion rx_std_rmfifo_ empty 1 e 2 b11 Full rx_rmfifostatus isa part of rx_parallel_data rx_ rmfifostatus corresponds to rx_ parallel_data 14 13 Table 2 46 8B 10B Encoder and Decoder tx_forcedisp lt n gt lt w gt lt s gt a120 Input Asynchronous This signal allows you to force the disparity of the 8B 10B encoder When 1 b1 forces the disparity of the output data to the value driven on tx_dispval When 1 b0 the current running disparity continues tx_forcedisp is a part of tx_parallel_data tx_ forcedisp corresponds totx_parallel_ data 9 t
229. acting with the Reconfiguration Inert ace ivissigsvacsivzieenccsueavicnwoiats lt anerarnisnseasismavcacesternenasrGawlerseinted 6 4 Performing a Read to the Reconfiguration Interacts ssscsvisescccscaisscnssenss catseaeatacedsicesensoassensuvenses 6 4 Performing a Write to the Reconfiguration Intertace ca ssscnsssccdssssossvsssarietaesistneswash sossacesseasdastees 6 4 Reconfiguring Channel and PLL BIOCks ccacarciinaiinnniindcutnwaneaaien mn uunaaneannd 6 5 Step 1 Generate Required Confiauration PICS jsisesicssasssicaapiciocserectapachsausausbicvusrasbiaddelanisdtsnagees 6 5 Step 2 Determine Address Offsets and Ditkerences sisi cssicsscsisecassssesscesccicaraniesaspnsceiustiacesacsinsed 6 7 Step 3 Perform Redd Mody W tes cvssccscarssachveassucdadesetviqessanveieivecaenioverachaahapiniavaavnaseraatianesbannes 6 7 Step 4 Reset Transceiver Cama els isi ccswssassssassannandiaasscatsnasdsswasavunea cusnaivaandendusal dacbuabanapavlonstagnicas 6 7 Using Config ration Piles sic sascsaaessunnsaneceitesieecsliuaicaniiiigadsbuieudeaieamuueaelsoangueneanmaunaues 6 7 Altera Corporation TOC 6 Arria 10 Transceiver PHY User Guide Transmitter PLL Sw tc isr ss sssitncssussacesasusoaastastisvastsasoiduspekianctsaivepaitawa ns assroaasisSeaarsavaasnespassaespaieei atau 6 9 Switching Reference CGS siise cerca ace rcs add E E AEA E EEE EE aE EEEa 6 10 ATX Reference Clock Swit GG sna tsns decbpvcinannceasassechacsecea ana aa a 6 10 fPLL Reference Clock Switching
230. age 5 1 For more information about PMA architecture Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks PLLs on page 3 3 PLL architecture and implementation details Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details Standard PCS and PMA Ports on page 2 52 Port definitions for the Transceiver Native PHY Standard Datapath Native PHY IP Parameter Settings for GbE and GbE with 1588 Table 2 68 General and Datapath Options The first two sections of the MegaWizard Plug In Manager for the Native PHY IP provide a list of general and datapath options to customize the transceiver Parameter VEIG Device speed grade fastest Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for GbE and GbE with 1588 2 89 error Message level for rule violations message GbE for GbE Transceiver configuration rules i GbE 1588 for GbE with 1588 TX RX Duplex Transceiver mode TX Simplex RX Simplex Number of data channels 1 to 96 Data rate 1250 Mbps Enable reconfiguration between Standard and Enhanced PCSs On Off Enable simplified data interface On Off Table 2 69 TX PMA Parameters Parameter Value TX channel bonding mode Not bonded TX local clock division factor 1 2 4 8 Number of TX PLL
231. ake changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO eS RYA 101 Innovation Drive San Jose CA 95134
232. al to other receiver PCS blocks down the receiver datapath and to the FPGA fabric Note The block synchronizer is designed in accordance with Interlaken Protocol specification as described in Figure 13 of Interlaken Protocol Definition v1 2 and 10GBASE R protocol specification as described in IEEE 802 3 2008 clause 49 Interlaken Disparity Checker The Interlaken disparity checker examines the received inversion bit inserted by the far end disparity generator to determine whether to reverse the inversion process of the Interlaken disparity generation Note The Interlaken disparity checker is available to implement the Interlaken protocol Descrambler The descrambler block descrambles received data to regenerate unscrambled data using the x x 1 polynomial Like the scrambler it operates in asynchronous mode or synchronous mode Related Information Scrambler on page 5 20 Interlaken Frame Synchronizer The Interlaken frame synchronizer delineates the metaframe boundaries and searches for each of the framing layer control words Synchronization Scrambler State Skip and Diagnostic When four consecutive synchronization words have been identified the frame synchronizer achieves the frame locked state Subsequent metaframes are then checked for valid synchronization and scrambler state words If four consecutive invalid synchronization words or three consecutive mismatched scrambler state words are Altera Corporation Arria 10
233. al feature reverses the order of the data received from the PMA It is performed at the output of the Word Aligner and is available even when the Word Aligner is disabled If the data received from the PMA is a 10 bit data the bit reversal feature switches bit 0 with bit 9 bit 1 with bit 8 and Altera Corporation Arria 10 Transceiver PHY Architecture GJ Send Feedback UG A10XCVR 2013 12 02 Word Aligner RX Byte Reversal Feature 5 41 so on For example if the 10 bit data is 1000010011 the bit reversal feature when enabled changes the data to 1100100001 Word Aligner RX Byte Reversal Feature The RX byte reversal feature is available only when the PCS PMA interface width is 16 bits or 20 bits This feature reverses the order of the data received from the PMA RX byte reversal reverses the LSByte of the received data with its MSByte and vice versa If the data received is 20 bits bits 0 9 are swapped with bits 10 20 so that the resulting 20 bit data is 10 20 0 9 For example if the 20 bit data is 11001100001000011111 the byte reversal feature changes the data to 10000111111100110000 RX Polarity Inversion Feature The RX polarity inversion feature inverts each bit of the data received from the PMA If the data received is a 10 bit data Bit 0 content is inverted to its complement bit 0 bit 1 is inverted to its complement bit 1 bit 2 is inverted to its complement bit 2 and so on For example if the
234. al_clk port of the PLL instance 4 ATX PLL at 4 9 GHz This connection uses the x1 clock line within the transceiver bank e Connect the 1 25 Gbps Gigabit Ethernet non bonded PHY IP instance to the tx_serial_clk port of the PLL instance 5 Make this connection twice one for each channel This connection uses the x1 clock line within the transceiver bank e Connect the PCIe Gen3 bonded group of 8 channels as follows e Connect the tx_bonding_clocks of the PHY IP to the tx_bonding_clocks port of the Transceiver PLL Instance 6 Make this connection for each of the 8 bonded channels e Connect the pipe_sw_done of the PHY IP to the pipe_sw port of the transceiver PLL instance 6 e Connect the p1l_pcie_clk port of the PLL instance 5 to the PHY IP s pipe_hclk_in port e Connect tx_serial_clk port of the PLL instance 5 to the mcgb_aux_c1k0 port of the PLL instance 6 This connection is required as a part of the PCle speed negotiation protocol Altera Corporation PLLs and Clock Networks CJ Send Feedback Resetting Transceiver Channels 2013 12 02 UG A10XCVR X lt Subscribe QC Send Feedback To ensure that transceiver channels are ready to transmit and receive data you must properly reset the transceiver PHY The recommended reset sequence ensures that the physical coding sublayer PCS and physical medium attachment PMA in each transceiver channel initialize and function correctly Figure 4 1 Typical Transceive
235. alculated as data rate 2 The PMA runs on a dual data rate clock In low latency datapath modes the transmitter and receiver FIFOs are always enabled Depending on the targeted data rate you can optionally bypass the byte serializer and deserializer blocks Related Information Arria 10 Standard PCS Architecture on page 5 31 Word Aligner Manual Mode 1 Set the RX word aligner mode to Manual PLD controlled 2 Set the RX word aligner pattern length option according to the PCS PMA interface width 3 Enter a hexadecimal value in the RX word aligner pattern hex field This mode adds rx_patterndetect and rx_syncstatus You can select the Enable rx_std_wa_patternalign port option to enable rx_std_wa_patternalign An active high on rx_std_wa_patternalign re aligns the word aligner one time Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 234 Word Aligner Manual Mode 2013 12 02 Note e rx_patterndetect is asserted whenever there is a pattern match e xrx_syncstatus is asserted after the word aligner achieves synchronization e rx_std_wa_patternalign isalso asserted to re align and re synchronize e Ifthere is more than one channel in the design rx_patterndetect rx_syncstatus and rx_std_wa_patternalign become busses in which each bit corresponds to one channel You can verify this feature by monitoring rx_parallel_data Figure 2 102 Manual Mode when the PCS PMA Interface Width i
236. alignment The block is realigned to the new block boundary following the receipt of a SKP Ordered Set as it can be of variable length Rate Match FIFO In asynchronous systems the upstream transmitter and local receiver can be clocked with independent reference clocks Frequency differences in the order of a few hundred PPM can corrupt the data when latching from the recovered clock domain to the local receiver reference clock domain The rate match FIFO compensates for small clock frequency differences between these two clock domains by inserting or removing SKP symbols in the data stream to keep the FIFO from going empty or full respectively The PCI Express 3 0 base specification defines that the SKP Ordered Set OS can be 66 98 130 162 or 194 bits long The SKP OS has the following fixed bits 2 bit Sync 8 bit SKP END and a 24 bit LFSR 34 Bits The Rate Match Clock compensation module adds or deletes the 4 SKP characters 32 bit to keep the FIFO from going empty or full respectively This module monitors the sk ip_found signal from the block sync module and if the FIFO is nearly full deletes the 4 SKP characters 32 bit by disabling write whenever a SKP is found If the FIFO is nearly empty the design waits for a SKP Ordered Set to start and then stops reading the data from the FIFO and inserts a SKP in the outgoing data The actual FIFO core memory element is in the Shared Memory block in the PCS channel Figure 5 52 Rate Matc
237. alon Memory Mapped Avalon MM slave interface provides access to PCS registers The PMA receives and transmits serial data Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY IP with FEC Option 2 105 Figure 2 50 Top Level Modules of the 1G 10GbE PHY MegaCore Function Altera Device with 10 3125 Gbps Serial Transceivers 1G 10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257 8 MHz TX Serial Be F TA ee ae Data 1G 10 Gb TolFi i Ethernet Ethernet orrom Hard PCS 1G 10Gb RX XGMII Data E 40 64 BEAK bes Reto Ethernet MAC TX GMII MII Data 1Gb Serial ata Optional 125 MHz Ethernet tes beard RX GMII Data pane RX Latency al Adjust 1G and 10G Link Status 322 265625 MHz or 644 53125 MHz Reference Clock Optional PCS Reconfig gt Request To From Modules in the PHY MegaCore Avalon MM E 125 MHz PHY Management or Reference Clock Interface TX PLL For 1 GbE Legend EA se Red With FEC Option An Avalon Memory Mapped Avalon MM slave interface provides access to the 1G 10GbE PHY IP Core registers These registers control the functions of the blocks shown in the above figure The Backplane Ethernet 1OGBASE KR PHY IP includes the following new modules to enable operation over a backplane e Link Training LT The LT mechanism allows the 1
238. ame gt Configura Transceiver Native PHY for the Native PHY Or reconfig altera_xcvr_native_a10 tion select one of the supported transmit PLL IP cores reconfig_parameters sv contains all under PLL Enable all options required for the base transceiver addresses and their bit configuration such as data rate PCS options and value for that transceiver configura PMA options tion e Enable all ports to be used by the modified configura oy tion For example if the bitslip feature is not required in the base configuration but required in modified lt PLL Base Instance Name gt configuration then you must enable the tx_std_ reconfig altera_xcvr_ lt type gt _pll bislipboundarysel port Reconfiguring between a10_reconfig_parameters sv Standard PCS and Enhanced PCS requires Enable contains all PLL addresses and reconfiguration between Standard and Enhanced their bit value for that PLL PCS datapaths be enabled The Transceiver configuration configuration rules define the initial mode of the PHY instance e Onthe Dynamic Reconfiguration tab turn on Enable dynamic reconfiguration and specify the Configura tion Options This flow uses the Generate SystemVerilog package file option Modified e Click Interfaces gt Transceiver PHY gt Arria 10 e lt Native PHY Modified Instance Configura Transceiver Native PHY Or select one of the Name gt reconfig altera_xcvr_native_ tion supported transmit PLL IP cores under PLL Enable
239. and phase relationship detector reaction times can be too long for some applications that require faster CDR lock time You can manually control the CDR to reduce its lock time using two optional input ports r x_set_locktoref and rx_set_locktodata Table 5 2 Relationship Between Optional Input Ports and the CDR Lock Mode rx_set_locktoref rx_set_locktodata CDR Lock Mode 0 0 Automatic Manual RX CDR LTR Manual RX CDR LTD Deserializer The deserializer block clocks in serial input data from the receiver buffer using the high speed serial recovered clock and deserializes the data using the low speed parallel recovered clock The deserializer forwards the deserialized data to the receiver PCS or FPGA fabric The deserializer supports the following deserialization factors 8 10 16 20 32 40 and 64 Altera Corporation Arria 10 Transceiver PHY Architecture J Send Feedback UG A10XCVR The deserializer block sends out the LSB of the input data first LSB DO gt Deserializer 2013 12 02 Figure 5 16 Deserializer Block Diagram Serial Data gt Dn re o o D2 gt D1 gt Loopback Serial Parallel Clock Clock The Arria 10 PMA supports serial diagnostic and reverse loopback paths Figure 5 17 Serial Loopback Path Loopback 5 13 g N Parallel gt Data The serial loopback path sets the CDR to recover th
240. annel in a non bonded configuration when the rate matcher is used e single rx_clkout 0 for all receiver channels in a bonded configuration for both cases when rate matcher is used and when rate matcher is not used PLLs and Clock Networks Altera Corporation CJ Send Feedback p UG A10XCVR 3 38 Channel Bonding 2013 12 02 You can clock the receiver datapath interface using either one of the following methods e Quartus II selected receiver datapath interface clock e User selected receiver datapath interface clock Channel Bonding For Arria 10 devices two types of bonding modes are available e PMA bonding e PMA and PCS bonding PMA bonding refers to the minimization of skew across the PMA channels Only the PMA portion of the transceiver datapath is skew compensated while the PCS is not skew compensated x6 xN clock networks or PLL feedback compensation are used for skew compensation in PMA bonding In PMA and PCS bonding both the PMA and the PCS blocks of the transceiver datapath are skew compensated For PCS bonding a master PCS channel provides the synchronized and skew compensated control signals such as the FIFO reset signals to each of the slave channels and ensures minimum skew across the bonded channel group Skew Calculations To calculate the maximum skew between the channels the following parameters are used e PMA to PCS datapath interface width S e Maximum difference in number of parallel clock cycles
241. ansceiver banks require PLLs in the same bank Currently the Quartus II software version 13 1 for Arria 10 devices does not support PMA bonding for 1OGBASE KR PHY IP Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 148 Design Example Design Example Altera provides a MAC and PHY design example and a PHY only design example to assist you in integrating your Ethernet PHY IP into your complete design UG A10XCVR 2013 12 02 The MAC and PHY design example instantiates the 1G 10GbE PHY IP along with the 1G 10G Ethernet MAC and supporting logic It is part of the Quartus II installation and is located in the lt quartus2_install_dir gt ip subdirectory For more information about this example design refer to the Ethernet MAC MegaCore Function User Guide The PHY only design example instantiates the 1G 10GbE and 10GBASE KR PHY IP and its supporting logic This design example is available on the Altera Wiki The following figure shows the block diagram of the 1G 10GbE PHY only design example The design example default configuration includes two channels for Backplane Ethernet and two channels for line side 1G 10G applications Figure 2 57 PHY Only Design Example with Two Backplane Ethernet and Two Line Side 1G 10G Ethernet Channels NF_DE_WRAPPER Management Master ISSP Clock and Reset JTAG to Avalon MM w Master XGMII CLK FPLL
242. ansmitting data This function allows you to reverse the order of bytes that were erroneously swapped The PCS can swap the ordering of both 8 bit and 10 bit words When the PCS to PMA interface width is 16 or 20 bits the PCS can swap the ordering of the individual 8 bit or 10 bit words This option is not valid under some Transceiver configuration rules Enable TX On Off When you turn this option on the tx_std_polinv port polarity inversion controls polarity inversion of TX parallel data to the PMA When you turn on this parameter you also need to turn on Enable tx_ polinv port Enable tx_polinv On Off When you turn this option on the tx_polinv input control port port is enabled You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout Enable RX bit On Off When you turn this option on the word aligner reverses RX reversal parallel data The received RX data bit order is reversed to MSB to LSB rather than the normal LSB to MSB This is a static setting and can only be changed dynamically through dynamic reconfiguration When you enable Enable RX bit reversal you must also enable Enable rx_std_bitrev_ena port Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 34 Standard PCS Parameters UG A10XCVR 2013 12 02 Enable rx_std_ On Off When you turn this option on asserting t
243. ase of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software XAUI PHY IP will be available in a future release of the Quartus II software Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 8 Arria 10 Transceiver Protocols and PHY IP Support 2013 12 02 Protocol Transceiver IP PCS Support Transceiver Protocol Preset Configuration Rule 10GBASE R Native PHY IP Enhanced 10GBASE R 10GBASE R 10GBASE R 1588 Native PHY IP Enhanced 10GBASE R 1588 10GBASE R 1588 10GBASE R with KR FEC Native PHY IP Enhanced 10GBASE R w 10GBASE R w KR FEC KR FEC 10GBASE KR and 1G 10GbE and Standard and Not applicable BackPlane_wo_1588 1000BASE X 10GBASE KR Enhanced PHY IP LineSide optical LineSide optical _1588 40GBASE R 100GBASE R Native PHY IP Enhanced Basic Enhanced User created PCS 40GBASE R with FEC Native PHY IP Enhanced Basic w KR FEC User created 40GBASE KR4 100GBASE R via CAUI 4 Native PHY IP PCS Direct Basic Enhanced User created CPPI 4 BP 4 Enhanced PCS PCS low latency mode 100GBASE R via CAUI Native PHY IP Enhanced Basic Enhanced User created PCS 100GBASE Rvia CAUI with Native PHY IP Enhanced Basic w KR FEC User created FEC XAUI XAUI PHY IP Standard Soft PCS Not applicable Not applicable SPAUI Native PHY IP Standard and Basic Custom User created Enhanc
244. ataout 19 10 i atl Encoding q tx_forcedisp 1 lt tx_dispval il lt tx_dispval 1 x datain 7 0 LSB q tx_datak 0 dataout 9 0 i atagutj o lt Encoding q tx forcedisp 0 E m tx_dispval 0 When the PCS PMA interface width is 10 bits one 8B 10B encoder is used to convert the 8 bit data into a 10 bit output When the PCS PMA interface width is 20 bits two cascaded 8B 10B encoders are used to convert the 16 bit data into a 20 bit output wherein the first eight bits LSByte is encoded by the first 8B 10B encoder and the next eight bits MSByte is encoded by the second 8B 10B encoder The running disparity of the LSByte is calculated first and passed on to the second encoder to calculate the running disparity of the MSByte Note You cannot enable the 8B 10B encoder when the PCS PMA interface width is 8 bits or 16 bits 8B 10B Encoder Control Code Encoding Figure 5 42 Control Code Encoding Diagram tx_clkout tx_parallel_data 15 0 X 8378 X BCBC X OF00 X BF3C X tx datak 1 0 0 Xo a X 0 Code Group p3 4 X D24 3 X D28 5 X K28 5 X D15 0 X 00 0 X D31 5X D28 1X tx_datak is used to indicate whether the 8 bit data being sent at the tx_parallel_data port should be a control word or a data word When t x_dat ak is high the 8 bit data is encoded as a control word Kx y
245. ate machine are included in the design example Altera recommends that you integrate these two modules into your design The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design Examples Wiki page Note The design examples on the Wiki page provide useful guidance for developing your own designs but they are not guaranteed by Altera Use them with caution Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Related Information Interlaken Design Example Native PHY IP Parameter Settings for Interlaken 2 75 Native PHY IP Parameter Settings for Interlaken Table 2 51 General and Datapath Parameters Parameter WELT Device speed grade fastest Message level for rule violations error warning Transceiver Configuration Rules Interlaken Transceiver mode TX RX Duplex TX Simplex RX Simplex Number of data channels 1 to 48 Data rate Up to 17 4 Gbps Enable reconfiguration between On Off Standard and Enhanced PCS Enable simplified data interface On Off Table 2 52 TX PMA Parameters Parameter WELT TX channel bonding mode Non bonded PMA bonding TX local clock division factor 1 2 4 8 Number of TX PLLs 1 2 3 4 Main TX PLL logical index 0 Table 2 53 RX PMA Parameters Parameter VEIG Number of CDR reference clocks 1to5 Selected CDR reference clock 0to4 Selected CDR reference clock frequency Sele
246. ates the detection process It is only used for Quick Path Intercon nect QPI applications Table 2 42 RX Standard PMA Data and Optional PMA Ports Ta ome ieseieO unMcl lt n gt LsO Output Asynchronous This port is available if you turn on Enable tx_ rxfound_pma port QPI in the GUI When asserted indicates that the receiver detect block in TX PMA has detected a transmitter at the other end of the channel It is only used for Quick Path Interconnect QPI applications rx_serial_data lt n gt Input Serial data input to the RX PMA 1 0 rx Cedie rerelko Input Clock Reference clock input to the RX clock data recovery CDR circuitry Optional Ports ex_car_refelkl rx_ Input Clock Reference clock inputs to the RX clock data cdr_refclk4 recovery CDR circuitry rx_pma_qpipullup lt n gt Input Asynchronous _ This port is only used for Quick Path Intercon 1 0 nect QPI applications rx ig lockedrto Output Asynchronous When asserted indicates that the CDR PLL is data lt n gt 1 0 locked to the incoming data rx_serial_ dota rx_is_ Output Asynchronous When asserted indicates that the CDR PLL is lockedtoref lt n gt 1 0 locked to the input reference clock Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS and PMA Ports 2 55 rx_set_lockedto Input Asynch
247. ation but latency will be minimized Figure 2 68 Rate Match Deletion The figure below shows an example of rate match deletion in the case where two K28 0 SKP symbols must be deleted Only one K28 0 SKP symbol is deleted per SKP ordered set received Skip Symbol Deleted First Skip Ordered Set ae i Second Skip Ordered Set n paral data K28 5 i K28 0 I Dx y rc paral data K28 5 y Dx y K28 5 y K28 0 K28 0 X K28 0 1 Y XXX i XXX X XXX i pipen status 2 0 X 3 b010 XXX x 3 b010 Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 186 PCle Reverse Parallel Loopback 2013 12 02 Figure 2 69 Rate Match Insertion The figure below shows an example of rate match insertion in the case where two SKP symbols must be inserted Only one K28 0 SKP symbol is inserted per SKP ordered set received First Skip Ordered Set Second Skip Ordered Set v parallel data K28 5 K28 0 Dx y K28 5 K28 0 X K28 0 X K28 0 K28 0 i rx_parallel_data K28 5 i K28 0 K28 0 pipen status 20 Y 3 b001 y XXX X XXX Skip Symbol Inserted Figure 2 70 Rate Match FIFO Full The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and drives pipestatus 2 0 3 b101 synchronous to the subsequent data byte The figure below shows the rate match FIFO full condition in PIPE mode The rate match FIFO becomes full a
248. ation details Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 198 2013 12 02 Native PHY IP Parameter Settings for PCI Express e Resetting Transceiver Channels on page 4 1 For information about the Reset controller and implementation details e Using PLLs and Clock Networks on page 3 40 e Design Example on page 2 215 Native PHY IP Parameter Settings for PCI Express Table 2 126 Parameterizing Arria 10 Native PHY IP in PIPE Gen1 Gen2 Gen3 Modes Parameter Device speed grade Fastest Fastest Fastest Message level for rule violations Error warning Error warning Error warning PCS Options Transceiver mode TX RX Duplex TX RX Duplex TX RX Duplex Initial PCS selection Standard Standard Standard Number of data channels Gen1 x1 1 Channel Gen1 x2 2 Channel Gen1 x4 4 Channel Gen x8 8 Channel Gen2 x1 1 Channel Gen2 x2 2 Channel Gen2 x4 4 Channel Gen2 x8 8 Channel Gen3 x1 1 Channel Gen3 x2 2 Channel Gen3 x4 4 Channel Gen3 x8 8 Channel Data rate 2 5 Gbps 5 Gbps 8 Gbps Enable reconfig between Standard and Enhanced PCS Of oul of Optional Optional If this option is If this option is Obpicuat selected as OFF selected as OFF If this option is selected as Enable simplified data interface refer to the table for refer to the table for OFF refer to the table for signal ma
249. atternalign depending upon the PCS PMA interface width selected Table 5 6 Word Aligner rx_std_wa_patternalign Behavior PCS PMA Interface Width rx_std_wa_patternalign Behavior 8 Rising edge sensitive 10 Level sensitive Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 38 Word Aligner Synchronous State Machine Mode 2013 12 02 PCS PMA Interface Width rx_std_wa_patternalign Behavior 16 Rising edge sensitive 20 Rising edge sensitive If rx_std_wa_patternalign is asserted the word aligner looks for the programmed word alignment pattern in the received data stream It updates the word boundary if it finds the word alignment pattern in a new word boundary If rx_std_wa_patternalign is deasserted the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary rx_syncstatus and rx_patterndetect with the same latency as the datapath are forwarded to the FPGA fabric to indicate the word aligner status After receiving the first word alignment pattern after rx_std_wa_patternalign is asserted both rx_syncstatus and rx_patterndetect are driven high for one parallel clock cycle Any word alignment pattern received thereafter in the same word boundary causes only rx_patterndetect to go high for one clock cycle Any word alignment pattern received thereafter in a different word boundary causes the word aligner to re align to the new word b
250. bit Mode tx_parallel_data 16hfcbe tx_std_bitslipboundarysel 5 b00011 bit slip by 3 bits tx_std_bitslipboundarysel 00011 tx_parallel_data fcbc rx_parallel_data 79f9 Figure 2 125 TX Bit Slip in 20 bit Mode tx_parallel_data 20 h3FCBC tx_std_bitslipboundarysel 5 b00111 bit slip by 7 bits tx_std_bitslipboundarysel 00111 tx_parallel_data f3cbc m_parallel_data e5e1f TX Polarity Inversion Transmitter polarity inversion can be enabled in low latency basic and basic rate match modes whereas the word aligner is available in any mode To enable the TX polarity inversion feature select the Enable TX polarity inversion and Enable tx_polinv port options This mode adds tx_polinv If there is more than one channel in the design tx_polinv is a bus with each bit corresponding to a channel As long as tx_polinv is asserted the TX data transmitted has a reverse polarity You can verify this feature by monitoring rx_parallel_data Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback p UG A10XCVR 2 244 TX Bit Reversal 2013 12 02 Figure 2 126 TX Polarity Inversion tx_polinv tx_parallel_data 11111100001110111100 rx_parallel_data 0000000 111111000011101 y 00000011110001000011 K 11111100001110111100 rX_patterndetect 00 y 01 rx_syncstatus 00 y 11 TX Bit Reversal The TX bit reversal feature can
251. blished information and before placing orders for products or services JN DTE RYA ISO 9001 2008 Registered 101 Innovation Drive San Jose CA 95134 3 2 PLLs and Clock Networks UG A10XCVR 2013 12 02 Figure 3 1 Arria 10 PLLs and Clock Networks Transceiver x1 Clock Lines x6 Clock Lines xN Clock Lines Bank CH2 CDR Local CGB gt a KE ROTO S Kao lt L lt 4 fPLL CH1 CDRICMU gt ATX Local CGB pa lt PLL 4 Master CHO CDR Pal ee o o P CGB Local CGB x L je Transceiver Bank CH5 CDR o Local CGB gt a aman et a a i fPLL CH4 CDRICMU gt ATX Local CGB ra lt 4 PLL lt Master CH3 CDR va oo o o gt CGB Local CGB 4 lt p 0 OO CH2 CDR Local CGB pi ai aa i lt lt fPLL CH1 CDRICMU gt ATX Local CGB 4 lt PLL lt q Master CHO CDR o o o o a gt CGB Local CGB E A 4 Related Information Channel Bonding on page 3 38 Altera Corporation PLLs and Clock Networks GJ Send Feedback UG A10XCVR 2013 12 02 PLLs 3 3
252. boundary Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR Word Aligner RX Bit Reversal Feature 5 40 Word Aligner RX Bit Reversal Feature 2013 12 02 PCS PMA Supported Supported Word rx_std_wa_ rx_syncstatus rx_patterndetect Interface Width Word Aligner Aligner Pattern patternalign behavior behavior Modes Lengths behavior Bit slip 16 N A N A N A Manual 8 16 32 Rising Edge Stays high after the Asserted high for one Sensitive word aligner aligns parallel clock cycle to the word when the word alignment pattern alignment pattern Goes low on appears in the current 16 receiving a rising word boundary edge on rx_std_ wa_ patternalign until a new word alignment pattern is received Bit slip 7 N A N A N A Manual 7 10 20 40 Rising edge Stays high after the Asserted high for one sensitive word aligner aligns parallel clock cycle to the word when the word alignment pattern alignment pattern Goes low on appears in the current receiving a rising word boundary edge on rx_std_ wa_ patternalign until a new word 20 alignment pattern is received Deterministic 10 latency CPRI mode only Synchronous 7 10 20 Stays high as long as Asserted high for one State the synchronization parallel clock cycle Machine conditions are when the word satisfied alignment pattern appears in the current word boundary The RX bit revers
253. c Enhanced PCS interface width must be 64 bits You can enable RX TX FIFO double width mode to create a FPGA fabric PCS interface width of 128 bits Click Finish to generate the Native PHY IP this is your RTL file Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 254 How to Implement Designs for Data Rates Above 17 4 Gbps Using Enhanced PCS in Low Latency Mode UG A10XCVR 2013 12 02 Figure 2 132 Signals and Ports of the Native PHY for Basic Enhanced PCS Transceiver Configuration Rule for Data Rates Above 17 4 Gbps and FPGA Fabric PCS Interface width of 128 bits tx_cal_busy lt rx_cal_busy lt 4 tx_serial_data lt tx_serial_clkO from TX PLL rx_serial_data NIOS _ reconfig_reset Reconfiguration h Hard Calibration IP Registers reconfig_clk gt reconfig_avmm TX PMA TX Enhanced PCS tx_digital_reset t_digital_reset tx_control 17 0 _ tx_control 17 0 tx_parallel_data 127 0 tx_parallel_data 127 0 Serializer k _ tx_coreclkin lt tx_coreclkin tx_clkout gt tx_clkout T T tx_enh_data_valid tx_enh_data_valid tx_analog_reset rx_analog_reset RX PMA RX Enhanced PCS rx_cdr_refclkO rx_is_lockedtodata lt rx_is_lockedtoref lt Deserializer
254. cade clock output port On Off Enables the cascade source output port for fPLL to fPLL to ATX PLL cascading ATX PLL cascading Connect this port to the refclk input port of the cascaded PLL Specifies which core outclk to be 0 3 Specifies the cascading source for fPLL to ATX PLL used as cascading source cascading Enable access to dynamic phase On Off Enables access to dynamic phase shift ports hi inpor When this option is selected phase_reset phase_en updn cntsel 3 0 num_phase_ shifts 2 0 reconfig_avmm phase_done ports are enabled Use as Transceiver PLL On Off Use fPLL to drive transceiver channels through the transceiver clock network Protocol Mode Basic Governs the internal setting rules for the VCO PCIe Gen1 This parameter is not a preset You must set all other PCIe Gen2 parameters for your protocol PLL output frequency Specifies the target output frequency for the PLL Use as Core PLL On Off Use fPLL as a general purpose PLL to drive the FPGA core clock network Number of Clocks 1to4 Specifies the number of output clocks Desired Frequency Enter the desired output clock frequency Actual Frequency Specifies the output clock frequency Phase shift units Specifies the unit used for phase shift measurement Select the appropriate unit Phase shift Specifies the requested phase shift value Enter the desired phase shift value Actual phase shift Specifies the actual phase shift value Altera Corporation
255. cal clock generation block CGB divider If a single base data rate is not possible you can use an additional PLL to generate the required data rates Table 2 134 Recommended Base Data Rates and Clock Generation Blocks for Available Data Rates 1228 8 9830 4 8 2457 6 9830 4 4 3072 0 6144 0 2 4915 2 9830 4 2 6144 0 6144 0 1 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 218 Supported Features for CPRI 2013 12 02 Data Rate Mbps Base Data Rate Local CGB Divider 9830 4 9830 4 1 Supported Features for CPRI The CPRI protocol places stringent requirements on the amount of latency variation that is permissible through a link that implements these protocols CPRI Auto and CPRI Manual transceiver configuration rules are both available for CPRI designs Both modes use the same functional blocks but the configuration mode of the word aligner is different between the Auto and Manual modes In CPRI Auto mode the word aligner works in deterministic mode In CPRI manual mode the word aligner works in manual mode To avoid transmission interference in time division multiplexed systems every radio in a cell network requires accurate delay estimates with minimal delay uncertainty Lower delay uncertainty is always desired for increased spectrum efficiency and bandwidth The devices are designed with features to minimize the delay uncertainty for both RECs and REs
256. cal_busy calc_clk_1g rx_syncstatus tx_pcfifo_error_1g tx_pcfifo_error_1g Icl_rf en_lIcl_rxeq rxeq_done tm_in_trigger 3 0 tm_out_trigger 3 0 rx_rlv rx_clkslip rx_latency_adj_1g 11 0 tx_latency_adj_1g 11 0 rx_latency_adj_10g 11 0 tx_latency_adj_10g 11 0 rx_data_ready dmi_mode_en dmi_frame_lock dmi_rmt_rx_ready dmi_Icl_coefl 5 0 dmi_lIcl_coefh 1 0 dmi_lIcl_upd_new dmi_rx_trained dmo_frame_lock dmo_rmt_rx_ready dmo_lIcl_coefl 5 0 dmo_Icl_coefh 1 0 dmo_lIcl_upd_new dmo_rx_trained upi_rx_trained upo_enable upo_frame_lock upo_cm_done upo_bert_done upo_ber_cnt lt w gt 1 0 upo_ber_max upo_coef_max gt lt lt Transceiver Serial Data Reconfiguration Status Daisy Chain Mode Input Interface Embedded Processor Interface Outputs The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box The interface type and name are used in the _hw tcl file If you turn on Show signals the block diagram displays all top level signal names For more information about _hw tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Clock and Reset Interfaces 2 117 Related Information Component Interface Tcl Reference For more information about _hw
257. cates a control word e 0 Synchronization header 1 indicates a data word e Interlaken With Enable simplified interface off e 19 10 Same as unused_rx_control 9 0 Can be left floating e 9 0 Same as above when you turn on Enable simplified interface Can be left floating Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS and PMA Ports 2 45 Description 10GBASE R 9 Active high status signal that indicates when Block Lock is achieved 8 Active high status signal that indicates a syn header error 7 XGMII control signal for rx_parallel_ data 63 56 6 XGMII control signal for rx_parallel_ data 55 48 5 XGMII control signal for rx_parallel_ data 47 40 4 XGMII control signal for rx_parallel_ data 39 32 3 XGMII control signal for rx_parallel_ data 31 24 2 XGMII control signal for rx_parallel_ data 23 16 1 XGMII control signal for rx_parallel_ data 15 8 0 XGMII control signal for rx_parallel_ data 7 0 Basic mode 64 bit data including synchronization header 9 Active high status signal indicating when Block Lock is achieved 8 Active high status signal that indicates a sync header error 7 2 Unused 1 Sync Header 1 indicates a control word 0 Sync Header 1 indicates a data word Basic 64 bit data excludin
258. ce These clocks can also be used to clock the core side of the TX and RX FIFOs when the Enhanced PCS Gearbox is used For example if the Enhanced PCS Gearbox was engaged with a 66 40 ratio the tx_pma_div_clkout could be used with a divide by 33 ratio to clock the write side of the TX FIFO instead of using a PLL to generate the required clock frequency or using an external clock source Transmitter Data Path Interface Clocking The clocks generated by the PLLs are used to clock the channel PMA and PCS blocks The clocking architecture is different for the standard PCS and the enhanced PCS Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR r 2013 12 02 Transmitter Data Path Interface Clocking 3 35 Figure 3 12 Transmitter Standard PCS and PMA Clocking The master local CGB provides the high speed serial clock to the serializer of the transmitter PMA and the low speed parallel clock to the transmitter PCS Transmitter PMA Transmitter Standard PCS FPGA Fabric g wo iss g g x S z R F C gje D es Z4 E g y g 3 e 3 s 8 PRBS Generator tx_coreclkin tx_clkout i I i 12 14 tx_pma_div_clkout telkou From Receiver Standard PCS 5 Clock Generation Block CGB ATX PLL CMU PLL Clock Divider me 3 Parallel and Se
259. ceiver N A has detected an electrical idle Active High pipe_rx_elecidl Out Signal encodes receive status and error codes for the receive data stream and receiver detection The following encodings are defined 3 b000 receive data OK 3 b001 1 SKP added 3 b010 1 SKP removed 3 b011 Receiver detected pipe rx statis 2 0 Out tx_pma_clk 3 b100 Both 8B 10B or 128b 130b decode error and optionally RX disparity error 3 b101 Elastic buffer overflow 3 b110 Elastic buffer underflow 3 b111 Receive disparity error not used if disparity error is reported using 3 b100 Signal to clock generation buffer indicating the rate switch request Use this signal for bonding mode only pipe_sw Out N A For non bonded applications this signal is internally connected to the local CGB Active High How to Place Channels for PIPE Configurations All the placement restrictions are dictated by the hardware not by the fitter or software model The restrictions are listed below 1 The channels must be contiguous for bonded designs 2 The master CGB is the only way to access x6 lines and has to be used in bonded designs ie the local CGB cannot be used to route clock signals to slave channels the local CGB does not have access to x6 lines Master Channel in Bonded Configurations For PCle both the PMA and PCS must be bonded There is no need to specify the PMA Master Channel because of the se
260. ch are striped round robin across the lanes The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65 536 logical channels Packets are split into small bursts that can optionally be interleaved The burst semantics include integrity checking and per logical channel flow control The Interlaken interface is supported with 1 to 48 lanes running at data rates up to 17 4 Gbps per lane Interlaken is implemented using the Enhanced PCS The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third party IP suppliers Figure 2 9 Transceiver Channel Datapath and Clocking for Interlaken This assumes the serial data rate is 12 5 Gbps and the PMA width is 40 bits tx_coreclkin rx_coreclkin Transmitter PMA Transmitter Enhanced PCS FPGA Fabric 5 64 bits s 5 5 o data s co E g g 3 bits w 5 x os oo So ao D e xo 4 g E g trol i 8 40 cu 5 g ge are con on a i ee H H Re 3 D E 5 8 Eg BF 1 v a a 8 55 E 3 a 5 u 186 97 MHz to 31 5MHz L a Sr ane Parallel Clock 312 5 MHz tx_clkout T p3 o wo N o x tx_pma_div_clkout 8 o
261. ch as SDH SONET OTN jitter testers Most 40G 100G and 10G applications use PRBS31 for link evaluation Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 20 Pseudo Random Pattern Generator 2013 12 02 Figure 5 24 PRBS Generator for Serial Implementation of PRBS9 Pattern e SO gt S1 K gt S4 e 5 S 88 Y v PRBS Output Note All supported PRBS generators are similar to the PRBS9 generator The square wave generator supports 64 bit PCS PMA interface widths It has a programmable n number of consecutive serial bit 1s and Os where n is 4 6 or 8 n defaults to 4 Figure 5 25 Generator for Square Wave Pattern nOs nis 7 Program the value of n through the Transceiver and PLL Address Map Pseudo Random Pattern Generator The pseudo random pattern PRP generator is specifically designed for the 1OGBASE R and 1588 protocols The PRP generator block operates in conjunction with the scrambler to generate pseudo random patterns for the TX and RX tests in the 10G Ethernet mode It generates various test patterns from various seeds loaded to the scrambler and select data patterns Set the following PRP generator options through the Transceiver and PLL Address Map e The data pattern select bit switch can be toggled between two data patterns e The value of Seed A and Seed B can be changed Note
262. cification Receiver Detection The PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopback for the receiver detect operation required by the PCIe protocol during the Detect state of the LTSSM When the pipe_tx_detectrx_loopback signal is asserted in the P1 power state the PCle interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence In the P1 power state the transmitter buffer must always be in the electrical idle state After receiving this command signal the receiver detect circuitry creates a step voltage at the output of the transmitter buffer If an active receiver that complies with the PCle input impedance requirements is present at the far end the time constant of the step voltage on the trace is higher when compared with the time constant of the step voltage when the receiver is not present The receiver detect circuitry monitors the time constant of the step signal seen on the trace to determine if a receiver was detected Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Gen1 and Gen2 Clock Compensation 2 185 Note For the receiver detect circuitry to function reliably the transceiver on chip termination must be used and the AC coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification 2 0 The PIPE co
263. ck is not available hold resets until the system clock is stable reset Input Asynchronous Asynchronous reset input to the Transceiver PHY Reset Controller When asserted all configured reset outputs are asserted Holding the reset input signal asserted holds all other reset outputs asserted Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 Transceiver PHY Reset Controller Interfaces 4 15 tx _Chigaital reset lt as 1120 Output Synchronous to the Transceiver PHY Reset Controller input clock Digital reset for TX The width of this signal depends on the number of TX channels This signal is asserted when any of the following conditions is true e reset is asserted e pll_powerdown is asserted e pll_cal_busy is asserted e tx_cal_busy is asserted e PLLhas not reached the initial lock p11_ locked deasserted e pll_lockedisdeasserted and t x_manual is deasserted When all of these conditions are false the reset counter begins its countdown for deassertion of tx_digital_reset If your design includes bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design tx_analogreset Output lt n gt 1 0 Synchronous to the Transceiver PHY Reset Controller input clock Analog reset for TX channels This signal follows pll_powerdown and is
264. ck Generation Block 2G 8 scics css tscesscattvaisisinosen aig ioauinieniainn teaneasenninmeans 1 21 Implementing Protocols in Arria 10 Transceivers csscsssesssssessssesesseeseee 27 L Altera Corporation Transc iyer Design IP BIGGS a csscnsnctaisspsnsvaspsch binge avs dvtestonhicksoaca tineta On EP REEERE EAN E ENa eR ink 2 1 Transeetyer Design Flow sascsseccsseiacexejeecassteveasiawsnsevucvacievnnveuseanennneln caeaveaaieietetavensiscesleriiareaniteiea S 2 2 Select and Instantiate PHY Ps Gap assscsstestaaucrcrivoasaiicaan oapessuesradtaectinechnaceadioiacscsiasiueatnewielnles 2 2 Coma TS RLY D E E EAE 2 3 Generate PHY VP ssi tesiscst ii wv an a E ERA ERE EAE E 2 4 EE PPL D e E EAE EE EEEE 2 4 Configure PLL UP p scssssscissiciveornetisiernsieusidentoanouenivaduncisumundienianucainamanets 2 5 Gemerate PEL IP cs cesccccsctactieies ieesasacsciesseasasstboucssubaspatievevcsbussstans dvespasedeegvevesveccanundeneepoueageesuuvepebrneanes 2 5 Reset Controller svarini dsc odbc aina a i iana EAA EAE ANENE sag aba 2 6 Create Reconfiguration Logic siesena vedgeenseveawiauecertoiq ondeveaedtienncabuasvahachdaniduenscassn 2 6 Connect PHY IP to PLL IP and Reset Controller esssseceeeeeessseneeeesetenesceeeeeseneneaeneenenees 2 6 Connect the Transceiver Datapath to MAC IP Core or to a Data Generator Apalyzef sscisscssovasgssaaussaswanasaanawataouansea shastneyeagudaancoanaeumecasa casa cate sckansdaandsavdaawscumemaeeuanenea teiswa
265. ck Networks Altera Corporation CJ Send Feedback s UG A10XCVR 3 32 Clock Generation Block 2013 12 02 Figure 3 10 GT Clock Lines Ch o1 CGB y CDR Ch D CGB p CDR ATX PLL1 Ch 2S CGB y CDR Ch N CGB y CDR Ch e E CDR Ch oO y Q O ow CDR Clock Generation Block In Arria 10 devices there are two types of clock generation blocks CGBs e Local clock generation block local CGB e Master clock generation block master CGB Each transmitter channel has a local clock generation block CGB For non bonded channel configurations the serial clock generated by the transmit PLL drives the local CGB of each channel The local CGB generates the parallel clock used by the serializer and the PCS There are two standalone master CGBs within each transceiver bank The master CGB provides the same functionality as the local CGB within each transceiver channel The output of the master CGB can be routed to other channels within a transceiver bank using the x6 clock lines The output of the master CGB can also Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Clock Generation Block 3 33 be routed to channels in other transceiver ban
266. clic code 2112 2080 For each block of 2080 message bits another 32 parity checks are generated by the encoder to form a total of 2112 bits The generator polynomial is 2 23 21 1 g x x OS ae aa ae ae KR FEC Scrambler The KR FEC scrambler block performs scrambling based on the generation polynomial x x 1 which is necessary for establishing FEC block synchronization in the receiver and to ensure DC balance KR FEC TX Gearbox The KR FEC TX gearbox converts 65 bit input words to 64 bit output words to interface the KR FEC encoder with the PMA This gearbox is different from the TX gearbox used in the Enhanced PCS The KR FEC TX gearbox aligns with the FEC block Because the encoder output also the scrambler output has its unique word size pattern the gearbox is specially designed to handle that pattern Receiver Datapath RX Gearbox RX Bitslip and Polarity Inversion The RX gearbox adapts the PMA data width to the larger bus width of the PCS channel Gearbox Expansion It supports different ratios PCS PMA interface width FPGA fabric PCS interface width such as 32 66 40 66 32 67 40 67 40 50 32 64 40 64 40 40 32 32 64 64 67 64 and 66 64 and a bit slipping feature Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 2013 12 02 RX bitslip is engaged when the RX block synchronizer or rx_bits1ipis enabled to shift the word boundary On the rising edge of the bitsl
267. clk mux s output The division factors supported are 1 2 4 and 8 Phase Frequency Detector PFD The refclk signal at the output of the N counter block and the feedback clock fbc1lk signal at the output of the M counter block is supplied as an input to the PFD The output of the PFD is proportional to the phase difference between the 2 inputs It is used to align the refc1k signal at the output of the N counter to the feedback clock ffc1k signal The PFD generates an Up signal when the reference clock s falling edge occurs before the feedback clock s falling edge Conversely the PFD generates a Down signal when feedback clock s falling edge occurs before the reference clock s falling edge Charge Pump and Loop Filter CP LF The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO The charge pump translates the Up Down pulses from the PFD into current pulses The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency The charge pump loop filter and VCO settings determine the bandwidth of the ATX PLL Lock Detector The lock detector block indicates when the reference clock and the feedback clock are phase aligned It generates an active high signal to indicate that the PLL is locked to its input reference clock Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Instantiating ATX PLL 3 5 Vol
268. clock and data The CMU PLL from transceiver channel 1 and channel 4 can be used to drive other transceiver channels within the same transceiver bank The CDR of channels 0 2 3 and 5 cannot be configured as a CMU PLL PLLs and Clock Networks GJ Send Feedback Altera Corporation UG A10XCVR 3 20 CMU PLL 2013 12 02 Figure 3 4 CMU PLL Block Diagram Lock to 4 User Control Reference LTR LTD Controller gt Lock to Reference l Lock gt ae e p gt PLL Lock Status CP Refclk LF VCO p L Counter Output Multiplexer Reference clock network up F own N Counter PFD Receiver input pin gt M Counter VCO Calibration Input Reference Clock The input reference clock for a CMU PLL can be sourced from either the reference clock network or a receiver input pin The input reference clock is a differential signal The input reference clock must be stable and free running at device power up for proper PLL operation Reference Clock Multiplexer Refclk Mux The refclk mux selects the input reference clock to the PLL from the various reference clock sources available N Counter The N counter divides the refclk mux s output The N counter division helps lower the loop bandwidth or reduce the frequency to within the phase frequency detector s PFD operating range Possible divide ratios are 1 bypass 2 4 and 8
269. clocking for this core Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 154 Clock and Reset Interfaces 2013 12 02 Figure 2 62 Clocks for Standard and 10G PCS and TX PLLs Native PHY 4 40 TX data GMIl TX Data GIGE i gt Standard TX PCS TX serial data TX PMA tx_coreclkin_1g p gt tx_pld clk tx_pma_clk m gt 125 MHz 40 pll_ref_clk_1g 64 EPL 125 MHz XGMII TX Data amp Cntl 72 72 TX data Of ae Enhanced TX PCS 62 5 MHz fractional fi xgmii_tx_cik Pa pll_ref_clk_10g pll_ref_clk_10 PLL 156 25 MHZ p gt tx_pld_clk tx_pma_clk lt TX PLL 644 53125 MHZ or instantiate 322 265625 MHz separately GMII RX Data GIGE 8 l A pes A Standard RX PCS 40 RX data red datapath includes FEC ee RX PMA serial data m_pld_clk rx_pma_clk 125 MHz ie ee XGMII RX Data amp Cnil 72 72 recovered clk be Enhanced RX PCS 257 8125 MHz D i 161 1 MHz xgmii_rx_c 15625 MHz p gt rx_pld_clk rx_pma_clk The following table describes the clock and reset signals Table 2 106 Clock and Reset Signals rx_recovered_clk Output The RX clock which is recovered from the received data You can use this clock as a reference to lock an external clock source Its frequency is 125 or 156 25 MHz tx elkout ig Output GMII TX clock for the 1G TX parallel dat
270. cols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 116 10GBASE KR PHY Interfaces UG A10XCVR 2013 12 02 CT INITPREVAL 0 15 Specifies the Initial Pre tap Value The default value 10GBASE KR PHY Interfaces Figure 2 55 10GBASE KR Top Level Signals XGMII GMII MII Interfaces Avalon MM PHY Management Interface Clocks and Reset Interface Embedded Processor Interface Inputs 10GBASE KR Top Level Ports xgmii_tx_dc 71 0 xgmii_tx_clk xgmii_rx_de 71 0 xgmii_rx_clk gmii_tx_d 7 0 gmii_rx_d 7 0 gmii_tx_en gmii_tx_err gmii_rx_err gmii_rx_dv mii_tx_d 3 0 mii_tx_en mii_tx_err mii_tx_clkena mii_tx_clkena_half_rate mii_rx_d 3 0 mii_rx_en mii_rx_err mii_rx_clkena mii_rx_clkena_half_rate mii_speed_select 1 0 mgmt_clk mgmt_clk_reset mgmt_address 10 0 mgmt_writedata 31 0 mgmt_readdata 31 0 mgmt_write mgmt_read mgmt_waitrequest tx_serial_clk_10g tx_serial_clk_1g rx_cdr_ref_clk_10g r_cdr_ref_clk_1g tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset upi_mode_en upi_adj 1 0 upe_inc upi_dec upi_pre upi_init upi_st_bert upi_train_err upi_lock_err rx_serial_data tx_serial_data mode_ig_10gbar rc_busy start_pcs_reconfig led_char_err led_link led_disp_err led_an rx_block_lock rx_hi_ber rx_is_lockedtodata tx_cal_busy rx_
271. config_address identifies the active channel The lower 10 bits specify the reconfiguration address Binary encoding is used to identify the active channel available only for Transceiver Native PHY Enable embedded JTAG Enable Includes a JTAG Avalon MM master to control the reconfiguration AVMM master Disable interface For example use System Console to control the JTAG Avalon MM master Disabled by default Generate SystemVerilog Enable Creates a SystemVerilog package file that contains the current package file Disable configuration data values for all reconfiguration addresses Disabled by default Generate C header file Enable Creates a C header file that contains the current configuration data Disable values for all reconfiguration addresses Disabled by default Generate MIF Memory Enable Creates a MIF file that contains the current configuration data values Initialize File Disable for all reconfiguration addresses Disabled by default CJ Send Feedback Altera Corporation 2 A z UG A10XCVR 6 4 Interacting with the Reconfiguration Interface 2013 12 02 Interacting with the Reconfiguration Interface This section describes how to interact with the reconfiguration interface by performing Avalon read and write operations to initiate dynamic reconfiguration of specific transceiver parameters All read and write operations must adhere to the Avalon specification Related Information e Avalon Interface
272. ct from drop down menu Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation R UG A10XCVR 2 76 Native PHY IP Parameter Settings for Interlaken 2013 12 02 PPM detector threshold 62 5 100 125 200 250 300 500 1000 Table 2 54 Enhanced PCS Parameters Parameter VEIG Enhanced PCS protocol mode Interlaken Enhanced PCS to PMA interface width 32 40 64 FPGA fabric to Enhanced PCS interface 67 width Enable RX TX FIFO double width mode Off TX FIFO mode Interlaken TX FIFO partially full threshold from 10 13 no less than pempty_threshold 8 TX FIFO partially empty threshold 2to5 Enable tx_enh_fifo_full port On Off Enable tx_enh_fifo_pfull port On Off Enable tx_enh_fifo_empty port On Off Enable tx_enh_fifo_pempty port On Off Enable tx_enh_fifo_cnt port On Off RX FIFO mode Interlaken RX FIFO partially full threshold from 10 29 no less than pempty_threshold 8 RX FIFO partially empty threshold 2 to 10 Enable RX FIFO alignment word On Off deletion Interlaken Enable RX FIFO control word deletion On Off Interlaken Enable rx_enh_fifo_data_valid port On Enable rx_enh_fifo_full port On Off Enable rx_enh_fifo_pfull port On Off Enable rx_enh_fifo_empty port On Off Enable rx_enh_fifo_pempty port On Off Enable rx_enh_fifo_cnt port On Off Altera Corporation Implementing Protocols
273. culation during that word is incorrectly inverted and thus the CRC created for that metaframe is incorrect Enable Interlaken On Off Enables the CRC 32 checker function RX CRC 32 checker Enable rx_enh_ On Off When you turn this option on the Enhanced PCS enables the crc32_err port rx_enh_crc32_err port This signal is asserted to indicate that the CRC checker has found an error in the current metaframe Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS Parameters 2 27 Table 2 14 10GBASE R BER Checker Parameters Enable rx_enh_ highber port 10GBASE R On Off Enables the rx_enh_highber port Enable rx_enh_ highber_clr_cnt port 10GBASE R On Off Enables the rx_enh_highber_clr_cnt input port Enable rx_enh_ clr_errblk_count port LOGBASE R On Off Enables the rx_enh_clr_errb1lk_count input port Table 2 15 64b 66b Encoder and Decoder Parameters Enable TX 64b On Off When you turn this option on the Enhanced PCS enables the TX 66b encoder 64b 66b encoder Enable RX 64b On Off When you turn this option on the Enhanced PCS enables the RX 66b decoder 64b 66b decoder Enable TX syne On Off When you turn this option on the Enhanced PCS supports cycle header error accurate error creation to assist in exercising error condition insertion testing on the receiver When error insert
274. cy of the reference clock is 312 5 MHz Figure 2 15 10X12 5 Gbps PLL Feedback Compensation Bonding Reference e Clock Transceiver PLL Instance 6 25 GHz Master ATX PLL gt CGB x6 Native PHY Instance 10 Ch Bonded 12 5 Gbps Transceiver Bank 1 Feedback Clock Transceiver PLL Instance 6 25 GHz gt Master ATX PLL gt CGB x6 Transceiver Bank 2 Feedback Clock Related Information PLL Feedback Compensation Bonding Mode on page 3 47 For other limitations on feedback compensation bonding TX Multi Lane Bonding and RX Multi Lane Deskew Alignment State Machine The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode In this mode of operation TX and RX FIFO control and status port signals are provided to the FPGA fabric Connect these signals to the MAC layer as required by the protocol Based on these FIFO status and control signals you can implement the multi lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block You must also implement the soft bonding logic to control the transceiver TX FIFO block TX FIFO Soft Bonding The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_enh_data_valid functions as a TX
275. d GXBL1H for Channels 3 4 and 5 GT Configuration A Configuration B Configuration C Configuration D Configuration E Configuration F Transceiver Channel Ch5 Unusable Unusable Unusable GX GX GX Ch4 en cr GX Unusable GT GX Ch3 GT GX GT GT Unusable GX Notes e Ifboth the channels 3 and 4 are used with either one of them configured as a GT channel and the other one as GT or GX then channel 5 is unusable For all other configurations of channels 3 and 4 channel 5 can only be configured as a GX channel e If either channel 3 or 4 is used as a GT channel then the ATX PLL adjacent to channel 3 and 4 needs to be reserved for GT channel configurations Transceiver PHY IP Arria 10 GT transceiver channels are implemented using the Native PHY IP with the Basic Enhanced PCS transceiver configuration rule Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback A z UG A10XCVR 2 252 PLL and GT Transceiver Channel Clock Lines 2013 12 02 e To support data rates from 17 4 Gbps to 28 1 Gbps the Enhanced PCS must be configured in low latency mode To configure the Enhanced PCS in low latency mode do not enable any functional blocks in the Enhanced PCS i e disable Block Sync Gearbox Scrambler amp Encoder e You can also use the PCS Direct mode for data rates from 17 4 Gbps to 28 1 Gbps PCS Direct will be available in a future release of the QuartusII software You can bu
276. d channels Note Transceiver Native PHY IP non bonded configuration to another Transceiver Native PHY IP non bonded configuration is supported Transceiver and PLL Address Map The transceiver and PLL address map provides a list of available PCS PMA and PLL addresses that you can use to change or reconfigure the functional behavior of the transceiver or PLL respectively Use the transceiver and PLL address map with the Avalon interface The address map is provided as an Excel spreadsheet for easy search and filtering Related Information Transceiver and PLL Address Map Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation CJ Send Feedback Document Revision History 2013 12 02 UG A10XCVR S subscribe QO Send Feedback The table below lists the revision history for this user guide ES December 2013 2013 12 02 Initial release 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Be www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Satsane i Altera s standard warranty but reserves the right to m
277. d clocking configurations PLLs and Clock Networks Altera Corporation CJ Send Feedback 3 50 Mix and Match Example Figure 3 24 Mix and Match Design Example PLL Instances Transceiver Bank nterlaken 12 5G t nterlaken 12 5G 7 nterlaken 12 5G ae ie CGB Interlaken 12 5G Interlaken 12 5G Interlaken 12 5G Transceiver Bank xN Interlaken 12 5G _ Interlaken 12 5G Interlaken 12 5G nterlaken 12 5G ae TR x1 TOGBASEKR 10GBASE KR Transceiver Bank z 10GBASE KR ATX PLL 5 15625 GHz x1 ATX PLL 4 9 GHz x1 Transceiver Bank 1 25G GbE fPLL 7 m 1 25G GbE 2 5 GHz Mego AUX PCle Gen 1 2 3 x8 t PCle Gen 1 2 3 x8 coe CGB PCle Gen 1 2 3 x8 x6 PCle Gen 1 2 3 x8 Transceiver Bank XN PCle Gen 1 2 3 x8 PCle Gen 1 2 3 x8 PCle Gen 1 2 3 x8 PCle Gen 1 2 3 x8 Unused Unused Legend Interlaken12 5G 1 25G GbE 10GBASE KR PCle Gen 1 2 3 E 1 25G 9 8G 10 3125G Unused channel UG A10XCVR 2013 12 02 In this example five ATX PLL instances and two fPLL instances are used Choose an appropriate reference clock for each PLL instance The Meg
278. d for PCI Express configurations status ports Enable PCIe On Off When you turn this option on enables the pipe_rx_polarity pipe_rx_polarity input control port You can use this to control channel signal port polarity for PCI Express configurations When the Standard PCS is configured for PCle the assertion of this signal causes the RX bit polarity to be inverted For other Transceiver configuration rules the optional rx_polinv port inverts the polarity of the RX bit stream Related Information Standard PCS and PMA Ports on page 2 52 Dynamic Reconfiguration Parameters Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device Each transceiver channel and PLL includes an Avalon MM slave interface for reconfiguration This interface provides direct access to the programmable address space of each channel and PLL Because each channel and PLL includes a dedicated Avalon MM slave interface you can dynamically modify channels either concurrently or sequentially If your system does not require concurrent reconfiguration you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs For example you can change the reference clock input to the TX PLL You can also change between the Standard and Enhanced datapaths Table 2
279. d from the transmitter PLL to the transmitter channel In this case the local CGB in each channel is bypassed and the parallel clocks generated by the Master CGB are used to clock the network The master CGB generates both the high and slow speed clocks a master channel generates the PCS control signals and distributes to other channels through a control plane block The default value is Not bonded PCS TX channel Auto 0 1 2 3 Specifies the master PCS channel for PCS bonded configurations bonding master Each Transceiver Native PHY IP instance configured with bonding must specify a bonding master If you select Auto the Transceiver Native PHY IP automatically selects a recommended channel The default value is Auto Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master Actual PCS TX 0 lt no of channels gt This parameter is automatically populated based on your selection channel bonding 1 for thePCS TX channel bonding master parameter Indicates the master selected master PCS channel for PCS bonded configurations Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Table 2 5 TX PLL Options PMA Parameters 2 19 TX local clock 1 2 4 8 Specifies the value of the divider available in the transceiver division factor channels to divide the TX PLL output clock to generate the correct frequencies
280. d into the Status field each time a DIAG word is created by the framing generator Figure 2 13 Interlaken Diagnostic Word bx10 b011001 h000000 Status CRC32 66 63 58 57 3433 3231 0 Interlaken Configuration Clocking and Bonding The Arria 10 Interlaken PHY layer solution is scalable and has flexible data rates You can implement a single lane link or bond up to 48 lanes together You can choose a lane data rate up to 17 4 Gbps You can also choose between different reference clock frequencies depending on the PLL used to clock the transceiver Refer to the Arria 10 Device Datasheet for the minimum and maximum data rates that Arria 10 transceivers can support at different speed grades You can use an ATX PLL or fPLL to provide the clock for the transmit channel An ATX PLL has better jitter performance compared to an fPLL You can use the CMU PLL to clock only the non bonded Interlaken implementation However if you use the CMU PLL you lose one RX transceiver channel For the multi lane Interlaken interface TX channels are usually bonded together to minimize the transmit skew between all bonded channels Currently xN bonding and a PLL feedback compensation bonding scheme are available to support a multi lane Interlaken implementation If the system tolerates higher channel to channel skew you can choose to not bond the TX channels To implement bonded multi channel Interlaken all channels must be placed contiguous
281. d_bitslip boumdarysel port Optional Optional Optional RX word aligner mode oya hronot n an eile Synchronous State Machine Machine Machine RX word aligner pattern length 10 10 10 RX word aligner pattern hex 0x0000 00000000017c 0x0000 00000000017c 0x0000 00000000017c Number of word alignment 3 3 3 patterns to achieve sync Number of invalid data words 16 16 16 to lose sync Number of valid data words to 15 15 15 decrement error count Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 202 Native PHY IP Parameter Settings for PCI Express 2013 12 02 Enable rx_std_wa_ i 5 e er neuls Gina Optional Optional Optional Enable rx_st d_wa_ off off off ala2size port Enable rx_std_bitslip boundarysel port Optional Optional Optional Enable rx_bitslip port Off Off Off Bit Reversal and Polarity Inversion Enable TX bit reversal Off Off Off Enable TX byte reversal Off Off Off Enable TX polarity inversion Off Off Off Enable RX bit reversal Off Off Off Enable RX byte reversal Off Off Off Enable RX polarity inversion Off Off Off Enable t x_polinv port Off Off Off Enablerx_std_bitrev_ena off off off port Enable rx_std_byterev_ off off off ena port Enable rx_polinv port off off off a Ener eleerdis Optional Optional Optional Enable rx_std_signalde 4 s a Optional Optional Optional PCIe P
282. data 7 0 rx_parallel_ data 39 32 7 0 rx_parallel_ data 55 48 39 32 23 16 7 0 rx_datak rx_parallel_data 8 rx_parallel_data 40 8 rx_parallel_data 56 40 24 8 rx_syncstatus rx_parallel_data 10 rx_parallel_ data 42 10 rx_parallel_data 58 42 26 10 pipe_phy_status rx_parallel_data 65 rx_parallel_data 65 rx_parallel_data 65 pipe_rx_valid rx_parallel_data 66 rx_parallel_data 66 rx_parallel_data 66 pipe_rx_status rx_parallel_ rx_parallel_ rx_parallel_data 69 67 data 69 67 data 69 67 pipe_tx_deemph N A tx_parallel_data 52 N A pipe_tx_sync_hdr N A N A tx_parallel_data 55 54 pipe_tx_blk_start N A N A tx_parallel_data 56 pipe_tx_data_valid N A N A tx_parallel_data 60 pipe_rx_sync_hdr N A N A rx_parallel_data 71 70 pipe_rx_blk_start N A N A rx_parallel_data 72 pipe_rx_data_valid N A N A rx_parallel_data 76 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 204 Native PHY IP Ports for PCI Express 2013 12 02 Native PHY IP Ports for PCI Express Figure 2 84 Signals and Ports of Native PHY IP for PIPE A10 Transceiver Native PHY pees Reconfiguration Nios Hard gt tx_cal_busy reconfig_ avm m Registers Calibration IP p
283. data rate is 1250 Mbps Transmitter PMA Transmitter Standard PCS FPGA Fabric Ss ao lp g 10 x T 16 5 n Boek amp 2 F ax eH Q s 2 D v cs N 5 g PRBS tx_coreclkin Generator 625 MHz 2 tx_clkout I kai 125 MHz 1 BAR Mel j 5 z 1 tx_pma_div_clkout tx_clkout Receiver PMA Receiver Standard PCS I is F 10 F 16 g o 4 a ite da zi gt Y gt gt gt o gt aS m gt lo R amp F 2 g 2 amp z rx_coreclkin Parallel Clock I Recovered rx_clkout a l 125 MHz 1 tx_clkout 4 D z 62 9 MHz 1 Parallel Clock 12 rx_clkout or From Clock PRBS tx_clkout Divider Verifier j m_pma_div_clkout Clock Generation Block CGB ATX PLL Clock Divider lt CMU PLL C r fPLL Serial Clock Parallel Clock Serial Clock Parallel and Serial Clock Parallel and Serial Clock Notes 1 The parallel clock tx_clkout or rx_clkout is calculated as data rate PCS PMA interface width 1250 10 125 MHz When the Byte Serializer is set to Serialize x2 mode tx_clkout and rx_clkout become 1250 20 62 5 MHz 2 The serial clock is c
284. de access to all registers Table 2 118 Avalon MM Interface Signals mgmt_clk Input Clock The clock signal that controls the Avalon MM PHY management interface If you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must restrict the frequency range to 100 125 MHz to meet the specifi cation for the transceiver reconfiguration clock mgmt_clk_ Input Reset Resets the PHY management interface This signal is reset active high and level sensitive mgmt _ Input Synchronous to 11 bit Avalon MM address addr 10 0 mgmt _clk mgmt _ Input Synchronous to Input data writedata 31 0 mgmt_clk mgmt _ Output Synchronous to Output data readdata 31 0 mgmt _clk mgmt_write Input Synchronous to Write signal Active high mgmt _clk mgmt _read Input Synchronous to Read signal Active high mgmt_clk Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation rare UG A10XCVR 2 168 Register Definitions 2013 12 02 mgmt _ Output Synchronous to When asserted indicates that the Avalon MM slave waitrequest mgmt _clk interface is unable to respond to a read or write request When asserted control signals to the Avalon MM slave interface must remain constant Related Information Avalon Interface Specifications Register Definitions The Avalon MM master interface signals provide access to the control and status registers
285. deasserted after the TX PLL comes out the reset and locks to the input reference clock tx_ready lt n gt Output Synchronous to the Status signal to indicate when the TX reset 10 Transceiver PHY sequence is complete This signal is deasserted Reset Controller while the TX reset is active It is asserted a few input clock clock cycles after the deassertion of t x_ digitalreset Some protocol implementa tions may require you to monitor this signal prior to sending data The width of this signal depends on the number of TX channels r_digital Output Synchronous to the Digital reset for RX The width of this signal reset lt n gt Transceiver PHY depends on the number of channels This signal 140 Reset Controller is asserted when any of the following conditions input clock is true e reset is asserted e rx_analogreset is asserted e rx_cal_busy is asserted e rx_is_lockedtodata is deasserted and rx manual is deasserted When all of these conditions are false the reset counter begins its countdown for deassertion of rx_digitalreset Resetting Transceiver Channels CQ se nd Feedback Altera Corporation UG A10XCVR 4 16 Transceiver PHY Reset Controller Resource Utilization 2013 12 02 rx_ready lt n gt Output Synchronous tothe Status signal to indicate when the RX reset 120 Transceiver PHY sequence is complete This signal is deasserted Reset Controller while the RX reset is active It is
286. defined 2 b10 Data block 2 b01 Control Ordered Set Block This value is read when pipe_tx_sync_hdr 1 0 In tx_pma_clk oo Refer to Lane Level Encoding in the PCI Express Base Specification Rev 3 0 for a detailed explanation of data transmission and reception using 128b 130b encoding and decoding Not used for Genl and Gen2 data rates Active High For Gen3 specifies the start block byte location for TX data in the 128 bit block data Used when the interface between the PCS and PHY pipe_tx_blk_start In tx_pma_clk MAC FPGA Core is 32 bits Not used for Gen1 and Gen2 data rates Active High Forces the transmit output to electrical idle Refer to Intel PHY Interface for PCI Express j lecidl In tx_pma_clk Bee oe megs ee PIPE for timing diagrams Active High Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Ports for PCI Express 2 207 pipe_tx_detectrx_ loopback In e _jomel_CALIk Instructs the PHY to start a receive detection operation After power up asserting this signal starts a loopback operation Refer to section 6 4 of Intel PHY Interface for PCI Express PIPE for a timing diagram Active High pipe_tx_compliance In tx_pma_clk Asserted for one cycle to set the running disparity to negative Used when transmitting the compliance pattern Refer to section 6 11 of Intel
287. del for this protocol is shown in the following figure The KR FEC sublayer increases the bit error rate BER performance of 1OGBASE R by providing additional link margin to account for variation in manufacturing and environmental conditions Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 94 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC UG A10XCVR 2013 12 02 Figure 2 38 Transceiver Channel Datapath and Clocking for 10GBASE R 10GBASE R with 1588 Transmitter PMA Transmitter Enhanced PCS FPGA Fabric TX 40 n 5 is Data amp g 58 Bs O Control 3 5 ge E Se a To 1031256 3 je z ee e bx zieje Fi F 8 3 8 o b 66 gr 64 8 x B 3 gt E B 25 MHz 2 156 25 MHz 8 from XGMII Parallel Clock 1 X i 3 i 4 k a 257 8125 MHz 3 _clkout tx_pma_div_clkout gt Receiver PMA Receiver Enhanced PCS rx_pma_div_clkout gt a amp E RX a 3 Data amp E s A 5 Ss 8 5 8 2 8 40 m S a 2 8 a aN o 9 Control 5 z fa c x Bs S Ox Bic 3 z BS bls oop xe gt 8 ae H Bie gt N Fi 3 3 as a 3 Le Bs 2x ad g 3 amp 66 g 3 L eg aE S al a a
288. devices PLL IP is not a part of the transceiver PHY IP Master Local Clock Generation Block Non Bonded and Bonded Clocks Avalon master allows access to Avalon MM reconfiguration registers via the Avalon j Memory Mapped interface It enables PCS PMA and PLL reconfiguration To access avoir the reconfiguration registers implement an Avalon master in the FPGA fabric This is a state machine that facilitates reconfiguration by performing reads and writers through the Avalon interface Avalon MM Interface ot EEE Reconfiguration Registers This block can be either a MAC IP core or a frame generator analyzer or a k data generator analyzer Parallel Data Bus Note 1 The Transceiver PHY IP can be either the Native PHY IP or the 1G 10GbE and 10GBASE KR PHY IP 2 You can either design your own reset controller or use the Altera Transceiver PHY Reset Controller IP Legend E Altera generated IP block E User created IP block Transceiver PHY IP controls the PCS and PMA configurations and transceiver channels functions for all communication protocols 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks
289. e can be used in reduced power mode In GT devices where none of the GT channels are used the transceiver channels can be used as GX channels in standard or reduced power mode Altera Corporation Arria 10 Transceiver PHY Overview CGJ Send Feedback UG A10XCVR 2013 12 02 Arria 10 GX and GT Device Package Details 1 11 Related Information Arria 10 GT Channel Usage on page 2 251 For details about Arria 10 GT channel usage guidelines Arria 10 GX and GT Device Package Details The following tables list package sizes available transceiver channels and PCI Express Hard IP blocks for Arria 10 GX and GT devices Table 1 3 Package Details for GX and GT Devices with Transceivers and HIP Blocks Located on the Left Side Periphery of the Device oie oe re one ee orem orem rom eo Transceiver Transceiver Transceiver Transceiver Transceiver Transceiver Transceiver Transceiver Count PCle Count PCle Count PCle Count PCle Count PCle Count PCle Count PCle Count PCle Hard IP Hard IP Hard IP Hard IP Hard IP Hard IP Hard IP Hard IP Block Block Block Block Block Block Block Block Count Count Count Count Count Count Count Count Table 1 4 Package Details for GX and GT Devices with Transceivers and Hard IP Blocks Located on the Left and Right Side Periphery of the Device SS a SS ee SS ee ee ee Transceiver Count Transceiver Count Transceiver Count Transceiver Co
290. e JEEE 1588 The following tables describe the parameters available If you specify an industry standard protocol in the GUL the Transceiver Native PHY IP prints error messages if the settings specified violate the protocol standard Table 2 9 Enhanced TX FIFO Parameters Note For detailed descriptions of the optional ports that you can enable or disable refer to the Enhanced PCS and PMA Ports on page 2 37 Enable RX TX On Off Enables the double width mode for the RX and TX FIFOs You FIFO double can use double width mode to run FPGA fabric at half the width mode frequency of the PCS TX FIFO Mode Phase Compensation Specifies one of the following modes Register e Phase Compensation The TX FIFO compensates for the clock phase difference between the read tx_clkout and write tx_ Interlaken coreclkin ortx_clkout clocks Basic e Register The TX FIFO is bypassed tx_parallel_data tx_controlandtx_enh_data_valid are registered at the FIFO output You must control t x_enh_data_valid based on gearbox ratio to avoid gearbox underflow or overflow conditions e Interlaken The TX FIFO acts as an elastic buffer In this mode there are additional signals to control the data flow into the FIFO Therefore the FIFO write clock frequency does not have to be the same as the read clock frequency You can control writes to the FIFO with tx_enh_data_valid By monitoring the FIFO flags you can avoid the FIFO full and empty conditions The Inte
291. e PHY the ability to detect to link partners that support 1G 10GbE but have disabled Auto Negotiation If you turn on the Enable automatic speed detection parameter the PHY includes the sequencer block During Auto Negotiation if AN cannot detect Differential Manchester Encoding DME pages from link partner the Sequencer reconfigures to 1GE and 10GE modes Speed Parallel detection until it detects a valid 1G or 1OGbE pattern Table 2 89 Speed Detection LL T opon T Deto Enable automatic speed detection On Off When you turn this option On the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able detect AN data Avalon MM clock frequency MOOS PORMHZ Specifies the clock frequency for phy_mgmt_c1k Link fail inhibit time for 10Gb Ethernet 504 ms Specifies the time before Link_status is set to FAIL or OK A link fails if the Link_fail_ inhibit_time has expired before link_ status is set to OK The legal range is 500 510 ms For more information refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Std 802 3ap 2007 Link fail inhibit time for 1Gb Ethernet Implementing Protocols in Arria 10 Transceivers CJ Send Feedback 40 50 ms Specifies the time before link_status is set to FAIL or OK A link fails if the link_fail_inhibit_ time has expired before Link_status is set to OK The legal range is 40 50
292. e Transceiver Native PHY IP GUI tx_pma_div_clkout Output Clock This is a divided version of the recovered parallel clock It is available when you turn on Enable tx_pma_div_clkout port in the Transceiver Native PHY IP GUI tx_pma_elecidle lt n gt Input Asynchronous When asserted this signal forces the transmitter 1 30 to electrical idle This port has no effect when you configure the transceiver for the PCI Express protocol Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 54 Standard PCS and PMA Ports UG A10XCVR 2013 12 02 tx_pma_qpipullup lt n gt 1 0 Input Asynchronous This port is available if you turn on Enable tx_ pma_gqpipullup port QPI in the Transceiver Native PHY IP GUL It is only used for Quick Path Interconnect QPI applications tx_pma_qpipulldn lt n gt 1 230 Input Asynchronous This port is available if you turn on Enable tx_ pma_qpipulldn port QPI in the Transceiver Native PHY IP GUL It is only used for Quick Path Interconnect QPI applications tx_pma_ txdetectrx lt n gt 1 0 Input Asynchronous This port is available if you turn on Enable tx_ pma_txdetectrx port QPI in the Transceiver Native PHY IP GUI When asserted the receiver detect block in TX PMA detects the presence of a transmitter at the other end of the channel After receiving tx_pma_txdetectrx request the receiver detect block initi
293. e data from serializer while data from receiver serial input pin is ignored by CDR The transmitter buffer sends data normally Transmitter Serial Differential Output Data Arria 10 Transceiver PHY Architecture GJ Send Feedback Transmitter PMA a Parallel Parallel i ata D i Data ee Serializer Data oe Ae Ar Parallel Serial loopback E oe Input erial loopbac Generation Transmitter npu Serial Block PLL fag Clock Receiver PMA a ae Parallel Parallel gt E Deserial Data Receiver Data FPGA CDR eserializer gt PCS E Fabric Serial Clock Parallel Clock Altera Corporation 5 14 Arria 10 Enhanced PCS Architecture Figure 5 18 Diagnostic Loopback Path UG A10XCVR 2013 12 02 The diagnostic loopback path sets the transmitter buffer to transmit data fed directly from the receiver buffer before being processed by the CDR circuitry Data from the serializer is ignored by the transmitter buffer Transmitter Serial Differential Output Data Receiver Serial Input Data Transmitter PMA Fale Parallel Parallel i ata a i Data i Serializer Data ead ahs 1 Parallel S iinta
294. e in the Transceiver Native PHY IP GUI t x_ control is 3 bits If you do not select Enable simplified interface t x_cont ro is 18 bits The following encodings are defined Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Enhanced PCS and PMA Ports 2 39 Description Interlaken With Enable simplified interface on 2 Inversion control Unused Ground Instead of controlled by this bit the Interlaken running disparity is internally maintained by Enhanced PCS built in disparity generator block e 1 Sync Header high indicates a control word low indicates a data word Bit 1 is mutually exclusive with bit 0 e 0 Sync Header high indicates a control word low indicates a data word Bit 0 is mutually exclusive with bit 1 Interlaken With Enable simplified interface off e 17 9 Unused Ground e 8 You can use this bit to insert sync header error or CRC32 errors Functions like tx_err_ ins Refer to the description of tx_err_ins for detailed information e 7 3 Unused Ground e 2 Inversion control Unused Ground Instead of controlled by this bit the Interlaken running disparity is internally maintained by Enhanced PCS built in disparity generator block e 1 Sync Header high indicates a control word low indicates a data word Bit 1 is mutually exclusive with bit 0
295. e on page 5 1 For more information about PMA architecture e Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks e PLLs on page 3 3 PLL architecture and implementation details e Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details e Enhanced PCS and PMA Ports on page 2 37 For detailed information about the available ports in the Basic protocol Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 230 Native PHY IP Parameter Settings for Basic Enhanced PCS and Basic with KR FEC 2013 12 02 Native PHY IP Parameter Settings for Basic Enhanced PCS and Basic with KR FEC Table 2 141 General and Datapath Parameters The first two sections of the MegaWizard Plug In Manager for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver Device speed grade fastest Message level for rule violations error warning Transceiver Configuration Rule Basic Enhanced PCS Basic with KR FEC Transceiver mode TX RX Duplex TX Simplex RX Simplex Number of data channels 1 to 96 Data rate 125 Mbps to 28 1 Gbps Enable reconfiguration between On Off Standard and Enhanced PCS Enable simplified data interface On Off Table 2 142 TX PMA Parameters TX channel bonding mode Non bonded PMA bonding PMA PCS bonding PCS TX cha
296. e speed grade This information is used for PLL frequency validation Reference clock frequency 27 MHz to 700 Specifies the PLL input reference clock frequency MHz Bandwidth Auto Specifies the VCO bandwidth Low Higher bandwidth reduces PLL lock time at the Medu expense of decreased jitter rejection High Number of PLL reference clocks 1to5 Specifies the number of input reference clocks for the fPLL Generally used for data rate reconfiguration Selected reference clock source 0to4 Specifies the initially selected reference clock input to the fPLL Enable fractional mode On Off Enables the fractional frequency synthesis mode This enables the PLL to output frequencies which are not integral multiples of the input reference clock Enable physical output clock On Off parameters Operation mode Direct Specifies the feedback operation mode for the fPLL Normal IQTXRXCLK Enable PCIe clock output port On Off Exposes the p11_pcie_clk port used for PCIe PLLs and Clock Networks CJ Send Feedback Altera Corporation 3 14 fPLL IP UG A10XCVR 2013 12 02 Enable cascade clock output port On Off Enables the cascade source output port for fPLL to fPLL to fPLL cascading fPLL cascading Connect this port to the refclk input port of the cascaded PLL Specifies which core outclk to be 0 3 Specifies the cascading source for fPLL to PLL used as cascading source cascading Enable cas
297. each step of the equalization settings Set ber_time_k_frames 4 d1000 0x43E8 for time bits to match the following values e A value of 3 is about 10 bits about 1 3 seconds e A value of 25 is about 10 bits about 11 seconds e A value of 250 is about 10 bits about 110 seconds Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY Register Definitions 2 137 Word R W Description Addr or RW LD coefficient update 5 0 Reflects the contents of the first 16 bit word of the training frame sent from the local device control channel Normally the bits in this register are read only however when you override training by setting the Ovride Coef enable control bit these bits become writeable The following fields are defined e 5 4 Coefficient 1 update e 2 b11 Reserved e 2 b01 Increment e 2 b10 Decrement e 2 b00 Hold e 3 2 Coefficient 0 update same encoding as 5 4 e 1 0 Coefficient 1 update same encoding as 5 4 For more information refer to bit 10G BASE KR LD coefficient update register bits 1 154 5 0 in Clause 45 2 1 80 3 of IEEE 802 3ap 2007 RO or RW LD Initialize Coefficients When set to 1 requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state When set to 0 continues normal operation For more information refer to 10G BASE KR LD coefficie
298. each time you reset the analog PMA or PLL However you can reset the digital PCS block alone Transceiver Block ro rx_digitalreset rx_ tx_digitalreset tx_ powerdown analogreset analogreset Yes CMU PLL ATX PLL Yes fPLL Yes Receiver Standard PCS Yes Receiver Enhanced PCS Yes Receiver PMA Yes Transmitter Standard PCS Transmitter Enhanced PCS Transmitter PMA Receiver PCIe Gen3 PCS Yes Transmitter PCIe Gen3 PCS Reset Signals for PLL PMA and PCS Blocks The following table shows the signals the reset controller must assert to reset the specified blocks To Reset Blocks Reset Controller Must Assert In Order PLL or CDR 1 pll_powerdown 2 tx_analogreset 3 tx_digitalreset TX PMA or RX PMA 1 tx_analogreset 2 tx_digitalreset TX PCS or RX PCS 1l tx_digitalreset Using the Altera Transceiver PHY Reset Controller Altera s Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in response to PLL lock activity You can use this IP core rather than creating your own user coded reset controller You can define a custom reset sequence for the IP core You can also modify the IP cores s generated clear text Verilog HDL file to implement custom reset logic Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 Using the Altera Transceiver PHY Reset Controller 4 9 The Transceiver PHY
299. eceived has a reverse polarity You can verify this feature by monitoring rx_parallel_data Figure 2 111 RX Polarity Inversion rx_polinv tx_parallel_data 11111100001110111100 i 11111100001110111100 rx_parallel_data 11111100001 00000011110001000011 rx_patterndetect 01 m_syncstatus 11 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 238 RX Bit Reversal 2013 12 02 RX Bit Reversal The RX bit reversal feature can be enabled in low latency basic and basic rate match mode The word aligner is available in any mode bit slip manual or synchronous state machine To enable this feature select the Enable RX bit reversal and Enable rx_std_bitrev_ena port options This adds rx_std_bitrev_ena If there is more than one channel in the design rx_std_bitrev_ena becomes a bus in which each bit corresponds to a channel As long as rx_std_bitrev_ena is asserted the RX data received by the core shows bit reversal You can verify this feature by monitoring rx_parallel_data Figure 2 112 RX Bit Reversal rx_std_bitrev_ena tx_parallel_data 11111100001110111100 rx_parallel_data 11111100001110111100 _ 00111101110000111111 11111100001110111100 rx_patterndetect 01 oo o1 rx_syncstatus 11 RX Byte Reversal The RX byte reversal feature can be enabled in low latency basic and basic rate matc
300. ect rx request the receiver detect block initiates the detection process It is only used for Quick Path Interconnect QPI applications tx_pma_rxfound lt n gt Output Asynchronous This port is available if you turn on Enable tx_rxfound 1 0 port QPI in the Transceiver Native PHY IP GUI Whenasserted indicates that the receiver detect block in TX PMA has detected a transmitter at the other end of the channel It is only used for Quick Path Interconnect QPI applications Table 2 33 Enhanced RX PCS Parallel Data Control and Clocks rx_parallel_ Output rx_ RX parallel data from the RX PCS to the FPGA fabric If you data lt n gt 128 coreclkin select Enable simplified interface in the Transceiver Native 1 0 PHY IP GUI rx_parallel_data includes only the bits Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS and PMA Ports 2 43 required for the configuration you specify Otherwise this interface is 128 bits wide When FPGA fabric PCS interface width is 64 bits single width mode you must ground data 127 64 The following bits are active for narrower interfaces e 32 bit FPGA fabric IF width data 31 0 Unused e 40 bit FPGA fabric IF width data 39 0 Unused e 50 bit FPGA fabric IF width data 49 0 remaining 63 50 unused e 64 bit FPGA fabric IF width data 63 0 When the FPGA fabric PCS interface width is 128 bit
301. ection Parameters on page 2 113 e PHY Analog Parameters on page 2 159 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 156 General Options 2013 12 02 General Options The General Options allow you to specify options common to 1GbE and 10GbE modes Table 2 107 General Options Parameters LL f oons T Peton Initial datapath 10G 1G Specifies the data rate need after reset or power up If you select 1G for the initial datapath the automatic speed detection function is not available Enable internal PCS reconfigura On Off When you turn this option on the core includes tion logic reconfiguration logic to dynamically change the initial configuration Enable IEEE 1588 Precision Time On Off When you turn this option on the core includes Protocol the soft FIFO for 1588 the associated logic and enables the ports required for IEEE 1588 PTP Enable tx_pma_clkout port On Off When you turn this option on the tx_pma_ clkout port is enabled Refer to clock and reset signals section for more information about his port Enable rx_pma_clkout port On Off When you turn this option on the rx_pma_ clkout port is enabled Refer to clock and reset signals section for more information about his port Enable tx_divclk port On Off When you turn this option on the tx_divclk port is enabled Refer to clock and reset signals section for more information about his port
302. ed Deassert rx_analogreset fora minimum duration Of trx_analogreset after device enters user mode The CONF_DONE pin is asserted when the device enters user mode 3 Wait for rx_is_lockedtodata to go high 4 Deassert rx_digitalreset after rx_is_lockedtodata is asserted for a minimum duration of tprp Ifrx_is_lockedtodata is asserted and toggles you must wait another additional tprp duration before deasserting rx_digitalreset The receiver is now out of reset and ready for operation Figure 4 5 Receiver Reset Sequence Following Power Up Device Power Up Device in User Mode rx_analogreset O gt lt Tiniis min 40ns rx_digitalreset gt rx_is_lockedtodata 3 7 rx_cal_busy Note rx_is_lockedtodata might toggle when there is no data at the receiver input rx_is_lockedtoref isa don t care when rx_is_lockedtodata is asserted rx_analogreset must always be followed by rx_digitalreset Resetting Transceiver Channels Altera Corporation CJ Send Feedback z P UG A10XCVR 4 6 Resetting the Receiver During Device Operation 2013 12 02 Resetting the Receiver During Device Operation Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation Use this reset to re establish a link or after dynamic reconfiguration The step numbers correspond to the numbers in the waveform 1 Assert rx_analogreset and rx_digitalreset Ensure that r
303. ed Standard PCS Basic Enhanced PCS 17 PHY IP on page 2 12 18 2 12 19 20 negotiation and sequencer functions 21 22 23 24 Altera Corporation PCI Express Hard IP is also available as a MegaCore function The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page Needs a user created Soft IP for link training auto speed negotiation and sequencer functions PCS Direct support will be available in a future release of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software XAUI PHY IP will be available in a future release of the Quartus II software Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Protocol Transceiver IP Arria 10 Transceiver Protocols and PHY IP Support 2 9 PCS Support Transceiver Configuration Rule 1 Protocol Prese DDR XAUI Native PHY IP Standard and Basic Custom User created Enhanced Standard PCS Basic Enhanced PCS Interlaken CEI 6G 11G Native PHY IP Enhanced Interlaken Interlaken 10x12 5Gbps Interlaken 6x10 3Gbps Interlaken 1x6 25Gbps OTU 4
304. ed The value is rounded up to the nearest clock cycle The default value is 4000 ns of the signals in the figure become buses if you choose separate reset controls The variables in the figure represent the following parameters e lt n gt The number of lanes e lt p gt The number of PLLs Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR nse 2013 12 02 Transceiver PHY Reset Controller Interfaces Figure 4 9 Transceiver PHY Reset Controller IP Core Top Level Signals Transceiver PHY Reset Controller Top Level Signals gt pll_locked lt p gt 1 0 tx_digitalreset lt n gt 1 0 PLL and gt pll_select lt p gt 1 0 tx_analogreset lt n gt 1 0 gt Calibration p tx_cal_busy lt n gt 1 0 tx_ready lt n gt 1 0 t gt j Status rx cal_busy lt n gt 1 0 D TX and RX gt n_is_lockedtodata lt n gt 1 0 rx_digitalreset lt n gt 1 0 _ Resets and Status rx_analogreset lt n gt 1 0 gt rx_ready lt n gt 1 0 _ PLL ix_manual lt n gt 1 0 Control p m_manual lt n gt 1 0 Clock gt clock pll_powerdown lt p gt 1 0 gt PLL Powerdown and Reset gt reset Note PLL control is available when you enable the Expose Port parameter Table 4 4 Top Level Signals This table describes the signals in the above figure in the order that they are shown in the fig
305. ed for Gen3 data rate e fPLL PLL used for Genl and Gen2 data rates e Reset controller e MAC e Data generator The design example exercises the PIPE specific features and blocks The pseudo MAC exercises the control signals and implements part of the LTSSM The data generator exercises various digital decoding blocks The data generator and checker can generate and verify various ordered sets such as TS1 TS2 EIOS EIEOS and SKP OS as well as scrambling and descrambling data while operating at Gen3 rates The PIPE Design Example User Guide located in the PIPE Design File on the Wiki page contains recommendations about SDC timing constraints Note The design examples on the Wiki page provide useful guidance for developing your own designs but they are not guaranteed by Altera Use them with caution Related Information PIPE Design Example Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 216 CPRI 2013 12 02 CPRI The CPRI interface is a high speed serial interface developed for wireless network REC to uplink and downlink data from available remote RE The CPRI protocol defines the interface of radio base stations between the radio equipment controller REC and the radio equipment RE The physical layer supports both the electrical interfaces for example traditional radio base stations and the optical interface for example radio base stations with a remote radio head T
306. ed for this example e Enable Include Master Clock Generation Block and turn ON Enable high frequency serial clock output port 3 Configure the Native PHY IP using the MegaWizard Plug In Manager e Set the Native PHY IP TX Channel bonding mode to either PMA bonding or PMA PCS bonding e Set the number of channels required by your design In this example the number of channels is set to 10 4 Connectivity e Create a top level wrapper to connect the PLL IP to Native PHY IP e In this case the PLL IP has tx_bonding_clocks output bus with width 5 0 e The Native PHY IP has tx_bonding_clocks input bus with width 5 0 multiplied by the number of transceiver channels 10 in this case For 10 channels the bus width will be 50 0 e Connect the PLL to the PHY IP by duplicating the output of the PLL 5 0 for the number of channels For 10 channels the Verilog syntax for the input port connection is tx_bonding_clocks number_of_channels tx_bonding_clocks_output Note Although the above diagram looks similar to the 10 channel non bonded configuration example the clock input ports on the transceiver channels bypass the local CGB in x6 xN bonding configuration This internal connection is taken care of when the Native PHY channel bonding mode is set to Bonded Figure 3 22 x6 xN Bonding Mode Internal Channel Connections Ch2 CGB g CDR Ch1
307. ed tap e Floating tap Enable rx_pma_clkout port On Off Enable rx_pma_div_clkout port On Off rx_pma_div_clkout division factor Disabled 1 2 33 40 50 66 Enable rx_pma_clkslip port On Off Enable rx_pma_qpipulldn port QPI On Off Enable rx_is_lockedtodata port On Off Enable rx_is_lockedtoref port On Off Enable rx_set_locktodata and rx_set_locktoref ports On Off Enable rx_seriallpbken port On Off Enable PRBS verifier control and status ports On Off Table 2 150 Standard PCS Parameters Standard PCS PMA interface width 8 10 16 20 FPGA Fabric Standard TX PCS interface width 8 10 16 20 32 40 FPGA Fabric Standard RX PCS interface width 8 10 16 20 32 40 On Off Enable Standard PCS low latency mode g Off for Basic with Rate Match e low_latency TX FIFO mode register_fifo e low_latency RX FIFO Mode register_fifo Enable tx_std_pcfifo_full port On Off Enable tx_std_pcfifo_empty port On Off Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations 2 249 Enable rx_std_pcfifo_full port On Off Enable rx_std_pcfifo_empty port On Off i e Disabled TX byte serializer mode Serialize x2 S e Disabled RX byte deserializer mode lt Deserialize x2 Enable TX 8B 10B encoder On Off Enable TX 8B 10
308. efined e 15 Next page bit e 14 ACK which is controlled by the SM e 13 Remote Fault bit e 12 10 Pause bits e 9 5 Echoed nonce which are set by the state machine e 4 0 Selector Bit 49 the PRBS bit is generated by the Auto Negotiation TX state machine 0x4C4 31 0 RW User base page high The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages ctrl bit is set The following bits are defined e 29 5 Correspond to page bit 45 21 which are the technology ability e 4 0 Correspond to bits 20 16 which are TX nonce bits Bit 49 the PRBS bit is generated by the Auto Negotiation TX state machine 0x4C5 15 0 RW User Next page low The Auto Negotiation TX state machine uses these bits if the Auto Negotiation next pages ctrl bit is set The following bits are defined e 15 next page bit e 14 ACK controlled by the state machine e 13 Message Page MP bit e 12 ACK2 bit e 11 Toggle bit For more information refer to Clause 73 7 7 1 Next Page encodings of IEEE 802 3ap 2007 Bit 49 the PRBS bit is generated by the Auto Negotiation TX state machine 0x4C6 31 0 RW User Next page high The Auto Negotiation TX state machine uses these bits if the Auto Negotiation next pages ctrl bit is set Bits 31 0 correspond to page bits 47 16 Bit 49 the PRBS bit is generated by the Auto Negotiation TX state machine 0x4C7
309. egaCore Function The frequency is 125 MHz for 1G and 156 25 MHz for 10G This clock is driven from the MAC The frequencies are the same if you enable 1588 or FEC 1G 10GbE GMII Data Interface gmii_tx_d 7 0 Input Synchronousto TX data for 1G mode Synchronized to tx_pma_ i clkout clock The TX PCS 8B 10B module encodes x_pma_ this data which is sent to link partner clkout Omit reed 7 0 Output Synchronous to RX data for 1G mode Synchronized to rx_pma_ clkout clock The RX PCS 8B 10B decoders decodes rx_pma_ this data and sends it to the MAC clkout gmii_tx_en Input Synchronousto When asserted indicates the start of a new frame It should remain asserted until the last byte of data on tx_pma_ p the frame is present on gmii_tx_d clkout gnii tx err Input Synchronousto When asserted indicates an error May be asserted at any time during a frame transfer to indicate an error tx_pma_ 3 in that frame elkong gmii_rx_err Output Synchronous to When asserted indicates an error May be asserted at rx_pma_ any time during a frame transfer to indicate an error clkout in that frame gnii rx cy Output Synchronousto When asserted indicates the start of a new frame It remains asserted until the last byte of data on the rx_pma_ fi s d rame is present on gmii_rx_d clkout MII Data Interface mii ex sa 3 0 Input Synchronousto TX data to be encoded and sent to the link partner Synchronized to the tx_pma_clkout clock cepa
310. eiver PHY reset controller is used the rx_digitalreset is automatically asserted After the rx_digitalreset signal gets asserted the rx_ready status signal is deasserted Assert the rx_set_locktodata signal high after tprg trp manual to switch the CDR to the lock to data mode The rx_is_lockedtodata status signal gets asserted when it acquires lock to the data The rx_is_lockedtoref status signal can be a high or low and can be ignored Deassert the rx_digitalreset signal after tLTD_ Manual After the rx_digitalreset signal is deasserted the rx_ready status signal gets asserted if you are using the Transceiver PHY Reset Controller indicating that the receiver is now ready to receive data with the CDR in manual mode Figure 4 7 Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode Control Signals rx_set_locktoref 2 bre 1mo manar MIN 15 HS rx_set_locktodata rx_digitalreset 2 t min 4 us i LTD_Manual rx_analogreset O Status Signals rx_is_lockedtoref 1 rx_is_lockedtodata 7 rx_ready D i 6 Resetting Transceiver Channels Altera Corporation os Send Feedback UG A10XCVR 4 8 Transceiver Blocks Affected by Reset and Powerdown Signals 2013 12 02 Transceiver Blocks Affected by Reset and Powerdown Signals The following blocks are affected by the specified reset and powerdown signals You must reset the digital PCS
311. eiver PLL Native PHY Instance Instance 5 GHz 10 CH Non Bonded 10 Gbps ATX PLL 4 Transceiver PLL ry Instance 5 GHz ATX PLL _ Il 4 Legend TX channels placed in the same transceiver bank a TX channels placed in the adjacent transceiver bank Steps to implement a Multi Channel x1 Non Bonded Configuration 1 Choose the PLL IP ATX PLL fPLL or CMU PLL you want to instantiate in your design and instantiate the PLL IP e Refer to Instantiating ATX PLL on page 3 5 or Instantiating CMU PLL IP on page 3 21 or Instantiating PLL IP on page 3 13 for detailed steps 2 Configure the PLL IP using the MegaWizard Plug In Manager e For ATX PLL IP set the PLL feedback type to internal and do not include the Master CGB e For fPLL IP set the PLL feedback operation mode to direct e For CMU PLL IP specify the reference clock and the data rate No special configuration rule is required 3 Configure the Native PHY IP using the MegaWizard Plug In Manager e Set the Native PHY IP TX Channel bonding mode to Non Bonded e Set the number of channels as per your design requirement In this example the number of channels is set to 10 4 Connectivity e Create a top level wrapper to connect the PLL IP to Native PHY IP e Thetx_serial_clk output port of the PLL IP represents the high speed serial clock e The Native PHY IP has 10 for this example tx_serial_clk i
312. ement CPRI in Arria 10 Transceivers Before you begin You should be familiar with the Standard PCS and PMA architecture PLL architecture and the reset controller before implementing your CPRI protocol 1 Open the MegaWizard Plug In Manager and select the PHY IP Refer to Select and Instantiate PHY IP on page 2 2 2 Select CPRI Auto or CPRI Manual from the Transceiver configuration rules list located under Datapath Options depending on which protocol you are implementing 3 Use the parameter values in the tables in Native PHY IP Parameter Settings for CPRI on page 2 222 as a starting point Or you can use the protocol presets described in Preset Configuration Options You can then modify the setting to meet your specific requirements 4 Click Finish to generate the Native PHY IP this is your RTL file Figure 2 93 Signals and Ports of Native PHY IP for CPRI Arria 10 Transceiver Native PHY reconfig_reset Bccal_muey NIOS Reconfiguration fo clk rx_cal_busy lt Hard Calibration IP Registers reconngLe 4 gt reconfig_avmm TX PMA TX Standard PCS amp m tx_digital_reset tx_datak 4 tx_datak 1 0 tx_parallel_data tx_parallel_data 15 0 tx_serial_data lt Serializer oe tx_coreclkin tx_coreclkin tx_clkout gt tx_clkout A unused_tx_parallel_data 118 0 4 tx_serial_clkO Local cen y Gene
313. en generator protocol Enable Interlaken On Off When you turn this option on the Enhanced PCS enables the RX disparity disparity checker This option is available for the Interlaken checker protocol Table 2 18 Block Synchronization Enable RX block On Off When you turn this option on the Enhanced PCS enables the RX synchronizer block synchronizer This option is available for the Interlaken and 10GBASE R protocols Enable rx_enh_ On Off Enables the rx_enh_b1k_lock port blk_lock port Table 2 19 Gearbox Parameters Enable TX data On Off When you turn this option on the TX gearbox operates in bitslip bitslip mode Enable TX data On Off When you turn this option on the gearbox inverts the polarity of polarity inversion TX data allowing you to correct incorrect placement and routing on the PCB Enable RX data On Off When you turn this option on the Enhanced PCS RX block bitslip synchronizer operates in bitslip mode Enable RX data On Off When you turn this option on the gearbox inverts the polarity of polarity inversion RX data allowing you to correct incorrect placement and routing on the PCB Enable tx_enh_ On Off Enables the tx_enh_bitslip port bitslip port Enable rx_bitslip On Off Enables the rx_bitslip port port Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS Parameters 2 29 Table
314. enting Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 How to Implement the Basic Enhanced PCS and Basic with KR FEC Transceiver Configuration Rules in Arria 10 2 227 Transceivers Figure 2 96 Transceiver Channel Datapath and Clocking for a Basic with KR FEC Configuration Transmitter PMA Transmitter Enhanced PCS FPGA Fabric 1x 9 Data amp 5 a 64 e _ Ro Control aoe eee E ja 3 B ae cs ZF 64 8 z wW A ci gs 5 tx hf clk z ae 4 a a cpl 156 25 mHz 9 L 88 tx _pma_cik tx_krtec_cik I Parallel Cock 161 13 MHz 3 ae i ae Tesseeesssnnseessenserfesnssssanporeesheneny oc clkout i E 28 g8 5 a WS hg HE UR ee BS el a go g5 Sa s5 S xx Yn g E g F 3 g SE tx_pma_div_clkout eg fo a ncerecenenesnecseeeneeneneesennenszetinents pma div gt a 3 Receiver PMA Receiver Enhanced PCS a 1X_pma_div_clkout g a aieo a ee eee g RX Data amp 3 7 5 A k 8 5 Control hup T lt A i g 8 z D gt 8 gt H L gt ge gt g z n pe 5 8 e ace E S 64 8 x f eg as ow PRP r 5 a Ix Teva clk t gt verifier 156 25 MHz 2 L 28 ea _ Parallel Clock 161 13 MHz 3 T
315. enting Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Control and Status Interfaces 2 123 rx_block_lock Output Synchronous to rx_ Asserted to indicate that the block synchronizer has clkout established synchronization rx_hi_ber Output Synchronous to rx_ Asserted by the BER monitor block to indicate a Sync clkout Header high bit error rate greater than 10 rx is Output Asynchronous signal When asserted indicates the RX channel is locked to lockedtodata input data tx_cal_busy Output Synchronous to When asserted indicates that the TX channel is being mgmt_clk calibrated rx_cal_busy Output Synchronous to When asserted indicates that the RX channel is being mgmt_clk calibrated cale elk ig Input Clock signal This clock is used to calculate the latency of the soft 1G PCS block This clock is only required for when you enable 1588 in 1G mode Its frequency is 80 MHz This clock should have the same PPM as the p11_ ref_clk_1ginput rx_sync_ Output Synchronous to rx_ When asserted indicates the word aligner has aligned status clkout to in incoming word alignment pattern Ex ipcrifos Output Synchronous to tx_ When asserted indicates that the Standard PCS TX error_1g clkout phase compensation FIFO is full rx_pcfifo_ Output Synchronous to rx_ When asserted indicates that the Standard PCS RX error_lg clkout phase compensation FIFO is
316. ents 4 Click Finish to generate the Native PHY IP this is your RTL file Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 72 How to Implement Interlaken in Arria 10 Transceivers Figure 2 21 Signals and Ports of Native PHY IP for Interlaken UG A10XCVR 2013 12 02 Arria 10 Transceiver Native PHY tx_cal_busy lt rx_cal_busy lt tx_serial_data lt Hard Calibration Block Reconfiguration Registers tx_serial_clk or gt tx_bonding_clocks from TX PLL rx_serialloopback 7 gt rx_serial_data gt rx_cdr_refclkO TX PMA Serializer 32 40 64 _ _ gt TX Enhanced PCS reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_clkout tx_coreclkin tx_control 17 0 tx_parallel_data 127 0 tx_enh_data_valid tx_enh_frame_burst_en tx_enh_frame_diag_status 1 0 tx_enh_frame PEE Jil tx_enh_fifo_cnt 3 0 gt tx_enh_fifo_full p gt tx_enh_fifo_pfull gt tx_enh_fifo_empty p gt tx_enh_fifo_pempty tx_analog_reset l rx_is_lockedtodata lt rx_is_lockedtoref lt RX PMA i v CDR 32 40 64 Deserializer RX Enhanced PCS rx_analog_reset 4 rx digital _reset p rx_clkout p gt rx_coreclkin lt 4 gt nx parallel _data 127 0 rx_cont
317. er the GMII is idle This ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted For the GbE protocol any Dx y following a K28 5 comma is replaced by the transmitter with either a D5 6 I1 ordered set or a D16 2 I2 ordered set depending on the current running disparity The Altera Corporation CJ Send Feedback 2 82 Reset Condition for 8B 10B Encoder in GbE GbE with 1588 a exception is when the data following the K28 5 is D21 5 C1 ordered set or D2 2 C2 ordered set If the running disparity before the K28 5 is positive an I1 ordered set is generated If the running disparity is negative a I2 ordered set is generated The disparity at the end of a I1 is the opposite of that at the beginning of the I1 The disparity at the end of a I2 is the same as the beginning running disparity right before the idle code This ensures a negative running disparity at the end of an idle ordered set A Kx y following a K28 5 is not replaced Note D14 3 D24 0 and D15 8 is replaced by D5 6 or D16 2 for I1 and I2 ordered sets D21 5 C1 is not replaced Figure 2 27 Idle Ordered Set Generation Example clock tx_datain y K28 5 Y D14 3 y K28 5 y D24 0 Y K28 5 Y D15 8 Y K28 5 Y D21 5 Y Dxy y tx_dataout X Dxy Y K28 5 Y D5 6 Y K28 5 Y D16 2 x K28 5 x D16 2 Y K28 5 Y D215 y
318. er using soft IP in the FPGA fabric Dynamic Switching Between Gen1 2 5 Gbps and Gen2 5 Gbps In a PIPE configuration Native PHY IP provides an input signal pipe_rate that is functionally equivalent to the RATE signal specified in the PCle specification A low to high transition on this input signal pipe_rate initiates a data rate switch from Gen1 to Gen2 A high to low transition on the input signal initiates a data rate switch from Gen2 to Gen1 Transmitter Electrical Idle Generation The PIPE interface block in Arria 10 devices puts the transmitter buffer in the channel in an electrical idle state when the electrical idle input signal is asserted During electrical idle the transmitter buffer differential and common configuration output voltage levels are compliant to the PCIe Base Specification 2 0 for both PCIe Gen1 and Gen2 data rates The PCle specification requires the transmitter driver to be in electrical idle in certain power states Note For more information about input signal levels required in different power states refer to Power State Management in the next section Power State Management The PCIe specification defines four power states PO POs P1 and P2 that the physical layer device must support to minimize power consumption e PO is the normal operating state during which packet data is transferred on the PCIe link e POs P1 and P2 are low power states into which the physical layer must transitio
319. error occurs Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback igs UG A10XCVR 5 44 Byte Deserializer 2013 12 02 PRBS_DONE is asserted when the PRBS sequence has completed one full cycle The PRBS verifier supports the following modes PRBS 9 G x 14 x x e PRBS 15 G x 1 xt x e PRBS 23 G x 1 x x e PRBS 31 G x 1 x x Byte Deserializer The byte deserializer allows the transceiver to operate at data rates higher than those supported by the FPGA fabric It deserializes the recovered data by multiplying the data width two or four times depending upon the deserialization mode selected The byte deserializer is optional in designs that do not exceed the FPGA fabric interface frequency upper limit and can be bypassed by using the Disabled option in the Quartus II Transceiver Native PHY The byte deserializer operates in disabled deserialize x2 or deserialize x4 mode Figure 5 48 Byte Deserializer Block Diagram Datapath from the Byte Serna iali L Datapath to the RX FIFO Rate Match FIFO gt Deserializer or Word Aligner Low speed 12 parallel clcok l4 Byte Deserializer Disabled Mode In disabled mode the byte deserializer is bypassed The data from the 8B 10B decoder rate match FIFO or word aligner is directly transmitted to the RX FIFO depending on whether or not the 8B 10B decoder and rate match FIFO are enabled Disabled mode
320. erved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN D E RYA 101 Innovation Drive San Jose CA 95134 UG A10XCVR 5 2 Transmitter Buffer 2013 12 02 Figure 5 2 Serializer Block The serializer block sends out the least significant bit LSB of the input data first Dn lt q e e e LSB Serial y Data Parallel DO q D1 lt q D2 e oq Dig Serializer lt D2 lt q Data Serial Parallel D1 lt Clock Clock y
321. essing this word Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 22 TX Gearbox TX Bitslip and Polarity Inversion 2013 12 02 Note The Interlaken disparity generator is available to implement the Interlaken protocol TX Gearbox TX Bitslip and Polarity Inversion The TX gearbox adapts the PCS data width to the smaller bus width of the PCS PMA interface Gearbox Reduction It supports different ratios FPGA fabric PCS Interface Width PCS PMA Interface Width such as 66 32 66 40 67 32 67 40 50 40 64 32 64 40 40 40 32 32 64 64 67 64 and 66 64 The gearbox mux selects a group of consecutive bits from the input data bus depending on the gearbox ratio and the data valid control signals Data valid generation logic is essential for gearbox operation Each block of data is accompanied by tx_enh_data_valid data valid signal which qualifies the block as valid or not The data valid toggling pattern is dependent on the data width conversion ratio For example if the ratio is 66 40 the data valid signal is high in 20 out of 33 cycles or approximately 2 out of 3 cycles and the pattern repeats every 33 tx_clkout TX low speed parallel clock cycles Figure 5 28 66 40 Data Valid Pattern rd_clk of TX FIFO tx_clkout tx_enh_data_valid The TX gearbox also has a bit slipping feature to adjust the data skew between channels The TX paralle
322. et controller You can use the system clock without synchronizing it to the PHY parallel clock The upper limit on the input clock frequency is the frequency achieved in timing closure pll_cal_busy Input A high on this signal indicates the PLL is being calibrated pll_locked Input A high on this signal indicates that the TX PLL is locked to the ref clock tx_cal_busy Input A high on this signal indicates that TX calibration is active If you have multiple PLLs you can OR their p11_cal_busy signals together rx_is_lockedto Input A high on this signal indicates that the RX CDR is in the lock to data data LTD mode Resetting Transceiver Channels Altera Corporation GJ Send Feedback UG A10XCVR 4 18 Combining Status or PLL Lock Signals 2013 12 02 rx_cal_busy Input A high on this signal indicates that RX calibration is active rx_is_lockedtoref Input A high on this signal indicates that the RX CDR is in the lock to reference LTR mode This signal may toggle or be deasserted when the CDR is in LTD mode Combining Status or PLL Lock Signals You can combine multiple PHY status signals before feeding into the reset controller as shown below Figure 4 11 Combining Multiple PHY Status Signals tx_cal_busy signals from channels To reset controller tx_cal_busy input port Note This configuration also applies to the rx_cal_busy signals When using multiple PLLs you can l
323. f rx_enh_fra me_lock this signal is not shown in the above state flow data is written into the RX FIFO after the first alignment word SYNC word is found on that channel Accordingly the RX FIFO partially empty flag rx_enh_fifo_pempty of that channel is asserted The state machine monitors the rx_enh_fifo_pempty and rx_enh_fifo_pfull signals of all channels Ifthe rx_enh_fifo_pempty signals from all ch annels deassert before any channels rx_enh_fifo_pful1 assert which implies the SYNC word has been found on all lanes of the link the MAC layer can start reading from all the RX FIFO by asserting rx_enh _fifo_rd_en simultaneously Otherwise if the rx_enh_fifo_pful1 signal of any channel asserts high before the rx_enh_fifo_pempty signals deassertion on all channels the state macihne needs to flush the RX FIFO by asserting rx_enh_fifo_align_clr high for 4 cycles and repeating the soft deskew process The following figure shows one RX deskew scenario In this scenario all of the RX FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted This indicates the deskew is successful and the FPGA fabric starts reading data from the RX FIFO Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Implement Interlaken in Arria 10 Transceivers Figure 2 20 RX FIFO Deskew rx_enh_fifo_full rx_enh_fifo_empty rx_enh_fifo_rd_en mx_enh_da
324. f you select 1G for the initial datapath the automatic speed detection function is not available Enable internal PCS reconfigura On Off When you turn this option on the core includes tion logic reconfiguration logic to dynamically change the initial configuration Enable IEEE 1588 Precision Time On Off When you turn this option on the core includes Protocol the soft FIFO for 1588 the associated logic and enables the ports required for IEEE 1588 PTP Enable tx_pma_clkout port On Off When you turn this option on the tx_pma_ clkout port is enabled Refer to clock and reset signals section for more information about his port Enable rx_pma_clkout port On Off When you turn this option on the rx_pma_ clkout port is enabled Refer to clock and reset signals section for more information about his port Enable tx_divclk port On Off When you turn this option on the tx_divclk port is enabled Refer to clock and reset signals section for more information about his port Enable rx_divclk port On Off When you turn this option on the rx_divclk port is enabled Refer to clock and reset signals section for more information about his port Enable tx_clkout port On Off When you turn this option on the tx_clkout port is enabled Refer to clock and reset signals section for more information about his port Enable rx_clkout port On Off When you turn this option on the rx_clkout port is enabled Refer to clock and
325. fer to the PLLs and Clock Networks chapter for details about the clock frequencies when using FIFO single and double width modes Register Mode In Register mode tx_parallel_data data tx_cont rol indicates whether tx_parallel_data is a data or control word and tx_enh_data_valid data valid are registered at the FIFO output The FIFO in register mode has one register stage or one parallel clock latency Note You must control the tx_enh_data_valid signal based on the gearbox ratio to avoid overflow or underflow in the gearbox Interlaken Mode In Interlaken mode the TX FIFO operates as an elastic buffer In this mode there are additional signals to control the data flow into the FIFO Therefore the FIFO write clock frequency does not have to be the same as the read clock frequency You control the writing to the TX FIFO with tx_enh_data_validby monitoring the FIFO flags The goal is to prevent the FIFO from becoming full or empty On the read side read enable is controlled by the Interlaken frame generator Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR z 2013 12 02 Basic Mode 5 17 Basic Mode In Basic mode the TX FIFO operates as an elastic buffer where you control the FIFO tx_enh_data_valid based on FIFO flags The FIFO read enable is controlled by gearbox data valid which is a function of gearbox input and output data width Interlaken Frame Generator The Interlaken frame genera
326. fifo_empty _00 tx_enh_fifo_pempty 00 tx_enh_fifo_cnt _ffffff tx_enh_frame 00 tx_enh_frame_burst_en 3 The User Logic Asserts data_valid The TX FIFO The Frame Generator Reads Data from to Send Data to the TX FIFO Based Writes Backpressure the TX FIFO for the Next Metaframe on the FIFO Status RX Multi lane FIFO Deskew State Machine Deskew logic is required at the receiver side to eliminate the lane to lane skew created at the transmitter of the link partner PCB medium and local receiver PMA You can implement a multi lane alignment deskew state machine to control the RX FIFO operation based on available RX FIFO status flags and control signals The following figure shows the state flow of RX FIFO deskew Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback 2 70 RX Multi lane FIFO Deskew State Machine Figure 2 19 RX FIFO Deskew Flow Exit from rx_digitalreset v Deassert all Lane s rx_enh_fifo_rd_en lt ______ All Lane s mx_enh_fifo_pempty Deasserted All Lane s rx_enh_fifo_pfull Deasserted RX FIFO Deskew Completed UG A10XCVR 2013 12 02 Assert rx_enh_fifo_align_clr for at least 4 rx_coreclkin Cycles A Each lane s rx_enh_fifo_rd_en should remain deasserted before the RX FIFO deskew is completed After frame lock is achieved indicated by the assertion o
327. for the Frequency fPLL Switch over Mode Automatic Specifies how input frequency switch over will be handled Manual Aumai Automatic will use built in circuitry to detect if Manual Override one of your input clocks has stopped toggling and switch to another one e Manual will create an EXTSWITCH signal which can be used to manually switch the clock by asserting high for at least 3 clock cycles e Automatic with Manual Override behaves as an Automatic Switch over until the EXTSWITCH goes high in which case it will switch and ignore any automatic switches as long as EXTSWITCH stays high Switch over Delays 0 to 7 Delays the switch over process by the specified number of cycles Createan active_clk On Off Creates an output which indicates the input clock signal to indicate the input clock currently in use by the PLL A logic Low on this signal in use indicates refclk0 is in use and a logic High indicates refc1k1 is in use Create a clkbad signal for On Off Generates 2 CLKBAD outputs one for each input each of the input clocks Altera Corporation clock A logic Low indicates the CLK is present and a logic High indicates the CLK is absent PLLs and Clock Networks GJ Send Feedback UG A10XCVR 2013 12 02 fPLL IP 3 17 Table 3 11 fPLL Generation Options Generates parameter documenta On Off Generates a csv file that contains descriptions of tion file all the PLL parameters
328. frequency synthesis and coarse resolution fractional frequency synthesis The ATX PLL is the transceiver channel s primary transmit PLL It can operate over the full range of supported data rates required for high data rate applications Related Information e ATX PLL on page 3 3 For more information on ATX PLL e ATX PLL IP on page 3 6 For details on implementing the ATX PLL IP Fractional PLL fPLL A fractional PLL fPLL is an alternate transmit PLL used for generating low clock frequencies for low data rate applications fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis Unlike the ATX PLL the fPLL can be used to synthesize frequencies that can drive the core through the FPGA fabric clock networks Related Information e fPLL on page 3 11 For more information on fPLL e fPLL IP on page 3 13 For details on implementing the fPLL IP Channel PLL CMU CDR PLL A channel PLL resides locally within each transceiver channel Its primary function is clock and data recovery in the transceiver channel when the PLL is used in CDR mode The channel PLLs of channel 1 and 4 can be used as a transmit PLL when reconfigured in CMU mode The channel PLLs of channel 0 2 3 and 5 cannot be reconfigured in CMU mode and therefore cannot be used as a transmit PLL Altera Corporation Arria 10 Transceiver PHY Overview CJ Send Feedback UG A10XCVR 2013 12 02 Clock Generation Block CGB 1 21
329. fter receiving data byte D4 tx_parallel_data X D1 Y D2 Y D3 D4 1 D5 y D6 1 D7 D8 1 rx_parallel_data X D1 X D2 Y D3 Y D4 y D6 y D7 1 D8 Y XX I xx x XX pipe_rx_status 2 0 y XXX X XXX y XXX y XXX X 3 b101 Y XXX X XXX Y XXX X Figure 2 71 Rate Match FIFO Empty The rate match FIFO automatically inserts K30 7 9 h1FE after the data byte that causes the FIFO to go empty and drives PIPE status 2 0 3 b110flag synchronous to the inserted K30 7 9 h1FE The figure below shows rate match FIFO empty condition in PIPE mode The rate match FIFO becomes empty after reading out data byte D3 tx_parallel_data y D1 Y D2 Y D3 D4 y D5 Y D6 X rX_parallel_data y D1 X D2 Y D3 1K 30 7 y D4 Y D5 y pipe_rx_status 2 0 X XXX X XXX y XXX 3 b110 Y XXX X XXX y PIPE 0 ppm The PIPE mode also has a 0 ppm configuration option that can be used in synchronous systems The Rate Match FIFO Block is not expected to do any clock compensation in this configuration but latency will be minimized to 3 or 4 cycles PCle Reverse Parallel Loopback PCle reverse parallel loopback is only available in a PCIe functional configuration for Gen1 Gen2 and Gen3 data rates The received serial data passes through the receiver CDR deserializer word aligner and rate matching FIFO buffer The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer The received data is also available to the F
330. full lel ri Input Synchronous to When asserted indicates a Remote Fault RF The xomii tz clk MAC sends this fault signal to its link partner Bit D13 oftheAuto Negotiation Advanced Remote Fault register 0xC2 records this error rx_clkslip Input Asynchronous signal When asserted indicates that the deserializer has either skipped one serial bit or paused the serial clock for one cycle to achieve word alignment As a result the period of the parallel clock could be extended by 1 unit interval UI during the clock slip operation rx_latency__ Output Synchronous to rx_ When you enable 1588 this signal outputs the real adj_ig 11 0 clkout time latency in GMII clock cycles 125 MHz for the RX PCS and PMA datapath for 1G mode tx_latency_ Output Synchronous to tx_ When you enable 1588 this signal outputs real time adj_lg 11 0 clkout latency in GMII clock cycles 125 MHz for the TX PCS and PMA datapath for 1G mode ix latency Output Synchronous to rx_ When you enable 1588 this signal outputs the real acdj_lOg lis 0 clkout time latency in XGMII clock cycles 156 25 MHz for the RX PCS and PMA datapath for 10G mode tx_latency_ Output Synchronous to tx_ When you enable 1588 this signal outputs real time adj_10g 11 0 clkout latency in XGMII clock cycles 156 25 MHz for the TX PCS and PMA datapath for 10G mode CJ Send Feedback Implementing Protocols in Arria 10 Transceivers Altera Corporation 2
331. g synchronization header 9 0 Unused Basic mode 128 bit data including synchronization header 19 Active high status signal indicating when Block Lock is achieved 18 Active high status signal that indicates a sync header error 17 12 Unused 11 Sync Header 1 indicates a control word 10 Sync Header 1 indicates a data word Basic mode 128 bit data excluding synchronization header 19 10 Unused Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2013 12 02 2 46 Enhanced PCS and PMA Ports unused_rx_ Output r These signals only exist when you turn on Enable simplified control f lt 7 10 coreclkin interface These outputs can be left floating Lgo rx_coreclkin Input Clock The FPGA fabric clock Drives the read side of the RX FIFO For Interlaken protocol the frequency of this clock could be from datarate 67 to datarate 32 If the frequency is too much higher than the frequency of rx_clkout the RX FIFO flags might be unable to update in time and cause data corruption rz Clkout Output Clock The low speed parallel clock generated by the transceiver RX PMA This clock times the blocks in the RX Enhanced PCS The frequency of this clock is equal to data rate divided by PCS PMA interface width rx_serial_data Input N A Serial data input to the RX PMA rx_cdr_refclk0 Input Clock
332. g the logical reference clock follow this procedure to switch to the selected CDR reference clock 1 Read from the logical reference clock offset and save the required 8 bit pattern For example switching to logical re fc1k3 requires saving bits 7 0 of offset 0x161 D 2 Perform a read modify write to bits 7 0 of offset 0x141 using the 8 bit value obtained from the logical refclk offset 3 Complete the required reset sequence Changing PMA Analog Parameters You can use the reconfiguration interface on the Transceiver Native PHY IP to change the value of PMA analog features Transceiver Native PHY IP configuration files do not contain analog settings Set analog parameters using Quartus II Settings File qsf variables or these steps To change any of the PMA analog features 1 Read from the PMA analog feature offset of the channel you want to change For example change pre emphasis 1 post tap read and store the value of offset 0x105 2 Select a valid value for the feature according to the Arria 10 register map For example a valid setting for pre emphasis 1 post tap is fir_post_1t_l1 which has a bit encoding of 6 b000001 3 Perform a read modify write to the offset of the PMA analog feature using the valid value For example changing the pre emphasis 1 post tap to setting fir_post_1t_l1 you must write 6 b000001 to offset 0x105 Table 6 11 PMA Analog Feature Offsets Pre emp
333. gmii_sdr_ctrl1 4 Lane4 control xgmii_rx_dc 52 45 xgmii_sdr_ Lane 5 data data 47 40 Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Serial Data Interface 2 165 zomi rz Cle 53 xgmii_sdr_ctrl1 5 Lane5control xgmii_rx_dc 61 54 xgmii_sdr_ Lane 6 data data 55 48 zomi rx delez xgmii_sdr_ctrl 6 Lane 6 control xgmii_rx_dc 70 63 xgmii_sdr_ Lane 7 data data 63 56 xgmii_rx_dc 71 xgmii_sdr_ctrl 7 Lane7 control Serial Data Interface This topic describes the serial data interface rx_serial_data Input RX serial input data tx_serial_ data Control and Status Interfaces Output TX serial output data The XGMII and GMII interface signals drive data to and from PHY Table 2 116 Control and Status Signals led_char_err Output Synchronous to rx_ 10 bit character error Asserted for one rx_clkout_lg elkout cycle when an erroneous 10 bit character is detected led link Output Synchronous to rx_ When asserted indicates successful link synchroniza clkout tion led_disp_err Output Synchronous to rx_ Disparity error signal indicating a 10 bit running clkout disparity error Asserted for one rx_clkout_lg parity cycle when a disparity error is detected A running disparity error indicates that more than the previous and perhaps the current received group had an error led_an Output Synchronous
334. gt an CH2 Bank CH1 CHO Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank PCle Gen1 Gen3 Hard IP with CvP Transceiver Bank Note 1 These devices have transceivers only on the left hand side of the device Legend PCle Gen 3 HIP blocks with CvP capabilities 1 PCle Gen 3 HIP blocks without CvP capabilities Arria 10 SX device with 24 transceiver channels and two PCle Hard IP blocks Arria 10 SX device with 36 transceiver channels and two PCle Hard IP blocks BS Arria 10 SX device with 48 transceiver channels and two PCle Hard IP blocks Arria 10 Transceiver PHY Overview Altera Corporation CJ Send Feedback 1 14 Arria 10 SX Device Package Details UG A10XCVR 2013 12 02 Figure 1 12 Arria 10 SX Device with 12 and 6 Transceiver Channels and One Hard IP Block Transceiver PCle Transceiver Gent Gen3 CH2 Bank Hard IP with CvP Transceiver Bank Note 1 These devices have transceivers only on the left hand side of the device Legend PCle Gen3 HIP blocks with CvP capabilities E Arria 10 SX device with 12 transceiver channels and one Hard IP block Figure
335. guring the word aligner in CPRI Manual the word aligner parses the incoming data stream for a specific alignment character After rx_digitalreset deasserts asserting the rx_std_wa_patternalign triggers the word aligner to look for the predefined word alignment pattern or its complement in the received data stream and automatically synchronizes to the new word boundary Any alignment pattern found thereafter in a different word boundary causes the word aligner to resynchronize to this new word boundary if the rx_std_wa_patternalign remains asserted If you deassert rx_std_wa_patternalign the word aligner maintains the current word boundary even when it finds the alignment pattern in a new word boundary When the word aligner is synchronized to the new word boundary rx_patterndetect and rx_syncstatus are assert for one parallel clock cycle Figure 2 92 Word Aligner in Manual Alignment Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data 0 fle4b6e4 b9dbfidb 915d061d e13f913f_ 7a4ae24a bcbc7b78 bcbcbcbc 95cd3c50 91c295cd ded691c2 rx_patterndetect 0 1100 1111 0000 rx_syncstatus 0000 1100 1111 Related Information Word Aligner on page 5 37 Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 220 How to Implement CPRI in Arria 10 Transceivers 2013 12 02 How to Impl
336. h Word Aligner The word aligner receives the serial data from the PMA and realigns the serial data to have the correct word boundary according to the word alignment pattern configured This word alignment pattern can be 7 8 10 16 20 32 and 40 bits in length Depending on your PCS PMA interface width the word aligner can be configured in one of the following modes e Bit slip e Manual alignment e Synchronous state machine e Deterministic latency Figure 5 45 Word Aligner Conditions and Modes Word Aligner Vv v Single Double Width Width v v v v 8 Bit 10 Bit 16 Bit 20 Bit Bit Slip Manual Bit Slip Deterministic Synchronous Manual Bit Slip Manual Bit Slip Deterministic Synchronous Manual Latency 1 State Machine Latency 1 State Machine Note 1 This option is available in CPRI mode Word Aligner Bit Slip Mode In bit slip mode the word aligner operation is controlled by rx_bitslip which has to be held for two parallel clock cycles At every rising edge of rx_bits1lip the bit slip circuitry slips one bit into the received data stream effectively shifting the word boundary by one bit Pattern detection is not used in bit slipping mode therefore rx_syncstatus is not valid in this mode Word Aligner Manual Mode In manual alignment mode the word aligner operation is controlled by rx_std_wa_patternalign The word aligner operation is edge sensitive or level sensitive to rx_std_wa_p
337. h FIFO fifo_pempty fifo_pfull rd_en wr_en SKIP L p Asynchronous SKIP Qata out Inserter FIFO Deleter Catanin data data rd_clk wr_clk RX FIFO Shared with Standard and Enhanced PCS The RX FIFO in each channel ensures a reliable transfer of data and status signals between the PCS channel and the FPGA fabric The RX FIFO compensates for the phase difference between the parallel PCS clock and the FPGA fabric clock In PIPE mode the RX FIFO works in low latency mode Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 PIPE Interface 5 49 Related Information Arria 10 Standard PCS Architecture on page 5 31 For more information about RX FIFO PIPE Interface This section describes the Auto Speed Negotiation and the Clock Data Recovery Control of the Gen3 PIPE interface Auto Speed Negotiation Auto speed negotiation controls the operating speed of the transceiver when operating under PIPE 3 0 modes By monitoring the rate control signal from the PHY MAC this feature changes the transceiver from PIPE Gen operation mode to Gen2 operation mode or from PIPE Gen operation mode to Gen2 operation mode to Gen3 operation mode or vice versa The switches among the Gen1 Gen2 and Gen3 data rates involve a reconfiguration of the PMA and PCS settings The PMA must re lock and provide a TX PLL clock and its CDR will also lock at a new i
338. h as CPRI RX FIFO mode low_latency register_fifo The following 2 modes are available e low_latency This mode adds 2 3 cycles of latency to the RX datapath e register_fifo In this mode the FIFO is replaced by registers to reduce the latency through the PCS Use this mode for protocols that require deterministic latency such as CPRI Enable tx_std_ On Off Enables the tx_std_pcfifo_full port pcfifo_full port Enable tx_std_ On Off Enables the tx_std_pcfifo_empty port pcfifo_empty port Enable rx_std_ On Off Enables the rx_std_pcfifo_full port pcfifo_full port Enable rx_std_ On Off Enables the rx_std_pcfifo_empty port pcfifo_empty port Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS Parameters 2 31 Table 2 23 Byte Serializer and Deserializer Parameters Enable TX byte Disabled Specifies the TX byte serializer mode for the Standard PCS The serializer Serialize x2 transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer The Serialize x4 byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths Serialize x4 is only applicable in PCIe mode Enable RX byte Disabled Specifies the mode for the RX byte deserializer in the Standard deserializer Deserialize x2 PCS The transceiver a
339. h mode whereas the word aligner is available in any mode To enable this feature select the Enable RX byte reversal and Enable rx_std_byterev_ena port options This adds rx_std_byterev_ena If there is more than one channel in the design rx_std_byterev_ena becomes a bus in which each bit corresponds to a channel As long as rx_std_byterev_ena is asserted the RX data received by the core shows byte reversal You can verify this feature by monitoring rx_parallel_data Figure 2 113 RX Byte Reversal rx_std_byterev_ena tx_parallel_data 11111100001110111100 m parallel data 111111 11101111001111110000 11111100001110111100 rX_patterndetect 01 10 o1 rx_syncstatus 11 Rate Match FIFO in Basic Single Width Mode Only rate match FIFO operation is covered in these steps 1 Select basic single width in the RX rate match FIFO mode list 2 Enter values for the following parameters RX rate match insert delete ve pattern 20 bits of data The first 10 bits correspond to the skip hex specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern The skip pattern must have neutral disparity Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Rate Match FIFO in Basic Single Width Mode 2 239 RX rate match insert delete ve pattern 20 bits of data The first 10 bits correspond to the skip he
340. h six channels one located at the top and the other at the bottom of the bank Transceiver banks with three channels have only one fPLL For transceiver and PLL cascading applications the fPLL can support continuous data rates from 611 Mbps to 12 5 Gbps in both integer and fractional frequency synthesis modes PLL cascading enables additional flexibility in terms of reference clock selection When used to drive the FPGA fabric s core clock network the PLL can support frequencies from 27 MHz up to the core clock network s maximum frequency fmax Figure 3 3 fPLL Block Diagram Refclk Multiplexer L Counter aa 1 2 48 gt edicated reference clock pin ___ Reference clock network gt Up Charge Receiver input pin N Counter gt PFD tone p VCO M Counter Output of another PLL gt Down A with PLL cascading Delta Sigma Modulator C Counter The fPLL generates output clocks with a fixed frequency and phase relation to an input reference clock The resolution of the fractional loop counter in the fPLL is and it can support fractional frequency modes for data rates from 611 Mbps to 12 5 Gbps Input Reference Clock This is the dedicated input reference clock source for the PLL The input reference clock can be sourced from either a dedicated reference clock pin or the reference clock network or a receiver input pin or the output of another PLL with PLL cascadi
341. hasis 1 post tap 0x105 5 0 Pre emphasis 1 post tap polarity 0x105 6 Pre emphasis 2 post tap 0x106 4 0 Pre emphasis 2 post tap polarity 0x106 5 Pre emphasis 1 pre tap 0x107 4 0 Pre emphasis 1 pre tap polarity 0x107 5 Pre emphasis 2 pre tap 0x108 3 0 Pre emphasis 2 pre tap polarity 0x108 4 Differential output voltage Vod 0x109 5 0 Pre emphasis 2 pre tap polarity 0x109 6 Using Data Pattern Generators and Checkers The Arria 10 transceivers contain hardened data generators and checkers to provide a simple and easy way to verify and characterize high speed links Hardening the data generators and verifiers saves FPGA core logic resources The pattern generator block supports the following patterns Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback Altera Corporation UG A10XCVR 6 14 Using PRBS and Square Wave Data Pattern Generator and Checker 2013 12 02 e Pseudo Random Binary Sequence PRBS e Pseudo Random Pattern PRP e Square wave Note The pattern generators and verifiers are supported only for non bonded channels Using PRBS and Square Wave Data Pattern Generator and Checker You can use PRBS to simulate traffic and easily characterize high speed links without developing or fully implementing any upper layer of a protocol stack The PRBS generator generates a self aligning pattern that doesn t require bit slipping or word alignment for a pattern lock Because
342. have to manually enable the MCGB for bonding applications PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR Enable bonding clock output On Off Enables the t x_bonding_clocks output ports of ports master CGB used for channel bonding This option should be turned ON for bonded designs Enable feedback compensation On Off Enables the feedback output path of the master CGB bonding output port used for feedback compensation bonding PMA interface width 8 10 16 20 32 Specifies PMA PCS interface width 40 64 Proper value must be selected for generating bonding clocks for Native PHY IP This value should match the PMA interface width selected for the Native PHY IUB Table 3 4 ATX PLL Dynamic Reconfiguration Enable reconfiguration On Off Enables the PLL reconfiguration interface Enables the simulation models and adds more ports for reconfiguration Configuration file prefix Enter the prefix name for the configuration files to be generated Generate SystemVerilog package On Off Generates a SystemVerilog package file containing all file relevant parameters used by the PLL Generate C header file On Off Generates a C header file containing all relevant parameters used by the PLL Generate MIF Memory Initialize On Off Generates a MIF file which contains the current File configuration Use this option for reconfiguration purposes in order to switch between different PLL c
343. he PCS is not locked to received blocks 0x482 3 RO TX_FULL When set to 1 the TX_F IFO is full 4 RO RX_FULL When set to 1 the RX_F IFO is full 5 RO RX_SYNC_HEAD_ERROR When set to 1 indicates an RX synchronization error 6 RO RX_SCRAMBLER_ERROR When set to 1 indicates an RX scrambler error 7 RO Rx_DATA_READY When set to 1 indicates the PHY is ready to receive data Arria 10 GMII PCS Registers This topic describes the GMI PCS registers Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 172 Arria 10 GMII PCS Registers UG A10XCVR 2013 12 02 A RESTART_ Set this bit to 1 to restart the Clause 37 Auto Negotiation AUTO_ sequence For normal operation set this bit to 0 which NEGOTIATION is the default value This bit is self clearing 12 RW AUTO_ Set this bit to 1 to enable Clause 37 Auto Negotiation 0x490 NEGOTIATION_ The default value is 1 ENABLE 15 RW Reset Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines comma detection function and the 8B 10B encoder and decoder For normal operation set this bit to 0 This bit self clears 2 R LINK_STATUS A value of 1 indicates that a valid link is operating A value of 0 indicates an invalid link If link synchroniza tion is lost this bit is 0 3 R AUTO_ A value of 1 indicates that the PCS function suppor
344. he rx_std_bitrev_ bitrev_ena port ena control port causes the RX data order to be reversed from the normal order LSB to MSB to the opposite MSB to LSB Enable RX byte On Off When you turn this option on the word aligner reverses the byte reversal order before storing the data in the RX FIFO This function allows you to reverse the order of bytes that were erroneously swapped The PCS can swap the ordering of both 8 and10 bit words When the PCS PMA interface width is 16 or 20 bits the PCS can swap the ordering of the individual 8 or 10 bit words This option is not valid under some Transceiver configuration rules When you enable Enable RX byte reversal you must also enable Enable rx_std_byterev_ena port Enable rx_std_ On Off When you turn this option on asserting rx_std_byterev_ byterev_ena port ena input control port causes swaps the order of the individual 8 or 10 bit words received from the PMA Enable RX On Off When this option is on the rx_std_polinv port controls polarity inversion polarity inversion of RX parallel data When you turn on this parameter you also need to enable Enable rx_polinv port Enable rx_polinv On Off When you turn this option on the rx_pol inv input is enabled port You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout Enable rx_std_ On Off When you turn this option on the optional rx_std_ signalde
345. he scope of the CPRI specification is restricted to the link interface only which is a point to point interface The link has all the features necessary to enable a simple and robust usage of any given REC and RE network topology including a direct interconnection of multiport REs Transceiver Channel Datapath and Clocking for CPRI You can accurately compute the transceiver datapath latencies when using the CPRI protocol standardized interfaces Figure 2 89 Transceiver Channel Datapath and Clocking for CPRI Transmitter PMA Transmitter Standard PCS FPGA Fabric D g 3 z g 8 as lt lt Eo S I ia p S ax 5 d 3 PRBS Generator t_coreclkin 245 MHz tx_clkout 4 Ji y es 245 MH 12 14 tx_pma_div_clkout beidko t Receiver PMA Receiver Standard PCS z S ir 7 4 5 5 7 32 2 p o a z 2 SPs 2 Mp gt 9 ze aR m gt P F 4 8 F 5 e foy re rx_coreclkin Parallel Clock lt Recovered ih rx_clkout 4 gt 4 245 MHz tx_clkout EEN 245 MHz Parallel Clock 12 14 rx_clkout or From Clock PRBS tx_clkout Divider Verifier rx_pma_div_clkout Clock Generation Block CGB A
346. header error insertion On Off Table 2 77 Scrambler and Descrambler Parameters Enable TX scrambler 10GBASE R On Interlaken TX scrambler seed 1OGBASE R OxO3 fFFTEETFFTTETT Interlaken Enable RX descrambler 1OGBASE R On Interlaken Table 2 78 Block Sync Parameters Enable RX block synchronizer On Table 2 79 Gearbox Parameters Enable TX data polarity inversion On Off Enable RX data polarity inversion On Off Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 102 Native PHY IP Ports for 10GBASE R and 10GBASE R with 1588 Transceiver Configurations 2013 12 02 Table 2 80 Dynamic Reconfiguration Parameters Enable dynamic reconfiguration On Off Share reconfiguration interface On Off Enable embedded JTAG AVMM master On Off Table 2 81 Configuration Files Parameters Configuration file prefix Generate SystemVerilog package file On Off Generate C header file On Off Generate MIF Memory Initialization On Off File Table 2 82 Generation Options Parameters Generate parameter documentation file On Off Native PHY IP Ports for 10GBASE R and 10GBASE R with 1588 Transceiver Configurations Figure 2 45 High BER This figure shows the rx_enh_highber status signal going high when there are errors on the rx_parallel_data output rx_parallel_data 11223344556677
347. hitecttres c ccsccsisosssscacssatssodosacadsonseassoseactonsdonsneacas 5 1 Atria 10 PMA Archit ct tesesnnnnnaan in nn Rn RE A A R 5 1 Transmittetouniiiiai ira ia a E E E G EEEE EEN 5 1 RECEIVED ETE E ET 5 4 URE DAC Wo casa N AEE EE 5 13 Arria 10 Enhanced PCS Ave teC tare sips eisiasspecassusiashdcarnsnanuonsdsuecdsausainisnssiubosteassevaashicacasnoidensiasinddeaons 5 14 Transmitter DATA A a cannsssnasssubsnspsnhdasonvnsosvivuansraedocssvnraandacassiadtanssaptatacudsuddssateswanssduchapsonasatbevimaasi 5 15 Receiver Datapatlts sisinccdscasstsas raven cisunmininetanredi anann 5 23 Atria 10 Standard PCS A CNC CLA Cia sahscasnteaniccctemrsssiid terecaubenasasnra Medanncanuctudmnaaconmniammienmiaraes 5 31 Transmitter Datapathiiv scoscsccscvesecanssesusesesceossostsavescesssontuavests ohaseviacsendessoediavhehsecbseeodsobanstunavenbsbceeee 5 31 Receiver Datapath EE E E A E N A EEE 5 37 Arria 10 PCI Express Gen3 PCS Arc te cine sisisi isirssiissssssiisrinisiisiii iiis 5 45 Transmitter Datapathivscscsssssssc ssncessersvcesuiaprerseiestaasenersaveveeisaascdacrvenhsvaneea need ervencondvecrnevecsoeentenatideens 5 47 Receiver TMA tai esate cesocp hens edscebaaa eons TAEAE EAREN EAE 5 48 PIPE nitertac E tices wiedona decir A EE 5 49 Reconfiguration Interface and Dynamic Reconfiguration ccssccsseeeeees 6 1 Ports and P aA 1S aia adaaisc gus tcaest vastus casecv onc anedbascekofhaboneabaneneodeastesduad eben echan E CRAEN ARE ESERLERE 6 1 Inter
348. i 1 Interpreter 1 l isa gt To FPGA Fabric Yv y Checker i Vref ODI e l Generator gt Sampler ia Deserializer gt l i i 1 ODl in Arria 10 transceivers uses a phase interpreter to generate a horizontal offset and the voltage reference Vref generator to generate a vertical offset to get the ODI sample By comparing the bit difference between the CDR sample and the ODI sample in the bit error register checker ODI can monitor link margin over live traffic ODI in Arria 10 transceivers provides 64 horizontal steps and 128 vertical steps to monitor eye margin You can set both horizontal and vertical steps through the Avalon MM registers Figure 5 14 Bit Error Register Checker 64 Steps lt gt A ODI Sample CDR Vertical 128 Steps Sample e p gt Offset Horizontal Offset y Clock Data Recovery CDR Unit The PMA of each channel includes a channel PLL that you can configure as a receiver clock data recovery CDR for the receiver or a clock multiplier unit CMU PLL for the transmitter Altera Corporation Arria 10 Transceiver PHY Architecture J Send Feedback UG A10XCVR 2013 12 02 Lock to Reference Mode 5 11 Figure 5 15 Channel PLL Configured as CDR Channel PLL bp 1x is lockedtodata LTRILTD gt Recovered Clock Controller L pE 1
349. idelines while designing with the 1OGBASE KR PHY IP Using the 10GBASE KR PHY without the Sequencer The sequencer brings up channel based initial datapath and performs parallel detection To use 1OGBASE KR PHY without the Sequencer turn off the Enable automatic speed detection parameter Turning off the sequencer results in the following additional ports e rc_busy e start_pcs_reconfig e mode_lg_l0gbar These ports are used to request manual reconfiguration The following figure shows the relationship of these ports for requesting 1G and 10G configuration The reconfiguration is complete when the rc_busy signal goes low Figure 2 56 Timing for Reconfiguration without the Sequencer mgmt_clk rc_busy start_pcs_reconfig mode_1g_10bar 1588 Delay Requirements The 1588 protocol requires symmetric delays or known asymmetric delays for all external connections In calculating the delays for all external connections you must consider the delay contributions of the following elements e The PCB traces e The backplane traces e The delay through connectors e The delay through cables Accurate calculation of the channel to channel delay is important in ensuring the overall system accuracy Channel Placement Guidelines The channels of multi channel 1G 10G designs do not need to be placed contiguously However channels instantiated in different tr
350. ies and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment These files are in clear text Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 62 Interlaken UG A10XCVR 2013 12 02 Table 2 50 Transceiver Native PHY Files and Directories _ _ E _ lt project_dir gt The top level project directory lt instance_name gt v or vhd The top level design file lt instance_name gt qip A list of all files necessary for Quartus II compilation lt instance_name gt bsf A Block Symbol File bsf for your Transceiver Native PHY instance lt project_dir gt lt instance_name gt The directory that stores the HDL files that define the protocol specific Transceiver Native PHY IP These files are used for synthesis lt project_dir gt lt instance_name gt _sim altera_xcvr_ lt PHY_IP_name gt The simulation directory Simulation files for Riviera PRO simulation tools lt project_dir gt lt instance_name gt _sim aldec lt project_dir gt lt instance_name gt _sim cadence Simulation files for Cadence simulation tools lt project_dir gt lt instance_name gt _sim mentor Simulation files for Mentor simulation tools lt project_dir gt lt instance_name gt _sim synopsys Simulation files for Synopsys simulation tool
351. ifies the data interface width between the Standard PCS and PMA interface the transceiver PMA width Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback Standard PCS Parameters UG A10XCVR 2013 12 02 FPGA fabric 8 10 16 20 32 40 Shows the FPGA fabric to TX PCS interface width This value is Standard TX PCS determined by the current configuration of individual blocks interface width within the Standard TX PCS datapath FPGA fabric 8 10 16 20 32 40 Shows the FPGA fabric to RX PCS interface width This value is Standard RX PCS determined by the current configuration of individual blocks interface width within the Standard RX PCS datapath Enable Standard On Off Enables the low latency path for the Standard PCS All individual PCS low latency functional blocks within the Standard PCS are bypassed to provide mode the lowest latency You cannot turn on this parameter while using Table 2 22 TX and RX FIFO Parameters the Basic Custom w Rate Match Standard PCS specified for Transceiver configuration rules TX FIFO mode low_latency register_fifo Specifies the Standard PCS TX FIFO mode The following 2 modes are available e low_latency This mode adds 2 3 cycles of latency to the TX datapath e register_fifo In this mode the FIFO is replaced by registers to reduce the latency through the PCS Use this mode for protocols that require deterministic latency suc
352. ign For a description of these options refer to the Transceiver PHY Reset Controller Parameters Click Finish The wizard generates files representing your parameterized IP variation for synthesis and simulation Transceiver PHY Reset Controller Parameters The Quartus II software provides a GUI to define and instantiate a Transceiver PHY Reset Controller to reset transceiver PHY and external PLL Table 4 3 General Options SS Dean Number of transceiver channels 1 1000 Specifies the number of channels that connect to the Transceiver PHY Reset Controller IP core The upper limit of the range is determined by your FPGA architecture Number of TX PLLS 1 1000 Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller IP core Input clock frequency 1 500 MHz Input clock to the transceiver PHY Reset Controller IP core The frequency of the input clock in MHz The upper limit on the input clock frequency is the frequency achieved in timing closure Synchronize reset input On Off When On the Transceiver PHY Reset Controller synchronizes the reset to the Transceiver PHY Reset Controller input clock before driving it to the internal reset logic When Off the reset input is not synchronized Use fast reset for simulation On Off When On the Transceiver PHY Reset Controller uses reduced reset counters for simulation TX PLL Enable TX PLL channel reset control On Off When On
353. igure shown is just one possible combination for the PCle Gen1 Gen2 Gen3 x8 mode 2 The x6 and xN clock networks are used for channel bonding applications 3 Each master CGB drives one set of x6 clock lines The x6 lines further drive the xN lines 4 Gen1 Gen2 x8 use the fPLL ONLY 5 Gen3 mode uses the ATX PLL ONLY 6 Use the pll_pcie_clk from the fPLL configured as Gen1 Genz2 This is the hclk required by the PIPE interface Related Information e PIPE Design Example For more information about the PLL MegaWizard configuration for PCIe e Using PLLs and Clock Networks on page 3 40 For more information about implementing clock configurations and configuring PLLs Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Implement PCI Express in Arria 10 Transceivers 2 197 How to Implement PCI Express in Arria 10 Transceivers Before you begin You must be familiar with Standard PCS architecture Gen3 architecture PLL architecture and the reset controller before implementing the PCI Express protocol 1 Open the MegaWizard Plug In Manager and select the Arria 10 Transceiver Native PHY IP Refer to Select and Instantiate PHY IP on page 2 2 for more details Select PIPE Gen1 Gen2 Gen3 from the Transceiver configuration rules list located under Datapath Options Use the parameter values in the tables in Native PHY IP Parameter Settings for PCI Express as a starting po
354. ile or MIF file types All configuration files are stored in lt IP instance name gt reconfig All configuration files generated for a particular IP instance contain the same configuration data The configuration file generates in the format you select For example the System Verilog package file type generates a System Verilog sv file type that contains a two dimension data array The data array stores either channel or PLL offsets depending on the configuration file generated including bitmasks and bit values Typical SystemVerilog Configuration File Line 26 hOO8FFO4 25 16 DPRIO address 0x008 15 8 bit mask OxFF 7 7 hssi_tx_pcs_pma_interface_pldif_datawidth_mode pldif_data_10bit 1 h0O 6 5 hssi_tx_pcs_pma_interface_tx_pma_data_sel ten_g_pcs 2 h0O 4 4 hssi_tx_pcs_pma_interface_prbs_gen_pat prbs_gen_dis 1 h0O 3 0 hssi_tx_pcs_pma_interface_sq_wave_num sq_wave_default 4 h4 Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation CJ Send Feedback 3 z z UG A10XCVR 6 8 Using Configuration Files 2013 12 02 localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_VALUE poldif_data_1l0bit localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_OFST 8 ocalparam HSSI_TX_PCS_PMA __ localparam HSSI_TX_PCS_PMA __ localparam HSSI_TX_PCS_PMA __ localparam HSSI_TX_PCS_PMA __ 32 h00000080 localparam HSSI_TX_PCS_PMA _ 32 h00000000 localparam
355. imilar to the TX FIFO phase compensation in double width mode Register Mode In Register mode rx_parallel_data data rx_cont rol indicates whether rx_parallel_data is a data or control word and rx_enh_data_valid data valid are registered at the FIFO output The RX FIFO in register mode has one register stage or one parallel clock latency Interlaken Mode In Interlaken mode the RX FIFO operates as an Interlaken deskew FIFO To implement the deskew process implement an FSM that controls the FIFO operation based on available FPGA input and output flags For example after frame lock is achieved data is written after the first alignment word SYNC word is found on that channel As a result rx_enh_fifo_pempty FIFO partially empty flag of that channel goes low You must monitor the rx_enh_fifo_pemptyand rx_enh_fifo_pful flags ofall channels Ifrx_enh_fifo_pempty flags from all channels deassert before any rx_enh_fifo_pful flag asserts which implies alignment word has been found on all lanes of the link you start reading from all the FIFOs by asserting rx_enh_fifo_rd_en Otherwise ifa rx_enh_fifo_pful1 flag from any channel goes high before a rx_enh_fifo_pempty flag deassertion on all channels you must reset the FIFO by toggling the rx_enh_fifo_align_clr signal and repeating the process Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback 5 28 10GBASE R Mode Figure 5 34 RX FIFO as Interlaken Deskew
356. ing the link using the state machine based training algorithm The following figure illustrates the link training process where the link partners exchange equalization data Figure 2 52 TX Equalization for Link Partners Encode Encode lt lt Handshake 2 lt 4 Decode Handshake Ack Change Send Eq Adapt Calculate G BER Decode a gt Data Transmission Adaptation Feedback TX equalization includes the following steps which are identified in this figure 1 The receiving link partner calculates the BER 2 The receiving link partner transmits an update to the transmitting link partner TX equalization parameters to optimize the TX equalization settings 3 The transmitting partner updates its TX equalization settings 4 The transmitting partner acknowledges the change This process is performed first for the V op then the pre emphasis the first post tap and then pre emphasis pre tap The optional backplane daisy chain topology can replace the spoke or hub switch topology The following illustration highlights the steps required for TX Equalization for Daisy Chain Mode Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR ent ge 2013 12 02 10GBASE KR Functional Description 2 109 Figure 2 53 TX Equalization in Daisy Chain Mode
357. int Or you can use the protocol presets described in Transceiver Native PHY Presets You can then modify the settings to meet your specific requirements Click Finish to generate the Native PHY IP this is your RTL file Instantiate and configure your PLL Create a transceiver reset controller You can use your own reset controller or use the Altera Transceiver PHY Reset Controller IP Connect the Native PHY IP to the PLL IP and the reset controller Use the information in Native PHY IP Ports for PCI Express to connect the ports Figure 2 83 Connection Guidelines for a PIPE Design 8 ATX PLL IP fPLL IP pll_refclk dy ATX PLL gt Pu Arria 10 and Master Gen1 Gen2 Transceiver CGB Gen3 Native PHY y tx_bonding_clocks tx_bonding_clocks pll_pcie_clk pipe_hclk_in tx_serial_clk A AAAA a a 3 D g 3 5 x _ S s s 3 I l bd Jae po z S ARARIRE S 3 L1B3 2 3 alas _ DOS 35 3 02 3 g z g a2 a alel zla e 2 SaaS 352 z xlizzx zxz z vvv Reset Controller gt D gg 5o g g oja Il 5JL zjx Note 1 This is one possible combination to represent the PIPE Gen3 solution using the Native PHY Simulate your design to verify its functionality Related Information Arria 10 Standard PCS Architecture on page 5 31 PLLs on page 3 3 For information about PLL architecture and implement
358. interface Transmitter PMA Transmitter Gen3 PCS FPGA s Fabric S a Transmitter Standard PCS ep euas x J Zeu peia 1 p09u3 807 88 J z jeu akg e e Oald XL A Receiver PMA Receiver Gen3 PCS vep yul Idid di p1eH ssaJdx3 19d y J zjuoyJU S 018 y Ola yen aY Receiver Standard PCS bBo Lep euas x1 itm i aao Jazieuasaq JauBlly Plo Odls yN Y 4aposaq 401 88 Jez jeuaseq aug Ola XY ry le Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 182 Supported PIPE Features 2013 12 02 Supported PIPE Features The features supported for a PCIe configuration differ according to Gen1 Gen2 or Gen3 configurations Table 2 124 Supported Features for PCle Configurations Protocol Feature Gen1 Gen3 2 5 Gbps 8 Gbps x1 x2 x4 x8 link configurations Yes Yes Yes PCle compliant synchronization state machine Yes Yes Yes 300 ppm total 600 ppm clock rate compensation Yes Yes Yes Transmitter driver electrical idle Yes Yes Yes Receiver Detection Yes Yes Yes 8B 10B encoder decoder disparity control Yes Yes N A 128B 130B encoder decoder N A N A
359. ion For information on design simulation and verification e Simulating the Transceiver Native PHY IP Core on page 2 256 Arria 10 Transceiver Protocols and PHY IP Support Table 2 1 Arria 10 Transceiver Protocols and PHY IP Support Protocol Transceiver IP PCS Support Transceiver Protocol Preset Configuration Rule PCIe Gen3 x1 x2 x4 x8 Native PHY IP Standard and PIPE Gen3 PCle PIPE Gen3 x1 19 IEE a PCle PIPE Gen3 x8 PCIe Gen2 x1 x2 x4 x8 Native PHY IP Standard PIPE Gen2 PCIe PIPE Gen2 x1 19 GLEE PCIe PIPE Gen2 x8 PCIe Gen x1 x2 x4 x8 Native PHY IP Standard PIPE Genl User created PIPE 1000BASE X Gigabit Native PHY IP Standard GbE GIGE 1 25 Gbps Ethernet 1000BASE X Gigabit Native PHY IP Standard GbE 1588 GIGE 1 25 Gbps 1588 17 18 19 20 21 22 23 24 Ethernet with 1588 For more information on Transceiver Configuration Rules refer to Using the Arria 10 Transceiver Native PHY IP on page 2 12 For more information on Protocol Presets refer to Using the Arria 10 Transceiver Native PHY IP on page 2 12 PCI Express Hard IP is also available as a MegaCore function The 1G 10GbE and 10GBASE KR PHY IP includes the necessary Soft IP for link training auto speed negotiation and sequencer functions Needs a user created Soft IP for link training auto speed negotiation and sequencer functions PCS Direct support will be available in a future rele
360. ion and disabled in another mode of operation The following other examples also require channel and PLL block reconfiguration e Switching between the Standard and Enhanced PCS e Changing the transmit PLL frequency e Enabling and disabling blocks within a PCS block You can dynamically reconfigure blocks within the transceiver channel or PLL through the reconfiguration interface Reconfiguration of the channel and PLL blocks requires the following steps Generate required configuration files Determine address offsets and differences Perform read modify writes A U N Reset transceiver channels and PLLs as appropriate Step 1 Generate Required Configuration Files Dynamic reconfiguration requires two instances of the Altera Transceiver Native PHY IP or PLL one instance defines the base transceiver or PLL configuration and the second instance defines the modified configuration Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation CJ Send Feedback 2 z F s UG A10XCVR 6 6 Step 1 Generate Required Configuration Files 2013 12 02 Click Tools gt MegaWizard Plug In Manager to define base and modified instances of the Transceiver Native PHY or PLL IP according to the following Table 6 4 Transceiver Native PHY or PLL IP Parameters Base and Modified Instances Native PHY Required Parameter Settings Instance Base e Click Interfaces gt Transceiver PHY gt Arria 10 e lt Native PHY Base Instance N
361. ion is enabled and the error flag is set the encoding sync header for the current word is generated incorrectly If the correct sync header is 2 b01 control type 2 b00 is encoded If the correct sync header is 2 b10 data type 2 b11 is encoded Table 2 16 Scrambler and Descrambler Parameters Enable TX scrambler LOGBASE R Interlaken On Off Enables the scrambler function This option is available for the Interlaken and 10OGBASE R protocols TX scrambler seed 1OGBASE R Interlaken User specified 58 bit value You must provide a non all zero seed for the Interlaken protocol For a multi lane Interlaken Transceiver Native PHY IP the first lane scrambler has this seed and other lanes scrambler have this seed increased by 1 per lane The initial seed for 1OGBASE R is 0x03FFFFFFFFFFFFFF This parameter is required for the 10GBASE R and Interlaken protocols Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2013 12 02 2 28 Enhanced PCS Parameters Enable RX On Off Enables the descrambler function This option is available for the descrambler Interlaken and 1OGBASE R protocols 10GBASE R Interlaken Table 2 17 Interlaken Disparity Generator and Checker Parameters Enable Interlaken On Off When you turn this option on the Enhanced PCS enables the TX disparity disparity generator This option is available for the Interlak
362. ip signal of the RX block synchronizer or rx_bits1ip from the FPGA fabric the word boundary is shifted by 1 bit Each bit slip removes the earliest received bit from the received data Figure 5 31 RX Bitslip 5 24 Block Synchronizer rx_bitslip is toggled two times which shifts the rx_parallel_data boundary two bits rx_clkout tx_ready rx_ready tx_parallel_data hex 00000001 rx_bitslip rx_parallel_data hex 00000000 00100000 00200000 00400000 The receiver gearbox can invert the polarity of the incoming data This is useful if the receiver signals are reversed on the board or backplane layout Enable polarity inversion through the Native PHY IP MegaWizard Block Synchronizer The block synchronizer determines the block boundary of a 66 bit word in the case of the 1OGBASE R protocol or a 67 bit word in the case of the Interlaken protocol The incoming data stream is slipped one bit at a time until a valid synchronization header bits 65 and 66 is detected in the received data stream After the predefined number of synchronization headers as required by the protocol specification is detected the block synchronizer asserts rx_enh_b1k_1lock block lock status sign
363. is used in low speed applications such as GigE where the FPGA fabric and the PCS can operate at the same clock rate Byte Deserializer Deserialize x2 Mode The deserialize x2 mode is used in high speed applications such as the PCIe Gen1 or Gen2 protocol implementation where the FPGA fabric cannot operate as fast as the TX PCS In deserialize x2 mode the byte deserializer deserializes 8 bit 10 bit when the 8B 10B encoder is not enabled 16 bit and 20 bit when the 8B 10B encoder is not enabled input data into 16 bit 20 bit 32 bit and 40 bit data respectively As the parallel data width from the word aligner is doubled the clock rate is halved Byte Deserializer Deserialize x4 Mode The deserialize x4 mode is used in high speed applications where the FPGA fabric cannot operate as fast as the TX PCS Altera Corporation Arria 10 Transceiver PHY Architecture J Send Feedback UG A10XCVR ae 2013 12 02 Bonded Byte Deserializer 5 45 In deserialize x4 mode the byte deserializer deserializes 8 bit data into 32 bit data As the parallel data width from the word aligner is divided four times the clock rate is quadrupled Bonded Byte Deserializer The bonded byte deserializer is also available for channel bundled applications such as PIPE In this configuration the control signals of the byte deserializers of all the channels are bonded together A master channel controls all the other channels to prevent skew between the channels
364. isplays the effective N counter value Divide factor L Counter Read only Displays the effective L counter value Table 3 14 CMU PLL Dynamic Reconfiguration Enable reconfiguration On Off Enables the PLL reconfiguration interface Enables the simulation models and adds more ports for reconfiguration Configuration file prefix Enter the prefix name for the configuration files to be generated Generate SystemVerilog package On Off Generates a SystemVerilog package file containing all file relevant parameters used by the PLL Generate C header file On Off Generates a C header file containing all relevant parameters used by the PLL Generate MIF Memory Initialize On Off Generates a MIF file that contains the current File configuration Use this option for reconfiguration purposes in order to switch between different PLL configurations Table 3 15 CMU PLL Generation Options Generate parameter documenta On Off tion file Altera Corporation Generates a csv file which contains the descriptions of all CMU PLL parameters and values PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 CMU PLL IP 3 23 Table 3 16 CMU PLL IP Ports _powerdown input Asynchronous _ Resets the PLL when asserted high plil rercik input N A Reference clock input port 0 There are 5 reference clock input ports The number of reference clock ports available depends on the Number of PLL
365. itter PLL when more than one PLL is connected to a channel To change the data rate of the CDR follow the detailed steps for reconfiguring channel and PLL blocks After determining the logical PLL to switch to follow this procedure to switch to the selected transmitter PLL 1 Read from the selected logical PLL offset for example offset 0x117 or 0x118 and save the required 4 bit pattern For example switching to logical PLL1 requires saving bits 7 4 of offset 0x117 2 Encode the 4 bit value read in the previous step into an 8 bit value according to the following table Table 6 7 Logical PLL Encoding 4 bit Logical PLL Offset 8 bit Mapping to Offset 0x111 Bits 3 0 logical_PLL_offset_readdata 3 logical_PLL_offset_readdata 1 0 logical_PLL_offset_ readdata 3 logical_PLL_offset_readdata 3 0 Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation CJ Send Feedback UG A10XCVR 6 10 Switching Reference Clocks 2013 12 02 4 bit Logical PLL Offset 8 bit Mapping to Offset 0x111 Bits 7 4 logical_PLL_offset_readdata 7 logical_PLL_offset_readdata 5 4 logical_PLL_offset_ readdata 7 logical_PLL_offset_readdata 7 4 Note For example if reconfiguring to logical PLL1 then bits 7 4 is encoded to an 8 bit value bit 7 bit 5 4 bit 7 bit 7 4 3 Perform a read modify write to bits 7 0 of offset 0x111 using the encoded 8 bit value 4 Complete the required reset sequence Related Info
366. iver mode TX RX Duplex Number of data channels 1 Data rate 1 2288 Gbps 9 830 Gbps Enable reconfiguration between Standard and Enhanced PCSs off Enable simplified data interface On Table 2 136 TX PMA Parameters Parameter VEIG TX channel bonding mode Not bonded TX local clock division factor 1 Number of TX PLL clock inputs per channel 1 Initial TX PLL clock input selection 0 Enable tx_pma_clkout port off Enable tx_pma_div_clkout port off tx_pma_div_clkout division factor Disabled Enable tx_pma_elecidle port off Enable tx_pma_qpipullup port QPI Off Enable tx_pma_qpipulldn port QPI Off Enable tx_pma_txdetectrx port QPI Off Enable tx_pma_rxfound port QPI Off Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Table 2 137 RX PMA Parameters Native PHY IP Parameter Settings for CPRI 2 223 Parameter VEIG Number of CDR reference Clocks 1 Selected CDR reference clock 0 Selected CDR reference clock frequency Select legal range defined by the Quartus II software PPM detector threshold 1000 Decision feedback equalization mode Disabled Enable rx_pma_clkout port Off Enable rx_pma_div_clkout port Off rx_pma_div_clkout division factor Disabled Enable rx_pma_clkslip port Off Enable rx_pma_qpipulldn port QPI Off Enable rx_is_lockedtodata port Off Enable rx_is_lockedtoref por
367. k Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank 2 Nomenclature of right column bottom transceiver banks may begin with C D or E Legend PCle Gent Gen3 Hard IP blocks with CvP capabilities PCle Gen1 Gen3 Hard IP blocks without CvP capabilities Arria 10 GX device with 48 transceiver channels and four PCle Hard IP blocks Arria 10 GX device with 72 transceiver channels and four PCle Hard IP blocks Altera Corporation Transceiver Bank CH2 Arria 10 Transceiver PHY Overview J Send Feedback UG A10XCVR 2013 12 02 Arria 10 GX Device Transceiver Layout 1 5 Figure 1 4 Arria 10 GX Devices with 66 Transceiver Channels and Three PCle Hard IP Blocks Transceiver Bank CH2 CH1 CHO Transceiver Bank CH5 CH4 CH3 CH2 CH1 CHO
368. k The local CGB in each transceiver channel is bypassed To drive the channels in adjacent transceiver banks the x6 clock network drives the xN clock network Figure 3 21 PHY IP and PLL IP Connection for x6 xN Bonding Mode Transceiver PLL Native PHY Instance Instance 5 GHz 10 CH x6 xN Bonding 10 Gbps ATX PLL p cop _ 6 Legend ie TX channels placed in the same transceiver bank m TX channels placed in the adjacent transceiver bank The advantage of the xN bonding mode is that it uses the least number of resources One PLL and one master CGB can drive all the channels A disadvantage of the xN bonding mode is the data rate restriction Because a centrally generated set of high speed serial and low speed parallel clocks are distributed to all TX channels there is a limit on the maximum data rate obtained This maximum data rate depends on the clock network span Steps to implement a x6 xN bonded configuration 1 2 You can instantiate either the ATX PLL of the fPLL for x6 xN bonded configuration e Refer to Instantiating ATX PLL on page 3 5 or Instantiating fPLL IP on page 3 13 for detailed steps Configure the PLL IP using the MegaWizard Plug In Manager PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 46 x6 xN Bonding Mode 2013 12 02 e Because the CMU PLL cannot drive the Master CGB only the ATX PLL or fPLL can be us
369. k is not operational rx_enh_crc32_err lt n gt Output Asynchronous When asserted indicates a CRC error in the 120 current Metaframe Asserted at the end of current Metaframe This signal is pulse stretched for 2 or 3 cycles Table 2 37 10GBASE R BER Checker rx_enh_ Output Asynchronous Active high When asserted indicates a bit error highber lt n gt 1 0 rate that is greater than 10 4 For the 1OGBASE R protocol this BER rate occurs when there are at least 16 errors within 125 us rx_enh_highber_ _ Input Asynchronous When asserted clears the internal counter that clr cnt lt n gt 1 0 Generated on rx__ indicates the number of times the BER state clkout machine has entered the BER_BAD_SH state rx_enh_clr_ Input Asynchronous For 10GBASE R enables the optional rx_enh_ errblk_count lt n gt Generatedon rx_ clr_errblk_count input port When 1 0 10GBASE R clkout asserted the error block counter resets to 0 and FEC Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the RX_E state In modes where the FEC block is enabled the assertion of this signal resets the status counters within the RX FEC block Table 2 38 Block Synchronizer rx_enh_blk_lock lt n gt 1 0 Output Asynchronous Active high When asserted indicates that block synchronizer has achieved block delineation This signal is used for 10GBASE
370. k Switching 2013 12 02 Specify the logical reference clock and respective offset and bits of the replacement clock when performing a reference clock switch Follow this procedure to switch to the selected reference clock 1 Read from the logical reference clock offset for MUX A and save the required 5 bit pattern For example switching to logical re c1k3 requires use of bits 4 0 of offset Ox11A 2 Perform a read modify write to bits 4 0 of offset 0x114 using the 5 bit value obtained from the logical refclk offset 3 Read from the logical reference clock offset for MUX B and save the required 5 bit pattern For example switching to logical refc1k3 requires use of bits 4 0 of offset 0x120 4 Perform a read modify write to bits 4 0 of offset 0x11C using the 5 bit value obtained from the logical refclk offset 5 Complete the required reset sequence CDR and CMU Reference Clock Switching You can use the reconfiguration interface to specify which reference clock source drives the CDR and CMU PLL The CDR supports clocking by up to five different reference clock sources Before initiating a reference clock switch ensure that your Transceiver Native PHY or CMU PLL instance defines more than one reference clock source Specify the Number of CDR reference clocks under the RX PMA tab when parameterizing the Native PHY Before initiating a reference clock switch ensure that your CDR and CMU defines more than one reference clock source F
371. kout reconfig_clk reconfig_reset reconfig_write reset reconfig_read For reconfig_address Reconfiguration reconfig_writedata reconfig_readdata t_serial_clk reconfig_waitrequest 8 Simulate your design to verify its functionality Related Information e Arria 10 Standard PCS Architecture on page 5 31 For more information about Standard PCS architecture e Arria 10 PMA Architecture on page 5 1 For more information about PMA architecture e Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks e PLLs on page 3 3 PLL architecture and implementation details Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details e Standard PCS and PMA Ports on page 2 52 Port definitions for the Transceiver Native PHY Standard Datapath Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations Table 2 147 General and Datapath Options Parameters Device speed grade fastest ee e error Message level for rule violations e warning Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR P 2013 12 02 Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations 2 247 e Basic Custom Standard PCS Transceiver configuration rules e Basic Custom w Rate Match Standard PCS e TX RX Duplex Transcei
372. ks using the xN clock lines Each transmitter channel has a multiplexer to select its clock source from either the local CGB or the master CGB Figure 3 11 Clock Generation Block and Clock Network The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network or the master CGB via the x6 xN network For example as shown by the red highlighted path the ATX PLL drives the x1 network which in turn drives the master CGB The master CGB then drives the x6 clock network which routes the clocks to the local channels As shown by the blue highlighted path the ATX PLL can also drive the x1 clock network which can directly feed a channel s local CGB In this case the low speed parallel clock is generated by the local CGB fPLL 1 ATX PLL 1 fPLL 0 ATX PLL 0 Master CGB1 gt Master CGBO gt Chs5 CDR Ch4 Chi CDR Cho Transceiver Bank PLLs and Clock Networks CJ Send Feedback Altera Corporation UG A10XCVR 3 34 FPGA Fabric Transceiver Interface Clocking 2013 12 02 FPGA Fabric Transceiver Interface Clocking The FPGA fabric transceiver interface consists of clock signals from the FPGA fabric into the
373. l PCS because the transmitter channel is capable of operating at higher clock rates compared to the FPGA fabric The byte serializer allows the transmitter channel to operate at higher data rates while keeping the FPGA fabric interface clock rate below its maximum limit This is accomplished by decreasing the channel width two or four times FPGA fabric to PCS interface width and doubling quadrupling the clock rate The byte serializer is disabled or operates in Serialize x2 or Serialize x4 modes Figure 5 40 Byte Serializer Block Diagram dataout Byte to the 8B 10 Encoder lt q Serializer lt datain from the TX FIFO or the TX Bit Slip 12 14 tx_clkout Related Information e Implementing Protocols in Arria 10 Transceivers on page 2 1 e Resetting Transceiver Channels on page 4 1 Altera Corporation Arria 10 Transceiver PHY Architecture J Send Feedback UG A10XCVR fae 2013 12 02 Bonded Byte Serializer 5 33 Bonded Byte Serializer The bonded byte serializer is available in Arria 10 and is used in applications such as PIPE CPRI and custom applications where multiple channels are grouped together The bonded byte serializer is implemented by bonding all the control signals to prevent skew induction between channels during byte serialization In this configuration one of the channels acts as master and the remaining channels act as slaves Byte Serializer Disabled Mode In disabled
374. l data is slipped on the rising edge of tx_enh_bit slip before it is passed to the PMA The maximum number of the supported bitslips is PCS data width 1 and the slip direction is from MSB to LSB and from current to previous word Figure 5 29 TX Bitslip tx_enh_bitslip 2 and PCS width of gearbox is 67 Current Word Bitindex 66 65 64 2 1 o 66 65 You can use transmitter data polarity inversion to invert the polarity of every bit of the input data word to the serializer in the transmitter path The inversion has the same effect as swapping the positive and negative signals of the differential TX buffer This is useful if these signals are reversed on the board or backplane layout Enable polarity inversion through the Native PHY IP MegaWizard KR FEC Blocks The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10G KRFEC and 40G KRFEC of the IEEE 802 3 specification The KR FEC implements the Forward Error Correction FEC sublayer a sublayer between the PCS and PMA sublayers Most data transmission systems such as Ethernet have minimum requirements for the bit error rate BER However due to channel distortion or noise in the channel the required BER may not be achievable In these cases adding a forward error control correction can improve the BER performance of the system Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Receive
375. l 1 and channel 4 only can be used as a transmit PLL PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 4 ATX PLL 2013 12 02 Figure 3 2 ATX PLL Block Diagram p Lock Detector 2 LCVCO 1 crt LCVCO 2 4 ay LF gt gt L Counter gt LCVCO 3 Refclk Multiplexer Dedicated reference clock pin gt Up Down Reference clock network gt Receiver input pin p N Counter PFD i M Counter kq Output of another PLL gt t with PLL cascading Delta Sigma Modulator 1 Note 1 The Delta Sigma Modulator is enaged only when the ATX PLL is used in fractional mode Input Reference Clock This is the dedicated input reference clock source for the PLL The input reference clock can be sourced from a dedicated reference clock pin the reference clock network a receiver input pin or the output of another PLL with PLL cascading The input reference clock is a differential signal Altera recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance The input reference clock must be stable and free running at device power up for proper PLL operation Reference Clock Multiplexer Refclk Mux The refclk mux selects the reference clock to the PLL from the various reference clock sources available N Counter The N counter divides the ref
376. l medium The CTLE supports both DC and AC gain DC gain circuitry provides an equal amplification to the incoming signal across the frequency spectrum AC gain circuitry provides amplification to the high frequency spectrum gain of the incoming signal Figure 5 9 CTLE AC and DC Gain Conceptualization A Gain dB pc Gain Control A gt Frequency AC Gain A Control Gain A dB gt Frequency Note Final equalization curves will be available in the Arria 10 datasheet Arria 10 transceiver channels have dual mode CTLE high gain mode and high data rate mode In high gain mode CTLE provides up to 16 dB programmable AC gain for data rates up to 12 5 Gbps In high data rate mode CTLE provides up to 12 dB programmable AC gain for data rates up to 28 1 Gbps Altera Corporation Arria 10 Transceiver PHY Architecture C Send Feedback UG A10XCVR 2013 12 02 Variable Gain Amplifier VGA 5 7 CTLE in Arria 10 transceivers also provides different bandwidth settings for different data rates High gain mode has the following options e low up to 6 25 Gbps e high up to 12 5 Gbps High data rate mode provides gain for higher data rate systems up to 28 1 Gbps You can choose from a range of programmable peaking frequencies for this mode of the CTLE The CTLE operates in both fixed and adaptive equalization modes Adaptive equalization is controlled by the Adaptive Parametric Tuning Engine You can select the
377. lation Use the ip make simscript Utility This utility generates simulation command scripts for multiple IP cores or Qsys systems To use this command you must specify Simulation Package Descriptor spd files for each IP core or Qsys system This utility compiles IP simulation models into simulation libraries Complete the following steps to use this command in Qsys 1 On the Qsys Tools menu select Nios II Command Shell gcc4 A command shell appears 2 To get usage information for the ip make simscript utility type the following command ip make simscript help 3 Then type ip make simscript with the appropriate arguments 4 You can run the scripts to compile the required device libraries and system design files in the correct order Then elaborate or load the top level design for simulation Related Information e Simulating Altera Designs e Creating a System with Qsys Altera Corporation GJ Send Feedback PLLs and Clock Networks 2013 12 02 UG A10XCVR X lt Subscribe QC Send Feedback This chapter provides information about the Arria 10 transceiver clocking architecture This chapter describes the transceiver phase locked loops PLLs internal clocking architecture and the clocking options for the transceiver and the FPGA fabric interface Transceiver banks can have either three or six transceiver channels Transceiver banks with six transceiver channels have two advanced transmit ATX PLLs fractional PLLs f
378. lete the following steps to specify the directory path and testbench settings for your simulator 1 On the Tools menu click Options and then click EDA Tool Options 2 Browse to the directory for your simulator The following table lists the directories for supported third party simulators Implementing Protocols in Arria 10 Transceivers Altera Corporation os Send Feedback 2 260 Custom Simulation Flow UG A10XCVR 2013 12 02 Table 2 156 Simulator Path Mentor Graphics ModelSim lt drive gt lt simulator install path gt win32 Windows Mentor Graphics QuestaSim lt simulator install path gt bin Linux Synopsys VCS VCS MX lt simulator install path gt bin Linux Cadence Incisive Enterprise lt simulator install path gt tools bin Linux Aldec Active HDL lt drive gt lt simulator install path gt bin Windows Aldec Riviera Pro lt simulator install path gt bin Linux 3 On Assignments menu click Settings 4 In the Category list under EDA Tool Settings select Simulation 5 In the Tool name list select your simulator 6 To enable your simulator on the Tools menu click Options and then click License Setup Make necessary 7 8 changes for EDA tool licenses Compile your design and testbench files Load the design and run the simulation in the EDA tool To learn more about third party simulators click on the appropriate link below Related Information Mentor Graphics ModelSim and Ques
379. lf duplex mode enable for the link partner A value of 1 indicates support for half duplex This bit should always be 0 because half duplex mode is not supported 8 7 PS2 PS1 Specifies pause support for link partner The following encodings are defined for PS1 PS2 e 2 b00 Pause is not supported e 2 b0 1 Asymmetric pause toward link partner e 2 b10 Symmetric pause e 2 b11 Pause is supported on TX and RX 13 12 RF2 RF1 Remote fault condition for link partner The following encodings are defined for RF1 RF2 e 2 b00 No error link is valid reset condition e 2 b0 1 Offline e 2 b10 Failure condition e 2 b11 Auto negotiation error 14 ACK Acknowledge for link partner A value of 1 indicates that the device has received three consecutive matching ability values from its link partner 15 NP Next page In link partner register When set to 0 the link partner has a Next Page to send When set to 1 the link partner does not a Next Page Next Page is not supported in Auto Negotiation 0x496 0x4A2 LINK_ PARTNER_ AUTO_ NEGOTIATION_ ABLE Set set to 1 indicates that the link partner supports auto negotiation The default value is 0 PAGE_RECEIVE AN link timer 15 0 A value of 1 indicates that a new page has been received with new partner ability available in the register partner ability The default value is 0 when the system management agent performs
380. lip tx_parallel_data bc rx_parallel_data 00 97 cb e5 f2 79 bc Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Figure 2 108 RX Bit Slip in 10 bit Mode tx_parallel_data 10 h3bc RX Polarity Inversion rx_std_bitslipboundarysel 01111 rx_bitslip tx_parallel_data 3bc rx_parallel_data 000 ade oef Figure 2 109 RX Bit Slip in 16 bit Mode tx_parallel_data 16 hfcbc rx_std_bitslipboundarysel 00001 I 00010 rx_bitslip tx_parallel_data fcbc rx_parallel_data 979f ji cbcf Figure 2 110 RX Bit Slip in 20 bit Mode tx_parallel_data 20 h3FCBC rx_std_bitslipboundarysel 00001 Y 00010 rx_bitslip tx_parallel_data 3fcbc rx_parallel_data ebdel y f2f0f RX Polarity Inversion Receiver polarity inversion can be enabled in low latency basic and basic rate match modes whereas the word aligner is available in any mode To enable the RX polarity inversion feature select the Enable RX polarity inversion and Enable rx_polinv port options This mode adds rx_polinv If there is more than one channel in the design rx_polinv isa bus in which each bit corresponds to a channel As long as rx_polinv is asserted the RX data r
381. ll port Enable tx_enh_ On Off Enables the tx_enh_fifo_pfull port fifo_pfull port Enable tx_enh_ On Off Enables the tx_enh_fifo_empty port fifo_empty port Enable tx_enh_ On Off Enables the tx_enh_fifo_pempty port fifo_pempty port Enable tx_enh_ fifo_cnt port On Off Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Enables the tx_enh_fifo_cnt port Altera Corporation 2 24 Enhanced PCS Parameters Table 2 10 Enhanced RX FIFO Parameters UG A10XCVR 2013 12 02 RX FIFO Mode Phase Compensation Specifies one of the following modes for Enhanced PCS RX FIFO Register e Phase Compensation This mode compensates for the clock iatsaaken phase difference between the read rx_coreclkin or rx_ clkout and write clock rx_clkout 10GBASE R e Register The TX FIFO is bypassed rx_parallel_data Basic rx_control and rx_enh_data_validare registered at the FIFO output e Interlaken Select this mode for the Interlaken protocol To implement the deskew process you must implement a FSM that controls the FIFO operation based on FIFO flags In this mode the FIFO acts as an elastic buffer e 10GBASE R In this mode data passes through the FIFO after block lock is achieved Idles OS Ordered Sets are deleted and Idles are inserted to compensate for the clock difference between the RX PMA clock and the fabric clock of 100 ppm for a maximum packet length of 64000 bytes e Basic
382. ll1_powe rdown is de asserted but before tx_analogreset is deasserted Alternatively this port can be deasserted at the same time aspll_powerdown mcgb_aux_cl1k0 tx _looimelimng Clocks 530 input Output N A N A Used for PCle implementation to switch between fPLL ATX PLL during link speed negotiation Optional 6 bit bus which carries the low speed parallel clock outputs from the master CGB Used for channel bonding and represents the x6 xN clock network mcgb_serial_clk Output N A High speed serial clock output for x6 xN non bonded configura tions pcie_sw 1 0 input N A 2 bit PCle rate switch control input pcie_sw_done 1 0 output N A 2 bit PCle rate switch status output Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 fPLL fPLL 3 11 Related Information Avalon Interface Specifications The ports related to reconfiguration are compliant with the Avalon Specification Refer to the Avalon Specification for more details about these ports The fractional PLL fPLL is used for generating lower clock frequencies It can support both integer and fractional frequency synthesis The fractional PLL fPLL can be used as a transmit PLL for transceiver applications It can be cascaded to the ATX or to another fPLL or it can be used to drive the core clock network There are two fPLLs in each transceiver bank wit
383. llowing tables Table 3 13 CMU PLL Parameters and Settings Device speed grade fastest Specifies the desired device speed grade This information is used for PLL frequency validation Protocol mode Basic Governs the internal setting rules for the VCO This parameter is not a preset You must set all other parameters for your protocol Bandwidth Low Specifies the VCO bandwidth Medium Higher bandwidth reduces PLL lock time at the High expense of decreased jitter rejection Number of PLL reference clocks lto5 Specifies the number of input reference clocks for the CMU PLL Generally used for data rate reconfiguration PLLs and Clock Networks GJ Send Feedback Altera Corporation 3 22 CMU PLL IP UG A10XCVR 2013 12 02 Selected reference clock source 0 to 4 Specifies the initially selected reference clock input to the CMU PLL Message level for rule violations Error Specifies the messaging level to use for parameter rule violations Warning e Error Causes all rule violations to prevent IP generation e Warning Displays all rule violations as warnings and will allow IP generation in spite of violations PLL output frequency Specify the target output frequency for the PLL PLL reference clock frequency 50 MHz to 800 Selects the input reference clock frequency for the MHz PLL Multiply factor M Counter Read only Displays the effective M divider value Divide factor N Counter Read only D
384. lo rx_is_lockedtodata rx_cal_bus tx_cal_bus tx_serialclkO rx_cdr_refclk tx_clkout tx_parallel_data rx_clkout rx_parallel_data 8 Simulate your design to verify its functionality Related Information Arria 10 Standard PCS Architecture on page 5 31 For more information about Standard PCS architecture Arria 10 PMA Architecture on page 5 1 For more information about PMA architecture Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks PLLs on page 3 3 PLL architecture and implementation details Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details Standard PCS and PMA Ports on page 2 52 Port definitions for the Transceiver Native PHY Standard Datapath Implementing Protocols in Arria 10 Transceivers GJ Send Feedback tx_ready nm ready tx_serial_data rx_serial_data Altera Corporation 2 222 Native PHY IP Parameter Settings for CPRI Native PHY IP Parameter Settings for CPRI Table 2 135 General and Datapath Options UG A10XCVR 2013 12 02 The first two sections of the MegaWizard Plug In Manager for the Native PHY IP provide a list of general and datapath options to customize the transceiver Parameter VEIG Device speed grade fastest Message level for rule violations error message Transceiver configuration rules CPRI Auto CPRI Manual Transce
385. lock synchronizer On Off Table 2 146 Gearbox Parameters Enable TX data bitslip On Off Enable TX data polarity inversion On Off Enable RX data bitslip On Off Enable RX data polarity inversion On Off Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 232 Using the Basic Custom Basic Custom with Rate Match Configurations of Standard PCS 2013 12 02 Using the Basic Custom Basic Custom with Rate Match Configurations of Standard PCS Use one of the following transceiver configuration rules to implement protocols such as SONET SDH SDI HD SATA or your own custom protocol e Basic protocol e Basic protocol with low latency enabled e Basic with rate match protocol Figure 2 100 Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate Match Configurations The data rate is 1250 Mbps Transmitter PMA Transmitter Standard PCS FPGA PRBS Fabric 10 E 625 MHz 2 Generator tx_coreclkin tx_clkout 4 4 125 MHz 1 7 62 MHZ 1 16 Wep puas x J ZIeu S dis a XL Japoouz 07 88 Jaziyeuas akg Odld XL
386. ls The Simulation Library Compiler saves simulation files in the output directory you specify Note Because the ModelSim Altera software provides precompiled simulation libraries you do not have to compile simulation libraries if you are use the ModelSim Altera software Complete the following steps to compile the simulation model libraries using the Simulation Library Compiler 1 2 3 4 Implementing Protocols in Arria 10 Transceivers On the Tools menu click Launch Simulation Library Compiler Under EDA simulation tool for the Tool name select your simulation tool Under Executable location browse to the location of the simulation tool you specified You must specify this location before you can run the EDA Simulation Library Compiler Under Library families select one or more family names and move them to the Selected families list Altera Corporation GJ Send Feedback 2 262 How to Generate Scripts eho M 5 Under Library language select Verilog VHDL or both 6 In the Output directory field specify a location in which to store the compiled libraries 7 Click Start Compilation Complete the following steps to add the simulation files to your project 1 On the Assignments menu click Settings 2 In the Category list select Files 3 Click Browse to open the Select File dialog box and select one or more files in the Files list to add to your project 4 Click Open and then Add to add the selected file s
387. ltera Corporation CJ Send Feedback UG A10XCVR 3 52 Mix and Match Example 2013 12 02 Connection Guidelines for PLL and Clock Networks e For 12 5 Gbps Interlaken with a bonded group of 10 channels connect the tx_bonding_clocks to the transceiver PLL s tx_bonding_clocks output port Make this connection for all 10 bonded channels This connection uses a master CGB and the x6 xN clock line to reach all the channels in the bonded group e Connect the tx_serial_clk port of the first two instances of the 1OGBASE KR PHY IP to the tx_serial_clk port of PLL instance 1 ATX PLL at 5 1625 GHz This connection uses the x1 clock line within the transceiver bank e Connect the tx_serial_clk port of the remaining two instances of the 1OGBASE KR PHY IP to the tx_serial_clk port of the PLL instance 2 ATX PLL at 5 1625 GHz This connection uses the x1 clock line within the transceiver bank e Connect the three tx_serial_clk ports for the custom multi data rate PHY IP as follows m e Connect tx_serial_clk0 port to the tx_serial_clk port of PLL instance 2 ATX PLL at 5 1625 GHz This PLL instance is shared with the two 1OGBASE KR PHY IP channels and also uses the x1 clock line within the transceiver bank e Connect the tx_serial_clk1 port to the tx_serial_clk port of the PLL instance 3 ATX PLL at 4 9 GHz This connection uses the x1 clock line within the transceiver bank e Connect the tx_serial_clk2 port to the tx_seri
388. ludes support for non standard link configurations where the TX and RX interfaces connect to different link partners This mode overrides the TX adaptation algorithm Enable microprocessor interface On Off When you turn this option On the core includes a microprocessor interface which enables the microprocessor mode for link training Maximum bit error count 15 31 63 127 Specifies the maximum number of errors before the 255 511 1023 Link Training Error bit 0xD2 bit 4 is set indicating an unacceptable bit error rate You can use this parameter to tune PMA settings For example if you see no difference in error rates between two different sets of PMA settings you can increase the width of the bit error counter to determine if a larger counter enables you to distinguish between PMA settings Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR Link Training Parameters 2 115 name Tate tecipson Number of frames to send before sending actual data 127 255 Specifies the number of additional training frames the local link partner delivers to ensure that the link partner can correctly detect the local receiver state PMA Parameters VMAXRULE VMINRULE Specifies the maximum Vop The default value is 60 which represents 1200 mV The range is 0 1200 mV If the backplane is short or lightly loaded you can reduce the maximum value t
389. ly The channels may all be placed in one bank if not greater than six lanes or they may span several banks Related Information e Arria 10 Device Datasheet e Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks xN Clock Bonding Scenario The following figure shows a xN bonding example supporting 10 lanes Each lane is running at 12 5 Gbps The first six TX channels reside in one transceiver bank and the other four TX channels reside in the adjacent transceiver bank The ATX PLL provides the serial clock to the master CGB The CGB then provides parallel and serial clocks to all of the TX channels inside the same bank and other banks through the xN clock network Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 66 PLL Feedback Compensation Clock Bonding Scenario 2013 12 02 Because of xN clock network skew the maximum achievable data rate decreases when TX channels span several transceiver banks Figure 2 14 10X12 5 Gbps xN Bonding Native PHY Instance Transcewer Pll 10 Ch Bonded 12 5 Gbps Instance 6 25 GHz Transceiver Bank 1 ATX PLL P ped mg 6 Transceiver Bank 2 Related Information e x6 xN Bonding Mode on page 3 45 For detailed information on xN bonding limitations e Using PLLs and Clock Network
390. ly reconfigure are in this address space Refer to reconfiguration chapter for further information 0x000 0x3 FF 9 0 RW Access to HSSI registers Enhanced PCS Registers These registers provide Enhanced PCS status information Table 2 103 PCS Registers a Because the PHY implements a single channel this register must remain at the default value of 0 to specify logical channel 0 0x480 31 0 Indirect_addr 2 RW RCLR_ERRBLK_CNT Error Block Counter clear register When set to 1 clears the RCLR_ERRBLK_CNT register When set to 0 normal operation continues 0x481 3 RW RCLR_BER_COUNT BER Counter clear register When set to 1 clears the RCLR_ BER_COUNT register When set to 0 normal operation continues Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2013 12 02 A 2 142 PMA Registers HI_BER High BER status When set to 1 the PCS is reporting a high BER When set to 0 the PCS is not reporting a high BER 2 RO BLOCK_LOCK Block lock status When set to 1 the PCS is locked to received blocks When set to 0 the PCS is not locked to received blocks 0x482 3 RO TX_FULL When set to 1 the TX_FIFO is full RO RX_FULL When set to 1 the RX_FIFO is full RO RX_SYNC_HEAD_ERROR When set to 1 indicates an RX synchronization error RO RX_SCRAMBLER_ ERROR When set to 1 indicates an RX scrambler error
391. m CLkowt mii_tx_en Input Synchronousto When asserted indicates the start of a new frame k mii_tx_enshould remain asserted until the last adie nibble of data on the frame is present on mii_tx_ clkout dist mii tz err Input Synchronousto When asserted it indicates an error in the frame a mii_tx_en should also be asserted for PHY to ee transmit invalid data clkout CJ Send Feedback Implementing Protocols in Arria 10 Transceivers Altera Corporation 2 120 XGMII Mapping to Standard SDR XGMII Data UG A10XCVR 2013 12 02 mii_tx_clkena Output Clock signal MII TX clock enable This clock frequency has the following frequencies e 25 MHz For an effective rate of 100 Mbps e 2 5 MHz For an effective rate of 10 Mbps ila ie _ llkeiae__ half_rate Output Clock signal MII RX clock enable when the FPGA fabric runs at half the PCS frequency This clock frequency has the following frequencies e 12 5 MHz For an effective rate of 100 Mbps e 1 25 MHz For an effective rate of 10 Mbps mii_rx_d 3 0 Output Synchronous to rx_pma_ clkout RX Data received from link partner Synchronized to the rx_pma_clkout clock iL iL r en Output Synchronous to When asserted indicates that data onmii_rx_ d 3 0 is valid rx_pma_ clkout mii_rx_err Output Synchronous to When asserted it indicates an error in the frame rx_pma_ clkout mii_rx_clkena Output Clock sig
392. mitter PLLs You can use the reconfiguration interface to specify which PLL drives the transceiver channel The PLL switching method remains the same regardless of the number of transmitter PLLs involved Before initiating the PLL switch procedure ensure that your Transceiver Native PHY instance defines more than one transmitter PLL input Specify the Number of TX PLL clock inputs per channel parameter on the TX PMA tab during Transceiver Native PHY parameterization The following table shows mapping of the Native PHY serial clock inputs to their respective logical mapping The reconfiguration process requires this logical mapping The number of exposed tx_serial_clk varies according to the number of transmitter PLLs you specify The following table shows the logical mapping and the selection MUX offsets Use the Native PHY reconfiguration interface for this operation Table 6 6 Logical Mapping of Native PHY Serial Clock Inputs Transceiver Native PHY Logical PLL Offset 4 bit Logical PLL Offset Bits Port tx_serial 0 Represents logical PLLO 0x117 3 0 tx_serial_clk1 Represents logical PLL1 0x117 7 4 tx_serial_clk2 Represents logical PLL2 0x118 3 0 tx_serial_clk3 Represents logical PLL3 0x118 7 4 N A PLL selection MUX 0x111 7 0 When performing a PLL switch you must specify the replacement logical PLL offset and respective and bits The following procedure describes selection of a specific transm
393. ms For more information refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Std 802 3ap 2007 Altera Corporation UG A10XCVR 2 114 10GBASE KR Auto Negotiation Parameters 2013 12 02 10GBASE KR Auto Negotiation Parameters The 1OGBASE KR Auto Negotiation parameters allow you to enable or disable auto negotiation Table 2 90 Auto Negotiation Settings SS Enable Auto Negotiation On Off When you turn this option On Auto Negotiation as defined in Clause 73 of the IEEE Std 802 3ap 2007 is enabled Pause Ability Co On Off When you turn this option On the core supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802 3 2008 Pause Ability Cl On Off When you turn this option On the core supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802 3 2008 10GBASE KR Link Training Parameters The 1OGBASE KR variant provides parameters to customize the Link Training parameters Table 2 91 Link Training Parameters In the following table the exact correspondence between numerical values and voltages is pending characterization of the Native PHY A a Enable Link Training On Off When you turn this option On the core includes the link training module which configures the remote link partner TX PMD for the lowest Bit Error Rate BER LT is defined in Clause 72 of IEEE Std 802 3ap 2007 Enable daisy chain mode On Off When you turn this option On the core inc
394. mum channel span of xN clock network is two transceiver banks above and two transceiver banks below the bank that contains the driving PLL and the master CGB Thus a maximum of 30 channels can be used in a single bonded or non bonded xN group The maximum data rate supported by the xN clock network while driving channels in either the bonded or non bonded mode depends on the voltage used to drive the transceiver banks All transceiver banks in a bonded group must share the same voltage Refer to the table below for the maximum data rate supported Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 7 2013 12 02 GT Clock Lines 3 31 Table 3 17 xN Clock Network Data Rate Restrictions Transceiver Voltage Maximum Data Rate Supported by xN Clock Network E 0 9 V 10 3125 Gbps 1 0 V 15 Gbps 1 1 V 16 Gbps Related Information x6 xN Bonding Mode on page 3 45 GT Clock Lines GT clock lines are dedicated clock lines available only in Arria 10 GT devices Each ATX PLL has two dedicated GT clock lines which connect the PLL directly to the transceiver channels within a transceiver bank The top ATX PLL drives channels 3 and 4 and the bottom ATX PLL drives channels 0 and 1 These connections bypass the rest of the clock network for higher performance These channels can be used only for non bonded configurations Cd The maximum data rate supported numbers are pending characterization data PLLs and Clo
395. n The following table shows mapping of the fPLL reference clock inputs to their respective logical mapping The reconfiguration process requires this logical mapping The number of exposed pl11_refclk ports varies according to the number of reference clocks you specify The following table shows the logical mapping and the selection MUX offsets Use the PLL reconfiguration interface for this operation Table 6 9 Logical Mapping of fPLL Reference Clock Inputs Transceiver ATX PLL Port Description Logical Reference Clock Offset pll_refcl1ko Represents logical refc1k0 for MUX_0 0x117 4 0 pll refelki Represents logical refclk1 for MUX_0 0x118 4 0 pll_refclk2 Represents logical refc1k2 for MUX_0 0x119 4 0 pll_refclk3 Represents logical refc1k3 for MUX_0 0x11A 4 0 pll_refclk4 Represents logical refc1k4 for MUX_0 0x11B 4 0 N A fPLL Refclk selection MUX_0 0x114 4 0 pll_refcl1k0 Represents logical refc1k0 for MUX_1 0x11D 4 0 pll_refclkl Represents logical refclk1 for MUX_1 0x11E 4 0 pll_refclk2 Represents logical refclk2 for MUX_1 0x11F 4 0 pll_refclk3 Represents logical refc1k3 for MUX_1 0x120 4 0 pll_refclk4 Represents logical refc1k4 for MUX_1 0x121 4 0 N A fPLL Refclk selection MUX_1 0x11C 4 0 Reconfiguration Interface and Dynamic Reconfiguration Altera Corporation CJ Send Feedback UG A10XCVR 6 12 CDR and CMU Reference Cloc
396. n Off Generate C header file On Off Generate MIF Memory Intialization On Off File Table 2 65 Configuration Profiles Parameters Parameter Value Enable multiple reconfiguration profiles On Off Generate reduced reconfiguration files On Off Number of reconfiguration profiles 2 3 4 5 6 7 8 Selected reconfiguration profile Table 2 66 Generation Options Parameters Implementing Protocols in Arria 10 Transceivers Generate parameter documentation file On Off Ethernet Data Rate Transceiver Configuration Rule IP 1G e Gigabit Ethernet e Gigabit Ethernet 1588 Altera Corporation CJ Send Feedback 2 80 Gigabit Ethernet GbE and GbE with 1588 UG A10XCVR 2013 12 02 Data Rate Transceiver Configuration Rule IP 10G e lOGBASE R e lOGBASE R 1588 e lOGBASE R with KR FEC e l1OGBASE KR PHY IP 1G 10G 1G 10G Ethernet PHY IP Gigabit Ethernet GbE and GbE with 1588 IEEE 802 3 defines Gigabit Ethernet as an intermediate or transition layer that interfaces various physical media with the media access control MAC in a Gigabit Ethernet system Gigabit Ethernet PHY shields the MAC layer from the specific nature of the underlying medium and is divided into three sub layers shown in the following figure Figure 2 25 GbE PHY Connection to IEEE802 3 MAC and RS osli Reference Model Layers Application Presentation Session Transpo
397. n The first skip cluster has a K28 5 control pattern followed by three K28 0 skip patterns The second skip cluster has a K28 5 control pattern followed by one K28 0 skip pattern The rate match FIFO inserts only two K28 0 skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion One K28 0 skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 240 Rate Match FIFO Basic Double Width Mode 2013 12 02 Figure 2 116 Rate Match FIFO Becoming Full After Receiving D5 x parallel data X D1 y D2 Y D3 X D4 y D5 y D6 Y D7 Y D8 X rx parallel data Y D1 X D2 X D3 Y D4 y D6 y D7 X D8 Y x X xx X x X rx_std_rmfifo_full Figure 2 117 Rate Match FIFO Becoming Empty After Receiving D3 bx parallel data X D1 X D2 Y D3 X D4 Y D5 X D6 Y rx parallel data X D1 X D2 Y D3 Y Kao Y D4 y D5 Y rx_std_rmfifo_empty Rate Match FIFO Basic Double Width Mode 1 Select basic double width in the RX rate match FIFO mode list 2 Enter values for the following parameters RX rate match insert delete ve pattern 20 bits of data The first 10 bits correspond to the skip hex specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern The skip pat
398. n as directed by the PHY MAC layer to minimize power consumption The PIPE interface in Arria 10 transceivers provides an input port for each transceiver channel configured in a PIPE configuration Note When transitioning from the PO power state to lower power states POs P1 and P2 the PCIe specification requires the physical layer device to implement power saving measures Arria 10 transceivers do not implement these power saving measures except for putting the transmitter buffer in electrical idle in the lower power states 8B 10B Encoder Usage for Compliance Pattern Transmission Support The PCle transmitter transmits a compliance pattern when the Link Training and Status State Machine LTSSM enters the Polling Compliance substate The Polling Compliance substate is used to assess if the transmitter is electrically compliant with the PCIe voltage and timing specifications Receiver Electrical Idle Inference IEI The PCle protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition with analog circuitry Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 184 Receiver Status UG A10XCVR 2013 12 02 In all PIPE configurations x1 x2 x4 and x8 each receiver channel PCS has an optional Electrical Idle Inference module that implements the electrical idle inference conditions specified in the PCIe Base Specification 2 0 Alte
399. n only be driven by the ATX PLL or the fPLL The CMU PLLs cannot drive the master CGB Therefore the CMU PLLs cannot be used for bonding purposes PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 28 x6 Clock Lines 2013 12 02 Figure 3 7 x1 Clock Lines x1 Network Ch Sz y CDR Ch D y ATX PLL1 CDR Ch wo x CDR Ch N y CDR Ch p y ATX PLLO CDR Ch oO y CDR x6 Clock Lines The x6 clock lines route the clock within a transceiver bank The x6 clock lines are driven by the master CGB There are two x6 clock lines per transceiver bank one for each master CGB Any channel within a transceiver bank can be driven by the x6 clock lines For bonded configuration mode the low speed parallel clock output of the master CGB is used and the local CGB within each channel is bypassed For non bonded configurations the master CGB can also provide a high speed serial clock output to each channel In this case the local CGB within each channel is not bypassed The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiver banks Altera Corporation PLLs and Clock Networks I Send Feedback UG A10XCVR 2013
400. n transceivers This mode enables you to connect the transceiver to a third party MAC to create a complete PCIe solution This section will focus on the implementation and configuration details for Native PHY IP in PIPE Gen1 Gen2 Gen3 transceiver configuration rules The PIPE specification version 3 0 provides implementation details for a PCle compliant physical layer The Native PHY IP for PIPE Gen1 Gen2 and Gen3 supports x1 x2 x4 or x8 operation for a total aggregate bandwidth ranging from 2 to 64 Gbps In a x1 configuration the PCS and PMA blocks of each channel are clocked and reset independently The x2 x4 and x8 configurations support channel bonding for two lane four lane and eight lane links In these bonded channel configurations the PCS and PMA blocks of all bonded channels share common clock and reset signals Gen1 and Gen2 modes use 8B 10B encoding which has a 20 overhead to overall link bandwidth Gen3 modes use 128b 130b encoding which has an overhead of less than 2 Gen1 and Gen2 modes use the Standard PCS while Gen3 mode uses the Gen3 PCS for its operation Table 2 123 Transceiver Solutions Arria 10 Hard IP for PCI Native PHY IP for PCI Express PIPE Express Gen1 Gen2 and Gen3 data rates Yes Yes MAC data link and transaction layer Yes User implementation in FPGA core Transceiver interface Hard IP through PIPE 3 0 e PIPE 2 0 for Gen1 and Gen2 based interface e PIPE3 0 based for Gen3 with Gen1 Gen
401. n3 PCS Reconfiguration Registers m Transmit Serial Q Receive Serial E Specify IP parameters by clicking Tools gt MegaWizard Plug In Manager and selecting your IP core variation To quickly specify appropriate initial settings for your configuration select a Preset matching your configuration Select Transceiver configuration rules to report an error for any parameters incompatible with the specified PCS and PMA Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 14 Using the Arria 10 Transceiver Native PHY IP Figure 2 6 Transceiver Native PHY IP GUI UG A10XCVR 2013 12 02 ESSLLLILIETITETITELTTETTETTT TETTI Als reset Yor native F Crnerai Device speed grade fasest E i Massage level fer rule violations error proja Datapath Options ss ee nnn FO oge g Transcetver configuration rules Transceiver mode Number ef data channels Oma rate LOCBASE R TX RX Oupiex B 1 20312 93 mtps Enable recorfigurat on between Sandard and Enhanced PCS datapaths Enable simplified dita interface D 10cesse r 1588 D 10cesse r wy FEC LY CPRI 9 8Cops Auto Mode O CPRI 9 8Cops Manual Mode D GiCE 1 25Cops D cice 1 25cops 1588 O interen 10x12 53bps Dimeriaen 16 25Cops Dimeriaen 6 gt 10 3 ps LD Low Latency Enhanced PCS AARARAARARARARARAAARANARARARARAARAAARAAGARARARANAA L TX PMA RX PMA Enhanced PG Oynamic Recontiguratiin
402. nal MII RX clock enable This clock frequency has the following frequencies e 25 MHz For an effective rate of 100 Mbps e 2 5 MHz For an effective rate of 10 Mbps mii_rx_clkena__ Output Clock signal MII RX clock enable when the FPGA fabric runs at half_rate half the PCS frequency This clock frequency has the following frequencies e 12 5 MHz For an effective rate of 100 Mbps e 1 25 MHz For an effective rate of 10 Mbps mii_speed_ Output Asynchronous Specifies the SGMII 4 speed mode The following Sel i130 signal encodings are defined e 2b 00 10 Gbps e 2 b01 1 Gbps e 2 b10 100 Mbps e 2 b11 10 Mbps XGMII Mapping to Standard SDR XGMII Data The 72 bit TX XGMII data bus format is different than the standard SDR XGMII interface The following table shows the mapping of this non standard format to the standard SDR XGMII interface Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 XGMII Mapping to Standard SDR XGMII Data 2 121 Table 2 94 TX XGMII Mapping to Standard SDR XGMII Interface xgmii_tx_dce 7 0 xgmii_sdr_data 7 0 Lane 0 data xgmii_tx_dc 8 xgmii_sdr_ctrl1 0 Lane0 control xgmii_tx_dc 16 9 xgmii_sdr_ Lane 1 data data 15 8 zomi ex deliyi xgmii_sdr_ctrl 1 Lane 1 control xgmii_tx_dc 25 18 xgmii_sdr_ Lane 2 data data 23 16 zogmii tx del26 xgmii_sdr_ctrl 2 Lane2 c
403. nchronous to the mgmt __c1lk This signal is only exposed under the following conditions e Turn off Enable automatic speed detection e Turn on Enable internal PCS reconfiguration logic e Turn on Enable 1Gb Ethernet protocol start_pcs_ Input Synchronous to When asserted initiates reconfiguration of the PCS reconfig mgmt_clk Sampled with the mgmt __c1k This signal is only exposed under the following conditions e Turn off Enable automatic speed detection Turn on Enable internal PCS reconfiguration logic e Turn on Enable 1Gb Ethernet protocol Avalon MM Register Interface The Avalon MM slave interface signals provide access to all registers Table 2 100 Avalon MM Interface Signals mgmt_clk Input Clock The clock signal that controls the Avalon MM PHY management interface If you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must restrict the frequency range to 100 125 MHz to meet the specifi cation for the transceiver reconfiguration clock mgmt_clk_ Input Reset Resets the PHY management interface This signal is reset active high and level sensitive mgmt _ Input Synchronous to 11 bit Avalon MM address addr 10 0 mgmt _clk mgmt _ Input Synchronous to Input data writedata 31 0 mgmt_clk mgmt _ Output Synchronous to Output data readdata 31 0 mgmt _clk mgmt_write Input Synchronous to Write signal Active high mgmt _clk mgmt
404. ncoming data rate The PIPE interface clock rate will also be adjusted to match the data throughput Related Information Rate Switch on page 2 188 Clock Data Recovery Control The CDR control feature is used for the LOs fast exit when operating in PIPE Gen3 mode Upon detecting an Electrical Idle Ordered Set EIOS this feature takes manual control of the CDR by forcing it into a lock to reference mode When an exit from electrical idle is detected this feature moves the CDR into lock to data mode to achieve fast data lock Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback Reconfiguration Interface and Dynamic Reconfiguration 2013 12 02 UG A10XCVR X lt Subscribe QC Send Feedback This chapter explains the purpose and the use of the Arria 10 reconfiguration interface that is part of the Transceiver Native PHY IP core and the Transceiver PLLIP core You can use the reconfiguration interface to perform dynamic reconfiguration and to interface with blocks within the transceiver channel such as the DFE and EyeQ blocks Dynamic reconfiguration is the ability to dynamically modify transceiver channels and PLLs to meet changing requirements during device operation Arria 10 transceiver channels and PLLs are fully customizable allowing a system to adapt to its operating environment You can customize channels and PLLs by dynamically triggering reconfiguration during device operation or following power up Each tran
405. nd before placing orders for products or services 101 Innovation Drive San Jose CA 95134 ISO 9001 2008 Registered JA DTE RYAN UG A10XCVR 4 2 When Is Reset Required 2013 12 02 When Is Reset Required You can reset the transmitter TX and receiver RX data paths independently or together The recommended reset sequence requires reset and initialization of the PLL driving the TX or RX channels as well as the TX and RX datapaths A reset may be required after any of the following events Table 4 1 Reset Conditions Device power up and configuration Requires reset to the transceiver PHY and the associated PLLs to a known initialize state PLL reconfiguration Requires reset to ensure that the PLL acquires lock at optimal operating conditions and also to reset the PHY PLL reference clock frequency Requires reset to the PLL to ensure PLL lock You must also reset the change PHY PLL recalibration Requires reset to the PLL to ensure PLL lock You must also reset the PHY PLL lock loss or recovery Requires reset after a PLL acquired lock from a momentary loss of lock You must also reset the PHY Channel dynamic reconfiguration Requires reset to the PLL and the PHY to initialize blocks for the new configuration Optical module connection Requires reset of RX to ensure lock of incoming data RX CDR lock mode change Requires reset of the RX channel any time the RX clock and data recovery CDR block
406. ndle several GT transceiver channels with one Native PHY IP instantiation but you will need to instantiate a separate ATX PLL IP for every ATX PLL used PLL and GT Transceiver Channel Clock Lines The ATX PLL is used to provide the clock source for the GT transceiver channels Each ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT transceiver channels within a transceiver bank The top ATX PLL drives channels 3 and 4 and the bottom ATX PLL drives channels 0 and 1 These connections bypass the rest of the clock network for higher performance Figure 2 131 GT Channel Configuration Ch o CGB y CDR Ch P E CDR ATX PLL1 Ch w vy Q Q w CDR N Ch CGB y CDR Ch e gt CGB x CDR Ch oO CGB y CDR Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Reset Controller 2 253 When both the channels 0 and 1 are configured as GT channels they are driven by the same ATX PLL and have to be configured to run at the same data rates This is also true for channels 3 and 4 when they are configured as GT channels Skew is expected between GT channels and the exact values are pending
407. ned in the Framing Layer Diagnostic Word bits 33 32 This message is inserted into the next Diagnostic Word generated by the Frame Generator Block This bus must be held constant for 5 clock cycles before and after the tx_enh_frame pulse The following encodings are defined e Bit 1 When 1 bl indicates the lane is operational When 1 b0 indicates the lane is not operational e Bit 0 When 1 bl indicates the link is operational When 1 b0 indicates the link is not operational ix emna Eeeme lt in il 0 Output Asynchronous When asserted indicates the beginning of a new received Metaframe rx_enh_frame_lock lt n gt 1 0 Output Asynchronous When asserted indicates the Frame Synchro nizer state machine has achieved Metaframe delineation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 50 Enhanced PCS and PMA Ports 2013 12 02 rx_enh_frame_diag_ Output Asynchronous Drives the lane status message contained in the stacus 2 lt ms 130 Framing Layer Diagnostic Word bits 33 32 This signal is latched when a valid Diagnostic Word is received in the end of the Metaframe while the frame is locked The following encodings are defined e Bit 1 When 1b 1 indicates the lane is operational When 0b 0 indicates the lane is not operational e Bit 0 When 1b l indicates the link is operational When 0b 0 indicates the lin
408. negotiation and sequencer functions PCS Direct support will be available in a future release of the Quartus II software A Soft PCS bonding IP design example will be available in a future release of the Quartus II software Altera Corporation 2 10 Arria 10 Transceiver Protocols and PHY IP Support Protocol Transceiver IP PCS Support Transceiver Configuration Rule UG A10XCVR 2013 12 02 18 Protocol Prese SONET SDH STS 192 STM Native PHY IP Enhanced Basic Enhanced User created 64 10G via SFP SFF PCS 8431 CEI 11G SONET SDH STS 192 STM Native PHY IP Enhanced SFI S User created 64 10G via OIF SFI 5 1s SxI 5 SFI 4 2 SONET STS 96 5G via OIF Native PHY IP Enhanced SFI S User created SFI 5 1s SONET SDH STS 48 STM Native PHY IP Standard Basic Custom User created 16 2 5G via SFP TFI 5 1 Standard PCS SONET SDH STS 12 STM Native PHY IP Standard Basic Custom User created 4 0 622G via SFP TFI 5 1 Standard PCS Intel QPI 1 1 2 0 Native PHY IP PCS Direct Not Available User created 10G SDI Native PHY IP Enhanced 10G SDI User created SD SDI HD SDI 3G SDI Native PHY IP Standard Basic Custom User created Standard PCS Vxl Native PHY IP Standard Basic Custom User created Standard PCS DisplayPort Native PHY IP Standard Basic Custom User created Standard PCS 1 25G 2 5G 10G GPON Native PHY IP Enhanced Basic Enhanced User created EPON PCS 2 5G 1 25G G
409. network is not compensated Single Channel x1 Non Bonded Configuration In x1 non bonded configuration the PLL source is local to the transceiver bank and the x1 clock network is used to distribute the clock from the PLL to the transmitter channel For a single channel design a PLL is used to provide the clock to a transceiver channel Figure 3 17 PHY IP and PLL IP Connection for Single Channel x1 Non Bonded Configuration Example Transceiver PLL Native PHY Instance Instance 5 GHz 1 CH Non Bonded 10 Gbps To implement this configuration instantiate a PLL IP and a PHY IP and connect them together as shown in the above figure Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Multi Channel x1 Non Bonded Configuration 3 41 Steps to implement a Single Channel x1 Non Bonded Configuration 1 Choose the PLL IP ATX PLL fPLL or CMU PLL you want to instantiate in your design and instantiate the PLL IP e Refer to Instantiating ATX PLL on page 3 5 or Instantiating CMU PLL IP on page 3 21 or Instantiating PLL IP on page 3 13 for detailed steps Configure the PLL IP using the MegaWizard Plug In Manager e For ATX PLL IP set the PLL feedback type to internal and do not include the Master CGB e For fPLL IP set the PLL feedback operation mode to direct e For CMU PLL IP specify the reference clock and the data rate No special configuration rule is required
410. nfiguration rules specifies Interlaken e Enhanced PCS Transceiver configuration rules specifies Basic and RX FIFO mode is Phase compensation e Enhanced PCS Transceiver configuration rules specifies Basic and RX FIFO mode is Register rx_enh_fifo_full lt n gt Output Asynchronous Active high When asserted indicates that the 1 0 RX FIFO is full rx_enh_fifo_pfull lt n gt Output Asynchronous Active high When asserted indicates that the 10 RX FIFO has reached its specified partially full threshold rx_enh_fifo_empty lt n gt Output Synchronous Active high When asserted indicates that the 1 0 to rx_ RX FIFO is empty coreclkin rx_enh_fifo_pempty lt n gt Output Synchronous Active high When asserted indicates that the 130 to rx_ RX FIFO has reached its specified partially coreclkin empty threshold rx_enh_fifo_del lt n gt Output Asynchronous When asserted indicates that a word has been 120 deleted from the RX FIFO This signal is used for the 1OGBASE R protocol rx_enh_fifo_insert lt n gt Output Synchronous When asserted indicates that a word has been 120 to rx_ inserted into the RX FIFO This signal is used coreclkin for the 10GBASE R protocol rx_enh_fifo_cnt lt n gt 5 Output rx_ Indicates the current level of the RX FIFO LQ coreclkin Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 E
411. ng The input reference clock is a differential signal Altera recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance The input reference clock must be stable and free running at device power up for proper PLL operation Reference Clock Multiplexer Refclk Mux The refclk mux selects the reference clock to the PLL from the various reference clock sources available N Counter PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 12 fPLL 2013 12 02 The N counter divides the reference clock refclk mux s output The N counter division helps lower the loop bandwidth or reduce the frequency within the PFD operating range The N counter supports division factors from 1 to 32 Phase Frequency Detector PFD The reference clock refclk signal at the output of the N counter block and the feedback clock fbc1k signal at the output of the M counter block is supplied as an input to the PFD The output of the PFD is proportional to the phase difference between the two inputs It is used to align the reference clock refclk to the feedback clock flbc1k The PFD generates an Up signal when the reference clock s falling edge occurs before the feedback clock s falling edge Conversely the PFD generates a Down signal when the feedback clock s falling edge occurs before the reference clock s falling edge Charge Pump and Loop Filter CP LF The PFD out
412. ng to Standard SDR XGMII Data UG A10XCVR 2013 12 02 zogmii tx del26 xgmii_sdr_ctrl 2 Lane2 control xgmii_tx_dc 34 27 xgmii_sdr_ Lane 3 data data 31 24 zomi tx de 35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_tx_dc 43 36 xgmii_sdr_ Lane 4 data data 39 32 xgmii_tx_dc 44 xgmii_sdr_ctrl 4 Lane4 control xgmii_tx_dc 52 45 xgmii_sdr_ Lane 5 data data 47 40 MoiMaLa_ tx _Cle 53 xgmii_sdr_ctrl1 5 Lane5control xgmii_tx_dce 61 54 xgmii_sdr_ Lane 6 data data 55 48 KGL cx delG2 xgmii_sdr_ctrl 6 Lane 6 control xgmii_tx_dc 70 63 xgmii_sdr_ Lane 7 data data 63 56 zgmii tx cel7Li xgmii_sdr_ctrl 7 Lane7 control The 72 bit RX XGMII data bus format is different from the standard SDR XGMII interface The following table shows the mapping of this non standard format to the standard SDR XGMII interface Table 2 115 RX XGMII Mapping to Standard SDR XGMII Interface xgmii_rx_dc 7 0 xgmii_sdr_data 7 0 Lane 0 data xgmii_rx_dc 8 xgmii_sdr_ctrl1 0 Lane 0 control xgmii_rx_dc 16 9 xgmii_sdr_ Lane 1 data data 15 8 RGM rz _cle 17 xgmii_sdr_ctrl 1 Lane1 control xgmii_rx_dc 25 18 xgmii_sdr_ Lane 2 data data 23 16 xgmii_rx_dc 26 xgmii_sdr_ctrl 2 Lane2 control xgmii_rx_dc 34 27 xgmii_sdr_ Lane 3 data data 31 24 zomi rx _Cle 35 xgmii_sdr_ctr1 3 Lane3 control xgmii_rx_dc 43 36 xgmii_sdr_ Lane 4 data data 39 32 xgmii_rx_dc 44 x
413. nge the default value which is 0x00000000 PHY Core version 16 bits 16 bit value This is an optional 16 bit value identifies the PHY core version Speed Detection Parameters By selecting the Enable automatic speed detection option in the MegaWizard Plug In Manager the PHY IP includes the sequencer module which implements the Parallel Detect function as described in the Ethernet specification Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G 10GbE but have disabled Auto Negotiation If you turn on the Enable automatic speed detection parameter the PHY includes the sequencer block During Auto Negotiation if AN cannot detect Differential Manchester Encoding DME pages from link partner the Sequencer reconfigures to 1GE and 10GE modes Speed Parallel detection until it detects a valid 1G or 1OGbE pattern Table 2 111 Speed Detection a T Deeton Enable automatic speed detection On Off When you turn this option On the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able detect AN data Avalon MM clock frequency MOOS PORMHZ Specifies the clock frequency for phy_mgmt_c1k Link fail inhibit time for 10Gb Ethernet 504 ms Specifies the time before Link_status is set to FAIL or OK A link fails if the Link_fail_ inhibit_time has expired before link_ status
414. nhanced PCS and PMA Ports 2 49 rx enna Cito align Output Synchronous When asserted indicates that the word valj lt n gt 1 0 torx_ alignment pattern has been found This signal clkoutkin is only valid for the Interlaken protocol rx_enh_fifo_align_ Input rx_ When asserted the FIFO resets and begins clr lt n gt 1 0 clkoutkin searching for a new alignment pattern This signal is only valid for the Interlaken protocol Assert this signal for at least 4 cycles Table 2 36 Interlaken Frame Generator Synchronizer and CRC32 tx_enh_frame lt n gt 1 0 Output Asynchronous Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new Metaframe ix _ Sioa iEvenne_lowliestt__ n lt n gt 1 0 Input tx_clkout If Enable frame burst is enabled this port controls frame generator data reads from the TX FIFO to the frame generator It is latched once at the beginning of each Metaframe If the value of tx_enh_frame_burst_enis 0 the frame generator does not read data from the TX FIFO for current Metaframe Instead the frame generator inserts SKIP words as the payload of Metaframe When tx_enh_ frame_burst_en is 1 the frame generator reads data from the TX FIFO for the current Metaframe This port must be held constant for 5 clock cycles before and after the tx_ enh_frame pulse tx_enh_frame_diag_ status lt n gt 2 1 0 Input tx_clkout Drives the lane status message contai
415. nnel bonding master Auto 0 1 Actual PCS TX channel bonding master 0 1 TX local clock division factor 1 2 4 8 Number of TX PLL clock inputs per 1 2 3 4 channel Initial TX PLL clock input selection 0 Table 2 143 RX PMA Parameters Number of CDR reference clocks 1to5 Selected CDR reference clock 0to4 Selected CDR reference clock frequency For Basic Enhanced PCS Depends on the data rate parameter For Basic with KR FEC 50 to 800 PPM detector threshold 62 5 100 125 200 250 300 500 1000 Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for Basic Enhanced PCS and Basic with KR FEC 2 231 Decision feedback equalization mode Disabled Fixed tap Floating tap Table 2 144 Enhanced PCS Parameters Enhanced PCS PMA interface width 32 40 64 Note Basic with KR FEC allows 64 only FPGA fabric Enhanced PCS interface 32 40 64 66 wade Note Basic with KR FEC allows 66 only Enable RX TX FIFO double width mode On Off TX FIFO mode Phase Compensation Register Basic TX FIFO partially full threshold TX FIFO partially empty threshold 10 11 12 13 14 15 1 2 3 4 5 RX FIFO mode Phase Compensation Register Basic RX FIFO partially full threshold 0 to 31 RX FIFO partially empty threshold 0 to 31 Table 2 145 Block Sync Parameters Enable RX b
416. nous flag rx_control 8 appears on the next block of 8 byte data There is also an asynchronous status signal rx_enh_fifo_del which does not go through the FIFO Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Idle Insertion 5 29 Figure 5 35 IDLE Word Deletion This figure shows the deletion of IDLE words from the receiver data stream Before Deletion pT rx_parallel_data lt 00000000000004ADh 00000000000004AEh 0707070707FD0000h 000000FB07070707h After Deletion i rx_parallel_data lt 00000000000004ADh lt 00000000000004AEh 0707070707FD0000h AAAAAAAAQOO000FBh Idle Deleted rd Figure 5 36 OS Word Deletion This figure shows the deletion of Ordered set words in the receiver data stream Before Deletion paaa a enh etionetanitati r rx parallel data lt FD000000000004AEh lt DDDDDDICDDDDDDICh lt 00000000000000F8h AAAAAAAAAAAAAAAAN After Deletion i i rx parallel data lt FD000000000004AEh X 000000FBDDDDDD9Ch N AAAAAAAA00000000h 00000000AAAAAAAAh OS Deleted Idle Insertion Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is deasserted Idles can be inserted following Idles or OS Idles are inserted in groups of 8 bytes Data shifting is not necessary There is a synchronous status rx_enh_fifo_insert signal that is attached to the 8 byte Idles being inserted Table 5 5 Cases Where Two Idle Words are Inser
417. nput ports Each port corresponds to the input of the local CGB of the transceiver channel e As shown in the figure above connect the first 6 tx_serial_clk input to the first transceiver PLL instance e Connect the remaining 4tx_serial_clk input to the second transceiver PLL instance Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Multi Channel xN Non Bonded Configuration 3 43 Multi Channel xN Non Bonded Configuration Using the xN non bonded configuration reduces the number of PLL resources and the reference clock sources used Figure 3 19 PHY IP and PLL IP Connection for Multi Channel xN Non Bonded Configuration In this example the same PLL is used to drive 10 channels across two transceiver banks Transceiver PLL Native PHY Instance Instance 5 GHz 10 CH Non Bonded 10 Gbps ATX PLL cop XN e Legend E TX channels placed in the same transceiver bank B TX channels placed in the adjacent transceiver bank Steps to implement a multi channel xN non bonded configuration 1 You can use either the ATX PLL or fPLL for multi channel xN non bonded configuration e Refer to Instantiating ATX PLL on page 3 5 or Instantiating fPLL IP on page 3 13 for detailed steps 2 Configure the PLL IP using the MegaWizard Plug In Manager e Because the CMU PLL cannot drive the master CGB only the ATX PLL or fPLL can be used for this e
418. nstraints To pass timing analysis you must decouple the clocks in different time domains The necessary Synopsys Design Constraints File sdc timing constraints for the are included in the top level wrapper file 1G 10 Gbps Ethernet PHY IP Core Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates The 1G 10Gbps Ethernet PHY IP core targets 1OMB 100MB 1G 10GbE data rates with one core This Ethernet PHY interfaces to 1G 10GbE dual speed SFP pluggable modules 10MB 10GbE 10GBASE T and 10MB 100MB 1000MB 1000BASE T copper external PHY devices to drive CAT 6 7 shielded twisted pair cables and chip to chip interfaces The 1G 10 Gbps Ethernet PHY MegaCore 1G 10GDbE Function allows you to support the following features of Ethernet standards e 1 GbE protocol as defined in Clause 36 of the IEEE 802 3 2008 Standard e GMII to connect PHY with media access control MAC as defined in Clause 35 of the IEEE 802 3 2008 Standard e Gigabit Ethernet Auto negotiation as defined inClause 37 of the IEEE 802 3 2008 Standard e 10GBASE R Ethernet protocol as defined inClause 49 of the IEEE 802 3 2008 Standard e Single data rate 64 data bits and 8 control bits XGMII to provide simple and inexpensive interconnection between the MAC and the PHY as defined in Clause 46 of the IEEE 802 3 2008 Standard e SGMII 10MB 100MB 1000MB serial interface e Forward Error correction FEC as defined in Cla
419. nt q Descrambler Test Pattern a Detect 5 y L a Pseudo Random Verifier Note You cannot enable the PRP and PRBS verifiers at the same time Enable the PRP verifier through the Transceiver and PLL Address Map The PRP pattern is automatically selected to match the PRP generator pattern that you selected 10GBASE R Bit Error Rate BER Checker The 1OGBASE R BER checker block is designed in accordance with the 1OGBASE R protocol specification as described in IEEE 802 3 2008 clause 49 After block lock synchronization is achieved the BER checker starts to count the number of invalid synchronization headers within a 125 s period If more than 16 invalid synchronization headers are observed in a 125 s period the BER checker provides the status signal rx_enh_highber to the FPGA fabric indicating a high bit error rate condition When the optional control input rx_enh_highber_clr_cnt is asserted the internal counter for the number of times the BER state machine has entered the BER_BAD_SH state is cleared When the optional control input rx_enh_clr_errb1lk_count is asserted the internal counter for the number of times the RX state machine has entered the RX_E state for the 1OGBASE R protocol is cleared In modes where the FEC block in enabled the assertion of this signal resets the status counters within the RX FEC block Note The 1OGBASE R BER checker is available to implement the 1OGBASE R protocol Interlaken CRC
420. nt update register bits 1 154 12 in Clause 45 2 1 80 3 and Clause 72 6 10 2 3 2 of IEEE 802 3ap 2007 0x4D4 RO or RW LD Preset Coefficients When set to 1 requests the link partner coefficients be set to a state where equalization is turned off When set to 0 the link operates normally For more information refer to bit 10G BASE KR LD coefficient update register bit 1 154 13 in Clause 45 2 1 80 3 and Clause 72 6 10 2 3 2 of IEEE 802 3ap 2007 RO LD coefficient status 5 0 Status report register for the contents of the second 16 bit word of the training frame most recently sent from the local device control channel The following fields are defined e 5 4 Coefficient post tap e 2 b11 Maximum e 2 b01 Minimum e 2 b10 Updated e 2 b00 Not updated e 3 2 Coefficient 0 same encoding as 5 4 e 1 0 Coefficient pre tap same encoding as 5 4 For more information refer to bit 10G BASE KR LD status report register bit 1 155 5 0 in Clause 45 2 1 81 of IEEE 802 3ap 2007 14 RO Link Training ready LD Receiver ready Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 138 10GBASE KR PHY Register Definitions Word R W Description Addr UG A10XCVR 2013 12 02 When set to 1 the local device receiver has determined that training is complete and is prepared to receive data When set to 0 the local device receiver is reque
421. o 1 indicates a frame lock was lost during Link Frame lock Error Training If the tap settings specified by the fields of 0x4D5 are the same as the initial parameter value the frame lock error was unrecoverable Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 136 10GBASE KR PHY Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr RW ber_time_ frames Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings Used only when ber_time_k_frames is 0 The following values are defined e A value of 2 is about 10 bytes e A value of 20 is about 10 bytes e A value of 200 is about 10 bytes The default value for simulation is 2 b11 The default value for hardware is 0 19 10 0x4D3 RW ber_time_k_ frames Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings Set ber_time_m_frames 0 for time bits to match the following values e A value of 3 is about 107 bits about 1 3 ms e A value of 25 is about 10 bits about 11ms e A value of 250 is about 10 bits about 11 Oms The default value for simulation is 0 The default value for hardware is 0x415 29 20 RW ber_time_m_ frames Specifies the number of millions of training frames to examine for bit errors on the link for
422. o limit the search space during link training Specifies the minimum Vop The default value is 9 which represents 165 mV If the backplane is long or heavily loaded you can increase the minimum value to limit the search space during link training VODMINRULE Specifies the minimum Vop for the first tap The default value is 24 which corresponds to 480 mV This value needs to be equal or greater than the VMINRULE value and less than the VMAXRULE VPOSTRULE Specifies the maximum value that the internal algorithm for pre emphasis will ever test in determining the optimum post tap setting The default value is 31 VPRERULE Specifies the maximum value that the internal algorithm for pre emphasis will ever test in determining the optimum pre tap setting The default value is 15 PREMAINVAL Specifies the Preset Vop Value Set by the Preset command as defined in Clause 72 6 10 2 3 1 of the link training protocol This is the value from which the algorithm starts The default value is 60 PREPOSTVAL Specifies the preset Pre tap Value The default value is 0 PREPREVAL Specifies the preset Post tap value The default value is 0 INITMAINVAL Specifies the Initial VOD Value Set by the Initialize command in Clause 72 6 10 2 3 2 of the link training protocol The default value is 52 INITPOSTVAL Specifies the initial first Post tap value The default value is 30 Implementing Proto
423. o recovered clock cycles to indicate that the rate match FIFO is empty The following figure shows the rate match FIFO empty condition when the read pointer is faster than the write pointer Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback UG A10XCVR 2 86 How to Implement GbE GbE 1588 in Arria 10 Transceivers 2013 12 02 Figure 2 34 Rate Match FIFO Empty Condition Ooo COO COO GOO OMe me HOO OOOO x_std_rmfifo_empty a i 24 N Sz The rx_std_rmfifo_empty status flag indicates that the FIFO is empty at this time In the case of rate match FIFO full and empty conditions you must assert the rx_digitalreset signal to reset the receiver PCS blocks Related Information Rate Match FIFO on page 5 41 How to Implement GbE GbE 1588 in Arria 10 Transceivers Before you begin You should be familiar with the Standard PCS and PMA architecture PLL architecture and the reset controller before implementing the GbE protocol 1 Open the MegaWizard Plug In Manager and select the PHY IP Refer to Select and Instantiate PHY IP on page 2 2 2 Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options depending on which protocol you are implementing 3 Use the parameter values in the tables in Native PHY IP Parameter Settings for GbE and GbE with 1588 on page 2 88 as a starting point Or you can use the protocol p
424. o the reference clock Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Arria 10 GMII PCS Registers 2 143 E tx_invpolarity Whenset to 1 the TX interface inverts the polarity of the TX data Inverted TX data is input to the 8B 10B encoder RW rx_invpolarity When set to 1 the RX channels inverts the polarity of the received data Inverted RX data is input to the 8B 10B decoder Ox4A8 RW rx_bitreversal_ When set to 1 enables bit reversal on the RX enable interface The RX data is input to the word aligner RW rx_bytereversal_ When set enables byte reversal on the RX interface enable The RX data is input to the byte deserializer RW force_ When set to 1 forces the TX outputs to electrical electrical_idle idle R rx_synestatus When set to 1 indicates that the word aligner is synchronized to incoming data R rx_patterndetect When set to 1 indicates the 1G word aligner has detected a comma R rx_rlv When set to 1 indicates a run length violation R rx_rmfifodatain When set to 1 indicates the rate match FIFO 0x4A9 serted inserted code group R CX When set to 1 indicates that rate match FIFO rmfifodatadeleted deleted code group R lex disperr When set to 1 indicates an RX 8B 10B disparity error R rx_errdetect When set to 1 indicates an RX 8B 10B error detected Arria 10 GMII PC
425. odes or disparity errors that invalid words to must be received before the word aligner loses synchronization lose sync The default is 3 Number of valid 0 255 Specifies the number of valid data codes that must be received to data words to decrement the error counter If the word aligner receives enough decrement error valid data codes to decrement the error count to 0 the word count aligner returns to synchronization lock Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Standard PCS Parameters 2 33 Enable rx_std_ wa_patternalign port On Off Enables the rx_std_wa_patternalign port Enable rx_std_ wa_ala2size port On Off Enables the rx_std_wa_ala2size port Enable rx_std_ bitslipbound arysel port Enable rx_bitslip On Off On Off Enables the rx_std_bitslipboundarysel port Enables the rx_bitslip port port Table 2 27 Bit Reversal and Polarity Inversion Enable TX bit On Off When you turn this option on the 8B 10B Encoder reverses TX reversal parallel data before transmitting it to the PMA for serialization The transmitted TX data bit order is reversed to MSB to LSB rather than the normal LSB to MSB This is a static setting and can only be changed dynamically through dynamic reconfiguration Enable TX byte On Off When you turn this option on the 8B 10B Encoder reverses the reversal byte order before tr
426. ogical AND the p11_locked signals feeding the reset controller Similarly you can logical OR the p11_cal_busy signals to the reset controller tx_cal_busy port as shown below Figure 4 12 Multiple PLL Configuration To reset controller pll_locked input port pll_lock signals from PLLs pll_cal_busy and tx_cal_busy signals To reset controller tx_cal_busy input port Resetting different channels separately requires multiple reset controllers For example a group of channels configured for Interlaken requires a separate reset controller from another group of channels that are configured for optical communication Timing Constraints for Bonded PCS and PMA Channels For designs that use bonded TX PCS and PMA channels the digital reset signal to all TX channels within a bonded group must meet a maximum skew tolerance imposed by physical routing This skew tolerance is one half the TX parallel clock cycle tx_clockout This requirement is not necessary for bonded TX PMA only channel or for RX PCS channels Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 Timing Constraints for Bonded PCS and PMA Channels 4 19 Figure 4 13 Physical Routing Delay Skew in Bonded Channels FPGA Fabric PHY Reset TX gt gt Controller tx_digitalreset Channel n 1 Bonded TX Channels TX Channel 1 TX Jd Channel 0 You must provide a Synop
427. ollowing table describes the signals in the XGMII GMII and MII interfaces The MAC drives the TX XGMII GMII and MII signals to the 1G 10GbE PHY The 1G 10GbE PHY drives the RX XGMII GMI or MII signals to the MAC Table 2 93 SGMII and GMII Signals 1G 10GbE XGMII Data Interface xgmii_tx_ Input Synchronousto XGMII data and control for 8 lanes Each lane consists de 7ilsO A of 8 bits of data and 1 bit of control Komi e CLE xgmii_tx_clk Input Clock signal Clock for single data rate SDR XGMII TX interface to the MAC It should connect to xgmii_rx_clk This clock can be connected to the t x_div_ clkout however Altera recommends that you connect it to a PLI for use with the Triple Speed Ethernet MegaCore Function The frequency is 125 MHz for 1G and 156 25 MHz for 10G This clock is driven from the MAC The frequencies are the same if you enable 1588 or FEC xomii_rx_ Output Synchronous to RX XGMII data and control for 8 lanes Each lane de 730 xe consists of 8 bits of data and 1 bit of control xomi i elk Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 Data Interfaces 2 119 xgmii_rx_clk Input Clock signal Clock for SDR XGMII RX interface to the MAC This clock can be connected to the tx_div_clkout however Altera recommends that you connect it to a PLI for use with the Triple Speed Ethernet M
428. on MM interface The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read Modify Write or Write commands to the PMA and PCS Figure 2 60 Reconfiguration Block Diagram Eight compile time configurations are supported These include the enumerated combination of reference clock 644 MHz or 322 MHz including the 1588 mode and the FEC sublayer Figure 2 61 Reconfiguration Block Details mgmt_clk tcfg_data e e e address data 1 PCS Reconfiguration I F lt gt Res one rm Controller x control v p Avalon MM Master RES Reconfiguration Requests Note Based on the control signal the data is streamed to the AVMM master Related Information e Arria 10 Enhanced PCS Architecture on page 5 14 e Arria 10 Standard PCS Architecture on page 5 31 Clock and Reset Interfaces You can use PLL or CMU PLL to generate the clock for the TX PMA for the either the 1G or 10G data rate For the 1G data rate the frequency of the TX and RX clocks is 125 MHz which is 1 8 of the MAC data rate For 10G protocol the frequency of TX and RX clocks is 156 25MHz 1 64 of the MAC data rate You can generate the 156 25MHz clock directly by using a fPLL or you can divide the clock from TX PLL by 33 can be used Bonded clocks are not supported for 1G 10GbE PHY The following figure provides an overview of the
429. on Scrambler State Skip Diagnostic Synchronization Scrambler State Skip The framing control words include e Synchronization SYNC for frame delineation and lane alignment deskew e Scrambler State SCRM to synchronize the scrambler e Skip SKIP for clock compensation in a repeater e Diagnostic DIAG provides per lane error check and optional status message To form a metaframe the Enhanced PCS frame generator inserts the framing control words and encapsulates the control and data words read from the TX FIFO as the metaframe payload Figure 2 11 Interlaken Synchronization and Scrambler State Words Format bx10 6011110 hOF678FF6 78F678F6 bx10 b001010 Scrambler State 66 63 58 57 0 Figure 2 12 Interlaken Skip Word Format bx10 b000111 h21E h1E h1E hiE h1E hie h1E 66 63 5857 4847 40 0 Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Interlaken Configuration Clocking and Bonding 2 65 The DIAG word is comprised ofa status field and a CRC 32 field The 2 bit status is defined by the Interlaken specification as e Bit 1 Bit 33 Lane health e 1 lane is healthy e 0 lane is not healthy e Bit 0 Bit 32 Link health e 1 Link is healthy e 0 Link is not healthy The tx_enh_frame_diag_status 1 0 input from the FPGA fabric is inserte
430. on The frequency is 125 MHz for 1G and 156 25 MHz for 10G This clock is driven from the MAC The frequencies are the same if you enable 1588 or FEC 1G 10GbE GMII Data Interface Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback 2 162 Data Interfaces UG A10XCVR 2013 12 02 gmii_tx_d 7 0 Input Synchronousto TX data for 1G mode Synchronized to t x_pma_ t clkout clock The TX PCS 8B 10B module encodes this data which is sent to link partner clkout mel ieee cre e310 Output Synchronous to RX data for 1G mode Synchronized to rx_pma_ clkout clock The RX PCS 8B 10B decoders decodes ae this data and sends it to the MAC clkout gmii_tx_en Input Synchronousto When asserted indicates the start of a new frame It should remain asserted until the last byte of data on tx_pma_ 2 the frame is present on gmii_tx_d clkout gdi tx err Input Synchronousto When asserted indicates an error May be asserted at any time during a frame transfer to indicate an error epas 9 in that frame clkout gmii_rx_err Output Synchronous to When asserted indicates an error May be asserted at rx_pma_ any time during a frame transfer to indicate an error clkout in that frame Omid rx dv Output Synchronous to When asserted indicates the start of a new frame It remains asserted until the last byte of data on the repns fi s d rame is present on gmii
431. on Scripts 2 263 Synopsys VCS MX simulation synopsys vcsmx vcsmx_ setup sh Run this script at the command line using quartus_sh t lt script gt Any testbench you specify with NativeLink is included in this script Cadence Incisive NCSim simulation cadence ncsim_setup sh Run this script at the command line using quartus_sh t lt script gt Any testbench you specify with NativeLink is included in this script Qsys Simulation Scripts Implementing Protocols in Arria 10 Transceivers If you use Qsys to create your design you have the following two options to create scripts Generate Scripts in Qsys Qsys system generation creates the interconnect between components It also generates files for synthesis and simulation including the spd files necessary for the ip make simscript utility Complete the following steps to generate a simulation module for a Qsys system 1 On the Generate menu click Generate The Generation dialog box appears 2 Under Create simulation model select your HDL Note that Qsys appends simulation to your project directory to create a subdirectory for simulation files 3 Click Generate Qsys generates simulation files and scripts for the Aldec Riviera Pro Cadence NCSim and Mentor Graphics ModelSim simulation tools 4 You can run the scripts to compile the required device libraries and system design files in the correct order Then elaborate or load the top level design for simu
432. on and emphasizes the remaining bits A different polarity on pre tap does the opposite Figure 5 5 Effect of the 1st Post Tap Vp T x Vp T 1 Vn T x Vn T 1 xe dex Adax i 1x tee i tox tex i ed i et i ed bet eC Ee Signal withoyt pre emphasis sw Post Tap x 1 x si EUERE TEETE TET Vp T x Vp T 1 Vn T x Vn T 1 Signal without pre emphasis Pre Tap Vp T x Vp T 1 Vn T x Vn T 1 L2X 1 4 ta Lt na 44x x1 xT eT X 1_ 5 x 1 DENA PATARENI Signal without pre emphasis Inverted Pre Tap Signal with pre emphasis Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 4 Programmable Transmitter On Chip Termination OCT 2013 12 02 Table 5 1 Pre Emphasis Taps All four pre emphasis taps provide inversion control shown by negative values Pre Emphasis Tap Number of Settings Channel Loss Compensation dB Second pre tap 15 2 31 First pre tap 33 6 62 First post tap 51 15 56 Second post tap 25 4 44 You can set pre emphasis taps through the Avalon MM registers which will be available in a future release of the Quartus II software Related Information For more information about pre emphasis refer to AN 602 Programmable Transmitter On Chip Termination OCT Transmitter buffers include programmable on chip differential termination of 850 100Q or OFF Receiver The receiver deserializes the high speed serial data creates a parallel data stream f
433. onding core and periphery power supplies Refer to Arria 10 Device Datasheet for more details 2 For SX and GX device variants the maximum transceiver data rates are specified for the fastest 1 transceiver speed grade 3 For GT device variants the maximum transceiver data rates are specified for 2 transceiver speed grade 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN D E RYA 101 Innovation Drive San Jose CA 95134 z Fi UG A10XCVR 1 2 Device Transcei
434. onfigurations Table 3 5 ATX PLL Generation Options Generate parameter documenta On Off Generates a csv file which contains descriptions of tion file ATX PLL IP parameters and values Table 3 6 ATX PLL IP Ports pll_powerdown input Asynchronous _ Resets the PLL when asserted high Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 ATX PLL IP 3 9 pll refelko input Reference clock input port 0 There are a total of five reference clock input ports The number of reference clock ports available depends on the Number of PLL reference clocks parameter pll_refclkl input N A Reference clock input port 1 plil _refelk input N A Reference clock input port 2 pll_refclk3 input N A Reference clock input port 3 pll_refclk4 input N A Reference clock input port 4 tx_serial_clk output N A High speed serial clock output port for GX channels Represents the x1 clock network tx serial clk g output N A High speed serial clock output port for GT channels Represents the x1 clock network pll_locked output Asynchronous Active high status signal which indicates if PLL is locked pll peie clk output N A Used for PCIe reconfig_clk0 input N A Optional Avalon interface clock Used for PLL reconfiguration The reconfiguration ports appear only if the Enable Reconfiguration parameter is selected in the PLL IP GUI
435. ontrol xgmii_tx_dc 34 27 xgmii_sdr_ Lane 3 data data 31 24 zgi tx cdels35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_tx_dc 43 36 xgmii_sdr_ Lane 4 data data 39 32 xgmii_tx_dc 44 xgmii_sdr_ctrl1 4 Lane4 control xgmii_tx_dc 52 45 xgmii_sdr_ Lane 5 data data 47 40 KGa tz Cle 53 xgmii_sdr_ctrl 5 Lane 5 control xgmii_tx_dc 61 54 xgmii_sdr_ Lane 6 data data 55 48 zgmii tz cel62 xgmii_sdr_ctrl 6 Lane 6 control xgmii_tx_dc 70 63 xgmii_sdr_ Lane 7 data data 63 56 zomii tx _Cle 7 iL xgmii_sdr_ctrl 7 Lane7 control The 72 bit RX XGMII data bus format is different from the standard SDR XGMII interface The following table shows the mapping of this non standard format to the standard SDR XGMII interface Table 2 95 RX XGMII Mapping to Standard SDR XGMII Interface xgmii_rx_dc 7 0 xgmii_sdr_data 7 0 Lane 0 data RGM d_iose_Cle xgmii_sdr_ctrl1 0 Lane 0 control xgmii_rx_dc 16 9 xgmii_sdr_ Lane 1 data data 15 8 zomi rz delly xgmii_sdr_ctrl 1 Lane1 control xgmii_rx_dc 25 18 xgmii_sdr_ Lane 2 data data 23 16 zom e Cle 26 Lane 2 control zemi _sclie_ ceil 2 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 122 Serial Data Interface 2013 12 02 xgmii_rx_dc 34 27 xgmii_sdr_ Lane 3 data data 31 24 zomi rz del35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_rx_dc 43 36 xgmii_sdr
436. or each protocol Refer to the appropriate protocol s section for selecting valid parameters for each protocol Related Information e Using the Arria 10 Transceiver Native PHY IP on page 2 12 For information on Native PHY IP e Interlaken on page 2 62 Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 4 Generate PHY IP 2013 12 02 e Gigabit Ethernet GbE and GbE with 1588 on page 2 80 e 10GBASE R 10GBASE R with 1588 and 1OGBASE R with KR FEC on page 2 92 e 10GBASE KR PHY IP with FEC Option on page 2 103 1G 10 Gbps Ethernet PHY IP Core on page 2 149 e PCI Express on page 2 179 e CPRI on page 2 216 e Using the Basic and Basic with KR FEC Configurations of Enhanced PCS on page 2 225 e Using the Basic Custom Basic Custom with Rate Match Configurations of Standard PCS on page 2 232 e Design Considerations for Data Rates Above 17 4 Gbps Using Arria 10 GT Channels on page 2 250 Generate PHY IP After configuring the PHY IP click the Finish button in the MegaWizard Plug In Manager window and generate PHY IP The Quartus II software generates a lt phy ip instance name gt folder lt phy ip instance name gt _sim folder lt phy ip instance name gt qip file and lt phy ip instance name gt file This lt phy ip instance name gt file is the top level design file for the PHY IP and the folders contain lower level design files used for simulation and compilation Select P
437. or either the receiver PCS or the FPGA fabric and recovers the clock information from the received data The receiver portion of the PMA is comprised of the receiver buffer the clock data recovery CDR unit and the deserializer Figure 5 7 Receiver PMA Block Diagram Receiver PMA Receiver a nae Parallel Parallel Receiver p di Data Receiver Data FPGA Serial ase Buffer gt CDR gt Deserializer gt PCS f Fabric Serial Clock Parallel Clock Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR i 2013 12 02 Receiver Buffer 5 5 Receiver Buffer The receiver input buffer receives serial data from rx_serial_data and feeds the serial data to the clock data recovery CDR unit and deserializer Figure 5 8 Receiver Buffer CTLE From Serial Data e gt b VGA To CDR Input Pins RX d gt and DFE rx_serial_data Termination 85Q 1000 OFF Adaptive Parametric Tuning Engine V The receiver buffer supports the following features e Programmable common mode voltage Vc e Programmable differential On Chip Termination OCT e Signal Detector e Continuous Time Linear Equalization CTLE e Variable Gain Amplifiers VGA e Adaptive Parametric Tuning Engine e Decision Feedback Equalization DFE Programmable Common Mode Voltage Vem
438. or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes ISO 9001 2008 Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYAN UG A10XCVR 2 2 Transceiver Design Flow 2013 12 02 Transceiver Design Flow Figure 2 2 Transceiver Design Flow Select PHY IP y Configure the PHY IP Y Generate the Altera Transceiver PHY Reset Controller IP x v or create your own User Coded Reset Controller Generate PHY IP Select PLL IP v aan Create reconfiguration logic Configure the PLL IP if needed v Generate PLL IP v A v Connect PHY IP to PLL IP Reset Controller and connect reconfiguration logic via AVMM interface y Connect Transceiver Datapath to MAC IP Core o
439. or the CDR specify the parameter on the PLL tab during ATX PLL parameterization For the CMU specify the Number of PLL reference clocks under the PLL tab when parameterizing the CMU PLL The following table describes the mapping of the CDR reference clock inputs to their respective logical mapping The reconfiguration process requires the logical mapping The number of exposed rx_cdr_refclk CDR or pll_refclk CMU varies according to the number of reference clocks you specify The following table shows the logical mapping and the selection MUX offsets Use the Native PHY reconfiguration interface for switching the CDR reference clock Use the CMU reconfiguration interface for switching the CMU reference clock Table 6 10 Logical Mapping of CDR Reference Clock Inputs Native PHY Port Description Logical Reference Clock Offset cdr_refcl Represents logical refcl 0x16A 7 0 edr_refclki Represents logical refclk1 0x16B 7 0 cdr_refclk2 Represents logical refclk2 0x16C 7 0 edr_refclk3 Represents logical refclk3 0x16D 7 0 cdr_refclk4 Represents logical refc1k4 0x16E 7 0 N A CDR Refclk selection MUX 0x141 7 0 Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 Changing PMA Analog Parameters 6 13 When performing a reference clock switch note the logical reference clock to switch to and the respective offset and bits After determinin
440. orresponds to rx_ parallel_data 11 rx_runningdisp lt n gt lt w gt Output rx_clkout When high indicates that rx_parallel_ lt s gt 1 0 Ora data was received with negative disparity coreclkin When low indicates that rx_parallel_ data was received with positive disparity rx_ runningdispisa part of rx_parallel_ data For each 128 bit word rx_ runningdisp corresponds to rx_ parallel _data 15 rx_patterndetect lt n gt lt w gt Output Asynchronous When asserted indicates that the programmed lt s gt 1 0 word alignment pattern has been detected in the current word boundary rx_patternde tect isa part of rx_parallel_data For each 128 bit word rx_patterndetect corresponds to rx_parallel_data 12 rx_syncstatus lt n gt lt w gt Output Asynchronous When asserted indicates that the conditions lt e gt 1 0 required for synchronization are being met rx_syncstatus isa part of rx_ parallel_dataa For each 128 bit word rx_syncstatus corresponds to rx_ parallel_data 10 Table 2 47 Word Aligner and Bitslip Can a_n Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS and PMA Ports 2 59 tx stad bitsiipgbovnc Input Asynchronous Bitslip boundary selection signal Specifies the arysel 5 lt n gt 1 0 number of bits that the TX bit slipper must slip rx_std_bitslipbound Output Asynch
441. orts Enable PCle dynamic datarate Off On On switch ports Enable PCle pipe_hclk_in and pipe_hclk_out ports on On Enable PCIe Gen3 analog Off off On control ports Enable PCIe electrical idle On On On control and status ports Enable PCIe pipenn On On On polarity port Enable dynamic reconfiguration Optional Optional Optional Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for PCI Express Table 2 130 Parameter Settings When the Simplified Interface Is Enabled For every 128 bit word 2 203 tx_parallel_data tx_parallel_data 7 0 tx_parallel_ data 29 22 7 0 tx_parallel_ data 40 33 29 22 18 11 7 0 tx_datak tx_parallel_data 8 tx_parallel_data 30 8 tx_parallel_data 41 30 19 8 pipe_tx_compliance tx_parallel_data 9 tx_parallel_data 31 9 tx_parallel_data 42 31 20 9 pipe_tx_elecidle tx_parallel_data 10 tx_parallel_ data 32 10 tx_parallel_data 43 32 21 10 pipe_tx_detectrx_loopback tx_parallel_data 46 tx_parallel_data 46 tx_parallel_data 46 pipe_powerdown pipe_tx_margin tx_parallel_ data 48 47 tx_parallel_ data 51 49 tx_parallel_ data 48 47 tx_parallel_ data 51 49 tx_parallel_data 48 47 tx_parallel_data 51 49 pipe_tx_swing tx_parallel_data 53 tx_parallel_data 53 tx_parallel_data 53 rx_parallel_data rx_parallel_
442. otiation The 10GBASE KR PHY supports A0 and A2 The following protocols are defined e AO 1000BASE KX e Al 10GBASE KX4 e A210GBASE KR e A340GBASE KR4 e A440GBASE CR4 e A5 100GBASE CRI10 e A24 6 are reserved For more information refer to Clause 73 6 4 and AN LP base page ability registers 7 19 7 21 of Clause 45 of IEEE 802 3ap 2007 27 RO AN LP ADV Remote Fault Received Remote Fault RF ability bits RF is encoded in bit D13 of the base link codeword in Clause 73 AN For more information refer to Clause 73 6 7 and bits AN LP base page ability register AN LP base page ability registers 7 19 7 21 of Clause 45 of IEEE 802 3ap 2007 30 28 RO AN LP ADV Pause Ability_ C 2 0 Received pause ability bits Pause C0 C1 is encoded in bits D11 D10 of the base link codeword in Clause 73 AN as follows e CO is the same as PAUSE as defined in Annex 28B e Cl isthe same as ASM_DIR as defined in Annex 28B e C2 is reserved For more information refer to bits AN LP base page ability registers 7 19 7 21 of Clause 45 of IEEE 802 3ap 2007 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 134 10GBASE KR PHY Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr Link Training enable When 1 enables the 1OGBASE KR start up protocol When 0 disables the 1OGBASE KR start up protocol The default value is 1 For more info
443. oundary only if rx_std_wa_patternalign is asserted The word aligner asserts rx_syncstatus for one parallel clock cycle whenever it re aligns to the new word boundary Word Aligner Synchronous State Machine Mode In synchronous state machine mode when the programmed number of valid synchronization code groups or ordered sets is received rx_syncstatus is driven high to indicate that synchronization is acquired rx_syncstatus is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups after which rx_syncstatus is driven low The word aligner indicates loss of synchronization rx_syncstatus remains low until the programmed number of valid synchronization code groups are received again Word Aligner Deterministic Latency Mode The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process and automatically synchronizes and aligns the word boundary by slipping a clock cycle in the deserializer Incoming data to the word aligner is aligned to the boundary of the word alignment pattern K28 5 Using deterministic latency state machine mode and after the initial alignment following the deassertion of reset rx_std_wa_patternalign must be reasserted to initiate another pattern alignment Table 5 7 PCS PMA Interface Widths and Protocol Implementations PCS PMA Interface Width Protocol Implementations 8 Ba
444. our variant includes Auto Negotiation this bit is tied to 1 For more information refer to bits 7 1 3 and 7 48 0 of Clause 45 of IEEE 802 3ap 2007 AN Status When set to 1 link is up When 0 the link is down The current value clears when the register is read For more information refer to bit 7 1 2 of Clause 45 of IEEE 802 3ap 2007 LP AN Ability When set to 1 the link partner is able to perform Auto Negotiation When 0 the link partner is not able to perform Auto Negotiation For more information refer to bit 7 1 0 of Clause 45 of IEEE 802 3ap 2007 Seq AN Failure When set to 1 a sequencer Auto Negotiation failure has been detected When set to 0 a Auto Negotiation failure has not been detected 0x4C2 RO 7 RO 9 RO 17 12 RO KR AN Link Ready 5 0 Provides a one hot encoding of an_receive_idle true and link status for the supported link as described in Clause 73 10 1 The following encodings are defined e 6 b000000 1OOOBASE KX e 6 b000001 Reserved e 66000100 1OGBASE KR e 6 b001000 Reserved e 6 b010000 Reserved e 6 b100000 Reserved Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 132 10GBASE KR PHY Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr 0x4C3 15 0 User base page low The Auto Negotiation TX state machine uses these bits if the AN base pages ctrl bit is set The following bits are d
445. ove 17 4 Gbps Using Arria 10 GT Channel es cscs neocon scene E e E AE RER 2 250 Simulating the Transceiver Native PHY IP Core ess sssessessesssssssssissssssresssessesssteesnnessnsnrressrreeesneee 2 256 NatiyveLink Simulation PLOW ssissicaisscscssssesenssonusesuneanisteneavancivivasvencteteaasapacceacetavartanaineeassenseassieees 2 256 Custom Simulation FloWsiireesnnn nnn RO aE 2 260 PLLs and Clock Networks sssssssssssssossesssisnsiresersesssssiorosossseostisssssnivsson eors uor stesse 3 1 PUL ears coisstistax n E RARR E NN 3 3 ATX PU D EEE E A dae A E ETE 3 3 a a a A isle ean E A EE EA 3 11 GMU TPT sonatas cha ninns ncaa iii niaaa EE E EE RE RA EE 3 19 Inp t Reference Cl ck SOUR a setae ius haat ccs tan ancl E eean E ache ius hades Sae AEE SEREA aira Sa 3 24 Dedicated Reterence Clock PihSenssiscansiucnninsinunnnanuinnnniiuna s 3 25 Receiver Input Pits sss sssdisicescssssechevencssseicasesceds dus eveevensvscescoenedponsdeuevasednehetsatucedended cotveendbaaecsdsiaaea 3 26 PLL Cascading as a Input Reference Clock Source aginanscrmivenisendiancamimamnasaisness 3 26 Reference Clock NetwWworkarsssisinicesannsosunnns asana 3 27 Tra smitter Clock INGO i sicsiieaasdsasontannipdsiwsipssnapsdiasddcarasnaxuonsaicadecdcassbinsisedssubspiiassetaashdcacashoidenniesanddeabens 3 27 Xl Clock LINES orsi de sanacsnseacpnski copays hvdave var bvwsubvnedngulsoransitachsvhusiiensssubeivwsehdeeainetabnwsdasshapthomlacesviosssn 3 27 X6 Clock MIM CSiccsdcscu
446. ow to Use NativeLink to Run a ModelSim Altera RTL Simulation The following figure illustrates the high level steps for NativeLink with ModelSim Altera simulation Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 258 How to Use NativeLink to Run a ModelSim Altera RTL Simulation 2013 12 02 Figure 2 134 NativeLink Simulation Flow Diagram Specify EDA Simulator amp Simulator Directory y Run RTL Functional or Gate Level Simulation Simulation Give Expected Results No gt Debug Design amp Make RTL Changes y Run Quartus II Analysis and Elaboration y Define Control Signals Using In System Sources amp Probes y Run Simulation Simulation Give Expected Results Complete the following steps to run an RTL functional simulation 1 Open your Quartus II project On the Tools menu select Run Simulation Tool then select RTL Simulation or Gate Level Simulation Complete the following steps to define control signals necessary for simulation PY Ny On the Tools menu select In System Sources and Probes Editor Note To re simulate after correcting errors you must first rerun Quartus II Analysis and Elaboration and re instantiate control signals that you defined using the In System Sources and Probe Editor The In System Sources and Probe Editor can only access the pins of the device Consequently
447. p numbers correspond to the numbers in the waveform 1 Perform the following steps a Assertp11_powerdown tx_analogresetand tx_digitalreset while pll_cal_busy and tx_cal_busy are low b Hold p11_powerdown asserted for a minimum duration of t511 c Deassert tx_analogreset at the same time or after you deassert p11_powerdown 2 The p11_locked status signal goes high after TX PLL acquires lock 3 Deassert tx_digitalreset after pl11_locked goes high Note You must reset the PCS blocks by asserting tx_digitalreset every time you assert pll_powerdown_powerdown and tx_analogreset Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 4 5 2013 12 02 Resetting the Receiver After Device Power Up Figure 4 4 Transmitter Reset Sequence During Device Operation Device Power Up pll_cal_busy tx_cal_busy pll_powerdown tx_analogreset Cee tx_digitalreset gt re th cigtareset min 20 ns pll_locked p I f4 taro MAX 10 us Resetting the Receiver After Device Power Up Follow this reset sequence to ensure a reliable receiver initialization after initial power up The following steps detail the receiver reset sequence after device configuration The step numbers correspond to the numbers in the waveform 1 Hold rx_analogreset and rx_digitalreset active at power up to hold the receiver in reset 2 Makesure the rx_cal_busy status is deassert
448. package 780 pins Packages F34 and F35 35 mm x 35 mm package size 1152 pins Package F40 40 mm x 40 mm package size 1517 pins Arria 10 Transceiver PHY Overview Altera Corporation CJ Send Feedback 1 16 Transceiver Bank Architecture Figure 1 14 Three Channel GX Transceiver Bank Architecture UG A10XCVR 2013 12 02 Three Channel GX Transceiver Bank Clock Distribution Network Pes Channel PLL CDR Only Local CGB2 fPLLO pcs FPGA Core Channel PLL Fabric CMU CDR Local CGB1 Naser CGBO Pes Channel PLL CDR Only Local CGBO ATX PLLO Figure 1 15 Six Channel GX Transceiver Bank Architecture Clock Six Channel GX Transceiver Bank Distribution Network Channel PLL Ll CDR Only Local CGB5 4 fPLL1 cal PLL CMUICDR Local CGB4 Master CGB1 Channel PLL CDR Onl Local CGB3 a FPGA Core PLL1 Fabric Local CGB1 Channel PLL CDR Onl Local CGB2 acid PLL CMU CDR ae eal PLL CDR Onl Local CGBO lt fPLLO Master CGBO ATX PLLO Altera Corporation Arria 10 Transceiver PHY Overview CJ Send Feedback UG A10XCVR 2013 12 02 Figure 1 16 GT Transceiver Bank Architecture PHY Layer Transceiver Components 1 17 In GT devices the transceiver bank
449. parate Master CGB in the hardware However a logical PCS Master Channel must be Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Master Channel in Bonded Configurations 2 213 specified and the Native PHY provides an option to set this You can choose any one of the data channels part of the bonded group as the logical PCS master channel Note Whichever channel you pick as the PCS master the fitter will select physical CH1 or CH4 of a 6 pack as the master channel This is because the ASN and Master CGB connectivity only exists in the hardware of these two channels of the 6 pack Altera recommends the following as defaults PIPE Configuration Logical PCS Master Channel default xl 1 x2 2 x4 2 x8 5 The following figures show the default configurations Figure 2 85 x2 Configuration CH5 fPLL CH4 Master ATX PLL CH3 6 Pack CH2 fPLL CH1 Master ATX CoB PLL CHO CH5 fPLL CH4 pa ATX PLL CH3 6 Pack CH2 fPLL 2 CH1 ATX PLL 1 CHO Logical Physical Channel Channel Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 214 Master Channel in Bonded Configurations Figure 2 86 x4 Configuration Figure 2 87 x8 Configuration 3 2 Logical Channel UG A10XCVR 2013 12 02 CH5 fPLL CH4 o A
450. pcssessuiadsetesssestalievatseontaddaaiasaontananpasaeoasavensanneccy 4 2 FLOW DG E RESO EEE EE 4 2 Recommended Reset Seqg ettesrissnsnsastieia se anas aeaa E shes E aad 4 3 Transceiver Blocks Affected by Reset and Powerdown Signals sssssesssssesssssresessrresrssreeesree 4 8 Altera Corporation Reset Signals for PLL PMA and PCS BIOS siccssscanssecsaskauasssianier dees lan pecan aanepamenaisaiaed 4 8 Using the Altera Transceiver PHY Reset Com troller ccsutcissscsrcsevtanviasrastng areeianandateiosaaentawaatts 4 8 Parameterizing the Transceiver PHY Reset Controller TP nwisissssascstssssosssssssvenscassssssnnsnscnsssonied 4 10 Transceiver PHY Reset Controller Paranstters scsscisiinsiscanivneeerdamniianwasennaaeas 4 10 Transceiver PHY Reset Controller litertaces ssiscisssscscciniedcincauiestnniainuanmumanuseases 4 12 Transceiver PHY Reset Controller Resource UtliZzationisscccsssscsnsassecsssectasacuusassasorscnsadssvnsssnnse 4 16 Using a User Coded Reset Controller cxciscssiiGosaiscnsrocnioeaancensianneainacstvinnrninined a 4 16 User Coded Reset Controller Signals ses seseessseseesesesssrsseressresssresnrestresstrsssrresreresreeesreesrreesnres 4 16 Combining Status or PLL Lock Signals ssscscsssssssissscoassaed cssnvavesssnssscvesastsensnvanachssaeniseasadsdubsaansassnsusssdnctbens 4 18 Timing Constraints for Bonded PCS and PMA Chaninels csccvsssssssssessssssssversesonasessrassssessausasscsiers 4 18 Arria 10 Transceiver PHY Arc
451. per address 10 lt N gt 1 0 clk bits specify the channel reconfig_ Input reconfig_ A 32 bit data write bus Data to be written into the writedata 32 lt N gt elk address indicated by reconfig_address LeO reconfig_ Output reconfig_ A 32 bit data read bus Valid data is placed on this readdata 32 lt N gt 1 0 clk bus after a read operation Signal is valid after waitrequest goes high and then low reconfig_ Output reconfig_ A one bit signal that indicates the Avalon interface waitrequest lt N gt 1 0 clk is busy Issue no Avalon commands while this signal is high If you enable Share reconfiguration interface for a 2 channel instance the reconfig_address bus becomes an 11 bit bus reconfig_address 10 address The uppermost bit 10 of 1 indicates channel 1 0 The lower 10 bits 9 0 is the reconfiguration indicates the active channel A value of 0 indicates channel 0 and a value Table 6 2 Reconfiguration Interface Ports with Share Reconfiguration Interface Enabled The following table lists the reconfiguration interface ports when Shared reconfiguration interface option is enabled N equals the number of channels in the following table reconfig_clk 0 0 Input N A Avalon clock Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 Ports and Parameters 6 3 reconfig_
452. phase compensation FIFO is full rx_pcfifo_ Output Synchronous to rx_ When asserted indicates that the Standard PCS RX error_lg clkout phase compensation FIFO is full leil mE Input Synchronous to When asserted indicates a Remote Fault RF The zgmii tx clik MAC sends this fault signal to its link partner Bit D13 oftheAuto Negotiation Advanced Remote Fault register 0xC2 records this error rx_clkslip Input Asynchronous signal When asserted indicates that the deserializer has either skipped one serial bit or paused the serial clock for one cycle to achieve word alignment As a result the period of the parallel clock could be extended by 1 unit interval UI during the clock slip operation rx_latency_ Output Synchronous to rx_ When you enable 1588 this signal outputs the real adj igiiils0 clkout time latency in GMII clock cycles 125 MHz for the RX PCS and PMA datapath for 1G mode tx_latency_ Output Synchronous to tx_ When you enable 1588 this signal outputs real time adj_lg 11 0 clkout latency in GMII clock cycles 125 MHz for the TX PCS and PMA datapath for 1G mode rx_latency__ Output Synchronous to rx_ When you enable 1588 this signal outputs the real acli_LoOg Lie clkout time latency in XGMII clock cycles 156 25 MHz for the RX PCS and PMA datapath for 10G mode tx_latency_ Output Synchronous to tx_ When you enable 1588 this signal outputs real time adj_10g 11 0 clkout latency in XGMII clock cycles
453. pldif_datawidth_mode with a value of 1 h0 e hssi_tx_pcs_pma_interface_tx_pma_data_sel with a value of 2 h0 e hssi_tx_pcs_pma_interface_prbs_gen_pat with a value of 1 h0 e hssi_tx_pcs_pma_interface_sq_wave_nunm with a value of 4 h4 Writing to bit 7 of offset 0x008 changes the hssi_tx_pcs_pma_interface_pldif_datawidth_mode feature The same data array information is also represented using the System Verilog parameter keyword localparam The C header file is setup similar to the System Verilog package file The consist of an unsigned data array of 26 bit hexadecimal values and the second part consists of constant values Both the data array and the constant values represent the same values The MIF is setup is setup similar to the data array in the System Verilog package file and the C header file Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration CJ Send Feedback UG A10XCVR 2013 12 02 Transmitter PLL Switching 6 9 Altera recommends following the flow described in section Reconfiguring Transceiver and PLL Blocks when performing dynamic reconfiguration of either the Native PHY or transmit PLL Related Information Reconfiguring Channel and PLL Blocks on page 6 5 Transmitter PLL Switching Dynamically switching data rates increases system flexibility to support multiple protocols You can change the transceiver channel data rate by switching the PLL You can clock transceiver channels with up to four different trans
454. ple checks the status of p11_lockedand pll_cal_busy Note You must ensure a stable reference clock is present at the PLL transmitter before releasing PLL powerdown p11_powerdown User Coded Reset Controller Signals Refer to the signals in the following figure and table for implementation of a user coded reset controller Altera Corporation Resetting Transceiver Channels CJ Send Feedback UG A10XCVR 2013 12 02 User Coded Reset Controller Signals 4 17 Figure 4 10 User Coded Reset Controller Transceiver PHY and TX PLL Interaction tx_analogreset User Coded tx_digitalreset Transceiver PHY Instance Reset rx_analogreset clock Controller Transmitter Transmitter cock j _xdigitalreset PCS PMA tx_cal_busy rxi cal_busy rx is lockedtoref rx_Is_lockedtodata Receiver Receiver PCS PMA zl gie D eea am 217 fo i AS I i DE Efe You can logical OR the pll_cal_busy en and tx_cal_busy signals Transmit PLL Table 4 6 User coded Reset Controller Transceiver PHY and ATXPLL Signals pll_powerdown Output Resets the TX PLL when asserted high tx_analogreset Output Resets the TX PMA when asserted high tx_digitalreset Output Resets the TX PCS when asserted high rx_analogreset Output Resets the RX PMA when asserted high rx_digitalreset Output Resets the RX PCS when asserted high Glock Input Clock signal for the user coded res
455. pping signal mapping signal mapping provided at provided at end of provided at end of end of this table this table this table Table 2 127 Parameterizing Arria 10 Native PHY IP in PIPE Gen1 Gen2 Gen3 Modes TX PMA TX Bonding Options Non bonded x1 Non bonded x1 Non bonded x1 TX chi bondi d CHANEL ponding MOTE PMA amp PCS Bonding PMA amp PCS Bonding PMA amp PCS Bonding PCS TX channel bonding Aut Auto Auto master Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for PCI Express 2 199 Actual PCS TX channel bonding master E 0 TX PLL Options TX local clock division factor N A Gen3 x1 2 Number of TX PLLs 1 1 hie SEE T Main TX PLL logical index N A N A N A TX PMA Optional Ports Enable t x_pma_clkout port Optional Optional Optional Enable t x_pma_div_ s eikene pori Optional Optional Optional tx_pma_div_clkout i 3 ea ei Optional Optional Optional Enable tx_pma_clkslip N A N A N A port Enable tx_pma_qpipullup port QPI Off Off Off Enable tx_pma_qpipulldn port QPI Off Off Off Enable t x_pma_ txdetectrx port QPI On Of Ce Enable tx_pma_rxfound off off off port QPI Table 2 128 Parameterizing Arria 10 Native PHY IP in PIPE Gen1 Gen2 Gen3 Modes RX PMA RX CDR Options Number of CDR reference il
456. ppm total difference between the upstream transmitter and the local receiver reference clock Note Rate match FIFO is not available in the GbE with 1588 protocol The GbE protocol requires the transmitter to send idle ordered sets I1 K28 5 D5 6 and 12 K28 5 D16 2 during inter packet gaps adhering to the rules listed in the IEEE 802 3 specification The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high The rate match FIFO deletes or inserts the I2 K28 5 D16 2 ordered set to prevent the rate match FIFO from overflowing or under running during normal packet transmission The rate match FIFO deletes or inserts the first two bytes of the C2 ordered set K28 5 D2 2 Dx y Dx y to prevent the rate match FIFO from overflowing or underflowing The rate match FIFO inserts or deletes as many 12 or C2 first two bytes as necessary to perform the rate match operation The following figure shows the rate match deletion operation where three symbols must be deleted Because the rate match FIFO can only delete I2 ordered sets it deletes two 12 ordered sets four symbols deleted Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Rate Match FIFO for GbE 2 85 Figure 2 31 Rate Match FIFO Deletion 2 SKIP Symbol Deleted Second 12 Ordered Set
457. put is used by the charge pump and loop filter to generate a control voltage for the VCO The charge pump translates the Up Down pulses from the PFD into current pulses The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency Voltage Controlled Oscillator VCO The fPLL has a ring oscillator based VCO The VCO transforms the input control voltage into an adjustable frequency clock VCO freq M refclk N N and M are the N counter and M counter division factors L Counter The L counter divides the VCO s clock output When fPLL acts as a transmit PLL the output of the L counter drives the clock generation block CGB and the TX PMA The division factors supported are 1 2 4 and 8 M Counter The M counter divides the VCO s clock output The M counter can select any VCO phase The output of the M counter and N counter have same frequency Delta Sigma Modulator The delta sigma modulator is used in fractional mode Depending on the value of K input it modulates the output of M counter over time The value of K input can be changed dynamically to use the PLL as replacement for the VCXO The delta sigma modulator can be configured in 1st order 2nd order or 3rd order mode C Counters The C counter s design is identical to the M counter s design However the C counter is present in the fPLL s output path and is not in the PLL s feedback path Dynamic Phase Shift The d
458. r Datapath 5 23 The FEC sublayer is optional and can be bypassed When used it can provide additional margin to allow for variations in manufacturing and environmental conditions FEC can achieve the following objectives e Support a forward error correction mechanism for the 1OGBASE R KR and 40GBASE R KR protocols e Support the full duplex mode of operation of the Ethernet MAC e Support the PCS PMA and Physical Medium Dependent PMD sublayers defined for the 1OGBASE R KR and 40GBASE R KR protocols With KR FEC the BER performance of the system can be improved Transcode Encoder The KR forward error correction KR FEC transcode encoder block performs the 64B 66B to 65 bit transcoder function by generating the transcode bit The transcode bit is generated from a combination of 66 bits after the 64B 66B encoder which consists of a 2 bit synchronization header SO and S1 and a 64 bit payload DO D1 D63 To ensure a DC balanced pattern the transcode word is generated by performing an XOR function on the second synchronization bit S1 and payload bit D8 The transcode bit becomes the LSB of the 65 bit pattern output of the transcode encoder Figure 5 30 Transcode Encoder 66 Bit Input D63 DI DB da DO S1 S0 65 Bit Output D63 D9 D8 i DO S1 D8 KR FEC Encoder FEC 2112 2080 is an FEC code specified in Clause 74 of the IEEE 802 3 specification The code is a shortened cy
459. r PHY Implementation tx_analogreset Reset tx_digitalreset Controller y_analogreset ae clock ransmitter Transmitter 2 p user coded rx_digitalreset PCS PMA or Altera IP Transceiver PHY Instance tx_cal_busy p cal_busy x_is_lockedtoref rx_is_lockedtodata Receiver Receiver PCS PMA 4 2 2 wo e g 8 S S Tl penatia You can logical OR the pll_cal_busy ane and tx_cal_busy signals Transmit PLL 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information a
460. r PLL Native PHY Instance Instance 5 GHz 10 CH Bonded 10 Gbps P ATXPLL p cop _ 6 e Feedback Clock p Transceiver PLL Instance 5 GHz 4 lp atx pit p cop E e Feedback Clock Legend E TX channels placed in the same transceiver bank m TX channels placed in the adjacent transceiver bank The data rate is limited by the x6 network speed limit A disadvantage of using PLL feedback compensation bonding is that it consumes more PLL resources Each transceiver bank consumes one PLL and one master CGB In PLL feedback compensation bonding mode the N counter reference clock divider is bypassed in order to ensure that the reference clock skew is minimized between the PLLs in the bonded group Because the N counter is bypassed the PLL reference clock has a fixed value for any given data rate The PLL IP MegaWizard Plug In Manager GUI displays the required data rate in the PLL reference clock frequency drop down menu Steps to implement a PLL Feedback Compensation Bonding Configuration PLLs and Clock Networks Altera Corporation GJ Send Feedback UG A10XCVR 2013 12 02 1 Choose the PLL IP ATX PLL or fPLL you want to instantiate in your design and instantiate the PLL IP Refer to Instantiating ATX PLL on page 3 5 or Instantiating fPLL IP on page 3 13 for detailed steps 2 Configure the PLL IP using the MegaWizard Plug In Manager e Because the
461. r Precision time protocol PTP as defined in the IEEE 1588 Standard Gen1 PIPE Enforces rules for a Genl PCIe PIPE interface that you can connect to soft MAC and Data Link Layer Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to soft MAC and Data Link Layer Gen3 PIPE Enforces rules for a Gen3 PCIe PIPE interface that you can connect to soft MAC and Data Link Layer Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 PMA Parameters 2 17 Basic Enhanced PCS Enforces a standard set of rules within the Enhanced PCS Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules Interlaken Enforces rules required by the Interlaken protocol SFIS Enforces rules required by the SFIS protocol 10G SDI Enforces rules required by the SDI 10G protocol 10GBASE R Enforces rules required by the 1OGBASE R protocol 10GBASE R 1588 Enforces rules required by the 1OGBASE R protocol when you enable 1588 10GBASE R w KR FEC Enforces rules required by the 1OGBASE R protocol when you enable the KR FEC block enabled Basic w KR FEC Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the
462. r fPLL for Gen1 Gen2 Gen3 x4 Mode X6 Network va chs CGB CDR Ch4 CGB CDR Ch3 CGB CDR Ch2 CGB CDR CGB Chi CDR CGB cho CDR The figure shown is just one possible combination for the PCle Gen1 Gen2 Gen3 x4 mode The x6 and xN clock networks are used for channel bonding applications Each master CGB drives one set of x6 clock lines Gen1 Gen2 mode use the fPLL ONLY Gen3 mode uses the ATX PLL ONLY Use the pll_pcie_clk from the fPLL configured as Gen1 Gen2 This is the hclk required by the PIPE interface 2 195 Altera Corporation UG A10XCVR 2 196 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode 2013 12 02 Figure 2 82 Use ATX PLL or fPLL for Gen1 Gen2 Gen3 x8 Mode e ch5 CGB oy CDR 6 6 6 N K Ch4 CGB CDR Master 6 CGB Ch3 CGB CDR One HSSI Ch2 Tile Connections Done CGB via X1 Network fPLL1 E CDR D msa Chi CGB ATX PLL1 CDR cho 4x6 CoB e CDR Ch5 s CGB CDR One cha HSSI Tile 4x6 CoB Master CGB CDR Notes 1 The f
463. r mode Arria 10 Transceiver PHY Architecture Altera Corporation GJ Send Feedback UG A10XCVR 5 32 TX FIFO Low Latency Mode 2013 12 02 Figure 5 39 TX FIFO Block Diagram Datapath to Byte Serializer TX Datapath from FPGA Fabric 8B 10B Encoder lt FIFO lt or PIPE Interface or Serializer rd_clk wr_clk tx_coreclkin tx_clkout __ The TX FIFO read port is clocked by the low speed parallel clock and its write port is clocked by either tx_clkout or tx_coreclkin tx_clkout is used when only one channel is being used tx_coreclkin is used when using multiple channels The TX FIFO is shared with PCIe Gen3 and Enhanced PCS data paths TX FIFO Low Latency Mode The low latency mode incurs two to three cycles of latency latency uncertainty when connecting it with the FPGA fabric The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases which in turn decreases the latency TX FIFO Register Mode The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements This is accomplished by tying the read clock of the FIFO with its write clock The register mode incurs only one clock cycle of latency when interfacing to the FPGA fabric Byte Serializer In certain applications the FPGA fabric interface cannot operate at the same clock rate as the transmitter channe
464. r more information about PMA architecture e Using PLLs and Clock Networks on page 3 40 For more information about implementing PLLs and clocks e PLLs on page 3 3 PLL architecture and implementation details e Resetting Transceiver Channels on page 4 1 Reset controller general information and implementation details e Enhanced PCS and PMA Ports on page 2 37 For detailed information about the available ports in the 1OGBASE R 1588 protocol Medium Native PHY IP Parameter Settings for 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC Table 2 72 General and Datapath Parameters The first two sections of the MegaWizard Plug In Manager for the Transceiver Native PHY provide a list of general Device speed grade and datapath options to customize the transceiver fastest Message level for rule violations error warning Transceiver Configuration Rule e 10GBASE R e 10GBASE R 1588 e 10GBASE R with KR FEC Transceiver mode TX RX Duplex TX Simplex RX Simplex Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 100 Native PHY IP Parameter Settings for 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC UG A10XCVR 2013 12 02 Number of data channels 1 to 96 Data rate 10312 5 Mbps Enable reconfiguration between On Off Standard and Enhanced PCS Enable simplified data interface Off Table 2 73 TX PMA Parameters
465. r the local device Set to 1 for half duplex support This bit should always be set to 0 8 7 RW PS2 PS1 Pause support for local device The following encodings are defined for PS1 PS2 e 2 b00 Pause is not supported e 2 b0 1 Asymmetric pause toward link partner e 2 b10 Symmetric pause e 2 b11 Pause is supported on TX and RX RF2 RF1 Remote fault condition for local device The following encodings are defined for RF1 RF2 e 2 b00 No error link is valid reset condition e 2 b0 1 Offline e 2 b10 Failure condition e 2 b11 Auto negotiation error Acknowledge for local device A value of 1 indicates that the device has received three consecutive matching ability values from its link partner Altera Corporation Next page In the device ability register this bit is always set to 0 Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Arria 10 GMII PCS Registers 2 145 M 0x495 Full duplex mode enable for the link partner This bit should always be 1 because only full duplex is supported Half duplex mode enable for the link partner A value of 1 indicates support for half duplex This bit should always be 0 because half duplex mode is not supported 8 7 PS2 PS1 Specifies pause support for link partner The following encodings are defined for PS1 PS2 e 2 b00 Pause is not supported e 2 b0 1 Asymmetric pause toward link par
466. r to a Data Generator Analyzer y Compile Design AA Verify Design Functionality Related Information Arria 10 Transceiver PHY Design Examples Note The design examples on the alterawiki page provide useful guidance for developing your own design However alterawiki is not guaranteed by Altera Select and Instantiate PHY IP Select the appropriate PHY IP to implement your protocol Refer to the Arria 10 Transceiver Protocols and PHY IP Support section to decide which PHY IP to select to implement your protocol To instantiate a PHY IP 1 Open the Quartus II software 2 Click Tools gt MegaWizard Plug In Manager 3 4 Select Arria 10 device family Select Create a new custom megafunction variation then click Next Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Configure the PHY IP 2 3 5 Under Interfaces select the PHY IP you would like to use 6 Under Which type of output file do you want to create select Verilog or VHDL as the hardware description language 7 In What name do you want for the output file browse to the location where you want to save your design and enter a filename 8 Click Next The PHY IP GUI window opens Figure 2 3 Arria 10 Transceiver PHY Types MegaWizard Plug In Manager page 2a x Which device family will you be using Arria 10 Me Which type of output file do
467. ra implements IEI for Genl and Gen2 modes For Gen1 mode IFI can be done by signal detect or the inference mechanism For Gen2 mode IEI is done by inference mechanism In Gen2 mode do not use signal detect Table 2 125 Electrical Idle Inference Conditions in Gen1 Gen2 LO 3b100 Absence of Skip Ordered Absence of Skip Ordered Set Set in 128 us window in 128 us window Recovery RcvrCfg Absence of TS1 or TS2 Absence of TS1 or TS2 3 b101 Ordered Set in 1280 UI Ordered Set in 1280 UI interval interval Recovery Speed when Absence of TS1 or TS2 Absence of TS1 or TS2 successful speed negotiation 3 b101 Ordered Set in 1280 UI Ordered Set in 1280 UI 1 b1 interval interval Recovery Speed when Absence of an exit from Absence of an exit from successful speed negotiation 3 b110 Electrical Idle in 2000 UI Electrical Idle in 16000 UI 1 b0 interval interval Loopback Active as slave 3b111 Absence of Skip Ordered N A Set in 128 us window Receiver Status Altera Corporation The PCIe specification requires the PHY to encode the receiver status on a 3 bit status signal pipe_rx_status 2 0 This status signal is used by the PHY MAC layer for its operation The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks and encodes the status on the pipe_rx_status 2 0 signal to the FPGA fabric The encoding of the status signals on the pipe_rx_status 2 0 signal conforms to the PCIe spe
468. ransceivers for Basic functionality using the Native PHY IP Basic Enhanced PCS transceiver configuration rule Basic with KR FEC is a KR FEC sublayer support with a low latency physical coding sublayer PCS The KR FEC sublayer increases the bit error rate BER performance ofa link Use this configuration to implement applications with low latency or low BER requirements or applications such as 10 Gbps or 40 Gbps Ethernet over backplane 1OGBASER KR or 40GBASE KR4 protocol The Forward Error Correction FEC function is defined in Clause 74 of IEEE 802 3ap 2007 FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet mandated Bit Error Rate BER of 10 The FEC sublayer provides additional link margin by compensating for variations in manufacturing and environmental conditions To distinguish it from other FEC mechanisms for example Optical Transport Network FEC FEC as defined in Clause 74 of IEEE 802 3ap 2007 is called KR FEC Note This configuration supports the FIFO in phase compensation and register modes and KR FEC PCS blocks You can implement all other required logic for your specific application such as standard or proprietary protocol multi channel alignment either in the FPGA fabric in soft IP or use Altera s 10GBASE KR PHY or 40GBASE KR4 PHY IP core products as full solutions in the FPGA Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback
469. ransmitter reset sequence during device power up The step numbers correspond to the numbers in the waveform 1 After the transmitter PLL p11_powerdown is deasserted the p11_1locked status is asserted after to11_lock 2 Deassert tx_digitalreset after ty digitalreset The transmitter is now out of reset and ready for operation Note During calibration p11_locked might assert and deassert as the calibration IP runs After calibration p11_locked is a steady signal ATX PLL ref clock must be stable before pll1_powerdown signal is deasserted Resetting Transceiver Channels Altera Corporation CJ Send Feedback i z P A UG A10XCVR 4 4 Resetting the Transmitter During Device Operation 2013 12 02 Figure 4 3 Transmitter Reset Sequence After Power Up Device Power Up lt Device in User Mode pll_cal_busy tx_cal_busy pll_powerdown 2 tx_analogreset max 10 us ll_lock 5 pll_locked oe 2 vi min 20 tx_digitalreset O ag Lee 420S Note 1 The TX PLL reference clock must be stable before the p11_powerdown signal is deasserted Resetting the Transmitter During Device Operation Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation Use this reset to reestablish a link or after dynamic reconfiguration The following steps detail the transmitter reset sequence during device operation The ste
470. rate scrambled data A data checker in the scrambler monitors the data to determine if it should be scrambled or not If a synchronization word is found it is transmitted without scrambling If a Scrambler State Word is detected the current scramble state is written into the 58 bit scramble state field in the Scrambler State Word and sent over the link The receiver uses this scramble state to synchronize the descrambler The seed is automatically set for Interlaken protocol Figure 5 27 Synchronous Scrambler Showing Different Programmable Seeds LFSR Seed SO S37 38 S57 OUT S Jf f gt o E 37 Lo 38 be G9 57 DP Interlaken Disparity Generator The Interlaken disparity generator block is in accordance with the Interlaken protocol specification and provides a DC balanced data output The Interlaken protocol solves the unbounded baseline wander or DC imbalance of the 64B 66B coding scheme used in 10Gb Ethernet by inverting the transmitted data The disparity generator monitors the transmitted data and makes sure that the running disparity always stays within a 96 bit bound It adds the 67th bit bit 66 to signal the receiver whether the data is inverted or not Table 5 3 Inversion Bit Definition Bit 66 Interpretation 0 Bits 63 0 are not inverted the receiver processes this word without modification Bits 63 0 are inverted the receiver inverts the bits before proc
471. ration tx_analog_reset from TX PLL Block rx_analog_reset RX PMA RX Standard PCS 7 x Hligital_reset rx_datak gt rx_datak 1 0 rx_parallel_data gt rx_parallel_data 15 0 Deserializer fe 0 20 y rx_clkout gt rx_clkout rx_coreclkin rx_coreclkin rx_errdetect gt rx_errdetect 1 0 rx_serial_data gt rx_disperr gt rx_disperr 1 0 rx_cdr_refclkO gt CDR rx_runningdisp gt rx_runningdisp 1 0 x_is_lockedtodata lt rX_patterndetect gt 1X_patterndetect 1 0 rx_is_lockedtoref lt rx_syncstatus gt rx_syncstatus 1 0 refclk rx_std_wa_patternalign rx_std_wa_patternalign unused_rx_parallel_data 118 0 5 Instantiate and configure your PLL 6 Create a transceiver reset controller Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Implement CPRI in Arria 10 Transceivers 2 221 You can use your own reset controller or use the Native PHY Reset Controller IP 7 Connect the Native PHY IP to the PLL IP and the reset controller Use the information in Figure 2 93 to connect the ports Figure 2 94 Connection Guidelines for a CPRI PHY Design clk reset pll_sel pll_refclk pll_locked pll_powerdown greset greset y y tx_digitalreset rx_digitalreset tx_analo rx_ana
472. ration and may restart AN LT or both if these modes are enabled usr fec reset Input When asserted resets the 10GBASE KR FEC module usr_soft_10g_pcs_reset Input When asserted resets the 10G PCS associated with the FEC module Related Information e Input Reference Clock Sources on page 3 24 e PLLs on page 3 3 Parameterizing the 1G 10GbE PHY The Arria 10 1G 10GbE and 10GBASE KR PHY IP Core allows you specify either the Backplane KR or 1Gb 10Gb Fthernet variant When you select the Backplane KR variant the Link Training LT and Auto Negotiation AN tabs appear The 1Gb 10Gb Ethernet variant 1G 10GbE does not implement LT and AN parameters Complete the following steps to configure the 1G 10GbE PHY IP Core in the MegaWizard Plug In Manager Aun kk wWN Related Information e General Options on page 2 111 e 10GBASE R Parameters on page 2 111 For Which device family will you be using select Arria 10 from the list Click Installed Plug Ins gt Interfaces gt Ethernet gt Arria 10 1G10GbE and 10OBASE KR PHYver Select Gb 10Gb Ethernetfrom the IP variant list in MegaWizard Plug In Manager Use the tabs on the MegaWizard Plug In Manager to select the options required for the protocol Refer to the topics listed as Related Links to understand and specify 1G 10GbE parameters Click Finish to generate your parameterized 1G 10GbE PHY IP Core e 10M 100M 1Gb Ethernet Parameters on page 2 112 e Speed Det
473. rchitecture allows the Standard PCS to operate at double or quadruple the data width of the PMA Deserialize x4 PCIe deserializer The byte deserializer allows the PCS to run at a lower mode only internal clock frequency to accommodate a wider range of FPGA interface widths Table 2 24 8B 10B Encoder and Decoder Parameters Enable TX 8B On Off Enables the rx_std_rmfifo_full port 10B encoder Enable TX 8B On Off When you turn this option on the Standard PCS includes disparity 10B disparity control for the 8B 10B encoder You can force the disparity of the control 8B 10B encoder using the tx_forcedisp control signal Enable RX 8B On Off When you turn this option on the Standard PCS includes the 8B 10B decoder 10B decoder Table 2 25 Rate Match FIFO Parameters RX rate match Disabled Basic Specifies the operation of the RX rate match FIFO in the Standard FIFO mode single width Basic PCS double width GIGE PIPE PIPE 0 ppm RX rate match User specified 20 bit Specifies the ve positive disparity value for the RX rate match insert delete ve pattern FIFO as a hexadecimal string pattern hex RX rate match User specified 20 bit Specifies the ve negative disparity value for the RX rate match insert delete ve pattern FIFO as a hexadecimal string pattern hex Enable rx_std_ On Off Enables the optional rx_std_rmfifo_full port rmfifo_full port GJ Send Feedback Implemen
474. re provides a 1 bit PHY status pipe_phy_status and a 3 bit receiver status signal pipe_rx_status 2 0 to indicate whether a receiver was detected or not as per the PIPE 2 0 specifications Gen1 and Gen2 Clock Compensation In compliance with the PIPE specification Arria 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to 300 ppm between the upstream transmitter and the local receiver clocks Things to remember for PIPE clock compensation spec are as follows e Insert delete one SKP symbol in a SKP ordered set e For deletion no min limit imposed on the number of SKP symbols present in SKP ordered set after deletion An ordered set may have a bare COM case after deletion e For insertion no max limit imposed on the number of the SKP symbols present in the SKP ordered set after insertion An ordered set may have more than 5 symbols appear in SKP ordered set after insertion e For INSERT DELETE cases Flag status will appear on the COM symbol of the SKP ordered set where insertion deletion occurred e For FULL EMPTY cases Flag status will appear where character is inserted or deleted Note When the PIPE interface is on it will translate the value of the flags to the appropriate pipe_rx_status signal e The PIPE mode also has a 0 ppm configuration option that can be used in synchronous systems The Rate Match FIFO Block is not expected to do any clock compensation in this configur
475. read modify write to offset 0xA with a value of 1 b1 to bit 7 2 Perform a read modify write to offset OxB according to the PRBS Generator and Square Wave Offsets table For PRBS9 PRBS15 or PRBS23 write a one to either bit 7 bit 6 or bit 5 respectively Write to bit 3 2 with the counter threshold before the rx_prbs_done signal goes high 3 Perform a read modify write to offset 0xC with a value of 1 b1 to bit 0 for PRBS31 otherwise 1 b0 of other PRBS patterns Write the other bits according to Table 6 14 4 Perform a read modify write to offset 0x13F according to Table 6 14 5 Perform a reset To disable the PRBS verifier write the original values back into the read modify write offsets listed above Table 6 14 PRBS Checker Offsets Reconfiguration Reconfiguration Attribute Other Offsets Attribute Bit Encoding Description Address HEX Bit Name Encoding prbs_clk_dis Disable PRBS checker OxA 7 prbs_clken prbs_clk_en 1 b1 Enable PRBS checker Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration GJ Send Feedback UG A10XCVR 2013 12 02 Enabling the PRBS Data Checker 6 1 Reconfiguration Reconfiguration Attribute Other Offsets Attribute Bit Encoding Description Address HEX Bit Name Encoding 3 2 rx_prbs_ mask prbsmask1024 2 b11 1023 prbsmask128 2 b00 Counter threshold to 127 prbsmask256 2 b01 255 prbsmask512
476. reclkin mai rx_errdetect gt rx_errdetect gt rx_disperr gt rx_disperr gt CDR rX_runningdisp gt rx_runningdisp rx_patterndetect gt rx_patterndetect 7 rx_syncstatus gt rx_syncstatus refclk rx_rmfifostatus rx_rmfifostatus 1 unused_rx_parallel_data 111 0 1 rx_rmfifostatus is not available in the GbE with 1588 configuration 5 Instantiate and configure your PLL 6 Instantiate a transceiver reset controller You can use your own reset controller or use the Native PHY Reset Controller IP 7 Connect the Native PHY IP to the PLL IP and the reset controller Use the information in Figure 2 36 to connect the ports Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 88 Native PHY IP Parameter Settings for GbE and GbE with 1588 UG A10XCVR 2013 12 02 Figure 2 36 Connection Guidelines for a GbE GbE with 1588 PHY Design tx_parallel_data tx_datak tx_serial_data pll_ref_clk tx_clkout nm serial_data pll_locked pll_powerdown tx_digital_reset tx_analog_reset rx_digital_reset tx_ready clk rx_is_lockedtoref rx_is_lockedtodata tx_parallel_data reset tx_serial_clk 8 Simulate your design to verify its functionality Related Information Arria 10 Standard PCS Architecture on page 5 31 For more information about Standard PCS architecture Atria 10 PMA Architecture on p
477. reference clocks parameter pll_refclkl input N A Reference clock input port 1 pli_refclk2 input N A Reference clock input port 2 pll_refclk3 input N A Reference clock input port 3 pll_refclk4 input N A Reference clock input port 4 tx_serial_clk output N A High speed serial clock output port for GX channels Represents the x1 clock network pll_locked output Asynchronous _ Active high status signal which indicates if PLL is locked reconfig_clk0 input N A Optional Avalon interface clock Used for PLL reconfiguration The reconfiguration ports appear only if the Enable Reconfiguration parameter is selected in the PLL IP GUI When this parameter is not selected the ports are set to OFF internally reconfig_reset0 input reconfig__ Used to reset the Avalon interface c1k0 reconfig_write0 input reconfig__ Active high write enable signal clko reconfig_read0 input reconfig__ Active high read enable signal c1k0 reconfig_address0 9 0 input reconfig__ 10 bit address bus used to specify cl1k0 address to be accessed for both read and write operations PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 24 Input Reference Clock Sources 2013 12 02 recontig input reconfig__ 32 bit data bus Carries the write writedata0 31 0 celko data to the specified address reconfig_ output reconfig_ 32 bit data bus Carries the read readdat
478. reset 0 0 Input reconfig_ Resets the Avalon interface elik reconfig_write 0 0 Input reconfig_ Write enable signal Signal is active high clk reconfig_read 0 0 Input reconfig_ Read enable signal Signal is active high clk reconfig_ Input reconfig_ A 10 bit address bus Used in read and write address log2 lt N gt 9 0 clk operations reconfig_ Input reconfig_ A 32 bit data write bus Data to be written into the writedatal31 0 clk address indicated by reconfig_address reconfig_ Output reconfig_ A 32 bit data read bus Valid data is placed on this readdata 31 0 clk bus after a read operation Signal is valid after waitrequest goes high and then low reconfig_ Output reconfig_ A one bit signal that indicates the Avalon interface waitrequest 0 0 clk is busy Issue no Avalon commands while this signal is high Table 6 3 Avalon Interface Parameters Specify values for the following parameters in the Dynamic Reconfiguration tab of the Transceiver Native PHY and TX PLL parameter GUIs Reconfiguration Interface and Dynamic Reconfiguration Enable dynamic reconfigura Enable Enables the reconfiguration interface Disabled by default The tion Disable reconfiguration interface is exposed when this option is enabled Share reconfiguration Enable Use a single reconfiguration interface to control all channels interface Disable Disabled by default If enabled the upper most bits of the re
479. resets described in Preset Configuration Options You can then modify the setting to meet your specific requirements 4 Click Finish to generate the Native PHY IP this is your RTL file Altera Corporation Implementing Protocols in Arria 10 Transceivers C Send Feedback UG A10XCVR 2013 12 02 How to Implement GbE GbE 1588 in Arria 10 Transceivers 2 87 Figure 2 35 Signals and Ports for Native PHY IP Configured for GbE GbE with 1588 tx_cal_busy lt Arria 10 Transceiver Native PHY rx_cal_busy lt 4 tx_serial_data 4 tx_serial_clk0 from TX PLL NIOS e reconfig_reset Reconfiguration Hard Calibration IP Registers reconfig_clk gt reconfig_avmm TX PMA TX Standard PCS tx digital _reset tx_datak gmii_tx_ctrl tx_parallel_data 7 0 gmii_tx_d 7 0 Serializer eo _ tx_coreclkin _ gmii_tx_clk tx_clkout gt tx_clkout T unused_tx_parallel_data 118 0 lt Local Clock m Generation 4 tx_analog_reset rx_serial_data rx_cdr_refclkO rx_is_lockedtodata lt rx_is_lockedtoref Note Block rx_analog_reset RX PMA RX Standard PCS nx _digital_reset rx_datak gt gmii_rx_ctrl rx_parallel_data 7 0 gt gmii_rx_d 7 0 Deserializer 4 1 rx_clkout gt gmii_rx_clk rx_co
480. resss 2 64 Interlaken Configuration Clocking and Bonding sesessssssesressseressrrrsessrerersreresnreerrsnrrersreee 2 65 How to Implement Interlaken in Arria 10 Transceivers seseeeseeesseseressreereesresrserrrssresseesees 2 71 Design Examplennsrssissnanunsnnnnian ae e a a 2 74 Native PHY IP Parameter Settings for Titers hen scssivicsexsseassvarnersapsasaveassasvetanusaansanesnateannsvonnnie 2 75 PERM a DI AEE EE SE EAE A EE AER E E E 2 79 Gigabit Ethernet GbE and GbE with 1588 ciscssuscnsiistieastiaicsisscassieanasedstiaaeniinisbinecees 2 80 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC seseeseeeseeerseresesee 2 92 10GBASE KR PHY IP with FEC Option ses sesesssessesesesrrsreesressreestesterseerrssteestentesnteerresreeseeees 2 103 EGO Gbps Ethernet PHY IP Coie ai accecescusucsusasccuatac starsat eaneaeniesatvanancarsanesatetdeseaaueneeaesoentes 2 149 ACLODYING oii cs sass cesssstsnsiees E E E E EE 2 179 PCI EXPS Sirino a RA EE EE E E 2 179 Transceiver Channel Datapath for PIPE iisiwiseavenidaarcssenleacivectaavicasemsviienavenerderasianives 2 181 Supported PIPE Featur esis ssseccesssce asescaitetes asexcescsverencavenscsnrarsavesdanoesotisnd sasesnsasnaeaseeacesanesespeace 2 182 How to Connect TX PLLs for PIPE Gen1 Gen2 and Gen3 Mode ceceeeseeeeeeseeeeseees 2 191 How to Implement PCI Express in Arria 10 Transceivers esceseseesesesesesseeeeeeeeeeees 2 197 Native PHY IP Parameter Settings for PCI Expresses sssisiaisu
481. reversal on the RX interface Used if the MSB and LSB of the transmitted data are erroneously swapped Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 60 Standard PCS and PMA Ports 2013 12 02 rx_std_bitrev_ena lt n gt Input Asynchronous When asserted enables bit reversal on the RX 120 interface Bit order may be reversed if external transmission circuitry transmits the most significant bit first When enabled the receive circuitry receives all words in the reverse order The bit reversal circuitry operates on the output of the word aligner Rewires D 7 0 toD 0 7 and so on tx_polinv lt n gt 1 0 Input Asynchronous When asserted the TX polarity bit is inverted Only active when TX bit polarity inversion is enabled rx_polinv lt n gt 1 0 Input Asynchronous When asserted the RX polarity bit is inverted Only active when RX bit polarity inversion is enabled Table 2 49 Signal Detection rx_std_signaldetect lt n gt Output Asynchronous When enabled the signal threshold detection 1 0 circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that specified You can specify the signal detect threshold using a Quartus II Settings File qsf assignment This signal is required for the PCI Express and SATA protocols rx_std_elecidle lt n gt Input Asynchronous
482. rial Clock fPLL Parallel Clock Serial Clock Serial Clock Parallel and Serial Clock Input Reference Clock In the Standard PCS for configurations that do not use the byte serializer the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO For configurations that use the byte serializer block the clock is divided by 2 for the byte serializer and the read side of the TX phase compensation FIFO The clock used to clock the read side of the TX phase compensation FIFO is also forwarded to the FPGA fabric to provide an interface between the FPGA fabric and the transceiver If the tx_clkout that is forwarded to the FPGA fabric is used to clock the write side of the phase compensation FIFO then both sides of the FIFO have 0 ppm frequency difference because it is the same clock which is used If you choose to use a different clock than the tx_clkout to clock the write side of the phase compensation FIFO then you must ensure that the clock provided must have 0 ppm frequency difference with respect to the tx_clkout PLLs and Clock Networks Altera Corporation CJ Send Feedback r r UG A10XCVR 3 36 Receiver Data Path Interface Clocking 2013 12 02 Figure 3 13 Transmitter Enhanced PCS and PMA Clocking The Master Local CGB provides the serial clock to the serializer of the transmitter PMA and the parallel clock to the transmitter PCS Transmi
483. rlaken frame generator controls reads e Basic The TX FIFO acts as an elastic buffer to control the input data flow using tx_enh_data_valid The gearbox data valid flag controls the FIFO read enable Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS Parameters 2 23 TX FIFO 10 11 12 13 14 15 Specifies the partially full threshold for the Enhanced PCS TX partially full FIFO Enter the value at which you want to the TX FIFO to flag threshold a partially full status tx_enh_fifo_pfull_ is synchronous totx_coreclkin Enhanced PCS 32 40 64 Specifies the data interface width between the Enhanced PCS and PMA interface the transceiver PMA width FPGA fabric 32 40 50 64 66 67 Specifies the FPGA fabric to transceiver PCS interface width Enhanced PCS between the Enhanced PCS and the FPGA Fabric nee eee The 66 bit FPGA fabric PCS interface width uses 64 bits from the TX and RX parallel data and the lower 2 bits from the control bus The 67 bit FPGA fabric PCS interface width uses the 64 bits from the TX and RX parallel data and the lower 3 bits from the control bus TX FIFO 1 2 3 4 5 Specifies the partially empty threshold for the Enhanced PCS TX partially empty FIFO Enter the value at which you want TX FIFO to flag a threshold partially empty status Enable tx_enh_ On Off Enables the tx_enh_fifo_full port fifo_fu
484. rmation Reconfiguring Channel and PLL Blocks on page 6 5 Switching Reference Clocks You can dynamically switch the input clock source to the ATX PLL the fPLL the CMU and the CDR ATX Reference Clock Switching You can use the reconfiguration interface on the ATX PLL instance to specify which reference clock source drives the ATX PLL The ATX PLL supports clocking by up to five different reference clock sources Independent of the number of transmitter PLLs specified the flow to select between the different reference clock sources remain the same Before initiating a reference clock switch ensure that your ATX PLL instance defines more than one reference clock source Specify the Number of PLL reference clocks parameter on the PLL tab during ATX PLL parameterization The following table shows mapping of the ATX PLL reference clock inputs to their respective logical mapping The reconfiguration process requires this logical mapping The number of exposed pl 1_refclk ports varies according to the number of reference clocks you specify The following table shows the logical mapping and the selection MUX offsets Use the ATX PLL reconfiguration interface for this operation Table 6 8 Logical Mapping of ATX PLL Reference Clock Inputs ane emote ae Offset pll_refclk0 Represents logical refcl 0x113 7 0 pll refrelki Represents logical refclk1 0x114 7 0 pll_refclk2 Represents logical refc1k2 0x115 7
485. rmation refer to Clause 72 6 10 3 1 and 10GBASE KR PMD control register bit 1 150 1 of IEEE 802 3ap 2007 1 RW dis_max_wait_ When set to 1 disables the LT max_wait_timer Used for tmr characterization mode when setting much longer BER timer values 2 RW quick_mode When set to 1 only the init and preset values are used to calculate the best BER 3 RW pass_one When set to 1 the BER algorithm considers more than the first local minimum when searching for the lowest BER The default value is 1 7 4 RW main_step_cnt Specifies the number of equalization steps for each main tap 3 0 update There are about 20 settings for the internal algorithm 0x4D0 to test The valid range is 1 15 The default value is 4 b0010 11 8 RW prpo_step_cnt Specifies the number of equalization steps for each pre and 3 0 post tap update From 16 31 steps are possible The default value is 4 b0001 13 12 RW equal_cnt Adds hysteresis to the error count to avoid local minimums 1 0 The default value is 2 b01 16 RW Ovride LP Coef When set to 1 overrides the link partner s equalization enable coefficients software changes the update commands sent to the link partner TX equalizer coefficients When set to 0 uses the Link Training logic to determine the link partner coefficients Used with 0x4D1 bit 4 and 0x4D4 bits 7 0 17 RW Ovride Local When set to 1 overrides the local device equalization RX Coef enable
486. rol 19 0 m rx_enh_fifo_rd_en gt rx_enh_data_valid lt lt gt rx_enh_fifo_align_val rx_enh_fifo_align_clr p gt rx_enh_frame gt rx_enh_fifo_cnt 3 0 gt rx_enh_fifo_full p gt x_enh_fifo_pfull gt rx_enh_fifo_empty gt rx_enh_fifo_pempty 1x_enh_frame_diag_status 1 0 p gt rx_enh_frame_lock p gt rx_enh_crc32_err b gt m_enh_blk_lock 5 Instantiate and configure your PLL 6 Create a transceiver reset controller You can use your own reset controller or use the Altera Transceiver PHY Reset Controller IP 7 Implement a TX soft bonding logic and an RX multi lane alignment deskew state machine using fabric logic resources for multi lane Interlaken implementation 8 Connect the Native PHY IP to the PLL IP and the reset controller Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Implement Interlaken in Arria 10 Transceivers Figure 2 22 Connection Guidelines for an Interlaken PHY Design 2 73 This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Altera Wiki website For blue blocks Altera provides a megafunction IP The gray blocks are the TX soft bonding logic and RX deskew logic that are included in the design example The white blocks are your test logic or MAC layer logic
487. roller Connect the PHY IP PLL IP and the reset controller Write the top level module to connect all the IP blocks All the I O ports for each IP can be seen in the lt phy instance name gt file Refer to the ports tables in the PLL IP Using the Transceiver Native PHY IP and Resetting Transceiver Channels chapters for the description of the ports Related Information e Enhanced PCS and PMA Ports on page 2 37 e Standard PCS and PMA Ports on page 2 52 Connect the Transceiver Datapath to MAC IP Core or to a Data Generator Analyzer Connect the transceiver PHY layer design to the Media Access Controller MAC IP or to a data generator analyzer or a frame generator analyzer This can be also be a user created IP block Compile Design To compile the transceiver design ensure all the lt phy_instancename gt qip files for all the IP blocks generated using the MegaWizard Plug In Manager are added to the Quartus II project library Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Verify Design Functionality 2 7 Related Information Quartus II Incremental Compilation for Hierarchical and Team Based Design For compilation details Verify Design Functionality Simulate your design to verify the functionality of your design Refer to Simulating the Native Transceiver PHY IP Core section for more details Related Information Quartus II Handbook Volume 3 Verificat
488. ronous This signal operates when the word aligner is arysel 5 lt n gt 1 0 in bitslip word alignment mode It reports the number of bits that the RX block slipped to achieve deterministic latency rx_std_wa_ Input Asynchronous Active when you place the word aligner in patternalign lt n gt 1 0 manual mode In manual mode you align words by asserting rx_std_wa_ patternalign When the PCS PMA Interface width is 10 bits rx_std_wa_ patternalign is level sensitive For all the other PCS PMA Interface widths rx_std_ wa_patternalign is edge sensitive rx_std_wa_ala2size lt n gt Input Asynchronous Used for the SONET protocol Assert when the 1 0 Aland A2 framing bytes must be detected A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits EX bitsiipi lt n 130 Input Asynchronous Used when word aligner mode is bitslip mode When the Word Aligner is in either Manual PLD controlled Synchronous State Machine or Deterministic Latency the rx_bitslip signal is not valid and should be tied to 0 For every rising edge of the rx_std_ bitslip signal the word boundary is shifted by 1 bit Each bitslip removes the earliest received bit from the received data Table 2 48 Bit and Byte Reversal and Polarity Inversion rx_std_byterev_ena lt n gt 1 0 Input Asynchronous This control signal is available when the PMA width is 16 or 20 bits When asserted enables byte
489. ronous This port provides manual control of the RX data lt n gt 1 0 CDR circuitry rx_set_ Input Asynchronous This port provides manual control of the RX lockedtoref lt n gt 1 0 CDR circuitry rx_seriallpbken lt n gt Input Asynchronous When asserted enables the TX to RX serial ie loopback path in the transceiver rx_prbs_done lt n gt Output rx_ When asserted indicates the verifier has aligned 1 0 coreclkin and captured consecutive PRBS patterns and the first pass through a polynomial is complete The generator has restarted the polynomial rx_prbs_err lt n gt 1 0 Output rx_ When asserted indicates an error only after the coreclkin rx_prbs_done signal has been asserted This signal pulses for every error that occurs Errors can only occur once per word rx_prbs_err_clr lt n gt Input gt a When asserted clears the PRBS pattern and 12 0 coreclkin deasserts the rx_prbs_done signal Ex pma_clkout Output Clock This is the recovered parallel from the RX CDR circuitry rx_pma_div_clkout Output Clock This is a divided version the recovered RX parallel clock For the parallel clock you can divide rx_pma_div_clkout by 1 or 2 For the serial clock you can divide by 33 40 50 or 66 This clock drives rx_coreclkin for different gear box ratios rx_pma_clkslip Input Clock A rising edge on this signal causes the RX deserializer to slip the serial data by one clock cycle 2 UI Table 2 43 R
490. rotocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Standard PCS and PMA Ports 2 53 unused_tx_parallel_ data Input tx_clkout This signal specifies the unused data when you turn on Enable simplified data interface Connect all these bits to 0 tx_datak lt n gt lt d gt lt s gt 1 0 Input tx_clkout When 1 indicates that the 8B 10B encoded word of tx_parallel_data is data When 0 indicates that the 8B 10B encoded word of t x_ parallel_dataiscontrol tx_datak isa part of tx_parallel_data For each 128 bit word tx_datak corresponds to t x_ parallel_data 8 tx coreclkin Input Clock The FPGA fabric clock This clock drives the write port of the TX FIFO tx_clkout Output Clock The low speed parallel clock generated by the Transceiver TX PMA This clock times tx_ parallel_data from the FPGA fabric to the TX PCS Table 2 41 TX Standard PMA Data and Optional PMA Ports tx_serial_data lt n gt Input Serial data output of the TX PMA 15 0 Optional Ports tx_serial_clk1 Inputs Clocks Serial Clock inputs from the TX PLL The ae wee frequency of this clock depends on the data rate tx_serial_clk2 abe and clock division factor tx_serial_clk3 tx_serial_clk4 ix pma_clkout Output Clock This is the low speed parallel clock from the TX PMA It is available when you turn on Enable tx_pma_clkout port in th
491. rt Network Data Link Physical Altera Corporation LAN CSMA CD LAYERS Higher Layers LLC Logical Link Control or other MAC Client a MAC Control Optional Media Access Control MAC re Reconciliation PCS PHY a ENA Sublayers PMD MDI Medium r 1 Gbps Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 8B 10B Encoding for GbE GbE with 1588 2 81 Figure 2 26 Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE GbE with 1588 Transmitter PMA Transmitter Standard PCS FPGA Fabric n 10 amp g 16 PRBS 625 MHz Generator tx_coreclkin a 125MHz tx clkout L ji J 4 125 MHz lt lt 12 tx_pma_div_clkout ouch Receiver PMA Receiver Standard PCS e 2 2 F 10 E z 8 16 8 8 a a 8 aul zD S hE p oe or Le y g 3 a 8 8 E B rx_coreclkin Parallel Clock l Recovered rx_clkout l l 125 MHz tx_clkout i 125 MHz Parallel Clock U n rx_clkout or From Clock PRBS tx_clkou
492. rt tx_digitalreset tx_digitalreset 3f f 00 tx_enh_data_valid 00 3f p 00 tx enh fifo full _00 F 3f tx_enh_fifo_pfull _00 E 3f tx_enh_fifo empty _3f Fa 00 tx_enh_fifo_pempty _3f Fi 7 tx_enh_fifo_cnt _ 000000 rd Ya 2 3 14 5 X6 A7 18 19 a b Ac Ad Jle L ffffff tx_enh_frame _00 r 3t 00 tx_enh_frame_burst_en _00 Deassert burst_en for all Lanes and Fill TX FIFO Until all Lane FIFOs Are Full After the TX FIFO pre fill stage completes the transmit lanes are synchronized and the MAC layer can begin to send valid data to the transceiver s TX FIFO You must never allow the TX FIFO to overflow or underflow If it does you must reset the transceiver and repeat the TX FIFO pre fill stage For a single lane Interlaken implementation TX FIFO soft bonding is not required You can begin sending an Interlaken word to the TX FIFO after the deassertion of tx_digitalreset The following figure shows the MAC layer sending valid data to the Native PHY after the pre fill stage tx_enh_frame_burst_en is asserted allowing the frame generator to read data from the TX FIFO The TX MAC layer can now control tx_enh_data_valid to write data to the TX FIFO based on the FIFO status signals Figure 2 18 MAC Sending Valid Data tx_digitalreset 00 tx_enh_data_valid 00 sf X00 tx_enh fifo_full 3 o0 F tx_enh_fifo_pfull 3 00 i JEH tx_enh_
493. rted e Manual The associated tx_digital_ reset controller is not reset when the p11_ locked signal is deasserted allowing you to choose corrective action e Expose Port The tx_manual signal is atop level signal of the IP Core You can dynamically change this port to AUTO or Manual 1 Manual 0 AUTO tx_digitalreset duration 1 999999909 Specifies the time in ns to continue to assert the tx_digitalreset after the reset input and all other gating conditions are removed The value is rounded up to the nearest clock cycle The default value is 20 ns pll_locked input hysteresis 1 999999999 Specifies the amount of hysteresis in ns to add to the pl11_locked status input to filter spurious unreliable assertions of the p11_locked signal A value of 0 adds no hysteresis A higher value filters glitches on the p11_locked signal RX Channel Enable RX channel reset control On Off When On the Transceiver PHY Reset Controller enables the control logic and associated status signals for RX reset When Off disables RX reset control and status signals Use separate RX reset per channel On Off When On each RX channel has a separate reset input When Off uses a shared RX reset controller for all channels Resetting Transceiver Channels CJ Send Feedback Altera Corporation 4 12 Transceiver PHY Reset Controller Interfaces RX digital reset mode Auto Manual Expose Port UG A1
494. rtially full and empty thresholds can also be set through the Transceiver and PLL Address Map Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details The TX FIFO supports the following operating modes e Phase Compensation mode e Register mode e Interlaken mode e Basic mode Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 6 1 Phase Compensation Mode In Phase Compensation mode the TX FIFO decouples phase variations between the FPGA fabric and transceiver clock domains In this mode the TX FIFO compensates for the phase difference between the read and write clocks You can use t x_coreclkin FPGA fabric clock or tx_clkout TX parallel low speed clock to clock the write side of the TX FIFO tx_clkout clocks the read side of the TX FIFO Note The TX FIFO write clock frequency and read clock frequency depend on the gearbox ratio tx_enh_data_valid control signal For example when using the 40 40 gearbox ratio and a data rate of 10 Gbps the tx_clkout frequency is 250 MHzand the tx_corecl1kin frequency is 250 MHz The tx_clkout frequency is 257 8125 MHz in 1OGBASE R mode when using the 66 40 gearbox ratio tx_coreclkin must run at 156 25 MHz Note Phase Compensation can also be used in double width mode where the FPGA fabric data width is doubled to allow the FPGA fabric clock to run at half rate The single double width mode is set in the Native PHY MegaWizard Re
495. rule violations error E Library Device speed grade fastest D PCle Gen1 and Gen2 Multi Lane 1C Aasi conduit _hssi_serial_clock m Protocol mode Basic B Ly PCle Gen1 and Genz Single Lane 1 loirerciko _ Bandwidth medium fi D PCle Gen3 Multi Lane 100Mhz Number of PLL reference clocks 1 R PCle Gens single Lane 100Mhz altera_xcvr_atx_pll Selected reference clock source g E Ports Primary PLL clock output buffer GT clock output buffer GX clock output buffer GT clock output buffer Enable PLL GX clock output p Mi Enable PLL GT clock output po Enable PCle clock output port Output Frequency PLL output frequency 14000 0 MHz PLL reference clock frequency 700 0 v MHz Multiply factor M Counter 40 Divide factor N Counter 4 Divide factor L Counter i PAE E gt A Warning ATXPLL This IP core is in beta stage IP ports and parameters are subject to change EDA Options Cancel Finish 6 Create a transceiver reset controller Refer to Resetting Transceiver Channels on page 4 1 for more details about configuring the reset IP 7 Connect the Native PHY IP to the PLL IP and the reset controller e The ATX PLL s port tx_serial_clk_gt represents the dedicated GT clock lines Connect this port to the Native PHY IP s tx_serial_c1k0 port Quartus II software will automaticall
496. s The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators e ModelSim SE e Synopsys VCS MX e Cadence NCSim If you select VHDL for your transceiver PHY only the wrapper generated by the Quartus II software is in VHDL All the underlying files are written in Verilog or System Verilog To enable simulation using a VHDL only ModelSim license the underlying Verilog and System Verilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top level VHDL wrapper without using a mixed language simulator For more information about simulating with ModelSim refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Handbook The Transceiver Native PHY IP cores do not support the NativeLink feature in the Quartus II software Related Information e Mentor Graphics ModelSim Support e Simulating the Transceiver Native PHY IP Core on page 2 256 Interlaken Altera Corporation Interlaken is a scalable channelized chip to chip interconnect protocol The key advantages of Interlaken are scalability and its low I O count compared to earlier protocols such as SPI 4 2 Other key features include flow control low overhead framing and extensive integrity checking Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Interlaken 2 63 Interlaken operates on 64 bit data words and 3 control bits whi
497. s The reconfiguration interface ports are bundled together The 32 bit wide ports are grouped into 32 bit groups The 1 bit ports are grouped into 1 bit groups For example a two channel Native PHY IP instance address bus would be reconfig_address 63 0 and the reconfiguration clock would be reconfig_clk 1 0 For the address bus the channel 0 reconfiguration address would comprise of reconfig_address 31 0 Channel 1 reconfiguration address would comprise of reconfig_address 63 32 For the reconfiguration clock channel 0 s reconfiguration clock would be reconfig_clk 0 and channel 1 reconfiguration clock would be reconfig_clk 1 The same bundling pattern applies to channel counts greater than two Table 6 1 Reconfiguration Interface Ports with Share Reconfiguration Interface Disabled The following table lists the reconfiguration interface ports when Shared reconfiguration interface option is disabled N equals the number of channels in the felons table reconfig_clk lt N gt Input Avalon clock The preliminary clock frequency is 70 100 MHz to 125 MHz reconfig_reset lt N gt Input reconfig_ Resets the Avalon interface le elik reconfig_write lt N gt Input reconfig_ Write enable signal Signal is active high LEO clk reconfig_read lt N gt Input reconfig_ Read enable signal Signal is active high 1 0 cti reconfig_ Input reconfig_ The lower 10 bits are the address lines The up
498. s the following bits are active e 32 bit FPGA fabric IF width data 95 64 Unused e 40 bit FPGA fabric IF width data 103 64 Unused e 50 bit FPGA fabric IF width data 113 64 remaining 127 114 unused e 64 bit FPGA fabric IF width data 127 64 unused_rx_ Output rx_clkout This signal specifies the unused data when you turn on parallel_data Enable simplified data interface Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2013 12 02 rx_control lt n gt Output r Indicates whether the rx_parallel_data busis control lt 20 gt 1 0 coreclkin or data Defined for the following configurations 2 44 Enhanced PCS and PMA Ports e Interlaken With Enable simplified interface on e 19 10 Unused e 9 When 1 b1 indicates that block lock and frame lock have been achieved e 8 When 1 b1 indicates a synchronization header error Metaframe error or CRC32 error e 7 When 1 b1 indicates the Diagnostic Word location within a Metaframe e 6 When 1 b1 indicates the SKIP Word location with a Metaframe e 5 When 1 b1 indicates the Scrambler State Word location in a Metaframe e 4 When 1b l indicates the Synchronization Word location in a Metaframe e 3 When 1b l indicates the Payload Word location in a Metaframe e 2 Inversion bit In the current implementation this bit is always 0 e 1 Synchronization header 1 indi
499. s 8 Bits tx_parallel_data 20 h3FC3BC and the word aligner pattern 0x3BC mX_std_wa_patternalign tx_parallel_data _bc rX_parallel_data 00 be rX_patterndetect rx_syncstatus X_std_wa_patternalign tx_parallel_data bc rx_parallel_data bc rx_patterndetect rx_syncstatus Figure 2 103 Manual Mode when the PCS PMA Interface Width is 10 Bits tx_parallel_data 20 h3FC3BC and the word aligner pattern 0x3BC rx_std_wa_patternalign tx_parallel_data 3bc rx_parallel_data 000 3bc rx_patterndetect rx_syncstatus rx_std_wa_patternalign tx_parallel_data 3bc rx_parallel_data 3bc rx_patterndetect rx_syncstatus Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Word Aligner Synchronous State Machine Mode 2 235 Figure 2 104 Manual Mode when the PCS PMA Interface Width is 16 Bits tx_parallel_data 20 h3FC3BC and the word aligner pattern 0x3BC rx_std_wa_patternalign tx_parallel_data f3bc rx_parallel_data _0000 f3bc rx_patterndetect _00 01 rx_syncstatus _00 i1 janl rx_std_wa_patternalign tx_parallel_data f3bc rx_parallel_data _f3bc m_patterndetect 01 rx_syncstatus 11 X00 y11 Figure 2 105 Manual Mode when the PCS PMA
500. s GXBLIE GXBLIF GXBL1G and GXBL1H include GT channels Clock Six Channel GT Transceiver Bank Distribution Network Channel PLL CDR Only Local CGB5 lt _ fPLL1 Pcs Channel PLL CMU CDR Local CGB4 Master af CGB1 Channel PLL CDR Only Local CGB3 ATX PLL1 Channel PLL E CDR Only Local CGB2 fPLLO Channel PLL CMU CDR Local CGB1 Master Jy CGBO Channel PLL CDR Only Local CGBO ATX PLLO FPGA Core Fabric Legend E GT GX Channel J GX Channel The transceiver channels perform all the required PHY layer functions between the FPGA fabric and the physical medium The high speed clock required by the transceiver channels is generated by the transceiver PLLs The master and local clock generation blocks CGBs provide the necessary high speed serial and low speed parallel clocks to drive the non bonded and bonded channels in the transceiver bank Related Information Transceiver Basics Online training course for transceivers PHY Layer Transceiver Components Transceivers in Arria 10 devices support both Physical Medium Attachment PMA and Physical Coding Sublayer PCS functions at the physical PHY layer Arria 10 Transceiver PHY Overview CJ Send Feedback Altera Corporation UG A10XCVR 1 18 The GX Transceiver Channel 2013 12 02
501. s on page 3 40 For more information about implementing PLLs and clocks PLL Feedback Compensation Clock Bonding Scenario In the following figure each lane is running at 12 5 Gbps The first six TX channels reside in one transceiver bank and the other four TX channels reside in the adjacent transceiver bank The difference between feedback compensation bonding and xN bonding is that feedback compensation bonding separates the TX channels into multiple bonding groups each group being driven by a separate x6 clock network In feedback compensation bonding the separate x6 clocks are in phase and frequency aligned with each other One PLL from each transceiver bank drives the clock to master CGB and then drives these clocks to TX channels that reside in the same bank only In xN bonding all channels are driven by the xN clock network The data rate decrease imposed by xN bonding does not apply to PLL feedback compensation bonding Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 The feedback to the PLL for each bonded group is the parallel clock from the master CGB which has the same frequency as tx_clkout The reference clock for the PLL must match the frequency of this feedback clock For example given that the Interlaken interface runs at 12 5Gbps per lane and PCS PMA width is TX Multi Lane Bonding and RX Multi Lane Deskew Alignment State Machine 40 bits the only available frequen
502. sceiver channel and PLL contains an Avalon Memory Mapped Avalon MM reconfiguration interface The reconfiguration interface provides direct access to the programmable space of each channel and PLL Because each channel and PLL has its own dedicated Avalon interface you can dynamically modify channels either concurrently or sequentially depending upon how the Avalon master is connected to the Avalon interface Communication with the channel and PLL reconfiguration interface requires an Avalon compliant master This chapter provides complete information about using the reconfiguration interface Related Information e Interacting with the Reconfiguration Interface on page 6 4 e Reconfiguring Channel and PLL Blocks on page 6 5 e Switching Reference Clocks on page 6 10 e Transmitter PLL Switching on page 6 9 e Changing PMA Analog Parameters on page 6 13 e Using Data Pattern Generators and Checkers on page 6 13 Ports and Parameters The reconfiguration interface is integrated into the Native PHY instance and TX PLL The following table lists the ports and parameters available for the Avalon Interface You can define parameters for IP components by clicking Tools gt MegaWizard Plug In Manager Dynamic reconfiguration is available for the Arria 10 Transceiver Native PHY fPLL ATX PLL and the CMU PLL IP cores To expose the ports of the reconfiguration interface enable the Enable reconfiguration option when parameterizing the IP core Each tran
503. sceiver channels that can support data rates up to 17 4 Gbps for chip to chip applications and 16 0 Gbps for backplane applications The Arria 10 GT devices have up to 16 GT transceiver channels that can support data rates up to 28 1 Gbps for short reach chip to chip and chip to module applications Additionally the GT devices have GX transceiver channels that can support data rates up to 17 4 Gbps for both chip to chip and backplane applications If all 16 GT channels are used then the largest GT devices can have up to 72 GX transceiver channels The Arria 10 transceivers support reduced power modes with data rates up to 11 3 Gbps chip to chip and 10 3125 Gbps backplane for critical power sensitive designs In GX devices that have transceivers on both sides of the device each side can be operated independently in standard and reduced power modes Table 1 1 Data Rates Supported by GX Transceiver Channel Type Device Standard Power Mode Reduced Power Mode Variant Chip to Chip Backplane Chip to Chip Backplane sx 2 611 Mbps to 17 4 Gbps 611 Mbps to 16 0 Gbps 611 Mbps to 11 3 Gbps 611 Mbps to 10 3125 Gbps Gx 611 Mbps to 17 4 Gbps 611 Mbps to 16 0 Gbps 611 Mbps to 11 3 Gbps 611 Mbps to 10 3125 Gbps gt 611 Mbps to 17 4 Gbps 611 Mbps to 17 4 Gbps 611 Mbps to 11 3 Gbps 611 Mbps to 10 3125 Gbps 1 To operate GX transceiver channels at designated data rates in standard and reduced power modes apply the corresp
504. sceivers for 1OGBASE R functionality by using the Native PHY IP to implement the PHY layer of the 1OGBASE R Transceiver Configuration Rule The Native PHY IP must be connected to a third party PHY MAC layer to create a complete 1OGBASE R design 10GBASE R with 1588 Arria 10 transceivers can implement the 1OGBASE R 1588 protocol using the 1OGBASE R 1588 Transceiver Configuration Rules The IEEE 1588 Precision Time Protocol is used for precise synchronization of clocks in distributed systems in telecommunications power generation and distribution industrial automation robotics data acquisition test and measurement The protocol is applicable to systems communicating by local area networks including but not limited to Ethernet The protocol enables heterogeneous systems that include clocks of various inherent precision resolution and stability to synchronize to a grandmaster clock The LOGBASE R 1588 protocol mode supports a lane rate of 10 3125 Gbps The PCS sublayer interfaces with the MAC through the gigabit medium independent interface GMII Use the Native PHY IP to implement the PHY Layer of the 1OGBASE R 1588 protocol The Native PHY IP must be connected to a third party PHY MAC layer to create a complete 1OGBASE R 1588 design 10GBASE R with KR FEC The 1OGBASE R with KR FEC protocol is a KR FEC sublayer placed between the PCS and PMA sublayers of the 1OGBASE R physical layer The Open Systems Interconnection OSI reference mo
505. scessssessssseseanscnsvudespssuacousasssssvssbocdec 2 198 Native PHY IP Ports for PCI Px press ccccscsstresnsaincinucisentgeeaeneidanceavewaeiciseeasence 2 204 How to Place Channels for PIPE Cotifi guration s scicssssincosstsctacscsctraricsiczeassncascamssindiotenrinaseaecs 2 212 Design Te A LG ove secazeseisasbeasenstebanstnacars oriescnnadicsaeh expe peviviateamabiaaspmeean a AKASAKA Sa aurea 2 215 lE A d E cvs ss fuss subse dinate ces susesvsussuscoi E EE EEE E RA ccatessss 2 216 Transceiver Channel Datapath and Clocking for CPRI csssssssesessseseesssssssssssesseesessseses 2 216 Supported Features for GPRD sca5sonccseciseds cep eect ccepecaperseatisaeiin lieu eneememaraame 2 218 Word Aligner in Manual Mode for CPR scssciasicccieseidl iccudsstansationsdecnestraatoiaaedesunceitalavertics 2 219 How to Implement CPRI in Arria 10 Transceivers e seeesseseeesrtesssserisrrsestestesrresrrssrrsseesees 2 220 Native PHY IP Parameter Settings for CPRI sseeessseeesssseeesssssresssrtesssstresssrrtesseeressnrreesnereree 2 222 Other DRCOG passa snssrisireesnsrioneersss iira eninitti otsite vt E Er ESEESE T EREDE E CARPERE EA EVERE E ANENE DEESA AEN RERE 2 225 Using the Basic and Basic with KR FEC Configurations of Enhanced PCS 2 225 Using the Basic Custom Basic Custom with Rate Match Configurations of Standard I O P ET 2 232 Altera Corporation TOC 4 Arria 10 Transceiver PHY User Guide Design Considerations for Data Rates Ab
506. sic 10 e Basic e Basic rate match e CPRI e PCIe Genl and Gen2 e GigE Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 Word Aligner Pattern Length for Various Word Aligner Modes 5 39 16 Basic 20 e CPRI e Basic e Basic rate match Word Aligner Pattern Length for Various Word Aligner Modes Table 5 8 Word Aligner Pattern Length for Various Word Aligner Modes PCS PMA Supported SupportedWord rx_std_wa_ rx_syncstatus rx_patterndetect Interface Width Word Aligner Aligner Pattern patternalign behavior behavior Modes Lengths behavior Bit slip 7 N A N A N A Manual 8 16 Rising Edge Asserted high for Asserted high for one Sensitive one parallel clock parallel clock cycle 8 cycle when the when the word word aligner aligns alignment pattern to a new boundary appears in the current word boundary Bit slip 7 N A N A N A Manual 7 10 Level Sensitive Asserted high for Asserted high for one one parallel clock parallel clock cycle cycle when the when the word word aligner aligns alignment pattern to a new boundary appears in the current word boundary Deterministic 10 10 latency CPRI mode only Synchronous 7 10 N A Stays high as long as Asserted high for one State the synchronization parallel clock cycle Machine conditions are when the word satisfied alignment pattern appears in the current word
507. smit PLL and channel has a dedicated reconfiguration interface The transmit PLL instance has a maximum of one reconfiguration interface Unlike the PLL instance the Native PHY instance can specify 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134 6 2 Ports and Parameters UG A10XCVR 2013 12 02 multiple channels For example a two channel Channel 0 and Channel 1 design would contain two reconfiguration interface
508. smitter channel In a non bonded channel configuration only the serial clock is routed to the transmitter channel and the parallel clock is generated locally within the channel To support various bonded and non bonded clocking configurations 4 types of transmitter clock network lines are available e xl Clock Lines e x6 Clock Lines e xN Clock Lines e GT Clock Lines x1 Clock Lines The x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiver bank The low speed parallel clock is then generated by that particular channel s local clock generation block CGB Non bonded channel configurations use the x1 clock network The x1 clock lines can be driven by the ATX PLL fPLL or by either one of the two channel PLLs Channel 1 and 4 when used as a CMU PLL within a transceiver bank The channel PLL of channel 1 and channel 4 can be configured in CMU mode in order to act as a transmit PLL When the channel PLL of channel 1 and channel 4 is configured in the CMU mode it can drive the local CGB of its own channel However because the CDR block is used as a transmit PLL it is not available for clock and data recovery functions and the channel can only be used as a transmitter channel The x1 clock lines are also used to drive the master CGB in bonded channel configurations Either one of the master CGB in each transceiver bank can drive the x6 clock lines for bonded channel configurations The master CGB ca
509. source Utilization 2 151 m Deon Vendor ID 6AF7 1G 10GbE PHY Performance and Resource Utilization This topic provides performance and resource utilization for the 1G 10GbE PHY IP core in Arria 10 devices The following table shows the typical expected resource utilization for selected configurations using the Quartus II software Arria 10 Edition v13 1 The numbers of ALMs and logic registers are rounded up to the nearest 100 Table 2 105 1G 10GbE PHY Performance and Resource Utilization 1G 10GbE PHY with 1588 2950 3900 4950 5 1G 10GbE PHY 750 1100 1300 2 1G 10GbE PHY with FEC 750 1100 1300 2 Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 1G 10GbE PHY Functional Description 2013 12 02 1G 10GbE PHY Functional Description Figure 2 59 10G 10GbE PHY Block Diagram Sequencer Auto Speed Detect Reconfiguration Block GigE PCS E Native PHY 40 32 1588 t Standard TX PCS o3 oe TX PMA po p gt tx_pld_clk tx_pma_clk Auto Negotiation Clause 73 L Enhanced TX PCS Link Training Clause 72 phtx pld clk tx_pma_clk a FIFO Standard RX PCS Bf gt rx_pld_clk rx_pma_clk GigE Enhanced RX PCS 40 32 PCS RX PMA Prx_pld_clk rx_pma_clk Divide by 33 1 2 _ E Soft Logic Hard Logic _ Not
510. sting that training continue Values for the receiver ready bit are defined in Clause 72 6 10 2 4 4 For more information refer to For more information refer to bit 10G BASE KRLD status report register bit 1 155 15 in Clause 45 2 1 81 of IEEE 802 3ap 2007 21 16 RO or RW LP coefficient update 5 0 Reflects the contents of the first 16 bit word of the training frame most recently received from the control channel Normally the bits in this register are read only however when training is disabled by setting low the KR Training enable control bit these bits become writeable The following fields are defined e 5 4 Coefficient 1 update e 2 b11 Reserved e 2 b01 Increment e 2 b10 Decrement e 2 b00 Hold e 3 2 Coefficient 0 update same encoding as 5 4 e 1 0 Coefficient 1 update same encoding as 5 4 For more information refer to bit 10G BASE KR LP coefficient update register bits 1 152 5 0 in Clause 45 2 1 78 3 of IEEE 802 3ap 2007 22 RO or RW LP Initialize Coefficients When set to 1 the local device transmit equalizer coefficients are set to the INITIALIZE state When set to 0 normal operation continues The function and values of the initialize bit are defined in Clause 72 6 10 2 3 2 For more information refer to bit 1OG BASE KR LP coefficient update register bits 1 152 12 in Clause 45 2 1 78 3 of IEEE 802 3ap 2007 23 RO or RW LP Preset Coefficients
511. sts a rate change through pipe_rate 1 0 2 The ASN block waits for Phase compensation FIFO to flush out data Then ASN block asserts the PCS reset 3 The ASN asserts clock shutdown signal to 8G PCS and Gen3 PCS to dynamically shutdown the clock 4 The ASN asserts the clock and data multiplexer selection signals This is performed only when rate changes from or to Gen3 speed 5 The ASN sends rate change request to PMA This is done through pipe_sw 1 0 output signal Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Gen3 Transmitter Electrical IDLE Generation 2 189 6 The ASN waits for rate change done from PMA This is done through continuously monitoring the pipe_sw_done 1 0 input signal 7 After the ASN receives pipe_sw_done it deasserts the clock shut down signals to release the clock The ASN deasserts the PCS reset 9 The ASN sends the speed change completion to PHY MAC interface This is done through the pipe_phy_status signal to PHY MAC interface 0e Figure 2 74 Speed Change Sequence pipe_tx_elecidle pipe_rate 1 0 00 10 pipe_sw 1 0 00 10 pipe_sw_done 1 0 00 10 pipe_phy_status Gen3 Transmitter Electrical IDLE Generation In the PIPE 3 0 based interface the user may place the transmitter in electrical idle during low power states Before the transmitter enters electrical idle the user must send
512. sys Design Constraint SDC for the reset signals to guarantee that your design meets timing The Quartus II software generates an sdc file when you generate the Transceiver Native PHY IP This sdc contains constraints for setting the maximum skew and false paths This constraint accounts for the skew introduced by routing delays inherent within the FPGA This skew is present whether you tie alltx_digitalresets together or you control them separately If your design includes the Transceiver PHY Reset Controller IP core you can substitute your instance and interface names for the generic names shown in the example Example 4 1 SDC Constraint for TX Digital Reset When Bonded Clocks Are Used set_max_skew from lt IP_INSTANCE_NAME gt tx_digitalreset r_reset to pld_pcs_interface lt 1 2 coreclk period in ps gt In the above example you must make the following substitutions e lt IP_INSTANCE_NAME gt substitute the name of your reset controller IP instance or PHY IP instance e lt coreclk period in ps gt substitute the the clock period of your design in picoseconds If your design has custom reset logic replace the lt IP_INSTANCE_NAME gt tx_digital reset r_reset with the source register for the TX PCS reset signal tx_digitalreset For more information about the set_max_skew constraint refer to the SDC and Time Quest API Reference Manual Related Information SDC and TimeQuest API Reference Manual Resetting Transcei
513. t rx_analog_reset _ rx_digital_reset rx_clkout gt rx_clkout rx_coreclkin rx_coreclkin gt CDR rx_parallel_data 127 0 gt rx_parallel_data 127 0 gt rx_control 19 0 gt rx_control 19 0 A refclk 5 Instantiate and configure your PLL 6 Create a transceiver reset controller You can use your own reset controller or use the Altera Transceiver PHY Reset Controller IP 7 Connect the Native PHY IP to the PLL IP and the reset controller Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Implement the Basic Enhanced PCS and Basic with KR FEC Transceiver Configuration Rules in Arria 10 2 229 Transceivers Figure 2 98 Connection Guidelines for a Basic Enhanced PCS Transceiver Design gt Reset PLL IP 4 Controller Design 32 bit data Testbench 32 32 I t gearbox ratio Arria 10 Transceiver 4 Native PHY Figure 2 99 Connection Guidelines for a Basic with KR FEC Transceiver Design PLL IP Reset 1 Controller Design Testbench I T 64d 8c Arria 10 Transceiver _ Native PHY 8 Simulate your design to verify its functionality Related Information e Arria 10 Enhanced PCS Architecture on page 5 14 For more information about Enhanced PCS architecture e Arria 10 PMA Architectur
514. t Divider Verifier rx_pma_div_clkout 625 MHz Clock Generation Block CGB ATX PLL Clock Divider lt a CMU PLL fPLL Parallel Clock Serial Clock Serial Clock Notes Parallel and Serial Clock 1 This block is set in low latency mode for GbE and register_fifo mode for GbE with 1588 2 Rate match FIFO is disabled for GbE with 1588 Parallel and Serial Clock Note The transceivers do not have built in support for other PCS functions for example the auto negotiation state machine collision detect and carrier sense If required you must implement these functions in the FPGA fabric or external circuits GbE with 1588 GbE with 1588 provides a standard method to synchronize devices on a network with submicrosecond precision To improve performance the protocol synchronizes slave clocks to a master clock so that events and time stamps are synchronized in all devices The protocol enables heterogeneous systems that include clocks of various inherent precision resolution and stability to synchronize to a grandmaster clock 8B 10B Encoding for GbE GbE with 1588 Implementing Protocols in Arria 10 Transceivers The 8B 10B encoder clocks 8 bit data and 1 bit control identifiers from the transmitter phase compensation FIFO and generates 10 bit encoded data The 10 bit encoded data is sent to the PMA The IEEE 802 3 specification requires GbE to transmit idle ordered sets I continuously and repetitively whenev
515. t S5 C s8 De Ds v PRBS Error The PRBS verifier has the following control and status signals available to the FPGA fabric e rx_prbs_done lIndicates the PRBS sequence has completed one full cycle It stays high until you reset it with rx_prbs_err_clr e xrx_prbs_err Goes high if an error occurs This signal is pulse extended to allow you to capture it in the RX FPGA CLK domain e rx_prbs_err_clr Used to reset the rx_prbs_err signal The Enhanced RX datapath does not include a verifier for the square wave Enable the PRBS verifier control and status ports through the Native PHY IP MegaWizard in the Quartus II software The PRBS pattern is automatically selected to match the PRBS generator pattern that you selected The Transceiver and PLL Address Map can be used to enable or disable PRBS verifier Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 26 PRP Verifier 2013 12 02 PRP Verifier The Pseudo Random Pattern PRP verifier is available for 1OGBASE R and 10GBASE R 1588 protocol modes The PRP verifier monitors the output of the descrambler when block synchronization is achieved The PRP verifier e Searches for a test pattern two local faults or all 0s or its inverse e Tracks the number of mismatches with a 16 bit error counter Figure 5 33 PRP Verifier Error Counter error_cou
516. t mii_rx_err Output Synchronous to When asserted it indicates an error in the frame rx_pma_ clkout mii_rx_clkena Output Clock signal MII RX clock enable This clock frequency has the following frequencies e 25 MHz For an effective rate of 100 Mbps e 2 5 MHz For an effective rate of 10 Mbps mii_rx_clkena__ Output Clock signal MII RX clock enable when the FPGA fabric runs at half_rate half the PCS frequency This clock frequency has the following frequencies e 12 5 MHz For an effective rate of 100 Mbps e 1 25 MHz For an effective rate of 10 Mbps mii_speed_ Output Asynchronous Specifies the SGMII 4 speed mode The following sel 1 0 signal encodings are defined e 2b 00 10 Gbps e 2 b01 1 Gbps e 2 b10 100 Mbps e 2 b11 10 Mbps XGMII Mapping to Standard SDR XGMII Data The 72 bit TX XGMII data bus format is different than the standard SDR XGMII interface The following table shows the mapping of this non standard format to the standard SDR XGMII interface Table 2 114 TX XGMII Mapping to Standard SDR XGMII Interface xgmii_tx_dc 7 0 xgmii_sdr_data 7 0 Lane 0 data xgmii_tx_dc 8 xgmii_sdr_ctrl1 0 Lane 0 control xgmii_tx_dc 16 9 xgmii_sdr_ Lane 1 data data 15 8 zomi tx delly xgmii_sdr_ctrl 1 Lane1 control xgmii_tx_dc 25 18 xgmii_sdr_ Lane 2 data data 23 16 Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 164 XGMII Mappi
517. t Off Enable rx_set_locktodata and rx_set_locktoref ports Off Enable rx_seriallpbken port Off Enable PRBS verifier control and status ports Off Table 2 138 Standard PCS Parameters Parameters VEIG Standard PCS PMA interface width 10 20 Enable Standard PCS low latency mode off TX FIFO mode register_fifo RX FIFO Mode register_fifo Enable tx_std_pcfifo_full port off Enable tx_std_pcfifo_empty port off Enable rx_std_pcfifo_full off Enable rx_std_pcfifo_empty port off TX byte serializer mode Disabled Serialize x2 RX byte deserializer mode Disabled Deserialize x2 Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 224 Native PHY IP Parameter Settings for CPRI 2013 12 02 Enable TX 8B 10B encoder On Enable TX 8B 10B disparity control Off Enable RX 8B 10B decoder On RX rate match FIFO mode Disabled RX rate match insert delete ve pattern hex 0x00000000 RX rate match insert delete ve pattern hex 0x00000000 Enable rx_std_rmfifo_full port Off Enable rx_std_rmfifo_empty port Off PCI Express Gen 3 rate match FIFO mode Bypass Enable TX bit slip On Enable tx_std_bitslipboundarysel port On RX word aligner mode Deterministic latency CPRI Auto configuration e Manual PLD controlled CPRI Manual configuration RX word aligner pattern length 10 RX word aligner pat
518. t n gt 1 0 EX coreclkin Output Synchronous to Active high This signal indicates when the TX FIFO reaches its partially full threshold ta emm ELEG empty lt n gt 1 0 Output Asynchronous When asserted indicates that the TX FIFO is empty tx_enh_fifo_ pempty lt n gt 1 0 Output Asynchronous Active high When asserted indicates that the TX FIFO has reached its specified partially empty threshold When you turn this option on the Enhanced PCS enables the tx_enh_fifo_ pempty port which is asynchronous T emn EEO Gime lt ime 1 20 Output txvelkout Indicates the current level of the TX FIFO Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 48 Enhanced PCS and PMA Ports Table 2 35 Enhanced PCS RX FIFO UG A10XCVR 2013 12 02 rx_enh_fifo_rd_en lt n gt Input For Interlaken only when this signal is 120 eae asserted a word is read form the RX FIFO You need to control this signal based on RX FIFO flags so that the FIFO won t underflow or overflow rx_enh_data_valid lt n gt Output rx_ When asserted indicates that rx_ 130 coreclkin parallel_data is valid For basic mode the rx_enh_data_valid signal toggles indicating valid RX data when the RX FIFO is in Phase compensation or Register mode This option is available when you select the following parameters e Enhanced PCS Transceiver co
519. t_writedata 31 0 mgmt_readdata 31 0 mgmt_write mgmt_read mgmt_waitrequest tx_serial_clk_1g rx_cdr_ref_clk_10g rx_cdr_ref_clk_1g tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_an_lIt_reset usr_seq_reset rx_serial_data tx_serial_data mode_1ig_10gbar rc_busy start_pcs_reconfig led_char_err led_link led_disp_err led_an rx_block_lock rx_hi_ber rx_is_lockedtodata tx_cal_busy rx_cal_busy calc_clk_1g rx_syncstatus tx_pcfifo_error_1g tx_pcfifo_error_1g Icl_rf tm_in_trigger 3 0 tm_out_trigger 3 0 rx_rlv rx_clkslip rx_latency_adj_1g 11 0 tx_latency_adj_1g 11 0 rx_latency_adj_10g 11 0 tx_latency_adj_10g 11 0 rx_data_ready 4 Transceiver gt Serial Data lt gt Recontigurati econfiguration lt _ m Status The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box The interface type and name are used in the _hw tcl file If you turn on Show signals the block diagram displays all top level signal names For more information about _hw tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook Note Some of the signals shown in are this figure are unused and will be removed in a future release The descriptions of these identifies them as not func
520. ta excluding synchroniza tion header e 17 9 Unused Ground unused_tx_ Input X concro llki iE coreclkin Leo Port is enabled when you enable Enable simplified interface Connect all of these bits to 0 Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Enhanced PCS and PMA Ports 2 41 tx_err_ins Input Cee For the Interlaken protocol you can use this bit to insert sync header and CRC32 errors if you have turned on Enable simplified interface When asserted the sync header for that cycle word is replaced with a corrupted one A CRC32 error is also inserted if Enable Interlaken TX CRC 32 generator error insertion is turned on The corrupted sync header is 2 b00 for a control word and 2 b11 for a data word For CRC32 error insertion the word used for CRC calculation for that cycle is incorrectly inverted causing an incorrect CRC32 in the Diagnostic Word of the Metaframe Note that a sync header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS Both the sync header error and the CRC32 errors are inserted if the CRC 32 error insertion feature is enabled in the Transceiver Native PHY IP GUI tx_coreclkin Input Clock The FPGA fabric clock Drives the write side of the TX FIFO For the Interlaken protocol the frequenc
521. taSim Support Synopsys VCS and VCS MX Support Cadence Incisive Enterprise Simulator Support Aldec Active HDL and Riviera Pro Support Custom Simulation Flow The custom simulation flow allows you to customize the simulation process for more complex simulation requirements This flow allows you to control the following aspects of your design Component binding Compilation order Run commands IP cores Simulation library model files The following figure illustrates the steps for custom flow simulation If you use a simulation script you can automate some of the steps Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 How to Use the Simulation Library Compiler 2 261 Figure 2 136 Custom flow Simulation Compile Sim Model Libs Using Sim Lib Compiler y Start Simulator amp Open Quartus II Project y Compile Design Testbench amp Simulation Libraries y Load Design amp Run Simulation Simulation Give Expected Results No y gt Debug Design amp Make RTL Changes y Compile Design Testbench amp Simulation Libraries Yy Load Design amp Run Simulation Simulation Give Expected Results Simulation Complete How to Use the Simulation Library Compiler The Simulation Library Compiler compiles Altera simulation libraries for supported simulation too
522. ta_valid rx_enh_fifo_pfull rx_enh_fifo_pempty rx_enh_frame_lock 5 Each Lane Is Frame Locked in a Different 2 Cycle 1 rx_enh_fifo_align_val rx_enh_fifo_align_clr After deskew is successful the user logic asserts rd_en for all lanes to start reading data from the RX FIFO 00 3f Ie Y 0 00 casani 00 BEE 00 3f te OOO 000000 Y10 1 00 21 Y 3f 00 How to Implement Interlaken in Arria 10 Transceivers Before you begin 2 71 data_valid is asserted indicating that the RX FIFO is outputting valid data Deassertion of pempty of all lanes before any lane pfull goes high which means the deskew is completed You should be familiar with the Interlaken protocol Enhanced PCS and PMA architecture PLL architecture and the reset controller before implementing the Interlaken protocol PHY layer 1 Open the MegaWizard Plug In Manager and select the Arria 10 Transceiver Native PHY IP Refer to Select and Instantiate PHY IP on page 2 2 for more details 2 Select Interlaken from the Transceiver configuration rules list located under Datapath Options 3 Use the parameter values in the tablesin Native PHY IP Parameter Settings for Interlaken as a starting point Or you can use the protocol presets described in Preset Configuration Options You can then modify the settings to meet your specific requirem
523. tage Controller Oscillator VCO The VCO used in ATX PLL is LC Tank based The output of the charge pump and the loop filter serve as an input to the VCO The output frequency of the VCO depends on the input control voltage The output frequency is adjusted based on the output voltage of the charge pump and loop filter Each ATX PLL has three LC tank circuits and each tank circuit has multiple frequency banks in order to support a continuous frequency range of operation from 7 GHz up to 14 05 GHz L Counter The L counter divides the differential clocks generated by the ATX PLL The division factors supported are 1 2 4 8 and 16 The L counter generates a differential clock and is not in the feedback path of the PLL M Counter The M counter s output is the same frequency as the N counter s output The VCO frequency is governed by the equation VCO freq M refclk N Because the L counter is not in the feedback path of the PLL an additional divider is required to divide the high speed serial clock output of the VCO before it reaches the M counter This divider divides by 2 The division factors supported by the M counter are 8 9 10 12 15 16 18 20 24 25 30 32 36 40 48 50 60 64 80 and 100 Delta Sigma Modulator The delta sigma modulator is used only in fractional mode It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis Instantiating ATX PLL The Arria 10 transceiver ATX PLL I
524. tcl files Clock and Reset Interfaces This topic defines the clock and reset signals The following table describes the clock and reset signals Table 2 92 Clock and Reset Signals tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA The frequency of this clock is 5 15625 GHz tx_serial_clk_lg Input High Speed clock from 1G PLL to drive the 1G PHY TX PMA This clock is not required if GbE is not used The frequency of this clock is 500 MHz rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock This clock frequency can be 644 53125 MHz or 322 2656 MHz ez Cae ret clk lg Input 1G PHY RX PLL reference clock The frequency is 125 MHz This clock is only required if 1G is enabled tx_pma_clkout Output This clock is used for the 1588 mode TX soft FIFO and 1G TX PCS parallel data This clock frequency is 125 MHz for 1G and 257 81 MHz for 10G This clock frequency is 161 13 MHz for 10G with FEC enabled rx_pma_clkout Output This clock is used for the 1588 mode RX soft FIFO and 1G RX PCS parallel data This clock frequency is 125 MHz for 1G and 257 81 MHz for 10G This clock frequency is 161 13 MHz for 10G with FEC enabled tx_clkout Output XGMII GMII TX clock for the TX parallel data source interface This clock frequency is 125 MHz in 1G mode and 257 81 MHz in 10G Mode and 161 13 MHz with FEC enabled ex elkout Output XGMII GMII RX clock for the RX parallel data
525. tect port signaldetect output port is enabled This signal is required for the PCI Express protocol If enabled the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified You can specify the signal detect threshold using a Quartus II QSF assignments Table 2 28 PCle Parameters Enable PCIe On Off When you turn this option on the pipe_rateand pipe_sw_ dynamic datarate done ports are enabled You should connect these ports to the switch ports PLL IP instance in multi lane PCIe Gen2 and Gen3 configurations These ports are only available for multi lane bonded configura tions Enable PCIe On Off When you turn this option on enables the pipe_hclk_in and pipe_hclk_in and pipe_hclk_out ports pipe_hclk_out These ports must be connected to the PLL IP instance for the PCI Express core Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Dynamic Reconfiguration Parameters 2 35 Enable PCIe On Off When you turn this option on enables the pipe_g3_txdeemph Gen3 analog and pipe_g3_rxpresenthint ports You can use these control ports ports to for equalization for Gen3 configurations Enable PCIe On Off When you turn this option on enables the pipe_rx_ electrical idle idleinfersel and pipe_rx_elecidle ports These control and ports are use
526. ted In this table X don t care S start OS order set I DS idle in data stream and I In idle inserted In cases 3 and 4 the Idles are inserted between the LW and UW Se a Se UW I DS I DS I In f LW X X I In UW OS OS I In i LW X X I In UW S I In S LW I DS I DS I In UW S I In S i LW OS OS I In Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback 5 30 i UG A10XCVR Basic Mode 2013 12 02 Figure 5 37 IDLE Word Insertion This figure shows the insertion of IDLE words in the receiver data stream Before Insertion y k rx_parallel data FD000000000004AEh BBBBBB9CDDDDDD9Ch lt d0000000000000FBh N AAAAAAAAAAAAAAAAR After Insertion i i rx parallel data FD000000000004AEh BBBBBB9CDDDDDD9Ch lt 0707070707070707h lt 00000000000000FBh Idle Inserted Basic Mode In Basic mode the RX FIFO operates as an elastic buffer The FIFO write enable is controlled by gearbox data valid which is a function of gearbox input and output data width You can monitor the rx_enh_fifo_pemptyandrx_enh_fifo_pfull flags to determine whether to read from the FIFO or not RX KR FEC Blocks KR FEC Block Synchronization You can obtain FEC block delineation for the RX KR FEC by locking onto correctly received FEC blocks with the KR FEC block synchronization Note The KR FEC block synchronization is available to implement the 10GBASE KR protocol KR FEC Descrambler The
527. tera Corporation Implementing Protocols in Arria 10 Transceivers GI Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Ports for PCI Express 2 209 pipe_g3_txdeemph 17 0 In tx_pma_clk For Gen3 selects the transmitter de emphasis The 18 bits specify the following coefficients 5 0 C 1 11 6 CO 17 12 C 1 In Gen3 capable designs the TX de emphasis for Gen2 data rate is always 6 dB The TX de emphasis for Gen1 data rate is always 3 5 dB Refer to section 6 6 of Intel PHY Interface for PCI Express PIPE Architecture for more information pipe_g3_rxpresethint In Ex _jome _CILIk Provides the RX preset hint for the receiver pipe_rx_eidlein fersel 2 0 7 tx_pma_clk When asserted high the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link The following encodings are defined 3 b0xx Electrical Idle Inference not required in current LTSSM state 3 b100 Absence of COM SKP OS in 128 ms window for Gen1 or Gen2 3 b101 Absence of TS1 TS2 OS in 1280 UI interval for Genl or Gen2 3 b110 Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2 3 b111 Absence of Electrical Idle exit in 128 ms window for Genl Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 210 Native PHY IP Ports for PCI Express
528. terface sends null pages This bit self clears Next Page NP is encoded in bit D15 of Link Codeword For more information refer to Clause 73 6 9 and bit 7 16 15 of Clause 45 2 7 6 of IEEE 802 3ap 2007 Implementing Protocols in Arria 10 Transceivers CI Send Feedback UG A10XCVR 2013 12 02 10GBASE KR PHY Register Definitions 2 131 Word R W Description Addr AN page received When set to 1 a page has been received When 0 a page has not been received The current value clears when the register is read For more information refer to bit 7 1 6 in Clause 73 8 of IEEE 802 3ap 2007 AN Complete When asserted Auto Negotiation has completed When 0 Auto Negotiation is in progress For more information refer to bit 7 1 5 in Clause 73 8 of IEEE 802 3ap 2007 AN ADV Remote Fault When set to 1 fault information has been sent to the link partner When 0 a fault has not occurred The current value clears when the register is read Remote Fault RF is encoded in bit D13 of the base Link Codeword For more information refer to Clause 73 6 7 of and bit 7 16 13 of IEEE 802 3ap 2007 When set to 1 the Auto Negotiation state machine is in the idle state Incoming data is not Clause 73 compatible When 0 the Auto Negotiation is in progress AN Ability When set to 1 the transceiver PHY is able to perform Auto Negotiation When set to 0 the transceiver PHY i s not able to perform Auto Negotiation If y
529. tern hex Oxl7c Number of word alignment patterns to achieve sync 3 Number of invalid data words to lose sync 3 Number of valid data words to decrement error count 3 Enable rx_std_wa_patternalign port Off Enable rx_std_wa_ala2size port Off Enable rx_std_bitslipboundarysel port Off Enable rx_bitslip port Off CPRI Auto configuration On CPRI Manual configuration All options under Word Bit Reversal and Polarity Inversion Off All options under PCIe Ports Off Table 2 139 Dynamic Reconfiguration Parameter VEIG Enable dynamic reconfiguration off Share reconfiguration interface off Enable embedded JTAG AVMM master On Off Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Other Protocols 2 225 Parameter VELTS Configuration file prefix altera_xcvr_native_a10 Generate SystemVerilog package file On Off Generate C header file On Off Generate MIF Memory Intialization File On Off Table 2 140 General Options Generate parameter documentation file On Off Other Protocols Using the Basic and Basic with KR FEC Configurations of Enhanced PCS You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G or 10G like protocols The Basic Enhanced PCS transceiver configuration rule allows access to the Enhanced PCS with full user control over the transceiver interfaces parameters and ports You can configure the t
530. tern must have neutral disparity RX rate match insert delete ve pattern 20 bits of data The first 10 bits correspond to the skip hex specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern The skip pattern must have neutral disparity The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing The rate match FIFO can delete a pair of skip patterns only if the two 10 bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20 bit word If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle the rate match FIFO cannot delete the pair of skip patterns Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Figure Figure Rate Match FIFO Basic Double Width Mode 2 241 2 118 Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion K28 5 is the control pattern and neutral disparity K28 0 is the skip pattern Two Pairs of Skip Patterns Deleted First Skip Cluster Second Skip Cluster v paralel dat iaio X Dx y K28 0 1 Dx y tx_parallel_data 9 0 y Dx y K28 5 rx_parallel_data 19 0 K Dxy K28 5 re ee i K28 0 Dxy A rx_parallel_data 9 0 y Dx y In this example the first skip cluster has a K28
531. terndetect is asserted whenever there is a pattern match e rx_syncstatus is asserted after the word aligner achieves synchronization e rx_std_wa_patternalign is also asserted to re align and re synchronize e If there is more than one channel in the design tx_datak rx_datak rx_errdetect rx_disperr rx_runningdisp rx_patterndetect and rx_syncstatus become busses in which each bit corresponds to one channel You can verify this feature by monitoring rx_parallel_data Figure 2 106 Synchronization State Machine Mode when the PCS PMA Interface Width is 20 Bits tx_datak 11 tx_parallel_data bc02 rx_parallel_data 0000 rx_datak 00 rx_disperr 11 rx_runningdisp 00 rx_errdetect 11 rx_patterndetect 00 rx_syncstatus 00 I 11 RX Bit Slip To use the RX bit slip select Enable rx_bitslip port and set the word aligner mode to bit slip This adds rx_bitslip asan input control port An active high edge on rx_bits1lip slips one bit at a time and when rx_bitslip is toggled then the word aligner slips one bit at a time on every active high edge You can verify this feature by monitoring rx_parallel_data The TX bit slip feature is optional and may or may not be enabled Figure 2 107 RX Bit Slip in 8 bit Mode tx_parallel_data 8 hbc rx_std_bitslipboundarysel 01111 rx_bits
532. th 1588 protocols is configured in automatic synchronization state machine mode The Quartus II software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets A synchronization ordered set is a K28 5 code group followed by an odd number of valid Dx y code groups The fastest way for the receiver to achieve synchronization is to receive three continuous K28 5 Dx y ordered sets Receiver synchronization is indicated on the rx_syncstatus port of each channel A high on the rx_syncstatus port indicates that the lane is synchronized a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization The receiver loses synchronization when it detects three invalid code groups separated by less than three valid code groups or when it is reset Table 2 67 Synchronization State Machine Parameter Settings for GbE Number of word alignment patterns to achieve sync 3 Number of invalid data words to lose sync 3 Number of valid data words to decrement error count 3 The following figure shows rx_syncstatus high when three consecutive ordered sets are sent through tx_parallel_data Figure 2 29 rx_syncstatus High Three Consecutive Ordered Sets Received to Achieve Synchronization spa YY BKB HYG BY EY BH 8c X 8d X 00 X 8c X Bd X 00 X 8c X ad tx_datak eae Co oror PEE y TEENE rx_datak
533. the fish expense of decreased jitter rejection Number of PLL reference clocks 1to5 Specifies the number of input reference clocks for the ATX PLL Generally used for data rate reconfiguration Selected reference clock source 0 to 4 Specifies the initially selected reference clock input to the ATX PLL Primary PLL clock output buffer GX clock output Specifies which PLL output is active initially Dulce If GX is selected turn ON Enable PLL GX clock GT clock output output port buffer e IfGT is selected turn ON Enable PLL GT clock output port Susie PLL GX clock output port On Off Enables the GX output port which feeds x1 clock lines 27 Must be selected for PLL output frequency less than 8 GHz or if reconfiguration below 8 GHz is planned Turn ON this port if GX is selected in the Primary PLL clock output buffer C You can enable both the GX clock output port and the GT clock output port However only one port can be in operation at any given time You can switch between the two ports using PLL reconfiguration Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR Enable PLL GT clock output On Off Enables the GT output port which feeds dedicated port high speed clock lines Must be selected for PLL output frequency greater than 8 GHz or if reconfiguration above 8 GHz is planned Turn ON this port if GT is selected in the Primary PLL clock output buffer parameter
534. the Electrical Idle ordered set consisting of 16 symbols with value 0x66 During electrical idle the transmitter differential and common mode voltage levels are based on the PCIe Base Specification 3 0 Gen3 Clock Compensation This mode can be enabled from the MegaWizard GUI when using the Gen3 PIPE transceiver configuration rule To accommodate PCle protocol requirements and to compensate for clock frequency differences of up to 300 ppm between source and termination equipment receiver channels have a rate match FIFO The rate match FIFO adds or deletes four SKP characters 32 bits to keep the FIFO from becoming empty or full It monitors the block synchronizer fora skip_found signal If the rate match FIFO is almost full the FIFO deletes four SKP characters If the rate match FIFO is nearly empty the FIFO inserts a SKP character at the start of the next available SKP ordered set FIFO full empty insertion and deletion is indicated by pipe_rx_status Note Refer to the Genl and Gen2 clock compensation section for waveforms Related Information Gen1 and Gen2 Clock Compensation on page 2 185 Gen3 Power State Management The PCle base specification defines low power states for PHY layer devices to minimize power consumption The Gen3 PCS does not implement these power saving measures except when placing the transmitter driver in electrical idle state in the low power states In P2 low power state the transceivers do not disable the P
535. the PLL f In N A tx_serial_clk_1 Note For Gen3 x1 ONLY tx_ serial_clk_1 is used Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback ERO Native PHY IP Ports for PCI Express 2 205 The 500 MHz clock used for the ASN block This clock is generated by the PLL pies ete Sa te N A configured for Gen1 Gen2 Note For Gen3 designs use from the fPLL that is used for Gen1 Gen2 The 500 MHz clock output pipe_hclk_out Out N A provided to the PHY MAC interface PIPE Input from PHY MAC Layer The TX parallel data driven from the MAC For Gen1 this can be 8 or 16 bits For Gen2 this is 16 bits only For Gen3 tx_parallel_data 31 0 In E arik this is 32 bits 15 0 or 7 0 Note unused_tx_ parallel_data should be tied to 0 Active High The data and control indicator for the received data For Gen1 or Gen2 when 0 indicates that tx_ parallel_data is data when 1 indicates that tx_ ex dataki Ol 130 or parallel_data is control In tx_pma_clk 0 For Gen3 Bit 0 corresponds to pipe_ txdata 7 0 bit 1 corresponds to pipe_ txdata 15 8 and soon Active High Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 206 Native PHY IP Ports for PCI Express 2013 12 02 For Gen3 indicates whether the 130 bit block transmitted is a Data or Control Ordered Set Block The following encodings are
536. the PRBS pattern is generated by an LFSR the next pattern can be determined based upon the previous pattern This is important for the PRBS checker because a portion of the received pattern can be used to generate the next sequence of bits to verify the next data sequence received is correct The PRBS generator and checker support two data width configurations 64 bit and 10 bit The PRBS generator PRBS checker and square wave must be configured to a supported bus width that is 64 bit or 10 bit independent of the FPGA PCS fabric width used For example if your FRGA PCS fabric width is set to a 40 bit width then you must configure the PRBS or square wave to a valid 64 bit or 10 bit width data generator Table 6 12 PRBS and Square Wave Supported Polynomials and Data Widths PRBS 9 G x 14 x5 x9 PRBS 15 G x 14 x14 x15 X PRBS 23 G x 1 x18 x23 x PRBS 31 G x 1 x28 x31 x Square Wave Number of consecutive 1 s and 0 s 4 6 8 x Enabling the PRBS and Square Wave Data Generator You must perform a sequence of read modify writes to the Native PHY reconfiguration interface to enable either the PRBS or square wave data generator You must perform the read modify writes to offsets 0x6 0x7 0x8 and 0x110 To enable either the PRBS or the square wave data generator follow these steps 1 Perform a read modify write to offset 0x6 according to the Table 6 13 2 Perform a read modify write to either offset
537. the scrambler scrambles There are two choices all 0 s or two local fault ordered sets The Pseudo Random Pattern shares the error signal with PRBS There is also an error count available Pseudo Random Pattern is only available when the scrambler is enabled You must perform a sequence of read modify writes to the Altera Corporation Reconfiguration Interface and Dynamic Reconfiguration GJ Send Feedback UG A10XCVR 2013 12 02 Enabling Pseudo Random Pattern Test Mode 6 19 reconfiguration interface to enable the Pseudo Random Pattern The read modify writes are required to offsets 0x82 0x97 and OxAC To enable the Pseudo Random Pattern complete the following steps A WO Nm Table 6 15 Pseudo Random Pattern Test Mode Offsets Perform a read modify write to offset 0x82X Perform a read modify write to offset 0x97 Perform a read modify write to offset OxAC Perform a reset To disable the PRBS verifier write the original values back into the read modify write offsets listed above Reconfiguration Reconfiguration Attribute Name Bit Encoding Description Address HEX Bit 0x72 7 0 r_tx_seed_a 7 0 Seed A value bit 7 0 0x73 r_tx_seed_a 15 8 Seed A value bit 15 8 0x74 r_tx_seed_a 23 16 Seed A value bit 23 16 0x75 r_tx_seed_a 31 24 Seed A value bit 31 24 0x76 r_tx_seed_a 39 32 Seed A value bit 39 32 0x77 r_tx_seed_a 47 40 Seed A value bit 47 40 0x78 r_tx
538. this channel The value greater than the INITPREVAL parameter for proper operation 28 RW LT VPre ovrd Enable When set to 1 enables the override value for the VPRERULE parameter stored in the LT VPre ovrd register field Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Hard Transceiver PHY Registers 2 141 Word R W Description Addr Counts the number of corrected FEC blocks Resets to 0 when read Otherwise it holds at the maximum count and does not roll over Refer to Clause 74 8 4 1 of IEEE 802 3ap 2000 for details The low order byte of each register maps to the following bits of the 32 bit counter OxODD OxO0DE OxODF 7 0 RSC FEC Corrected Blocks 0x0DC 7 0 7 0 0x0DD 7 0 15 8 Ox0DE 7 0 23 16 0x0DF 7 0 31 24 Ox0EO0 Ox0E1 Ox0E2 Ox0E3 7 0 RSC FEC Uncorrected Blocks Hard Transceiver PHY Registers Table 2 102 Hard Transceiver PHY Registers Counts the number of uncorrectable FEC blocks Resets to 0 when read Otherwise it holds at the maximum count and does not roll over Refer to Clause 74 8 4 1 of IEEE 802 3ap 2000 for details The low order byte of each register maps to the following bits of the 32 bit counter 0x0E0 7 0 7 0 0x0E1 7 0 15 8 0x0E2 7 0 23 16 0x0E3 7 0 31 24 pair fa acess ame econ All registers in the PCS and PMA that you can dynamical
539. tiacinnisrcenneshnasemaianentviniasd cceseraeotnanmny iGwammeniet 3 28 XN Clock Tines reuersi inrait ecenbecaa ona aodeacacea nna davaeatncnasdbded a teraansstuanaa tenn pennatavecsdvesss 3 29 CGT Clock LiNE Serran rerien bupaa isos aa bane DA AE EE 3 31 Clock Generation BN Gore cen erie A EE E a E ETE e aa 3 32 FPGA Fabric Transceiver Interface Clocking ssesessssesesssseresesessersrreesssnrerrteessssntereennsernrreesnsnrnree 3 34 Transmitter Data Path Interface Clocking seseeesesseeesesereesesrtessssstesssrtetsssrressrrttesnrttetssrrteserrresnrrreesreet 3 34 Receiver Data Path Interface Clocking ess ssseesssssrrssssserssseerssssteesesusssrnrtsesnsntereeersnssntereennnsrnrreessssnrreee 3 36 Cha nel Bs nh A avast also asn ncaa tS wp a aaa aaea 3 38 PLL Feedback and Cascading Clock Net wait lk sq soxesovsvsseaancesaiansesainadstvdnsveinsicghvennvcesbceauslandentsstonsiansienive 3 38 Using PLLs and Clock NetWOTKS iissa n aaa aiaa 3 40 Non bonded configurations scicscscieassindesacinseadsadevisasueiaceseraherearanerusimevandeadevnecnietiveiines 3 40 Bonded COMMA UPATONS sissicsisecniesiicsiiescascaaehthveuivedd n E E E EIEEE EEES 3 44 PLE c sc din gsi e r a Ar TEE aaaaiee 3 48 Mix and Match Exampleencsinerniieiianiiiinaatii iriiria iieiea erii a 3 49 Resetting Transceiver Channels eessesssessseeesessssossseesseseseesssesssoessesssessseessses 4 1 When Is Reset Required sisistacce ssiavessceccncsseretsdecssescutdhse
540. ting Protocols in Arria 10 Transceivers Altera Corporation 2 32 Standard PCS Parameters UG A10XCVR 2013 12 02 Enable rx_std_ On Off Enables the rx_std_rmfifo_empty port rmfifo_empty port PCI Express Bypass 0 ppm 600 Specifies the PPM tolerance for the PCI Express Gen3 rate match Gen3 rate match ppm FIFO FIFO mode Table 2 26 Word Aligner and Bitslip Parameters Enable TX bitslip On Off When you turn this option on the PCS includes the bitslip function The outgoing TX data can be slipped by the number of bits specified by the tx_std_bitslipboundarysel control signal Enable tx_std_ On Off Enables the tx_std_bitslipboundarysel bitslipbound arysel port RX word aligner bitslip Specifies the RX word aligner mode for the Standard PCS The mode word aligned width depends on the PCS and PMA width and manual PLD i whether 8B 10B is enabled controlled synchronous state machine deterministic latency RX word aligner 7 8 10 16 20 32 40 Specifies the length of the pattern the word aligner uses for pattern length alignment RX word aligner User specified Specifies the word aligner pattern in hex pattern hex Number of word 0 255 Specifies the number of valid word alignment patterns that must alignment be received before the word aligner achieves synchronization lock patterns to The default is 3 achieve sync Number of 0 63 Specifies the number of invalid data c
541. tion FIFO Related Information Arria 10 Enhanced PCS Architecture on page 5 14 For more information about the Enhanced PCS Architecture How to Implement 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC in Arria 10 Transceivers Before you begin You should be familiar with the 1OGBASE R and PMA architecture PLL architecture and the reset controller before implementing the 1OGBASE R 1OGBASE R with 1588 or 1OGBASE R with KR FEC Transceiver Configuration Rules You must design your own MAC and other layers in the FPGA to implement the 1OGBASE R 10GBASE R with 1588 or 1OGBASE R with KR FEC Transceiver Configuration Rule using the Native PHY IP 1 Open the MegaWizard Plug In Manager and select the Arria 10 Transceiver Native PHY IP Refer to Select and Instantiate PHY IP on page 2 2 for more details 2 Select 1OGBASE R 1OGBASE R 1588 or 1OGBASE R with KR FEC from the Transceiver configuration rule list located under Datapath Options depending on which protocol you are implementing 3 Use the parameter values in the tables in Native PHY IP Parameter Settings for 1OGBASE R 10GBASE R with 1588 and 1OGBASE R with KR FEC as a starting point Or you can use the protocol presets described in Preset Configuration Options You can then modify the settings to meet your specific requirements 4 Click Finish to generate the Native PHY IP this is your RTL file Implementing Protocols in Arria 10 Transceivers Altera Corporation
542. tion Implementing Protocols in Arria 10 Transceivers CJ Send Feedback s p R How to Implement the Basic Basic with Rate Match Transceiver Configuration Rules in Arria 10 Transceivers 2 245 Refer to Select and Instantiate PHY IP on page 2 2 2 Select Basic Custom Standard PCS or Basic Custom w Rate Match Standard PCS from the Transceiver configuration rules list located under Datapath Options depending on which configuration you want to use 3 Use the parameter values in the tables in Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations as a starting point Or you can use the protocol presets described in Preset Configuration Options You can then modify the setting to meet your specific requirements 4 Click Finish to generate the Native PHY IP this is your RTL file Figure 2 129 Signals and Ports of Native PHY IP for Basic Basic with Rate Match Configurations A10 Transceiver Native PHY EE gt Reconfiguration Nios Hard p gt tx_cal_busy eae tin Ed Registers Calibration IP p gt rx_cal_busy tx_digital_resei p TX Standard PCS TX PMA tx_datak tx_datak tx_parallel_data 7 0 tx_parallel_data 7 0 10 gt tx_coreclkin A Serializer tx_serial_data tx_clkou al tx_clkout A tx_analog_rese Moors 4 tx_serial_clk0 from TX PLL rx_analog_rese
543. tional Related Information Component Interface Tcl Reference Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 160 Clock and Reset Interfaces 2013 12 02 Clock and Reset Interfaces This topic defines the clock and reset signals The following table describes the clock and reset signals Table 2 112 Clock and Reset Signals tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA The frequency of this clock is 5 15625 GHz tx_serial_clk_lg Input High Speed clock from 1G PLL to drive the 1G PHY TX PMA This clock is not required if GbE is not used The frequency of this clock is 500 MHz rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock This clock frequency can be 644 53125 MHz or 322 2656 MHz ex edn ret clk lg Input 1G PHY RX PLL reference clock The frequency is 125 MHz This clock is only required if 1G is enabled tx_pma_clkout Output This clock is used for the 1588 mode TX soft FIFO and 1G TX PCS parallel data This clock frequency is 125 MHz for 1G and 257 81 MHz for 10G This clock frequency is 161 13 MHz for 10G with FEC enabled rx_pma_clkout Output This clock is used for the 1588 mode RX soft FIFO and 1G RX PCS parallel data This clock frequency is 125 MHz for 1G and 257 81 MHz for 10G This clock frequency is 161 13 MHz for 10G with FEC enabled tx_clkout Output XGMII GMII TX clock for the TX
544. tionauens 2 6 Aeon pT IST A a E aces bcd nn anndbanua sneha eibadnnn E 2 6 Verity Design F nctionality sss as stecivanetv essai cxsttetetaieanveuenddorcpentesbasteamuae cau tabeastantaaiw vata 2 7 Arria 10 Transceiver Protocols and PHY IP Suppott eesessssesssececseesesesecsseseseseesecseseseeeeeeeseeeeees 2 7 Using the Arria 10 Transceiver Native PHY UP ssssicncisacsspessinasivacsasacdcasdosaeadbssusesiadheaadetantaneasixedeedssiaens 2 12 General and Datapath Parameters ss sssessssessseesssesessesesesrssetesstesntesntesntresteesrtresrteesreeesreesreeesrres 2 15 PMA Paraimetersyisc casiscssssscasisteseni scsedssindssiosssdecatesvedhatonsadsesecedisscasssesdicuesssndhatesd TEER KEE NEEE RAEES 2 17 Arria 10 Transceiver PHY User Guide TOC 3 Enhanced POS Parameters siscsxcacssass beau s5vchascd asia otaatonsascandhsssassg sabes EER aAa 2 22 Standard POS PAPAS LEI S o ereet seis aaa te waded EA eens estar erase 2 29 Dynamic Reconfiguration Parameters jaa sscisusscessascechncsecssnennssonesayannstuntiesinantanielaibispnandesnsnnds 2 35 Enhanced PCS nd PMA POG sissc sts cintsie iaensnuvisnsnrsitenerdamnnianmmenadaaens 2 37 Standard POS atid PMA POrts issstcsccccssscsiscssctessacanscoisqstin a E E 2 52 Pres t Co figuration OPtionSsenscriie tiiran aaa 2 61 IP Core Pile Locations sisaria i r a A R ETERA 2 61 IEE os EN EEE E E E EE E EE EEE 2 62 Metaframe Format and Framing Layer Control Word sss sssssssssssesssssssesrrresssssrressersssneer
545. tner e 2 b10 Symmetric pause e 2 b11 Pause is supported on TX and RX 13 12 RF2 RF1 Remote fault condition for link partner The following encodings are defined for RF1 RF2 e 2 b00 No error link is valid reset condition e 2 b0 1 Offline e 2 b10 Failure condition e 2 b11 Auto negotiation error 14 ACK Acknowledge for link partner A value of 1 indicates that the device has received three consecutive matching ability values from its link partner 15 NP Next page In link partner register When set to 0 the link partner has a Next Page to send When set to 1 the link partner does not a Next Page Next Page is not supported in Auto Negotiation 0x496 0x4A2 LINK_ PARTNER_ AUTO_ NEGOTIATION_ ABLE Set set to 1 indicates that the link partner supports auto negotiation The default value is 0 PAGE_RECEIVE AN link timer 15 0 A value of 1 indicates that a new page has been received with new partner ability available in the register partner ability The default value is 0 when the system management agent performs a read access Low order 16 bits of the 21 bit auto negotiation link timer Each timer step corresponds to 8ns assuming a 125 MHz clock The total timer corresponds to 16 ms The reset value sets the timer to 10 ms for hardware mode and 10 us for simulation mode 0x4A3 4 0 AN link timer 4 0 Implementing Protocols in Arria
546. to 1 the receiver is trained and is ready to receive data When set to 0 receiver training is in progress For more information refer to the state variable rx_trained as defined in Clause 72 6 10 3 1 and bit 1OGBASE KR PMD control register bit 1OGBASE_KR PMD status register bit 1 151 0 of IEEE 802 3ap 2007 1 RO Link Training Whensetto 1 the training frame delineation has been detected Frame lock When set to 0 the training frame delineation has not been detected For more information refer to the state variable frame_lock as defined in Clause 72 6 10 3 1 and 1OGBASE_KR PMD status register bit 1OGBASE_KR PMD status register bit 1 151 1 of IEEE 802 3ap 2007 2 RO Link Training When set to 1 the start up protocol is in progress When set Start up to 0 start up protocol has completed For more information Ox4D2 protocol refer to the state training as defined in Clause 72 6 10 3 1 and status 10GBASE_KR PMD status register bit 1 151 2 of IEEE 802 3ap 2007 3 RO Link Training Whenset to 1 a training failure has been detected When set failure to 0 a training failure has not been detected For more information refer to the state variable training _failure as defined in Clause 72 6 10 3 1 and bit 1OGBASE_KR PMD status register bit 1 151 3 of IEEE 802 3ap 2007 4 RO Link Training When set to 1 excessive errors occurred during Link Training Error When set to 0 the BER is acceptable 5 RO Link Training When sett
547. tor block takes the data from the TX FIFO and encapsulates the payload and burst idle control words from the FPGA fabric with the framing layer s control words Synchronization word scrambler state word skip word and diagnostic word to form a metaframe The Native PHY IP MegaWizard allows you to set the metaframe length from five 8 byte words to a maximum value of 8192 64Kbyte words Program the same value for the metaframe length for the transmitter and receiver Figure 5 21 Interlaken Frame Generator The Interlaken frame generator is available to implement the Interlaken protocol 64 Bit Data inteviaken To Interlaken From TX FIFO h Frame p 66 Bit Blocks on 1 Bit Control Genersior CRC 32 Generator Payload y Synchronization Samber skip Word 66 65 64 63 o 66 0 66 eee ojpi ynchronization lt 6 Word Skip Wor Data L Provides Per gt Sync Header Lane Error Check gt inversion Bit Place Holder for Bit Inversion Information and Optional Status ___________ Used for Clock Compensation in a Repeater Message gt Used to Synchronize the Scrambler gt Used to Align the Lanes of the Bundle Interlaken CRC 32 Generator The Interlaken CRC 32 generator block receives data from the Interlaken frame generator and calculates the cyclic redundancy check CRC code for each block of data This CRC code value is
548. ts 0x491 NEGOTIATION_ Clause 37 Auto Negotiation ABILITY 5 R AUTO_ A value of 1 indicates the following status fe ee eas e The Auto Negotiation process is complete e The Auto Negotiation control registers are valid 5 RW FD Full duplex mode enable for the local device Set to 1 for full duplex support 6 RW HD Half duplex mode enable for the local device Set to 1 for half duplex support This bit should always be set to 0 8 7 RW PS2 PS1 Pause support for local device The following encodings are defined for PS1 PS2 e 2 b00 Pause is not supported e 2 b0 1 Asymmetric pause toward link partner e 2 b10 Symmetric pause e 2 b11 Pause is supported on TX and RX 0x494 13 12 RW RF2 RF1 Remote fault condition for local device The following encodings are defined for RF1 RF2 e 2 b00 No error link is valid reset condition e 2 b0 1 Offline e 2 b10 Failure condition e 2 b11 Auto negotiation error 14 RO ACK Acknowledge for local device A value of 1 indicates that the device has received three consecutive matching ability values from its link partner 15 RW NP Next page In the device ability register this bit is always set to 0 Altera Corporation Implementing Protocols in Arria 10 Transceivers J Send Feedback UG A10XCVR 2013 12 02 Arria 10 GMII PCS Registers 2 173 LL 0x495 Full duplex mode enable for the link partner This bit should always be 1 because only full duplex is supported Ha
549. tter PMA Transmitter Enhanced PCS FPGA MAn peN PRP Generator J TX Data amp Control PRBS Generator Parallel Clock j TX Gearbox TX FIFO A Scrambler Interlaken Disparity Generator and TX SM Interlaken CRC32 Generator Interlaken Frame Generator Enhanced PCS tx_serial_data I Serializer A 64B 66B Encoder a Bean N f tx_coreclkin tx_clkout e Encoder KR FEC TX Gearbox A KR FEC Scrambler KR FEC Encoder Transcode tx_pma_div_clkout Clock Generation Block CGB e Parallel Clock Serial Clock Parallel and Serial Clocks ae ATX PLL gie Clock Divider lt fPLL 9 j CMU PLL Parallel and Serial Clocks Serial Clock j Input Reference Clock In the Enhanced PCS the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO For the enhanced PCS the transmitter PCS forwards the following clocks to the FPGA fabric e tx_clkout foreach transmitter channel in non bonded configuration e tx_clkout 0 forall transmitter channels in bonded configuration You can clock the transmitter datapath interface by using one of the follo
550. ty bit OxBO 16 FEC ability bit during power up and reset causing the core to advertise the FEC ability This option is required for FEC functionality Set FEC_Enab1e bit on power up and reset On Off When you turn this option On the core sets the KR FEC Request bit 0xBO 18 during power up and reset causing the core to request the FEC ability during Auto Negotiation This option is required for FEC functionality 10M 100M 1Gb Ethernet Parameters The 10M 100M 1GbE parameters allow you to specify options for the MII interface and the 1GbE data rate Table 2 110 10M 100M 1Gb Ethernet a Enable 1Gb Ethernet protocol On Off When you turn this option on the core includes the GMII interface and related logic Enable 10M 100Mb Ethernet On Off When you turn this option on the core includes functionality the MII PCS It also supports 4 speed mode to implement a 10M 100M interface to the MAC for the GbE line rate Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation 2 158 Speed Detection Parameters UG A10XCVR 2013 12 02 A Deerton PHY ID 32 bits 32 bit value An optional 32 bit value that serves as a unique identifier for a particular type of PCS The identifier includes the following components e Bits 3 24 of the Organizationally Unique Identifier OUI assigned by the IEEE e 6 bit model number e 4 bit revision number If unused do not cha
551. ual RX CDR LTD Altera Corporation Resetting Transceiver Channels GI Send Feedback UG A10XCVR 2013 12 02 Resetting the Transceiver in CDR Manual Lock Mode 4 7 Resetting the Transceiver in CDR Manual Lock Mode You can use the clock data recovery CDR manual lock mode to override the default CDR automatic lock mode depending on your design requirements The two control signals to enable and control the CDR in manual lock mode are rx_set_locktoref and rx_set_locktodata Follow this sequence to reset your transceiver when the CDR is in manual lock mode The numbers in the following figure correspond to the numbered list which guides you through the steps to put the CDR in manual lock mode 1 Make sure that the calibration is complete rx_cal_busy is low and the transceiver goes through the initial reset sequence The rx_digitalreset and rx_analogreset signals should be low The rx_is_lockedtoref isa don t care and can be either high or low The rx_is_lockedtodata and rx_ready signals should be high indicating that the transceiver is out of reset Alternatively you can start directly with the CDR in manual lock mode after the calibration is complete Assert the rx_set_locktoref signal high to switch the CDR to the lock to reference mode The rx_is_lockedtodata status signal is deasserted Assert the rx_digitalreset signal high at the same time or after rx_set_lockedtoref is asserted if you use the user controlled reset When the Transc
552. ue Values for the receiver ready bit are defined in Clause 72 6 10 2 4 4 For more information refer to bit 10G BASE KR LP status report register bits 1 153 15 in Clause 45 2 1 79 of IEEE 802 3ap 2007 5 0 R LT Vop setting Stores the most recent Vop setting that LT specified using the Transceiver Reconfiguration Controller IP core It reflects Link Partner commands to fine tune the Vop 12 8 R LT Post tap 0x4D5 setting Stores the most recent post tap setting that LT specified using the Transceiver Reconfiguration Controller IP core It reflects Link Partner commands to fine tune the TX pre emphasis taps 19 16 R LT Pre tap setting Stores the most recent pre tap setting that LT specified using the Transceiver Reconfiguration Controller IP core It reflects Link Partner commands to fine tune the TX pre emphasis taps Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation 2 140 10GBASE KR PHY Register Definitions UG A10XCVR 2013 12 02 Word R W Description Addr LT VODMAX ovrd Override value for the VMAXRULE parameter When enabled this value substitutes for the VMAXRULE to allow channel by channel override of the device settings This only effects the local device TX output for the channel specified This value must be greater than the INITMAINVAL parameter for proper operation Note this will also override the PREMAINVAL parameter value RW LT VOD
553. ulation model files and Altera simulation library models manually You can simulate the following three netlists e The RTL functional netlist This netlist provides cycle accurate simulation using Verilog HDL SystemVerilog and VHDL design source code Altera and third party EDA vendors provide the simulation models e The post synthesis gate level functional netlist This netlist verifies functionality after synthesis e The gate level timing netlist This netlist verifies both functionality and timing Prerequisites to Simulation Before you can simulate your design you must have successfully passed Quartus II Analysis and Synthesis Related Information Simulating Altera Designs NativeLink Simulation Flow The NativeLink settings available in the Quartus II software allow you to specify your simulation environment simulation scripts and testbenches The Quartus II software saves these settings in you project Once you specify the NativeLink settings you can start simulations easily from the Quartus II software How to Use NativeLink to Specify a ModelSim Altera Simulation Complete the following steps to specify the directory path and testbench settings for your simulator 1 On the Tools menu click Options and then click EDA Tool Options 2 Browse to the directory for your simulator The following table lists the directories for supported simulators Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ
554. umber of CDR reference clocks 1 5 Specifies the number of CDR reference clocks Up to 5 sources are possible The default value is 1 Selected CDR reference clock 0 lt number of CDR reference clocks gt Specifies the initial CDR reference clock The parameter Number of CDR reference clocks determines the available CDR references available used The default value is 0 Selected CDR lt data rate Specifies the CDR reference clock frequency This value depends reference clock dependent gt on the data rate specified frequency PPM detector 62 5 100 125 200 Specifies the PPM threshold for the CDR If the PPM threshold threshold 250 300 500 1000 value you select here is exceeded the CDR loses lock The default value is 1000 Decision Disabled Specifies the operating mode for the decision feedback equalization feedback DFE block in the RX PMA equalization eee q The default value is Disabled mode Floating tap Table 2 8 RX PMA Optional Ports Enable rx_pma_ clkout port On Off Enables the optional rx_pma_clkout output clock This port is the recovered parallel clock from the RX clock data recover CDR Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 PMA Parameters 2 21 Enable rx_pma_ div_clkout port On Off Enables the optional rx_pma_div_clkout output clock The deserializer generates this clock Use
555. unction can auto negotiate between 1000BASE X 1000BASE KR and 1000BASE KRwith FEC e Gigabit Media Independent Interface GMII to connect PHY with media access control MAC as defined in Clause 35 of the IEEE 802 3 2008 Standard e Auto negotiation as defined inClause 37 of the IEEE 802 3 2008 Standard e Gigabit Ethernet protocol as defined inClause 49 of the IEEE 802 3 2008 Standard e XGMII to provide simple and inexpensive interconnection between the MAC and the PHY as defined in Clause 46 of the IEEE 802 3 2008 Standard e Forward Error correction FEC as defined in Clause 74 of the IEEE 802 3 2008 Standard e Precision time protocol PTP as defined in the IEEE 1588 Standard e 10M 100Mbps MII to connect physical media with the MAC as defined in Clause 22 of the IEEE 802 1 2008 Standard Using the Backplane Ethernet PHY MegaCore function you can implement the 1GbE protocol using the Standard PCS and 10GbE protocol using Enhanced PCS and PMA You can switch dynamically between the 1G and 10G data rates using dynamic reconfiguration to reprogram the transceivers Or you can use the speed detection option to automatically switch data rates based on received data The following figure shows the top level modules of the 1G 10GbE PHY IP As show in the following figure the 1G 10 Gbps Ethernet PHY connects to a separately instantiated MAC The Enhanced PCS receives and transmits XGMII data The Standard PCS receives and transmits GMII data An Av
556. unt PCle PCle Hard IP Block PCle Hard IP Block PCle Hard IP Block Hard IP Block Count Count Count Count GX 090 66 3 48 4 72 4 96 4 Package U19 19mm x 19mm package 484 pins Package F27 27mm x 27mm package 672 pins o Package F29 29mm x 29mm package 780 pins Packages F34 F35 and F36 35 mm x 35 mm package size 1152 pins 6 Package F40 40 mm x 40 mm package size 1517 pins Arria 10 Transceiver PHY Overview Altera Corporation GI Send Feedback z UG A10XCVR 1 12 Arria 10 SX Device Transceiver Layout 2013 12 02 a a E E E Transceiver Count Transceiver Count Transceiver Count Transceiver Count PCle PCle Hard IP Block PCle Hard IP Block PCle Hard IP Block Hard IP Block Count Count Count Count GT 090 72 4 96 4 GT 115 72 4 96 4 Arria 10 SX Device Transceiver Layout The largest SX device includes 48 transceiver channels All SX devices have GX transceiver channel type The transceiver banks in SX devices are located on the left side periphery of the device 0O Package F45 45mm x 45mm package size 1932 pins Altera Corporation Arria 10 Transceiver PHY Overview GJ Send Feedback A10XCVR z A ASNO Arria 10 SX Device Transceiver Layout 1 13 Figure 1 11 Arria 10 SX Device with 48 36 and 24 Transceiver Channels and Two Hard IP Blocks Transceiver Bank CH5 CH4 Transceiver 3 Bank CH3 Transceiver
557. up to six channels in the same transceiver bank e Connect the PLL to the PHY IP by duplicating the output of the PLL 5 0 for the number of transceiver channels used in the bonding group Note For this 10 channel example two ATX PLLs are instantiated 6 channels of the tx_bonding_clocks on the Native PHY IP are connected to the first ATX PLL and the remaining four channels are connected to the second ATX PLL s tx_bonding_clock outputs PLL cascading In PLL cascading the output of the first PLL feeds the input reference clock to the second PLL Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Mix and Match Example 3 49 For example if the input reference clock has a fixed frequency and the desired data rate was not an integer multiple of the input reference clock In this case the first PLL can be used to generate the correct reference clock frequency This output is fed as the input reference clock to the second PLL This second PLL generates the clock frequency required for the desired data rate The transceivers in Arria 10 devices support PLL to fPLL or fPLL to ATX PLL cascading The first PLL must be a fPLL The following example describes PLL to ATX PLL cascading PLL IP MegaWizard configuration Generate the fPLL IP The first PLL used in a PLL cascading configuration must be a fPLL Turn ON Enable Cascade clock output port fPLL to ATX PLL cascading Turn ON Use as Core PL
558. ure pll_locked lt p gt Input Asynchronous status Provides the PLL locked status input from each 1 0 from TX PLL PLL When asserted indicates that the TX PLL is locked When deasserted the PLL is not locked There is one signal per PLL pll_select lt p gt Input Synchronous to the When you select Use separate TX reset per 130 Transceiver PHY channel this bus provides enough inputs to Reset Controller specify an index for each p11_locked signal input clock Set to to listen to for each channel When Use separate zero when not using TX reset per channel is disabled the p11_ multiple PLLs select signal is used for all channels tx_cal_busy lt n gt Input N A This is the calibration status signal that results 1 0 from the logical OR of p11_cal_busy and tx_cal_busy signals The signal goes high when either the TX PLL or Transceiver PHY calibration is active The signal goes low when calibration is completed This signal gates the TX reset sequence The width of this signals depends on the number of TX channels rx_cal_busy lt n gt Input Asynchronous This is calibration status signal from the 1 0 Transceiver PHY IP core When asserted calibration is active When deasserted calibration has completed This signal gates the RX reset sequence The width of this signals depends on the number of RX channels Resetting Transceiver Channels Altera Corporation GJ Send Feedback UG A10XCVR 4 14
559. ursor e ISI occurs when the data sampled at precursor or postcursor is not Zero The DFE circuit stores delayed versions of the data The stored bit is multiplied by a coefficient and then summed with the incoming signal The polarity of each coefficient is programmable The DFE architecture supports seven fixed taps and four floating taps The modes of operation for DFE are e Continuous adaptation Continuously runs DFE adaptation e Triggered adaptation Stops adaptation once DFE adaptation is complete e Manual You can manually set the fixed tap and floating tap values through the Avalon MM registers The seven fixed taps translate to the DFE capable of removing the ISI from the next 7 bits beginning from the current bit The pulse at the output of the channel shows a long decaying tail because of the frequency dependent losses along with other signal quality degradation Altera Corporation Arria 10 Transceiver PHY Architecture CJ Send Feedback UG A10XCVR 2013 12 02 On Die Instrumentation ODI Figure 5 11 Channel Pulse Response vi Signal at the Region of Influence Channel Input for Fixed Taps lt gt Region of Influence for Floating Taps very Signal at the Channel Output ul gt 5 9 Reflections also appear on the post cursor tail at a later time These reflections occur due to impedance discontinuities at various points along the signal path Some such points are bet
560. use 74 of the IEEE 802 3 2008 Standard e Precision time protocol PTP as defined in the IEEE 1588 Standard e 10M 100Mbps MII to connect physical media with the MAC as defined in Clause 22 of the IEEE 802 1 2008 Standard The 1G 10Gbps Ethernet PHY MegaCore Function allows you to implement the 1GbE protocol using the Standard PCS and 10GbE protocol using Enhanced PCS and PMA You can switch dynamically between the 1G and 10G data rates using dynamic reconfiguration to reprogram the core Or you can use the speed detection option to automatically switch data rates based on received data The 1G 10Gbps Ethernet PHY also supports a SGMII 10MB 100MB 1000MB interface The following figure shows the top level modules of the 1G 10GbE PHY IP As this figure indicates the 1G 10 Gbps Ethernet PHY connects to a separately instantiated MAC The Enhanced PCS receives and Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 150 1G 10GbE PHY Release Information UG A10XCVR 2013 12 02 transmits XGMII data The Standard PCS receives and transmits GMII data An Avalon Memory Mapped Avalon MM slave interface provides access to PCS registers The PMA receives and transmits serial data Figure 2 58 Level Modules of the 1G 10GbE PHY MegaCore Function To From 1G 10Gb Ethernet MAC Optional 1588 TX and RX Latency Adjust 1G and 10G PCS Reconfig Request Avalon MM PHY Management Interface 156
561. uts are connected to the feedback and cascading clock network The input reference clock to the first PLL can be sourced from the same network In this mode the output of one PLL Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Reference Clock Network 3 27 drives the reference clock input of another PLL PLL cascading can generate frequency outputs not normally possible with a single PLL solution The transceivers in Arria 10 devices support fPLL to fPLL or fPLL to ATX PLL cascading Reference Clock Network The reference clock network distributes a reference clock source to either the entire left or right side of the FPGA where the transceivers reside This allows any reference clock pin to drive any transmitter PLL on the same side of the device Designs using multiple transmitter PLLs which require the same reference clock frequency and are located along the same side of the device can share the same dedicated reference clock refclk pin Transmitter Clock Network The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel It provides following two types of clocks to the transmitter channel e High Speed Serial clock high speed clock for the serializer e Low Speed Parallel clock low speed clock for the serializer and the PCS In a bonded channel configuration both the serial clock and the parallel clock are routed from the transmitter PLL to the tran
562. v13 1 for Arria 10 devices The numbers of ALMs and logic registers are rounded up to the nearest 100 Table 2 84 10GBASE KR PHY Performance and Resource Utilization 10GBASE KR PHY with 1588 4700 6600 6750 E 10GBASE KR PHY 2400 3750 3100 1 10GBASE KR PHY with FEC 2400 3750 3100 1 10GBASE KR Functional Description This topic provides high level block diagram The following figure shows the 1OGBASE KR PHY IP and the supporting modules required for integration into your system Altera Corporation Implementing Protocols in Arria 10 Transceivers GJ Send Feedback UG A10XCVR 2013 12 02 10GBASE KR Functional Description 2 107 Figure 2 51 10GBASE KR PHY IP Block Diagram Sequencer Auto Speed Detect Reconfiguration p Block Native PHY 40 32 Standard TX PCS TX PMA ie p gt tx_pld_clk tx_pma_clk Auto Negotiation Clause 73 1588 FIFO Enhanced TX PCS pptx pld clk tx_pma_clk Link Training Clause 72 Standard RX PCS gt rx_pld_clk rx_pma_clk Enhanced RX PCS Aue RX PMA PCS KP P gt mx_pld_clk rx_pma_clk gt Divide by 33 1 2 4 E Soft Logic Hard Logic As this figure illustrates the Backplane Ethernet 1OGBASE KR PHY IP core is built using the Native PHY It includes the following modules Standard and
563. vailable in a future release of the Quartus ll software 4 The Standard PCS and PCle Gen3 PCS blocks are available when the GT channel is reconfigured as a GX transceiver channel Table 1 7 PCS Types and Data Rates Supported by GT Channel Configurations GT Channel Configuration PCS Type Data Rates Supported Standard PCS Not available GT Enhanced PCS 17 4 Gbps to 28 1 Gbps PCIe Gen3 PCS Not available Standard PCS 611 Mbps to 10 Gbps GX Enhanced PCS 611 Mbps to 17 4 Gbps PCIe Gen3 PCS 8 Gbps Note The GT channels can also operate in PCS Direct configuration for data rates between 611 Mbps to 28 1 Gbps The Enhanced PCS must be configured in low latency mode to support data rate range from 17 4 Gbps to 28 1 Gbps Arria 10 Transceiver PHY Overview Altera Corporation CJ Send Feedback UG A10XCVR 1 20 Transceiver Phase Locked Loops 2013 12 02 Transceiver Phase Locked Loops Each transceiver channel in Arria 10 devices has direct access to three types of high performance PLLs e Advanced Transmit ATX PLL e Fractional PLL fPLL e Channel PLL Clock Multiplier Unit CMU PLL These transceiver PLLs along with the Master or Local Clock Generation Blocks CGB drive the transceiver channels Related Information PLLs on page 3 3 For more information on transceiver PLLs in Arria 10 devices Advanced Transmit ATX PLL An advanced transmit ATX PLL is a high performance PLL It supports both integer
564. vcssivsnis desiatenwrausuviacsinerasivaneeniauialannnuausnuiines 6 11 CDR and CMU Reference Clock Switching sese esseseeesessseesssreeessseressrrrtessstrerssrrteseerersnreeresreet 6 12 Changing PMA Anal g Parameter Sisesnuraniinunsneniniianei niaaa 6 13 Using Data Pattern Generators and CheckerS ss ssssessseessresssesssressreeesrtesntessntesntessntesnteeserrsrerssereese 6 13 Using PRBS and Square Wave Data Pattern Generator and Checker esses 6 14 Unsupported Beatin es ests amp sse eieaa es darsan a E AEE E a a a a asta aoe eaa Ra 6 20 Transceiver and PLL Address Map cessssssscssscssssssseeeeeessseseneeeecensnesenceucuceenesssececacueaesnscecucaeaeanseeeseees 6 21 Document Revision History scsssccseseesds ciassscscsccecccscsossacsceccaascessscssescesacebansteuceceds 7 1 Altera Corporation Arria 10 Transceiver PHY Overview 2013 12 02 UG A10XCVR S subscribe es Send Feedback This user guide provides details on the Arria 10 transceiver physical PHY layer architecture PLLs clock networks and transceiver PHY IP It also describes available transceiver features like reset controller dynamic reconfiguration and provides protocol specific implementation details Altera s Arria 10 devices offer up to 96 transceivers with integrated advanced high speed analog signal conditioning and clock data recovery techniques for chip to chip chip to module and backplane applications The Arria 10 GX and SX devices have GX tran
565. ve transceivers only on the left hand side of the device Legend PCle Gen1 Gen3 Hard IP blocks with CvP capabilities __ PCle Gen1 Gen3 Hard IP blocks without CvP capabilities C Arria 10 GX device with 48 transceiver channels and two PCle Hard IP blocks _ Arria 10 GX device with 36 transceiver channels and two PCle Hard IP blocks Arria 10 GX device with 24 transceiver channels and two PCle Hard IP blocks Altera Corporation Arria 10 Transceiver PHY Overview CJ Send Feedback UG A10XCVR z 1 7 2013 12 02 Arria 10 GT Device Transceiver Layout Figure 1 6 Arria 10 GX Devices with 12 Transceiver Channels and One PCle Hard IP Block CH5 CH4 i i A m Transceiver PCle Transceiver An Gen1 Gen3 CH2 Bank Hard IP CHI with CvP CHO Transceiver i ne Bank Note 1 These devices have transceivers only on the left hand side of the device Legend PCle Gen3 HIP blocks with CvP capabilities Arria 10 GX device with 6 transceiver channels and one PCle Hard IP block Figure 1 7 Arria 10 GX Devices with 6 Transceiver Channels and One PCle Hard IP Block Transceiver PCle Hard IP Transceiver Bank Note 1 These devices have transceivers only on the left hand side of the device Legend PCle Geni
566. ver Channels Altera Corporation CJ Send Feedback Arria 10 Transceiver PHY Architecture 2013 12 02 UG A10XCVR X lt Subscribe QC Send Feedback Arria 10 PMA Architecture The Physical Medium Attachment PMA acts as the analog front end for the Arria 10 transceivers The PMA receives and transmits high speed serial data depending on the transceiver channel configuration All serial data transmitted and received passes through the PMA Transmitter The transmitter takes the parallel data and serializes it to create a high speed serial data stream The transmitter portion of the PMA is composed of the transmitter serializer and the transmitter buffer The serializer clock is provided from the transmitter PLL Figure 5 1 Transmitter PMA Block Diagram Transmitter PMA Transmitter aenal Parallel Parallel Serial Differential Output Transmitter a si Data Transmitter Data FPGA Buffer A Seaizer eM pes Fabric Data Parallel Sen G a Transmitter Input eneration Clock lt Reference Block PLL Clock Serializer The serializer converts the incoming low speed parallel data from the transceiver PCS or FPGA fabric to high speed serial data and sends the data to the transmitter buffer The channel serializer supports the following serialization factors 8 10 16 20 32 40 and 64 2013 Altera Corporation All rights res
567. ver Layout 2013 12 02 Table 1 2 Data Rates Supported by GT Transceiver Channel Type Device Variant Chip to Chip Backplane GT 611 Mbps to 28 1 Gbps 611 Mbps to 17 4 Gbps Note The device data rates are dependent on the device speed grade Refer to Arria 10 Device Datasheet for details on available speed grades and supported data rates Related Information Arria 10 Device Datasheet Device Transceiver Layout Figure 1 1 Arria 10 FPGA Architecture Block Diagram The transceiver channels are placed on the left side periphery in most Arria 10 devices For larger Arria 10 devices additional transceiver channels are placed on the right side periphery a a I 2 2 o S Ea Ss Ss is fa x mo m m x Sita 3 G SIS o E fsi a iQ a oO 2 2 a oO 5 aoa aS S Ss Q 5 e03 E 2 5 2 3 5 2 g kig 2 5 2 5 L a g D a Be at T Be D S S E 2 S 2 amp ro ro Ec gt ij Eci S gt ov gt D gt g 2 O O oO a a kel me g i T an m pO o o oO oO 7 A o o g L es gt X lt gt x lt iit iit oO oO eT a Because the GT transceiver channels are designed for peak performance they do not have a reduced power mode of operation Altera Corporation Arria 10 Transceiver PHY Overview CJ Send Feedback U
568. ver mode e TX Simplex e RX Simplex Number of data channels 1 to 96 Data rate 125 Mbps to 10 Gbps Enable reconfiguration between Standard and Enhanced PCS On Off datapaths Enable simplified data interface On Off Table 2 148 TX PMA Parameters TX channel bonding mode Not bonded e PMA bonding e PMA PCS bonding PCS TX channel bonding master Auto 0 1 Actual PCS TX channel bonding master 0 1 TX local clock division factor 1 2 4 8 Number of TX PLL clock inputs per channel 1 2 3 4 Initial TX PLL clock input selection 0 Enable tx_pma_clkout port On Off Enable tx_pma_div_clkout port On Off tx_pma_div_clkout division factor Disabled 1 2 33 40 66 Enable tx_pma_elecidle port On Off Enable tx_pma_qpipullup port QPI On Off Enable tx_pma_qpipulldn port QPI On Off Enable tx_pma_txdetectrx port QPI On Off Enable tx_pma_rxfound port QPI On Off Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 248 Native PHY IP Parameter Settings for Basic Basic with Rate Match Configurations 2013 12 02 Table 2 149 RX PMA Parameters Number of CDR reference clocks 1 2 3 4 5 Selected CDR reference clock 0 1 2 3 4 Selected CDR reference clock frequency Legal range defined by Quartus II PPM detector threshold 62 5 100 125 200 250 300 500 1000 Decision feedback equalization mode e Disabled e Fix
569. wed by one K28 0 skip pattern in the LSByte of the next clock cycle The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback 2 242 How to Enable Low Latency in Basic UG A10XCVR 2013 12 02 Figure 2 120 Rate Match FIFO Becoming Full After Receiving the 20 Bit Word D5D6 tx_parallel_data 19 0 tx_paral rX_paralle rx_paral lel_data 9 0 data 19 10 lel_data 9 0 Xs d_rmfifo_ful X D2 X D4 y D1 X D3 x D2 X D4 y D1 X D3 Figure 2 121 Rate Match FIFO Becoming Empty After Reading out the 20 Bit Word D5D6 tx_parallel_data 19 0 tx_para rx_parallel rx_paral llel_data 9 0 data 19 10 llel_data 9 0 rx_std_rmfifo_empty 7 D2 X D4 y D1 X D3 y D2 X D4 y D1 X D3 How to Enable Low Latency in Basic In the Arria 10 Transceiver Native PHY IP Core MegaWizard use the following settings to enable low latency 1 Select the Enable Standard PCS low latency mode option PNA MN kW NY Select either low_latency or register FIFO in the TX FIFO mode list Select either low_latency or register FIFO in the RX FIFO mode list Select either Disabled or Serialize x2 in the TX byte serializer mode list Select either Disabled or Serialize x2 in the
570. ween the package and daughter card daughter card and connecter connector and backplane and so on Increasing the number of fixed taps can help mitigate these reflections However instead of having a large number of fixed taps it is more efficient to have a few fixed taps and some floating taps which can be positioned as needed DFE in Arria 10 transceivers has four floating taps and their location can be selected anywhere from 8 UI up to 64 UI Figure 5 12 DFE Floating and Fixed Taps 014 48 47 4 13 12 Yuyo 9 8 7y 65y 4 3 2 y 1 0 A 4 Floating Taps Can be Positioned Anywhere from Bit 8 to Bit 64 lt rid gt 7 Fixed Taps Current Bit On Die Instrumentation ODI On Die Instrumentation ODI provides on chip eye monitoring capabilities EyeQ Arria 10 Transceiver PHY Architecture Altera Corporation CJ Send Feedback UG A10XCVR 5 10 Clock Data Recovery CDR Unit 2013 12 02 This capability helps to both optimize link equalization parameters during board bring up and provide in system link diagnostics Figure 5 13 Receiver and ODI Architecture Receiver CTLE e DFE CDR gt j Deserializer gt To PCS FPGA Fabric Input 1 od inji i From FPGA Deserializer gt Fabric gt Logic Phase i i i Bit Error
571. winc_Incle 1 3 Out Tx omel Clik For Gen3 indicates whether the 130 bit block being transmitted is a Data or Control Ordered Set Block The following encodings are defined 2 b10 Data block 2 b01 Control Ordered Set block This value is read when rx_ blk_start 4 b0001 Refer to Section 4 2 2 1 Lane Level Encoding in the PCI Express Base Specification Rev 3 0 for a detailed explanation of data transmission and reception using 128b 130b encoding and decoding pipe_rx_blk_start Out tx_pma_clk For Gen3 specifies the start block byte location for RX data in the 128 bit block data Used when the interface between the PCS and PHYMAC FPGA Core is 32 bits Not used for Genl and Gen2 data rates Active High pipe_rx_data_valid Out tx_pma_clk For Gen3 this signal is de asserted by the PHY to instruct the MAC to ignore rx_parallel_data for one clock cycle A value of 1 b1 indicates the MAC should use the data A value of 1 b0 indicates the MAC should not use the data Active High pipe_rx_valid Out tx_pma_clk Asserted when RX data and control are valid pipe_phy_status Out ise joe CILie Signal used to communicate completion of several PHY requests Active High Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 212 How to Place Channels for PIPE Configurations 2013 12 02 When asserted the re
572. wing methods e Quartus II selected transmitter datapath interface clock e User selected transmitter datapath interface clock Receiver Data Path Interface Clocking The CDR block present in the PMA of each channel recovers the serial clock from the incoming data The CDR block also divides the recovered serial clock to generate the recovered parallel clock Both the recovered serial and the recovered parallel clocks are used by the deserializer The receiver PCS can use the following clocks based on the configuration of the receiver channel e Recovered parallel clock from the CDR in the PMA e Parallel clock from the clock divider used by the transmitter PCS if enabled for that channel Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR P 2013 12 02 Receiver Data Path Interface Clocking 3 37 Figure 3 14 Receiver Standard PCS and PMA Clocking Receiver PMA Receiver Standard PCS FPGA Fabric s Bg kd 2 e a 8 z zi gt Sp 2 gt z 9 23 a 2 Fy EIT n 8 a S a pal a o rx_coreclkin Parallel Clock I Recovered Ji rx_clkout ji tx_clkout D i Parallel Clock 12 14 rx_clkout or From Clock PRBS tx_clkout Divider Verifier m _pma_div_clkout Clock Generation Block CGB ATX PLL Clock Divider e CMU PLL
573. with 1588 configurations this signal is connected from the output of TX FIFO in the FPGA fabric Instantiate and configure your PLL Native PHY Reset Controller IP 7 Create a transceiver reset controller You can use your own reset controller or use the Arria 10 Transceiver Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller Figure 2 43 Connection Guidelines for a 10GBASE R or 10GBASE R with KR FEC PHY Design To MAC RS through XGMII Interface Reset RELIE Controller i 64d 8c Arria 10 Transceiver Native PHY Medium Altera Corporation Implementing Protocols in Arria 10 Transceivers CJ Send Feedback UG A10XCVR 2013 12 02 Native PHY IP Parameter Settings for 10GBASE R 10GBASE R with 1588 and 10GBASE R with KR FEC 2 99 Figure 2 44 Connection Guidelines for a 10GBASE R with 1588 PHY Design a To MAC RS PLL IP Reset through XG MII lt Controller Interface aada FIFO in the I i 8c FPGA core gt for Arria 10 Transceiver gt Native PHY lt ____ FIFO in the lt J 64d 8c FPGA core for RX 8 Simulate your design to verify its functionality Related Information e Arria 10 Enhanced PCS Architecture on page 5 14 For more information about Enhanced PCS architecture e Arria 10 PMA Architecture on page 5 1 Fo
574. x specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern The skip pattern must have neutral disparity Figure 2 114 Rate Match FIFO Deletion with Three Skip Patterns Required for Deletion First Skip Cluster Second Skip Cluster koe Three Skip Patterns Deleted Note K28 5 is the control patter and K28 0 is the skip pattern In this example the first skip cluster has a K28 5 control pattern followed by two K28 0 skip patterns The second skip cluster has a K28 5 control pattern followed by four K28 0 skip patterns The rate match FIFO deletes only one K28 0 skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion Two K28 0 skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement The rate match FIFO can insert a maximum of four skip patterns in a cluster if there are no more than five skip patterns in the cluster after insertion Figure 2 115 Rate Match FIFO Deletion with Three Skip Patterns Required for Insertion First Skip Cluster Second Skip Cluster tx paralel data Y K285 A K28 0 i K28 0 Y K28 0 y K28 5 Y K28 0 Y K28 0 y Dxy y i K28 0 y K28 0 i K28 0 Y Dxy y n paralel deta K28 5 K28 0 y K28 0 Three Skip Patterns Inserted In this example K28 5 is the control pattern and neutral disparity K28 0 is the skip patter
575. x_cal_busy is low You must reset the PCS by asserting rx_digitalreset every time you assert rx_analogreset 2 Deassert rx_analogreset after a minimum duration of 40 ns Ensure rx_is_lockedtodata remains asserted before deasserting rx_digitalreset 4 Deassert rx_digitalreset after rx_is_lockedtodata is asserted for a minimum duration of W tLTD Figure 4 6 Receiver Reset Sequence During Device Operation Device Power Up mic two clock cycles of reset o clock cycles of res rx_analogreset gt let analogreset ia i rx_digitalreset gt et tp rx_is_lockedtodata rx_cal_busy lockedtodata might toggle when there is no data at the receiver input Lockedtoref isa don t care when rx_is_lockedtodata is asserted Note rx_is_ rx_is_ Resetting the Transceiver in CDR Manual Lock Mode You can use the clock data recovery CDR manual lock mode to override the default CDR automatic lock mode depending on your design requirements The two control signals to enable and control the CDR in manual lock mode are rx_set_locktorefandrx_set_locktodata Follow this sequence to reset your transceiver when the CDR is in manual lock mode Control Settings for CDR Manual Lock Mode Use the following control settings to set the CDR lock mode Table 4 2 Control Settings for the CDR in Manual Lock Mode rx_set_locktoref rx_set_locktodata CDR Lock Mode 0 0 Automatic 1 0 Manual RX CDR LTR X 1 Man
576. x_dispval lt n gt lt w gt lt s gt eo Input Asynchronous Specifies the disparity of the data t x_ dispval isa part oftx_parallel_data tx_dispval corresponds to tx_ dispval 10 rx_datak lt n gt lt w gt lt s gt 1 0 Input rx_clkout When 1 indicates that the 8B 10B decoded word of rx_parallel_datais data When 0 indicates that the 8B 10B decoded word of rx_parallel_dataiscontrol rx_datak is part of rx_parallel_data For each 128 bit word rx_dat ak corresponds to rx_ parllel_data 8 Implementing Protocols in Arria 10 Transceivers GJ Send Feedback Altera Corporation UG A10XCVR 2 58 Standard PCS and PMA Ports 2013 12 02 rx_errdetect lt n gt lt w gt lt s gt Output rx_clkout When asserted indicates a code group 1 0 or rx_ violation detected on the received code group coreclkin Used along with rx_disperr signal to differentiate between code group violation and disparity errors the following encodings are defined for rx_errdetect rx_disperr e 2 b00 no error e 2 b10 code group violation e 2 b11 disparity error rx_errdetect is a part of rx_parallel_data For each 128 bit word rx_errdetect corresponds to rx_parallel_ daira 9 rx_disperr lt n gt lt w gt lt s gt Output rx_clkout When asserted indicates a disparity error on 1 0 orrx_ the received code group rx_disperr isa coreclkin part of rx_parallel_data For each 128 bit word rx_disperr c
577. x_enh__ On Off Enables the active high rx_enh_fifo_pfull port fifo_pfull port Enable rx_enh_ On Off Enables the active high rx_enh_fifo_empty port fifo_empty port Enable rx_enh__ On Off Enables the rx_enh_fifo_pempty port fifo_pempty port Enable rx_enh_ On Off Enables the optional rx_enh_fifo_cnt status output port fifo_cnt port Enable rx_enh__ On Off Enables the optional rx_enh_del_cnt status output port fifo_del port 10GBASE R Enable rx_enh__ On Off Enables the rx_enh_fifo_insert port fifo_insert port 10GBASE R Enable rx_enh_ On Off Enables the rx_enh_fifo_rd_en input port fifo_rd_en port Interlaken Enable rx_enh_ On Off Enables the rx_enh_fifo_align_val status output port fifo_align_val port Interlaken Enable rx_enh_ On Off Enables the rx_enh_fifo_align_clr input port fifo_align_clr port Interlaken Table 2 11 Interlaken Frame Generator Parameters Enable Interlaken On Off Enables the frame generator block of the Enhanced PCS frame generator Frame generator 5 8192 Specifies the metaframe length of the frame generator This metaframe length metaframe length includes 4 framing control words created by frame generator Enable frame On Off Enables frame generator burst This determines whether the frame burst generator reads data from the TX FIFO based on the input of port tx_enh_frame_burst_en Enable tx_enh_ On Off Enables the tx
578. xample e Enable Include Master Clock Generation Block and turn ON Enable high frequency serial clock output port 3 Configure the Native PHY IP using the MegaWizard Plug In Manager e Set the Native PHY IP TX Channel bonding mode to Non Bonded e Set the number of channels as per your design requirement In this example the number of channels is set to 10 4 Connectivity PLLs and Clock Networks Altera Corporation CJ Send Feedback UG A10XCVR 3 44 Bonded configurations 2013 12 02 e Create a top level wrapper to connect the PLL IP to Native PHY IP e In this case the PLL IP has mcgb_serial_clk output port This represents the xN clock line e The Native PHY IP has 10 for this example tx_serial_clk input ports Each port corresponds to the input of the local CGB of the transceiver channel e As shown in the figure above connect the mcgb_serial_clk output port of the PLL IP to the 10 tx_serial_clk input ports of the Native PHY IP Figure 3 20 Multi Channel x1 xN Non Bonded Example PLL IP hasatx_serial_clk output port This port can optionally be used to clock the six channels within the same transceiver bank as the PLL These channels are clocked by the x1 network The remaining four channels outside the transceiver bank are clocked by the xN clock network This is shown in the following figure Transceiver PLL Native PHY Instance Instance 5 GHz 10 CH Non Bonded
579. xample instantiates the 1G 10GbE PHY IP along with the 1G 10G Ethernet MAC and supporting logic It is part of the Quartus II 13 1 installation and is located in the lt quartus2_install_dir gt ip subdirectory For more information about this example design refer to the Ethernet MAC MegaCore Function User Guide A design example that includes on the PHY instantiates the 1G 10G PHY and its supporting logic This design example is available on the Altera wiki The following figure shows the block diagram of the 1G 10GbE PHY only design example The default configuration includes two channels for backplane Ethernet and two channels for line side 1G 10G applications Implementing Protocols in Arria 10 Transceivers Altera Corporation GJ Send Feedback 2 178 Simulation Support Figure 2 65 1G 10GbE PHY Only Design Example UG A10XCVR 2013 12 02 NF_DE_WRAPPER Test Harness THO_ADDR OxFnnn Management Master TTAG to Test Harness TH1_ADDR OxEnnn ISSP Avalon MM XGMI XGMII XGMI XGMII es Master Source Sink GEN CHK Clock and Reset XGMII 1G 10GbE P
580. y GX Transceiver Channels Standard PCS 611 Mbps up to 10 Gbps Enhanced PCS 611 Mbps up to 17 4 Gbps PCIe Gen3 PCS 8 Gbps Note The GX channel can also operate in PCS Direct configuration for data rates from 611 Mbps to 17 4 Gbps Altera Corporation Arria 10 Transceiver PHY Overview J Send Feedback UG A10XCVR 2013 12 02 The GT Transceiver Channel 1 19 The GT Transceiver Channel The GT transceiver channels are used for supporting data rates from 17 4 Gbps to 28 1 Gbps The GT transceiver channels can also be reconfigured as GX transceiver channels When they are reconfigured as GX transceiver channels the Standard PCS Enhanced PCS and PCIe Gen3 PCS are available and they support data rates from 611 Mbps to 17 4 Gbps Figure 1 18 GT Transceiver Channel in Full Duplex Mode Operating Between 17 4 Gbps and 28 1 Gbps Transmitter PMA Transmitter PCS FPGA Fabric Standard PCS 4 PCle Gen3 PCS 4 2 lt H Serializer 2 tt er eS Receiver PMA Receiver PCS StandardPCS 4 PCle Gen3 PCS 4 2 H gt CDR H gt Deserializer Notes 1 The Enhanced PCS must be configured in lowl latency mode to support data rate range from 17 4 Gbps to 28 1 Gbps 2 The FPGA Fabric PCS and PCS PMA interface widths are configurable 3 PCS Direct support will be a
581. y of this clock could be from datarate 67 to datarate 32 However if the frequency is too much lower than t x_ clkout the TX FIFO flags may be unable to update in time and cause data corruption tx_clkout Output Clock The parallel clock generated by the transceiver TX PMA This clock times the blocks of the TX Enhanced PCS The frequency of this clock is equal to datarate divided by PCS PMA interface width tx_serial_ data Output N A Serial data output from the TX PMA tx_serial_clk0 Input Clock Serial Clock input from the TX PLL For non bonded channels only The frequency of this clock depends on the data rate and clock division factor tx_serial_ c1k0 is for non bonded channels only For bonded channels use the tx_bonding_clocks clock TX input tx_bonding_ Clocks lt ma gt lt 65 11 20 Input Clock 6 bit bus which carries the low speed parallel clock per channel Outputs from the Master CGB Use for bonded channels only Optional Ports Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 42 Enhanced PCS and PMA Ports 2013 12 02 tx_serial Inputs Clocks Serial Clock inputs from the TX PLL The frequency k ial elk of this clock depends on the data rate and clock AES division factor When you specify more than 1 TX ex serial clk PLLs these additional clock ports are enabled tiser likelka
582. y use the dedicated GT clocks instead of the x1 clock network Note The Quartus II software version 13 1 does not perform legality checks for PCS to FPGA Fabric speeds The transceiver data rate is checked but the PCS to FPGA fabric data rate can be set too high For example if the PCS PMA interface width is less than 40 bits for data rates above 17 4Gbps then the PCS to FPGA fabric data rate can be set too high PCS interface legality checking will be available in a future release of the Quartus II software Implementing Protocols in Arria 10 Transceivers Altera Corporation CJ Send Feedback UG A10XCVR 2 256 Simulating the Transceiver Native PHY IP Core 2013 12 02 Simulating the Transceiver Native PHY IP Core Use simulation to verify the Native PHY transceiver functionality The Quartus II software supports register transfer level RTL and gate level simulation in both ModelSim Altera and third party simulators You run simulations using your Quartus II project files The following simulation flows are available e NativeLink with ModelSim Altera This flow simplifies simulation by allowing you to start a simulation from the Quartus II software This flow automatically creates a simulation script and compiles design files IP simulation model files and Altera simulation library models e Custom Flow This flow allows you to customize simulation for more complex requirements You can use this flow to compile design files IP sim
583. ynamic phase shift block allows the user to adjust the phase of the M and C counters in user mode In fractional mode dynamic phase shift is only available for the C counters Latency The fPLL contains a 1 ns delay with 50 ps resolution on each C M and N counter In addition there is a 7 ns delay with 1 ns resolution on both the reference clock and feedback clock paths The C and M counters can be configured to select any VCO phase and a delay of up to 128 clock cycles The selected VCO phase can be changed dynamically The M counter s phase cannot be changed in fractional mode Altera Corporation PLLs and Clock Networks CJ Send Feedback UG A10XCVR 2013 12 02 Instantiating fPLL IP Instantiating fPLL IP 3 13 The fPLL IP for Arria 10 transceivers provides access to fPLLs in hardware One instance of PLL IP represents one fPLL in hardware Sr e ae Se Open the Quartus II software Click Tools gt MegaWizard Plug In Manager Select the Arria 10 device family Select PLL in the Installed Plug Ins tree Choose Arria 10 fPLL In What name do you want for the output file browse to the location where you want to save your design and enter a filename Click Next The fPLL IP MegaWizard Plug In Manager window opens fPLL IP The fPLL configuration options and parameters are listed in the following tables Table 3 7 fPLL Parameters and Settings Device speed grade fastest Specifies the desired devic
584. ynchronous output signal Enable rx_is_ On Off Enables the optional rx_is_lockedtoref status output port lockedtoref port This signal indicates that the RX CDR is currently locked to the CDR reference clock This is an asynchronous output signal Enable rx_set_ On Off Enables the optional rx_is_lockedtodata and rx_set_ lockedtodata port lockedtoref control input ports You can use these control and rx_set_ ports to manually control the lock mode of the RX CDR These lockedtoref ports are asynchronous input signals Enable rx_ On Off Enables the optional rx_seriallpbken control input port seriallpbken port When you assert this port rx_seriallpbken the TX to RX serial loopback path is enabled This is an asynchronous input signal Enable PRBS On Off Enables the optional rx_prbs_err rx_prbs_clr andrx_ verifier control prbs_done control ports These ports control and collect status and status port from the internal PRBS verifier Implementing Protocols in Arria 10 Transceivers CJ Send Feedback Altera Corporation UG A10XCVR 2 22 Enhanced PCS Parameters 2013 12 02 Related Information PLLs and Clock Networks on page 3 1 Enhanced PCS Parameters This section defines parameters available in the Transceiver Native PHY GUI to customize the individual blocks in the Enhanced PCS You can implement the following protocols using the Enhanced PCS e Ethernet 1OGBASE R and 1OGBASE KR e Interlaken e SFI S and SFI 5 2 e 10G SDI

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