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Stratix IV GX FPGA Development Kit, 530 Edition User Guide

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1. PSR Sets the MAX II PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 6 Chapter 6 Board Test System Using the Board Test System PSS Displays the MAX II PSS register value Refer to Table 6 1 for the list of available options SRST Resets the system and reloads the FPGA with a design from flash memory based on the other MAX II register values Refer to Table 6 1 for more information 7 Because the Config tab requires that a specific design is running in the FPGA writing 0 to SRST or changing the PSO value can cause the Board Test System to stop running JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Stratix IV GX device is always the first device in the chain E Setting DIP switch SW6 1 to the off position includes the MAX II device in the chain Flash Memory Map The Flash memory map control shows the memory map of the flash memory device on your board Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 7 Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the LCD read
2. Switch gredi Function BM Switch 3 has the following options 3 LCD PWRMON m When on the LCD is driven from the MAX II device On m When off the LCD is driven from the FPGA Switch 4 has the following options 4 FAN FORCE ON m When on the fan is forced on at full speed Off m When off the fan speed is controlled by the MAX1619 device Switch 5 has the following options 5 CLK SEL m When the 100 MHz oscillator input is selected On m When off the SMA input is selected Switch 6 has the following options 6 CLK ENABLE m When on the on board oscillator is enabled On m When off the on board oscillator is disabled Switch 7 has the following options 7 S4VCCH_SEL m When 1 4 V is selected On m When off reserved Switch 8 has the following options 8 S4VCCA SEL m When on 3 3 V is selected On m When off 2 5 V is selected 4 Set DIP switch bank SW5 to match Table 4 3 and Figure 4 2 Table 4 3 SW5 Dip Switch Settings Switen Board Function Position Switch 1 has the following options 1 PCIE PRSNT2n x1 m When on x1 presence detect is enabled Off m When off x1 presence detect is disabled Switch 2 has the following options 2 PCIE PRSNT2n x4 m When on x4 presence detect is enabled Off m When off x4 presence detect is disabled Switch 3 has the following options 3 PCIE PRSNT2n x8 m When on x8 presence detect is enabled Off m When off x8 presence detect is disabled Switch 4 has the following op
3. 5 2 Chapter 6 Board Test System Preparing the Boardi d Tue qure LUI I M ee 6 3 Running the Board Test System 6 3 Using the Board Test System 6 4 Th Configure PER Pete eae eyed equ yas peas dec 6 4 ui ouod tette uuu ULP DI MIU 6 4 Board Intormation isset eh rm RA eO EU ahead C UNA RR edd 6 5 MAX IDReSISEetS aiite cachet scent etes taut vag 6 5 JTAG Chain 23 REP Yury be EE dde eee 6 6 Flash Memory re ear SEO ae PTT er Se Et 6 6 GPIO Tab EREN ere pre RE Ru end 6 7 Character LOD 6 7 User DIP Switches eeu RR 6 7 User LEDS crre 6 8 Push Button Switches bes p RR Rn steeds led 6 8 Jhe5RAMGEHlash Tab eere Merten a tetas E 6 8 SRAM i een oye exe pes valet _________ ______ be 6 9 Flash P PE 6 9 The DDR3 Tab er Rete bp E Rep EPERE
4. Vee 6 15 Pr 6 15 Error Control 42 e reb 2 6 15 SAFE PEREAT 6 16 SLOP d eas 6 16 Performance Indicators 1 5 4 6 16 The Video Tab teed 6 17 HDMI 225 a a a oea 6 18 6 19 The Power pea eed wag 6 19 General Information 5 54 e AR ER anwar es 6 20 Temperature 6 21 Power Informations e bode Peete E peed Ped 6 21 12 V Power Consumption 1 1 2 7 7 6 21 Power Graph nee ere gabe deba 6 21 Graph ee Eee p ar ewe WEES 6 21 mc LT 6 21 Calculating POWEL c DI eR eh cU CDU CI dE 6 22 The Clock Control 222m ER sates es 6 22 Serial Port Registers sec sk ak EP E Y hr ad b 6 23 IXTAL Peet ddan be Ep ad ned E oed edie dees
5. r Data type PRBS Memory Math Read and write control Write then read Read only C Write only The following sections describe the controls on the DDRS tab Port The Port control directs communication to one of two DDR3 memory ports on your board A 16 bit interface connects to the top bank of the Stratix IV GX FPGA and a 64 bit interface connects to the bottom banks of the FPGA Start The Start control initiates DDR3 memory transaction performance analysis Stop The Stop control terminates transaction performance analysis Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 11 Using the Board Test System Performance Indicators These controls display current transaction performance analysis information collected since you last pressed Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve Write MBps Read MBps and Total MBps Show the number of bytes of data analyzed per second The top port data bus is 16 bits wide and the frequency is 533 MHz double data rate 1066 Mbps per pin equating to a theoretical maximum bandwidth of 2132 MBps The bottom port data bus is 64 bits wide and the frequency is 533 MHz double data rate 1066 Mbps per pin equating to a theoretical maximum bandwidth of 8528 M
6. 1 About This Kit Kit Features oerte tied ber ae 1 1 Hardware nF cites 1 1 von P DOLUS 1 2 Quartus II Subscription Edition Software 1 2 Stratix IV GX FPGA Development Kit 530 Edition Installer 1 3 Chapter 2 Getting Started Betore ed ae 2 1 Inspect the Board e bre ebd Sede eet tant 2 1 2 PE m 2 2 Chapter 3 Software Installation Installing the Quartus II Subscription Edition Software 3 1 Licensing Considerations ERR EH E E RR a ed pete na eoe 3 1 Installing the Stratix IV GX FPGA Development Kit 530 Edition 3 2 Installing the USB Blaster Driver 3 3 Chapter 4 Development Board Setup aa deir meu MULUS c a een 4 1 Factory Default Switch Settings 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page 5 1 Using the Board Update Portal to Update User Designs
7. 530 Edition Reference Manual Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 23 The Clock Control The Clock Control communicates with the MAX II device on the board through the JTAG bus The Si570 programmable oscillator is connected to the MAX II device through 2 wire serial bus Figure 6 11 shows the Clock Control Figure 6 11 The Clock Control FAN clock Control 1 NU S 24 Disable oscillator Serial port registers Target frequency HS DIV 9 100 us 1 6 Valid frequency range values are 10 00000000 810 00000000 MHz RFREQ O2f39bf56e FXTAL 114 3448 MHz Reset Si570 USB Blaster on localhost USB 0 EPM 221082 Messages The following sections describe the Clock Control controls Serial Port Registers The Serial port registers control shows the current values from the 51570 registers For more information about the 51570 registers refer to the Si570 Si571 datasheet available on the Silicon Labs website www silabs com fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values T For more information about the fyrar value and how it is calculated refer to the 51570 51571 datasheet available on the Silicon Labs website www silabs com Disable Oscillator The Disable oscillator enables and dis
8. DIP switch settings turn LEDs on or off and detect push button presses Figure 6 3 shows the GPIO tab Figure 6 3 GPIO Tab ff Board Test System Configure Help About Config GPIO SRAM amp FIash DORA CORTA 5 vides ANU amp RYAN Character LCD eem stratisrv Gx 530 GNE Development Kit Power Monitor r User DIP switch S EN CE s I por Pon User LEDs rur All Messages Detected GPIO SRAM Flash Project r Push button switches The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display 7 Ifyou exceed the 16 character display limit on either line warning message appears User DIP Switches The read only User DIP switches control displays the current positions of the switches in the user DIP switch bank SW3 Change the switches on the board to see the graphical display change accordingly November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 8 User LEDs Chapter 6 Board Test System Using the Board Test System The User LEDs control displays the current state of the user LEDs Click the graphical representation of the LEDs to turn the board LEDs on and off Push Button Switche
9. development board Make sure you have the Nios IT EDS installed and perform the following instructions 1 10 11 12 13 Set the board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 24 for more information Click Add File and select install dir gt kits stratixIVGX_4s x530_fpga factory_recovery s4sg x530_fpga_ bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The CONF DONE LED D5 and the eight lower user LEDs D16 D23 illuminate indicating that the flash device is ready for programming On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell In the Nios command shell navigate to the install dir gt kits stratixIVGX_4sgx530_fpga factory_recovery directory and type the following command to run the restore script restore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes cycle the POWER switch SW1 off then on Using the Quartus II Programmer click Add File and sel
10. progressive m 720p 1280 x 720 progressive Start Initiates the test Stop Terminates the test Get EDID Reads the extended display information data EDID from the monitor and displays the results Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 19 The Power Monitor SDI Testing the SDI requires connecting a SMB loopback cable as shown in Figure 6 9 Figure 6 9 Board with SMB Loopback Cable Once connected the following controls are available m Reset Restarts the test Load Passes a new seed value to the PRBS generator on the device m Status Displays the following status information during the loopback test Tx PLL Shows whether the Tx PLL is locked or unlocked Rx PLL Shows whether the Rx PLL is locked or unlocked Error status Shows No Error Detected when the test is running correctly otherwise shows pertinent error m Error control Provides the following controls to display data errors detected during analysis and allow you to insert errors m Errors Displays the number of errors detected in the hardware m Insert Error Inserts a one word error into the transaction stream each time you click the button m Clear Resets the Errors counter to zero The Power Monitor The Power Monitor measures and reports current power and temperature information for the board To start the application cli
11. 4000000 to Ox07FFFFFF flash memory address space a warning message identifies the valid flash memory address range To update the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents To prevent overwriting the dedicated portions of flash memory the application limits the writable flash memory address range from 0x07FE0000 to Ox07FFFFFF which corresponds to the unused flash memory address range of 0x03FE0000 shown in Figure 6 1 on page 6 2 and Table 1 on page A 1 November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 10 Chapter 6 Board Test System Using the Board Test System The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board Figure 6 5 shows the DDR3 tab Figure 6 5 The DDR3 Tab ARAT Test System xl Configure Help About cero ERESHE DDR3 Gone ATERA B e P Bottom Start Stop Power Monitor Write Read Total Write MBps 992 6758 Read MBps 987 8710 Total MBps 1980 5468 Error control Detected Errors 0 Inserted Errors 0 Insert Error Clear of addresses to write and read Messages Min Detected DDR3 Project
12. 6 23 Disable OscillatoE o e RE ER RR RR MEER S Eid 6 23 Target Prequency de e deb e CREE band iced ed Ede ae o es 6 24 Reset ONO 0 6 24 Set New Erequency eoe ye kad e een pce ede o e elo ace rato E un 6 24 Configuring the FPGA Using the Quartus II Programmer 6 24 Appendix A Programming the Flash Memory Device CFI Flash Memory Map eter Per ate Eee be AW PE Roe E pee bie eee toss A 1 Preparing Design Files for Flash Programming 1 A 2 Creating Flash Files Using the Nios EDS 2 Programming Flash Memory Using the Board Update Portal A 2 Programming Flash Memory Using the Nios 5 A 3 Restoring the Flash Device to the Factory Settings A 4 Restoring the MAX II CPLD to the Factory Settings A 5 Additional Information Document Revision History i cessere eee Hen e ue ia qe Re Info 1 How to Contact Altera 2 Info 1 Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Contents i Typographic Conventio
13. About This Kit 1 3 Kit Features m MegaCore IP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware gt The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production St For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions Nios Embedded Design Suite EDS A full featured set of tools that allow you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Stratix IV GX FPGA Development Kit 530 Edition Installer The license free Stratix IV GX FPGA Development Kit 530 Edition installer includes all the documentation and design examples for the kit Download the Stratix GX FPGA Development Kit 530 Edition installer from the Stratix IV GX FPGA Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website No
14. Bps 7 Performance figures are based on 100 MHz input clock from programmable oscillator Using the The Clock Control on page 6 22 to adjust the frequency changes the circuit speed in real time and the DDR3 tab performance indicators which are capped at 100 for increased frequencies Physical layer speeds equal the oscillator X6 frequency times the input PLL multiplier ratio The default is 533 MHz 100 MHz x 5 33 or 1066 Mbps per pin Changing the oscillator X6 frequency to 125 MHz changes the circuit speed to 667 MHz or 1333 Mbps per pin Typically you need to reset the DDR3 design after changing the clock frequency Error Control The Error control controls display data errors detected during analysis and allow you to insert errors Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transaction stream Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes Valid values range from 2 to 16 777 216 Data Type The Data type control specifies the type of data c
15. DEEP Ride ee mde tpe eg 6 10 POE css tercer ep CD ESO ebrius eed quie esses rd seda 6 10 qud Re Pee hes ______ 6 10 na See EEE TP 6 10 November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide iv Contents Performance Indicators 2000 bc e cuban cages 6 11 Error Control CK C 6 11 Number of Addresses to Write and Read 6 11 Data rM 6 11 Read and Write Control 2 suede 6 12 The he pac e x Re bre aceite dba cec Ete 6 12 ted ve Sek a DE 6 13 urn ge 6 13 SOPs mieu s Sees ci tsi rence tee 6 13 Performance Indicators 2 6 13 Error Control sesers bad etree hes XX RA Ru x Aa EXON a e ee eee A 6 13 Number of Addresses to Write and Read 6 13 rm 6 14 voie attese ache Me die eam dake 6 14 Status ee alps Pare
16. Licensing Center page of the Altera website log into or create your myAltera account and take the following actions 1 Onthe Activate Products page enter the serial number provided with your development kit in the License Activation Code box November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 3 2 Chapter 3 Software Installation Installing the Stratix GX FPGA Development Kit 530 Edition Your serial number is printed on the development kit box below the bottom bar code The number is 10 or 11 alphanumeric characters and does not contain hyphens Figure 3 1 shows the correct serial number such as 351505 Figure 3 1 Locating Your Serial Number DK DSP 3SL150 YY LOT XXXXX 38150SPXXXX 2 Consult the Activate Products table and to determine how to proceed follow one of these steps m Ifthe administrator listed for your product is someone other than you skip the remaining steps and contact your administrator to become a licensed user m Ifthe administrator listed for your product is you proceed to step 3 m Ifthe administrator listed for your product is Stocking activate the product making you the administrator and proceed to step 3 3 Use the Create New License page to license your product for a specific user you on specific computers The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing
17. PGA Development Kit 530 Edition Installed Directory Structure 7 lt install dir gt The default Windows installation directory is C altera lt version gt kits stratixIVGX_4sgx530_fpga board_design_files D demos o documents D examples factory_recovery Note to Figure 3 2 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Table 3 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a board uesign Hips starting point for a new prototype board design demos Contains demonstration applications documents Contains the kit documentation examples Contains the sample design files for the Stratix IV GX FPGA Development Kit 530 Edition Contains the original data programmed onto the board before shipment Use this data to restore factory the board with its original factory contents Installing the USB Blaster Driver The Stratix GX FPGA development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the USB Blaster driver on the host computer T Installation instructions for the USB Blaster driver for your operating system a
18. Stratix FPGA Development Kit 530 Edition contents The Stratix IV GX FPGA Development Kit 530 Edition includes the following hardware Stratix IV GX FPGA development board A development platform that allows you to develop and prototype hardware designs running on the Stratix IV GX EP4SGX530N FPGA For detailed information about the board components and interfaces refer to the Stratix IV GX FPGA Development Board 530 Edition Reference Manual HSMC loopback board A daughtercard that allows for loopback testing all signals on the HSMC interface using the Board Test System HSMC debug breakout board A daughtercard that routes 40 CMOS signals to a 0 1 header and adds 20 LEDs to the remaining 40 CMOS signals November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide Software Chapter 1 About This Kit Kit Features m Power supply and cables The kit includes the following items Power supply and AC adapters for North America Japan Europe and the United Kingdom USBcable Ethernet cable m 75 QSMB video cable The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to have Altera mail the software to you on DVDs Quartus Il Subscription Edition Software The Quartus II Subscription Edition Software is a licensed set of Altera tools with full functionality Your kit includ
19. Stratix IV GX FPGA Development Kit 530 Edition User Guide 101 Innovation Drive San Jose CA 95134 www altera com UG 01095 1 0 gt lt Subscribe Copyright 2010 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo and specific device designations are trademarks and or service marks of Altera Corporation in the U S and other countries All other words and logos identified as trademarks and or service marks are the property of Altera Corporation or their respective owners Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the appfication or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services QUALITY 150 9001 2008 NSAI Certified Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation N DTE RYN Contents Chapter
20. ables the 51570 output buffer Turn on Disable oscillator to power down the 51570 output buffer Turn off the Disable oscillator to drive the 51570 output buffer normally November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 24 Chapter 6 Board Test System Configuring the FPGA Using the Quartus Programmer Target Frequency The Target frequency control allows you to specify the frequency of the clock Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possible within 100 parts per million ppm The Target frequency control works in conjunction with the Set New Frequency control Reset Si570 The Reset 51570 control sets the Si570 programmable oscillator to the default frequency of 100 MHz Set New Frequency The Set New Frequency control sets the 51570 programmable oscillator frequency to the value in the Target frequency control Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Configuring the FPGA Using the Quartus Programmer You can use the Quartus IT Programmer to configure the FPGA with a specific sof Before configuring the FPGA ensure that the Quartus Programmer and the USB Blaster driver are installed on the host computer the USB cable is connected t
21. al Information The General information controls display the following information about the MAX II device version Indicates the version of MAX II code currently running on the board The MAX II code resides in the install dir NkitsNstratixXIVGX 4sgx530 fpgaMfactory recovery and install dir gt kits stratixIVGX_4sgx530_fpga examples max2 directories Newer revisions of this code might be available on the Stratix IV GX FPGA Development Kit page of the Altera website Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 21 The Power Monitor m Power rail Indicates the currently selected power rail The rotary switch SW2 on your board controls which rail to measure After setting the switch for the desired rail click Reset to refresh the screen with new board readings T A table with the power rail switch positions is available in the Stratix IV GX FPGA Development Board 530 Edition Reference Manual Temperature Information The Temperature information controls display the following temperature readings for the board and the FPGA on the board m FPGA Indicates the temperature of the FPGA device m Board lIndicates the overall board temperature Power Information The Power information control displays current maximum and minimum power readings for the following units m mVolt mAmp mg mWatt 12 V Power Consumption Th
22. al to Update User Designs The Board Update Portal allows you to write new designs to the user hardware portion of flash memory Designs must be in the Nios II Flash Programmer File flash format gt Design files available from the Stratix IV GX FPGA Development Kit page of the Altera website include flash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page 2 for information about preparing your own design for upload To upload a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page 2 Inthe Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank 3 Click Upload The progress bar indicates the percent complete 4 Toconfigure the FPGA with the new design after the flash memory upload process is complete set the rotary switch SW2 to the 1 position and power cycle the board or press the CONFIG button S1 La As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write ne
23. aphic Conventions Visual Cue Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important c The hand points to information that requires special attention 2 A question mark directs you to a software help system with related information Is The feet direct you to another document or website with related information CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible sit
24. ays the following status information during the loopback test PLL lock Shows the PLL locked or unlocked state Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected Port The Port control allows you to specify the type of test to run on the HSMC ports The following HSMC port tests are available HSMA 4 Tranceivers 0 3 HSMA 4 Tranceivers 4 7 m 4 Tranceivers 0 3 HSMB x2 Tranceivers 4 5 HSMA x17 LVDS SERDES HSMB x17 LVDS SERDES HSMA x3 Single Ended Loopback HSMB x3 Single Ended Loopback Data Type The Data type control specifies the type of data contained in the transactions and only applies to transceivers The following data types are available for analysis m PRBS7 Selects pseudo random 7 bit sequences m PRBS15 Selects pseudo random 15 bit sequences m PRBS23 Selects pseudo random 23 bit sequences PRBS31 Selects pseudo random 31 bit sequences Error Control The Error control controls display data errors detected during analysis and allow you to insert errors m Detected errors Displays the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream m Insert Error Inserts a one word
25. ck Power Monitor in the Board Test System application gt You can also run the Power Monitor as a stand alone application PowerMonitor exe resides in the install dir NkitsNstratixXIVGX 4sgx530 fpgaNexamplesNboard test system directory On Windows click Start gt All Programs gt Altera gt Stratix IV GX FPGA Development Kit 530 Edition lt version gt gt Power Monitor to start the application November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 20 Chapter 6 Board Test System The Power Monitor The Power Monitor communicates with the MAX II device on the board through the JTAG bus A power monitor circuit attached to the MAX II device allows you to measure the power that the Stratix IV GX FPGA device is consuming regardless of the design currently running Figure 6 10 shows the Power Monitor Figure 6 10 The Power Monitor A Power Monitor Oj xl Power information RYA RMS Maximum Minimum mivolt 892 892 892 General information ieee LENS MAX II version 2 4062 4065 3599 Power 54 mWatt 3627 3629 3213 Temperature information 12 V power consumption FPGA 389 C Board 31 2107 25280 mw 10000 mw 5000 m a M 8229005 Graph settings USB Blaster on localhost USB 0 Scale select Update speed frat Reset The following sections describe the Power Monitor controls Gener
26. ctory Default Switch Settings on page 4 2 57 Setting DIP switch SW6 1 to the off position includes the MAX II device in the JTAG chain Launch the Quartus II Programmer Click Auto Detect Click Add File and select install dir NkitsNstratixIVGX 4sgx530 fpgaMfactory recovery max2 pof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the MAX II CPLD Configuration is complete when the progress bar reaches 100 that you have the most up to date factory restore files and information about this product refer to the Stratix IV GX FPGA Development Kit page of the Altera website November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide A 6 Chapter Restoring the MAX II CPLD to the Factory Settings Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes November 2010 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera c
27. e 12 V Power consumption control displays 12 V power consumption readings for the following units mA B mW Power Graph The power graph displays the mWatt power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset The yellow line indicates the minimum value read since the last reset Graph Settings The following Graph settings controls allow you to define the look and feel of the power graph m Scale select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the entire range of recorded values m Update speed Specifies how often to refresh the graph Reset This Reset control clears the graph resets the minimum and maximum values and restarts the Power Monitor November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 22 Chapter 6 Board Test System The Clock Control Calculating Power The Power Monitor calculates power by measuring two different voltages with the LT2418 A D and applying the equation P V x I to determine the power consumption The LT2418 measures the voltage after the appropriate sense resistor Vsense and the voltage drop across that sense resistor Vdif The current 1 is calculated by dividing the measured voltage drop across the resistor by the value of the sense resis
28. ect lt install dir NkitsNstratixIVGX 4sgx530 fpgaMfactory recovery Ns4sgx530 fpga bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The CONF DONE LED D5 and the eight lower user LEDs D16 D23 illuminate indicating the flash memory device is now restored with the factory contents Cycle the POWER switch SW1 off then on to load and run the restored factory design The restore script cannot restore the board s MAC address automatically In the Nios II command shell type the following Nios II EDS command nios2 terminal and follow the instructions in the terminal window to generate a unique MAC address Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 5 Restoring the MAX II CPLD to the Factory Settings that you have the most up to date factory restore files and information about this product refer to the Stratix IV GX FPGA Development Kit page of the Altera website Restoring the MAX CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX II CPLD on the FPGA development board Make sure you have the Nios II EDS installed and perform the following instructions 1 Set the board switches to the factory default settings described in Fa
29. ent power and temperature information for the board Because the application communicates over the JTAG bus to the MAX II device you can measure the power of any design in the FPGA including your own designs 7 The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap Embedded Logic Analyzer Because the Quartus programmer uses most of the bandwidth of the bus other applications using the bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 3 Preparing the Board Preparing the Board With the power to the board off perform the following steps 1 Connect the USB cable to the board 2 Verify the settings for the board settings DIP switch bank SW4 match Table 4 2 on page 4 3 3 Set the rotary switch SW2 to the 1 position 4 Verify the settings for the JTAG DIP switch bank SW6 located on the back of the board match Table 4 4 on page 4 5 These settings determine the devices to include in the JTAG chain St For more information about the board s DIP switch and jumper settings refer to the Stratix IV GX FPGA Development Board 530 Edition Reference Manual 5 Turn the power to the board on The board loads the design sto
30. error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 16 Chapter 6 Board Test System Using the Board Test System Start The Start control initiates HSMC transaction performance analysis Stop The Stop control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve Tx MBps and Rx MBps Show the number of bytes of data analyzed per second The HSMA 7 4 HSMA 3 0 and HSMB 3 0 transceiver buses are 4 bits serial channels wide and clocked using the 100 MHz oscillator with a PLL multiplier of 20 the data rate is 2 Gbps totaling 8 Gbps per transceiver port The LVDS SERDES bus is 17 bits wide The HSMC x17 SERDES buses on both HSMC and B 17 bits wide and clocked using the 125 MHz oscillator with a PLL multiplier of 13 equating to a 1 625 Gbps per pin or a 27 625 Gbps bandwidth for each x17 SERDES port The HSMB 5 4 transceiver bus is 2 serial channels wide and the total data rate is 4 Gbps
31. es a development kit edition DKE license for the Quartus II software Windows platform only This license entitles you to all the features of the subscription edition for a period of one year After the year you must purchase a renewal subscription to continue using the software For more information refer to the Altera website www altera com Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website The Quartus II Subscription Edition Software includes the following items m Quartus Software The Quartus II software including the SOPC Builder system development tool provides a comprehensive environment for system on a programmable chip SOPC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools St The kit includes a development kit edition license for the Quartus software Windows platform only This license entitles you to all the features of the subscription edition for a period of one year After the year you must purchase a renewal subscription to continue using the software For more information refer to the Altera website www altera com Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 1
32. esign example and a default user configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios II EDS just as the hardware design was created using the Quartus II software For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map CAUTION Table 1 shows the default memory contents of the 512 Mb 64 MB single die CFI flash device For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered Table A 1 Byte Address Flash Memory Map Block Description Size Address Range Unused 32 KB 0 03 0000 OxO3FFFFFF User software 11 797 0x034A0000 OxO3FDFFFF User hardware 21 627 KB 0x02000000 0x0349FFFF zipfs html web content 5 898 0x01A60000 0x01 FFFFFF Factory software 5 898 0x014C0000 0x01 A5FFFF Factory hardware 21 627 KB 0x00020000 0x014BFFFF PFL option bits 32 KB 0x00018000 0x0001 FFFF Board information 32 KB 0x00010000 0x00017FFF Ethernet option bits 32 KB 0x00008000 0 0000 User design reset vector 32 KB 0x00000000 0x00007FFF Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with
33. ff m When off a logic 0 is selected Switch 3 has the following options 3 USER DIPSW2 m When on a logic 1 is selected Off m When off a logic 0 is selected Switch 4 has the following options 4 USER DIPSWS3 m When on alogic 1 is selected Off m When off a logic 0 is selected Switch 5 has the following options 5 USER DIPSWA m When on a logic 1 is selected Off m When off a logic 0 is selected Switch 6 has the following options 6 USER DIPSW5 m When on a logic 1 is selected Off m When off a logic 0 is selected Switch 7 has the following options 7 USER_DIPSW6 m When logic 1 is selected Off m When off a logic 0 is selected Switch 8 has the following options 8 USER DIPSW7 m When on a logic 1 is selected Off m When off a logic O is selected 3 Set DIP switch bank SW4 to match Table 4 2 and Figure 4 2 Table 4 2 SW4 Dip Switch Settings Part 1 of 2 Switen Board Function Position Switch 1 has the following options 1 MAX_DIP When on reserved off When off reserved Switch 2 has the following options 2 USB_DISABLEn When on the embedded USB Blaster is disabled Off When off the embedded USB Blaster is enabled November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide Chapter 4 Development Board Setup Factory Default Switch Settings Table 4 2 SW4 Dip Switch Settings Part 2 of 2
34. g sections describe the controls on the SRAM amp Flash tab Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 9 Using the Board Test System SRAM The SRAM control allows you to read and write the SRAM on your board Type a starting address in the text box and click Read Values starting at the specified address appear in the table The SRAM addresses display in the format the Nios II processor within the FPGA uses that is each SRAM address is offset by 0x00400000 Thus the first location in SRAM appears as 0x00400000 in the GUI If you enter an address outside of the 0x00400000 to 0x005FFFFF SRAM address space a warning message identifies the valid SRAM address range To update the SRAM contents change values in the table and click Write The application writes the new values to SRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents Flash The Flash control allows you to read and write the flash memory on your board Type a starting address in the text box and click Read Values starting at the specified address appear in the table The flash memory addresses display in the format the Nios II processor within the FPGA uses that is each flash memory address is offset by 0x04000000 Thus the first location in flash memory appears as 0x04000000 in the GUI If you enter an address outside of the 0x0
35. h locations and the default position of each switch on the top side of the board Chapter 4 Development Board Setup Figure 4 1 Switch Locations and Default Settings on the Board Top Factory Default Switch Settings TRIS OFF 1 emm Rotary User DIP Switch Switch Lel mo Figure 4 2 shows the switch locations and the default position of each switch on the bottom side of the board Figure 4 2 Switch Locations and Default Settings on the Board Bottom s Settings mmm ON 0 OFF 1 To restore the switches to their factory default settings follow these steps 1 Set the rotary switch SW2 to the 0 position as shown in Figure 4 1 Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 4 Development Board Setup Factory Default Switch Settings 2 Set DIP switch bank SW3 to match Table 4 1 and Figure 4 1 Table 4 1 SW3 Dip Switch Settings 4 3 Switen Board Function Position Switch 1 has the following options 1 USER DIPSWO m When on a logic 1 is selected Off m When off a logic 0 is selected Switch 2 has the following options 2 USER DIPSW1 m When logic 1 is selected O
36. ideo HDMI Color Bar Test Pattern Start Stop Color Bar C Red Resolution Green Blue Get EDID SDI Tx PLL Locked Start Stop Rx PLL Locked Error Status No Error Detected Messages Detected Video Project Error Control Please connect HDMI cable to monitor Errors 0 Please connect SDI cable Insert Error Clear Monitor is detected The following sections describe the controls on the Video tab November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 18 Chapter 6 Board Test System Using the Board Test System Testing the HDMI requires connecting a monitor with at least UXGA 1600 x 1200 resolution to your board Once connected the following controls define the output to the monitor m Color bar test pattern Specifies the test pattern to output to the monitor The following choices are available m Color bar Red m Green m Blue Table 6 2 shows the color bar test pattern and corresponding color names and RGB values Table 6 2 HDMI Color Bar Test Pattern Color Bars Color RGB Values White Grey 180 180 180 Yellow 180 180 16 Cyan 16 180 180 Green 16 180 16 Magenta 180 16 180 Red 180 16 16 Blue 16 16 180 Black 16 16 16 Resolution Specifies the resolution to output to the monitor The following choices are available m 1080p 1920 x 1080
37. ink is not necessary However under extreme conditions the board might require additional cooling to stay within operating temperature guidelines You can perform power consumption and thermal modeling to determine whether your application requires additional cooling For information about measuring board and FPGA temperature in real time refer to The Power Monitor on page 6 19 For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 2 2 References Chapter 2 Getting Started References Use the following links to check the Altera website for other related information For the latest board design files and reference designs refer to the Stratix IV GX FPGA Development Kit page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Stratix IV GX device documentation refer to the Literature Stratix IV Devices page To purchase devices from the eStore refer to the Devices page For Stratix IV GX OrCAD symbols refer to the Capture CIS Symbols page For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation N D TE 2Ya 3 Software Installation This chapter explains how to install the f
38. is complete when the progress bar reaches 100 The CONF DONE LED D5 and the eight lower user LEDs D16 D23 illuminate indicating that the flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios Command Shell 9 In the Nios command shell navigate to the install dir gt kits stratixIVGX_4sgx530_fpga factory_recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios EDS on page 2 and type the following Nios II EDS command nios2 flash programmer base 0x08000000 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type the following Nios II EDS command nios2 flash programmer base 0x08000000 lt yourfile gt sw flash 11 Set the rotary switch SW2 to the 1 position and power cycle the board or press the CONFIG button 51 to load and run the user hardware design Programming the board is now complete St For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide A 4 Chapter Restoring the Flash Device to the Factory Settings Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the FPGA
39. ixIV GX_4sgx530_fpga examples directory Newer revisions of this code might be available on the Stratix IV GX FPGA Development Kit page of the Altera website m MAC Indicates the MAC address of the board MAX II Registers The MAX II registers control allows you to view and change the current MAX II register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately For example writing a 0 to SRST resets the board Table 6 1 MAX Registers Read Write Capability Register Name Description System Reset SRST Write only Set to 0 to initiate an FPGA reconfiguration Determines which of the up to eight 0 7 pages of flash Page Select Register Read Write memory to use for FPGA reconfiguration The flash memory WS ships with pages 0 and 1 preconfigured When set to 0 the value in PSR determines the page of Page Select Override flash memory to use for FPGA reconfiguration When set to PSO Read Write 1 the value in PSS determines the page of flash memory to use for FPGA reconfiguration Page Select Switch PSS Read only Holds the current value of the rotary switch SW2 PSO Sets the MAX II PSO register The following options are available m Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration
40. lowing sections describe the controls on the ODRII tab Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 13 Using the Board Test System Port The Port control directs communication to one of two QDR II ports on your board Start The Start control initiates QDR memory transaction performance analysis Stop The Stop control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m Write and Read performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Write MBps and Read MBps Show the number of bytes of data analyzed per second The QDR II buses are 18 bits wide for both read and write and the frequency is 400 MHz double data rate 800 Mbps per pin equating to a theoretical maximum bandwidth of 1800 MBps and 3600 MBps for simultaneous read and write 7 Performance figures are based on a 100 MHz input clock from programmable oscillator X6 Using the The Clock Control on page 6 22 to adjust the frequency changes the circuit speed in real time and the QDR II tab performance indicators which are capped at 100 for increased frequencies Physical layer speeds equal the oscillator X6 frequency times the input PLL multiplier ratio The default i
41. nicates over the JTAG bus to a test design running in the Stratix GX device Figure 6 1 shows the initial GUI for a board that is in the factory configuration November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 2 Chapter 6 Board Test System Figure 6 1 Board Test System Graphical User Interface ARAT Test System Configure Help About Config GPIO SRAMBFlash DDR3 ODRIIS Video Board information e Board Name Stratix IV GX Development Board Board P N 6XX 43106R Serial number Power Monitor Factory test version rev l MAC 00 00 07 14 43 II registers SRST JTAG chain vel 1 EP4SGX530 ESQ81 2 221082 Flash Memory Address Data 0 0146 0000 O1FF FFFF Zipfs Messages Detected GPIO SRAM Flash Project Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears and allows you to exercise the related board features Highlights appear in the board picture around the corresponding components The Power Monitor button starts the Power Monitor application that measures and reports curr
42. ns crepe aan ere ee CERES HUE DUC REA ROPA Leelee Info 1 November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide vi Contents Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation N DTE SYN 1 About This Kit The Altera Stratix IV GX FPGA Development Kit 530 Edition is a complete design environment that includes both the hardware and software you need to develop Stratix IV GX FPGA designs The PCI SIG compliant board and the one year license for the Quartus II software provide everything you need to begin developing custom Stratix IV GX FPGA designs The following list describes what you can accomplish with the kit Kit Features Develop and test PCI Express PCIe 2 0 designs Develop and test memory subsystems consisting of DDR3 and QDR memories Build designs capable of migrating to Altera s low cost HardCopy IV ASICs Take advantage of the modular and scalable design by using the high speed mezzanine card HSMC connectors to interface to over 30 different HSMCs provided by Altera partners supporting protocols such as Serial RapidIO 10 Gigabit Ethernet SONET Common Public Radio Interface CPRI Open Base Station Architecture Initiative OBSAI and others Develop FPGAs design for cost sensitive applications and volume production Measure the FPGA s low power consumption This section briefly describes the
43. o the FPGA development board power to the board is on and no other applications that use the JTAG chain are running To configure the Stratix GX FPGA perform the following steps 1 Start the Quartus Programmer 2 Click Add File and select the path to the desired sof 3 Turn on the Program Configure option for the added file 4 Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 Using the Quartus II programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to loose their connection to the board Restart those applications after configuration is complete Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation A Programming the Flash Memory JN DTE RYA Device As you develop your own project using the Altera tools you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Stratix GX FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device The Stratix IV GX FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal d
44. ollowing software m Quartus II Subscription Edition Software m Stratix IV GX FPGA Development Kit 530 Edition m USB Blaster driver Installing the Quartus Il Subscription Edition Software The Quartus II Subscription Edition Software provides the necessary tools used for developing hardware and software for Altera FPGAs Included in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including SOPC Builder and the Nios II EDS are the primary FPGA development tools used to create the reference designs in this kit To install the Altera development tools perform the following steps 1 Run the Quartus II Subscription Edition Software installer you acquired in Software on page 1 2 2 Follow the on screen instructions to complete the installation process T Ifyou have difficulty installing the Quartus II software refer to Altera Software Installation and Licensing Licensing Considerations Purchasing this kit entitles you to a one year DKE license for the Quartus II Subscription Edition Software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not you need to obtain and install a license file To begin go to the Self Service
45. om support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Inita labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets gt For example file name and project name pof file Indicate keyboard keys and menu names For example the Delete key and the Options menu Initial Capital Letters November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide Info 2 Additional Information Typogr
46. onfiguring your board November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 4 Chapter 6 Board Test System Using the Board Test System Using the Board Test System This section describes each control in the Board Test System application The Configure Menu Each test design tests different functionality and corresponds to one or more application tabs Use the Configure menu to select the design you want to use Figure 6 2 shows the Configure menu Figure 6 2 The Configure Menu ARET Test System Configure Help About Configure as SRAM Flash GPIO Configure as DDR3 Configure as QDRII Configure as HSMC Configure as Video Exit Ctrl Q Quartus Programmer Fast Config Mode To configure the FPGA with a test system design perform the following steps 1 On the Configure menu click one of the following options to determine how to pass data through the JTAG chain Use Fast Configuration Compresses the Raw Binary File rbf in the board_test_system sof directory and sends it over JTAG using System Console and decompresses in the Max II device converting to Fast Passive Parallel FPP format to program the FPGA Use Quartus Programmer Configures the FPGA with the SRAM Object File sof file in the board_test_system sof directory using the Quartus II Programmers s JTAG configuration mode 2 On the Configure menu click the configure command that corre
47. ons to connect to the Board Update Portal web page 7 Before you proceed ensure that you have the following A PC with a connection to a working Ethernet port on DHCP enabled network separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform the following steps 1 With the board powered down set the rotary switch SW2 to the 0 position 2 Attach the Ethernet cable from the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays the IP address 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser 5 Click Stratix IV GX FPGA Development Kit 530 Edition on the Board Update Portal web page to access the kit s home page Visit this page occasionally for documentation updates and additional new designs November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs Te You can also navigate directly to the Stratix IV GX FPGA Development Kit page of the Altera website to determine if you have the latest kit software Using the Board Update Port
48. ontained in the transactions The following data types are available for analysis m PRBS Selects pseudo random bit sequences m Memory Selects a generic data pattern stored in the on chip memory of the Stratix IV GX device November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 12 Chapter 6 Board Test System Using the Board Test System m Math Selects data generated from a simple math function within the FPGA fabric Read and Write Control The Read and write control specifies the type of transactions to analyze The following transaction types are available for analysis m Write then read Selects read and write transactions for analysis m Read only Selects read transactions for analysis m Write only Selects write transactions for analysis The QDRII Tab The ODRII tab allows you to read and write the QDR II memory on your board and independently test each QDR II port Figure 6 6 shows the QDRII tab Figure 6 6 The QDRII ARAT Test System E E x Configure Help About aea a 27 Port Porti Start Stop Write Read Power Monitor Write MBps 1799 9695 Read MBps 1799 9695 Error control Detected Errors Inserted 5 0 Insert Error Clear X Messages Detected QDRII Project Data type PRBS 7 Memory The fol
49. r outlet A Use only the supplied power supply Power regulation circuitry on the 77 board can be damaged by power supplies with greater voltage 4 Set the POWER switch SW1 to the on position When power is supplied to the board a blue LED D24 illuminates indicating that the board has power The MAX II device on the board contains among other things a parallel flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and configures the FPGA The rotary switch SW2 controls which design to load When the switch is in the 0 position the PFL loads the design from the factory portion of flash memory When the switch is in the 1 position the PFL loads the design from the user hardware portion of flash memory The kit includes a MAX II design which contains the MAX II PFL megafunction The design resides in the install dir gt kits stratixIV GX_4sgx530_fpga examples max2 directory When configuration is complete the CONF DONE LED D5 illuminates signaling that the Stratix IV GX device configured successfully For more information about the PFL megafunction refer to AN 386 Using the Parallel Flash Loader with the Quartus II Software November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 4 2 Factory Default Switch Settings This section shows the factory switch settings for the Stratix GX FPGA development board Figure 4 1 shows the switc
50. ra Corporation N DTE RYN 5 Board Update Portal The Stratix IV GX FPGA Development Kit 530 Edition ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios embedded processor an Ethernet MAC and an HTML web server When you power up the board with the rotary switch SW2 in the 0 position the Stratix IV GX FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to the user hardware portion of flash memory and provides links to useful information on the Altera website including kit specific links and design resources After successfully updating the user hardware flash memory you can load the user design from flash memory into the FPGA To do so set the rotary switch SW2 to the 1 position and power cycle the board The source code for the Board Update Portal design resides in the install dir gt kits stratixIVGX_4sgx530_fpga examples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page 4 to restore the board with its original factory contents Connecting to the Board Update Portal Web Page This section provides instructi
51. re available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 3 4 Chapter 3 Software Installation Installing the USB Blaster Driver Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation N DTE RYN 4 Development Board Setup This chapter explains how to set up the Stratix IV GX FPGA development board Setting Up the Board To prepare and apply power to the board perform the following steps 1 The Stratix IV GX FPGA development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch Settings on page 4 2 to return the board to its factory settings before proceeding 2 The FPGA development board ships with design examples stored in the flash memory device Verify the rotary switch SW2 is set to the 0 position to load the design stored in the factory portion of flash memory Figure 4 1 shows the rotary switch location on the Stratix GX FPGA development board 3 Connect the DC adapter 16 V 3 75 A to the DC power jack J4 on the FPGA board and plug the cord into a powe
52. red in the user hardware portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the tests and flash memory To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System gt To run the application navigate to the install dir NkitsNstratixXIVGX 4sgx530 fpgaNexamplesNboard test system directory and run the BoardTestSystem exe application On Windows click Start gt All Programs gt Altera gt Stratix IV GX FPGA Development Kit 530 Edition version Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design running in the FPGA The Stratix IV GX FPGA development board s flash memory ships preconfigured with the design that corresponds to the Config GPIO and SRAM amp fFlash tabs If you power up your board with the rotary switch 5W2 in a position other than the 1 position or if you load your own design into the FPGA with the Quartus II Programmer you receive a message prompting you to configure your board with a valid Board Test System design Refer to The Configure Menu for information about c
53. rogramming Flash Memory Using the Nios Il EDS If you have generated a sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios EDS The Nios IT EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform the following steps 1 Set the rotary switch SW2 to the 0 position to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board 3 Ifthe board has powered up and the LCD displays either Connecting or a valid IP address such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the CONF DONE LED D5 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 24 for more information 5 Click Add File and select install dir NkitsNstratixXIVGX 4sgx530 fpgaMfactory recovery Ns4sgx530 fpga bup sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration
54. s The read only Push Button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The SRAM amp Flash Tab The SRAM amp Flash tab allows you to read and write SRAM and flash memory on your board Figure 6 4 shows the SRAM amp Flash tab Figure 6 4 The SRAM amp Flash Tab Al Board Test System Configure Help About x Messages Detected GPIO SRAM Flash Project Config GPIO SRAMBFlash 2255 Video SRAM Start address Range 0x400000 0xSFFFFF oxaooooc Read Write 16398 16 04a0271a 3a17d244 Ox400010 02396f6d 431cifc 7fd8e4ed e6d91a14 Ox400020 3e94e2ed 7 1244 65465964 0 400030 4724 970424490 291615 40 5 0 400040 6260 0 7799085 7e a48b0 dc336c9e 0 400050 76288303 af2f751a 94965 Fe34b524 Ox400060 9ae88fc2 dfc6424c ef9e41b5 00809 6ed6e2a0 937 1 fc9b703f j Flash Start address Range 0 4000000 Ox7FFFFFF ox4000000 Read wite 3001483a 31bff804 0010e03a 101800034 0080d2b4 108042 4 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF The followin
55. s 400 MHz 100 MHz x 4 00 or 800 Mbps per pin Changing the oscillator X6 frequency to 125 MHz changes the circuit speed to 500 MHz or 1000 Mbps per pin Typically you need to reset the QDR design after changing the clock frequency Error Control The Error control controls display data errors detected during analysis and allow you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transaction stream Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes Valid values range from 2 to 1 048 576 November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 14 Chapter 6 Board Test System Using the Board Test System Data Type The Data type control specifies the type of data contained in the transactions The following data types are available for analysis PRBS Selects pseudo random bit sequences Memory Selects a generic data pattern stored in the on chip memory of the Stratix IV GX device m Math Select
56. s data generated from a simple math function within the FPGA fabric The HSMC Tab The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B ports Figure 6 7 shows the HSMC tab Figure 6 7 The HSMC Tab ff Board Test System A Configure Help About contia HSMC Status PLL Lock locked Channel Lock locked Pattern Sync synced HSMC control x4 Transceivers 0 3 C x4 Transceivers 4 7 x4 Transceivers 0 3 x2 Transceivers 4 5 5 x17 LVDS SERDES 7 HSMB x17 LVDS SERDES x3 Single Ended Loopback HSMB x3 Single Ended Loopback PMA Setting Data type Error control 57 Detected Errors PRBSIS Inserted Errors 523 Insert Error Messages C 531 Detected HSMC Project Loopback Please install HSMC loop back connecto Ts r Start Stop Tx MBps 8000 0160 Rx MBps 8000 0160 57 You must have the loopback installed on the connector that you are testing for this test to work correctly Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 15 Using the Board Test System The following sections describe the controls on the HSMC tab Status The Status control displ
57. sponds to the functionality you wish to test 3 In the dialog box that appears click Configure or Download Start to download the corresponding design s sof to the FPGA The download process usually takes about a minute 4 When configuration finishes close the Quartus II Programmer if using it The design begins running in the FPGA The corresponding GUI application tabs that interface with the design enable The Config Tab The Config tab shows he board s current configuration Figure 6 1 on page 6 2 shows the Config tab The tab displays the contents of the MAX II registers the JTAG chain the board s MAC address the flash memory map and other details stored on the board Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 5 Using the Board Test System The following sections describe the controls on the Config tab Board Information The Board information controls display static information about your board m Board Name Indicates the official name of the board given by the Board Test System Board PN Indicates the part number of the board m Serial number Indicates the serial number of the board W Factory test version Indicates the version of the Board Test System used in testing at the factory m MAXII Indicates the version of MAX II code currently running on the board The MAX II code resides in the install dir gt kits strat
58. system gt To license the Quartus II software you need your computer s network interface card NIC ID a number that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig allata command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line 4 When licensing is complete Altera emails a license dat file to you Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus II software to enable the software For complete licensing details refer to Altera Software Installation and Licensing Installing the Stratix IV GX FPGA Development Kit 530 Edition To install the Stratix IV GX FPGA Development Kit 530 Edition perform the following steps 1 Run the Stratix IV GX FPGA Development Kit 530 Edition installer you acquired in Software on page 1 2 Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 3 Software Installation 3 3 Installing the USB Blaster Driver 2 Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to your Quartus II software as the default locations The installation program creates the Stratix GX FPGA Development Kit 530 Edition directory structure shown in Figure 3 2 Figure 3 2 Stratix IV GX F
59. t Altera gt Nios II EDS gt Nios II Command Shell 2 In the Nios II command shell navigate to the directory where your design files reside and type the following Nios IT EDS commands m For Quartus II sof files sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x2000000 pfl optionbit 0x00018000 programmingmode PS m For Nios II elf files elf2flash base 0x08000000 end 0xOBFFFFFF reset 0xB4A0000 input lt yourfile gt sw elf output lt yourfile gt sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader cfi srec The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them gt The Board Update Portal standard flash format conventionally uses either filename hw flash for hardware design files or filename sw flash for software design files Programming Flash Memory Using the Board Update Portal Once you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter A 3 P
60. the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page 4 November 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide A 2 Chapter Preparing Design Files for Flash Programming Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Stratix IV GX FPGA Development Kit page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled sof into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board Update Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user hardware and user software locations of the flash memory For more information about Nios II EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios EDS If you have an FPGA design developed using the Quartus IT software and software developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click All Programs g
61. tions 4 MAX EN m When on reserved Off m When off reserved Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 4 Development Board Setup 4 5 Factory Default Switch Settings 5 Set DIP switch bank SW6 to match Table 4 4 and Figure 4 2 Table 4 4 SW6 Dip Switch Settings Switch de Function Switch 1 has the following options 1 EPM2210_JTAG_EN When on the MAX II device is not included in the JTAG chain Off When off the MAX II device is included in the JTAG chain Switch 2 has the following options 2 HSMA_JTAG_EN When HSMA is not included in the JTAG chain On When off HSMA is included in the JTAG chain Switch 3 has the following options 3 HSMB_JTAG_EN When on HSMB is not included in the JTAG chain On When off HSMB is included in the JTAG chain Switch 4 has the following options 4 PCIE_JTAG_EN m When on PCI Express is not included in the JTAG chain On m When off PCI Express is included in the JTAG chain Development Board 530 Edition Reference Manual November 2010 Altera Corporation For more information about the FPGA board settings refer to the Stratix IV GX FPGA Stratix IV GX FPGA Development Kit 530 Edition User Guide 4 6 Stratix IV GX FPGA Development Kit 530 Edition User Guide Chapter 4 Development Board Setup Factory Default Switch Settings November 2010 Alte
62. tor I Vdif R Through substitution the equation for calculating power becomes P V x I Vsense x Vdif R Vsense x Vdif x 1 003 You can verify the power numbers shown in the Power Monitor with a digital multimeter that is capable of measuring microvolts to ensure you have enough significant digits for an accurate calculation Measure the voltage on one side of the resistor the side opposite the power source and then measure the voltage on the other side The first measurement is Vsense and the difference between the two measurements is Vdif Plug the values into the equation to determine the power consumption The Clock Control The Clock Control application sets the 51570 programmable oscillator to any frequency between 10 MHz and 810 MHz with eight digits of precision to the right of the decimal point The oscillator drives a 2 to 4 buffer that drives a copy of the clock to all four edges of the FPGA The Clock Control application runs as a stand alone application ClockControl exe resides in the install dir NkitsNstratixXIVGX 4sgx530 fpgaNexamplesNboard test system directory On Windows click Start gt All Programs gt Altera gt Stratix IV GX FPGA Development Kit 530 Edition version Clock Control to start the application 5 For more information about the Si570 and the Stratix IV GX FPGA development board s clocking circuitry and clock input pins refer to the Stratix IV GX FPGA Development Board
63. uation that can cause you injury Lj The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation
64. using a 100 MHz REFCLK The x3 single ended data bus is 3 bits wide and clocked using a 50 MHz clock single data rate for 50 Mbps per pin or a 150 Mbps bandwidth for each x3 single ended data port Performance figures are based on a 100 MHz input clock from programmable oscillator X6 Using the The Clock Control on page 6 22 to adjust the frequency changes the circuit speed in real time and the HSMC tab performance indicators which are capped at 100 for increased frequencies Physical layer speeds equal the oscillator X6 frequency times the input PLL multiplier ratio The default is 100 MHz x 20 2 Gbps per pin or 8 Gbps total Changing the oscillator X6 frequency to 425 MHz changes the circuit speed to 8 5 Gbps or 34 Gbps total for x4 transceivers 17 Gbps for x2 transceivers Typically you need to reset the HSMC design after changing the clock frequency La TheHSMC x17 SERDES and x3 single ended ports use fixed frequency oscillators and are not affected by the Clock Control application Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation Chapter 6 Board Test System 6 17 Using the Board Test System The Video Tab The Video tab allows you to test the HDMI and SDI video interfaces on your board Figure 6 8 shows the Video tab Figure 6 8 The Video Tab ARAT Test System E Configure Help About GORI SMG V
65. vember 2010 Altera Corporation Stratix IV GX FPGA Development Kit 530 Edition User Guide 1 4 Chapter 1 About This Kit Kit Features Stratix GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation DTE 2 Getting Started The remaining chapters in this user guide lead you through the following Stratix IV GX FPGA development board setup steps Inspecting the contents of the kit m Installing the design and kit software m Setting up powering up and verifying correct operation of the FPGA development board m Configuring the Stratix IV GX FPGA m Running the Board Test System designs For complete information about the FPGA development board refer to the Stratix IV GX FPGA Development Board 530 Edition Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the board to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Board To inspect the board perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment A Without proper anti static handling you can damage the board CAUTION 2 Verify that all components are on the board and appear intact In typical applications with the Stratix GX FPGA development board a heat s
66. w designs to the user hardware portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 Stratix IV GX FPGA Development Kit 530 Edition User Guide November 2010 Altera Corporation S 6 Board Test System The kit includes a design example and application called the Board Test System to test the functionality of the Stratix IV GX FPGA development board The application provides an easy to use interface to alter functional settings and observe the results You can use the application to test board components modify functional parameters observe performance and measure power usage The application is also useful as a reference for designing systems To install the application follow the steps in Installing the Stratix IV GX FPGA Development Kit 530 Edition on page 3 2 The application provides access to the following Stratix IV GX FPGA development board features General purpose I O GPIO SRAM Flash memory DDR3 and QDR II memories HSMC connectors High definition multimedia interface HDMI video Serial digital interface SDI video m Character LCD The application allows you to exercise most of the board components While using the application you reconfigure the FPGA several times with test designs specific to the functionality you are testing A GUI runs on the PC that commu

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