Home

Serial Digital Interface (SDI) MegaCore Function User Guide

Contents

1. tx_pelk 74 25MHz _J LJ LI WLI VIT LI VI VI tx_sta 1 0 20 X 01 rst tx sync 1 o X Note to Figure 3 30 1 Internally synchronized reset for the transmit circuits Figure 3 31 Behavior of tx std tx trs and tx In Signals 425MA EAV SAV EAV tx pelk 1 ix irs S eX txdata 19 10 sm y ww o I wa Spo 9 8 omm ww ww Jy x txdata 9 0 Y o y xay se y ww Y o AP AS Y ww Y wc 0 tx_std 1 0 I K 4 tx In 21 11 7 176 ix In 10 0 ma 0 1102 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 48 Chapter 3 Functional Description Signals Figure 3 32 Behavior of tx std tx trs and tx In Signals 425MB EAV SAV EAV 1 tx_trs J amp txdata 19 10 SFR 0096 009 7 Y OOOICHY OOTY CAO XVZVY 4 AFFF 0 XYZ 0096 000 009 000 XYZ txdata 9 0 SFF SER o0 c 000 Y 000C 0000 XYZIOKXYZY BFFIC SFFIY 000 ZZ FFCF 009 009 000 XYZ tx_std 1 0 10 tx In 21 11 11d 1103 tx In 10 0 1102 11704 Figure 3 33 Behavior of crc error y and cr
2. SD SDI 2 SDI MegaCore gt Ix clk 67 5 MHz PU a Serial Data gt Function M ir rmv Mr P rx data valid out rx data Y V y jv Y rx data valid out d f H i i i 67 5 MHz HD SDI rx_clk SDI MegaCore gt rx clk 74 25 MHz Function __y rx data valid out rx data i Serial Data o rx data valid out 74 25 74 175 MHz Dual Standard SDI MegaCore x_clk 67 5 74 MHz Serial Data i Function I M rx data valid out 67 5 MHz Transmitter Transceiver Interface Altera provides a transceiver interface which interfaces the transceiver to the SDI function The transceiver interface implements the following functions m Transmitter Retiming m HD SDI Two Times Oversampling m SD SDI Transmitter Oversampling 57 When using the two times oversampling transmitters in Stratix GX devices you cannot have HD SDI receivers in the same quad The quad requires the same frequency reference clocks for both the receivers and transmitters within a quad HD SDI receivers and two times oversampling transmitters have different frequency reference clocks refer to Table 3 5 and Table 3 6 on page 3 15 Transmitter Retiming The txdata parallel
3. SD SDI Serial Data 50 MegaCore er D qeu Function rx data valid out rx data Y V y jv Y rx data valid out d Y f H i i 67 5 MHz HD SDI rx_clk SDI MegaCore rx_clk 74 175 or 74 25 MHz L3 LE LI LJ Function ___y rx data valid out rx data rx_data_valid_out Serial Data _ gt 74 25 or 74 175 MHz 3G SDI or Dual Standard or Triple Standard SDI MegaCore I rx ck 148 5 MHz or 74 xx MHz when receiving HD Serial Data i Function P rx data valid out 148 5 MHz Transmitter Transceiver Interface Altera provides a transceiver interface which interfaces the transceiver to the SDI function The transceiver interface implements the following functions m Retiming from the parallel video clock domain to the transceiver transmitter clock domain m Optional two times oversampling for HD m Transmitter oversampling for SD Transmitter Retiming The txdata parallel data input to the transceiver must be synchronous and phase aligned to the tx coreclk transceiver clock input SD SDI and optionally HD SDI requires a retiming function because of the oversampling logic The transmitter uses a small 16 x 20 FIFO buffer for the retiming For HD SDI the FIFO buffer realigns the parallel video input to
4. TX PLL SELECT RECONEIG Control Transmitter S and Intercept SDI START RECONFIG only UserLogic lg Protocol SDI IP Core Transmitter ALT2GXB_INST User Guide When enabling the transmitter clock multiplexer feature the ALT2GXB_RECONFIG block handles the programming of the ROM contents to the transceiver megafunction The ROM holds the information setting for the default reference clock selection of the TX PLL in the transmitter as well as the values of the logical tx pll seland logical tx pll sel en pins The reconfiguration control and intercept user logic block detects changes in the trigger port sets the logical tx pll seland logical tx pll sel ento the corresponding value and initiates the reprogramming of the transmitter megafunction ALT2GXB RECONFIG Connections for Receiver The SDI START RECONFIG and SDI RECONFIG DONE signals handle the handshaking between the SDI MegaCore function and the user logic The RX STD signal must select the correct transceiver setting Table 3 19 on page 3 54 lists the five signals that handle transceiver dynamic reconfiguration Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation Chapter 3 Functional Description Block Description 3 33 Figure 3 21 shows the handshaking between the SDI MegaCore function and the user logic and the expected output of some of the ALT2GXB RECONFIG signals Figure 3 21 Handshaking Betw
5. quartus Contains the Quartus II NativeLink project testbench Contains the testbench files pattern_gen Contains the pattern generator files for the testbench Contains the HD SDI 3 Gbps simulation files quartus Contains the Quartus II NativeLink project testbench Contains the testbench files pattern_gen Contains the pattern generator files for the testbench I hdsdi dual link Contains the HD SDI dual link simulation files quartus Contains the Quartus II NativeLink project testbench Contains the testbench files pattern gen Contains the pattern generator files for the testbench hdsdi 3g 8 modelsim Contains the ModelSim simulation files 1 Create a custom variation of the SDI MegaCore function 2 Implement the rest of your design using the design entry method of your choice Use the IP functional simulation model to verify the operation of your design For more information on IP functional simulation models refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started 2 3 SDI Walkthrough 4 Use the Quartus II software to compile your design 57 You can also generate an OpenCore Plus time limited programming file which you can use to verify the
6. 1 1 Input Transceiver reference clock input Low jitter Refer to Table 3 5 Optional port for transceiver reference clock input Low jitter Similar tx serial refclkl Input to tx serial refclk Only available for Arria Il Stratix IV GX and HardCopy IV GX devices Note to Table 3 13 1 You must tie the tx_serial_refclk and rx serial _refclk signals together if you generate SDI duplex using Arria V or Stratix V devices Serial Digital Interface 501 MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 41 Signals Table 3 14 lists the transceiver PHY management clock and reset signals Table 3 14 Transceiver PHY Management Signals 1 Signal Direction Description Avalon MM clock input for the transceiver PHY management interface Use the same clock for the PHY management interface and transceiver reconfiguration The frequency range is 100 125 MHz to meet the specification of the transceiver reconfiguration clock Reset signal for the transceiver PHY management interface This signal is active high and level sensitive This signal can be tied to the same reset port as tx rst Or rx_rst signal in simplex mode phy mgmt clk reset Input In duplex mode this reset signal acts as a global reset for both the transmitter and receiver If you require a different reset for the transmitter and receiver separate this signal from the tx rst and rx rst Signal
7. IL I N represents the number of channels instantiated The SDI_GXB_POWERDOWN signal of all the instances that are to be combined in a single transceiver block must be connected to a single point same input or same logic Any difference in the driving logic prevents the instances from being combined in a single transceiver block 7 This signal must be connected directly to the ALTPLL_RECONFIG megafunction and only exposed to the top level when you select the Use PLL reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor co The transceivers are available for Cyclone IV GX devices only 9 You require xx sta and sdi start reconfig signals for PLL reconfiguration February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 56 Parameters Chapter 3 Functional Description Parameters The parameters can only be set in the MegaWizard Plug In Manager refer to Parameterizing on page 2 5 Table 3 20 lists the protocol options Table 3 20 Protocol Options Parameter Video standard Value SD SDI HD SDI 3G SDI HD SDI dual link dual or triple standard SDI Description Selection of HD SDI or SD SDI Selecting HD SDI switches in LN insertion and extraction and CRC generation and extraction blocks selecting SD SDI switches out LN insertion and extraction and CRC generation and extraction blocks Selecting SD SDI als
8. Input Serial input Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description Signals Table 3 16 Interface Signals Part 3 of 5 3 43 Signal txdata tx ln Width 20N 1 0 21 0 Direction Input Input Description User supplied transmitter parallel data 50 501 uses 9 0 HD SDI uses 20 1 0 SD bits 19 10 unused bits 9 0 Cb Y Cr Y multiplex HD bits 19 10 Y bits 9 0 C Dual link bits 39 30 Y link B bits 29 20 C link B bits 19 10 Y link A bits 9 0 C link A 3G SDI Level A bits 19 10 Y bits 9 0 C 3G SDI Level B bits 19 10 Cb Y Cr Y multiplex link A bits 9 0 Cb Y Cr Y multiplex link B Transmitter line number For use in HD SDI and 3G SDI line number insertion HD SDI bits 21 11 11 d0 bits 10 0 LN Dual link bits 21 11 LN link B bits 10 0 LN link A 30 501 Level A bits 21 11 11 d0 bits 10 0 LN 36 501 Level B bits 21 11 LN link A bits 10 0 LN link B Refer to Figure 3 31 and Figure 3 32 tx trs N 1 0 Input Transmitter TRS input For use in HD SDI LN and CRC insertion Assert on first word of both EAV and SAV TRSs Refer to Figure 3 31 and Figure 3 32 tx std trs loose lock 1 0 N 1 0 Input Output Transmitter standard 00 for SD SDI 01 for HD SDI 11 for 3G SDI Level A and 10 for 3G SDI Level B This signal must be set up and
9. Output The video line signal that provides for easy connection to the Altera SDI MegaCore function vid out data 19 0 Output The video output signal Table 4 4 lists the audio input signals for the SDI Audio Embed MegaCore function Table 4 4 Audio Input Signals Signal aud clk Width 24 1 0 Direction Input Description Set this clock to 3 072 MHz that is synchronous to the extracted audio In asynchronous mode set this to any frequency above 3 072 MHz Altera recommends that you set this clock to 50 MHz For SD SDI inputs this mode of operation limits the core to extracting audio that is synchronous to the video For HD SDI inputs this clock must either be generated from the optional 48 Hz output or the audio must be synchronous to the video aud de 24 1 0 Input Assert this data enable signal to indicate valid information on the aud ws and aud data signals In synchronous mode the core ignores this signal aud ws 24 1 0 Input Assert this word select signal to provide framing for deserialization and to indicate left or right sample of channel pair aud data 24 1 0 Input Internal AES data signal from the AES input module Refer to Figure 4 9 Note to Table 4 4 1 Nrepresents the number of audio groups February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 6 C
10. To add the additional tcl file you must compile your design and perform post compilation timing analysis using the TimeQuest timing analyzer On the Assignments menu click Use TimeQuest Timing Analyzer during compilation and click OK You may have to further edit your scripts if your design requires single channel or multiple channels Single Channel The following section describes what you must do if your design requires a single channel using SDI triple standard transmitter and receiver instances as shown in Figure 2 3 on page 2 11 Figure 2 3 Instantiating Single Channel of SDI Instances SYSTEM TOP LEVEL Transceiver Bank 1 tx serial refclk topt SDI triple standard transmitter SDI triple standard receiver Ix Serial refclk top1 f lt starting_channel_number 0 starting_channel_number 4 57 The SDI instances must have a unique starting channel number if they are merged into a same quad or bank To specify the constraints follow these steps 1 Parameterize and generate your SDI MegaCore functions SDI triple standard transmitter and receiver February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 2 12 Chapter 2 Getting Started Specifying Constraints 2 Edit the Tcl script so that the transceiver top level reference clock matches the clock pin names that you have chosen for your design for example tx serial ref
11. phy mgmt clk Input Note to Table 3 14 1 The transceiver PHY management clock and reset signals are available for Stratix V and Arria V devices only Table 3 15 lists the soft transceiver clock signals Table 3 15 Soft Transceiver Clock Signals Signal Direction Description rx sd refclk 337 Input Soft transceiver 337 5 MHz sampling clock rx sd refclk 337 90deg Input Soft transceiver 337 5 MHz sampling clock with 90 phase shift rx sd refclk 135 Input Soft transceiver 135 MHz parallel clock for receiver tx sd refclk 270 Input Soft transceiver 270 MHz parallel clock for transmitter Table 3 16 lists the interface signals Table 3 16 Interface Signals Part 1 of 5 Signal Width Direction Description enable crc N 1 0 Input Enables CRC insertion for HD SDI and 3G SDI hai search 1 Input Enables search for HD SDI signal in dual or triple standard iliis mode t es 1 Input Enables search for SD SDI signal in dual or triple standard 72 mode enable 3g search 1 Input Enables search for 3G SDI signal in triple standard mode ee 1 0 Input Enables line number insertion for HD SDI and 3G SDI modes TO 1 Enables aligner and format blocks to realign immediately en_syne_swike so that the downstream is completely non disruptive Reset signal which holds the receiver in reset It must be synchronous to rx_serial_refclk
12. Table 4 22 and Table 4 23 list the register maps for the SDI Clocked Audio Input MegaCore function Table 4 22 SDI Clocked Audio Input MegaCore Function Register Map Bytes Offset Name 00h Channel 0 Register 01h Channel 1 Register 02h FIFO Status Register 03h FIFO Reset Register Table 4 23 SDI Clocked Audio Input MegaCore Function Register Map Part 1 of 2 Bit Name Access Description Channel 0 Register 7 0 Channel 0 RW The user defined channel number of audio channel 0 Channel 1 Register 7 0 Channel 1 RW The user defined channel number of audio channel 1 FIFO Status Register 7 0 FIFO status RO This sticky bit reports the overflow of the clocked audio input FIFO Serial Digital Interface 501 MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores 4 19 Clocked Audio Output MegaCore Function Table 4 23 SDI Clocked Audio Input MegaCore Function Register Map Part 2 of 2 Bit Name Access Description FIFO Reset Register 6 0 Unused WO Reserved 7 FIFO reset WO Resets the clocked audio FIFO Clocked Audio Output MegaCore Function The Clocked Audio Output MegaCore function accepts clocked Avalon ST audio and converts to audio in modified AES formats Parameters Table 4 24 lists the MegaWizard Plug In Manager parameters for the SDI Clocked Audio Output MegaCore function Table 4 24 SDI Clock
13. Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode Cyclone IV GX To implement transceiver dynamic reconfiguration for dual and triple standard SDI using Cyclone IV GX devices you can also use PLL reconfiguration mode To reprogram Cyclone IV GX device family with PLL reconfiguration mode you must include the ALTPLL_RECONFIG megafunction in your design You can get this parameterization from the simulationNmodelsimNtrsdi c4gxNpll reconfigNtestbench pattern gen directory in the example simulation Serial Digital Interface SDI MegaCore Function User Guide 3 34 Chapter 3 Functional Description Block Description Figure 3 22 shows the block diagram of how the SDI MegaCore function and the ALTPLL_RECONFIG megafunction are connected Figure 3 22 Transceiver Dynamic Reconfiguration Block Diagram Using PLL Reconfiguration Mode rom_address_out pll_scandataout ROM 3G ALTPLL_RECONFIG SDI IP Core Receiver write_rom_enable pll_scandone ALTGX_INST pll_areset write from rom pll_configupdate ROM HD reconfig pll_scanclk pll_scanclkena lt q pll_scandata rom_address_out Protocol rom_data_in RECONFIG Control Logic sdi_start_reconfig rx_std Encrypted RECONFIG Megafunction nmi Encrypted SDI IP Core The ALIPLL RECONFIG block handles the programming of the ROM contents into the transceiver megafunc
14. 3 10 Chapter 3 Functional Description Block Description The format block latches the user input en_sync_switch signal for three lines to realign to anew TRS alignment immediately During switching you see zero interrupt at downstream The trs_locked and frame_locked signals never get deasserted during sync switch Figure 3 6 Format Block Behavior en_sync_switch en_sync_switch_reg line 10 Y 11 12 I 13 I detect J n y eav position 2200 2199 2200 trs_locked rx_status 3 frame_locked rx_status 4 previous TRS timing new TRS timing Ls CAUTION HD SDI LN Extraction The HD SDI LN extraction module extracts and formats the LN words defined by SMPTE292M section 5 4 from the HD SDI chroma channel The design provides the LN as an output HD SDI CRC Checking The CRC module checks the CRC defined by SMPTE292M section 5 5 for the HD SDI luma and chroma channels This module is common to the receiver and the transmitter The check is implemented by recalculating the CRCs for each received video line and then checking the results against the CRC data received If the results differ an error flag is asserted There are separate error flags for the luma and chroma channels The flag is held asserted until the next check is performed Accessing Transceiver The Quartus II software enables you to access the transceiver through the unencrypted A
15. Serial Digital Interface SDI MegaCore Function User Guide A 4 Appendix A Constraints Specifying TimeQuest Timing Analyzer Constraints Table A 2 Step 2 Set Timing Exceptions Part 2 of 2 Standard Soft transceiver SDI idi pce set clock group set false path pond nom Setup 1 5 clocks 4 43 ns from the switchline 337 5 MHz zero degree get_clocks clock to the 135 MHz 5 receive pes0 clkout Clock gxb_rxclk Hold zero clocks from the 337 5 MHz clock to the 135 MHz clock Note to Table A 2 1 Switchline is an internal signal equivalent to the switch reg signal in Figure 3 6 Table A 3 Step 3 Minimize the Timing Skew Standard Minimize Timing Skew SD SDI HD SDI HD SDI dual link 3G SDI DR TR Soft transceiver SDI 1 0 to sample a b c d 0 path as short as possible The following constraints are specifically used to constrain a duplex SDI MegaCore function targeting Stratix IV device m Specify Clock Characteristics m SetMulticycle Paths m Minimize Timing Skew Specify Clock Characteristics Use the following constraints for the TimeQuest timing analyzer m SD SDI rx sd oversample clk 67 5 MHz tx pclk 27 MHz tx serial refclk 67 5 MHz create clock name rx sd oversample clk in period 14 814 waveform 0 000 7 407 get ports rx sd oversample clk in create clock name tx pclk period 14 814 waveform
16. Audio Control Packet MSB LSB MSB LSB vo e V7 4 4 F 1st frame 24th frame 192nd frame of V bit of V bit of V bit Note to Figure 4 6 1 The sequence of audio control packets begins with V bit U bit and finally C bit The audio control packets for U and C bits are similar to V bits The Avalon ST audio protocol separates the audio data from the control or status data to facilitate audio data processing The protocol defines that the data is packed LSB first which matches the AES3 data The audio data size is configurable at compile time and matches the audio data sample size Including the aux the audio data word would be 24 bits In Avalon ST audio the data is packed as 24 bit symbols typically with 1 symbol per beat 23 0 The core transmits the audio control data as a packet after the audio data to meet the latency requirements The packet type identifier defines the packet type The packet type identifier is the first value of any packet when the start of packet signal is high The audio data packet identifier is Ox A and the audio control data packet identifier is OxE Table 4 29 lists the packet types Table 4 29 Avalon ST Packet Types Type Identifier Description 0 Video data packet 1 8 User packet types 10 Audio data packet 14 Audio control data packet 15 Video control data packet 9 15 Reserved The preamble data XYZ from AES describes whether the data is
17. Some audio receivers provide a word select output to align the serial outputs of several audio extract cores In these circumstances assert this signal to control the output timing of the audio extract externally otherwise set it to 0 This signal must be a repeating cycle of high for 32 1 cycles followed by low for 32 c1k cycles aud_de 0 0 Output The core asserts this data enable signal to indicate valid information on the aud_ws and aud_data signals In synchronous mode the core drives this signal high aud_ws 0 0 Output The core asserts this word select signal to provide framing for deserialization and to indicate left or right sample of channel pair aud_data 0 0 Output The core asserts this signal to extract the internal AES audio signal from the AES output module Refer to Figure 4 9 Table 4 14 lists the Avalon ST audio signals when you instantiate the SDI Audio Extract MegaCore function in SOPC Builder Table 4 14 Avalon ST Audio Signals for SDI Audio Extract MegaCore Function February 2013 Altera Corporation Signal Width Direction Description aude 0 0 Input ae E audio input signals are IHN4B 70 a aud sop 0 0 dpt funtion assen thie sina when aame siart aud_eop 0 0 freon assen ths signal lena rane ende 7 0 Output This signal indicates which aud_data 23 0
18. any edits that were previously made to the sdc script are preserved Execute the Tcl script in the Quartus II software and perform the following steps a Onthe Tools menu click Tcl script b Select the Tcl script of the instance SDI triple standard transmitter A and click Run Perform steps 2 to 4 for the other three instances Figure 2 5 Instantiating Multiple Channels of SDI Instances Sharing Multiple Reference Clocks ix serial refclk top1 SYSTEM TOP LEVEL Transceiver Bank 1 rx serial refclk top1 tx serial refclk top2 SDI triple standard transmitter A starting channel number 0 SDI triple standard receiver A starting channel number 4 SDI triple standard transmitter B starting channel number 8 SDI triple standard receiver B starting channel number 12 Transceiver Bank 2 SDI triple standard transmitter A starting channel number 0 SDI triple standard receiver A starting channel number 4 rx serial refclk top2 SDI triple standard transmitter B starting channel number 8 SDI triple standard receiver B starting channel number 12 February 2013 Altera Corporation To specify constraints for multiple channels of SDI MegaCore function with multiple top level reference clocks as shown in Figure 2 5 perform the following steps 1 For the SDI instances in Transceiver Bank
19. component clk0 to your megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1_component _clk2 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Appendix A Constraints A 9 Constraints for the SDI Soft Transceiver Cyclone Devices Only These constraints apply to Cyclone devices only not Cyclone Cyclone III or other device families Classic Timing Analyzer Use the following constraints for the Classic timing analyzer set global assignment name FMAX REQUIREMENT 27 MHz section id input refclk set instance assignment name CLOCK SETTINGS input refclk to rx 27 refclk set instance assignment name CLOCK SETTINGS rxclk to lt megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv set global assignment name BASED ON CLOCK SETTINGS input refclk section id rxclk set global assignment name MULTIPLY BASE CLOCK PERIOD BY 5 section id rxclk set global assignment name DIVIDE BASE CLOCK PERIOD BY 25 section id rxclk set global assignment name ENABLE CLOCK LATENCY ON set instance assignment name SETUP RELATIONSHIP 4 43 ns from lt megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks pll sclk cyc rx pll gen u rx pll altpll altpll component cl ko to
20. gt Detector HD SD 3G Figure B 3 shows how you must clock the transceivers for version 7 1 and later SDI cores with international clocking Both American and European standards are catered for Figure B 3 Version 7 1 and Later International Clocks Phase SDI Receiver 148 5 MHz Transceiver e Frequency VCXO Detector SDI Out ransmitter 148 35 MHz x Transceiver P HD SD VEXO 12 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Appendix B Clocking Figure B 3 shows how you must clock the transceivers for version 7 1 and later SDI cores with international clocking Both American and European standards are catered for Figure B 1 Version 11 1 and Later International Clocks Optional SDI Out SDI Transmitter Transceiver SDI Receiver eI Transceiver 9 Frequency 39 vexo Detector 148 35 MHz HD SD VCXO 2 A Serial Digital Interface 501 MegaCore Function User Guide February 2013 Altera Corporation N DTE RYN C Receive and Retransmit You cannot reuse the HD and 3G recovered clocks for transmitting because the transmitter jitter is then e
21. m Voltage output differential m Pre emphasis control pre tap m Pre emphasis control 1st post tap m Pre emphasis control 2nd post tap m Equalizer DC gain m Equalized DC control The ALTGX_RECONFIG megafunction interfaces with the ALTGX using reconfig togxb 3 0 and reconfig fromgxb 16 0 ports for a single channel To enable the analog control and channel reconfiguration during run time use the reconfig mode sel signal St For more information about how to use the analog control with the ALTGX RECONFIG megafunction refer to the ALTGX_RECONFIG Megafunction User Guide in the respective device handbooks February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 12 Transceiver Clock Chapter 3 Functional Description Block Description Figure 3 7 shows the general clocking scheme for the receiver Figure 3 7 Receiver Clocking Scheme rx_serial_refclk gxb2_cal_clk sdi_reconfig_clk ew oe ee ee eee P rxclk E i 1 ALTGXB 1 xc 1 9xb refclk rxclk rx_clkout rxdata 19 0 4 rxword 19 0 gxb_rxword 19 0 lt rx dataout 19 0 s Ix refclk gt rx_cruclk serialidata in r3 cal i Transceiver Soft Logic Implementation The soft logic implementation differs for the transmitter and the receiver Transmitter For the transmitter in the soft logic transceiver a
22. vid clk Programmable add Digital p gt 3 072 MHz Output PLL Extracted Clock Phase audio data Recovery 128 Parameters Table 4 10 lists the parameters for the SDI Audio Extract MegaCore function Table 4 10 SDI Audio Extract MegaCore Function Parameters Parameter Value Description Channel status RAM On or off Turn on to store the received channel status data Turn on to enable extra error checking logic to use the error status register Turn on to enable extra logic to report the audio FIFO status on the ifo status port or register Turn on to enable the logic to recover both a sample rate clock and a 64 x sample rate clock With HD SDI inputs the core generates the output by using the embedded clock phase information With SD SDI inputs the core generates this output by using the counters running on the 27MHz video clock This generation limits the SD SDI embedded audio to being synchronous to the video Turn on to include the SDI Clocked Audio Input MegaCore Include Avalon ST interface On or off When you turn on this parameter the Avalon ST interface signals in Table 4 14 appear at the top level Otherwise the audio input signals in Table 4 17 appear at the top level Turn on to include the Avalon MM control interface Include Avalon MM control On or off When you turn on this parameter the register interface signals interface in Table 4 7 appear at the top level Otherwise the di
23. 1 perform steps 1 to 5 you would do for SDI instances sharing the same reference clock 2 For the SDI instances in Transceiver Bank 2 duplicate an sdc script for SDI triple standard transmitter A and SDI triple standard receiver A in Transceiver Bank 2 Serial Digital Interface SDI MegaCore Function User Guide 2 14 Chapter 2 Getting Started Compiling the Design 57 You are not required to duplicate sdc script for SDI triple standard transmitter B and SDI triple standard receiver B in Transceiver Bank 2 Instances with same video standard can share an sdc script 3 Edit the sdc script so that the reference clock name matches the name of the clock pin connected to SDI triple standard transmitter A for example tx_serial_refclk_top2 Locate tx_serial_refclk_name in the script and change totx serial refclk top2 4 Edit another sdc script so that the reference clock name matches the name of the clock pin connected to SDI triple standard receiver A for example rx serial refclk top2 Locate set rx serial refclk name in the script and change to rx serial refclk top2 5 Add these two duplicate sdc scripts to your project On the Project menu click Add Remove Files in Project and browse to select the scripts Compiling the Design You can use the Quartus II software to compile your design For instructions about performing compilation refer to Quartus II Help You can find an example design using an SD
24. 16 5 are negligible for Cyclone IV GX m For Arria V Cyclone V and Stratix V devices SDI RECONFIG FROMGXB 92N 1 0 or SDI RECONFIG 46 1 0 if the receiver in the interface settings is selected RX STD 1 0 Output Receive video standard 00 SD SDI 01 HD SDI 10 3G SDI The SDI MegaCore function can recover both SMPTE 425M A and 425M B formatted streams The receiver indicates which format it detects by setting the level of the xx sta bus m rx std 1 0 2 b11 425M A m rx std 1 0 2010 425M B PLL ARESET 7 8 9 Input Drives the areset signal on the transceiver PLL to be reconfigured This signal indicates that the transceiver PLL must be reset PLL CONFIGUPDATE 7 8 9 Input Drives the configupdate signal on the transceiver PLL to be reconfigured Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description Signals 3 55 Table 3 19 Transceiver Dynamic Reconfiguration Signals Part 2 of 2 Signal Direction Description PLL_SCANCLK ingit Drives the scanc1k signal on the transceiver PLL to be 0 8 9 reconfigured PLL_SCANCLKENA iipit Acts as a clock enable for the scanc1k signal on the transceiver 7 8 9 PLL to be reconfigured PLL SCANDATA Drives the scandata signal on the transceiver PLL to be q 8 0 Input re
25. 2 Each channel has a start of packet and an end of packet signal which allows the channel interleaving and de interleaving Figure 4 8 Multiple Audio Channel Start of packet for audio End of packet for audio End of packet for audio sample data channel 1 sample data channel 1 sample data channel 2 Start of packet for audio Channel signal indicates sample data channel 1 audio channel number Sop p xa eop data A a Jot ANE E D2 pa D4 ree o1eXD19H 01e E Yeong E date channel 1 Keay CEAN 2 W 2 Instantiating the IP Cores You can instantiate the SDI Audio Embed and Audio Extract MegaCore functions the following ways m Instantiates within SOPC Builder with audio inputs exposed outside SOPC Builder m Instantiate within SOPC Builder with audio inputs exposed as Avalon ST Audio within SOPC Builder m Directly instantiate in RTL with a CPU register interface m Instantiate the encrypted core directly on RTL with control ports February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 24 Chapter 4 SDI Audio IP Cores Simulating the Testbench As the SDI Audio Embed and Audio Extract MegaCore functions use an Avalon MM slave interface to access the control registers the most convenient way for you to instantiate the components are within SOPC Builder You are provided with the component declarat
26. 3 14 Figure 3 14 Locking Algorithm trs_strobe AN n th missing EAV New TRS reasserts word count trs_loose_lock Y Because the aligner realigns to a new alignment if two consecutive TRSs with the same alignment are detected this scheme allows for an SDI source switch and an alignment change without affecting the transceiver reset state machine The SDI MegaCore function also monitors the incoming EAV and SAV signals to ensure their spacing is consistent over a number of lines The MegaCore function monitors by incrementing a counter on each incoming SDI word and storing the count values at which an EAV or SAV is detected If the EAV and SAV spacing is consistent over 6 video lines the MegaCore function indicates trs locked on the rx status 3 output An enhancement in the current SDI MegaCore function allows a number of missing EAV or SAV that you specify to be tolerated without deasserting the trs locked signal For example when you specify the Tolerance to consecutive missed EAV SAV parameter to 2 one or two consecutive missing EAVs set a missed flag but do not cause the trs locked signal to deassert A good EAV in the correct position resets the missed flag The operation of this missing or misplaced TRS tolerance is shown in Figure 3 15 Figure 3 16 and Figure 3 17 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 26 Ch
27. 9 10 y 000 v9 Sy AFC yj rx_anc_valid 3 i H rx_anc_valid 2 i i i ma o rx_anc_valid 0 i i i rX_anc_error 3 i i rx anc error i i nx anc error t c rx anc error O Notes to Figure 3 40 1 Sequence starts with Data Indentifier DID followed by Secondary Data Indentifier SDID or Data Block Number DBN The Y channel goes wrong Data Count DC word User data word UDW up to 255 words Checksum word Figure 3 41 Behavior of rx anc data valid error Signals Without Error SD rx_clk 67 5 MHz rx_anc_data 9 0 00 X 3FF 179 20F Y 055 rx anc valid 0 TAJ I xx rx anc error 0 Figure 3 42 Behavior of rx anc data valid error Signals With Error SD Ix clk 67 5 MHz rx anc data 9 0 X 000 Y 3FF 3F Y 17 00 Y 20F Y 055 rx anc valid 0 WV rx anc error 0 L February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 54 Chapter 3 Functional Description Signals Table 3 19 lists the signals that handle the transceiver dynamic reconfiguration operation Table 3 19
28. Classic timing analyzer set instance assignment name SETUP RELATIONSHIP 4 43 ns from lt megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1l component clk0 to lt megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1 component clk2 Set instance assignment name HOLD RELATIONSHIP 0 ns from cyour megacore your megacore inst gt sdi_megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1 component 1 0 to cyour megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1 component clk2 TimeQuest Timing Analyzer Use the following constraints for the TimeQuest timing analyzer set max delay 4 43 from your megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1 component 1 0 to your megacore your megacore inst sdi megacore top sdi megacore top inst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpl 1 component clk2 set min delay 0 from your megacore your megacore inst sdi megacore top sdi megacore top i nst sdi clocks u sdi clocks stratix c2 pll sclk u rx pll altpll altpll
29. Click Next to display the Parameter Settings page for the SDI MegaCore function amp You can change the page that the MegaWizard Plug In Manager displays by clicking Next or Back at the bottom of the dialog box You can move directly to a named page by clicking the Parameter Settings EDA or Summary tab Also you can directly display individual parameter settings by clicking on the Protocol Options Transceiver Options or Receiver Transmitter Options tab Parameterizing To parameterize your MegaCore function follow these steps 1 ge m 9 Select the video standard Some of the standards may be grayed out because they are not supported on the currently selected device family Select Bidirectional Receiver or Transmitter interface direction Click the Transceiver Options tab Under Transceiver and Protocol click Generate transceiver and protocol blocks For SD SDI only turn on Use soft logic for transceiver to implement the transceiver in logic rather than using Stratix GX Stratix IT GX or Stratix IV GX transceivers Select the starting channel number Turn on Use PLL reconfiguration for transceiver dynamic reconfiguration if you select an EP4CGX110 or EP4CGX150 device for Cyclone IV GX using dual and triple standards You may turn on this option for other Cyclone IV GX devices but it is not recommended Turn on Enable TX PLL select for 1 1 000 and 1 1 001 data rate reconfiguration if your design requires two
30. E ale eoa te ia ate ed wc ae c 4 15 Clocked Audio Input MegaCore Function 6 6 66 eens 4 17 Parameters ede t pe te ee pee e dee ed degen eee tete oe Pee Pe dee ed de eet 4 17 CA 4 17 Register Maps ce doe o dera oe Rte eee 4 18 Clocked Audio Output MegaCore Function 0 0000s 4 19 Paxainetetrs Jue oe Eee CE erbe Cete dee eod eate e dee e 4 19 SIENAS e ee tule ear edie toenail 4 19 Register Maps nee pe reae eee to eae ANI eee dae bod eect eoe ase Rr e Ga 4 20 AES 510 oo 0 MEN AERE TO EE DP 4 21 Avalon ST Audio Interface 2 0 0 ene eee hrs 4 21 Instantiating the IP Cones eee ence er eee e IER Hehe One se ee er Res e eed kie ee 4 23 Simulating the Testbench eee nee 4 24 Design Example o eiecti ka A eee den quere E 4 25 Components edes dae Pacta cd De Pe a d a dre de eee i Spo bee d Vo et 4 26 SIDE Transmitter PO i erre epe er ete ex RE Mop dub e ee ees 4 26 SDI Duplex eroe terre Sete eee ven Ue oe ed die dee eio 4 26 Audio Extracte 4 27 AES Output Mod le srry re tia tied Dees e ee ete ina elec ee eae ae 4 27 AES Input Modules osse oen oet obere re etie EEE iet cid 4 27 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Contents Audi
31. Output Avalon ST data bus This bus transfers data Serial Digital Interface SDI MegaCore Function User Guide 4 14 Table 4 15 Direct Control Interface Signals Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function Table 4 15 shows the direct control interface signals The direct control interface is internal to the audio extract component Signal Width Direction Description reg clk 0 0 Input Clock for direct control interface signals i 70 Input This signal does the same function as the audio control 7 0 pu register in Table 4 17 This signal does the same function as the audio presence audio presence 7 0 Output register in Table 4 17 i 7 0 Output This signal does the same function as the audio status a 7 register in Table 4 17 a 7 0 Output This signal does the same function as the error status register in Table 4 17 Set bit of this port high for a single cycle of reg_clk to 7 0 input clear the corresponding bit of the error_status signal erron Setting any of bits 3 0 high for clock cycle resets the entire 4 bit error counter This signal does the same function as the FIFO status register fifo status 7 0 Output in Table 4 17 Set high for a single cycle of reg_c1k to clear the underflow saa 09 d or overflow field of the 1 o status signal This signal does the same function as the
32. SDI MegaCore Function User Guide The SDI Audio Embed MegaCore function consists of an encrypted audio embedder core and a register interface block that provides support for an Avalon MM control bus The audio embedder accepts the audio in AES format and stores each channel pair in an input FIFO buffer As the embedder places the audio sample in the FIFO buffer it also records and stores the video clock phase information When accepting the audio in AES format the SDI Audio Embed MegaCore function either maintains the channel status details or replaces the details with the default or the RAM versions February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Parameters 4 3 Table 4 1 lists the parameters for the SDI Audio Embed MegaCore function Table 4 1 SDI Audio Embed MegaCore Function Parameters Parameter Value Description Specifies the maximum number of audio groups supported Number of supported audio 1234 Each audio group consists of 4 audio channels 2 channel groups pairs You must specify all the four channels to the same sample frequencies Async Audio Interface On or Off Turn on to enable the Asynchronous input In this mode the audio clock provides higher than 64 sample rate Frequency of fix_clk 0 24 576 25 50 100 200 Specifies the frequency of the ix_clk signal Channel status RAM 0 1 2 Enables storage of the custom channel s
33. at the start of a block and which channel the audio refers to In Avalon ST audio protocol you are not required to transport the preamble data because the information stored in the data is described by the start of packet end of packet and channel signals Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores 4 23 Instantiating the IP Cores The start of packet end of packet and channel signals indicate the start of the audio sample data and the associated audio channel For a single audio channel the channel signal indicates channel 1 for all valid samples Figure 4 7 shows an example of a single audio channel Figure 4 7 Single Audio Channel Audio data Audio data control packet header identifier header identifier LSB 4 bits A eop W L3 data 23 0 Jos Jos N 301901 E Yvo Xvi X Jva vs Jve v7 Joe Jes Joe Audio sample data Audio control data channel 1 a 1 W Single channel audio data Channel 1 For multiple channels the Avalon ST interface standard allows the packets to interleave across the channels By interleaving the interface allows multiple audio sources to be multiplexed and demultiplexed Figure 4 8 shows an example of two audio channels where the channel signal indicates either channel 1 or channel
34. clock status clock status 7 0 Output register in Table 4 17 Channel status RAM address The contents of the selected csram addr 5 0 Input address will be valid on the csram data signal after one cycle of reg clk P 7 0 Output Channel status data This signal does the same function as coron dara p the channel status RAM in Table 4 17 Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function Register Maps 4 15 Table 4 16 and Table 4 17 list the register maps for SDI Audio Extract MegaCore function Table 4 16 SDI Audio Extract MegaCore Function Register Map Bytes Offset Name 00h Audio Control Register 01h Audio Presence Register 02h Audio Status Register 03h Reserved 04h Error Status Register 05h Reserved 06h FIFO Status Register 07h Clock Status Register 08h 09h Reserved 10h 3Fh Channel Status RAM 0x00 0x01 0x2F Table 4 17 SDI Audio Extract MegaCore Function Register Map Part 1 of 2 Bit Name Access Description Audio Control Register 0 Enable RW Enables the audio extraction component and internal AES output Defines the audio pair that the component extracts For example 3 1 Extract pair RW m 000 Extract the first channel pair of audio signal m 111 Extract the eighth channel pair of audio si
35. clocked audio output FIFO FIFO Reset Register 6 0 Unused WO Reserved 7 FIFO reset WO Resets the clocked audio FIFO Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores 4 21 AES Format AES Format The SDI cores use the AES standard The Audio Engineering Society AES together with the European Broadcasting Union EBU created a digital audio transmission standard known as the AES EBU standard The AES standard is a digital audio standard for transporting digital audio signals serially between devices Using the AES format requires the entire 64 bit AES frame to be sent serially As the AES defines the preambles as biphase mark codes which cannot be directly decoded to 4 bits you must replace the preambles with X 0000b Y 0001b and Z 0010b This internal AES format serializes the bit parallel data words by sending the least significant bits LSB first with the audio sample up to 24 bits Figure 4 4 shows the timing diagram of the internal AES format Figure 4 4 Internal AES Format Timing Diagram clock aud de aud ws aud data uM ee eC y V ZIX Preamble i y Parit DEED _15 0 M0 _5 Y 158 1 A lt gt Word n Left Channel 32 bits Avalo
36. controller controls the transceiver When the interface receives SD SDI the transceiver receiver PLL locks to the receiver reference clock When the interface receives HD SDI the transceiver receiver PLL is first trained by locking to the receiver reference clock When the PLL is locked it can then track the actual receiver data rate If a period of time passes without a valid SDI signal the PLL is retrained with the reference clock and the process is repeated The transceiver controller allows the transceiver to support the reception of both SD SDI and HD SDI data by using an algorithm that alternately searches for one rate then the other First it looks for an HD SDI signal training the PLL then letting it track the serial data rate If a valid HD SDI signal is not seen within 0 1 s the receiver path is reset and the PLL is trained for SD SDI Conversely if a valid SD SDI signal is not seen within 0 1 s the receiver path is reset and the process repeated The transceiver controller also resets and starts searching again if the SDI receiver indicates that the signal is no longer valid For HD SDI operation if 100 consecutive bits with the same value are seen the receiver is reset and the PLL is retrained The maximum legal run length for HD SDI is 59 bits For more information on the Stratix GX transceiver refer to the Stratix GX Device Handbook Transceiver Arria GX Arria Il GX Arria V Cyclone IV GX Cyclone V Stratix
37. data input to the transceiver must be synchronous and phase aligned to the tx coreclk transceiver clock input SD SDI and optionally HD SDI requires a retiming function because of the oversampling logic The transmitter uses a small 16 x 20 FIFO buffer for the retiming Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 17 Block Description For HD SDI the FIFO buffer realigns the parallel video input to the transceiver tx_coreclk clock It is written on every tx_pclk clock and read on every tx coreclk For SD SDI the FIFO buffer also provides the rate conversion required by the transmitter oversampling logic It is written on every other tx pclk using the SD SDI data width conversion logic It is read on every fifth tx 1 This operation ensures that the transmitter oversampling logic is provided with a word of parallel video data on every fifth clock HD SDI Two Times Oversampling This mode performs two times oversampling and runs the transceiver at double rate which gives better output jitter performance This mode requires a higher rate reference clock refer to Table 3 5 on page 3 14 SD SDI Transmitter Oversampling SD SDI requires a 270 Mbps serial data rate which is achieved by transmitting a 1 350 Mbps signal with each bit repeated five times This process ensures that the transceiver runs at a supported frequency Receiver Trans
38. lt megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv set instance assignment name HOLD RELATIONSHIP 0 ns from lt megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks pll sclk cyc rx pll gen u rx pll altpll altpll component c1 ko to lt megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv TimeQuest Timing Analyzer Use the following constraints for the TimeQuest timing analyzer derive pll clocks use tan name create clock name rx 27 refclk period 37 037 waveform 0 000 18 518 get ports rx 27 refclk create clock name tx 27 refclk period 37 037 waveform 0 000 18 518 get ports tx 27 refclk create generated clock name your megacore sdi megacore top sdi megacore top inst sdi clocks u sd i clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv source your megacore sdi megacore top sdi megacore top inst sdi clocks u sd i clocks pll sclk cyc rx pll gen u rx pll altpll altpll component 0 multiply by 2 divide by 5 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide A 10 Appendix A Constraints Constraints for the SDI Soft Transceiver set_max_delay from get_clocks your megacore sdi megacore top sdi megacore top inst sdi clocks u s
39. operation of your design in hardware 5 Purchase a license for the SDI MegaCore function After you have purchased a license for the SDI MegaCore function follow these additional steps 1 Set up licensing 2 Generate a programming file for the Altera device or devices on your board 3 Program the Altera device or devices with the completed design SDI Walkthrough This walkthrough explains how to create an SDI design using the MegaWizard Plug In Manager and the Quartus II software After you generate a custom variation of the SDI MegaCore function you can incorporate it into your overall project Ka You can alternatively use the IP Advisor to help start your SDI MegaCore design On the Quartus II Tools menu point to Advisors and then click IP Advisor The IP Advisor guides you through a series of recommendations for selecting parameterizing evaluating and instantiating an SDI MegaCore function into your design It then guides you through a complete Quartus II compilation of your project This walkthrough requires the following steps 1 Creating a New Quartus II Project 2 Launching MegaWizard Plug In Manager 3 Parameterizing 4 Setting Up Simulation 5 Generating Files Creating a New Quartus 11 Project You must create a new Quartus II project with the New Project Wizard which specifies the working directory for the project assigns the project name and designates the name of the top level des
40. serial input clocks to the TX block 57 This feature is only available for the Arria II Stratix IV GX and HardCopy IV GX device families Click the Receiver Transmitter Options tab 10 Turn on the required receiver options 11 Turn on the required transmitter options 12 Click Next or the EDA tab to display the EDA page For more information about parameters refer to Parameters on page 3 56 and for more information about the protocol options refer to Table 3 20 on page 3 56 For more information about the transceiver options refer to Table 3 21 on page 3 56 For more information about the receiver transmitter options refer to Table 3 22 on page 3 57 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 2 6 Chapter 2 Getting Started SDI Walkthrough Setting Up Simulation CAUTION An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software The model allows for fast functional simulation of IP using industry standard VHDL and Verilog HDL simulators You may only use these models for simulation and expressly not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design To generate an IP functional simulation model for your MegaCore function follow these steps 1 Turn on Generate simulation model 2 Some third party synthesis tools can use a netlist t
41. serial input pin Because these four registers are using four different clock domains place two of the four registers in one LAB and the other two in another LAB Furthermore place the two chosen LABs within the same row regardless of the placement of the serial input Finally do not place the four sampling registers at the immediate rows or columns next to the I O but at the second row or column next to the I O bank This location is because inter LAB interconnects between I O banks and their immediate rows or columns are much faster than core interconnect The following code is an example of a constraint which you can set using the Quartus II Assignment Editor set location assignment PIN 99 to sdi rx set location assignment LC X32 Y17 NO to sdi_megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port soft serdes rx rx soft serdes gen soft serdes rx inst serdes s2p u s2p sample a 0 set location assignment LC X33 Y17 NO to sdi_megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port soft serdes rx rx soft serdes gen soft serdes rx inst serdes s2p u s2p sample b 0 set location assignment LC X32 Y17 N1 to sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port soft serdes rx rx soft serdes gen soft serdes rx inst serdes s2p u s2p sample c 0 set location assignment LC X33 Y17 N1 to sdi megacore top sdi megacore top inst sdi t
42. stable prior to device bring up or core reset Refer to Figure 3 31 and Figure 3 32 TRS locking signal for protocol only receiver mode You can connect this signal to the xx protocol locked pin of the transceiver only receiver block crc error y 1 0 Output CRC error on luma channel HD SDI bit 1 unused bit 0 crc error y Dual link bit 1 link B crc error y bit 0 link A crc error y 3G SDI Level A bit 1 unused bit 0 crc error y 36 501 Level B bit 1 link A cre_error_y bit 0 link B crc error y Refer to Figure 3 33 crc error c 1 0 Output CRC error on chroma channel HD SDI bit 1 unused bit 0 crc error c Dual link bit 1 link B error c bit O link A crc error c 3G SDI Level A bit 1 unused bit 0 crc error c 36 501 Level B bit 1 link A cre_error_c bit 0 link B crc error c Refer to Figure 3 33 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 44 Table 3 16 Interface Signals Part 4 of 5 Chapter 3 Functional Description Signals Signal rx AP Width 1 0 Direction Output Description This is an active picture interval timing signal The receiver aserts this signal when the active picture interval is active HD SDI SD SDI bit 1 unused bit 0 xx ap Dual link bit 1 link B unused bit 0 link A xx ap 3G SDI Level A bit 1 unused bit 0 xx 3G SDI Level B bit 1 link A xx ap bit
43. support The IP core is verified with final timing models for this device family The IP core meets all functional and timing requirements for the device family and can be used in production designs HardCopy Compilation The IP core is verified with final timing models for the HardCopy device family The IP core meets all functional and timing requirements for the device family and can be used in production designs Table 1 4 shows the level of support offered by the SDI MegaCore function for each Altera device family Table 1 4 Device Family Support Part 1 of 2 Device Family Support Arria GX Final Arria II 1 Final Arria V Refer to the What s New in Altera IP page of the Altera website Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 1 About This MegaCore Function 1 3 General Description Table 1 4 Device Family Support Part 2 of 2 Device Family Support Cyclone Final 3 Cyclone Il 2 Final Cyclone III 2 Final Cyclone III LS 2 Final Cyclone IV GX 4 Final Refer to the What s New in Altera IP page of Cyclone V 5 the Altera website HardCopy III IV E HardCopy Compilation HardCopy IV GX HardCopy Compilation Stratix 2 Final Stratix GX Final Stratix 1 2 Final Stratix Il GX Final Stratix 111 2 Final Stratix IV 1 Final Refer to the What s New in Altera I
44. support m Added dual and triple standard information m Added transceiver dynamic reconfiguration information December 2006 7 0 Added support for Cyclone III devices December 2006 6 1 Updated for new MegaWizard Plug In Manager Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Additional Information How to Contact Altera How to Contact Altera Info 3 To locate the most up to date information about Altera products refer to the following table Contact 1 Contact Method Address Technical support Website www altera com support V Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters bold type Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI Indicates directory names project names disk drive names file names file name extensions software utility names an
45. the MegaWizard Plug In Manager parameters for the SDI Clocked Audio Input MegaCore function Table 4 18 SDI Clocked Audio Input MegaCore Function Parameters Parameter Value Description Defines the internal FIFO depth For example a value of 3 means 23 8 Turn on to include the Avalon MM control interface Include Avalon MM control Onorati When you turn on this parameter the register interface signals interface in Table 4 7 appear at the top level Otherwise the direct control interface signals in Table 4 21 appear at the top level FIFO size 3 10 Signals Table 4 19 lists the Avalon ST audio signals when you instantiate the SDI Clocked Audio Input MegaCore function in SOPC Builder Table 4 19 Audio Input Signals Signal Width Direction Description aes clk 0 0 Input Audio input clock aes de 0 0 Input Audio data enable aes ws 0 0 Input Audio word select aes data 0 0 Input Audio data input in internal AES format Table 4 20 lists the Avalon ST audio signals when you instantiate the SDI Clocked Audio Input MegaCore function in SOPC Builder Table 4 20 Avalon ST Audio Signals Part 1 of 2 Signal Width Direction Description Clocked audio clock All the audio input signals are 0 0 Input synchronous to this clock Avalon ST ready signal Assert this signal when the aud ready 0 0 impui device is able to receive dat
46. these steps 1 Set DIP switch 2 1 00 2 The demonstration runs and the LEDs indicate the following conditions a LED D16 blinks indicating the heartbeat of the receiver s recovered clock LED D17 illuminates when the receiver is frame locked LED D18 illuminates when the receiver is TRS locked LED D19 illuminates when the receiver is alignment locked LED D23 illuminates when the data packet of audio group 1 is detected in the incoming SDI stream Figure 4 11 shows the condition of the LEDs Figure 4 11 Condition of LEDs for Transmitting SDI SDI Video Standard De D7 DI D10 011 D12 D16 D17 D18 D19 D20 D21 D22 D23 UN Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores Design Example 4 31 The external waveform monitor WFM700 displays the following observation a Colorbar video pattern b Video format detect is 625i 50 00 Embedded audio standard detected is SMPTE272M Audio channel pairs 1 2 and 3 4 are present Transmit HD SDI with Embedding of Audio Group 1 and 2 To transmit the HD SDI video standard follow these steps 1 Set DIP switch 2 1 01 2 The demonstration runs and the LEDs indicate the following conditions a LED D6 and D7 indicate the internal video pattern generator signal standard LED D8 and D9 indicate the r
47. to 1b when the audio control packet is present in the video stream Error Status Register Counts up to 15 errors since last reset 3 0 Error counter RW RN Write 1b to any bit of this field to reset the entire counter to zero Indicates that an error has been detected in the ancillary packet 4 Ancillary CS fail RW checksum This bit stays set until cleared by writing 1b to this register Indicates that an error has been detected in at least one of the parity fields the ancillary packet parity bit the audio sample parity bit for 2 Ancilary party Tal RW D SDI or the AES sample parity bit for HD SDI This bit stays set until cleared by writing 1b to this register Indicates that an error has been detected in the channel status CRC G This bit stays set until cleared by writing 1b to this register Indicates that an error has been detected in the ECRC that forms part 7 Audio packet ECRC fail RW of the HD audio data packet This bit stays set until cleared by writing 1b to this register FIFO Status Register Reports the amount of data in either the audio output FIFO or the 6 0 FIFO fill level RO Avalon ST audio FIFO when the optional Avalon ST Audio interface is used This register bit goes high if there is either underflow overflow of the audio output FIFO or the overflow of the Avalon ST audio FIFO 7 Overflow Underflow RW depending on the output mode used This register always goes high at the beginning so
48. to the Overview for Cyclone V Device Family chapter in volume 1 of the Cyclone V Device Handbook Only Stratix IV and Stratix V variants with transceivers support all SDI rates SNINSSSSIS lt X S S S x S S lt LI 4 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 1 About This MegaCore Function 1 5 General Description Table 1 6 lists the HD SDI standard video format specification Table 1 6 HD SDI Video Format Specification 1 2 SMPTEZ92M Video Format Pramo pato 2200 1125 60 Yes 2640 1125 50 Yes 274M 1920 x 1080 1920 1080 2200 1125 30 Yes 2640 1125 25 Yes 2750 1125 24 Yes 1650 750 60 Yes 1980 750 50 Yes 296M 1280 x 720 1280 720 3300 750 30 Yes 3960 750 25 Yes 4125 750 24 Yes 260M 1920 x 1035 1920 1035 2200 1125 30 Yes 295M 1920x1080 1920 1080 2 2376 1250 50 Yes Notes to Table 1 6 1 The video formats support 4 2 2 YC gC p 10 bit 4 4 4 RGB YC gC g 4 4 4 4 RGB A YC gC p A 10 bit 4 4 4 YC gC p 12 bit 4 4 4 RGB 12 bit and 4 2 2 YC C 12 bit mapping structures 2 3G SDI is similar to HD SDI except the data bit rate is twice that of HD SDI or approximately 3 Gbps OpenCore Plus Evaluatio
49. 0 tx_status 0 0 gxb_tx_clkout 0 0 sdi_reconfig_fromgxb 16 0 Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description Signals Figure 3 28 Interface Signals for SDI Triple Standard Duplex Instance 3 47 SDI Triple Standard Duplex Instance Pp ist rx rst ix Ix serial refclk refclk rate ix serial refclk ix serial reflclk1 optional pclk sdi rx 0 0 sync switch enable hd search enable sd search enable 3g search txdata 19 0 std 1 0 trs 0 0 In 21 0 enable In enable cr gxb2_cal Sdi recon Sdi recon Sdi recon sdi gxb powerdown 0 0 c 0 0 ig_clk ig_done ig_togxb 3 0 clk gxb4_cal_clk rx_clk rxdata 19 0 rx data valid out 1 0 rx std flag hd sdn 0 0 Ix status 10 0 rx std 1 0 Ix trs IX eav Xyz Xyz valid rx anc data 19 0 rx anc valid 3 0 rx anc error 3 0 IX video format 7 0 sdi 1 0 0 ix status 0 0 gxb_tx_clkout 0 0 sdi_reconfig_fromgxb 16 0 sdi_start_reconfig Figure 3 29 through Figure 3 37 show the behavior of some signals in Table 3 16 Figure 3 29 Power up Reset for the Receiver rst rx rx serial refclk 74 25MHz F Ly Figure 3 30 Power up Reset for the Transmitter mtx 7
50. 0 000 7 407 get ports tx pclk create clock name tx serial 1 period 14 814 waveform 0 000 7 407 get ports tx serial refclk m HD SDI HD SDI dual link rx serial refclk 74 25 MHz tx_pclk 74 25 MHz tx_serial_refclk 74 25 MHz create clock name rx_serial_refclk period 13 468 waveform 0 000 6 734 get ports rx serial refclk create clock name tx pclk period 13 468 waveform 0 000 6 734 get ports tx 1 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Appendix A Constraints A 5 Specifying TimeQuest Timing Analyzer Constraints create clock name tx serial refclk period 13 468 waveform 0 000 6 734 get ports tx serial refclk m 3G SDI rx serial refclk 148 5 MHz tx pclk 148 5 MHz tx serial refclk 148 5 MHz create clock name rx_serial_refclk period 6 734 waveform 0 000 3 367 get ports rx serial refclk create clock name tx pclk period 6 734 waveform 0 000 3 367 get ports tx pclk create clock name tx serial 1 period 6 734 waveform 0 000 3 367 get ports tx serial refclk m Dual standard triple standard SDI create clock name rx_serial_refclk period 6 734 waveform 0 000 3 367 get ports rx serial refclk create clock name tx serial refclk period 6 734 waveform 0 000 3 367 get ports tx serial refclk create clock name tx pclk per
51. 0 link B xx ap rxdata 20N 1 0 Output Receiver parallel data SD SDI uses 9 0 HD SDI uses 20V 1 0 SD SDI bits 19 10 unused bits 9 0 Cb Y Cr Y multiplex HD SDI bits 19 10 Y bits 9 0 C Dual link bits 39 30 Y link B bits 29 20 C link B bits 19 10 Y link A bits 9 0 C link A 3G SDI Level A bits 19 10 Y bits 9 0 C 3G SDI Level B bits 19 10 Cb Y Cr Y multiplex link A bits 9 0 Cb Y Cr Y multiplex link B rx data valid out 1 0 Output Data valid from the oversampling logic Asserted to indicate current data on rxdata is valid Bit 0 of this bus indicates valid data on xxdata When receiving SMPTE 425M B signals in 3G SDI or triple standard bit 1 indicates that data on rxdata is from virtual link A bit 0 indicates the data is from virtual link B Refer to Figure 3 34 and Figure 3 35 and SMPTE425M B 2006 3Gb s Signal Data Serial Interface Source Image Format Mapping rx F 1 0 Output This is a field bit timing signal This signal indicates which video field is currently active For interlaced frame 0 means first field FO while 1 means second field F1 For progressive frame the value is always 0 HD SDI SD bit 1 unused bit 0 xx Dual link bit 1 unused bit 0 xx 36 501 Level A bit 1 0 unused 36 501 Level B bit 1 0 unused 1 0 Output This is a horizontal blanking interval timing signal The receiver asserts this signal when t
52. 00 vane er ae Ee erae A 7 Constraints for the SDI Soft Transceiver eee nee A 7 Non Cyclone Devices lt i sess pda veh de I Pee ae ek hee Dead ee een A 8 Classic Timing Analyzer eg ees Reed eed adr he Les A 8 TimeQuest Timing Analyzer e m emori rd ees ed e mdr eed Pak A 8 Cyclone Devices ONIY impio esce quiete itd A 9 Classic Timing A alyZer esise rrac i su e Rr Rye qa Va us cae re a tes e E E S eds A 9 TimeQuest Dmm AnalyZet s oes tern awed OMe ce dettes cte rete eate iode test A 9 Appendix B Clocking Appendix C Receive and Retransmit Loopback FIFO Buffer asi brii pee abe ERU ER ni hb PR PE RR n C 1 Additional Information Document Revision History I nnn Info 1 How to Contact Altera 2 ve EE EDI pae RE uU rU ER UE Ea N Info 3 Typographic Conventos seid se rs SOY We VERA ney dud ER ee XA Y EP e ag Info 3 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide vi Contents Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide N DTE RYN 1 About This MegaCore Function This user guide describes the Altera Serial Digital Interface SDI MegaCore function and the accompanying SDI Audio IP cores The SDI MegaCore function implem
53. 1 0 Output Serial output tx protocol out 20N 1 0 Output Data out protocol only mode February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Chapter 3 Functional Description Signals Figure 3 26 through Figure 3 28 illustrate the input and output signals in Table 3 16 for SDI triple standard instances Figure 3 26 Interface Signals for SDI Triple Standard Receiver SDI Triple Standard Receiver Instance ISt IX prx serial refclk refclk rate sdi_rx 0 0 sync switch enable hd search enable sd search enable 3g search sdi reconfig clk gxb2 cal clk gxb4 cal sdi reconfig togxb 3 0 sdi reconfig done sdi gxb powerdown IX rxdata 19 0 rx data valid out 1 0 rx std flag hd sdn 0 0 Ix status 10 0 rx std 1 0 Ix trs IX eav IX XyZ Xyz valid rx anc data 19 0 rx anc valid 3 0 rx anc error 3 0 Ix video format 7 0 sdi reconfig fromgxb 16 0 sdi start reconfig HAN Figure 3 27 Interface Signals for SDI Triple Standard Transmitter SDI Triple Standard Transmitter Instance pst tx ix p tx serial refclk prx serial refclk1 optional txdata 19 0 ix std 1 0 tx trs 0 0 ix In 21 0 enable In 0 0 enable crc 0 0 9xb2 cal clk gxb4 cal sdi reconfig sdi reconfig togxb 3 0 sdi gxb powerdown sdi tx 0
54. 10 bit parallel word is converted into a serial data output format A 10 bit shift register loaded at the word rate from the encoder and unloaded at the bit rate of the LVDS output buffer is implemented for that function A PLL that multiplies a 27 MHz reference clock by ten provides the bit rate clock and enables jitter controlled SDI transmit serialization Transmitter Clocks The serializer requires a 270 MHz clock which you can generate from an external source tx sd refclk 270 The 27 MHz parallel video clock tx_pclk samples and processes the parallel video input Transmitter Clock Multiplexer Option This is a new feature introduced in version 11 1 The transmitter block has the option of receiving an additional reference clock to allow dynamic switching between the 1 1000 and 1 1 001 data rates This feature is available in Arria II Stratix IV and HardCopy IV devices By default you can use the tx serial refclk for any normal SDI operations and the tx serial 1 1 additional clock input parameter You can then switch to the clock source selected by using the transceiver dynamic reconfiguration Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 13 Block Description Receiver For the receiver in the soft logic transceiver the serial data stream from the LVDS input buffer is sampled using four different clocks phase shi
55. 3 Functional Description Block Description Figure 3 4 shows the top level block diagram for the SDI receiver Figure 3 4 SDI Receiver Block Diagram SDI RECEIVER Protocol Block Descrambler rx_status 10 0 Ix irs t E Y rx In 21 0 en sync switch d Aligner rxdata 19 0 Ix data valid out 1 0 crc error c 1 0 LN Extract crc error y 1 0 P rx anc data 19 0 gt CRC Extract rx anc valid 3 0 rx anc error 3 0 gt ANC Track rx H 1 0 rx V 1 0 gt TRS Match IX Rn Xyz valid rx xyz rx eav gt Format a 2 e SHE Transceiver Interface Block rst_rx gt GXB RX Sample rx clk rx_serial_refclk nx std t 0 enable_sd_search ernie enable hd search J 4 GXB Control FSM enable 3g search H sdi_reconfig_done aa Triple Rate Detect Q o 9 2 ilo le 9 E BE 9 8 D gj e m 8 TSt IX rx_serial_refclk L3 sdi rx serial data gxb4_cal_clk Transceiver Block sdi_reconfig_clk J sdi reconfig togxb 8 0 sdi_gxb_powerdown yv rx std flag hd sdn sdi start reconfig sdi reconfig fromgxb 16 0 The received data is NRZI decoded and descrambled and then presented as a word aligned parallel output 20 bit for HD SDI 10 bit for SD SDI ref
56. 3 Altera Corporation Chapter 3 Functional Description 3 51 Signals Table 3 18 Status Signals Part 2 of 2 Signal Width Direction Description Receiver status m rx_status 10 dual link ports aligned m rx_status 9 link B frame locked m rx status 8 link B TRS locked six consecutive TRSs with same timing m rx status 7 link B alignment locked a TRS has been spotted and word alignment performed rx status 6 link B receiver in reset rx status 5 link B transceiver PLL locked rx status 4 link A Frame locked rx status 3 link A TRS locked six consecutive TRSs with same timing m rx status 2 link A alignment locked a TRS has been spotted and word alignment performed m rx status 1 link A receiver in reset m rx status 0 link A transceiver PLL locked For non HD SDI dual link versions only bits 4 0 are active For transceiver only receiver block in HD SDI dual link versions only bits 6 5 and 1 0 are active This signal is active high for Stratix GX devices and active low for other Altera transceiver based device families This signal indicates lock of the PLL when the transceiver is training from a refclk source This signal may oscillate when the transceiver is correctly locked to the incoming data in HD SDI or 3G SDI modes In SD SDI modes remain this signal at PLL locked at all times For xx status 3 and rx status 8 the TRS spacing is not required to meet a particular SMPTE standard b
57. 35 MHz Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 19 Block Description Cyclone IV GX devices EP4CGX30 F484 EPACGX50 EPACGX75 EP4CGX110 and EP4CGX150 have eight regular transceiver channels from the upper and lower quads There are four MPLLs and two GPLLs that you can use to clock the transceiver channels Each receiver in EP4CGX50 and EP4CGX75 devices has a clock divider which allows one MPLL to drive all the receiver channels The receiver in EP4CGX110 and EP4CGX150 devices does not have a clock divider which limits each MPLL to drive only one receiver channel to accommodate the different standards within a single quad You must supply two receive reference clocks for example 148 5 MHz and 148 35 MHz to the SDI receiver Implement the PPM detection function in the user logic to detect the ppm difference between the receive reference clock and the recovered clock Based on the difference detected you must switch between the two receive reference clocks by toggling the rx_serial_refclk_clkswitch signal Table 3 16 on page 3 41 For more information about the Cyclone IV GX transceiver architecture refer to Cyclone IV Transceivers Architecture chapter in volume 2 of the Cyclone IV Device Handbook Cyclone V devices have up to 12 transceiver channels The SDI support for Cyclone V transceivers requires the use of the Cyclone V Tra
58. 5 2 The ALTGX_RECONFIG is required for offset cancellation purposes for all transceiver instances a For more information about transceiver dynamic reconfiguration refer to the Arria GX Device Handbook Arria II GX Device Handbook Cyclone IV Device Handbook Stratix II GX Device Handbook and Stratix IV Device Handbook Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode Arria 1 GX HardCopy IV GX Stratix GX Stratix Il GX and Stratix IV GX Transceiver dynamic reconfiguration allows you to change the settings of the device transceivers ALT2GXB or ALTGX at any time Transceiver dynamic reconfiguration reprograms the transceivers to support the three SDI rates The triple standard SDI uses 11 times oversampling for receiving SD SDI Hence only Arria II GX or Stratix II GX transceiver configurations are required as the rates for 3G SDI and SD SDI 11 times are the same February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 3 28 Serial Digital Interface SDI MegaCore Function User Guide Chapter 3 Functional Description Block Description Table 3 10 lists the transceiver dynamic reconfiguration requirements Table 3 10 Transceiver Dynamic Reconfiguration Requirements SDI Standard Receiver Transmitter 1 Duplex 7 SD SDI No Yes Yes HD SDI No Yes Yes 3G SDI No Yes Yes Dual link No Yes Yes Dual standard Yes Yes Yes Triple standar
59. CLKENA U U U U U NES PLL_SCANDATA isse PLL_SCANDATAOUT JUL jJ Let PLL_SCANDONE PLL RECONFIG 4 RESET_ROM_ADDRESS ROM_DATA_IN IL Lh N g WRITE_FROM_ROM 4 p BUSY WRITE_ROM_ENA ROM ADDRESS OUT ILTIIDIILILELU 4 z 3 4 an The following sequence of events occur for handshaking to the reconfiguration logic 1 The SDI MegaCore function sets rx_std 1 0 to the desired video standard This action is performed as part of the video standards detection algorithm 2 The SDI MegaCore function asserts SDI_START_RECONFIG to make a reconfiguration request 3 The reconfig control logic sets WRITE_FROM_ROM line to 1 and signals the ALTPLL_RECONFIG megafunction to write from the ROM 4 The reconfig control logic asserts the PLL_RECONFIG line to 1 and signals the ALTPLL_RECONFIG megafunction to start the reconfiguration process 5 When the reconfiguration has been performed the transceiver s PLL asserts the output signal PLL_SCANDONE to the ALTPLL_RECONFIG megafunction indicating that the PLL is reconfigured and internally indicates to the SDI MegaCore function to start locking to the incoming data 6 The SDI MegaCore function sets the SDI START RECONFIG line to 0 to indicate that the request is completed and acknowledged February 2013 Altera Corporation Serial Digital I
60. Core Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 39 3 Copy and modify the mif files for the HD SDI ROMs and edit word 23 4 Set the appropriate ROMs to use the mif files generated in steps 2 and 3 5 Run the Quartus II compilation For Arria II GX and Stratix IV devices you must set the ROMs to use the fixed mif in the example a2gx_tr source sdi_dprio_siv directory and compile once Ensure that you use the supporting reconfiguration code in the same directory for your design OpenCore Plus Time Out Behavior Signals 57 Signals OpenCore Plus hardware evaluation can support the following two modes of operation m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions For MegaCore functions the untethered time out is 1 hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires and the rst signal goes high For more information on OpenCore Plus hardware evaluation r
61. D SDI 1 140 832 HD SDI 1 122 808 3G SDI 1 402 997 Cyclone V Dual link HD SDI 2 351 1 696 Dual standard receiver 1 539 1 042 Dual standard transmitter 352 260 Triple standard 2 217 1 508 Stratix 50 801 875 Stratix 11 SD SDI 581 533 Stratix III SD SDI 602 565 50 801 1 182 HD SDI 1 316 Stratix GX Dual link HD SDI 2 703 Dual standard 1 819 SD SDI 834 640 HD SDI 919 683 3G SDI 1 161 865 Stratix I GX Dual link HD SDI 1 906 1 423 Dual standard receiver 1 188 831 Dual standard transmitter m 247 185 Triple standard 1 794 1 215 SD SDI 839 680 HD SDI 978 833 3G SDI 1 259 1 015 Stratix IV GX Dual link HD SDI 2 029 1 711 Dual standard receiver 1 257 926 Dual standard transmitter 267 180 Triple standard 1 891 1 305 SD SDI 913 707 HD SDI 955 703 Stratix V 3G SDI 1 126 823 Dual link HD SDI 2 049 1 522 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 1 8 Chapter 1 About This MegaCore Function Resource Utilization Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide N DTE BAN 2 Getting Started Design Flow To evaluate the SDI MegaCore function using the OpenCore Plus feature follow these steps in your design flow 1 Obtain and install the SDI MegaCore function The SDI MegaCore function
62. Extract MegaCore Function Block Diagram ye aud_clk vid_clk AES A i to i Sample FIFO Avalon ST Audio _ Avalon ST Packet Find i Audio Extract f Clock Recovery Audio Extract with Avalon Only Channel Error Detection Status RAM 48 KHz Clock Core Register Interface Avalon MM gt Audio Extract or Audio Extract with Avalon The SDI Audio Extract MegaCore function consists of the audio extraction core and a register interface block that provides support for an Avalon MM control bus The clock recovery block recreates a 64 x sample rate clock which you can use to clock the audio output logic As the component recreates this clock from a 200 MHz reference clock the created clock may have a higher jitter than is desirable Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores 4 11 SDI Audio Extract MegaCore Function A digital PLL synchronizes this created clock to a 24 kHz reference source For the HD SDI embedded audio the 24 kHz reference source is the embedded clock phase information For the SD SDI embedded audio where the embedded clock phase data is not present you can create the 24 kHz reference signal directly from the video clock Figure 43 shows the clock recovery block diagram Figure 4 3 Clock Recovery Block Diagram Video standard
63. G SDI dual standard triple standard SDI set clock groups exclusive group get clocks rx serial refclk group get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcsO clkout set clock groups exclusive group get clocks tx pclk group get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto_generated transmit_pcs0 clkout Set false path from get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port switchline to get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcsO clkout m HD SDIduallink for the additional channel set clock groups exclusive group get clocks rx serial refclk group get clocks sdi megacore top inst sdi txrx port gen 1 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcsO clkout Set false path from get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port switchline to get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcs0 clkout set clock groups exclusive group get clocks tx pclk group get clocks sdi megacore top inst sdi txrx port gen 1 u txrx port gen duplex al
64. GX Stratix IV GX and Stratix V Devices The Arria GX Arria II GX Arria V Cyclone IV GX Stratix II GX Stratix IV GX or Stratix V transceiver deserializes the high speed serial input For HD SDI the CDR function performs the deserialization and locks the receiver PLL to the receiver data For SD SDI the transceiver provides a fixed frequency oversample of the serial data with the receiver PLL constantly locked to a reference clock which allows the transceiver to support the 270 Mbps data rate The transceiver can process either SD SDI or HD SDI data The data rate can be automatically detected so that the interface can handle both SD SDI and HD SDI without the need for device reconfiguration Arria GX Arria II GX Arria V Stratix II GX Stratix IV GX and Stratix V devices have two transmitter PLLs per quad Each quad allows two independent transmitter rates Receivers in a quad share a common training clock but have independent receiver PLLs Because the same training clock is used for SD SDI and HD SDI receivers can accommodate the different standards within a single quad Arria II GX including Arria II GZ and Stratix IV GX devices also provide the option for you to enable an additional serial reference clock port This additional clock port allows you to have two different clock rates for different data rates using a single transceiver block with the ability to switch between the desired clock rates for example 148 5 MHz and 148
65. GX devices the contents of the ROM are set by mif The Quartus II software outputs the mif for the configuration settings of the ALT2GXB instance that is set by the design This file generation is not performed by default You must adjust the Fitter settings On the Assignments menu click Settings In the Settings dialog box click Fitter Settings and then click More Settings In the Name list select Generate GXB Reconfig MIF and in the Setting list select On February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 38 Chapter 3 Functional Description Block Description For the SDI MegaCore function the Quartus II generated mif is for 3G SDI setup These mif files relate to a specific ALT2GXB instance in the device Therefore you cannot use the same mif files or ROMs for multiple ALT2GXBs in the same device For the SDI MegaCore function the differences between the ALT2GXB setups are very small Only three bits of the ROM change between the HD SDI and SD SDI or 3G SDI setups The three bits are in word 23 and you can see in the following examples of the mif files Example 3 1 and Example 3 2 Example 3 1 3G SDI ROM Content Example 22 1010100000011111 23 0111110000010100 24 0001000101101000 Example 3 2 HD SDI ROM Content Generated from 3G SDI Version 22 1010100000011111 23 0111110000001101 24 0001000101101000 This particular word is stati
66. I MegaCore function in the ip sdi example directory This design is targeted at the Stratix II GX audio video development kit St For more information about the example design refer to AN 339 Serial Digital Interface Demonstration for Stratix GX Devices and for information about the development kit refer to Audio Video Development Kit Stratix II GX Edition Programming a Device After you have compiled the example design you can program your targeted Altera device to verify the design in hardware With Altera s free OpenCore Plus evaluation feature you can evaluate the SDI MegaCore function before you obtain a license OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time limited programming file St For more information about OpenCore Plus hardware evaluation using the SDI MegaCore function refer to OpenCore Plus Evaluation on page 1 5 OpenCore Plus Time Out Behavior on page 3 39 and AN 320 OpenCore Plus Evaluation of Megafunctions Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started 2 15 Setting Up Licensing Setting Up Licensing You must purchase a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production After you purchase a license for SDI MegaCore function you can request a license file from
67. LN words LNO LN1 overwrite the two words that follow the XYZ word of the EAV TRS sequence The same value is included in the luma and chroma channels For correct LN insertion you must assert the tx trs signal must be asserted for the first word of both EAV and SAV TRSs refer to Figure 3 31 on page 3 47 and Figure 3 32 on page 3 48 If the system does not know the line number you can implement logic to detect the output video format and then determine the current line This function is outside the scope of this SDI MegaCore function HD SDI CRC Generation and Insertion SMPTE292M section 5 5 defines a CRC that is included in the chroma and luma channels for each HD SDI video line The HD SDI CRC module generates formats and inserts the required CRC in the output data The HD SDI CRC module identifies the words that you must include in the CRC calculation and also determines where you must insert the words in the output data The formatted CRC data words YCRO and YCR1 for the luma channel CCRO and CCR1 for the chroma channel overwrite the two words that follow the line number words after the EAV A separate calculation is provided for the luma and chroma channels Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description Block Description 3 5 The CRC is calculated for all words in the active digital line starting with the first active wor
68. LTGX wrapper file You can access the ALTGX wrapper files for Arria II GX Arria V Cyclone IV GX Stratix II GX and Stratix IV GX configurations You can use one of the two following ways to access the ALTGX wrapper files m Edit the ALTGX wrapper file using legal range provided in the respective device handbooks m Use analog control through the ALTGX_RECONFIG megafunction Do not reinstantiate the customized ALTGX wrapper file using the MegaWizard Plug In Manager so that you do not lose the default content of the wrapper file after regeneration Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 11 Block Description Editing the ALTGX Wrapper File If you want to change the settings of the parameters edit the legal ranges in the ALTGX wrapper file For example if you want to change the voltage output differential control setting from 4 to 7 change the following line in the wrapper file alt4gxb component vod ctrl setting 4 to this line alt4gxb component vod ctrl setting 7 know the exact legal ranges for a specific Altera device refer to the respective device handbooks Using Analog Control If you want the flexibility to access and control the ALTGX settings use the ALTGX RECONFIG megafunction to enable analog reconfiguration You can use the analog control to edit the default settings of the following transceiver parameters
69. P page of Stratix V 1 the Altera website Other device families No support Notes to Table 1 4 If you have only 27 MHz to drive the SDI MegaCore function in SD SDI mode you require an additional PLL to generate a 67 5 MHz reference clock The Cyclone series of devices and Stratix Stratix Il and Stratix IIl devices only support soft serializer deserializer SERDES Cyclone device support is limited to 6 speed grade devices Transceiver dynamic configuration with channel reconfiguration mode is not supported for dual and triple standard in EPACGX110 and EPACGX150 devices Use transceiver dynamic reconfiguration with PLL reconfiguration mode instead The Cyclone V devices does not support the SDI Audio IP cores General Description The Society of Motion Picture and Television Engineers SMPTE have defined an SDI that video system designers use widely as an interconnect between equipment in video production facilities The SDI MegaCore function can handle the following SDI data rates 270 megabits per second Mbps SD SDI as defined by SMPTE259M 1997 10 Bit 4 2 2 Component Serial Digital Interface 1 5 Gbps HD SDI as defined by SMPTE292M 1998 Bit Serial Digital Interface for High Definition Television Systems 3 Gbps SDI as defined by SMPTE425M AB 2006 3Gb s Signal Data Serial Interface Source Image Format Mapping Preliminary support for dual link SDI as defined by SMPTE372M Dual Link 1 5Gb s Digit
70. Serial Digital Interface SDI MegaCore Function RYN 101 Innovation Drive San Jose CA 95134 www altera com UG SDI1005 16 0 User Guide Document last updated for Altera Complete Design Suite version Document publication date 12 1 February 2013 NA Feedback Subscribe 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks eb Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide N DTE RYN Conten
71. Transceiver Dynamic Reconfiguration Signals Part 1 of 2 Signal SDI RECONFIG DONE Direction Input Description Indicates back to MegaCore function that reconfiguration has finished This signal is not required for PLL reconfiguration SDI RECONFIG 1 9 4 Input Data input for the embedded transceiver instance 2 Data width m For all devices except Arria V Cyclone V and Stratix V SDI RECONFIG TOGXB 3 0 m SDI RECONFIG TOGXB 3 is negligible for Arria GX and Stratix Il GX m For Arria V Cyclone V and Stratix V devices SDI RECONFIG TOGXB 140N 1 0 or SDI_RECONFIG_TOGXB 70N 1 0 if the receiver in the interface settings is selected SDI RECONFIG CLK 8 SDI GXB POWERDOWN Input Input Clock input for the embedded transceiver instance 2 This signal is not applicable for Arria V Cyclone V and Stratix V devices Powers down and resets circuits in all transceiver instance 9 This signal is not applicable for Arria V Cyclone V and Stratix V devices SDI START RECONFIG Output Request from MegaCore function to start reconfiguration SDI RECONFIG FROMGXB 9 4 Output Data output from embedded transceiver instance 2 9 Data width m For all devices except Arria V Cyclone V and Stratix V SDI RECONFIG FROMGXB 17N 1 0 m SDI RECONFIG FROMGXB 16 1 are negligible for Arria GX and Stratix 11 GX m SDI RECONFIG FROMGXB
72. a Avalon ST valid signal The MegaCore function 0 0 Output asserts this signal when it is outputs data February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 4 18 Table 4 20 Avalon ST Audio Signals Part 2 of 2 Chapter 4 SDI Audio IP Cores Clocked Audio Input MegaCore Function Signal Width Direction Description Avalon ST start of packet signal The MegaCore aud_sop 0 0 Output function asserts this signal when it is starting a new frame Avalon ST end of packet signal The MegaCore aud cup 0 0 Output function asserts this signal when it is ending a frame Avalon ST data bus The MegaCore function asserts quo data 23 0 this signal to transfer data Table 4 21 lists the direct control interface signals The direct control interface is internal to the audio extract component Table 4 21 Direct Control Interface Signals Signal Width Direction Description channel0 7 0 Input Indicates the channel number of audio channel 1 11 7 0 Input Indicates the channel number of audio channel 2 fifo reset 7 0 Input Drive bit 7 high to reset the clocked audio input FIFO buffer Assert this signal when the clocked audio input FIFO buffer fifo status 0 0 Output overflows For register interface signals refer to Table 4 7 All SDI audio cores use the same register interface signals Register Maps
73. a_valid_out 0 Ix data valid out 1 Figure 3 35 Behavior of rx data valid Signal 425MB mx clk 148 5 MHz rxdata 19 10 Y3FF C 3FF Y Y 000 C Y 000 Y 000 C Y 000 Y J XYZ C rxdata 9 0 Y3FF C 3FF Y 0006 J 000 Y f 000 C 000 Y XYZ C rx data valid out 0 rx data valid out 1 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 49 Signals Figure 3 36 Behavior of rx trs rx xyz xyz valid and rx eav Signals 425MA x clk 148 5 MHz mdata 19 10 y 3FF 00j oe XC 090 X380 X WONN 9 0 Y o e y c Y SFY 090 W nts i i i i IX XyZ xyz valid IX eav I d Figure 3 37 Behavior of rx_trs rx_xyz xyz_valid and rx_eav Signals 425MB x clk 148 5 MHz rxdata 19 10 y SF 000 jc T JMMC X ser Y o Y Y Nin rxdata 9 0 X 3FF 000 joe AC X ser T 090 X aeo Y MEE qm del Ra meli GS spl xyz xyz_valid IX eav Table 3 17 lists the 8 bit rece
74. able 3 3 EAV and SAV Sequences Video Standard EAV and SAV Sequences SDI 3FF 000 000 HD SDI 3FF 3FF 000 000 000 000 3G SDI Level A 3FF 3FF 000 000 000 000 3G SDI Level B 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000 The aligner matches the selected pattern in the descrambled receiver data If the pattern is detected at any of the possible word alignments then a flag is raised and the matched alignment is indicated This process is applied continuously to the receiver data The second stage of the aligner determines the correct word alignment for the data It looks for three consecutive TRSs with the same alignment and then stores that alignment If two consecutive TRSs are subsequently detected with a different alignment then this new alignment is stored The final stage of the aligner applies a barrel shift function to the received data to generate the correctly aligned parallel word output For this SDI MegaCore function the barrel shifter allows the design to instantly switch from one alignment to another Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 9 Block Description Video Timing Flags Extraction The TRS match module extracts the F V and H video timing flags from the received data You can use these flags for receiver format detection or in the implementation of a flywheel function The TRS match module also ident
75. al Interface for 1920x1080 and 2048x1080 Picture Formats February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 1 4 Chapter 1 About This MegaCore Function General Description m Dual standard support for 270 Mbps and 1 5 Gbps SDI m Triple standard support for 270 Mbps 1 5 Gbps and 3 Gbps SDI m SMPTE425M Level A support direct source image formatting m SMPTE425M Level B support dual link mapping Table 1 5 lists the SDI standard support for various devices Table 1 5 SDI Standard Support 1 SDI Standard SD SDI HD SDI 3G SDI HD SDI Dual Link Dual Standard Triple Standard v v4 v v4 v v4 v4 v v4 v4 v4 v4 v v v4 Device Family Arria GX Arria 1 GX Arria V Cyclone Cyclone Il Cyclone 111 Cyclone IV GX EP4CGX15 EP4CGX30 Cyclone IV GX EP4CGX30 F484 50 EP4CGX75 EP4CGX110 EP4CGX150 Cyclone V 9 HardCopy IV GX Stratix Stratix GX Stratix 11 Stratix GX Stratix 111 Stratix IV 4 Stratix V 4 Notes to Table 1 5 All standards other than SD SDI require a transceiver based or GX device 2 The HD SDI dual link supports timing difference up to 40 ns between link A and link B fulfilling the SMPTE372M requirement 3 The 3G SDI standard is not supported in Cyclone V devices with transceiver speed grade 7 due to the excessive data rate required For more information about the Cyclone V device refer
76. all devices barring Arria II GX and Stratix IV devices For Arria II GX and Stratix IV devices the logic modifies the ROM read data when it reads word 29 For examples refer to the intercept logic exampleNs2gx trNsourceNsdi dprioNsdi mif intercept v and exampleNa2gx trNsourceNsdi dprio sivNsdi mif intercept siv v February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 32 Chapter 3 Functional Description Block Description The transceiver megafunction is embedded inside the SDI MegaCore function The reprogramming ports reconfig togxb 3 0 and reconfig fromgxb Nx16 1 gt 0 for the transceiver megafunction are brought to the top level interfaces of the MegaCore function This interface only connects to the ALT2GXB RECONFIG or ALTGX RECONFIG block Figure 3 19 shows the block diagram of how the SDI MegaCore function and the ALT2GXB RECONFIG megafunction are connected when you use the transmitter clock multiplexer feature Figure 3 20 Transceiver Dynamic Reconfiguration for Transmitter Clock Multiplexer Block Diagram ROM Hold MIF ALT2GXB ROM CLK ENABLE RECONFIG TOGXB 2 0 LL ROM ADDRESS RECONFIG INST RECONFIG FROMGXBIO User Logic Encrypted RECONFIG Megafunction Protocol Encrypted SDI IP Core ROM DATA OUT SDI IP Core Duplex SDI RECONFIG DONE ALT2GXB INST I
77. ally generated video The transmitter transmits the serial signal through a BNC cable to the receiver of the SDI duplex instance SDI Duplex The triple standard SDI duplex provides a full duplex SD SDI HD SDI and 3G SDI standards The SDI duplex instance routes the received data to the SDI Audio Extract MegaCore function to extract the AES audio The SDI Audio Embed MegaCore function embeds the internally generated audio in AES format into the internally generated video The transmitter in this duplex connects its output to the external waveform monitor such as the WFM700 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores 4 27 Design Example Audio Extract The Audio Extract MegaCore function extracts the embedded AES audio from the SDI stream The Audio Extract MegaCore function routes the extracted AES audio to the AES output of the daughter card AES Output Module The AES output module converts the aud_de aud_ws and aud_data signals to AES signal This module configures the extracted internal AES audio signal aud_data without the biphase mark encoding When this module interfaces with the Audio Extract MegaCore function it must use the same clock as the Audio Extract MegaCore function AES Input Module The AES input module converts the AES signal to aud_de aud_ws and aud_data internal AES signals to interface with Audio Embed P1 When this module int
78. aps for SDI Audio Embed MegaCore function Table 4 8 SDI Audio Embed MegaCore Function Register Map Table 4 9 SDI Audio Embed MegaCore Function Register Map Bytes Offset Name 00h Audio Control Register 01h Extended Control Register 02h Video Status Register 03h Audio Status Register 04h Channel Status Control Registers 3 0 05h Channel Status Control Registers 7 4 06h 07h Reserved 08h Sine Channel 1 Frequency 09h Sine Channel 2 Frequency OAh Sine Channel 3 Frequency OBh Sine Channel 4 Frequency OCh OFh Reserved 10h 3Fh Channel Status RAM 0x00 0x01 0x2F Bit Name Access Description Audio Control Register Enables the embedding of each audio group When working with HD SDI or 3G SDI video embedding of the audio control packet is also enabled when one or more audio groups are enabled The following bits correspond to the number of audio groups you 3 0 Audio group enable RW specify m Bit 0 Audio group 1 m Bit 1 Audio group 2 m Bit 2 Audio group 3 m Bit 3 Audio group 4 7 4 Unused Reserved for future use Extended Control Register When you specify the Channel Status RAM parameter to 2 this field 2 0 Channel status RAM RW selects the channel pair for the RAM written to by registers 10h to select 3Fh If you specify the Channel Status RAM parameter to 0 or 1 ignore this signal 3 Unused Reserved for futur
79. apter 3 Functional Description Block Description Figure 3 15 and Figure 3 16 show how one or two consecutive missing EAVs do not cause the trs_locked signal to deassert Figure 3 15 Single Missing EAV Signal Error in EAV SAV data E 0 I EAV SAV SAV trs_strobe gn n IL dl prev eav missed g host_eav trs_locked Figure 3 16 Two Consecutive Missing EAV Signal 1st error in EAV SAV data EAV SAV 2nd error in EAV SAV trs_strobe iL H f prev_eav_missed g host_eav trs_locked Figure 3 17 shows how three consecutive missing EAVs cause the trs_locked signal to deassert Figure 3 17 Three Consecutive Missing EAV Signal 1st error in EAV SAV 3rderrorinEAV SAV data EAV SAV 2nd error in EAV SAV trs_strobe l T prev eav missed g host eav trs_locked The frame_locked signal detects TRS EAV inspects the transition of field F and vertical V synchronizations and then counts the line number The inspecting transitions on the F and V synchronizations provide the frame timing The line count value is stored if there is a rising or falling edge on the F and V synchronizations through the frame The stored count values are compared over multiple frames to make sure they are stable before the frame_locked signal is asserted The frame_locked signal deasserts when there are
80. ault ROM CLK ENABLE ALT2GXB_INST ALT2GXB gt ROM_ADDRESS RECONFIG_INST g RECONFIG_FROMGXB O HD M L value Protocol if ROM ADDRESS RX PMA f Encrypted 5 Note to Figure 3 19 3G SB M L value ROM_DATA_OUT SDI IP Core Duplex SDI_RECONFIG_DONE Pa ALT2GXB_INST RECONFIG Control and Intercept select hd User Logic SPES TART RECONFIG 1 Protocol A RX_STD SDI IP Core Transmitter ALT2GXB_INST User Logic Encrypted RECONFIG Megafunction Protocol IP Core 1 The SDI_START_RECONFIG and SDI RECONFIG DONE signals are not connected to the SDI MegaCore transmitter The ALT2GXB RECONFIG block handles the programming of the ROM contents into the transceiver megafunction It performs data serialization and also handles protection of certain data bits in the serial stream You can only connect this block to the reprogramming ports of the transceiver instance The ROM holds the transceiver setting information for the 3G SDI video standard As the setup for SD SDI is similar to 3G SDI only two settings are required one for SD SDI and 3G SDI and one for HD SDI The reconfiguration control and intercept user logic selects the correct transceiver setting and also provides the handshaking between the SDI MegaCore function and the ALT2GXB RECONFIG block The logic modifies the ROM read data when it reads word 23 for
81. bad F or V synchronizations or when there is a rising edge from frame to frame The frame_locked signal also deasserts when the trs_locked signal deasserts When the frame_locked signal is zero the frame is invalid and the receiver is not considered to receive reliable video data Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 27 Block Description Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers Dual standard and triple standard SDI receivers or receivers of duplex SDIs require the transceiver dynamic reconfiguration feature of Arria GX Arria II GX Cyclone IV GX Stratix II GX and Stratix IV devices to perform autodetection and locking to different SDI rates Table 3 9 lists the transceiver dynamic reconfiguration support for Arria II GX Cyclone IV HardCopy IV Gx Stratix GX Stratix GX and Stratix IV GX devices Table 3 9 Transceiver Dynamic Reconfiguration Support for Altera Devices 1 Transceiver Dynamic Arria II GX p ela Stratix GX Cyclone IV GX T Reconfiguration Support and Stratix IV GX EPACGX50 EP4CGX75 EP4CGX150 2 Channel Reconfiguration Yes Yes No PLL Reconfiguration No Yes Yes Transceiver Reconfiguration No No No Note to Table 3 9 1 The SDI MegaCore function versions 10 1 and later do not support MIF generation for EP4CGX30 F484 EPACGX50 and EP4CGX7
82. braries b Type path ip into the Library name field where path is the directory in which you installed the SDI c Click Add to add the path to the Quartus II project d Click OK to save the library path in the project 7 Click Next to close this page and display the New Project Wizard Family amp Device Settings page 8 Onthe New Project Wizard Family amp Device Settings page choose the target device family in the Family list 9 The remaining pages in the New Project Wizard are optional Click Finish to complete the Quartus II project Launching MegaWizard Plug In Manager To launch the MegaWizard Plug In Manager in the Quartus II software follow these steps 1 On the Tools menu click MegaWizard Plug In Manager 57 For more information about how to use the MegaWizard Plug In Manager refer to Quartus II Help 2 Specify that you want to create a new custom megafunction variation and click Next 3 Expand the Interfaces gt SDI folder and click SDI lt version gt 4 Selectthe output file type for your design the wizard supports VHDL and Verilog HDL Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started SDI Walkthrough 2 5 The MegaWizard Plug In Manager shows the project path that you specified in the New Project Wizard Append a variation name for the MegaCore function output files lt project path gt lt variation name gt
83. c error c Signals 1 rx_clk rxdata 19 0 Jar Y ooo Too xvz unt esca i ooo xvz unt jora EDI rxdata 9 0 js Y 000 lw i uni onc enca js Y ooo jw LN1 esca WE v uw i 3 LE p 2 v rx In i i i i q i crc error y V crc_error_c 7 2 3 Notes to Figure 3 33 1 When a CRC error occurs the crc error y or crc_error_c signal goes high until the next line For HD Dual Link and 3G Level A only crc error y 0 and crc error c 0 signals are used For 3G Level B crc_error_y 0 and crc error c 0 signals are used for link and crc error y 1 and crc error c 1 signals are used for link A 2 The CRC error signals are asserted after the CRC data checked when the rx_H signal is high A high CRC signal indicates that there is error in the previous line data In this case both Y and C have CRC error 3 The CRC error signals are deasserted on the next line after the CRC data is checked Figure 3 34 Behavior of rx data valid Signal 425MA rx_clk 148 5 MHz rxdata 19 10 oov oov X XYZY rxdata 9 0 __3FF C 0c 00006 X rx_dat
84. c over all SDI ALT2GXB instances in the device You can generate the mif for the HD SDI ROM from the mif that the Quartus II software generates by modifying this memory word within the mif Starting Channel Number To correctly address each transceiver by the ALT2GXB_RECONFIG block you must specify a starting channel number for each transceiver instance in the parameter editor This starting channel number must meet certain criteria for the transceiver dynamic reconfiguration T For more information about the criteria refer to the Arria GX Device Handbook Arria II GX Device Handbook Stratix II GX Device Handbook and Stratix IV Device Handbook Quartus Il Design Flow For Arria GX and Stratix II GX devices SDI MegaCore function designs using transceiver dynamic reconfiguration require a two pass compilation The first compilation writes the ALT2GXB setup as a mif During this compilation you must set the mif ROMs in the design to have a dummy mif for their initialization Before the second compilation set the initialization mif files of the ROMs to be generated in the first compilation This second compilation therefore sets up the ROMs to have the correct settings for the ALT2GXB megafunction This process requires the following steps 1 Set the reconfiguration ROMs in the designs with a dummy mif 2 Run the Quartus II compilation and ensure that the software writes the mif files Serial Digital Interface SDI Mega
85. cation 1 0 standard assignments and drive strength If you launch IP Toolbench outside of the Pin Planner application you must explicitly load this file to use Pin Planner variation name sdi sdc Contains timing constraints for your SDI variation variation name constraints tcl Quartus II file that sets the Quartus II to use TimeQuest timing analyzer and patches the generated sdc script with a new clock name If your top level design clock pin names do not match the default clock pin names or a prefixed version edit the assignments in this file variation gt or vho VHDL or Verilog HDL IP functional simulation model variation name hb v A Verilog HDL black box file for the MegaCore function variation Use this file when using a third party EDA tool to synthesize your design variation name gip Contains Quartus Il project information for your MegaCore function variations You can now integrate your custom MegaCore function variation into your design simulate and compile February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 2 8 Simulating the Design Chapter 2 Getting Started Simulating the Design This section describes the following simulation techniques Simulate with IP Functional Simulation Models m Simulating with the ModelSim Simulator m Simulating in Third Party Simulation Tools Using NativeL
86. ceiver Interface Altera provides a transceiver interface which interfaces the transceiver to the SDI function The transceiver interface implements the following functions m SD SDI Receiver Oversampling m Transceiver Controller When using the two times oversampling transmitters in Stratix GX devices you cannot have HD SDI receivers in the same quad The quad requires the same frequency reference clocks for both the receivers and transmitters within a quad HD SDI receivers and two times oversampling transmitters have different frequency reference clocks refer to Table 3 5 on page 3 14 and Table 3 6 on page 3 15 SD SDI Receiver Oversampling The Stratix GX transceiver does not support CDR for data rates less than 500 Mbps The receiver uses fixed frequency oversampling for the reception of 270 Mbps SD SDI The serial data is sampled by the transceiver at 1 350 Mbps and the original 270 Mbps data is extracted by the SD SDI receiver oversampling logic Figure 3 10 shows an example of the receiver data timing Figure 3 10 Receiver Data Timing rx olk 67 5MHz rxdata rx_data_valid_out February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 3 18 Chapter 3 Functional Description Block Description Transceiver Controller To achieve the desired receiver functionality for the SDI the transceiver
87. ck Description Figure 3 19 shows a flow chart of the SDI dynamic reconfiguration process for transceiver based devices Figure 3 18 Dynamic Reconfiguration Process Flow for Transceiver based Devices SDI MegaCore Receiver Duplex Normal Operation 4 3 4 No Data Rate Change Start e SDI START RECONFIG Reconfiguration in Process Reconfiguration Done Notes to Figure 3 18 ALT2GXB_RECONFIG Control Logic gt Idle Reconfiguration in Process 4 Yes ALT2GXB RECONFIG Busy Write to ALT2GXB Last ROM Address Reconfiguration Done SDI RECONFIG DONE 1 SDI MegaCore Receiver Duplex asserts xx analogreset and rx digitalreset signals to transceiver when the transceiver is being reconfigured 2 The rx analogreset signal deasserts when the transceiver is completely reconfigured and xx digitalreset signal deasserts when rx p11 is stable Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 31 Block Description Figure 3 19 shows the block diagram of how the SDI MegaCore function and the ALT2GXB_RECONFIG megafunction are connected Figure 3 19 Transceiver Dynamic Reconfiguration for Receiver Block Diagram SDI IP Core Receiver ROM Hold MIF 3G by def
88. clk topl Locate tx_serial_refclk_name in the script and change totx serial refclk topl 57 The SDI triple standard transmitter has a transceiver top level reference clock tx serial refclk 3 Execute the Tcl script to patch the generated sdc script with the new clock names 57 A back up copy of the sdc script is created before the patch is made and any edits that were previously made to the sdc script are preserved 4 Execute the Tcl script in the Quartus II software and follow these steps a On the Tools menu click Tcl script b Select the Tcl script of the instance SDI triple standard transmitter and click Run 5 Perform steps 2 to 4 for the SDI triple standard receiver instance Multiple Channels The following section describes what you must do if your design requires multiple channels using four instances of SDI triple standard transmitter and four instances of SDI triple standard receiver In this case assume that you must fit all instances into Transceiver Bank 1 and 2 as shown in Figure 2 4 and the SDI instances in both banks have the same video standard You do not have to regenerate the SDI instances in Transceiver Bank 2 Figure 2 4 Instantiating Multiple Channels of SDI Instances Sharing Same Reference Clock SYSTEM TOP LEVEL Transceiver Bank 1 tx serial refclk top1 p SD triple standard transmitter A starting_channel_number 0 SDI triple standard receiver A star
89. clock domain for the receiver Issues a reset to the SDI MegaCore function after rst rx 1 Input power up to ensure reliable operation Refer to Figure 3 29 For HD SDI dual link receiver assert this signal when both link A and link B are ready for the first time February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide Table 3 16 Interface Signals Part 2 of 5 Chapter 3 Functional Description Signals Signal rst_tx Width Direction Input Description Reset signal which holds the transmitter in reset The reset synchronization for the transmitter is handled within the SDI MegaCore function The video mode tx_std and clocks must be set up and stable before device bring up or core reset Issues a reset to the SDI MegaCore function after power up to ensure reliable operation Refer to Figure 3 30 rx serial refclk clkswitch Input Reference clock switching Available only when you use a Cyclone IV GX device Toggle between xx serial refclk and rx serial refclk1 at every positive edge triggered rx protocol clk N 1 0 Input External clock for protocol data rx protocol hd sdn N 1 0 Input Selection of HD SDI or SD SDI processing for dual or triple standard protocol block This signal only appears on dual or triple standard protocol blocks and indicates 3G SDI 1 HD SDI 1 or SD SDI 0 data on the rx protocol in signal Yo
90. configured This signal holds the scan data input to the ES transceiver PLL for the dynamically reconfigurable bits PLL SCANDONE 8 9 Output Determines when the transceiver PLL is reconfigured PLL SCANDATAOUT Output This signal holds the transceiver PLL scan data output from the dynamically reconfigurable bits Notes to Table 3 19 1 These signals must be connected directly to a reconfiguration megafunction 2 The transceivers are available for Arria GX Arria II GX Arria V Cyclone IV GX Cyclone V Hardcopy IV GX Stratix II GX Stratix IV and Stratix V devices only 3 SDI transmitters do not require the use of transceiver dynamic reconfiguration but to enable the cores to merge into a transceiver quad that has transceiver dynamic reconfiguration enabled you must connect these ports correctly 4 In the Quartus II software version 8 1 and later the Stratix IV transceivers requires receiver buffer calibration through an ALTGX RECONFIG transceiver dynamic reconfiguration controller The additional RECONFIG port bits are used for receiver buffer calibration You must connect these ports to the ALTGX RECONFIG controller externally For further information on the receiver buffer calibration refer to the Stratix IV Dynamic Reconfiguration chapter in volume 2 of the Stratix IV Device Handbook If you are using the Quartus II software version 10 1 make sure to upgrade the SDI MegaCore function to version 10 1 as well c
91. d Figure 3 39 Behavior of rx_anc_data valid error Signals 425MB o0 0 0 148 5 MHz rx_anc_data 19 1 j 000 OFFI Y 19 y 2x 0857 1 J 17 rx_anc_data 9 10 000 SFF X e oo 2 055 e T rx_anc_valid 3 4 i i PLP Li LL LS VLE LG i rx_anc_valid ESTAJ VANS ANS LS ALU 4 rx anc valid Lr VAT rx anc valid i i i i FA Ix anc error i rX_anc_error rx anc error rx anc error Notes to Figure 3 39 1 000 C 000 Y 2 3FF C 3FF Y 3FF C 3FF Y 3 Sequence starts with Data Indentifier DID followed by Secondary Data Indentifier SDID or Data Block Number DBN The Y channel of Link B goes wrong Data Count DC word User data word UDW up to 255 Checksum word Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 53 Signals Figure 3 40 Behavior of rx_anc_data valid error Signals HD 12 4 5 AE WE NE rx_clk 148 5 Hz rx_anc_data 19 10 y 000 jus 0 y 06 Lic rx_anc_data
92. d GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters italic type Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 Variable names are enclosed in angle brackets lt gt For example file name and lt project name gt poft file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequenc
93. d LEs Combinational ALUTs Logic Registers SD SDI 834 640 HD SDI 919 683 36 501 1 161 865 Arria GX Dual link HD SDI 1 906 1 423 Dual standard receiver 1 188 831 Dual standard transmitter 247 185 Triple standard 1 794 1 215 SD SDI 839 680 HD SDI 978 833 3G HD SDI 1 259 1 015 Arria 11 GX Dual Link HD SDI 2 029 1 711 Dual standard receiver 1 257 926 Dual standard transmitter 267 180 Triple standard 1 891 1 305 SD SDI 1 189 920 HD SDI 1 185 910 36 501 1 444 1 142 Arria V Dual link HD SDI 2 446 1 880 Dual standard receiver 1 605 1 175 Dual standard transmitter 349 269 Triple standard 2 273 1 677 Cyclone SD SDI 875 Cyclone SD SDI 867 Cyclone III SD SDI 874 Cyclone III LS SD SDI 929 Cyclone IV GX EP4CGX15 SD SDI 916 EP4CGX30 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 1 About This MegaCore Function Resource Utilization Table 1 7 Resource Utilization Part 2 of 2 Device Video Standard LEs Combinational ALUTs Logic Registers SD SDI 1 129 671 HD SDI 1 164 670 1 409 790 EP4CGX75 Dual link HD SDI 2 515 1 467 Sip E and Dual standard receiver 1 479 755 Dual standard transmitter 364 229 Triple standard 2 235 1 121 S
94. d Lines Total Line 7 5 Pro gressive interlace Frame Rate 1080p60 60 7 2200 1080p59 94 1080 59 94 1 1 6 1080p50 2640 50 5 1080p30 30 4 2200 1080p29 97 29 97 3 1080p25 1080 2640 25 1 1 2 1080p24 24 1 2750 1080p23 97 23 97 0 Table 3 18 lists the status signals Table 3 18 Status Signals Part 1 of 2 Signal Width Direction Description Received ancillary data SD SDI bits 19 10 unused bits 9 0 Cb Y Cr Y multiplex HD SDI bits 19 10 Y bits 9 0 C rx anc data 20N 1 0 Output Dual link bits 39 30 Y link B bits 29 20 C link B bits 19 10 Y link A bits 9 0 C link A 3G SDI Level A bits 19 10 Y bits 9 0 C 3G SDI Level B bits 19 10 Cb Y Cr Y multiplex link A bits 9 0 Cb Y Cr Y multiplex link B Ancillary data or checksum error SD SDI bits 3 1 unused bit 0 xx anc error HD SDI bits 3 2 unused bit 1 Y bit 0 C 3 0 Output Dual link bit 3 Y link B bit 2 C link B bit 1 Y link A dn bit 0 C link A 3G SDI Level A bits 3 2 unused bit 1 Y bit 0 C 3G SDI Level B bit 3 Y link A bit 2 C link A bit 1 Y link B bit 0 C link B Ancillary data valid Asserted to accompany data ID DID secondary data ID data block number SDID DBN data count DC and user data words UDW on rx anc data SD SDI bits 3 1 unused bit 0 xx anc valid HD SDI bits 3 2 unused bit 1 Y bit 0 C rx anc valid 3 0 Output Serial Digital Interface SDI MegaCore Function User Guide February 201
95. d Yes Yes Yes Note to Table 3 10 1 Ifthe additional serial reference clock feature is enabled the transmitters require dynamic reconfiguration to enable toggling switching between the two input clocks Table 3 11 lists the rates for the different SDI standards Table 3 11 SDI Standard Rates SDI Standard Data Rate Oversampling niu iene tek rx_clk Rate MHz SD SDI 270 Mbps 11 times 2 970 148 5 148 5 HD SDI 1 485 Gbps None 1 485 148 5 74 25 1 30 501 2 970 Gbps None 2 970 148 5 148 5 Note to Table 3 11 1 Also supports the 1 1 001 rates for all supported devices except Cyclone IV GX devices For Cyclone IV GX devices the transceiver reference clock must be 148 35 MHz to support the 1 1 001 rates To reprogram the transceivers you must include the ALT2GXB_RECONFIG or ALTGX_RECONFIG megafunction in your design However to reprogram Arria II GX or Stratix IV device family you require an ALTGX_RECONFIG megafunction You can get this parameterization from the example a2gx_tr source sdi_dprio_siv directory in the example design Similarly to reprogram Cyclone IV GX device family with channel reconfiguration mode you require a slightly different configuration of the ALTGX_RECONFIG megafunction You can get this parameterization from the simulation modelsim trsdi_c4gx channel_reconfig testbench pattern_gen directory in the example simulation For more information about th
96. d line and finishing with the final word of the line number LN1 The initial value of the CRC is set to zero then the polynomial generator equation CRC X X18 X5 1 is applied The HD SDI CRC module implements the CRC calculation by iteratively applying the polynomial generator equation to each bit of the output data processing the LSB first For correct CRC generation and insertion the tx_trs signal must be asserted for the first word of both EAV and SAV TRS refer to Figure 3 31 on page 3 47 and Figure 3 32 on page 3 48 Scrambling and NRZI Coding SMPTE292M section 5 and SMPTE292M section 7 define a common channel coding that is used for both SDI and HD SDI This channel coding consists of a scrambling function G X X X 1 followed by NRZI encoding G X X 1 The scrambling module implements this channel coding You can configure the module to process either 10 bit or 20 bit parallel data The scrambling module implements the channel coding by iteratively applying the scrambling and NRZI encoding algorithm to each bit of the output data processing the LSB first Figure C 1 of SMPTE259M shows how the algorithm is implemented Transceiver Clock Figure 3 3 shows the clocking scheme for the transmitter The tx_serial_refclk1 is an optional port that is enabled when you turn on the Enable TX PLL select for 1 1 000 and 1 1 001 data rate reconfiguration in the SDI parameter editor Figure 3 3 Transmitter Cloc
97. dard gt lt DPRIO mode gt modelsim sdi_sim do Edit it to point to your installation of the ModelSim Altera simulator and edit the path set QUARTUS ROOTDIR C altera lt version gt quartus La Where lt version gt is the version of the Quartus II software you are using 2 Start the ModelSim Altera simulator 3 Run sdi_sim do in the simulation modelsim lt video standard gt lt DPRIO mode gt modelsim directory This file compiles the design and starts the ModelSim Altera simulator A selection of signals appears on the waveform viewer To test the transmitter operation the testbench generates a reference clock and parallel video data The design encodes and serializes this parallel video data The serial output is sampled non return to zero inverted NRZI decoded descrambled and then reconstructed into parallel form The testbench detects the presence of TRS tokens end of active video EAV and start of active video SAV in the output to check the correct operation To test the receiver operation the testbench connects the serial transmitter data to the receiver input The testbench checks that the receiver achieves word alignment and verifies that the extracted LN is correct Simulating in Third Party Simulation Tools Using NativeLink You can perform a simulation in a third party simulation tool from within the Quartus II software using NativeLink For more information about NativeLink refer to the Simulati
98. data for SD SDI 10 bit parallel data For txdata bus definition refer to Table 3 16 on page 3 41 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 4 Chapter 3 Functional Description Block Description Table 3 1 lists the bit allocation for txdata Table 3 1 Bit Allocation for txdata for Supported Video Standards txdata SD SDI HD SDI 3G SDI Level A 3G SDI Level B Cb Y Cr Y multiplex link A Cb Y Cr Y Cb Y Cr Y multiplex multiplex link B 19 10 Unused Y Y 9 0 For HD SDI operation the current video line number is inserted at the appropriate point in each line A CRC is also calculated and inserted for the luma and chroma channels The parallel video data is scrambled and NRZI encoded according to the SDI specification The transceiver converts the encoded parallel data into the high speed serial output parallel to serial conversion HD SDI LN Insertion SMPTE292M section 5 4 defines the format of two words that are included in each HD SDI video line to indicate the current line number The HD SDI LN insertion module takes the lower 11 bit tx_1n and formats and inserts it as two words in the output data The HD SDI LN insertion module accepts the current line number as an input For more information about the line insertion for other video standards refer to the description for tx_1n signal in Table 3 16 on page 3 41 The
99. database before you specify timing constraints for your design On the Processing menu click Start Compilation A message indicates when compilation is complete On the Tools menu click TimeQuest Timing Analyzer Create timing netlist double click Create Timing Netlist in the Tasks pane The timing netlist appears in the Report pane Specify timing constraints and exceptions To enter your timing requirements you can use constraint entry dialog boxes or edit the previously created sdc file To save your constraints in an sdc file on the Constraints menu click Write SDC File February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide A 2 Appendix A Constraints Specifying TimeQuest Timing Analyzer Constraints Figure A 1 shows the flow of the constraint design Figure A 1 Constraints Design Flow Step 1 Specify Clock Characteristics Set Multicyle Paths 1 Step 2 Set Timing Exceptions Specify Asynchronous Clocks set_clock_group SD HD Dual link 3G DR TR set false path SD HD Dual link 3G DR TR Soft Transceiver Step 3 Minimize Timing Skew 2 Notes to Figure 1 1 Applicable for SD SDI only 2 Applicable for Soft SERDES only Define Setup and Hold 2 Serial Digital Interface 501 MegaCore Function User Guide February 2013 Altera Corporatio
100. delSim Altera simulator and the Quartus II software and edit the path set PATH MODELSIM DIR win32aloem set QUARTUS ROOTDIR c altera 81 quartus For example edit QUARTUS_ROOTDIR tools acds 11 0 157 linux32 quartus L Where video standard is hdsdi or hdsdi dual link 2 Start the ModelSim Altera simulator 3 Run sdi sim bat in the simulation modelsim video standard Nmodelsim directory This file compiles the design and starts the ModelSim Altera simulator A selection of signals appears on the waveform viewer The simulation runs automatically providing a pass fail indication on completion February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 2 10 Chapter 2 Getting Started Simulating the Design For Cyclone IV GX devices Altera provides two new fixed testbenches in the simulation modelsim video standard gt lt DPRIO mode gt modelsim directory where lt video standard gt lt DPRIO mode gt is trsdi_c4gx channel_reconfig or trsdi_c4gx pll_reconfig The testbenches instantiate the design and test the triple standard mode of operation using Cyclone IV GX devices The testbenches also demonstrate the transceiver dynamic reconfiguration with channel and phase locked loop PLL reconfiguration modes To use one of these testbenches with the ModelSim Altera simulator follow these steps 1 Ina text editor open the simulation do file simulation modelsim lt video stan
101. di clocks pll sclk cyc rx pll gen u rx pll altpll altpll component cl k0j to get clocks your megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv 4 430 set min delay from get clocks your megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks pll sclk cyc rx pll gen u rx pll altpll altpll component c1 k0j to get clocks your megacore sdi megacore top sdi megacore top inst sdi clocks u s di clocks clkdiv 2p5 cyc rx pll gen u clkdiv clkdiv 0 000 Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide N DTE RYN B Clocking Figure B 1 shows the transceiver clocks for the SDI MegaCore function for version 7 0 and previous Figure B 1 Version 7 0 and Earlier Clocks SDI Receiver E Transceiver Frequency gt vexo Detector SDI Out SDI Transmitter Transceiver m HD SD VCXO 2 A PLL 11 5 Figure B 2 shows how you must clock the transceivers for current SDI cores You can now derive all clocks from a single 148 5 MHz voltage controlled crystal oscillator VCXO and the transceivers require no external multiplexing Figure B 2 Version 7 1 and Later Clocks SDI Out SDI Receiver Phase 148 5 MHz SDI Transmitter Transceiver e Frequency VCXO Transceiver
102. e ALI2GXB RECONFIG megafunction refer to the Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide For more information about the ALTGX_RECONFIG megafunction refer to the Stratix IV ALTGX_RECONFIG Megafunction User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 29 Block Description Ls Transceiver Reconfiguration for Transmitter Clock Multiplexer The transmitter reconfiguration requires its own Memory Initialization Files mif that is stored in the device The mif contains information about the default selection of the TX PLL that is based on the logical tx pll seland logical tx pll sel en pins These pins are available in the transceiver port when you enable the transmitter clock multiplexer feature By toggling the values in these ports and reconfiguring the transmitter megafunction you can internally switch the TX PLL to select different reference clock inputs For Arria II and Stratix IV devices these are 19 words by 16 bits files The following are the sequence of events that occur during the SDI transmitter clock toggling 1 SDI MegaCore function detects a change request to the serial reference clock 2 The ALTGX_RECONFIG block reads the appropriate ROM sets the logical tx pll seland logical_tx_pll_sel_en ports to the required value and reprograms the ALTGX in the transmitter block 3 When step 2 is completed the SDI transmitter begins locking on the new serial reference clock User
103. e errors misse If you want the receiver core not to tolerate any errors set this option to 0 HD SDI transmitter only When turned on runs the transceiver at twice Two times oversample mode On or off the rate and has improved jitter performance Requires 148 5 MHz tx serial refclk reference clock MegaCore Verification The MegaCore verification involves testing to the following standards m For the SD SDI to SMPTE259M 1997 10 Bit 4 2 2 Component Serial Digital Interface m Forthe HD SDI to SMPTE292M 1998 Bit Serial Digital Interface for High Definition Television Systems February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 58 Chapter 3 Functional Description MegaCore Verification Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide N D 2Ya 4 SDI Audio IP Cores The SDI Audio IP cores ease the development of video and image processing designs For some instances you combine the audio and video into one digital signal and at other times you process the audio and video signals separately You can use the following cores to embed extract or convert audio SDI Audio Embed MegaCore Function SDI Audio Extract MegaCore Function Clocked Audio Input MegaCore Function Clocked Audio Output MegaCore Function You can instantiate the SDI Audio with the SDI MegaCore function and configure each SDI Audio core at run time using an Aval
104. e of the items is not important i The hand points to information that requires special attention February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Info 4 Additional Information Typographic Conventions Visual Cue Meaning The question mark directs you to a software help system with related information ed The feet direct you to another document or website with related information Eb ul The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents DE The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation
105. e use Test sine generator When set to 1b this bit ignores the audio inputs and uses the output 4 RW enable of the sine generator as the data for each audio group 75 Unused Reserved for future use Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function 4 9 Table 4 9 SDI Audio Embed MegaCore Function Register Map Bit Name Video Status Register Access Description 7 0 Active channels RO Reports the detected video input standard Bits 7 5 Picture structure code Defined values for picture structure code are 001b 486 or 576 line SD SDI 100b 720 line HD SDI 101b 1080 line HD SDI 010b 1080 line 3G SDI Bit 4 0b Interlace or segmented frame 1b Progressive Bits 3 0 Frame rate code Defined values for frame rate code in Hz are 0010b 23 97 0011 24 0101 25 0110b 29 97 0111b 30 1001b 50 1010b 59 94 1011b 60 Audio Status Register 7 0 Unused Reserved for future use Channel Status Control Registers 7 0 CS mode select RW When set to 00b the core keeps the existing channel status data When set to 01b the core replaces the channel status data with default values When set to 10b the core replaces the data with the contents of the appropriate channel status RAM The following bits correspond to the
106. eceive video standard LED D16 blinks indicating the heartbeat of the receiver s recovered clock The frequency is blinking is slower than the previous demonstration LED D17 illuminates when the receiver is frame locked LED D18 illuminates when the receiver is TRS locked LED D19 illuminates when the receiver is alignment locked LED D23 and D22 illuminate when the data packet of audio groups 1 and 2 are detected in the incoming SDI stream Figure 4 12 shows the condition of the LEDs Figure 4 12 Condition of LEDs for Transmitting HDI SDI Video Standard D7 DI D10 D11 D12 D16 D17 D18 D19 D20 D21 D22 D23 MERR NN 3 The external waveform monitor WFM700 displays the following observation a Colorbar video pattern February 2013 Altera Corporation Video format detect is 1080i 60 00 Embedded audio standard detected is SMPTE299M Audio channel pairs 1 2 3 4 5 6 and 7 8 are present Serial Digital Interface SDI MegaCore Function User Guide 4 32 Chapter 4 SDI Audio IP Cores Design Example Transmit 3G SDI Level A with Embedding of Audio Group 1 2 and 3 To transmit the 3G SDI Level A video standard follow these steps 1 2 Set DIP switch 2 1 11 The demonstration runs and the LEDs indicate the following conditions a LED D6 and D7 indicate the internal video pattern generator signal standard LED D8 and D9 indicate the receive vid
107. ed Audio Output MegaCore Function Parameters Parameter Value Description Defines the internal FIFO depth For example a value of 3 means 23 8 Turn on to include the Avalon MM control interface Include Avalon MM control On or Off When you turn on this parameter the register interface signals interface in Table 4 7 appear at the top level Otherwise the direct control interface signals in Table 4 6 appear at the top level FIFO size 3 10 Signals Table 4 25 lists the Avalon ST audio input and output signals when you instantiate the SDI Clocked Audio Output MegaCore function in SOPC Builder Table 4 25 Audio Input and Output Signals Signal Width Direction Description aes clk 0 0 Input Audio input clock aes de 0 0 Output Audio data enable aes ws 0 0 Output Audio word select aes data 0 0 Output Audio data output in internal AES format Table 4 26 lists the Avalon ST audio signals when you instantiate the SDI Clocked Audio Output MegaCore function in SOPC Builder Table 4 26 Avalon ST Audio Signals Part 1 of 2 Signal Bits Direction Description Clocked audio clock All the audio input signals are synchronous to this clock Avalon ST ready signal Assert this signal when the device is able to receive data aud clk 0 0 Input aud ready 0 0 Output February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function Use
108. een SDI MegaCore Function and ALT2GXB RECONFIG Signals 5 RX STD 1 0 12 3 4 SDI MegaCore Ports Zt SDI START RECONFIG A A UU VAL SDI RECONFIG DONE ALT2GXB RECONFIG Ports RECONFIG_DATA X X X X ROM ADDRESS 0 X 1 E Y 26 Y 27 X CHANNEL RECONFIG DONE RECONFIG TO GXB X X T 0000000000002 1300000000000 February 2013 Altera Corporation The following sequence of events occur for handshaking to the reconfiguration logic 1 The SDI MegaCore function sets rx std 1 0 to the desired video standard This action is performed as part of the video standards detection algorithm 2 The SDI MegaCore function asserts SDI START RECONFIG to make a reconfiguration request 3 The user logic sets SDI RECONFIG DONE to 0 which indicates to the MegaCore function that the reconfiguration is in progress 4 When the reconfiguration has been performed the user logic sets the SDI RECONFIG DONE to logic 1 which indicates to the SDI MegaCore function to start locking to the incoming data 5 The SDI MegaCore function sets the SDI START RECONFIG line to 0 to indicate that the request is completed and acknowledged 57 The CRC error signal is asserted during the reconfiguration of the transceiver in the receiver The assertion of the CRC error signal is normal during receiver reconfiguration as the receiver protocol is interrupted
109. efer to OpenCore Plus Evaluation on page 1 5 and AN320 OpenCore Plus Evaluation of Megafunctions Table 3 12 lists the receiver clock signals Table 3 12 Receiver Clock Signals Part 1 of 2 Signal Direction Description gxb2 cal clk Input Calibration clock for Arria GX and Stratix II GX transceivers only Calibration clock for Arria Il GX Arria V Cyclone IV GX SED cal cik Input HardCopy IV and Stratix IV transceivers only rx sd oversample clk in Input 67 5 MHz oversample clock input SD SDI only Transceiver training clock for HD SDI dual standard and triple 1 rx serial refclk Input Secondary transceiver training clock Clock frequency of jui septi input 74 175 MHz for HD SDI or clock frequency of 148 35 MHz for i ie CE 3G SDI dual standard and triple standard Available only when you use a Cyclone IV GX device February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 3 40 Table 3 12 Receiver Clock Signals Part 2 of 2 Chapter 3 Functional Description Signals Signal rx coreclk refclk rate 2 Direction Input Input Description Receiver controller clock input For Cyclone IV GX devices only The frequency of this clock must be the same as xx serial refclk Because of hardware constraint the transceiver PLL and core logic cannot share the same clock input pin if they use transceiver PLL6 and PLL7 This signal is related
110. en 01 enables the embedding of audio group 1 and 2 When 11 enables the embedding of audio group 1 2 and 3 When 10 enables the embedding of audio group 1 2 3 and 4 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 30 Chapter 4 SDI Audio IP Cores Design Example Running the Design Example To run the design example you must set up the development board To set up the development board follow these steps 1 Set up the board connections a Connect the SDI HSMC to HSMA port on the Stratix IV GX development board Connect the development board to the power supply Connect the SDI_OUT_2 port SDI TX PO to the SDI_IN_1 port SDI duplex using external BNC cable Connect the AES OUT 1 port to the AES IN 1 port using external BNC cable Connect the SDI OUT 1 port SDI duplex to the external waveform monitor so that you can analyze the embedded audio in the SDI video stream 2 Launch the Quartus II software b On the File menu click Open Project navigate to ip altera audio_embed example s4gx_sdi_audio s4gxsdi_audio qpf and click Open On the Processing menu click Start Compilation 3 Download the Quartus II generated SRAM Object File sof After you set up the board run the different configurations described in the following sections Transmit SD SDI with Embedding of Audio Group 1 To transmit the SD SDI video standard follow
111. ent locked Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores Design Example 4 29 Table 4 30 Function of Each LED on the Stratix IV GX FPGA Development Board D18 LED Description Indicates that the receiver of the SDI duplex MegaCore function is TRS locked D17 Indicates that the receiver of the SDI duplex MegaCore function is frame locked D16 Indicates the recovered clock heartbeat of the receiver D13 Indicates the ancillary checksum failure D12 Indicates the ancillary parity failure D11 Indicates the channel status CRC failure D10 Indicates the audio packet failure D9 D8 Indicate the SDI receive video standards 00 SD SDI 01 HD SDI 11 3G SDI Level A 10 3G SDI Level B D7 D6 Indicate the SDI transmit video standards 00 SD SDI 01 HD SDI 11 3G SDI Level A 10 3G SDI Level B Table 4 31 lists the function of each user defined dual in line package DIP switch settings Table 4 31 Function of Each DIP Switch DIP Switch Description Resets the system Resets the Audio Extract MegaCore function status registers Unused 2 1 Configure the internally generated video standards for both SDI transmitters 00 SD SDI 01 HD SDI 11 3G SDI Level A 10 3G SDI Level B When 00 enables the embedding of audio group 1 Wh
112. ents a receiver transmitter or full duplex SDI at standard definition SD high definition HD or 3 gigabits per second 3G The SDI MegaCore function also supports dual standard HD SDI and SD SDI and triple standard SD SDI HD SDI and 3G SDI These modes provide automatic receiver rate detection You can instantiate the SDI Audio IP cores with the SDI MegaCore function gt For more information about the SDI Audio cores refer to SDI Audio IP Cores on page 4 1 Features Table 1 1 lists the features of the SDI MegaCore function Table 1 1 SDI MegaCore Function Features Feature Description Multiple SDI standards and video formats refer to Table 1 5 and Table 1 6 RP168 video switch line requirement OpenCore Plus evaluation Cyclical redundancy check CRC encoding HD only Line number LN insertion HD only Word scrambling Transmitter clock multiplexer optional CRC decoding HD only LN extraction HD only Framing and extraction of video timing signals Word alignment and descrambling Easy to use parameter editor Use in Altera supported VHDL and Verilog HDL simulators Support Transmitter Receiver MegaWizard Plug In Manager IP functional simulation models February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Release Information Chapter 1 About This MegaCore Function Release Information Table 1 2 lists infor
113. eo standard LED D16 blinks indicating the heartbeat of the receiver s recovered clock LED D17 illuminates when the receiver is frame locked LED D18 illuminates when the receiver is TRS locked LED D19 illuminates when the receiver is alignment locked LED D23 D22 and D21 illuminate when the data packet of audio groups 1 2 and 3 are detected in the incoming SDI stream Figure 4 13 shows the condition of the LEDs Figure 4 13 Condition of LEDs for Transmitting 3G SDI Level A Video Standard D7 DI D10 D11 D12 I D16 D17 D18 D19 D20 D21 D22 D23 UN NN Transmit 3G SDI Level B with Embedding of Audio Group 1 2 3 and 4 To transmit the 3G SDI Level B video standard follow these steps 1 Set DIP switch 2 1 10 2 The demonstration runs and the LEDs indicate the following conditions a LED D6 and D7 indicate the internal video pattern generator signal standard LED D8 and D9 indicate the receive video standard LED D16 blinks indicating the heartbeat of the receiver s recovered clock LED D17 illuminates when the receiver is frame locked LED D18 illuminates when the receiver is TRS locked LED D19 illuminates when the receiver is alignment locked LED D23 D22 D21 and D20 illuminate when the data packet of audio groups 1 2 3 and 4 are detected in the incoming SDI stream Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporat
114. er to Table 3 16 on page 3 41 for rxdata bus definition February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 8 Chapter 3 Functional Description Block Description Table 3 2 lists the bit allocation for rxdata Table 3 2 Bit Allocation for rxdata for Supported Video Standards rxdata SD SDI HD SDI 3G SDI Level A 36 501 Level B Cb Y Cr Y 19 10 Unused Y Y multiplex link A Cb Y Cr Y Cb Y Cr Y 9 0 C multiplex multiplex link B The receiver interface extracts and tracks the F V and H timing signals in the received data Active picture and ancillary data words are also identified for your use For HD SDI the received CRC is checked for the luma and chroma channels The LN is also extracted and provided as an output from the design NRZI Decoding and Descrambling The descrambler module provides the channel decoding function that is common to both SDI and HD SDI It implements the NRZI decoding followed by the required descrambling The algorithm indicated by SMPTE259M figure C 1 is iteratively applied to the receiver data with the LSB processed first Word Alignment The aligner word aligns the descrambled receiver data such that the bit order of the output data is the same as that of the original video data The EAV and SAV sequences determine the correct word alignment Table 3 3 lists the pattern for each standard T
115. erfaces with the Audio Embed MegaCore function both must use the same clock Audio Embed PO P1 The Audio Embed embeds the AES audio generated by the Audio Pattern Generator into the video stream as a transmitting data for the SDI transmitter PO The Audio Embed P1 embeds the AES audio from the external AES input into the video stream for the SDI duplex Video Pattern Generator PO P1 You can configure the internal video pattern generator to output an SD SDI HD SDI 3G SDI Level A or 3G SDI Level B colorbar pattern Audio Pattern Generator You can configure the internal audio pattern generator to create an AES audio test sample that comprises an increasing count You configure the generator using the 48 kHz clock output from the Audio Embed MegaCore function Ancillary Data Insertion PO P1 The Ancillary Data Insertion module inserts the ancillary data defined by SMPTE352 into the SDI video stream Transceiver Dynamic Reconfiguration Control Logic The transceiver dynamic reconfiguration control logic block handles the reconfiguration of the receiver in the SDI duplex February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 28 Chapter 4 SDI Audio IP Cores Design Example Hardware and Software Requirements The demonstration requires the following hardware and software m Stratix IV GX Audio Video Development Kit Stratix IV GX FPGA development board and SDI HSMC SDI MegaCore
116. esign Example February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 26 Chapter 4 SDI Audio IP Cores Design Example Components Figure 4 9 shows a high level block diagram of the design example Figure 4 9 High Level Block Diagram of Stratix IV GX FPGA Stratix IV GX FPGA Video Pattern gt Ancillary Data Generator PO Insertion PO Audio Pattern SDI OUT_2 Generator gt AudioEmbedPO SDITX PO Transceiver Dynamic Reconfiguration lt Control Logic SDI Duplex aud_de __ AES Output Module kg 42 S___ Audio Extract o i AES OUT 1 aud data MCO RX e 4 Tinternal AES eee E SDIIN 1 AES aud de P qu E m Waveform AES Input Module S 5 gt Audio Embed P1 e cur Monitor B internal AES gt 7 WFM 700 Video Pattern Ancillary Data Generator P1 Insertion 1 Encrypted MegaCore Function The following sections describe the various elements in Figure 4 9 SDI Transmitter PO The triple standard SDI transmitter that outputs a 3G SDI 2 970 Gbps HD SDI 1 485 Mbps or SD SDI 270 Mbps data stream This transmitter gets the parallel data source from the SDI Audio Embed MegaCore function The SDI Audio Embed component embeds the internally generated audio in AES format into the intern
117. evice you may wish to use them Starting channel Dual or triple standard only Each dual or triple standard SDI must 0 4 8 156 have a unique starting channel number This parameter is not applicable for Stratix V Arria V and Cyclone V devices Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description MegaCore Verification Table 3 21 Transceiver Options 3 57 Parameter Use PLL reconfiguration for transceiver dynamic reconfiguration Enable TX PLL select for 1 1 000 and 1 1 001 data rate reconfiguration Value On or off On or off Description Dual or triple standard and Cyclone IV GX devices only You must turn on this option if you select an EPACGX110 or EPACGX150 device Enables an additional input port for transmitter serial reference clock Available for Arria Il Stratix IV and HardCopy IV devices only Table 3 22 shows the receiver transmitter options Table 3 22 Receiver Transmitter Options Parameter Value Description CRC error output On or off Turns on or off CRC monitoring HD SDI and 3G SDI only SDI synchronization output On or off Provides synchronization outputs Receiver protocol only Allows you to set the number of consecutive missing EAVs to be tolerated in the incoming video Specify a higher MU Me 0 1 2 15 value if you want the receiver core to tolerate mor
118. for PLL reconfiguration in Table 3 18 Updated Figure 3 29 and Figure 3 30 to include tx_1n signal behavior November 2009 May 2009 9 0 Added Cyclone 111 LS and Cyclone IV support Added a section on Specify Constraints Updated information on rst rxand rst tx signals in Table 3 15 Added block diagram for input and output interface signals flow Added top level block diagram for transmitter and receiver Added a section on Reset Requirement During Reconfiguration Updated information on txdata tx_1n crc error y crc error rx AP rxdata rx data valid out rx F rx rx 1n rx v signals in Table 3 15 Updated information on xx anc data rx anc error rx anc validand rx status signals in Table 3 17 March 2009 9 0 Added Arria 11 GX support Added a section on RP168 Updated information on video formats Removed tx data valid a bn signal November 2008 8 1 Added a section on Locking Algorithm Added new signals and updated existing signal descriptions Updated Appendix A Constraints May 2008 8 0 Added Stratix IV support Improved receiver lock algorithm Updated 425MB support October 2007 7 2 Updated device support Updated standards support 3G SDI now supports SMPTE425M B 2006 3Gb s Signal Data Serial Interface Source Image Format Mapping Changed rx std signal description Added tx data valid a bn signal May 2007 Updated device
119. fted by 90 from each other Two out of these four clocks are created from an on chip PLL The two remaining clocks are created by inversion of the PLL clock outputs Samples are then all converted to the same clock domain and deserialized into a 10 bit parallel word The serial clock that samples the bit stream must be 337 5 MHz which is 5 4 of the incoming bit 270 bit rate x 5 4 x 4 sample per clock 1 350 Mbps The parallel clock that extracts data from the deserializer is running at 135 MHz To achieve timing you must correctly constrain your design refer to Constraints on page A 1 Receiver Clocks The deserializer requires three clocks refer to Table 3 15 on page 3 41 which you can generate from an external source Transceiver Stratix GX Devices The Stratix GX transceiver deserializes the high speed serial input For HD SDI the clock data recovery CDR function performs the deserialization and locks the receiver PLL to the receiver data For SD SDI the transceiver provides a fixed frequency oversample of the serial data with the receiver PLL constantly locked to a reference clock which allows the transceiver to support the 270 Mbps data rate The transceiver can process either SD SDI or HD SDI data The data rate can be automatically detected so that the interface can handle both SD SDI and HD SDI without the need for device reconfiguration In Stratix GX devices the transmitters in a quad share a common refere
120. function SDI Audio Embed MegaCore function SDI Audio Extract MegaCore function The Quartus II software version 11 1 For more information about how the Stratix IV GX FPGA development board connects to the SDI HSMC refer to AN 600 Serial Digital Interface Reference Design for Stratix IV Devices You can obtain the design example from the directory structure in Figure 4 10 Figure 4 10 Directory Structure 1 lt path gt Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores altera Contains the Altera MegaCore IP Library audio_embed Contains the Audio Embed MegaCore function files example Contains design examples s4gx_sdi_audio Contains a design example for Stratix IV GX Hardware Setup Table 4 30 lists the function of each LED on the Stratix IV GX FPGA development board Table 4 30 Function of Each LED on the Stratix IV GX FPGA Development Board LED Description Indicates the presence of audio group 1 data packet in the incoming D23 embedded audio Indicates the presence of audio group 2 data packet in the incoming D22 embedded audio Indicates the presence of audio group 3 data packet in the incoming D21 d embedded audio Indicates the presence of audio group 4 data packet in the incoming D20 embedded audio D19 Indicates that the receiver of the SDI duplex MegaCore function is alignm
121. ge 0 u txrx port sdi format format gen u format to get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge 0 u txrx port sdi format format gen u format 1 0 Specify Clocks that are Exclusive or Asynchronous The SDI MegaCore function may show timing violations in slower speed grade devices These paths are not required to have fast timing so you can use the following constraints to remove these timing paths You can use the command set_clock groups or set_false path February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide A 6 Appendix A Constraints Specifying TimeQuest Timing Analyzer Constraints La The following SDC commands are only applicable for duplex core and Stratix IV devices you must use the constraint entry dialog boxes to constrain the separate receiver or transmitter core and other device families m SD SDI set clock groups exclusive group get clocks tx pclk group get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated transmit pcsO clkout set false path from get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 0 u txrx port switchline to get clocks sdi megacore top inst sdi txrx port gen 0 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcs0 clkout m HD SDI 3
122. gnal For 3G SDI Level A standard this field extends the extract pair field to 4 Extract pair MSB RW allow for future implementations with 32 embedded audio channels For 3G SDI Level B standard this field selects the active video half of the 3G multiplex 5 Mute RW Drive this register high to mute the audio output 7 6 Unused Reserved for future use Audio Presence Register RO Reports which audio data groups are detected in the SDI stream The following bits correspond to the number of audio groups detected 3 0 Data packet present m Bit 0 Audio group 1 m Bit 1 Audio group 2 m Bit 2 Audio group 3 m Bit 3 Audio group 4 7 4 Control packet present RO Reports which audio control packets are detected in the SDI stream Audio Status Register 3 0 Acivechannal RW Reflects the lower four bits of the ACT active field of the audio control packet February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 16 Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function Table 4 17 SDI Audio Extract MegaCore Function Register Map Part 2 of 2 Bit Name Access Description Reflects the asx bit of the RATE sampling rate field of the audio 4 Asynchronous RW control packet Reports the X1 and bits of the sample rate code from the RATE 2 sampe iag iu field of the audio control packet 7 Status valid RW Set
123. gure 3 11 shows the transmitter clocks for different video standards Figure 3 11 Transmitter Clocks Arria GX Arria Il GX Arria V Cyclone IV GX Cyclone V Stratix 1 GX Stratix IV and Stratix V Devices SD SDI SDI MegaCore I p Serial Data Function 67 5 MHz from PLL or Pin HD SDI SDI MegaCore gt Serial Data Function 74 XX MHz 1 from reference clock Dual Standard SDI MegaCore I gt Serial Data Function 67 5 MHz 74 XX MHz 1 4 2 3G SDI or Triple Standard SDI MegaCore I p Serial Data Function 148 XX MHz 3 from reference clock 3G SDI or Triple Standard with additional reference clock port SDI MegaCore ___y Serial Data Function 148 35 MHz 4 148 5 MHz Notes to Figure 3 11 1 This frequency can be either 74 175 or 74 25 MHz to support 1 4835 or 1 485 Gbps HD SDI respectively 2 The multiplexer must not be in the device 3 This frequency can be either 148 35 or 148 5 MHz to support 2 967 or 2 970 Gbps HD SDI respectively 4 You can source both 148 5 MHz and 148 35 MHz together if the additional clock port is enabled February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 22 Receiver Clocks Chapter 3 Functional Description Block Description The transceiver requires a receiver reference clock rx_serial_refclk This clock trains the receiver PLL in the transceive
124. hapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Table 4 5 lists the Avalon ST audio signals when you instantiate the SDI Audio Embed MegaCore function in SOPC Builder Table 4 5 Avalon ST Audio Signals for SDI Audio Embed MegaCore Function Signal Width Direction Description Clocked audio clock All the audio input signals are ele 0 0 Input synchronous to this clock Avalon ST ready signal Assert this signal when the 0 0 Baur device is able to receive data Avalon ST valid signal The MegaCore function SUUM 0 0 Input asserts this signal when it receives data Avalon ST start of packet signal The MegaCore aud n sop 0 0 Input function asserts this signal when it is starting a new frame Avalon ST end of packet signal The MegaCore sadn eop 0 0 Input function asserts this signal when it is ending a frame Avalon ST select signal Use this signal to select a aud n channel 7 0 Input specific channel aud n data 23 0 Input Avalon ST data bus This bus transfers data Note to Table 4 5 1 n represents the channel number Table 4 6 lists the direct control interface signals These signals are exposed as ports if you turn off the Include Avalon MM Control Interface parameter Table 4 6 Direct Control Interface Signals Part 1 of 2 Signal Width Direction Description
125. hat contains only the structure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist 3 Click Next or the Summary tab to display the Summary page Generating Files You can use the check boxes on the Summary page to enable or disable the generation of specified files A gray checkmark indicates a file that is automatically generated a red checkmark indicates an optional file You can click Back to display the previous page or click Parameters Settings EDA or Summary to change any of the MegaWizard options To generate the files follow these steps 1 Turn on the files you wish to generate gt LS At this stage you can still click Back to display any of the other pages in the MegaWizard Plug In Manager to change any of the parameters 2 To generate the specified files and close the MegaWizard Plug In Manager click Finish 57 The generation phase may take several minutes to complete 57 The Quartus File qip is a file generated by the parameter editor and contains information about the generated IP core You are prompted to add this qip file to the current Quartus II project at the time of file generation In most cases the qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler Genera
126. he horizontal blanking interval is active HD SDI SD SDI bit 1 unused bit 0 xx Dual link bit 1 unused bit 0 xx h 3G SDI Level A bit 1 unused bit 0 xx h 3G SDI Level B bit 1 link A xx h bit 0 link B xx h Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description Signals Table 3 16 Interface Signals Part 5 of 5 3 45 Signal Width Direction Description Receiver line number output HD SDI bits 21 11 unused bits 10 0 LN rx ln 21 0 Output Dual link bits 21 11 unused bits 10 0 LN 30 501 Level A bits 21 11 unused bits 10 0 LN 3G SDI Level B bits 21 11 LN link A bits 10 0 LN link B xtd flee hd da 1 Output Bos a at for dual or triple standard only This is a vertical blanking interval timing signal The receiver asserts this signal when the vertical blanking interval is active rx V 1 0 Output HD SDI SD SDI bit 1 unused bit 0 xx v Dual link bit 1 unused bit 0 xx v 3G SDI Level A bit 1 unused bit 0 xx v 3G SDI Level B bit 1 link A xx v bit 0 link B xx v rx 1 Output Receiver output that indicates current word is XYZ word xd valid 1 Output nee a current TRS format is legal rx eav 1 Output Receiver output that indicates current TRS is EAV 1 Output Receiver output that indicates current word is TRS This signal is asserted at the first word of 3FF 000 000 TRS sdi tx N
127. ifies the line number and CRC words for HD SDI RP168 Switching Compliance To meet the RP168 requirements the transceiver must be able to recover by the end of the switching line Table 3 4 lists the supported video switching type For more information about the switching line and time for different video formats refer to RP168 Table 3 4 Supported Video Switching Type Standard Data Rate Format RP168 Support Switching Source Fixed Switch same format Yes HD 1080i30 to HD 1080i30 Fixed Switch No HD 1080 to HD 720 Switch Fixed No HD 1080 to SD 525 Switch Switch No HD 1080 to SD 525 Figure 3 5 and Figure 3 6 show the behaviors of the aligner and format blocks during the RP168 switching The aligner block immediately aligns to the next TRS timing based on the user input en sync switch signal Figure 3 5 Aligner Block Behavior 1 2 3 rx data 10200 J 00000 00 40020 JJ 10200H JJ 10200H 0 10200 W 10200H tx data 10200 f 00000H 10200H 0 10200H JJ 10200H JJ 10200H JJ 10200H dead time switch line y 10 T 12 alignment 03H 12H 4 align locked rx status 2 Notes to Figure 3 5 1 Mismatch in alignment 2 New alignment on the next TRS 3 Data aligned to new alignment 4 Zero interrupt February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide
128. ign entity To create a new project follow these steps 1 Choose Programs Altera Quartus II version Windows Start menu to run the Quartus II software Alternatively you can use the Quartus II Web Edition software 2 On the File menu click New Project Wizard 3 Click Next in the New Project Wizard Introduction page the introduction page does not display if you turned it off previously February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 2 4 Chapter 2 Getting Started SDI Walkthrough 4 In the New Project Wizard Directory Name Top Level Entity page enter the following information a Specify the working directory for your project For example this walkthrough uses the c altera projects sdi_project directory 57 The Quartus II software automatically specifies a top level design entity that has the same name as the project This walkthrough assumes that the names are the same b Specify the name of the project This walkthrough uses project for the project name 5 Click Next to close this page and display the New Project Wizard Add Files page La When you specify a directory that does not already exist a message prompts you to create a specified directory Click Yes to create the directory 6 If you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software you must add the user libraries a Click User Li
129. ink Testbench In general all testbenches are constructed in such a way that the serial transmit data is looped back to receiver Figure 2 2 shows how the serial transmit data is looped back to the receiver in the testbench Figure 2 2 General Simulation Testbench SDI RECEIVE TEST Transmitter TRS Counter SDI Pattern Generator SD 270 Mbps HD 1 485 Gbps 3G 2 97 Gbps Transmitter Data Descrambler r gt SDI IP CORE Transmitter SDI TRANSMIT TEST ALTGXB RECONFIG 1 SDI IP CORE Receiver y Receiver TRS Checker Receiver Lock Checker Receiver Line Checker Note to Figure 2 2 1 For dual or triple standard only Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 2 Getting Started 2 9 Simulating the Design A testbench basically consists of transmit test and receive test The transmit test accepts the same serial data as the receive device under test DUT deserializes and decodes the transmitted data and computes the number of time reference signals TRS seen The receive test verifies the features that are supported by the SDI receiver by monitoring the received data status bits line numbering and other related features For dual and triple standard modes the SDI receiver requires reconfigu
130. ints i d cias iei e yh Renner ede dedo e tt Pee bee e de deer 2 11 Single Channel eee ettet teretes eer p iriure ceder atado 2 11 Multiple Channels died at pe QUEUE quee Fa ete topo Ua ee NOE ees 2 12 Compiling the Design uis t pde teh estet eese stc eese dase eese abn 2 14 Programming a Device esee c doe CER RR e REEL RR E Re on d e dh Soon dod setas 2 14 Setting Up Licensing Re e Rache RR IR RR Rr UR ee M RD rien 2 15 Chapter 3 Functional Description Block DescriptiOD Oa be RHEE eek be Sb dt E petet 3 2 Transmitter D 3 2 HID SDLEN Insertion 2b re ace pa eda e ea cioe at 3 4 HD SDI CRC Generation and Insertion 6 06 eee 3 4 Scrambling and NRZI Coding 0 66 n 3 5 Transceiver Clock E mu 3 5 Receiver iai ee qc d A Ea Feed d dct ie et Pi a Ee ud es dia o e ede 3 6 NRZI Decoding and Descrambling 3 8 Word Alignment oce Eee CET CI eerie ib eed bedding 3 8 Video Timing Flags Extraction 6 cc nee 3 9 RP168 Switching Compliance 60 66 enn 3 9 5011 EXER A CHOI cer ete ERR terr gebe pu eben 3 10 HID 9SDILCRC Checking i eI e bte Ie EHE ane E AC eee bait 3 10 Accessing rariscetvet isse seed RR e REOR ed REA X M Ga eR eate a kd R n 3 10 Transceiver Clock pet
131. iod 6 734 waveform 0 000 3 367 get ports tx pclk m Softtransceiver SDI create clock name rx sd refclk 135 3 703 get ports rx sd refclk 135 period 7 407 waveform 0 000 create clock name rx sd refclk 337 period 2 967 waveform 0 000 1 484 get ports rx sd refclk 337 ww create clock name rx_sd_refclk_ 337 90deg period 2 967 waveform 0 000 1 484 get ports rx sd refclk 337 90deg create clock name tx sd refclk 270 period 3 703 waveform 0 000 1 852 get ports tx sd refclk 270 create clock name tx pclk period 37 037 waveform 0 000 18 519 get ports tx pclk Set Multicycle Paths In some device families and speed grades timing violations may occur in the format block of the SDI MegaCore function For SD SDI these violations are multicycle and can be fixed by applying the following constraints to your design these constraints apply only to 50 5015 they are single cycle paths in all other video standards Set multicycle path setup end from get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge 0 u txrx port sdi format format gen u format to get keepers 501 megacore top sdi megacore top inst sdi txrx port sdi txrx port ge 0 u txrx port sdi format format gen u format 2 5 et_multicycle path hold from get_keepers sdi_megacore_top sdi_megacore_top_inst sdi_txrx_port sdi_txrx_port_
132. ion User Guide Chapter 4 SDI Audio IP Cores 4 33 Design Example Figure 4 14 shows the condition of the LEDs Figure 4 14 Condition of LEDs for Transmitting 3G SDI Level B Video Standard D7 DI D10 D11 D12 EN D16 D17 D18 D19 D20 D21 D22 D23 UN NN NEN February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 34 Chapter 4 SDI Audio IP Cores Design Example Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide RYN A Constraints For the SDI MegaCore function to work reliably you must implement the following Quartus II constraints Specify clock characteristics Set timing exceptions such as false path maximum and minimum delays and multicycle path Minimize the timing skew among the paths from I O pins to the four sampling registers Set the oversampling clock that the oversampling interface to 135 MHz uses as an independent clock domain Specifying TimeQuest Timing Analyzer Constraints To ensure your design meets timing and other requirements you must constrain the design This section provides the necessary steps to properly constrain your SDI design using the TimeQuest timing analyzer 1 Make sure that TimeQuest is specified as the default timing analyzer in the Timing Analysis Settings page of the Settings dialog box Perform initial compilation to create an initial design
133. ion TCL files to support either the ordinary AES audio inputs or the Avalon ST audio interface If you select a MegaCore function with ordinary audio interfaces within SOPC Builder the audio interfaces are exposed for connection at the top level of the SOPC Builder design Otherwise the Avalon ST audio interfaces are exposed within SOPC Builder for connection to other components Alternatively you can also instantiate the SDI Audio Embed and Audio Extract MegaCore functions directly in your RTL and drive the direct control interface signals directly without the accompanying Avalon MM register interface Simulating the Testbench Altera provides a fixed testbench as an example to simulate the SDI Audio cores You can obtain the testbench from ip altera audio_embed simulation directory To use the testbench with the ModelSim simulator follow these steps 1 Open the Quartus II software 2 On the File menu click the New Project Wizard 3 Specify the working directory to ip altera audio embed simulation megacore build and give a sensible name for your project and top level entity Click Next and select Stratix IV for the device family Click Finish On the Tools menu click the MegaWizard Plug In Manager Select Edit an existing custom megafunction variation and click Next Locate and click the variant audio embed avalon top v file and click Next 3 opo Coo UON GT In the SDI Audio Embed parameter editor click Finish
134. is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website at www altera com St For system requirements and installation instructions refer to Altera Software Installation amp Licensing Figure 2 1 shows the directory structure after you install the SDI MegaCore function where lt path gt is the installation directory The default installation directory on Windows is c altera lt version gt on Linux it is opt altera lt version gt February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 2 2 Chapter 2 Getting Started Design Flow Figure 2 1 Directory Structure C path Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores Lf altera Contains the Altera MegaCore IP Library common m Contains shared components sdi Contains the SDI MegaCore function files Contains design examples a2gx_tr Contains a design example for Arria II GX 0 s2gx_tr Contains a design example for Stratix II GX see AN 339 Serial a lib Digital Interface Demonstration for Stratix Il GX Devices ___ Contains encrypted lower level design files and other support files simulation Contains simulation files M hdsdi Contains the HD SDI simulation files
135. iving video format specification Table 3 17 Receiving Video Format Specification Part 1 of 2 rx_video_format rx_video_format Video Total Active Word per Rate rx video format 4 3 0 Standard Lines Total Line 7 5 Pro gressive Interlace Frame Rate SD 0 0 8 720p60 60 7 4 16560 720p59 94 59 94 6 720p50 1980 50 5 720p30 720 30 4 P 3300 2 1 720p29 97 29 97 3 720p25 3960 25 2 720p24 24 1 4125 720 23 97 23 97 0 1035130 30 3 0 4 1035 2200 1035129 97 29 97 3 0 3 1080125 2376 25 4 2 1080160 60 7 2200 1080159 94 59 94 6 L 1080 l 0 1080i50 2640 50 1 5 1080i24 24 1 2750 1080123 97 23 97 0 February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 3 50 Table 3 17 Receiving Video Format Specification Part 2 of 2 Chapter 3 Functional Description Signals Dual link bit 3 Y link bit 2 C link B bit 1 Y link A bit 0 C link A 36 501 Level A bits 3 2 unused bit 1 Y bit 0 C 3G SDI Level B bit 3 Y link A bit 2 C link A bit 1 Y link B bit 0 C link B rx video format rx video format Video Total Active Word per Rate rx video format 4 3 0 Standar
136. king Scheme tx_pclk 5 tx_serial_refclk tx_serial_refclk1 4 gxb2_cal_clk sdi_reconfig_clk Protocol Block Transmitter Transceiver Interface Block Transceiver Block i txdata 19 0 tx pclk encoded data 19 0 iy gxb_tx_core_clk gxb_txword 19 0 tx_pclk ALTOXB tx_clkout pll_inclk 1 pll_inclk1 optional cal_blk_clk reconfig_clk gxb tx clkout sdi tx serialidata out a E E E February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 6 Chapter 3 Functional Description Block Description Receiver The receiver contains the following elements m Transceiver plus control and interface logic with multirate dual or triple standard SD HD SDI receiver operation SD HD SDI receiver descrambler and word aligner HD SDI receiver CRC and LN extractor Receiver framing with extraction of video timing signals Identification and tracking of ancillary data The SDI receiver consists of the following functions NRZI decoding and descrambling Word alignment Video timing flags extraction RP168 switching compliance HD SDI LN extraction HD SDI CRC Accessing transceiver Serial Digital Interface 501 MegaCore Function February 2013 Altera Corporation User Guide Chapter
137. ling rate is 11 For SD SDI operation the transmitter reference clock can be derived from pclk by using one of the transceiver PLLs The PLL can multiply the 27 MHz pclk signal by 5 2 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 20 Chapter 3 Functional Description Block Description For all other standards use an external multiplexer to select between the alternative reference clocks Table 3 7 lists the frequencies of the transmitter clock tx serial refclk for Arria GX Arria II GX Arria V Cyclone IV GX Cyclone V Stratix II GX Stratix IV and Stratix V devices Table 3 7 Transmitter Clock Frequency Arria GX Arria Il GX Arria V Cyclone IV GX Cyclone V Stratix Il GX Stratix IV and Stratix V Devices SD SDI Video Standard Clock Frequency MHz 67 5 HD SDI including dual link 74 175 74 25 HD SDI with two times oversample 148 35 148 5 1 Dual standard 67 5 74 175 74 25 Triple standard 148 35 148 5 1 36 901 148 35 148 5 Note to Table 3 7 1 Thetx serial refclk signal must be externally multiplexed If additional input reference clock port is enabled for serial reference clock external multiplier is no longer required Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 21 Block Description Fi
138. ller SD SDI Receiver Oversampling Arria GX and Stratix II GX transceivers do not support CDR for data rates less than 622 Mbps Arria II GX Arria V Stratix IV and Stratix V transceivers do not support CDR for data rates less than 600 Mbps The receiver uses fixed frequency oversampling for the reception of 270 Mbps SD SDI The transceiver samples the serial data at 1 350 or 2 970 Mbps and the SD SDI receiver oversampling logic extracts the original 270 Mbps data Figure 3 13 shows an example of the receiver data timing Figure 3 13 Receiver Data Timing rx olk 67 5MHz rxdata rx_data_valid_out Transceiver Controller To achieve the desired receiver functionality for the SDI the transceiver controller controls the transceiver When the interface receives SD SDI the transceiver receiver PLL locks to the receiver reference clock When the interface receives HD SDI the transceiver receiver PLL is first trained by locking to the receiver reference clock When the PLL is locked it can then track the actual receiver data rate If a period of time passes without a valid SDI signal the PLL is retrained with the reference clock and the process is repeated Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 25 Block Description First the transceiver contro
139. ller makes a coarse rate detection of the incoming data stream Then the transceiver is reprogrammed using transceiver dynamic reconfiguration refer to Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers on page 3 27 and Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode Cyclone IV GX on page 3 33 to the correct rate for the standard that has been detected After the reprogramming the transceiver attempts to lock to the incoming stream If no valid data is seen in 0 1 s the receiver path is reset and the rate detection is performed again At the start of the rate detection process the level of the three enable xx signals is sampled The level of these signals and the knowledge of the currently programmed state of the transceiver determines if the transceiver requires programming This process ensures that the transceiver is reprogrammed only when necessary Locking to the Incoming SDI Stream The transceiver control state machine uses the presence or absence of TRSs on the stream to determine if SDI is being correctly received A single valid TRS indicates to the control state machine that the receiver is acquiring some valid SDI samples The control state machine only deasserts this flag when it does not detect any EAV sequences within the number of consecutive lines you specified At this point the controller state machine resets and performs the relock algorithm refer to Figure
140. lly a single qip file is generated for each MegaCore function or system in the Quartus II compiler 3 Click Exit to close the Generation window Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started SDI Walkthrough 2 7 Table 2 1 describes the generated files and other files that may be in your project directory The names and types of files specified in the MegaWizard Plug In Manager report vary based on whether you created your design with VHDL or Verilog HDL Table 2 1 Generated Files Extension variation name v or vhd Description A MegaCore function variation file which defines a VHDL or Verilog HDL description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus II software variation name cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name hsf Quartus symbol file for the MegaCore function variation You can use this file in the Quartus Il block diagram editor variation name gt html MegaCore function report file variation name ppf This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner MegaCore pin attributes include pin direction lo
141. logic is required in handling the handshaking between the SDI MegaCore function and the ALTGX RECONFIG block By default the receiver reconfiguration has higher priority than the transmitter reconfiguration Transceiver Reconfiguration for Receiver The ROMs store the alternative setups for the transceiver settings within the device These setups are 28 words by 16 bits for Arria GX and Stratix II GX devices and 38 words by 16 bits for Arria II and Stratix IV devices The ALT2GXB megafunction has a serial reprogramming interface so the ALT2GXB_RECONFIG block must serialize this parallel data before loading The following sequence of events occur during an SDI receiver rate change 1 SDI MegaCore function detects the incoming video rate and requests reprogramming 2 The ALT2GXB RECONFIG block reads the appropriate ROM serializes the data and applies the serial data to the correct transceiver instance 3 When step 2 is completed the ALT2GXB RECONFIG block indicates to the SDI that reprogramming is complete 4 TheSDI starts the process of locking to the incoming data 57 Some user logic is required to handle the handshaking between the SDI MegaCore function and the ALI2GXB RECONFIG megafunction For example refer to the example design in the exampleNs2gx trNsourceNsdi dprio directory February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 30 Chapter 3 Functional Description Blo
142. mation about this release of the SDI MegaCore function Table 1 2 Release Information Item Description Version 12 1 Release Date January 2013 Ordering Code IP SDI Product ID s 00AE SDI MegaCore function OOEF SDI Audio cores Vendor ID 6AF7 and Errata Te For more information about this release refer to the MegaCore IP Library Release Notes Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release Device Family Support Table 1 3 defines the device support levels for Altera IP cores Table 1 3 Altera IP Core Device Support Levels FPGA Device Families Preliminary support The IP core is verified with preliminary timing models for this device family The IP core meets all functional requirements but might still be undergoing timing analysis for the device family It can be used in production designs with caution HardCopy Device Families HardCopy Companion The IP core is verified with preliminary timing models for the HardCopy companion device The IP core meets all functional requirements but might still be undergoing timing analysis for the HardCopy device family It can be used in production designs with caution Final
143. mese dedu iacta ue woe a eh ec 3 12 Transceiver Soft Logic Implementation 3 12 Transmitter p C S S 0SSSSnSnnm 3 12 Transmitter Clocks 4s sete exe tete iter ether dto see deste teo tun Dent atten 3 12 Receiver A aa Sea shea he avenue acini arcu Sheen ae les aca ese UR eae 3 13 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide iv Contents Receiver Clocks uos eR ERE RERO ER ES EAE quat hee naan sae e EAD ake dacs 3 13 Transceiver Stratix GX Devices s lllelleleeeees esr 3 13 Transmitter Clocks Y Shek ud RE Pe ev deber Wa add 3 13 Receiver Clocks RE ERR RANE DOS EE Re EE ee PG E aar 3 15 Transmitter Transceiver Interface 0 ce cn nen ene t re 3 16 Receiver Transceiver Interface ccc eee eee rre 3 17 Transceiver Arria GX Arria II GX Arria V Cyclone IV GX Cyclone V Stratix II GX Stratix IV GX and Stratix V Devices 2 0 0 ce ee ee ee ent tenet teen e e 3 18 Transmitter Clocks su eor eee ERR eELEY CR Gp RE Oe a ane EVER A e A 3 19 Receiver Clocks ai b e Ce RR ARRA Re e d ag e Read uw 3 22 Transmitter Transceiver Interface 0 ccc ee ee eh re 3 23 Receiver Transceiver Interface 0 0 ee een ence rs 3 24 Locking to the Incoming SDI Stream 1 1 3 25 Transceiver Dynamic Reco
144. n Appendix A Constraints A 3 Specifying TimeQuest Timing Analyzer Constraints Table A 1 through Table A 3 show the values for the constraints Table A 1 Step 1 Specify Clock Characteristics Standard Clocks Units transceiver data rate 270 Mbps tx pclk 27 MHz SDI SD tx serial refclk 67 5 MHz rx 5 oversample clk in 67 5 MHz transceiver data rate 1485 Mbps HD SDI tx pclk 74 25 MHz HD SDI dual link tx serial refclk 74 25 MHz rx serial refclk 74 25 MHz transceiver data rate 2970 Mbps 3G SDI tx pclk 148 5 MHz tx serial refclk 148 5 MHz rx serial refclk 148 5 MHz transceiver data rate 2970 Mbps DR TR tx pclk 148 5 MHz tx serial refclk 148 5 MHz rx serial refclk 148 5 MHz rx sd refclk 135 135 MHz rx sd refclk 337 337 MHz Soft transceiver SDI rx sd refclk 337 90 337 MHz tx sd refclk 270 270 MHz tx pclk 27 MHz Table A 2 Step 2 Set Timing Exceptions Part 1 of 2 Set Multicycle 1 Define Setup and Hold Standard Paths set_clock_group set false path 1 Relationship t to tx pclk switchline get clocks 50 501 pM transmit pcs0 clkout g receive pcs0 clkout u_torma xb_tx_coreclk gxb rxclk HD SDI rx serial refclk switehline i receive_pcs0 clkout gst clocks HD SDI dual link pace receive pcs0 clkout 3G SDI tiie gxb rxclk E DR tx pclk TR transmit pcs0 clkout g xb tx coreclk February 2013 Altera Corporation
145. n With Altera s free OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPP megafunction within your system m Verify the functionality of your design and quickly evaluate its size and speed with ease m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware You are required to obtain a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production St For more information about OpenCore Plus hardware evaluation using the SDI refer to OpenCore Plus Time Out Behavior on page 3 39 and AN 320 OpenCore Plus Evaluation of Megafunctions February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 1 6 Chapter 1 About This MegaCore Function Resource Utilization Resource Utilization Table 1 7 lists the typical resource utilization for various parameters with the Quartus II software version 11 1 57 The resource utilization of the MegaCore function is based on the bidirectional interface settings unless otherwise specified Table 1 7 Resource Utilization Part 1 of 2 Device Video Standar
146. n ST Audio Interface To allow the standard components inside SOPC Builder to interconnect you must define the Avalon ST audio interface The Avalon ST audio interface must carry audio to and from physical AES3 interfaces which means to support the AES3 outputs the interface must transport the extra V U and C bits You may create the P bit Each audio block consists of 192 frames and each frame has channels 1 and 2 Each frame has a combination of the bits shown in Figure 4 5 Figure 4 5 AES Format AUX data Preamble 4 bit or Audio data 4 bit AES channel pair 1 sub frame 2 CH2 Audio data 20 bit The Avalon ST is a packet based interface which carries audio information as a sequence of data packets The functions define the types of packets as audio data packets and audio control packets February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 22 Chapter 4 SDI Audio IP Cores Avalon ST Audio Interface Figure 4 6 shows the audio data and audio control packets for Avalon ST audio interface Figure 4 6 Audio Data and Audio Control Packets for Avalon ST Audio Interface Audio Data Packet 1 MSB LSB MSB LSB T T 55 DO AUX data 4 bits Audio data 20 bits D192 AUX data 4 bits Audio data 20 bits bse
147. n g Altera Designs chapter in volume 3 of the Quartus II Handbook Altera provides the following three Quartus II projects for use with NativeLink in the ip altera sdi simulation directory m HD SDlin the hdsdi directory m HD SDI3 Gbps in the hdsdi 3g directory m HD SDIduallink in the hdsdi dual link directory m Triple standard SDI in the trsdi directory Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started Specifying Constraints 2 11 To set up simulation in the Quartus II software using NativeLink follow these steps 1 On the File menu click Open Project Browse to the desired directory hdsdi hdsdi_3g hdsdi_dual_link or trsdi 2 Open sdi_sim qpf Check that the absolute path to your third party simulator executable is set On the Tools menu click Options and select EDA Tools Options 4 On the Processing menu point to Start and click Start Analysis amp Elaboration 5 On the Tools menu point to Run EDA Simulation Tool and click EDA RTL Simulation Specifying Constraints You must apply the Altera provided timing constraint file in Synopsys Design Constraints File sdc format and the additional Tcl Script File tcl to ensure the SDI MegaCore function meets the design timing requirements To add the sdc file to your project click Add Remove Files in Project on the Project menu and browse to select lt variation name gt _sdi sdc file
148. nal serial reference clock feature m Updated Table 3 21 with Enable TX PLL select for 1 1 000 and 1 1 001 data rate reconfiguration parameter m Updated information in the Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers m Updated Table 4 1 Table 4 4 and Table 4 14 to include information about asynchronous and synchcronous modes m Added information about accessing transceiver m Updated Table 3 12 with new signals re clk rate and rx video format July 2011 11 0 Updated the high level block diagram of design example for the SDI Audio IP Core to include AES input and output modules m Updated the SDI Audio IP Core register maps m Added two new GUI parameters for SDI MegaCore function Enable Spread Spectrum feature and Tolerance to consecutive missed EAV m Added a chapter on the SDI Audio IP Cores SDI Audio Embed Audio Extract Clocked Audio Input and Clocked Audio Output MegaCore functions February 2013 12 1 November 2011 11 1 December 2010 10 1 February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Info 2 Additional Information Document Revision History Date July 2010 Version 10 0 Changes m Added information for Cyclone IV devices m Added a section on transceiver dynamic reconfiguration with PLL reconfiguration mode Cyclone IV GX Added transceiver dynamic reconfiguration signals
149. nce clock which prevents them from operating independently Receivers in a quad share a common training clock but have independent receiver PLLs Because the same training clock is used for SD SDI and HD SDI receivers can accommodate the different standards within a single quad Transmitter Clocks The transmitter requires two clocks a parallel video clock tx pclk and a transmitter reference clock x serial refclk The parallel video clock samples and processes the parallel video input For SD SDI it is 27 MHz for HD SDI it is 74 25 or 74 175 MHz The transceiver uses the transmitter reference clock to generate the high speed serial output The transceiver is configured for 20 bit operation so the reference clock is 1 20 of the serial data rate For SD SDI because of the oversampling implementation the serial data rate is five times the SDI bit rate for example 1 350 Mbps For HD SDI operation pc1k can drive the transmitter reference clock February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 14 Chapter 3 Functional Description Block Description For SD SDI operation you can derive the transmitter reference clock from pclk by using one of the Stratix GX PLLs The PLL can multiply the 27 MHz pclk signal by 5 2 For dual standard operation use an external multiplexer to select between the SD SDI and HD SDI reference clock The Stratix GX architecture allows each gro
150. nfiguration for Dual Standard and Triple Standard Receivers 3 27 Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode Arria II GX HardCopy IV GX Stratix GX Stratix and Stratix IV GX usse deret Tb pre ibn at ped er qa idu eto E pde 3 27 Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode Cyclone IV GX 3 33 Reset Requirement During Reconfiguration 0 0 3 36 OpenCore Plus Time Out Behavior een 3 39 Signals essei re o belium ue ba ceva shop reda eva o C edere ne EE NU Rr d RE 3 39 Parameters mp C be REDIERE EA E ad be A E ea Slew eS 3 56 MegaCore Verification dcs use du rk e y vlr Ra Ede b re Pd 3 57 Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function 2 6 ene 4 1 Functional Description si set ec eee VET X pae arta eas Vallae ea e VE Re YR RR p e 4 2 Parameters eU Ra RECO REG RERO EG CER Ces 4 3 Signal s ehe debe kia diea 4 4 Register Maps i atts RET 4 8 SDI Audio Extract MegaCore Function 0 4 10 Functional Description cotes e Pe AE A en eee en 4 10 Parameters ses cers ates teh Mae bean areas einer edie erac ed ce ERA ERR EA A oe ORAN de RU Seok 4 11 OignalS sc eee eset face Ed ceu pdt grt cee IM E dae 4 12 Register Maps ivo 2S d eode t Ue ate et ou cela ace PAR
151. nsceiver Native PHY IP Core The native PHY is a thin IP layer with an embedded transceiver PLL The Cyclone V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels Unlike other PHY IP cores the Native PHY IP Core does not include an Avalon Memory Mapped Avalon MM interface Instead it exposes all signals directly as ports The Cyclone V Transceiver Native PHY IP Core includes the Standard PCS You can select the PCS functions and control and status port that your transceiver PHY requires The Native Transceiver PHY does not include an embedded reset controller For more information about the Cyclone V Transceiver Native PHY IP Core refer to the Altera Transceiver PHY IP Core User Guide Transmitter Clocks The transmitter requires two clocks a parallel video clock tx pclk and a transmitter reference clock tx_serial_refclk The parallel video clock samples and processes the parallel video input For SD SDI it is 27 MHz for HD SDI it is 74 25 or 74 175 MHz for 3G SDL it is 148 5 or 148 35 MHz The transceiver uses the transmitter reference clock to generate the high speed serial output The transceiver is configured for 20 bit operation so the reference clock is 1 20 of the serial data rate For SD SDI because of the oversampling implementation the serial data rate is five times the SDI bit rate for example 1 350 Mbps for the triple standard SDI the oversamp
152. nterface SDI MegaCore Function User Guide 3 36 Chapter 3 Functional Description Block Description Reset Requirement During Reconfiguration When a receiver placed in the same channel with a transmitter detects a video format change the receiver goes through a reset sequence for reconfiguration However as both the receiver and transmitter work independently the IP core does not reset the transmitter during the receiver reconfiguration If you require the transmitter to go through a reset sequence you can reset it externally To reset the transmitter externally you must instantiate a separate transmitter and receiver at the Interface Settings option Then connect the SDI_START_RECONFIG signal from the receiver instance to the rst input port in the corresponding transmitter instance while the dynamic reconfiguration controller reconfigures the receiver refer to Figure 3 24 Figure 3 24 Resetting Transmitter Externally During Receiver Reconfiguration Receiver and Transmitter in One Channel sdi reset gt rst Receiver Instance SDI_START_RECONFIG 80 MegaCore Transmitter Instance SDI MegaCore gt Piist Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 37 Block Description Figure 3 25 shows a timing diagram of the receiver reset sequence Figure 3 25 Rese
153. ntirely dependent on the input jitter and jitter transfer function The general recommended approach to system locking with the SDI MegaCore function is to use a voltage controlled crystal oscillator VCXO external to the device The VCXO must be locked to the receiver clock out of the SDI MegaCore function The SDI MegaCore function then uses the clean VCXO output as the transmit clock Loopback FIFO Buffer For more efficient transmission place a FIFO or buffer between the receiver clock domain logic and the transmit clock domain logic The decoded receiver data is connected to the transmitter input through a FIFO buffer When the receiver is locked the logic writes the receiver data to the FIFO buffer When the FIFO is half full the transmitter starts reading encoding and transmitting the data Figure C 1 shows the clocking scheme of the received and retransmitted data Figure C 1 Receive and Retransmit SDI Receiver FIFO SDI Transmitter rx data Ji data J petx data sdi out rx_clk wrclk tx_clk gxb_clkout refclk refclk XTAL a VCXO sdi in February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide c 2 Appendix C Receive and Retransmit Loopback FIFO Buffer Serial Digital Interface SDI MegaCore Function February 2013 Altera Corp
154. number of audio groups you specify m Bit 1 0 Audio group 1 m Bit 3 2 Audio group 2 m Bit 5 4 Audio group 3 m Bit 7 6 Audio group 4 Sine Channel n Frequency T 0 Sine channel frequency RW Defines the frequency of the generated audio Channel Status RAM 7 0 Channel status data WO Write accesses within the address range 10h to 3Fh to the channel status RAM This field returns the 24 bytes of channel status for X channels starting at address 10h to 27h and the 24 bytes of channel status for Y channels starting at address 28h to 3Fh February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 10 Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function SDI Audio Extract MegaCore Function The SDI Audio Extract MegaCore function accepts the SD HD and 3G SDI from the SDI MegaCore and extracts one channel pair of embedded audio The format of the embedded audio is in accordance with the SMPTE272M A standard for the SD SDI video standard or in accordance with the SMPTE299M standard for HD SDI and provisionally for 3G SDI video standard If you are extracting more than one channel pair you must use multiple instances of the component This MegaCore function supports AES audio format for 48 kHz sampling rate Functional Description Figure 4 2 shows a block diagram of the SDI Audio Extract MegaCore function Figure 4 2 SDI Audio
155. o Embed PO PT e rrr A a a a TE Ay GE e Tae das 4 27 Video Pattern Generator PO P1 cscs ccc RR RR RR 4 27 Audio Pattern Generator 2 0 0 0 ee cn ence ete en hr 4 27 Ancillary Data Insertion PO P1 1 6 eee nn 4 27 Transceiver Dynamic Reconfiguration Control Logic 66666 e eee 4 27 Hardware and Software Requirements 2 6 6c enn eee ene 4 28 Hardware Setup css sisser ee e Re ree Rr pEYE DE ad yes EENE a EE 4 28 Running the Design Example E A EE EE EE AEE eee 4 30 Transmit SD SDI with Embedding of Audio Group 1 1 2 0 0 eee eee 4 30 Transmit HD SDI with Embedding of Audio Group 1 2 4 31 Transmit 3G SDI Level A with Embedding of Audio Group 1 2 4 32 Transmit 3G SDI Level B with Embedding of Audio Group 1 2 3 and 4 4 32 Appendix A Constraints Specifying TimeQuest Timing Analyzer Constraints A 1 Specify Clock Characteristics ccs ccce pere EE CH e oer es deir hee eta A 4 Set Multicycle 2 sees ee eid ced ee pd E need ee A 5 Specify Clocks that are Exclusive or Asynchronous ees A 5 Define the Setup and Hold Relationship between 135 MHz Clocks and 337 5 MHz Zero degree CIOCKS se cia sched dared cues ZU PIXTCURPEeRPG3eCKPPGUCERQGA Rea CET Gerad E Recte etes A 6 Minimize Timing SKEW 0
156. o includes oversampling logic Selecting dual or triple standard SDI includes the processing blocks for both SD SDI and HD SDI standards In addition logic for bypass paths and logic to automatically switch between the input standards is included Interface settings Bidirectional receiver transmitter Selects the ports to be receiver transmitter or bidirectional It switches in or out the receiver and transmitter supporting logic appropriately The same setting is applied to all channels in the variation If you want some to be transmitter and some to be duplex simply create two different MegaCore variations Table 3 21 lists the transceiver options Table 3 21 Transceiver Options Parameter Transceiver and protocol Value Generate transceiver and protocol blocks generate transceiver block only or generate protocol block only Description Selects transceiver or protocol blocks or both When non GX device is chosen only SD SDI protocol block is permitted If you want to generate HD SDI or 3G SDI protocol block you must select a GX device Use soft logic for Uses soft logic to implement the transceiver logic rather than using Stratix II GX Stratix IV or Stratix GX transceivers SD SDI only number transceiver On or off For example if you run out of hard transceivers in your device you can implement the function in soft logic If you have spare transceivers in a d
157. ock trains the receiver PLL in the transceiver For HD SDI operation the clock must be nominally 1 20 of the serial data rate The clock do not have to operate at the data rate because it is only used for the training of the receiver PLL For SD SDI operation the clock must be nominally 1 4 of the serial data rate for example 67 5 MHz The clock do not have to be frequency locked to the data For dual standard operation the receiver reference clock must be 67 5 MHz which allows the transceiver to sample the data for SD SDI at the correct frequency For HD SDI the receiver PLL trains with the 67 5 MHz reference and then tracks to the actual incoming data rate All receiver interfaces can share a common receiver reference clock Table 3 6 lists the frequencies of the receiver clock rx serial refclk forStratix GX devices Table 3 6 Receiver Clock Frequency Stratix GX Devices Video Standard 1 Clock Frequency MHz SD SDI 67 5 HD SDI including dual link 74 175 74 25 2 Dual standard 67 5 Notes to Table 3 6 1 Stratix GX devices do not support 3G SDI and triple standard modes 2 The rx serial refclk signal must be externally multiplexed February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 16 Chapter 3 Functional Description Block Description Figure 3 9 shows the receiver clocks for different video standards Figure 3 9 Receiver Clocks
158. on MM slave interface SDI Audio Embed MegaCore Function The SDI Audio Embed MegaCore function embeds audio into the SD HD and 3G SDI video standards The format of the embedded audio is in accordance with the SMPTE272M standard for the SD SDI video standard or in accordance with the SMPTE299M standard for HD SDI and provisionally for 3G SDI video standard This MegaCore function supports AES audio format for 48 kHz sampling rate The SDI Audio Embed MegaCore function embeds up to 16 channels or 8 channel pairs The input audio can be any of the sample rates permitted by the SMPTE272M A and SMPTE299M standards synchronous to the video If you want to embed audio pairs together in a sample audio group the audio pairs must be synchronous with each other February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 2 Functional Description Figure 4 1 shows a block diagram of the SDI Audio Embed MegaCore function Figure 4 1 SDI Audio Embed MegaCore Function Block Diagram Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function SD HD BG SDI 4 FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Audio Packet Packet Channel Embedder Creation Distribution Status RAM SD HD Audio Embedder Register Interface Audio Embed or Audio Embed with Avalon SD Avalon HD 3G SDI MM Serial Digital Interface
159. or SD SDI 74 25 MHz or 74 17 MHz for HD SDI or 148 5 MHz or 148 35 MHz for 3G SDI standards You can use higher clock rates with the vid datavalid signal vid std 1 0 Input Set this signal to indicate the following formats m 00 for10 bit SD SDI m 01 for 20 bit HD SDI m 10 for 3G SDI Level B m 11 for 3G SDI Level A vid datavalid 0 0 Input Assert this signal when the video data is valid Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Table 4 3 Video Input and Output Signals Part 2 of 2 4 5 Signal vid_data Bits 19 0 Direction Description Input This signal carries luma and chroma information This signal carries luma and chroma information SD SDI m 19 10 Unused m 9 0 Cb Y Cr Y multiplex HD SDI and 3G SDI Level A m 19 10 Y m 9 0 C 3G SDI Level B m 19 10 Cb Y Cr Y multiplex link A m 9 0 Cb Y Cr Y multiplex link B vid out datavalid 0 0 Output The core drives this signal high during valid output video clock cycles vid out trs 0 0 Output The core drives this signal high during the first 3FF clock cycle of a video timing reference signal the first two cycles for 3G SDI Level B This signal provides easy connection to the Altera SDI MegaCore function vid out 1n 10 0
160. oration User Guide N DTE BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this user guide Date Version Changes Updated Table 1 2 Table 1 4 Table 1 5 and Table 1 7 for version 12 1 release Updated information on duplex setting in Table 3 10 Updated information on xx video format signal in Table 3 12 Added a note in Table 3 13 to include information about Arria V and Stratix V devices Added Table 3 14 transceiver PHY management clock and reset signals Updated information on xx status signal in Table 3 18 Added data width information for SDI RECONFIG TOGXB and SDI RECONFIG FROMGXB signals in Table 3 19 Updated the Starting channel number parameter description in Table 3 21 Added reset sequence information and timing diagram in Figure 3 25 Added information about Arria V and Stratix V devices Updated Table 1 2 Table 1 5 Table 1 6 and Table 1 7 for version 11 1 release Updated Parameterizing section to include additional steps to turn on the Enable TX PLL select for 1 1 000 and 1 1 001 data rate reconfiguration option m Updated Transmitter Clocks Transceiver Arria GX Arria Il GX Arria V Cyclone IV GX Cyclone V Stratix GX Stratix IV GX and Stratix V Devices Table 3 7 Table 3 9 Figure 3 3 Figure 3 8 to include information about the optio
161. peration Transmitter clock multiplexer optional The transmitter performs the following functions m HD SDI LN insertion m HD SDI CRC generation and insertion m Scrambling and NRZI coding Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description Block Description m Internal switching between two reference clock signals in the transmitter block This feature is optional and only available for Arria II GZ Stratix IV GX and HardCopy IV devices Figure 3 2 shows the top level block diagram for the SDI transmitter Figure 3 2 SDI Transmitter Block Diagram rst_tx gt txdata 19 0 tx_std 1 0 SDI TRANSMITTER Y Protocol Block ix trs ix In 21 0 enable In enable crc ret tx_pclk reset tx_serial_refclk tx_serial_refclk1 optional gxb4_cal_clk sdi reconfig togxb 3 0 sdi_gxb_powerdown TRS Match LN Insert L3 CRC c CRC y Scrambler 4 0 61 erep oq vy Transceiver Interface Block GXB RX Sample gt ix status gt gxb tx clkout 0 61 urerep jnoyoo o oq yv vvv Transceiver Block gt sdi tx serial data p gt sdi reconfig fromgxb 16 For HD SDI the transmitter accepts 20 bit parallel video
162. r For HD SDI operation the clock must be nominally 1 20 of the serial data rate The clock does not have to be frequency locked to the data because the design only uses it for the training of the receiver PLL For SD SDI operation the clock must be nominally 1 4 of the serial data rate for example 67 5 MHz The clock does not have to be frequency locked to the data For dual or triple standard operation the receiver reference clock must be 148 5 MHz In this mode the transceiver oversamples the SD SDI signals by a factor of 11 All receiver interfaces can share a common receiver reference clock Table 3 8 shows the receiver clock rx serial refclk frequencies Table 3 8 Receiver Clock Frequency Arria GX Arria Il GX Arria V Cyclone IV GX Cyclone V Stratix II GX Stratix IV and Stratix V Devices Video Standard SD SDI HD SDI including dual link Clock Frequency MHz 67 5 74 175 74 25 0 Dual or triple standard 36G SDI 148 35 148 5 9 2 148 35 148 5 Notes to Table 3 8 1 You can use either reference clock for training 2 Must be 148 5 MHz for correct SD SDI operation Serial Digital Interface SDI MegaCore Function User Guide February 2013 Altera Corporation Chapter 3 Functional Description 3 23 Block Description Figure 3 12 shows the receiver clocks for different video standards Figure 3 12 Receiver Clocks
163. r Guide 4 20 Table 4 26 Avalon ST Audio Signals Part 2 of 2 Chapter 4 SDI Audio IP Cores Clocked Audio Output MegaCore Function Signal Bits Direction Description Avalon ST valid signal The MegaCore function aud valrd 0 0 Input asserts this signal when it receives data Avalon ST start of packet signal The MegaCore aud_sop 0 0 Input function asserts this signal when it is starting a new frame Avalon ST end of packet signal The MegaCore aud eop 0 0 put function asserts this signal when it is ending a frame aud data 23 0 Input Avalon ST data bus This bus transfers data For register interface signals refer to Table 4 7 All SDI audio cores use the same register interface signals Register Maps Table 4 27 and Table 4 28 list the register maps for the SDI Clocked Audio Output MegaCore function Table 4 27 SDI Clocked Audio Output MegaCore Function Register Map Bytes Offset Name 00h Channel 0 Register 01h Channel 1 Register 02h FIFO Status Register 03h FIFO Reset Register Table 4 28 SDI Clocked Audio Output MegaCore Function Register Map Bit Name Access Description Channel 0 Register T 0 Channel 0 RW The user defined channel number of audio channel 0 Channel 1 Register T 0 Channel 1 RW The user defined channel number of audio channel 1 FIFO Status Register 7 0 FIFO status RO This sticky bit reports the overflow of the
164. r the SDI Audio Embed MegaCore function Table 4 2 General Input and Output Signals Signal reset fix_clk Width 0 0 0 0 Direction Input Input Description This signal resets the system This signal provides the frequency reference used when detecting the difference between video standards using 1 and 1 1 001 clock rates If its frequency is 0 the signal only detects either one of the clock rates The core limits the possible frequencies for this signal to 24 576 MHz 25 MHz 50 MHz 100 MHz and 200 MHz Set the required frequency using the Frequency of fix parameter vid std rate 0 0 Input If you set the Frequency of fix clk parameter to 0 you must drive this signal high to detect a video frame rate of 1 1 001 and low to detect a video frame rate of 1 For other settings of the Frequency of fix parameter the core automatically detects these frame rates and drives this signal low vid clk48 0 0 Output The 48 kHz output clock that is synchronous to the video This clock signal is only available when you turn on the Frequency Sine Wave Generator or Include Clock parameter Table 4 3 lists the video input and output signals for the SDI Audio Embed MegaCore function Table 4 3 Video Input and Output Signals Part 1 of 2 Signal vid clk Bits 0 0 Direction Input Description The video clock that is typically 27 MHz f
165. ration The SDI receiver reconfigures using transceiver dynamic reconfiguration to perform autodetection and locking to different SDI video standards For more details about transceiver dynamic reconfiguration refer to Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers on page 3 27 Simulate with IP Functional Simulation Models You can simulate your design using the MegaWizard generated VHDL and Verilog HDL IP functional simulation models You can use the IP functional simulation model with any Altera supported VHDL or Verilog HDL simulator To use the IP functional simulation model that you created in Setting Up Simulation on page 2 6 create a suitable testbench St For more information about IP functional simulation models refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Simulating with the ModelSim Simulator For Arria and Stratix series of devices Altera provides two fixed testbenches as examples in the simulation Nmodelsim video standard Nmodelsim directory where video standard is hdsdi or hdsdi dual link The testbenches instantiate the design and test the HD SDI or dual link mode of operation To use one of these testbenches with the ModelSim Altera simulator follow these steps 1 Ina text editor open the simulation batch file simulation Nmodelsim video standard NmodelsimNsdi sim bat Edit it to point to your installation of the Mo
166. rect control interface signals in Table 4 15 appear at the top level Include error checking On or off Include status register On or off Include clock On or off February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 4 12 Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function Signals Table 4 11 lists the clock recovery input and output signals for the SDI Audio Extract MegaCore function Table 4 11 Clock Recovery Input and Output Signals Signal Width Direction Description reset 0 0 Input This signal resets the system Assert this 200 MHz reference clock when you turn on the pele 0 0 Input Include Clock parameter The core asserts this 64 x sample rate clock 3 072 MHz audio clock when you turn on the Include Clock parameter You use this clock to clock the audio interface in synchronous aud clk out 0 0 Output mode As the core creates this clock digitally it is prone to higher levels of jitter The core asserts this sample rate clock when you turn on the aud DURUM 0 0 Output Include Clock parameter Table 4 12 shows the video input signals for the SDI Audio Extract MegaCore function Table 4 12 Video Input Signals Signal Width Direction Description The video clock that is typically 27 MHz for SD SDI 74 25 MHz or 74 17 MHz for HD SDI or 148 5 MHz or 148 35 MHz for 3G SDI standards You can
167. reg clk 0 0 Input Clock for the direct control interface This signal does the same function as the audio control audio control 7 0 Input register in Table 4 9 This signal does the same function as the extended control extended control 7 0 Input register in Table 4 9 This signal does the same function as the video status video status 7 0 Output register in Table 4 9 This signal does the same function as the audio status audio status 7 0 Output register in Table 4 9 This signal does the same function as the channel status ge control 15 0 Input control registers in Table 4 9 T 7 0 input This signal does the same function as the sine channel 1 sine rreq c d frequency register in Table 4 9 This signal does the same function as the sine channel 2 a a ps 7 0 Input frequency register in Table 4 9 hi 7 0 inut This signal does the same function as the sine channel 3 Sine_treq_ c frequency register in Table 4 9 This signal does the same function as the sine channel 4 sine freg chi EP pu frequency register in Table 4 9 csram addr 5 0 Input Channel status RAM address Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Table 4 6 Direct Control Interface Signals Part 2 of 2 4 7 Signal Width Direction csram_we 0 0 Input Description Drive this
168. signal high for a single cycle of reg c1k signal to load the value of the csram data port into the channel status RAM at the address on the csram port If each input audio pair gets separate channel status RAMs this signal addresses the RAM selected by the extended control port csram data 7 0 Input Channel status data This signal does the same function as the channel status RAM register in Table 4 9 Table 4 7 lists the register interface signals The register interface is a standard 8 bit wide Avalon MM slave Table 4 7 Register Interface Signals Signal Width Direction Description reg_clk 0 0 Input Clock for the Avalon MM register interface reg reset 0 0 Input Reset for the Avalon MM register interface reg base addr 5 0 Input Address in target region of first byte of transfer reg burst count 5 0 Input Transfer size in bytes reg waitrequest 0 0 Output Wait request reg write 0 0 Input Write request reg writedata 7 0 Input Data to be written to target reg read 0 0 Input Read request reg readdatavalid 0 0 Output Requested read data valid after read latency reg readdata 7 0 Output Data read from target February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 4 8 Register Maps Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Table 4 8 and Table 4 9 lists the register m
169. t Agxb u gxb alt4gxb component auto generated transmit pcsO clkout Set false path from get keepers sdi megacore top sdi megacore top inst sdi txrx port sdi txrx port ge n 1 u txrx port switchline to get clocks sdi megacore top inst sdi txrx port gen 1 u txrx port gen duplex alt Agxb u gxb alt4gxb component auto generated receive pcsO clkout Define the Setup and Hold Relationship between 135 MHz Clocks and 337 5 MHz Zero degree Clocks These constraints apply only to soft transceiver SDI m Setup 1 5 clocks 4 43 ns from the 337 5 MHz zero degree clock to the 135 MHz clock Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Appendix A Constraints A 7 Constraints for the SDI Soft Transceiver m Hold zero clocks from the 337 5 MHz clock to the 135 MHz clock Use the set_min_delay command to specify an absolute minimum delay for a given path set min delay from get clocks rx_sd_refclk_337 to get clocks rx sd refclk 135 0 000 Use the set max delay command to specify an absolute maximum delay for a given path set max delay from get clocks rx sd refclk 337 to get clocks rx sd refclk 135j 4 430 Minimize Timing Skew You must minimize the timing skew among the paths from I O pins to the four sampling registers sample a 0 sample b 0 sample c 0 and sample d 0 To minimize the timing skew manually place the sampling registers close to each other and to the
170. t Sequence of the Receiver During Reconfiguration Reconfiguration In Progress sdi start reconfig sdi reconfig done Reconfiguration Input to SDI Complete MegaCore Function analog reset Rx GXB _ digital_reset Rx GXB PLL_LOCK Active Low The following sequence of events occur for the reset sequence of the receiver 1 The SDI MegaCore function resets the Rx transceiver analog and digital reset are asserted after detecting a change in the data rate The SDI MegaCore function asserts SDI_START_RECONFIG to make a reconfiguration request to the ALT2GXB RECONFIG block The ALT2GXB RECONFIG block sets 501 RECONFIG DONE to 0 which indicates to the MegaCore function that the reconfiguration is in progress When the reconfiguration has been performed the ALT2GXB_RECONFIG block sets the SDI RECONFIG DONE to logic 1 which indicates to the SDI MegaCore function to start locking to the incoming data The analog reset of the SDI MegaCore function receiver is deasserted When the CDR PLL locks to the received data HD 3G mode or reference clock SD mode successfully the digital reset of the SDI MegaCore function receiver is deasserted so that the receiver can continue to process valid data The SDI MegaCore function sets the SDI START RECONFIG line to 0 to indicate that the request is completed and acknowledged Generation of ROM Contents For Arria GX and Stratix II
171. tatus data Select 1 to generate a single channel status RAM or 2 to generate separate RAMs for each input audio pair Frequency sine wave generator On or Off Turn on to enable a four frequency sine wave generator You can use the four frequency sine wave generator as a test source for the audio embedder Include clock On or Off Turn on to enable a 48 kHz pulse generator synchronous to the video clock You can use the 48 kHz pulse generator to request data from a sample rate convertor When you turn on the Frequency Sine Wave Generator parameter the core automatically includes this pulse generator Include Avalon ST interface On or Off Turn on to include the SDI Clocked Audio Output MegaCore When you turn on this parameter the Avalon ST interface signals in Table 4 14 appear at the top level Otherwise the audio input signals in Table 4 4 appear at the top level Include Avalon MM control interface On or Off Turn on to include the Avalon MM control interface When you turn on this parameter the register interface signals in Table 4 7 appear at the top level Otherwise the direct control interface signals in Table 4 6 appear at the top level February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide Signals Chapter 4 SDI Audio IP Cores SDI Audio Embed MegaCore Function Table 4 2 lists the general input and output signals fo
172. ter Protocol Blocks ae Scrambler i 1 1 i 1 1 i 1 1 i i FIFO i 1 i 1 1 i 1 1 i ri 1 1 1 i Buffer n Parallel Video In Insert Insert LN CRC i 1 1 il TEC CCEPIT 1 1 1 1 1 1 1 1 Ly i Receiver Protocol Blocks 1 i i i Extract Check LN CRC i Parallel Ali Video Out ger i 1 Track Detect TRS l Ancilliary Format Match i T V he HD SDI Only Misp spiony Ey and Note to Figure 3 1 Descrambler 1 Transmitter PLL 1 For SD SDI designs only you can have a soft logic implementation of the transceiver SDIOut Parallel to Serial T D 1 1 1 1 1 re 1 1 i NEA Nae EE ah a E 1 1 i 1 1 Transceiver 1 1 SDIIn Serial to Parallel i i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rot Receiver i PLL i 1 1 1 1 1 1 l Transmitter The transmitter contains the following elements SD HD SDI transmitter scrambler HD SDI transmitter data formatter which includes a CRC and LN insertion Transceiver plus control and interface logic with multirate dual or triple standard SD HD SDI transmitter o
173. the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative February 2013 Altera Corporation Serial Digital Interface 501 MegaCore Function User Guide 2 16 Chapter 2 Getting Started Setting Up Licensing Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide N D 2Ya 3 Functional Description The SDI MegaCore function implements a receiver transmitter or full duplex interface The SDI MegaCore function can handle SD HD and or 3G SDIs The SDI MegaCore function consists of the following elements m Protocol blocks m SDlreceiver m SDI transmitter m A transceiver A transceiver controller In the MegaWizard Plug In Manager you can specify either protocol or transceiver blocks or both for your design For example if you have multiple protocol blocks in a design you can multiplex them into one transceiver The transceiver can be either a soft logic implementation or a GX transceiver February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 2 Block Description Figure 3 1 shows the SDI MegaCore function block diagram Figure 3 1 SDI MegaCore Function Block Diagram Chapter 3 Functional Description Block Description oe Transmit
174. the far end of the processing chain The SDI Audio Embed MegaCore function accepts these video and audio test sources to create a video stream with embedded audio The SDI Audio Extract MegaCore function then receives the resulting stream to recover the embedded audio You can examine this audio sequence to ensure that the count pattern that was created is preserved The synchronisation requirements of the receive FIFO buffer in the SDI Audio Extract MegaCore function allows you to repeat the occasional sample from the SDI Audio Extract MegaCore function Synchronisation may take up to a field period of typically 16 7 ms to complete You can instantiate another SDI Audio Embed MegaCore function with Avalon ST interface with embedded clocked audio output component and the associated SDI Audio Extract MegaCore function with Avalon ST interface with embedded clocked audio input component in this testbench by selecting G INCLUDE AVALON ST 1 Design Example Altera provides a design example with the SDI Audio Embed and Audio Extract MegaCore functions This design example include the SDI Audio MegaCore functions and instances of the SDI MegaCore function This section discusses the requirements and related procedures to demonstrate the SDI Audio example design with the Stratix IV GX Audio Video Development Kit This section contains the following topics m Components m Hardware and Software Requirements m Hardware Setup m Running the D
175. the transceiver tx coreclk clock It is written on every tx pclk clock and read on every tx coreclk February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 24 Chapter 3 Functional Description Block Description For SD SDI the FIFO buffer also provides the rate conversion required by the transmitter oversampling logic It is written on every other tx_pclk using the SD SDI data width conversion logic It is read on every fifth or eleventh tx coreclk This operation ensures that the transmitter oversampling logic is provided with a word of parallel video data on every fifth or eleventh clock HD SDI Two Times Oversampling This mode performs two times oversampling and runs the transceiver at double rate which gives better output jitter performance This mode requires a higher rate reference clock refer to Table 3 5 on page 3 14 SD SDI Transmitter Oversampling SD SDI requires a 270 Mbps serial data rate which is achieved by transmitting a 1 350 Mbps signal with each bit repeated five times This process ensures that the transceiver runs at a supported frequency In triple standard mode bit are transmitted at 2 970 Mbps with each bit repeated 11 times Receiver Transceiver Interface Altera provides a transceiver interface which interfaces the transceiver to the SDI function The transceiver interface implements the following functions m SD SDI Receiver Oversampling Transceiver Contro
176. ting_channel_number 4 rx_serial_refclk_top1 Ly SDI triple standard transmitter starting_channel_number 8 SDI triple standard receiver B starting_channel_number 12 Transceiver Bank 2 SDI triple standard transmitter A starting_channel_number 0 SDI triple standard receiver A starting_channel_number 4 SDI triple standard transmitter starting_channel_number 8 SDI triple standard receiver B starting_channel_number 12 Serial Digital Interface 501 MegaCore Function User Guide February 2013 Altera Corporation Chapter 2 Getting Started Specifying Constraints 2 13 To specify the constraints perform the following steps 1 5 Parameterize and generate your SDI MegaCore functions SDI triple standard transmitter A SDI triple standard transmitter B SDI triple standard receiver A and SDI triple standard receiver B with their unique starting channel number Edit the Tcl script so that the transceiver top level reference clock matches the name of the clock pin connected to SDI triple standard transmitter A for example tx serial refclk topl Locate tx_serial_refclk_name in the script and change totx serial refclk topl Execute the Tcl script to patch the generated sdc script with the new clock names 57 A back up copy of the sdc script is created before the patch is made and
177. tion The ROM holds the transceiver setting information for 3G SDI video standard As the setup for SD SDI is similar to 3G SDI only two settings are required one for SD SDI and 3G SDI and one for HD SDI The reconfiguration control logic selects the correct transceiver setting and also provides the handshaking between the SDI MegaCore function and the ALTPLL RECONFIG block The PLL reprogramming signals for the transceiver are brought to the top level interface of the SDI MegaCore function This interface is only available when you select Use PLL reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor You must connect this interface only to the ALTPLL_RECONFIG block Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 35 Block Description ALTPLL_RECONFIG Connections Figure 3 21 shows the handshaking between the SDI MegaCore function and the reconfig control logic and the expected output of some of the ALTPLL_RECONFIG signals Figure 3 23 Handshaking between SDI MegaCore Function and ALTPLL_RECONFIG Signals 21 6 SDI_START_RECONFIG y 7 Rx smD t0 11 4 01 c PLL_ARESET PLL_CONFIGUPDATE M PLL_SCAN
178. to regenerate the variant audio embed avalon top v file and produce the simulation model 10 Repeat steps 6 to 9 for the remaining variant files provided in the megacore build directory 11 In a text editor open the simulation script simulation run tcl Edit the script to point to your installation of the Quartus II software For example set quartusdir tools acds 11 0 157 linux32 quartus eda sim_lib 12 Start the ModelSim simulator 13 Run run tcl in the simulation directory This file compiles the design A selection of signals appears on the waveform viewer The simulation runs automatically providing a pass or fail indication upon completion Use this testbench to simulate the SDI Audio Embed MegaCore and the associated SDI Audio Extract MegaCore functions and the SDI Clocked Audio Input MegaCore and the associated Clocked Audio Output MegaCore functions Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores 4 25 Design Example You can select the video standard for the video test source through the generic G TEST STD of the testbench entity which can be set to 0 1 2 or 3 to select SD SDI HD SDI 3G SDI Level A or 3G SDI Level B respectively The audio test source uses the 48 kHz clock output from the SDI Audio Embed MegaCore function The audio test sample comprises an increasing count which allows the testbench to check the extracted audio at
179. to the xx video format signal Detects the received video standard Set input to 0 for a 148 35 MHz receiver serial reference clock Set input to 1 for 148 5 MHz RX serial reference clock gxb tx clkout Output Transmitter clock out of transceiver This clock is the output of the voltage controlled oscillator VCO and is used as a parallel clock for the transmitter It connects internally to the tx_clkout signal of the ALTGX or ALT2GXB megafunction rx clk Output Transceiver CDR clock rx_sd_oversample_clk out Output 67 5 MHz oversample clock output for cascading MegaCore functions SD SDI only rx_video_format Output This signal is related to the refclk_rate signal Indicates the format for the received video The xx video format value is valid after the frame locked signal is asserted For more information about the video specification refer to Table 3 17 Notes to Table 3 12 1 You must tie the tx serial refclkand rx_serial_refclk signals together if you generate SDI duplex using the Stratix V or Arria V devices 2 For Cyclone IV GX devices set the refclk_rate according to the 1 frequency Table 3 13 lists the transmitter clock signals Table 3 13 Transmitter Clock Signals Signal Direction Description lk Input Transmitter parallel clock input For SD SDI 27 MHz _Pe for HD SDI 74 MHz and for 30 501 148 5 MHz tx serial
180. ts Chapter 1 About This MegaCore Function Features idea C e Bd a e Ear b ied o vd eap 1 1 Release InformatiOn i leesenkc aac e hace ad b ab p a RES EEEE EDE ERARE ERE E EEE EDEN Ea 1 2 Device Family Support eS PR qu ony REPRE RN NER M RO wwe P a es 12 General Description miert truan aaa tyes eye UE Dd MN tU Lp ENEE 1 3 OpenCore Plus Evaluation kr renee KERN HORN E ERR eee ee ERE E RE A Ce 1 5 Resource Utilization a RE RECO PER ERE eee aces 1 6 Chapter 2 Getting Started ddl ete diate Re batch dee he doa dated deeded 2 1 SDL Walkthrong TET 2 3 Creating a New Quartus Project 6 ccc ccc cee ence E 2 3 Launching MegaWizard Plug In Manager 0 006 2 4 Paraieterinp sete ddd ace dle ad ada ea decane Rd eee c e e ORE dee bee tea dede tede es 2 5 Setting Up Simulation dss osse ete pe e rer ee e pP Te URSI PER e ea gren aee dr aeri 2 6 Generating Files P slay gs Ade 2 6 Simulating the Designs ete cue ener ee eruitur d desi Saas lend ope An ed KREE EEES 2 8 Testb nch RD 2 8 Simulate with IP Functional Simulation Models 6 ccc een eee 2 9 Simulating with the ModelSim Simulator 0 6 6 eee eens 2 9 Simulating in Third Party Simulation Tools Using NativeLink 2 10 Specifying Constra
181. u must connect this signal to the rx std flag hd sdnoutput of the transceiver block in a split protocol transceiver design rx protocol in 20N 1 0 Input External data in for protocol only mode rx protocol locked N 1 0 Input Input to transceiver control logic When active this signal indicates to the transceiver control logic that the protocol blocks are locked to stop the transceiver search algorithm at the current rate rx protocol rst N 1 0 Input Reset for the protocol block This signal resets the protocol blocks You can connect this signal to the rx status 1 pin sdi reset in a split transceiver protocol design rx protocol valid N 1 0 Input External data valid in for protocol only mode rx protocol rate 1 0 Input Input to the protocol block This signal indicates the received video standard to the protocol block However this signal does not distinguish between 3G SDI Level A and 3G SDI Level B streams The aligner block in the protocol block distinguishes the 3G SDI Level A and 3G SDI Level B streams You must connect this signal to the sta port of the transceiver block in a split transceiver protocol design rx xcvr trs lock N 1 0 Input Input to transceiver control logic You must connect this signal to the xx status 3 pin trs locked of the protocol only receiver block sdi rx N 1 0
182. up of four transmitters a transceiver quad to have a separate transmitter reference clock Table 3 5 lists frequencies of the transmitter clock tx_serial_refclk for Stratix GX devices Table 3 5 Transmitter Clock Frequency Stratix GX Devices Video Standard 1 Clock Frequency MHz SD SDI 67 5 HD SDI including dual link 74 175 74 25 2 HD SDI with two times oversample 148 35 148 5 2 Dual standard 67 5 74 175 74 25 2 Notes to Table 3 5 1 Stratix GX devices do not support 3G and triple standard modes 2 The tx_serial_refclk signal must be externally multiplexed Figure 3 8 shows the transmitter clocks for different video standards Figure 3 8 Transmitter Clocks Stratix GX Devices SD SDI SDI MegaCore P Serial Data Function 67 5 MHz from PLL or Pin HD SDI SDI MegaCore __y Serial Data Function 74 XX MHz 1 from reference clock Dual Standard SDI MegaCore ___y Serial Data Function 67 5 MHz 74 XX MHz 1 Notes to Figure 3 8 1 This frequency can be either 74 175 or 74 25 MHz to support 1 4835 or 1 485 Gbps HD SDI respectively 2 The multiplexer must not be in the device Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Functional Description 3 15 Block Description Receiver Clocks The transceiver requires a receiver reference clock rx_serial_refclk This cl
183. use higher clock rates with the vid datavalid signal Set this signal to to indicate 10 bit SD SDI vid std 1 0 Input formats 01b for 20 bit HD SDI formats 11b for 3G Level A formats and 10b for 3G SDI Level B formats vid datavalid 0 0 Input Assert this signal when the video data is valid This signal carries luma and chroma information SD SDI m 19 10 Unused m 9 0 Cb Y Cr Y multiplex HD SDI and 3G SDI Level A m 19 10 Y m 9 0 C 3G SDI Level B m 19 10 Cb Y Cr Y multiplex link A m 9 0 Cb Y Cr Y multiplex link B vid locked 0 0 Input Assert this signal when the video is locked vid clk 0 0 Input vid data 19 0 Input Serial Digital Interface SDI MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 SDI Audio IP Cores SDI Audio Extract MegaCore Function 4 13 Table 4 13 lists the audio input and output signals for the SDI Audio Extract MegaCore function Table 4 13 Audio Input and Output Signals Signal aud_clk Width 0 0 Direction Input Description Set this clock to 3 072 MHz that is synchronous to the extracted audio For SD SDI inputs this mode of operation limits the core to extracting audio that is synchronous to the video For HD SDI inputs you must generate this clock from the optional 48 kHz output or the audio must be synchronous to the video aud_ws_in 0 0 Input
184. ut it must be consistent over time for this signal to remain active Transmitter status which indicates the transmitter PLL has locked to the tx serial refclk signal This signal is active high for Stratix GX devices and active low for other Altera transceiver based device families rx status 10 0 Output tx status W 1 0 Output February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide 3 52 Chapter 3 Functional Description Signals Figure 3 38 and Figure 3 42 show the behavior of the rx anc data signal in Table 3 18 on page 3 50 Figure 3 38 Behavior of rx anc data valid error Signals 425MA me g 4 5 J i d d rx_clk 148 5 Hz rx_anc_data 19 10 y 00 jus Y 09 vy a EN NEN pic jJ rx_anc_data 9 10 C00 195 5 x anc valid 3 i i i i i i i i rx anc valid 2 i i 1 rx anc error 3 i i i i i i rx anc error rx anc error 1 rx_anc_error 0 i Notes to Figure 3 38 1 Sequence starts with Data Indentifier DID followed by Secondary Data Indentifier SDID or Data Block Number DBN 2 The Y channel goes wrong 3 Data Count DC 4 User data word UDW up to 255 words 5 Checksum wor
185. xrx port sdi txrx port ge n 0 u txrx port soft serdes rx rx soft serdes gen soft serdes rx inst serdes s2p u s2p sample d 0 Constraints for the SDI Soft Transceiver There are constraints specific only to Cyclone devices and there are other constraints that apply to the other devices including Cyclone II Cyclone III and Cyclone IV devices There are also different constraints that apply to the Classic timing analyzer and the TimeQuest timing analyzer February 2013 Altera Corporation Serial Digital Interface SDI MegaCore Function User Guide A 8 Appendix A Constraints Constraints for the SDI Soft Transceiver Non Cyclone Devices These constraints apply to all device families excluding Cyclone but including Cyclone II Cyclone III and Cyclone IV devices that are configured to use a soft transceiver for their receivers Define the following setup and hold relationship between the 135 MHz clocks and the 337 5 MHz zero degree clocks m Setup 1 5 clocks 4 43 ns from the 337 5 MHz zero degree clock to the 135 MHz clock m Hold zero clocks from the 337 5 MHz clock to the 135 MHz clock If you choose to include the PLLs inside the MegaCore function modify the following constraints and apply them to your design Alternatively apply similar constraints to the clocks connected to the rx sd refclk 337 and rx sd refclk 135 signals on your SDI MegaCore function Classic Timing Analyzer Use the following constraints for the
186. you must clear the audio FIFO first for the register to indicate underflow or overflow Clock Status Register Returns the current status of the digital PLL used to create the output e Offset 64 x sample rate clock 6 5 Unused Reserved for future use To create a 48 kHz signal synchronous to the video clock you must 7 74 17 MHz video clock RO detect whether a 1 or 1 1 001 video clock rate is used If you detect a 1 1 001 video clock rate this field returns high Channel Status RAM Read accesses within the address range 10h to 3Fh to the channel status RAM This field returns the 24 bytes of channel status for en Channel status data Wd channel starting at address 10h and the 24 bytes of channel status for Y channel starting at address 28h Serial Digital Interface SDI MegaCore Function User Guide For register interface signals refer to Table 4 7 on page 4 7 All SDI audio cores use the same register interface signals February 2013 Altera Corporation Chapter 4 SDI Audio IP Cores 4 17 Clocked Audio Input MegaCore Function Clocked Audio Input MegaCore Function The Clocked Audio Input MegaCore function converts clocked audio in AES formats to Avalon ST audio For a typical AES input for each channel the Clocked Audio Input function creates a 192 bit validity word user word and channel status word and presents the words as a control packet after the audio data packet Parameters Table 4 18 lists

Download Pdf Manuals

Related Search

Related Contents

Mode d`emploi Espace collaborative Entraide VAE  Security Guide - Oracle Documentation  BP User Manual  Stearns Safety & Survival 429-07 User's Manual  管理運営の基準（PDF：390KB）  Samsung GT-I7500 מדריך למשתמש  Commissioning and Operation USER MANUAL TTX 350/OCELOT    Stoßdämpfer-Prüfgeräte  OWNER`S MANUAL  

Copyright © All rights reserved. Failed to retrieve file