MAX 10 User Flash Memory User Guide
Contents
1. dock read write address _addr _ burstcount 1 waitrequest writedata readdatavalid readdata data Figure 4 9 Read Operation for 10M40 and 10M50 Devices in Parallel Mode dock read write address addr burstcount T1 j waitrequest writedata readdatavalid readdata datao Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 UFM Burst Read Operation 4 13 Figure 4 10 Read Operation for MAX 10 Devices in Serial Mode dock JT TN UT eee II read write address 1 addr burstcount 32 waitrequest Los kaaa writedata readdatavalid l readdata y p eee feo UFM Burst Read Operation The burst read operation is a streaming 32 bit read operation The burst read operation offers the following modes e Data incrementing burst read allows a maximum of 128 burst counts e Data wrapping burst read has fixed burst counts of 2 10M04 08 and 4 10M16 25 40 50 To perform a U2. Pr ekere erk erkek ee IU r kek eK 4 1 Piles Generated for Altera IP COT S 44 4 55 545n40i5 40 kiy 0E M Dien eta adv kara dnos 4 3 Simulating Altera IP Cores in other EDA TO0ls4 eiie tti HR n E HERR RE EIER IUE 4 6 UFM Avalon MM Operating Modes isset diko cu kelanken a sya dera eoi oko bl std ione eee 4 7 UFM Read Status and Control RegiSter qr D IUo DNO Iq EP HUE REPE HORAE 4 7 UEM Write Control Register uere cipit ptt rui a ek dpa tei dde UR Read aie 4 8 UFM Program Write Operation 4 inn ettet east gode reat tue orit d epp RS rens 4 8 UEM Sector Erase Operation eee tee t e pr ce cy i cre ien nic kek n n k 4 10 UFM Page Erase Operdliohuoocso ndun tidesinists nort ei vn rei Cipro e aliii d pda eiit aus 4 10 UEM Read Operation eret tti ex enm RR REPE e d k da k nek k r ake KEN 4 11 UEM Burst Read Operation itt E RR RR ETE RISE E NU SENE HEL EIL ERR RE RES 4 13 Altera On Chip Flash IP Core References eere eene 5 1 Altera On Chip Flash Parametete oues o si T ERIS MENE M RAM D KN M I ce bav DI dE dS 5 1 PY Renge SJ Rubeo T 5 2 Altera On Chip Flash RSIS CGI T 5 4 Additional Information for MAX 10 UFM User Guide A 1 Document Revision History for Content MAX 10 User Flash Memory User Guide A 1 Altera Corporation MAX 10 User Flash Memory Overview 2015 05 04 UG M10UFM X subscrib
3. MAX 10 UFM Architecture and Features C Send Feedback UG M10UFM 2015 05 04 UFM Operating Modes 2 5 Read and program mode this mode allows both data and control slave interface This mode is applicable for both UFM and CFM sectors e Read only mode this mode allows only data slave interface and restricted to only read operations This mode is applicable for both UFM and CFM sectors e Hidden this mode does not allow any read or program write operations This mode is applicable only for CFM sectors The following table shows the comparison between parallel and serial modes Table 2 4 Comparison between Parallel Mode and Serial Mode Avalon MM Data Interface Parallel mode with 32 bit Serial mode with 32 bits based burst data bus count Access Mode Read and program e Read and program Read only e Read only Hidden e Hidden Read Mode Incrementing burst Incrementing burst read only read Wrapping burst read Program Write Operation Single 32 bit parallel Single 32 bit serial program program operation operation MAX 10 UFM Architecture and Features Altera Corporation CJ Send Feedback MAX 10 UFM Design Considerations 2015 05 04 UG M10UFM X subscribe C Send Feedback There are several considerations that require your attention to ensure the success of your designs Unless noted otherwise these design guidelines apply to all variants of this device family Guideline UFM Power Supply Requirement Durin
4. specified device and configuration mode If the protection bit IP core sets one of these bits you cannot read 8 sp CFMI T or program on the specified sector protection bit 9 sp CFMO protection bit 31 10 dummy All of these bits are set to 1 padding Table 5 5 Altera On Chip Flash Control Register 19 0 pe page erase address All 1 s Sets the page erase address to initiate a page erase operation The IP core only accepts the page erase address when it is in IDLE state Otherwise the page address will be ignored The legal value is any available address The IP core erases the corresponding page of the given address Altera On Chip Flash IP Core References CJ Send Feedback Altera Corporation 5 6 Altera On Chip Flash Registers UG M10UFM 2015 05 04 22 20 se sector erase 3 b111 Sets the sector erase address to initiate a sector address erase operation The IP core only accepts the sector erase address when it is in IDLE state Otherwise the page address will be ignored 3 b001 UFMI 3 b010 UFMO 3 b011 CFM2 3 b100 CFM1 3 b101 CFMO 3 b111 Not set Other values Illegal address Note If you set both sector address and page address at the same time the sector erase address gets the priority The IP core accepts and executes the sector erase address and ignores the page erase address 23 wp UFMI write 1 protection The IP core us
5. The UFM operating modes use Avalon MM interface UFM Read Status and Control Register You can access the control register value through the Avalon MM control slave interface MAX 10 UFM Implementation Guides Altera Corporation CJ Send Feedback UG M10UFM 4 8 UFM Write Control Register 2015 05 04 Figure 4 4 Read Status and Control Register The figure below shows the timing diagram for the read status and control register dock address j addr j read readdata value Y To use the control register assert the read signal and send the control register address to the control slave address The flash IP core then sends the register value through the readdata bus UFM Write Control Register You can program write the control register value through Avalon MM control slave interface Figure 4 5 Program Write Control Register The figure below shows the timing diagram for the program control register clock address j addr i write writedata j value j To program the control register assert the write signal The flash IP core then sends address 0x01 control register and writedata register value to control the slave interface UFM Program Write Operation The UFM offers a single 32 bit program write operation Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 UFM P
6. UFM space UFM space Single uncompressed image with UFM space UFM space N E _ memory initialization Single compressed image with UFM space UFM space _ _ _ memory initialization Table 2 3 Dynamic Flash Size Support Compact Variant Dual compressed images Not available Single uncompressed image UFM space UFM space Single compressed image UFM space UFM space Single uncompressed image with Not available memory initialization Single compressed image with Not available memory initialization UFM Block Diagram This figure shows the top level view of the Altera On Chip Flash IP core block diagram The Altera On Chip Flash IP core supports both parallel and serial interfaces for all MAX 10 FPGAs except for 10M02 devices 10M02 devices only allow serial interface Figure 2 1 Altera On Chip Flash IP Core Block Diagram Avalon MM Avalon MM Avalon MM i v Avalon MM Slave Parallel Controller Data Avalon MM Slave Serial Controller Data Parallel Serial UFM Block Interface la Control Register ka Avalon MM Slave Controller Control altera_onchip_flash This IP block has two Avalon MM slave controllers Altera Corporation MAX 10 UFM Architecture and Features C Send Feedback UG M10UFM 2015 05 04 UFM Block Diagram 2 3 e Data a wrapper of the UFM block that p
7. UG M10UFM 2015 05 04 lt your_ip gt qsys System or IP integration file your ip sopcinfo Software tool chain integration file your ip tb qsys Testbench system file lt your_testbench gt _tb csv lt your_testbench gt _tb spd The Qsys system or top level IP variation file lt my_ip gt is the name that you give your IP variation lt system gt sopcinfo Describes the connections and IP component parameterizations in your Qsys system You can parse its contents to get requirements when you develop software drivers for IP components Downstream tools such as the Nios II tool chain use this file The sopcinfo file and the system h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave Different masters may have a different address map to access a particular slave component Altera Corporation MAX 10 UFM Implementation Guides send Feedback UG M10UFM 2015 05 04 Files Generated for Altera IP Cores 4 5 ee RT SEE eee lt my_ip gt cmp The VHDL Component Declaration cmp file is a text file that contains local generic and port definitions that you can use in VHDL design files lt my_ip gt html A report that contains connection information a memory map showing the address of each slave with respect to each master to which it is connected and parameter assignments lt my_ip gt _generation rp
8. write Data Control write writedata read writedata 31 0 ITI internal e 9d Control Register Le rite extemal burstcount x 0 internal write Status Register read Kl external These figures show the detailed overview of the Avalon MM interface during read only operation MAX 10 UFM Architecture and Features LJ Send Feedback Altera Corporation 2 4 UFM Operating Modes UG M10UFM 2015 05 04 Figure 2 4 Altera On Chip Flash IP Core Avalon MM Slave Read Only Operation in Parallel Mode altera_onchip_flash clock reset_n addr x 0 read Avalon MM Slave readdata 31 0 Parallel Controller waitrequest Data readdatavalid burstcount x 0 _ UFM Block I F Parallel UFM Block Interface Figure 2 5 Altera On Chip Flash IP Core Avalon MM Slave Read Only Operation in Serial Mode altera onchip flash clock reset n addr x 0 read Avalon MM Slave readdata Serial Controller waitrequest Data readdatavalid burstcount x 0 REK UFM Block I F Serial UFM Block Interface UFM Operating Modes The UFM block offers the following operating modes Read Burst read Program Write Sector erase Page erase Sector write protection You can choose one of the following access modes in the Altera On Chip Flash parameter editor to read and control the operations Altera Corporation
9. Allows you the flexibility to adjust the burst count bus width e Parallel mode This setting represents the maximum burst count number e Serial mode This setting supports stream read and represents the words to be read for each read operation The Avalon MM interface burst count bus width is equal to 32 read burst count 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG M10UFM 2015 05 04 Con
10. parallel mode and 32 for serial mode In incrementing burst read mode the supported read burstcount range Parallel mode 1 2 burstcount width 1 Serial mode 1 128 32 In wrapping burst read mode parallel mode only the supported read burstcount is fixed to 2 and 4 10M04 and 10M08 2 10M16 10M25 4 10M40 and 10M50 Altera On Chip Flash Registers The following table lists the address mapping and registers for the Altera On Chip Flash IP core Table 5 3 Altera On Chip Flash Control Address Mapping Status Register 0x00 Read only Stores the status and result of recent operations and sector protection mode Control Register 0x01 Read Program Stores the following information e Page erase address e Sector erase address Sector write protection mode Table 5 4 Altera On Chip Flash Status Register busy 2 b00 2 b00 IDLE 2 b01 BUSY_ERASE 2 b10 BUSY_WRITE 2 b11 BUSY READ 2 rs read 1 b0 1 b0 Read failed successful 1 b1 Read successful Altera Corporation Altera On Chip Flash IP Core References C Send Feedback UG M10UFM 2015 05 04 Altera On Chip Flash Registers 5 5 1 b0 ws write 1 b0 Write failed successful 1 b1 Write successful 4 es erase 1 b0 1 b0 Erase failed successful 1 b1 Erase successful 5 sp UFMI _ protection bit 6 sp UFMO protection bit The IP core sets these bits based on the y sp CFM2
11. to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 MAX 10 UFM Architecture and Features 2 2015 05 04 UG M10UFM X subscribe C Send Feedback The UFM architecture of MAX 10 devices is a combination of soft and hard IPs You can only access the UFM using the Altera On Chip Flash IP core in the Quartus II software UFM and CFM Array Size Each array is organized as various sectors You can erase each page or sector independently The Altera On Chip Flash IP core also gives you access to configuration flash memory CFM based on your specification in the parameter editor Table 2 1 UFM and CFM Array Size This table lists the dimensions of the UFM and CFM arrays Pages per Sector PESE Total User Flash restless etfi 0 0 34 10M02 3 3 10M04 0 8 41 29 70 16 1248 2240 10M08 8 8 41 29 70 16 1376 2240 10M16 4 4 38 28 66 32 2368 4224 10M25 4 4 52 40 92 32 3200 5888 10M40 4 4 48 36 84 64 5888 10752 4 4 UFM Memory Organization Map The address scheme changes based on the configuration mode you specify in the Altera On Chip Flash parameter editor The following tables show the dynamic UFM and CFM support based on different configuration mode and MAXIO FPGA var
12. 7 Figure 4 3 Simulation in Quartus ll Design Flow Design Entry HDL Qsys DSP Builder Altera Simulation Models Quartus II Design Flow g Gate Level Simulation Post synthesis functional Post synthesis Analysis amp Synthesis y av simulation netlist functional simulation EDA Fitter T x Netlist Post fit functional Post fit functional lace and route gt F p j Writer simulation netlist simulation Post fit timing Optional Post fit TimeQuest Timing Analyzer imulati li simulation netlist timing simulation Device Programmer Note Post fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current version of the Quartus II software Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models support fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Related Information Simulating Altera Designs UFM Avalon MM Operating Modes
13. FM burst read operation follow these steps 1 Assert the read signal and send the legal burstcount and legal data addresses to the data interface 2 The flash IP core asserts the waitrequest signal when it is busy 3 The flash IP core then asserts the xeaadatavalid signal and sends the data through the readdata bus Note For data wrapping burst read operation if the address reaches the end of the flash it wraps back to the beginning of the flash and continues reading 4 The flash IP core sets the busy field in the status register to 2 b11 or busy read when the read operation is in progress 5 If the operation goes well the flash IP core sets the read successful field in the status register to 1 b1 or read successful It sets the read successful field in the status register to 1 50 failed and changes all empty flash to 1 if you try to read from an illegal address or protected sector UFM Data Incrementing Burst Read The following figures show the timing diagrams for the data incrementing burst read operations for the different MAX 10 devices MAX 10 UFM Implementation Guides Altera Corporation LJ Send Feedback UG M10UFM 4 14 UFM Data Incrementing Burst Read 2015 05 04 Figure 4 11 Incrementing Burst Read Operation for 10M04 and 10M08 D
14. M25 32 128 4 The address wraps back to the 10MAO or 10M50 previous boundary after 128 bits or 4 cycles For example for a wrapping in a 32 bit data interface 1 Start address is 0x02 2 Address sequence will be 0x02 and 0x03 then back to address 0x00 and 0x01 Altera Corporation MAX 10 UFM Implementation Guides send Feedback UG M10UFM 2015 05 04 UFM Data Wrapping Burst Read 4 17 The following figures show the timing diagrams for the data wrapping burst read operations for the different MAX 10 devices Figure 4 16 Wrapping Burst Read Operation for 10M04 and 10M08 Devices clock read write address _ addi y addr1 burstcount 2 waitrequest writedata readdatavalid readdata data0 data1 J data2 data3 Figure 4 17 Wrapping Burst Read Operation for 10M16 and 10M25 Devices clock read write address 341 addr ji addr1 burstcount 4 4 waitrequest di bes 1 writedata readdatavalid readdata data0 data1 data2 data3 data4 data5 data6 j data7 MAX 10 UFM Implementation Guides Altera Cor
15. MAX 10 User Flash Memory User Guide GX subscribe UG M10UFM 2015 05 04 LJ Send Feedback 101 Innovation Drive am an Jose CA 95134 N OPS nA www altera com TOC 2 Contents MAX 10 User Flash Memory Overview e eeeeeeee eee eee Hen n Hee eee e HHR KAK 1 1 MAX 10 UFM Architecture and Features eese entente 2 1 UFM and CFM ATrAYy S Z6 4 44 40 2 1 UFM Memory Organization Map eet be Rr WENE REME Hee ENE RN HEWER N SES KEN WR RE TAR 2 1 UFM Block Stu ER 2 2 Uses cic d Me 2 4 MAX 10 UFM Design Considerations eere eene eene eene 3 1 Guideline UEM Power Supply Reqddlebietitsiosseete dria rincnic na panier EDU FIN RH EDU HAH AK ru AE 3 1 Guideline Program and Read UEM with JT AGL ee otia tinus toes ehe eek kc e RR AHA o 3 1 Guideline UEM Content Initialization eto p ebrii rtr rper tdi ostio ia uU AK HHHH IRE 3 2 Guideline Erase Before Program S aborde n hana nde taion dl bek Wa Ekal ak NE 3 2 MAX 10 UFM Implementation Guides eee eene e eese nene ennnte 4 1 Altera On Chip Flash IP Core 5 entretient re day ee RR lewe E WEL A van a e din dakan 4 1 Introduction to Altera IP Canes a cs i45s3 4o00x i080 4080 Weki nek 0 i khe ke ke Rue tu ke del k n 4 1 Specifying IP Core Parameters and ODptionS
16. atavalid readdata data0 data1 j data2 data3 data4 data5 data6 MAX 10 UFM Implementation Guides CJ Send Feedback Altera Corporation UG M10UFM 4 16 UFM Data Wrapping Burst Read 2015 05 04 Figure 4 15 Incrementing Burst Read Operation for MAX 10 Devices in Serial Mode clock l l eee lii read write address addr kund hun burstcount 64 waitrequest writedata readdatavalid M2 Mo appe readdata Gees e e e Bibi UFM Data Wrapping Burst Read The UFM IP supports data wrapping when it receives an unaligned address Note Wrapping burst read is available only for parallel interface Table 4 2 Data Wrapping Support for MAX 10 Devices Device Data Register Flash IP Data Fixed Supported Data Wrapping Length Bus Width Burst Count 10M04 or 10M08 The address wraps back to the previous boundary after 64 bits or 2 cycles For example for a wrapping in a 32 bit data interface 1 Start address is 0x01 2 Address sequence will be 0x01 then back to address 0x00 10M16 10
17. ation synopsys vcsmx Contains a shell script vcsmx setup sh and synopsys sim setup file to set up and run a VCS MX simulation cadence Contains a shell script ncsim setup sh and other setup files to set up and run an NCSIM simulation submodules Contains HDL files for the IP core submodule lt child IP cores gt For each generated child IP core directory Qsys generates synth and sim sub directories Simulating Altera IP Cores in other EDA Tools The Quartus II software supports RTL and gate level design simulation of Altera IP cores in supported EDA simulators Simulation involves setting up your simulator working environment compiling simulation model libraries and running your simulation You can use the functional simulation model and the testbench or example design generated with your IP core for simulation The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts generated with the testbench You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts NativeLink launches your preferred simulator from within the Quartus II software Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 UFM Avalon MM Operating Modes 4
18. d STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 UG M10UFM 4 2 Specifying IP Core Parameters and Options 2015 05 04 1 Altera Corporation In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core to customize The parameter editor appears Specify a top level name for your custom IP variation The parameter editor saves the IP variation settings in a file named lt your_ip gt qsys Click OK Specify the parameters and options for your IP variation in the parameter editor includ
19. e C Send Feedback Altera MAX 10 FPGAs offer a user flash memory UFM block that stores non volatile information The UFM provides an ideal storage solution that you can access using the Avalon Memory Mapped Avalon MM slave interface to UFM The UFM block also offers the following features HEMEN NE IN Endurance Counts up to 10 000 program erase cycles Data retention after 10 000 program 20 years at 85 C erase cycles e 10 years at 100 C Maximum operating frequency e Serial interface 7 25 MHz e Parallel interface 116 MHz Data length Stores data of up to 32 bits length in parallel 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed
20. e You can copy and paste the contents of this file into your HDL file to instantiate the IP variation lt my_ip gt regmap If the IP contains register information the regmap file generates The regmap file describes the register map information of master and slave interfaces This file complements the sopcinfo file by providing more detailed register information about the system This enables register display views and user customizable statistics in System Console MAX 10 UFM Implementation Guides Send Feedback Altera Corporation 4 6 Simulating Altera IP Cores in other EDA Tools UG M10UFM 2015 05 04 a el lt my_ip gt svd Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system During synthesis the svd files for slave interfaces visible to System Console masters are stored in the sof file in the debug section System Console reads this section which Qsys can query for register map information For system slaves Qsys can access the registers by name lt my_ip gt v or lt my_ip gt vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation mentor Contains a ModelSim script msim setup tcl to set up and run a simulation aldec Contains a Riviera PRO script rivierapro setup tcl to setup and run a simulation synopsys vcs Contains a shell script ves_setup sh to set up and run a VCS simul
21. egisters Added information for the following new Avalon MM slave interface signals for serial mode addr read readdata write writedata waitrequest readdatavalid and burstcount Added information for the following new parameters e Data Interface that allows you to choose between Parallel and Serial interface Configuration Scheme and Configuration Mode that replace Dual Images The new parameters include all supported configu ration modes e Read Burst Count that allows the burstcount width to be auto adjusted September 2014 2014 09 22 Initial release Altera Corporation Additional Information for MAX 10 UFM User Guide O Send Feedback
22. es these bits to protect the sector 24 wp UFMO write 1 from write and erase operation You must clear protection the corresponding sector write protection bit before your program or erase the sector 25 wp CFM2 write 1 Disable write protected protection 1 b0 mode a WP EN Ene Enable write protected protection 1 b1 mode 27 wp CFMO write 1 protection 31 28 dummy All of these bits are set to 1 padding Altera Corporation Altera On Chip Flash IP Core References C Send Feedback 2015 05 04 UG M10UFM Additional Information for MAX 10 UFM User Guide amp Subscribe C Send Feedback Document Revision History for Content MAX 10 User Flash Memory User Guide ERLENNINMEMNE cH May 2014 2015 05 04 Changed write to industry standard term program Added a note to the UFM and CFM Array Size section that the total UFM size is the maximum possible value which is dependent on the selected mode Added design consideration information about the maximum slew rate requirement for power supply ramp down Added design consideration information about erasing the flash location before performing a program operation 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and
23. evices in Parallel Mode clock read write address addr burstcount 8 waitrequest writedata readdatavalid om readdata data0 data1 data2 data3 data4 data5 data6 data7 Figure 4 12 Incrementing Burst Read Operation for 10M16 and 10M25 Devices in Parallel Mode clock read write address addr addr burstcount 6 2 waitrequest Lud Ld writedata readdatavalid readdata data1 data2 data taa atas tna kaz Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 Figure 4 13 Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode clock read write address burstcount waitrequest writedata readdatavalid readdata UFM Data Incrementing Burst Read 4 15 data0 j data1 data2 data3 data4 data5 data6 data7 Figure 4 14 Unaligned Address Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode clock read write address burstcount waitrequest writedata readd
24. figuration mode Single Allows you to select the configuration mode You can uncompressed choose one of these options image 5 2 Altera On Chip Flash Signals e Dual compressed images e Single uncompressed image Accesses CFM2 sector as UFM e Single compressed image Accesses CFM2 and CEMI sectors as UFM e Single uncompressed image with memory initiali zation e Single compressed image with memory initializa tion Flash Memory The sector ID address range value and flash type are generated dynamically by hardware tel based on the device and configuration mode you select Indicates the address mapping for each sector and adjusts the Access Mode for each sector individually Note Only CFM sectors support Hidden access mode Clock frequency 116 0 MHz Key in the appropriate clock frequency in MHz The maximum frequency is 116 0 MHz for parallel interface and 7 25 MHz for serial interface Initialize flash content Off Turn on this option to initialize the flash content Enable non default initializa Off Turn on this option to enable your preferred initiali tion file zation file If you choose to have a non default file type the filename or select the hex file using the browse button User created hex or mif file This option is only available if you turn on Enable non default initialization file Assign your own hex or mif filename User created dat file for This option is only available if yo
25. g UFM and CFM operations make sure to follow the maximum slew rate requirement for power supply ramp down This setting prevents device damage in case of power loss Table 3 1 Maximum Slew Rate Requirement Single supply device 0 073V us Multi supply device 0 023V us 3 3V lt 0 073V us 0 023V us Single Supply Device Multi Supply Device Guideline Program and Read UFM with JTAG You can program UFM using JTAG interface version IEEE Standard 1149 1 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published informatio
26. iant 9 The maximum possible value which is dependent on the mode you select 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN DO fs S AN 101 Innovation Drive San Jose CA 95134 2 2 UFM Block Diagram Table 2 2 Dynamic Flash Size Support Flash and Analog Variants UG M10UFM 2015 05 04 Dual compressed images UFM space UFM space Single uncompressed image UFM space UFM space UFM space Single compressed image UFM space UFM space
27. ing one or more of the following Refer to your IP core user guide for information about specific IP core parameters e Optionally select preset parameter values if provided for your IP core Presets specify initial parameter values for specific applications Specify parameters defining the IP core functionality port configurations and device specific features e Specify options for processing the IP core files in other EDA tools Click Generate HDL the Generation dialog box appears Specify output file generation options and then click Generate The IP variation files generate according to your specifications To generate a simulation testbench click Generate gt Generate Testbench System To generate an HDL instantiation template that you can copy and paste into your text editor click Generate gt HDL Example Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project gt Add Remove Files in Project to add the file After generating and instantiating your IP variation make appropriate pin assignments to connect ports MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 Figure 4 1 IP Parameter Editor Files Generated for Altera IP Cores A IP Parameter Editor unnamed qsys users brossar unnamed qsys mE File Edit Syste
28. logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any ISO 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA UG M10UFM A 2 Document Revision History for Content MAX 10 User Flash Memory User Guide 2015 05 04 ERENNIMEN cC NN December 2014 2014 12 15 Added support for serial interface Added maximum operating frequency of 7 25 MHz for serial interface Updated the UFM block diagram to include serial interface Added design consideration information about creating initial memory content using the IP core and programming UFM using JT AG interface version IEEE Standard 1149 1 Added new timing diagrams for read and write operations in serial mode Added information for the new serial interface related GUI parameters signals and r
29. m Generate View Tools Help Parameters 00 a DEAR Block Symbol 2 unsaved gt altclkctrl_0 li moat amm altcikctri i Name altcikctrl BED E i 4 Anakan E Version 14 0 Author Altera Corporation Altcikctri represents clock buffers that drive the Global Clock Network the Regional Clock Network nti and the dedicated External Clock path Ji Desenption no deseiaptiun Sie YETA Te UE ec MI ij Grou Basic Functions Clocks How do you want to use the ALTCLKCTRL For global clock E P Ha ae How many clock inputs would you like 11 i vum Altclkct Create ena port to enable or disable the clock network driven by this buffer d Altclkctrl How do you want to register the ena port pan C Ensure glitch free switchover implementation New IP Instance New IP Variation Your IP settings will be saved in a qsys file Create IP Variation Entityname unnamed Save in folder users jbrossar 141 sv source i for ALTCLKCTRL 14 0 la a i Target Device i ew BERE Twe ewe unknown R 0 3 Inf unsi e Info Your IP will be saved in users jbrossar 141 sv source unnamed qsys l 5 o jenes lunsa Los New 4 f 0 Errors 0 Warnings i Specify your IP variation name and target device Files Generated for Altera IP Cores The Quartus II software generates the following IP core
30. n and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 UG M10UFM 3 2 Guideline UFM Content Initialization 2015 05 04 The JTAG interface supports Jam Standard Test and Programming Language STAPL Format File Jam Programmer Object File pof and JAM Byte Code File jbc Guideline UFM Content Initialization You can initialize the UFM content using Altera software The initial memory content supports Memory Initialization File mif and Hexadecimal Intel Format File hex You can initialize the UFM content using either one of the following ways e Set the initial memory content through the Altera On Chip Flash IP core e Set the initial memory content through the Convert Programming File tool in the Quartus II software when you convert sof to pof Guideline Erase Before Program Make sure to erase the flash location before you perform a program write operation Altera Corporation MAX 10 UFM Design Considerations C Send Feedback 2015 05 04 MAX 10 UFM Implementation Guides UG M10UFM x Subscribe C Send Feedback Altera On Chip Flash IP Core The Altera IP core design flow helps you get started with any Altera IP core Introduction to Altera IP Cores Altera and strategic IP partners offer a broad portfolio of off the shelf configurable IP cores optimized for Altera devices The Quartus II software installation includes the Altera IP libra
31. output file structure MAX 10 UFM Implementation Guides CJ Send Feedback Apply preset parameters for specific applications View IP port and parameter details Altera Corporation 4 4 Files Generated for Altera IP Cores Figure 4 2 IP Core Generated Files f lt your_ip gt v or vhd Top level simulation file an lt simulator_setup_scripts gt Table 4 1 IP Core Generated Files Femme Delon o my ip qsys f lt your_ip gt v or hd lt your_ip gt cmp VHDL component declaration file lt your_ip gt _bb v Verilog HDL black box EDA synthesis file lt your_ip gt _inst v or vhd Sample instantiation template lt your_ip gt ppf XML 1 0 pin information file lt your_ip gt qip Lists IP synthesis files lt your_ip gt sip Contains assingments for IP simulation files your ip generation rpt IP generation report lt your_ip gt debuginfo Contains post generation information lt your_ip gt html Connection and memory map data lt your_ip gt bsf Block symbol schematic lt your_ip gt spd Combines simulation scripts for multiple cores Top level IP synthesis file A HDL files gt lt testbench gt _tb testbench system a lt testbench gt _tb testbench files simulation files lt EDA tool setup scripts gt f HDI files
32. peration 4 11 To perform a UFM page erase operation follow these steps 1 Disable the write protection mode Write 0 into the write protection register for the sector through the Avalon MM control interface 2 Write the appropriate bits into the control register to select the page erase location The flash IP core stores the page erase address and initiates the page erase operation Note The IP core only accepts the page erase address when the IP is in IDLE state busy field at status register is2 b00 If the IP core is busy it will ignore the page erase address 3 The flash IP core sets the busy field in the status register to 2 b01 when the erase operation is in progress 4 The flash IP core then asserts the wait request signal if there are any new incoming read or write commands from the data interface 5 The flash IP core erases the page It stores the physical flash erase result in the erase successful field in the status register when the page erase operation completes Note The maximum erase time is 350 ms 6 The flash IP core sets the erase successful field in the status register to 1b 0 failed if you send an illegal address 7 Repeat the earlier steps if you want to perform another page erase operation 8 You have to enable back the write protection mode when the page erase operation completes Write 1 into the write protection register for the corresponding page through the Avalon MM control interface Note Check the s
33. poration LJ Send Feedback UG M10UFM 4 18 UFM Data Wrapping Burst Read 2015 05 04 Figure 4 18 Wrapping Burst Read Operation for 10M40 and 10M50 Devices clock read write address addr0 Y addr1 burstcount 4 waitrequest L L writedata readdatavalid readdata data data1 data2 data3 data4 data5 data6 data7 Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback Altera On Chip Flash IP Core References 2015 05 04 UG M10UFM CX subscribe C Send Feedback This section provides information about the Altera On Chip Flash IP Core parameters signals and registers Altera On Chip Flash Parameters The following table lists the parameters for the Altera On Chip Flash IP core Table 5 1 Altera On Chip Flash IP Core Parameters Data interface Parallel Allows you to select the type of interface You can choose parallel or serial Note 10M02 devices support only serial interface Read burst mode Incrementing Allows you to select the type of read burst mode You can choose incrementing or wrapping Incrementing Burstcount range is 1 2 4 mode Zi wo 129 Wrapping Burstcount fixed to 2 or 4 mode Note Serial mode supports only incrementing mode Read burst count 2
34. rogram Write Operation 4 9 To perform a UFM program operation follow these steps 1 Disable the write protection mode Write 0 into the write protection register for the sector of the given data through the Avalon MM control interface Program the following data into flash through the Avalon MM data interface Address legal address from Avalon MM address map e Data user data Set burstcount to 1 parallel mode or 32 serial mode The flash IP core sets the busy field in the status register to 2 b10 when the program operation is in progress If the operation goes well the flash IP core sets the write successful field in the status register to 1 b1 or write successful The flash IP core sets the write successful field in the status register to 1 b0 failed if one of the following conditions takes place e The burst count is not equal to 1 parallel mode or 32 serial mode The given address is out of range e The sector protection mode or write protection mode of the corresponding sector is not clear the value is not 1 50 Repeat the earlier steps if you want to perform another program operation You have to enable back the write protection mode when the program operation completes Write 1 into the write protection register for the corresponding sector through the Avalon MM control interface Note Check the status register after each write to make sure the program operation is successful write
35. rovides read and program accesses to the flash e Control the CSR and status register for the flash which is required only for program and erase operations These figures show the detailed overview of the Avalon MM interface during read and program write operation Figure 2 2 Altera On Chip Flash IP Core Avalon MM Slave Read and Program Write Operation in Parallel Mode This diagram shows the standard interface for all 10M04 10M08 10M16 10M25 10M40 and 10M50 devices in parallel mode altera_onchip_flash clock clock reset_n UFM reset_n SS Block I F UFM addr x 0 lt gt Block addr read Avalon MM Slave Parallel Interface Avalon MM Slave read readdata 31 0 Parallel Controller Controller readdata 31 0 write Data Control write writedata 31 0 read writedata 31 0 WERE internal e Control Register la wite extemal burstcount x 0 internal write Status Register read external Figure 2 3 Altera On Chip Flash IP Core Avalon MM Slave Read and Program Write Operation in Serial Mode This diagram shows the standard interface for all MAX 10 devices in serial mode altera onchip flash clock clock reset_n UFM reset_n gt E Block I F UFM addr x 0 lt gt Block addr read Avalon MM Slave Serial Interface Avalon MM Slave read readdata Serial Controller Controller lt readdata 31 0
36. ry You can integrate optimized and verified Altera IP cores into your design to shorten design cycles and maximize performance You can evaluate any Altera IP core in simulation and compilation in the Quartus II software The Quartus II software also supports integration of IP cores from other sources Use the IP Catalog to efficiently parameterize and generate synthesis and simulation files for a custom IP variation The Altera IP library includes the following categories of IP cores Basic functions DSP functions Interface protocols Low power functions Memory interfaces and controllers Processors and peripherals Note The IP Catalog Tools IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera and other supported IP cores Related Information IP User Guide Documentation Altera IP Release Notes Specifying IP Core Parameters and Options You can quickly configure a custom IP variation in the parameter editor Use the following steps to specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS an
37. successful Figure 4 6 Program Operation in Parallel Mode The figure below shows the write data timing diagram in parallel mode clock address y l addr y write burstcount ji l 1 l y writedata ji l data y waitrequest j Write d UFM Programming UFMReet t address Max 305 us Max250 jis to UFM MAX 10 UFM Implementation Guides Altera Corporation CJ Send Feedback UG M10UFM 4 10 UFM Sector Erase Operation 2015 05 04 Figure 4 7 Program Operation in Serial Mode The figure below shows the write data timing diagram in serial mode clock eco address addr write burstcount 3 writedata 31 j 30 25 27 29 25 e e e efs aBa j waitrequest u Write address to UFM Serial Write 32 bits Data i to UFM 32 Cycles UFM Sector Erase Operation The sector erase operation allows the UFM to erase by sectors To perform a UFM sector erase operation follow these steps 1 Disable the write protection mode Write 0 into the write protection register for the sector through the Avalon MM control interface Write the appropriate bits into the control register to select the sector erase location The flash IP core stores the sector erase address and initiates the sector erase operation Note The IP core only accepts the sector erase address when it is in IDLE sta
38. t IP or Qsys generation log file A summary of the messages during IP generation lt my_ip gt debuginfo Contains post generation information Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect lt my_ip gt qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software Contains information about the upgrade status of the IP component lt my_ip gt csv lt my_ip gt bsf A Block Symbol File bsf representation of the IP variation for use in Quartus II Block Diagram Files bdf lt my_ip gt spd Required input file for ip make simscript to generate simulation scripts for supported simulators The spd file contains a list of files generated for simulation along with information about memories that you can initialize lt my_ip gt ppf The Pin Planner File ppf stores the port and node assignments for IP components created for use with the Pin Planner lt my_ip gt _bb v You can use the Verilog black box _bb v file as an empty module declaration for use as a black box lt my_ip gt sip Contains information required for NativeLink simulation of IP components You must add the sip file to your Quartus project lt my_ip gt _inst v or _inst vhd HDL example instantiation templat
39. tatus register after each erase to make sure the erase operation is successful erase successful UFM Read Operation The UFM offers a single 32 bit read operation To perform a read operation the address register must be loaded with the reference address where the data is or is going to be located in the UFM To perform a UFM read operation follow these steps l Assert the read signal to send the legal data address to the data slave interface 2 Setthe burstcount to 1 parallel mode or 32 serial mode 3 The flash IP core asserts the waitrequest signal when it is busy 4 The flash IP core asserts the xeaadatavalid signal and sends the data through the readdata bus 5 The flash IP core sets the busy field in the status register to 2 b11 when the read operation is in progress 6 If the operation goes well the flash IP core sets the read successful field in the status register to 1 b1 or read successful It sets the read successful field in the status register to 1 50 failed and returns empty flash if you try to read from an illegal address or protected sector The following figures show the timing diagrams for the read operations for the different MAX 10 devices in parallel and serial modes MAX 10 UFM Implementation Guides Altera Corporation LJ Send Feedback UG M10UFM 4 12 UFM Read Operation 2015 05 04 Figure 4 8 Read Operation for 10M04 10M08 10M16 and 10M25 Devices in Parallel Mode
40. te busy field at status register is2 b00 If the IP core is busy it will ignore the sector erase address The flash IP core sets the busy field in the status register to 2 b01 when the erase operation is in progress The flash IP core then asserts the waitrequest signal if there are any new incoming read or write commands from the data interface The flash IP core erases the sector It stores the physical flash erase result in the erase successful field in the status register when the sector erase operation completes Note The maximum erase time is 350 ms The flash IP core sets the erase successful field in the status register to 1 b0 failed if one of the following conditions takes place e You send an illegal sector number e The sector protection mode or write protection mode of the corresponding sector is not clear the value is not 1 50 Repeat the earlier steps if you want to perform another sector erase operation You have to enable back the write protection mode when the sector erase operation completes Write 1 into the write protection register for the corresponding sector through the Avalon MM control interface Note Check the status register after each erase to make sure the erase operation is successful erase successful UFM Page Erase Operation The page erase operation allows the UFM to erase by pages Altera Corporation MAX 10 UFM Implementation Guides C Send Feedback UG M10UFM 2015 05 04 UFM Read O
41. u turn on Enable simulation non default initialization file Assign your own simulation filename Altera On Chip Flash Signals The following table lists the signals for the Altera On Chip Flash IP core Table 5 2 Avalon MM Slave Input and Output Signals for Parallel and Serial Modes ENCCENEEE INNEREN Deerton NN Clock and Reset clock 1 Input System clock signal that clocks the entire peripheral Altera Corporation Altera On Chip Flash IP Core References C Send Feedback UG M10UFM 2015 05 04 Altera On Chip Flash Signals 5 3 HEMZE EKANI KM HEREKE reset_n Input System synchronous reset signal that resets the entire peripheral The IP core asserts this signal asynchronously This signal becomes synchronous in the IP core after the rising edge of the clock Control avmm_csr_addr 1 Input Avalon MM address bus that decodes registers avmm_csr_read 1 Input Avalon MM read control signal The IP core asserts this signal to indicate a read transfer If present the readdata signal is required avmm_csr_readdata 32 Output Avalon MM read back data signal The IP core asserts this signal during read cycles avmm csr write 1 Input Avalon MM write control signal The IP core asserts this signal to indicate a write transfer If present the writedata signal is required avmm csr writedata 32 Input Avalon MM write data bus The bus master asserts this bus during write c
42. ycles Data avmm data addr User defined Input Avalon MM address bus that indicates the flash data address The width of this address depends on your selection of device and configuration mode avmm data read 1 Input Avalon MM read control signal The IP core asserts this signal to indicate a read transfer If present the readdata signal is required avmm data readdata Parallel Output Avalon MM read back data signal The IP core mode 32 asserts this signal during read cycles e Serial mode 1 avmm_data_write 1 Input Avalon MM write control signal The IP core asserts this signal to indicate a write transfer If present the writedata signal is required avmm data writedata parallel Input Avalon MM write data bus The bus master asserts mode 35 this bus during write cycles e Serial mode 1 avmm data 1 Output The IP core asserts this bus to pause the master waitrequest when the IP core is busy during read or write operations avmm_data_readdata 1 Output The IP core asserts this signal when the readdata valid signal is valid during read cycles Altera On Chip Flash IP Core References Send Feedback Altera Corporation 5 4 Altera On Chip Flash Registers UG M10UFM 2015 05 04 sore f wen f precion TO Deerton avmm_data_ burstcount User defined Input The bus master asserts this signal to initiate a burst read operation e In write operations the burstcount is always fixed to 1 for
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