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KITPF0200EPEVBE, Evaluation Board - User Guide

1. A I LDO SUPPLIES VGEN SENSE I a HY R20 DNP H U1B r DNP VGEN1 I ma VGEN1 veeni KVEN I R24 DNP VINi 17 16 VGEN1 C34 22UF 33 AA VIN1 VGEN1 vape 1 DNP Queen R22 VIN2 27 18 VGEN2 A0 VGEN2 1 sw HA VIN2 VGEN2 vus e VGEN2 lt lt VREFDDRI vin 82 DNP VINS 40 ng vena 29 VGEN3 venu D 2 2UF ih TER vega ven VREFDDR R25 28 VGEN4 ATUF NA sw Ha VGEN4 BN VGENS 3 C41 DNP 9 VGEN4 C40 39 VGENS C42 22UF VGEN4 1 1 0UF VGENS VGENG 1 T VOEM amp e 3 31 41 VGENG cas DNP VGENS I swan 392 ES VREFDDR VGEN6 NA verns Veens VINREFDDR 1 swaB D R27 DNP VINREFDDRT ucen 42 A ES O vcens 1 J20 VGEN6 LL c84 F 29 Ar VSNVS R86 1 CUP VHALF1 e T 0 Ho 1 2 DNP VSNVS1 I DNP 43 DNP Cap CLOSED BATI VSNVS VSNVS VSNVS ISNVS o2uF STO lt 1 C47 HDR 1X3 MMPF0200NPAEP 0 47uF a LICELL 1 Sen Leaded 1 Place Top H Bar 1 a BK 879 6 8mm Place Bottom DNP 1 1 LE p Wo paaa aaa I INPUT SUPPLIES LDO INPUT SENSE 1 i SWIN PVN SWVIN VIN 1 w T VIN1 VIN Pigs op 0 34 VIN2 VIN2 J25 yo HDR1X2T
2. 1 USB Connector Type A H CLOSED 2 3 I VIN USB Y E MAIN IC 1 993 MC9S08JM60 sl cso i H 057 our PEA HOR 1X3 Place on Bottom 1 1 DE 1 x bal va p H Usain gt VIN_USB 1 uz E D 1 FT L41 24 a 9 VUSBEN d HI1812V101R 10 I AAH ES HS O BSTEN D 11 VPGMEN 1 PTE2 TPMICHO 3VSEN I PTESITPMICH L D e e gt a Raz n0281 PTBOMISO2 ADPO 8 PTE4 MISO1 D Bie D m 4 1 PTB1 MOSI2 ADP1 ba PTESIMOSI1 LAR Es D i VDDOTPIN_SNS gt 29 PAPA PTESSESCK1 16 BSTDN 1 H E 1 SC 2 user 1 PTBA KBIPA ADPA D 1 NAG 1 PTBS KBIPS ADP5 T 5 l eS ud PTC0 SCL PrrorPMiCH2 i SENS D 5 PTO1SDA PTFI TPMICH3 LE 1 HH812V101R 10 g7 PTC2 PTF4 TPM2CHO L 1 1 1 7 PTCamoa PTFSITPM2CH1 LA 1 4671 PTCA PTF6 L i PTCSIRXD2 m 1 e 1 R73 PTGO KBIPO 53 4 GPIO1 0 32 SE H GPIOZ 02V 37 PTDO ADP8 ACMP PTG2 KBIPS 39 H E PTD1 ADP9 ACMP PTG3 KBIP7 LAT XTAL JM60 E 1 Se 37 PTD2 KBIP2 ACMPO PTGA XTAL 43 EXTA uer H L S prov PTGS EXTAL I ete H 1 1 gt IROMPMOLK Z vuspas Hi E 1 BDM Programmer EE Al RESET o USBDN 19 USEDN ER I use PWR 1 ces GONG 10 BKGDMS G 2 USBDP H OF fogo AUF 2928 1
3. PTB2 SPSCK2 ADP2 PTEG SPSCK1 Lag BSTDN D VDDOTPIN SNS 29 Eu ER 16 BSTDN Dr R45 Ii 30 PIB3 SS2 ADP3 PTE7 SS1 H G Tang USBDP i 100 O WAL ajan anga ndah H H MCU SCL i pe SS Ma PrcolscL PTFOMTPM1CH2 E AH 67 PTCISDA PTF1 TPMICH3 1 Lo 1 otuF O tuF 46 5 HHB12V101R 10 7 PTC2 PTF4 TPM2CHO LS 1 1 va gt PTC3 TxD2 PTFS TPM2CH1 La 1 va ag PTOS PTFS n H 881 PTCS RxD2 22 H 1 el H R73 PTGO KBIPO 23 PTG1 KBIP1 aR 1 PA PAA E SE i 1 VVV gg PTD1 ADP9 ACMP PTG3 KBIP7 47 XTAL JM60 1 1 va RA 37 PTD2 KBIP2 ACMPO PTG4 XTAL css PTD7 PTGS EXTAL i 2 janin ka in is di a ja pj o rere LW 27 IRQ TPMCLK 4 VUsB33 Hg RST_JM60 1 BDM Programmer USB PWR va 5 Zd RESET 5 9 USBDN e USSDR C64 a ces 1 E 1 1 BKGD MS 8 USBDP bere rx 4TUF 932 0 1uF 2228 R51 R49 47K 1 5K I i MC9SOBJMBOCGTE leie HE H BKGD JM60 l RST_JM60 1 1 1 TE 1 HDR2X3 I gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 1 A e e e e e e e 2 2 e e e G e e e d ee AS RS I DV B Place on Bottom 1 Crystal H Boost Converter Place on Bottom l 1 2 1 bib I RAT TM 1 H 1 oo d 1 22UH 1 4 Vg 1 GND4 ato oe us a H FDN360P FDN360P MAX686 ba FDN360P H M 1 d VIN USB EXTAL JM60 1 L 2 2 33 y a 5 a pela po e amp 2
4. zu ma e N i KN Mo gt So aL SS A MI mones BS SIPSIPIN Figure 9 Key Test Point Locations and Default Voltages KTPF0200HWUG Rev 1 0 18 Freescale Semiconductor 9 6 Miscellaneous Components 9 6 1 Power on Push Button A footprint for a normally open momentary push button SW1 is provided at the PWRON pin to allow a momentary low state by pressing the push button J47 allows isolation of the PWRON pin from the MCU GPIO controlling this pin while J26 forces the PWRON pin to ground when closed JREDIG REREF RE REF OTP NO CONSUMER E Figure 10 Power on Circ VSNVS PWRON1 onp J47 2 foo 14 KPWRON HDR 1X2 TH 1 PWRON e 4 o HDR 1X2 TH gt RA R30 10 0K 10 0k 1 2 FSMSM a D J26 PVN PVN PVIN 2 Evaluation Board Configuration R32 10 0K Palang RESET MCU T REsETBMCU STANDBY1 Sou STANDBY ft TSTANDBY DWNB1 ln fa jo SDWN INT TSONG eh e INTB1 9 6 2 PMIC LED Indicators LED indicators are provided to notify the PMIC status to the user Figure 11 shows the PMIC status LEDs D2 D3 and D4 to monitor INTB PWRON and RESETBMCU signals respectively 5 ICTEST 0 R35 ICTEST ICTESTA L Song DNP NP KEAN EAR ERA CN ES SES 1 INTERRUPT SHUTDOWN RESET INDICATOR INDICATOR INDICATOR 1 i PVI
5. LX SWA3 E DNP i DNP ain 1 sw 1 coo 1 uH I T ZTE I E Bu 22UF SW3AFB gt sum ma I RIT I R16 H 0 001 1 0 001 DNP I swB3 LX swB3 ome e Dr 1 DNP i EES SW3BLX 3 een 2 NG BND 1 1 4 I 0 001 c32 033 DNP 22UF 22UF SW3BFB 3 Figure 15 KITPF0200EPEVBE Switching Regulators Schematic KTPF0200HWUG Rev 1 0 Freescale Semiconductor 25 Evaluation Board Schematic 0 I USB Connector Type A I H USB PWR CLOSED 2 3 1 I VIN_USB USB_PWR 339 PVN H 1 1 MAIN IC 000 1 1 C va Fi m i C58 el C59 H H I Cr rr H 0 5A 1a i HDR1X3 O uF Place on Bottom J34 E I USB MiniB gt gt VIN USB I u2 ar 3 I ra L11 24 i 9 VUSBEN L 1 1 PTAO us PTEO TXD1 HT BSTEN I HI1812V101R 10 DB pras PTEURXD1 L VPGMEN l va 8 PTE2 TPM1CHO 13 3V3EN H 1 a 12 SV3EN H a ES va 25 PTBOMISO2 ADPO 8 TEST 13 LGON i 1 v n LL ii PURON ZO PTB1MOSIZ ADP1 ud PTESIMOSI LS
6. Debug Port 3 Debugging connector for future development tools J44 STANDBY gt gt SDWNB RESETBMCU SWBST VDDIO MCU SCL MCU_SDA PVIN SWVIN HDR 2X10 DNP KTPF0200HWUG Rev 1 0 14 Freescale Semiconductor Evaluation Board Configuration 9 5 Debug and Configuration Components The KITPFO200EPEVBE allows full flexibility to change the default configuration of SW1A B and SW3AIB outputs to a more suitable configuration for a specific application It also provides several source options for the LDO supplies to test various loading and supplying scenarios Test point are provided on key nodes of the KITPF0200EPEVBE to allow full debugging capability during application development 1 SW1AIB Conti ion Compo 9 5 nfiguration ponents SWAB1 gt gt SW1AB e L2 R4 sto SWIALX 1 IBP l 4 tuH 0 001 C21 C22 c23 c24 2 R6 R7 pa SWIABFB LX SWA1 0 001 0 001 22UF z2UF 22UF 22UF _ SUB TB 2x1 DNP DNP L3 R8 cse x SW1BLX 1 2 NG AA a T L LX SWB1 i SE a DNP R9 R10 DNP for KITPF0200EPEVBE 1 oan 0 004 QNID en 1 1 DNP DNP an H L4 R11 H SW1CLX d e e 170 H 1 DNP 0 001 cos os S 22UF SW1CFB LX_SWC1 DNP The SW1A B regulator can be configured in various operating modes as described in Table 5 SUB_TB_2x1 DNP Figure 5 S
7. Rev 1 0 Freescale Semiconductor 21 Evaluation Board Configuration 9 7 Programming an External MMPF0200 Through J36 If the KITPF0200EPEVBE is used as an external programmer for either a customer board or a dedicated MMPF0200 programming socket J36 provides the required signals for such a task However it will be necessary to isolate the communication signals from the on board PMIC by doing the following 1 Remove all jumpers from J22 2 Remove all jumpers from J17 3 Remove all jumpers from J45 4 Remove jumper J47 Note If it is desired to perform One Time Programming of the MMPF0200 device soldered on the KITPF0200EPEVBE evaluation board ensure that the board hardware is correctly configured according to the chosen OTP settings The KITPF0200EPEVBE allows the configuration of the SW2 regulator or an external 3 3 V LDO output as the Vppio IZC pull up supply By default the SW2 regulator is the source for the Vppjo supply J46 3 4 If the SW2 regulator is to be set below 3 0 V then make sure the 3 3 V LDO output is connected to Vppjo and the 12C pull up resistors by changing J46 position to 1 2 KTPF0200HWUG Rev 1 0 22 Freescale Semiconductor Evaluation Board Schematic 10 Evaluation Board Schematic
8. co O e x e 09 o G o 00 o e O Q O It s Ng 000000000000 4 y Figure 20 Inner Layer 1 Routing KTPF0200HWUG Rev 1 0 30 Freescale Semiconductor KITPF0200EPEVBE Board Layout Inner Layer 2 Routing 11 5 Figure 21 Inner Layer 2 Routing Rev 1 0 31 Freescale Semiconductor KITPF0200EPEVBE Board Layout 11 6 Bottom Layer Routing VIA 8ch VS 0 NN o Sw CEL LEID z Figure 22 Bottom sali r Routing KTPF0200HWUG Rev 1 0 32 Freescale Semiconductor 12 Bill of Materials Table 9 Bill of Materials 2 Bill of Materials Schematic m Item Qty Notes Label Value Description Part Number Manufacturer 1 1 0 BATI BATTERY LITHIUM 3 0V MS621F FL11E SII MICRO PARTS LTD 5 5 MAH 2 1 2 BAT2 HOLDER COIN CELL 6 8 MM SMT BK 879 MEMORY PROTECTION DEVICES INC 3 7 C1 C3 C5 C8 C9 CAP CER 4 7 uF 10 V 10 X5R C12 C13 0603 4 7 C2 C6 C10 C11 CAP CER 0 1 uF 10 V 10 X5R C14 C44 C45 0402 5 5 C4 C7 C19 C56 CAP CER 0 1 uF 10 V 10 X7R C77 0402 6 1 C15 CAP CER 0 01 uF 50 V 10 X7R 0402 7 14 C16 C21 C22 CAP CER 22 uF 10 V 20 X5R C25 C26 C27 0805 C28 C29 C30 C31 C32 C33 C82 C83 8 1 2 c17 CAP CER 1000 PF 50 V X7R 596 0402 9 1 C18 CAP CER 10 uF 10 V 10 X7R 0805 10 15 C20 C34 C38 CAP CER 2 2 uF 6 3 V 2096 X5R C42 C43 04
9. L 20 SWAIN 1 I 2 2 2 22 22 2 2 2 2 nnii RSVDS SW1VSSSNS 21 swax HOR 1X2 TH D RSVD6 1 ciosen SWAX 2 yy LX swedri D 46 SWBSTLX lo swin AT VIN SW2 25 nanaig SWBSTLX d SEET H T A E Dm IN swesrin 45 SUBSTIN AP DNP 1 wor nama Za Pr aus e was pt smese E til 1 a l 1 47uF 0AUF 3 E MBR120LSFT1G 0 001 I m rp unes 1 I D o NP C17 L 0 01UF 22UF 2 ES 1 DNP 5 2 1 O vw awpen SWBSTFB I me I 2 SWVIN 2190911 y 1 I LE Lom HDR 1X2 TH I 0 1UF 22UF H 1 12 R4 sto SWIALX 1 2 A d io H 1uH 0001 e 022 cz Jem pa R6 R7 UAE EN SW1ABFB 1 LX swat 0001 toot SUB TB 2x1 DNP re DNP SWIBLX 2 I CSWB1 q H DNP R9 DNP for KITPF0200EPEVBE S 1 I 0 001 ewe 1 H DNP La nm SWiCLX 1 2 1 Wi 1 1 T T SE D 1 DNP 0 001 C25 C26 1 1 1X SWC1 DNE Ed B SUB_TB_2x1 DNP DNP I EE 1 LX SW2 mem 1 DNP 1 15 1 SW2LX 1 2 10H T d T C27 28 22UF 22UF SW2FB TOYS ame PAPA e EI nai na 4 H 1 DNP for KITPFO200EPEVBE LX swa 1 DNP 16 1 1 SWALX 1 2 ee I 4 4 DNP e 1 1 SUB TB 2x1 1 H DNP D 2 2 2 2 4 D
10. ee COD VOO so S qn uc AR E um d ze e e E O 2 Sek NS E a a m SE VR e a 5 6 i E ou i V a eR79 Sa Q VGEN5 C7 Tee Ny o E PATE MOMS s m e suasi 8 Reed e 90919 E C C34 ee 1x swei e je e 1 an e R8 as Og C32 J4 z ee u sus E 000 ange 959 2 000 lt i 8 7 4 R85 R10 o 4460 e e 5 s ke ee eg E 010 e e ma C33 S H Ab se mm IS LX SWB3 i J39 SER VR KI ai MO ROT E co x So L4 R21 soil a TER 7 1 c26000 2 y Mm cl2 EH e VIN SWB3 5 T m e 2e E WW mm Y E 2 3 SCH H VIN VREFDDR1 a e e PES SWC1 m mo N 6 E VIN SWCl o e J7 e E 50 0 l cette SS 1 A C ces O DIOM E R67 NG C28 VIN sw2 EI R68 ES e ARC LIL ix d F1 Ze VIN SW4 EE E 9 S m Sy o i GND2 O ee R42 e e R45 e BO 2013 FREESCALE N M om OM H EH BH3 PLACE LABEL HERE Sw1C GND SWIAB GND Figure 3 Default Jumper Configuration Diagram KTPF0200HWUG Rev 1 0 PWRON STBY GND SW3A GND 10 Freescale Semiconductor Evaluation Board Configuration 9 2 Hardware Description The KITPF0200EPEVBE operates with a single power supply from 3 1 to 4 5 V and is controlled via USB with the help of an integrated USB I C communication bridge By applying the input voltage supply the KITPF0200EPEVBE will power up according to the default power up sequence described in the MMPF0200 datasheet For controlling the MMPF0200 device
11. 0 SMT 100 MIL 51 1 L1 IND PWR 2 2 uH 100 KHZ 2 0 A LPS3015 222ML COILCRAFT 20 SMT 52 1 L2 IND PWR 1 0 uH 100 kHz 6 0 A XAL4020 102MEC COILCRAFT 20 SMT 53 4 L3 L4 L5 L8 IND PWR 1 0 uH 3100 KHZ 2 4 A LPS4012 102NLC COILCRAFT 30 SMT 54 1 L6 IND PWR 1UH 1MHZ 2 0 A 30 VLS252010T 1RON TDK SMT 55 1 L7 IND PWR 1 0 uH 100 KHZ 2 65 A LPS5015 102MLC COILCRAFT 20 SMT 56 1 L9 IND FER 100 OHM 100 MHZ H11812V101R 10 LAIRD TECHNOLOGIES 8 0 A 25 SMD 1812 57 1 L10 IND PWR CHK 22 yH 1 0 KHZ 744773122 WURTH ELEKTRONIK 1 0 A 2096 SMD EISOS GMBH amp CO KG 58 1 L11 IND FER 100 OHM 100 MHZ HI1812V101R 10 LAIRD TECHNOLOGIES 8 0 A 25 SMD 1812 59 1 Q1 TRAN MOSFET DUALN amp P FDC6327C FAIRCHILD CHANNEL 2 5 V S SOT6 60 2 Q2 Q3 TRAN PMOS SW 120 MA 25 V FDV302P FAIRCHILD SOT23 61 3 Q5 Q6 Q10 TRAN PMOS SW 2 0 A30 V FDN360P FAIRCHILD SSOT3 62 2 Q8 Q9 TRAN NMOS 50 V 220 MA SOT 23 BSS138 FAIRCHILD 63 R1 R3 R4 R6 R8 RES 0 001 OHM 1 4 W 5 0805 LMI R001 5 0 ISABELLENHUTTE R16 HEUSLER GMBH amp CO KG 64 1 2 R2 RES MF 1 0 OHM 1 16 W 1 0402 65 5 Op R7 R9 R10 R17 RES 0 001 OHM 1 4 W 5 0805 LMI R001 5 0 ISABELLENHUTTE R70 HEUSLER GMBH amp CO KG 66 1 R11 RES MF 0 001 OHM 1 0 W 1 CSNL1206FT1L00 STACKPOLE 1206 ELECTRONICS 67 5 2 R20 R23 R24 RES MF ZERO OHM 1 10 W 1 R27 R86 0603 68 5 R21 R22 R25 RES MF ZERO OHM 1 10 W 1 R26 R85 0603 69 2 R28 R41 RES MF 1 0 M 1 16 W 1 0402 K
12. 02 11 1 C23 CAP CER 22 uF 10 V 20 X5R 0805 12 1 C24 CAP CER 22 uF 10 V 10 X7R 1210 13 2 C35 C41 CAP CER 4 7 uF 6 3 V 2096 X5R 0402 14 13 C36 C37 C39 CAP CER 10 uF 16 V 10 X7R 0805 15 9 C40 C48 C49 CAP CER 1 0 uF 10 V 1096 X5R C50 C51 C52 0402 C54 C84 C87 16 2 C46 C53 CAP CER 0 22 uF 16 V 10 X7R 0402 17 1 C47 CAP CER 0 47 uF 10 V 10 X7R 0402 18 1 2 C55 CAP CER 1 0 uF 10 V 10 X5R 0402 19 5 C57 C58 C62 CAP CER 0 1 uF 16 V 1096 X5R C63 C65 0402 KTPF0200HWUG Rev 1 0 Freescale Semiconductor 33 Bill of Materials Table 9 Bill of Materials Y continued Schematic T Item Qty Notes Label Value Description Part Number Manufacturer 20 1 C59 CAP TANT 10 pF 16 V 10 3216 18 21 3 C60 C61 C72 CAP CER 22 PF 25 V 5 COG 0402 22 11 C64 CAP CER 0 47 uF 16 V 10 X7R 0603 23 11 C66 CAP TANT 4 7 yF 10 V 10 3216 18 24 11 C71 CAP TANT ESR 0 600 OHMS 15 uF 25 V 10 3528 21 25 1 C73 CAP TANT 4 7 pF 25 V 10 3528 21 26 1 C74 CAP CER 0 1 pF 25 V 10 X5R 0402 27 JA C75 CAP CER 1 0 uF 25 V 10 X5R 0603 28 11 C76 CAP CER 0 1 uF 6 3 V 10 X7R 0402 29 2 C78 C86 CAP CER 470 PF 50 V 5 COG 0603 30 1 2 c79 CAP CER 2 2 uF 16 V 1096 X5R 0603 31 1 C80 CAP CER 1 0 uF 16 V 1096 X5R 0603 32 11 C81 CAP TANT ESR 1 800 OHMS 2 2 uF 10 V 10 3216 18 33 1 2 C85 CAP CER 2 2 pF 6
13. 2 3 VDDOTPIN 2 apa ida T BI I R76 ere 12 uo MBR130LSFT1G gt R56 E ET 12 MHz 1 D eli C71 100 ER 604K C74 470k RIT ceo H 1 15UF IEEE 8 R59 22PF 100k e 22PF 2078 Amt O tuF i 1UF I 1 VDDOTPIN SNS J I len ee sens ee ee d vussen 1 6 ra anant an aga adangu BSS138 100K r q 2 y ESD PROTECTION 1 5 g i VPGME 1 et i z ol 3 3 BSS138 ga ER 9 9 S 8 S ma N 5o So Bo Bo H 47K E 8 2 2 1 H Za 3 3 H H 8 3 3 8 D Ze 6 ia H l lt 1 1 LDO REGULATOR 3 3V Place on Bottom T7777 VIN USB ava us R cso 1 0UF a orl H SEN EN 4 Y ce J ADA 470PF 2 aub i MIC5205 DNP H VOUT 1 242 X R2 R1 1 3 3V H R2 VOUT 1 242 1 X R1 D LED INDICATORS Va Et i q t 4 1 T USB PWR USB PWR i lt s Dit 2 W LED Red 2 8 ES o I 1 4 R68 1 470 E 1 LRON Programming Interface 3V3 436 VDDOTPIN y shoot oF S ott MCU SCL MCU_SDA PWRON GPIO1 Es Tibo GPIO2 baad HDR 2x4 Figure 16 KITPF0200EPEVBE Control Programming Interface Schematic KTPF0200HWUG Rev 1 0 26 Freescale Semiconductor 11 KITPF0200EPEVBE Board Layout 11 1 Assembly
14. 3 V 20 X5R 0402 34 1 D1 DIODE SCH PWR RECT 1A 20 V MBR120LSFT1G ON SEMICONDUCTOR SMT 35 3 D2 D3 D11 LED RED SGL 30 MA 0603 SML LXFM0603SIC TR LUMEX 36 1 D4 LED DUAL GRN RED 30 MA SMT LTST C195KGJRKT LITE ON 37 4 D5 D6 D7 D8 DIODE TVS ESD PROT ULT LOW ESD9L5 0ST5G ON SEMICONDUCTOR CAP 5 5 4 V SOD 923 38 1 D9 DIODE SCH PWR RECT 1A 30 V MBR130LSFT1G ON SEMICONDUCTOR SOD 123 39 11 D10 LED GRN SGL 30 MA SMT 0603 SML LXFM0603SUGCTR LUMEX 40 JA F1 FUSE PLYSW 0 5 A 13 2 V SMT MICROSMDO50F 2 RAYCHEM 41 56 e i TEST POINT RED 40 MIL DRILL 180 MIL TH 109L 42 14 J1 J2 J3 J4 J5 J6 HDR 1X2 TH 100 MIL SP 339H AU J7 J9 J24 J26 118L J27 J40 J41 J47 43 9 J8 J10 J11 J12 SUBASSEMBLY CON 1X2 TB TH J13 J14 J15 J31 3 81 MM SP 201H 138L TERM J33 BLOCK PLUG 3 81MM 2POS KTPF0200HWUG Rev 1 0 34 Freescale Semiconductor Table 9 Bill of Materials continued Bill of Materials Schematic ds Item Qty Notes Label Value Description Part Number Manufacturer 44 7 J16 J18 J19 J21 SUBASSEMBLY CON 1X3 TB TH J25 J29 J32 3 81 MM SP 201H 138L TERM BLOCK PLUG 3 81MM 3POS 45 2 J17 J35 HDR 2X3 TH 100 MIL 46 3 J20 J22 J39 HDR 1X3 TH 100 MIL 47 2 J46 J45 HDR 2x2 TH 100 MIL 48 1 J34 CON 5 USB MINI B RA SHLD SKT 675031340 MOLEX SMT 31 MIL SP AU 49 1 J36 HDR 2X4 TH 100 MIL 50 3 2 1042 J43 J44 HDR 2X1
15. 9 200 OHM 200 OHM ala z El FDC6327C lt lt K 4 Ha Red K 4 LED Red iS x o pem ern EEN 42 i Ho swic 2 1 swic oo 2 Loo VGEN1 STANDBY y PWRON i o o 1 Lo o VGEN2 INTB SW1AB Loot WIAB 1 515613 VGEN3 t SDWNB A loo e A 1 tooth VGEN4 EI RESETBMCU sw 810049 5554 122211 12 basch ji LUPI loo VGENS VDDIO swz Go o 29 2 Lo o VGENG MCU SCL SW3B QE too Sswas 87297 6 MCU_SDA 20 1 9 9148 1 Loot VSNVS PVIN SW3A oo W3A 1 201904 VREFDDR 29 SWIN 28 CON 2X10 4 CON 2x10 CON 2X10 p pe Kaer M HI LDO Terminal Blocks 4 I Interface Terminal Blocks 1 I2C Terminal Blocks J29 E b 3 va 1 NG SUB TB 2x1 J16 ING ALO 1 J31 SDWNB 219 RESETEMCUS y 1 musa il i ot H MCU_SD o SUBASSY TB 3x1 SUBASSY TB 3x1 I SU TB 433 18 1 STANDBY A VDDO 1 yoo ELT L3 o 1r me 13 GND va fol 4 3 o 1 M i SUB TB 2x1 SUBASSY_TB_3x1 SUBASSY TB SK 1 i n9 H D SE VGENS 1 imn I een Yen sfo 0 t i FE HOT PLUG WORKAROUND LEGACY TB 3x d J21 i PVIN ur 1 s H me 2 ES i RB 40 1 5 VREFDDR CE to
16. 94 1 U4 IC DAC CTRL BOOST INV MAX686EEE MAXIM 27 5 V 2 7 5 5 V QSOP16 95 2 U5 U7 IC LIN VREG LDO 1 5 15V 150 MA MIC5205YM5 MICREL 2 5 16 V SOT23 5 96 1 Y1 XTAL 12 MHZ SER 9 0 PF SMT ECS 120 9 42X CKM TR ECS INC INTERNATIONAL Notes 1 For critical components it is recommended to use the manufacturer listed 2 Do not populate 3 Freescale does not assume liability endorse or warrant components from external manufacturers that are referenced in circuit drawings or tables While Freescale offers component recommendations in this configuration it is the customer s responsibility to validate their application KTPF0200HWUG Rev 1 0 36 Freescale Semiconductor 13 References References Document Number Description URL MMPF0200 Data Sheet http cache freescale com files analog doc data sheet MMPF0200 pdf MMPF0200ER Errata http cache freescale com files analog doc errata MMPF0200ER pdf PFSERIESFS Fact Sheet http cache freescale com files analog doc fact_sheet PFSeriesFS pdf AN4622 Layout Application Note http cache freescale com files analog doc app_note AN4622 pdf KTPFSWUG4 Software User Guide http cache freescale com files analog doc user_guide KTPFSWUG4 pdf Product Summary Page http www freescale com webapp sps site prod_summary jsp code MMPF0200 Tool Summary Page http www freescale com webapp sps site prod_summary jsp code KITPFO200EPEVBE Analog Home P
17. Freescale Semiconductor Document Number KTPF0200HWUG User s Guide Rev 1 0 2 2014 KITPF0200EPEVBE Evaluation Board Featuring the MMPF0200 12 Channel Configurable PMIC Figure 1 KITPF0200EPEVBE Evaluation Board Contents RI Contes Patang List ud aad org d REA dA ERR RE dole d d Rode K A dedo DAA PARA dob aug ia 2 PAN SIME aaa teniti PAA Rad d rg de Cad qp AA AA 2 e driportanb NOIE ri te psi k aks darias 3 A E RECOGE Here RI Mes PREIS RAP e RI Kb 4 hn Evasion Board PORN AAA ARAR AL A AR LR AER KR ALEK E E B KAERRA RAL K 5 6 MMPF0200NPAEP Device Features ius cc naa ks EELER SR E On KO EAR Re p RO EG X Re Rep X ANDA apk 7 TMC SSG INGO Device Features aursiesseseRbsceRERIERENIPPREGGQHEREOSRRE QHRePRG P NE Rede FERE NAGANA 7 S Required EQURMaN E Gave a pe es LEE SOS e UKG a a BA S Ari die d 8 9 Evaluation Board ETIKA rai 9 10 Evaluation Board BEE 23 11 BITPF ZDOEPEVBE Boato EE EE 27 T2 BUT MATANG aa baana ken BE GER RARE Rid BARA WOE T E i ad a PAGKA RA Ru ET 33 RCC LINCE AAN 37 EN MODE ossadas EE Par re Pek AE 38 O Freescale Semiconductor Inc 2014 All rights reserved freescale P Kit Contents Packing List 1 Kit Contents Packing List KITPF0200EPEVBE evaluation board KITPF0200QSG Quick Start Guide Warranty card and Technical support brochure 2 Jump Start Goto www freescale com analogtools Locate your kit Review your Tool Summary Page Look for Pal Jump Start Your Design Downlo
18. H od 7 q pre 9 3 SWVIN os 9 croseo O prosep I VIN3 VIN3 VCOREDIG PVIN DNP Cam T DR 1x2 TH Pip 1x2 H NITA took I GND 1 i SUBASSY_TB_3x1 1 i 1 CONTROL LOGIC N3 VIN PWRON1 M E Son VSNVS 1 2 3 CLOSED i J22 J47 1 a R28 foo KPWRON FOR t3 HDR 1X2 TH 126 PVIN PVN PVIN 1 1M loo i VIN SENSE1 USA HDR 1X2 TH R31 R309 R32 VCOREDIG1 vcorenie Sr vin 56 1 2 FSMSM M Sa ss e RI VCOREDIG PWRON fe o o SWI I DNP 1 DNP p ycorerert VCOREREF 82 COREREF RESET mcu L ESETBMCU i Ze DNP VCORE1 VCORE 48 VCORE Paa S L Synesereucu STANDBY1 DNP t lt NP 2051 2 052 t C53 2054 D 48 GNDREF sown L ey L jSDWNB1 3 4 CLOSED tour 1 0UF 0 22uF 1 0UF 1 sowne Cone eli INTB1 I MB T VDDOTP VDDOTP 47 INT t INTA One i d 10072 E Vie VDDOTP 47 vpporp CSR a VSNVS 1 Z 00 d ser vobio Y HRZ C55 C56 45 Bio ICTEST R35 10UF C aM des ifoga sa ICTEST Za 1 DNP 04UF HS ESA bad CTEST1 E Hs 53 z 324 SDA B L GE CONSUMER dd 19 i SDA1 3 DNP R36 R37 1 47K 2 Ame MIMRFP2QONPAEP STANDBY 1 VDDIO 2 087 R29 I 1 0UF gt 100k 1 1 1 1 L Figure 13 KITPF0200EPEVBE LDO Control Schematic Part 1 KTPF0200HWUG Rev 1 0 Freescale Semiconductor 23 Evaluation Board Schematic INTERRUPT SHUTDOWN RESET INDICATOR INDICATOR INDICATOR PVIN Z PVN PVIN Y Y Fovso2P FDV302P Ang Q3 El lt pi pa R69 R40 200 OHM 200 OHM kah S D4 LED RED GRN R38 R3
19. Layer Top BH2 J25 T J3T 1 333 1 p2J8 12 J29 1 HA m 1 1 AT 3 o a R36 03 gre poe D ST LE lt per Gi s d a mm EEO Jao J27 R37 RR 5 E 8 o o RESETBMCU1 VIN SENSE1 puna 5 s a eg I ee J41 TE J17 Do O euer noo OO c83 1 o o ase E 1002 00 Tr J46 L O icresn eiie HI O O J1 LX SWAT m Li s or m 000 VINLSWAI WHHn25 eeR79 Soo EW ER C77e0 e e N C43 L7 dees 2 swasi e ao VEER oe e Cs 28 oo Lx swei 9 Je o R8 2 o 00 VIN sw5 Em 900 93 446 O 03 SND4 bio deso 2 E 2 o e x 82 a m L8 J39 c25000 0 oll o R26 R27 5 L4 R21 kol Ka J35 via c26000 5 Mm C12 35g 82 e mor DO ian ie JO see 2 SCH kn N VIN2 00 Lj ec O vn sa 9 e 2 J1 gand dy Tg comes Jo AR ROMS vu O DION M eeR67 o E on E O D11 EH eenoa J5 ARC L11 1 Figure 17 Assembly Top Layer KTPF0200HWUG Rev 1 0 KITPF0200EPEVBE Board Layout 006c COMS OOOOOOO BH4 BAT1 lt e m z a VGENS VIN_SWA3 VIN SWB3 VREFDDR1 VGEN4 c VINREFDDR1 GK VHALF1 VGEN3 Freescale Semiconductor 27 KITPF0200EPEVBE Board Layout 11 2 Assembly Layer Bottom III o D O BH2 J32 J8 J33 J31 J25 le gogdoggomu oo u E paa an lt 2 J27 J40 J26 J24 z 1 1 a O z m o O z S S m 9 v 3 o o 3 ze 22 1 o m e GND5 Z Avcorepigi
20. N mm PVIN BT S 7 T l S v Y Fovso2P FDV302P BN Q3 ah d 92 Ph R69 R40 200 OHM 200 OHM 1 o o 1 o E N D4 LED RED GRN I R38 R39 200 OHM 200 OHM Y 1 H 3 EIS FDC6327C al a s i Y LED Red Ka LED Red E d i x 3 1 o 1 i al H 1 Figure 11 PMIC Status Indicator KTPF0200HWUG Rev 1 0 Freescale Semiconductor 19 Evaluation Board Configuration Table 8 describes the meaning of the LED states Table 8 LED State Description LED Description D2 Interrupt Notification ON PMIC has detected an unmasked interrupt OFF No interrupt detected D4 RESETBMCU Notification Green PMIC is in regulation and operating properly Red PMIC is out of regulation D3 PWRON State ON PWRON pin is low OFF PWRON pin is high 9 6 3 Control Programming Interface This onboard USB to I C interface comprises three basic blocks 1 Controlling MCU MC9SO8JM60CGTE for USB I2C translation 2 3 3 V LDO supply for external device controlling 3 8 25 V boost converter for OTP programming The control programming interface allows one to program the onboard MMPF0200 PMIC Alternatively the interface can serve as a programmer for external devices though the connector J36 KTPF0200HWUG Rev 1 0 20 Freescale Semiconductor Evaluation Board Configuration
21. NP VIN3 40 26 VGEN3 C38 2 2UF DNP VGEN3 E VIN SA AS VIN3 VGEN3 VOEN 1 Voens YEN VREFDDR R25 28 VGEN4 J amp 7uF sue L MY IX iz WEE VGENS aan DNP VGEN4 pan 39 VGENS C42 22UF VGEN4 _ tour VGENS VGENG 1 k e 31 41 VGEN6 C43 DNP VGENS SW3A gt y R26 VREFDDR voe 3 2 20F voens q VGENS da N TE 30 q ag VINREFDDR O SA R27 DNP VINREFDDRT T 42 DNP VGEN6 2 cA DNP GEL T m VGENG q VGENG cas OAUF EURE VSNVS R86 10UF VHALFT e T 0 Ho 1 2 a DNP VSNVS1 DNP sia 38 DNP C46 21 ci seo BAT1 vsnvs lt YSNVS 5 SNVS 0220F 35 04UF E A MMPFO200NPAEP AMETS PE paak S 6 8mm Leaded el Place Top ale TU Bam al KR Place Bottom DNP Figure 7 LDO Schematic Configuration KTPF0200HWUG Rev 1 0 16 Freescale Semiconductor Evaluation Board Configuration N3 VIN WRON1 H Y as o VSNVS J22 347 H 0900 R28 Leio Kwon 1 lalo DR 1X3 HDR 1X2 TH 1 BO PVIN PVN PVN M 00 1 VIN SENSE1 ua FIDR 1X2 TH R3 gt R309 R3 50 Yn 10 0k 10 0k 10 0k ka e copie VCOREDIG B VIN TIRES to 92 psu DNP VCOREREF1 VCOREREF 52 3 RESETBMCU1 p EH VCOREREF RESET MCU t SET ka VDDIO1 DNP gvcoRE1 VCORE 49 m STANDBYI Si E651 35052 2 css 2 054 48 Mae d 2 SE SDWNB1 1 3 4 CLO
22. Rot 1 2226 H 1 47K MCSSOBJMOCGTE sss H H BKGD JM60 D D 1 RST Aen E E q D H 8V Boost Converter Place on Bottom 1 H H i va 1 Lo 1 Rat TM 1 2 ma vi 1 I ato os ww UM os Lan spe FDN360P FDN360P MAX686 HA FDN360P H XTAL_JM60 E C a q i 1 VIN USB 2 33 a los xeda pp e 5 S x 2 2 3 VDDOTPIN I al ag vos EA R76 NH Az ec MBR130LSFT1G WW na 7 ENE 1 470K 9 Reo va C81 D els c71 100 D c74 470K RIT Tg tur ISET pacour E 100K 1 1 c75 Our H H 1UF t FB VDDOTPIN SNS Y 1 a NC S mm EE pp UP POK DN ESD PROTECTION POL o REF H z 1 8 c E d e BSS138 1 ER 93 S H bo bo The boards are reworked lz 2 I 1 to connect pin 2 of Q9 H a 8 1 to ground as 1 2 2 4 LDO REGULATOR 3 3V Place on Bottom LED INDICATORS Programming Interface VIN USB A E m Dir IN our USB PWR VDDOTPIN 7 15012 EN 215914 AS C78 470PF GND HDR 2X4 MIC5205 0 1 242 X R2 R1 1 3 3V R2 VOUT 1 242 1 X R1 4 S S d LED Green Figure 12 Control Programming Interface Schematic KTPF0200HWUG
23. SED 1 0UF 1 0UF 0 22uF 1 0UF EH SORRE SH TSONG 2 95v 46 mH 4 qu KI 5 1 VDDOTP VDDOTP 47 ppoTP Tne Bou ro SIC 55 VSNVS 1 E 3150 Te VDDIO Y exu Y WIB C55 C56 pas DNP 5 ICTEST 0 R35 ales ICTEST 1 0UF MCU_SCL 1Lool2 Sic E H DNP 0 1UF MGU SD L Zee u ICTEST1 5 Ac HUE 7 Consumer d lo SDA1 Z L DNP R36 R37 47K an MMPPO2DONPAEP STANDBY VDDIO 2 ce7 R29 1 0UF S 100k Figure 8 Logic and Core Supplies Schematic Table 7 LDO Input Supply Configuration Chart Input Pin Input options VIN1 Input supply for VGEN1 and VGEN2 R20 External 3 3 V Supply R21 SW2 VIN2 Input supply for VGEN3 and VGEN4 R24 External 3 3 V Supply R22 SW2 VIN3 Input supply for VGEN5 and VGEN6 R23 VIN R25 SW2 VINREFDDR VREFDDR input supply R26 SW3A R27 SW3B 1 Make sure to populate only one option per input pin to avoid shorts between various sources KTPF0200HWUG Rev 1 0 Freescale Semiconductor 17 EST Evaluation Board Configuration 9 5 4 Test Point All test points are clearly marked on the KITPF0200EPEVBE evaluation board Figure 9 shows the location of various test points of interest during evaluation VDDIO INTB SDWNB RESETBMCU STANDBY VCOREREF 1 2V VCOREDIG 1 5V VCORE 2 8V PWRON VSNVS Je SWBST VDDOTP SW1AB e wy VREFDDR VGEN4 SD SOP DNS B E 7
24. TPF0200HWUG Rev 1 0 Freescale Semiconductor 35 Bill of Materials Table 9 Bill of Materials Y continued Schematic T Item Qty Notes Label Value Description Part Number Manufacturer 70 2 R29 R79 RES MF 100 K 1 16 W 596 0402 71 3 R30 R31 R32 RES MF 10 0 K 1 16W 196 0402 72 3 R35 R73 R74 RES MF ZERO OHM 1 10 W 0402 73 l4 R36 R37 R50 R51 RES MF 4 70 K 1 16 W 196 0402 74 l4 R38 R39 R40 R69 RES MF 200 OHM 1 10 W 196 0402 75 2 R42 R45 RES MF 33 0 OHM 1 16 W 196 0402 76 2 2 R48 R49 RES MF 1 5K 1 16 W 596 0402 77 1 R55 RES MF 100 OHM 1 10 W 196 0603 78 1 R56 RES MF 604 K 1 16 W 196 0402 79 1 R59 RES MF 374 K 1 16 W 196 0402 80 2 R60 R76 RES MF 470 K 1 16 W 196 0402 81 1 R61 RES MF 120 K 1 16 W 196 0402 82 l3 R63 R64 R65 RES MF 10 K 1 16 W 596 0402 83 2 R66 R75 RES MF 47 K 1 16 W 196 0402 84 2 R67 R68 RES MF 470 OHM 1 16 W 196 0402 85 1 R71 RES MF 20K 1 10 W 5 0603 86 1 R72 RES MF 12 0K 1 10 W 1 0603 87 2 R77 R78 RES MF 100 K 1 16 W 196 0402 88 1 R80 RES MF 27 K 1 16 W 5 0402 89 1 R81 RES MF 470 K 1 16 W 596 0402 90 3 2 R82 R83 R84 RES MF ZERO OHM 1 10 W 0402 91 1 2 swi SW SPST PB 12 V 50 MA SMT 92 1 U1 IC POWER MANAGEMENT MMPF0200NPEP FREESCALE CONSUMER INDUSTRIAL QFN56 SEMICONDUCTOR 93 1 U2 IC MCU 8BIT 48 MHZ 60 KB MC9S08JM60CGT FREESCALE FLASH 2 7 5 5 V QFN48 SEMICONDUCTOR
25. W1A B C Output Configuration Table 5 SW1AB Configuration Chart Component SW1A B Single phase SW1A B Dual phase R6 Closed DNP R4 Closed Closed R7 DNP Closed R8 DNP Closed L2 1 0 uH 1 0 uH ISAT 4 5 A ISAT 2 4 A L3 N A 1 0 uH ISAT 2 4 A L4 RESERVED RESERVED R9 RESERVED RESERVED R11 RESERVED RESERVED R10 RESERVED RESERVED KTPF0200HWUG Rev 1 0 Freescale Semiconductor Evaluation Board Configuration 9 5 2 SW3A B Configuration Components by SWB3 D N Ke DNP Figure 6 SW3A B Output Configuration The SW3AIB regulator can be configured in various operating modes as described in Table 6 Table 6 SW3ABC Configuration Chart COmponent SW3A B SW3A B SW3A Independent p Single phase Dual phase SW3B Independent R16 Closed DNP DNP R17 Closed Closed DNP R70 DNP Closed Closed L7 1 0 uH 1 0 uH 1 0 uH ISAT 3 9A ISAT 3 0 A ISAT 3 0 A L8 N A 1 0 uH 1 0 uH ISAT 3 0 A ISAT 3 0 A 9 5 3 LDO Input Supply Source Selection LDO SUPPLIES VGEN SENSE ava BEE DNP sw IA 21 wis DNP VGEN1 VGEN1 veeni lt VGEN1 R24 DNP MINA 47 16 VGEN1 C34 2 2UF ava gt bu VIN1 VGEN1 VGENZ DNP VGEN2 me GA AR L VIN2 27 mo vane LN Yene HI Ve q VGEN2 VREFDDR1 R23 D
26. able 1 provides a list of all available versions of this board and the respective software compatibility and marking differences The hardware configuration outlined in this document is valid for layout REV D and schematic Rev D Table 1 Board Deviation Summary Layout Hardware Board Name Revision deviations Software Version Software User Guide 170 27458 KITPFO200EPEVBE Rev D KITPFGUI 4 0 release 4 0 0 x Refer to Document KTPFSWUGA pdf KTPF0200HWUG Rev 1 0 Freescale Semiconductor Evaluation Board Features Layout Revision printed in Copper 630167 00006 47 TOP amp FT a Pa 02 coos BOT d PL a MB SCH 28014 REV D oBnoon 700 28014 REV D P KTPF0200HWUG Rev 1 0 6 Freescale Semiconductor MMPF0200NPAEP Device Features 6 MMPF0200NPAEP Device Features The MMPF0200 is highly integrated power management IC ideally suited i MX 6 series of applications processors It features the following Four buck regulators Boost regulator to 5 0 V output Six general purpose linear regulators e Programmable output voltage sequence and timing OTP One Time Programmable memory for device configuration Coin cell charger and RTC supply DDR termination reference voltage Power control logic with processor interface and event detection Freescale analog ICs are manufactured using the SMARTMOS process a combinational BICMOS manufac
27. ad documents software and other information KTPF0200HWUG Rev 1 0 Freescale Semiconductor Important Notice 3 Important Notice Freescale provides the enclosed product s under the following conditions This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY It is provided as a sample IC pre soldered to a printed circuit board to make it easier to access inputs outputs and supply terminals This EVB may be used with any development system or other source of I O signals by simply connecting it to the host MCU or computer board via off the shelf cables This EVB is not a Reference Design and is not intended to represent a final design recommendation for any particular application Final device in an application will be heavily dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering transient suppression and UO signal quality The goods provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety measures typically found in the end product incorporating the goods Due to the open construction of the product itis the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge In order to minimize risks associated with the customers applications adequate design and operating safeguards must be provided by the
28. age www freescale com analog Power Management Home Page www freescale com PMIC 13 4 Support Visit Freescale com support for a list of phone numbers within your region 13 2 Warranty Visit Freescale com warranty for a list of phone numbers within your region KTPF0200HWUG Rev 1 0 Freescale Semiconductor 37 Revision History 14 Revision History Revision Date Description of Changes 1 0 2 2014 Initial release KTPF0200HWUG Rev 1 0 38 Freescale Semiconductor How to Reach Us Home Page freescale com Web Support freescale com support VRoHS Information in this document is provided solely to enable system and software implementers to use Freescale products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document Freescale reserves the right to make changes without further notice to any products herein Freescale makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation conseguential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do v
29. ary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address freescale com SalesTermsandConditions Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off SMARTMOS is a trademark of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2014 Freescale Semiconductor Inc Document Number KTPF0200HWUG Rev 1 0 2 2014 p Po freescale
30. customer to minimize inherent or procedural hazards For any safety concerns contact Freescale sales and technical support services Should this evaluation kit not meet the specifications indicated in the kit it may be returned within 30 days from the date of delivery and will be replaced by a new kit Freescale reserves the right to make changes without further notice to any products herein Freescale makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications and actual performance may vary over time All operating parameters including Typical must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur Should the Buyer purchase or use Freescale products for any such unin
31. he control interface 9 4 Connectors and Terminal Blocks Description Table 3 Terminal Blocks descriptions Connector Function Pin definition J8 SWBST Pin 1 SWBST Output Pin 2 GND J10 SW1AB Pin 1 SW1AB Output Pin 2 GND J11 Not Available Reserved for board compatibility J12 SW2 Pin 1 SW2 Output Pin 2 GND J13 Not Available Reserved for board compatibility J14 SW3A Pin 1 SW3A Output Pin 2 GND J15 SW3B Pin 1 SW3B Output Pin 2 GND J16 VGEN1 VGEN2 Pin 1 VGEN1 Output Pin 2 GND Pin 3 VGEN2 Output J18 VGEN3 VGEN4 Pin 1 VGEN3 Output Pin 2 GND Pin 3 VGEN4 Output J19 VGEN5 VGEN6 Pin 1 VGEN5 Output Pin 2 GND Pin 3 VGEN6 Output J21 VSNVS VREFDDR Pin 1 VSNVS Output Pin 2 GND Pin 3 VREFDDR Output J25 Main Input Supply Pin 1 GND Pin 2 PVIN Pin 3 SWVIN J29 Interfacing 1 Pin 1 INTB Pin 2 SDWNB Pin 3 RESETBMCU J32 Interfacing 2 Pin 1 STANDBY Pin 2 PWRON Pin 3 GND KTPF0200HWUG Rev 1 0 12 Freescale Semiconductor Table 3 Terminal Blocks descriptions continued Evaluation Board Configuration Connector Function Pin definition J31 IC Signals Pin 1 SCL Pin 2 SDA J33 VDDIO Pin 1 VDDIO Pin 2 GND SWBST Output RESETBMCU VDDIO SDWNB PC Interface SEN Vin Supply Input PE STANDBY INTB State Indicator PWRON State Indicator VREFDDR Output VSNVS Output VGEN6 Output VGEN5 Output VGEN4 O
32. l 1 i SUBASSY_TB_3x1 LI css va 470PF DNP MIC5205 1 I DNP D X ar EE NG PP AA PAA AA APA tds Mounting Holes GND s DNP BH1 BH2 BH3 BH4 GND1 GND2 GND3 GND4 GND5 GND6 DNP DNP DNP DNP DNP Figure 14 KITPF0200EPEVBE LDO Control Schematic Part 2 KTPF0200HWUG Rev 1 0 24 Freescale Semiconductor Evaluation Board Schematic pp cessou em e m m no em e e m mee 2 22 2 2 2 2 cuoseD swan 1t VIN SWAT wig CLOSED H 2 1 VIN SWA3 SWIN 1 00 Dil 1 Cz T MMPF0200NPAEP T DNP o J2 k a H l WOR mo ms o 2 os AWET OAUF SWIABFB A LA anta swara 39 SW3AEB R I i HOR 1X2 TH 1 CLOSED LA awan SAINZ 0 1UF DO i Se s VIN_SWB1 SWIAX 8 swtALX saa 36 SWaALX 1 2 1 00 1 1 CLOSED ea SWiBX 9 max Swap x 35 SW3BLX VIN SWB3 e ut Swin i 1 Lo SMBIN 10 waging swaein 44 SWSBIN oo f es 1 ST dE swiclx n swapre k MEBEB O HOR 1X2 TH H 45 Smax 1 navo Ka ig VIN SWC1 1 2 1 SWICN 12 32 I oo TONE co 00 RSVD2 SW3VSSSNS a CLOSED l SWICFB 13 H HDR1X2TH AWET 04UE Rays 39 swar8 sch SWVIN l DNP DNP RSVD4 1 Ka Ho o
33. m gt LO 2 D 9 c SC mo 10 O vss O O80 o oi 000 0000 er m LX SWBST1 J43 J2 J20 J9 STANDBY1 20 19 a O o O O O vswesTi oom o og J17 mm mm VIN SWBST1 on o O O a J46 O GND6 2 o D 1 E u 1 o m c onis on ICTEST1 00 mm mo VGEN6 00 ooo O soos ES lt lt r O VGEN5 G e uh qu EH 2 mm mm O VIN SWA3Q 2 2 SWAB1Q Sea Ge LX SWA3 20 Jg E o SWA3Q Lx SWB1 O oo Ea ES 1 J4 o umm bl H os VIN_swB1 o0 1 O o LC NG GND4 80 01 2 1 O OLx swes a J36 2 2 J39 Ovin sWB3 y o 2 S m J35 Oo Z vit 200 a OVREFDDR1 po B 2 0 O Over y viNe uusap Mi 370 00 R ig L Ovin_zsw gt e e K O VHALF1 e 6 o o m K S gt fg vcen3 ke ke K GND2 2 0 N D J6 Q 1 1 1 1 1 1 OO DO DO DO Do D J14 J15 J12 J13 J10 J t 19 1 R760 C E 21 N TTT Figure 18 Assembly Layer Bottom KTPF0200HWUG Rev 1 0 28 Freescale Semiconductor KITPF0200EPEVBE Board Layout 11 3 Top Layer Routing TIN N 4 d o NG o o o Bo o o o o o LY A AO 4 M o E M NG y o 4 a S o o T o NA Figure 19 Top Layer Routing G Rev 1 0 29 Freescale Semiconductor KITPF0200EPEVBE Board Layout 11 4 Inner Layer 1 Routing o eo a A S k S 2 e 00800280280 30009500 o i o l a LAT o O O o sa o e w o 0000000 0000 CH a Add Die O 00 00 0 o E Ng OO DO
34. oard Configuration 9 Evaluation Board Configuration Connect the power supply and the USB communication cables as shown in Figure 2 Voltmeters are optional but they are recommended to accurately verify that each one of the output supplies provides the correct voltage level PC POWER SUPPLY PF0200 Evaluation Board MULTIMETER Figure 2 Evaluation Board Setup Note The KITPF0200EPEVBE allows the selection of an SW2 regulator output or an external 3 3 V LDO output as the Vppjo I2C pull up supply By default the SW2 regulator is the source for the Vppio supply J30 3 2 If the SW2 regulator is to be set below 3 0 V then make sure the 3 3 V LDO output is connected to Vppjo and the DC pull up resistors by removing R34 and R33 and the shorting pins 1 2 and 3 of J30 KTPF0200HWUG Rev 1 0 Freescale Semiconductor 9 Evaluation Board Configuration 9 1 Hardware Configuration By default the KITPFO200EPEVBE evaluation board is set to power up from the default power up sequence Verify that the jumpers are placed in the right position as shown in Figure 3 For a detailed description of the jumper functionality refer to Table 2 SWVIN PVIN GND SDA SCL GND VDDIO GND SWBST RSTMCU SDWNB INTB GND e e BH2 BH4 GND1 2 EBD 3 R39 39e Race eR69 Ig Ig SE 6 lt lt E or m omo 5 amp 13H 1H H SP Ch 8 8 a e e a d Ul VIN SENSEI VDDIOL SDAL 3 a amp
35. or programming the OTP registers refer to the KTPFSWUG4 PDF user guide Important notice If power up sequences and configuration are to be modified the user must ensure that the register settings are consistent with the hardware configuration This is most important for the buck regulators where the quantity size and value of the inductors depend on the configuration single dual phase or independent mode and the switching frequency Additionally if an LDO is powered by a buck regulator it will be gated by the buck regulator in the start up sequence Refer to the MMPF0200 Data Sheet for details on buck regulator setup 9 3 Jumper Description Table 2 KITPF0200EPEVBE Jumper Description Jumper Default Description J1 J7 Closed Buck regulators input power path isolation Short these jumpers to allow SWXIN to be powered from the SWVIN supply J9 Closed SWBST regulator input power path isolation Short this jumper to allow SWBSTIN to be powered from the SWVIN supply J17 5 6 VDDOTP Supply selector 1 2 Connect VDDOTP to the OTP Boost output VDDOTPIN for OTP programming 3 4 Connect VDDOTP to GND to power up from OTP TBB sequence 5 6 Connect VDDOTP to VCOREDIG to power up from Default Power up sequence J20 1 2 Coin cell selector 1 2 Enables BAT1 as the main coin cell supply 2 3 Enables BAT2 as the main coin cell supply J40 Closed Shorts PVIN and SWVIN Allows supply isolation to
36. ow the customer to program the OTP TBB One Time Programmable Try Before Buy memory and select it as the default source for the power up configuration Likewise the programming interface allows full control of the MMPF0200 through the 12 communication lines This document is intended to provide the hardware description of the KITPF0200EPEVBE evaluation board KTPF0200HWUG Rev 1 0 4 Freescale Semiconductor 5 Evaluation Board Features Input voltage operation range from 3 1 to 4 5 V Output voltage supplies accessible through detachable terminal blocks Three to four independent buck converters One 5 0 V boost regulator Six general purpose LDO regulators One DDR memory termination voltage reference One VSRTC supply Coin cell support for Try Before Buy TBB mode e On off push button support Evaluation Board Features Hardware configuration flexibility through various jumper headers and resistors Integrated USB to ke programming interface for full control configuration Onboard OTP programming supply and control Onboard PMIC control through the GC register map Fully featured programmer through J36 for external device control programming Onboard connectors for interfacing with future evaluation debug tools Compact form factor 4 x 4 in 5 1 Board Identification The KITPF0200EPEVBE evaluation board is designed to be used along with the KITPFGUI 4 0 Graphical User Interface T
37. provide more accurate efficiency readings on the switching supplies J41 Open Shorts SWVIN to VIN Allows one to isolate or connect the MMPF0200 logic input supply to SWVIN net debugging option J27 Closed Shorts PVIN to VIN Allows one to isolate or connect the MMPF0200 logic input supply to PVIN net debugging option J22 2 3 MMPF0200 input logic supply selector 1 2 Connects MMPF0200 VIN pin to the 3 3 V external LDO regulator for debugging purposes 2 3 Connects MMPF0200 VIN pin to the main input supply Refer to Figure 13 J26 Open Short to hold PWRON pin low J24 Open Short to pull STANDBY to VSNVS voltage supply J47 Close Connects PWRON pin on the MMPF0200 to an I O on the MCU J45 1 2 Allows I C signal isolation on the local MMPF0200 when the KITPF0200EPEVBE is used as 3 4 an external programmer KTPF0200HWUG Rev 1 0 Freescale Semiconductor 11 Evaluation Board Configuration Table 2 KITPF0200EPEVBE Jumper Description continued Jumper Default Description J46 3 4 VDDIO supply 2c pull up supply selector 1 2 Pull the SCL SDA signals to the external 3 3 V LDO regulator output 3 4 Pull the SCL SDA signals to SW2 output NOTE Do not connect both positions at the same time J39 1 2 Control Interface input supply selector 1 2 Enables PVIN node as the input supply source for the control interface 2 3 Enables USB power as the input supply source for t
38. tended or unauthorized application the Buyer shall indemnify and hold Freescale and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2014 KTPF0200HWUG Rev 1 0 Freescale Semiconductor 3 Introduction 4 Introduction The KITPF0200EPEVBE evaluation board allows full evaluation capability of the MMPF0200 PMIC for the i MX family of application processors It provides access to all output voltage rails as well as control and signal pins through terminal block connectors for an easier out of the box evaluation experience A single terminal block connector for the input power supply allows the user to supply the board with an external DC power supply to fully evaluate the performance of the device The KITPF0200EPEVBE comes with a non programmed version of the MMPF0200 PMIC and it is configured to power up from the default power up sequence However an integrated control fuse programming interface is provided to all
39. turing flow that integrates precision analog power functions and dense CMOS logic together on a single cost effective die 7 MC9508JM60 Device Features The KITPF0200EPEVBE implements a Freescale MC9508JM60 low cost high performance 8 bit HCS08 microcontroller to interface via USB to I2C to control the main PMIC 8 bit HCS08 Central Processing Unit CPU Up to 24 MHz internal bus 48 MHz HCS08 core frequency offering 2 7 to 5 5 V across temperature range of 40 to 85 C Support for up to 32 peripheral interrupt reset sources On Chip Memory Up to 60K flash read program erase over full operating voltage and temperature Upto4K RAM 256 Byte USB RAM KTPF0200HWUG Rev 1 0 Freescale Semiconductor 7 Required Equipment 8 Required Equipment 8 1 Hardware Requirements Power supply Output voltage range from 3 1 to 4 5 V Current capability from 3 0 to 5 0 A current requirement is dependent on output loading Supply to board connection cables capable of withstanding up to 5 0 A current USB male to mini USB male communication cable USB enabled computer e Multimeter 8 2 Software Requirements e Windows XP or Windows 7 operating system KITPFGUI 4 0 zip Graphical User Interface GUI for KITPF0200EPEVBE e Refer to document KTPFSWUG4 PDF located at Freescale com for detailed instruction on software installation and control KTPF0200HWUG Rev 1 0 8 Freescale Semiconductor Evaluation B
40. utput Device Attached VGEN3 Output Indicator OTP Programming Indicator Mini USB gt SW1AB Output L1 KITPF0200EPEVBE Figure 4 Input Output Terminal Blocks KTPF0200HWUG Rev 1 0 VGEN2 Output VGEN1 Output SW3A Output SW3B Output SW2 Output Freescale Semiconductor 13 Evaluation Board Configuration Table 4 Connector Description Connector J34 Function Mini USB connector Pin definition Pin 1 VBUS Pin 2 D Pin 3 D Pin 4 NC Pin 5 GND Chassis GND J35 BDM connector Pin 1 BKGD JM60 Pin 2 GND Pin 3 NC Pin 4 RST JM60 Pin 5 NC Pin 6 USB PWR J36 Programmer connector Pin 1 VDDOTPIN 8 5 V boost output Pin 2 3V3 3 3 V LDO output Pin 3 GND Pin 4 MCU SCL PC clock signal Pin 5 MCU SDA IC data signal Pin 6 PWRON Controls the PWRON on the target device Pin 7 GPIO 1 General Purpose GPIO Pin 8 GPIO 2 General Purpose GPIO J42 J43 Debug Port 1 Debug Port 2 Debugging connector for future development tools wc Loo 1 s c o w lt o0 syswias sw 2 ene SW2 a i Sc ap K oo 47 Ze swa lt 2 Lo o 19 Zenn HDR 2X10 DNP Debugging connector for future development tools 2 Laa 1 VGEN1 3 VGEN2 EES VGEN3 Ka VGEN4 oo VGENS Boot VGENG Lo o loo VsNvS VREFDDR HDR 2X10 DNP J44

KITPF0200EPEVBE, Evaluation Board - User Guide

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