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JESD204B IP Core User Guide

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1. UG 01142 2015 05 04 TX Data Transmission 5 17 Figure 5 4 TX Operation Behavior This figure shows the data transmission for a system configuration of LMF 112 N N 16 S 1 Operation e Upon the deassertion ofthe txframe_rst_n signal the jes d204 tx link early ready signal from the DLL to the transport layer is asserted some time later which activates the transport layer to start sampling the 3es 204 tx datain 15 0 signal from the Avalon ST interface e Each sampled 16 bit data is first written in a FIFO with a depth of four e Once the FIFO accumulates 32 bit data the data is streamed to the DLL accordingly through the jesd204 tx link datain 31 0 signal e Finally the jesa204 tx link early ready and jesd204 tx data ready signals deassert because the DLL has entered code group synchronization state in this scenario sees EL GRECE ey axe NE a ae a txframe rst n txlink rst n i i 1 l jesd204 tx data valid i d jesd204 tx link early ready jesd204 tx data ready jesd204 tx datain 15 0 m l E ETT eso jesd204 tx link data valid jesd204_tx_link_datain 31 0 alts area m aa TX Data Transmission This section explains the data transmission behavior when there is a valid TX data out from the TL to DLL Upon the d
2. TXFRAME_CLK TXLINK_CLK ATY_INT SYSREF SYNC_N JESD204 TX Transport Layer with Base and Transceiver Design Example M zm Transceiver TX Per Device Avalon MM Per Device TX CSR A To Avalon Yy Per Device y Interface CSR Bus 1 Avalon ST ni e ASI 32 Bit PCS aa TEE eassembly Per Channel 0 ar Per Device SHBISpENOIOTE b gt Scrambler H gt ps mA p PCS p and p Serial Interface JESD204B y TX Transceiver TX_n TX_p TX Per Device The transmitter block consists of the following modules Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 TX Data Link Layer 4 5 TX CSR manages the configuration and status registers TX_CTL manages the sync_n signal state machine that controls the data link layer states LMFC and also the deterministic latency throughout the link TX Scrambler and Data Link Layer takes in 32 bits of data that implements the Initial Lane Alignment Sequence ILAS performs scrambling lane insertion and frame alignment of characters TX Data Link Layer The JESD204B IP core TX data link layer includes three phases to establish a synchronized link Code Group Synchronization CGS Initial Lane Synchronization ILAS and User Data phase TX CGS The CGS phase is achieved through the following process TX ILAS
3. V JESD204B IP Core Duplex CSR PHY Transceiver Avalon MM Reconfiguration amp 9 pu ROM Controller Avalon MM i i Control Unit Clock MIF Avalon MM ROM Avalon MM Ie SPI Master PLL MIF JESD MIF ADC MIF DAC MIF ROM ROM ROM ROM A E 8 c al a ev E amp E E 2 S zz 2 Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 MIF ROM 5 51 Figure 5 20 Dynamic Reconfiguration Block Diagram For 20 nm Device Families Arria 10 JESD204B IP Core Duplex CSR PHY Avalon MM Avalon MM Control Unit buy MIE Clock MIE Avalon MM ROM ROM Avalon MM SP Master PLL MIF JESD MIF ADC MIF DAC MIF ROM ROM ROM ROM A c al l 2 E 2 S 2 gE 3 The MIF ROM content for maximum and downscale configuration e PLL MIF ROM contains the PLL counter charge pump and bandwidth setting e JESD MIF ROM contains the LMF information e PHY MIF ROM contains the transceiver channel and PLL setting e ADC MIF ROM contains the ADC converter setting DAC MIF ROM contains the DAC converter setting e CLK MIF ROM contains the device clock setting MIF ROM You need to generate two MIF files for each reconfigurable IP core as shown in Figure 5 20 or Figure 5 21 and merge them
4. FPGA Device JESD204B IP Core TX D SYSREF SYNC N DEV SYNC N MDEV SYNC N SYSREF Tied to 0 for Subclass 0 JESD204B IP Core TX p SYSREF eb DEV SYNC N MDEV SYNC N JESD204B IP Core TX SYNC N p SYSREF DEV_SYNC_N MDEV_SYNC_N DAC Reference Clock FPGA Reference Clock Clock Chip SYNC 1 Note 1 SYNC is not associated to SYNC N in the JESD204B specification SYNC refers to JESD204A Subclass 0 converter devices that may support synchronization via additional SYNC signalling For Subclass 1 implementation you may choose to combine or not to combine the sync_n signal from the converter device If you implement two ADC converter devices as a multipoint link and one of the converter is unable to link up the functional link will still operate You must manage the trace length for the sysREF signal and also the differential pair to minimize skew The svxc x is the direct signal from the DAC converters The error signaling from syNc_n is filtered and sent out as dev sync n output signal The dev sync n signal from the JESD204B TX IP core must loopback into the mdev sync n signal of the same instance without combining the sync_n signal Apart from that you must set the same RBD offset value csr_rbd_offset to all the JESD204B RX IP cores within the same multipoint link for the RBD release the latest lane arrival for each of the links The JESD204 RX IP core w
5. eal A Device Clock rx_sysref 3 i Pattern Checker 2 2 Transceiver Reset Controller Transceiver Reconfiguration Controller 11 tx_sysref rx_sysref Device Clock Clock and SYSREF M Control Unit CU i 10 ROM 1 Frame Clock Domain Management Clock Domain 100 MHz Management Clock 2 Link Clock Domain Device Clock Domain PLL 9 J PLL Reconfiguration f 11 Device Clock The list below describes the mechanism of the design example architecture with reference to the note numbers in the design example block diagram 1 For multiple links the JESD204B IP core is instantiated multiple times For example in 2x112 LMF configuration two cores are instantiated where each core is configured at LMF 112 2 The number of pattern generator or pattern checker instances is equivalent to the parameter value of LINK The data bus width per instance is equivalent to the value of FRAMECLK DIV M S N 9 3 The number of transport layer instances is equivalent to the parameter value of LINK The legal value of LINK is 1 and 2 The data bus width per instance is equivalent to the value of FRAMECLK DIV M S N U The test mode 0 signal indicates a normal operation mode where the assembler takes data from the Avalon ST source Otherwise the assembler takes data from the
6. I 4 8 REGOIVED n a a R A 4 8 RX Data Link Layf 4 9 RX PHY Layer M TERES 4 12 oce 4 13 Operating MOGs p 4 13 Altera Corporation JESD204B IP Core User Guide TOC 3 Serambler Descrambler T Q S 4 14 SYNC N Signal aorin PC M R 4 14 iba lir uro c 4 16 Link Startup Se TCO TEC 4 17 Error Reporting Through SYNC N SIEBAL s oq rintipin abate n ita ret det intus 4 18 Clocking Sehem PN 4 18 Device oo dem 4 20 liis 4 21 Local M lti Fram CIC e 4 22 Clock Correlati i M 4 23 Reset SCREMG T 4 24 house 4 25 Dor H P 4 26 fbcunulc e 4 27 RECEIVER sconti maei m EH ERHETR EAT HOO CREER ORE RT 4 36 zu 4 43 Register Access Type COBVEBEDOR usuris ikrt anke ede si kente peret etae ce qur enis a ssie 4 43 JESD204B IP Core Design Guidelines eee eene 5 1 JESD204B IP Core Design Exatmpleiusesecoset tri
7. Use Connections Name Description Export Clock Base End IRQ Auto Export E v Em clk Clock Source clk_in Clock Input clk exported EJ Dj clk_in_reset Reset Input reset clk in Bl cik Clock Output mgmt clk M clk reset Reset Output mgmt clk el E link clk Clock Source D clk_in Clock Input ick 0 exported v D4 clk_in_reset Reset Input reset cIk in 4 clk Clock Output link_clk x clk_reset Reset Output link_clk vl El mm master bfm Altera Avalon MM Master BFM clk Clock Input mgmtclk clk_reset Reset Input clk a mo Avalon Memory Mapped Master clk raj B jesd tx Jesd204b T nd txlink clk Clock Input link cIk gt txlink rst n Reset Input txlink_cik jesd204_tx_avs_clk Clock Input mgmt cik 1 1 jesd204 t1x avs rst n Reset Input jjesd204 tx avs cIk r x jesd204 tx avs Avalon Memory Mapped Slave jesd204 tx avs cIk 0 x0000 0000 0xOOOO O3ff D4 jesd204 tx link Avalon Streaming Sink jjesd tx jesd204 tx link txlink_cik ivi El atx pil Arria 10 Transceiver ATX PLL pll powerdown Conduit atx_pll_pll_powerdown iz all eee eed pll refclko Clock Input mgmt_cik oa pll_locked Conduit atx pli pil locked pli cal busy Conduit atx pll pil cal busy mcgb rst Conduit at lt _pll_mcgb_rst tx bonding clocks HSS Bonded Clock Output lel E phy rst ctrl Transceiver PHY Reset Controller Ll 9T clock Clock Input mgmt cik 9 9 reset Reset Input pll_powe
8. 0 0000000000000001 L 1 0000000000000001 M 2 0000000000000001 F 3 1111111111111111 End of MIF 4 7 0000000000000000 Downscale Configuration MIF 8 0000000000000000 L 9 z 0000000000000000 M 10 z 0000000000000001 F Altera Corporation maximum config downscale config JESD204B IP Core Design Guidelines C Send Feedback UG 01142 Generating and Simulating the Design Example 5 55 2015 05 04 11 1111111111111111 End of MIF 22 15 0000000000000000 END ADC DAC CLK The content for ADC DAC CLK MIF is vendor specific The general format for the MIF is as shown below with each section terminated by all 1 s Maximum Configuration MIF WIDT DEP H 32 H 128 ADDRESS RADIX UNS DATA RADIX BIN CONTENT BEGIN 0 10000100000000000001000001111100 Maximum Config 1 10000100000000000001010000000101 2 10000100000000000001011000000101 3 10000100000000000001110000000010 28 10000001000000001111111100000001 29 4 10000001000000000101111100010100 30 11111111111111111111111111111111 End of MIF 31 63 00000000000000000000000000000000 Downscale Configuration MIF 64 10000100000000000001000001111100 downscale config 65 10000100000000000001010000000101 66 10000100000000000001011000000101 67 10000100000000000001110000000010 92 10000001000000001111111100000001 93 100000010000000001011111
9. v Assert Link and Frame Transceiver Reset v SPI Reconfiguration v LMF Reconfiguration v PLL Reconfiguration v Transceiver Reconfiguration v Deassert Transceiver Reset v Clear tx err rx err and rx err status registers Deassert Link and Frame Reset v Reconfiguration Done UG 01142 2015 05 04 The control unit is a finite state machine FSM that works with multiple memory blocks ROMs Each ROM holds the configuration data required to configure the external converter or clock devices for each SPI slave A memory initialization file MIF contains the initial values for each address in the memory Each memory block requires a separate file The MIF can be created in the Quartus II software text editor tool Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Finite State Machine FSM 5 39 Figure 5 16 Example of MIF Format and Content MIF content for ADC WIDTH 24 the size of data in bits DEPTH 8 the size of memory in words ADDRESS RADIX UNS the radix for address values DATA RADIX BIN the radix for data values CONTENT BEGIN 0 000000000101111100010101 write 0x15 to link control 1 register Ox5F to disable the lane 1 000000000101111001000100 write 0x44 to quick config register 0x5E for L 4 M 4 2 000000000110010011000000 wr
10. jesd204 rx dlb data L Input Optional signal to indicate valid data for each byte valid in TX to RX loopback testing desee rx ee kebar Dp Input Optional signal to indicate the K character value catal for each byte in TX to RX loopback testing 09 jesd204_rx_dlb_ 1 4 Input Optional signal to indicate 8B 10B error 99 errdetect jesd204 rx dlb 1 4 Input Optional signal to indicate running disparity disperr 26 This signal is only for internal testing purposes Tie this signal to low Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Registers Registers 4 43 The JESD204B IP core supports a basic one clock cycle transaction bus There is no support for burst mode and wait state feature the avs_waitrequest signal is tied to 0 The JESD204B IP core Avalon MM slave interface has a data width of 32 bits and is implemented based on word addressing The Avalon MM slave interface does not support byte enable access Each write transfer has a write WaitTime of 0 cycle while a read transfer has a read WaitTime of 1 cycle and readLatency of 1 cycle The following HTML files list the TX and RX core registers The register address in the register map is written based on byte addressing The Qsys interconnect automatically converts from byte to word addressing You do not need to manually shift the address bus If the Avalon MM master interfaces to the IP core
11. Run Time Reconfiguration The JESD204B IP core supports run time reconfiguration for the LMF and data rate settings The design example only demonstrates the following set of configuration Transport Layer 0 JESD204B IP Duplex Core 0 LMF 112 Assembler iiic TX Base Core LMF 1125 1 Z LMF 112 S 1 gt N 16 N 16 Duplex SERDES PHY Deassembler is RX Base Core LMF 112 1 LMF 112 5 1 Transport Layer 1 JESD204B IP Duplex Core 1 LMF 112 Assembler E l TX Base Core LMF 112 5 1 H IMF 12 5 1 Py N 16 N 16 Duplex SERDES PHY Deassembler ma RX Base Core IMF 112 S 1 2 LMF 112 S 1 ke To generate the design example with run time reconfiguration enabled the LMF and bonding mode parameters must match the default value listed in the table below Table 5 20 Run time Reconfiguration Demonstrated By The Design Example Run time Reconfiguration LMF 222 112 FRAMECLK_DIV 2 2 Data Rate 6144 Mbps 3072 Mbps Link Clock 153 6 MHz 76 8 MHz Frame Clock 153 6 MHz 76 8 MHz Bonding Mode Non bonded Non bonded JESD204B IP Core Design Guidelines G Send Feedback Altera Corporation UG 01142 5 44 System Interface Signals 2015 05 04 System Interface Signals Table 5 21 Interface Signals Clock Direction Description Domain Clocks and Resets device elis Input Device clock signal from the external converter
12. Bonded Non bonded 1 8 1 1 307 2 153 6 4 Bonded Non bonded 1 8 2 1 307 2 153 6 4 Bonded Non bonded 1 8 4 1 307 2 153 6 4 Bonded Non bonded 8 4 153 6 Dynamic Reconfiguration Non bonded 2 p 153 6 153 6 153 6 The following figures show the datapath of single and multiple JESD204B links Figure 5 17 Datapath of A Single JESD204B Link Pattern Generator M 1 S 1 N 16 FRAMECLK_DIV 1 LINK 0 Pattern Checker M 1 S 1 N 16 FRAMECLK_DIV 1 Altera Corporation Duplex SERDES PHY Taf port Layero JESD2048 IP Duplex Core 0 LMF 211 ad Assembler m TX Base Core lt Wr 21 1 c LMF 211 5 1 gt N 16 N 16 Avalon ST Avalon ST E Deassembler M T RX Base Core MF 2115 1 _ LMF 211 S 1 N 16 N 16 JESD204B IP Core Design Guidelines CJ Send Feedback UG 01142 2015 05 04 Figure 5 18 Datapath of Multiple JESD204B Links LINK 0 LINK 1 Pattern Generator 0 M 1 S 1 N 16 FRAMECLK_DIV 1 Run Time Reconfiguration 5 43 Avalon ST 16 Pattern Checker 0 M 1 S 1 N 16 FRAMECLK_DIV 1 Avalon ST 16 Pattern Generator 1 M 1 S 1 N 16 FRAMECLK_DIV 1 Avalon ST 16 Pattern Checker 1 M 1 S 1 N 16 FRAMECLK_DIV 1 Avalon ST 16
13. Getting Started Altera Corporation GJ send Feedback 3 10 Compiling the JESD204B IP Core Design Table 3 3 Simulation Run Scripts ModelSim Altera example design directory lip sim testbench mentor UG 01142 2015 05 04 run altera jesd204 tb tcl SE AE VCS example design directory lip sim testbench synopsys vcs run altera jesd204 tb sh VCSMX example design directory lip sim testbench synopsys run altera jesd204 tb sh vcsmx Aldec Riviera example design directory lip sim testbench aldec run altera jesd204 tb tcl Cadence example design directory lip sim testbench cadence run altera jesd204 tb sh To simulate the testbench design using the ModelSim Altera or Aldec Riviera PRO simulator follow these steps 1 Launch the ModelSim Altera or Aldec Riviera PRO simulator 2 On the File menu click Change Directory gt Select example design directory ip sim testbench simulator name 3 On the File menu click Load gt Macro file Select run altera jes204 tb tcl This file compiles the design and runs the simulation automatically providing a pass fail indication on completion To simulate the testbench design using the VCS VCS MX in Linux or Cadence simulator follow these steps 1 Launch the VCS VCS MX or Cadence simulator 2 On the File menu click Change Directory gt Select example design directory lip sim testbench simulator name gt 3 Run the run a
14. e avst_usr_din 15 0 link0 m0 15 0 e avst_usr_din 31 16 link0 m1 15 0 e avst_usr_din 47 32 link1 m0 15 0 e avst_usr_din 63 48 link1 m1 15 0 Indicates whether the data from the Avalon ST source interface to the transport layer is valid or invalid e 0 data is invalid e 1 data is valid avst_usr_din_ready frame_ Output Indicates that the transport layer is ready to accept data from the Avalon ST source interface e 0 transport layer is not ready to receive data e 1 transport layer is ready to receive data JESD204B IP Core Design Guidelines CJ Send Feedback Altera Corporation 5 48 System Interface Signals UG 01142 2015 05 04 Clock Direction Description Domain avst_usr_ dout FRAMECLK_ DIV LINK M S N 1 0 avst usr dout valid frame clk frame_ Output Output RX data to the Avalon ST sink interface The transport layer arranges the data in a specific order as illustrated in the cases below Case 1 If F1 F2_FRAMECLK_DIV 1 LINK 1 M 1 S 1N 16 e avst_usr_dout 15 0 Case 2 If F1 F2_FRAMECLK_DIV 1 LINK 1 M 2 denoted by m0 and m1 S 1 N 16 e avst_usr_dout 15 0 m0 15 0 e avst_usr_dout 31 16 m1 15 0 Case 3 If F1 F2_FRAMECLK_DIV 1 LINK 2 denoted by link0 and link1 M 1 S Z1 N 16 e avst usr dout 15 0 linkO e avst usr dout 31 16 link1 Case 4 If F1 F2 FRAMECLK DIV 1 LINK 2 denoted b
15. the shift register e If PRBS 7 is required set this parameter to 7 e If PRBS 9 is required set this parameter to 9 e If PRBS 15 is required set this parameter to 15 e If PRBS 23 is required set this parameter to 23 e If PRBS 31 is required set this parameter to 31 This parameter value must not be larger than N which is the output data width of the PRBS pattern generator or converter resolution If an N of 12 14 is required PRBS 7 and PRBS 9 are the only feasible options If an N of 15 16 is required PRBS 7 PRBS 9 and PRBS 15 are the only feasible options 6 Values supported or demonstrated by this design example Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 System Parameters 5 41 a NN NR FEEDBACK TAP 6 5 14 18 Defines the feedback tap for the PRBS pattern generator and 28 checker This is an intermediate stage that is XOR ed with the last stage to generate to next PRBS bit e If PRBS 7 is required set this parameter to 6 e If PRBS 9 is required set this parameter to 5 e If PRBS 15 is required set this parameter to 14 e If PRBS 23 is required set this parameter to 18 e If PRBS 31 is required set this parameter to 28 Table below lists the configuration that this design example supports However the design example generated by the Osys system is always fixed at a data rate of 6144 Mbps and a limited set of configuration as shown in
16. jesd204 rx link error JESD204B IP Core Design Guidelines Altera Corporation LJ Send Feedback UG 01142 5 36 RX Latency 2015 05 04 RX Latency The RX latency is defined as the time needed to fully transfer a 32 bit data in a lane jesd204_rx_link_datain to the Avalon ST interface jesd204 rx dataout when the jesd204_rx_link_data_valid signal equals to 1 Table 5 17 RX Latency Associated with Different F and FRAMECLK_DIV Settings TENES FRAMECLK DIV RX Latency 1 1 e Maximum 5 rxframe clk period for byte 3 e Minimum 2 rxframe_clk period for byte 0 1 4 2 rxframe_clk period 2 1 e Maximum 3 rxframe_c1k period for byte 2 and byte 3 e Minimum 2 rxframe_clk period for byte 0 and byte 1 2 2 p txframe clk period 4 2txframe clk period 8 2 txframe_clk period Serial Port Interface SPI An external converter device with a SPI allows you to configure the converter for specific functions or operations through a structured register space provided inside the converter device The SPI gives flexibility and customization depending on the application Addresses are accessed via the serial port and can be written to or read from the port The memory is organized into bytes that can be further divided into fields The SPI communicates using two data lines a control line and a synchronization clock A single SPI master can work with multiple slaves The SPI core
17. output pin Indicates the converter resolution This 5 bit bus represents the N value in zero based binary format For example if N 16 the csr_n 4 0 01111 This design example supports the following values e 01011 e 01100 e 01101 e 01110 e O1111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr n 4 0 value always match the system parameter N value Connect this signal to the RX DLL csr_n output pin RX Path Operation The data transfer protocol between the Avalon ST interface and the RX path transport layer is data transfer without backpressure Therefore the sink shall always be ready to sample the incoming data whenever data at the source is valid Altera Corporation JESD204B IP Core Design Guidelines G send Feedback UG 01142 2015 05 04 RX Data Reception 5 31 Figure 5 10 RX Operation Behavior This figure shows the data transmission for a system configuration of LMF 112 N 12 N 16 S 1 Operation Upon the deassertion of the vx rame rst n signal the jesd204 rx link data ready signal from the deassembler to the DLL is asserted at the next rxframe_clk e Subsequently the DLL asserts the 3esa204 rx link data valid signal for the deassembler to activate the 2 divi cnt signal logic and to start sampling the jesd204_rx_link_datain 31 0 signal 69 e At the following rxframe_clk t
18. In the Tcl Console type cd example design directory ip simto go to the specified directory Type source gen sim verilog tcl Verilog or source gen sim vhdl tcl VHDL to generate the simulation files To run the Tcl script using the command line follow these steps Obtain the Quartus II software resource Typecd example design directory ip simto go to the specified directory Typequartus sh t gen sim verilog tcl Verilog orquartus sh t gen sim vhdl tcl VHDI to generate the simulation files Simulating the IP Core Testbench The JESD204B IP core simulation supports the following simulators ModelSim Altera SE AE VCS VCS MX Cadence Aldec Riviera Note VHDL is not supported in ModelSim Altera AE VCS simulators and Aldec Riviera for Arria 10 devices only Table 3 2 Simulation Setup Scripts This table lists the simulation setup scripts and run scripts ModelSim Altera example design directory lip sim testbench setup msim_setup tcl SE AE scripts mentor VCS lt example_design_directory gt lip_sim testbench setup_ vcs_setup sh scripts synopsys vcs VCS MX lt example_design_directory gt ip_sim testbench setup_ vcsmx_setup sh ipt l scripts synopsys vcsmx synopsys_sim setup Aldec Riviera lt example_design_directory gt ip_sim testbench setup_ rivierapro_setup tcl scripts aldec Cadence lt example_design_directory gt ip_sim testbench setup_ ncsim_setup sh scripts cadence
19. Operation e Example Feature Dynamic Reconfiguration JESD204B IP Core Debug Guidelines Updated the Clocking scheme section Added new transceiver signals that is supported in Arria 10 devices Updated the Transport Layer section Added run time reconfiguration parameter values in the System Parameters section Updated the file directory names November 2013 2013 11 04 Initial release How to Contact Altera Table 8 1 Altera Contact Information Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature 39 You can also contact your local Altera sales office or sales representative Additional Information LJ Send Feedback Altera Corporation UG 01142 8 4 How to Contact Altera 2015 05 04 Nontechnical General Email nacomp altera com support Software licensing Email authorizationgaltera com Related Information e www altera com support e www altera com training e www altera com literature 89 You can also contact your local Altera sales office or sales representative Altera Corporation Additional Information C Send Feedback
20. csr s Output Indicates the number of samples per converter per frame cycle The transport layer can use this signal as a run time parameter coro Output Indicates the high density data format The transport layer can use this signal as a run time parameter JESD204B IP Core Functional Description CJ Send Feedback Altera Corporation UG 01142 4 42 Receiver 2015 05 04 I A esr_cf Output Indicates the number of control words per frame clock period per link The transport layer can use this signal as a run time parameter cer lane powercown l L Output Indicates which lane is powered down You need to set this signal if you have configured the link and want to reduce the number of active lanes csr_rx_testmode 4 Output Indicates the address space that is reserved for DLL testing within the JESD204B IP core e O reserved for the IP core e l program different tests in the transport layer Refer to the csr_rx_testmoderegister Signal Width Direction Description Out of band OOB dete sx int 1 Output Interrupt pin for the JESD204B IP core Interrupt is asserted when any error is detected Configure the xx err enable register to set the type of error that can trigger an interrupt Direction Description Debug or Testing jesd204 rx dlb data 39 Input Optional signal for parallel data to the DLL in TX to RX loopback testing
21. EEEMJNYVNM D D D D power cycle Eb eb eb e e e n ficia S ponnn S RBD count 3 Latest arriva j Ed O O O i RBD count 5 Latest arrival lane in fifth BN o 0 power yde nomm S Lele e da S aa i H f i Tink clock or LMFC 4 countto cater for E i power cycle variation Aligned i outputs on al lt lt lt ee o Ko lanes Le b e asa e b e aa Ld ng S DREREREN S RBD Elastic Buffers gt Released Set csr_rbd_offset 1 JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation LJ Send Feedback UG 01142 6 4 Programmable RBD Offset 2015 05 04 Figure 6 3 Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi Frames Scenario In this example the RBD count varies from 7 to 1 the R character is received at the previous local multi frame when the RBD count 1 the R character is received at the current local multi frame when the RBD count 0 and 7 In this scenario deterministic latency is not guaranteed because the RBD elastic buffer is released either at the current LMFC boundary when the RBD count 0 and 1 or one local multi frame period later at the next LMFC boundary when the RBD count 7 You can fix this issue by setting the RBD offset so that the RBD elastic buffer is always released at the next local multi frame Setting csr_rbd_offset 5 forces the release of RBD elastic
22. K character and causes the RX converter to enter CGS phase After RX deasserts svwc N the CSR enters ILAS phase and will stay in that phase indefinitely until this setting changes In ILAS loop the multi frame transmission is the same where R character K28 0 marks the start of multi frame and A character K28 3 marks the end of multi frame with dummy data in between The dummy data is an increment of Dx y User Data Phase During the user data phase character replacement at the end of frame and end of multi frame is opportunistically inserted so that there is no additional overhead for data bandwidth Character replacement for non scrambled data The character replacement for non scrambled mode in the IP core follows these JESD204B specification rules e At end of frame not coinciding with end of multi frame which equals the last octet in the previous frame the transmitter replaces the octet with F character K28 7 However if an alignment character was transmitted in the previous frame the original octet will be encoded e At the end of a multi frame which equals to the last octet in the previous frame the transmitter replaces the octet with A character K28 3 even if a control character was already transmitted in the previous frame For devices that do not support lane synchronization only F character replacement is done At every end of frame regardless of whether the end of multi frame equals to the last octe
23. SYSREF SYNC Scrambler p Frame Lane Alignment Character Generation jesd204 rx top MAC jesd204 rx base PHY jesd204 rx phy Deassembly Altera Corporation Soft Logic Frame Lane Alignment Descrambler 4 Character Buffer al Replace Monitor 8B Dec W Ali Hard Logic JESD204B IP Core Functional Description C Send Feedback UG 01142 4 2015 05 04 JESD204B IP Core Functional Description 3 Figure 4 2 JESD204B IP Core TX and RX Datapath Block Diagram The JESD204B IP core utilizes the Avalon ST source and sink interfaces with unidirectional flow of data to transmit and receive data on the FPGA fabric interface TXFRAME CLK TXLINK_CLK TX INT SYSREF SYNC N I l Y Y Transceiver Duplex a p IXCIL Per Device i CSR Per Device l TXCSR A gt l To Avalon v Per Device CSR v GR Interface lg SR Ly Bus TX Frame Avalon ST Avalon ST 32 Bit PCS p Assembly 32 Bits per Channel Data Link Per hannel Soft Hard PGS j Serial Interface Per Device p gt Scrambler p gt Layer TX p PCS p and p t JESD
24. e 00000 e 00001 e 00011 e 00111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr 1 4 0 value always match the system parameter L value Runtime reconfiguration supports L fallback For static configuration set the maximum L and reconfigure csr 1 to a smaller value during runtime This transport layer only supports higher index channels to be powered down To interleave the de commision channels you need to modify the interface connection from the DLL to transport layer Connect this signal to the RX DLLcsz 11 output pin 65 This signal should be static and valid before the deassertion of the 1ink rst nand frame rst n signals JESD204B IP Core Design Guidelines CJ Send Feedback Altera Corporation 5 30 RX Path Operation UG 01142 2015 05 04 esr_f 7 0 09 cor in 4 0 35 mgmt clk mgmt clk Input Input Indicates the number of octets per frame This 8 bit bus represents the F value in zero based binary format For example if F 2 the csr_ 7 0 00000001 This design example supports the following values e 00000000 e 00000001 e 00000011 e 00000111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr_f 7 0 value always match the system parameter F value Connect this signal to the RX DLL csr_f
25. 1 boundary during RBD elastic buffer is released at the current the first power H4 LMFC boundary during the second and 14 cyde when fifth power cycle when csr_rbd_offset 0 csr _rbd_offset 0 lt _ Latency variation 1 local multi frame period Aligned j D D D D j outputs on all SS S 1 1L 1 lanes ie e e e e e e e e S 1linkdockorLMFC P Set csr_rbd_offset 5 count to cater for f RBD Elastic power cycle variation Nel Buffers Released In the example above lane de skew error could happen if the sum of the difference of R character s LMFC count in the earliest arrival lane to the latest arrival lane and the number of LMFC count up to the release of RBD elastic buffer exceeds the RBD elastic buffer size If this is the root cause of lane de skew error setting RBD offset is one of the techniques to overcome this issue Not every RBD offset value is legal Figure below illustrates the technique to decide the legal RBD offset value Altera Corporation JESD204B IP Core Deterministic Latency Implementation Guidelines C Send Feedback UG 01142 2015 05 04 Figure 6 4 Selecting Legal RBD Offset Value Programmable LMFC Offset 6 5 Current LMFC RBD elastic buffer size exceeded Next LMFC First LMFC boundary boundary and causes lane deskew error boundary genes Free running LMFC counter 0 1 2 S 2 3 4 X 5 6 7 0 X 1 2 X 3 4X5 6 7 X 0 1 4 i l
26. 10 9 8 Ul 6 5 4 3 2 1 Transport Layer to Data Link Layer 10 jesd204_rx_link_datain 31 0 Data Link Layer to Transport Layer prd DT 87 71 10 6 1stjesd204 rx dataout1 1 0 10 Transport Layer to Avalon ST Interface 1stjesd204 rx eut Transport Layer to Avalon ST Interface NT T UM mmol n n v e 9 i6 e a m n 2ndjesd204 rx ctrlout 0 Transport Layer to Avalon ST Interface TX Path The assembler in the TX path consists of the tail bits dropping assembling and multiplexing blocks Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 TX Path 5 11 Figure 5 3 TX Path Assembler Block Diagram Interface with Interfaces with JESD204 IP Core Avalon ST Data Link Layer and Control Unit JESD204B Transport Layer TX Block JESD204B IP Core Data Data Data Data p Tail Bits B B B Data Link Layer jesd204_tx_datain gt piadina gt Assembling H gt Multiplexing p gt jesd204 tx link datain L 32 1 0 DATA_BUS_WIDTH 1 0 9 PET 1 Paull pp m a p Configuration Register Settings Parameter L M EN NS F1_FRAMECLK_DIV i Y F2 FRAMECLK DIV i ill i jesd204 tx link early ready jesd204
27. 2 4 multi frame in ILAS phase 2 d multi frame contains the JESD204B link configuration data h Start of 3 d multi frame i Start of 4 multi frame j Device lanes alignment is achieved In this example there is only one device the dev 1ane aligned connects to a11dev lane aligned and both signals are asserted together k Start of user data phase where user data is streamed through the JESD204B link JESD204B IP Core Debug Guidelines Altera Corporation CJ Send Feedback UG 01142 Debugging JESD204B Link Using SignalTap II and System Console 2015 05 04 Transport Layer Verify the RX transport layer operation using these signals in the altera_jesd204_transport_rx_top sv e jesd204_rx_dataout e jesd204_rx_data_valid e jesd204_rx_data_ready e jesd204_rx_link_data_ready e jesd204_rx_link_error e Ix rame rst n Use the rxframe_clk signal as the sampling clock For normal operation the jesd204 rx data valid jesd204 rx data ready and jesd204 rx link data ready signals should be asserted while the jesa204 xx link error should be deasserted You can view the ramp or sine wave test pattern on the jesd204 rx dataout bus Figure 7 2 Ramp Pattern on the 5es 204 rx dataout Bus This is a SignalTap II image during the JESD204B user data phase with ramp pattern transmitted from the ADC f rx datain lane Jtjjesd204 rx link datain 127 96 rx datain lane ortjjesd204 rx link datain 95 64 ortjjesd
28. 3 Targeted device with LMF 421 K 32 and Data rate 10 0 Gbps Device Clock selected 250 MHz obtained during IP core generation Link Clock 10 GHz 40 250 MHz Frame Clock 10 GHz 10x1 1 GHz 9 Local Multi frame clock 1 GHz 32 31 25 MHz SYSREF Frequency Local Multi frame Clock n n integer 1 2 Local multi frame clock counter F x K 4 1x32 4 8 link clocks 09 09 Eight link clocks means that the local multi frame clock counts from value 0 to 7 and then loopback to 0 09 The link clock and frame clock are running at the same frequency You only need to generate one clock from the Altera PLL or Altera IO PLL IP core CO For this example the frame clock may not be able to run up to 1 GHz in the FPGA fabric The JESD204B transport layer in the design example supports running the data stream of half rate 1 GHz 2 500 MHz at two times the data bus width or of quarter rate 1GHz 4 250MHz at four times the data bus width JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback UG 01142 4 24 Reset Scheme 2015 05 04 Related Information e Device Clock on page 4 20 e Link Clock on page 4 21 Local Multi Frame Clock on page 4 22 Reset Scheme All resets in the JESD204B IP core are synchronous reset signals and should be asserted and deasserted synchronously Note Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion Table 4
29. C Send Feedback UG 01142 2015 05 04 TX Path 5 13 Ese S EN talinkvelic Input Reset for the TX link clock domain logic in the assembler This reset is an active low signal and the deassertion is synchronous to the rising edge of txlink_clk txframe_rst_n txframe_clk Input Reset for the TX frame clock domain logic in the assembler This reset is an active low signal and the deassertion is synchronous to the rising edge of txframe_clk Signal Clock Domain Direction Description Between Avalon ST and Transport Layer jesd204 tx txframe clk Input TX data from the Avalon ST source interface datain DATA BUS The source shall arrange the data in a specific WIDTH 1 0 order as illustrated in the cases listed in TX Path Data Remapping section jesd204 tx txframe clk Input TX control data from the Avalon ST source controlin CONTROL interface The source shall arrange the data in a BUS WIDTH 1 0 specific order as illustrated in the cases listed in TX Path Data Remapping section jesd204 tx data txframe clk Input Indicates whether the data from the Avalon ST valid source interface to the transport layer is valid or invalid e 0 data is invalid e 1 data is valid Jesd204 tx data txlink clk Output Indicates that the transport layer is ready to ready accept data from the Avalon ST source interface e 0 transport layer is not ready to receive data e 1 transport layer is ready to receive
30. Clock device clock i Trace Matching 1 Notes 1 The device clock to the Altera core PLL and SYSREF must be trace matched The device clock to the converter device and SYSREF must be trace matched The phase offset between the SYSREF to the FPGA and converter devices should be minimal 2 For Arria 10 devices the transceiver PLL is outside of the JESD204B IP core For Arria V and Stratix V devices the transceiver PLL is part ofthe JESD204B IP core 3 The Altera core PLL provdes the link clock frame clock and AVS clock The link clock and frame clock must be synchronous Related Information Clock Correlation on page 4 23 Link Clock The device clock is the timing reference for the JESD204B system Due to the clock network architecture in the FPGA JESD204 IP core does not use the device clock to clock the SYSREF signal because the GCLK or RCLK is not fully compensated You are recommended to use the Altera PLL IP core in Arria V and Stratix V devices or Altera IOPLL IP core in Arria 10 devices to generate both the link clock and frame clock The Altera PLL IP core must operate in normal mode or source synchronous mode to achieve the following state e the GCLK and RCLK clock network latency is fully compensated e the link clock and frame clock at the registers are phase aligned to the input of the clock pin To provide consistency across the design regardless of frame clock and sampling clock the link clock is used as a timing
31. Core Design Guidelines C Send Feedback UG 01142 2015 05 04 System Interface Signals 5 45 Clock Direction Description Domain rx sysref LINK 1 0 dime Input RX SYSREF signal for JESD204B Subclass 1 implementation tx dev sync n LINK link clk Output Indicates a clean synchronization request at the TX ee path This is an active low signal and is asserted 0 to indicate a synchronization request The syNc_N signal error reporting is masked out of this signal This signal is also asserted during software initiated synchronization dev_lane_ link_c1k Output Indicates that all lanes for this device are aligned at aligned LINK 1 0 the RX path rx_dev_sync_n LINK link clk Qutput _ Indicates a sync_n to the transmitter This is an 1 0 active low signal and is asserted 0 to indicate a synchronization request Instead of reporting the link error through this signal the JESD204B IP core uses the 3esd204 rx int signal to indicate an interrupt Clock Direction Description Domain SPI mise selik Input Output data from a slave to the input of the master oou Bere Output Output data from the master to the inputs of the slaves SOR mgmt clk Output Clock driven by the master to slaves to synchronize the data bits ss n 2 0 BOUE Output Active low select signal driven by the master to individual slaves to select the target slave Defaults to 3 bits Clock Direction Descript
32. DLL testing within the JESD204B IP core e O reserved for the IP core l program different tests in the transport layer Refer to csr_tx_testmode register ger Cx Lestpattern 32 Output A 32 bit fixed data pattern for the test al mode 9 por xot eEn 32 Output A 32 bit fixed data pattern for the test bt mode 9 csr_tx_testpattern 32 Output A 32 bit fixed data pattern for the test ell mode 9 cer ts col n ce 32 Output A 32 bit fixed data pattern for the test eti mode Signal Width Direction Description Out of band OOB jesd204 tx int 1 Output Interrupt pin for the JESD204B IP core Interrupt is asserted when any error or synchronization request is detected Configure thetx err enable register to set the type of error that can trigger an interrupt Signal Width Direction Description Debug or Testing Jesd204 tx dlb 2 Output Optional signal for parallel data from the DLL pore in TX to RX loopback testing 9 jesd204 tx dlb L 4 Output Optional signal to indicate the K character k har caesar value for each byte in TX to RX loopback testing 3 You can use this signal in the transport layer to configure programmable test pattern 4 This signal is only for internal testing purposes You can leave this signal disconnected JESD204B IP Core Functional Description Altera Corporation LJ Send Feedback UG 01142 4 36 Receiver 2015 05 04 Receiver Tab
33. Design Guidelines Altera Corporation CJ Send Feedback 5 34 RX Path Data Remapping UG 01142 2015 05 04 Casel M 1 S 4 MOSO FOF1 MOS1 F4F5 cnt 0 M0S2 F8F9 M0S3 F12F13 decns jesd204_rx_ Case2 M 2 S 2 MOSO FOF1 MOSI FAFS dataout 63 0 M1S0 F8F9 M1S1 F12F13 F12F13 F8F9 F4E5 FOF1 Case3 M 4 S 1 MOS0 FOF1 M1S0 F4F5 M2S0 F8F9 M3S0 F12F13 F2_ Casel M 1 S 4 MOSO F2F3 MOS1 F6F7 FRAMCL MOS2 F10F11 K_DIV 1 MO0S3 F14F15 jesd204 rx Case2 M 22 S 2 MOS0 F2F3 MOS1 F6F7 2nd frameclk dataout 63 0 M1S0 F10F11 F14F15 M1S1 F14F15 FIOF11 F6F7 F2F3 Case3 M 4 S 1 MOSO F2F3 MISO F6F7 M2S0 F10F11 M3S0 F14F15 F2_ jesd204_rx_dataout 127 0 F14F15 F10F11 F6F7 F2F3 F12F13 F8F9 F4F5 FOF1 FRAMCL K DIV 2 Table 5 15 Data Mapping for F 4 L 4 Lane L3 L2 L1 LO Data In F12 F13 F14 F8 F9 F10 F11 F4 F5 FG F7 FO Fl F2 F3 F15 Supported M M S 8 for F 4 L 4 ands F 4 supports either casel M 1 S 8 case2 M 2 S 4 case3 M 4 S 2 or case4 M 8 S 1 Casel M 1 S 8 MO0S7 MOS6 M0S5 M0S4 M0S3 MOS2 MOS1 MOSO jesd204_rx_ dataout 127 0 Case2 M 22 S 4 M1S3 M182 MISI MISO MOS3 M0S2 ic F14F15 MOS1 MOSO FI2FIS FIOFll Case3 M 4 S 2 M3S1 M3S0 M2S1 M2S0 MISI M150 F8F9 F6E7 FAE5 MOS1 MOSO F2F3 FOF1 Case4 M 8 S 1 M7S0 M6S0 M5S0 M4S0 M3S0 M2S0 M1S0 MOSO Altera Corpor
34. Sushi dpa br bl nad e Rp 3 7 Generating and Simulating the IP Core TestDenchiau neuer tpa RI EO dA 3 8 Compiling the JESD204B IP Core Design sse sseesssressrtessresssrtsrteesreeesrtesrtesntessntesntesnrrrsnreesee 3 10 Programming an FPGA Device ssasisscsccsissssescssecessossssnseecussonssstanvce ssoassnaeisessonuevnssgsedsosbevassaseasiebese 3 11 JESD204B IP Core Design Considerations sic esceiencuavnneratnantatindein cen iatnaaenan iinet 3 11 Integrating the JESD204B IP core in Qsys iis csassscscassncssaserassssiisnsvsnsocsenasanasscssbitsecesssrvessnacssarss 3 11 Pin Assignim ents oio eiecit ERR ERR HER HER EIER REUS ERE REIR S 3 12 Adding External Transceiver PU ws ssississscsnssavecssessicsnansdussstnsvsenisdansansaisatvnavsatessduanssassunntdesaieneede 3 13 Timing Constraints For Input Clocks sssssesssssssssstessssseessssterssssrensnsntesssneessnsntessnereesnrreeesneee 3 13 JESD204B IP Core Paramietets 5 irent orte eddie die e v eod prins 3 16 JESD204B IP Core Component Piles Jioc ivo eesa ptt eh ehh reed tH pi etu rh uA ra toi uias 3 21 JESD204B IP Core Testbetich ace vid eterni ete rt ate eer nth eerie iden ede ava pd 3 21 Testbench Simulation EIOS ttis rto aeons ate oane ce aan ie ine aes ate anise 3 23 JESD204B IP Core Functional Description eeeeeeee esee eene eren enne 4 1 bru M 4 4 B MR CHE diri C G 4 5 IDEADA E
35. Transceiver PHY Reset Controller IP core Some configurations are preset and are not programmable in the JESD204B IP core testbench For example the JESD204B IP core always instantiates in duplex mode even if RX or TX mode is selected in the JESD204B parameter editor Note Dynamic reconfiguration is not supported in this JESD204B IP core testbench Getting Started J send Feedback Altera Corporation 3 22 JESD204B IP Core Testbench UG 01142 2015 05 04 Table 3 8 Preset Configurations for JESD204B IP Core Testbench JESD204B Wrapper Base and PHY MAC and PHY Data Path Duplex PLL CDR Reference Clock Frequency e data rate 20 if you turn on Enabled Hard PCS e data rate 40 if you turn on Enabled Soft PCS Link Clock Data rate 40 AVS Clock 125 MHz Figure 3 5 JESD204B IP Core Testbench Block Diagram The external ATX PLL is present only in the JESD204B IP core testbench targeting an Arria 10 FPGA device family JESD204B Testbench Reference Clock Generator Link Clock Generator AVS Clock Generator Packet Generator Checker Loopback Transceiver PHY Reset Controller IP Core Related Information Generating and Simulating the IP Core Testbench on page 3 8 Altera Corporation Getting Started G send Feedback UG 01142 2015 05 04 Testbench Simulation Flow 3 23 Testbench Si
36. Type e CMU Select the Phase Locked Loop PLL types depending on the ATX FPGA device family e Cylone V CMU e Arria V CMU e Stratix V CMU ATX 02 The maximum data rate is limited by different device speed grade transceiver PMA speed grade and PCS options Refer to Table 3 4 for the maximum data rate support Getting Started LJ Send Feedback Altera Corporation UG 01142 3 18 JESD204B IP Core Parameters 2015 05 04 Bonding Mode e Bonded Select the bonding modes e Non bonded Bonded select this option to minimize inter lanes skew for the transmitter datapath e Non bonded select this option to disable inter lanes skew control for the transmitter datapath Note The bonding type is automatically selected based on the device family and number of lanes that you set PLL CDR Reference 50 0 625 0 Set the transceiver reference clock frequency for PLL or CDR Clock Frequency Enable Bit reversal and On Off Turn on this option to set the data transmission order in MSB Byte reversal first serialization If this option is off the data transmission order is in LSB first serialization Enable Transceiver On Off Turn on this option to enable dynamic data rate change When Dynamic Reconfigura you enable this option you need to connect the reconfigura tion tion interface to the transceiver reconfiguration controller 5 For Arria 10 devices turn on this option to enable the Transceiver Nativ
37. Upon reset the converter device RX issues a synchronization request by driving syNc_n low The JESD204 TX IP core transmits a stream of K K28 5 symbols The receiver synchronizes when it receives four consecutive K symbols For Subclass 0 the RX converter devices deassert syNc_N signal at the frame boundary After all receivers have deactivated their synchronization requests the JESD204 TX IP core continues to emit K symbols until the start of the next frame The core proceeds to transmit ILAS data sequence or encoded user data if csr_lane_sync_en signal is disabled For Subclass 1 and 2 the RX converter devices deassert syNc_N signal at the LMFC boundary After all receivers deactivate the syNc_N signal the JESD204 TX IP core continues to transmit K symbols until the next LMFC boundary At the next LMFC boundary the JESD204B IP core transmits ILAS data sequence There is no programmability to use a later LMFC boundary When lane alignment sequence is enabled through the csz 1ane sync en register the ILAS sequence is transmitted after the CGS phase The ILAS phase takes up four multi frames For Subclass 0 mode you can program the CSR csr_ilas_multiframe to extend the ILAS phase to a maximum of 256 multi frames before transitioning to the encoded user data phase The ILAS data is not scrambled regardless of whether scrambling is enabled or disabled The multi frame has the following structure Each multi frame starts with
38. a R character K28 0 and ends with a A character K28 3 The second multi frame transmits the ILAS configuration data The multi frame starts with R character K28 0 followed by Q character K28 4 and then followed by the link configuration data which consists of 14 octets as illustrated in the table below It is then padded with dummy data and ends with A character K28 3 marking the end of multi frame Dummy octets are an 8 bit counter and is always reset when it is not in ILAS phase For a configuration of more than four multi frames the multi frame follows the same rule above and is padded with dummy data in between R character and A character JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback 4 6 TX ILAS Table 4 1 Link Configuration Data Transmitted in ILAS Phase Configura imoa ER CREER ER ER 0 DID 7 0 UG 01142 2015 05 04 DID Device ID 1 ADJCNT 3 0 BID 3 0 ADJCNT Number of adjustment resolution steps 9 BID Bank ID 2 0 ADJDI PHA LID 4 0 ADJDIR Direction to adjust DAC LMFC 09 PHADJ Phase adjustment request 9 LID Lane ID 3 SCR JO 0 L 4 0 SCR Scrambling enabled disabled L Number of lanes per device link 4 F 7 0 F Number of octets per frame per lane K 4 0 K Number of frames per multi frame 6 M 7 0 7 CS 1 0 0 N 4 0 M Number of converters per
39. be differential in phase due to a different clock network For Subclass 1 you cannot use the output of txphy clksignalas txlink clk signal To sample SYSREF correctly the core PLL must provide the tx1ink clk signal and must be configured as normal operating mode eee Cee cese ni Input Reset for the TX link clock signal This reset is an active low signal exphy edet L Output TX parallel clock output for the TX PCS This clock must have the same frequency as txlink clk signal This clock is output as an optional port for user if the txlink_clk and txframe clk signals are operating at the same frequency in Subclass 0 operating mode tx digitalreset 0 y Input Reset for the transceiver PCS block This reset is an active high signal tx analogreset 0 L Input Reset for the transceiver PMA block This reset is an active high signal 92 The Transceiver PHY Reset Controller IP Core controls this signal JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback 4 28 Transmitter UG 01142 2015 05 04 EE WEM E RENS pll lockea 2 Output PLL locked signal for the hard transceiver This signal is asserted to indicate that the TX transceiver PLL is locked This signal is an output signal for V series FPGA variants but an input signal for 10 series FPGA variants and above tx cal busy 0 L Output TX calibration in progress signal This s
40. by the DAC manufacturer Altera Corporation JESD204B IP Core Debug Guidelines C Send Feedback UG 01142 S 2015 05 04 Debugging JESD204B Link Using SignalTap Il and System Console 7 5 Figure 7 1 JESD204B Link Initialization This is a SignalTap II image during the JESD204B link initialization The JESD204B link has two transceiver channels L 2 0 32 64 96 128 160 192 224 256 288 Name nannte nee tarnen les re erneuern tnmen eerte edem nier iaRera jesd204 inst phy inst phyjesd204 rx pcs data vald i iC __jesd204_inst_phy inst_phyjjesd204_rx_pcs_errdetect 7 4 Oh E ea Oh __ra_jesd204_inst_phy inst_phyjesd204_rx_pcs_disperr 7_4 Oh it D Oh __ jesd204 ist phy inst phyjesd204 rx pcs kchar data 7 4 Oh m Ello o To sm 9 Oh X era jesd204 ist phynst phyjesd204 rx pcs dataj 3 56 ooh IIl iech BEN era jesd204 inst phy inst phyjesd204 rx pcs data 55 48 00h era jesd204 inst phy ins phyjesd204 rx pcs data 47 40 00h BCh E era_jesd204_inst_piry inst_phyjesd204_rx_pcs_data 39 32 00h H ecn d jatera_jesd204_inst_phy inst_phyjjesd204_rx_pcs_data_vald 0 H 654204 inst phy inst phyfjesd204 rx pcs errdetect 3 0 Oh iy 998 Oh ra jesd204 inst phy inst phyjesd204 rx pcs disperr 3 0 Oh AeA Oh E jesd204 inst phy nst phyjesd204 rx pcs kchar data 3 0 o Miem filii o Jg o 9 9PFTq o 9 era jesd204 ist phys phyjesi204 n pcs deta 24 Oon IN oon E era jesd204 inst
41. core name gt Contains the IP core source files Note The default IP installation directory on Windows is drive altera version number on Linux it is home directory gt altera version number Related Information e Altera Licensing Site e Altera Software Installation and Licensing Manual Upgrading IP Cores IP core variants generated with a previous version of the Quartus II software may require upgrading before use in the current version of the Quartus II software Click Project Upgrade IP Components to identify and upgrade outdated IP core variants Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required optional or unsupported for IP cores in your design This dialog box may open automatically when you open a project containing upgradeable IP variations You must upgrade IP cores that require upgrade before you can compile the IP variation in the current version of the Quartus II software The upgrade process preserves the original IP variation file in the project directory as my variant BAK qsys for IP targeting Arria 10 and later devices and as my variant BAK v sv or vhd for legacy IP targeting 28nm devices and greater Note Upgrading IP cores for Arria 10 and later devices may append a unique identifier to the original IP core entity name s without similarly modifying the IP instance name There is no requirement to update these entity references in any supp
42. crucial for deterministic latency throughout the link e RX Scrambler and Data Link Layer takes in 32 bits of data that decodes the ILAS performs descram bling character replacement as per the JESD204B specification and error detection code group error frame and lane realignment error RX Data Link Layer The JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elastic buffers can be released Special character substitution are done in the TX link so that the RX link can execute frame and lane alignment monitoring based on the JESD204B specification RX CGS The CGS phase is the link up phase that monitors the detection of K28 5 character The CGS phase is achieved through the following process e Once the word boundary is aligned the RX PHY layer detects the K28 5 20 bit boundary and indicate that the character is valid e The receiver deasserts syNc_N on the next frame boundary for Subclass 0 or on the next LMFC boundary for Subclass 1 and 2 after the reception of four successive K characters e After correct reception of another four 8B 10B characters the receiver assumes full code group synchronization Error detected in this state machine is the code group error Code group error always trigger link reinitialization through the assertion of syNc_n signal and this cannot be disabled through the CSR The CS state machine is defined as cS_INIT Cs CHECK and CS DATA The minimum
43. deassembler at the RX path e maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL through the Avalon ST interface e reports AL error to the DLL if it encounters a specific error condition on the Avalon ST interface during RX data streaming Supported System Configuration The transport layer supports static configurations where before compilation you can modify the configu rations using the IP core s parameter editor in the Quartus II software To change to another configura tion you have to recompile the design The following list describes the supported configurations for the transport layer Data rate maximum 12 5 Gbps F1 FRAMECLK Div 4 and F2_FRAMECLK_DIV 2 L 1 8 F 1 2 4 8 N 12 13 14 15 16 N 16 CS 0 3 CF 0 HD 0 for F 2 4 8 1 for F 1 Dynamic Downscaling Of System Parameters L N and F The Dynamic Downscaling of System Parameters DDSP feature enables you to dynamically downscale specific JESD204B system parameters through the CSR without having to recompile the FPGA The transport layer supports dynamic downscaling of parameters L F and N only The supported M and S parameters are determined by the L F and N parameters Some parameters for example CS and N Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Relationship Between Frame Clock and Link Clock 5 9
44. do not have this capability in the transport layer If you needs to change any of these parameters you must recompile the system You are advised to connect the power down channels to higher indexes and connect used channel at lower lanes Otherwise you have to reroute the physical used channels to lower lanes externally when connecting the IP core to the transport layer For example when L 4 and csr 1 8 d1 which means two lanes out of four lanes are active with lane 1 and lane 3 being powered down connection from the MAC to the transport layer for lane 0 remains However lane 1 is powered down while lane 2 is not powered down Thus lane 2 output from the MAC should be rerouted to lane 1 data input of the transport layer The data port for those power down channels will be tied off within the transport layer The 16 bit N data for F 1 is formed through the data from 2 lanes Thus F 1 is not supported for odd number of lanes for example when LMF 128 In this case you can only reconfigure from F 8 to F 4 and F 2 but not F 1 Relationship Between Frame Clock and Link Clock The frame clock and link clock are synchronous The ratio of 1ink clk period to rame c1k period is given by this formula 32x L MxSxN Table 5 3 txframe_clk and rxframe_clk Frequency for Different F Parameter Settings For a given fri txlink clk frequency and fj rxlink clk frequency the fiframe txframe_clk frequency and fxframe r
45. for TX PLL and two for channel MIF Then merge the files into two xcvr atx pll combined mif and xcvr_cdr_combined mif Only the JESD204B IP cores with maximum configuration is used in final compilation xcvr atx pll combined mif Maximum Configuration MIF CONTENT BEGIN 00 E 102FF71 Start of MIF 01 103BF01 02 1047F04 03 1054700 10 11AFF00 11 11CE020 12 11DE020 13 3FFFFFF End of MIF Downscale Channel Configuration MIF 14 102FF71 Start of MIF 15 103BF01 16 i 1047F04 17 1054700 24 L1AFFOO 225 11CE020 26 11DE020 JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 54 MIF ROM 27 3FFFFFF End of MIF END xcvr cdr combined mif Maximum Configuration MIF CONTENT BEGIN 00 i 006DF02 Start of MIF 01 007FF09 02 008FF04 03 OOAFFO1 76 i 173FF31 77 R 1741F0C 78 1753F13 79 3FFFFFF End of MIF Downscale Channel Configuration MIF 7A 006DF02 Start of MIF 7B 007FF09 76 008FF04 7D i OOAFFO1 FO 173FF31 Fl 1741F0C F2 1753F13 F3 3FFFFFF End of MIF END JESD UG 01142 2015 05 04 The current JESD MIF contains only the LMF information You need to manually code the MIF content in the following format Maximum Configuration MIF WIDTH 16 DEPTH 16 ADDRESS RADIX UNS DATA RADIX BIN CONTENT BEGIN
46. frame error input pin Signal Clock Domain Direction Description CSR in DLL 60 If a JESD device of No Multiple Converter Device Alignment Single Lane NMCDA SL class is deployed Altera recommends that you tie this input signal to 1 Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 TX Path 5 15 csr l 4 0 6 mgmt clk Input Indicates the number of active lanes for the link This 5 bit bus represents the L value in zero based binary format For example if L 1 the csr 1 4 0 00000 This design example supports the following values e 00000 e 00001 e 00011 e 00111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr 1 4 0 value always matches the system parameter L value when it is in static configura tion Runtime reconfiguration supports L fallback For static configuration set the maximum L and reconfigure csr 1 to a smaller value during runtime This transport layer only supports higher index channels to be powered down To interleave the de commision channels you need to modify the interface connection from the DLL to transport layer Connect this signal to the TX DLL csr_1 output pin csr f 7 0 0D mgmt clk Input Indicates the number of octets per frame This 8 bit bus represents the F value in zero based binary format F
47. i RBD Elastic i gt a p lt RBD elastic buffersize 8 buffers released Internal LMFC counter resets at LMFC boundary when RBD count 7 7 LMFC counts with reference to the next LMFC boundary lt Set cst_tbd_offset 5 lt Aligned auis on all FSESESESESESESES S e e e laalaa aalala n D L lanes P Illegal Gr rbd offset 1 2 3 exceeding RBD elastic buffer size Legal csr_rbd_offset 4 i within RBD elastic buffer size RBD Elastic Buffers Released Because the IP core does not report the position of the earliest lane arrival with respect to the LMFC boundary you should perform multiple power cycles to observe the RBD count and tune the RBD offset accordingly until no lane de skew error occurs From the example in the figure above the recommended RBD offset value is 4 or 5 Setting RBD offset to 1 2 or 3 is illegal because this exceeds the RBD elastic buffer size for the F and K configurations Related Information SYNC_N Signal on page 4 14 Programmable LMFC Offset If your JESD204B subsystem design has deterministic latency issue the programmable LMFC offset in the TX and RX IP cores provides flexibility to ensure that deterministic latency can be achieved The TX LMFC offset can align the TX LMFC counter to the LMFC counter in DAC the RX LMFC offset can align the RX LMFC counter to the LMFC counter in ADC Phase offset b
48. is an active high signal and requires the jesd204 tx avs writedata 31 0 signal to be in use 32 bit data driven from the Avalon MM slave to master in response to a read transfer jesd204 tx avs waitrequest Signal JESD204 Interface Width Output Direction This signal is asserted by the Avalon MM slave to indicate that it is unable to respond to a read or write request The JESD204B IP core ties this signal to 0 to return the data in the access cycle Description sysref Input SYSREF signal for JESD204B Subclass 1 implementation For Subclass 0 and Subclass 2 mode tie off this signal to 0 Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Transmitter 4 33 AM SS oP Input Indicates sync_n from the converter device or receiver This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting from the converter device To indicate a synchronization request the converter device must assert this signal for at least five frames and nine octets To indicate an error reporting the converter device must ensure that the pulse is at least one cycle of the txlink_c1k signal or two cycles of the txframe_clk signal whichever period is longer dev_sync_n 1 Output Indicates a clean synchronization request This is an active low signal and is asserted 0 to indicate a synchronization
49. is recovered from the serial data stream 5 The Transceiver PHY Reset Controller IP Core controls this signal Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Receiver 4 37 Signal With irection Deseripton O reconfig to xcvr L 70 Input Dynamic reconfiguration input for the hard transceiver This signal is only applicable for V series FPGA variants You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run time reconfiguration is enabled or disabled The Transceiver Reconfiguration Controller IP core also supports various calibra tion function during transceiver power up reconfig from xcvr L 46 Output Dynamic reconfiguration output for the hard transceiver This signal is only applicable for V series FPGA variants You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run time reconfiguration is enabled or disabled The Transceiver Reconfiguration Controller IP core also supports various calibra tion function during transceiver power up reconfig_clk Input The Avalon MM clock input The frequency range is 100 125 MHz This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_reset Input Reset signal for the Transceiver Reconfiguration Controller I
50. lane is reported as the RBD count In the first power cycle the R character is received at 4 LMFC counts before the next LMFC boundary hence the RBD count 4 In the second power cycle the R character is received at 3 LMFC counts before next LMFC boundary hence the RBD count 3 In five power cycles the RBD count varies from 3 to 5 Since there are limited number of power cycles and boards for characterization 1 LMFC count tolerance is allocated as a guide to set early RBD release opportunity Hence setting csr_rbd_offset 1 can safely release the elastic buffer 1 LMFC count earlier at LMFC count 7 before the next LMFC boundary If the RBD elastic buffer is released before the latest arrival lane this will cause a lane de skew error Link clock SYSREF pulse is sampled by IP core internal register w IX Sysref SYNC N deasserted lt at LMFC boundary SYNC N i 1 link clock period LMFC count zin dock cycle BEN H H higi fog ed y 1tLMEC boundary 2 MEC boundary 31d LMFC boundary 4th LMFC boundary Internal IMEC Counter Free running LMFC counter SK 0 X 1 2 SS lt 7 XK 0XK 1K 2 SS and 10 S K 3 eX 6 7 X 0 1 RBD count 4 4 LMFC counts from Internal LMFC counter resets i ret LMFC boundary Latest arriva lane in first SS
51. only Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 JESD204B IP Core Parameters 3 17 Data Path e Receiver Select the operation modes This selection enables or disables e Transmitter the receiver and transmitter supporting logic e Duplex e RX instantiates the receiver to interface to the ADC e TX instantiates the transmitter to interface to the DAC e Duplex instantiates the receiver and transmitter to interface to both the ADC and DAC JESD204B Subclass 0 Select the JESD204B subclass modes e l e 0 Set subclass 0 2 e Set subclass 1 e 2 Set subclass 2 Data Rate 1 0 12 5 Set the data rate for each lane 0 e Cyclone V 1 0 Gbps to 5 0 Gbps Arria V 1 0 Gbps to 6 55 Gbps e Arria V GZ 2 0 Gbps to 9 9 Gbps e Arria 10 2 0 Gbps to 12 5 Gbps e Stratix V 2 0 Gbps to 12 5 Gbps PCS Option e Enabled Select the PCS modes Hard PCS P Enabled Sofi Enabled Hard PCS utilize Hard PCS components Select o opon this option to minimize resource utilization with data rate that supports up to the limitation of the Hard PCS Note For this setting you will utilize 8G PCS mode with 20 bits PMA width and 32 bits PCS width e Enabled Soft PCS utilize Soft PCS components Select this option to allow higher supported data rate but increase in resource utilization Note For this setting you will utilize 10G PCS mode with 40 bits PMA width and 40 bits PCS width PLL
52. pattern generator 4 The Avalon ST interface data bus is fixed at 32 bit The number of 32 bit data bus is equal to the number of lanes L 5 The number of lanes per converter device L 27 Refer to Figure 5 18 and Figure 5 19 for the illustration of a single and multiple JESD204B links Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Design Example Components 5 3 6 You can enable internal serial loopback by setting the rx_seriallpbken input signal You can dynamically toggle this input signal When toggled to 1 the RX path takes the serial input from the TX path internally in the FPGA When toggled to 0 the RX path takes the serial input from the external converter device During internal serial loopback mode the assembler takes input from the pattern generator 7 Asingle serial port interface SPI master instance can control multiple SPI slaves The SPI master is a 4 wire instance If the SPI slave is a 3 wire instance use a bidirectional I O buffer in between the master and slave to interface the 4 wire master to 3 wire slave 8 The SPI protocol interface All slaves share the same data lines MISO and MOSI or DATAIO Each slave has its own slave select or chip select line ss n 9 The PLL takes the device clock from an external clock chip as the input reference The PLL generates two output clocks utilizing two output counters from a single VCO Clock 1 is the frame c
53. phy inst phyjesd204 rx pcs data 23 16 Rera_jesd204_inst_phy inst_phyjjesd204_rx_pcs_data 15 8 E atera_jesd204_inst_phy inst_phyjesd204_rx_pcs_data 7 0 jesd204b edu jesd204b edialidev lane algned 0 0 RA LLML 1h jesd204b edu jesd204b edidev lane slgned 0 0 842045502048 DUPLEX COREIO u jesd204irx somf 0 o 04 JES02048_0UPLEX_CORE 0 u_jesd204irxink_rst_n_reset_n jesd204 JES02048_DUPLEX_CORE 0 u_jesd204jesd204_rx_int i jesd204 JES02048_DUPLEX_CORE O u jesd204rx_dev syncen Lie UT jesd204 inst phy inst phyjesd204 rx pcs kchar data 3 0 E era jesd204 inst phy inst phyjesd204 rx pcs data 3 98 39 era jesd204 inst phy inst phyjesd204 rx pcs data 23 16 era jesd204 inst phy inst phyjesd204 rx pcs data 15 8 altera jesd204 inst phy inst phyjesd204 rx pcs data 7 0 Description of the timing diagram a The JESD204B link is out of reset b The RX CDR is locked and PCS outputs valid characters to link layer c No running disparity error and 8b 10b block within PCS successfully decodes the incoming characters d The ADC transmits K character or BC hexadecimal number to the FPGA which starts the CGS phase e Upon receiving 4 consecutive K characters the link layer deasserts the xx dev sync n signal f The JESD204B link transition from CGS to ILAS phase when ADC transmit R or 1C hexadecimal after K character g Start of
54. reference JESD204B IP Core Functional Description Altera Corporation LJ Send Feedback UG 01142 4 22 Local Multi Frame Clock 2015 05 04 The Altera PLL IP core should provide both the frame clock and link clock from the same PLL as these two clocks are treated as synchronous in the design For Subclass 0 mode the device clock is not required to sample the SYSREF signal edge The link clock does not need to be phase compensated to capture SYSREF Therefore you can generate both the link clock and frame clock using direct mode in the Altera PLL IP core If F 4 where link clock is the same as the frame clock you can use the parallel clock output from the transceiver txphy_clk or rxphy_clk signal Related Information Clock Correlation on page 4 23 Local Multi Frame Clock The Local Multi Frame Clock LMFC is a counter generated from the link clock and depends on the F and K parameter The K parameter must be set between 1 to 32 and meet the requirement of at least a minimum of 17 octets and a maximum of 1024 octets in a single multi frame In a 32 bit architecture the K x F must also be in the order of four In a Subclass 1 deterministic latency system the SYSREF frequency is distributed to the devices to align them in the system The SYSREF resets the internal LMFC clock edge when the sampled SYSREF signal s rising edge transition from 0 to 1 Due to source synchronous signaling of SYSREF with respect to the device clock sam
55. the Altera PLL IP Core for Arria V Cyclone V and Stratix V or Altera I O PLL IP Core for Arria 10 using the derive pll clocks command e Comment out the create clock commands for the tx1ink clk reconfig to xcvr 0 or reconfig clk andtx avs clk rxlink clk and rx avs clk clocks in the altera jesd204 sdc file e Identify the base and generated clock name that correlates to the tx1ink clk reconfig clk and tx avs clk rxlink clk and rx avs clk clocks using the report clock command e Describe the relationship between base and generated clocks in the design using the set clock groups command After you complete your design you must modify the clock names in your sdc file to the full design clock names taking into account both the IP core instance name in the full design and the design hierarchy Be careful when adding the timing exceptions based on your design for example when the JESD204B IP core handles asynchronous timing between the cx1ink clk rxlink clk pll ref clk tx avs clk rx avs clk and reconfig clk for Arria 10 only clocks The table below shows an example of clock names in the altera jesd204 sdc and input clock names in the user design In this example there is a dedicated input clock for the transceiver TX PLL and CDR at the refclk pin The device_clk is the input to the core PLL c1kin pin The IP core and transceiver Avalon MM interfaces have separate external clock sources with different frequencies Altera Corpora
56. to device I O pins You can create virtual pins to avoid making specific pin assignments for top level signals This is useful when you want to perform compilation but are not ready to map the design to hardware Altera recommends that you create virtual pins for all unused top level signals to improve timing closure Note Do not create virtual pins for the clock or reset signals Getting Started C Send Feedback Altera Corporation UG 01142 2015 05 04 Adding External Transceiver PLL 3 13 Adding External Transceiver PLL The JESD204B IP core variations that target an Arria 10 FPGA device require external transceiver PLLs for compilation JESD204B IP core variations that target a V series FPGA device contain transceiver PLLs Therefore no external PLLs are required for compilation You are recommend to use an ATX PLL or CMU PLL to get a better jitter performance Note The PMA width is 20 bits for Hard PCS and 40 bits for Soft PCS Related Information Arria 10 Transceiver PHY User Guide More information about the Arria 10 transceiver PLLs and clock network Timing Constraints For Input Clocks When you generate the JESD204B IP core variation the Quartus II software generates a Synopsys Design Constraints File sdc that specifies the timing constraints for the input clocks to your IP core When you generate the JESD204B IP core your design is not yet complete and the JESD204B IP core is not yet connected in the design Th
57. 00010100 94 11111111111111111111111111111111 End of MIF 95 127 i 00000000000000000000000000000000 END Generating and Simulating the Design Example To use the JESD204B IP core design example testbench follow these steps 1 Generate the design example simulation testbench Refer to Generating the Design Example Simulation Model on page 5 55 2 Simulate the design example using simulator specific scripts Refer to Simulating the JESD204B IP Core Design Example on page 5 56 Generating the Design Example Simulation Model After generating the IP core generate the design example simulation testbench using the script gen ed sim verilog tcl or gen ed sim vhdl located in the example design directory led sim directory JESD204B IP Core Des ign Guidelines LJ Send Feedback Altera Corporation UG 01142 5 56 Simulating the JESD204B IP Core Design Example 2015 05 04 Note For more information about the JESD204B design example testbench refer to the README_DESIGN_ EXAMPLE txt file located in the lt example_design_directory gt ed_sim folder To run the Tcl script using the Quartus II sofware follow these steps 1 Launch the Quartus II software 2 On the View menu click Utility Windows and select Tcl Console 3 In the Tcl Console type cd lt example_design_directory gt ed_sim to go to the specified directory 4 Type source gen_ed_sim_verilog tcl Verilog or source gen ed sim vhdl tcl VHDL to generate th
58. 1888 1285 0 8 1908 2969 1757 0 1 1056 1542 1215 0 2 1642 2363 1857 0 RX 4 2936 4097 3140 0 8 5546 7697 5712 0 1 719 1150 948 0 2 937 1488 1083 0 TX 4 1358 2114 1353 0 8 2137 3417 1894 0 Related Information e JESD204B IP Core Parameters on page 3 16 e Fitter Resources Reports in the Quartus II Help Information about the Quartus II resource utilization reporting including ALMs needed 9 MIOK for Arria V device M20K for Arria V GZ Stratix V and Arria 10 devices The Quartus II software may auto fit to use MLAB when the memory size is too small Conversion from MLAB to M20K or M10K was performed for the numbers listed above The Quartus II software may auto fit to use MLAB when the memory size is too small Conversion from MLAB to M20K or M10K was performed for the numbers listed above About the JESD204B IP Core CJ Send Feedback Altera Corporation Getting Started 2015 05 04 UG 01142 amp Subscribe L J Send Feedback The JESD204B IP core is part of the MegaCore IP Library distributed with the Quartus II software and downloadable from the Altera website at www altera com Related Information Altera Software Installation amp Licensing Introduction to Altera IP Cores Altera and strategic IP partners offer a broad portfolio of off the shelf configurable IP cores optimized for Altera devices The Quartus II software installation includes the Altera IP library You can integrate optimized and verified Altera IP c
59. 204 rx avs dk GENERIC STATES pll locked from TX PLL Transceiver PHY Reset Controller tx_ready rx_ready jesd204 tx avs rst n jesd204 rx avs rst n Naf NAP NEP NE o NC MAD XX XJ NNI NS I X XE LIVI VSN VS VS VS Ku Ne Nery PN NN TRANSCEIVER amp PLL POWERUP AVALON SLAVE CONFIGURATION PHASE TESDZOABTP OPERATION gt baink_eltink_ek IA IATA IAIN NAINA NIN IN IN INI NINN NIN INN INN txlink_rst_n rxlink_rst_n txframe_clk rxframe_clk txframe rst n rframe rst n Signals The JESD204B IP core signals are listed by interface Transmitter e Receiver Note You should terminate any unused signals Altera Corporation i JESD204B IP core register configuration and converter devices SPI programming JESD204B IP core link initialization begins JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Transmitter 4 27 Transmitter Table 4 5 Transmitter Signals Signal width rection Description O Clocks and Resets pil ref cik 1 Input Transceiver reference clock signal The reference clock selection depends on the FPGA device family and data rate This signal is only applicable for V series FPGA variants txlink_cik 1 Input TX link clock signal This clock is equal to the TX data rate divided by 40 This clock must have the same frequency as the txphy_clk signal but can
60. 204 rx link datain 63 32 portjjesd204 rx link datain 31 0 rx gatan tanel rx Catan laned m rx dataa 3 sportjjesd204 rx dataout 47 36 3 rx dataout 2 sportjjesd204 rx dataout 35 24 a rx dataout 1 sportjjesd204 rx dataout 23 12 i nsport jesd204 rx dataout 11 0 Verify the TX transport layer operation using these signals in the altera jesd204 transport tx top sv e txframe rst n e jesd204 tx datain e jesd204 tx data valid e jesd204 tx data ready e jesd204 tx link early ready e jesd204 tx link data valid e jesd204 tx link error Use the tx rame c1k signal as the sampling clock For normal operation the jesd204 tx data valid jesd204 tx data ready jesd204 tx link early ready and jesd204 tx link data valid signals should be asserted while the 3esd204 tx link error should be deasserted You can verify the user data arrangement shown in the data mapping tables in the TX Path Data Remapping on page 5 18 by referring to the jesd204 tx datain bus Altera Corporation JESD204B IP Core Debug Guidelines C Send Feedback UG 01142 2015 05 04 Debugging JESD204B Link Using SignalTap II and System Console 7 7 Related Information AN 696 Using the JESD204B MegaCore Function in Arria V Devices More information about the performance and interoperability of the JESD204B IP core AN 729 Implementing JESD204B IP Core System Reference Design with Nios II Proces
61. 204B y TX Transceiver Ln Dp TX Per Device l l RXFRAME_CLK Ta ARNT SYSREF ASYNC_N i gt RX CTL l Avalon MM CSR Per Device RXCSR g A To Avalon Per Device sp v GR gt l Interface PISIN iius Bus Iavalon ST RX Frame 32 Bit PCS PCS Avalon ST Deassembly 32 Bi Channel Data Link Per Channel Soft Hard PCS Serial Interface Per Device 4 its per Channe Descrambler Layer RY PCS and 41 RI n RI p l JESD204B y RX Transceiver n RA p RX Per Device JESD2048 TX and RX Transport Layer with Base and Transceiver Design Example l ee E pe ap p e E 32 Bits Architecture The JESD204B IP core consist of 32 bit internal datapath per lane This means that JESD204B IP Core expects the data samples to be assembled into 32 bit data 4 octets per lane in the transport layer before sending the data to the Avalon ST data bus The JESD204 IP core operates in the link clock domain The link clock runs at data rate 40 because it is operating in 32 bit data bus after 8B 10B encoding As the internal datapath of the core is 32 bits the F x K value must be in the order of 4 to align the multi frame length on a 32 bit boundary Apart from this the deterministic latency counter values such as LMFC counter RBD counter and Subclass 2 adjustment counter will be in link clock count instead of frame clock count Avalon ST Interface The JESD204 IP core and transport layer in the design example use
62. 4 JESD204B IP Core Resets TX RX Link Clock Active low reset controlled by the clock and reset unit txlink rst n rxlink rst n Altera recommends that you e Assert the tx1ink rst n rxlink rst n and txframe rst n lrxframe rst n signals when the transceiver is in reset e Deassert the cx1ink rst nandtxframe rst n signals after the Altera PLL IP core is locked and the tx_ready signal from the Transceiver Reset Controller is asserted e Deassert the xx1ink rst nand rxframe_ rst n signals after the Transceiver CDR rx islockedtodata signal and rx ready signal from the Transceiver Reset Controller are asserted The txlink rst n rxlink rst n and txframe rst n rxframe rst nsignals can be deasserted at the same time These resets can only be deasserted after you configure the CSR registers TX RX Frame Clock Active low reset controlled by the clock and reset unit If the TX RX link clock and the TX EEE ENG Et RX frame clock has the same frequency both can share the same reset txframe_rst_n Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Reset Sequence 4 25 Transceiver Native PHY Active high reset controlled by the transceiver Analog Reset reset controller This signal resets the TX RX rx analogreset L 1 0 PMA tx analogreset L 1 0 The link clock frame clock and AVS clock reset signals txlink rst n rxlink rst n txframe rst n rxframe
63. 5 0 163 84 supported supported speed grade gt speed grade Arria V GZ 2 3 2 0 to 9 9 0 247 50 Arria V GZ 3 4 2 0 to 8 8 0 220 00 Arria 10 1 1 2 0 to 12 0 2 0 to 12 5 312 50 Arria 10 2 1 2 0 to 12 0 2 0 to 12 5 312 50 Arria 10 2 2 2 0 to 9 83 2 0 to 12 5 312 50 Arria 10 3 1 2 0 to 12 0 2 0 to 12 5 312 50 Arria 10 3 2 2 0 to 9 83 2 0 to 12 5 Arria 10 4 3 2 0 to 8 83 2 0 to 12 5 312 50 Arria 10 5 3 2 0 to 8 0 2 0 to 8 0 312 50 Stratix V 1 lor2 2 0 to 12 2 2 0 to 12 5 312 50 Stratix V p lor2 2 0 to 12 2 2 0 to 12 5 312 50 Stratix V 2 3 2 0 to 9 8 2 0 to 12 5 312 50 9 Select Enable Soft PCS to achieve maximum data rate For the TX IP core enabling soft PCS incurs an additional 3 896 increase in resource utilization For the RX IP core enabling soft PCS incurs an additional 10 20 increase in resource utilization 9 Enabling Soft PCS does not increase the data rate for the device family and speed grade You are recommended to select the Enable Hard PCS option Altera Corporation About the JESD204B IP Core C Send Feedback UG 01142 aa 2015 05 04 Performance and Resource Utilization 2 7 Data Rate PMA Speed FPGA Fabric Device Family Grade Seekers Enable Hard EnableSoftPcs Link Clock Fmax MHz PCS Gbps Gbps 9 Stratix V 3 1 2 3 or 4 2 0 to 8 5 2 0 to 8 5 312 50 The following table lists the resources and expected performance of the JESD204B IP core These results are obtained us
64. Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 z 2015 05 04 Transmitter 4 31 ESSE jesd204 tx link Input Indicates whether the data from the transport valid layer is valid or invalid The Avalon ST sink interface in the TX core cannot be backpres sured and assumes that data is always valid on every cycle when the jesd204_tx_link_ready signal is asserted e 0 data is invalid e 1 data is valid Bete link 1 Output Indicates that the Avalon ST sink interface in ready the TX core is ready to accept data The Avalon ST sink interface asserts this signal on the JESD204B link state of USER DATA phase The ready latency is 0 jesd204 tx frame 1 Output Indicates that the Avalon ST sink interface in ready the transport layer is ready to accept data The Avalon ST sink interface asserts this signal on the JESD204B link state of ILAS 4 multiframe and also the USER DATA phase The ready latency is 0 Signal Width Direction Description Avalon MM Interface jesd204 tx avs clk 7 Input The Avalon MM interface clock signal This clock is asynchronous to all the functional clocks in the JESD204B IP core The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz jesd204_tx_avs_rst_n Input This reset is associated with the jesd204_tx_ avs_clk signal This reset is an active low signal You can assert th
65. Avalon MM interface shares the same clock source as the transceiver management clock 09 For Arria 10 device only Getting Started CJ Send Feedback Altera Corporation 3 16 JESD204B IP Core Parameters Table 3 5 Example B Original clock names in altera_ jesd204 sdc User design input clock names UG 01142 2015 05 04 Frequency Recommended SDC timing constraint MHz tx_pll_ref_clk rx_pll_ref_clk create_clock name device_clk period 8 0 get_ports device_clk create_clock name mgmt_clk period 10 0 get_ports mgmt_clk device_clk 125 txlink_clk rxlink_clk tx_avs_clk rx_avs_clk reconfig_clk 11 mgmt_clk 100 derive_pll_clocks set_clock_groups asynchronous group device_clk lt base and generated clock names as reported by report_clock commands gt group mgmt_clk lt base and generated clock names as reported by report_clock commands gt JESD204B IP Core Parameters Table 3 6 JESD204B IP Core Parameters Main Tab Device Family Aras Select the targeted device family Arria V GZ e Arria 10 e Cyclone V e Stratix V JESD204B Wrapper Base Only Select the JESD204B wrapper e PHYOnly e Base Only generates the DLL only e Both Base e PHY Only generates the transceiver PHY layer only soft and PHY and hard PCS e Both Base and PHY generates both DLL and transceiver PHY layers For Arria 10 device
66. Avalon MM slave without the Qsys interconnect to perform byte to word addressing conversion you are recommended to shift the Avalon MM master address bus by 2 bits divide by 4 when connecting to the IP core s Avalon MM slave In this connection the Avalon MM master address bit 2 connects to the IP core Avalon MM slave address bit 0 while the Avalon MM master bit 9 connects to the IP core address bit 7 TX register map RX register map Register Access Type Convention This table describes the register access type for Altera IP cores Table 4 7 Register Access Type and Definition RO Software read only no effect on write The value is hard tied internally to either 0 or 1 and does not vary RO v Software read only no effect on write The value may vary RC e Software reads shall return the current bit value then the bit is self clear to 0 e Software reads also cause the bit value to be cleared to 0 RW e Software reads shall return the current bit value e Software writes shall set the bit to the desired value RWIC e Software reads shall return the current bit value e Software writes 0 shall have no effect e Software writes 1 shall clear the bit to 0 if the bit has been set to 1 by hardware e Hardware sets the bit to 1 e Software clear has higher priority than hardware set JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback UG 01142 4 44 Register Access Type Conventi
67. B IP Core Functional Description J send Feedback Altera Corporation 4 30 Transmitter UG 01142 2015 05 04 SS a RHEE reconfig_avmm_ Input The input data accu This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ 32 Output The output data pee This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig avmm write Input Write signal This signal is active high This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig avmm read 1 Input Read signal This signal is active high This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ 1 Output Wait request signal cud E This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants Signal Width Direction Description Avalon ST Interface jesc204 ts ink 132 Input Indicates a 32 bit user data at cx1ink clk datal clock rate where four octets are packed into a 32 bit data width per lane The data format is big endian The first octet is located at bit 31 24 followed by bit 23 16 bit 15 8 and the last octet is bit 7 0 Lane 0 data is always located in the lower 32 bit data If more than one lane is instantiated lane 1 is located at bit 63 32 with the first octet position at bit 63 56
68. B first transmission the serialization of the left most bit of 8B 10B code group bit a is transmitted first Receiver The receiver block which interfaces to ADC devices receives the serial streams from one or more TX blocks and converts the streams into one or more sample streams The receiver performs the following functions e Data deserializer e 8B 10B decoding e Lane alignment e Character replacement e Data descrambling Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 RX Data Link Layer 4 9 Figure 4 4 Receiver Data Path Block Diagram RXFRAME_CLK ey ARX INT SYSREF 4 SYNC_N JESD204 RX Transport Layer with Base and Transceiver Design Example v Transceiver RX gt RX CTL Per Device Avalon MM CSR Per Device RX CSR A To Avalon v Per Device m v gt E mS CSR b gt on iul Deassembly Avalon ST hae Soft Hard Pcs 32 Bits per Channel Data Link Serial Interface Per Device Descrambler H Layer RX PCS 4 and 4 RI n RX p JESD204B RX Transceiver RX Per Device The receiver block includes the following modules e RX CSR manages the configuration and status registers e RX_CTL manages the sync_n signal state machine that controls the data link layer states LMFC and also the buffer release which is
69. CORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 4 2 JESD204B IP Core Functional Description Figure 4 1 Overview of the JESD204B IP Core Block Diagram DAC Application Layer Transport Layer JESD204B Design Example ADC Application Data Frame Data Link Layer UG 01142 2015 05 04 Physical Layer JESD204B IP Core jesd204 tx top MAC jesd204 tx base PHY jesd204 tx phy Assembly Layer lt Frame Clock Data Frame A
70. DAC to determine whether deterministic latency is achieved and RBD elastic buffer size has not exceeded Altera Corporation JESD204B IP Core Deterministic Latency Implementation Guidelines C Send Feedback UG 01142 2015 05 04 Programmable LMFC Offset 6 9 The SYSREF pipeline registers in the FPGA introduce additional latency to SYSREF when detected by the IP core Therefore you can use TX LMFC offset to reduce or eliminate this additional latency The next figure illustrates the technique of optimizing latency using TX LMFC offset Figure 6 8 Optimizing IP Core Latency Using TX LMFC Offset Sequence of events in the diagram 1 The DAC samples the SYSREF pulse 2 The DAC s internal LMFC counter resets after a deterministic delay 3 The SYSREF pipeline registers introduces an additional 2 link clock latency 4 Thecsr Imfc offset field is set to 4 The IP core internal LMFC counter resets after 2 link clock cycles 5 The LMFC boundary is delayed by 4 link clock 6 The DAC deasserts SYNC N at the LMFC boundary 7 SYNC N deassertion is detected by the JESD204B IP core 8 Because LMFC boundary is delayed by 4 link clock the IP core detects the SYNC N deassertion before the second LMFC boundary ILAS transmis
71. EF SYNC N TX ILA Begins on First LMFC Zero Crossing x Deterministic Delay from SYSREF gt le after SYNC N Is Deasserted Devi Sampled High to LMFC Zero Crossing i evice H wt t 7 ft 1 Multi Fram L Transmit Lanes KR REEERE RIEKE D DDBROC IcD p Dr SYSREF SYNC N SYNC N Deasserted Directly after LMFC Zero Crossing gt Deterministic Delay from i SYSREF Sampled High E RX Elastic Buffers Released to LMFC wae T A E 4 RX RX Elastic Buffer RBD Frame RBD Frame RBD Frame i RBD Frame 4 Device Release Opportunity Cycles Cycles Cycles gt Cycles gt Earliest Arrival Lane IRRIRIRRIRRIRERIRIRRIERIRIRIRRIERIRIERIRO oa q C0 ORROD aest avallare iIRRKKKKIE RRR RR 4g polito o 2 Character Elastic Buffer Delay for Latest Arrival gt 6 Character Elastic Buffer Delay for Latest Arrival Migned Outputon Al Lanes KRREKERIGEKEKRRRRRRRRRRIR IERI oic Co O O terministic Delay from TX ILA Output to RX ILA Output RX PHY Layer The word aligner block identifies the MSB and LSB boundaries of the 10 bit character from the serial bit stream Manual alignment is set because the K character must be detected in either LSB first or MSB first mode When the programmed word alignment pattern is detected in the current word boundary the PCS indicates a valid pattern in the xx sync status mapped as pcs_valid to the IP core The code synchronization state is detected after the detection of the K character boundary f
72. F 2 1 2 mn The divider ratio on the frame_c1k The assembler always use the post divided frame clk txframe cIk RECONFIG EN Enable reconfiguration support in the transport layer Only 0 1 downscaling reconfiguration is supported Disable the reconfiguration to reduce the logic DATA BUS The data input bus width size that depends on the F and L 8 F L N DEDE bus width M S N N PRIME F M S N PRIME 8 L M S 8 F L N PRIME Therefore the data bus width 8 F L N N PRIME CONTROL BUS The control output bus width size The width depends on the CS OUTPUT WIDTH parameter as well as the M and S parameters When CS is 0 the BUS control data is one bit wide tie the signal to 0 WIDTH N CS If CS 0 the bus width 1 Otherwise the bus width OUTPUT BUS WIDTH N CS while OUTPUT BUS WIDTH N M S Table 5 5 Assembler Signals Control Unit txlink clk e Input TX link clock signal This clock is equal to the TX data rate divided by 40 This clock is synchronous tothe txframe clk signal txframe clk Input TX frame clock used by the transport layer The frequency is a function of parameters F F1 FRAMECLK DIV F2 FRAMECLK DIV and txlink clk This clock is synchronous to the tx1ink clk signal 09 Refer to the Table 5 7 to set the desired frame clock frequency with different FRAMECLK DIV and F values Altera Corporation JESD204B IP Core Design Guidelines
73. F4 DIV 4 6 Lane L3 L2 L1 LO Data Out F12 F13 F14 F8 F9 F10 F11 F4 F5 F6 F7 FO FL F2 F3 F15 Table 5 7 Data Mapping for F 2 L 4 Supported M S 4 for F 2 L 4 MM F 2 supports either casel M 1 S 4 case2 M 2 S 2 or case3 M 4 S 1 32 The effective frame clock in the Transport Layer is 4x of the link clock 33 The effective frame clock in the Transport Layer is same as the link clock JESD204B IP Core Design Guidelines CJ Send Feedback Altera Corporation 5 22 TX Path Data Remapping UG 01142 2015 05 04 Casel M 1 S 4 MOSO FOFI MOS1 F4E5 MOS2 F8F9 MOS3 F12F13 jesd204 tx at Ist frameclk M E Case2 M 2 S 2 MOSO FOF1 MOSI FAES FBF9 FAPS FOF1 MISO FS8F9 M1S1 F12F13 Case3 M 4 S 1 MOSO FOF1 MISO FAFS M2S0 F8F9 M3S0 F12F13 F2_ FRAMCL Casel M 1 S 4 MO0S0 F2F3 MOS1 F6F7 K_DIV 1 MO0S2 F10F11 M0S3 F14F15 ne Case2 M 2 2 MOSO F2E3 MOSI EGET 2nd frameclk Vm M1S0 F10F11 ELAF ID MI1S1 F14F15 F10F11 F6F7 F2F3 H Case3 M 4 S 1 MOSO F2F3 MISO F6F7 M2S0 F10F11 M3S0 F14F15 F2_ jesd204_tx_datain 127 0 F14F15 F10F11 F6F7 F2F3 F12F13 F8F9 F4F5 FOF1 FRAMCL K DIV 2 Lane L3 L2 Ll LO Data Out F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Table 5 8 Data Mapping for F 4 L 4 Supported M M S 8 for F 4 L 4 ane F 4 supports either casel M 1
74. HAS VENE ase RR 7 2 Debugging JESD204B Link Using SignalTap II and System Console sss 7 3 Additional Information sesesseesesseseesseseeseseesseseesoeserseseeeseserseeseesessereeserseesereeeseee 8 1 JESD204B IP Core Document Revision History essent tenente tette tenentes 8 1 How to Contact 2 licis n 8 3 Altera Corporation JESD204B IP Core Quick Reference 2015 05 04 UG 01142 GX subscribe Send Feedback The Altera JESD204B MegaCore function is a high speed point to point serial interface intellectual property IP The JESD204B MegaCore function is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website at www altera com Note For system requirements and installation instructions refer to Altera Software Installation e Licensing Table 1 1 Brief Information About the JESD204B MegaCore Function o0 mem Dedi O O Version 15 0 Release Date May 2015 Relace Ordering Code IP JESD204B Information Product ID 0116 Vendor ID 6AF7 e Joint Electron Device Engineering Council JEDEC JESD204B 01 2012 standard release specification e Device subclass IP Core Provocalibeatures e Subclass 0 Backwards compatible to JESD204A Information e Subclass 1 Uses SYSREF signal to support deterministic latency e Subclass 2 Uses SYNC_N detection to support determin isti
75. Input Indicates whether the 3esd204 rx link datain is valid or invalid e 3esd204 rx link datain is invalid 1 3jesd204 rx link datain is valid Connect this signal to the RX DLL jesa204 rx link valid output pin jesd204 rx link data ready rxframe clk Output Indicates that the transport layer is ready to sample jesd204 rx link datain e 0 transport layer is not ready to sample jesd204 rx link datain e 1 transport layer starts sampling jesd204_ rx link datain at the next clock cycle Connect this signal to the RX DLL jesa204 rx link ready input pin jesd204 rx link Error Signal CSR in DLL rxlink clk Clock Domain Output Direction Indicates an empty data stream due to invalid data This signal is asserted high to indicate an error at the Avalon ST sink interface for example when jesd204_rx_data_valid l while jesd204 rx data ready 0 The DLL subsequently reports this error to the CSR block Connect this signal to the RX DLL jesa204 rx frame error input pin Description Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 RX Path 5 29 csr l 4 0 G9 mgmt clk Input Indicates the number of active lanes for the link This 5 bit bus represents the L value in zero based binary format For example if L 1 the csr 1 4 0 00000 This design example supports the following values
76. JESD204B IP Core User Guide Last updated for Altera Complete Design Suite 15 0 bX Subscibe UG 01142 101 Innovation Drive 2015 05 04 San Jose CA 95134 C Send Feedback www altera com TOC 2 JESD204B IP Core User Guide Contents JESD204B IP Core Quick Reference sscssscsscsssssecsssssccssscescssscesesssecscesses 1 1 About the JESD204B IP COFGdieissndvrnEp R RUPES RENE IU ONUS ERREUR FI ES uL SM CUL RU KE NEA EON ME 2 1 D tapath DI M 2 3 Ier a feris 2 3 JESD204B IP Core Configurati M M 2 4 R n Tim Cohen a sane shana tease abt av anne SSE eec pip Ep quibas quM RR 2 4 ciii ID 2 5 Performance and Resource Utiliza loDiau doces eee eroe ni i dab Ep EDO Ue pe e E LER ELI EHE XE DUE 2 6 Getting Started assisi ies P Tm 3 1 Introduction to Altera IP COFPPS vchisiepe uti ie o dn ad vid du uitio hb Od i 3 1 Installing and Licensing IP COs sis sicciscssasssevacacsicnspssnivantesanayaiachssveaianssaesisn ra ER M h a Po UHR a lS rcu 3 2 B ucniopaldeo 3 2 IP Catalog and Paratneter Editot e ior eter dtr rei bt xl Le bp LANE HEAR FOX ei Ep 3 5 Design Walkthrough iei sei eR red OH E R SRM cra RRS 3 6 Creating New Quartus II Project sxuissicusasissnnsacdesaccndapiasabasasnaassuasscsantnsasacassecabsaedasesantesinssivnnsndaitac 3 6 Parameterizing and Generating the IP CODO eise
77. K K K r gt p p p Lt D SYSREFpuleis H sampled by IP core internal register rx sysref i i SYNC_N deasserted direct SYNC_N i 2 ly transmitted by RX H H after LMFC boundary EE 4 1 link clock period LMFC count 2 link clock cycle deterministic ee delay from SYSREF sampled Heime 4 r Fourth LMFC high to the first LMFC bouna gt 2 ra ae boundary boundary Internal c i TFC Gaal Fre running LMFC counter n Se 6 3 4 5 6 1X0 LMEC phase offset Internal LMFC counter resets lt lt r gt esr Imfe offset Latest arrival s lane in multiple EMEN lt Sca REPE D D DD power cycles Internal i lt LMFC Counter Free running LMFC counter SE OTS Ms ex TC Scien SS ee 1 2 3 4 xs es LMFC boundary is Internal counter rese _ delayed by 3 link clock i LMFC boundary at new location csr Imfc offset 5 Latest arrival g Baisse K KI KK K K K K KIK S amp power cycles 22 Third LMFC boundary at new location lt gt link clock or LMFC count ater for power cycle variation RBD elastic buffer released 2 when csr rbd offset 0 D DID DID JESD204B IP Core Deterministic Latency Implementation Guidelines C Send Feedback UG 01142 2015 05 04 Programmable LMFC Offset 6 7 You should set a safe LMFC offset value to ensure deterministic latency from one power cycle to another power cycle In Figure 6 6 t
78. LL IP core in Arria V and Stratix V devices or Altera IOPLL IP core in Arria 10 devices to generate the link clock and frame clock The link clock is used in the JESD204 IP core MAC and the transport layer Based on the JESD204B specification the device clock is the timing reference and is source synchronous with SYSREF Due to the clock network architecture in the FPGA you are recommended to use the device clock to generate the link clock and use the link clock as timing reference The JESD204B protocol does not support rate matching Therefore you must ensure that the TX or RX device clock pll ref clk and the PLL reference clock that generates link clock txlink clk or rxlink_clk and frame clock txframe_clk or rxframe_clk have 0 ppm variation Both PLL reference clocks should come from the same clock chip Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Link Clock 4 21 Figure 4 8 JESD204B Subsystem Clock Diagram For Arria V and Stratix V Devices FPGA Device Core PLL Normal Mode 3 Frame Clock avs dock Link Clock SYSREF 3 Trace Matching 1 JESD204B IP Core Vv MAC PHY Test Pattern JESD2048 Avalon ST Transceiver Transport PLL 2 Generator Layer 2 Check FPGA Device kd SYSREF Converter Device
79. LMFC counter in DAC JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation C Send Feedback UG 01142 6 8 Programmable LMFC Offset 2015 05 04 Figure 6 7 Example of Reducing LMFC Phase Offset between TX and RX LMFC Counter Sequence of events in the diagram SYSREF pulse arrives at the FPGA IP core port tx_sysref The IP core s internal LMFC counter resets after two link clock cycles SYSREF pulse is sampled by the DAC The DAC s internal LMFC counter resets after a deterministic delay The LMFC phase offset is 3 5 link clock cycles The DAC deasserts SYNC N at the LMFC boundary SYNC N deassertion is detected by the JESD204B IP core Because SYNC N deassertion is detected after the second LMFC boundary at the FPGA ILAS transmission begins at the third LMFC boundary 9 Thecsr Imfc offset is set to 4 This delays the TX LMFC boundary by 4 link clock cycles If csr Imfc offset is set to 5 the TX LMFC boundary is delayed by 3 link clock cycles 10 The LMFC phase offset between the TX and RX LMFC reduces to 0 5 link clock cycle CoN UU Om o Ea m Link clock SYSREF pulse is mp PGA 2 link dockigyde deterministic delay from i i 7a SYSREF sampled high to the first LMFC boundary 1 link clock period Second L
80. M variation name gt v or vhd IP core variation file which defines a VHDL or Verilog HDL description of the custom IP core Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus II software variation name cmp variation name sdc variation name qip A VHDL component declaration file for the IP core variation Add the contents of this file to any VHDL architecture that instantiates the IP core Contains timing constraints for your IP core variation Contains Quartus II project information for your IP core variation variation name tcl Tcl script file to run in Quartus II software variation name sip Contains IP core library mapping information required by the Quartus II software The Quartus II software generates a sip file during generation of some Altera IP cores You must add any generated sip file to your project for use by NativeLink simulation and the Quartus II Archiver variation name spd Contains a list of required simulation files for your IP core JESD204B IP Core Testbench The JESD204B IP core includes a testbench to demonstrate a normal link up sequence for the JESD204B IP core with a supported configuration The testbench also provides an example of how to control the JESD204B IP core interfaces The testbench instantiates the JESD204B IP core in duplex mode and connects with the Altera
81. MFC Third LMFC LMFC count boundary boundary Fourth LMFC tx sysref i T gt lt _ boundary P we boundary d A nternal 1 j 1 LMFC Counter OXI XIX KAS XX S DX 1x IXGXA4AxX5x6 XO Free running B B i LMFC counter i i Internal LMFC counter resets B H csr_Imfc_offset 0 SYNC N deassertion is i i SYNC_N O detected by the IP core l i b transmission by the PG 8 arrival at TX L Transmit ines ipie S zn me Y L D D D LMFC phase offset Internal LMFC Counter X 4 5 6 Free running i LMFC counter 0x 1X 21X3 x MSG x AX SCSXIXOXAXCIXCGGXCA i i LMFC boundary is i H First LMFC boundary i delayed O 4 link clock at new location H rnal LMFC counter resets cr Imfc offset 4 transmission by the FPGA ut ui E s HE J0 Reduced LMFC 10 gt lt t phase offset SYSREF pulse is sampled by DAC M SYNC N transmitted SYNC_N deasserted at by DAC i H the LMFC boundary Deterministic delay from 4 SYSREF sampled high to i First LMFC Second LMFC Tenia the first LMFC boundary zi m n e a boundary TUM Free running LMFC counter S X 0 1 S 0 1 LED ACECEESE S aa 6 7 9 1 2 3 i Alternative to tuning RBD offset at the DAC adjusting TX LMFC offset in the FPGA helps you to achieve deterministic latency You should perform multiple power cycles and read the RBD counts at the
82. MIF e 1 Upscale back to maximum data rate setting stored in PLL PHY and clock MIF Assuming the compile time data rate is 3 072 Gbps set this signal to 0 to scale down the data rate to 1 536 Gbps Set this signal to 1 to scale up the data rate back to 3 072 Gbps cu busy mgmt clk Owutput Assert high to indicate that the control unit is busy All reconfiguration input will be ignored when this signal is high Clock Direction Description Domain Avalon ST User Data Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Clock Direction Description Domain System Interface Signals 5 47 avost aSr din FRAMI DOVA ETNIK 99518 AL BO avst_usr_din_valid ECLK_ frame_ eiik frame_ Input Input TX data from the Avalon ST source interface The source arranges the data in a specific order as illustrated in the cases below Case 1 If F1 F2_FRAMECLK_DIV 1 LINK 1 M zls L IN le e avst_usr_din 15 0 Case 2 If F1 F2_FRAMECLK_DIV 1 LINK 1 M 2 denoted by m0 and m1 S 1 N 16 e avst usr din 15 0 m0 15 0 e avst usr din 31 16 m1 15 0 Case 3 If FI F2 FRAMECIK DIV 1 LINK 2 denoted by link0 and link1 M 1 S Z1 N 16 e avst usr din 15 0 linkO e avst usr din 31 16 link1 Case 4 If F1 F2 FRAMECLK DIV 1 LINK 2 denoted by link0 and link1 M 2 denoted by m0 and m1 S 1 N 16
83. Mapping for F 1 L 4 Lane L3 I2 L1 LO Data In F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Supported M S 2 for F 1 L 4 M and S F 1 supports either casel M 1 S 2 or case2 M 2 S 1 Assuming N 16 M0S0 jesd204 rx dataout 15 0 MOSI MISO jesd204_rx_dataout 31 16 Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 RX Path Data Remapping 5 33 m Casel M 1 S 2 MOS0 F0F4 MOSI F8F12 ist framedk jesd204 IX Case2 M 22 S 1 MO0SO0 FOFA M1S0 F8F12 dataout 31 0 F8F12 FOF4 Hee Casel M 1 S 2 MOS0 F1F5 M0S1 F9F13 2nd frame cik jesd204 IX Case2 M 22 S 1 MO0S0 FIF5 MISO F9F13 dataout 31 0 Fi F9F13 F1E5 FRAMCL K DIV 1 cnt 2 Casel M 1 S 2 MO0SO0 F2F6 MOSI FIOF14 3rd famedik jesd204 IX Case2 M 22 S 1 MOS0 F2F6 M1S0 F10F14 dataout 31 0 F10F114 F2F6 Casel M 1 S 2 MOS0 F3F7 MOSI FIIFIS 4th framecli jesd204 IX Case2 M 2 S 1 MOS0 F3F7 M1S0 F11F15 dataout 31 0 F11F15 F3F7 ae jesd204_rx_dataout 127 0 F11F15 F3F7 F10F114 F2F6 F9F13 F1E5 F8F12 FOF4 K_DIV 4 Table 5 14 Data Mapping for F 2 L 4 Lane 13 L2 L1 LO Data In F12 F13 F14 F15 F8 F9 F10 F11 FA F5 F6 F7 F0 F1 F2 F3 Supported M S 4 for F 2 L 4 M a F 2 supports either casel M 1 S 4 case2 M 2 S 2 or case3 M 4 S 1 JESD204B IP Core
84. P core This signal is active high and level sensitive This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ address log L 1024 Input The Avalon MM address This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ writedata 32 Input The input data This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants JESD204B IP Core Functional Description J send Feedback Altera Corporation 4 38 Receiver UG 01142 2015 05 04 Sl reconfig_avmm_ Output The output data oar This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig GAM write 1 Input Write signal This signal is active high This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig avmm_ read 1 Input Read signal This signal is active high This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ 1 Output Wait request signal doc This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants Signal Width Direction Description Avalon ST Interface jesd204 rx link data L 32 Output Indicates a 32 bit data from the DLL to the transport layer The dat
85. PHY IP Core User Guide for the timing diagram of the tx_analogreset rx_analogreset tx_digitalreset and rx_digitalreset signals JESD204B IP Core Functional Description Altera Corporation J send Feedback 4 26 Signals The bring up sequence 1 Ensure that the core PLL and transceiver PLL are out of reset first UG 01142 2015 05 04 If the Transceiver PHY Reset Controller and Transceiver Reconfiguration blocks rely on the clock from the core PLL output for example the management clocks and reset then the core PLL must be out of reset first If the Transceiver PHY Reset Controller and Transceiver Reconfiguration blocks are clocked by the external clock generator the core PLL and transceiver PLL can be out of reset concurrently 2 Deassert the transceiver reset 3 Ensure that all core PLL and transceiver PLL are locked 4 Once the transceiver is out of reset deassert the AV MM interface reset for the IP core At the configu ration phase the subsystem can program the converter devices through the SPI interface During this configuration phase the subsystem may program the JESD204B IP core if the default IP core register settings need to change 5 Deassert both the link reset for the IP core and the frame reset for the transport layer Figure 4 9 Reset Sequence Timing Diagram pll_ref_clk tx rx pll Transceiver PHY Reset Controller reset input active high reconfig_clk Arria 10 only jesd204_tx_avs_clk jesd
86. Q P7 P6 iP5 i P4 P3 P2 P1 i po R W W1 WO A12 A11 A10 A9 A8 A7 A6 A5 M a3 a2 A1 AO D7 D6 Ds D4 D3 D2 D1 Do 8 Bit Pre Selection 16 Bit Instruction 8 Bit Register Data In this design example the SPI core is configured as a 4 wire master protocol to control three independent SPI slaves ADC DAC and clock devices The width of the receive and transmit registers are configured at 32 bits Data is sent in MSB first mode in compliance with the converter device default power up mode The SPI clock scik rate is configured at a frequency of the SPI input clock rate divided by 5 If the SPI input clock rate is 100 MHz in the mgmt__clock domain the sc1k rate is 20 MHz If the external converter device s SPI interface is a 3 wire protocol without both MOSI master output slave input and MISO master input slave output lines but with a single DATAIO pin you can use the ALTIOBUF Megafunction IP core configured with bidirectional buffer with the SPI master to convert the MOSI and MISO lines to a single DATAIO pin The DATAIO pin can be dynamically reconfigured as MOSI by asserting the output enable oe signal or as MISO by deasserting the oe signal For implementa tio
87. S 8 case2 M 2 S 4 case3 M 4 S 2 or case4 M 8 S 1 Casel M 1 S 8 MO0S7 MOS6 M0S5 M0S4 M0S3 MOS2 MOS1 MOSO jesd204_tx_ datain 127 0 Case2 M 2 S 4 M1S3 M182 MISI M1S0 MOS3 MO0S2 f F14F15 F12F13 MOS1 MOSO F10F11 Case3 M 4 S 2 M3S1 M3S0 M2S1 M2S0 MISI M180 F8F9 F6F7 F4E5 MOS1 MOSO F2F3 FOF1 Case4 M 8 S 1 M7S0 M6S0 M5S0 M4S0 M3S0 M2S0 M1S0 MOSO Lane L3 L2 L1 LO Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 TX Error Reporting 5 23 Data Out F12 F13 F14 F15 Table 5 9 Data Mapping for F 8 L 4 M S 16 for F 8 L 4 Supported M and S F8 F9 F10 F11 F4 F5 F6 F7 FO F1 F2 F3 F 8 supports either casel M 1 S 16 case2 M 2 S 8 case3 M 4 S 4 case4 M 8 S 2 or case5 M 16 S 1 F 8 jesd204_tx_ datain 255 0 F3031 F28F29 F26F27 F24F25 F22F23 F20F21 F18F19 F16F17 F14F15 F12F13 F10F11 F8F9 F6R7 F4F5 F2F3 FOF1 L3 Casel M 1 S 16 L2 M0S15 M0S14 M0S13 M0S12 MOS11 MO0S10 MOS9 MOS8 M0S7 M0S6 MOS5 M0S4 M0S3 M0S2 MOS1 MOSO Ll LO Lane Data Out at linkclk TO F24 F25 F26 F27 F16 F17 F18 F19 F8 F9 F10 F11 F0 F1 F2 F3 Data Out at linkclk T1 F28 F29 F30 F31 F20 F21 F22 F23 F12 F13 F14 F15 F4 F5 F6 F7 TX Error Repor
88. S OUTPU WIDTH parameter as well as the M and S parameters When CS is 0 the T BUS control data is one bit wide tie the signal to 0 WIDTH N CS If CS 0 the bus width 1 Otherwise the bus width OUTPUT BUS WIDTH N CS while OUTPUT BUS WIDTH N M S Table 5 12 Deassembler Signals Control Unit el inke be Input RX link clock signal This clock is equal to the RX data rate divided by 40 This clock is synchronous to the rxframe_clk signal rxframe_clk Input RX frame clock used by the deassembler The frequency is a function of parameters F F1_ FRAMECLK_DIV F2_FRAMECLK_DIV and rxlink_clk This clock is synchronous to the rxlink_clk signal rexel wine esw do gex m eerte Input Reset for the RX link clock domain logic in the deassembler This reset is an active low signal and the deassertion is synchronous to the rising edge of ex larik Cll rxframe_rst_n rxframe clk Input Reset for the RX frame clock domain logic in the deassembler This reset is an active low signal and the deassertion is synchronous to the rising edge of rxframe clk Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 RX Path 5 27 Between Avalon ST and Transport Layer RX data to the Avalon ST source interface The jesd204_rx_ rxframe_clk Output dataout OUTPUT_BUS_ transport layer arranges the data in a spec
89. a format is big endian where the earliest octet is placed in bit 31 24 and the latest octet is placed in bit 7 0 jesd204_rx_link_valid 1 Output Indicates whether the data to the transport layer is valid or invalid The Avalon ST source interface in the RX core cannot be backpressured and will transmit the data when the jesd204_rx_data_ valid signal is asserted e 0 data is invalid e 1 data is valid jesd204_rx_link_ready 1 Input Indicates that the Avalon ST sink interface in the transport layer is ready to receive data jesd204_rx_frame_error 1 Signal Width Avalon MM Interface Input Direction Indicates an empty data stream due to invalid data This signal is asserted high to indicate an error during data transfer from the RX core to the transport layer Description Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Receiver 4 39 EENE M jesd204_rx_avs_clk Input The Avalon MM interface clock signal This clock is asynchronous to all the functional clocks in the JESD204B IP core The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz jesd204_rx_avs_rst_n Input This reset is associated with the jesd204 rx avs clk signal This reset is an active low signal You can assert this reset signal asynchronously but must deassert it synchronously t
90. accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01142 3 2 Installing and Licensing IP Cores 2015 05 04 Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license Some Altera MegaCore IP functions require that you purchase a separate license for production use However the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software After you are satisfied with functionality and perfformance visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 3 1 IP Core Installation Path acds quartus Contains the Quartus II software iip Contains the Altera IP Library and third party IP cores _ altera Contains the Altera IP Library source code T IP
91. ade required f Amy nave phy arria 10 Transceiver Native PHY 14 2 amia 10 Upgrade details elei Upgrade El A my sdi2 spi 141 Arria 10 optional amp E my viterbi Viterbi 141 Arria 10 1 Warning Upgrading IP components changes your design files Altera recommends archiving your design before upgrading IP components Archive Help Perform Automatic Upgrade Close Runs Auto Upgrade on all supported outdated cores Opens editor for manual IP upgrade Note IP cores older than Quartus II software version 12 0 do not support upgrade Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core The Altera IP Release Notes reports any verification exceptions for Altera IP cores Altera does not verify compilation for IP cores older than the previous two releases Related Information Altera IP Release Notes Altera Corporation C Getting Started Send Feedback UG 01142 2015 05 04 IP Catalog and Parameter Editor 3 5 IP Catalog and Parameter Editor The Quartus II IP Catalog Tools gt IP Catalog and parameter editor help you easily customize and integrate IP cores into your project You can use the IP Catalog and parameter editor to select customize and generate files representing your custom IP variation Note The IP Catalog Tools gt IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection an
92. airly consistent within 2 counts variation from one power cycle to another power cycle In the following examples the parameter values are L gt 1 F 1 and K 32 The legal values of the LMFC counter is 0 to FxK 4 1 which is 0 to 7 In Figure 6 2 the latest arrival lane variation falls within 1 local multi frame period In this scenario if latency is not a concern you can leave the default value of csr rbd offset 0 which means the RBD elastic buffer is released at the LMFC boundary In Figure 6 3 the latest arrival lane variation spans across 2 local multi frames the latest arrival lane variation happens before and after the LMFC boundary In this scenario you need to configure the RBD offset correctly to avoid lane de skew error as indicated in bit 4 of xx erro register Altera Corporation JESD204B IP Core Deterministic Latency Implementation Guidelines C Send Feedback UG 01142 2015 05 04 Programmable RBD Offset 6 3 Figure 6 2 Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi Frame Scenario In this example the SYSREF pulse at rx_sysref port of the IP core is sampled by the internal register After 2 link clock cycles the LMFC counter resets The delay from SYSREF sampled high to LMFC counter resets is deterministic The transition of K character to R character marks the beginning of ILAS phase The number of LMFC count of the R character relative to the next LMFC boundary in the latest arrival
93. ame rate as the frame clock The JESD204B transport layer in the design example also supports running the frame clock in half rate or quarter rate by using the FRAMECLK_ DIV parameter The JESD204B transport layer requires both the link clock and frame clock to be synchronous For more information refer to the F1 F2 FRAMECLK DIV parameter description and its relationship to the frame clock TX RX Transceiver Serial Clock and Parallel Clock Internally derived from the data rate during IP core generation The serial clock is the bit clock to stream out serialized data The transceiver PLL supplies this clock and is internal to the transceiver The parallel clock is for the transmitter PMA and PCS within the PHY This clock is internal to the transceiver and is not exposed in the JESD204B IP core For Arria V and Stratix V devices these clocks are internally generated as the transceiver PLL is encapsulated within the JESD204B IP core s PHY For Arria 10 devices you need to generate the transceiver PLL based on the data rate and connect the serial and parallel clock These clocks are referred to as serial clk and bonding clock in Arria 10 devices Refer to the Arria10 Transceiver PHY IP Core User Guide for more information JESD204B IP Core Functional Description LJ Send Feedback Altera Corporation 4 20 Device Clock UG 01142 2015 05 04 TX RX PHY Clock txphy_clk rxphy_clk Data rate 40 The l
94. and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA UG 01142 8 2 JESD204B IP Core Document Revision History 2015 05 04 ERLENE OMEN KH December 2014 Altera Corporation 2014 12 15 Updated the JESD204B IP Core FPGA Performance table with the data rate range Updated the JESD204B IP Core FPGA Resource Utilization table Updated the JESD204B IP Core Parameters table with the following changes e Revised the parameter name of Enable PLL CDR Dynamic Reconfiguration to Enable Transceiver Dynamic Reconfigura tion e Added information for a new parameter Enable Altera Debug Master Endpoint e Added details ab
95. ansmitter inserts this character at the end of frame The A character indicates the end of multi frame The character replace ment algorithm depends on whether scrambling is enabled or disabled regardless of the csr lane sync en register setting The alignment detection process e ftwo successive valid alignment characters are detected in the same position other than the assumed end of frame without receiving a valid or invalid alignment character at the expected position between two alignment characters the receiver realigns its frame to the new position of the received alignment characters e Iflane realignment can result in frame alignment error the receiver issues an error In the JESD204 RX IP core the same flexible buffer is used for frame and lane alignment Lane realign ment gives a correct frame alignment because lane alignment character doubles as a frame alignment character A frame realignment can cause an incorrect lane alignment or link latency The course of action is for the RX to request for reinitialization through svuc x 7 Lane Alignment After the frame synchronization phase has entered rs para the lane alignment is monitored via A character K28 3 at the end of multi frame The first A detection in the ILAS phase is important for the RX core to determine the minimum RX buffer release for inter lane alignment There are two types of error that is detected in lane alignment phase e Arrival of A c
96. ates the PLL clock frequencies e device clock transceiver reference clock frequency 153 6 MHz e link clock 6144 40 153 6 MHz e frame clock 153 6 x 32 8 x 2 307 2 MHz JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 4 PLL Reconfiguration 2015 05 04 Related Information e Clocking Scheme on page 4 18 More information about the JESD204B IP core clocks PLL Reconfiguration The PLL reconfiguration utilizes the ALTERA PLL RECONFIG IP core to implement reconfiguration logic to facilitate dynamic real time reconfiguration of PLLs in Altera devices You can use this megafunc tion IP core to update the output clock frequency PLL bandwidth and phase shifts in real time without reconfiguring the entire FPGA The design example uses the MIF approach to reconfigure the core PLL The ALTERA PLL RECONFIG IP core has two parameter options Enable MIF Streaming and Path to MIF file for the MIF input Turn on Enable MIF Streaming option and set the core pll mif as the value to Path to MIF file parameter The following PLL reconfiguration Avalon MM operations occurs during data rate reconfiguration Table 5 1 PLL Reconfiguration Operation Operation Avalon MM Byte Interface Address Signal Offset 6bits Arria V and Stratix V Devices Set MIF base address pll mgmt 0x01F 8 0 0x000 maximum configuration or 0x02E downscale configuration Write to the START
97. ation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 RX Error Reporting 5 35 Table 5 16 Data Mapping for F 8 L 4 Lane L3 L2 L1 LO Data In linkclk F24 F25 F26 F16 F17 F18 F8 F9 F10 F11 F0 EL F2 F3 TO F27 F19 Data In linkclk F28 F29 F30 F20 F21 F22 F12 F13 F14 FA F5 F6 F7 Tl F31 F23 F15 Supported M M S 16 for F 8 L 4 and S F 8 supports either casel M 1 S 16 case2 M 2 S 8 case3 M 4 S 4 case4 M 8 S 2 or case5 M 16 S 1 F 8 jesd204_rx Casel M 1 S 16 M0S15 M0S14 M0S13 M0S12 MOS11 dataout 255 0 M0S10 M0S9 MOS8 M0S7 MOS6 MOSS F3031 MOSA MOS3 M0S2 MOSI MOSO F28F29 F26F27 F24F25 F22F23 F20F21 F18F19 F16F17 F14F15 F12F13 F10F11 F8F9 F6F7 F4F5 F2F3 FOF1 RX Error Reporting For RX path error reporting the transport layer expects the AL to always be ready to sample the RX data as indicated by the jesd204_rx_data_ready signal equal to 1 as long as the jesd204_rx_data_valid remains asserted If the jesd204_rx_data_ready signal unexpectedly deasserts the transport layer reports the error to the DLL by asserting the 3esa204 rx link error signal as shown in the timing diagram below Figure 5 12 RX Error Reporting jesd204 rx data ready jesd204 rx data valid l l
98. atus Registers 9 On Off Turn on this option to enable soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug Signals include rx_is_ locktoref rx_is_locktodata tx_cal_busy rx_cal_busy rx serial loopback set rx locktodata set rx locktoref tx analogreset tx digitalreset rx analogreset and rx digitalrest For more information refer to the Arria 10 Transceiver User Guide Enable Prbs Soft Accumulators 9 On Off JESD204B Configurations Tab Turn on this option to set the soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker Lanes per converter device 1 8 Set the number of lanes per converter device 0 L Converters per device M 1 256 Set the number of converters per converter device Enable manual F configu On Off Turn on this option to set parameter F in manual mode maton and enable this parameter to be configurable Otherwise the parameter F is in derived mode You have to enable this parameter and configure the appropriate F value if the transport layer in your design is supporting Control Word CF and or High Density format HD Note The auto derived F value using formula F M S N 8 L may not apply if parameter CF and or parameter HD are enabled Octets per frame F 1 2 4 256 The number of octets per frame derived from the formula of F M N S 8 L Converter resolut
99. aximum requirements For example the ADC AD9250 has a minimum sampling rate of 40 Msps For L 2 M 1 configuration the minimum data rate of this ADC is calculated this way 40 1 16 22 Minimum AD9250 data rate 400 Mbps The minimum data rate for the JESD204B link is effectively 611 Mbps Check these items e Reduce the data rate or sampling clock frequency if your targeted operating requirement does not work e Verify the minimum and maximum data rate requirements in the device manufacturer s data sheet Signal Polarity and FPGA Pin Assignment Verify that the transceiver channel pin assignments sync_n and SYSREF for Subclass 1 only device clock and SPI interface are correct Also verify the signal polarity of the differential pairs like sync_n and transceiver channels are correct Altera Corporation JESD204B IP Core Debug Guidelines C Send Feedback UG 01142 2015 05 04 Debugging JESD204B Link Using SignalTap ll and System Console 7 3 Check these items e Review the schematic and board layout file to determine the polarity of the physical pin connection e Use assignment editor and pin planner to check the pin assignment and I O standard for each pin e Use RTL viewer in the Quartus II software to verify that the top level port are connected to the lower level module that you instantiate Debugging JESD204B Link Using SignalTap II and System Console The SignalTap II provides dynamic view of signals
100. buffer 5 LMFC counts before the next LMFC boundary This corresponds to LMFC count of 3 at the current local multi frame In this scenario setting csr_rbd_offset not only optimizes user data latency through the IP core it also resolves the deterministic latency issue Link clock SYSREF pulse is sampled by IP core s internal register TX Sysref la SYNC N deasserted directly SYNC N i H after LMFC boundary 1 link dock period LMFC count 2 link clock cycle deterministic i d delay from SYSREF sampled 2nd LMFC Current LMFC Next LMFC high to LMFC zero crossing Ist LMFC boundary boundary boundary Internal Free running LMFC counter SOT 2 S 0 1 2 Se 7 0 1 2 3 4 5 6 7 0 1 boundary C Counter RBD count 7 7 LMFC counts with Internal LMFC counter resets i i reference to the next i LMFC boundary atest arrival laneinfirst Nh Sh Sh Rh Ri S ata D D D D D D power cycle i RBD count 0 atest arrival laneinsecond MIEL o S eee D D D D D D D power cyde RBD count 1 with reference to the current LMFC boundary atest arrival i D D D D D D D D j oaar hates lanein fifth ni 5 is released at the power cycle DESHSESEPESESEREN S next LMFC j
101. c latency 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S p AN 101 Innovation Drive San Jose CA 95134 UG 01142 1 2 JESD204B IP Core Quick Reference 2015 05 04 ee Dedi O O O Core Features Run time configuration of parameters L M and F e Data rates up to 12 5 gigabits per second Gbps e Single or multiple lanes up to 8 lanes per link e Serial lane alignment and monitoring e Lane synchronization e Modular design that supports multidevic
102. ce are aligned Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Receiver 4 41 SS alldev_lane_aligned Signal CSR Width Input Direction Aligns all lanes for this device For multidevice synchronization multiplex all the dev_lane_aligned signals before connecting to this signal pin For single device support connect the dev_lane_ aligned signal back to this signal Description esr li Output Indicates the number of active lanes for the link The transport layer can use this signal as a run time parameter cer fI Output Indicates the number of octets per frame The transport layer can use this signal as a run time parameter esr ikili Output Indicates the number of frames per multiframe The transport layer can use this signal as a run time parameter csr m Output Indicates the number of converters for the link The transport layer can use this signal as a run time parameter csr esii Output Indicates the number of control bits per sample The transport layer can use this signal as a run time parameter csr n Output Indicates the converter resolution The transport layer can use this signal as a run time parameter esir moll Output Indicates the total number of bits per sample The transport layer can use this signal as a run time parameter
103. ch is the data for the first two link clock cycles The data can be translated to the frame G9 The 2 divi cnt signal is internally generated in the RX control block to correctly stream data to the Avalon ST interface JESD204B IP Core Design Guidelines Altera Corporation LJ Send Feedback F UG 01142 5 32 RX Path Data Remapping 2015 05 04 clock cycle depending on the F and FRAMECLK_DIV parameters selected based on the frame clock to link clock relationship Figure 5 11 RX Data Reception rxframe_clk rxlink_clk rxframe_rst_n ecc ndink rt n Scrambler Corrupted Data jesd204_rx_link_datain 63 0 Junk l Valid Data Junk jesd204_rx_link_data_valid jesd204 rx dataout 15 0 AIL Os i i Valid Data Alls jesd204 rx data valid Related Information Relationship Between Frame Clock and Link Clock on page 5 9 RX Path Data Remapping The JESD204B IP core implements the data transfer in big endian format The RX path data remapping is the reverse of TX path data remapping Refer to Figure 5 7for the RX transport layer remapping operation The following tables show examples of data mapping for L 4 F 1 2 4 8 and M S 2 4 8 16 The configurations that the transport layer support are not limited to these examples Table 5 13 Data
104. d If no error is detected the testbench issues a TESTBENCH PASSED message stating that the simulation was successful If an error is detected the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed Getting Started Altera Corporation LJ Send Feedback JESD204B IP Core Functional Description 2015 05 04 UG 01142 amp Subscribe LJ Send Feedback The JESD204B IP core implements a transmitter TX and receiver RX block Each block has two layers and consists of the following components e Media access control MAC DLL block that consists of the link layer link state machine and character replacement CSR Subclass 1 and 2 deterministic latency scrambler or descrambler and multiframe counter Physical layer PHY PCS and PMA block that consists of the 8B 10B encoder word aligner serializer and deserializer You can specify the datapath and wrapper for your design and generate them separately The TX and RX blocks in the DLL utilizes the Avalon ST interface to transmit or receive data and the Avalon MM interface to access the CSRs The TX and RX blocks operate on 32 bit data width per channel where the frame assembly packs the data into four octets per channel Multiple TX and RX blocks can share the clock and reset if the link rates are the same O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGA
105. d mode the number of TX_PLL is equal to number of lanes The number of reconfiguration interface 2 x number of lanes L The transceiver reconfiguration controller interfaces e MIF Reconfiguration Avalon MM master interface connects to the MIF ROM e Transceiver Reconfiguration interface connects to the JESD204B IP core which eventually connects to the native PHY e Reconfiguration Management Avalon MM slave interface connects to the control unit Note The transceiver reconfiguration controller is only used in Arria V and Stratix V devices For Arria 10 devices the control unit directly communicates with the transceiver in the JESD204B IP core through the recon ig avmm interface signals The following transceiver reconfiguration controller Avalon MM operations are involved during data rate reconfiguration Table 5 2 Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices Operation Avalon MM Byte Address WELT Interface Signal Offset 6bits Write logical channel number reconfig mgmt 0x38 9 0 Write MIF mode reconfig mgmt 0x3A 3 2 2 b00 Write 0 to streamer offset register reconfig mgmt 0x3B 15 0 0 Write MIF base address to streamer reconfig mgmt 0X3C 31 0 32 h1000 data register Initiate a write of all the above data reconfig mgmt 0x3A 0 I b1 Write 1 to streamer offset register reconfig mgmt 0x3B 15 0 1 Write to streamer data r
106. d parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists installed IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter editor prompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following features to help you quickly locate and select an IP core e Filter IP Catalog to Show IP for active device family or Show IP for all device families If you have no project open select the Device Family in IP Catalog e Type in the Search field to locate any full or partial IP core name in IP Catalog e Right click an IP core name in IP Catalog to display details about supported devices open the IP core s installation folder and view links to documentation e Click Search for Partner IP to access partner IP information on the Altera website Getting Started Altera Corporation LJ Send Feedback UG 01142 3 6 Design Walkthrough 2015 05 04 Figure 3 3 Quartus II IP Catalog IP Catalog i Eg Device Family Cyclone V E GX GT SX SE ST m di distin Ui bor Od nari dr oes v d
107. data Signal Clock Domain Direction Description Between Transport Layer and DLL JESD204B IP Core Design Guidelines CJ Send Feedback Altera Corporation UG 01142 5 14 TX Path 2015 05 04 Jesd204_ ta link txlink_clk Output Indicates transmitted data from the transport datain L 32 1 0 layer to the DLL at tx1ink_c1k clock rate where four octets are packed into a 32 bit data width per lane The data format is big endian The table below illustrates the data mapping for L 4 jesd204_tx_link_datain x y 31 0 0 63 32 1 95 64 2 127 96 3 Connect this signal to the TX DLL jesa204 tx link data input pin jesd204 tx link pis cii Output Indicates whether the 3esa204 tx link data valid datain is valid or invalid e 3jesd204 tx link datain is invalid e 1 jesd204 tx link datain is valid Connect this signal to the TX DLL jesa204 tx link validinput pin jesd204 tx link exc Latine cilk e Input Indicates that the DLL requires valid data at the coni npn subsequent implementation specific duration Connect this signal to the TX DLL jesd204_tx_ frame ready output pin jesd204 tx link iiic eik Output Indicates an error at the Avalon ST source error interface Specifically this signal is asserted when jesd204 tx data valid 0 while jesd204_ tx data ready 1 The DLL subsequently reports this error to the CSR block Connect this signal to the TX DLL jesa204 tx
108. device CS Number of control bits per sample N Converter resolution 8 SUBCLASSV 2 0 N PRIME 4 0 SUBCLASSV Subclass version N_PRIME Total bits per sample 9 JESDV 2 0 S 4 0 JESDV JESD204 version S Number of samples per converter per frame 10 HD 0 0 CF 4 0 HD High Density data format CF Number of control words per frame clock per link 09 Applies to Subclass 2 only Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 User Data Phase 4 7 Configura onfigura 0000 0 0 BIS ooo m zs ISSN EO esos Oe a ELEC Vic 11 RES1 7 0 RESI Reserved Set to 8 h00 12 RES2 7 0 RES2 Reserved Set to 8 h00 13 FCHK 7 0 automatically calculated using run time ECHIK siihe modius 2 of the configuration sum of the 13 configuration octets above If you change any of the octets during run time make sure to update the new FCHK value in the register The JESD204 TX IP core also supports debug feature to continuously stay in ILAS phase without exiting You can enable this feature by setting the bit in csr_ilas_loop register There are two modes of entry e RX asserts sync_n and deasserts it after CGS phase This activity triggers the ILAS phase and the CSR will stay in ILAS phase indefinitely until this setting changes e Link reinitialization through CSR is initiated The JESD204B IP core transmits
109. directory ed synth to go to the specified directory Typequartus sh t gen ed quartus synth tcl to generate the JESD204B design example for compilation Compiling the JESD204B IP Core Design Example You can use the generated qip file to include relevant files into your project Generate the Quartus II synthesis compilation files by running the script gen quartus synth tcl located in the example design directory ed synth directory Note If you use the Quartus II Tcl console to generate the gen quartus synth tcl script close all Quartus II project before you start generating To compile your design using the Quartus II software follow these steps 1 Launch the Quartus II software 2 On the File menu click Open Project gt Select lt example_design_directory gt led_synth example_design 3 4 On the Processing menu click Start Compilation Select jesd204b ed qpf 99 At the end of the compilation the Quartus II software provides a pass fail indication G9 This is the default quartus project file that the Quartus II software automatically generates You can edit this file and the qsf file according to your design preference JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback JESD204B IP Core Deterministic Latency Implementation Guidelines 2015 05 04 UG 01142 amp Subscribe L J Send Feedback Subclass 1 and Subclass 2 modes support deterministic latency This section desc
110. duration for a synchronization request on the syNc_N is five frames plus nine octets Frame Synchronization After CGS phase the receiver assumes that the first non K28 5 character marks the start of frame and multi frame If the transmitter emits an initial lane alignment sequence the first non K28 5 character JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback UG 01142 4 10 Frame Alignment 2015 05 04 will be K28 0 Similar to the JESD204 TX IP core the csr_lane_sync_en is set to 1 by default thus the RX core detects the K character to R character transition If the csr_lane_sync_en is set to 0 the RX core detects the K character to the first data transition An ILAS error and unexpected K character is flagged if either one of these conditions are violated When csr_lane_sync_en is set to 0 you have to disable data checking for the first 16 octets of data as the character replacement block takes 16 octets to recover the end of frame pointer for character replace ment When csr_lane_sync_en is set to 1 default JESD204B setting the number of octets to be discarded depends on the scrambler or descrambler block The receiver assumes that a new frame starts in every F octets The octet counter is used for frame alignment and lane alignment Related Information e Scrambler Descrambler on page 4 14 Frame Alignment The frame alignment is monitored through the alignment character F The tr
111. e San Jose CA 95134 UG 01142 7 2 SPI Programming 2015 05 04 Check these items e Turn off the scrambler and descrambler options as needed e Use single lane configuration and K 32 value to isolate multiple lane alignment issue e Use Subclass 0 mode to isolate SYSREF related issues like setup or hold time and frequency of SYSREF pulse SPI Programming The SPI interface configures the converter Hence it is important to check the SPI programming sequence and register bit settings for the converter If you use the MIF to store the SPI register settings of the converter mistakes may occur when modifying the MIF for example setting a certain bit to 1 instead of 0 missing or extra bits in a MIF content row Check these items e For example in the ADI AD9250 converter Altera recommends that you first perform register bit setting for the scramble SCR or lane L register at address Ox6E before setting the quick configura tion register at address Ox5E e Determine that each row of the MIF has the same number of bits as the data width of the ROM that stores the MIF Converter and FPGA Operating Conditions The transceiver channels at the converter and FPGA are bounded by minimum and maximum data rate requirements Always check the most updated device data sheet for this info For example the Arria V GT device has a minimum data rate of 611 Mbps Ensure that the sampling rate of the converter is within the minimum and m
112. e CF 0 Control bits are added if CS gt 1 Depending on the value of CS and N the number of tail bits added is N N CS For example N 16 N 12 and CS 2 the number of tail bits added to form a nibble group NG is 2 The JESD204B IP core implements the data transfer in big endian format Data is reshuffled in big endian format before crossing to the link clock domain through an adaptor The data is arranged so that the LO is always on the right LSB in the data bus interfacing with the JESD204B IP core In big endian implementation the oldest data F0 is placed at the MSB in LO 32 bits or 4 octets of data are transferred to the IP core in one link clock cycle For example of F 8 2 link clock cycles are needed to transfer all 8 octets to the IP core JESD204B IP Core Design Guidelines Altera Corporation C Send Feedback UG 01142 5 20 TX Path Data Remapping 2015 05 04 Figure 5 7 User Data Format that Feeds into the Transport Layer and Output to the Link Layer MSB LSB Application layer or user logic s Avalon ST data bus Sample from the converter is N bits wide Theuserreordersthe 75 data so that MOSO is cad at the LSB and M M 1 S S 1 is at the MSB Data out from the RX has tthe same orientation MOSO at the LSB This Region of the Transport Layer Is in the Frame Clock Domain ea the control bit a Add the tail bit to N 16 The
113. e IP core transmits K character and wait for the receiver to assert SyNC_N to indicate that it has entered cs 1r state e For RX the IP core asserts syNc_N to request for link reinitialization Hardware initiated link reinitialization can be globally disabled through the csx 1ink reinit disable register for debug purposes Hardware initiated link reinitialization can be issued as interrupt depending on the error type and interrupt error enable If lane misalignment has been detected as a result of a phase change in local timing reference the software can rely on this interrupt trigger to initiates a LMFC realignment The realignment process occurs by first resampling SYSREF and then issuing a link reinitialization request Link Startup Sequence Set the run time LMF configuration when the cx1ink rst nOrrxlink rst n signals are asserted Upon txlink rst n Or rxlink rst n deassertion the JESD204B IP core begins operation The following sections describe the detailed operation for each subclass mode TX Subclass 0 Upon reset deassertion the JESD204B TX IP core is in CGS phase sync_n deassertion from the converter device enables the JESD204B TX IP core to exit CGS phase and enter ILAS phase if csr_lane_sync_en 1 or User Data phase if csz 1ane sync en 0 TX Subclass 1 Upon reset deassertion the JESD204B TX IP core is in CGS phase sync_n deassertion from the converter device enables the JESD204B TX IP core to exit CGS phase The IP c
114. e PHY reconfiguration interface with Share Reconfiguration Interface enabled for multiple channels Enable Altera Debug On Off Turn on this option for the Transceiver Native PHY IP core to Master Endpoint include an embedded Altera Debug Master Endpoint ADME This ADME connects internally to the Avalon MM slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver It can perform certain test and debug functions via JTAG using System Console This parameter is valid only for Arria 10 devices and when you turn on the Enable Transceiver Dynamic Reconfiguration parameter Enable Capability On Off Turn on this option to enable capability registers which Registers 19 provides high level information about the transceiver channel s configuration Set user defined IP 0 255 Set a user defined numeric identifier that can be read from the identifier user identifer offset when you turn on the Enable Capability Registers parameter 03 To perform dynamic reconfiguration you have to instantiate the Transceiver Reconfiguration Controller from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr and reconfig from xcvr interface 9 To support the Transceiver Toolkit in your design you must turn on this option Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 JESD204B IP Core Parameters 3 19 Enable Control and St
115. e ROM on per word basis and write to the SPI master for SPI write transaction to the external SPI slave b Perform a read transaction from the next ROM and perform the same SPI write transaction to next SPI slave 2 Initialize the JESD204B IP base core transport layer pattern generator and pattern checker upon successful initialization of the transceiver JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 40 System Parameters System Parameters Table 5 18 System Parameter Settings UG 01142 2015 05 04 This table lists the parameters exposed at the system level LINK Number of JESD204B link One link represent one JESD204B instance L 1 2 4 8 2 Number of lanes per converter device M 12 48 2 Number of converters per device F 1 2 4 8 2 Number of octets per frame S 1 2 1 Number of transmitted samples per converter per frame N 12 16 16 Number of conversion bits per converter N 16 16 Number of transmitted bits per sample in the user data format Fl FRAMECIK 1 4 4 The divider ratio on rame c1k when F 1 The transport DIV layer uses the post divided rame cix F2_FRAMECLK_ 1 2 2 The divider ratio on rame c1k when F 2 The transport DIV layer uses the post divided rame cik POLYNOMIAL 7 9 15 23 7 Defines the polynomial length for the PRBS pattern generator LENGTH 31 and checker which is also the equivalent number of stages for
116. e final clock names and paths are not yet known Therefore the Quartus II software cannot incorporate the final signal names in the sdc file that it automatically generates Instead you must manually modify the clock signal names in this file to integrate these constraints with the timing constraints for your full design This section describes how to integrate the timing constraints that the Quartus II software generates with your IP core into the timing constraints for your design The Quartus II software automatically generates the altera jesd204 sdc file that contains the JESD204B IP core s timing constraints Three clocks are created at the input clock port e JESD204B TX IP core e txlink clk e reconfig to xcvr 0 for Arria V Cyclone V and Stratix V devices only e reconfig clk for Arria 10 device only e tx avs clk e JESD204B RX IP core e rxlink clk e reconfig to xcvr 0 for Arria V Cyclone V and Stratix V devices only e reconfig clk for Arria 10 device only e rx avs clk In a functional system design these clocks except for xecon ig to xcvr 0 clock are typically provided by the core PLL Getting Started Altera Corporation LJ Send Feedback I UG 01142 3 14 Timing Constraints For Input Clocks 2015 05 04 In the sdc file for your project make the following command changes e Specify the PLL clock reference pin frequency using the create_clock command e Derive the PLL generated output clocks from
117. e grouped and synchronized together Table 4 2 Example of SYSREF Frequency Calculation In this example you can choose to perform one of the following options e provide two SYSREF and device clock where the ADC groups share both the device clock and SYSREF 18 75 MHz and 9 375 MHz e provide one SYSREF running at 9 375 MHz and device clock for all the ADC and DAC groups because the SYSREF period in the DAC is a multiplication of n integer ADC Group 1 2 ADCs LMF 222 6 GHz 40 2 x 16 4 18 75 MHz K 16 e Data rate 6 Gbps ADC Group 2 2 ADCs LMF 811 6 GHz 40 1 x 32 4 18 75 MHz e K 32 e Data rate 6 Gbps DAC Group 3 2 DACs IME 222 3 GHz 40 2 x 16 4 9 375 MHz K 16 e Data rate 3 Gbps Subclass 2 The JESD204 IP core maintains a LMFC counter that counts from 0 to F x K 4 1 and wraps around again The LMFC count starts upon reset and the logic device always acts as the timing master The converters adjust their own internal LMFC to match the master s counter The alignment of LMFC within the system relies on the correct alignment of SYNC_N signal deassertion at the LMFC boundary The alignment of LMFC to RX logic is handled within the TX converter The RX logic releases SYNC_N at the LMFC tick and the TX converter adjust its internal LMFC to match the RX LMFC JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback 4 14 Scrambler Descramb
118. e nearest 10 Note The resource utilization data are extracted from a full design which includes the Altera Transceiver PHY Reset Controller IP Core Thus the actual resource utilization for the JESD204B IP core should be smaller by about 15 ALMs and 20 registers Device Family Data Path Number of ALMs ALUTs Logic Memory Block Lanes Registers M10K M20K 9 7 1 1047 1543 1200 1 2 1594 2325 1825 2 RX 4 2832 4043 3080 4 8 5354 7525 5585 8 Cyclone V 1 728 1148 948 0 2 889 1424 1066 0 TX 4 1218 1941 1293 0 8 1715 2837 1757 0 1 1052 1543 1197 1 2 1586 2325 1823 2 RX 4 2830 4043 3077 4 8 5330 7525 5584 8 Arria V 1 719 1148 947 0 2 887 1424 1062 0 TX 4 1208 1941 1292 0 8 1724 2853 1754 0 1 1062 1542 1215 0 2 1634 2363 1858 0 RX 4 2934 4097 3141 0 8 5526 7697 5711 0 Arria V GZ 1 728 1150 948 0 2 937 1488 1083 0 TX 4 1365 2114 1354 0 8 2141 3417 1895 0 MIOK for Arria V device M20K for Arria V GZ Stratix V and Arria 10 devices Altera Corporation About the JESD204B IP Core C Send Feedback UG 01142 2015 05 04 Performance and Resource Utilization Device Family Data Path Number of ALMs ALUTs Logic Memory Block Lanes Registers M10K M20K 9 7 1043 1504 1194 2 1575 2265 1815 0 RX 4 2828 3927 3060 0 8 5356 7347 5546 0 1 695 1092 931 0 2 878 1373 1049 0 TX 4 1240
119. e simulation automatically providing a pass fail indication on completion To simulate the design using the Aldec Riviera PRO simulator follow these steps 1 Start the Aldec Riviera PRO simulator 2 On the File menu click Change Directory Select example design directory ed sim testbench aldec 3 On the Tools menu click Execute Macro Select run tb top tcl This file compiles the design and runs the simulation automatically providing a pass fail indication on completion Generating the Design Example For Compilation Use the gen quartus synth tcl script to generate the JESD204B design example for compilation Note If you use the Quartus II Tcl console to generate the gen quartus synth tcl script close all Quartus II project before you start generating Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Compiling the JESD204B IP Core Design Example 5 57 To run the Tcl script using the Quartus II sofware follow these steps 1 2 3 4 Launch the Quartus II software On the View menu click Utility Windows and select Tcl Console In the Tcl Console type cd example design directory ed synth to go to the specified directory Type source gen quartus synth tcl to generate the JESD204B design example for compila tion To run the Tcl script using the command line follow these steps Obtain the Quartus II software resource Typecd example design
120. e simulation files To run the Tcl script using the command line follow these steps 1 Obtain the Quartus II software resource 2 Typecd example design directory ed simto go to the specified directory 3 Typequartus sh t gen ed sim verilog tcl Verilog or quartus sh t gen ed sim vhdl tcl VHDL to generate the simulation files Simulating the JESD204B IP Core Design Example By default the Quartus II software generates simulator specific scripts containing commands to compile elaborate and simulate Altera IP models and simulation model library files You can copy the commands into your simulation testbench script or edit these files to add commands for compiling elaborating and simulating your design and testbench To simulate the design using the ModelSim Altera SE AE simulator follow these steps 1 Start the ModelSim Altera simulator 2 On the File menu click Change Directory gt Select example design directory ed sim testbench mentor 3 Onthe File menu click Load Macro file Select run tb top tcl This file compiles the design and runs the simulation automatically providing a pass fail indication on completion To simulate the design using the VCS MX simulator in Linux follow these steps 1 Start the VCS MX simulator 2 On the File menu click Change Directory gt Select example design directory ed sim testbench synopsys vcsmx 3 Run run tb top sh This file compiles the design and runs th
121. e synchronization MAC and PHY partitioning e Deterministic latency support e 8B 10B encoding e Scrambling Descrambling e Avalon Streaming Avalon ST interface for transmit and receive datapaths e Avalon Memory Mapped Avalon MM interface for Configuration and Status registers CSR e Dynamic generation of simulation testbench Typical Application e Wireless communication equipment IP Core e Broadcast equipment Information e Military equipment e Medical equipment e Test and measurement equipment Device Family Support e Cyclone V FPGA device families e Arria V FPGA device families e Arria V GZ FPGA device families e Arria 10 FPGA device families e Stratix V FPGA device families Refer to the device support table andWhat s New in Altera IP page of the Altera website for detailed information Design Tools e Osys parameter editor in the Quartus II software for design creation and compilation e TimeQuest timing analyzer in the Quartus II software for timing analysis e ModelSim Altera Aldec Riviera Pro VCS VCS MX and NCSim software for design simulation or synthesis Related Information e Altera Software Installation and Licensing e What s New in Altera IP Altera Corporation JESD204B IP Core Quick Reference C Send Feedback About the JESD204B IP Core 2015 05 04 UG 01142 amp Subscribe L J Send Feedback The Altera JESD204B IP core is a high speed point to point serial interface for di
122. eassertion of txframe_rst_n signal the link s 3esa204 tx link early reaGy signal equals to 1 This setting activates the TL to start sampling 3esd204 tx datain signal from the Avalon ST interface and transmits sampled data jesa204 tx link datain to the TX link The TX link only captures valid data from the TL when the jesd204 tx link ready signal equals to 1 in user data phase This means all the data transmitted from the TL before jesa204 tx link ready signal equals to are ignored JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 18 TX Path Data Remapping Figure 5 5 TX Data Transmission UG 01142 2015 05 04 txframe_clk i txlink_clk txframe rst n jesd204 tx datavalid TL jesd204 tx link early ready tdink rst n j jesd204 tx datain 15 0 Junk l Valid Data l LINK jesd204_tx_link_ready jesd204_tx_link_datain 31 0 Figure 5 6 TX Data Transmission For F 8 Dunk SampledData ValidData txlink_clk txframe_clk j txframe rst n txlink rst n M X jesd204 tx datavalid jesd204 tx link early ready jesd204 tx datain 63 0 LINK jesd204 tx link ready jesd204 tx link datain 31 0 TX Path Data Remappi
123. egister to set up reconfig mgmt 0x3C 31 0 3 MIF streaming Initiate a write of all the above data to reconfig_mgmt_ 0x3A 0 I b1 start streaming the MIF Read the busy bit to determine when reconfig mgmt 0x3A 8 1 Busy the write has completed 0 Operation completed Note The above steps are repeated for the number of channels and followed by the number of TX_PLLs JESD204B IP Core Design Guidelines J send Feedback Altera Corporation UG 01142 5 6 Transceiver Reset Controller 2015 05 04 For Arria 10 devices the only Avalon MM operation is a direct write to the transceiver register through the reconfig avmm interface at the JESD204B IP core Every line in the MIF is DPRIO_ADDR 25 16 BIT MASK 15 8 DATA 7 0 The control unit maps the DPRIO ADDR to reconfig avmm address and BIT MASK amp DATA to reconfig avmm data Related Information e Altera Transceiver PHY IP Core User Guide More information about the transceiver reconfiguration controller e Altera Arria 10 Transceiver PHY IP Core User Guide Transceiver Reset Controller The transceiver reset controller uses the Altera s Transceiver PHY Reset Controller IP Core to ensure a reliable initialization of the transceiver The reset controller has separate reset controls per channel to handle synchronization of reset inputs hysteresis of PLL locked status and automatic or manual reset recovery mode In this d
124. eight octets In a typical application where the reset value of the scrambler seed is different from the converter device to FPGA logic device the correct user data is recovered in the receiver in two link clocks due to the 32 bit architecture The PRBS pattern checker on the transport layer should always disable checking of the first eight octets from the JESD204 RX IP core SYNC_N Signal For Subclass 0 implementation the svNc n signal from the DAC converters in the same group path must be combined In some applications multiple converters are grouped together in the same group path to sample a signal referred as multipoint link The FPGA can only start the LMFC counter and its transition to ILAS after all the links deassert the synchronization request The JESD204B TX IP core provides three signals to facilitate this application The sync_w is the direct signal from the DAC converters The error signaling from syNc_N is filtered and sent out as dev sync n signal For Subclass 0 you need to multiplex all the dev sync n signals in the same multipoint link and then input them to the IP core through naev sync n signal Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 JESD204B IP Core Functional Description SYNC_N Signal 4 15 Figure 4 6 Subclass 0 Combining the sync_n Signal for JESD204B TX IP Core
125. eport an error through sync_n signaling Instead the RX IP core issues an interrupt when any error is detected You can check the csz x err csr rx err0 andcsr rx erri register status to determine the error types Clocking Scheme This section describes the clocking scheme for the JESD204B IP core and transceiver Table 4 3 JESD204B IP Core Clocks TX RX Device Clock PLL selection during IP core generation pll ref clk The PLL reference clock used by the TX Transceiver PLL or RX CDR This is also the recommended reference clock to the Altera PLL IP Core for Arria V or Stratix V devices or Altera IOPLL for ArrialO devices Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Clocking Scheme 4 19 TX RX Link Clock Data rate 40 The timing reference for the JESD204B IP core The link clock runs at data rate 40 because the IP core is talink elk operating in a 32 bit data bus architecture after 8B elini elk 10B encoding The JESD204B transport layer in the design example requires both the link clock and frame clock to be synchronous TX RX Frame Clock Data rate 10 x F The frame clock as per the JESD204B specification in design example txframe_clk rxframe clk This clock is applicable to the JESD204B transport layer and other upstream devices that run in frame clock such as the PRBS generator checker or any data processing blocks that run at the s
126. er resets two link clock cycles after SYSREF is sampled The LMFC phase offset between the LMFC counter at ADC and FPGA is 3 5 link clock cycles Because SYNC_N deassertion is detected after the second LMFC boundary at ADC ILAS transmission 9 In this example the ILAS arrives at the IP core s RBD elastic buffer within one local multi frame In other system the arrival at the RBD elastic buffer could span more than one local multi frame Assuming csr rbd offset 0 RBD elastic buffer may be released at the third or fourth LMFC boundary due to power cycle variation 10 Setting csr Imfc offset 5 resets the LMFC counter to the value of 5 11 The first LMFC boundary is delayed by three link clock cycles 12 The third LMFC boundary has been delayed past the latest arrival lane power cycle variation The RBD elastic buffer is always released at the third LMFC boundary SYSREF pulse is G sampled by ADC LS First LMFC Second LMFC Third LMFC Fourth LMFC PNS ME boundary boundary E boundary lie boundary ADC NE e Internal lt Xo 1 2 3 4 5 6 TX SKS TX 1 2 3 4 7 X 0 1 LMFC Counter lt 7 T Free running LMFC countet Internal p MEC counter resets i SYNC N deassertion is detected by ADC 399 SYNC N if ILAS transmission by ADC arrival at TX i 8 L Transmit c Janis Kk
127. ere there are multiple ADC and DAC converters you need to use the Quartus II software to merge the transceivers and group them into the transceiver architecture For example to create two instances of the JESD204B TX IP core with four lanes each and four instances of the JESD204 RX IP core with two lanes each you can apply one of the following options e MAC and PHY option 1 Generate JESD204B TX IP core with four lanes and JESD204B RX IP core with two lanes 2 Instantiate the desired components 3 Use the Quartus II software to merge the PHY lanes e MAC only and PHY only option based on the configuration above there are a total of eight lanes in duplex mode 1 Generate the JESD204B Duplex PHY with a total of eight lanes TX skew is reduced in this configuration as the channels are bonded 2 Generate the JESD204B TX MAC with four lanes and instantiate it two times 3 Generate the JESD204B RX MAC with two lanes and instantiate it four times 4 Create a wrapper to connect the JESD204B TX MAC and RX MAC with the JESD204B Duplex PHY Note Ifthe data rate for TX and RX is different the transceiver does not allow duplex mode to generate a duplex PHY In this case you have to generate a RX only PHY on the RX data rate and a TX only PHY on the TX data rate About the JESD204B IP Core Altera Corporation CJ Send Feedback 2 4 JESD204B IP Core Configuration JESD204B IP Core Configuration Table 2 1 JESD204B IP Core Confi
128. es uiridi tirer reti puse ioter ioa ddp eiiie 5 1 esten Example ConpoORENSo qoom odori tna es bea URDU RU PARERE NUN LORD PN RD e S ipi 5 3 System Parameters icona eiecit ee co ERE e Ue ege ete oue 5 40 System Interface Signals ausn ausos trn aie t end cr eb Ple Soria b RR RHENO Sce ert 5 44 Example Feature Dynamic Reconfigutatiofi usas eei e rie priis eren RH RE Rhep OU 5 49 Generating and Simulating the Design Example sesenta bte ten p rH qi rn MER 5 55 Generating the Design Example For Compilatioti riter ritenuta ER ihs etd 5 56 Compiling the JESD204B IP Core Design Example icri ttn etta ttes heben einen 5 57 JESD204B IP Core Deterministic Latency Implementation Guidelines 6 1 Constraining Incoming SYSREP Signal iencescitsn n HE RIpOR RR I RR AS NONU INE 6 1 Programmable RBD OBSEDsgecbesdustdveneit pilis hdapte deed QSe cmd ee AEE Eea roin Ub EA d pud 6 2 Programmable LMFG Offset sssri ierastos quud AEE e i qvid OR x una E ee SE 6 5 JESD204B IP Core Debug Guidelines cissssscccsscsssesssnsseussndsnacsedsevsiisessscdsennsessvessaves 7 1 i odabTuAcdilzu M T M 7 1 JESD204B Paranietets 2 th ne ire rp rr atr rtt eir tate e her arde Drei c GER E Ed Edd 7 1 SPI Programming E 7 2 Converter and FPGA Operating COHGOGIUOBS esci rss reas eheu rho ap iid dua hi M Roe e ERR 7 2 Signal Polarity and FPGA Pin Asst oi aie nl o ence mer prex trae alb anis a Qu
129. esign example the reset controller targets both the TX and RX channels The TX PLL TX Channel and RX Channel parameters are programmable to accommodate single and multiple 2 JESD204B links Related Information e Altera Transceiver PHY IP Core User Guide More information about the Transceiver PHY Reset Controller IP Core e Arria V Device Handbook Volume 2 Transceivers More information about the device usage mode Pattern Generator The pattern generator instantiates any supported generators and has an output multiplexer to select which generated pattern to forward to the transport layer based on the test mode during run time Additionally the pattern generator also supports run time reconfiguration downscale on the number of converters per device M amp samples per converter per frame S The pattern generator can be a parallel PRBS alternate checkerboard or ramp wave generator The data output bus width of the pattern generator is equivalent to the value of FRAMECLK_DIV xM xS xN The pattern generator includes a REVERSE_DATA parameter to control data arrangement at the output The default value of this parameter is 0 e 0 no data rearrangement at the output of the generator e 1 data rearrangement at the output of the generator For example when M 2 S 1 N 16 F1 F2 FRAMECLK DIV 1 the input or output data width equals to 31 0 with the following data arrangement 0 m1s0 31 16 m0s0 15 0 1 m0s0 31 16 m1
130. etween the TX and RX LMFC counters in the both ends of the JESD204B link contributes to deterministic latency uncertainty The phase offset is caused by e SYSREF trace length mismatch in the PCB between the TX and RX devices FPGA and converters e delay differences in resetting the LMFC counter when SYSREF pulses are detected by the FPGA and converter devices The RX device in the JESD204B link is responsible for deterministic latency adjustments The following figure illustrates the adjustments that you can make to the RX LMFC offset using the csr Imfc offset field in the syncn sysref ctr1register This is an alternative to using csr rbd offset to achieve deterministic latency JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation J send Feedback Altera Corporation Programmable LMFC Offset Figure 6 5 Selecting Legal LMFC Offset Value for RX Sequence of events in the diagram 1 Due to trace length mismatch SYSREF pulse arrives at the ADC first Some deterministic delay occurs in between the time when the SYSREF pulse is sampled high to the M reset of the ADC internal LMFC counter The FPGA deasserts SYNC N at the LMFC boundary The ADC JESD204B core detects the SYNC N deassertion PNA PY begins at the third LMFC boundary UG 01142 2015 05 04 The SYSREF pulse arrives at the FPGA IP core port rx_sysref after the pulse s arrival at the ADC The FPGA IP core s internal LMFC count
131. ext clock cycle is generated by an increment by one of the last N bits sample on the MSB of the data pattern on current clock cycle Pattern Checker The pattern checker instantiates any supported checkers and support run time reconfiguration downscale of the number of converters per device M and samples per converter per frame S The pattern checker can be either a parallel PRBS checker alternate checkerboard checker or ramp wave checker The data input bus width of the pattern checker is equivalent to the value of FRAMECLK DIV x MxSxN The pattern checker includes an ERR THRESHOLD parameter to control the number of error tolerance allowed in the checker The default value of this parameter is 1 The pattern checker also includes a REVERSE DATA parameter to control data arrangement at the input The default value of this parameter is 0 e 0 no data rearrangement at the input of the checker e l data rearrangement at the input of the checker Parallel PRBS Checker The PRBS checker contains the same polynomial as in the PRBS generator The polynomial is only updated when the enable signal is active which indicates that the input data is valid The feedback path is XOR ed with the input data to do a comparison The checker flags an error when it finds any single mismatch between polynomial data and input data Alternate Checkerboard Checker The alternate checkerboard checker is implemented in the same way as in the alternate c
132. fference in time arrival at the FPGA pins between SYSREF and device clock In most cases the register in the IP core which detects the SYSREF signal is far away from the SYSREF I O pin The long interconnect routing delay results in timing violation You are recommeded to use multi stages pipeline registers to close timing Use the same clock domain as the JESD204B IP core s rxlink clk and txlink_clk to clock the multi stages pipeline registers O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for p
133. g mode for the transceiver When you select bonded channel and L26 the IP core automatically selects x6 PLL fb compensa tion bonding mode for the transceiver In non bonded channel configuration the transceiver clock skew is higher and latency is unequal in the transmitter phase compensation FIFO for each channel This may result in a higher channel to channel skew Device Family Bonding Mode Configuration Maximum Number of Lanes L Bonded 32 2 PHY only Non bonded 32 2 Arria V Bonded 6 MAC and PHY Non bonded 8 About the JESD204B IP Core g 2 The maximum lanes listed here is for configuration simplicity Refer to the Altera Transceiver PHY User Guide for the actual number of channels supported Altera Corporation Send Feedback UG 01142 2 6 Performance and Resource Utilization 2015 05 04 Device Family Core Variation Bonding Mode Configuration Maximum Number of Lanes L Bonded 320 Arria V GZ PHY only Non bonded 320 Arria 10 Bonded 8 Stratix V MAC and PHY Non bonded 8 Performance and Resource Utilization Table 2 3 JESD204B IP Core FPGA Performance Enable Hard Enable Soft PCS PCS Gbps Gbps 9 PMA Speed Grade FPGA Fabric Speed Grade Device Family Link Clock Fmax MHz Cyclone V 5 Any 1 0 to 5 0 125 00 supported speed grade Cyclone V 6 60r7 1 0 to 3 125 78 125 Arria V lt Any lt Any 1 0 to 6 5
134. gital to analog DAC or analog to digital ADC converters to transfer data to FPGA devices This unidirectional serial interface runs at a maximum data rate of 12 5 Gbps This protocol offers higher bandwidth low I O count and supports scalability in both number of lanes and data rates The JESD204B IP core addresses multi device synchronization by introducing Subclass 1 and Subclass 2 to achieve deterministic latency The JESD204B IP core incorporates e Media access control MAC data link layer DLL block that controls the link states and character replacement e Physical layer PHY physical coding sublayer PCS and physical media attachment PMA block The JESD204B IP core does not incorporate the Transport Layer TL that controls the frame assembly and disassembly The TL and test components are provided as part of a design example component where you can customize the design for different converter devices O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Alte
135. guration UG 01142 2015 05 04 L Number of lanes per converter device 1 8 M Number of converters per device 1 256 F Number of octets per frame 1 2 4 256 S Number of transmitted samples per converter per frame 1 32 N Number of conversion bits per converter 1 32 N Number of transmitted bits per sample JESD204 word size 1 32 which is in nibble group K Number of frames per multiframe 17 F lt K lt 32 1 32 CS Number of control bits per conversion sample 0 3 CF Number of control words per frame clock period per link 0 32 HD High Density user data format O0or1 LMFC Local multiframe clock F x K 4 link clock counts Run Time Configuration The JESD204B IP core allows run time configuration of LMF parameters The most critical parameters that must be set correctly during IP generation are the L and F parameters Parameter L denotes the maximum lanes supported while parameter F denotes the size of the deskew buffer needed for deterministic latency The hardware generates during parameterization which means that run time programmability can only fall back from the parameterized and generated hardware but not beyond the parameterized IP core You can use run time configuration for prototyping or evaluating the performance of converter devices with various LMF configurations However in actual production Altera recommends that you generate the JESD204B IP core with the intended LMF to get an optim
136. haracter from multiple lanes exceed one multi frame e Misalignment detected during user data phase 07 Dynamic frame realignment and correction is not supported Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 ILAS Data 4 11 The realignment rules for lane alignment are similar to frame alignment e Iftwo successive and valid A characters are detected at the same position other than the assumed end of multi frame without receiving a valid invalid A character at the expected position between two A characters the receiver aligns the lane to the position of the newly received A characters e Ifa recent frame alignment causes the loss of lane alignment the receiver realigns the lane frame which is already at the position of the first received A character at the unexpected position ILAS Data The JESD204 RX IP core captures 14 octets of link configuration data that are transmitted on the 2 multi frame of the ILAS phase The receiver waits for the reception of Q character that marks the start of link configuration data and then latch it into ILAS octets which are per lane basis You can read the 14 octets captured in the link configuration data through the CSR You need to first set the csr ilas data sel register to select which link configuration data lane it is trying to read from Then proceed to read from the csr_ilas_octet register Initial Lane Synchronizatio
137. he illegal csr_Imfc_offset values of 1 2 and 3 will cause lane de skew error because the RBD buffer size has exceeded Figure 6 6 Selecting Illegal LMFC Offset Value for RX Causing Lane Deskew Error SYSREF pulse is sampled by IP core s internal register CE TX Sysref SYNC N I SYNC N deasserted at LMFC boundary transmitted by RX 1 link clock period LMFC count 2 link clock cycle deterministic i delay from SYSREF sampled H i Third LMFC Fourth LMFC high to the first LMFC boundary al i i karda boundary boundary m Free running LMFC counter x 0 x 15025 SS OKA SS a j 5 x 6 7 X 0 K TAXIDAG XAG XE XTA Internal LMFC counter resets cst_Imfc_offset 0 RBD elastic buffer size 8 Power cyde variation latest arrival i Ni i lane in multiple LEE PAPE D D D D D D power cycles iem Free running LMFC counter XX EXE XTX OKI SS X 2 X 3 XK 4X5 8X1 0X 1X 1x3 A LMFC boundary is H First LMFC boundary H RBD elastic buffer Third LMFC boundary at new location Internal LMFC counter resets delayed by 5 link clock atnewlocation released cr Imfc offset 3 i gii when csr _rbd_offset 0 RBD elastic buffer size is exceeded Latest arrival T H id i i lane in multiple SS es oe ee D D D D D D power cycles You can use the TX LMFC offset to align the LMFC counter in IP core to the
138. he jes d204 rx data valid is asserted along with the multiplexed jesd204 rx dataout 11 0 signal to stream data to the Avalon ST interface e Finally the DLL deasserts the 3esa204 rx link data valid signal when there is no more valid data e The deassembler deactivates the 2 divi cnt signal logic accordingly and deasserts the jesd204 rx data validat the next rxframe_clk rxframe_clk rxframe_rst_n rxlink_rst_n jesd204_rx_link_data_ready jesd204 rx link data valid i i jesd204_rx_link_datain 31 0 i i junk i i i Ka baa rxdata_mux_out 15 0 j junk i j i i Fxddc xbba dd au junk jesd204 mx dataout 10 nk A RT RUE SURE ROB xddc vA junk jesd204 rx crtlout 0 j j j j j jesd204 rx data valid j l j j j j j j l jesd204 rx data ready RX Data Reception This section explains when there is a valid RX data out from the DLL to the TL to with scrambler enabled The MAC layer process the 3esd204 rx dataout signal once the TL asserts the 3esd204 rx data valid signal However there are some data that should be discarded by the upper layer when the you enable the scrambler This is because the initial unknown seed value within the scrambler can corrupt the very first eight octets whi
139. heckerboard generator To do a comparison an initial seed internally generates a set of expected data pattern result to XOR ed with the input data The seed is updated only when the enable signal is active which indicates JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 8 Ramp Wave Checker UG 01142 2015 05 04 that the input data is valid The checker flags an error when it finds any single mismatch between the expected data and input data Ramp Wave Checker The ramp wave checker is implemented in the same way as in the ramp wave generator To do a comparison an initial seed internally generates a set of expected data pattern result to XOR ed with the input data The seed is updated only when the enable signal is active which indicates that the input data is valid The checker flags an error when it finds any single mismatch between the expected data and input data Transport Layer The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at the RX path The transport layer provides the following services to the application layer AL and the DLL The assembler at the TX path e maps the conversion samples from the AL through the Avalon ST interface to a specific format of non scrambled octets before streaming them to the DLL e reports AL error to the DLL if it encounters a specific error condition on the Avalon ST interface during TX data streaming The
140. ific WIDTH 1 0 order as illustrated in the cases listed in RX Path Data Remapping section jesd204_rx_ rxframe_clk Output RX control data to the Avalon ST source cont rolout CONTROL_ interface The transport layer arranges the data in BUS WIDTH 1 0 a specific order as illustrated in the cases listed in RX Path Data Remapping section jesd204 rx data rxframe clk Output Indicates whether the data from the transport valid layer to the Avalon ST sink interface is valid or invalid e 0 data is invalid e 1 data is valid jesd204 rx data eens sik Input Indicates that the Avalon ST sink interface is ready ready to accept data from the transport layer e O Avalon ST sink interface is not ready to receive data e 1 Avalon ST sink interface is ready to receive data Signal Clock Domain Direction Description Between Transport Layer and DLL Jesd204_rx link rxlink_clk Input Indicates received data from the DLL to the datain n 32 1 0 transport layer where four octets are packed into a 32 bit data width per lane The data format is big endian The table below illustrates the data mapping for L 4 jesd204 rx link datain xy 31 0 0 63 32 1 95 64 2 127 96 3 Connect this signal to the RX DLL jesd204_rx_ link_data output pin JESD204B IP Core Design Guidelines LJ Send Feedback Altera Corporation 5 28 RX Path UG 01142 2015 05 04 jesd204_rx_link_ data_valid rxlink clk
141. ignal is asserted to indicate that the TX transceiver calibration is in progress pll powerdown e lifbonding Input TX transceiver PLL power down signal pon E zs This signal is only applicable for V series o lubens FPGA variants mode feedback compensation tx Bonding clocks 6 Input The transceiver PLL bonding clocks The Single Channel transceiver PLL generation provides these tx_bonding_clocks_ clocks ch 0 L 1 gt Multiple This signal is only available if you select Channels Bonded mode for Arria 10 FPGA variants tx_serial_c1k0 Single 1 Input The transceiver PLL serial clock This is the Channel serializer clock in the PMA The transceiver ETRAS E PLL generation provides these clocks ch 0 1 1 Multiple This signal is only available if you select Non Channels bonded mode for Arria 10 FPGA variants Signal Width Direction Description Transceiver Interface tx serial ses L Output Differential high speed serial output data The clock is embedded in the serial data stream Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Transmitter 4 29 a NE HN reconfig to xcvr L 1 70 if bonding mode N L 140 if bonding mode feedback compensation Input Reconfiguration signals from the Transceiver Reconfiguration Controller IP core to the PHY device This signal is only applicable for V series FPGA variants You must co
142. ility Subclass 0 mode for backward compatibility to JESD204A Subclass 1 mode for deterministic latency support using SYSREF between the ADC DAC and logic device Subclass 2 mode for deterministic latency support using SYNC_N between the ADC DAC and logic device Multi device synchronization About the JESD204B IP Core C Send Feedback UG 01142 2015 05 04 Datapath Modes 2 3 Datapath Modes The JESD204B IP core supports TX only RX only and Duplex TX and RX mode The IP core is a unidirectional protocol where interfacing to ADC utilizes the transceiver RX path and interfacing to DAC utilizes the transceiver TX path The JESD204B IP core generates a single link with a single lane and up to a maximum of 8 lanes If there are two ADC links that need to be synchronized you have to generate two JESD204B IP cores and then manage the deterministic latency and synchronization signals like SYSREF and SYNC_N at your custom wrapper level The JESD204B IP core supports duplex mode only if the LMF configuration for ADC RX is the same as DAC TX and with the same data rate This use case is mainly for prototyping with internal serial loopback mode This is because typically as a unidirectional protocol the LMF configuration of converter devices for both DAC and ADC are not identical IP Core Variation The JESD204B IP core has three core variations e JESD204B MAC only e JESD204B PHY only e JESD204B MAC and PHY In a subsystem wh
143. ill deskew and output the data when the RBD offset value is met The total latency is consistent in the system and is also the same across multiple resets Setting a different RBD offset to each link or setting an early release does not guarantee deterministic latency and data alignment Altera Corporation CJ Send Feedback 4 16 Link Reinitialization Figure 4 7 Subclass 1 Combining the sync_n Signal for JESD204B TX IP Core FPGA Device SYNC_N SYNC_N SYNC_N SYSREF Subclass 1 DAC Reference ie Reference Clock Clock Clock Chip SYSREF and SYSREF SYSREF Related Information Programmable RBD Offset on page 6 2 Link Reinitialization The JESD204B TX and RX IP core support link reinitialization Altera Corporation UG 01142 2015 05 04 JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Link Startup Sequence 4 17 There are two modes of entry for link reinitialization e Hardware initiated link reinitialization e For TX the reception of sync_n for more than five frames and nine octets triggers link reinitializa tion e For RX the loss of code group synchronization frame alignment and lane alignment errors cause the IP core to assert syNc_N and request for link reinitialization e Software initiated link reinitialization both the TX and RX IP core allow software to request for link reinitialization For TX th
144. ing the Quartus II software targeting the following Altera FPGA devices e Cyclone V 5SCGTFD9ESF31I7 e Arria V BAGXFB3HAF35C5 Arria V GZ 5AGZMES5K2F40C3 e Arria 10 10AX115H2F34I2SGES e Stratix V 5SGXEA7H3F35C3 All the variations for resource utilization are configured with the following parameter settings Table 2 4 Parameter Settings To Obtain the Resource Utilization Data JESD204B Wrapper Base and PHY JESD204B Subclass 1 Data Rate 5 Gbps PCS Option Enabled Hard PCS PLL Type e ATX for 10 series devices e CMU for V series devices Bonding Mode Non bonded Reference Clock Frequency 125 0 MHz Octets per frame F 1 Enable Scrambler SCR Off Enable Error Code Correction ECC_EN Off 9 Select Enable Soft PCS to achieve maximum data rate For the TX IP core enabling soft PCS incurs an additional 3 896 increase in resource utilization For the RX IP core enabling soft PCS incurs an additional 10 20 increase in resource utilization When using Soft PCS mode at 12 5 Gbps the timing margin is very limited You are advised to enable HIGH fitter effort register duplication and register retiming to improve timing performance About the JESD204B IP Core Altera Corporation LJ Send Feedback ae UG 01142 2 8 Performance and Resource Utilization 2015 05 04 Table 2 5 JESD204B IP Core Resource Utilization The numbers of ALMs and logic registers in this table are rounded up to th
145. ink clock generated from the transceiver serial or parallel clock for the TX path or the link clock generated from the CDR for the RX path This clock has the same frequency as the TX RX link clock and is an output from the JESD204B IP core There is limited use for this clock Only if the JESD204B configuration is F 4 and operating at Subclass 0 mode this clock can be used as input for both the txlink_clk and txframe_clk or rxlink_ clk and rxframe_clk TX RX AVS Clock jesd204_tx_avs_clk jesd204_rx_avs_clk 75 125 MHz The configuration clock for the JESD204B IP core CSR through the Avalon MM interface Transceiver Management Clock reconfig_clk 100 MHz 125 MHz The configuration clock for the transceiver CSR through the Avalon MM interface This clock is exported only when the transceiver dynamic reconfiguration option is enabled This clock is only applicable for Arria 10 devices Device Clock In a converter device the sampling clock is typically the device clock For the JESD204 IP core in an FPGA logic device the device clock is used as the transceiver PLL reference clock and also the core PLL reference clock The available frequency depends on the PLL type bonding option number of lanes and device family During IP core generation the Quartus II software recommends the available device clock frequency for the transceiver PLL based on the user selection Note You need to generate the Altera P
146. into a single MIF file for each IP core The following section shows the MIF file format Core PLL The MIF format is fixed by the PLL You need to generate two PLLs with maximum and downscale setting to get these two MIF files Then merge the files into one core_pll mif Only the PLL with maximum configuration is used in final compilation Maximum Configuration MIF WIDTH 32 DEPTH 92 ADDRESS_RADIX UNS JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 52 MIF ROM 2015 05 04 DATA_RADIX BIN CONTENT BEGIN 0 00000000000000000000000000111110 START OF MIF 1 00000000000000000000000000000100 2 00000000000000000000000100000001 3 00000000000000000000000000000011 42 00000000000000000000000000000010 43 00000000000000000000000000001000 44 00000000000000000000000001000000 45 00000000000000000000000000111111 END OF MIF Downscale Configuration MIF 46 00000000000000000000000000111110 START OF MIF 47 00000000000000000000000000000100 48 00000000000000000000000100000001 49 00000000000000000000000000000011 88 00000000000000000000000000000010 89 00000000000000000000000000001000 90 00000000000000000000000001000000 91 00000000000000000000000000111111 END OF MIF END PHY Stratix V and Arria V The MIF format is fixed by the PHY You need to generate two JESD204B IP cores with maximum and downscale se
147. ion Domain Serial Data and Control rx serial Input Differential high speed serial input data The clock is data LINK L 1 0 recovered from the serial data stream tx serial device Output Differential high speed serial output data The clock d ta E TNKY LSL BANI clk is embedded in the serial data stream JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 46 System Interface Signals 2015 05 04 Direction Description Uu Assert this signal to enable internal serial loopback in Seriel lporen LINE Le the duplex transceiver 1 s0 Clock Direction Description Domain User Request Control secte mgmt cik TInput Active high reconfiguration request Set this signal to static 0 during compile time if run time reconfigura tion is not required runtime_lmf mgmt_clk Input Reconfigure the LMF value at run time This value must be stable prior to assertion of the reconfig signal e 0 Downscale to the LMF value stored in MIF file e 1 Upscale back to maximum LMF value Assuming at compile time the LMF configuration is 222 set this signal to 0 to scale down the LMF configuration to 112 Set this signal to 1 to scale up the LMF configuration back to 222 puntine datarate mgmt c input Reconfigure the data rate at run time This value must be stable prior to assertion of reconfig signal e 0 Downscale to data rate setting stored in PLL PHY and clock
148. ion N 1 32 Set the number of conversion bits per converter Transmitted bits per 1 32 Set the number of transmitted bits per sample JESD204B sample N word size Note If parameter CF equals to 0 no control word parameter N must be larger than or equal to sum of parameter N and parameter CS N 2 N CS Otherwise parameter N must be larger than or equal to parameter N N ZN Samples per converter per 1 32 Set the number of transmitted samples per converter per frame S frame 09 Refer to the Table 3 6 table for the supported range for L Getting Started LJ Send Feedback Altera Corporation UG 01142 3 20 JESD204B IP Core Parameters 2015 05 04 Frames per multiframe 1 32 Set the number of frames per multiframe This value is K dependent on the value of F and is derived using the following constraints e The value of K must fall within the range of 17 F lt K lt min 32 floor 1024 F e The value of F K must be divisible by 4 Enable scramble SCR On Off Turn on this option to scramble the transmitted data or descramble the receiving data Control Bits CS 0 3 Set the number of control bits per conversion sample Control Words CF 0 32 Set the number of control words per frame clock period per link High density user data On Off Turn on this option to set the data format This parameter format HD controls whether a sample may be divided over more lanes e On High Densi
149. iplexed data to the Avalon ST interface determined by certain control signals from the RX control block Table 5 11 Deassembler Parameter Settings L Number of lanes per converter device 1 8 F Number of octets per frame 1 2 4 8 CS Number of control bits or conversion sample 0 3 N Number of conversion bits per converter 12 16 N Number of transmitted bits per sample in the user data format 16 Fl FRAMECLK DIV Only applies to cases where F 1 1 4 The divider ratio on the rame cix The deassembler always uses the post divided frame clk rxframe_clk 9 34 Refer to the Table 5 7 to set the desired frame clock frequency with different FRAMECLK DIV and F parameter values JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 26 RX Path UG 01142 2015 05 04 F2 FRAMECLK DIV Only applies to cases where F 2 1 2 The divider ratio on the frame_c1k The deassembler always uses the post divided frame clk rxframe_clk 6 RECONFIG EN Enable reconfiguration support in the transport layer Only 0 1 downscaling reconfiguration is supported Disable the reconfigura tion to reduce the logic OUTPUT BUS The data output bus width size that depends on the F and L B P L WIDTH S N N_ bus_width M S N PRIME F M S N_PRIME 8 L M S 8 F L N_PRIME Therefore the output bus width 8 F L N N_PRIME CONTROL_BUS_ The control output bus width size The width depends on the C
150. is reset signal asynchronously but must deassert it synchro nously to the jesd204 tx avs clk signal After you deassert this signal the CPU can configure the CSRs JESD204B IP Core Functional Description Altera Corporation LJ Send Feedback 4 32 Transmitter UG 01142 2015 05 04 SiS aa jesd204_tx_avs_ chipselect Input When this signal is present the slave port ignores all Avalon MM signals unless this signal is asserted This signal must be used in combination with read or write If the Avalon MM bus does not support chip select you are recommended to tie this port to 1 jesd204_tx_avs_ address Input For Avalon MM slave the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data For example address 0 selects the first word of the slave and address 1 selects the second word of the slave jesd204_tx_avs_ writedata 32 Input 32 bit data for write transfers The width of this signal and the jesa204 tx avs readdata 31 0 signal must be the same if both signals are present jesd204 tx avs read Input This signal is asserted to indicate a read transfer This is an active high signal and requires the jesd204 tx avs readdata 31 0 signal to be in use jesd204 tx avs write jesd204 tx avs readdata 32 Input Output This signal is asserted to indicate a write transfer This
151. ite 0xC0 to DID register 0x64 3 000000000110111000000011 write 0x03 to parameter SCR L register Ox6E to disable scrambler 4 000000000111000000001111 write OXOF to parameter K register 0x70 for K 16 in base IP core 5 000000000000110100000100 write 0x04 to test mode register 0x0D for checkerboard test pattern 6 000000000101111100010100 write 0x14 to link control 1 register 0x5F to enable the lane 7 1131111111111111111111111 indicates end of mif or end of programming sequence END The initial values for each address and sequence is defined based on the requirement of the external converter and clock devices The example above is based on 24 bit SPI write only programming The last word must not be a valid data and must be set to all 1 s to indicate the end of the MIF or programming sequence This is because each converter device may have a different number of programmable registers and hence involves a different number of MIF words In this design example three ROMs are used by default for each external ADC DAC and clock devices If either one of the device is not used a single word MIF with all 1 s can be created Note The MIFs in this design example is an example for a particular converter device You must define the MIF content based on the requirement of the external converter devices Finite State Machine FSM The steps below describe the FSM flow 1 Initialize the SPI a Perform a read transaction from th
152. ized gate count For example if a converter device supports LMF 442 and LMF 222 to check the performance for both configurations you need to generate the JESD204B IP core with maximum F and L which is L 4 and F 2 During operation you can use the fall back configuration to disable the lanes that are not used in LMF 222 mode You must ensure that other JESD204B configurations like M N S CS CF and HD do not violate the parameter F setting You can access the Configuration and Status Register CSR space to modify other configurations such as K multi frame device and lane IDs enable or disable scrambler enable or disable character replacement 0 The value of F x K must be divisible by 4 Altera Corporation About the JESD204B IP Core C Send Feedback UG 01142 2015 05 04 Channel Bonding 2 5 F Parameter This parameter indicates how many octets per frame per lane that the JESD204B link is operating in You must set the F parameter according to the JESD204B IP Specification for a correct data mapping To support the High Density HD data format the JESD204B IP core tracks the start of frame and end of frame because F can be either an odd or even number The start of frame and start of multi frame wrap around the 32 bits data width architecture The RX IP core outputs the start of frame sof 3 0 and start of multiframe som 3 0 which act as markers using the Avalon ST data stream Based on these mar
153. kers the transport layer build the frames In a simpler system where the HD data format is set to 0 the F will always be 1 2 4 6 8 and so forth This simplifies the transport layer design so you do not need to use the sof 3 0 and somf 3 0 markers Channel Bonding The JESD204B IP core supports channel bonding bonded and non bonded modes The channel bonding mode that you select may contribute to the transmitter channel to channel skew A bonded transmitter datapath clocking provides low channel to channel skew as compared to non bonded channel configurations Table 2 2 Maximum Number of Lanes L Supported in Bonded and Non Bonded Mode In PHY only mode you can generate up to 32 channels provided that the channels are on the same side In MAC and PHY integrated mode you can generate up to 8 channels In bonded channel configuration the lower transceiver clock skew and equal latency in the transmitter phase compensation FIFO for all channels result in a lower channel to channel skew You must use adjacent channels when you select x6 bonding You must also place logical channel 0 in either physical channel 1 or 4 Physical channels 1 and 4 are indirect drivers of the x6 clock network The JESD204B IP core automatically selects between xN or feedback compensation fb compensation bonding depending on the number of transceiver channels you set When you select bonded channel and L 6 the IP core automatically selects xN x6 bondin
154. layer can use this signal as a run time parameter cer ml Output Indicates the number of converters for the link The transport layer can use this signal as a run time parameter esr osi esre oii Output Output Indicates the number of control bits per sample The transport layer can use this signal as a run time parameter Indicates the converter resolution The transport layer can use this signal as a run time parameter csr_np Output Indicates the total number of bits per sample The transport layer can use this signal as a run time parameter ese elll Output Indicates the number of samples per converter per frame cycle The transport layer can use this signal as a run time parameter csr hd Output Indicates the high density data format The transport layer can use this signal as a run time parameter esc wt Output Indicates the number of control words per frame clock period per link The transport layer can use this signal as a run time parameter csr lane powerdown Output Indicates which lane is powered down You need to set this signal if you have configured the link and want to reduce the number of active lanes Altera Corporation JESD204B IP Core Functional Description G send Feedback UG 01142 2015 05 04 Transmitter 4 35 ENLCEENEN NN NN NN csr tx testmoce l Output Indicates the address space that is reserved for
155. le 4 6 Receiver Signals Signal With irection Description Clocks and Resets pil ref cik 1 Input Transceiver reference clock signal rxlink clk 1 Input RX link clock signal used by the Avalon ST interface This clock is equal to RX data rate divided by 40 For Subclass 1 you cannot use the output of rxphy_clk signal as rxlink_clk signal To sample SYSREF correctly the core PLL must provide the rxlink clk signal and must be configured as normal operating mode relink rot ye ee ei Input Reset for the RX link clock signal This reset is an active low signal rxphy_clk L Output Recovered clock signal This clock is derived from the clock data recovery CDR and the frequency depends on the JESD204B IP core data rate rx_digitalreset L Input Reset for the transceiver PCS block This reset is an active high signal rx analogreset L Input Reset for the CDR and transceiver PMA block This reset is an active high signal rx_islockedtodata 09 p Output This signal is asserted to indicate that the RX CDR PLL is locked to the RX data and the RX CDR has changed from LTR to LTD mode rx cal busy L Output RX calibration in progress signal This signal is asserted to indicate that the RX transceiver calibra tion is in progress Signal Width Direction Description Transceiver Interface zx serial cel L Input Differential high speed serial input data The clock
156. ler safaris For the alignment of LMFC to the TX logic the JESD204 TX IP core samples SYNC_N from the DAC receiver and reports the relative phase difference between the DAC and TX logic device LMFC in the TX CSR dbg_phadj dbg_adjdir and dbg_adjcnt Based on the reported value you can calculate the adjustment required Then to initiate the link reinitialization through the CSR set the value in the TX CSR csr_phadj csr_adjdir and csr adjcnt The values on the phase adjustment are embedded in bytes 1 and 2 of the ILAS sequence that is sent to the DAC during link initialization On the reception of the ILAS the DAC adjusts its LMFC phase by step count value and sends back an error report with the new LMFC phase information This process may be repeated until the LMFC at the DAC and the logic device are aligned Scrambler Descrambler Both the scrambler and descrambler are designed in a 32 bit parallel implementation and the scrambling descrambling order starts from first octet with MSB first The JESD204 TX and RX IP core support scrambling by implementing a 32 bit parallel scrambler in each lane The scrambler and descrambler are located in the JESD204 IP MAC interfacing to the Avalon ST interface You can enable or disable scrambling and this option applies to all lanes Mixed mode operation where scrambling is enabled for some lanes is not permitted The scrambling polynomial 14 15 1 x x The descrambler can self synchronize in
157. lock for the transport layer pattern generator and pattern checker Clock 2 is the link clock for the transport and link layer 10 The control unit implements a memory initialization file MIF method for configuring the SPI Each MIF corresponds to a separate external converter per device or clock chip For example in a system that interacts with both DAC and ADC two MIFs are needed one each for DAC and ADC 11 The PLL reconfiguration and transceiver reconfiguration controller instances are only required for run time reconfiguration of the data rate Design Example Components The design example for the JESD204B IP core consists of the following components e PLL e PLL reconfiguration e Transceiver reconfiguration controller e Transceiver reset controller e Pattern generator e Pattern checker e Assembler and deassembler in the transport layer e SPI e Control unit The following sections describe in detail the function of each component PLL The design example requires four different clock domains device clock management clock frame clock and link clock Typically the device clock is generated from an external converter or a clock device while the management clock AVS clock is generated from an on board 100 MHz oscillator For instance if the JESD204B IP core is configured at data rate of 6 144 Gbps transceiver reference clock frequency of 153 6 MHz and number of octets per frame F 2 the example below indic
158. logic is synchronous to the clock input provided by the Avalon MM interface When configured as a master the core divides the Avalon MM clock to generate the scLK output Figure 5 13 Serial Port Interface 24 bit Timing Diagram Figure shows the timing diagram of a 24 bit SPI transaction required by a typical external converter 5 device sux Dti S U PL PLIN NUNT U ee C 05 SDIO Don t Care R W wi WO A12 A11 A10 A9 AB A7 D D4 D3 D2 D1 DO K Don tCare The first 16 bits are instruction data The first bit in the stream is the read or write indicator bit This bit goes high to indicate a read request W1 and WO represent the number of data bytes to transfer for either a read or write process For implementation simplicity W1 and W0 are always set at 0 in this design Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Control Unit 5 37 example The subsequent 13 bits represent the starting address of the data sent The last 8 bits are register data For a 32 bit SPI transaction each SPI programming cycle needs to be preceded with a preselection byte The preselection byte is typically used to forward the SPI command to the right destination figure shows the timing diagram of a 32 bit SPI transaction Figure 5 14 Serial Port Interface 32 bit Timing Diagram sn oo SQK m SDI
159. ltera jes204 tb sh file This file compiles the design and runs the simulation automati cally providing a pass fail indication on completion Related Information Simulating Altera Designs More information about Altera simulation models Compiling the JESD204B IP Core Design Before you begin Refer to the JESD204B IP Core Design Considerations on page 3 11 before compiling the JESD204B IP core design To compile your design click Start Compilation on the Processing menu in the Quartus II software You can use the generated qip file to include relevant files into your project Related Information JESD204B IP Core Design Considerations on page 3 11 Quartus II Help More information about compilation in Quartus II software Altera Corporation Getting Started C Send Feedback UG 01142 T 2015 05 04 Programming an FPGA Device 3 Programming an FPGA Device After successfully compiling your design program the targeted Altera device with the Quartus II Programmer and verify the design in hardware For instructions on programming the FPGA device refer to the Device Programming section in volume 3 of the Quartus II Handbook Related Information Device Programming JESD204B IP Core Design Considerations You must be aware of the following conditions when integrating the JESD204B IP core in your design e Intergrating the IP core in Qsys e Pin assignments e Adding external transceiver PLL Timing constraint
160. mentation Guidelines Altera Corporation CJ Send Feedback JESD204B IP Core Debug Guidelines 7 2015 05 04 UG 01142 amp Subscribe LJ Send Feedback This section lists some guidelines to assist you in debugging JESD204B link issues Apart from applying general board level hardware troubleshooting technique like checking the power supply external clock source physical damage on components a fundamental understanding of the JESD204B subsystem operation is important Related Information e Clocking Scheme on page 7 1 e JESD204B Parameters on page 7 1 e SPI Programming on page 7 2 Converter and FPGA Operating Conditions on page 7 2 e Signal Polarity and FPGA Pin Assignment on page 7 2 e Debugging JESD204B Link Using SignalTap II and System Console on page 7 3 Clocking Scheme To verifying the clocking scheme follow these steps 1 Check that the frame and link clock frequency settings are correct in the Altera PLL IP core For the design example the frame clock is assigned to outclk0 and link clock is assigned to outclk1 2 Check the device clock frequency at the FPGA and converter For Subclass 1 check the SYSREF pulse frequency 4 Check the clock frequency management For the design example using Stratix V and Arria V devices this frequency is 100 MHz JESD204B Parameters The parameters in both the FPGA and ADC should be set to the same values For example when you set K 32 on the FPGA set the converter
161. meter an interrupt is triggered However this register does not prevent CGS SYSREF race condition The following conditions occur if both CSR bits are set e resets the local multi frame clock counter at every rising edge of SYSREF e prevents CGS SYSREF race condition e checks SYSREF period Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Clock Correlation 4 23 Related Information Clock Correlation on page 4 23 Clock Correlation This section describes the clock correlation between the device clock link clock frame clock and local multi frame clock Example 1 Targeted device with LMF 222 K 16 and Data rate 6 5 Gbps Device Clock selected 325 MHz obtained during IP core generation Link Clock 6 5 GHz 40 162 5 MHz Frame Clock 6 5 GHz 10x2 325 MHz Local Multi frame clock 325 MHz 16 20 3125 MHz SYSREF Frequency Local Multi frame Clock n n integer 1 2 Local multi frame clock counter F x K 4 2x16 4 8 link clocks 09 Example 2 Targeted device with LMF 244 K 16 and Data rate 5 0 Gbps Device Clock selected 125 MHz obtained during IP core generation Link Clock 5 GHz 40 125 MHz 0 Frame Clock 5 GHz 10x4 125 MHz 0 Local Multi frame clock 125 MHz 16 7 8125 MHz SYSREF Frequency Local Multi frame Clock n n integer 1 2 Local multi frame clock counter F x K 4 4x8 4 8 link clocks 9 Example
162. mulation Flow The JESD204B testbench simulation flow 1 At the start the system is under reset all the components are in reset 2 After 100 ns the Transceiver Reset Controller IP core power up and wait for the tx_ready signal from 9 the Transceiver Reset Controller IP to assert The reset signal of the JESD204B TX Avalon MM interface is released go HIGH once the tx ready signal is asserted At the next positive edge of the 1ink c1k signal the JESD204B TX link powers up by releasing its reset signal The JESD204B TX link starts transmitting K28 5 characters and wait for the Transceiver Reset Controller IP core to assert the xx xeaay signal The reset signal of the JESD204B RX Avalon MM interface is released go HIGH once the xx ready signal is asserted At the next positive edge of the 1ink c1k signal the JESD204B RX link powers up by releasing its reset signal Once the link is out of reset a SYSREF pulse is generated to reset the LMFC counter inside both the JESD204B TX and RX IP core When the txiink ready signal is asserted the packet generator starts sending packets to the TX datapath The packet checker starts comparing the packet sent from the TX datapath and received at the RX datapath after the xx1ink valid signal is asserted The testbench reports a pass or fail when all the packets are received and compared The testbench concludes by checking that all the packets have been receive
163. n The receivers in Subclass 1 and Subclass 2 modes store data in a memory buffer Subclass 0 mode does not store data in the buffer but immediately releases them on the frame boundary as soon as the latest lane arrives The RX IP core detects the start of multi frame of user data per lane and then wait for the latest lane data to arrive The latest data is reported as RBD count csr_rbd_count value which you can read from the status register This is the earliest release opportunity of the data from the deskew FIFO referred to as RBD offset The JESD204 RX IP core supports RBD release at 0 offset and also provides programmable offset through RBD count By default the RBD release can be programmed through the csr_rbd_offset to release at the LMFC boundary If you want to implement an early release mechanism program it in the csr rbd offset register The csr rbd offset and csr rbd count is a counter based on the link clock boundary not frame clock boundary Therefore the RBD release opportunity is at every four octets JESD204B IP Core Functional Description Altera Corporation C Send Feedback UG 01142 4 12 RX PHY Layer 2015 05 04 Figure 4 5 Subclass 1 Deterministic Latency and Support for Programmable Release Opportunity SYSR
164. n simplicity you can directly connect the master MOSI pin to the slave DATAIO pin if read transac tions are not required Related Information I O Buffer ALTIOBUF Megafunction User Guide More information about configuring the ALTIOBUF Megafunction IP Core Control Unit The control unit has access to the CSR interface of the JESD204B IP core duplex base core PLL reconfiguration transceiver reconfiguration controller and SPI master The control unit also serves as a clock and reset unit CRU for the design example The control unit replaces the software based Nios II processor to perform device configuration and initialization on the JESD204B duplex base core This configuration and initialization process includes the transceivers transport layer pattern generator and checker external converters ADC DAC and clock devices over the SPI interface JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 38 Memory Block ROM Figure 5 15 Control Unit Process Flow Power Up and Reset Y Assert Transceiver user triggered Frame and CSR Reset v SPI Configuration Y Assert Link Frame and CSR Reset v Deassert Transceiver Reset v Deassert CSR Reset followed by Link and Frame Reset v INIT Done v IDLE reconfig 1 b1 Memory Block ROM v Start Reconfiguration
165. ng Wink When F 8 the data latency for jesd204 tx link datain should always be in an even latency link clk count to ensure that the first valid data captured by the TX link is TO data followed by T1 data The JESD204B IP core implements the data transfer in big endian format Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 TX Path Data Remapping 5 19 Figure below illustrates the converter sample to transceiver lane mapping operation in the transport layer Each converter sample has N bits M converters per ADC DAC device and S samples per converter M per frame clock cycle The transport layer operates at full rate or FRAMECLK_DIV 1 1 The application layer or user logic data path interfaces directly with the transport layer through the Avalon ST data bus if the application layer operates in frame clock domain If the application layer operates at a different clock domain than the frame clock domain add a FIFO for the clock domain crossing You have to reorder the samples so that sample 0 of converter 0 is located at LSB of the Avalon ST data bus followed by sample 1 of converter 0 if S21 or sample 0 of converter 1 if S 1 The most signifi cant bits MSB of the Avalon ST bus has a sample of S 1 of converter M 1 For example if S 4 and M 4 the most significant bits will be occupied by sample 3 of converter 3 In this example there is no control word becaus
166. nnect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run time reconfigu ration is enabled or disabled The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up reconfig_from_xcvr L 1 46 if bonding mode XN L 92 if bonding mode feedback compensation Output Reconfiguration signals to the Transceiver Reconfiguration Controller IP core This signal is only applicable for V series FPGA variants You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run time reconfigu ration is enabled or disabled The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up reconfig clk 1 Input The Avalon MM clock input The frequency range is 100 125 MHz This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_reset 1 Input Reset signal for the Transceiver Reconfigura tion Controller IP core This signal is active high and level sensitive This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_avmm_ address logL 1024 Input The Avalon MM address This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants JESD204
167. nt version of the g Quartus II software due to incompatibility with the current version of the Quartus II software You are prompted to replace the unsupported IP core with a supported equivalent IP core from the IP Catalog Refer to the Descrip tion for details about IP core version differences and links to Release Notes IP End of Life Altera designates the IP core as end of life status You may or may not be able to edit the IP core in the parameter editor Support for this IP core aA discontinues in future releases of the Quartus II software Encrypted IP Core The IP variation is encrypted Follow these steps to upgrade IP cores 1 In the latest version of the Quartus II software open the Quartus II project containing an outdated IP core variation The Upgrade IP Components dialog automatically displays the status of IP cores in Getting Started LJ Send Feedback Altera Corporation Upgrading IP Cores UG 01142 2015 05 04 your project along with instructions for upgrading each core Click Project gt Upgrade IP Components to access this dialog box manually To upgrade one or more IP cores that support automatic upgrade ensure that the Auto Upgrade option is turned on for the IP core s and then click Perform Automatic Upgrade The Status and Version columns update when upgrade is complete Example designs provided with any Altera IP core regenerate automatically whenever you upgrade an IP core To man
168. o the jesd204_ rx avs clk signal After you deassert this signal the CPU can configure the CSRs jesd204 rx avs chipselect Input When this signal is present the slave port ignores all Avalon MM signals unless this signal is asserted This signal must be used in combination with read or write If the Avalon MM bus does not support chip select you are recommended to tie this port to 1 jesd204 rx avs address Input For Avalon MM slave the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data For example address 0 selects the first word of the slave and address 1 selects the second word of the slave jesd204 rx avs writedata jesd204 rx avs read 32 Input Input 32 bit data for write transfers The width of this signal and the 3esa204 rx avs readdata 31 0 signal must be the same if both signals are present This signal is asserted to indicate a read transfer This is an active high signal and requires the jesd204 rx avs readdata 31 0 signal to be in use jesd204 rx avs write Input This signal is asserted to indicate a write transfer This is an active high signal and requires the jesd204 rx avs writedata 31 0 signal to be in use jesd204 rx avs readdata 32 Output 32 bit data driven from the Avalon MM slave to master in response to a read transfer JESD204B IP Core F
169. on 2015 05 04 RWIS Software reads shall return the current bit value Software writes 0 shall have no effect Software writes 1 shall set the bit to 1 Hardware clears the bit to 0 if the bit has been set to 1 by software Software set has higher priority than hardware clear Altera Corporation JESD204B IP Core Functional Description C Send Feedback 2015 05 04 JESD204B IP Core Design Guidelines UG 01142 amp Subscribe Send Feedback This section describes the design example included with the IP core and some implementation guidelines JESD204B IP Core Design Example The design example entity consists of various components that interface with the JESD204B IP core to demonstrate the following features single or multiple link configuration different LMF settings with scrambling and internal serial loopback enabled interoperability against diverse converter devices dynamic reconfiguration You can use the synthesizable design example entity in both simulation and hardware environments Figure 5 1 illustrates the high level system architecture of the JESD204B IP core design example 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the
170. ook Design Walkthrough This walkthrough explains how to create a JESD204B IP core design using Osys in the Quartus II software After you generate a custom variation of the JESD204B IP core you can incorporate it into your overall project Creating a New Quartus II Project You can create a new Quartus II project with the New Project Wizard This process allows you to Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 Parameterizing and Generating the IP Core 3 7 e specify the working directory for the project e assign the project name e designate the name of the top level design entity 1 From the Windows Start menu select Programs gt Altera gt Quartus II version to launch the Quartus II software Alternatively you can use the Quartus II Web Edition software 2 On the File menu click New Project Wizard 3 In the New Project Wizard Directory Name Top Level Entity page specify the working directory project name and top level design entity name Click Next 4 In the New Project Wizard Add Files page select the existing design files if any you want to include in the project Click Next 5 In the New Project Wizard Family amp Device Settings page select the device family and specific device you want to target for compilation Click Next 6 In the EDA Tool Settings page select the EDA tools you want to use with the Quartus II software to develop your project 7 Review the
171. or clock device mgmt_clk Input Management clock signal from the on board 100 MHz oscillator Acier le Output Internally generated clock The Avalon ST user data input must be synchronized to this clock domain for normal operation mode global rst mgmt_clk Tnput Global reset signal from the push button This reset is an active low signal and the deassertion of this signal is synchronous to the rising edge of mgmt _clk Clock Direction Description Domain JESD204B tx eysref rrNk 1 0 link clk Input TX SYSREF signal for JESD204B Subclass 1 implementation sync_n LINK 1 0 link elk Tnput Indicates a TX sync_n from the receiver This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting mdew sync Se eee Sian Indicates a multidevice synchronization request at the TX path Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal In a single link instance where multidevice synchronization is not needed you need to tie this signal to the dev_sync_n signal alldev_lane_aligned link_clk Input Aligns all lanes for this device at the RX path For multidevice synchronization multiplex all the dev_lane_aligned signals before connecting to this signal pin For single device support connect the dev_lane_ aligned signal back to this signal Altera Corporation JESD204B IP
172. or LINK 1 0 frame Output Asserted to indicate that the pattern checker has found a mismatch in the received data and the expected data One error signal per pattern checker Jesd204 tx int LINK link_clk Output Interrupt pin for the JESD204B IP core TX The a interrupt signal is asserted when an error condition or synchronization request is detected jesd204 rx int LINK link clk ps5 Output Interrupt pin for the JESD204B IP core RX The interrupt signal is asserted when an error condition or synchronization request is detected Example Feature Dynamic Reconfiguration The JESD204B IP core design example demonstrates dynamic run time reconfiguration of either the LMF or data rate at any one time Dynamic Reconfiguration Operation The dynamic reconfiguration feature implements various reconfiguration controller modules such as PLL reconfiguration Transceiver Reconfiguration Controller SPI master and JESD204B IP core Avalon MM slave These modules connect to the control unit through the Avalon MM interface You can control the reconfiguration using the reconfig runtime l1mf and runtime datarate input ports exposed at control unit interface JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 50 Dynamic Reconfiguration Operation 2015 05 04 Figure 5 19 Dynamic Reconfiguration Block Diagram For 28 nm Device Families Stratix V and Arria
173. or all lanes In a normal operation whenever synchronization is lost JESD204 RX IP core always return back to the CS INIT state where the word alignment is initiated For debug purposes you can bypass this alignment by setting the csr_patternalign_en register to 0 The 8B 10B decoder decode the data after receiving the data through the serial line The JESD204 IP core supports transmission order from MSB first as well as LSB first The PHY layer can detect 8B 10B not in table NIT error and also running disparity error Altera Corporation JESD204B IP Core Functional Description C Send Feedback UG 01142 2015 05 04 Operation 4 13 Operation Operating Modes The JESD204B IP core supports Subclass 0 1 and 2 operating modes Subclass 0 The JESD204 IP core maintains a LMFC counter that counts from 0 to F x K 4 1 and wraps around again The LMFC counter starts counting at the deassertion of SYNC N signal from multiple DACs after synchronization This is to align the LMFC counter upon transmission and can only be done after all the converter devices have deasserted its synchronization request signal Subclass 1 The JESD204 IP core maintains a LMFC counter that counts from 0 to F x K 4 1 and wraps around again The LMFC counter will reset within two link clock cycles after converter devices issue a common SYSREF frequency to all the transmitters and receivers The SYSREF frequency must be the same for converter devices that ar
174. or example if F 2 the csr_ 7 0 00000001 This design example supports the following values e 00000000 e 00000001 e 00000011 e 00000111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer Ensure that the csr_f 7 0 value always matches the system parameter F value when it is in static configuration Connect this signal to the TX DLL csr_f output pin 6D This signal should be static and valid before the deassertion of the 1ink rst nand frame rst n signals JESD204B IP Core Design Guidelines J send Feedback Altera Corporation UG 01142 2015 05 04 csr n 4 0 6 mgmt clk Input Indicates the converter resolution This 5 bit bus represents the N value in zero based binary format For example if N 16 the csr_n 4 0 01111 This design example supports the following values 5 16 TX Path Operation e 01011 e 01100 e 01101 e 01110 e O1111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr n 4 0 value always match the system parameter N value Connect this signal to the TX DLL csr_n output pin TX Path Operation The data transfer protocol between the Avalon ST interface and the TX path transport layer is data transfer with backpressure where ready latency 0 Altera Corporation JESD204B IP Core Design Guidelines CJ Send Feedback
175. ore ensures that at least one SYSREF rising edge is sampled before exiting CGS phase and entering ILAS phase This is to prevent a race condition where the sync_n is deasserted before SYSREF is sampled SYSREF sampling is crucial to ensure deterministic latency in the JESD204B Subclass 1 system TX Subclass 2 Similar to Subclass 1 mode the JESD204B TX IP core is in CGS phase upon reset deassertion The LMFC alignment between the converter and IP core starts after syNc_Nn deassertion The JESD204B TX IP core detects the deassertion of sync_n and compares the timing to its own LMFC The required adjustment in the link clock domain is updated in the register map You need to update the final phase adjustment value in the registers for it to transfer the value to the converter during the ILAS phase The DAC adjusts the LMFC phase and acknowledge the phase change with an error report This error report contains the new DAC LMFC phase information which allows the loop to iterate until the phase between them is aligned JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback 4 18 Error Reporting Through SYNC_N Signal RX Subclass 0 UG 01142 2015 05 04 The JESD204B RX IP core drives and holds svuc x dev sync n signal low when it is in reset Upon reset deassertion the JESD204B RX IP core checks if there is sufficient K character to move its state machine out of synchronization request Once sufficient K character i
176. ores into your design to shorten design cycles and maximize performance You can evaluate any Altera IP core in simulation and compilation in the Quartus II software The Quartus II software also supports integration of IP cores from other sources Use the IP Catalog to efficiently parameterize and generate synthesis and simulation files for a custom IP variation The Altera IP library includes the following categories of IP cores e Basic functions e DSP functions e Interface protocols e Low power functions e Memory interfaces and controllers e Processors and peripherals Note The IP Catalog Tools IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera and other supported IP cores Related Information e IP User Guide Documentation e Altera IP Release Notes O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in
177. orting Quartus II file such as the Quartus II Settings File qsf Synopsys Design Constraints File sdc or SignalTap File stp if these files contain instance names The Quartus II software reads only the instance name and ignores the entity name in paths that specify both names Use only instance names in assignments Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 Upgrading IP Cores 3 3 Table 3 1 IP Core Upgrade Status IP Upgraded Your IP variation uses the lastest version of the IP core IP Upgrade Optional Upgrade is optional for this IP variation in the current version of the Quartus LI II software You can upgrade this IP variation to take advantage of the latest development of this IP core Alternatively you can retain previous IP core characteristics by declining to upgrade Refer to the Description for details about IP core version differences If you do not upgrade the IP the IP variation synthesis and simulation files are unchanged and you cannot modify parameters until upgrading IP Upgrade Mismatch Warning g Warning of non critical IP core differences in migrating IP to another device family IP Upgrade Required You must upgrade the IP variation before compiling in the current version of the Quartus II software Refer to the Description for details about IP core e version differences IP Upgrade Unspported Upgrade of the IP variation is not supported in the curre
178. out the rule check for parameter N value Added a new topic Integrating the JESD204B IP core in Qsys on page 3 11 Updated Figure 8 1 Figure 8 3 and Figure 8 4 Added a new table Register Access Type Convention to describe the access type for the IP core registers Added new signals description for jes 204 tx controlout and jesd204 rx controlout Added CONTROL BUS WIDTH parameter and description for the assembler and deassembler Added information on how to run the Tcl script using the Quartus II sofware before compiling the design example Updated the section on Debugging JESD204B Link Using SignalTap II and System Console on page 7 3 with verification information for TX PHY link layer interface TX link layer and TX transport layer operations Additional Information C Send Feedback UG 01142 2015 05 04 How to Contact Altera 8 3 ENCEENNU IMEEM KH June 2014 2014 06 30 Updated Figure 2 1 to show a typical system application Updated the list of core key features Updated the Performance and Resource utilization values Updated the Getting Started chapter to reflect the new IP Catalog and parameter editor Added the following new sections to further describe the JESD204B IP core features e Channel Bonding e Datapath Modes e IP Core Variation e JESD204B IP Core Testbench e JESD204B IP Core Design Considerations e TX Data Link Layer TX PHY Layer e RX Data Link Layer e RX PHY Layer
179. pling provided from the clock chip the JESD204 IP core does not directly use the device clock to sample SYSREF but instead uses the link clock to sample SYSREF Therefore the Altera PLL IP core that provides the link clock must to be in normal mode to phase compensate the link clock to the device clock Based on hardware testing to get a fixed latency at least 32 octets are recommended in an LMFC period so that there is a margin to tune the RBD release opportunity to compensate any lane to lane deskew across multiple resets If F 1 then K 32 would be optimal as it provides enough margin for system latency variation If F 2 then K 16 and above 18 20 22 24 26 28 30 32 is sufficient to compensate lane to lane deskew The JESD204B IP core implements the local multi frame clock as a counter that increments in link clock counts The local multi frame clock counter is equal to F x K 4 in link clock as units The rising edge of SYSREF resets the local multi frame clock counter to 0 There are two CSR bits that controls SYSREF sampling e csr sysref singledet resets the local multi frame clock counter once and automatically cleared after SYSREF is sampled This register also prevents CGS exit to bypass SYSREF sampling csr_sysref_alwayson resets the local multi frame clock counter at every rising edge of SYSREF that it detects This register also enables the SYSREF period checker If the provided SYSREF period violates the F and K para
180. property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01142 5 2 JESD204B IP Core Design Example 2015 05 04 Figure 5 1 Design Example Block Diagram t tx sysref I 1 Avalon ST Y Assembler 7 32Bit TX Base i Transport Core PCS gt Layer 4 Link Layer Pattern Generator 2 Avalon ST Ser DAC H gt sync n I E 3 7N Duplex ou 9 sync n Reel SerDes SPI Device test_mode rx_dev sync n syste PHY Clock D T Avalon ST m tx sysref eassembler 32Bit ase 32 Transport 4H Core x dev sync n Avalon ST User Data 3 Layer 4 Link Layer
181. ra s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 2 2 About the JESD204B IP Core UG 01142 2015 05 04 Figure 2 1 Typical System Application for JESD204B IP Core The JESD204B IP core utilizes the Avalon ST source and sink interfaces with unidirectional flow of data to transmit and receive data on the FPGA fabric interface FPGA 1 Link L Lanes Multi Device Synchronization through Subclass 1 or Subclass 2 1 Link L Lanes SYNC_N Logic Device TX l DAC Device Device Clock 2 Clock 1 1 Link L Lanes Multi Device Synchronization through Subclass 1 or Subclass 2 1 Link L Lanes SYNC_N Logic Device RX ADC Device Device Clock 2 Clock 1 Key features of the JESD204B IP core Altera Corporation Data rate of up to 12 5 Gbps Run time JESD204B parameter configuration L M F S N K CS CF MAC and PHY partitioning for portab
182. rations tab select the following configurations Common configurations L M Enable manual F configuration F N N S K Advanced configurations SCR CS CF HD ECC EN PHADJ ADJCNT ADJDIR 5 In the Configurations and Status Registers tab set the the following configurations e Device ID BankID e LaneID e Lane checksum 6 After parameterizing the core click Generate Example Design to create the simulation testbench Skip to step 8 if you do not want to generate the design example 7 Seta name for your example design directory and click OK to generate supporting files and scripts The testbench and scripts are located in the example design directory lip sim folder The Generate Example Design option generates supporting files for the following entities e IP core for simulation refer to Generating and Simulating the IP Core Testbench on page 3 8 e IP core design example for simulation refer to Generating and Simulating the Design Example on page 5 55 e IP core design example for synthesis refer to Compiling the JESD204B IP Core Design Example on page 5 57 8 Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications The parameter editor generates the top level qip or qsys IP variation file and HDL files for synthesis and simulation The top level IP variation is added to the current Quartus II project Click Project gt Add Remove Files in Projec
183. rdown Conduit phy rst ctl pll powerdown tx analogreset Conduit phy_rst_ctl_tx_analogreset 4 tx digitalreset Conduit phy rst ctl tx digitalreset tx ready Conduit phy rst ctl tx ready 4 pli locked Conduit phy rst ctl pll locked pll select Conduit phy rst ctl pll select tx cal busy Conduit phy rst ctl tx cal busy 4 il fe she Kal R Current filter my filter JZ Messages 05 Type Path Message TA 2 Warnings jesdjesd tx jesd txjesd204 tx dlb data must be exported or connected to a matching conduit jjesdjesd tx jesd Uxjesd204 tx dlb kchar data must be exported or connected to a matching conduit e 4 Info Messages jesdjesd vxinst phy inst xcvr Simplified data interface has been enabled The Native PHY will present the data control interface for the current configuration only Dynamic reconfiguration eo jesd jesd vcinst phy inst xcvr For the selected device 10X 115U2F4512SGES transceiver speed grade is 2 and core speed grade is 2 e jesd jesd txinst phy inst xcvr Note The external TX PLL IP must be configured with an output clock frequency of 2500 0 MHz e jesd xcvr atx pll a10 0 For the selected device 104X115U2F45I2SGES PLL speed grade is 2 Related Information Transport Layer on page 5 8 Pin Assignments Set the pin assignments before you compile to provide direction to the Quartus II software Fitter tool You must also specify the signals that should be assigned
184. register to pll_mgmt_ 0x02 0 0 0x01 begin Arria 10 Devices Start MIF streaming with MIF pll_mgmt_ 0x010 31 0 0x000 maximum configuration base address specified in data or value 0x02E downscale configuration 28 Related Information AN 661 Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions More information about the MIF streaming option Transceiver Reconfiguration Controller The transceiver reconfiguration controller allows you to change the device transceiver settings at any time Any portion of the transceiver can be selectively reconfigured Each portion of the reconfiguration 8 The MIF base address is 9 bits LSB The remaining bits are reserved Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 Transceiver Reconfiguration Controller 5 5 requires a read modify write operation read first then write in such a way that it modifies only the appropriate bits in a register and not changing other bits In the design example MIF approach is used to reconfigure the ATX PLL and transceiver channel in the JESD204 IP core via the Transceiver Reconfiguration Controller The number of reconfiguration interface is determined by number of lanes L number of TX_PLL different number of TX_PLL for bonded and non bonded mode Since the MIF approach reconfiguration for transceiver only supports non bonde
185. request only The sync_n signal error reporting is being masked out of this signal This signal is also asserted during software initiated synchronization mdev_sync_n 1 Input Indicates a multidevice synchronization request Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal e For subclass 0 combine the dev_sync_n signal from all multipoint links before connecting to the mdev_sync_n signal e For subclass 1 connect the dev_sync_n signal to the mdev_sync_n signal for each link respectively In a single link instance where multidevice synchronization is not needed tie the dev_ sync_n signal to this signal Signal Width Direction Description CSR jesd204 qos freme 1 Input Optional signal to indicate an empty data Up stream due to invalid data This signal is asserted high to indicate an error during data transfer from the transport layer to the TX core JESD204B IP Core Functional Description Altera Corporation LJ Send Feedback 4 34 Transmitter UG 01142 2015 05 04 a Ss es csr LI Output Indicates the number of active lanes for the link The transport layer can use this signal as a run time parameter esr fF Output Indicates the number of octets per frame The transport layer can use this signal as a run time parameter csr kI Output Indicates the number of frames per multiframe The transport
186. ribes the features available in the JESD204B IP core that you can use to achieve Subclass 1 deterministic latency in your design This section also covers some best practices for Subclass 1 implementation like constraining the incoming SYSREF signal Features available e Programmable RBD offset e Programmable LMFC offset Constraining Incoming SYSREF Signal The SYSREF signal resets the LMFC counter in the IP core for subclass 1 implementation Constraining the SYSREF signal ensures that the setup relationship between SYSREF and device clock is established The setup time is analyzed when you set the timing constraint for the SYSREF signal in the user sdc file When the setup time is met the SYSREF signal detection by the IP core is deterministic the number of link clock cycles of SYSREF signal that arrives at the FPGA pin to the LMFC counter resets is determin istic Apply the set input delay constraint on the SYSREF signal with respect to device clock in the user sdc file set input delay clock device clock name at FPGA pin sysref IO delay in ns get ports sysref name at FPGA pin gt The SYSREF IO delay is the board trace length mismatch between device clock and SYSREF For example set input delay clock device clk 0 5 get ports sysref The above statement constrains the FPGA SYSREF signal sysref with respect to the FPGA device clock device clk pin The trace length mismatch resulted in 500 ps or 0 5 ns di
187. riod 4 ltxframe clk period 8 ltxframe clk period RX Path The deassembler in the RX path consists of the tail bits dropping deassembling and multiplexing blocks Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 RX Path 5 25 Figure 5 9 RX Path Assembler Block Diagram Interfaces with JESD204B IP Core Interface with Data Link Layer and Control Unit Avalon ST JESD204B Transport Layer RX Block JESD204B IP Core Data Link Layer Data e ke ie Bus B T il Bi B jesd204_rx_link_datain L 32 1 0 ma Deassembling LUS A Multiplexing Donna Le LR jesd204 rx dataout jesd204 rx link data valid OUTPUT BUS WIDTH 1 0 jesd204 rx linkdata ready jesd204 rx linkerror bl ji i T s Configuration Register Settings Parameter L M F N VS i F1_FRAMECLK_DIV i Y F2 FRAMECLK DIV i mi vi Control Unit rxframe_clk gt rxframe_rst_n o gt gt gt p jesd204 rx data valid RX Control rxlink clk rink rst n Hm jesd204 rx data ready e Tail bit dropping block drops padded tail bits in the incoming data jesa204 rx link datain e Deassembling block rearranges the resulting data bits in a specific way according to the mapping scheme refer to Figure 5 2 e Multiplexing block sends the mult
188. roducts or services ANU S RYA 101 Innovation Drive San Jose CA 95134 UG 01142 6 2 Programmable RBD Offset 2015 05 04 Figure 6 1 Multi Stage Pipeline Register for SYSREF Signal Figure shows a two stages pipeline registers for the SYSREF signal To ore SYSREF at internal logic Paapin LL 2 1 Q D Q D LT User logic User logic stage 2 stage i pipeline pipeline IP core register register register rxlink_clk or txlink_clk Programmable RBD Offset In the RX IP core the programmable RBD offset provides flexibility for an early RBD release to optimize the latency through the IP core You can configure the RBD offset using the csr_rbd_offset field in the syncn sysref ctrl register You should set a safe RBD offset value to ensure deterministic latency from one power cycle to another power cycle Follow these steps to set a safe RBD offset value Read the RBD count from the csr rbd count field in xx statuso register Record the value Power cycle the JESD204B subsystem which consists of the FPGA and converter devices Read the RBD count again and record the value Repeat steps 1 to 3 atleast 5 times and record the RBD count values Setthecsr rbd offset accordingly with one LMFC count tolerance ON Ui d WN Perform multiple power cycles and make sure lane de skew error does not occur using this RBD offset value The RBD count should be f
189. rst n and jesd204 t x avs rst n jesd204 rx avs rst n canonly be deasserted after the transceiver comes out of reset C Transceiver Native PHY Active high reset controlled by the transceiver Digital Reset reset controller This signal resets the TX RX ise eligptiEedieeswen Li 89 PCS tx digitalreset L 1 0 The link clock frame clock and AVS clock reset signals txlink rst n rxlink rst n txframe rst n rxframe rst n and jesd204 t x avs rst n jesd204 rx avs rst n canonly be deasserted after the transceiver comes out of reset ee ee TX RX AVS CSR Active low reset controlled by the clock and Clock reset unit Typically both signals can be jess204 Fx avs rst n deasserted after the core PLL and transceiver PLL are locked and out of reset If you want to dynamically modify the LMF at run time you can program the CSRs after AVS reset is deasserted This phase is referred to as the configuration phase After the configuration phase is complete then only the txlink rst n rxlink rst n and txframe rst n rxframe rst n signals can be deasserted Related Information e Altera Transceiver PHY IP Core User Guide e Altera Arria 10 Transceiver PHY IP Core User Guide Reset Sequence Altera recommends that you assert reset for the JESD204B IP core and transport layer when powering up the PLLs and transceiver QU Refer to the Altera Transceiver PHY IP Core User Guide and Altera Arria 10 Transceiver
190. s K value to 32 as well Scrambling does not affect the link initiali zation in the CGS and ILAS phases but in the user data phase When scrambling is enabled on the ADC the FPGA descrambling option has to be turned on using the Enable scramble SCR option in the JESD204B IP core Qsys parameter editor When scrambling is enabled on the FPGA the DAC descram bling has to be turned on too 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Driv
191. s Show IP only for target device eee se Search for installed IP cores v 45 Installed IP Refresh IP catalog Ctrl R v Project Directory No Selecton Available v Show IP for all device families i v Library Show IP for active device family EAMUS v Basic Functions gt Arithmetic gt Bridges and Adaptors v Clocks PLLs and Resets x AVLICLEETRIG eene eee eee Double click to customize right click for ALTCLKCTRL p s P PL detailed information gt Configuration anc i gt VO Add version 15 0 P Miscellaneous Details ALTCLKCTRL altcikctri gt On Chip Memory Altera Corporation gt Simulation Debug and Verification EARN CES SES b DSP Supported Device Families Arria II GZ Arria V Arria V GZ Cyclone IV E Cyclone V P Interface Protocols Arria 10 Arria Il GX Cyclone IV GX Stratix V Stratix IV gt Low Power MAX 10 b Memory Interfaces and Controllers Location Aoots acds 15 0 139 nux64 Ap altera megafunctions altcikctri altcikctri fw tcl gt Processors and Peripherals lj DATASHEET P University Program amp Open Component Folder Kk Search for Partner IP Note The IP Catalog is also available in Qsys View gt IP Catalog The Qsys IP Catalog includes exclusive system interconnect video and image processing and other system level IP that are not available in the Quartus II IP Catalog For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handb
192. s detected the IP core deasserts SYNC N RX Subclass 1 The JESD204B RX IP core drives and holds the sync_n dev sync n signal low when it is in reset Upon reset deassertion the JESD204B RX IP core checks if there is sufficient K character to move its state machine out of synchronization request The IP core also ensures that at least one SYSREF rising edge is sampled before deasserting syNc_N This is to prevent a race condition where the sync_n is deasserted based on internal free running LMFC count instead of the updated LMFC count after SYSREF is sampled RX Subclass 2 The JESD204B RX IP core behaves the same as in Subclass 1 mode In this mode the logic device is always the master timing reference Upon sync_n deassertion the ADC adjusts the LMFC timing to match the IP core Error Reporting Through SYNC N Signal The JESD204 TX IP core can detect error reporting through svuc N when svNc N is asserted for two frame clock periods if F gt 2 or four frame clock periods if F 1 When the downstream device reports an error through sync_n the TX IP core issues an interrupt The TX IP core samples the syNc_N pulse width using the link clock For a special case of F 1 two frame clock periods are less than one link clock Therefore the error signaling from the receiver may be lost You must program the converter device to extend the syNc_N pulse to four frame clocks when F 1 The JESD204 RX IP core does not r
193. s for the input clock Integrating the JESD204B IP core in Qsys You can integrate the JESD204B IP core with other Qsys components within Qsys You can connect standard interfaces like clock reset Avalon MM Avalon ST HSSI bonded clock HSSI serial clock and interrupt interfaces within Qsys However for conduit interfaces you are advised to export all those interfaces and handle them outside of Qsys This is because conduit interfaces are not part of the standard interfaces Thus there is no guarantee on compatibility between different conduit interfaces Note The Transport Layer provided in this JESD204B IP core design example is not supported in Qsys Therefore you must export all interfaces that connect to the Transport Layer for example jesd204 tx link interface and connect them to a transport layer outside of Qsys 9 You can also connect conduit interfaces within Qsys but you must create adapter components to handle all the incompatibility issues like incompatible signal type and width Getting Started Altera Corporation LJ Send Feedback 3 12 Pin Assignments UG 01142 2015 05 04 Figure 3 4 Example of Connecting JESD204B IP Core with Other Qsys Components in Qsys Figure shows an example of how you can connect the IP core with other Qsys components in Qsys System jesd Path mgmt_cik
194. s0 15 0 Parallel PRBS Generator PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources for serial data links The output sequence is not truly random but repeats after 2 1 bits where X denotes the Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 201 MART Alternate Checkerboard Generator 5 7 length of the shift register Polynomial notation which the polynomial order corresponds to the length of the shift register and the period of PRBS provides a method of describing the sequence Alternate Checkerboard Generator The alternate checkerboard generator circuit consists of simple flip registers that serve as test sources for serial data links The output sequence of subsequent N bits sample is generated by inverting the previous N bits counting from LSB to MSB of the same data pattern at that clock cycle The first N bits sample from LSB of the data pattern on next clock cycle is generated by inverting the last N bits sample on the MSB of the data pattern on current clock cycle Ramp Wave Generator The ramp wave generator circuit consists of a simple register and adders that serve as test sources for serial data links The output sequence of subsequent N bits sample is an increment by one of the previous N bits sample counting from LSB to MSB in the same data pattern at that clock cycle The first N bits sample from LSB of the data pattern on n
195. sion begins at the second LMFC boundary instead of the third LMFC boundary in Figure 6 7 The latency is shortened by 4 LMFC counts or link clock cycles Link dock rus at by SRE ele eases G IP core H Second LMEC p IM tx_systef__ L i boundary ey i f First LMFC i i boundary i Nr LAN Free running LMFC counter 0 1 2 3 x 4 S K 7 X 0 1 2 3X 45 SS C lt 0 1 2 3 Internal LMFC eunte resets j csr_Imfc_offset 0 SYNC_N deassertion is i i i m SYNC N detected bylPcre i H i ILAS transmission by FPGA arrival at TX i H i id Zn o oO AENMEG CONNECT UNE Wine high to LMFC counter resets n i ul eal Freerumning MFC ote XA XS XE XT KOSS KEK EX TK EXT KD SKIKE KEXT XD Antena LMFC NM First LMFC boundary LMFC boundary is ILAS transmission by Fitch cst_Imfc_offset 4 at new location 1 delayed by 4 link clocks E A gt SYSREF pulse is Qo sampled by DAC 0 SYNC N iik by DAC acd INC boundary mms Em l Second m high to M LMFC ie gt B nhe FeenmigCeun lt 0 XT 19 3 SS DX XD SK EXT XOKT XIE XE XERXES The csr_Imfc_offset field provides a convenient way to achieve deterministic latency and potentially optimizing the IP core latency There are other ways that you can achieve deterministic latency by using the features available at the converters Consult the converter manufacturer for details of these features JESD204B IP Core Deterministic Latency Imple
196. sor As Control Unit e Altera Transceiver PHY IP Core User Guide More information about the transceiver PHY signals JESD204B IP Core Debug Guidelines Altera Corporation C Send Feedback 2015 05 04 UG 01142 Additional Information ES Subscribe GC Send Feedback Additional information about the document and Altera JESD204B IP Core Document Revision History ELENEINMEMN KK May 2015 2015 05 04 Added support for Cyclone V FPGA device family Updated the JESD204B IP Core Configuration values e M value from 1 32 to 1 256 e N value from 4 32 to 1 32 Updated the JESD204B IP Core FPGA Performance table Updated the JESD204B IP Core FPGA Resource Utilization table Added new parameters to the JESD204B IP Core Parameters table e Enable Capability Registers Set user defined IP identifier Enable Control and Status Registers Enable Prbs Soft Accumulators Enable manual F configuration Added new topics Timing Constraints For Input Clocks on page 3 13 e JESD204B IP Core Deterministic Latency Implementation Guidelines on page 6 1 Revised the note in Simulating the IP Core Testbench to state that VHDL is not supported in Aldec Riviera for Arria 10 devices only Updated Figure 8 16 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent
197. summary of your chosen settings in the New Project Wizard window then click Finish to complete the Quartus II project creation Parameterizing and Generating the IP Core Before you begin Refer to Table 3 6 for the IP core parameter values and description 1 In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core you want to customize 2 Specify a top level name for your custom IP variation This name identifies the IP core variation files in your project If prompted also specify the target Altera device family and output file HDL preference Click OK 3 In the Main tab set the following options e Jesd204b wrapper Data path e Jesd204b subclass e Data Rate e PCS Option PLL Type Bonding Mode e PLL CDR Reference Clock Frequency Enable Bit reversal and Byte reversal Enable Transceiver Dynamic Reconfiguration Enable Altera Debug Master Endpoint e Enable Capability Registers 9 To include existing files you must specify the directory path to where you installed the JESD204B IP core You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software Getting Started Altera Corporation LJ Send Feedback 3 8 Generating and Simulating the IP Core Testbench rige Setuser defined IP identifier Enable Control and Status Registers Enable Prbs Soft Accumulators 4 In the Jesd204b Configu
198. t bit for each lane should be o JESD204B IP Core Debug Guidelines Altera Corporation CJ Send Feedback UG 01142 7 4 Debugging JESD204B Link Using SignalTap Il and System Console 2015 05 04 Measure the rxphy_clk or txphy c1k frequency by connecting the clock to the CLKOUT pin on the FPGA The frequency should be the same as link clock frequency Link Layer Verify the RX PHY link layer interface operation through these signals in the ip variant name inst phy v e jesd204 rx pcs data e jesd204 rx pcs data valid e jesd204 rx pcs kchar data e jesd204 rx pcs errdetect e jesd204 rx pcs disperr Verify the RX link layer operation through these signals in the ip variant name v e jesd204 rx avs rst n e rxlink rst n reset n e rx sysref for Subclass 1 only IX dev sync n e jesd204 rx int e alldev lane aligned e dev lane aligned e rx somf Use the rxlink_c1k signal as the sampling clock Verify the TX PHY link layer interface operation through these signals in the lt ip_variant_name gt _inst_phy v e jesd204_tx_pcs_data e jesd204_rx_pcs_kchar_data Verify the TX link layer operation through these signals in the lt ip_variant_name gt v e jesd204_tx_avs_rst_n e txlink rst n reset n e tx sysref for Subclass 1 only e sync n e tx dev sync n e mdev sync n e jesd204 tx int Altera recommends that you verify the JESD204B functionality by accessing the DAC SPI registers or any debug feature provided
199. t in previous frame the transmitter encodes the octet as F character K28 7 if it fits the rules above JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback UG 01142 4 8 TX PHY Layer 2015 05 04 Character replacement for scrambled data The character replacement for scrambled data in the IP core follows these JESD204B specification rules e At end of frame not coinciding with end of multi frame which equals to OxFC D28 7 the transmitter encodes the octet as F character K28 7 e At end of multi frame which equals to 0x7C the transmitter replaces the current last octet as A character K28 3 For devices that do not support lane synchronization only F character replacement is done At every end of frame regardless of whether the end of multi frame equals to OxFC D28 7 the transmitter encodes the octet as F character K28 7 if it fits the rules above TX PHY Layer The 8B 10B encoder encodes the data before transmitting them through the serial line The 8B 10B encoding has sufficient bit transition density 3 8 transitions per 10 bit symbol to allow clock recovery by the receiver The control characters in this scheme allow the receiver to e synchronize to 10 bit boundary e insert special character to mark the start and end of frames and start and end of multi frames e detect single bit errors The JESD204 IP core supports transmission order from MSB first as well as LSB first For MS
200. t to manually add a qip or qsys file to a project Make appropriate pin assignments to connect ports Note Some parameter options are grayed out if they are not supported in a selected configuration or it is a derived parameter Generating and Simulating the IP Core Testbench You can simulate your JESD204B IP core variation by using the provided IP core demonstration testbench To use the JESD204B IP core testbench follow these steps 1 Generate the simulation model Refer to Generating the Testbench Simulation Model on page 3 9 2 Simulate the testbench using the simulator specific scripts that you have generated Refer to Simulating the IP Core Testbench on page 3 9 Note Some configurations are preset and are not programmable in the JESD204B IP core testbench For more details refer to JESD204B IP Core Testbench on page 3 21 or the README txt file located in the lt example_design_directory gt ip_sim folder Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 Generating the Testbench Simulation Model 3 9 Generating the Testbench Simulation Model To generate the testbench simulation model execute the generated script gen_sim_verilog tcl or gen sim vhdl tcl located in the lt example_design_directory gt ip_sim folder To run the Tcl script using the Quartus II sofware follow these steps 1 2 3 4 Launch the Quartus II software On the View menu click Utility Windows Tcl Console
201. the Avalon ST source and sink interfaces There is no backpressure mechanism implemented in this core The JESD204B IP core expects continuous stream of data samples from the upstream device JESD204B IP Core Functional Description Altera Corporation CJ Send Feedback UG 01142 4 4 Transmitter 2015 05 04 Avalon MM Interface The Avalon MM slave interface provides access to internal CSRs The read and write data width is 32 bits DWORD access The Avalon MM slave is asynchronous to the txlink_clk txframe_clk rxlink clk and rxframe clk clock domains You are recommended to release the reset for the CSR configuration space first All run time JESD204B configurations like L F M N N CS CF and HD should be set before releasing the reset for link and frame clock domain Each write transfer has a write WaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle and readLatency of 1 cycle Related Information Avalon Interface Specification More information about the Avalon ST and Avalon MM interfaces including timing diagrams Transmitter The transmitter block which interfaces to DAC devices takes one of more digital sample streams and converts them into one or more serial streams The transmitter performs the following functions e Data scrambling e Frame or lane alignment Character generation e Serial lane monitoring e 8B 10B encoding e Data serializer Figure 4 3 Transmitter Data Path Block Diagram
202. the table below If your setting in the Qsys parameter editor does not match one of the LMF and bonded mode parameter values in Table the design example is generated with the default values of LMF 124 Table 5 19 Static and Dynamic Reconfiguration Parameter Values Supported Link L Reference Frame Link F1_ F2_ Clock Clock Clock FRAMECLK FRAMECLK_ DIV DIV Static Bonded Non bonded 2 1 1 2 153 6 153 6 153 6 2 Bonded Non bonded 1 1 1 4 153 6 153 6 153 6 1 Bonded Non bonded 1 1 2 4 153 6 153 6 153 6 1 Bonded Non bonded 1 1 4 8 153 6 76 8 153 6 1 Bonded Non bonded 1 2 1 1 153 6 153 6 153 6 4 Bonded Non bonded 1 2 1 2 153 6 153 6 153 6 2 Bonded Non bonded 1 p il 4 153 6 153 6 153 6 1 Bonded Non bonded 2 2 2 2 153 6 153 6 153 6 2 Bonded Non bonded 1 p 2 4 153 6 153 6 153 6 1 Bonded Non bonded 1 2 4 4 153 6 153 6 153 6 1 Bonded Non bonded 1 4 2 1 153 6 153 6 153 6 4 Bonded Non bonded 1 4 2 2 153 6 153 6 153 6 2 Bonded Non bonded 1 4 4 2 153 6 153 6 153 6 2 Bonded Non bonded 1 4 4 4 153 6 153 6 153 6 1 Bonded Non bonded 1 4 8 4 153 6 153 6 153 6 1 37 Values supported or demonstrated by this design example JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback 5 42 System Parameters Reference Clock Frame Clock FRAMECLK_ F1_ DIV UG 01142 2015 05 04 F2_ FRAMECLK_ DIV
203. ting For TX path error reporting the transport layer expects a valid stream of TX data from the Avalon ST interface indicated by jesd204_tx_data_valid signal 1 as long as the jesd204_tx_data_ready remains asserted If the jesd204_tx_data_valid signal unexpectedly deasserts during this stage the transport layer reports an error to the DLL by asserting the j sd204_tx_link_error signal and deasserting the jesd204_tx_link_data_valid signal accordingly as shown in the timing diagram below JESD204B IP Core Design Guidelines CJ Send Feedback Altera Corporation UG 01142 5 24 TX Latency 2015 05 04 Figure 5 8 TX Error Reporting The jesd204_tx_data_valid signal deasserts for one frame_clk and cannot be sampled by the link_clk txframe_clk jesd204 tx data valid jesd204 tx data ready jesd204 tx link data valid jesd204 tx link error TX Latency Table 5 10 TX Latency Associated with Different F and FRAMECLK DIV Settings ET FRAMECLK DIV TX Latency 1 1 3 txframe_clk period e Maximum 5 txframe_clk period for byte 3 e Minimum 2 txframe_clk period for byte 0 1 4 1 txframe clk period 2 1 3 txframe_clk period e Maximum 4 txframe_clk period for byte 2 and byte 3 e Minimum 3 txframe_clk period for byte 0 and byte 1 2 2 ltxf rame_clk pe
204. tion Getting Started C Send Feedback UG 01142 2015 05 04 Table 3 4 Example A Original clock names in altera_ jesd204 sdc User design input clock names Frequency Timing Constraints For Input Clocks 3 15 Recommended SDC timing constraint tx_pll_ref_clk xcvr_tx_rx_refclk 250 rx_pll_ref_clk txlink_clk device_clk 125 rxlink_clk tx_avs_clk jesd204_avs_clk 100 rx_avs_clk reconfig_clk phy_mgmt_clk 75 10 create_clock name xcvr_tx_rx_refclk period 4 0 get_ports xcvr_tx_rx_refclk create_clock name device_clk period 8 0 get_ports device_clk create_clock name jesd204_avs_clk period 10 0 get_ports jesd204_avs_clk create_clock name phy_mgmt_clk period 13 3 get_ ports phy_mgmt_clk derive_pll_clocks set_clock_groups asynchronous group xcvr_tx_rx_refclk lt base and generated clock names as reported by report_clock commands gt group device_clk lt base and generated clock names as reported by report_clock commands gt JA group jesd204_avs_clk V group phy_mgmt_clk lt base and generated clock names as reported by report_clock commands gt However if your design requires you to connect the xx avs c1k and reconfig_clk to the same clock you need to put them in the same clock group The table below shows an example where the device_c1k in this design is an input into the transceiver refclk pin The IP core s
205. transport layer z reshuffles the datain 4 big endian format is This Region of the Transport Layer 2nd link clock EE F 8 in this example Is in the Link Clock Domain 32 bits of data per Ist link clock lane in the link clock i k domain is packed to id the JESD204B IP core Altera JESD IP Core The following tables show examples of data mapping for L 4 F 1 2 4 8 and M S 2 4 8 16 The configurations that the transport layer support are not limited to these examples Table 5 6 Data Mapping for F 1 L 4 Supported M__ M S 2 for F 1 L 4 and S F 1 supports either casel M 1 S 2 or case2 M 2 S 1 Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 TX Path Data Remapping 5 21 Casel M 1 22 MOSO FOF4 jesd204 tx MOS1 F8F12 1st frameclk datain 31 0 F8F12 FOF4 Case2 M 2 S 1 MO0SO0 FOFA M1S0 F8F12 Casel M 1 S 2 MOSO F1F5 jesd204_tx_ MOS1 F9F13 2nd frameclk datain 31 0 F9F13 F1F5 Case2 M22 S 1 MOS0 F1F5 Fl MISO F9F13 FRAMCIK DIV2162 Casel M 1 22 M0OSO F2F6 jesd204_tx_ MOSI FIOF14 3rd frameclk datain 31 0 F10F114 F2F6 Case2 M 2 S 1 MOSO F2F6 M1S0 F10F14 Casel M 1 S 2 MOSO F3F7 jesd204_tx_ MOSI FI1F15 4th frameclk datain 31 0 F11F15 F3E7 Case2 M 2 S 1 MOSO F3F7 M1S0 F11F15 Fl jesd204 tx datain 127 0 F11F15 F3F7 F10F114 F2F6 F9F13 F1F5 F8F12 J FRAMCLK_ FO
206. tting Then compile each of the setting to get a total of four MIF files two for TX PLL and two for channel MIF Then merge the files into one phy mif Only the JESD204B IP cores with maximum configuration is used in final compilation Maximum TX PLL Configuration MIF WIDTH 16 DEPTH 186 ADDRESS RADIX UNS DATA RADIX BIN CONTENT BEGIN 0 0000000000100001 Start of MIF opcode TX PLL 6144Mbps 1 0000000000100010 10 0011000000000000 11 1 0000000000011111 End of MIF opcode Maximum Channel Configuration MIF 12 0000000000100001 Start of MIF opcode Channel 6144Mbps 13 0000000000000010 Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 2015 05 04 MIF ROM 5 53 88 91 0000000000000000 92 0000000000011111 End of MIF opcode Downscale TX PLL Configuration MIF 93 0000000000100001 Start of MIF opcode TX PLL 3072Mbps 94 0000000000100010 103 0011000000000000 104 0000000000011111 End of MIF opcode Downscale Channel Configuration MIF 105 0000000000100001 Start of MIF opcode Channel 3072Mbps 106 5 0000000000000010 181 184 i 0000000000000000 185 0000000000011111 End of MIF opcode END PHY Arria 10 The MIF format is fixed by the PHY You need to generate two JESD204B IP cores with maximum and downscale setting Then compile each of the setting to get a total of four MIF files two
207. tx data valid P jesd204 tx data ready gt jesd204 tx link data valid p jesd204_tx_link_error TX Control Control Unit E txframe_clk tframe rst n 9 txlink_clk l txlink_rst_n Note 1 The DATA_BUS_ WIDTH value is the data input bus width size which depends on the F and L parameter bus_width M S N F M S N_PRIME 8 L M S 8 F L N_PRIME bus_width 8 F L N N_PRIME e Tail bits padding block pads incoming data jesd204_tx_datain with 0 if N lt 16 so that the padded data is 16 bits per sample e Assembling block arranges the resulting data bits in a specific way according to the mapping scheme refer to Figure 5 2 e Multiplexing block sends the multiplexed data to the DLL interface determined by certain control signals from the TX control block Table 5 4 Assembler Parameter Settings L Number of lanes per converter device 1 8 F Number of octets per frame 1 2 4 8 CS Number of control bits or conversion sample 0 3 N Number of conversion bits per converter 12 16 N Number of transmitted bits per sample in the user data format 16 JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 12 TX Path 2015 05 04 Fl FRAMECLIK Only applies to cases where F 1 1 4 DIV The divider ratio on the zame c1k The assembler always use the post divided frame clk txframe_clk 99 F2 FRAMECIK Only applies to cases where
208. ty format e Off Data should not cross the lane boundary Enable Error Code On Off Turn on this option to enable error code correction ECC Correction ECC EN for memory blocks Phase adjustment request On Off Turn on this option to specify the phase adjustment PHADJ request to the DAC e On Request for phase adjustment e Off No phase adjustment This parameter is valid for Subclass 2 mode only Adjustment resolution 0 15 Set the adjustment resolution for the DAC LMFC step count ADJCNT This parameter is valid for Subclass 2 mode only Direction of adjustment Advance Select to adjust the DAC LMFC direction ADJDIR or This parameter is valid for Subclass 2 mode only Configurations and Status Registers Tab Device ID 0 255 Set the device ID number Bank ID 0 15 Set the device bank ID number Lane ID 0 31 Set the lane ID number Lane checksum 0 255 Set the checksum for each lane ID Altera Corporation Getting Started C Send Feedback UG 01142 2015 05 04 Related Information JESD204B IP Core Component Files 3 21 Performance and Resource Utilization on page 2 6 JESD204B IP Core Component Files The following table describes the generated files and other files that may be in your project directory The names and types of generated files specified may vary depending on whether you create your design with VHDL or Verilog HDL Table 3 7 Generated Files ee E
209. ually upgrade an individual IP core select the IP core and then click Upgrade in Editor or simply double click the IP core name The parameter editor opens allowing you to adjust parameters and regenerate the latest version of the IP core Figure 3 2 Upgrading IP Cores Description Release Notes 15 0 Updated IP configuration rules Release Notes IP upgrade is required The option one time for the parameter DFE adaptation mode is not valid anymore If its value is one time auto upgrade will map its value to continuous If this is not a desired mapping you need to upgrade manually 14 1 Support for silicon revision was added 15 0 Analog bit settings were changed IP upgrade is optional You will need to update your design if you are migrating to Arria 10 from a 28nm device family because the IP ports have changed IP upgrade is optional File my atx pli qsys my native phy asys my sdi2 qsys my viterbi qsys v Upgrade IP Components The following IP components are used in your design You should upgrade outdated components to the latest version IP Upgrade requires the IP core s qip or qsys file within the original Quartus II generated file structure Auto Upgrade pgi 4 e e e Suppori ted eun s Entity IP Component Version Device Family Regan A my atx pil Arria 10 Transceiver ATX PLL E Arria 10 v Success H a Auto Upgrade successful Upgr
210. unctional Description J send Feedback Altera Corporation 4 40 Receiver UG 01142 2015 05 04 ETE jesd204_rx_avs_ waitrequest Output This signal is asserted by the Avalon MM slave to indicate that it is unable to respond to a read or write request The JESD204B IP core ties this signal to 0 to return the data in the access cycle Direction Description JESD204 Interface yo Input SYSREF signal for JESD204B Subclass 1 implementation For Subclass 0 and Subclass 2 mode tie off this signal to 0 dev_synce_n Output Indicates a SYNC from the receiver This is an active low signal and is asserted 0 to indicate a synchronization request Instead of reporting the link error through this signal the JESD204B IP core uses the jesd204 rx int signal to interrupt the CPU sefl Output Indicates a start of frame e 3 start of frame for jesd204_rx_link_ data 31 24 e 2 start of frame for jesd204_rx_link_ data 23 16 e 1 start of frame for jesd204_rx_link_ data 15 8 e 0 start of frame for jesd204_rx_link_ cata lt lt 0 somf Output Indicates a start of multiframe e 3 start of multiframe for jesd204_rx_link_ data 31 24 e 2 start of multiframe for jesd204_rx_link_ data 23 16 e l start of multiframe for jesd204_rx_link_ data 15 8 e 0 start of multiframe for jesd204_rx_link_ data 7 0 gev_lane_aligned Output Indicates that all lanes for this devi
211. while the system console provides access to the JESD204B IP core register sets through the Avalon MM interfaces The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues To use the system console your design must contain a Qsys subsystem with the JTAG to Avalon MM Master bridge component and the Merlin slave translator ports that connect to the JESD204B IP core Avalon MM interface PHY Layer Verify the RX PHY status through these signals in the ip variant name v e rx is lockedtodata e rx analogreset e rx digitalreset e IX cal busy Verify the TX PHY status through these signals in the ip variant name v e pll locked e pll powerdown e tx analogreset e tx digitalreset e tx cal busy Verify the RX TX PHY status through these signals in the ip variant name v e rx is lockedtodata e rx analogreset e rx digitalreset e IX cal busy e rx seriallpbken e pll locked e pll powerdown e tx analogreset e tx digitalreset e tx cal busy Use the rxphy_clk 0 or txphy c1k 0 signal as sampling clock for the SignalTap II For a normal operation of the JESD204B RX path the xx is 1ockedtodata bit for each lane should be 1 while the xx cai busy rx analogreset and rx digitalreset bit for each lane should be 0 For a normal operation of the JESD204B TX path the p11 1ockea bit for each lane should be 1 while the tx cal busy pll powerdown tx analogreset and tx digitalrese
212. xframe clk frequency are derived from the formula listed in this table f frame txframe_clk frequency f frame txframe_clk frequency 1 ftxlink X 4 F1_FRAMECLK_DIV f xink X 4 F1_FRAMECLK_DIV 2 ftxlink X 2 F2_FRAMECLK_DIV fixlink X 2 F2_FRAMECLK_DIV 4 ftxlink frxlink 8 ftxlink 2 frxtink 2 Data Bit and Content Mapping Scheme One major function of the transport layer is to arrange the data bits in a specific way between the Avalon ST interface and the DLL in the JESD204B IP core Figure 5 2 shows the mapping scheme in the transport layer across various TX to RX interfaces for a specific system configuration JESD204B IP Core Design Guidelines Altera Corporation CJ Send Feedback UG 01142 5 10 TX Path 2015 05 04 Figure 5 2 Mapping of Data Bit and Content Across Various Interfaces LMF 112 N 12 N 16 S 1 T represents the tail bits Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 111109 8 17 6 5 4 3 2 1 0 vlan interact anspor Layer 1 10 9 8 C 6 159 a C2 CO o 2ndjesd204 tx ctrlin 0 Avalon ST interface to Transport Layer NP qm e cede M 11 10 al al 7 6 s wl Bl 02 1stjesd204 tx ctrlin 0 Avalon ST interface to Transport Layer jesd204 tx link datain 31 0 11
213. y link0 and link1 M 2 denoted by m0 and m1 S Z1 N 16 e avst usr dout 15 0 linkO m0 15 0 e avst usr dout 31 16 link0 m1 15 0 e avst usr dout 47 32 link1 m0 15 0 e avst usr dout 63 48 link1 m1 15 0 Indicates whether the data from the transport layer to the Avalon ST sink interface is valid or invalid e 0 data is invalid e 1 data is valid avst usr dout ready frame Input Indicates that the Avalon ST sink interface is ready to accept data from the transport layer e O Avalon ST sink interface is not ready to receive data e 1 Avalon ST sink interface is ready to receive data Altera Corporation JESD204B IP Core Design Guidelines C Send Feedback UG 01142 m 2015 05 04 Example Feature Dynamic Reconfiguration n Direction Description test moce 2e0 teon c Imput Specifies the operation mode e 0000 Normal mode The design example takes data from the Avalon ST source e 1000 Test mode The design example generates alternate checkerboard data pattern e 1001 Test mode The design example generates ramp wave data pattern e 1010 Test mode The design example generates the PRBS data pattern e Others Reserved Clock Direction Description Domain Status zz is lockedtodata device Output Asserted to indicate that the RX CDR PLL is locked EE prs to the RX data and the RX CDR has changed from LTR to LTD mode data_err

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