Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Contents
1. The fbc1k port is aligned with the input clock e Ifyou select the zero delay buffer mode the PLL must feed an external clock output pin and compensate for the delay introduced by that pin The signal observed on the pin is synchronized to the input clock The PLL clock output connects to the altbidir port and drives zdbfbc1k as an output port If the PLL also drives the internal clock network a corresponding phase shift of that network occurs e Ifyou select the lvds mode the same data and clock timing relationship of the pins at the internal SERDES capture register is maintained The mode compensates for the delays in LVDS clock network and between the data pin and clock input pin to the SERDES capture register paths Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide GJ Send Feedback UG 01155 2015 05 04 Altera IOPLL IP Core Parameters PLL Tab 3 Number of Clocks 1 9 Specifies the number of output clocks required for each device in the PLL design The requested settings for output frequency phase shift and duty cycle are shown based on the number of clocks selected Specify VCO Frequency Turn on or Turn off Allows you to restrict the VCO frequency to the specified value This is useful when creating a PLL for LVDS external mode or if a specific dynamic phase shift step size is desired VCO Frequency e When Enable physical output clock parameters is turned on displays the VCO frequen2. 2015 05 04 Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide UG 01155 ES subscribe G Send Feedback The Altera IOPLL megafunction IP core allows you to configure the settings of Arria 10 I O PLL Altera IOPLL IP core supports the following features Supports six different clock feedback modes direct external feedback normal source synchronous zero delay buffer and LVDS mode Generates up to nine clock output signals for the Arria 10 device Switches between two reference input clocks Supports adjacent PLL adjp11in input to connect with an upstream PLL in PLL cascading mode Generates the Memory Initialization File mif and allows PLL dynamic reconfiguration Supports PLL dynamic phase shift Related Information Introduction to Altera IP Cores Provides more information about the Altera IP cores and the parameter editor Operation Modes on page 8 Output Clocks on page 8 Reference Clock Switchover on page 9 PLL to PLL Cascading on page 9 Device Family Support The Altera IOPLL IP core only supports the Arria 10 device family Altera IOPLL IP Core Parameters The Altera IOPLL IP core parameter editor appears in the PLL category of the IP Catalog Altera lIOPLL IP Core Parameters PLL Tab Table 1 Altera IOPLL IP Core Parameters PLL Tab Device Family Arria 10 Specifies the device family 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGAC
3. Mode Zero Delay Buffer External Feedback Modes EBIN LVDS Compensation Mode LVDS Clock Network Source Synchronous Normal Modes GCLK RCLK Network Altera Corporation UG 01155 8 PLL Lock 2015 05 04 The following terms are commonly used to describe the behavior of a PLL e PLL lock time also known as the PLL acquisition time PLL lock time is the time for the PLL to attain the target frequency and phase relationship after power up after a programmed output frequency change or after a PLL reset Note Simulation software does not model a realistic PLL lock time Simulation shows an unrealisti cally fast lock time For the actual lock time specification refer to the device datasheet e PLL resolution the minimum frequency increment value of a PLL VCO The number of bits in the m and n counters determine the PLL resolution value e PLL sample rate the Frer sampling frequency required to perform the phase and frequency correction in the PLL The PLL sample rate is frpp N PLL Lock The PLL lock is dependent on the two input signals in the phase frequency detector The lock signal is an asynchronous output of the PLLs The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated lock circuitry Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal Operation Modes The Alter
4. ORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 2 Altera IOPLL IP Core Parameters PLL Tab UG 01155 2015 05 04 Component Specifies the targeted device Speed Grade Specifies the speed grade for targeted device PLL Mode Integer N PLL Specifies the mode used for the Altera IOPLL IP core The only legal selection is Integer N PLL If you need a fractional PLL you must use the Arria 10 FPLL IP core Reference Clock Specifies the input frequency for the input clock refc1k in Fr
5. a IOPLL IP core supports six different clock feedback modes Each mode allows clock multipli cation and division phase shifting and duty cycle programming The following list describes the operation modes for the Altera IOPLL IP core e Direct mode the PLL minimizes the feedback path length to produce the smallest possible jitter at the PLL output In this mode the PLL does not compensate for any clock networks e Normal mode the PLL feedback path source is a global or regional clock network minimizing clock delay from the input clock pin to the core registers through global or regional clock network e Source Synchronous mode the data and clock signals arrive at the input pins at the same time In this mode the signals have the same phase relationship at the clock and data ports of any Input Output Enable register e External Feedback mode the PLL compensates for the foc1k feedback input to the PLL thus minimizing the delay between the input clock pin and the feedback clock pin e Zero Delay Buffer mode the PLL feedback path is confined to the dedicated PLL external output pin The clock port driven off chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output e LVDS mode maintains the same data and clock timing relationship of the pins at the internal SERDES capture register This mode compensates for the LVDS clock network delay plus any delay difference between the d
6. ata pin and clock input pin to the SERDES capture register paths The compensation mimic path mimics the clock and data delay of the receiver side Output Clocks The Altera IOPLL IP core can generate up to nine clock output signals The generated clock output signals clock the core or the external blocks outside the core You can use the reset signal to reset the output clock value to 0 and disable the PLL output clocks Altera Corporation Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide GJ Send Feedback UG 01155 2015 05 04 Reference Clock Switchover 9 Each output clock has a set of requested settings where you can specify the desired values for output frequency phase shift and duty cycle The desired settings are the settings that you want to implement in your design The actual values for the frequency phase shift and duty cycle are the closest settings best approximate of the desired settings that can be implemented in the PLL circuit Reference Clock Switchover The reference clock switchover feature allows the PLL to switch between two reference input clocks Use this feature for clock redundancy or for a dual clock domain application such as in a system The system can turn on a redundant clock if the primary clock stops running Using the reference clock switchover feature you can specify the frequency for the second input clock and select the mode and delay for the switchover The clock loss detecti
7. cy based on the values for Reference Clock Frequency Multiply Factor M Counter and Divide Factor N Counter e When Enable physical output clock parameters is turned off allows you to specify the requested value for the VCO frequency The default value is 600 0 MHz Give clock global name Turn on or Turn off Allows you to rename the output clock name Clock Name The user clock name for Synopsis Design Constraints SDC Desired Frequency Specifies the output clock frequency of the corresponding output clock port outc1k in MHz The default value is 100 0 MHz The minimum and maximum values depend on the device used The PLL only reads the numerals in the first six decimal places Actual Frequency Allows you to select the actual output clock frequency from a list of achievable frequencies The default value is the closest achievable frequency to the desired frequency Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output clock port outc1k in picoseconds ps or degrees Desired Phase Shift Specifies the requested value for the phase shift The default value is 0 ps Actual Phase Shift Allows you to select the actual phase shift from a list of achievable phase shift values The default value is the closest achievable phase shift to the desired phase shift Desired Duty Cycle 0 0 100 0 Specifies the requested value for the duty cycl
8. e The default value is 50 0 Actual Duty Cycle Allows you to select the actual duty cycle from a list of achievable duty cycle values The default value is the closest achievable duty cycle to the desired duty cycle This parameter is only available when Enable physical output clock parameters is turned off Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide CJ Send Feedback Altera Corporation 4 Altera IOPLL IP Core Parameters Settings Tab UG 01155 2015 05 04 Multiply Factor M 4 511 Specifies the multiply factor of m counter Counter The legal range of the m counter is 4 511 However restric tions on the minimum legal PFD frequency and maximum legal VCO frequency restrict the effective m counter range to 4 160 Divide Factor N 1 511 Specifies the divide factor of N counter Counter The legal range of the N counter is 1 511 However restric tions on the minimum legal PFD frequency restrict the effective range of the counter to 1 80 Divide Factor C 1 511 Specifies the divide factor for the output clock c counter Counter Altera IOPLL IP Core Parameters Settings Tab Table 2 Altera IOPLL IP Core Parameters Settings Tab PLL Bandwidth Preset Low Medium Specifies the PLL bandwidth preset setting The default or High selection is Low PLL Auto Reset Turnonor Automatically self resets the PLL on loss of lock Turn off Create a s
9. econd input clk Turnonor Turn on to provide a backup clock attached to your PLL refclkT Turn off that can switch with your original reference clock Second Reference Clock Selects the frequency of the second input clock signal The Frequency default value is 100 0 MHz The minimum and maximum value is dependent on the device used Create an active_clk signal Turnonor Turn on to create the activec1k output The activeclk to indicate the input clock Turn off output indicates the input clock which is in use by the PLL in use Output signal low indicates refc1k and output signal high indicates refclkl Create a clkbad signal for Turnonor Turnon to create two clkbad outputs one for each input each of the input clocks Turn off clock Output signal low indicates the clock is working and output signal high indicates the clock is not working This parameter is only available when Enable physical output clock parameters is turned on Altera Corporation Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide G send Feedback UG 01155 2015 05 04 Altera IOPLL IP Core Parameters Settings Tab 5 Switchover Mode Automatic Specifies the switchover mode for design application The IP Switchover supports three switchover modes S Manua If you select the Automatic Switchover mode the PLL witchover or cae Automatic circuitry monitors the selected reference clock If one S
10. equency MHz The default value is 100 0 MHz The minimum and maximum value is dependent on the selected device Enable Locked Output Turn onor Turn on to enable the locked port Port Turn off Enable physical output Turn onor Turn on to enter physical PLL counter parameters instead of clock parameters Turn off specifying a desired output clock frequency Operation Mode direct Specifies the operation of the PLL The default operation is external direct mode eors e Ifyou select the direct mode the PLL minimizes the normal length of the feedback path to produce the smallest source E possible jitter at the PLL output The internal clock and synchronous zero delay external clock outputs of the PLL are phase shifted with maa ak respect to the PLL clock input In this mode the PLL does Altera Corporation not compensate for any clock networks e Ifyou select the normal mode the PLL compensates for the delay of the internal clock network used by the clock output If the PLL is also used to drive an external clock output pin a corresponding phase shift of the signal on the output pin occurs e Ifyou select the source synchronous mode the clock delay from pin to I O input register matches the data delay from pin to I O input register e Ifyou select the external feedback mode you must connect the fbclk input port to an input pin A board level connection must connect both the input pin and external clock output port fboutclk
11. extswitch Input Optional Assert the ext switch signal high 1 b1 for at least 3 clock cycles to manually switch the clock activeclk Output Optional Output signal to indicate which reference clock source is in used by I O PLL clkbad Output Optional Output signal that indicates the status of reference clock source is good or bad cascade_out Output Optional Output signal that feeds into downstream I O PLL adjpllin Input Optional Input signal that feeds from upstream I O PLL outelk _ Output Optional Output clock from I O PLL Altera Corporation Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide CJ Send Feedback UG 01155 2015 05 04 Document Revision History 11 Document Revision History a May 2015 2015 05 04 Updated the description for Enable access to PLL LVDS_CLK LOADEN output port parameter in Altera IOPLL IP Core Parameters Settings Tab table Added a link to the Signal Interface Between Altera IOPLL and Altera LVDS SERDES IP Cores table in the I O and High Speed I O in Arria 10 Devices chapter August 2014 2014 08 18 Initial release Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide Send Feedback Altera Corporation
12. l Interface Between Altera IOPLL and Altera LVDS SERDES IP Cores table in the I O and High Speed I O in Arria 10 Devices chapter Enable access to the PLL Turnonor Turn on to enable the PLL DPA output port DPA output port Turn off Enable access to PLL Turnonor Turn on to enable the PLL external clock output port external clock output port Turn off Specifies which outclk to be CO C8 Specifies the outc1k port to be used as extclk_out 0 used as extclk_out 0 source source Specifies which outclk to be CO C8 Specifies the outc1k port to be used as extclk_out 1 used as extclk_out 1 source source Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide CJ Send Feedback Altera Corporation UG 01155 6 Altera IOPLL IP Core Parameters Cascading Tab 2015 05 04 Related Information Signal Interface Between Altera IOPLL and Altera LVDS SERDES IP Cores Provides more information about PLL lvds_clk and loaden signals when the PLL is in LVDS mode Altera IOPLL IP Core Parameters Cascading Tab Table 3 Altera IOPLL IP Core Parameters Cascading Tab Create a cascade out signal Turnonor Turnon to create the cascade_out port which indicates to connect with a Turn off that this PLL is a source and connects with a destination downstream PLL downstream PLL Specifies which outclk to be 0 8 Specifies the cascading source used as cascading source Create an adjpllin or cclk Turnonor T
13. n CJ Send Feedback 10 Ports UG 01155 2015 05 04 fbclk Input Optional The external feedback input port for the I O PLL The Altera IOPLL IP core creates this port when the I O PLL is operating in external feedback mode or zero delay buffer mode To complete the feedback loop a board level connection must connect the fbc1k port and the external clock output port of the I O PLL ioctrtelik Output Optional The port that feeds the fbc1k port through the mimic circuitry The fboutclk port is available only if the I O PLL is in external feedback mode zdbfbclk Bidirectional Optional The bidirectional port that connects to the mimic circuitry This port must connect to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I O PLL The zdbfbclk port is available only if the I O PLL is in zero delay buffer mode locked Output Optional The Altera IOPLL IP core drives this port high when the PLL acquires lock The port remains high as long as the IOPLL is locked The I O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance When the difference between the two clock signals exceeds the lock circuit tolerance the I O PLL loses lock refclkl Input Optional Second reference clock source that drives the I O PLL for clock switchover feature
14. nals from a noisy communi cation channel or distribute clock signals throughout your design Building Blocks of a PLL The main blocks of the I O PLL are the phase frequency detector PFD charge pump loop filter VCO and counters such as a feedback counter m a pre scale counter N and post scale counters c The PLL architecture depends on the device you use in your design Figure 1 Typical I O PLL Architecture For single ended clock inputs only the CLKp pin has a dedicated connection to the PLL If you use the CLKn pin ag Dedicated Clock Inputs GCLK RCLK Cascade Input from Adjacent 1 0 PLL and Dedicated refclk 4 obal or regional clock is used inclkO Lock Circuit ait inclk1 eH c N Clock Switchover Block pm m gt dkbadd gt dkbad1 gt activeclock PFD clkswitch Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide G Send Feedback To DPA Block C gt Casade Output gt locked zO to Adjacent 1 0 PLL gt GCLKs 8 roa a RCLKs LF vco f 02 5 a z a RX TX Clock B gt RIX Load Enable e e a gt FBQUT mene This FBOUT port is fed by the M counter in the PLLs 08 gt External Memory Interface DLL M Direct Compensation
15. on and reference clock switchover block has the following functions e Monitors the reference clock status If the reference clock fails the clock automatically switches to a backup clock input source The clock updates the status of the clkbad and act iveclk signals to alert the event e Switches the reference clock back and forth between two different frequencies Use the ext switch signal to manually control the switch action After a switchover occurs the PLL may lose lock temporarily and go through the reckoning process PLL to PLL Cascading Ports If you cascade PLLs in your design the source upstream PLL must have a low bandwidth setting while the destination downstream PLL must have a high bandwidth setting During cascading the output of source PLL serves as the reference clock input of the destination PLL The bandwidth settings of cascaded PLLs must be different If the bandwidth settings of the cascaded PLLs are the same the cascaded PLLs may amplify phase noise at certain frequencies The adjpllin input clock source is used for inter cascading between fracturable fractional PLLs Table 6 Altera IOPLL Ports refclk Input Required The reference clock source that drives the I O PLL rst Input Required The asynchronous reset port for the output clocks Drive this port high to reset all output clocks to the value of 0 Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide Altera Corporatio
16. urn on to create an input port which indicates that this signal to connect with an Turn off PLL is a destination and connects with a source upstream upstream PLL PLL Altera IOPLL IP Core Parameters Dynamic Reconfiguration Tab Table 4 Altera IOPLL IP Core Parameters Dynamic Reconfiguration Tab Enable dynamic reconfigu Turnonor Turn on the enable the dynamic reconfiguration of this PLL ration of PLL Turn off in conjunction with Altera PLL Reconfig IP core Enable access to dynamic Turnonor Turn on the enable the dynamic phase shift interface with phase shift ports Turn off the PLL Generate MIF file Turn onor Turn on to generate the mif file for the current PLL profile Turn off The generated mif file contains current PLL profile and a collection of physical parameters such as m N C K bandwidth and charge pump that defines that PLL You can then load this mif file into the Altera PLL Reconfig IP core Enable Dynamic Phase Turnonor Turn on to store dynamic phase shift properties for PLL Shift for MIF Streaming Turn off _ reconfiguration DPS Counter Selection C0 C8 All C Selects the counter to undergo dynamic phase shift or M Number of Dynamic Phase 1 7 Selects the number of phase shift increments The size of a Shifts single phase shift increment is equal to 1 8 of the VCO period The default value is 1 Dynamic Phase Shift Positive or Determines the d
17. witchover clock stops the circuit automatically switches to the backup clock in a few clock cycles and updates the status with Manual Override signals clkbad and activeclk e Ifyou select the Manual Switchover mode when the control signal ext switch changes from logic low to logic high and stays high for at least three clock cycles the input clock switches to the other clock The ext switch can be generated from FPGA core logic or input pin e Ifyou select Automatic Switchover with Manual Override mode when the ext switch signal is high it overrides the automatic switch function As long as ext switch remains high further switchover action is blocked To select this mode your two clock sources must be running and the frequency of the two clocks cannot differ by more than 20 If both clocks are not on the same frequency but their period difference is within 20 the clock loss detection block will detect the lost clock The PLL most likely drops out of lock after the PLL clock input switchover and needs time to lock again Switchover Delay 0 7 Turn on to create two clkbad outputs one for each input clock Output signal low indicates the clock is working and output signal high indicates the clock is not working Enable access to PLL Turnonor Turnon to enable the PLL Lvps_cLkK LOADEN output port soe Tol Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL For more information refer to the Signa
18. ynamic phase shift direction to store into Direction Negative the PLL MIF 3 This parameter is only available when Enable dynamic reconfiguration of PLL is turned on This parameter is only available when Generate MIF file is turned on This parameter is only available when Enable Dynamic Phase Shift for MIF Streaming is turned on Altera Corporation Altera I O Phase Locked Loop Altera IOPLL IP Core User Guide CJ Send Feedback UG 01155 2015 05 04 Altera IOPLL IP Core Parameters Advanced Parameters Tab Altera lIOPLL IP Core Parameters Advanced Parameters Tab Table 5 Altera IOPLL IP Core Parameters Advanced Parameters Tab Displays a table of physical PLL settings that will be Advanced Parameters implemented based on your input Functional Description An I O PLL is a frequency control system that generates an output clock by synchronizing itself to an input clock The PLL compares the phase difference between the input signal and the output signal of a voltage controlled oscillator VCO and then performs phase synchronization to maintain a constant phase angle lock on the frequency of the input or reference signal The synchronization or negative feedback loop of the system forces the PLL to be phase locked You can configure PLLs as frequency multipliers dividers demodulators tracking generators or clock recovery circuits You can use PLLs to generate stable frequencies recover sig
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