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I/O Buffer (ALTIOBUF) Megafunction User Guide

1. 101 Innovation Drive San Jose CA 95134 www altera com UG 01024 3 0 1 0 Buffer ALTIOBUF Megafunction User Guide Subscribe 2012 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as Py agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 150 9001 2008 Registered February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide N DTE RYN Contents Chapter 1 About this Megafunction POA BUR CS da prid 1 1 Device Supporti tr ____ _________ 1 1 I O
2. February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 4 Chapter 3 Functional Description Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Devices When dynamic delay chains are enabled two key primitives are used together with the I0 OBUF primitive output buffer They are the IO_CONFIG primitive and the DELAY CHAIN primitive The 10 CONFIG primitive functions to control the configuration of the necessary delay settings The necessary delay settings are set into the respective DELAY CHAIN primitive that delays the data that passes through the delay chain based on the delay settings before going through the 10 OBUF primitive output buffer The design uses the output and output enable oe path of the dynamic delay chain where both share the same 10 CONFIG settings Each of the output and oe delay chains is built from two cascaded output delay cells In this case xxx dyn delay chainla 0 the first output delay cell s dataout is connected to xxx dyn delay chain2a O0 the second output delay cell s datain where xxx represents either the output path or oe path This is because the parameters chosen during the megafunction creation are use out dynamic delay 1 and use out dynamic delay chain2 Note the cascaded nature of the delays dyn delay chainla Q the first output delay cell s delayctrlin inputs are 4 bits This actually signifies the possible delay se
3. USE DYNAMIC TERMINATION CONTROL Specifies dynamic termination control Values are TRUE and FALSE If omitted the default is FALSE No String An error is issued if parallel termination Rt is on and dynamic termination control is not connected on a bidir pin An error is issued if nt is off and dynamic termination control is connected on an input or bidirectional pin February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 22 Chapter 3 Functional Description Ports and Parameters Table 3 12 ALTIOBUF Megafunction As Bidirectional Buffer Parameter Part 2 of 2 Port Name USE_IN_DYNAMIC_DELAY_CH AIN Required No Type String Description Specifies whether the input buffer incorporates the user driven dynamic delay chain in the megafunction specifically IO_CONFIG and an input delay cell Additional input ports are io_config_clk io_config_clkena io config update and io config datain Values are TRUE and FALSE If omitted the default is FALSE USE OUT DYNAMIC DELAY C HAIN1 No String Specifies whether the output buffer incorporates a user driven dynamic delay chain in the megafunction specifically IO_CONFIG and the first output delay cell Additional input ports are io config clk io config clkena io config update and io config datain Values are TRUE and FALSE If omitted the default is FALSE USE OUT DYNAMIC DELA
4. 1 0 DATAIN DELAYCTRLIN 3 0 DATAOUT DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN oe dyn delay chain2a 0 STRATIXIII DELAY CHAIN DATAIN DELAYCTRLIN 3 0 obufa 0 DATAOUT d OE gt dataout 0 0 STRATIXIII DELAY CHAIN STRATIXIII IO OBUF February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide Chapter 1 About this Megafunction 1 0 Buffer and Dynamic Delay Integration Bidirectional Buffer The bidirectional buffer essentially combines the input buffer and the output buffer incorporating the input path output path and oe path By combining the input and output buffers the output path and oe path are placed before the buffer and the input path is placed after the buffer as shown in Figure 1 6 By following these specifications only the input path needs a register external to the megafunction The output and oe registers that are added externally to the megafunction are optional Figure 1 6 Internal Architecture of ALTIOBUF Megafunction Bidirectional Buffer Mode output delay chainia 0 ibufa_O ioconfiga 0 C PADTOINPUTREGISTERDELAYSETTING 3 0 CH CLK COs C UPDATE OUTPUTDELAYSETTING 3 0 OUTPUTDELAYSETTING 2 0 input dyn delay chaina 0 DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN output delay chain2a 0 DATAIN o
5. DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN gt STRATIXIII IO IBUF STRATIXIII IO CONFIG oe delay 0 DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN obufa 0 1 oe dyn delay chain2a 0 DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII DELAY CHAIN STRATIXIII IO OBUF dataio 1 Figure 1 7 shows an example of the ALTIOBUF megafunction bidirectional buffer mode when output oe and input path registers are used that are external to the megafunction The external register placement is similar to the input output buffers where the output and oe registers drive the datain and oe ports of the ALTIOBUF megafunction bidirectional buffer mode and the dataout port drives the input register Figure 1 7 ALTIOBUF Megafunction Bidirectional Buffer Mode Connected with External Flipflops io config clk tc bidir Ot altiobuf bidir io config output ff io config datain datain outffclk io_config_update datain 0 0 dataio 0 0 io config clkena 0 0 0 0 C gt dataout dataout 0 0 oe dataio io config clkena io config datain io config update inffclk CAU
6. eriesterminationcontrol wire io config datain io config update number of channels 1 0 oe number of channels 1 0 oe width ptc number of c widt h ptc number of c width stc number of c width stc number of c endmodule altiobuf out ALTIOBUF BIDIR module altiobuf bidir parameter intended device family parame parame parame Cer enable_bus_hold FALSE number_of_channels 1 open_drain_output FALS pu param parame parame parame parame parame 1 0 Buffer ALTIOBUF Megafunction User Guide use_differential_mode FALSE use_dynamic_termination_control use_in_dynamic_delay_chain use_out_dynamic_delay_chainl use_out_dynamic_delay_chain2 use termination control FALS nannels nannels 15 hannels seriesterminationcontrol b synthesis syn black box 1 unused FALSE FALSE FA FA pw G y SE SE February 2012 Altera Corporation Chapter 3 Functional Description 3 11 VHDL Component Declaration for the ALTIOBUF Megafunction parameter width_ptc 14 parameter width_stc 14 parameter lpm type altiobuf bidir parameter lpm hint unused input wire number of channels 1 0 datain inout wire number of channels 1 0 dataio inout wire number of channels 1 0 dataio b output wire
7. 57 The hand points to information that requires special attention 2 The question mark directs you to a software help system with related information on The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury Lj The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation
8. 7 Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix III Devices The delay only takes effect when the out_io_config_update signal is asserted for one clock cycle at 2 249 686 ps cursor 13 After the signal is de asserted the delay from out_datain at 2 450 000 ps cursor 14 to out_dataout at 2 450 750 ps cursor 15 is 750 ps This is shown in Figure 3 4 Figure 3 4 Dynamically Changing the Delay Chain Value to 750 ps Edt View Insert Format Tools Window 1516282 ps to 2724602 ps Oe S sos gum imr al RM er Ix QQQmx 1E 7altobut_design_example_1_vig_vec_tst out_datain 2 Jaltobul_design_example_1_vig_vec_tst out_datacut 2 design example 1 vig vec tst out io conhg 4 lahiobul design example 1 vig vec tit out jo config 4 Jal obul design example vig vec Ist oul jo config datain 4 slicbul design example 1 vig vec tst out jo corlig 4 Jolicbul design example 1 vig vec Now 10us Delta 7 The third part of the simulation at 2 950 173 ps cursor 16 to 3 499 919 ps cursor 17 out_io_config_clkena is asserted for approximately 11 clock cycles Because there is an 11 bit shift register in IO_CONFIG primitive io_config_clkena is asserted for 11 clock cycles When fully loaded the shift register has its bits arranged to correspond with the datain s values datain values set du
9. Also this skew changes and can change from device to device Having the ability to deskew from the fabric allows you to remove uncertainties that would have to be considered in the timing budget This allows you to gain more timing margin which allows higher frequencies Figure 1 10 shows an example of deskew Figure 1 10 Example Illustrating Deskew 5 poo L 4 por Y Y Y 7 1 deskewed _ _ D0 02 For example if the input or output bus signals are DQ 0 and DQ 1 board trace skew transmitter device skew or even FPGA package skew could cause signals that were initially aligned to become misaligned The third waveform shows the window available to the receiver for capturing the data If DQ 0 was delayed a bit to match DQ 1 a wider window would become available to the receiver The deskew delay chains are not meant to find the middle of a data valid window but just to deskew the incoming or outgoing data to widen the overall window for a bus of inputs or outputs To do this you only need to align just one edge for example the left edge of the data valid window of all the pins To find the left and right edges of the data valid window you need to do coarser adjusments one possible method is to use the new phase adjustment functionality of the PLL ALTPLL megafunction The range of the deskew delay ch
10. Buffer and Dynamic Delay Integration 1 2 Input Output OE Path aod 1 2 Input Butter M D tics me id te decease 1 3 Output DuUffer speet er tiie bed ciate ap Hien Mido rus He paren te ay e Ker 1 4 Bidirectional Buffer eerie eq ves a ed sce 1 6 Dynamic Delay Chain Valid Values 1 7 Assignments Necessary For Dynamic Delay Chain Usage 1 7 Common Applications cer te perte eR ere e pod e eder 1 8 Chapter 2 Parameter Settings Using the Port and Parameter Definitions 2 4 Chapter 3 Functional Description Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix III Devices 3 1 Generate the Output Buffer Block 3 1 View How the Megafunction is Implemented in the Technology Map Viewer 3 2 Functional Results Analyzing the Functional Behavior of the Design in ModelSim Altera Software 3 4 Verilog HDL Prototype for the ALTIOBUF Megafunction 0 cece cece eee 3 9 AL HOBUP TNE EDO 3 9 ALTIOBUFE OUT ee
11. b0000 In this case is not relevant because the output buffer does not have an input delay cell datain values set during the next three clock cycles this is b000 for the second output delay cell xxx dyn delay chain2a 0 therefore the total delay is 0 ps 0 50 datain values set during the last four clock cycles this is b0001 for the first output delay cell xxx dyn delay chainla 0 therefore the total delay is 50 ps 1 50 The total effective delay is the sum of both delay chains because the delay chains are cascaded 0 50 50 ps February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 6 Chapter 3 Functional Description Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Devices The delay only takes effect when the out_io_config_update signal is asserted for one clock cycle at 1101716 ps Cursor 10 After the signal is de asserted the delay from out_datain at 1250000 ps Cursor 4 to out_dataout at 1250050 ps Cursor 7 should be noticeable which is 50 ps This is shown in Figure 3 3 Figure 3 3 Dynamically Changing the Delay Chain Value to 50 ps wave default File Edit View Insert Format Tools Window 41675 ps to 2458315 ps gt 45 ei OO m ha es Ix wali QQemx altiobsl_design_example_1_vig_vec_tet out_datain Zatiobul_design_example_1_vig_vec_tst out_datacut 4 s
12. channels 1 downto 0 io config clk in std logic 0 io config clkena in std logic vector number of channels 1 downto 0 others gt 0 io config datain in std logic 0 io config update in std logic 0 oe in std logic vector number of channels 1 downto 0 others gt oe b in std logic vector number of channels 1 downto 0 others gt EDT parallelterminationcontrol in std logic vector width ptc number of channels 1 downto 0 others gt 0 parallelterminationcontrol b in std logic vector width ptc number of channels 1 downto 0 others gt 0 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 3 Functional Description 3 13 VHDL Component Declaration for the ALTIOBUF Megafunction seriesterminationcontrol in std_logic_vector width_stc number of channels 1 downto 0 others gt 0 seriesterminationcontrol_b in std_logic_vector width_stc number of channels 1 downto 0 others gt 0 end component ALTIOBUF_BIDIR component altiobuf_bidir generic intended device family string unused enable bus hold string FALSE left shift series termination control string FALSE number of channels natural open drain output string FALSE use differential mode string FALSE use dynamic termination control string FALSE use in dynamic delay chainl strin
13. internal architecture of the ALTIOBUF megafunction input buffer mode when NUMBER OF CHANNELS is equal to 2 and the dynamic delay chain feature is enabled The internal architecture of the megafunction itself is described in Input Buffer on page 1 3 Output Buffer on page 1 4 and Bidirectional Buffer on page 1 6 Figure 1 1 Sample ALTIOBUF Input Buffer Mode Architecture when NUMBER OF CHANNELS 2 ibufa 1 datain 1 0 input_dyn_delay_chaina_1 datain_b 1 0 IBAR O DATAIN DELAYCTRLIN 3 0 DATAOUT STRATIXIII IO IBUF STRATIXIII DELAY CHAIN ioconfiga 1 DATAIN CLK ENA UPDATE PADTOINPUTREGISTERDELAYSETTING S 0 STRATIXIII IO CONFIG ibufa 0 input dyn delay chaina 0 IBAR DATAIN DELAYCTRLIN 3 0 DATAOUT gt dataout 1 0 STRATIXIII IO IBUF STRATIXIII DELAY CHAIN ioconfiga 0 io config datain io config clk io config clkena 1 0 io config update 9 3 UPDATE DATAIN PADTOINPUTREGISTERDELAYSETTING S 0 STRATIXIII IO CONFIG Input Buffer The input buffer megafunction uses the input path of the dynamic delay chain The datain and datain b input ports of the ALTIOBUF megafunction input buffer mode connect to the i and ibar ports if differential mode is enabled of the input buffer respectively In the input path the value of the input buffer s dat
14. is used only if the use differential mode parameter is set to TRUE Table 3 12 ALTIOBUF Megafunction As Bidirectional Buffer Parameter Part 1 of 2 Port Name ENABLE BUS HOLD Required Type Description Specifies whether the bus hold circuitry is enabled Values are TRUE and FALSE When set to TRUE bus hold circuitry is enabled and the previous value instead of high impedance is No String assigned to the output port when there is no valid input If omitted the default is FALSE Note Currently ENABLE BUS HOLD and USE DIFFERENTIAL MODE cannot be used simultaneously USE DIFFERENTIAL MODE Specifies whether the bidirectional buffer is differential Values are TRUE and FALSE When set to TRUE the output is the difference between the dataio and dataio ports If omitted No String the default is FALSE Note Currently ENABLE BUS HOLD and USE_DIFFERENTIAL_MODE Cannot be used simultaneously OPEN_DRAIN_ OUTPUT Open drain mode Values are TRUE and FALSE If omitted the default is FALSE OPEN DRAIN OUTPUT and USE DIFFERENTIAL MODE cannot be used simultaneously No String USE TERMINATION CONTROL Specifies series termination control and parallel termination control Values are TRUE and FALSE If omitted the default is No String FALSE When this parameter is used for Arria GX devices and Cyclone series only series termination control is available Stratix series supports both
15. left shift series termination control Not selected 10 Click Next Page 4 appears 11 Select the options shown in Table 3 2 Table 3 2 ALTIOBUF Plug In Manager Page 4 Options Option Selection Enable input buffer dynamic delay chain Not selected Enable output buffer dynamic delay chain 1 Selected Enable output buffer dynamic delay chain 2 Selected Create a clkena port Selected 12 Click Next Page 5 appears 13 This shows the EDA tab Click Next Page 6 appears 14 Select all available output files 15 Click Finish The test output iobuffer module is built 16 On the File menu click Save View How the Megafunction is Implemented in the Technology Map Viewer This section describes how the design is implemented after full compilation and describes some of the key components of the design 1 To compile the design on the Processing menu click Ctrl K only analysis synthesis 2 When the Compilation is Successful message appears click OK 3 On the Project Navigator window expand the design hierarchy and select the test output iobuffer hierarchy level 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation Chapter 3 Functional Description 3 3 Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix III Devices 4 Right click and select Locate and then select Locate in Technology Map Viewer Figure 3 1 Figure 3 1 Viewing th
16. output iobuffer iobuf out 1 0 Buffer ALTIOBUF Megafunction User Guide 1 8 Chapter 1 About this Megafunction Common Applications You can also use the Assignment Editor as shown in Figure 1 9 and set the column fields as shown in Table 1 1 Figure 1 9 Assigning the MEMORY_INTERFACE_DATA_PIN_GROUP Asssignment S test output iobuffer u2 test outp Interface Data Pin Group lt lt new gt gt lt lt new gt gt Table 1 1 Assigning the MEMORY_INTERFACE_DATA_PIN_GROUP Asssignment Column Setting From u2 test_output_iobuffer_iobuf_out_kk21 test_output_iobuffer_i obuf_out_kk21_component obufa_0 To u2 test_output_iobuffer_iobuf_out_kk21 test_output_iobuffer_i obuf_out_kk21_component obufa_0 Assignment MEMORY_INTERFACE_DATA_PIN_GROUP Name Value 4 Enable Yes The Value field needs to be set based on Table 1 2 Table 1 2 MEMORY_INTERFACE_DATA_PIN_GROUP Value Number of Channels MEMORY_INTERFACE_DATA_PIN_GROUP Value 1 6 4 7 12 9 13 24 18 25 48 36 The design example associated with this user guide has this assignment Common Applications The I O buffers have standard capabilities such as bus hold circuitry differential mode open drain output and output enable port Te For details about these featured applications refer to the I O features chapter of the respective device handbooks One of the key applications for this meg
17. 1 zip to any working directory on your PC 2 Open the project file ALTIOBUF design example 1 qar 3 In the Quartus II software on the Tools menu click MegaWizard Plug In Manager 4 On page 1 select Create a new custom megafunction variation Click Next Page 2a appears 5 For Which device family will you be using select Stratix III oy 6 In the Which megafunction would you like to customize list click the to expand I O and select ALTIOBUF 7 For Which type of output file do you want to create select Verilog HDL 8 Name the output file test output iobuffer Click Next Page 3 appears February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide Chapter 3 Functional Description Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Devices 9 Select the options shown in Table 3 1 Table 3 1 ALTIOBUF Plug In Manager Page 3 Options Option Section Option Selection Currently selected device family Stratix Module How do you want to configure this module As an output buffer What is the number of buffers to be instantiated 1 Use bus hold circuitry Not selected Use differential mode Not selected Use open drain output Not selected Configuration Use output enable port Selected Use dynamic termination control Not selected Use series and parallel termination control Not selected Use
18. DATA PIN GROUP 4 iobuf 2 EMORY INTERFACE DATA PIN GROUP 4 iobuf n iobuf is the name of the buffer either a strati 18 36 from iobuf 0 18136 from iobuf 0 18136 from iobuf 0 18 36 from iobuf 0 0 0 epo to ixiii io for the output buffer or stratixiii io ibuf for the input buffer For the bidirectional buffer either one is acceptable Figure 1 8 shows an example of an output buffer Figure 1 8 Output Buffer ioconfiga 0 DATAIN CLK ENA UPDATE OUTPUTDELAYSETTING 1 3 0 OUTPUTDELAYSETTING2 2 0 output_dyn_delay_chainia_0 DATAIN DELAYCTRLIN 3 0 _ oe_dyn_delay_chain2a_0 DATAIN DATAOUT oe delay chain a 0 DATAIN DELAYCTRLIN 3 o DELAYCTRLIN 3 0 output dyn delay chain2a 0 DATAIN DATAOUT DELAYCTRLIN S 0 To allow this particular design to be fit add the following line in the Quartus Setting File qsf set instance assignment name M u2 test output iobuffer iobuf out kk21 _kk21_component obufa_0 u2 test output iobuffer iobuf out kk21 t0 _kk21_component obufa_0 February 2012 Altera Corporation EMORY_INT ERFACE DATA PIN GROUP 4 from test output iobuffer iobuf out test
19. If you are unfamiliar with Altera megafunctions refer to the Introduction to Megafunctions User Guide Features The ALTIOBUF megafunction provides the following features Device Support Capable of bus hold circuitry Can enable differential mode Can specify open drain output Can specify output enable port oe Can enable dynamic termination control ports for I O bidirectional buffers Can enable series and parallel termination control ports for I O output buffers and I O bidirectional buffers Can enable dynamic delay chains for I O buffers The ALTIOBUF megafunction supports the following device families Arria II GX devices Arria II GZ devices Arria V devices Cyclone III devices Cyclone IV devices Cyclone V devices HardCopy III devices HardCopy IV devices Stratix III devices Stratix IV devices Stratix V devices February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide Chapter 1 About this Megafunction 1 0 Buffer and Dynamic Delay Integration 1 0 Buffer and Dynamic Delay Integration Altera recommends that you use the ALTIOBUF megafunction to utilize the I O buffers for any purpose that includes LVDS interfaces using the ALTLVDS megafunction DDR interfaces using the ALTDDIO IN ALTDDIO OUT ALTDDIO BIDIR ALTDQ ALTDQS and ALTDO DOS megafunctions and dynamic on chip termination OCT control using the ALTOCT megafunction Input Output and OE Path The three path types use
20. TION The dynamic termination control path also contains output delay chain 1 and output delay chain 2 which are not accessible through the ALTIOBUF megafunction bidirectional buffer mode When both the oe and dynamic termination control are used the two signals oe and dynamic termination control can be out of synchronization therefore it is not recommended to switch these two signals simultaneously 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation Chapter 1 About this Megafunction V O Buffer and Dynamic Delay Integration Dynamic Delay Chain Valid Values For information about the delay chain valid values refer to the Programmable IOE Delay section of the respective device handbook or data sheet Assignments Necessary For Dynamic Delay Chain Usage If you utilize the dynamic delay chain for the I O buffer megafunction a MEMORY INTERFACE DATA PIN GROUP assignment to the I O buffer block is necessary to enable it to go through fitting This is because the megafunction utilizes the I0 CONFIG and DELAY CHAIN blocks that are associated with the use of DDR interfaces Therefore the Quartus II Fitter requires the assignment to determine the placement of the blocks with the respective 10 xBUF block The format of the MEMORY INTERFACE DATA PIN assignments generally appears as the following EMORY INTERFACE DATA PIN GROUP 4 iobuf 0 EMORY INTERFACE DATA PIN GROUP 4 iobuf 1 EMORY INTERFACE
21. To set up the ModelSim Altera software follow these steps 1 Unzip the ALTIOBUF_ex1_msim zip file to any working directory on your PC Start ModelSim Altera software On the File menu click Change Directory Select the folder in which you unzipped the files Click OK 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 3 Functional Description 3 5 Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Devices 6 On the Tools menu point to TCL and click Execute Macro The Execute Do File dialog box appears Select the ALTIOBUF_ex1_msim do file and click Open This is a script file for ModelSim that automates all the necessary settings for the simulation Verify the results by looking at the Waveform Viewer window You can rearrange signals remove signals add signals and change the radix by modifying the script in ALTIOBUF_ex1_msim do The first part of the simulation at time before 502288 ps out_datain and out_dataout do not have any delays but at 502288 ps Cursor 8 to 1054392 ps Cursor 9 out_io_config_clkena is asserted for approximately 11 clock cycles Because there is 11 bit shift register in the I0 CONFIG primitive io_config_clkena is asserted for 11 clock cycles When fully loaded the shift register has its bits arranged to correspond with the datain s values datain values set during the first four clock cycles this is
22. UMBER_OF_CHANNELS USE_DYNAMIC_TERMINATI No Strin Specifies dynamic termination control Values are True and ON_CONTROL 9 False If omitted the default is False Table 3 6 shows the input ports for the ALTIOBUF megafunction as output buffer Table 3 6 ALTIOBUF Megafunction As Output Buffer Input Ports Part 1 of 2 Port Name Required Description The output buffer input port Yes Input port NUMBER_OF_CHANNELS 1 0 wide For differential signals this port supplies the positive signal input Inputs fed to the 1 0 output buffer element Input port that feeds the datain port of 10 IG for user driven dynamic delay chain Aes No Input port used to feed input data to the serial load shift register The value is eee 1 bit wire shared among all 1 0 instances This port is available when the USE_OUT_DYNAMIC_DELAY_CHAIN1 Of USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE Input clock port that feeds the 1o_CONF IG for user driven dynamic delay chain Note that the maximum frequency for this clock is 30 MHz io_config_clk No Input port used as the clock signal of shift register block The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE Input clock enable that feeds the ena port of 10 for user driven dynamic delay cha
23. Y C HAIN2 No String Specifies whether the output buffer incorporates a user driven dynamic delay chain in the megafunction specifically 10 CONFIG and the second output delay cell Additional input ports are io config clk io config clkena io config update and io config datain Values are TRUE and FALSE If omitted the default is FALSE NUMBER OF _ CHANNELS Yes Integer Specifies the number of 1 0 buffers that must be instantiated Value must be greater than or equal to 1 A value of 1 indicates that the buffer is a 1 bit port and accommodates wires A value greater than 1 indicates that the port can be connected to a bus of width NUMBER OF CHANNELS WIDTH STC No Integer Specifies the width setting for the series termination control bus WIDTH PTC No Integer Specifies the width setting for the parallel termination control bus 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation DTE 5 Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table lists the revision history for this user guide Date Version Changes Updated device support Added references to device handbook for delay chain values Updated to new template Updated ports and parameters Added prototypes and component declarations Added sentence to 1 0 Buffer and Dynami
24. afunction is to have more direct termination control of the buffers By enabling series and parallel termination control ports for the I O output buffers and I O bidirectional buffers you can connect these ports to the ALTOCT megafunction to enable dynamic calibration for on chip termination 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 1 About this Megafunction 1 9 Common Applications Te For more information refer to the ALT OCT Megafunction User Guide and the I O features chapter of the respective device handbooks The additional dynamic termination control ports allow control when series termination or parallel termination are enabled for bidirectional buffers Parallel termination needs to only be enabled when the bi directional I O is receiving input Otherwise it needs to be disabled so that the output performance and power dissipation is optimal Another key application for this megafunction is for dynamic delay chain in the I O buffer Dynamic I O delay allows implementing automatic deskew especially for memory interfaces such as DDR3 which is handled by the memory interface intellectual property IP You need to dynamically deskew and not calculate manually because much of the skew can come from the I O buffers of either the FPGA or the other device the FPGA is interfacing with for example memory Even if the trace lengths are matched there can still be electrical skew in the system
25. ains is only designed to compensate for a reasonable amount of board and package layout skew February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide N DTE SYN 2 Parameter Settings Table 2 1 ALTIOBUF P This section describes the parameter settings for the ALTIOBUF megafunction On page 1 of the MegaWizard Plug In Manager select Create a new custom megafunction variation Edit an existing megafunction variation or Copy an existing megafunction variation On page 2a of the MegaWizard Plug In Manager specify the device family to use type of output file to create and the name of the output file You can choose AHDL tdf VHDL vhd or Verilog HDL v as the output file type On page 3 of the ALTIOBUF MegaWizard Plug In Manager you can select the module configuration an input buffer an output buffer or a bidirectional buffer specify the instantiated buffers and specify the additional options Table 2 1 lists the options available on page 3 of the ALTIOBUF MegaWizard Plug In Manager lug In Manager Page 3 Options Part 1 of 2 Option family Currently selected device Description Specify the device family you want to use How do you want to configure this module Specify whether it is an input buffer output buffer or bidirectional buffer What is the number of buffers to be instantiated Specify the number of buffers to be used This defines the size of th
26. aout port is passed into the input delay chain The dataout port of the ALTIOBUF megafunction input buffer mode is the output of the dataout delay chain You must add a register external to the megafunction either a regular DFFE or a DDIO and connect its input to the megafunction s dataout port Figure 1 2 shows the internal architecture of the input buffer in the ALTIOBUF megafunction Figure 1 2 Internal Architecture of ALTIOBUF Megafunction Input Buffer Mode ibufa 0 datain 0 0 gt STRATIXII _1O_IBUF ioconfiga 0 input delay chaina 0 io config datain gt DATAIN DATAIN io config gt CLK PADTOINPUTREGISTERDELAYSETTING 3 0 4 DELAYCTRLIN 3 0 DATAOUT gt dataout 0 0 io config clkena 0 0 gt ENA STRATIXIIL DELAY CHAIN io config update C D gt UPDATE STRATIXIII IO CONFIG February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 1 4 Chapter 1 About this Megafunction 1 0 Buffer and Dynamic Delay Integration Figure 1 3 shows how to connect the external register to the megafunction Figure 1 3 ALTIOBUF Megafunction Input Buffer Mode Connected to the External Flipflop inddcO1 wh altiobuf in io config clk io config clk input ff io config datain io config datain PRN io config update io config update dataout 0 0 D gt dataout datain datain 0 0 io config clkena io
27. bus hold circuitry is enabled and the previous value instead of high impedance is No String assigned to the output port when there is no valid input If omitted the default is FALSE Note Currently ENABLE BUS HOLD and USE DIFFERENTIAL MODE cannot be used simultaneously USE DIFFERENTIAL MODE Specifies whether the input buffer is differential Values are TRUE and FALSE When set to TRUE the output is the difference between the datain and datain_b ports If omitted the default Ne String FALSE Note Currently ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE Cannot be used simultaneously DELAY_CHAIN USE_IN_DYNAMIC_ Specifies whether the input buffer incorporates the user driven dynamic delay chain in the megafunction specifically IO_CONFIG and an input delay cell Values are TRUE and FALSE If omitted the default is FALSE No String February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 16 Chapter 3 Functional Description Ports and Parameters Table 3 5 ALTIOBUF Megafunction As Input Buffer Parameters Port Name Required Type Comments Specifies the number of 1 0 buffers that must be instantiated NUMBER OF Value must be greater than or equal to 1 A value of 1 indicates Integer that the buffer is a 1 bit port and accommodates wires a value CHANNELS greater than 1 indicates that the port can be connected to a bus of width N
28. c Delay Integration Added two last paragraph to Common Applications Added extra note to Table 3 5 Remove figures November 2007 1 0 Initial Release February 2012 3 0 November 2010 2 1 December 2008 2 0 How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support m Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide Info 2 Additional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns
29. config clkena 0 0 ENA CLR gt Output Buffer The ALTIOBUF megafunction output buffer mode uses the output and oe path of the dynamic delay chain where both share the same IO CONFIG settings Contrary to the input path in the output and oe paths you can add two optional registers which are external to the megafunction One is for the output path and the other is for the oe path Instead of connecting the input data to the datain port of the ALTIOBUF megafunction output buffer mode it is connected to the input of the registers that are external to the megafunction The output of the register is then driven to the datain port of the first output delay chain port In a similar way the inverted input oe is connected to the oe register that is external to the megafunction which drives the datain port of the first oe delay chain port Figure 1 4 shows how to connect the output and oe registers to the ALTIOBUF megafunction Figure 1 4 ALTIOBUF Output Buffer Mode Megafunction Connected with the External Flipflops tc outO1 altiobuf out io config io config clk output ff io config datain PRN io config update dataout 0 0 datain D Q datain 0 0 outffclk gt io_config_clkena 0 0 ENA 0 0 CLR oe ff PRN oe gt gt CLR io_config_clkena CD io_config_datain io confi
30. d for one clock cycle at 4 901 805 ps cursor 23 After the signal is deasserted the delay from out_datain at 5 150 000 ps cursor 24 to out_dataout at 5 151 100 ps Cursor 25 is 1 100 ps This is shown in Figure 3 6 Figure 3 6 Dynamically Changing the Delay Chain Value to 1 100 ps X wave default Edt View Insert Format Tools Window 3867678 ps to 6284386 Now 10us Delta 7 4 shi desgn example 1 2 4 example 1 vig vec Ist out jo config update MELOS RE Verilog HDL Prototype for the ALTIOBUF Megafunction You can locate the following Verilog HDL prototypes in the Verilog Design File v altera mf v in the Quartus II installation directory NedaNsynthesis directory ALTIOBUF IN module altiobuf in parameter intended device family unused parameter enable bus hold FALSE parameter number of channels 1 parameter use differential mode FALSE parameter use dynamic termination control FALSE parameter use in dynamic delay chain FALSE parameter lpm type altiobuf in parameter lpm hint unused input wire number of channels 1 0 datain input wire number of channels 1 0 datain output wire number of channels 1 0 dataout input wire number of channels 1 0 dynamicterminationcontrol input wire io config clk input wire number of channels 1 0 io config clkena input wire io config datain input w
31. d with the I O buffer in the delay chain architecture are input path output path and oe path Dynamic delay chains are integrated in the input path for input and bidirectional buffers Dynamic delay chains are integrated in the output and oe paths for output and bidirectional buffers This section describes the dynamic delay chain related components only paths share a similar configuration in which the delay cells are getting their delay control signal from the IO CONFIG component For the input path the IO CONFIG s PADTOINPUTREGISTERDELAYSETTING output port drives the DELAY CHAIN s input delay cell DELAYCTRLIN input port For the output and oe path use the IO CONFIG s OUTPUTDELAYSETTING 1 and 2 output ports to drive the DELAYCTRLIN port of the first and second output delay cells respectively The number of delay chains needed is NUMBER CHANNELS Each instance of the I O buffer includes a delay chain Assume NUMBER CHANNELS is equal to x There must be x instances of input delay chain for x input buffer and 2x instances of the first output delay chain and 2x instances of the second output delay chain output buffer because it uses the output and oe paths The bidirectional buffer combines all instances of the delay chains mentioned above 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 1 About this Megafunction 1 3 1 0 Buffer and Dynamic Delay Integration Figure 1 1 shows the
32. directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and project gt file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword sUBDESIGN and logic function names for example An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important
33. e acie PR od Cpe ra s 3 10 E eden ete dee 3 10 VHDL Component Declaration for the ALTIOBUF Megafunction 3 11 AT TIOBDIESIN 7 e tt Matar Ban ad 3 11 ALTIOBURE OUT 52 55 vend V e B ed ce c ede 3 12 AJETIOBBEESBIDIR s ec 3 13 VHDL LIBRARY USE Declaration 3 14 Ports arid Parameters oret iege hen eee Madd one ald 3 14 Additional Information Document Revision History 2 Info 1 How to Contact Altera lE UE ROUES ERES vie Wu x dg EN S ea Info 1 Typographic Conventions 25 5 CO e VOR EK E Ea abd Info 2 February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide N DTE SYN 1 About this Megafunction This user guide describes the features of the ALTIOBUF megafunction that implements either an I O input buffer ALTIOBUF in I O output buffer ALTIOBUF out or I O bidirectional buffer ALTIOBUF bidir You can configure the megafunction through the parameter editor in the Quartus II software This user guide assumes that you are familiar with megafunctions and how to create them
34. e Design Using the Technology Map Viewer Quartus II Edit View Project Assignments Processing Tools Window Jaltiobuf_design_example_1 i o A A amp Compilation Report amp B Legal Notice Flow Summary Successful Tue Sep 25 14 12 02 2007 Flow Settings Quartus Version 7 2 Build 149 09 19 2007 SJ Web Edition GES Flow Non Default Global Settings Geer altiobuf design example 1 Flow Elapsed Time Oy Saat T 109 wen Entity Name T TEE lysis amp Synthesis Set as Top Level Entity Summary Met timing requirements N A o ALUTs Locate in Timing Closure Floorplan UTs Locate in Chip Planner Floorplan amp Chip Editor logic registers Export Assignments Locate in Resource Property Editor 0 0 0 Hierarchy DE Locate in Technology Map Viewer 7 _ pet as Design Parson Locate in RTL Viewer pins 0 0 0 0 0 Locate in Design File emory bits Technology Map Print 1 DSP block 18 bit elements Ir Print All Design Files Total PLLs Copy Total DLLs Properties Open in Main Window w Enable Docking after synthesis the final resource count might be different sis was successful 0 errors 0 warnings Running Quartus Netlist Viewers Preprocess C
35. e buffer Use bus hold circuitry If enabled the bus hold circuitry can weakly hold the signal on an 1 0 pin at its last driven state Available in input buffer output buffer or bidirectional buffer Use differential mode If enabled datain datain_b is used for input buffers both dataout dataout_b are used for output buffers and both dataio dataio_b are used for bidirectional buffers This option is not available for Cyclone III Cyclone and Cyclone V devices Use open drain output If enabled the open drain output enables the device to provide system level control signals for example interrupt and write enable signals that can be asserted by multiple devices in your system This option is only available for output buffers and bidirectional buffers Use output enable port s If enabled there is a port used to control when the output is enabled This option is only available for output buffers and bidirectional buffers February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 2 2 Chapter 2 Parameter Settings Table 2 1 ALTIOBUF Plug In Manager Page 3 Options Part 2 of 2 Option control s Description If enabled this port receives the command to select either Rs code when input value low Rt code when input value high from the core Only enable Rt when the bi directional 1 0 is receiving input Otherwise it needs to be disabled so that th
36. e output performance and power dissipation is optimal This option is available only for input and bidirectional buffers This option is not available in Cyclone 111 Cyclone IV and Cyclone Vdevices Use dynamic termination An error is issued if parallel termination Rt is on and dynamic termination control is not connected on a bidir pin An error is issued if parallel termination Rt is off and dynamic termination control is connected on an input or bidirectional pin Note that two 1 05 in the same dynamic termination control group needs to have the same dynamic termination control signal If the 1 05 have separate dynamic termination control signals the Quartus software produces a fitting error A dynamic termination control group is a group of pins that share the same physical dynamic termination control signal on the chip Use series and parallel termination controls If enabled this allows the series and parallel termination control ports to be used These ports can then be connected to termination logic blocks to receive the Rs or Rt code from the termination logic blocks This option is only available for output buffers and bidirectional buffers The series and parallel termination control ports are 14 bit wide for series or parallel termination For Cyclone 111 Cyclone IV and Cyclone V devices this option is available for output buffers and bidirectional buffers but not for input buffers Only series termination is avai
37. g FALSE use in dynamic delay chain2 string FALSE use termination control string FALSE width ptc natural 14 width stc natural 14 lpm hint string UNUSED lpm type string altiobuf out port datain in std logic vector number of channels 1 downto 0 dataio inout std logic vector number of channels 1 downto 0 dataio b inout std logic vector number of channels 1 downto 0 dataout out std logic vector number of channels 1 downto 0 dynamicterminationcontrol in std logic vector number of channels 1 downto 0 others gt 0 dynamicterminationcontrol b in std logic vector number of channels 1 downto 0 others gt 0 io config clk in std logic vector number of channels 1 downto 0 others gt 0 io config clkena in std logic vector number of channels 1 downto 0 others gt 0 io config datain in std logic Ms io config update in std logic 0 oe in std logic vector number of channels 1 downto 0 oe b in std logic vector number of channels 1 downto 0 others gt ys parallelterminationcontrol in std logic vector width ptc number of channels 1 downto 0 others gt 0 parallelterminationcontrol b in std logic vector width ptc number of channels 1 downto 0 others gt 0 February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 14 Chapter 3 Functional Description Ports and Parameters seriestermi
38. g update L Each of the output and oe delay chains are built from two cascaded output delay chains The first output delay chain s dataout is connected to the second output delay chain s datain Depending on the parameter chosen use out dynamic delay chainl Or use out dynamic delay chain2 one or both of the output delay chains can be dynamic In this megafunction you can set the delay only for the dynamic delay chains 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 1 About this Megafunction V O Buffer and Dynamic Delay Integration 1 5 The second output delay chain s dataout is connected to the output buffer s i input port for the output path and to the output buffer s oe port for the oe path Note that the output path and the oe path have their own cascaded delay chains see Figure 1 5 for the internal architecture of the ALTIOBUF megafunction Figure 1 5 Internal Architecture of ALTIOBUF Megafunction Output Buffer Mode ioconfiga 0 output delay chain a 0 io config datain gt DATAIN config gt CLK io config clkena 0 0 gt ENA io config update gt UPDATE OUTPUTDELAYSETTING S 0 OUTPUTDELAYSETTING 2 0 DATAIN DELAYCTRLIN 3 0 DATAOUT output dyn delay chain2a 0 0 0 datain 0 0 STRATIXIII IO CONFIG STRATIXIII DELAY CHAIN oe delay
39. gafunction as output buffer Table 3 7 ALTIOBUF Megafunction As Output Buffer Output Ports Port Name Required Description Output buffer output port dataout Yes Output port NUMBER CHANNELS 1 0 wide The 1 0 output buffer element output Differential output buffer negative output dataout_b No Output port NUMBER_OF_CHANNELS 1 0 wide The 1 0 output buffer negative B output Port is applicable only when the USE DIFFERENTIAL MODE parameter value is TRUE February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 18 Chapter 3 Functional Description Ports and Parameters Table 3 8 shows the parameters for the ALTIOBUF megafunction as output buffer Table 3 8 ALTIOBUF Megafunction As Output Buffer Parameter Part 1 of 2 Port Name ENABLE BUS HOLD Required No Type String Description Specifies whether the bus hold circuitry is enabled Values are TRUE and FALSE When set to TRUE bus hold circuitry is enabled and the previous value instead of high impedance is assigned to the output port when there is no valid input If omitted the default is FALSE Note Currently ENABLE BUS HOLD and USE DIFFERENTIAL MODE Cannot be used simultaneously USE DIFFERENTIAL MOD E No String Specifies whether the output buffer mode is differential Values are TRUE and FALSE When set to TRUE both the dataout and dataout_b ports are used If omi
40. in 4 Input port NUMBER OF CHANNELS 1 0 wide Input port used as the clock signal of shift register block This port is available only if the USE OUT DYNAMIC DELAY CHAIN1 or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE Input port that feeds the ro coNrrc update port for user driven dynamic delay chain uds No When asserted the serial load shift register bits feed the parallel load register The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE The output enable source to the tri state buffer Input port NUMBER OF CHANNELS 1 0 wide When the oe port is asserted dataout and dataout_b are enabled When oe is de asserted both dataout and dataout_b are disabled This port is used only when the USE_OE parameter value is TRUE If omitted the default is Vec V O Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation Chapter 3 Functional Description 3 17 Ports and Parameters Table 3 6 ALTIOBUF Megafunction As Output Buffer Input Ports Part 2 of 2 Port Name Required Description The output enable source to the tri state buffer Input port NUMBER OF CHANNELS 1 0 wide When the oe port is TET No asserted dataout and dataout_b are enabled When oe is de asserted both dataout and dataout_b are disabled Thi
41. io config clkena io config update and io config datain This option is not available for Cyclone 111 Cyclone IV and Cyclone V devices If enabled the output or bidirectional buffer incorporates the user driven dynamic delay chain in the megafunction that 15 the IO CONFIG and the first output delay cell Additional input ports are enabled io config clk io config clkena io config update and io config datain This option is not available for Cyclone 111 Cyclone IV and Cyclone V devices If enabled the output buffer or bidirectional buffer incorporates a user driven dynamic delay chain in the megafunction that is the IO CONFIG and the second output delay cell Additional input ports are enabled io config clk io config clkena config update and io config datain This option is not available for Cyclone Cyclone IV and Cyclone V devices If enabled there is a port used to control when the configuration clock is enabled This option is not available for Cyclone III Cyclone IV and Cyclone V devices Enable input buffer dynamic delay chain Enable output buffer dynamic delay chain 1 Enable output buffer dynamic delay chain 2 Create a clkena port Table 2 2 lists the options available on page 5 and 6 of the ALTIOBUF MegaWizard Plug In Manager Table 2 3 ALTIOBUF Plug In Manager Page 5 and 6 Options Option Description Simulation Libraries Specifies the libra
42. ire io config update synthesis syn black box 1 endmodule altiobuf in February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 10 ALTIOBUF_OUT module altiobuf_out parameter intended_device_family parame parame parame parame parame Chapter 3 Functional Description Verilog HDL Prototype for the ALTIOBUF Megafunction enable_bus_hold FALSE left shift series termination control number of channels 1 open_drain_output FALS pseudo_differential_mode pn param parame parame parame parame parame parame parame parame input wire number Cer LOr use_differential_mode FALSE use_oe FALSE use_out_dynamic_delay_chainl use_out_dynamic_delay_chain2 use_termination_control width_ptc 14 width_stc 14 lpm_type altiobuf_out lpm_hint unused FALSE unused FALSE FAL FA FALSE of channels 1 0 datain output wire number of channels 1 0 dataout output wire number of channels 1 0 dataout b input inpu input inpu inpu inpu input 1 0 input 1 0 input 1 0 s inpu 120 wire io config clk wire number of channels 1 0 io config clkena wire wire wire wire wire parallelterminationcontrol wire parallelterminationcontrol b wire
43. lable The series termination control ports are 16 bit wide The width of these ports increases depending on the amount of buffers instantiated Use left shift series termination control If enabled you can use the left shift series termination control to get the calibrated OCT R with half of the impedance value of the external reference resistors connected to RUP and RDN pins This option is useful in applications which required both 25 Q and 50 calibrated OCT R at the same Vecio For more information refer to 1 0 features chapter of the respective device handbooks S Table 2 2 lists the options available on page 4 of the ALTIOBUF MegaWizard Plug In Manager These options are not available for Cyclone III Cyclone IV and Cyclone V devices When the dynamic delay chain is used the static delay chains cannot be set You need to add the necessary external flipflop s either DFFE or DDIO 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 2 Parameter Settings 2 3 For more information about the dynamic delay chain refer to I O Buffer and Dynamic Delay Integration on page 1 2 Table 2 2 ALTIOBUF Plug In Manager Page 4 Options Function Description If enabled the input or bidirectional buffer incorporates the user driven dynamic delay chain in the megafunction that is the IO CONFIG and the input delay cell Additional input ports are enabled io config clk
44. liobul_design_example_1_vig veo_tst out_jo_config_ ok aliobul design example 1 vig vec Ist out io conlig cena 4 aliobul deiion example 1 vig vec Ist out jo config 4 design exemple 1 Vig vec jo config update aliobd design example 1 vig vec Ist oul oe Now 1005 Delta 7 The second part of the simulation at 1 651 448 ps cursor 11 to 2 200 393 ps cursor 12 out_io_config_clkena is asserted for approximately 11 clock cycles Because there is an 11 bit shift register in IO_CONFIG primitive io_config_clkena is asserted for 11 clock cycles When fully loaded the shift register has its bits arranged to correspond with the datain s values m datain values set during the first four clock cycles this is b0000 This is not relevant in this case because the output buffer does not have an input delay cell datain values set during the next three clock cycles this is b000 for the second output delay cell xxx_dyn_delay_chain2a_0 therefore total delay is 0 ps 0 50 datain values set during the last four clock cycles this is b1111 for the first output delay cell xxx dyn delay 1 0 therefore total delay is 750 ps 15 50 The total effective delay is the sum of both delay chains because the delay chains are cascaded 0 750 750 ps 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 3 Functional Description 3
45. meters properly For a list of the megafunction ports and parameters refer to Functional Description on page 3 1 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide 3 Functional Description This chapter describes the design example that uses the ALTIOBUF megafunction to configure the delay chains dynamically for the Stratix III device during user mode This chapter also describes the prototypes component declarations ports and parameters of the ALTIOBUF megafunction You can use the ports and parameters to customize the ALTIOBUF megafunction according to your application Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Ill Devices This example compiles the megafunction as an output buffer and the circuitry is in Technology Map Viewer You can analyze the behavior of the dynamic delay chains with the ModelSim Altera software The design example files are available in the User Guides section on the Documentation page of the Altera website at www altera com In this example complete the following tasks m Generate the megafunction as an output buffer used in the design m View the megafunction implementation in the Technology Map Viewer window m Analyze the behavior of the design using the ModelSim Altera software Generate the Output Buffer Block To generate the output buffer block perform the following steps 1 Unzip ALTIOBUF_DesignExample_
46. nal of the shift register block This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE Input port that feeds the 10_CONFIG update port for user driven dynamic delay chain When asserted the serial load shift register bits feed the parallel load io config update No register The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE DYNAMIC DELAY CHAIN USE OUT DYNAMIC DELAY CHAINI or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE The output enable source to the tri state buffer oe Yes Input port NUMBER CHANNELS 1 0 wide If omitted the default is Vec February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 20 Chapter 3 Functional Description Ports and Parameters Table 3 9 ALTIOBUF Megafunction As Bidirectional Buffer Input Ports Part 2 of 2 Port Name Required No Description The output enable source to the tri state buffer Input port NUMBER_OF_CHANNELS 1 0 wide If omitted the default is Port is available only when the USE DIFFERENTIAL MODE parameter value is TRUE dynamictermination control No Input signal for bidirectional 1 05 Input port NUMBER CHANNELS 1 0 wide When specified this port selects from the core either Rs code when the input value is LOW or Rt code when
47. nationcontrol in std_logic_vector width_stc number of channels 1 downto 0 others gt 0 seriesterminationcontrol_b in std_logic_vector width_stc number of channels 1 downto 0 others gt 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL component declaration LIBRARY altera_mf USE altera mf altera mf components all Ports and Parameters The parameter details are only relevant if you bypass the parameter editor and use the megafunction as a directly parameterized instantiation in your design The details of these parameters are hidden from MegaWizard Plug In Manager interface users The options listed in this section describe all of the ports and parameters that are available to customize the ALTIOBUF megafunction according to your application Table 3 3 lists the input ports for the ALTIOBUF megafunction as input buffer Table 3 3 ALTIOBUF Megafunction As Input Buffer Input Ports Part 1 of 2 Port Name datain Required Description The input buffer normal data input port Yes Input port NUMBER OF CHANNELS 1 0 wide The input signal to the 1 0 output buffer element For differential signals this port acquires the positive signal input datain b The negative signal input of a differential signal to the 1 0 input buffer element No Input port NUMBER OF CHANNELS 1 0 wide When connected the datain_b
48. nt state of the pull up and pull down Rt control buses from a termination logic block Input port WIDTH NUMBER CHANNELS 1 0 wide Port is applicable only when the USE TERMINATION CONTROL parameter value is TRUE parallelterminationcont rol b No Receives the current state of the pull up and pull down Rt control buses from a termination logic block Input port WIDTH NUMBER OF CHANNELS 1 0 wide Port is applicable only when the USE TERMINATION CONTROL parameter value is TRUE 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation Chapter 3 Functional Description Ports and Parameters 3 21 Table 3 10 ALTIOBUF Megafunction As Bidirectional Buffer Output Ports Port Name Required dataout Yes Description Buffer output port Output port NUMBER OF CHANNELS 1 0 wide The 1 0 output buffer element output Table 3 11 ALTIOBUF Megafunction As Bidirectional Buffer Bidirectional Ports Port Name Required Description Bidirectional port that directly feeds a bidirectional pin in the top level design dataio Yes Bidirectional port NUMBER OF CHANNELS 1 0 wide Bidirectional DDR port that directly feeds a bidirectional pin in the top level design dataio_b No Bidirectional port NUMBER OF CHANNELS 1 0 wide The negative signal input output to from the 1 0 buffer This port
49. number of channels 1 0 dataout input wire number of channels 1 0 dynamicterminationcontrol input wire number of channels 1 0 dynamicterminationcontrol b input wire io config clk input wire number of channels 1 0 io config clkena input wire io config datain input wire io config update input wire number of channels 1 0 oe input wire number of channels 1 0 oe b input wire width ptc number of channels 1 0 parallelterminationcontrol input wire width ptc number of channels 1 0 parallelterminationcontrol b input wire width stc number of channels 1 0 seriesterminationcontrol input wire width stc number of channels 1 0 seriesterminationcontrol b synthesis syn black box 1 endmodule altiobuf bidir VHDL Component Declaration for the ALTIOBUF Megafunction You can locate the following VHDL Design File vhd altera mf vhd in the Quartus II installation directory MibrariesNvhdlNaltera mf directory ALTIOBUF IN component altiobuf in generic intended device family string unused enable bus hold string FALSE number of channels natural use differential mode string FALSE use dynamic termination control string FALSE use in dynamic delay chain string FALSE lpm hint string UNUSED lpm type string altiobuf in port datain in std logic vector number of channels 1 downto 0 datain b in std logic vect
50. ommand quartus altiobuf design example 1 c altiobuf_design_example_1 netlist type atom Info Quartus II Netlist Viewers Preprocess was successful 0 errors 0 warnings 4 Processing 04 4 Extra Info Info 14 Warning Critical Warning Error Suppressed Flag 5 Message 0 of 28 l Location Locate in Technology Map Viewer ide 5 The Technology Map Viewer window highlights the design implementation Figure 3 2 Figure 3 2 Design Implementation Using the Technology Map Viewer Quartus 45 Edit View Project Assignments Processing Tools Window Help Deug 8 Es c design example 1 xx L ZR GH b am 9 Project Navigator x 1 Page Title Post Mapping Locate Page 1 of 1 Entity LC Combin T Hierarchy List Stratix Ill AUTO By Strait AUT Ell altiobuf design EI Instances TT Primitives amp Pins m Nets 100 gt 0 warnings unning Quartus II Netlist Viewers Preprocess Command quartus rpp altiobuf design example 1 c altiobuf design example 1 netlist type atom Quartus II Netlist Viewers Preprocess was successful 0 errors 0 warnings Processing 14 Extra Info Info 14 Waming Critical Warning A Suppressed imu ltl Lo For Help press F1 hen 8 Idle NM
51. or number of channels 1 downto 0 others gt 0 February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 12 Chapter 3 Functional Description VHDL Component Declaration for the ALTIOBUF Megafunction dataout out std logic vector number of channels 1 downto 0 dynamicterminationcontrol in std logic vector number of channels 1 downto 0 others gt 0 io config clk in std logic 0 io config clkena in std logic vector number of channels 1 downto 0 others gt 0 io config datain in std logic 0 io config update in std logic Tots end component ALTIOBUF OUT component altiobuf out generic intended device family string unused enable bus hold string FALSE left shift series termination control string FALSE number of channels natural open drain output string FALSE pseudo differential mode string FALSE use differential mode string FALSE use oe string FALSE use out dynamic delay chainl string FALSE use out dynamic delay chain2 string FALSE use termination control string FALSE width ptc natural 14 width stc natural 14 lpm hint string UNUSED lpm type string altiobuf out port datain in std logic vector number of channels 1 downto 0 dataout out std logic vector number of channels 1 downto 0 dataout b out std logic vector number of
52. oul io conhg clkena 4 aliobul design example 1 vig vec Ist out jo config datain 4 design example 1 vg vec tst ou4 jo config update For the final part of the simulation at 4 302 377 ps cursor 21 to 4 851 327 ps Cursor 22 out io config clkena is asserted for approximately 11 clock cycles io confi g_clkena is asserted for 11 clock cycles because there is an 11 bit shift register in IO CONFIG primitive When fully loaded the shift register has its bits arranged to correspo datai nd with the datain s values in values set during the first four clock cycles this is b0000 In this case this not relevant because the output buffer does not have an input delay cell datai in values set during the next three clock cycles this is b111 for the second output delay cell xxx dyn delay chain2a 0 therefore total delay is 350 ps 7 50 datain values set during the last four clock cycles this is b1111 for the first output delay cell xxx dyn delay chainla 0 therefore total delay is 750 ps 15 50 The total effective delay is the sum of both delay chains because the delay chains are cascaded 350 750 1 100 ps 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation Chapter 3 Functional Description 3 9 Verilog HDL Prototype for the ALTIOBUF Megafunction The delay only takes effect when the out_io_config_update signal is asserte
53. port is always fed by a pad port atom This port is used only if the USE DIFFERENTIAL MODE parameter value is TRUE io config datain Input port that feeds the datain port of coNr 1G for user driven dynamic delay chain No Input port used to feed input data to the serial load shift register The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE IN DYNAMIC DELAY CHAIN parameter value is TRUE io config clk Input clock port that feeds the ro coNrre for user driven dynamic delay chain Take note that the maximum frequency for this clock is 30 MHz No Input port used as the clock signal of shift register block The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE IN DYNAMIC DELAY CHAIN parameter value is TRUE io config clkena Input clock enable that feeds the ena port of 10 for user driven dynamic delay chain No Input port NUMBER_OF_CHANNELS 1 0 wide Input port used as the clock enable signal of the shift register block This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE 1 0 Buffer ALTIOBUF Megafunction February 2012 Altera Corporation User Guide Chapter 3 Functional Description Ports and Parameters 3 15 Table 3 3 ALTIOBUF Megafunction As Input Buffer Input Ports Part 2 of 2 Port Name Required Descri
54. ption Input port that feeds the 10 update port for user driven dynamic delay chain io_config_ No When asserted the serial load shift register bits feed the parallel load register The value is update 1 bit wire shared among all 1 0 instances This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN parameter value is TRUE Input signal for bidirectional 1 05 Input port NUMBER_OF_CHANNELS 1 0 wide When specified this port selects from the core either Rs code when the input value is LOW or Rt code when the input value is HIGH Enable Rt only when the bidirectional 1 0 is receiving input When the bidirectional Xon No 1 0 is not receiving input disable this port for optimal output performance and power dissipation control Value Rs Code Rt Code 0 1 0 1 0 1 Table 3 4 shows the output ports for the ALTIOBUF megafunction as input buffer Table 3 4 ALTIOBUF Megafunction As Input Buffer Output Ports Port Name dataout Required Yes Description Input buffer output port Input port NUMBER OF CHANNELS 1 0 wide The 1 0 input buffer element output Table 3 5 shows the parameters for the ALTIOBUF megafunction as input buffer Table 3 5 ALTIOBUF Megafunction As Input Buffer Parameters Port Name ENABLE BUS HOLD Required Type Comments Specifies whether the bus hold circuitry is enabled Values are TRUE and FALSE When set to TRUE
55. ries needed for functional simulation by third party tools Specifies whether to turn on the option to generate synthesis area and timing estimation Generate netlist netlist Specifies the types of files to be generated A gray checkmark indicates a file that is automatically generated a green checkmark indicates an optional file Choose from the following types of files AHDL Include file function name inc VHDL component declaration file lt function name gt cmp Summary Quartus symbol file lt function name gt bsf Instantiation template file lt function name gt _inst v or lt function name gt _inst vhd Verilog HDL block box file lt function name gt _bb v Pin Planner File lt function name gt _ ppf If you turn on the Generate netlist option the file for that netlist is also available function name syn v February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 2 4 Chapter 2 Parameter Settings Using the Port and Parameter Definitions Instead of using the MegaWizard Plug In Manager you can instantiate the megafunction directly in your Verilog HDL VHDL or AHDL code by calling the megafunction and setting its parameters as you would any other module component or subdesign Altera strongly recommends that you use the MegaWizard Plug In Manager for complex megafunctions The MegaWizard Plug In Manager ensures that you set all megafunction para
56. ring the first four clock cycles this is b0000 In this case this is not relevant because output buffer does not have input delay cells datain values set during the next three clock cycles this is b001 for the second output delay cell xxx_dyn_delay_chain2a_0 therefore total delay is 50 ps 1 50 B datain values set during the last four clock cycles this is b1111 for the first output delay cell xxx_dyn_delay_chainla_0 therefore total delay is 750 ps 15 50 The total effective delay is the sum of both delay chains because the delay chains are cascaded 50 750 800 ps February 2012 Altera Corporation 1 0 Buffer ALTIOBUF Megafunction User Guide 3 8 Chapter 3 Functional Description Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix Devices The delay only takes effect when the out_io_config_update signal is asserted for one clock cycle at 3 549 609 ps cursor 18 After the signal is deasserted the delay from out_datain at 3 750 000 ps cursor 19 to out_dataout at 3 750 800 ps cursor 20 is 800 ps This is shown in Figure 3 5 Figure 3 5 Dynamically Changing the Delay Chain Value to 800 ps 39 design example 1 MELLE 4 design example 1 vig vec 11 04 2541947 ps to 4958587 ps 2 10 5 Delta 7 4 design example 1 vig vec Ist ou io config 4 design example 1 vig vec Ist
57. rts for ALTIOBUF megafunction as bidirectional buffer and Table 3 12 shows the parameters for ALTIOBUF megafunction as bidirectional buffer Table 3 9 ALTIOBUF Megafunction As Bidirectional Buffer Input Ports Part 1 of 2 Port Name Required Description The input buffer input port datain Yes Input port NUMBER OF CHANNELS 1 0 wide The input signal to the 1 0 output buffer element Input port that feeds the dat ain port of 10 coNr IG for user driven dynamic delay chain dae No Input port used to feed input data to the serial load shift register The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE IN DYNAMIC DELAY CHAIN USE OUT DYNAMIC CHAINI or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE Input clock port that feeds the corr for user driven dynamic delay chain Note that the maximum frequency for this clock is 30 MHz io config clk No Input port used as the clock signal of shift register block The value is a 1 bit wire shared among all 1 0 instances This port is available only if the USE IN DYNAMIC DELAY CHAIN USE OUT DYNAMIC DELAY CHAINI or USE OUT DYNAMIC DELAY CHAIN2 parameter value is TRUE Input clock enable that feeds the ena port of for user driven dynamic delay chain Input port NUMBER_OF_CHANNELS 1 0 wide Input port used as the clock sig
58. s port is used only when the USE DIFFERENTIAL MODE parameter value is TRUE If omitted the default is V Receives the current state of the pull up and pull down Rs control buses from a termination logic block seriestermination trol No Input port WIDTH_STC NUMBER_OF_CHANNELS 1 0 wide Port is available only when the USE_TERMINATION_CONTROL parameter value is TRUE Receives the current state of the pull up and pull down Rs control buses from a termination logic block seriestermination Input port WIDTH STC NUMBER OF CHANNELS 1 0 wide Portis available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE Receives the current state of the pull up and pull down Rt control buses from a termination logic block parallelterminationcont No Input port WIDTH PTC NUMBER OF CHANNELS 1 0 wide Portis rol available only when the USE TERMINATION CONTROL parameter value is TRUE The port is available for Stratix III device families only Supported in Stratix series only Receives the current state of the pull up and pull down Rt control buses from a termination logic block parallelterminationcont No Input port WIDTH PTC NUMBER OF CHANNELS 1 0 wide Portis rol b available only when the USE DIFFERENTIAL MODE parameter value is TRUE The port is available for Stratix III device families only Supported in Stratix series only Table 3 7 shows the output ports for the ALTIOBUF me
59. teger Specifies the number of 1 0 buffers that must be instantiated Value must be greater than or equal to 1 A value of 1 indicates that the buffer is a 1 bit port and accommodates wires A value greater than 1 indicates that the port can be connected to a bus of width NUMBER CHANNELS WIDTH STC No Integer Specifies the width setting for the series termination control bus WIDTH No Integer Specifies the width setting for the parallel termination control bus USE OE No String Specifies whether the oe port is used 1 0 Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation Chapter 3 Functional Description Ports and Parameters 3 19 Table 3 8 ALTIOBUF Megafunction As Output Buffer Parameter Part 2 of 2 Port Name Required Type Description Values are True and False If omitted the default is False LEFT_SHIFT_SERIES_TE Michi TTO CONTROL No String uie for all supported devices except Cyclone series device Specifies the pseudo differential mode Values are True and String False If omitted the default is False Available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE Table 3 9 shows the input ports for the ALTIOBUF megafunction as bidirectional buffer Table 3 10 shows the output ports for ALTIOBUF megafunction as bidirectional buffer Table 3 11 shows the bidirectional po
60. the input value is HIGH Enable only when the bidirectional 1 0 is receiving input When the bidirectional 1 0 is not receiving input disable this port for optimal output performance and power dissipation Value Rs Code Rt Code 0 1 0 1 0 1 dynamictermination control_b No Input signal for bidirectional 1 05 Input port NUMBER_OF_CHANNELS 1 0 wide When specified this port selects from the core either Rs code when the input value is LOW or Rt code when the input value is HIGH Enable Rt only when the bidirectional 1 0 is receiving input When the bidirectional 1 0 is not receiving input disable this port for optimal output performance and power dissipation Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE Value Rs Code Rt Code 0 1 0 1 0 1 seriestermination control No Receives the current state of the pull up and pull down Rs control buses from a termination logic block WIDTH_STC NUMBER_OF_CHANNELS 1 0 wide Port is applicable only when the USE_TERMINATION_CONTROL parameter value is TRUE seriestermination control_b No Receives the current state of the pull up and pull down Rs control buses from a termination logic block WIDTH STC NUMBER OF CHANNELS 1 0 wide Port is applicable only when the USE TERMINATION CONTROL parameter value is TRUE parallelterminationcont rol No Receives the curre
61. tted the default is FALSE Note Currently ENABLE BUS HOLD and USE DIFFERENTIAL MODE Cannot be used simultaneously OPEN DRAIN OUTPUT No String Open drain mode Values are TRUE and FALSE If omitted the default is FALSE Note Currently OPEN DRAIN OUTPUT and USE DIFFERENTIAL MODE Cannot be used simultaneously USE TERMINATION CONTROL No String Specifies series termination control and parallel termination control Values are TRUE and FALSE If omitted the default is FALSE When this parameter is used for Arria Il GX devices and the Cyclone series only series termination control is available Stratix series support both USE OUT DYNAMIC _ DELAY CHAINI1 No String Specifies whether the output buffer incorporates a user driven dynamic delay chain in the megafunction specifically IO coNrIG and the first output delay cell Additional input ports io config clk io config clkena io config update and io config datain Values are TRUE and FALSE If omitted the default is FALSE USE OUT DYNAMIC DELAY CHAIN2 No String Specifies whether the output buffer incorporates a user driven dynamic delay chain in the megafunction specifically IO_CONFIG and the second output delay cell Additional input ports are io config clk io config clkena io config update and io config datain Values are TRUE and FALSE If omitted the default is FALSE NUMBER OF CHANNELS Yes In
62. ttings taps value available for this DELAY CHAIN primitive which are 0 to 15 taps Each taps represents 50 ps of delay This allows a total delay value between 50 ps 1 50 to 750 ps 15 50 For xxx dyn delay chain2a 0 the second output delay cell s delayctrlin inputs are 4 bits but the MSB is tied to 0 This signifies the possible delay settings taps value available for this DELAY CHAIN primitive which are 0 to 7 taps Each taps represents 50 ps of delay This allows a total delay value between 50 ps 1 50 to 350 ps 7 50 Because of the cascaded nature of the two delay chains the effective delay is the sum of both DELAY CHAIN primitives This is reflected more clearly in the simulation results later in this chapter For xxx dyn delay chain2a 0 the second output delay cell s dataout is connected to the 0 output buffer s input port for the output path and to the obu a 0 output buffer s oe port for the oe path Note that the output path and the oe path have their own cascaded delay chains Functional Results Analyzing the Functional Behavior of the Design in ModelSim Altera Software This user guide assumes that you are familiar with using the ModelSim Altera software before trying out the design example If you are unfamiliar with the ModelSim Altera software refer to www altera com support software products modelsim mod modelsim html There are links to topics such as installation usage and troubleshooting

I/O Buffer (ALTIOBUF) Megafunction User Guide

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