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MSC121x User's Guide

1. 0000 000 General call 0000 000 Start byte for slow de vices 0000 001 Address for CBUS protocol 0000 010 Address reserved for different protocol 0000 011 to To be defined 0000 111 0001 000 to I2C device addresses 1110 111 1111 0aa Reserved Most significant two bits of 10 bit address 1111 1xx Reserved To increase the number of addressable devices the 12C standard was ex tended to accommodate an additional 10 bit address space The most signifi cant two bits are contained within addresses that were originally reserved while the remaining eight bits are provided in the following byte The MSC1211 13 neither generates nor accepts 10 bit addresses automatically However the 10 bit addressing protocol may be replicated under software control to implement either a master transmitter or a slave receiver A master receiver or slave transmitter cannot be implemented because the interpreta tion of the R W flag precludes transmission or reception respectively of the low part of the address as a data byte 9 18 Chapter 10 Serial Peripheral Interface SPI This chapter describes the serial peripheral interface SPI of the MSC121x Topic Page 10 1 Description 7 9e exce sene eser na ee errare nier e 10 2 10 2 SPI Configuration c C PEEEECCPECCCECHTT T ICCIECTECEEE 10 2 10 3 SBlilnterrupis ae ae e a e a 10 5 10 4 SPI FIFO Buffer ccce rer e E E ET 10 6 10 5 SBliExamples maa E E E E e 10 9
2. 10 1 Description 10 1 Description The Serial Peripheral Interface or SPI is a synchronous bit serial full duplex communications standard that simultaneously transfers eight bits of data from a master to a slave and another eight bits of data from the slave to the master The MSC121x can be programmed to behave as a master or a slave and uses four signals to coordinate transfers These signals are 1 SS Slave Select shared with P1 4 INT2 2 MOSI Master Out Slave In shared with P1 5 INT3 3 MlSO Master In Slave Out shared with P1 6 INTA SDA 4 SCK SPI Clock shared with P1 7 INT5 SCL 10 2 SPI Configuration The usual interconnection between a master and slave is shown in Figure 10 1 To multiplex data from more than one slave the MISO output may be selectively enabled via the active low slave select pin Although less common the MSC121x permits multiple masters by enabling their MOSI and SCK outputs under software control The transmit and receive data pathways are double buffered but may also in clude a first in first out FIFO buffer that uses part of the core SRAM This con figuration permits higher speed transfers and reduces CPU overhead To provide compatibility with other slave devices such as hardware shift regis ters the default order of bits transferred can be changed from 7 0 to O 7 Also the phase and polarity of the clock SCK can be configured The SPI subsystem is only activ
3. Figure 6 3 shows the basic input structure of the MSC121x Figure 6 3 Analog Input Structure without Buffer RswrrcH 3k typical High Aw O GO AM Impedance gt 1GQ Cs 9pF typical Sampling uu Frequency fgayp AGND PGA a VREF E VREF 2 VREF 2 VREF 4 VREF 4 VREF 8 VREF 8 VREF 16 VREF 16 VREF 32 VREF 32 VREF 64 VREF 64 VREF 128 VREF 128 NOTE fMop ACLK frequency 64 Analog To Digital Converters 6 5 Input Impedance PGA and Voltage References Table 6 3 ADCONO ADC Control Register 0 SFR DCh Reset Value 30h Bit Name Action or Interpretation Reference Clock MSC1211 12 13 14 only The reference is specified with a 250kHz clock REFCLK should be selected by choosing the appropriate source so that it does not exceed 250kHz 0 tork ACLK 1 x 4 USEC i 4 Burnout Detect When enabled a 2uA current source is connected from AVpp to the positive input while a 2uA current sink is connected from the negative input to ground Write 0 Burnout Current Sources Off default 1 Burnout Current Sources On Enable Internal Voltage Reference Write 0 Internal Voltage Reference Off 1 Internal Voltage Reference On default If the internal voltage reference is not used it should be turned off to save power and reduce noise Voltage Reference High Select Write 0 REFOUT is 1 25 V 1 REFOUT is 2 5 V default Enable Buffer
4. ADC modulator clock Timing Chain and Clock Controls At power on or after a RESET the signal from the oscillator is not allowed to propagate until after 217 1 periods This period of time allows the power rails and crystal oscillator to stabilize Thereafter if neither PSEN nor ALE is low the CPU will begin to execute code starting at location 0000h While operating the CPU may set bit 1 of PCON at 87h to assert a STOP condition that can only be exited by a hardware reset In this condition all dynamic activity ceases but the port I O pins retain their levels To pause the CPU and core peripherals temporarily bit 0 may be set This will invoke an IDLE state that is terminated by an auxiliary interrupt associated with AIE at A6h a wake up via EWU at C6h or a RESET See chapter 13 for further detail on interrupts and their sources PSEN and ALE are used with RESET to enter serial or parallel flash programming modes Subsystems are enabled disabled by bits in PDCON at F1h in any combina tion except that SPI and 12C subsystems must not be simultaneously active When a bit is high the associated subsystems are inactive and power is re duced to a minimum static level SPICON 7 5 at 9Ah provides a 3 bit code N which selects a tap into a binary divider chain to provide the clock for the SPI interface at a frequency of fci k 2 NH When the 12C subsystem is active and bit 2 of IPCCON at 9Ah is set the MSC1211 is in Master
5. 0 0ff 11110111 11110000 include lt Reg1211 h gt include lt stdio h gt define xtal 22118400 sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM sbit SlaveSelect P1 0 avoids onboard SPI devices code at OxFFF3 void autobaud void data unsigned char j 69 Letter E Auxiliary Interrupt void AuxInt void interrupt 6 using 1 unsigned char i while PAI switch PAI case 3 SPI RX while SPIRCON putchar SPIDATA empty the buffer printf Mn break case 8 Seconds i SECINT remove seconds interrupt flag for i 65 i lt j i while AIE amp 0x08 SPIDATA i output break EICON amp 0x10 remove AI flag void main void PDCON amp 0x03 turns on System Timer and SPI PIDDRH 0x40 CMOS output for P1 7 PIDDRL 0x01 CMOS output for P1 4 SPIEND 0x9F 32 byte buffer SPISTART 0x80 Start at 0x80 and initialise SPICON 0xD4 Divide 128 FIFO on msb master SPIRCON 0x04 RX IRQ on 16 or more 10 10 SPI Examples Example 10 2 Continued SPITCON 0x28 SCK driver on SlaveSelect 0 autobaud MSEC xtal 1000 1 ims tick HMSEC 100 1 100ms tick SECINT 0x89 write 9 immediately for 10 x 100 ms printf FIFO interrupt loopback SPI n AIE 0x84 enable Seconds and SPI RX interrupts EICON 0x20 enable auxiliary interrupt RIO 0 Clear received flag in UART while
6. 2 005 1 12 On Chip and Off Chip Resources ssssssssssssssses teens 2 2 MSC121x Timing Chain and Clock Control 00 0 aasan cee eee 5 2 ADC Subsystem Elements sssssssssssssessss eee eens 6 2 Input Multiplexer Configuration 00 0 ete 6 4 Analog Input Structure without Buffer 00 000 cece eee eens 6 5 Filter Frequency Responses 000s cece eee eee nh 6 10 DAC Architecture os roides i ei ene nsn 7 2 12C Bus Connection of Standard and Fast Mode Devices 0c0eeee eee 9 3 START and STOP Conditions sss riensi isasid iisi aiaei teen eens 9 3 2C B s EIE TEAUSIBE uou e d edat tede dad e dor ARES ud d in Edad ach au ERO du Ta aca 9 3 I C Bus Data Transfer ce eiui gore oo eR cs Re e CR RC wee a eae 9 4 55 Acknowledge 2 qid Donati iode ui tage be aD awe ha darc md 9 5 SPI Master Slave Interconnect 0 000 cece eects 10 2 SPI Glock Data TIMING i2 nares oui at ep RUPRR er IU Ragga arched ebbe pad 10 4 SPLFIFO Operation o eka REESE RERRSREERTREEAT XD E wed Ree 10 6 Timer 0 1 Modes 0 and T sicieceios elu bx eE ERA Ree y PEINER ENA nr r4 err Rb 11 5 Turier 0 1 MOGOO 2 e cakes ate dte age came ght res keira dba Ge Raf ME EUR 11 6 Timer 0 MOode 3 serrant ranite IAEE satus davies Ru he spnerceneebfag edd 11 7 Timer Counter 2 16 Bit with Capture 0 cece cece esee 11 9 Timer Counter 2 16 Bit with Reload 0 00 cece eee tenes 11
7. SPIEND 90 EXIF MPAGE CADDR CDATA MCON 88 TMOD TLO TL1 THO TH1 CKCON MWS 80 SP DPLO DPHO DPL1 DPH1 DPS PCON 1 In general the low part of multi byte SFRs such as the 16 bit pointer comprised of DPLO and DPHO reside at adjacent addresses but this is not always the case See TLO at 8Ah and THO at 8Ch 2 The least significant part of a 16 bit variable is usually at an even address but this is not always the case See P2DDRL at B1h and P2DDRH at B2h PSDDRL at B3h and P2DDRH at B4h DACL at B5h and DACH at B6h 3 Refer to the individual product data sheets for information regarding implementation of this function 3 2 Referencing SFRs in Assembly and C Languages 3 2 Referencing SFRs in Assembly and C Languages When writing programs in assembly language an SFR can be referenced by its absolute address or by a symbol associated with its address In C language a variable must first be declared as shown in Example 3 1 For assembly language programs declarations that associate common sym bols with values are usually grouped in an include file with the name inc that is referenced in the source code Similarly for C language declarations ap pear in a file with the name Example 3 1 Assembly Code and C Code Purpose Assembly Code C Code Compiler Dependant Directives Output the character A to SBUFO DATA 99H at 0x99 sfr SBUFO serial port 0 MOV 99H 441H _ MOV SBUFO 41H SBUFO 0x41 Ena
8. cceeee eee eee eee eee eee 2 1 2 1 hueelteipgere ETT 2 2 2 2 Program Memory and Data Memory sssssssssesss sse 2 3 2 3 Core Data Memory and Special Function Registers 0 cece eee 2 5 24 Beyond 64 KBytes osos bao Rege RR eem ERR ER REGE CERE RE RUE 2 6 Special Functions Registers useuuleeeseeeeeeeee nn nnn 3 1 ou ntrogdilctiol 23 c suce A a EE i Sette rt retur DL Lene Lupe rua Pu ee 3 2 3 2 Referencing SFRs in Assembly and C Languages 0eeeeee eee eeee 3 3 8 3 SER Types cssc epe Rn Dub Rede lb ed crud aed ed eo 3 4 34 SFR OVGNVICW 22 3022 erue reaa h repel px bebo REVERSE E E Deedee eee 3 4 Programmer s Model and Instruction Set 2 0c cece eee e eee eee eee eee 4 1 4d Introduction uiuos tete dam ne dae des cher x ae a Rd dator qe eee 4 2 4 2 JHegisterS c cocsetiuesl ee tes de n der ER RR ER RE URRE Verr C P PUER rS 4 2 4 3 Instruction Types and Addressing Modes 00 cee ee ete ete eee e ees 4 4 44 MSC121x Op Code Table ccc ider iiaa siida Deadia 4 10 4 5 Examples of MSC121x Instructions 0 0 0 cece nents 4 12 System Clocks Timers and Functions 0 cece eee ee eee eens 5 1 5 1 Timing Chain and Clock Controls sinsi arisi 0 00 cece cece daian iiai eR g 5 2 5 2 System Clock Divider MSC1211 12 13 14 2 0 2 eee 5 5 5 2 1 Behavior in Delay Mode 105 cece eens 5 6 5 9 Watchdog IMO o ersan Le RRUCEERAT I D Res
9. Active high bits within PDCON provide selective power down of the subsystems DAC 12C PWM ADC Watchdog System Timer and SPI PASEL F2h PSEN ALE Select When off chip memory is not used control signals PSEN and ALE are not needed Three bits in PASEL allow the pin associated with PSEN to be either the usual PSEN signal sys tem clock ADC modulator clock low or high Two other bits allow the pin associated with ALE to be either the usual ALE signal low or high NOTE When these two lines are used as output lines they should be lightly loaded to avoid entering serial or parallel flash programming modes on reset ACLK F6h Analog Clock The frequency of the delta sigma ADC modulator is given by fork ACLK 1 x 64 where fCLk is the frequency of the system clock SRST F7h System Reset Register If bit 0 is set high then low the MSC121x will be reset This causes exactly the same behavior as if a system reset had been initiated by the RST pin ALE PSEN and EA will be sampled after the power up delay EIP F8h Extended Interrupt Priority Five bits determine the priority for interrupts Watchdog INT5 INT4 INT3 and INT2 See Extended Interrupt Flags EXIF at 91h and Extended Interrupt Enable EIE at E8h SECINT F9h Seconds Timer Interrupt The seconds interrupt if enabled occurs at an interval given by SECINT 1 x HMSEC 1 x MSEC 1 x tci k If bit 7 is
10. 9 11 12C Fast Mode Assuming USEC is defined to give an internal reference of 1us and bit 3 of I2CCON is clear the 12C subsystem will generate standard setup and hold times However if bit 3 of IPCCON is set this timing will be altered to permit transfers at up to 400kHz as determined by the value written to I2CSTAT In fast mode the SCL and SDA inputs incorporate Schmitt triggers and spike suppression as well as active slew rate control of falling edges Compared with standard mode it may be necessary to reduce the value of pull up resis tors and or load capacitance In exceptional cases the pull up may be a high Speed active current source of up to 3mA For bus loads up to 400pF the pull up resistor can be a current source of up to 3mA or a switched resistor circuit 9 12 12C General Call When bit 2 of I2CCON is 0 the MSC1211 13 is configured as a slave device In this state if bit 7 of I2CGM at 9Ch is 1 or 0 a general call address of 00h will be recognized or ignored respectively When recognized the status code is set to 70h and the slave should respond to the following data byte according to the 12C standard Inter IC 12Ct Subsystem 9 17 12C 10 Bit Adaressing 9 13 12C 10 Bit Addressing The original 7 bit addressing scheme of the I2C standard allocates addresses according to Table 9 9 Table 9 9 Address Allocation Most Significant R W Extended Meaning Seven Bits Bit Standard Meaning Where Different
11. CD 11 CE 11 CF 1 XCH XCH XCH XCH XCH XCH XCH XCH A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 D8 2 3 D9 2 3 DA 2 3 DB 2 3 DC 2 3 DD 2 3 DE 2 3 DF 2 3 DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ RO rel8 R1 rel8 R2 rel8 R3 rel8 R4 rel8 R5 rel8 R6 rel8 R7 rel8 E8 1 1 E9 14 EA 14 EB 1 1 EC 1 1 ED 14 EE 14 EF 1 1 MOV MOV MOV MOV MOV MOV MOV MOV A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 F8 1 1 F9 14 FA 14 FB 1 1 FC 1 1 FD 14 FE 14 FF 1 1 MOV MOV MOV MOV MOV MOV MOV MOV RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 A Programmer s Model and Instruction Set 4 11 Examples of MSC121x Instructions 4 5 Examples of MSC121x Instructions For a particular application suppose it is required to compute the logical func tion Q W amp X Y not Z given a byte where Q is bit 7 of port 2 W is bit 0 X is bit 1 Y is bit 2 and Z is bit 3 The assembler listing below shows how this can be achieved in a number of different ways and allows the reader to see the application of many different types of instructions Example 4 3 Assembler Code Assembly Language Example include reg1210 W bit ACC O X bit ACC 1 Y bit ACC 2 Z bit ACC 3 Q bit P2 7 CSEG AT 0100H inc main mov R7 0 initial value main 1 lcall funi decision tree lcall fun2 better tree lcall fun3 boolean operations lcall fun4 look up table lcall fun5 faster lcall fun6 fastest inc R7 cjne R7 H10H main 1 try
12. Example 8 1 Continued PWMCON 3 square break case staircase PWMCON 7 staircase break tout time while tout void main void PDCON amp 0x12 power up PWM generator and seconds tout 0 time out is over MSEC xtal 1000 1 1ms tick HMSEC 100 1 100ms tick SECINT 0x89 write 9 immediately for 10 x 100 ms RedLed 0 indicate start of autobaud autobaud set up serial rate AIE 0x80 enable Seconds interrupt EICON 0x20 enable auxiliary interrupt PWMCON 0x08 PWMSEL Period Register fclk INT1 1 Pin P3 3 is high P3DDRL amp 0xCO0 8051 output RedLed 1 indicate waiting for carriage return while 1 printf nPress 1 PWM 2 SQUARE or 3 STAIRCASE n prompt RI_0O 0 wait for character while RI_0 i SBUF0 amp 3 limit range RI 0 0 printf Tone in Progress switch i case 0 break case 1 beep divA 1 3 pwm parameters computed at compile time break case 2 beep divA 2 1 4 square divA 2 1 is 25133 54 truncated to 0x622d break case 3 Pulse Width Modulator and Tone Generator 8 5 PWM Generator Example Example 8 1 Continued beep divA 2 1 5 staircase printf Tone Complete n beep 0 1 null printf Press Enter or cr MnMn SRST 1 SRST 0 RESET Chapter 9 Inter IC I2C Subsystem This chapter describes the Inter IC I2C subsystem
13. External memory cycles may occur if 1 The EA pin was low when the RST pin was released 2 Aninstruction is fetched from an address that is not associated with on chip FLASH or 3 When EGPO of HCR1 0 and a MOVC or MOVX instruction executes Port 1 provides not only eight independently programmable bits but also a va riety of alternate functions as shown in Table 1 3 Table 1 3 Port 1 Alternate Functions Port 1 Bit Name Alternate Function P1 0 T2 Clock source for Timer Counter 2 when C T2 T2CON 1 is 1 P1 1 T2EX If Timer Counter 2 is in auto reload mode and EXEN2 T2CON 3 is 1 a negative edge 1 0 transition causes Timer Counter 2 to be reloaded and EXF2 T2CON 6 to be set which in turn may cause an interrupt P1 2 RxD1 Serial input to USART1 An external receiver is needed to level shift RS232 signals P1 3 TxD1 Serial output from USART1 An external driver is needed to level shift RS232 signals Positive edge triggered external 2 interrupt or active low Slave Select output during SPI operations P1 5 INT3 MOSI Negative edge triggered external 3 interrupt or the Master Out Slave In during SPI operations P1 4 INT2 SS P1 6 INT4 MISO SDA Positive edge triggered external 4 interrupt or Master In Slave Out during SPI operations serial data during 12C operation P1 7 INT5 SCK SCL Negative edge triggered external 5 interrupt or serial clock output f
14. SFR Overview Table 3 2 SFR Overview continued Address Name Hex Description MWS 8Fh Memory Write Select When bit 0 is clear default any writes to Flash memory via MOVX instructions are written to data space otherwise writes are directed to code space Writing to Flash memory may be inhibited via RSL bit 5 and PML bit 6 in HCRO P1 90h Port 1 Controls the byte wide bit programmable input output called Port 1 Each bit in the SFR corre sponds to a pin on the actual part Individual bits may be configured as bidirectional CMOS out put open drain output or input via the Data Direction SFRs for Port 1 See P1DDRL at AEh and P1DDRH at AFh Each pin may also be used to provide an alternate function and this may require particular values in P1 and the corresponding data direction bits For example P1 4 may be either a general pur pose 1 O bit an input for interrupt INT2 or an active low Slave Select input or output for the SPI interface EXIF 91h External Interrupt Flag Four bits represent interrupt flags for interrupts INT2 INT3 INT4 and INT5 that must be cleared manually by software INT2 and INT4 are triggered by a rising edge while INT3 and INT5 re spond to a negative edge If a bit is set in software an interrupt will occur if it is enabled See Extended Interrupt Enable EIE at E8h and Extended Interrupt Priority EIP at FBh MPAGE 92h Memory Page During execution of MOVX Ri A or MOVX
15. Slave Address Acknowledgement from Receiver EN I 1 1 1 I Acknowledgement 1 from Receiver i i I 1 1 I i 1 1 I tosa ACK ACK t START a STOP Condition Byte Complete Clock Line Held Low By Receiver Condition I2C Data Transfers and the Acknowleage Bit Once addressed a multi byte data transfer can be terminated when a slave generates a NACK rather than the usual ACK In addition after the acknowl edge bit a slave may pull the SCL line low while it performs local processing this often occurs when the slave is a microcontroller that executes a time con suming interrupt service routine While the SCL line is held low the master will wait Figure 9 5 2C Acknowledge m 1 1 Data Output e 1 I 1 Receiver 1 DE Data Output i l Master i LUN JN SCL l 1 2 ES 7 8 9 START Acknowledgement Condition Clock Pulse If a master issues a slave address with a R W bit that is 1 it will become a mas ter receiver when the slave responds with an ACK Thereafter the slave pro vides data bytes to the master but releases the SDA line every ninth clock pulse and samples the acknowledgement that is provided by the master Typi cally the master will generate ACKs for as long as it expects more data and then generate a NACK to inform the slave on the last byte Inter IC 12Ct Subsystem 9 5 12c Principal Registers 9 5 12C Principal Registers There are four principal Special Function Registers SF
16. 0x40 TRL is 1 TMOD 0x00 Timerl 13 bit Baud xtal 16 4 8192 21 1 T2CON 0x34 Timer 2 is rate generator and enabled RCAP2 65536 xtal 32 BAUD while 1 if RI O wait for key press if n lt limit put character into buffer if i gt limit i 0 wrap on pointer buffer i SBUFO save save character n increment count if n limit 2 RedLed 0 show impending overflow RI 020 remove receive flag irt RT T 4 Is serial Port 2 Tx empty if n Is buffer not empty if j gt limit j 0 wrap off pointer TI 1 07 indicate serial port 1 Tx is busy SBUF1 buffer jl send character n decrenemt count Serial Ports USARTO and USART1 12 11 Example Program Example 12 1 Continued else RedLed 1 turn off overflow LED if RI_1 is serial port 1 Rx full SBUFO SBUF1 copy Rx port 1 to Tx port 0 RI 1 0 YellowLed RXD1 monitor serial port 1 bit stream 12 12 Chapter 13 Interrupts This chapter describes the MSC121x interrupts Topic Page 13 1 Description 7 9909 ssena EEE EEE EE 13 2 13 2 Standard and Extended Interrupts Lssussussssss 13 2 13 3 Auxiliary Interrupt Sources sseeeeeeeeeeee 13 4 Tes Multiple interruptsq er ESTEE E 13 5 13 5 Example of Multiple and Nested Interrupts 13 6 13 6 Example of Wake Up From Idle LL
17. 1 while RI_0 YellowLed YellowLed main program RI_0O 0 any character to pause while RI_0 wait for character j SBUFO limit is received character A a allowed RI_0 0 continue Serial Peripheral Interface SPIt 10 11 10 12 Chapter 11 Timers and Counters This chapter describes the MSC121x timers and counters Topic Page A151 Descriptlonz zen ssena e serre na e e eaae s rere 11 2 11 2 Timer Go nters 0 and 1 TEC EECPEECEEEPETHETIPIPIEIITEPIE 11 3 AMES S Timer Gounter 2 e e re toate TEE t 11 8 11 4 Example Program Using Timers 0 1 and 2 11 13 Description 11 1 Description The MSC121x includes three Timer Counter modules 0 1 and 2 that behave in the same way as those found in the 8051 8052 When a module is clocked from the system clock it changes at a known rate and in this mode is referred to as a Timer However when clocked from an external source it may be con sidered as an event counter or timer There are numerous modes of operation which include but are not limited to 13 bit timer 16 bit gated timer 16 bit gated counter 8 bit with auto reload 16 bit timer capture L LE L 5 O Baud rate generator Note Not all modes are available within each module but the combination of modes satisfies many application environments Timer Counters 0 and 1 11 2 Timer Counters 0 and 1 Bits in TMOD at 89h and T
18. 1 by 16 Serial Port 0 19 by 16 Serial Port 0 RCLK TCLK TH2 Reload RCAP2H Timer 2 Interrupt EXF2 Timer Counter 2 Baud Rate Generator 0 C T2 EXEN2 E o 1 1 to 0 Pin T2 Pin Edge TEE Detection TR2 Timers and Counters 41 11 Timer Counter 2 11 3 4 Summary of Control Bits and SFRs for Timer Counter 2 Table 11 6 Control Bit and SFR Summary for Timer Counter 2 Timer 2 Signal Control or Data SFR Address SFR Bit Address Timer overflow flag T2CON 7 CFh External interrupt flag T2CON 6 CEh Count high byte TH2 Count low byte TL2 Capture reload high byte RCAP2H Capture reload low byte RCAP2L Timer counter select C T2 T2CON 1 C9h Receiver clock select RCLK T2CON 5 CDh Transmitter clock select TCLK T2CON 4 CCh Capture reload flag CP RL2 T2CON 0 C8h Divide by 4 or 12 select T2M CKCON 5 External clock input T2 P1 0 T2 90h Timer run control T2CON 2 CAh Internal timer gate T2CON 3 CBh External trigger input P1 1 91h Enable interrupt IE 5 ADh Interrupt priority IP 5 BDh 11 12 Example Program Using Timers 0 1 and 2 11 4 Example Program Using Timers 0 1 and 2 In the example the red and yellow LEDs on the MSC1210 evaluation module are associated with overflow interrupts from Timers 0 and 2 respectively Seri al port 0 is repeatedly tested for receipt of any character at a bau
19. Active low or negative edge triggered interrupt Gate for Timer Counter 0 P3 3 INT1 TONE PWM Active low or negative edge triggered interrupt Tone or Pulse Width Modulated output Gate for Timer Counter 1 P3 4 TO Clock source for Timer Counter 0 if TMOD 2 is 1 See description of the Timer Counters for gated conditions P3 5 T1 Used as a clock source for Timer Counter 1 if TMOD 6 is 1 See description of the Timer Count ers for gated conditions P3 6 WR Active low write strobe for external memory if used P3 7 RD Active low write strobe for external memory if used Introduction 1 9 MSC121x Pinout 1 2 2 Oscillator XOUT pin 1 and XIN pin 2 In many applications a quartz crystal or ceramic resonator is connected be tween XOUT and XIN to provide a reference clock that is between 1MHz and approximately 30MHz The static design of the MSC121x allows a digital clock to be applied to XIN that is between OMHz and 30MHz A commonly used crys tal for exact baud rates is 11 0592MHz TT 1 Note The load capacitors for the crystal must be verified to work over the operating conditions of the application Due to the design of the oscillator circuit it is generally better to use lower value load capacitors than those recommended by the crystal manufacturer 1 2 3 Reset Line RST pin 13 RST is the master reset line When it is brought high for two or more clock cycles the MSC121x is res
20. I C Bus Bit Transfer STOP Condition QUE C aS ONE a I se OOOO Yo No Y I i Change I l i Data Line Stable of Data Data Valid Allowed a Inter IC 12Ct Subsystem 9 3 I2C Data Transfers and the Acknowledge Bit 9 4 12C Data Transfers and the Acknowledge Bit Once a master asserts a START condition the bus is no longer free The mas ter then transmits eight bits comprising of the 7 bit address of the slave fol lowed by a read write R W bit In a system with multiple asynchronous mas ters there may be a period of bus contention and arbitration before the ad dress of the slave is transmitted If the slave is to receive data the R W bit must be 0 otherwise it will prepare to transmit data since the RAW bit is 1 For some 12C devices such as memo ries it is necessary to first write an internal address to the slave and then read or write data bytes In this case a START condition can be re asserted When a master has generated eight SCL pulses it places its own SDA output high and generates a ninth clock pulse If the addressed slave has responded it will have pulled the SDA line low this represents an acknowledgement ACK However if the addressed slave leaves the SDA line high the master recognizes that the slave has not acknowledged NACK the transfer Figure 9 4 I C Bus Data Transfer CN SC OC OON sm 0 o 9 4 MSB 3 I I l l I l I l L I Data to Slave
21. In particular it offers more resolution when acting as a baud rate generator RCAP2L RCAP2H CAh CBh Timer 2 Capture Low least significant byte Timer 2 Capture High most significant byte RCAP2H RCAP2L form a 16 bit value that is either the value of Timer 2 when in capture mode or the reload value when in auto reload mode The function of these SFRs depends on the configuration given in T2CON at C8h TL2 TH2 CCh CDh Timer 2 Low least significant byte Timer 2 High most significant byte TH2 TL2 represents the 16 bit value of Timer Counter 2 The clock source and controls for Timer Counter 2 are determined by T2CON at C8h PSW DOh Program Status Word The processor Program Status Word is accessed via PSW Bits 7 to 0 represent in order Carry Auxiliary Carry User Flag 0 Register Bank Select 1 and 0 Overflow Flag User Flag 1 and Par ity Flag PSW is not saved on the stack automatically at the start of an interrupt service routine ISR and it is common for each ISR to begin with the instruction PUSH PSW OCL OCM OCH Dih D2h D3h ADC Offset Calibration Low least significant byte ADC Offset Calibration Middle ADC Offset Calibration High most significant byte OCH OCM OCL represents a 24 bit value that compensates for the offsets within the ADC or system Usually values are provided by the ADC subsystem when the ADC is instructed to per form a calibration cycle but for so
22. P1DDRH at B4h Each pin can also be used to provide an alternate function and this may require particular values in P3 and the corresponding data direction bits For example P3 0 may be either a general pur pose I O bit or an input for serial port 0 If EGP23 bit 0 or EGPO bit 1 of HCR1 are 0 or EA is 0 when the RST pin is released P3 6 is an active low write strobe and P3 7 an active low read strobe These are used in conjunction with ALE and PSEN to coordinate access to off chip memory P2DDRL Bih Port 2 Data Direction Low configures bits 3 2 1 and 0 in Port 2 P2DDRH B2h Port 2 Data Direction High configures bits 7 6 5 and 4 in Port 2 Adjacent bits in PEDDRL and P2DDRH control the type of bit presented to device pins by Port 2 Standard 8051 that is bidirectional with weak pull up is 00 CMOS output is 01 Open drain output is 10 and input only is 11 If EGP23 bit 0 of HCR1 is 0 or pin EA is 0 when the RST pin is released P2 is either a CMOS input or output and P2DDRL and P2DDRH have no effect P3DDRL B3h Port 3 Data Direction Low configures bits 3 2 1 and 0 in Port 3 P3DDRH B4h Port 3 Data Direction High configures bits 7 6 5 and 4 in Port 3 Adjacent bits in PSDDRL and P3DDRH control the type of bit presented to device pins by Port 3 Standard 8051 that is bidirectional with weak pull up is 00 CMOS output is 01 Open drain output is 10 and input only is 11 If EGP23 bit 0 or EGPO bit 1 of HCR1
23. WDTCON 4 0 at FFh plus 1 defines the number of 100ms intervals before the watchdog timer expires assuming that the watchdog restart sequence is not performed The watchdog is enabled or disabled by writing a 1 0 se quence to bit 7 or bit 6 of WDTCON Writing 1 0 to bit 5 restarts the time out When the watchdog is enabled and expires it generates either an interrupt or a reset default as determined by bit 3 of HCRO WDTI must be cleared within the interrupt service routine Setting WDTI in soft ware generates a watchdog timer interrupt if enabled Table 5 2 Watchdog Control Bits Watchdog Interrupt has priority 12 Low and jumps to address 63h Bit Name Abbreviation Name of related SFR Abbreviation Address Hex Global Interrupt Enable EA Interrupt Enable IE 7 A8 Enable Watchdog Interrupt EWDI Extended Interrupt Enable EIE 4 E8 Watchdog Timer Interrupt flag WDTI Enable Interrupt Control EICON 3 D8 Watchdog Interrupt Priority PWDI Extended Interrupt Priority EIP 4 F8 5 6 Watchdog Timer Example Program 5 3 1 Watchdog Timer Example Program When the program is run it first requires a carriage return CR character to be received so that the baud rate can be determined Thereafter a CR code must be repeatedly received within 3 seconds otherwise the MSC121x is re set and the autobaud routine is restarted In Example 5 1 EWDR bit 3 of HCRO must be 1 default for a reset to occur In another applicatio
24. 10 Timer Counter 2 Baud Rate Generator cece eee eee eens 11 11 Synchronous Receive at fo_K 4 2 0 cee eee nn 12 7 Synchronous Transmit at fci K 4 6 eee n 12 7 Asynchronous 10 Bit Transmit Timing 0000 eee eee 12 8 Asynchronous 10 Bit Receive Timing 2 6 c eee e eee eens 12 8 Asynchronous 11 Bit Receive 00 een 12 9 Asynchronous 11 Bit Transmit 0 0 00 0 tet eee ees 12 9 Serial Port with Software Buffer 000 c cece nents 12 10 Ld Jod Ld bod Job dn do 45 4 do dedo ook Lodo P 45 de Lo d4 DL WE own dodo bog Ibo bo Lb Eu oll 7o Q do do qo dodvoocoo0 uoooooosoooocooogoGcogooognsesBs6BBggonmmomaaaza SO Uie Co Doo Se L5 d amp CO Jo I D OO c4 0 Ol Roto Jo c r D O9 74 O UI d OX TO d OMS To ONS doo No Tables MSC121x Product Family Matrix 0 000 e eens 1 3 MSC121x Pin Descriptions 00 cece 1 5 Port 1 Alternate Functions 0 20 c eee eee nnn 1 8 Port 3 Alternate Functions 0 c cece aia iaee aia n enna 1 9 Program Memory and External Data Memory Addresses 0000 e cece eens 2 3 MSC121x Flash Memory Partitioning and Addresses 000 c cece e eens 2 4 On Chip 8051 Meimoty yes esos beh ott dosed reni csraw dere pU Eterdarrei Reisk 2 5 Special Function Register Map ssssssssssssssss e eens 3 2 Sldauod NU ME Cc UNUM 3 4 8051 Working Registers ers dee
25. 5 Yellow LED on EVM sbit SlaveSelect P1 0 avoids onboard SPI devices code at OxFFF3 void autobaud void unsigned char SPIoutin unsigned char n while AIE amp 0x08 RedLed RedLed wait for TX empty SPIDATA n output while AIE amp 0x04 YellowLed YellowLed wait for RX return SPIDATA input void main void data unsigned char i j 0x41 AIE 0 No interrupts PDCON amp 0x01 turns on SPI P1DDRH 0x40 CMOS output for P1 7 P1DDRL 0x01 CMOS output for P1 4 SPICON 0xCA Divide 128 FIFO off msb master SPITCON 0x28 SCK driver on SlaveSelect 1 autobaud printf Simple polled loopback SPI n RI O 0 Clear received flag in UART while 1 while RI_0 RedLed YellowLed 0 SlaveSelect 0 i SPIoutin j SlaveSelect 1 putchar i RI_0O 0 any character to pause while RI_0 wait for character j SBUFO get character RIO 0 continue Serial Peripheral Interface SPIt 10 9 SPI Examples A burst of characters is written to the FIFO in every second and with MOSI and MISO joined together they are read back by the CPU whenever the number of received characters is 16 or more If the burst size is less than 16 2 or more seconds will be needed to trigger a receive interrupt Example 10 2 SPI FIFO Mode File spiFIFOint c outputs and receives bytes via SPI FIFO MSC1211 EVM Switches 1 0n SW3 12345678 SW5 12345678
26. 8 bit pointer it is pre in cremented and post decremented which means that the stack grows up wards and SP always points to the most recent entry The stack can store ei ther data values or addresses Registers The default value for SP is 7 so it starts to grow just above memory associated with address bank 0 at core data memory locations 00h to 07h Since address bank 1 occupies locations 08h to OFh care must be taken to redefine the initial value of SP whenever register bank 1 or 2 or 3 is to be used The selection of the active register bank is determined by bits 4 and 3 of the Program Status Word PSW For example when RS1 1 and RSO 1 bank 3 is active and R2 corresponds with core data memory location 1Ah PSW also contains the Carry flag CY Auxiliary Carry AC General purpose flags F1 and FO as well as the Overflow flag OV and the Parity flag P Some instructions change the flags but the majority do not Register B is sometimes useful to store a byte wide variable or 8 bit wide vari ables especially for applications written entirely in assembly language Care is needed because it is used by MUL and DIV instructions that may be called by C run time libraries The 16 bit program counter PC is incremented as sequential instructions are executed For jumps it is loaded with a new value and for CALLs and inter rupts it is stored to the stack for recovery during RETurns and RETI It always points to a byte in p
27. A A PC fun4 1 mov C ACC 0 mov Q C ret fun4 t db 1 1 1 1 1 1 1 1 n db 0 0 0 1 1 1 1 1 Clocks MSC121x 52 8051 funb5 mov A R7 xrl a 08H dlr C subb A 3 cpl C mov Q C ret Clocks MSC121x 44 8051 fun6 mov A R7 xrl A 08H add A 0FDH Q C mov ret end 4 14 108 84 Ratio 2 4 get input values Z Y X W Carry W Carry W amp X Carry W amp X Y Carry W amp X Y Z Output new Q value Ratio 1 9 get input values Z Y X W ensure just 4 bits offest for instructions get table entry lsb into carry and hence Q table represents easy way to implement any function Ratio 2 1 get input values Z Y X W complement Z clear carry test for boundary correct polarity and output to Q Ratio 1 9 get input values Z Y X W complement Z identify boundary and output to Q Chapter 5 System Clocks Timers and Functions This chapter describes the system clocks timers and functions of the MSC121x Topic Page 5 1 Timing Chain and Clock Controls Luuuuueeeee 5 2 5 2 System Clock Divider cr ERNST 5 5 5 32avatchdogilimeri eee ceerELo PEST 5 6 5 4 Low Voltage Detection a aI a n 5 8 BS InETCMEnG Configuration e P eee ee e e e E E 5 9 5 6 Breakpoinis een e eSI 5 11 5 1 Timing Chain and Clock Controls 5 1 Timing Chain and Clock Controls Along with Timer Counters 0 1 and 2 found in the 8051 8052 architectu
28. A Ri an 8 bit low order address may be presented to external off chip data memory via pins associated with Port 0 In the MSC121x the upper byte of a 16 bit address is placed in MPAGE This value appears automatically on pins associated with Port 2 when the MOVX instruction is executed CADDR 93h Configuration Address Register The MSC121x contains 128 bytes of Flash memory that may represent hardware configuration data such as the date of manufacture or any other identification data This memory is distinct from all other memory addressed by the MSC121x during normal execution of instructions To access this configuration data a 7 bit address must first be written to CADDR See CDATA at 94h CDATA 94h Configuration Data Register Data in the 128 bytes of Flash hardware configuration memory is accessed via this read only register The 7 bit address must first be written to CADDR at 093h NOTE The instruction reading CDATA must not be in Flash memory itself otherwise the data read will be invalid Typically instructions will be executed from the internal boot ROM SRAM that is mapped to code space or off chip program memory when reading CDATA MCON 95h Memory Configuration Bit 7 is used to identify one of two 16 bit breakpoint registers while bit O determines if the exter nal on chip RAM is mapped to both code and data spaces or just to data space SCONO 98h Serial Control 0 Contains six bits that determine the format of data on serial port 0
29. Change to subtraction mode 2 3 Next CPU subtraction on write to SUMRO A A B 1 olo Shift right by SSS 1 bits 0 clc Add ADC conversions to Summation register 2 CCC 1 times that is 2 to 256 times Add ADC conversions to Summation register 2 CCC 1 times 1 Cc yc that is 2 to 256 times Then shift right by SSS 1 bits and set the summation complete interrupt flag 1 For the MSC1210 writing 00h to SSCON clears the 32 bit hardware accumulator and selects CPU con trolled summation For other devices the 32 bit hardware accumulator is cleared but the mode is not changed 2 These operations are not available in the MSC1210 3 If the polarity bit in ADCON1 at DDh is 0 the 24 bit ADC conversion is sign extended to 32 bits That is bit 7 of ADRESH is propagated to all higher bits Analog To Digital Converters 6 13 32 Bit Summation Register Immediately after a CPU instruction writes data to SUMRO it may trigger an addition subtraction or shift depending on the value of SSCON Addition and subtraction take a single cycle tc x Shifting is performed either 1 or 2 bits per cycle and takes up to 4 tc x periods to complete Table 6 9 Summation Interrupt Controls Family Bit 6 of AIE at A6h Bit 6 of AISTAT at A7h Bit 6 of AIPOL at A4h Part Enable Summation Interrupt Summation Interrupt Status Flag Summation Interrupt Poll MSC1211 Write Read Read MSC1212 9 Masked 0 Inactive or masked Summation i
30. DER bone dos oro a ud e odor ee 4 2 Symbol Descriptions for Instruction List Table 4 3 000s 4 5 Instruction ISt osred vue Pg essier este dak3 kt cfr sessed ae ER erhdeeqs 4 5 MSC121x Op COd6S ue bare dr bw eee Stc E Oe daa Deed aee d 4 10 SYSCLK System Clock Divider Register cece eee eee eee eee es 5 5 Watchdog Control Bits 1 2222 a orao daada en e e a a a a ee nid ee LUPA 5 6 LVDCON Low Voltage Detect Control 00 0 eee 5 8 Low Voltage Detect 0 ccc niesi iiia naa aiana a aa Ei aa tee eens 5 8 Hardware Configuration Register 0 0 c ccc e eee 5 9 Hardware Configuration Register 1 0 ccc cece cette eee 5 10 MCON Memory Control 00 ccc mnn 5 11 BPCON Breakpoint Control sssssssssssssssses 5 11 BPL Breakpoint Low Address for BP Register Selected in MCON at 95h 5 12 BPH Breakpoint High Address for BP Register Selected in MCON at 95h 5 12 BI CAKDOINS 2 desserts E A hartesku d tette tit apta iesu tede fcc 5 12 ADMUX ADC Multiplexer ssssssessseee III 6 4 Impedance Divisor G for a Given PGA isssssslssssssssesssse sh 6 5 ADCONO ADC Control Register 0 00 00 eee ee 6 6 ADCONO Bit Parameters 0000 ess eens 6 7 ADCON1 ADC Control Register 1 0 00 cece eee eee eee 6 9 ADC Interrupt Controls y saa aad au mari ian aa a ai aa ia nett nh 6 11 Summation Register eio ai
31. ESO and ETO enabled EMSEC enabled Auxiliary interrupts enabled low foreground program Interrupts from Timers 0 and 2 are both in the low priority group and are there fore mutually exclusive and share register bank 1 The priority of Serial Port 0 is raised to high by writing a 1 to bit 4 of register IP and therefore uses a differ ent register bank Similarly since the milliseconds interrupt is in the highest group the service routine is allocated its own register bank If interrupts from Timer 0 and Timer 2 are pending at the same moment Timer 0 will be serviced first because it has a higher relative priority within the low group In this particular example individual service routines may not use registers de pending upon the efficiency and optimization level of the compiler However the allocation of register banks ensures mutually exclusive contexts and is the usual practice The interrupt number used in C is given by ISR Address 3 divided by 8 Example of Wake Up from Idle 13 6 Example of Wake Up from Idle In order to reduce operating power the MSC121x can be placed into an idle state by writing 1 to bit 0 of PCON at 87h In this state the CPU Timers 0 1 and 2 and USARTs are not clocked although other peripherals remain ac tive unless previously powered down via bits in PDCON at F1h Once in the idle state normal operation is resumed by an enabled auxiliary interrupt or an enabl
32. Exclusive OR A to direct byte 2 2 8 12 62 XRL direct data Exclusive OR immediate data to direct byte 3 3 12 24 63 CLRA Clear A 1 1 4 12 E4 CPLA Complement A 1 1 1 4 12 F4 RLA Rotate A left 1 1 4 12 23 RLCA Rotate A left through carry X 1 1 4 12 33 RRA Rotate A right 1 1 1 4 12 03 RRCA Rotate A right through carry X 1 1 4 12 13 SWAPA Swap nibbles of A 1 1 4 12 C4 1 Flags CY AC and OV may also be changed by explicit writes to corresponding bits in the PSW 2 Number of cycles is user selectable See SFR CKCON at 8Eh Table 4 3 Instruction List continued Instruction Types and Addressing Modes Flags 1 g o g 11 X as a P o ajo B8 Q 5 Code Mnemonic Description civi z z e Hex Data Movement MOV A Rn Move register to A 1 1 4 12 E8 EF MOV A direct Move direct byte to A 2 2 8 12 E5 MOV A Ri Move indirect data memory to A 1 1 4 12 E6 E7 MOV A data Move immediate data to A 2 2 8 12 74 MOV Rn A Move A to register 1 1 4 12 F8 FF MOV Rngirect Move direct byte to register 2 2 8 24 A8 AF MOV Rn data Move immediate data to register 2 2 8 12 78 7F MOV direct A Move A to direct byte 2 2 8 12 F5 MOV direct Rn Move register to direct byte 2 2 8 24 88 8F MOV direct direct Move direct byte to direct byte 3 3 12 24 85 MOV dire
33. IN pin is used as the reference for the DAC Consequently if either the 2 5V or 1 25V on chip reference is used the ADC subsystem has to be powered up using bit 3 of PDCON In addition voltage to current converters may be selectively enabled for DACO or DAC1 and result in a scaled current as well as a voltage on sepa rate pins If bit 5 of DACOCON or DAC1CON is 0 a current equal to DACO RDACO or DAC1 RDAC1 is generated via a current mirror and flows out of the MSC1211 from the AVpp supply The analog pathways are depicted in Figure 7 1 along with pin allocations some of which are multiplexed with inputs to the ADC Figure 7 1 DAC Architecture rx oO 21 AIN3 VDAC3 o Q 20 AIN2 VDAC2 eto Q o oo 31 VDAC1 Tire paoi oo Sink ct AVpp 28 Q 19 AINT IDACI Source Current Mirror 32 RDACT AN REFOUT REF IN oO 17 VDACO EL pe Sink L AINO IDACO DAG OduF 18 Sink O F REF Source Current Connection 2 5V 1 25V Mirror RDACO 16 WW 7 2 DAC Selection 7 2 DAC Selection Each DAC has an 8 bit control register a buffered 16 bit data register and two additional bits which determine the way that the output data register is loaded Three SFRs are used to access and control the DACs using an indirect ad dressing schem
34. Jump relative if direct bit is 1 3 4 16 24 20 JNB bit rel Jump relative if direct bit is O 3 4 16 24 30 JBC bit rel Jump relative if direct bit is 1 and clear the bit 3 4 16 24 10 JMP A DPTR Jump indirect Program counter becomes 1 3 12 24 73 DPTR plus A JZ rel Jump relative if accumulator is 00h 2 3 12 24 60 JNZ rel Jump relative if accumulator is not 00h 2 3 12 24 70 CJNE A direct rel Compare A with direct data and jump relative if X 3 4 16 24 B5 not equal CJNE A data rel Compare A with immediate data and jump X 3 4 16 24 B4 1 Flags CY AC and OV may also be changed by explicit writes to corresponding bits in the PSW relative if not equal 2 Number of cycles is user selectable See SFR CKCON at 8Eh Table 4 3 Instruction List continued Instruction Types and Addressing Modes o o o x ri 8 Flags 1 o g __ x x 8 a N gt o CclAo 2 9 8 amp Code Mnemonic Description Y lc vm z z amp Hex CJNE Rn data rel Compare register with immediate data and X 38 4 16 24 B8 BF jump relative if not equal CJNE Ri data rel Compare indirect with immediate data and X 38 4 16 24 B6 B7 jump relative if not equal DJNZ Rn rel Decrement register and jump relative if not 0 2 12 24 D8 DF DJNZ direct rel Decrement direct byte and jump relative if not 0 16 24 D5 Miscellaneous NOP No operation 1 1 12 00 ees um 4 1 12
35. O3FFh If RAMMAP is 1 this SRAM is replicated as code and data at addresses 8400h to 87FFh in user mode MSC121x Addressable Resources Program Memory and Data Memory In typical 8051 architecture program memory is read only However in the MSC121x Flash memory that is allocated to code space can be modified when an instruction such as MOVX DPTR A is executed with bit 0 of MWS SFR 8Fh set to 1 For more details see the Program Memory Lock and Reset Sector Lock bits in HCRO Although modifying code in this way can provide flexibility of design it is not intended to support repetitive use of self modifying coding techniques For this purpose the user may choose to map the 1024 bytes of on chip SRAM to data and code spaces The Boot ROM provides functions to manipulate the Flash memory but other routines can be copied to code mapped SRAM The on chip Flash memory may be partitioned so that it is shared between code and data spaces This is done via the three least significant bits DFSEL in HCRO when the MSC121x is programmed 2KB of on chip Boot ROM is used during serial and parallel programming modes when it is temporarily mapped to 0000h to 07FFh During normal pro gram execution it may be mapped into addresses F800h to FFFFh to provide access to useful routines for example serial I O This occurs by default via bit 4 of HCRO Program memory is accessed in an implicit manner as a program is executed or by explicit use of t
36. Program 6 9 ADC Example Program Example 6 1 shows how the ADC may be used in a polled environment with a foreground activity that produces a pseudo random binary data stream The number of characters output per line equals the temperature of the MSC121x in degrees Celsius C The main program is written in C and calls the Boot ROM to determine the baud rate and an assembly language function to read the ADC conversion It is intended for use directly with Texas Instruments MSC1210 DAQ EVM or full EVMs with an appropriate value for ACLK Example 6 1 ADC Program Polledadc c Pseudo Random Binary Sequence generator with Polled ADC MSC1210 EVM Switches 1 0n SW3 12345678 SW6 12345678 0 Off I1110111 11110000 include lt Reg1210 h gt include lt stdio h gt sbit RedLed P3 4 RED LED on EVM A sbit YellowLed P3 5 Yellow LED on EVM code at OxFFF3 void autobaud void extern signed long bipolar void reads ADC value void main void data char mask 0x8E r 1 n j x temp 50 count 255 data signed long reading data int iy data float y PDCON Ox0f7 would turn adc on but turn other subsystems off PDCON amp 0b00001000 turns on adc and leaves other subsystems unchanged PDCON amp 0x08 turns on adc and leaves other subsystems unchanged ACLK 2 ACLK frequency 1 8432MHz 241 0 6144MHz for MSC1210 DAQEVM ACLK 17 11 0592MHz 17 1 0 6144MHz for MSC1210EV
37. R means that RAW bit is 1 Inter IC 12Ct Subsystem 9 9 I2C Related Registers 9 6 12C Related Registers The I2C interface shares pins and registers with the Serial Peripheral Interface SPI both interfaces must not be enabled at the same time via bit 5 PDI2C and bit 0 PDSPI of Power Down Control PDCON SFR at F1h Table 9 7 PDCON of 12C and SPI PDCON at Fih Bit 5 PDI2C Bit 0 PDSPI 12C SPI 0 0 Undefined Undefined 0 1 Enabled Disabled 1 0 Disabled Enabled 1 1 Disabled Disabled The 12C interface uses bit 2 EI2C of the Auxiliary Interrupt Enable AIE SFR at A6h to enable interrupts as well as bit 2 I2CSI of the Auxiliary Interrupt Status Register AISTAT SFR at A7h and bit 4 Al of the Enable Interrupt Con trol EICON SFR at D8h The setup and hold times for data transfers are determined by the frequency f of the MSC1211 13 oscillator and the value written to the USEC SFR at FBh It is expected that USEC is set to f 1 where fis in MHz so that an internal reference of approximately 1us is obtained Table 9 8 Interrupt Control for 12C SFR SFR Bit Bit Name Address Number Name Action or Interpretation AIPOL 12C Status Interrupt before masking Read 0 12C interrupt inactive 1 12C interrupt active Pending Auxiliary Interrupt Register Read 00112 indicates 12C interrupt pending PAI AIE Enable 12C Status Interrupt Write 0 Masked 1 Enabled shared vector to addre
38. SFR CKCON at 8Eh Programmer s Model and Instruction Set 4 7 Instruction Types and Addressing Modes Table 4 3 Instruction List continued Flags 1 o o g FT T4 2 E p o o C o 89 D 5 Code Mnemonic Description Y vm z z Hex Boolean CLRC Clear carry 0 1 1 4 12 C3 CLR bit Clear direct bit 2 2 8 12 C2 SETBC Set carry 1 1 1 4 12 D3 SETB bit Set direct bit 2 2 8 12 D2 CPL C Complement carry X 1 1 4 12 B3 CPL bit Complement direct bit 2 2 8 12 B2 ANL C bit AND direct bit to carry X 2 2 8 24 82 ANL C bit AND inverse of direct bit to carry X 2 2 8 24 BO ORL C bit OR direct bit to carry X 2 2 8 24 72 ORL G bit OR inverse of direct bit to carry X 2 2 8 24 AO MOV C bit Move direct bit to carry X 2 2 8 12 A2 MOV bit C Move carry to direct bit 2 2 8 24 92 Branching ACALL addr11 Absolute call to subroutine within current page 2 3 12 24 11 F1 LCALL addr16 Long call to subroutine PC becomes addr16 3 4 16 24 12 RET Return from subroutine 1 4 16 24 22 RETI Return from interrupt 1 4 16 24 32 AJMP addr11 Absolute unconditional jump within current 2 3 12 24 01 E1 page LJMP addr16 Long jump PC becomes addr16 3 4 16 24 02 SJMP rel Unconditional relative jump 2 3 12 24 80 JC rel Jump relative if carry is 1 2 3 12 24 40 JNC rel Jump relative if carry is 0 2 3 12 24 50 JB bit rel
39. a 1 to RXFLUSH bit 7 of SPIR CON which causes CPUrxp to be set equal to SPIrxp and RXcount to 0o The transmit buffer may be flushed by writing a 1 to TXFLUSH bit 7 of SPIT CON which causes CPUtxp to be set equal to SPItxp and TXcount to 0 Serial Peripheral Interface SPIt 10 7 SPI FIFO Buffer Table 10 9 SPIRCON SPI Receive Control Register SPIRCON SFR 9Ch Reset Value 00h Action When Written 7 RXFLUSH Flush Receive FIFO Write 0 No effect 1 The pointer used by the CPU to fetch data from the FIFO CPUrxp is set equal to the pointer used by the SPI interface to put data into the FIFO SPlrxp In effect this clears the receive FIFO The receive counter RXcount is also cleared 6 3 Undefined 2 RXIRQ2 Receiver IRQ count threshold when in FIFO mode RXIRQ RXIRQ2 RXIRQ1 RXIRQO 0005 to 1115 Generates SPI receive IRQ when receive count 2RXIRQ or more that is 1 or more to 128 or more See ESPIR bit 2 of AIE at A6h and SPIR bit 2 of AISTAT at A7h 1 RXIRQ1 0 RXIRQO Bit Name Interpretation When Read 7 0 RXCNT The number of bytes in the FIFO and RX BUF still to be read 0 to 129 This is RXcount Table 10 10 SPITCON SPI Transmit Control Register SPITCON SFR 9Dh Reset Value 00h Bit Name Action When Written 7 TXFLUSH Flush Transmit FIFO Write 0 No effect 1 The pointer used by the CPU to put data into the FIFO CPUtxp is set eq
40. a byte al ways results in reception of a byte This passes from the receiver shift reg ister RX SR via RX BUF to the SRAM pointed to by SPIrxp This SRAM location was used to hold a transmitted byte and is now overwritten with the received byte SPIrxp is incremented along with RXcount 4 The CPU reads data from SRAM pointed to by CPUrxp via SPIDATA CPUrxp is incremented and RXcount is decremented Figure 10 3 SPI FIFO Operation 8 Bytes Written 4 Bytes Queued 2 Bytes Sent and Received SPIDATA FIFO In SPI Transmit wa ud SPIDATA Pointer SPI Receive Transmit Receive Shift Register Special conditions FIFO Out 12 Byte FIFO Memory 1 Ifthe FIFO is full when the CPU writes to SPIDATA the data are discarded and neither CPUtxp nor TXcount are altered 2 Ifthe FIFO is empty and the CPU reads from SPIDATA the value returned is undefined and neither CPUrxp nor RXcount are altered 10 6 SPI FIFO Buffer Table 10 7 SPISTART SPI Buffer Start Address SPISTART SFR 9Eh Reset Value 80h Action or Interpretation Always 1 SPISTART Write The start address of the circular FIFO buffer somewhere within SRAM from 80h to FEh The value must be less than SPIEND The FIFO resides between SPIS TART and SPIEND inclusive Writing to SPISTART initializes all the FIFO pointers and counters CPUwrp SPItxp CPUrdp SPIrxp SPISTART and TXcount RXcount 0 Read The current val
41. and coordinate the transfer of data between itself and slave ICs If active it can transmit data onto the 12C bus or receive data from the bus In either case it generates the synchronizing clock Similarly where the MSC1211 13 is considered a slave to another microcon troller it is able to transmit and receive data synchronized by this master Many MSC1211 13s can share a single IC bus where each acts as a master at different times The active master can be determined by software or result from bus arbitration in the event of asynchronous contention Table 9 1 describes selected 12C terms Table 9 1 12C Terminology 9 2 Name Description Transmitter The IC that sends data to the bus Receiver The IC that receives data from the bus Master The IC that initiates a transfer generates clock signals and terminates a transfer Slave The IC addressed by a master Multi master More than one master can attempt to control the bus at the same time without corrupting the message Arbitration Procedure to ensure that if more than one master simulta neously tries to control the bus only one is allowed to do so and the message is not corrupted Synchronization Procedure to synchronize the clock signals of two or more ICs 12C Bus Lines and Basic Timing 9 3 12C Bus Lines and Basic Timing The 12C bus uses two bidirectional data lines One is the data line SDA and the other is the clock line SCL Each is connected
42. and the polarity of the clock to suit various applications Data to be transmitted are written to the SPI Data Register SPIDATA at 9Bh which is then passed to the double buffered SPI transmit interface Similarly data that has been received are read via this SFR from the double buffered SPI receive interface Data are routed through a FIFO buffer of up to 128 bytes if bit 4 of SPICON at 9Ah is set Table 10 4 SPIDATA SPI Data Register SPIDATA SFR 9Bh Reset Value 00h Action or Interpretation SPIDATA Write Read Data to be transmitted by or received from the Serial Peripheral Interface 10 4 10 3 SPI Interrupts SPI Interrupts When an SPI interrupt is active and enabled the MSC121x CPU jumps to loca tion 0033h The interrupt service routine may read the Pending Auxiliary Inter rupt Register PAI at A5h to establish the source of the interrupt For the SPI receiver the number returned is 3 and for the SPI transmitter it is 4 This as sumes that higher priority auxiliary interrupts have not occurred Al bit 4 of EICON must be cleared within the interrupt service routine when no further auxiliary interrupts are pending Setting Al in software generates an Auxiliary Interrupt if enabled but if there are no pending interrupts the Pend ing Auxiliary Interrupt vector in PIA at A5h will read as O When the FIFO buffer is disabled the transmit interrupt flag will be set whenev er the SPI transmitter is empty and
43. as well as two bits for transmit and receive interrupt flags It is used in conjunction with TCON at 88h TMOD at 89h and various timer data registers SBUFO 99h Serial Buffer 0 When written SFUFO provides data for the transmitter associated with serial port 0 When read data is provided by the receive register Serial data is output on pin TxDO and received on pin RxDO 3 6 SFR Overview Table 3 2 SFR Overview continued Address Name Hex Description SPICON 9Ah I2CCON 9Ah SPI Control If the Serial Peripheral Interface SPI is enabled see bit 0 of PDCON at F1h SPICON config ures SPI communication characteristics such as data rate clock polarity and whether the MSC121x is a master or slave Writing to SPICON resets the counters and pointers used by the SPI interface in FIFO mode 12C Control If the I2C interface is enabled see bit 5 of PDCON at Fh I2CCON configures IC communica tion characteristics such as START STOP ACK clock stretching and whether the MSC121x is a master or slave Writing to IICCON does not reset the 12C interface SPIDATA 9Bh I2CDATA 9Bh SPI Data If the SPI is enabled see bit 0 of PDCON at F1h data written to SPIDATA causes it to be trans mitted via the SPI interface while received data is obtained by reading SPIDATA I2C DATA If the 12C Interface is enabled see bit 5 of PDCON at F1h data written to I2CDATA causes it to be transmitted via the I2C interface while
44. at OOOBh or cleared manually by writing a O to it in software Figure 11 1 Timer 0 1 Modes 0 and 1 Baud Rate to Serial Ports Timer 1 Only THO Mode 1 Interrupt TOM is CKCON 3 Mode 0 Timer Counters 0 and 1 fork 12 if TOM 0 cu u Modes 0 anat fcud4 if TOM 1 cb NOTE Signals and names shown are with respect to Timer 0 The same functional behavior is available from Timer 1 Pin TO m m ae Pu Pin INTO Table 11 3 Modes 0 and 1 Operation C T TOM Pin TO TRO GATE PinINTO CLOCK 0 0 x 1 0 x fcLK 12 0 0 x 1 1 1 foLK 12 0 1 X 1 0 x fcuk 4 0 1 x 1 1 1 fcik 4 1 X 1to0 1 0 X Increment 1 x 1 to 0 1 1 1 Increment 1 x 1 1 to 0 0 x Increment 1 X 1 1to0 1 1 Increment 1 X 1 1 0 to 1 0 Increment 1 X 1 1 1 1to0 Increment NOTE For all other combinations of control bits and pins THO TLO is unchanged Timers and Counters 11 5 Timer Counters 0 and 1 11 2 2 Mode 2 The description that follows is with respect to Timer Counter 0 but applies to Timer Counter 1 with appropriate re allocation of control bits However the overflow condition of Timer 1 alone is able to act as a reference clock for the serial ports Figure 11 2 Timer 0 1 Mode 2 11 6 THO fe iel Reload Interrupt gg Timer Counters 0 and 1 TONIS CKCON 3 Mode 2 foik 12 if TOM 0 NOTE Signals and d 4 if TOM 1 i feud if TO O names shown are 1 W
45. back to serial port 0 as shown in Figure 12 7 Figure 12 7 Serial Port with Software Buffer 12 10 Serial Port 0 Receiver Software Buffer Serial Port 1 Transmitter Serial Port 0 Transmitter Serial Port 1 Receiver When implemented in a software development environment together with an MSC1210EVM the user is able to type characters at the PC keyboard and see the same characters on the download window but with a noticeable delay The yellow LED will flicker as characters are passed at 21 baud on pin P1 2 The baud rate of serial port 1 is slow so the buffer may quickly fill up if keys are typed too rapidly Impending overflow is indicated by the red LED Example Program Example 12 1 Serial Port with Software Buffer Code File SerialOlbuf c Using serial ports 0 and 1 with a buffer MSC1210 EVM Switches 1 0n SW3 12345678 SW6 12345678 0 Off TLITIOT11 11110000 include lt Reg1210 h gt define xtal 11059200 define BAUD 9600 define limit 8 sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM Join J4 pins 2 and 3 on EVM for loopback void main void data unsigned char i limit j limit n 0 empty buffer idata unsigned char buffer limit SCON0 0x70 Serial Port 0 mode 1 10 bit asyn SCON1 0x72 Serial Port 1 mode 1 10 bit asyn TI gt empty RI_O RI_1 0 clear received flags CKCON 0x10 Timer 1 at fclk 4 EICON 0x80 SMOD1 1 TCON
46. classed as low high and highest it is possible to have three nested levels of interrupt For example the main program may be interrupted by an event of low priority but the service routine may be interrupted by an event of high priority which in turn could be interrupted by an event of highest priority It is essential that there is no unintentional interaction between different inter rupts and that the operating environment or context is restored prior to ter mination of an ISR For all but the simplest of ISRs it is necessary to save and restore the primary context PSW and Accumulator to and from the stack Similarly working registers RO to R7 may need to be PUSHed and POPed but this is time consuming and can be avoided by register bank switching Once the primary context has been PUSHed onto the stack the value of bits 4 and 3 in the PSW may be changed to select a different bank of 8 bit working registers In this way the values in the previous bank are not changed by in structions that reference registers relative to the new bank It is practical to allo cate bank 0 to the main program bank 1 to low interrupts bank 2 to high and bank 3 to highest Since working registers are also mapped to memory loca tions it is possible to modify and corrupt any register by writing to an explicit location For example R4 of bank 2 is at data address 14h Care may be need ed in this regard when using multiple interrupts Interrupts 1
47. code and external data by the MOVC and MOVX instructions respec tively See Data Pointer Select DPS at 86h SFR Overview Table 3 2 SFR Overview continued Address Hex Description Name DPL1 84h Data Pointer 1 Low least significant byte DPH1 85h Data Pointer 1 High most significant byte DPL1 and DPH1 are read and written independently except for the instruction MOV DPTR data16 but are used together by instructions that reference the 16 bit data pointer called DPTR DPTR is used to address code and external data by the MOVC and MOVX instructions respec tively Data Pointer Select DPS at 86h DPS 86h Data Pointer Select The original 8051 architecture has one DPTR but the MSC121x has two If bit O of DPS is low DPTR is formed from DPHO DPLO otherwise it is formed by DPH1 DPL1 PCON 87h Power Control The core processor may be placed in low power modes by setting the STOP and IDLE bits of this SFR It also contains two general purpose flags which are often used to help coordinate power up and power down activities There is also a bit called SMOD which may be used to double the baud rate for serial port 0 This bit is not to be confused with PDCON at F1h which is used to turn various subsystems on and off TCON 88h Timer Control Bits within TCON control the response to interrupts from Timer Counters 0 and 1 and external inputs INTO and INT1 Timer Counters 0 and 1 may also be halted
48. contents of Register 1 provide the 8 bit address of the data in 27h core memory that is added to A ADD A PO Direct The code byte at PC 1 provides the 8 bit address of the data in 25 80h core memory that is added to A In this case SFR PO at 80h ADD A R4 Register The contents of Register 4 is added to the accumulator The core 2Ch memory location corresponding to register 4 is either 04h OCh 14h or 1Ch depending on the register bank select bits in PSW Instruction Types and Addressing Modes Table 4 2 Symbol Descriptions for Instruction List Table 4 3 Symbol Description A Accumulator Rn Register RO R7 of the current register bank direct Internal core address RAM 00h 7Fh or SFR 80h FFh Ri RO or R1 act as an 8 bit pointer to internal core RAM OOh FFh except MOVX references external data space rel Two s complement offset byte 128 to 127 relative to the start address of the next sequential instruction bit Direct bit address Bits 00h 7Fh map to RAM while 80h FFh map to SFRs data 8 bit immediate constant data16 16 bit immediate constant adadr16 16 bit destination address anywhere within program memory address space addr11 11 bit destination address anywhere within the current 2K page of program memory Table 4 3 Instruction List o 7 2 8 ee pe SENE 2m Sie Mnemonic Desc
49. in software writing a 1 to it causes an interrupt if it is enabled 11 10 Timer Counter 2 11 3 3 Baud Rate Generator When either RCLK is 1 or TCLK is 1 Timer Counter 2 operates as a baud rate generator for serial port O In this mode TH2 TL2 is reloaded from RCAP2H RCAP2L whenever it overflows from FFFFh to 0000h Control bit TR2 is active high and enables either an internal clock or an external clock on pin P1 0 T2 according to the state of C T2 Specifically when C T2 is 0 TH2 TL2 runs at fc k 2 otherwise when C T2 is 1 it runs at a rate deter mined by pin P1 0 T2 A negative edge on pin P1 1 T2EX when control bit EXEN2 is 1 causes the interrupt flag EXF2 to be set If interrupt enables ET2 and EA bits 5 and 7 respectively of IE at A8h are both 1 the CPU jumps to the interrupt service routine at 002Bh EXF2 has to be cleared in software and writing a 1 to it causes an interrupt if enabled To accommodate applications that require different transmit and receive baud rates the overflow of Timer 1 optionally divided by 2 may be selected as shown in Figure 11 6 When Timer Counter 2 uses the internal clock to determine the baud rate of serial port 0 the rate is given by fci 32 65536 RCAP2H RCAP2L Figure 11 6 Timer Counter 2 Baud Rate Generator Tx and Rx Clocks Serial Port 1 divide 0 EICON7 Timer 1 Overflow by 2 PCON 7 0 0 m divide Rx Clock B divide Tx Clock
50. of the MSC1211 and MSC1213 Topic Page 9 41 Introduction to the I2C Bus esseseeeee eene 9 2 92 2C Terminology 9 9 seer aero erie ne sere RESET 9 2 9 3 12C Bus Lines and Basic Timing 00eceeeeeeeeeeeenees 9 3 9 4 12C Data Transfers and the Acknowledge Bit 9 4 9 5 9I2c PrinclpallRegisterss 95 5 ee oer cee reer en ere 9 6 9 6 12C Realted Registers ssssesesen nnne 9 10 9 7 12C Example MSC1211 13 as Master use 9 11 9 8 12C Example MSC1211 13 as Slave 9 13 9 9 12C Example MSC1211 13 as an Interrupt Driven Slave 9 15 9 10 12C Synchronization and Arbitration 00000eeee 9 17 93415 I2C East Modes 55 ae a o dte seca emia semen eine eye 9 17 9 12 112C General Call oaae ea 9 099 9 5 E 9 17 9 13 12C 10 Bit Addressing eee 9 18 9 1 Introduction to the IFC Bus 9 1 Introduction to the 12C Bus The MSC1211 13 provide hardware support for serial transfers according to the I2C protocol This protocol was defined to permit multiple 8 bit transfers be tween multiple integrated circuits on the same 2 wire bus At any one time a bus master coordinates transfers from one slave or to multiple slaves For a detailed description of the 12C bus refer to The 2C bus Specification by Philips 9 2 12C Terminology For many systems where the MSC1211 13 is the only microcontroller it will be the master
51. or allowed to run TMOD 89h Timer Mode Configures the modes of operation for Timer Counters 0 and 1 for example whether clocks are internal or external the number of bits and the reload options All 8051 Timer Counters except for system timers increment count up when they are clocked TLO 8Ah Timer 0 Low THO 8Ch Timer 0 High Depending on the mode of operation defined by TMOD at 89h these SFRs may be considered as independent 8 bit entities or together as a 13 or 16 bit register NOTE These SFRs do not have adjacent addresses and cannot be referenced using the C compiler keyword sfr16 TL1 8Bh Timer 1 Low TH1 8Dh Timer 1 High Depending on the mode of operation defined by TMOD at 89h these SFRs may be considered as independent 8 bit entities or together as a 13 bit or 16 bit register NOTE These SFRs do not have adjacent addresses and cannot be referenced using the C com piler keyword sfr16 CKCON 8Eh Clock Control The original 8051 required 12 system clock pulses per instruction cycle and each timer had a divide by 12 prescaler Since the MSC121x uses only four clocks three bits within CKCON selec tively allow the prescalers of Timers 0 1 or 2 to be divide by 12 default or divide by 4 Three other bits determine the number of wait states introduced into the timing of read RD P3 7 and write WR P3 6 strobes when the MOVX instruction is used to access off chip memory Special Functions Registers 3 5
52. program becomes stuck waiting for a condition that does not occur for example when an unexpected NACK is received The program uses the MSC1211 13 to coordinate data transfers between a real time clock PCF8593 and an I O port PCF85744 to cause its bit 7 to pulse once per second The control byte at address zero within the PCF8593 is repeatedly redefined and while this is not strictly necessary it is convenient in Example 9 1 After writing this byte the internal address is automatically incremented so that it points to the fractions of a second register Example 9 1 MSC1211 as a Master Program RTCIO 02 c MSC1211 to from Philips PCF8593 Real Time Clock at address A2 and PCF8574A 8 bit I O port at address 7E Including synchronisation with SCL include stdio h include REG1211 h PRAGMA NOIP code at OxFFF3 void autobaud void char 1 11 12 13 global Variables void main PDCON Ox5F enable I2C alone autobaud printf I2C RTC to IO n n RI 0 0 USEC x divide by 22 I2CCON 0x04 NACK 0 Normal Master No stretch Not Filtered I2CGM 0x00 single master I2CSTAT 0x6D for 22MHz osc 100 kHz clock while 1 while RI_0 continue until serial character I2CCON 0x80 START while AIE amp 0x04 wait for I2C interrupt flag i I2CSTAT if i 20x08 break handle unexpected condition while SCL wait I2CDATA OxA2 S
53. received data is obtained by reading I2CDATA SPIRCON 9Ch I2CGM 9Ch SPI Receive Control If the SPI is enabled see bit 0 of PDCON at F1h SPIRCON defines and monitors the behaviour of the first in first out SPI receive buffer 12C GM Register If the I2C interface is enabled see bit 5 of PDCON at F1h I2CGM determines if a slave MSC1211 13 should respond to a General Call address or if a master shares a bus with other masters SPITCON 9Dh I2CSTAT 9Dh SPI Transmit Control If the SPI is enabled see bit 0 of PDCON at F1h SPITCON defines and monitors the behavior of the SPI transmit buffer and other transmitter features 12C Status If the 12C Interface is enabled see bit 5 of PDCON at F1h I2CSTAT determines the master clock frequency and also the status of the 12C hardware SPISTART 9Eh I2ZCSTART SPI Buffer Start Address If the SPI is configured to use a circular first in first out buffer SPISTART specifies the start ad dress in the range 80h to FFh that is indirect core SRAM 12C Start If the 12C interface is enabled see bit 5 PDCONat F1h writing to I2CSTART will reset the 12C peripheral to its intitial state SPIEND 9Fh SPI Buffer End Address If the SPI is configured to use a circular first in first out buffer SPIEND specifies the end address in the range 80h to FFh that is indirect core SRAM SPISTART must be less than SPIEND and together define a buffer from SPISTART to SPIEN
54. scale digital output Alternatively the overall system can be placed into a defined zero state and then calibrated for offset CAL 100 followed by a full scale condition and calibrated for gain CAL 101 Each type of calibration takes seven tp ATA peri ods as summarized in Table 6 3 CAL 001 takes 14 tpATA periods For best results calibration should be performed with the Sinc or auto filter selected 32 Bit Summation Register 6 7 32 Bit Summation Register To use the 32 bit summation register either under the control of the CPU and or the ADC bit 3 of PDCON at F1h must be 0 Operations are controlled by SSCON at Eth with data accessed via SUMR3 SUMRO Table 6 7 Summation Register Register Address Read Write Name Hex Summation Register Temporary Register SUMR3 E5 Bits 31 to 24 most significant Bits 31 to 24 most significant SUMR2 E4 Bits 23 to 16 Bits 23 to 16 SUMR1 E3 Bits 15 to 8 Bits 15 to 8 SUMRO E2 Bits 7 to 0 least significant Bits 7 to 0 least significant Table 6 8 SSCON Summation Shift Control SSCON SFR E1h Reset Value 00h Bit Name and Number Action or Interpretation where o Read of Summation Register A Write to Temporary Register B Select CPU summation mode for MSC12x N ojo SSCON1 s e see GGG ser e see SSCNTO SHF1 Clear Summation register A zero 1 Change to summation mode 2 3 0 Next CPU summation on write to SUMRO A A B aly
55. starting at address 0000h Otherwise internal program memory will be accessed where available 46 47 PO 0 PO 7 Port 0 is an 8 bit bidirectional input output port with alternate functions 49 54 PORT 0 x _ Alternate Name Alternate Use P0 0 ADO Address Data bit 0 PO 1 AD1 Address Data bit 1 P0 2 AD2 Address Data bit 2 P0 3 AD3 Address Data bit 3 P0 4 AD4 Address Data bit 4 P0 5 AD5 Address Data bit 5 P0 6 AD6 Address Data bit 6 P0 7 AD7 Address Data bit 7 55 56 P1 0 P1 7 Port 1 is an 8 bit bidirectional input output port with alternate functions 59 64 PORT 1 x Alternate Name Alternate Use P1 0 T2 Address Data bit 0 P1 1 T2EX Address Data bit 1 P1 2 RxD1 Address Data bit 2 P13 TxD1 Address Data bit 3 P1 4 INT2 SS Address Data bit 4 P1 5 INT3 MOSI Address Data bit 5 P1 6 INTA MISO SDA 1 Address Data bit 6 P1 7 INT5 SCL 1 SCK Address Data bit 7 1 SCL and SDA not present on MSC1210 12 14 1 6 MSC121x Pinout 1 2 1 Input Output I O Ports PO P1 P2 and P3 In principle each port consists of eight bits each of which may be placed low high or read by accessing the corresponding bit in the appropriate special function register SFR However when alternate functions are used the port SFRs are not usually accessed Every I O port bit has an optional pull up resistor that is enabled when the bit is in 8051 compatible mode default aft
56. the receiver interrupt flag will be set when ever there is a received byte to read Writing to SPIDATA will clear the transmit interrupt flag if previously set Similarly reading SPIDATA will clear the receive interrupt flag if previously set Because of the bit synchronous nature of the SPI a byte is only received when one is transmitted Consequently if a master expects a reply that is dependent upon the byte it sent to a slave it must ignore the first byte returned and transmit dummy bytes to receive subsequent reply bytes Table 10 5 SPI Interrupts Have Highest Priority and Jump to Address 0033h Bit Name Abbreviation Name of Related SFR Abbreviation Address Enable Auxiliary Interrupt EAI Enable Interrupt Control EICON 5 D8h Auxiliary Interrupt Flag Al Enable Interrupt Control EICON 4 D8h Enable SPI Transmit interrupt ESPIT Auxiliary Interrupt Enable AIE 3 A6h SPIT AISTAT 3 A7h SPI Transmit Interrupt Status Flag Auxiliary Interrupt Status Register ESPIT AIPOL 3 A4h Enable SPI Receive Interrupt ESPIR Auxiliary Interrupt Enable AIE 2 A6h SPIR AISTAT 2 A7h SPI Receiver Interrupt Status Flag Auxiliary Interrupt Status Register ESPIR AIPOL 2 A4h Table 10 6 PAl Pending Auxiliary Interrupt Register SFR A5h Reset Value 00h Interpretation When Read Return 0 01 01 01 01 Auxiliary Interrupt Status 0000 No Pending Auxiliary IRQ 0001 Digital Low Voltage or Hardware Breakpoint IRQ Pending 00
57. unexpected condition STOP request wait for stop to occur START request wait for I2C interrupt flag handle unexpected condition wait slave address with read bit wait for I2C interrupt flag handle unexpected condition with ACK read byte to trigger data transfer wait for I2C interrupt flag handle unexpected condition read fractions of seconds wait for I2C interrupt flag handle unexpected condition with NACK read seconds wait for I2C interrupt flag handle unexpected condition read minutes STOP request wait for stop to occur START wait for I2C interrupt flag handle unexpected condition wait slave address with write bit wait for I2C interrupt flag handle unexpected condition value for P8547 wait for I2C interrupt flag handle unexpected condition STOP request wait for stop to occur flag valid termination printf unexpected condition 4d to be handled n i break RIO 0 while RI 0 RIO 0 while 1 9 12 wait for character endless loop I2C Example MSC1211 13 as a Slave 9 8 12C Example MSC1211 13 as a Slave When operating as a slave data may be received transmitted or both In Example 9 2 two bytes are received from a master and their AND and OR are sent back To simulate the time taken for additional computations encoun tered in most real
58. 00 cece eee eee eee 13 4 13 3 EWU Enable Wake Up 00 cee 13 9 Examples 2 1 INSWUCHONS 3 iiec ena pip adie hie Reda ei eee eae esa eee 2 6 3 1 Assembly Code and C Code 0 cece nett t eens 3 3 4 1 lntr ction Types ic ci eee cs eee eee id bead oe eae eee ee PER NE eee 4 4 4 2 Instruction Addressing Modes 0 cece eects 4 4 4 3 Assembler Code srr er 0cbocseeteeeadasrdeeeaeesbaddessg de bag daas da ae Aa 4 12 5 1 Watchdog Timer Program 2 cece eet tenes 5 7 6 1 ADC Progra widens idane wii athened pean bd ARIAS dA dA baa P adobe dd uud 6 17 Tale DAG LOSING PEE 7 4 f 2 DAC Program 22 2i 402 tus teen bete dd d ae ie dede aed Maen ees 7 8 8 1 PWM Generator o osais an Eeen ovale Ye E REPRE GC ER REPE UPPPS pg dda takes RE ER 8 4 9 1 MSC1211asaMaster sssssslellseessees eee eens 9 11 9 2 MSC1211 13asaSlave luuuussssellllllle hn 9 13 9 3 MSC1211 13 as an Interrupt Driven Slave 0 00 eects 9 15 10 1 SPI Simple Polled Environment 0 0 ccc ccc net eee eens 10 9 10 2 SPLEIFO MOde iss ee Eae ed aed eem Gade ida pu alee Rd act te 10 10 11 1 Program Using Timers 0 1 and 2 0 0 0 tenes 11 14 12 1 Serial Port with Software Buffer Code 00 ccc eee eee 12 11 13 1 Multiple and Nested Interrupts 0 00 cece 13 6 19 2 Wake Up From idle 5252 ace issis inset whee craw ted etm a bad chee da 13 10 Chapte
59. 000b This means that bits within 16 of the 128 possible SFRs may be manipulated by the bit addressing instructions Only RO or R1 may be used as 8 bit indirect pointers to on chip SRAM between 00h and FFh MSC121x Addressable Resources Beyond 64 KBytes Example 2 1 Instructions Instruction Condition or Comment Net Effect on SRAM or SFR Location MOV R1 4AH Register bank 1 is active Contents of RAM at 4Ah is copied to RAM at 09h MOV R1 F4H Register bank 2 is active and RAM at address Immediate code data of F4h is copied to RAM at 11h contains 8Ah 8Ah SETB sync sync 5Eh Bit 6 of RAM at 2Bh is set PUSH 34H Stack Pointer SP is 9Bh but is pre incremented Contents of RAM at 34h is copied to RAM at 9Ch to 9Ch POP PO PO 80h which is the SFR for physical Port 0 Contents of RAM at 80h is copied to the SFR at Stack Pointer SP is 80h and is post decrem 80h ented to 7Fh INC P1 P1 90h which is the SFR for physical Port 1 SFR at 90h is incremented DEC R6 Register bank 0 is active Contents of RAM at 06h is decremented CLC C C carry bit 7 of the Program Status Word at Bit 7 of SFR at DOh is cleared DOh MUL AB Accumulator 12h Register B 3Bh The accumulator SFR at EOh becomes the low part of the product 26h and reg B SFR at FOh becomes the high part 04h CPL TF1 TF1 8Fh the bit address of timer 1 overflow flag Complement bit 7 of SFR TCON at 88h CLCA The accumu
60. 005 Analog To Digital Converters 6 9 ADC Data Rate Filters and Calibration When the voltage presented to the ADC changes the time it takes to receive valid data depends upon the type of filter that is selected as well as the conver Sion time tp ATA Higher order filters provide better noise immunity but take lon ger to settle and the user must make considered judgments as to system per formance based on resolution settling time and notch frequency In Auto mode the type of filter that is used changes whenever the input multi plexer ADMUX or PGA are altered The ADC first makes two conversions us ing the Fast filter then one with Sinc and then one with Sinc3 In the graphs shown in Figure 6 4 fpata Data Output Rate 1 tpATA The ADC performs conversions at a regular rate of fpata as shown in the fol lowing equation f fox DATA 164 x ACLK 1 x Decimation Ratio Figure 6 4 Filter Frequency Responses SINC FILTER RESPONSE SINC FILTER RESPONSE 3dB 0 262 foara 3dB 0 318 fpara 60 Gain dB Gain dB 80 100 120 FAST SETTLING FILTER RESPONSE 30B 0 469 e foara Gain dB DATA NOTE fpata Data Output Rate 1 tpata 6 10 ADC Data Rate Filters and Calibration In applications where more than one analog input is measured the program should write different values to A
61. 1 Via instructions with an 8 bit direct address between 80h and FFh For ex ample CLR 80H clears all bits in port 0 to 0 Bit addressing instructions with bits in the range 80h and FFh For exam ple SETB 0A9H enables interrupts from Timer 0 By instructions with implicit access For example PUSH 13H increments the Stack Pointer at SFR address 81h before using it as a pointer to save the contents of Register 3 in bank 2 The 8 bit addresses of all SFRs are shown in Table 3 1 with respect to a base group at addresses of the form 1xxxx000b The SFRs in this group are byte and bit addressable and shaded in the table Reading an unassigned SFR will give 00h while any values written will be ig nored All SFRs are read and written by the processor one byte at a time even when they are part of a multi byte value Table 3 1 Special Function Register Map 1 2 F8 SECINT MSINT USEC MSECL MSECH HMSEC WDTCON FO PDCON PASEL ACLK SRST E8 HWPCO HWPC1 HDWVER Reserved Reserved FMCON FTCON EO SSCON SUMRO SUMR1 SUMR2 SUMR3 ODAC LVDCON D8 ADRESL ADRESM ADRESH ADCONO ADCON1 ADCON2 ADCON3 DO OCL OCM OCH GCL GCM GCH ADMUX C8 RCAP2L RCAP2H TL2 TH2 Co SBUF1 EWU SYSCLK 3 B8 BO P2DDRL P2DDRH P3DDRL P3DDRH DACL 3 DACH 3 bDaAcsEL 3 A8 BPCON BPL BPH PODDRL PODDRH P1DDRL P1DDRH AO PWMCON bate SER AIPOL 3 PAI AIE AISTAT 98 SBUFO isccont wecDATAC ecam icstar wcstanrt
62. 10 Analog Low Voltage IRQ Pending 0011 SPI Receive IRQ Pending or I2C Status Interrupt Pending 00 SPI Transmit IRQ Pending 01 One Millisecond System Timer IRQ Pending 10 Analog to Digital Conversion IRQ Pending 11 Accumulator IRQ Pending 1000 One Second System Timer IRQ Pending Serial Peripheral Interface SPIt 10 5 SPI FIFO Buffer 10 4 SPI FIFO Buffer If the FIFO buffer is to be used its start and end addresses in core SRAM must be defined by writing to SPISTART at 9Eh and SPIEND at 9Fh respectively The SRAM between SPISTART and SPIEND inclusive should not be used by the application software The activity of the FIFO buffer is controlled by four pointers and two counters Once initialized by writing to either SPICON or SPISTART all pointers equal SPISTART and both counters are 0 Both SPISTART and SPIEND must be a location within SRAM between 80h and FER If a pointer to be incremented is equal to SPIEND it will instead be set to SPISTART The registers are changed as follows 1 The CPU writes data to SPIDATA which is copied to SRAM pointed to by CPUtxp CPUtxp is then incremented along with TXcount The CPU may write further bytes to SPIDATA during the following steps 2 Txcount is no longer 0 and the byte pointed to by SPItxp is copied to TX BUF and on to the transmission shift register TX SR SPltxp is increm ented and TXcount is decremented 3 The synchronous nature of the SPI means that transmission of
63. 11 12 13 14 5 2 System Clock Divider MSC1211 12 13 14 In order to reduce the average operating power of the microcontroller a pro grammable system divider may lower the frequency of the internal clocks Table 5 1 SYSCLK System Clock Divider Register SYSCLK SFR C7h Reset Value 00h Bit Name Action or Interpretation 7 6 0 Always 0 5 4 DIVMOD Clock Divide Mode Write 00 Normal mode default no divide 01 Immediate mode start divide immediately return to Normal mode on an IDLE wakeup condition or direct write to SFR 10 Delay mode same as Immediate mode except that the mode changes with the millisecond interrupt MSINT If MSINT is enable the divide will start on the next MSINT and return to normal mode on the following MSINT If MSINT is not enabled the divide will start on the next MSINT condition even if masked but will not leave the divide mode until the MSINT counter overflows which follows a wakeup condition 11 Medium mode same as Immediate mode but cannot return to Normal mode on IDLE wakeup condition Must write directly to SFR Read Status 00 No divide 01 Divider is in Immediate mode 10 Divider is in Delay mode 11 Medium mode 3 0 Always 0 2 0 DIV Divide Mode fci fosc Divisor 000 divide by 2 default 001 divide by 4 010 divide by 8 011 divide by 16 100 divide by 32 101 divide by 1024 110 divide by 2048 111 divide by 4096 System Clocks Timers and Funct
64. 3 5 Example of Multiple and Nested Interrupts 13 5 Example of Multiple and Nested Interrupts The example shows interrupt service routines for interrupts of low high and highest priority Based on a clock of 11 0592MHz the program does the follow ing 1 Toggles signal sync3 P1 3 as frequently as possible subject to servicing interrupts Assuming the main program is implemented as the instruction CPL P1 3 sync3 will toggle every 0 723us 2 Transmits a digit between 0 and 3 at 9600 baud on serial port 0 every 20ms as triggered by the milliseconds system timer 3 Uses the interrupt from Timer 0 to toggle syncO P1 0 every 278ms 4 Uses the interrupt from Timer 2 to toggle sync2 P1 2 every 10ms 5 Receives characters from serial port 0 via an interrupt and toggles sync1 P1 1 6 Shows the level of interrupt nesting by the value of the digit transmitted If the time to execute the ISR associated with Timer 0 is short then most inter rupts will occur with respect to the main program However every application with multiple interrupts should cater to the least likely combination of events In this case it is possible that the main program is interrupted by an overflow from either Timer 0 or Timer 2 which is then interrupted due to a character re ceived on serial port 0 which itself is interrupted by the milliseconds timer The variable called evel will then be 3 and cause a 3 to be transmitted because the Msecl
65. A5 Reserved 1 Flags CY AC and OV may also be changed by explicit writes to corresponding bits in the PSW No operation 2 Number of cycles is user selectable See SFR CKCON at 8Eh Programmer s Model and Instruction Set 4 9 MSC121x Op Code Table 4 4 MSC121x Op Code Table Table 4 4 MSC121x Op Codes Table Cell Contents opcode bytes cycles instruction operand s Operand Definitions addr11 11 bit address addr16 16 bit address bit addressable bit dir direct address 3138 8 bit immediate data d16 16 bit immediate data rel8 8 bit relative address 00 1 2 3 2 2 06 1 1 07 1 1 NOP AJMP LJMP INC INC INC addr11 addr16 dir RO R1 10 3 4 2 3 12 3 4 2 2 16 1 1 17 14 JBC ACALL LCALL DEC DEC DEC bit rel8 addr11 addr16 dir RO R1 20 3 4 2 3 22 1 4 25 2 2 26 1 1 27 1 1 JB AJMP RET ADD ADD ADD bit rel8 addr11 A dir A RO A R1 30 3 4 2 3 35 2 2 36 1 1 37 14 JNB ACALL ADDC ADDC ADDC bit rel8 addr11 A dir A RO A R1 40 2 3 2 3 2 2 46 1 1 47 14 JC AJMP ORL ORL ORL ORL rel8 addr11 dir d8 A dir A RO A R1 50 2 3 2 3 53 3 3 2 2 56 1 1 57 1 1 JNC ACALL ANL ANL ANL ANL rel8 addr11 dir d8 A dir A RO A R1 60 2 3 2 3 63 3 3 2 2 66 1 1 67 1 1 JZ AJMP XRL XRL XRL XRL rel8 addr11 dir d8 A dir A RO A R1 70 2 3 2 3 73 1 3 75 3 3 76 2 2 77 2 2 JNZ ACALL JMP MOV MOV MOV rel8 addr11 A DPTR dir d8 RO
66. ADD A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 38 1 1 39 1 1 3A 1 1 3B 1 1 3C 1 1 3D 1 1 3E 1 1 3F 1 ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 48 14 1 1 4A 14 4B 1 1 4C 14 4D 1 1 4E 14 4F 1 1 ORL ORL ORL ORL ORL ORL ORL ORL A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 58 1 1 1 1 5A 1 1 5B 1 1 5C 1 1 5D 1 1 5E 1 1 5F 1 ANL ANL ANL ANL ANL ANL ANL ANL A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 68 1 1 1 1 6A 1 1 6B 1 1 6C 14 6D 14 6E 14 6F 1 XRL XRL XRL XRL XRL XRL XRL XRL A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 78 2 2 79 2 2 7A 2 2 7B 2 2 7C 2 2 7D 2 2 7E 2 2 7F 2 2 MOV MOV MOV MOV MOV MOV MOV MOV RO d8 R1 d8 R2 d8 R3 d8 R4 d8 R5 d8 R6 d8 R7 d8 88 2 2 89 2 2 8A 2 2 8B 2 2 8C 2 2 8D 2 2 8E 2 2 8F 2 2 MOV MOV MOV MOV MOV MOV MOV MOV dir RO dir R1 dir R2 dir R3 dir R4 dir R5 dir R6 dir R7 98 1 1 99 1 1 9A 1 1 9B 1 1 9C 14 9D 14 9D 1 1 9F 1 SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 A8 2 2 A9 2 2 AA 2 2 AB 2 2 AC 2 2 AD 2 2 AE 2 2 AF 2 2 MOV MOV MOV MOV MOV MOV MOV MOV RO dir R1 dir R2 dir R3 dir R4 dir R5 dir R6 dir R7 dir B8 3 4 B9 3 4 BA 3 4 BB 3 4 BC 3 4 BD 3 4 BE 3 4 BF 3 4 CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE RO d8 rel8 R1 d8 rel8 R2 d8 rel8 R3 d8 rel8 R4 d8 rel8 R5 d8 rel8 R6 d8 rel8 R7 d8 rel8 C8 1 1 C9 1 1 CA 1 1 CB 14 CC 11
67. CCLK MODCLK P3 3 INT1 TONE PWM 6 43 P2 7 A15 P3 4 T0 7 42 DVpp P3 5 T1 8 MSC121x 41 DGND P3 6 WR 9 40 P2 6 A14 P3 7 RD 10 39 P2 5 A13 DVpp 11 38 P2 4 A12 DGND 12 37 P2 3 A11 RST 13 36 P2 2 A10 DVpp 14 35 P2 1 A09 DVpp 15 34 P2 0 A08 RDACO or NC 16 33 NC s o N o N N N N N A N a N o N N N N o o wo N VDACO or AGND IDACO AINO IDAC1 AIN1 9 VDAC2 AIN2 VDAC3 AIN3 AIN4 AIN5 AING EXTD AIN7 EXTA AINCOM AGND AVpp REF IN REFOUT REF IN VDAC1 or REFOUT RDAC1 or NC NOTES Non bolded pin names are on MSC1210 1 SCL and SDA not present on MSC1210 12 14 2 Pins 16 and 32 are not connected NC on MSC1210 3 AGND for MSC1210 VDACO for MSC1211 12 13 14 4 IDACO and IDAC1 on MSC1211 12 13 14 5 VDAC2 and VDAC3 on MSC1211 12 6 For MSC1210 REFOUT is on pin31 For MSC1211 12 13 14 REFOUT is shared with REF IN on pin 30 and VDAC1 is on pin 31 1 4 Table 1 2 MSC121x Pin Descriptions MSC121x Pinout Pin Name Description 1 XOUT The output of an oscillator that supports parallel resonant AT cut crystals and ceramic resonators 2 XIN The input to the crystal oscillator that can also be used as an an external clock input 3 10 P3 0 P3 7 Port 3 is an 8 bit bidirectional Input Output port with alternate functions PORT 3 x Alt
68. CON at 88h configure the operation of Timer Count er 0 and Timer Counter 1 They have identical relative behavior in modes 0 1 and 2 but differ in mode 3 as expressed in the following tables and figures Table 11 1 TMOD Timer Mode Control TMOD SFR 89h Reset Value 00h Bit Name Action or Interpretation Timer Counter 1 Gate Control Write 0 Operation of Timer Counter 1 does not depend upon pin P3 3 INT1 1 Pin P3 3 INT1 has to be 1 to enable clocking See TR1 bit 6 of TCON at 88h Timer Counter 1 Select Write 0 Timer Counter is clocked at fc K 12 default or fo 4 See CKCON 4 at 8Eh 1 Timer Counter is clocked from pin P3 5 T1 See also TR1 bit 6 of TCON at 88h Timer Counter 1 Mode Select 00 Mode 0 13 bit counter 01 Mode 1 16 bit counter 10 Mode 2 8 bit counter with auto reload 11 Mode 3 Timer Counter 1 is halted but holds its count Same effect as clearing TR1 Timer Counter 0 Gate Control Write 0 Operation of Timer 1 does not depend upon pin P3 2 INTO 1 Pin P3 2 INTO has to be 1 to enable clocking See TRO bit 4 of TCON at 88h Timer Counter 0 Select Write 0 Timer Counter is clocked at fc K 12 default or fo 4 See CKCON 3 at 8Eh 1 Timer Counter is clocked from pin P3 4 TO See TRO bit 4 of TCON at 88h Timer Counter 0 Mode Select 00 Mode 0 13 bit counter 01 Mode 1 16 bit counter 10 Mode 2 8 bit counter with
69. Communications 12 8 Multiprocessor Communications For serial ports operating in modes 2 or 3 with control bit SM2 1 the RI flag will only be set if the ninth bit of a received data field is 1 In this way a byte may cause an interrupt only when the ninth data bit is 1 In a multiprocessor system when a master chooses to send a block of data to one of several slaves it first transmits an address with the ninth data bit from SCON 3 at 1 Assuming all slaves initially have SM2 set then each will be interrupted because RI is set but only the one matching the address will change its SM2 bit to 0 Thereafter data bytes with the ninth data bit at O will be ignored by unaddressed slaves but cause an interrupt in the addressed slave 12 9 Example Program In Example 12 1 the program has both serial ports operating in mode 1 where asynchronous 8 bit data is preceded by a start bit and succeeded by a stop bit Since both ports have SM2 1 SCONx 5 1 the RI flags are set only if a valid stop bit is received Serial port 0 is configured to receive and transmit characters at 9600 baud us ing Timer Counter 2 whereas serial port 1 has a non standard rate of approxi mately 21 baud using Timer1 Characters received on serial port 0 are buffered in software and presented for transmission via serial port 1 It is assumed that serial port 1 transmitter is looped back to serial port 1 receiver Characters re ceived at serial port 1 are copied
70. D inclusive P2 AO0h Port 2 Controls the byte wide bit programmable input output called Port 2 Each bit in the SFR corre sponds to a pin on the actual part Individual bits may be configured as bidirectional CMOS out put open drain output or input via the Data Direction SFRs for Port 2 See P2DDRL at B1h and PODDRH at B2h The same device pins may also be used to provide the high order address for access to off chip memory In this case EGP23 bit 1 of HCR1 must be 0 and the program should not reference P2 Special Functions Registers 3 7 SFR Overview Table 3 2 SFR Overview continued Address Name Hex Description PWMCON Ath PWM Control Configures the pulse width modulated signal generator The PWM subsystem is enabled by bit 4 of PDCON at F1h PWMLOW A2h PWM Low least significant TONELOW h Tone Low PWMHI A3h PWM High most significant TONEHI AaS Tone High PWMHI PWMLOW or TONEHI TONELOW represents a 16 bit value for a dedicated counter that is used by the PWM subsystem AIPOL A4h Auxiliary Interrupt Poll Configures the read operation for AIE and AIPOL AIE register content or interrupt before masking PAI A5h Pending Auxiliary Interrupt Provides a 4 bit number that corresponds with the hardware priority of the highest pending auxil iary interrupt All auxiliary interrupts transfer control to location 0033h AIE A6h Auxiliary Interrupt Enable Bits written determi
71. DAC buffers are reloaded as required before the corresponding timer tick Note that an interrupt service routine may be associ ated with MSEC but not directly with HMSEC For applications where multiple DACs must be updated synchronously under direct program control mode 119 is provided Once this mode is established values written to the data registers are transferred to the output registers when mode 112 is rewritten to the control bits Given that the settling time of the DACs is approximately 8us it is possible for all four DACs to be updated by software within this time scale using mode 0 and cause them to apparently change together However in general this will only be true for environments without interrupts Care should be taken when using load mode 002 with what appears to be sequential updates of different DACs In terms of program flow they may appear adjacent but interrupt activi ty will cause them to be separated in time DAC Configuration and Control 7 3 DAC Configuration and Control Each DAC has a corresponding control register DACxCON x 0 to 3 which is used to configure its mode of operation as summarized in Table 7 4 Table 7 4 DAC Control Registers DACSEL Reset SFRx DAC Value sel 04h CORO EODO IDACODIS SELREFO 63h SFR B5h sel 04h COR1 EOD1 IDAC1DIS SELREF1 B L 63h SFR B6h sel 05h SELREF2 B 03h SFR B5h d ELREF h SFR B6h S 3 0 03 where Bit Name Meani
72. DACSEL 4 DACL 0x24 DACO IDAC off Ref REFOUT REFIN DACH 0x24 DAC1 IDAC off Ref REFOUT REFIN DACSEL 5 DACL 0x24 DAC2 Ref REFOUT REFIN DACH 0x24 DAC3 Ref REFOUT REFIN while 1 DACSEL 0 DAC 0x8000 1 25 V pulse on DACO for j 0 j 100 j delay DAC 0 Synchronize scope to negative edge for i 0 i lt 251 i 10 DACSEL 1 DAC 250 i Linear DAC1 DACSEL 2 DAC i i Square DAC2 DACSEL 3 j 40 i j j 252 DAC j j j Cube DAC3 DACSEL 6 DACL OxFC load DACs 3 2 1 simultaneously 7 8 Chapter 8 Pulse Width Modulator and Tone Generator This chapter describes the pulse width modulator PWM and tone generator of the MSC121x Topic Page 8 1 Description we cis acs 69er ete nnnm n sieur eun eel ayn staples 8 2 EIEE ENE EEE EAEE S SENEE AES EOE GUERE 8 4 8 2 PWM Generator Example 8 1 Description 8 1 Description The PWM subsystem consists of the following components 6 bit control register PWMCON 16 bit Period register P and 16 bit Duty register D which share the same SFR addresses LJ 16 bit down counter 16 bit comparator and a finite state machine J A single output pin shared with bit 3 of Port 3 The PWM subsystem is enabled by 1 making bit 4 of PDCON at F1h equal to 0 2 making bit 3 of P3 equal to 1 3 configuring bit 3 of Port 3 to be a standard 8051 port or open drain This is achieved by writing 005 or 105 re
73. DACxH DACxL16 bit data buffer which will be transferred to 01 the DAC output register on the next tick of the MSEC system timer register See SFRs FDh and FCh Delayed load Values are written to the DACxH DACxL16 bit data buffer which will be transferred to 10 the DAC output register on the next tick of the HMSEC system timer register See SFR FEh Synchronized load 11 Values are written to the DACxH DACxL16 bit data buffer which will be transferred to the DAC output register when 119 is re written to these bits Digital To Analog Converters 7 3 DAC Selection Direct load mode 002 provides a simple means of updating DACs in an arbi trary order and at various times according to the flow of the user s program For a particular DAC it is essential that DACH is written before DACL The code sequence to write C147h to DAC2 in mode 00 is shown in Example 7 1 Example 7 1 DAC Loading 74 C Assembler DACSEL 0x06 MOV DACSEL 6 DACL 0x00 MOV DACL 0 DACSEL 0x02 MOV DACSEL 2 DACH OxC1 MOV DACH 0C1H DACL 0x47 MOV DACL 47H or DAC OxC147 not MOV DACL 47H MOV DACH 0C1H In cases where synchronization is essential three methods are provided Delayed modes 019 and 102 assume that all DACs will be updated at regular intervals as determined by the milliseconds timer MSEC or the hundreds of milliseconds timer HMSEC respectively In either of these modes the pro gram should ensure that all
74. DMUX in a way that is synchronized with con versions to get the best throughput rate Ideally ADMUX should be updated as soon as the ADC interrupt flag is set but there will always be a software delay Assuming the delay is less than 20 x top and the decimation ratio is large over 1000 any error introduced is less than intrinsic noise The 24 bit result is held in the logically concatenated registers ADRESH high ADRESM and ADRESL low at SFR addresses DBh DAh and D9h respectively These registers are loaded when a conversion is completed as long as ADRESL has been read since the last value was written In devices that have the AIPOL register reading AIE may return the mask bits that were previously written Therefore these devices support read modify write instructions such as ORL AIE 020H to enable the ADC interrupt and ANL AIE 0BFH to disable the summation interrupt However this must not be attempted with other devices where reading AIE returns the value of the in terrupt flags before masking To allow dynamic modification of interrupt enable bits on these parts the programmer should first manipulate a byte in memory with read modify write instructions and then copy it to AIE If the memory byte is updated by a sequence of instructions in general they should be protected from interrupts Table 6 6 ADC Interrupt Controls Family Bit 5 of AIE at A6h Enable Bit 5 of AISTAT at A7h Bit 5 of AIPOL at A4h ADC Part ADC Inter
75. Description Complementing the high resolution ADC is a precision voltage reference pro grammable gain amplifier PGA and analog multiplexer mux as well as a temperature sensor and low voltage detectors Apart from numerous bit wise programmable digital ports there are two USARTS three timer counters a watchdog timer and a serial SPI bus Up to 32k of FLASH memory and 1 2K RAM are included as well The MSC1211 13 also support 12C serial transfers Taken together the MSC121x features blend analog and digital functions to significantly simplify the overall system design which reduces the design time and board space as well as the need for external components For systems requiring additional memory address and data lines are provided via multifunction I O ports This document applies to the following MSC devices MSC1210 MSC1211 MSC1212 MSC1213 MSC1214 O C O C O For convenience the abbreviation MSC121x is used to indicate all of the MSC devices listed in this user s guide unless otherwise specified Table 1 1 compares the basic features and functionality of the MSC121x family Table 1 1 MSC121x Product Family Matrix MSC1210 MSC1211 MSC1212 MSC1213 MSC1214 Clock Frequency kB 33 33 33 33 Flash Memory kB 32 32 32 32 SRAM kB 1 2 1 2 1 2 1 2 ADC Channel x Resolution ice oe oe one DAC Quad Quad Dual Dual Channel x Resolution N A Voltage Dual Voltage Dual Voltage Dual Voltage Du
76. Generator Example 8 2 PWM Generator Example Example 8 1 shows how the generator can be configured in PWM square or staircase modes It also indicates how to use the system timers to produce an interrupt every second Once a particular mode is selected after reset it should not be changed until after another reset However any mode may be disabled and then restored Example 8 1 PWM Generator File TONE4 c Testing Tone generator MSC1211 EVM Switches 1 0n SW3 12345678 SW5 12345678 0 Off IXITOLITI 11110000 include lt Reg1211 h gt include lt stdio h gt define xtal 22118400 define divA xtal 440 Concert pitch A sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM data unsigned char i tout typedef enum null code at OxFFF3 void pwm square staircase pwmtype autobaud void Auxiliary Interrupt void AuxInt void interrupt 6 using 1 char temp YellowLed YellowLed if tout tout temp SECINT EICON amp 0x10 remove seconds interrupt flag remove AI flag void beep unsigned int divisor unsigned char time pwmtype type PWMCON amp 0x37 TONE divisor switch type POL 0 PWMSEL 0 disable Period register case null break case pwm PWMCON 0x10 Duty register TONE 9 unsigned long divisor 10 PWMCON 1 break case square 8 4 pwm PWM Generator Example
77. INTO 1 sync2 0 PCON 1 IDLE sync2 1 for j 0 3 lt 30 j syncO sync0 If an external interrupt is configured for falling edge detection the IDLE bit must be set when the input is high Similarly for rising edge detection IDLE must be set when the input is low 13 10
78. M ACLK 35 22 1184MHz 35 1 0 6144MHz for MSC1211EVM DECIMATION 1920 gt 200ms per conversion ODAC 0 offset DAC is zero after RESET ADCONO 0500100000 BOD off Vref on 1 25V Buff off PGA 1 ADCONO 0x20 BOD off Vref on 1 25V Buff off PGA 1 autobaud printf MSC121x Random bit generator with polled ADCWMn printf Readings begin in 14 3 200ms 3 4 seconds Mn ADMUX Oxff Select Temperature diodes ADCON1 0x01 bipolar auto mode self calibration offset and gain Analog To Digital Converters 6 17 ADC Example Program Example 6 1 Continued for j 0 j lt 3 j while AIE amp 0x020 reading bipolar RI_0 0 while AIE I while 1 amp 0x20 while RI O if AIE amp 0x20 reading bipolar y reading 692199 2534 1 y reading 700875 2567 1 y reading 704509 2595 1 iy y 0 5 if iy gt 0 amp amp iy 50 temp iy if count gt temp printf ns3d temp YellowLed RedLed count 0 n r amp mask j 0 while n n amp n 1 j r r r j amp 1 if r amp 1 else count RI_O 0 while RI_0 RIO 0 6 18 putchar printfi wait for character continue discard 3 conversions after calibration Clear rec
79. M 0x00 General Call Ignored I2CSTAT OxF4 Master sees slave at E8 AIE 0x04 I2C Status Interrupt Enable AI 0 ensure auxiliary interrupt flag is clear EAI m enable auxiliary interrupts while 1 while RI O0 continue until serial character putchar a a foreground task putchar SBUF RI_0 0 while RI 0 RIO 0 wait for character 9 16 12c Synchronization and Arbitration 9 10 I2C Synchronization and Arbitration Byte level synchronization is achieved when an MSC1211 13 acting as a slave holds SCL low after the ninth bit of any byte transferred However bit level synchronization is also supported when an MSC1211 13 is configured as a master and a slave pulls SCL low after each bit In effect it will pause if it senses a low level on SCL when it should be high More generally the SCL clock has a low period determined by the device with the longest clock low peri od and a high period determined by the device with the shortest high period In a system with multiple masters there is a chance that two or more masters will attempt to place data on SDA at the same time When one master attempts to transmit a high level while another is already transmitting a low level it will disable its output stage and relinquish control of SDA The 12C Status Code of the losing master shows loss of arbitration while the winning master is left to control the bus and pass error free data
80. MSC121x Precision ADC and DACs with 8051 Microcontroller and Flash Memory User s Guide April 2005 Data Acquisition Products SBAU101 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent rig
81. Rs associated with the MSC1211 13 12C interface These SFRs are I2CCON at 9Ah provides primary control I2CDATA at 9Bh provides data I2CGCM at 9Ch provides additional control I2CSTAT at 9Dh provides status The I2C Control register I2CCON is described in Table 9 2 All 12C bytes are written to or read from I2CDATA When the byte written repre sents an 12C slave address between 0001000 and 11110115 bit 0 is the RAW flag such that R W 1 for read and R W 0 for write see Table 9 3 Bit 7 of IPCGM at 9Ch is used to control the behavior of a slave to the General Call address or to allow multiple masters see Table 9 4 Table 9 2 2CCON I7C Control Register I2CCON SFR 9Ah Reset Value 00h Bit Name Action or Interpretation 7 START Read Current status of START condition or repeated START condition Write valig only i 0 No action Metus 1 Transmit a START condition If the bus is not free a START condition will be transmitted after a STOP condition has been received If the START bit is set after at least one byte has been transmitted a repeated START condition is transmitted after the current data transfer is completed If both START and STOP are set while the bus is free a START condition will be fol lowed by a STOP condition 6 STOP Read Current status of STOP condition lid only if Write very 0 No action MSTR 1 1 Transmit a STOP condition If both START and STOP are s
82. Rx will change to 1 and the DAC outputs current and voltage will be disabled until released by writing a 0 to CORx IDACxDIS and DOMXx bits are not altered by the over current protection mech anism If EODx is 0 and depending upon the specific application the program should poll the CORx bit to confirm that an over current condition does not exist DAC Technology and Limitations 7 4 DAC Technology and Limitations The DACs in the MSC1211 are based upon the 16 bit DAC type DAC8531 also manufactured by Texas Instruments Consequently all DACs use a string of tapped resistors to establish a scale of voltages that are ensured to be monotonic which is essential for many closed loop control systems This is effectively 65 536 resistors that can be tapped for voltages from AGND to the DAC reference voltage The output amplifiers for the DACs cannot reach OV and must have at least 1 5V of operating headroom that is to say AVpp should be 1 5V above the maximum voltage output by a DAC Due to the former constraint DAC codes below about 0x0200 are not recommended and are precluded from linearity calculations used in the preparation of electrical characteristics as found in product datasheets Increased nonlinearity may also be seen for near full scale codes when the headroom constraint is not satisfied For example when a DAC uses the on chip 2 5V reference and AVpp is less than 4 0V The linearity of the DAC can be improved with the t
83. Write 0 Buffer disabled default 1 Buffer enabled results in increased power and impedance but reduced range 2 0 6 6 Programmable Gain Amplifier Write 000 to 111 Gives a gain G 2PGA or 1 default to 128 Input Impedance PGA and Voltage References Bits of ADCONO determine various parameters according to Table 6 4 By default the internal voltage reference is turned on at 2 5V when the ADC subsystem is powered up Therefore if an external reference is provided the internal reference should be disabled via EVREF before bit 3 of PDCON at F1h is cleared If the internal voltage reference is to be used the default level of 2 5V is al lowed only if AVpp is between 3 3V and 5 25V The internal 1 25V Vggr can be used over the entire analog supply range AVpp 2 7V to 5 25V When the internal voltage reference is disabled an external differential refer ence is represented by the voltage between REF IN and REF IN This per mits ratiometric measurements but the absolute voltage on either input must be from AGND to AVpp In both cases the REF IN pin should have a 0 1uF capacitor to AGND Table 6 4 ADCONO Bit Parameters PGA Effective RMS Resolution Bits Sampling Number of Bits for Vngr 2 5V 2 0 Gain Full Scale Range Frequency at 10Hz Rate nV 000 1 Vper fob 21 7 1468 001 2 Vngp 2 fMOD 21 5 843 010 4 VpREF 4 fMOD 21 4 452 011 8 VREF 8 2 fMOD 31 2 259 100 16 Vng
84. X Baud Rate Generator No 1 11 3 1 16 Bit Timer Counter with Optional Capture o eo ze k a1 a o x lt x Xx To select this mode RCLK TCLK and CP RL2 in T2CON must all be 0 Control bit TR2 is active high and enables either an internal clock or an external clock on pin P1 0 T2 according to the state of C T2 Specifically when C T2 is 0 TH2 TL2 is a gated timer running at either fc 12 default or fci k 4 However when C T2 is 1 it is a gated event counter Figure 11 4 Timer Counter 2 16 Bit with Capture Timer 2 Interrupt EXF2 7 Timer Counter 2 16 Bit with Capture Capture lu 0 C T2 d foil if T2M 1 S Ed rw 1 to 0 1 Pin Edge Pin T2 T2EX Detection TR2 As TH2 TL2 overflows from FFFFh to 0000h the interrupt flag TF2 is set this must be cleared in software If interrupt enables ET2 and EA bits 5 and 7 respectively of IE at A8h are both 1 the CPU jumps to the interrupt service routine at 002Bh Writing a 1 to TF2 causes an interrupt if it is enabled A negative edge on pin P1 1 T2EX when control bit EXEN2 is 1 causes the current value of TH2 TL2 to be copied into capture registers RCAP2H RCAP2L and sets the interrupt flag EXF2 This is ORed with TF2 and may cause a Timer2 interrupt in a manner similar to TF2 EXF2 has to be cleared in software and writing a 1 to it causes an interrupt if it is enabled Time
85. a is either received or transmitted eight bits at a time in a synchronous fashion with respect to a shared input output pin and a common clock output Reception is triggered when REN 1 and RI 0 while transmis sion is triggered by a write to SBUF If SM2 is 0 the clock runs at fci 12 other wise it runs at fci 4 as shown in Figure 12 1 and Figure 12 2 There are no start or stop bits in this mode RI is set three fc cycles after the eighth bit has been received and TI is set three fci cycles after the eighth bit has been transmitted This is true when SM2 0 but the delays change to four fci cycles when SM2 1 Figure 12 1 Synchronous Receive at fc 4 clk mem_ale rxdO in rxdO out txdO TI RF o LLL LL LL LLLLLLLLLLLLLIL AL Al Figure 12 2 Synchronous Transmit at fo 4 clk mem_ale rxdO in BO 7 r oq E ox Egg TI RI Serial Ports USARTO and USART1 12 7 Mode 1 10 Bit Asynchronous 12 6 Mode 1 10 Bit Asynchronous In mode 1 serial data is received or transmitted eight bits at a time in an asyn chronous fashion with respect to independent input and output pins The baud rate is determined by the overflow rate of Timer Counter 1 or 2 for serial port 0 or Timer Counter 1 for serial port 1 Reception of a byte begins when REN is 1 and a start bit is recognized This occ
86. a low level 1 INT1 is sensitive to a negative falling edge Interrupt O edge detect If INTO is edge sensitive because ITO 1 IEO is set when a negative edge is de tected It is cleared when the CPU jumps to the interrupt service routine at 0013h or by writing O in software If ITO 0 IE1 is set when the INTO pin is low and cleared when the INTO pin is high Interrupt O type select Write 0 INTO is sensitive to a low level 1 INTO is sensitive to a negative falling edge NOTE Bit 0 to bit 3 of TCON are not associated with the operation of any Timer Counter Timer Counters 0 and 1 11 2 1 Modes 0 and 1 The description that follows is with respect to Timer Counter 0 but also applies to Timer Counter 1 with appropriate re allocation of control bits However the overflow condition of Timer 1 alone is able to act as a reference clock for the serial ports THO TLO represents a 13 bit negative edge triggered up counter that can be clocked from a variety of sources When C T is 0 it behaves as a gated timer running at either fo 12 default or fc 4 However when C T is 1 it behaves as a gated event counter where appropriate transitions on pin TO TRO GATE or pin INTO cause it to increment In mode 0 the upper three bits of TLO are undefined and should not be used When THO overflows from FFh to 00h the interrupt flag TFO is set It is cleared automatically as the CPU jumps to the service routine
87. al Current x 16 Current x 16 Current x 16 Current x 16 Features 34 I O 34 I O 34 I O 34 I O 34 I O 32 Bit Accumulator Internal VREF Internal PGA Internal Buffer SPI Brownout Reset Low Voltage Detect External Memory External Memory External Memory External Memory External Memory Dual USARTs Dual USARTs Dual USARTs Dual USARTs 2c 2c Serial Parallel Programming Dual USARTs Serial Parallel Programming Serial Parallel Programming Serial Parallel Programming Serial Parallel Programming System Clock Divider System Clock Divider System Clock Divider System Clock Divider Package TQFP 64 TQFP 64 TQFP 64 TQFP 64 TQFP 64 Introduction 1 3 MSC121x Pinout 1 2 MSC121x Pinout The names and functions of pins are similar to those found on most 8051 com patible devices but with extensions that are specific to the MSC121x The pin configuration is shown in Figure 1 2 and the pin descriptions are listed in Table 1 2 Figure 1 2 MSC 121x Pin Configuration g ox x a 9 9 l o o O 2 o 2 2 9 x EEE a G Hw 8a 8 BSB Z Z Z Z cT aQ E E x X X X N 4 N A Z 6 O UYU o F m r gt oO o o o o o o a a a a a a a a a Qa a a Qa a A a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 xout 1 O 48 EA XIN 2 47 P0 6 AD6 P3 0 RXxDO 3 46 P0 7 AD7 P3 1 TxDO 4 45 ALE P3 2 INTO 5 44 PSEN OS
88. al data pointers and executes most instructions up to three times faster than a standard 8051 core This in creased execution speed provides greater flexibility in applications requiring a trade off among speed power and noise For some designers the MSC121x is viewed as a microcontroller with inte grated analog functions while to others it is a high performance analog to dig ital converter ADC with an integrated microcontroller The MSC121x pro vides unparalleled analog and digital integration for all designers concerned with embedded instrumentation and control Figure 1 1 MSC121x Block Diagram IDACO A IDAC1 3 A VDAC2 9 A VDAC3 S A 1 2 pe AGND AVpp REFOUT REF IN REFIN DV DGND V I e H Timers gg Counters 1 ALE p WDT Alternate Functions PORTO a APDR T2 PORTI 81 SPI EXT I2C i USARTI i PORT2 8 ADDR i i USARTO i EXT PORT3 8 TO Ti IDAC1 PWM AIN1 AIN3 lt VDAC3 a RDACO RDAC1 3 VDACO VDAC10 XIN XOUT NOTES 1 On the MSC1210 the REF IN pin 30 and REFOUT pin 31 functions are split onto two pins On the MSC1211 12 13 14 REFOUT and REF IN are combined onto pin 30 and the VDAC1 output is on pin 31 2 REF IN must be tied to AGND when using internal V _ 3 DAC functions are only available on the MSC1211 12 13 14 4 C is available only on the MSC1211 and MSC1213 MSC121x
89. an auxiliary interrupt but a user specific mecha nism must be used to recognize this as a separate source For a particular interrupt flag to be set the corresponding subsystem must be powered up as determined by bits in PDCON at F1h For example PDCON 3 must be 0 for an ADC interrupt to occur Table 13 2 Auxiliary Interrupts with Highest Group Priority Relative Priority Enable ISR Adar Event Fo and Value Cleared By a aa NGC S from PAI DVpp Low Voltage AIE 0 AIE 0 Highest 1 Voltage is restored HW Breakpoint BPCON 7 BPCON O Highest 1 Set BPCON 7 1 AVpp Low Voltage AIE 1 AIE 1 Highest 2 Voltage is restored SPI or I2C Receive AIE 2 AIE 2 Highest 3 Read SPIDATA at 9Bh SPI or 12C Transmit AIE 3 AIE 3 Highest 4 Write SPIDATA at 9Bh Milliseconds Timer AIE 4 AIE 4 Highest 5 Read MSINT at FAh ADC Conversion AIE 5 AIE 5 Highest 6 Read ADRESL at D9h Summation Register AIE 6 AIE 6 Highest 7 Read SUMRO at E2h Seconds timer AIE 7 AIE 7 Highest 8 Read SECINT at F9h 13 4 Multiple Interrupts 13 4 Multiple Interrupts In some applications there may be no interrupts while in others there may be many When there is just one interrupt the service routine is usually relatively easy to write and the model of the timing is simple However with multiple sources of different priorities the complexity in terms of timing and exact be havior grows quickly Since there are three groups of priority
90. applications a delay is introduced to emphasize the effect of a stretched clock when the slave holds SCL low The 12C Status Interrupt flag in AIE is set as a result of the positive edge of SCL during the Acknowledge bit but SCL is not stretched until the negative edge The SCLS bit in I2CCON must be set in order to release the SCL line but this must not occur until the clock is being stretched The C code uses a switch statement to create a multi way branch for each of the expected status codes More efficient code may be created using assem bler language Example 9 2 MSC1211 13 as a Slave Slave04 c I2C master to from slave MSC1211 at address 1110100 Returned data are functions of received data include stdio h include REG1211 h PRAGMA NOIP code at OxFFF3 void autobaud void char i r1 0 r2 0 t1 1 t2 2 global Variables int j void delay void for js0 j 1000 j44 void release void while SCL ensure clock is low I2CCON 0x02 set clock stretch release bit void process data void tl rl amp r2 AND t2 rl x2 OR delay simulate additional processing time void main PDCON Ox5F enable I2C alone autobaud printf MSC1211 as an I2C slave MnMn RI 0 0 USEC 21 divide by 22 I2CCON 0x20 ACK 0 Normal Slave No stretch Not Filtered I2CGM 0x00 General Call Ignored I2CSTAT OxF4 Master sees slave at E8 Inter IC 12Ct S
91. are 0 or EA is 0 when the RST pin is released P3 6 is an active low write strobe and P3 7 an active low read strobe They are CMOS outputs and P3DDRH bits 4 to 7 have no effect DACL B5h Digital to Analog Converter Low least significant byte DACH B6h Digital to Analog Converter High most significant byte DACH DACL represents 16 bit data values for the four DACs present in the MSC1211 These SFRs are redirected to registers associated with each individual DAC using bits within DACSEL at B7h Apart from four 16 bit data registers five different control registers are accessed via DACL DACH in conjunction with DACSEL DACSEL B7h Digital to Analog Converter Select Writes to DACH and DACL are redirected to other data and control registers according to the least significant three bits of DACSEL This indirection increases the number of instructions need ed to set up all the DACs but has the benefit that fewer SFR addresses are needed overall IP B8h Interrupt Priority Bits within IP correspond in position with those enables in IE at A8h Each determines if the cor responding interrupt has a low or high priority using 0 or 1 respectively SCON1 COh Serial Control 1 Contains six bits that determine the format of data on serial port 1 as well as two bits for transmit and receive interrupt flags It is used in conjunction with TCON at 88h TMOD at 89h and various timer data registers Special Functions Regi
92. as a period given by HMSEC 1 x MSECH x 256 MSECL 1 x tCLK When the associated down counter reaches zero it is reloaded with the value in HMSEC WDTCON FFh Watchdog Control Once enabled the watchdog timer expires after a delay of WDCNT 1 x HMSEC to WDCNT 2 x HMSEC Writing a 1 then O sequence to bit 7 bit 6 or bit 5 enables disables or restarts the watchdog timer respectively If the associated down counter reaches zero a watchdog timeout occurs By default this causes a RESET but EWDR bit 3 in HCRO may disable the reset and trigger an interrupt instead During normal operation the counter must be repeatedly restarted before it reaches zero 3 14 Chapter 4 Programmer s Model and Instruction Set This chapter describes the programmer s model and instruction set for the MSC121x Topic Page 41 Introduction cR RII rr oes a 4 2 4 2 Registers 75 99 uei earn essen He RIS a nene EERE ES 4 2 4 3 Instruction Types and Addressing Modes 4 4 4 4 MSC121x Op Code Table seeeeeeee 4 10 4 5 Example of MSC121x Instructions Luuueee 4 12 4 1 Introduction 4 1 Introduction 4 2 Registers The MSC121x incorporates a microcontroller that has the same instruction set as the industry standard 8051 however for a given external clock it executes up to three times more quickly The increased rate is beca
93. auto reload 11 Mode 3 Timer Counter 0 acts as two independent 8 bit Timer Counters Timers and Counters 11 3 Timer Counters 0 and 1 Table 11 2 TCON Timer Counter Control TCON SFR 88h Reset Value 00h Bit 2 Name Action or Interpretation Timer 1 Interrupt Overflow Flag Read 0 No Overflow 1 Timer 1 reached the maximum count and changed to 0 Write 0 Clear flag 1 Set flag and generate interrupt request if unmasked Cleared in software by writing 0 or cleared automatically as the processor jumps to the interrupt service routine at 001Bh Timer 1 Run Control Write 0 Timer 1 cannot be clocked 1 Timer 1 may be clocked Timer 0 Interrupt Overflow Flag Read 0 No Overflow 1 Timer 0 reached maximum count and changed to 0 Write 0 Clear flag 1 Set flag and generate interrupt request if unmasked Cleared in software by writing 0 or cleared automatically as the processor jumps to the interrupt service routine at OOOBh Timer 0 Run Control Write 0 Timer 0 cannot be clocked 1 Timer 0 may be clocked Interrupt 1 Edge Detect If INT1 is edge sensitive because IT1 1 IE1 is set when a negative edge is de tected It is cleared when the CPU jumps to the interrupt service routine at 0013h or by writing O in software If IT1 0 IE1 is set when the INT1 pin is low and cleared when the INT1 pin is high Interrupt 1 type select Write 0 INT1 is sensitive to
94. auxiliary interrupts with highest group priority Global Enable EAI EICON 5 where EICON is at D8h Auxiliary Interrupt Enable AIE is at A6h All these interrupts set the Al flag EICON 4 which must be cleared in software in addition to the individual interrupt flags Setting Al in soft ware generates an auxiliary interrupt if enabled Note that in the first column of Table 13 2 the normal text describes the event while the italic text de scribes how to clear it When multiple auxiliary interrupts are enabled the service routine at 0033h can read the Pending Auxiliary Interrupt PAI at A5h to identify the interrupt of great est relative priority If PAI returns 0 there is no pending auxiliary interrupt Pending active and enabled interrupts can be identified by testing the corre sponding bits in AISTAT at A7h This allows the programmer to service auxilia ry interrupts with arbitrary and even dynamic relative priorities Unlike the Interrupt Enable IE register at A8h which returns the value of en able mask bits when read the Auxiliary Interrupt Enable AIE register re turns the status of interrupt flags before masking This means that read modify write operations on AIE may unintentionally enable interrupts and should not be used Unlike flags in the low and high priority groups no interrupt flag in the highest priority group may be set in software to cause an interrupt However Al El CON 4 can be set to trigger
95. ber MSC1211EVM User s Guide SLAUO86 MSC1210EVM User s Guide MSC1210 DAQ EVM User s Guide For a complete list of application notes and related documentation see the MSC web site at www ti com msc 12C is a trademark of Koninklijke Philips Electronics N V SPI is a trademark of Motorola All other trademarks are the property of their respective owners Contents Iepiferell oiii E D mn 1 1 11 MSC121x Description 22 2 sudra bue sace das ode da uto doner a xod ae 1 2 12 MSCI21x PINOUT i oaa paaa aaa d ga Ebo rU oload dence nsa E ru Rx ARREST EA 1 4 1 2 1 Input Output I O Ports PO P1 P2 and P3 0 cece eee 1 7 1 2 2 Oscillator XOUT pin 1 and XIN pin2 sees 1 10 1 28 Reset Line RST pin 13 0 eee eee 1 10 1 2 4 Address Latch Enable ALE pin 45 0 cece eee eee 1 10 1 2 5 Program Store Enable PSEN pin 44 00 cece cece 1 11 1 2 6 External Access EA pin 48 0 2 c00cccecsceeeeedewstceeeeevens 1 11 1 3 Enhanced 8051 Core 0 cc s 1 12 1 4 Family Compatibility 2 0 0 2 0 0 0 1 13 bo Flash Memory o octets atid teed Rod hie Seti sewteeaega adeta AEA eb eee deeds 1 13 1 6 Internal SRAM sosia pismenu bies enter e CX ieee ag eae ed wate eden 1 13 1 7 High Performance Analog Functions 0 00 e eee e eee eens 1 13 1 8 High Performance Peripherals 00sec eee ete eh 1 14 MSC121x Addressable Resources
96. ble interrupt for Timer 1 IE DATA 0A8H at OxA8 sfr IE ET1 BIT OABH at OxAB sbit ET1 or or ET1 BIT IE 3 sbit ET1 IE 3 SETB ET1 Edi Set the decimation ratio for decimation DATA ODEH at OxDE sfr16 decimation the ADC to 3E8h MOV decimation 0E8H decimation 1000 MOV decimation 1 3 1 Indicating a hexadecimal number in assembly language requires a trailing H and leading 0 if the first character would other wise be a letter for example 99H or 099H but 0A8H instead of A8H 2 In C a hexadecimal number always starts with Ox for example 0x99 and 0xA8 3 The keyword sfr16 cannot be used with THO TLO as TimerO because the addresses are not adjacent This is also true for TH1 TL1 However sfr16 is allowed with TH2 TL2 as Timer2 because TH2 and TL2 are adjacent Special Functions Registers 3 3 SFH Types 3 3 SFH Types The SFRs belong to functional groups that relate to different aspects of the op eration of the MSC121x Port Input Output with bit manipulation _j Interrupts Lj Integrated peripherals for example ADC SPI USARTS or Counter Tim ers 1 System functions for example power down clock generators and break point registers The core processor architecture for example Stack Pointer Accumulator and Program Status Word Extensions to the architecture for example auxiliary data pointer 3 4 SFR Overview Table 3 2 lists the SFRs with addresses and descriptions Underlined SFRs may n
97. bse eer RA REDE eU cide E X aerea RPROSS RUPEE pad 10 5 10 4 SPI FIFO Buiter cceteetemr RR mera ane oe eRe PERE AGREE EA Re wed ees 10 6 10 5 SPI Example6S 22edos ep Re ESRee aed e tees aes ean edead e a aa de A a 10 9 vi Contents 11 Timers and Counters eon url ee ewe da ch n wx Ra emer d fene 11 1 11 1 Description niet aem eed m tun donet daa Le ead E aedes d eres 11 2 11 2 Timer Counters 0 and 1 iuuuiuussssssssssessssssess en 11 3 11 24 Modes 0 and 1 1i iisces dece deecem anew beens Da dew haw caddie Peake ed 11 5 W224 ModE NET 11 6 11 2 3 M dO 9 noie erem i E AEEA A CAP A E ATOA d aE 11 7 11 2 4 Summary of Control Bits and SFRs for Timer Counters 0 and 1 11 7 11 93 imer Co nter 2 665 ideeradhe vateordedavin gach e ik Marc E ey REPE 11 8 11 3 1 16 Bit Timer Counter with Optional Capture 0 00 cece eee 11 9 11 3 2 16 Bit Timer Counter with Automatic and Forced Reload 11 10 11 3 8 Baud Rate Generator sssususssssessese ess 11 11 11 3 4 Summary of Control Bits and SFRs for Timer Counter 2 11 12 11 4 Example Program Using Timers 0 1 and 2 cece eee 11 13 12 Serial Ports USARTO and USART1 euuueeeeleeeele eene 12 1 121 DOSCHIOUOM ERE CT TTD 12 2 12 2 Control Bits in SCONO and SCON1 sssuuesssssssssse nes 12 3 12 3 Pin and Interrupt Assignments 00 cece eens 12 4 12 4 Timer Counters 1 an
98. chip FLASH memory that is ac cessed only with MOVX X for external instructions even though it is on chip Typically data here consists of lookup tables Aconfigurable number of KBytes of user defined read only memory that is off chip It is accessed only with MOVX instructions Figure 2 1 On Chip and Off Chip Resources 2 2 On Chip Resources On Chip and Off Chip Resources 128 bytes indirectly addressable addressable RAM 128 bytes directly addressable RAM FFFF 64 KBytes 64 KBytes addressable addressable Program External Space Data Space On chip On chip 128 bytes directly SFRs FLASH FLASH ROM RAM RAM and or and or external external memory memory 0000 Program Memory and Data Memory Memory for program code may be on chip or off chip On chip it is realized by FLASH ROM or SRAM within the address range of 0000 to FFFFh During program execution if a code address is referenced that is not associated with on chip memory off chip memory will be accessed Even if on chip program memory is present off chip memory will be used as long as EA is low when the RST reset pin is released EA also overrides access to on chip SRAM that is mapped into code space Both program memory and data memory have 16 bit address spaces They are logically distinct and usually physically separate 2 2 Program Memory and Data Memory Table 2 1 shows the addresses associated with program memor
99. ct Ri Move indirect data memory to direct byte 2 2 12 24 86 87 MOV direct data Move immediate data to direct byte 3 3 12 24 75 MOV QRiA MOV A to indirect data memory 1 1 4 12 F6 F7 MOV R direct Move direct byte to indirect data memory 2 2 8 24 A6 A7 MOV Ri data Move immediate data to indirect data memory 2 2 8 12 76 77 MOV DPTR data Move 2 bytes of immediate data to data pointer 3 3 12 24 90 MOVC A A DPTR Move a byte in code space A unsigned after 1 3 12 24 93 DPTRtoA MOVC A A PC Move a byte in code space A unsigned after 1 3 12 24 83 from the address of the next instruction to A MOVX A Ri Move external data A8 to A 1 29 2 8 12 E2 E3 MOVX A DPTR Move external data A16 to A i 1 292 8 24 EO MOVX Ri A Move A to external data Upper 8 bit address 1 292 8 24 F2 F3 comes from MPAGE SFR MOVX DPTR A Move A to external data memory 1 292 8 24 FO PUSH direct Push direct byte onto stack 2 8 24 CO POP direct Pop direct byte from stack 2 2 8 24 DO XCH A Rn Exchange A and register 1 1 4 12 C8 CF XCH A direct Exchange A and direct byte 2 2 8 12 C5 XCH A QRi Exchange A and indirect data memory 1 1 4 12 C6 C7 XCHD A Ri Exchange A and indirect data memory nibble 1 1 4 12 D6 D7 in bits 3 0 1 Flags CY AC and OV may also be changed by explicit writes to corresponding bits in the PSW 2 Number of cycles is user selectable See
100. d 1 receive shift register is enabled for mode 0 RI 0 is also required 9th Transmission Bit State The state of the 9th bit to be transmitted in modes 2 and 3 9th Received Bit State The state of the 9th bit received in modes 2 and 3 In mode 1 when SM2 0 RB8_0 is the state of the stop bit RB8 O0 is not used in mode 0 TI 0 Transmitter Interrupt Flag This bit is set when the transmit buffer has been completely shifted out In mode 0 this occurs at the end of the 8th data bit while in all other modes it is set at the beginning of the STOP bit This flag must be manually cleared by software and can be set in software to cause an interrupt RI 0 Receiver Interrupt Flag This bit indicates that a byte has been received in the input shift register In mode 0 it is set at the end of the 8th data bit in mode 1 after the last sample of the incoming stop bit and in modes 2 and 3 after the last sample of the 9th data bit This bit must be manually cleared by software and can be set in software to cause an interrupt If IDLE bit 7 of PCON at 87h is set the CPU Timer Counters 0 1 and 2 and both serial ports will freeze until there is an auxiliary interrupt or external wake up see AIE at A6h EICON at D8h and EWU at C6h In modes 1 and 3 serial port 0 may be clocked by Timer Counter 1 or Timer Counter 2 as determined by RCLK and TCLK see T2CON at C8h whereas serial port 1 may be clocked only by Timer C
101. d interrupt 4 using 2 level RedLed YellowLed monitor if RI 0 syncl syncl monitor process simulate additional execution time RI_0 0 remove Rx flag if TI_0 test transmit interrupt flag TI_0 0 remove Tx flag if send SBUFO send send 0 level void TimerOInt void interrupt 1 using 1 level sync0O syncO0 monitor YellowLed 0 process simulate additional execution time YellowLed 1 level Interrupts 13 7 Example of Multiple and Nested Interrupts Example 13 1 Continued void Timer2Int void level sync2 sync2 TF2 0 level void main void PDCON 0x7D SCON0 0x50 CKCON 0x20 PCON 0x30 TMOD 0x22 TCON 0x50 TH1 THO 0 T2CON 0x04 256 xtal 32 12 BAUD interrupt 5 using 1 monitor remove Timer 2 overflow flag System Timer enabled Serial 0 enable RI 0 cleared Timer 2 at fclk 4 Timers 0 and 1 at fclk 12 SMOD Timers 1 and 0 Auto reload TR1 and TRO are 1 0 gt normal Baud rate eqution Timer 1 reload value Overflows every 256 12 tclk Timer 2 is auto reload and TR2 is 1 RCAP2 65536 xtal 4 RATE MSEC xtal 1000 1 MSINT 20 1 IP 0x90 IE 0xB2 AIE EICON 0x60 while 1 sync3 sync3 0x10 13 8 1 ms reference 20 ms interrupt interval Priorities Timer2 SerialO high TimerO low ER ET2
102. d 2 Baud Rate Generation 0000s 12 5 12 5 Mode 0 8 Bit Synchronous 0 00 0 e cece eens 12 7 12 6 Mode 1 10 Bit Asynchronous sess en 12 8 12 7 Modes 2 and 3 11 Bit Asynchronous 0 cece ees 12 9 12 8 Multiprocessor Communications 00 ccc eee eee 12 10 12 9 Example Programi reor eerte eis cae C EE VERRE AR TOES ed 12 10 139 Interrupts 1 52 conl Ru s Rer RR RR RR ede DX TE Ex aae 13 1 ou EPI c 13 2 13 2 Standard and Extended Interrupts 0 eee eee 13 2 19 3 Auxiliary Interrupt Sources 0 eee eens 13 4 13 4 Multiple Interrupts secsi reiii 2 0 00 ccc nent eens 13 5 13 5 Example of Multiple and Nested Interrupts 0 0 c eects 13 6 13 6 Example of Wake Up from Idle 0 0 13 9 Contents vii Figures l ARONIA RONIEHSANDARONG SooSo crt rT tt ee TT er rre ITTF gt 72 0N l N 11 3 11 4 11 5 11 6 12 4 12 2 12 3 12 4 12 5 12 6 12 7 viii MSC121x Block Diagram ine ee aa tenet E aeS 1 2 MSC 121X Pin Configuration isissssssssssssess en 1 4 Standard 8051 I O Pin Structure 2 0 ccc eens 1 7 CMOS Output Pin Structure 0 000 in eee ees 1 7 Open Drain Output Pin Structure 2 0 cect ees 1 7 Input Pin Structure cincasvtecbiea febees 82420 een SYR d ewes tbrehrPs eX sk 1 8 Comparison of MSC121x Timing to Standard 8051 Timing
103. d Extended Interrupts ISR Priority Addr 0 Low 1 High Relative IEO 03 PXO IP O TCON 1 EXO Timer 0 Overflow Cleared automatically TCON 5 ETO External Interrupt 1 Notes 2 3 TCON 3 EX1 Timer 1 Overflow Cleared automatically TCON 7 ET1 Serial Port 0 Clear RI 0 SCONO 0 ESO Serial Port 0 Clear TI 0 SCONO 1 ESO Timer 2 Overflow Clear TF2 T2CON 7 ET2 Serial Port 1 Clear RI 1 SCON1 0 ES1 Serial Port 1 Clear TI 1 SCON1 1 ES1 External Interrupt 2 Positive Edge Clear IE2 EXIF 4 EX2 External Interrupt 3 Negative Edge Clear IE3 External Interrupt 4 Positive Edge Clear IE4 10 External Interrupt 5 Negative Edge Clear IE5 11 Watchdog 3 4 Clear WDTI EICON 3 12 Low 1 Interrupt Enable IE is at A8h Interrupt Priority IP is at BBh Extended Interrupt Enable EIE is at E8h Extended Interrupt Priority EIP is at F8h External Interrupt Flag EXIF is at 91h 2 Ifthe interrupt was edge triggered the flag is cleared automatically as the service routine is entered otherwise the flag follows the state of the pin 3 May also cause a wakeup from idle if enabled 4 For the Watchdog Timer to generate an interrupt bit 3 of HCRO must be cleared otherwise a Reset default will occur Interrupts 13 3 Auxiliary Interrupt Sources 13 3 Auxiliary Interrupt Sources Table 13 2 shows the
104. d rate of 9600 as determined by Timer 1 The character is echoed and TF2 is set to generate an additional interrupt The red LED is on for 1 second and then off for 1 second while the yellow LED flashes at half this rate Initially the LEDs light at the same moment but each received character causes an extra call Timer2Int which produces an in creasing visible phase shift between the flashing of the LEDs fci k is the same frequency as the external crystal oscillator unless the Sys tem Clock Divider SFR SYSCLK at C7h is present and active SYSCLK is provided in the MSC1211 12 13 14 with a default value that causes no division of the external clock Table 11 7 Timer Modes Mode Type Clock Overflow or Baud Rate 11 0592MHz Clock 0 13 bit fei k 12 it fok _ 11059200 _ 12 8192 98304 B bitreload fcik 12 1 4 fci _ 11059200 2 16 12 x 256 TH1 1152 Where TH1 253 16 bitreload fcix 4 1 fox _ 11059200 _ 4 65536 RCAP2H RCAP2L 4 x 12288 Where RCAP2H RCAP2L 53248 112 5 9600 Baud 225 Timers and Counters 11 13 Example Program Using Timers 0 1 and 2 Example 11 1 Program Using Timers 0 1 and 2 File Timer012b c Timer 0 in 13 bit mode Timer 1 in 8 bit reload and Timer 2 in releoad MSC1210 EVM Switches 1 0n SW3 12345678 SW6 12345678 0 0ff 11110111 11110000 include lt Reg1210 h gt include lt stdio h gt define fclk 11059200 d
105. d8 R1 d8 80 2 3 2 3 83 1 3 85 3 3 86 2 2 87 2 2 SJMP AJMP MOVC MOV MOV MOV rel8 addr11 A A PC dir dir dir RO dir R1 90 3 3 2 3 93 1 3 95 2 2 96 1 1 97 1 1 MOV ACALL MOVC SUBB SUBB SUBB DPTR d16 addr11 A A DPTR A dir A RO A R1 AO 2 2 2 3 A3 1 3 A5 1 1 A6 2 2 A7 2 2 ORL AJMP INC NOP MOV MOV C bit addr11 DPTR o RO dir R1 dir BO 2 2 B1 2 3 B3 14 B5 3 4 B6 3 4 B7 3 4 ANL ACALL CPL CJNE CJNE CJNE CJNE C bit addr11 C A d8 rel8 A dir rel8 RO d8 rel8 R1 d8 rel8 CO 2 2 C1 2 3 C3 C4 1 1 C5 2 2 C6 1 1 C7 1 1 PUSH AJMP SWAP XCH XCH XCH dir addr11 A A dir A RO A R1 DO 2 2 D1 2 3 D4 11 D5 3 4 D6 11 D7 1 1 POP ACALL DA DJNZ XCHD XCHD dir addr11 A dir rel8 A RO A R1 EO 1 2 9 E1 2 3 E5 2 2 E6 14 E7 14 MOVX AJMP MOV MOV MOV A DPTR addr11 A dir A RO A R1 FO 1 2 9 F1 2 3 F5 2 2 F6 1 1 F7 14 MOVX ACALL MOV MOV MOV DPTR A addr11 dir A R0 A R1 A MSC121x Op Code Table Table 4 4 MSC121x Op Codes continued Table Cell Contents Operand Definitions addr11 11 bit address 3108 8 bit immediate data d16 16 bit immediate data rel8 8 bit relative address opcode bytes cycles instruction operand s addr16 16 bit address bit addressable bit dir direct address 08 1 1 OF 1 INC INC RO R7 18 1 1 1F 1 DEC DEC RO R1 R2 R3 R4 R5 R6 R7 28 14 14 2A 1 1 2B 1 1 2C 14 2D 14 2E 14 2F 1 1 ADD ADD ADD ADD ADD ADD ADD
106. der of additions is not defined in C it is possible that SUMRO is accessed first and the ADC interrupt flag is cleared If other interrupts are present and their service routines take more time to complete than the next conversion SUMRS 2 1 may be overwritten before being used to complete the evaluation of the expression Another approach is to define a union to overlay byte wide variables with a 4 byte long integer typedef union unsigned long v char va 4 struct char v3 v2 v1 v0 vs type sumv type sumv data s variable s is placed in core on chip data space Then use S VS V3 SUMR3 S VS V2 SUMR2 s vs v1l SUMR1 S VS v0 SUMRO SUMRO is accessed last reading f s v some function of the 4 byte variable v s Analog To Digital Converters 6 15 Accessing the ADC Multi Byte Conversion in C 6 16 Alternatively array elements may be used but the order of subscripts is reversed s va 0 SUMR3 s va 1 SUMR2 s va 2 SUMR1 s va 3 SUMRO Although the code needed to access the union may appear clumsy it maps to simple inline assembly level MOV instructions that take 3 x 4 12 machine cycles to execute In other words it is approximately 100 times faster than us ing multiple shifts In the next example the ADC results register is read using an assembly level program which makes expressions in C more intuitive This technique may also be used to read the summation register ADC Example
107. e This configuration makes accessing each DAC more in volved than simply writing to independent SFRs but has the advantage of us ing the SFR memory space efficiently The DAC select register SFR B7h determines the individual DAC buffer or control register to be accessed as well as the shared Load Control Register The interpretation of SFRs B6h and B5h depends upon the value in DACSEL as shown in Table 7 1 Table 7 1 DACSEL Values DACSEL B7h DACH B6h DACL B5h Reset Value 00h DACO high DACO low 0000h 01h DAC1 high DAC1 low 0000h 02h DAC2 high DAC2 low 0000h 03h DAC3 high DAC3 low 0000h 04h DAC1CON DACOCON 6363h 05h DAC3CON DAC2CON 0303h 06h LOADCON xx00h 07h to FFh Reserved Reserved Reserved The way a DAC output register is loaded is determined by two bits in the Load Control Register LOADCON as shown in Table 7 2 and Table 7 3 The LOADCON register is accessed indirectly via the SFR at B5h when DACSEL 06h Table 7 2 LOADCON SFR DACSEL z 06h SFR B5h Table 7 3 DxLOAD Output Modes for DACx DxLOAD 0 DxLOAD Output Mode for DACx Direct load A write to the DAC high byte DACxH is directed to the upper byte of the 16 bit data 00 buffer and does not alter the output register A write to the DAC low byte DACXL is directed to the lower byte of the 16 bit data buffer which is immediately copied to the output register Delayed load Values are written to the
108. e 0 8 Bit Synchronous 00 cece eee eee eee eee 12 7 12 6 Mode 1 10 Bit Asynchronous seeeeeeeee 12 8 12 7 Mode 2 and 3 11 Bit Asynchronous seeeeese 12 9 12 8 Multiprocessor Communications eee 12 10 12 9 Example Program 9 92 0e ese rares SEENE nuces 12 10 12 1 Description 12 1 Description 12 2 The MSC121x has two serial ports Both may be configured in almost the same variety of synchronous or asynchronous modes and clocked via fc the over flow from Timer Counter 1 or Timer Counter 2 USART stands for Universal Synchronous Asynchronous Receiver Transmitter Each port has a control register and a data register referenced as SCONO at 98h and SBUFO at 99h for serial port 0 and as SCON1 at COh and SBUF1 at C1h for serial port 1 Control Bits in SCONO and SCON1 12 2 Control Bits in SCONO and SCON1 Table 12 1 SCONO0 and SCON1 Serial Port 0 and Serial Port 1 Control Action or interpretation 0 0 0 0 8 SCONO SFR 98h smcm 0 0 PI SCON1 SFR COh Synchronous fei 12 0 0 0 1 Synchronous 8 feik 4 SMO 0 SVO 1 0 Asynchronous 1 0 1 10 Timer 2 1 3 Asynchronous 0 Asynchronous 11 2 1 0 Asynchronous a x f 4 1 5 11 64 CLK Multiprocessor 3 1 1 0 Asynchronous 11 Timer 2 3 1 pis a ynenronans 11 Timer 2 Multiprocessor Receive Enable Write 0 receive shift register is disable
109. e if PDSPI bit 0 of PDCON at F1h is 0 Howev er the SPI and I2C interface if present cannot both be enabled because the same SFR addresses are used to support them with different interpretations according to which interface is powered up Figure 10 1 SPI Master Slave Interconnect 10 2 MSC121x MSC121x Master SPI Slave SPI MOSI MOSI SPIDATA at 9Bh SCK SCK SPIDATA at 9Bh Read Read MISO MISO 7 e s 4 s 2 1 o SPIDATA at 9Bh Write SPIDATA at 9Bh Write port bit SPI Configuration The SPI is configured by SPICON at 9Ah according to Table 10 1 Table 10 1 SPICON SPI Control SPICON SFR 9Ah Reset Value 00h Bit Name Action or Interpretation 7 SCK Selection SCK SCK2 SCK1 SCKO 0005 to 1115 6 SPI clock frequency fci 2 SCK 1 That is fci 2 to fo_K 256 in powers of 2 5 SPI clock period tc x 2 SCK 1 That is to_ x 2 to to x 256 in powers of 2 4 Enable FIFO buffer in core SRAM 0 Transmit and receive pathways are double buffered 1 Circular FIFO buffer is used for to transmit and receive bytes 3 Sets bit order for transmit and receive 0 Most significant bit first 1 Least significant bit first 2 SPI Master Mode 0 Slave mode 1 Master mode 1 Serial clock phase control 0 Valid data starting from half SCK period before the first edge of SCK 1 Valid data starting from the first edge of SCK 0 CPOL serial clock p
110. echniques discussed in Ap plication Note SBAA112 MSC1211 12 DAC INL Improvement available for download at www ti com For DACs operating in voltage mode the reference voltage may extend to AVpp but the output voltage should remain 1 5V lower The nominal reference current is 254A per DAC Therefore when the internal voltage reference is disabled and Vpgr is derived from an external source con nected to the REFOUT REF IN pin the origin and impedance of the source voltage should be considered Digital To Analog Converters 77 DAC Example Program 7 5 DAC Example Program Example 7 2 shows a C program in which a variable i ranges from 0 to 250 in steps of 10 For each value 250 x i ix i and 40 x j 252 3 are calculated using only integer arithmetic The 3 functions are computed at different times but synchronous load mode 119 ensures that DACs 1 2 and 3 are updated simultaneously this may be verified with an oscilloscope Note that the ADC has to be powered to make the internal voltage reference available Example 7 2 DAC Program File DACO4 Testing DAC on MSC1211 with direct and synchronous loading MSC1211 EVM Switches 1 0n SW3 12345678 SW5 12345678 0 0ff 11110111 11110000 include lt Reg1211 h gt data unsigned int i j void main void PDCON amp 0x48 Turn on dacs and adc ADCONO 0x30 REFOUT REFIN Internal 2 5V ref DACSEL 6 DACL OxFC load DACs 3 2 1 simultaneously
111. ed wake up condition Three wake up conditions are enabled by bits in the Enable Wake Up EWU SFR at C6h as shown in Table 13 3 Table 13 3 EWU Enable Wake Up SFR C6h Reset Value 00h Action or Interpretation Undefined EWUWDT Enable wake up on watchdog timer 0 Disable wake up on watchdog timer interrupt 1 Enable wake up on watchdog timer interrupt EWUEX1 Enable wake up on external 1 0 Disable wake up on external interrupt source 1 1 Enable wake up on external interrupt source 1 EWUEXO Enable wake up on external 0 0 Disable wake up on external interrupt source 0 1 Enable wake up on external interrupt source 0 It is possible to synchronize the activity of a program to an external input by repeatedly reading its level However this requires more power than configur ing an interrupt and placing the MSC1211 into an idle state Interrupts 13 9 Example of Wake Up from Idle Example 13 2 Wake Up From Idle File Idle c MSC1210 EVM Switches 1 0n SW3 12345678 SW6 12345678 0 0ff 11110111 11110000 include Reg1210 h sbit syncO P1 0 Port 1 bit O sbit syncl P1 1 Port 1 bit 1 sbit sync2 P1 2 Port 1 bit 2 data unsigned char j void INTOInt void interrupt 0 using 1 No action syncl syncl monitor for interest void main void IE 0x81 EA EXO EWU 20x01 Enable Wakeup ITO 1 Falling edge on INTO while 1 while INTO wait for
112. edad POSEE ee UE ERE ME Ud PE pu 5 6 5 3 1 Watchdog Timer Example Program ssesssseesss esee 5 7 5 4 Low Voltage Detection 0 0 cece teen eee eee 5 8 5 5 Hardware Configuration 06 cece nents 5 9 5 6 Breakpolits gis enact dayne tm Lesen e dort da deno d Rot kad iS 5 11 Contents 6 Analog To Digital Converters 00 ccc eee een nnn nnn 6 1 6 51 ADC Functional Blocks sssssssssssssssesssse se 6 2 6 2 ADC Signal Flow and General Description 0000 cee eee tenes 6 3 6 3 Analog Input Stage seu mb edu nisiende d dus woe ded dd Rd des 6 3 6 4 Input Impedance PGA and Voltage References ssseeseelllesesss 6 5 6 5 Offset DAC iiie esee grob bares aces Re EAE ad ubdepe atau deed da dere 6 8 6 6 ADC Data Rate Filters and Calibration sesee IIR 6 9 6 7 32 Bit Summation Register 0 00 ccc ete es 6 13 6 8 Accessing the ADC Multi Byte Conversion in C 0060 caure ruanan 6 15 69 ADC Example Program csessesi lees ru Red ES e Peet RELRT4 ee RE Y IRSE ERA 6 17 7 BDigital To Analog Converters ssseseeeeeee eene nnn nnn 7 1 4 4 ntroductlon 2i eder dee Ron dace raum a Varie dE Aces dda dee 7 2 7 2 DAC Selection ssssuussssssssssle es 7 3 7 38 DAC Configuration and Control 00 cc e 7 5 7 4 DAC Technology and Limitations 00 eens 7 7 5 DAC Example Program ttn dee ni miis Makes ren dem
113. ee External Interrupt Flags EXIF at 91h HWPCO E9h Hadware Product Code 0 Refer to the respective data sheet for the code that indicates the type of device HWPC1 EAh Hardware Product Code 1 Refer to the respective data sheet for the code that indicates the type of device HDWVER EBh Hardware version number Refer to the respective data sheet for the code that indicates the type of device FMCON EEh Flash Memory Control Three bits to provide control of the Flash memory specifically page mode erase frequency con trol mode and busy FTCON EFh Flash Memory Timing Control The upper four bits FER determine the Flash erase time while the lower four bits FWR deter mine the Flash write time according to the following equations Erase time 1 FER x MSECH MSECL 1 x tc 5 ms 11ms for commercial industrial temperatures Write time 5 x 1 FWR x USEC 1 x tcLK The write time should be between 30us and 40us See MSECH and MSECL at FDh and FCh respectively and USEC at FBh B FOh B Register The B register is used only by the instructions MUL AB and DIV AB If these instructions are not used B is available to store a byte wide variable or eight single bit variables Caution is needed when programming in C because run time libraries may use these instructions and thus corrupt the value in B 3 12 SFR Overview Table 3 2 SFR Overview continued Address Hex Description Name PDCON Fih Power Down Control
114. eee a deg dades 7 8 8 Pulse Width Modulator and Tone Generator seeeeeeeeeeeeeeeee 8 1 8 1 prem TEES 8 2 8 2 PWM Generator Example 2 0 cece eee e 8 4 9 Inter IC I C Subsystem 000 cc cece eee eee eee eee nnn 9 1 Bl Intr ducti n to the 5D BUS Lu idus tiated er ida a ea a o AG P Lab os d Eat capt 9 2 Ba PPG Pm ace sing se whic do dodo OR ACER dai t PORC Sei xn Meigs Mn ION da 9 2 9 3 OC Bus Lines and Basic Timing 3 222223 ron ARE RUOTA RC ca Bee 9 3 9 4 12C Data Transfers and the Acknowledge Bit 000 ccc cece e eee 9 4 95 J G Principal Registers 2e cde ho RRE E RR ENQE PE ROPA OPER nave eed ded 9 6 9 6 l2C Related Registers sssssssssssssssssesss nen eee n eee n ees 9 10 9 7 C Example MSC1211 13 as a Master 2 0 neces 9 11 9 8 C Example MSC1211 13 as a Slave 0 cence eee nes 9 13 9 9 12C Example MSC1211 13 as an Interrupt Driven Slave 0 0000 ee 9 15 9 10 12C Synchronization and Arbitration 0 0 0 ccc esses 9 17 9 11 12C Fast Mode 6 cece sss s 9 17 932 eG General Calls steer e PES LL LS eM E 9 17 9 13 12C 10 Bit Addressing ssssssssssssssssssses ss n 9 18 10 Serial Peripheral Interface SPI 00 cece eee eee eee 10 1 10 1 DOSCIPUON g2c20 2e 082iardnsteonisbavoseebsieebsesedsrseddessetestenl steed 10 2 10 2 SPI Configuration 00 ccc 10 2 10 3 SPI Interrupts i2 o
115. efine BAUD 9600 define limit 225 sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM data unsigned int i 1 j 1 void TimerOInt void interrupt 1 using 1 if i i limit YellowLed YellowLed void Timer2Int void interrupt 5 using 1 if j j limit RedLed RedLed TF2 0 remove overflow flag void main void CKCON 0x20 Timer 2 at fclk 4 Timers 0 1 at fclk 12 PCON 20x30 SMOD 0 TMOD 20x20 Timer 1 Auto reload Timer 0 13 bit TCON 0x50 TR1 and TRO are 1 TH1 256 fclk 32 12 BAUD Timer 1 reload value T2CON 0x04 TR2 is 1 and Timer 2 is auto reload RCAP2 65536 fclk 4 limit SCON0 0x52 Asynchronous and enabled TI_0 1 RI_0 0 while RI_0 wait for key press printf nMSC1210 Timer 0 in mode 0 Timer 1 in mode 2 printf Mn Timer 2 in 16 bit auto reload n IE 0xA2 EA ET2 and ET1 enabled while 1 while RI_0 wait for key press SBUFO SBUFO echo TF2 1 Force Timer 2 interrupt RI 0 0 11 14 Chapter 12 Serial Ports USARTO and USART1 This chapter describes the serial ports of the MSC121x Topic Page 12 1 Description 7 9 tereos see rele eser aae e e ejua es nara 12 2 12 2 Control Bits in SCONO and SCON1 sese 12 3 12 3 Pin and Interrupt Assignments 00 cece cece eee eee 12 4 12 4 Timer Counters 1 and 2 and Baud Rate Generation 12 5 12 5 Mod
116. eived flag in USART wait for conversion test ADC interrupt flag get reading and clear flag simple theoretical convert to Degrees C empirical 1 convert to Degrees C empirical 2 nearest integer clamp range if line length gt temperature output new line and temperature PRBS generator with 4 bit feedback j will become the sum of 1 s inn shift r left with lsb of sum Note putchar takes 28 machine cycles but printf takes 354 machine cycles increment character count ADC Example Program Example 6 1 Continued From TI file Utilities A51 File name utilities a51 Copyright 2003 Texas Instruments Inc as an unpublished work All Rights Reserved Revision History Version 1 1 Assembler Version Keil V2 38 Raisonance V6 10 13 Module Description ADC routines to read 24 bit ADC and return the value as a long integer PRR RR KR k k k k k k k RK k k RK KK RK k k k k KK k k k k k k k k k k ck kck ck kc kck ck ck kck ck ck k k ck ck k k ck ck k k ck k k k k k k Sinclude legal a51 Texas Instruments Inc copyright and liability include reg1210 inc PRR RRR sk cce ke kc he ke e he ke ke he e e She ke e he he ke e he ke ke he he ke e he ke KERR ke e he he ke che he ke e he ke kc he ke e he ke ke he he ke e e ke e e e ek PUBLIC unipolar bipolar read sum regs adc sub SEGMENT CODE RSEG adc sub unsigned long unipolar void return the 3 byte adres to R4567 MSB LSB unsigned long int
117. er RESET as configured by the PxDDRH and PxDDRL SFRs where x 0 to 3 The pull up resistor is disabled when the port bit is configured as either a CMOS output open drain output or input or when accessing external memory as shown in Figure 1 3 through Figure 1 6 When a port pin is to act as an input to an alternate function it is essential that the pin is not configured as an output To make use of the alternate functions associated with Ports 1 and 3 the corresponding port output latches should be high with the data direction bits defined in a manner appropriate to the alternate function L A special case exists for the 8051 mode which has a weak pull up resistor and offers bidirectional capability Figure 1 3 Standard 8051 I O Pin Structure DVDD Read Pin lt e 10k Read Register 1 E Pn n All Functions Figure 1 4 CMOS Output Pin Structure CMOS Output Figure 1 5 Open Drain Output Pin Structure Open Drain ais Output Introduction 17 MSC121x Pinout Figure 1 6 Input Pin Structure 1 2 1 1 Port 0 PO 1 2 1 2 Port 1 P1 Input By default Port O provides eight independently programmable input output bits However it may be configured to provide eight multiplexed low order ad dress and data lines so that external memory may be accessed See bit 1 of hardware configuration register 1 HCR1
118. er Slave address R transmitted NACK received 0A Master Receiver Data byte received ACK transmitted 0B Master Receiver Data byte received 1 9 8 NACK transmitted W means R W bit is 0 R means that RW bit is 1 12c Principal Registers Table 9 6 12C Status Codes continued Status Code State Hex Action Taken by the 12C 0C Slave Receiver Own slave address W already received ACK transmitted oD Invalid Reserved OE Slave Receiver General call address 00h received ACK returned OF Invalid Reserved 10 Slave Receiver Own slave address W already received Data byte received ACK transmitted 11 Slave Receiver Own slave address W already received Data byte received NACK transmitted 12 Slave Receiver General call address 00h received Data byte received ACK transmitted 13 Slave Receiver General call address 00h received Data byte received NACK transmitted 14 Slave Receiver A STOP or repeated START received while addressed as a slave or General Call 15 Slave Transmitter Own slave address R already received ACK transmitted 16 Invalid Reserved 17 Slave Transmitter Data byte transmitted ACK received 18 Slave Transmitter Data byte transmitted NACK received 19 Slave Transmitter Last data byte transmitted will switch to non addressed slave 1A to Invalid Reserved 1E 1F Invalid Reserved 1 W means R W bit is 0
119. eration where PSEN is always an output that usually acts as an active low strobe to read from external program memory When no external memory is present PSEN may be used as an independent output that can be placed low high or reflect the ADC modulator clock via PSEN mode bits in PASEL at F2h 1 2 6 External Access EA pin 48 EA is sampled as the RST pin is de asserted low and determines whether the MSC121x fetches instruction codes from internal or external memory When EA is high code is fetched from internal memory otherwise code is al ways fetched from external memory Changing the level on EA during normal operation has no effect Code is fetched at addresses pointed to by the Program Counter PC during program execution and also when a MOVC instruction is executed In either case if EA is high but there is no internal memory associated with a particular address an external fetch will occur Introduction 1 11 Enhanced 8051 Core 1 3 Enhanced 8051 Core All members of the MSC121x family of mixed signal microcontrollers use a core that is instruction set compatible with the industry standard 8051 All in struction codes have the same binary patterns and produce exactly the same logical changes However the MSC121x is approximately three times faster in execution for the same clock frequency instead of using 12 clocks per in struction cycle the MSC121x uses four The designer can either make use of the increa
120. ernate Name s Alternate Use P3 0 RxDO Serial port 0 input P3 1 TxDO Serial port 0 output P3 2 INTO External interrupt 0 P3 3 INT1 TONE PWM External interrupt 1 TONE PWM output P3 4 TO Timer 0 input P3 5 T1 Timer 1 input P3 6 WR External data memory write strobe P3 7 RD External data memory read strobe 11 14 15 DVpp Digital power supplies All must be used 42 58 12 41 57 DGND Digital grounds All must be used 13 RST A HIGH on the reset input for two clock cycles resets the device Base MSC1210 Pin Function Alternate or Additional in MSC1211 12 13 14 16 NC No connection RDACO MSC1211 12 13 14 only 17 AGND Analog ground VDACO MSC1211 12 13 14 only 18 AINO Analog input channel 0 AINO AINO and IDACO MSC1211 12 13 14 only 19 AIN1 Analog input channel 1 AIN1 AIN1 and IDAC1 MSC1211 12 13 14 only 20 AIN2 Analog input channel 2 AIN2 AIN2 and VDAC2 MSC1211 12 only 21 AIN3 Analog input channel 3 AIN3 AIN3 and VDAC3 MSC1211 12 only 22 AIN4 Analog input channel 4 AIN4 same 23 AIN5 Analog input channel 5 AIN5 same 24 AING Analog input channel 6 AIN6 and same EXTD digital low voltage detect input 25 AINT Analog input channel 7 AIN7 and same EXTA analog low voltage detect input 26 AINCOM Analog common for single ended same inputs 27 AGND Analog ground same 28 AVpp Analog power supply same 29 REF IN Voltage reference negative input same 30 REF IN Voltage reference positive input REFOUT REF IN 31 REFOUT Vo
121. es 8400h to 87FFh in external data memory and program memory share the same on chip RAM Table 5 8 BPCON Breakpoint Control SFR A9h Reset Value 00h Action or Interpretation Write 0 No effect 1 clear breakpoint interrupt flag for breakpoint register selected by MCON 7 Read 0 no breakpoint interrupt 1 breakpoint match from either breakpoint register Always 0 Write 0 break on address in external data memory 1 break on address in program memory Applies to breakpoint register selected by MCON 7 Write 0 disable interrupt on address match 1 enable interrupt on address match Applies to breakpoint register selected by MCON 7 System Clocks Timers and Functions 5 11 Breakpoints Table 5 9 BPL Breakpoint Low Address for BP Register Selected in MCON at 95h Reset Value 00h Write Read Low eight bits of 16 bit breakpoint register Applies to register selected by MCON 7 Reset Value 00h Write Read High eight bits of 16 bit breakpoint register Applies to register selected by MCON 7 Table 5 11 Breakpoints Breakpoint interrupt has priority 0 high and jumps to address 33h shared with DVpp low voltage interrupt Address Bit Name Abbreviation Name of related SFR Abbreviation Hex Enable Auxiliary Interrupt EAI Enable Interrupt Control EICON 5 D8 Auxiliary Interrupt flag Al Enable Interrupt Control EICON 4 D8 Enable Digital Low Voltage EDLVB Auxilia
122. essed from either data or code space as determined by BPCON at A9h an interrupt may occur These SFRs are used to assist in real time debugging PODDRL ACh Port 0 Data Direction Low configures bits 3 2 1 and 0 in Port 0 PODDRH ADh Port 0 Data Direction High configures bits 7 6 5 and 4 in Port 0 Adjacent bits in PODDRL and PODDRH control the type of bit presented to device pins by Port 0 Standard 8051 that is bidirectional with weak pull up is 00 CMOS output is 01 Open drain output is 10 and input only is 11 If EGPO bit 1 of HCR1 is 0 or pin EA is 0 when the RST pin is released PO is either a CMOS input or output and PODDRL and PODDRH have no effect 3 8 SFR Overview Table 3 2 SFR Overview continued Address Name Hex Description P1DDRL AEh Port 1 Data Direction Low configures bits 3 2 1 and 0 in Port 1 P1DDRH AFh Port 1 Data Direction High configures bits 7 6 5 and 4 in Port 1 Adjacent bits in P1DDRL and P1DDRH control the type of bit presented to device pins by Port 1 Standard 8051 that is bidirectional with weak pull up is 00 CMOS output is 01 Open drain output is 10 and input only is 11 P3 BOh Port 3 Controls the byte wide bit programmable input output called Port 3 Each bit in the SFR corre sponds to a pin on the actual part Individual bits may be configured as bidirectional CMOS out put open drain output or input via the Data Direction SFRs for Port 3 See P3DDRL at B3h and
123. et All SFRs are placed at their default values and the program counter is reset to 0000h The contents of internal SRAM are not affected by a reset and instruction execution begins when RST is brought low when both PSEN and ALE are high If either PSEN or ALE is low when RST is brought low the MSC121x enters Flash Programming mode The RST pin has a CMOS Schmitt trigger input that permits the use of a simple RC network to achieve reset when power is first applied For the MSC1210 the internal pull down resistor is typically 200kQ For the MSC1211 12 13 14 there is no internal pull down resistor 1 2 4 Address Latch Enable ALE pin 45 As RST is de asserted low ALE temporarily acts as an input with a 9kQ inter nal pull up resistor and is used in conjunction with PSEN to place the MSC121x in a programming mode If neither is pulled low the MSC121x be gins normal operation where ALE is always an output that usually controls a strobed latch to demultiplex the address appearing on Port 0 When no external memory is present ALE may be used as an independent output that can be placed low or high via the ALE mode bits in PASEL at F2h MSC121x Pinout 1 2 5 Program Store Enable PSEN pin 44 As RST is de asserted low PSEN temporarily acts as an input with a 9kQ internal pull up resistor and is used in conjunction with ALE to place the MSC121x in a programming mode If neither is pulled low the MSC121x be gins normal op
124. et 2 6 2 1 Introduction 2 1 Introduction Some microprocessors have a single unified address space that is used for program code data values and Input Output ports However most 8051 cores and thus the MSC121x have several distinct addressable spaces that serve different purposes as shown in Figure 2 1 In fact the MSC121x implements all address spaces found in the 8051 but with a feature that permits self modi fiable code Direct and indirect 8 bit addresses access up to 384 bytes of on chip re sources comprised of 256 bytes of static random access memory SRAM and up to 128 SFRs 16 bit pointers PC and DPTR allow up to 64 KBytes of program memory and 64 KBytes of extended data memory to be accessed which may be on chip and or off chip Memory for data may be allocated in different places depending upon the size of the data how frequently it is altered and how efficiently it is accessed The resources available on the MSC121x are 256 bytes of on chip SRAM for working registers bit wide variables byte and multi byte variables and a stack This memory is accessed by the ma jority of data processing instructions 1024 bytes of on chip extended SRAM which is considered by the archi tecture as logically external data It is used for variables that are needed less frequently and accessed only with MOVX X for external instructions even though it is on chip A configurable number of KBytes of on
125. et during a data transfer a STOP condition is trans mitted followed by a START condition Defines the type of acknowledgement generated during the acknowledge cycle Master or slave receiver write 0 Not acknowledge NACK high level on SDA is generated 1 Acknowledge ACK low level on SDA is generated Slave transmitter write 0 The current byte will be the last byte transmitted because NACK occurs 1 One or more bytes to follow the current transaction because ACK occurs Reserved Always write 0 Write 0 Standard Mode 100 kHz 1 Fast Mode 400 kHz 9 6 12c Principal Registers Table 9 2 I2CCON I C Control Register continued Write 0 Slave Mode 1 Master Mode SFR 9Ah Reset Value 00h Write 0 No effect 1 Remove stretch of SCL low when in slave mode Allowed only after I2C master has put SCL low 50ns glitch filter Write 0 Filter disabled 1 Filter of approximately 50ns is enabled Table 9 3 I2CDATA SFR I2CDATA Reset SFR 9Bh 7 6 5 4 3 2 1 0 Value Data MSB LSB 00h Address MSB LSB R W 00h Table 9 4 12CGM I2C General Call Multiple Master Control I2CGM SFR 9Ch Reset Value 00h Bit Action or Interpretation GCMEM _ Write only Slave mode write 0 General Call address will be ignored 1 General Call address will be detected Master mode write 0 Single Master 1 Multiple Master mode Inter IC 12Ct Subsystem 9 7 12c Principa
126. g Reset 0 Disable Watchdog from causing a reset and allow an interrupt if unmasked 1 Enable Watchdog Reset default 2 DFSEL2 1 DFSEL1 0 DFSELO DFSEL Data Flash Memory Size On chip Flash memory can be partitioned between data memory and program memory The total memory available depends on the Y version of the device See section 2 2 for a complete description of memory partitioning 000 Reserved 001 4 KB 8 KB 16 KB or 32 KB 010 4 KB 8 KB or 16 KB 011 4 KB or 8 KB 100 4 KB 101 2 KB 110 1 KB 111 0 KB System Clocks Timers and Functions 5 9 Hardware Configuration Table 5 6 Hardware Configuration Register 1 HCR1 Non SFR address 7Eh accessed indirectly via SFR CADDR at 93h Erased Value FFh Bit Name Action or Interpretation 7 DBLSEL1 Digital Brownout Level Select The digital brownout level is loaded after POR therefore a proper POR must occur for digital brownout levels to be properly loaded 00 4 5 V DBLSEL FRED 01 4 2V 10 2 7 V 11 2 5 V default 5 ABLSEL1 Analog Brownout Level Select The analog brownout level is loaded after POR therefore a proper POR must occur for analog brownout levels to be properly loaded 00 4 5 V 4 ABLSELO 01 42 V 10 2 7 V 11 2 5 V default 3 Disable Analog Power Supply Brownout Detection 0 Analog Brownout causes reset 1 Analog Brownout reset is disabled default 2 Disable Digital Power Supply Br
127. he assembly level MOVC instruction Data memory is always accessed via the assembly level MOVX instruction Even though this mnemonic stands for MOV eXternal the memory may be on chip Table 2 2 MSC121x Flash Memory Partitioning and Addresses HCRO Binary DFSEL 000 001 010 011 100 101 110 111 default MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5 PM DM PM DM PM DM PM DM reserved reserved reserved reserved reserved reserved reserved reserved 32 KB 0 KB 4 KB 0 KB 8 KB 0 KB 16 KB 0 KB 0400 13FF 0400 23FF 0400 43FF 0400 83FF 0 KB 4 KB 0 KB 8 KB 0 KB 16 KB 16 KB 16 KB 0400 13FF 0400 23FF 0400 43FF 0000 3FFF 0400 43FF 8KB 0 KB 4 KB 0 KB 8 KB 8 KB 8 KB 24 KB 0400 13FF 0400 23FF 0000 1FFF 0400 23FF 0000 5FFF 0400 23FF 0 KB 4 KB 4KB 4KB 12 KB 4KB 28 KB 4KB 0400 13FF 0000 0FFF 0400 13FF 0000 2FFF 0400 13FF 0000 6FFF 0400 13FF 2KB 2KB 6 KB 2KB 14 KB 2KB 30 KB 2KB 0000 07FF 0400 0BFF 0000 17FF 0400 0BFF 0000 37FF 0400 OBFF 0000 77FF 0400 0BFF 1KB 3KB 1KB 7KB 1KB 15 KB 1KB 31 KB 0000 0BFF 0400 07FF 0000 1BFF 0400 07FF 0000 3BFF 0400 07FF 0000 7BFF 0400 07FF 4KB 0 KB 8 KB 0 KB 16 KB 0 KB 32 KB 0 KB 0000 0FFF 0000 1FFF 0000 3FFF 0000 7FFF 1 PM Program Memory Code Space DM Data Memory Data Space 2 Execution from off chip memory may be forced when pin EA i
128. he parts differ only in the amount of on chip Flash memory available 1 5 Flash Memory The MSC121x parts feature flexible Flash memory that can be partitioned into program and data areas that are best suited for each application They may be programmed over the entire operating voltage range and temperature range using serial parallel and self programming methodologies 1 6 Internal SRAM The MSC121x contains a total of 1280 bytes of static random access memory RAM 128 bytes are directly addressable using instructions that incorporate the address An additional 128 bytes are indirectly addressable via instruc tions using a register as a pointer while 1024 bytes are logically external but physically internal and accessed with the MOVX instruction 1 7 High Performance Analog Functions The analog functionality is state of the art The ADC is extremely low noise and meets the most stringent requirements for analog instrumentation The in tegrated programmable gain amplifier PGA further improves the perfor mance of the ADC which then achieves nanovolt resolution The integrated low drift high accuracy voltage reference complements the performance of the ADC and usually eliminates the need for an external refer ence However ratiometric measurements are still possible and easily imple mented Also present are a programmable filter an analog multiplexer for single ended and differential signals a temperature sensor burnout cu
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130. ifted into an input shift register of which eight bits are then loaded into the received SBUF register if 1 Rlis 0 and 2 SMeis 1 and the ninth bit is 1 or SM2 is O that is the state of the ninth bit does not matter If the conditions are not met the received data is lost RB8 is not loaded and RI is not set If SBUF is loaded the state of the ninth data bit is copied into RB8 at SCON 2 and RI is set Transmission is triggered by a write to SBUF and results in an 11 bit frame con sisting of a low level start bit eight data bits from SBUF TB8 from SCON 3 and a high level stop bit The start bit begins at the next rollover of the local divide by 16 counter and TI is set at the beginning of the stop bit For mode 2 the baud rate is fc K 64 if SMOD is 0 default or fc 32 if SMOD is 1 SMODO is bit 7 of PCON at 87h and SMOD is bit 7 of EICON at D8h For mode 3 the baud rate is determined by the overflow rate of Timer Count ers 1 or 2 for serial port 0 or Timer Counter 1 for serial port 1 Figure 12 5 Asynchronous 11 Bit Receive Write to SBUFO TX CLK SHIFT txdO TIO grant D0 X 01 XE X 98 X 04 X 05 X SX OF K Tew STOP Figure 12 6 Asynchronous 11 Bit Transmit RX CLK rxdO in Bit Detector Sampling SHIFT grant 00 C51 K Be KX BS C94 C05 X BSF XCR88 STOP RI 0 Serial Ports USARTO and USART1 12 9 Multiprocessor
131. imer Counters 0 and 1 Signal Control or Data Bit Address Address Bit Address Address Timer overflow flag TCON 7 88h 8Fh TCON 5 88h 8Dh Count high byte TH1 THO Count low byte TL1 TLO Timer Counter select T TMOD 6 TMOD 2 Mode bit 1 TMOD 5 TMOD 1 Mode bit 0 TMOD 4 TMOD 0 Divide by 4 or 12 select CKCON 4 CKCON 3 External clock input P3 5 T1 P3 4 TO B4h Timer run control TCON 6 TCON 4 8Ch Internal timer gate TMOD 7 TMOD 3 External timer gate P3 3 INT1 P3 2 INTO B2h Enable interrupt IE 3 IE 1 A9h Interrupt priority IP 3 IP 1 B9h Timers and Counters 11 7 Timer Counter 2 11 3 Timer Counter 2 Timer Counter 2 consists of the register pair TH2 TL2 which act as a 16 bit neg ative edge triggered up counter The associated register pair RCAPH RCAPL may either capture the current value of TH2 TL2 or provide a reload value accord ing to the mode of operation selected by bits in T2CON at C8h Table 11 5 T2CON Timer 2 Control T2CON SFR C8h Reset Value 00h Bit Name Action or Interpretation 7 Timer 2 Overflow Flag Read 0 No Overflow 1 Timer 2 reached maximum count of FFFFh and overflowed to 0 It is not cleared auto matically as the processor jumps to the interrupt service routine at 002Bh Write 0 Clear flag if set 1 Set overflow flag and generate interrupt if enabled 6 Timer 2 External Flag This flag is set by a high to low transition on pin P1 1 T2EX wi
132. ions 5 5 Watchdog Timer 5 2 1 Behavior in Delay Mode 102 Changes in the divisor are synchronized with the timeout of the milliseconds system timer MSINT at FAh which must be powered up that is bit 1 of PDCON at F1h must be 0 Once a new divisor is written to SYSCLK with this mode it will take effect at the next MSINT timeout During this time bit O of PCON at 87h can be set to place the CPU in the IDLE state and reduce the power still further When the divisor is active and the milliseconds interrupt is enabled via EMSEC bit 4 of AIE at A6h the timeout causes immediate removal of the divisor This is likely to occur when a real time elapsed clock is supported in software by maintaining a record of the accumulated number of millisecond interrupts The program must compensate for the increase in time caused by the divisor In effect if the milliseconds interrupt is enabled via EMSEC when the divider mode is changed to 10 the divisor will become active on the next MSINT in terrupt and return to divide by 1 on the following MSINT interrupt However if the milliseconds interrupt is masked the divisor will still become active on the next MSINT interrupt but will not return to divide by 1 until the milliseconds interrupt after a wake up condition If the wake up condition is caused by an enabled seconds interrupt that is synchronous with a millisecond interrupt the divider immediately returns to divide by 1 5 3 Watchdog Timer
133. ith respect to l Timer 0 The same i PINO 1 functional behavior i TRO is available from L1 Lo rade GATE m mM H Pin INTO TLO represents an 8 bit negative edge triggered counter that is reloaded from THO as it overflows It may be from clocked from a variety of sources as de scribed for modes 0 and 1 Baud Rate to Serial Ports Timer 1 Only Timer Counters 0 and 1 11 2 3 Mode 3 The behavior of Timer Counter 0 in mode 3 is not the same as Timer Counter 1 because the interrupt flag usually associated with Timer 1 is controlled by THO Figure 11 3 Timer 0 Mode 3 THO Interrupt 7 6 5 4 3 2 i o TLO Interrupt 7 6 s 4 3 2 1 o Timer 0 TRI _ Mode 3 e post ce TOM is CKCON 3 NOTE THO triggers i the interrupt foik 12 if TOM 0 associated with i feik 4 if TOM 1 1 Timer 1 When Timer 0 is in Mode 1 3 Timer 1 can still Pin TO i I I I I be used in Modes 1 0 1 and 2 but TRO without an overflow cate o7 gt oo eee Pin INTO TLO is an 8 bit timer or counter that is clocked and gated in a manner similar to Mode 0 THO must be clocked from the same source but is gated only by control bit TR1 Without TR1 and TF1 Timer 1 can still be used for baud rate generation 11 2 4 Summary of Control Bits and SFRs for Timer Counters 0 and 1 Table 11 4 Control Bit and SFR Summary for T
134. l at least one instruction will be executed before another interrupt is acknowledged When application code is written in C protection of the operating context is usually managed by the compiler 13 2 Standard and Extended Interrupts 13 2 Table 13 1 shows the standard and extended interrupts with low or high group priorities and high or low relative priorities Global Enable EA IE 7 where IE is at A8h Note that in the first column of Table 13 1 the normal text de scribes the event while the italic text describes how to clear it By default all standard and extended interrupts are grouped with a low priority However individual interrupts may be changed to have a high priority by writ ing 1 to the appropriate bit within either the IP or EIP registers All interrupts in a high priority group are serviced before those of a low priority group and those within a group are serviced in the order of relative priority shown in Table 13 1 For example if Timer 0 and Serial Port 0 are both low priority then the timer will be serviced before the port However if bit 4 of IP at B8h is set to 1 the interrupt from Serial Port 0 will have a higher priority and be serviced before Timer 0 Any interrupt flag associated with a low or high priority interrupt may be set in software to cause an interrupt if enabled Table 13 1 Standard and Extended Interrupts Event Cleared by External Interrupt 0 Notes 2 3 Standard an
135. l Registers In master mode a write to I2CSTAT sets the frequency of the SCL line to SYSCLK 2 x SCKD 1 where the minimum value allowed for SCKD is 3 In slave mode a write to I2CSTAT sets the slave address in bits 6 to 0 which is only recognized if Slave Address Enable SAE is 1 Table 9 5 shows the I2CSTAT SFR In either mode reading I2CSTAT returns a 5 bit status code that is left justified and clears the 12C Status Interrupt flag in bit 2 of AIE Left justified status codes can be used to implement jump table easily The status codes are listed in Table 9 6 Table 9 5 I2CSTAT SFR I2CSTAT Reset SFR 9Dh 7 6 5 4 3 2 1 0 Value Read STAT7 STAT6 STAT5 STAT4 STAT3 0 0 0 x Write SAE SA6 SA5 SA4 SA3 SA2 SA1 SAO 00h Write SCKD7 SCKDe SCKD5 SCKD4 SCKD3 SCKD2 SCKD1 SCKDO x Table 9 6 I C Status Codes Status Code State Hex Action Taken by the 12C 00 Waiting No action 01 Master Transmitter Receiver START condition transmitted 02 Master Transmitter Receiver Repeated START condition transmitted 03 Master Transmitter Slave address W 1 transmitted ACK received 04 Master Transmitter Slave address W transmitted NACK received 05 Master Transmitter Data byte transmitted ACK received 06 Master Transmitter Data byte transmitted NACK received 07 Master Transmitter Arbitration lost 08 Master Receiver Slave address R 1 transmitted ACK received 09 Master Receiv
136. lator at SFR EOh is cleared 1 The Stack Pointer SP itself an SFR at 81h has a default value of 07h Hence register bank 1 or above must not be used unless SP is given a higher value 2 Direct addresses between 80h and FFh always address the SFR space even when no SFR is defined at a particular loca tion SRAM between 80h and FFh can only be accessed indirectly or implicitly 3 The Serial Peripheral Interface SPI may be configured to use a circular memory buffer within SRAM and this must be placed so that it does not conflict with other operations 2 4 Beyond 64 KBytes If more than 64 KBytes of either program or data storage are required various bank switching techniques can be used These may be supported automati cally with some C compilers and development environments refer to the soft ware vendor for further information Chapter 3 Special Functions Registers This chapter describes the special function registers of the MSC121x Topic Page 3 1 Introduction 7 eerie n keen orn E 188 Ian ee o E enin 3 2 3 2 Referencing SFRs in Assembly and C Languages 3 3 S S SER ile sscnescsceadscs ooccddacdccosemeseoseossunsecescesaaas 3 4 CHL SIAR Overview condo dendnonbhaonnponononseabonmaenadsesensponc 3 4 3 1 Introduction 3 1 Introduction Special Function Registers SFRs are addressable resources within the MSC121x architecture They can be accessed by a program in several ways
137. lave address with write bit while AIE amp 0x04 wait for I2C interrupt flag i I2CSTAT if i 0x18 break handle unexpected condition I2CDATA 0x00 Address within PCF8593 while AIE amp 0x04 wait for I2C interrupt flag i I2CSTAT if i 20x28 break handle unexpected condition Inter IC 12Ct Subsystem 9 11 I2C Example MSC1211 13 as a Master Example 9 1 Continued I2CDATA 0x00 while AIE amp 0x04 i I2CSTAT if i 0x28 I2CCON 0x40 break while i I2CCON i amp 0x40 I2CCON 0x80 while AIE amp 0Ox04 i I2CSTAT if i 0x08 while SCL I2CDATA 0xA3 while AIE amp 0x04 i I2CSTAT if i 0x40 I2CCON 0x20 i I2CDATA while AIE amp 0Ox0A4 i I2CSTAT if i 0x50 il I2CDATA while AIE amp 0Ox0A4 i I2CSTAT if i 0x50 I2CCON amp 0x20 i22I2CDATA while AIE amp 0x04 i I2CSTAT if i 0x58 i3 I2CDATA I2CCON 0x40 break break break break break while i I2CCON i amp 0x40 I2CCON 0x80 while AIE amp 0x04 i I2CSTAT if i 0x08 while SCL I2CDATA Ox7E while AIE amp 0x04 i I2CSTAT if i 0x18 I2CDATA i1 amp 0x80 while AIE amp 0x04 i I2CSTAT if i 0x28 I2CCON 0x40 break break break while i I2CCON i amp 0x40 i 0xFF if 1 0xFF Control byte gt 32768 osc wait for I2C interrupt flag handle
138. le effect Typical examples of the latter are brilliance control of a lamp power of a heating element or speed control of a dc motor When the staircase mode is used the output repeats as a strong 1 High Z strong 0 and High Z If a PWM signal is used in a closed loop real time control system the Duty register will be regularly updated as part of normal operation Since this 16 bit register is modified by writing to two 8 bit SFRs there is a possibility that either an interrupt will occur between the writes or the PWM generator will use the Duty register between writes In either case one or more cycles may occur with the wrong 16 bit value and cause undesired perturbation of the controlled system To avoid this possibility writes to the Duty or Period or Tone regis ters should be protected from interrupts and or synchronized with changes on pin P3 3 Since this pin is shared INT1 may be monitored to assist in synchro nization in PWM and square wave modes In PWM mode if the value in the Duty register is larger than that in the Period register the output is held either low or high depending on the state of PPOL bit 5 in PWMCON Table 8 2 PWM Output PPOL Condition Duty Cycle High 0 Period X Duty 0 0 0 0 Duty x Period Intermediate value 0 Duty Period 100 1 Period X Duty 0 100 1 0 Duty x Period Intermediate value 1 Duty Period 0 Pulse Width Modulator and Tone Generator 8 3 PWM
139. ltage reference output VDAC1 MSC1211 12 13 14 only 32 NC No connection RDAC1 MSC1211 12 13 14 only 33 NC No connection same Introduction 1 5 MSC121x Pinout Table 1 2 MSC121x Pin Descriptions continued Description 34 40 43 P2 0 P2 7 Port 2 is an 8 bit bidirectional input output port with alternate functions PORT 2 x Alternate Name Alternate Use P2 0 A8 Address bit 8 P2 1 A9 Address bit 9 P2 2 A10 Address bit 10 P2 3 A11 Address bit 11 P2 4 A12 Address bit 12 P2 5 A13 Address bit 13 P2 6 A14 Address bit 14 P2 7 A15 Address bit 15 44 PSEN Program store enable Connected to optional external memory as a chip enable OSCCLK PSEN provides an active low pulse It is used in conjunction with RST and ALE MODCLK _ to define serial or parallel programming mode When not using external program Low or High memory this pin can also be selected to output the oscillator clock ADC modu lator clock low or high See SFR PASEL F2h ALE PSEN Program Mode Selection at reset NC NC Normal operation 0 1 Parallel programming of FLASH 1 0 Serial programming of FLASH 0 0 Reserved 45 ALE Low Address latch enable Used for latching the low byte of the address during an High access to external memory See PSEN and SFR PASEL F2h 48 EA If EA is low as RST falls and neither ALE nor PSEN is low see above code access will always be to external memory
140. me applications the user may provide other values 3 10 SFR Overview Table 3 2 SFR Overview continued Address Hex Description Name GCL D4h ADC Gain Low least significant byte GCM D5h ADC Gain Middle GCH D6h ADC Gain High most significant byte GCH GCM GCL represents a 24 bit value that sets the gain of the ADC or system Usually val ues are provided by the ADC subsystem when the ADC is instructed to perform a calibration cycle but for some applications the user may provide other values ADMUX D7h ADC Multiplexer Register Selects the sources for the positive and negative inputs of the differential delta sigma ADC This includes nine pins on the MSC121x and an internal temperature related source EICON D8h Enable Interrupt Control EICON contains the enable for the auxiliary interrupts EAI the auxiliary interrupt flag Al the watchdog timer interrupt flag WDTI and a mode bit for serial port 1 SMOD1 which doubles the baud rate when set ADRESL D9h ADC Conversion Results Low least significant byte ADRESM DAh ADC Conversion Results Medium ADRESH Ben ADC Conversion Results Low High most significant byte ADRESH ADRESM ADRESL represents the 24 bit read only value of the latest ADC conversion These registers are not updated on an ADC conversion unless ADRESL has been read from the previous result ADCONO DCh ADC Control 0 Sets the Burnout Detect Internal External voltage refere
141. mode The frequency for the 12C clock is then feu k 2 IPCSTAT 7 0 1 The external clock input or crystal oscillator provides the system clock either directly or via a programmable divider MSC1211 12 13 14 only With a sys tem clock of f MHz the program must write f 1 to the USEC register at FBh in order to provide a clock period as close to 1us as possible This clock pro vides the start and stop timing for the 12C interface and is used in conjunction with FTCON 3 0 at EFh to define the Flash memory write cycle timing The least significant four bits of FTCON are referred to as FWR and should be set so that 1 FWR x USEC 1 x 5 x tgj k is between 301s and 40us The de signer should consider the relative trade offs between crystal frequency and accuracy of baud rate generation versus accuracy of other real time counters By default the output of the USEC divider is used to clock the PWM generator but fc may be selected by setting bit 3 of PWMCON at A1h The operation of the PWM generator is described later Just as USEC is programmed to provide a 1us reference MSECH at FDh and MSECL at FCh are used together to provide a signal with a period of 1ms to clock other counters The period is 256 x MSECH MSECL 1 x tci y which may not be an integer number of milliseconds For example with a 11 0592MHz crystal and MSECH MSECL set to 11058 the period will be 1 000018ms The default value for MSECH MSECL is 399940 and as
142. n the programmer may clear EWDR so that when the tim er expires an interrupt is requested via WDTI bit 3 of EICON at D8h Example 5 1 Watchdog Timer Program File WDT c Watch Dog Timer MSC1210 EVM Switches 1 On SW3 12345678 SW6 12345678 0 0ff 11110111 11110000 include lt Reg1210 h gt include lt stdio h gt define xtal 11059200 sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM code at OxFFF3 void autobaud void data unsigned char i A void main void PDCON amp 0x04 power up WatchDog MSEC xtal 1000 1 1ms tick HMSEC 100 1 100ms tick RedLed 0 Turn Red LED on autobaud Requires CR printf nMSC1210 Watchdog Test printf MnRepeatedly press CR Enter within 3 seconds n RI_O 0 clear received flag in USART WDTCON 0x80 start watchdog and define WDTCON 3 0 30 100ms timeout RedLed 1 Turn Red LED off while 1 while RI 0 wait for key press YellowLed YellowLed Toggle Yellow Led putchar i i i 1 amp Ox5F 32 character sequence if SBUFO amp Ox7F 0x0D Test for CR WDTCON 0x20 restart Watchdog timer WDTCON amp 0x20 with 1 0 sequence in bit 5 RIO 0 clear received flag in USART System Clocks Timers and Functions 5 7 Low Voltage Detection 5 4 Low Voltage Detection Bits 3 and 2 of HCR1 are used to enable a low voltage on either the analog or digital supplies respecti
143. nce 1 25V or 2 5V internal reference VREF Clock source analog buffer and programmable gain amplifier for the delta sigma ADC ADCON1 DDh ADC Control 1 Sets the polarity filter tyoe and conversion mode for the delta sigma ADC It also indicates if an overflow or underflow of the summation register has occurred ADCON2 DEh ADC Control 2 ADCON3 DFh ADC Control 3 ADCONG ADCON2 represent an 11 bit value for the Decimation Ratio of the delta sigma ADC The ADC conversion rate is ACLK 1 64 Decimation Ratio See ACLK at F6h ACC EOh Accumulator The Accumulator is the implicit destination of many operations Instructions that reference the Accumulator implicitly are always shorter and faster than similar instructions that reference it as an SFR However as an SFR it may be used to advantage by instructions such as JB ACC 2 label or PUSH ACC SSCON E1h Summation and Shift Control The result of an ADC conversion is placed in ADRES D9h to DBh but may be automatically added to a 32 bit sum represented by SUMR E2h to E5h The operation of the summation reg ister is controlled by SSCON which includes the number of times ADC conversions are added to the sum and the number of bits that the sum is shifted to the right There is also a mode where 32 bit values provided by the CPU may be added to or subtracted MSC1211 12 13 14 only from the summation register when SUMRO is written If OOh is written to SSCON the 32 bit summation registe
144. nd Jump to Address 0033h 2 10 5 10 6 PAl Pending Auxiliary Interrupt Register isses 10 5 10 7 SPISTART SPI Buffer Start Address 0 eee 10 7 10 8 SPISEND SPI Buffer End Address sssssssssssssse eens 10 7 10 9 SPIRCON SPI Receive Control Register cc cece eee eens 10 8 10 10 SPITCON SPI Transmit Control Register 0 0 c cece eee eee es 10 8 11 1 TMOD Timer Mode Control 000 ccc teen eens 11 3 11 2 TCON Timer Counter Control 0 c cee ete een ees 11 4 11 3 Modes O0 and 1 Operation a iieii nake ia ene eens 11 5 11 4 Control Bit and SFR Summary for Timer Counters 0 and 1 0 0 eee eee 11 7 11 5 T2CON Timer 2 Control 0 cee ess hen 11 8 11 6 Control Bit and SFR Summary for Timer Counter 2 0000 eee eee 11 12 Ti e7 hmerMOdeSs ens euer ib nac ox RR OR RIRs ane or e dh RO Gees bad 11 13 12 1 SCONO and SCON1 Serial Port 0 and Serial Port 1 Control 12 3 12 2 USART Pin and Interrupt Assignments 00000 eese 12 4 12 3 Timer Counter 2 Baud Rate Generation 0 000 eee 12 5 12 4 Timer Counter 1 Baud Rate Generation 0 0 0 12 5 12 5 USART Baud Rate Generation 0 teens 12 6 13 1 Standard and Extended Interrupts 00 cece eens 13 3 13 2 Auxiliary Interrupts with Highest Group Priority
145. nd the decimation ratio which is a right justified 11 bit field in ADCONS at DFh high concatenated with ADCON at DEh low Its default value is 1563 f ADC Output Data Rate fpata Decimation Sao fork where foo TAGLK 1 x64 When the decimation ratio PGA AVpp or temperature are changed the ADC must be recalibrated The mode of operation of the ADC is controlled by ADCON1 at DDh This de termines whether the inputs are interpreted as unipolar or bipolar the type of digital filter and the type of calibration Table 6 5 ADCON1 ADC Control Register 1 ADCON1 SFR DDh Reset Value 30h Bit Name Action or Interpretation Summation Invalid If this bit is set the data in the summation register is invalid Either an overflow or un derflow occurred The bit is cleared by writing a O to it Polarity Write 0 Bipolar such that FSR 0x800000 zero 0x000000 and FSR Ox7FFFFF 1 Unipolar such that FSR 0x000000 zero 0x000000 and FSR OxFFFFFF Settling Mode Write 00 Auto 01 Fast 10 Sinc2 11 Sinc8 Not Used Calibration Control number of tpata periods to complete Write 000 No Calibration default 001 Self Calibration for Offset and Gain 14 010 Self Calibration for Offset only 7 011 Self Calibration for Gain only 7 100 System Calibration for Offset only 7 101 System Calibration for Gain only 7 110 Reserved 111 Reserved Read 0
146. ne if a particular auxiliary interrupt is enabled not masked In this group are interrupts from the Seconds timer ADC Summation ADC Milliseconds timer SPI Transmit SPI Receive l2C Status Analog Low Voltage Detect and Digital Low Voltage Detect Bits read indicate the status of each auxiliary interrupt before masking refer to AIPOL at A4h EIA bit 5 of EICON at D8h is a common enable for all auxiliary interrupts See AISTAT at A7h AISTAT A7h Auxiliary Interrupt Status When read AISTAT indicates the status of each auxiliary interrupt after masking A 1 indicates that an interrupt is pending while a 0 indicates there is either no interrupt or that it is masked See AIE at A6h IE A8h Interrupt Enable Bits written determine if a particular interrupt is enabled not masked In this group are enables for Serial port 1 Timer 2 Serial port 0 Timer 1 external INT1 Timer 0 and external INTO Bit 7 is a Global Enable for this group of interrupts Bits read indicate the status of each enable bit that is returns what was previously written BPCON A9h Breakpoint Control Three bits specify the breakpoint conditions There is a status flag a bit to select either external data memory or program memory and another bit to enable an interrupt BPL AAh Breakpoint Address Low least significant byte BPH ABh Breakpoint Address High most significant byte BLH BPL represents the address of 16 bit breakpoint When this 16 bit address is acc
147. ng s CORO Current Over Range Write COR1 0 Release from high impedance state back to normal mode unless an over range still exists Write 1 NOP Read 0 IDACx is not over current Read 1 IDACx is over 125mA If EODx 0 the indication is immediate If EODx 1 the over current condition must occur for three consecu tive ticks of MSEC EODO Enable Over Current 0 Disable over current detection EOD1 Detection 1 Enable over current detection default SELREFx Select Reference 0 DACx reference is AVpp default 1 DACx reference is REFOUT REF IN pin see SFR DCh and DOMx 1 0 Voltage VDACx x 0 1 2 3 Current IDACx x 0 1 00 Normal output IDAC controlled by IDACxDIS 01 Output off 1k to AGND IDAC off 10 Output off 100k to AGND IDAC off 11 Output off high impedance default IDAC off default Digital To Analog Converters 7 5 DAC Configuration and Control 7 6 Under normal operating conditions the maximum current output of either IDACO or IDAC1 should be no more than 25mA as set by VngE Rpggr with the additional constraints that Vagr is no more than 2 5V and AVpp is at least 1 5V above Vpgr CORx will be set when the current reaches approximately 125mA with a range of 50mA to 225mA due to process variations If a fault condition is to be triggered by CORx ensure that the current capability of AVpp supply is sufficiently large When EODx is 1 and an over current condition is detected CO
148. niin pe ai d SR E eee ede RH ix d Pun odd 6 13 SSCON Summation Shift Control 0 0 2 0 0 6 13 Summation Interrupt Controls 0 0 nett eee eee 6 14 DACSEL ValUSS gic cie desert wet aes Rp RE RR CU ERREUR CR E MEER UAE 7 3 LOADGON SER sce sunset ebb Le rad dled dr REIR ro be P Ra Rs 7 8 DxLOAD Output Modes for DACX ssssuussssssssssss aan E E EA 7 3 DAC Control Registers 0 teeter eens 7 5 PWMCON PWM Control esias suura nianiar aea i i eee m 8 2 PWM OUTPUT 5e terr Rec eX RR a a S Ea E Ea Ru E aware A a 8 3 2C TermiNOlOgy miesi osina eR EE is oh nae a a eth Donnie eU ded Sates TR EG 9 2 I2CCON I2C Control Register cs iicdcindininionindveiedeted ad aha orb Rd Cr 9 6 I2ZCDATA SFR esse redi erasa anA AS AAS E ERE EEEE ET CP kanes 9 7 I2CGM I C General Call Multiple Master Control 0 0c cece eee eee 9 7 I2GSTAT SER zasinu preni a a nidio donde EEN a ll ada dee edat dpud dob edulis 9 8 2C Status Codes oxi d 9 8 PDCON SITO and SPI 22 osi auuiua uta uE E A E cord Manet E aon ut 9 10 Contents ix 9 8 Interrupt Control for lC 2 teen hee 9 10 9 9 Address Allocation x csxeskkxt p ee Eu ME Rede RERO eae weeded a ERE 9 18 10 1 SPICON SPI Control 0 0 ccc cent ee eens 10 3 JU acl 10 3 10 3 P1DDRH Port 1 Data Direction Register 0 0 eee eee 10 4 10 4 SPIDATA SPI Data Register 0 c ccc tte eee ees 10 4 10 5 SPI Interrupts Have Highest Priority a
149. nt ISR forces a transmit interrupt for serial port O by setting TI 0 The characters most often transmitted are 1 and 2 However a 3 may be seen occasionally depending upon the relative timing of the received charac ter with respect to the other interrupts The probability is affected considerably by the rate at which characters are received the value of LIMIT and the effi ciency of the code produced by the compiler Example 13 1 Multiple and Nested Interrupts File Interrupts 4 c MSC1210 EVM Switches 1 0n SW3 12345678 SW6 12345678 0 Off 11110111 11110000 include lt Reg1210 h gt include lt stdio h gt define xtal 11059200 define BAUD 9600 define LIMIT 150 define RATE 100 sbit RedLed p3 4 RED LED on EVM sbit YellowLed P3 5 Yellow LED on EVM sbit syncO P1 0 Port 1 bit O 13 6 Example of Multiple and Nested Interrupts Example 13 1 Continued sbit syncl P1 1 Port 1 bit 1 sbit sync2 P1 2 Port 1 bit 2 sbit sync3 P1 3 Port 1 bit 3 data unsigned int j char level 0 send void process void data char i simulate additional execution time for i 0 i lt LIMIT i void MsecInt void interrupt 6 using 3 data char temp level temp MSINT xead MSINT to remove interrupt AI 0 remove auxiliary flag send 0 level characters 1 to 3 TI O trigger serial output level void SerialOInt voi
150. nterrupt flag MSC1213 1 Enabled 1 Active before masking Read While active no new data will be PM peel in MSC1214 Summation interrupt flag be written to SUMR Cleared by read s fore masking RDSEL 0 or ing SUMRO at E2h value of ESUM RDSEL 1 MSC1210 Write Read 0 Masked 1 Enabled Read Mask value 6 14 0 Inactive or masked 1 Active Not present While active no new data will be written to SUMR Cleared by read ing SUMRO at E2h Accessing the ADC Multi Byte Conversion in C 6 8 Accessing the ADC Multi Byte Conversion in C ADRESH ADRESM ADRESL represent a 24 bit register while SUMR3 SUMR2 SUMR1 SUMRO represent a 32 bit register It is often useful to map both of these to long integers in C but care should be taken For exam ple assuming that the variable sum has been declared to be of type signed long int it is tempting to write sum SUMR3 lt lt 24 SUMR2 lt lt 16 SUMRI lt lt 8 SUMRO However this produces a pattern dependent incorrect value because of the ANSI defined 16 bit integer promotion rules within most compilers for the 8051 family Changing to sum unsigned long SUMR3 lt lt 24 unsigned long SUMR2 lt lt 16 unsigned long SUMR1 lt lt 8 unsigned long SUMRO will produce the expected value but may take between approximately 800 and 1200 machine cycles as compilers call run time libraries to achieve multi bit shifts Since the or
151. nts AIN7 AINCOM 6 2 AVpp Burnout REFOUT Detect REF IN Burnout Offset Detect REF il DAC REFOUT REFIN fuop fparA AX ADC Modulator ADC Result Register Summation Block Gain Calibration Calibration REF IN Register Register OO GOR D3hn Dan Din Deh D5h D4h SUMR esha E ADC Signal Flow and General Description 6 2 ADC Signal Flow and General Description Analog signals from pins AINO to AIN7 AINCOM or internal temperature sensitive diodes are selected independently by two analog multiplexers to pro vide a differential signal to the programmable gain amplifier PGA which may optionally be preceded by a high impedance buffer An analog offset of up to 50 of the full range may be injected into the PGA by the Offset DAC The delta sigma AX ADC can be configured for sampling rate and decimation ratio as well as filter type before its output is passed to digital offset and gain calibration stages to give a 24 bit unipolar or bipolar result ADC conversions can be automatically added to a 32 bit summation register SUMRS to SUMRO which is considerably more efficient than using machine code instructions A defined number of conversions may also trigger an auto matic right shift to produce an averaged value The CPU can control the 32 bit hardware accumulator directly as long as the ADC subsystem is powered up All MSC121x family par
152. olarity 0 SCK idle at logic LOW 1 SCK idle at logic HIGH Bits in Port 1 at 90h that are shared with SPI signals should be left in their de fault states or possibly configured as inputs or CMOS outputs depending on the signal and mode of operation Table 10 2 P1 Port 1 P1 Reset Value FFh Bit Bit Type Bit Type Port Value 4 8051 or CMOS 8051 or input 1 8051 or CMOS r 5 or Open Drain 8051 or input 1 8051 or CMOS 6 8051 or Input or Open Drain 1 7 BES or CMOS 8051 or input 1 or Open Drain NOTE Bits configured as open drain may require a pull up resistor Serial Peripheral Interface SPIt 10 3 SPI Configuration Table 10 3 PIDDRH Port 1 Data Direction Register P1DDRH SFR AFh Reset Value 00h Bit Action or Interpretation 7 6 P17H P17L Port bit type 5 4 P16H P16L 00 Standard 8051 32 P15H P15L 01 CMOS output i 10 Open drain output 1 0 P14H P15L 11 Input Figure 10 2 SPI Clock Data Timing Pot ft agp ap op sp ep v e SCK Cycle SCK CPOL 0 SCK CPOL 1 Sample Input CPHA 0 Data Out Sample Input CPHA 1 Data Out 7 SS to Slave Slave CPHA 1 Transfer in Progress ae a Slave CPHA 0 Transfer in Progress 1 Em Asserted a 8 4 2 First SCK Edge 3 CNTIF Set dependent on CPHA bit 4 SS Negated CPHA and CPOL alter the phase of the data
153. or SPI operations serial clock during 12C operation 1 2 1 3 Port 2 P2 1 2 1 4 Port 3 P3 MSC121x Pinout By default Port 2 acts as eight general purpose input output signals Howev er its alternate function is to provide the upper byte of a 16 bit external address as determined by the EA pin and bit 0 EGP23 of HCR1 If EA is low when RST is de asserted all memory accesses are external and Port 2 continually out puts the high order byte of 16 bit addresses It also outputs bits of an address if EGP23 is 0 and a MOVX instruction is executed regardless of EA This is either the upper byte of the data pointer or the value in MPAGE at 92h accord ing to whether the MOVX instruction references DPTR or Rx respectively When EA causes external memory accesses the read and write strobes at P3 7 and P3 6 respectively are enabled automatically Selective external ac cesses must enable these strobes by clearing bit 1 EGPO or bit 0 EGP23 of HCR1 to 0 If EGP23 1 and EA 1 Port 2 output pins are always derived from its data latch Port 3 provides not only eight independently programmable bits but also alter nate functions as shown in Table 1 4 Table 1 4 Port 3 Alternate Functions Port 1 Bit Name Alternate Function P3 0 RxDO Serial input to USARTO An external receiver is needed for RS232 signals P3 1 TxDO Serial output from USARTO An external driver is needed for RS232 signals P3 2 INTO
154. ork when clocked internally because T2CON 1 0 Overflow Rate 5 65536 RCAP2H ACAPAL fro when clocked from pin P1 0 T2 because T2CON 1 1 Overflow Rate 65536 RCAP2H RCAP2L Serial Ports USARTO and USART1 12 5 Timer Counters 1 and 2 Baud Rate Generation Table 12 5 USART Baud Rate Generation Serial Port T2CON xx00xxxxo PCON 7 SMODO 1 TCON 010000005 TMOD 0100xxxxa fr4 19 660800MHz Baud Rate f 19660800 8192 131072 7 90 x 1 16 T2CON xx00xxxxo PCON 7 SMODO 0 CKCON 4 T1M 0 TCON 010000005 TMOD 0010xxxx TH1 253 fci k 11 059200MHz i ui fork _ 11059200 2 16 12 x 256 THI 384x 3 9900 T2CON xx00xxxxo EICON 7 SMOD1 1 CKCON 4 T1M 1 TCON 010000005 TMOD 0010xxxx TH1 112 fci 11 059200MHz 1 fork _ 11059200 _ 16 4x 256 TH1 64 x 144 1200 T2CON xx00xxxxo EICON 7 SMOD1 1 TCON 010000002 1 fr _ 22118400 TMOD 011 Oxxxxp 716 56 TH 16x 72 19200 TH1 184 fry 22 118400MHz T2CON 001101005 zd TS RCAP2H RCAP2L 65211 2 16 65536 RCAP2H RCAP2L foLk 25MHz _ 25000000 _ 32 x 325 7404 12 6 T2CON 001101105 RCAP2H RCAP2L 65406 fro 10MHz 1 7 1 T fra 2 16 65536 RCAP2H RCAP2L 10000000 46 x 130 7 4808 Mode 0 8 Bit Synchronous 12 5 Mode 0 8 Bit Synchronous In mode 0 serial dat
155. ot be available in all MSC121x devices Shaded SFR addresses in the table are bit addressable Table 3 2 SFR Overview Address Hex Name Description PO 80h Port 0 Controls the byte wide bit programmable input output called Port 0 Each bit in the SFR corre sponds to a pin on the actual part Individual bits may be configured as bidirectional CMOS out put open drain output or input via the Data Direction SFRs for Port 0 See PODDRL at ACh and PODDRH at ADh The same device pins may also be used to provide a multiplexed address and data bus for ac cess to off chip memory In this case bit 1 EGPO of HCR1 must be 0 and the program does not reference PO SP 81h Stack Pointer SP acts as an 8 bit pointer to core RAM It creates a last in first out data structure that is used by the instructions PUSH POP ACALL LCALL RET RETI and interrupt calls The stack is placed in low memory and grows upwards SP is pre incremented and post decrem ented and therefore points to the most recent entry on the stack The default value is 07h but this is often increased so that additional register banks may be ac cessed DPLO 82h Data Pointer 0 Low least significant byte DPHO 83h Data Pointer 0 High most significant byte DPLO and DPHO are read and written independently except for the instruction MOV DPTR data16 but are used together by instructions that reference the 16 bit data pointer called DPTR DPTR is used to address
156. otive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated Preface Read This First About This Manual This users guide describes the function and operation of the MSC121x preci sion ADC and DACs with 8051 microcontroller and flash memory Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully Contents Related Documentation and Tools From Texas Instruments Trademarks Data Sheet Literature Number MSC1210 SBAS203 MSC1211 SBAS267 MSC1212 SBAS278 MSC1213 SBAS323 MSC1214 SBAS323 User s Guide Literature Num
157. ouching the MSC121x with a finger The pattern repeats every 255 characters LLL 6 20 Chapter 7 Digital To Analog Converters This chapter describes the digital to analog converters DACs of the MSC121x Topic Page 7 1 Introduction ere ERES E Essa Erin eux Ee EE Reus 7 2 7 2 DAC Selection s cere Inr ENTE 7 3 73 cContigurationrandiControll TTC 7 5 7 4 DAC Technology and Limitations eeeeeeeeeeeeee 7 7 See DAG ExampleiProgramiberrreeeer reer ere ttt ter terrae tesa et 7 8 7 1 Introduction 7T 1 Introduction The MSC1211 12 contain four mutually independent 16 bit DACs referred to as DACO to DAC3 The MSC1213 14 contain two mutually independent 16 bit DACs referred to as DACO to DAC1 Each produces a voltage as shown in the following equation DAC Voi DAC REF x ge zz where DAC REF is the selected DAC reference DAC is the value written to the DAC register PDDAG bit 6 of PDCON at Fih must be 0 for the DACs to be altered via DACL DACH and DACSEL at B5h B6h and B7h respectively When PDDAC is 1 a DAC may remain active To power down and isolate a DAC output the output mode bits DOMx 1 and DOMx_0 in the appropriate control register must both be 1 default When Vngr is selected the voltage on the REFOUT REF
158. ounter 1 In mode 1 with SM2 1 Rl is activated only if a valid stop bit is received For USARTO SMODO is bit 7 of PCON at 87h For USART1 SMOD is bit 7 of EICON at D8h In modes 2 and 3 with SM2 1 RI is activated only if the ninth received data bit is 1 Serial Ports USARTO and USART1 12 3 Pin and Interrupt Assignments 12 3 Pin and Interrupt Assignments Table 12 2 USAHT Pin and Interrupt Assignments USART 0 SBUFO at 99h USART 1 SBUF1 at Cth Mode 0 m P3 0 P3 1 P1 3 Transmit triggered by write to SBUF Mode 0 P3 0 P3 1 P1 8 Receive triggered by REN 1 and RI 0 Modes 1 2 and 3 Transmit triggered by write to SBUF with TI 2 1 P3 0 P3 1 Received data read via SBUF when RI 1 and REN 1 SFR Bit Name Address Address Address Address Interrupt Enable IE 4 AEh Interrupt Priority IP 4 BEh NOTE In mode 0 the Rx pin is used to receive and transmit synchronous data Consequently the corre sponding data direction bits should be defined as input output or bidirectional as appropriate 12 4 Timer Counters 1 and 2 Baud Rate Generation 12 4 Timer Counters 1 and 2 Baud Rate Generation In asynchronous modes 1 and 3 the overflow rate of either Timer Counter 1 or Timer Counter 2 can determine the receive or transmit baud rate for serial port 0 However in these modes USART1 can only use the overflow rate of Timer Counter 1 The overflow of all Timer Counters passes through a fi
159. ownout Detection 0 Digital Brownout causes reset 1 Digital Brownout reset is disabled default 1 Enable General Purpose I O for Port 0 0 Port 0 is used for external memory P3 6 and P3 7 used for WR and RD 1 Port 0 is used as general purpose I O default 0 Enable General Purpose I O for Ports 2 and 3 5 10 0 Port 2 is used for external memory P3 6 and P3 7 used for WR and RD 1 Port 2 and Port 3 are used as general purpose I O default Breakpoints 5 6 Breakpoints The MSC121x supports hardware breakpoints at addresses in either external data space or code space When a memory access occurs with an address that matches the value in either of two 16 bit breakpoint registers an interrupt is generated The breakpoint registers can aid system debugging but caution is needed be cause of interrupt latency and instruction prefetch Latency may cause two or three instruction cycles to occur after an address match while prefetch may trigger a false interrupt for example when the breakpoint is placed after a con ditional branch that is taken Table 5 7 MCON Memory Control SFR 95h Reset Value 00h Action or Interpretation Write 0 select breakpoint register 0 1 select breakpoint register 1 Bit Read the breakpoint register that created the last interrupt 0 or 1 6 5 0 Always 0 4 1 Undefined 0 RAMMAP Write 0 addresses 0000h to O3FFh in external data memory are on chip RAM default 1 address
160. r 1 Introduction This chapter provides a functional overview of the MSC121x precision analog to digital converter ADC and digital to analog converters DACs with 8051 microcontroller and flash memory Topic Page 1 1 IMSC121x Description cesse 5 5 oes senses eceee ciel incre re 1 2 1 2 MSCI21x Pinout mre enne eser aes enne 1 4 1 399 Enhanced 8051 Core ae nae ae ae ee a 1 12 CA Famy Gompatb My e E E rater terete terete 1 13 Ud ElashiMemoryis eee iere eel 1 13 1 6 Internal SRAM c ue Ex EE E e IMEEM 1 13 1 7 High Performance Analog Functions 1 13 1 8 High Performance Peripherals eeeeeeeee 1 14 MSC121x Description 1 1 MSC121x Description The MicroSystem family of devices is designed for high resolution measurement applications in smart transmitters industrial process control weigh scales chromatography and portable instrumentation They provide cost effective high performance mixed signal solutions The MicroSystem family not only includes high performance analog features and digital processing capability but also integrates many digital peripherals to offer a unique and effective system solution The main components of a MicroSystem product include High performance analog functions L Low power enhanced 8051 microcontroller core J RAM and Flash memory L High performance digital peripherals The enhanced 8051 microcontroller includes du
161. r 16 4 fuop 20 8 171 101 32 Vnpr 32 8 fuop 20 4 113 110 64 Vper 64 16 fMOD 20 74 5 111 128 tVnpr 128 16 fMOD 19 74 5 Analog To Digital Converters 6 7 Offset DAC 6 5 6 8 Offset DAC The input to the PGA may be offset by up to 50 of the range via the offset DAC This 8 bit DAC is controlled by ODAC at E6h with a coding scheme such that the most significant bit represents the sign of the offset while the least sig nificant seven bits represent the magnitude When the magnitude is zero the ODAC is disabled and the voltage into the PGA is not offset Offset Veer ODAC E 0 ron 2PGA 127 where PGA is the gain of the programmable gain amplifier Here VpeF is the voltage on the REF IN pin with respect to REF IN and should not be confused with the internal voltage reference that is with respect to AGND The gain error of the 8 bit ODAC is typically about 1 5 of its range which means its absolute accuracy can be significant in some applications However itis monotonic with an integral nonlinearity of less than 0 25 bits and has a tem perature coefficient of typically 1ppm C It may be used in a predictive man ner with due regard to its range resolution stability and accuracy or it may be calibrated using the ADC ADC Data Rate Filters and Calibration 6 6 ADC Data Rate Filters and Calibration The data rate for ADC conversions is determined by the frequency of the mod ulator clock fiyop a
162. r is cleared Special Functions Registers 3 11 SFR Overview Table 3 2 SFR Overview continued Address Name Hex Description SUMRO E2h Summation Register 0 least significant byte SUMR1 E3h Summation Register 1 SUMR2 ES Summation Register 2 SUMR3 Summation Register 3 most significant byte SUMR3 SUMR2 SUMR 1 SUMRO represent the 32 bit sum and optional shift of a number of ADC conversions See SSCON at Eth ODAC E6h ADC Offset DAC Register An analog voltage of up to half the range of the ADC is set with an 8 bit DAC and used to offset the input voltage to the ADC The ODAC register cannot be used to to extend the analog inputs beyond their specified input range LVDCON E7h Low Voltage Detection Control The voltages present on the analog and digital supply pins may be enabled to generate interrupts if they fall below preset limits For either analog or digital the limits are 2 7V 3 0V 3 3V 4 0V 4 2V 4 5V and 4 7V The analog low voltage interrupt may be generated if AIN7 falls below 1 2V while the digital low voltage interrupt may be generated if AIN6 falls below 1 2V This provides a means of detecting an impending power fail condition while the supply pins themselves are still valid It can also be used to measure other voltages EIE E8h Extended Interrupt Enable Provides selective enables for the watchdog timer INT5 INT4 INT3 and INT2 See WDTI bit 3 in EICON at D8h S
163. re the MSC121x has numerous additional system timers and clock generators The main crystal oscillator provides the system clock at frequency fc either di rectly or via a programmable system clock divider tc 1 fcLk Figure 5 1 MSC121x Timing Chain and Clock Control Oscillator IDLE PCON 0 divide by Timer Lll EN 1 SCENA bi nly TM 4 Counter1 USART NOTE PCON and PDCON are SYSCLK C7h divide by 4 or 12 MSC1211 12 13 14 divide by Timer IE Counter 2 USART O separate SFRs 1 I I I I I I I I I I I i i I I l 1 I MSC121x Core CPU I i a SPICON SPI clock SCK PDCON O 9Ah I i PBGONS 12C clock SCL MSC1211 13 Only 1 PWMCON 3 PWMLOW I PWMH 4 ENT o m aon PWM clock I USEC l ius FTCON Flash write timing FBh 3 0 EFh 30Ls to 40us i I I MSECH MSECL ims FTCON Flash erase timing FDh FCh 7 4 EFh 5ms to 11ms 1 I I l MSINT Milliseconds interrupt FAh see AIE 4 PDCON 1 4 i gt SECINT Seconds interrupt i F9h see AIE 7 L i l MSC1211 12 13 14 Only HMSEC D WDTCON Watchdog interrupt or PEPEE dee ees 4 FE FFh reset see EWU 2 i I PDCON 2 i I I i I I I I I i I I I ADC Ouput Data Rate see AIE 5 ADCON2 DEh fsamP ADC Power Down ADCONO DCh PDCON 3
164. ription Y 7 amp 2 2 3 aes Arithmetic ADD A Rn Add register to A X X X 1 1 4 12 28 2F ADD A direct Add direct byte to A X X X 2 2 8 12 25 ADD A Ri Add indirect data memory to A XIX X 1 1 4 12 26 27 ADD A data Add immediate data to A X X X 2 2 8 12 24 ADDC A Rn Add register to A with carry XIX X 1 1 4 12 38 3F ADDC A direct Add direct byte to A with carry X X X 2 2 8 12 35 ADDC A Ri Add indirect data memory to A with carry XIX X 1 1 4 12 36 37 ADDC A data Add immediate data to A with carry X X X 2 2 8 12 34 SUBB A Rn Subtract register from A with borrow X X X 1 1 4 12 98 9F SUBB Agirect Subtract direct byte from A with borrow X X X 2 2 8 12 95 SUBB A Ri Subtract indirect data memory from A with X X X 1 1 4 12 96 97 borrow SUBB A data Subtract immediate data from A with borrow X X X 2 2 8 12 94 INC A Increment A 1 1 4 12 04 INC Rn Increment register 1 1 4 12 08 0F INC direct Increment direct byte 1 2 2 8 12 05 INC Ri Increment indirect data memory 1 1 4 12 06 07 DECA Decrement A 1 1 4 12 14 DEC Rn Decrement register 1 1 4 12 18 1F DEC direct Decrement direct byte 1 2 2 8 12 15 DEC QRi Decrement indirect data memory 1 1 4 12 16 17 INC DPTR Increment 16 bit data pointer 1 3 12 24 A3 MUL AB Multiply A by B 0 X 1 5 20 48 A4 1 Flags CY AC and OV may also be changed by explicit writes to corresponding bits in the PSW 2 Number of cycles is
165. rnout Detect 2uA Temperature Sensor AVpp AVpp Qe AINCOM Table 6 1 ADMUX ADC Multiplexer SFR D7h Positive input selection Reset Value 01h Negative input selection AINO default positive input AIN1 default negative input AIN2 AINS3 AIN4 AIN5 AIN6 AIN7 AINCOM 6 4 Temperature sensor Requires ADMUX FFh Input Impedance PGA and Voltage References 6 4 Input Impedance PGA and Voltage References When the buffer is enabled the input current is typically 0 5nA impedance is over 1G and the common mode range is from AGND 50mV to AVpp 1 5 V The buffer should be enabled whenever burnout detection is used However when the buffer is not enabled each analog input is presented with a dynamic load such that the mean differential impedance is 7MQ G where G is defined in Table 6 2 The input impedance is lowered and varies with gain however the input range is from AGND 0 1 V to AVpp 0 1 V Table 6 2 Impedance Divisor G for a Given PGA PGA 1 2 4 8 16 32 64 128 G 1 2 4 8 16 32 64 64 When the buffer is not selected the input impedance of the analog input changes with ACLK clock frequency ACLK SFR F6h and gain PGA The relationship is An Impedance Q 1MHz zwe ACLK Frequency G where fork ACLK frequency fack ACLK 4 1 f fcuk MOD 64
166. rogram memory and has a reset value of 0000h Programmer s Model and Instruction Set 4 3 Instruction Types and Addressing Modes 4 3 Instruction Types and Addressing Modes MSC121x instruction types are shown in Example 4 1 For each type of instruction there may be more than one mode of addressing For example there are four different modes associated with the ADD instruc tion as shown in Example 4 2 The MOV instruction has the greatest number of combinations of addressing modes with special variants such as MOVX and MOVC Table 4 3 shows all instructions with their mnemonic description flags cycles clocks and op code If the exact operation is unclear the reader is re ferred to any of the numerous data sheets and books for the 8051 that are gen erally available Example 4 1 Instruction Types Examples MOV R4 0A3H MOVX A DPTR ADDC A 10H SETB 084H SJMP relative address MUL MOV A R5 MOV A R1 DEC R3 CLR C LCALL 16 bit address DJNZ R4 relative address Simple data movement MOV P1 A PUSH PSW ORL P2 5 ANL C FO CJNE A 4 address DA Data movement Data processing Bit operations Program Flow Miscellaneous Example 4 2 Instruction Addressing Modes Hexadecimal Assembly level Addressing Operation instruction Mode Code s ADD A 0C3H Immediate The code byte at PC 1 that is C3h is added to A 24 C3h ADD A R1 Indirect The
167. rrent sources an analog input buffer and an offset DAC Introduction 1 13 High Performance Peripherals 1 8 High Performance Peripherals Additional digital peripherals are included which offload CPU processing and control functions from the core to improve further the overall efficiency In par ticular there is a 32 bit accumulator closely associated with the ADC an SPI compatible serial port with a FIFO buffer two USARTs power on reset browout reset low voltage detection multiple digital ports with configurable I O a 16 bit pulse width modulator PWM a watchdog timer and three timer counters The SPI interface and FIFO buffer allow synchronous serial communications with minimal CPU overhead For the MSC1211 and MSC1213 an 12C inter face may be enabled which replaces the SPI The 32 bit accumulator significantly reduces the processing overhead associ ated with multi byte data It allows automatic 32 bit additions from the ADC and shifts without using CPU registers 32 bit addition is supported with mini mal program interaction IET C PA MSC121x Addressable Resources This chapter provides a detailed description of the MSC121x addressable resources Topic Page 2 1 gt Introduction el eR wie eve nace eee clade ae TREE 2 2 2 2 Program Memory and Data Memory seeees 2 3 2 3 Core Data Memory and Special Functions Registers 2 5 2 4 Beyond 6A4 KBytes ee ETITIEe tener
168. rs and Counters 11 9 Timer Counter 2 11 3 2 16 Bit Timer Counter with Automatic and Forced Reload When RCLK and TCLK are both 0 but CP RL2 is 1 RCAP2H RCAP2L does not contain a captured value as in the previous mode Instead it represents the value to be reloaded into TH2 TL2 Reloading occurs because either TH2 TL2 overflows from FFFFh to 0000h or pin P1 1 T2EX changes from 1 to 0 while EXEN2 is 1 Figure 11 5 Timer Counter 2 16 Bit with Reload Timer 2 Reload Interrupt RCAP2H Timer Counter 2 16 Bit with Reload EXEN2 Pin 1 to 0 ToEX Edge Pin T2 Detection TR2 Control bit TR2 is active high and enables either an internal clock or an external clock on pin P1 0 T2 according to the state of C T2 Specifically when C T2 is 0 TH2 TL2 is a gated timer running at either fc 12 default or fc 4 How ever when C T2 is 1 it is a gated event counter As TH2 TL2 overflows from FFFFh to 0000h the interrupt flag TF2 is set this must be cleared in software If interrupt enables ET2 and EA bits 5 and 7 re spectively of IE at A8h are both 1 the CPU jumps to the interrupt service rou tine at 002Bh Writing a 1 to TF2 causes an interrupt if it is enabled A negative edge on pin P1 1 T2EX when control bit EXEN2 is 1 causes the interrupt flag EXF2 to be set It is ORed with TF2 and may cause a Timer2 interrupt in a manner similar to TF2 EXF2 has to be cleared
169. rupt ADC Interrupt Status Flag Interrupt Poll MSC1211 Write Read Read MSC1212 0 Masked 0 Inactive or masked ADC interrupt flag before 1 Enabled 1 Active masking RDSEL 1 or val MSC1213 ue of EADC RDSEL 0 Read While active no new data will MSC1214 Apc interrupt flag before be written to ADRES Cleared masking RDSEL 0 or val by reading ADRESL at D9h ue of EADC RDSEL 1 MSC1210 Write Read 0 Masked 0 Inactive or masked 1 Enabled 1 Active Not present Read While active no new data will Mask value be written to ADRES Cleared by reading ADRESL at D9h Analog To Digital Converters 6 11 ADC Data Rate Filters and Calibration 6 12 When the MSC121x is reset default values are loaded into the digital offset and digital gain calibration registers associated with the ADC Specifically for offset OCH OCM OCL 00000000h and for gain GCH GCM GCL 5FEC5Ah See Application Note SBAAO099 Calibration Routines and Register Value Generation for the ADS121x Series for additional information Although the ADC will then produce an output that varies linearly with the differential input voltage it will not have the correct scale A program is able to write any desired value to these calibration SFRs but is most likely to set the CAL bits in AD CONO to force an internal calibration for offset and gain CAL 001 A differ ential input of Vpgp REF IN REF IN will then map to a full
170. ry Interrupt Enable AIE O A6 interrupt or Breakpoint interrupt Digital Low Voltage Detect or DLVD Auxiliary Interrupt Status Register AISTAT O A7 Breakpoint interrupt status flag The BP bit in BPCON must be set within the interrupt service routine to clear the interrupt and bit BPSEL in MCON may be read to determine which break point register caused the interrupt 5 12 Chapter 6 Analog To Digital Converters This chapter describes the digital to analog converters ADCs of the MSC121x Topic Page 6 1 ADC Functional Blocks on set 6 2 6 2 ADC Signal Flow and General Description 6 3 6 3 AnalogiinputiStage rere rs 6 3 6 4 Input Impedance PGA and Voltage References 6 5 6 5 OffseUL DAC or rrr rrr emer E EEE 6 8 6 6 ADC Data Rate Filters and Calibration 6 9 6 7 32 Bit Summation Register eeeeeeeeeeeee 6 13 6 8 Accessing ADC Multi Byte Conversions in C 6 15 6 9 ADC Example Program 9 9 aranma EEAS ESVE E 6 17 6 1 ADC Functional Blocks 6 4 ADC Functional Blocks A key feature of the MSC121x that differentiates it from other mixed signal mi crocontrollers is a high precision analog to digital subsystem with a perfor mance that is usually found only in embedded systems with a separate ADC and microprocessor The major elements of the ADC subsystem are shown in Figure 6 1 Figure 6 1 ADC Subsystem Eleme
171. s low at reset 2 4 Program Data Memory and Special Function Registers 2 3 Program Data Memory and Special Function Registers The MSC121x has 256 bytes of on chip SRAM that are closely associated with the core processor as well as over 100 SFRs as shown in Table 2 3 As instructions are executed the address of SRAM or SFRs is either explicit or implicit as shown by the examples in Example 2 1 Table 2 3 On Chip 8051 Memory SFR Base Hex co C8 DO D8 EO E8 FO Bit Addressable Bit 1 CO C7 C8 CF DO D7 D8 DF EO E7 E8 EF FO F7 SFR Base Hex 80 88 90 98 A0 A8 BO Bit Addressable Bit 1 80 87 88 8F 90 97 98 9F AO A7 A8 AF BO B7 Start Content End Designation Address Hex Address Hex Hex SFRs 80 128 byte space for SFRs only directly addressable FF SRAM 80 128 bytes of SRAM only indirectly addressable FF SRAM 30 80 bytes of SRAM directly and indirectly addressable 7F Bit 1 28 40 47 48 4F 50 57 58 5F 60 67 68 6F 70 77 78 7F 2F Bit 1 20 00 07 08 0F 10 17 18 1F 20 27 28 2F 30 37 38 3F 27 Register Bank 3 18 RO R1 R2 R3 R4 R5 R6 R7 1F Register Bank 2 2 10 RO R1 R2 R3 R4 R5 R6 R7 10 Register Bank 1 2 08 RO R1 R2 R3 R4 R5 R6 R7 OF Register Bank 0 2 00 RO R1 R2 R3 R4 R5 R6 R7 07 Bit variables numbered 00h to 7Fh are mapped to SRAM bytes 20h to 2Fh Bit variables numbered 80h to FFh are mapped to SFRs with an address of the form 1xxxx
172. sed speed of execution or achieve the same speed but at a lower clock frequency A lower clock speed results in less system noise and lower power dissipation Figure 1 7 Comparison of MSC121x Timing to Standard 8051 Timing Single Byte Single Cycle Instruction I AE fF LJ LSJ LJ LE PsN LIT LI L awa XX LXX XX XX prr X LXX X 4 Cycles lt gt 12 Cycles a E XXX gt lt X port XXX a Single Byte Single Cycle Instruction MSC121x Timing Standard 8051 Timing When porting existing 8051 code to the MSC121x the designer programmer may need to consider the change in performance associated with all software timing loops and make adjustments where necessary By default hardware timers are still clocked every 12 clock cycles this may be changed to every four cycles if required Software development tools for the 8051 8052 can be used directly to develop programs for the MSC121x Family Compatibility 1 4 Family Compatibility The MSC121x family allows the most cost effective part to be used for each application and ensures a migration path towards larger memories when re quired Code written for the 4K byte part runs unaltered on 8K 16K and 32K parts Between the MSC1210 and MSC1211 the allocation and meaning of pins is similar but not identical because of the different functions that are pro vided However among all the MSC121x devices t
173. seeeeeese 13 9 13 1 Description 13 1 Description The MSC121x extends the interrupt sources provided by the 8051 architecture in two ways First the MSC121x has more interrupts which have program mable priorities of low or high Second the MSC121x has a new group of auxil iary interrupts of highest priority When an interrupt occurs the normal execution of machine level codes is al tered by the forced insertion of an LCALL instruction to an address that de pends upon the source of the interrupt The interrupt itself is generated when the following conditions are present 1 An asynchronous event sets an interrupt flag 2 The corresponding interrupt enable bit is set 3 The group enable bit is set 4 Aninterrupt of equal or higher priority has not already occurred Normal subroutines are entered via LCALL or ACALL instructions which au tomatically pushes the Program Counter PC onto the stack and are termi nated by the RET instruction which recovers the PC from the stack Interrupt service routines ISR are similar but must be terminated by the RETI instruction which not only recovers the PC from the stack but also restores the interrupt level Typically at the start of an ISR the Program Status Word PSW and Accumulator are PUSHed onto the stack and POPed off just before the RETI instruction Once an RETI instruction has returned control to an inter rupted environment and restored the interrupt leve
174. set when SECINT is written the SECINT value will be loaded into the counter immedi ately otherwise it will be delayed until the current count expires When the associated down counter reaches zero it is reloaded with the value in SECINT See Bit 7 ESEC of AIE at A6h MSINT FAh Milliseconds Interrupt The milliseconds interrupt if enabled occurs with an interval given by MSINT 1 x MSEC 1 x tcLk If bit 7 is set when MSINT is written the MSINT value will be loaded into the counter immediately otherwise it will be delayed until the current count expires When the associated down counter reaches zero it is reloaded with the value in MSINT See Bit 4 EMSEC of AIE at A6h USEC FBh Microsecond Register The internal microseconds clock has a period given by USEC 1 x tci K USEC t fci When the associated down counter reaches zero it is reloaded with the value in USEC See FTCON at EFh Special Functions Registers 3 13 SFR Overview Table 3 2 SFR Overview continued Name MSECL MSECH Address Hex FCh FDh Description Millisecond Low Millisecond High MSECH MSECL together represent MSEC which determines the time between millisecond inter rupts given by MSECH x 256 MSECL 1 x tcL When the associated down counter reaches zero it is reloaded with the value in MSECH MSECL HMSEC FEh Hundred Millisecond Clock The hundred milliseconds counter h
175. spectively to bits 7 and 6 of P3DDRL The mode of operation is determined by bits within PWMCON as summarized in Table 8 1 Table 8 1 PWMCON PWM Control PWMCON SFR A1h Reset Value 00h Bit Name Action or Interpretation 7 Not used 6 Not used 5 Period Polarity If 0 the Duty register determines the time the PWM output is high If 1 the Duty register determines the time the PWM output is low 4 PWMSEL PWM Register Select If 0 data written to PWLHI PWMLO at A3h and A2h respectively will be directed to the Period register If 1 data written to PWLHI PWMLO at A3h and A2h respectively will be directed to the Duty register 3 SPDSEL Speed Select If 1 the down counter is clocked every tc x seconds Otherwise the down counter is clocked every tc_K x USEC 1 where USEC is the 5 bit SFR at FBh 2 0 TPCNTL 000 Disable High Impedance HiZ 001 PWM If PPOL is 0 then output is high for D every P and Duty cycle D P If PPOL is 1 then output is low for D every P and Duty cycle P D P 011 Square Low for P High for P 111 Staircase High for P Z HiZ for Z Low for P Z HiZ for Z NOTE P Period 15 0 1 D Duty 15 0 Z Period 15 2 that is the integer part of Period divided by 4 For large P Z is approximately P 4 8 2 Description The PWM output may be filtered to give a dc level or used directly in switching systems with inherent filtering to produce a variab
176. ss 0033h Read Current value of I2C status interrupt before masking I2C Status Interrupt Read 0 I2CSI interrupt inactive or masked 1 12CSI interrupt active AISTAT EICON Enable Auxiliary Interrupt The Auxiliary Interrupt accesses nine different interrupts that are masked by AIE SFR A6h and identified by AISTAT SFR A7h and PAI SFR A5h Write 0 Auxiliary Interrupt disabled default 1 Auxiliary Interrupt enabled EICON Auxiliary Interrupt Flag When PAI indicates that there are no pending auxiliary interrupts that is all auxiliary interrupts have been serviced Al must be cleared by soft ware before exiting the interrupt service routine otherwise the interrupt will occur again Setting Al in software generates an auxiliary interrupt if enabled 0 No Auxiliary Interrupt detected default 1 Auxiliary Interrupt detected 12C Example MSC1211 13 as a Master 9 7 12C Example MSC1211 13 as a Master In order to transmit or receive data via the 12C bus the programmer must write code that generates the sequence of transfers required by each particular 12C de vice The transition between states is reflected in the 12C status codes returned via IZCSTAT Depending upon the frequencies of the system clock and SCL as well as overall complexity the programmer may choose to use inline code or make use of interrupt structures Care should be taken to account for all possible state transitions in case the
177. sters 3 9 SFR Overview Table 3 2 SFR Overview continued Name SBUF1 Address Hex Cth Description Serial Buffer 1 When written SBUF1 provides data for the transmitter associated with serial port 1 When read data is provided by the receive register Serial data is output on pin TxD1 and received on pin RxD1 EWU C6h Enable Wake up When the processor has been placed in the IDLE condition by writing a 1 to bit 0 of PCON at 87h it may be returned to normal operation by an interrupt from either the Watchdog timer INT1 or INTO Bits 2 1 and 0 correspond in order with these interrupt sources and act as selective en ables when set An auxiliary interrupt can also restore normal operation this configuration is enabled with EAI bit 5 of EICON at D8h SYSCLK C7h System Clock Divider By default the crystal oscillator is used as the system clock that is fCLK fosc SYSCLK allows fc x to be fosc divided by 1 2 4 8 16 32 1024 2048 or 4096 and for the change in the divider to be immediate or synchronized with the milliseconds interrupt The speed of the processor and all other timers that use fc will be affected When fc is decreased the power consumption is reduced T2CON C8h Timer Control 2 Timer Counter 2 is not present in the 8051 It was introduced in the 8052 and therefore the MSC121x It has more 16 bit modes of operation than either Timer Counter 0 or 1
178. sumes a 4MHz oscillator Note that if the system divider defined by SYSCLK at C7h is present and active an extra division factor may be present as well The output of MSECH MSECL clocks three different counters with reload lim its set by FTCON 7 4 at EFh MSINT 6 0 at FAh and HMSEC 7 0 at FEh System Clocks Timers and Functions 5 3 Timing Chain and Clock Controls 5 4 They define the Flash memory erase timing between 5ms and 11ms the num ber of counts for the milliseconds interrupt and the hundreds of millisecond in terrupt respectively Each counter repeats in N 1 clocks where Nis the value written to the bits in each SFR If bit 7 of MSINT is set the associated counter will be reloaded as the SFR is written otherwise the new value will be loaded next time the count expires The interrupt associated with SECINT 6 0 at F9h can be set between 1 and 128 counts of the hundred millisecond counter If bit 7 of SECINT is set the associated counter will be reloaded as the SFR is written otherwise the new value will be loaded next time the count expires The frequency of the ADC modulator is given by fork fuod TAGLK 1 x 64 where ACLK is the SFR at F6h The conversion data rate is given by E fuop ABO e PAE Decimator HEU The decimation ratio is ADCON3 2 0 at DFh concatenated with ADCON2 7 0 at DEh plus 1 and the ADC output data rate is fiyop decimation ratio System Clock Divider MSC12
179. t1 1 t2 2 global Variables int 3 void delay void for js20 j 1000 j44 void release void while SCL ensure clock is low I2CCON 0x02 set clock stretch release bit void process data void tl rl amp r2 AND t2 r1 r2 OR delay simulate additional processing time void Aux Int void interrupt 6 using 1 char i i PAI Auxiliary Interrupt status code if i 3 I2CCON 0x20 ACK i I2CSTAT get status and clear I2C interrupt flag switch i slave address W case 0x60 release break received data case 0x80 rl r2 r2 I2CDATA release break stop case 0xA0 break slave address R case 0xA8 process data I2CDATA t1 release break transmit data ACK case OxB8 I2CCON amp 0x20 I2CDATA t2 release break transmit data NACK case OxCO release break default Inter IC 12Ct Subsystem 9 15 12c Example MSC1211 13 as an Interrupt Driven Slave Example 9 3 Continued printf Unexpected condition 4d to be handled n i while 1 AI 0 clear Auxiliary Interrupt flag eise printf Unexpected interrupt 4d to be handled Wn i while 1 void main PDCON Ox5F enable I2C alone autobaud printf MSC1211 as an I2C slave using interrupts n n RI O 0 USEC 21 22MHz xtal Divide by 22 to give 1 us I2CCON 0x20 ACK 0 Normal Slave No stretch Not Filtered I2CG
180. th EXEN2 previously set Write 0 Clear flag if set 1 Set overflow flag and generate interrupt if enabled 5 Receive Clock Select Write 0 or 1 Timer 1 or 2 overflow rate determines the receiver baud rate for USARTO in modes 1 or 3 Setting this bit forces Timer 2 into a 16 bit auto reload mode where the reference clock is fci 2 or pin P1 0 T2 USART 1 can only be clocked from Timer Counter 1 4 Transmit Clock Select Write 0 or 1 Timer 1 or 2 overflow rate determines the transmitter baud rate for USARTO in serial modes 1 or 3 Setting this bit forces Timer 2 into a 16 bit auto reload mode where the reference clock is fci 2 or pin P1 0 T2 USART 1 can only be clocked from Timer Counter 1 3 Timer 2 External Enable Write 0 Ignore negative edges on pin P1 1 T2EX 1 Negative edge on pin P1 1 T2EX sets EXF2 and causes capture or reload depending on the operating mode of Timer Counter 2 Timer 2 Run Control Write 0 Timer 2 cannot be clocked 1 Timer 2 may be clocked 11 8 Timer 2 Counter Timer Select Write 0 Counter Timer is clocked at fc 12 default or fci K 4 or fci 2 in Baud Rate mode 1 Counter Timer is clocked from pin P1 0 T2 Timer Counter 2 Table 11 5 T2CON Timer 2 Control continued T2CON SFR C8h Reset Value 00h Bit Name Action or Interpretation 0 CP RL2 T TEE Select Hold 0 16 bit Timer Counter with auto reload Yes 0 16 bit Timer Counter with capture Yes
181. to a positive supply voltage via a pull up resistor and when the bus is free both lines are high The output stages of 12C interfaces connected to the bus must have an open drain or open collector to perform the wired AND function The original specifi cation for the 12C bus allowed the data transfer rate to be up to 100kbits s how ever this has been extended to 400kbits s in fast mode which is supported by the MSC1211 13 In either mode the maximum rate is determined by the value of the pull up resistors and the capacitance to ground Figure 9 1 12C Bus Connection of Standard and Fast Mode Devices Vpp Pull Up Resistors i Fig SDA Serial Data Line SCL Serial Clock Line i SCLK EE 1 o e ao SCLNI P DATAN1 E 1 1 SCLN2 OUT OUT OUT l prem bog iae I I I I l I I SCL DATA 1 SCL I IN IN n IN E cape hg eee ek pe LC Device 1 DATAN2 ami DATA IN OUT Device 2 Unique START and STOP conditions are identified when SCL is high and SDA changes If SDA changes from 1 to 0 a START condition is created if SDA changes from 0 to 1 a STOP condition is created All ICs connected to the bus including the MSC1211 13 recognize and respond to START and STOP con ditions For a data bit transfer SCL is pulsed high while SDA is stable Figure 9 2 START and STOP Conditions START Condition Figure 9 3
182. ts except for the MSC1210 also support 32 bit subtrac tion 6 3 Analog Input Stage Special function register ADMUX at D7h provides two groups of four bits each that specify the analog source channels for the noninverting positive and in verting negative inputs to the buffer and or the PGA The upper four bits control the noninverting input while the lower four bits con trol the inverting input Codes 00005 to 01115 represent channels AINO to AIN7 respectively Code 10002 selects AINCOM and if both codes are 11112 two temperature sensitive diodes are selected When Burnout Detection is enabled current sources cause the inputs to be pulled to either AVpp or AGND if the selected channel is open circuit as may happen when a resistive sensor is broken The internal diodes are used to provide a temperature sensitive differential voltage of approximately nk In 80 q Tc 273 16 aT P For typical values of and B refer to the respective data sheets For further information about accuracy and calibration see Texas Instruments application report SBAA100 Using the MSC121x as a High Precision Intelli gent Temperature Sensor available for download at www ti com Analog To Digital Converters 6 3 Analog Input Stage Figure 6 2 Input Multiplexer Configuration AINO C AIN1 AIN2 AIN3 Burnout Detect 2uUA AIN4 AIN5 AIN6 AIN7 Bu
183. ual to the pointer used by the SPI to get data from the FIFO SPItxp In effect this clears the transmit FIFO The transmit counter TXcount is also cleared Undefined SCK Driver Enable in Master Mode Write 0 Disable SCK Driver 1 Enable SCK Driver 4 DRV DLY Drive Delay used with Drive Enable DRV EN MOSI for master MISO for slave Write 00 Disable tri state immediately 3 DRV EN 01 Enable output drive immediately B 10 Disable tri state after current byte transfer 11 Enable output drive after current byte transfer 2 TXIRQ2 Transmit IRQ count threshold when in FIFO mode TXIRQ TXIRQ2 TXIRQ1 TXIRQO 000 to 1115 Generates SPI transmit IRQ when transmit count 2TXIRQ or less that is 1 or less to 128 or less See ESPIT bit 3 of AIE at A6h and SPIT bit 3 of AISTAT at A7h 1 TXIRQ1 0 TXIRQO Bit Name Interpretation When Read 7 0 TXCNT The number of bytes in the FIFO TX BUF and TX SR still to be transmitted 0 to 130 This is TXcount 10 8 SPI Examples 10 5 SPI Examples Two examples are shown using the SPI Example 10 1 shows a simple polled environment Example 10 1 SPI Simple Polled Environment File SPIpolled c outputs and receives bytes via SPI MSC1211 EVM Switches 1 0n SW3 12345678 SW5 12345678 0 Off TITITIOTI 11110000 include Reg1211 h include lt stdio h gt sbit RedLed P3 4 RED LED on EVM sbit YellowLed P3
184. ubsystem 9 13 I2C Example MSC1211 13 as a Slave Example 9 2 Continued while i while RI 0 continue until serial character I2CCON 0x20 ACK while AIE amp 0x04 wait for I2C interrupt flag i I2CSTAT get status and clear I2C interrupt flag switch i slave address W case 0x60 release break received data case 0x80 rl r2 r2 I2CDATA release STOP case OxAO break slave address R case 0xA8 process data I2CDATA t1 release break transmit data ACK case OxB8 I2CCON amp 0x20 I2CDATA t2 release break transmit data NACK case OxCO release break default printf Unexpected condition 4d to be handled n i while 1 RIO 0 while RI 0 RIO 0 wait for character 9 14 12c Example MSC1211 13 as an Interrupt Driven Slave 9 9 12C Example MSC1211 13 as an Interrupt Driven Slave In many applications 12C communications occur via interrupts as shown in Example 9 3 It provides the same functional behavior as Example 9 2 ex cept the MSC1211 13 is free to run a foreground task Example 9 3 MSC1211 13 as an Interrupt Driven Slave Slave04i01 c Using interrupts I2C master to from slave MSC1211 at address 1110100 returned data are functions of received data Common release mechanism include stdio h include REG1211 h PRAGMA NOIP code at OxFFF3 void autobaud void char r1 0 r2 0
185. ue of the CPU Transmit Pointer CPUwrp This is where the next byte for transmission is placed when the CPU writes to SPIDATA Writing to SPIDATA increments the transmit counter and increments CPUwrp unless that would make CPUtxp equal to the SPI Receive pointer SPIrxp Table 10 8 SPISEND SPI Buffer End Address SPIEND SFR 9Fh Reset Value 80h Bit Action or Interpretation 7 Always 1 SPIEND Write The end address of the circular FIFO buffer somewhere within SRAM from 80h to FFh The value must be greater than SPISTART The FIFO resides between SPISTART and SPIEND inclusive 6 0 Read The current value of the CPU Receive Pointer CPUrxp This indicates where the next byte will be taken from as the CPU reads SPIDATA Reading SPIDATA decrements the receive counter and increments the SPI Receive Pointer SPIrxp unless the receive counter is zero To sustain data transfers via the SPI while minimizing CPU overhead the FIFO buffer will usually be filled and emptied in bursts by the application software To coordinate this type of activity the SPI Receive Control register SPIRCON at 9Ch and the SPI Transmit Control register SPITCON at 9Dh allow inter rupts to be determined by the amount of data in the buffer A receive interrupt can be set to occur when 2Nor more bytes have arrived and a transmit inter rupt when 2or less remain to be transmitted where Nis between 0 and 7 The receive buffer may be flushed by writing
186. urs after a high to low transition on the receive pin followed by a low level on two of three consecutive samples made at 7 16th 8 16th and 9 16th of the bit time In this way short lived pulses are not regarded as a valid start bit During reception eight bits are shifted into an input shift register which is then loaded into the received SBUF register if 1 Rlis 0 and 2 SMe2is 1 and the stop bit is 1 or SM2 is O that is the state of the stop bit does not matter If these conditions are not met the received data is lost and RI is not set If SBUF is loaded the state of the stop bit is copied into RB8 Transmission is triggered by a write to SBUF and results in a 10 bit frame con sisting of a low level start bit eight data bits and a high level stop bit The start bit begins at the next rollover of the local divide by 16 counter and TI is set at the beginning of the stop bit Figure 12 3 Asynchronous 10 Bit Transmit Timing RX CLK l l l rxdO in Bit Detector Sampling SHIFT eramm D0 X 51 X 92 X 95 X 4 X 05 X 05 X97 STOP RLO LAB Figure 12 4 Asynchronous 10 Bit Receive Timing Write to SBUFO TX CLK SHIFT 12 8 Modes 2 and 3 11 Bit Asynchronous 12 7 Modes 2 and 3 11 Bit Asynchronous Modes 2 and 3 are similar in principle to mode 1 except the data field is ex tended to nine bits During reception nine bits are sh
187. use the MSC121x is based on a machine cycle that consists of four clocks rather than the original 12 Although the most frequently used instructions are three times faster the ag gregate speed improvement for programs written in C language is about 2 3 times faster If application programs are written in C the programmer has little control over the compiler s choice of instructions however for efficient hard real time op erations assembly level routines can be achieved that approach a 3x rate in crease over the 8051 The MSC121x manipulates data via a single 8 bit accumulator A together with eight 8 bit registers RO to R7 The result of all arithmetic and logical op erations is placed in the accumulator which can then be copied to Rn on chip memory or off chip memory by various MOV instructions To the programmer the MSC121x may be modelled as shown in Table 4 1 Table 4 1 8051 Working Registers 4 2 Register B Register n n 0 to 7 Accumulator Data Pointer Low Data Pointer High Stack Pointer Data Pointer High Data Pointer Low Program Counter The Data Pointer DPTR is composed of two 8 bit SFRs accessed as sepa rate bytes However it is used implicitly by some instructions as a 16 bit pointer to either code or data memory The Stack Pointer SP is used to support a first in first out data structure with in core data memory When referenced implicitly as an
188. user selectable See SFR CKCON at 8Eh Programmer s Model and Instruction Set 4 5 Instruction Types and Addressing Modes Table 4 3 Instruction List continued Flags 1 g o g FT T4 2 px p a F o ciao B 5 Code Mnemonic Description Yic jv e Hex DIV AB Divide A by B 0 x 1 5 20 48 84 DAA Decimal adjust A to give 2 BCD nibbles Used X 1 1 4 12 D4 after ADD or ADDC Logical ANL A Rn AND register to A 1 1 4 12 58 5F ANL A direct AND direct byte to A l 1 2 2 8 12 55 ANL A Ri AND indirect data memory to A 1 1 4 12 56 57 ANL A data AND immediate data to A 2 2 8 12 54 ANL direct A AND A to direct byte 2 2 8 12 52 ANL direct data AND immediate data to direct byte 3 3 12 24 53 ORL A Rn OR register to A 1 1 4 12 48 4F ORL A direct OR direct byte to A 2 2 8 12 45 ORL A Ri OR indirect data memory to A 1 1 4 12 46 47 ORL A data OR immediate data to A 2 2 8 12 44 ORL direct A OR A to direct byte 2 2 8 12 42 ORL direct data OR immediate data to direct byte 8 3 12 24 43 XRL A Rn Exclusive OR register to A 1 1 4 12 68 6F XRL A direct Exclusive OR direct byte to A 2 2 8 12 65 XRL A Ri Exclusive OR indirect data memory to A 1 1 4 12 66 67 XRL A data Exclusive OR immediate data to A I 12 2 8 12 64 XRL direct A
189. values 00 to OF sjmp main 4 12 Example 4 3 Continued Max Clocks MSC121x 120 funl mov A R7 anl A 8h cjne A 0 funl 1 sjmp funl_setQ funl_1 mov A R7 anl A 4 cjne A 4 funl 2 sjmp funl_setQ funl 2 mov A R7 anl A 3h cjne A 3 funl_clrQ sjmp funl_setQ funl_clrQ clr OQ sjmp funi z funl_setQ setb Q funl z ret Max Clocks MSC121x 114 fun2 mov A R7 anl A 8 jz fun2 setQ mov A R7 anl A 4 jnz fun2 setQ mov A R7 rrc A mov RO A rlc A anl A RO anl A 1 jnz funl setQ clr Q sjmp fun2 z fun2 setO setb Q fun2 z ret 8051 204 1 8051 252 Examples of MSC 121x Instructions Ratio 1 7 get input values W X Y Z select Z test for Z 0 set Q 1 because Z 0 recover input values select Y test for Y 1 set Q 1 because Y 1 recover input values select W X test for W X 1 clear Q set Q Ratio 2 2 get input values Z Y X W select Z ll eo set Q because Z recover inputs select Y set Q because Y 1 recover inputs W into carry X in bit 0 recover W AND with X get just W amp X set Q because W amp X 1 Q 0 Q 1 Programmer s Model and Instruction Set 4 13 Examples of MSC121x Instructions Example 4 3 Continued Clocks MSC121x 60 8051 fun3 mov A R7 mov C W anl C X orl C Y C Z Q c orl mov ret Clocks MSC121x 64 8051 fun4 mov A R7 anl A 0FH 144 120 add A fun4_t fun4 1 move
190. vely to cause a reset The user may also configure additional low voltages to generate interrupts via LVDCON at E7h When high ALVD or DLVD indicate an active interrupt while a low level indi cates an inactive or masked interrupt Table 5 3 LVDCON Low Voltage Detect Control LVDCON SFR E7h Reset Value 00h ALVDIS ALVD2 Bit 7 DLVDIS DLVD2 Bit 3 Analog Threshold of AVpp Digital Threshold of DVpp 1 X X X Detection Disabled 0 0 0 0 2 7 V default 0 0 0 1 3 0 V 0 0 1 0 3 3V 0 0 1 1 4 0 V 0 1 0 0 4 2V 0 1 0 1 4 5V 0 1 1 0 4 7 V 0 1 1 1 Analog pin AIN7 or digital AIN6 compared with 1 2 V Table 5 4 Low Voltage Detect Low Voltage interrupts have priority 0 High and jump to address 33h shared with other interrupts Address Bit Name Abbreviation Name of related SFR Abbreviation Hex Enable Auxiliary Interrupt EAI Enable Interrupt Control EICON 5 D8 Enable Analog Low Voltage interrupt EALV Auxiliary Interrupt Enable AIE 1 A6 Enable Digital Low Voltage Interrupt EDLVB Auxiliary Interrupt Enable AIE O A6 or Breakpoint interrupt Auxiliary Interrupt flag Al Enable Interrupt Control EICON 4 D8 Analog Low Voltage Detect interrupt ALVD Auxiliary Interrupt Status Register AISTAT 1 A7 status flag Digital Low Voltage Detect or Break DLVD Auxiliary Interrupt Status Register AISTAT O A7 point interrupt status flag 00102 for analog low voltage PAI3 0 Pending Au
191. with R4 0 unipolar mov r4 0 mov r5 adresh mov r6 adresm mov r7 adresl ret Signed long bipolar void return the 3 byte adres to R4567 MSB LSB return signed long int with sign extendsion on R4 bipolar mov r4 0 mov a adresh mov rb a mov r6 adresm mov r7 adresl jnb acc 7 positive mov r4 0ffh positive ret Analog To Digital Converters 6 19 ADC Example Program Example 6 1 Continued Signed long read sum regs void return the 4 byte sumr to R4567 MSB LSB return signed long int sign extension done by hardware read sum regs mov r4 SUMR3 mov rb SUMR2 mov r6 SUMRI mov r7 SUMRO ret end Produces MSC121x Random bit generator with polled ADC Readings begin in 14 3 200ms 3 4 seconds 25 X kkk DE Eoll 95 RRR e OR ee 25 uot uid eet D ME E 25 kk KKKK kK kkk kkk OK 26 RR ee ee d SR e oe FF 26 RR EERE RE RS ss usas 27 kkk k kkkk kk ce e e e kk Aq i Pa E lis AT FERE 49 EE ot ER a ecu RRR OK 28 Eoia PRR o LO Lees susce um PEE Li 2B ll AA EIR EL o o LL 28 xk k o 0 CE o 0 k 28 KK KK k kk ke ke ke ke x ko KK KK 28 3S o UU E RR oe EVER 2B coi ks SERER Lo de c s 29 x X kkk X ok ke k x ke e ke kn o PONE MET E O ee 7 1 Note The temperature is shown in degrees Celsius C followed by the same number of pseudo random characters The temperature was increased from 25 C to 29 C by t
192. xed divide by 16 count er see Figure 11 6 that is reset when a START condition is identified By de fault the overflow output of Timer Counter 1 is also divided by 2 but this may be avoided if SMODx 1 For Timer Counter 1 see Table 12 4 Table 12 3 Timer Counter 2 Baud Rate Generation Configuration Bits Serial port 0 Serial port 0 Serial port 1 in T2CON at C8h Rx Baud Rate Tx Baud Rate Rx and Tx Baud Rate oes SMODO 0 SMODO 1 SMODO 0 SMODO 1 SMOD1 0 SMOD1 1 0 Timer 1 Timer 1 Timer 1 Timer 1 Timer 1 Timer 1 32 16 32 16 32 16 0 Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 1 32 16 16 16 32 16 1 Timer 2 Timer 2 Timer 1 Timer 1 Timer 1 Timer 1 16 16 32 16 32 16 1 Timer 2 Timer 2 Timer 2 Timer 2 Timer 1 Timer 1 16 16 16 16 32 16 SMODO is bit 7 of PCON at 87h SMOD1 is bit 7 of EICON at D8h Table 12 4 Timer Counter 1 Baud Rate Generation Mode of Timer Counter 1 Timer Counter 1 Overflow Rate Timer Counter 1 Overflow Rate Determined by TMOD When Clocked Internally When Clocked Externally at 89h TMOD 6 0 TMOD 6 1 CKCON 4 TIM 0 CKCON 4 T1M 1 CKCON 4 T1M 2 0or 1 fork fork fr 12 x 8192 4 x 8192 8192 fork fork fr 12 x 65536 12 x 655362 65536 fork fok fr 12 x 256 TH1 4 x 256 TH1 256 TH1 Stopped Stopped Stopped NOTES fy is the frequency of the signal at pin P3 5 T1 For Timer Counter 2 the overflow rate is f
193. xiliary Interrupt PAI 3 to PAI O A5 00012 for digital low voltage 5 8 Hardware Configuration 5 5 Hardware Configuration There are two hardware configuration registers HCRO at 7Fh and HCR1 at 7Ehy which form part of 128 bytes of configuration Flash memory They cannot be accessed directly as they are not Special Function Registers Instead ei ther may be read by first writing its address to CADDR at 93h and then reading CDATA at 94h Writing to HCRO or HCR1 can only occur during serial or paral lel device programming when they are mapped to code space addresses 807Fh and 807Eh respectively Table 5 5 Hardware Configuration Register 0 HCRO Non SFR address 7Fh accessed indirectly via SFR CADDR at 93h Erased Value FFh Bit Name Action or Interpretation Enable Programming Memory Access security bit 0 After a reset following programming mode Flash memory can only be accessed in User Application Mode UAM or mass erased 1 Fully accessible default Program Memory Lock PML has priority over RSL if RSL 0 0 Enable writing to program memory in UAM 1 Disable writing to program memory in UAM default Reset Sector Lock 4 KB of Flash memory from 0000h to OFFFh 0 Enable reset sector writing 1 Disable reset sector writing default Enable Boot Rom 2 KB of read only memory from F800h to FFFFh 0 Disable Internal Boot ROM 1 Enable Internal Boot ROM default Enable Watchdo
194. y and exter nal data memory which may be located on chip or off chip Accessing off chip memory requires additional circuitry and the use of numerous pins Additional memory is gained at the expense of other functions associated with these pins Table 2 1 Program Memory and External Data Memory Addresses Program Code Memory 1 Data Memory 1 FFFF 2K Boot ROM F800 if EBR is 1 30K off chip F7FF 28K off chi 8800 8K off chip 87FF 1 K on chip 1K on chip 8400 or off chip or off chip 83FF 1K off chi 16K 8000 TED ZEFF 16K K 4000 9 2 3EFF 8K 4K 2000 1FFF 4K 4K 1000 OEF 1K on chip 0000 or off chip Y2 Y3 Y4 and Y5 suffix on part code indicates total FLASH of 4K 8K 16K and 32K respectively This may be partitioned between code and external data spaces The shaded cells shows the areas that can be defined All MSC121x devices have 2 KBytes of on chip Boot ROM This is enabled by default see EBR bit 4 of HCRO and gives the user program access to a number of useful routines When disabled the space is available for external program memory To permit off chip expansion all MSC121x devices have a region for external code and or data memory that is 8800h to F7FFh boot ROM enabled or 8800h to FFFFh boot ROM disabled for code and 8800h to FFFFh for data By default bit 0 of MCON RAMMAP SFR 95h is 0 and 1 KBytes of on chip SRAM appears only as external data memory between addresses 0000h and

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