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Lightning (DSPC-8681E) User Guide

1. 16 2 5 Example Simple Web Server 16 2 6 Example PC DSP 0 4 4 16 2 7 Example Image Processing ziii 16 2 8 Patch Platform Library 17 3 DSP Progr m Loader 18 3 1 Host System 18 3 2 Metro 18 3 2 1 Build the Driver and Demo 18 3 3 Installation Usage 19 Trusted ePlatform Services AD ANTECH Advantech Confidential 3 4 DSP Loader DI 20 3 4 1 Query DSP Information 20 3 4 2 Download DSP Program 21 3 4 3 DSP Memory Bd ecrire tr etit eua 22 3 4 4 DSP Memory 22 3 4 5 Download DSP Binary 22 3 4 6 Save DSP Memory as a Binary 23 3 4 7 DSP em 24 4 Ref
2. 667 PCIEEP IOCTL GET BAR INFO Get the current BAR information of the specified window 667 PCIEEP IOCTL DMA BUFFER ALLOC Allocate buffers of contiguous in physical memory for specified DSP Trusted ePlatform Services AD ANTECH Advantech Confidential Tl667x PCIEEP IOCTL DMA BUFFER FREE Free all allocated buffers for specified DSP Tl667X PCIEEP IOCTL GET PCI INFO Get PCI Information of DSP Table 2 2 Kernel Mode Driver I O Control Code List A user mode driver is also provided Developers can implement their own application based on this user mode PCle driver The APIs are listed below Export API Description pcie_drv_open Open the devices which are registered by kernel driver and set up the access of PCle BAR regions pcie_drv_close Close the devices and free all allocated resources pcie_drv_set_ep_config Set PCle endpoint related configurations such as interrupt and privilege register pcie drv dsp set entry point Write the entry point to boot magic address The boot magic address is the lasted DWORD of L2 memory for C6678 the address is 0x0087FFFC pcie drv dsp write Write to DSP memory using memcpy over PCle pcie drv dsp read Read from DSP memory using over PCle pcie drv dma mem alloc Allocate contiguous host memory for specified DSP pcie drv dma mem free Free the allocated physic
3. Lightning PCIE dsp loader driver module sh unload sh The device information is shown by dmesg command Lightning PCIE dsp loader driver module dmesg dspc868x pcie ep Found TI667x PCIe EP QOxffff8801d536e000 dspc868x pcie ep Found TI667x PCIe EP QOxffff8801d536f000 dspc868x pcie ep Found TI667x PCIe EP QOxffff8801d4848000 dspc868x pcie ep Found TI667x PCIe EP QOxffff8801d4849000 dspc868x pcie ep detect 4 DSP in this system pci 0000 05 00 Major 249 Minor 0 assigned pci 0000 05 00 Added device to the sys file system pci 0000 05 00 BAR Configuration pci 0000 05 00 Start Length Flags pci 0000 05 00 0 8400000 00004096 0 00040200 0000 05 00 Oxdf000000 16777216 0 00042208 0000 05 00 0xde000000 16777216 0 00042208 0000 05 00 0xdc000000 33554432 0 00042208 0000 05 00 0000 06 00 0000 06 00 0000 06 00 667 registers mapped to Oxffffc900117ec000 Major 249 Minor 1 assigned Added device to the sys file system BAR Configuration pci 0000 06 00 Start Length Flags pci 0000 06 00 0x 8300000 00004096 0 00040200 0000 06 00 0xd7000000 16777216 0 00042208 0000 06 00 0xd6000000 16777216 0 00042208 0000 06 00 0xd4000000 33554432 0 00042208 0000 06 00 0000 07 00 0000 07 00 0000 07 00 667 registers mapped to Oxffffc900117ee000 Major 249 Minor 2 assigned
4. The 2 stage boot loader will configure PLL and PCIE BAR window when DSP boots from 12 EEPROM Table 1 3 and Table 1 4 show the detailed configuration of Switch 1 Figure 1 4 2 Boot Mode PCIE boot Setting Switch 1 pins 4 3 2 1 Boot mode Endian Table 1 3 Switch 1 pin decoding Bit Field Value Description 4 2 111 Emulation boot mode 110 2 boot mode Boot from address 0x51 32bits address BAR setting 100 2 boot mode Boot from address 0x50 64bits address BAR setting Trusted ePlatform Services AD ANTECH Advantech Confidential Others Reserved 1 Endian 0 Little endian 1 Big endian Table 1 4 Switch 1 Configuration Bit Field Description CAUSION It is a known issue when DSPC 8681E boots through secondary boot loader by 2 boot mode the DSP may not complete boot process before BIOS scanning PCle device tree Usually DSPC 8681E can be detected after restart BIOS or reboot Linux system The four PCle switch LEDs should begin flashing to indicate the status of PCle interface connection to individual DSP The placement of 4 LEDs is shown in Figure 1 5 for DSP 2 and DSP 3 and Figure 1 6 for DSP 0 and DSP 1 Figure 1 5 Two PCle Switch LEDs on Front Side Trusted ePlatform Services AD ANTECH Advantech Confidential m pum ml Comme 40 Figure 1 6 Tw
5. amp The following example read 7496169 bytes DSP 1 at DDR beginning address 0x80000000 by using DMA and saves as test image output jpg Lightning PCIE dsp loader app bin dsp loader loadbinary 1 0x80000000 0 1 home advantech test_image jpg Load Binary file home advantech test_image jpg to DSP1 start address 0x80000000 Size 0x00000000 Written to dsp 7496169 bytes Time measured 16225 us Trusted ePlatform Services AD ANTECH M Advantech Confidential Load Binary OK Lightning PCIE dsp loader app bin dsp loader savebinary 1 0x80000000 7496169 1 home advantech test image output jpg Save Binary file home advantech test image output jpg from DSP 1 start address 0x80000000 Size 0x007261e9 Saved from dsp 7496169 bytes Time measured 21871 us Save Binary OK 3 4 7 DSP Local Reset The command syntax is dsp loader reset chip The command is to do a local reset of DSP The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC The following example reset DSP 0 Lightning PCIE dsp loader app bin dsp loader reset 0 Iterations waited for entry point to clear 1 Dsp 0 DSP Reset success Trusted ePlatform Services AD ANTECH Advantech Confidential 4 Reference Implementations 4 1 Patch of Platform Library and NDK Library The example programs have to link with DSPC8681 platform library and NDK library A develope
6. back data blocks from DSP memory to PC PC interrupts DSP DSP interrupts PC Emulate console output The implementation enables the DSP to display messages to PC This could be helpful when developing and debugging DSP applications ee 4 5 1 Build Instruction Steps to build DSP program are listed below Trusted ePlatform Services AD ANTECH Advantech Confidential 1 Import the demo evmc6678l CCS project from Lightning_PCIE examples ipc dsp evmc6678I directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Select DSPC8681E as active configuration 3 Clean the demo evmc6678l project and re build the project After build is completed demo_evm6678l out and demo evm6678l map be generated under Lightning_PCIE examples ipc dsp evmc6678l bin DSPC8681E directory 4 5 2 Usage User can use shell script file Lightning PCIE examples script DSPC8681 E ipc sh to load demo evm6678l hex into the specific DSP The script will do following four jobs Load dem ps qe m Convert out to hex o evm6678l hex to the specified DSP Run the PC DSP intercommunication demo repeat 1000 times Run the console output demo There two Steps to launch IPC example 1 Perform init 1000 sh to initialize DDR 2 Runipc sh The following example captures the result of running Lightning PCIE examples script DSPC8681 E ipc sh Refer to 4 5 4 DSP Demo Program to get detailed pro
7. sia Jak Advantech Confidential image bin DSPC8681E image_processing_evmc66781_master hex to 0 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8681E image_processing_evmc66781_master hex to 1 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8681E image_processing_evmc66781_master hex to 2 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8681E image_processing_evmc66781_master hex to 3 0 start address 0x0c000000 Load HEX OK 3 Please refer to the Figure 4 8 Input the BMP image form the internet browser The URL of DSPs are http 192 168 1 10X X 1 4 Select the number of core and image path for processing 4 The output result is shown in Figure 4 9 Trusted ePlatform Services AD ANTECH non ek Advantech Confidential G Multicore Image Processing Demonstration Windows Internet Explorer Qo 192 168 1 101 sji RORE Multicore Image Processing Demonstration Hl 10 192 168 1 104 oS Multicore Image Processing Demonstration Number of Cores Eight v Image processing function Edge Detection Select Image to Process les image 7 8 1920x1080 5 93MB 8 Lightning PCIE examples amp mage processing mages evmc6678 1920x1080 5 93MB bmp Note 8 24 bit bitmap BMP images are supported BIOS MCSDK Image Processing Demonstrat
8. 0000001f 00000020 0x607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 0x607220 00000029 0000002a 0000002b 0000002 00000024 0000002 0000002 00000030 0x607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 0x607260 00000039 0000003a 0000003b 0000003 0000003d 0000003e 0000003 00000040 0x607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048 0x6072a0 00000049 0000004 0000004b 0000004 0000004d 0000004e 0000004 00000050 0x6072c0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058 0x6072e0 00000059 0000005 0000005b 0000005 0000005d 0000005 0000005 00000060 0 607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068 0 607320 00000069 0000006 00000066 0000006 00000064 0000006 00000067 00000070 0 607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078 0 607360 00000079 0000007 0000007 0000007 00000074 0000007 0000007 00000080 0 607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088 0 6073 0 00000089 0000008 00000086 0000008c 00000084 0000008e 0000008f 00000090 0 6073 0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098 0 6073 0 00000099 0000009 00000096 0000009 00000094 0000009e 0000009 000000a0 Synchronizing done PCIe Hello World Example this is 05 1 Debug GEM INTC Configuration Completed Debug 0 Configur
9. 00003a 00000036 0000003 00000034 0000003e 0000003f 0 607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047 0 6072 0 00000048 00000049 0000004 00000046 0000004 00000044 0000004e 0000004f 0 6072 0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057 0 6072 0 00000058 00000059 0000005 00000056 0000005 00000054 0000005e 0000005f 0 607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067 0 607320 00000068 00000069 0000006 00000066 0000006 00000064 0000006 0000006f 0 607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077 0 607360 00000078 00000079 0000007 00000076 0000007 00000074 0000007 0000007 0 607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087 0 6073 0 00000088 00000089 0000008 00000086 0000008 00000084 0000008 0000008f 0 6073 0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097 0 6073 0 00000098 00000099 0000009 00000096 0000009 00000094 0000009e 0000009 receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation 0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 0x6071a0 00000009 0000000 0000000b 0000000 0000000d 0000000e 0000000 00000010 0x6071c0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 0x6071e0 00000019 0000001a 0000001b 0000001c 00000014 0000001
10. 0069 0000006 00000066 0000006 00000064 0000006e 0000006f 00000070 0 607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078 0 607360 00000079 0000007 00000076 0000007 00000074 0000007 0000007 00000080 0 607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088 0 6073 0 00000089 0000008 00000086 0000008 00000084 0000008e 0000008 00000090 0 6073 0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098 0 6073 0 00000099 0000009 00000096 0000009 00000094 0000009 0000009 000000 0 4 6 Image Processing Demonstration The image processing program is modified from the example codes in MCSDK This application shows implementation of an image processing system using a simple multicore framework This application will run Tl image processing kernels imagelib on multiple cores to do image processing eg edge detection etc on an input image Slave Processing Node s Core 0 SYSIBIOS Master Processing Node Core 1 NDK DHCP HTTP 8YS BIOS SYSIBIOS Core N SYS BIOS Figure 4 7 Image Processing Application Software Framework The user input image will be BMP image The image will be transferred to external memory using NDK http The Ethernet port on the bracket of the Lightning board must be connected Trusted ePlatform Services AD ANTECH Advantech Confidential to an external Ethernet switch support gigab
11. 0084 0000008 0000008f 0 6073 0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097 0 6073 0 00000098 00000099 0000009 00000096 0000009 00000094 0000009 0000009f receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation 0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 Trusted ePlatform Services AD ANTECH hob ef Advantech Confidential 0x6071a0 00000009 0000000a 0000000b 0000000c 0000000d 0000000e 0000000f 00000010 0 6071 0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 0 6071 0 00000019 0000001 00000016 0000001 00000014 0000001e 0000001 00000020 0 607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 0 607220 00000029 0000002 00000026 0000002 00000024 0000002 0000002f 00000030 0 607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 0 607260 00000039 0000003a 00000036 0000003 00000034 0000003 0000003f 00000040 0 607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048 0 6072 0 00000049 0000004 00000046 0000004 00000044 0000004 0000004f 00000050 0 6072 0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058 0 6072 0 00000059 0000005 00000056 0000005 00000054 0000005 0000005 00000060 0 607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068 0 607320 0000
12. 2 13 Holland Huang 1 The SW package 0 7 support MCSDK version 2 01 02 05 2 Add individual platform library for DSPC8681 and DSPC8682 in patch of MCSDK 3 Add user mode PCle driver and DSP local reset function 4 Add DSP init script to support DSP running at 1GHz and 1 25GHz 5 IPC example modification and support PCle Trusted ePlatform Services AD ANTECH Advantech Confidential interrupt in DSP SYS BIOS application Trusted ePlatform Services AD ANTECH Advantech Confidential Content soo dU mem 7 1 1 Hardware Description MP 7 1 2 DSPG 8581E Block 8 1 3 8 1 4 9 1 5 HyperLink 444 9 1 6 Serial RapidlO Interia6Ge ico ie eiie neta secta de 9 1 7 6 erp 9 1 8 T 10 1 9 Hardware Environment Setting Leur rur eremi orti 11 2 COMIBII Ga feni 14 2 1 API Interface of DSP 14 2 2 DSP Program Loader Utility 16 2 3 Example DDR3 dicat dus 16 2 4 Example DSP Initialization for Local
13. 781 out gt text web client evmc66781 DSPC8681E client evnc66781 out gt const web client evmc66781 DSPC8681E client evnc66781 out gt Switch 1 web client evmc66781 DSPC8681E client evmc66781 out gt vecs web client evmc66781 DSPC8681E client evnc66781 out gt Switch 2 web client evmc66781 DSPC8681E client evnc66781 out gt cinit Load HEX image bin DSPC8681E client_evmc66781 hex to 0 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8681E client evmc6678l hex to 1 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8681E client_evmc66781 hex to 2 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8681E client_evmc66781 hex to 3 0 start address 0x80300000 Load HEX OK Check the result by internet browser The URL of DSPs are http 192 168 1 10X X 1 4 The result is shown in Figure 4 4 and Figure 4 5 Trusted ePlatform Services AD ANTECH Advantech Confidential BRV REY Q Q HAG s 60 2 c L J FEO d heen 192 168 1 104 te 1 GNAI PROCESSING TCP IP Sample Client Program This page demonstrates how TCP IP can be used to interface your DSP application to a standard WEB browser Ce View realtime TCRAP stack statistics This this a small example page being served out of a RAM file sy
14. Added device to the sys file system BAR Configuration pci 0000 07 00 Start Length Flags pci 0000 07 00 0 8200000 00004096 0 00040200 0000 07 00 Oxcf000000 16777216 0 00042208 0000 07 00 0xce000000 16777216 0 00042208 0000 07 00 0 000000 33554432 0 00042208 0000 07 00 0000 08 00 0000 08 00 0000 08 00 1667 registers mapped to Oxffffc900117f0000 Major 249 Minor 3 assigned Added device to the sys file system BAR Configuration 0000 08 00 Start Length Flags pci 0000 08 00 0 8100000 00004096 0 00040200 0000 08 00 0 7000000 16777216 0 00042208 0000 08 00 0 6000000 16777216 0 00042208 Trusted ePlatform Services AD ANTECH se ae Advantech Confidential pci 0000 08 00 0 0xc4000000 33554432 0 00042208 pci 0000 08 00 0 TI667X registers mapped to Oxffffc900117f2000 3 4 DSP Loader Utility DSP loader offers the functions to load the program into DSP memory and notify the DSP to run program 3 4 1 Query DSP Information The command syntax is loader query list or dsp loader query I dsp loader query chip The command is to display the PCI information of DSP which are installed in the system The more detailed information will be displayed when user specify the chip parameter The chip are the number o
15. EX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX bin DSPC8681E image_processing_evmc6678l_slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 hex to 2 2 hex to 2 hex to 2 hex to 2 hex to 2 hex to hex to hex to hex to hex to hex to to hex hex to Trusted ePlatform Services AD ANTECH
16. HEX image start address Load HEX OK bin DSPC8681E image_processing_evmc66781_slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 bin DSPC8681E image processing evmc66781 slave 0x0c100000 hex hex hex hex hex hex hex hex hex hex hex hex hex to 0 to 0 to 0 to 0 to 0 to 1 to 1 to 1 to 1 to 1 to 1 to 1 to 2 Trusted ePlatform Services AD ANTECH Advantech Confidential Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load H
17. Trusted ePlatform Services AD ANTECH Advantech Confidential ieee Lightning DSPC 8681E User Guide Revision v0 7 Holland Huang Job Supervisor Signature Initiated by Sungyi Chen Title Senior Engineer Dick Lin Job Software Manager Signature Approved Title by pnd Job Signature Title Approved Release Release Date Status Trusted ePlatform Services AD ANTECH son Advantech Confidential Revision History Version Date Author Description 0 1 08 08 11 Sungyi Chen Initial draft Holland Huang 0 2 09 26 11 Holland Huang The version number of this document is change to synchronize with SW package 0 2 0 3 10 20 11 Jason Hsueh 1 The SW package 0 3 support MCSDK version 2 0 3 15 2 Add image processing example 0 4 01 11 12 Holland Huang 1 Add memory read write function in DSP loader 2 Driver modification to ensure stability of memory read write 3 Support both Legacy and MSI interrupt in ipc example 0 5 06 19 12 Holland Huang 1 The SW package 0 5 support MCSDK version 2 00 09 21 2 Support memory writing into chip cfg space in PCIe driver 3 Add DMA read write function in PCle driver 0 6 11 16 12 Holland Huang 1 The SW package 0 6 support Samsung 4G DDR module 2 Add subsystem ID and subsystem vendor ID 3 Add 2 boot from address 0x50 to support 64bits address BAR 0 7 04 0
18. a specified DSP The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 core core is used to notify individual core range from 0 to 7 within DSP to run 3 image entry point image entry point is the start address of the loaded image User can find the entry point symbol of c intOO in the map For example init map information is displayed in List 3 1 The reader can find the entry point of the program in the top of map file kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk TMS320C6x Linker PC v7 2 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk gt gt Linked Mon Aug 15 15 03 07 2011 OUTPUT FILE NAME lt bin init out gt ENTRY POINT SYMBOL _c_int00 address 008362a0 List 3 1 entry point in the init map 4 image file name image file name is the full path of hex file name which is loaded into DSP The following example demonstrates how to load Lightning PClE bin init hex DSP image for DDR initialization into DSP 1 and use CPU 0 to run DSP image Lightning_PCIE dsp_loader app bin dsp_loader load 1 0 0x008362A0 Lightning_PCIE bin init hex Load HEX image Lightning_PCIE bin init hex to 1 0 start address 0x008362A0 Load HEX OK Trusted ePlatform Services a Advantech Confidential Note Image entry point depends on DSP i
19. adline5 dev deb or libreadline5 dev rpm for Redhat families libreadline gplv2 dev for kernel 3 5 and above 4 DSP development tool Code Composer Studio v5 1 or higher MCSDK for TMS320C66x Processors V2 01 02 05 please refer to web site http software dl ti com sdoemb sdoemb public sw bios mcsdk 02 01 02 05 DS html 3 2 Build Instruction 3 2 1 Build the Driver and Demo Application The driver is closely tied to Linux kernel running on PC therefore it must be rebuilt to work with the supporting kernel The commands for building PCIE driver are listed below Lightning_PCIE make clean Lightning PCIE make This compiles the PCle kernel driver user mode driver dsp loader utility and pc site application of ipc example The Module libraries can be found the dsp_loader driver module directory The user mode driver library will be generated in the dsp loader driver lib directory The dsp loader executable can found dsp_loader app bin directory The pc site application dsp_demo executable will be produced in the examples ipc pc bin Trusted ePlatform Services AD ANTECH Advantech Confidential 3 3 Installation and Usage Linux host PCIE driver is used to create mapping between PC memory and DSP memory Users can run the shell script load sh to load and install the driver The script unload sh is used to unload the driver Lightning PCIE dsp loader driver module sh load sh
20. al memory and unmap all host memory for specified DSP pcie drv dma write Write data to DSP memory from provided contiguous host memory pcie drv dma read Read data from DSP memory to provided contiguous host memory pcie drv dsp int select Wait interrupt signal from DSP pcie drv get dsp dev info Get PCle information of all DSP devices Table 2 3 User Mode Driver API List Trusted ePlatform Services AD ANTECH hob ef Advantech Confidential 2 2 DSP Program Loader Utility DSP program loader utility contains a hex parser and is used to load hex files into DSPs and notify DSPs to run program 2 3 Example DDR3 Initialization The DDR3 initialization example contains CCS project settings to build a boot image This program will initialize DDR by reading parameter that stored in EEPROM address 0x51 offset 65500 bytes after software 0 6 release otherwise the Samsung 2Gb and Micron 4Gb DDR module initialization parameter are hard code setting DSP will wait loader utility to load the next program after DDR initialization finished A file format conversion tool provided by TI is also included and can be used to convert out file format into hex file format 2 4 Example DSP Initialization for Local Reset The DSP reset example contains CCS project settings to build a boot image This program is a part of DSP local reset procedure By running this program coreO will poll PCle legacy INTA that i
21. atically The following steps set up image processing program on 4 DSPs 1 Perform init 1000 sh to initialize DDR 2 Run image processing sh it will convert out file to hex and load the images to each DSP Trusted ePlatform Services AD ANTECH Advantech Confidential Lightning_PCIE examples script DSPC8681E image_processing sh 4 Translating to Intel format image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt text c 1 100 image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt text image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt const image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt switch image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt vecs image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt cinit Translating to Intel format image processing ipc evmc66781 master DSPC8681E image processing e vmc66781 master out gt text _c_int00 image processing ipc evmc6678 master DSPC8681E image processing e vmc66781 master out gt text image processing ipc evmc66781 master DSPC8681E image processing vmc66781 master out gt const 1 image processing ipc evmc6678 master DSPC8681E image pro
22. ation Debug 0 Configuration Completed 4 5 3 PC Site Utility The PC site demo application dsp_demo contains two commands demo and console function Trusted ePlatform Services o Advantech Confidential 4 5 3 1 Inter Communication The demo command is used to demonstrate the negotiation between DSP and PC host dsp demo will perform the data blocks read write and wait the interrupt signal which is sent from PCle driver The command syntax is dsp demo demo chip chip the number of DSPs parameter selects which DSP will be accessed by PC 4 5 3 2 Console Simulation This command is for creating a virtual console to display the debug message by the program running in specific DSP chip from DSP 0 to DSP 3 and cores core from CPU cores to CPU 7 The command syntax is dsp demo console chip core The following example displays the debug message of demo evm6678l hex DSP demo program which is executed by CPU 0 in DSP 0 Lightning PCIE examples ipc pc bin dsp demo console 0 0 Synchronizing done PCIe Hello World Example this is DSPO Debug GEM INTC Configuration Completed Debug 0 Configuration Debug 0 Configuration Completed DSPO generated interrupt to host DSPO receive interrupt from host DSPO finish operating dummy data Note DSP program demo evm6678l hex should be downloaded to DSP device first before issuing
23. cedure of the DSP demo program Lightning PCIE examples script DSPC8681E ipc sh 1 Translating to Intel format ipc dsp evmc66781 bin DSPC8681E demo evm66781 out gt text int0O ipc dsp evmc66781 bin DSPC8681E demo evn66781 o0ut gt text ipc dsp evmc66781 bin DSPC8681E demo evm66781 o0ut gt const ipc dsp evmc66781 bin DSPC8681E demo evm66781 out gt csl ipc dsp evmc66781 bin DSPC8681E demo evm66781 out gt switch ipc dsp evmc66781 bin DSPC8681E demo evm66781 out gt cinit Load HEX image bin DSPC8681E demo_evm66781 hex to 1 0 start address 0x00840000 Load HEX OK DDR of DSP is initialized ready to write dummy data to DSP dump dummy buffer before DSP operation 0x607180 0x6071a0 0 6071 0 0 6071 0 0 607200 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 00000009 0000000 00000006 0000000 00000004 0000000 0000000f 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 0000001 00000016 0000001 00000014 0000001 0000001 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 Trusted ePlatform Services AD ANTECH Advantech Confidential 0x607220 00000028 00000029 0000002 0000002b 0000002 00000024 0000002 0000002f 0 607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037 0 607260 00000038 00000039 00
24. cessing e vmc66781 master out gt const 2 image processing ipc evmc66781 master DSPC8681E image processing e vmc66781 master out gt switch 1 image processing ipc evmc6678 master DSPC8681E image processing e vmc66781 master out gt vecs image processing ipc evmc6678 master DSPC8681E image processing e vmc66781 master out gt switch 2 image processing ipc evmc6678 master DSPC8681E image processing e vmc66781 master out gt cinit Load HEX image bin DSPC8681E image processing evmc66781 slave hex to 0 1 start address 0x0c100000 Load HEX OK Load HEX image bin DSPC8681E image processing evmc66781 slave hex to 0 2 start address 0x0c100000 Trusted ePlatform Services AD ANTECH Advantech Confidential Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load
25. d ePlatform Services AD ANTECH hob ef Advantech Confidential 1 Introduction This document describes how to set up the software configurations for quad DSP PCle board called Lightning DSPC 8681E before using it The Lightning board contains four Texas Instruments TMS320C6678 DSPs with PCle HyperLink Serial RapidlO and SGMII interfaces 1 1 Hardware Description The placement of the Lightning broad is shown in Figure 1 1 Each Lightning board contains four TMS320C6678 codename Shannon DSPs one PLX PEX8624 PCle switch and one Xilinx XC3S200AN FPGA The TMS320C6678 multi core fixed and floating point digital signal processor is based on advanced KeyStone architecture from Texas Instruments Each 5320 6678 on Lightning board is supported by external DDR3 the DDR3 module type depends on different HW version devices for data and program storage The four TMS320C6678 devices are connected through PEX8624 PCle device which is 24 lane 6 port PCle Gen2 switch The XC3S200AN FPGA device provides the required control signals to the Lightning board XILINX 5200 DDR3 x16b 4Gb EN 3 9 2 5V gt PEX8624 mm mm PCIEx8 Gen2 Figure 1 1 DSPC 8681E Placement Trusted ePlatform Services AD ANTECH con ab Advantech Confidential 1 2 DSPC 8681E Block Diagram An interfac
26. e block diagram for the Lightning broad is shown in Figure 1 2 Each TMS320C6678 DSP contains several interfaces such as DDR HyperLink Serial RapidlO and SGMII Figure 1 2 DSPC 8681E Interface Block Diagram 1 3 DDR3 Interface Each TMS320C6678 DSP is connected to four 4Gbit DDR3 memory devices with 64 bit data and 2GB capacity at current implementation The DDR memory space is ranging from 0x80000000 to OxFFFFFFFF at DSP device Note Some A101 version board is mounted 2Gbit DDR3 memory devices and 1GB capacity The DDR memory space of those boards will be ranging from 0x80000000 to OxBFFFFFFF at DSP device User can distinguish the HW version by bar code label 9692868100E is A101 9692868102E is A103 Trusted ePlatform Services AD ANTECH Advantech Confidential Figure 1 3 Bar Code Label of DSPC 8681E 1 4 PCle Interface Each TMS320C6678 DSP is connected to PEX8624 switch by x2 lane of PCle Gen2 with 5Gb speed per lane The PEX8624 PCle switch will connect the Lightning board to host PC through x8 lane interface 1 5 HyperLink Interface Each pair of TMS320C6678 DSP devices are connected by four lanes of HyperLink interface with 50Gbaud rate in between DSPO and is the first DSP pair and DSP2 and DSP3 is the second DSP pair DSPO can exchange data to DSP1 via HyperLlink interface while DSP2 can exchange data to DSP3 via HyperLink interface as well 1 6 Serial RapidlO Interface The Light
27. e using it The modification is listed as below 1 DSPC 8681E uses to connect to BCM54616 Ethernet PHY This patch adds the initialization of SGMII port 0 and change settings of SGMII port 0 and port 1 for BCM54616 Ethernet PHY 2 DSPC 8681E uses different DDR memory devices the parameters for initialization of DDR controller is not the same as C6678 EVM This patch supports the DDR memory device which is mounted on DSPC 8681E 3 The reference clocks of DDR and SGMII is not the same as C6678 EVM and this patch modifies the relevant MPY settings Trusted ePlatform Services AD ANTECH ond Advantech Confidential 3 DSP Program Loader After the whole system booting up all DSP chips stay in idle mode The PC is responsible to download DSP codes to every chip and awaken DSPs to execute the loaded codes The loader consists of a driver and a utility running in PC Linux environment This package contains source code of the program loader The developer must rebuild and install them to the Linux before starting using the Lightning board 3 1 Host System Requirement A reference of the OS used to develop and execute this software release is 1 Linux distribution Ubuntu 10 10 Other distributions including Debian Redhat CentOS and Fedora should work with this software package 2 Kernel Linux kernel version 2 6 35 22 fact the driver should work with any kernel with version gt 2 6 20 3 Pre required Library libre
28. erence Me 25 4 1 Patch of Platform Library Library 25 4 1 1 How to Use Patch and Pre built 25 4 1 2 salsum e 25 4 2 DSP DDR3 Hu PU DRM 27 4 2 1 Ed 27 4 2 2 EU PP PE 27 4 3 DSP Local clo 28 4 3 1 2 2 28 4 3 2 29 4 4 Ethernet and Simple Web 29 4 4 1 echt 29 4 4 2 oo 2 30 4 5 Communication between 32 4 5 1 Build e T rm 32 4 5 2 Usage Q 33 4 5 3 PO Site 34 Trusted ePlatform Services AD ANTECH hop ad Advantech Confidential 4 5 4 DSP Demo 35 4 5 5 IPC Demo SYS BIOS DSP 37 4 6 Image Processing Demonstration 8 38 4 6 1 TAS UCONN css TE 39 4 6 2 39 Truste
29. f DSPs attached to the PC Since there are four DSP devices on the Lightning board this parameter can be set into 0 3 for those PC systems installed with one Lightning card For those PC systems installed with two Lightning cards there will be eight chips available to the PC systems and the parameter can be set into 0 7 The following two examples demonstrate the result of query command when PC system install with two Lightning card and query the detailed information of DSP 7 Lightning PCIE dsp loader app bin dsp loader query list Card 0 Chip 0 Device 8681 Chip 1 Device 8681 Chip 2 Device 8681 Chip 3 Device 8681 Card 1 Chip 4 Device 8681 Chip 5 Device 8681 Chip 6 Device 8681 Chip 7 Device 8681 Lightning PCIE dsp loader app bin dsp loader query 7 Chip 7 PCI Bridge from 9 PCI Bus Num 14 Vendor ID 0 104 Device ID 0 005 Subsystem VendorID 0 13 Subsystem DevID 0 8681 Class 0x00048000 Header 0 Pin 1 Trusted ePlatform Services AD ANTECH onl at Advantech Confidential BAR Configuration Start Length Flags Oxf79ff000 00004096 0 00040200 0 4000000 16777216 0 00042208 0 000000 16777216 0 00042208 0 0000000 33554432 0 00042208 3 4 2 Download DSP Program Image The command syntax is dsp_loader load chip core image entry point image file name hex The command is to download a DSP program DSP image into to RAM of
30. ion Version 1 00 00 03 Figure 4 8 Image Processing Input Page Trusted ePlatform Services AD ANTECH Advantech Confidential G Multicore Image Processing Demonstration Output Windows Internet Explorer 1921681104 RRE Multicore Image Processing Demonstration Output Multicore Image Processing Demonstration Output Return Main Page Image Processing Function Edge Detection Image Dimension in pixels 1920x1030 Input Image Size in bytes 6220854 Number of Cores Used e e e 3 in Processing Time Figure 4 9 Image Processing Output Page
31. it rates before running this example Each DSP has a fixed IP number that is determined by its order The pre given IP addresses are shown below The user can use a browser to input the BMP image form web page provided by HTTP server IP DSPO 192 168 1 101 PC Setting DSP 1 192 168 1 102 IP 192 168 1 100 DSP 2 192 168 1 103 Subnet Mask 255 255 254 0 DSP 3 192 168 1 104 4 6 1 Build Instruction Steps to build image processing program are listed below 1 Import the image_processing_evmc6678l_master and image processing evmc6678l slave CCS projects from Lightning PCIEYexamplesimage processingNpc evmc6678l directory CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Select DSPC8681E as active configuration 3 Clean the image_processing_evmc6678l_master project and re build the project After build is completed image processing evmc6678l master out will be generated under the directory Lightning PCIE examples image_processing ipc evmc66 78l master DSPC8681 E 4 Clean the image processing evmc6678l slave project and re build the project After build is completed image processing evmc66781l slave out will be generated under the directory Lightning PClEvexamplesimage processing Nipe evmc6678hslave Debug 4 6 2 Usage User can use the shell script Lightning PCIE examples script DSPC8681E image processing sh to setup image processing program on each DSP autom
32. le implementation and the debug message will be written into L2 memory PC host can use dsp_demo console command to dump these messages for debug purpose Trusted ePlatform Services AD ANTECH Advantech Confidential 4 5 5 IPC Demo SYS BIOS DSP Application The IPC feature also works in 5 SYS BIOS architecture The demo program is embedded in the Ethernet example to show how to register an interrupt in SYS BIOS architecture In order to run this IPC demo users can follow two steps below 1 Initialize DDR3 module perform init 1000 sh 2 Run SYS BIOS IPC demo script perform SYSBIOS sh Lightning PCIE examples script DSPC8681E ipc SYSBIOS sh 1 Translating to Intel format web client evmc66781 DSPC8681E client evmc66781 0out gt text c 1 100 web client evmc66781 DSPC8681E client evmc66781 o0ut gt web client evmc66781 DSPC8681E client evmc66781 0ut gt const web client evmc66781 DSPC8681E client_evmc66781 out gt Switch 1 web client evmc66781 DSPC8681E client evmc66781 out gt 5 web client evmc66781 DSPC8681E client_evmc66781 out gt Switch 2 web client evmc66781 DSPC8681E client_evmc66781 out gt cinit Load HEX image bin DSPC8681E client_evmc66781 hex to 1 0 start address 0x80300000 Load HEX OK DDR of DSP is initialized ready to write dummy data to DSP dump dummy_buffer before DSP opera
33. lect Lite as Active Configuration Step 3 Trusted ePlatform Services AD ANTECH Advantech Confidential 3 Clean the platform lib dspc8681 project and re build the project After build is completed the ti platform dspc8681 lite lib will be generated under the directory C6678 1 1 2 5 packages ti platform dspc8681 platform_lib lib debug 4 Repeat step 2 and step 3 select Debug as active configuration and re build the project ti platform dspc8681 ae66 will be generated under the same directory Steps to build ndk lib are listed below 1 Import the CCS project from C6678 1 1 2 5 packages ti transport ndk nimu directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Clean the nimu eth evmc6678l project and re build the project After build is completed ti transport ndk nimu ae66 will be generated under the directory C6678 1 1 2 5 packages ti transport ndk nimu lib debug 4 2 DSP DDR3 Initialization The Boot ROM codes only initialize L2 internal memory when booting from PCIE boot mode The on board DDR3 control registers need to be explicitly initialized by this supplied example program User has to initialize DDR3 control registers before loading the application into DSP After initialization of DDR3 control registers this program will clear boot address and wait dsp loader to write new entry point in boot address When boot address is updated this program will jump to new e
34. mage The image entry point of init hex DSP image uses address 0x008362A0 as local address for each CPU Individual local CPU address can also be transferred to DSP global address with offset For example CPU 0 local address 0x00800000 is equal to DSP global address 0x1080000 CPU 1 local address 0x00800000 is equal to DSP global address 0 1180000 3 4 3 DSP Memory Read The command syntax is dsp loader rmem chip address The command is to read 32bits DWORD from DSP The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 address read data address The following example is to read DSP 2 data at address 0 10800000 Lightning PCIE dsp loader app bin dsp loader rmem 2 0x10800000 OxO1bc54f6 3 4 4 DSP Memory Write The command syntax is loader load chip address value The command is to write a 32bits DWORD into DSP memory The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 address written data address 3 value written data The following example writes data Ox55AA55AA into DSP 2 at address 0x10800000 Lightning PCIE dsp loader app bin dsp loader 2 0x10800000 0x55aa55aa Lightning PCIE dsp loader app bin dsp loader rmem 2 0x10800000 0x55aa55aa 3 4 5 Download DSP Binary File The command syntax is Trusted ePlatform Ser
35. ning board contains a two lane Serial RapidlO sRIO chaining through 5320 6678 DSP sRIO laneO and lane1 at 5 Gbaud rate Each DSP can communicate to the other DSPs through the sRIO interface 1 7 SGMII Interface 5320 6678 DSP contains an on chip Ethernet switch with two Ethernet interfaces EMACO and EMAC1 TMS320C6678 DSP can connect to another DSP by Ethernet interface without extra Ethernet switch in between The SGMII interface connection and the topology of the Ethernet link on the Lightning broad is shown in Figure 1 2 The DSPO on Lightning board contains two SGMII interfaces and EMACO is connected to Broadcom BCM54616 Ethernet PHY for external Ethernet access and EMAC1 is connected to EMACO of EMAC1 of is connected to EMACO of DSP2 EMAC1 of DSP2 is connecting to EMACO of DSP3 Programmers only need to enable Ethernet switch feature of TMS320C6678 DSP Trusted ePlatform Services T Advantech Confidential and Ethernet packet will forward to the matched DSP by hardware accelerator of on chip Ethernet switch without intervention of DSP cores inside 1 8 DSP Identification The Lightning board use GPIO 1 2 pins to identify each DSP and the assignment of DSP ID is shown below GPIO2 1 DSPO 0 0 0 1 0 1 DSP2 1 0 DSP3 1 1 Table 1 1 DSP ID and table The Linux command lspci can list which type of board it is running by checking s
36. ntry point and start to run the next program 4 2 1 Build Instruction Steps to build DDR3 initialization program are listed below 1 Import the demo evmc6678l init CCS project from Lightning 66781 directory in CCSv5 Project Import Existing CCS CCE Eclipse Projects 2 Select DSPC8681E as active configutation Clean the demo evmc66781l init project and re build the project After build is completed init out and init map will be generated under Lightning PCIEYexamplesWddr3 evmc6678lNbin DS PC8681 E directory 4 2 2 Usage User can use the shell script examples scrip DSPC8681 ENnit 1000 sh or init 1250 sh to initialize DSP DDR the procedure is composed of three jobs 1 Convert out to hex by executable Hex6x 2 Externally set PLL Multiplier configuration by dsp loader Trusted ePlatform Services AD ANTECH oe ak Advantech Confidential Load hex to DSP by dsp loader There are two scripts init_1000 sh and init_1250 sh for users to initialize DSP They load the init hex in Lightning PCIE bin DSP initialization be done by invoking the init scripts The difference between init_1000 sh and init_1250 sh is that the former runs DSP at 1GHz the latter overclocks DSP to 1 25GHz There is the prebuilt binary bundled in Lightning_PCIE bin Users can initialize DSP DDR module without building the image from source However when running the script it will show the version
37. o PCle Switch LEDs on Back Side Trusted ePlatform Services Advantech Confidential 2 Package Content This package is created to help customer quickly boot DSP through PCIE the package includes Path Purpose Lightning_PCIE dsp_loader driver DSP Program Loader Driver Lightning_PCIE dsp_loader app DSP Program Loader Utility Lightning PCIE examples ddr3 Example DDR3 Initialization Lightning PCIE examples dsp reset Example DSP Initialization for Local Reset Lightning PCIE examples image processing Example Image Processing using Multi Core Lightning PCIE examples ipc Example PC DSP Communication Lightning PCIE examples script Common demo related scripts Lightning PCIE examples web Example Simple Web Server Lightning PCIE patch Patch Platform Library and NDK Library of PDK C6678 1 1 2 5 inside MCSDK 2 1 2 5 Table 2 1 Package content list 2 1 API Interface of DSP Driver It is a Linux based PCIE driver which is used to map between PC memory and DSP memory prerequisite for DMA to function is that memory needs to be contiguous in physical memory Memory allocated using malloc is not contiguous Ubuntu Linux doesn t have any user mode APIs to allocate contiguous physical memory and hence a Kernel mode driver to allocate contiguous physical memory is necessary Currently the implemented controls are listed below IOCTL code Description
38. o included and can be used to convert out file format into h file which will be used as the source file when make DSP loader utility 4 3 1 Build Instruction Steps to build DSP reset program are listed below Trusted ePlatform Services AD ANTECH Advantech Confidential 1 Import the pcieboot_localreset CCS project from Lightning _PCIE examples dsp_reset build directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Clean the pcieboot_localreset project and re build the project After build is completed pcieboot localreset out and pcieboot localreset map will be generated under Lightning PCIEYexamplesdsp resetWbuild bin directory 3 Enter in Lightning PCIEYexamples script utilsvelf 2HUtils and launch pcieboot localreset elf2HBin sh After the steps of script are completed the pcieLocalReset h will be generated under Lightning_PCIE dsp_loader app inc 4 Enter in Lightning PCIEV make clean and make follow chap 3 2 to re build DSP loader 4 3 2 Usage Refer to 3 4 7 to get detailed procedure of the DSP local reset 4 4 Ethernet and Simple Web Server The Ethernet program is modified from the example codes in MCSDK This example implements a simple web server running on DSP The Ethernet port on the bracket of the Lightning board must be connected to an external Ethernet switch support gigabit rate before running this example Each DSP has a fixed IP number that is determined by its
39. of your DSP PG1 or PG2 and for PG2 chip it will also show the maximum running frequency e g 1GHz 1 2GHz or 1 25GHz Notice At present we only guarantee the stability for PG2 version of C6678 to run at 1GHz The following example initializes 4 DSP Lightning_PCIE examples script DSPC8681E init_1000 sh 4 Translating to Intel format ddr3 evmc66781 bin DSPC8681E init out gt text _c_int00 _ ddr3 evmc66781 bin DSPC8681E init out gt text ddr3 evmc66781 bin DSPC8681E init out gt const ddr3 evmc66781 bin DSPC8681E init out gt cinit Silicon Version PG1 0 Load HEX image bin DSPC8681E init hex to 0 0 start address 0 00830000 Load HEX OK Silicon Version PG1 0 Load HEX image bin DSPC8681E init hex to 1 0 start address 0x00830000 Load HEX OK Silicon Version PG1 0 Load HEX image bin DSPC8681E init hex to 2 0 start address 0x00830000 Load HEX OK Silicon Version PG1 0 Load HEX image bin DSPC8681E init hex to 3 0 start address 0x00830000 Load HEX OK 4 3 DSP Local Reset After DSP code is downloaded once the DSP runs downloaded code In order to re download the different DSP code the DSP local reset function is needed When user perform the reset function by DSP loader utility the utility will configure related registers of each module of DSP and download the DSP reset program to each core The file format conversion tool is als
40. order The pre given IP addresses are shown below The user can use a browser to view the simple web page provided by this simple web server IP DSPO 192 168 1 101 DSP 1 192 168 1 102 DSP2 192 168 1 103 DSP 192 168 1 104 4 4 1 Build Instruction Steps to build web server program are listed below 1 Import the client evmc6678l CCS project from Lightning PCIE examples web client evmc6678l directory in CCSv5 Project Import Existing CCS CCE Eclipse Projects 2 Select DSPC8681E as active configuration Trusted ePlatform Services AD ANTECH T Advantech Confidential 3 Clean the client evmc6678l project and re build the project After build is completed client evmc6678l out client evmc6678l map will be generated under Lightning PCIEYexamples Web clientevmc6678NDSP C8681 E directory 4 4 2 Usage User can use the shell script Lightning PCIE examples scrip DSPC8681 E ethernet sh to setup Ethernet program on each DSP automatically The following steps set up ethernet program on 4 DSPs 1 Perform the init 1000 sh to initialize DDR 2 Perform the ethernet sh to convert client evmc6678l out to client evmc6678l hex and load the hex file into each DSP Lightning PCIE examples script DSPC8681E ethernet sh 4 Translating to Intel format web client evmc66781 DSPC8681E client evnc66781 out gt text c 1 100 web client evmc66781 DSPC8681E client evmc66
41. r has to install MCSDK first and applies the provided patch The default path of MCSDK in Windows is C Program Files Texas Instruments or 4 1 1 How to Use Patch and Pre built Libraries 1 Copy Lightning C6678 1 1 2 5 2 Paste to C Program Files Texas Instruments pdk_C6678_1 1 2 5 3 The pre built libraries are included in the provided patch a developer can use these libraries directly 4 1 2 Build Instruction Steps to build platform lib are listed below 1 Import the CCS project from C6678 1 1 2 5 packages ti platform dspc8681 platform_lib directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Refer to Figure 4 1 Figure 4 3 and select Lite as active configuration in CCSv5 Project Properties C C Build Pant voni guration m gt nee Viscovery 0110 3 Environment Logging Settings Genera oo 2 ro v n v ct References Debug Settings k o Figure 4 1 Select Lite as Active Configuration Step 1 Trusted ePlatform Services Advantech Confidential O O 5583 2 Qc Figure 4 2 Select Lite as Active Configuration Step 2 Configuration Lite Active 1 Configuration Description Debug Release Release 85 Big endian rele NEN TEM Bu 8 r Ma Bu Figure 4 3 Se
42. s generated from host Other cores will enter idle state after local reset related registers are set by DSP Program Loader 2 5 Example Simple Web Server A web demo example contains CCS project settings to build an image It can set up a web server so user can use network browser to access the web page stored in the DSP This program is modified from MCSDK example which is located the mcsdk 2 01 02 05 examples ndk client The each DSP will be configured with a static IP instead of DHCP 2 6 Example PC DSP Communication This example contains two parts a DSP image and a PC utility The dsp folder included contains CCS project settings of building an image This example provides sample codes on how to communicate between PC and DSP 2 7 Example Image Processing The image processing demo example contains two CCS project settings to build the demo images This application will run TI image processing kernels imagelib on multiple cores to do image processing eg edge detection etc on an input image This program is modified Trusted ePlatform Services AD ANTECH Advantech Confidential from MCSDK example which is located in the mcsdk 2 01 02 O5WemosWmage processingNpc The each DSP will be configured with a static IP instead of DHCP 2 8 Patch Platform Library and NDK Library There are some differences between the Lightning board and C6678 EVM hence developer should patch these files in the TI PDK befor
43. stem It uses CGI functions on the DSP to dynamically create HTML WEB Display IP Address Information pages The form to the right uses the CGI post operation to command Display Sockets Usage the DSP to generate simple HTTP response pages based on current O Display Route TCP IP status HTTP server also supports the CGI get operation For example these links are equivalent to the Selections on the form above IP Address Information inform cgi ipinfo Disphy Sockets Usage inform cgi sockets Di amp phy Route Tabie inform cgi route ae m mamin Figure 4 4 TCP IP Demo Page Trusted ePlatform Services AD ANTECH m Advantech Confidential 2 nttp 192 168 1 104 infora cgi Microsoft Internet Explorer BRU ROREW REY Qa O HAO 1e 33 FED 48 http 192 168 1 104 inform 1 4 gt 192 168 1 104 int HBOS 83 Texas INSTRUMENTS REAL WORLD SIGNAL PROCESSING IP Address Information HTTP Server IP Address 192 168 1 104 HTTP Server Hostname DNS Reply Your IP Address 192 168 1 100 Your Hostname No DNS Reply Return to Main Page am Figure 4 5 IP Address Information page 4 5 Communication between PC and DSP This example demonstrates several functions for manipulating the DSPs including Write data blocks to DSP memory from PC Read
44. this virtual console command Refer to the source code of DSP demo program to get detailed implementation 4 5 4 DSP Demo Program DSP demo program configures DSP CSL INTC registers to receive PCle Legacy INTB and MSIO interrupt from PC host The procedure of demo example is illustrated below with flow chart displayed in Figure 4 6 Trusted ePlatform Services AD ANTECH Advantech Confidential 1 DSP application set up INTC for ISR handler to receive Legacy INTB and MSIO then wait the interrupt sent from PC host 2 PC host writes test data pattern whose length is 640 byte to DSP DDR and sends an interrupt to DSP after finishing the writing of the test data pattern 3 The test data pattern in DDR will be added by 1 when DSP receives the interrupt from PC host After finishing the operation DSP will send an interrupt back to PC host 4 PC Host receives the interrupt from DSP as the indication that the test data pattern has already been changed and prints the test data pattern 5 Repeat the communication 1000 times dsp_loader sar ose IPC demo starts PCIE boot mode complete enter IDLE Write Dummy to DSP DDR DEMO TRI Increment each DWORD in DDR Interrupt Set DSP 510 Print Dummy ex enas Figure 4 6 Flow Diagram of IPC Example Besides the interrupt demo the demo code also contains the virtual conso
45. tion 0x607180 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 0x6071a0 00000008 00000009 0000000 00000006 0000000 0000000d 0000000 0000000f 0x6071c0 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 0x6071e0 00000018 00000019 0000001 0000001b 0000001 00000014 0000001 0000001f 0 607200 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 0 607220 00000028 00000029 0000002 00000026 0000002 00000024 0000002 00000024 0 607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037 0 607260 00000038 00000039 0000003a 00000036 0000003 00000034 0000003e 0000003f 0 607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047 0 6072 0 00000048 00000049 0000004 00000046 0000004 00000044 0000004 0000004f 0 6072 0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057 0 6072 0 00000058 00000059 0000005 00000056 0000005 00000054 0000005e 0000005f 0 607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067 0 607320 00000068 00000069 0000006 00000066 0000006 00000064 0000006e 0000006f 0 607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077 0 607360 00000078 00000079 0000007 00000076 0000007 00000074 0000007 0000007 0 607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087 0 6073 0 00000088 00000089 0000008 00000086 0000008 0000
46. ubsystem ID and subsystem vendor ID as table 1 2 SUBSYS_ID SUBSYS_VEN_ID Value 0x8681 Ox13FE Table 1 2 Subsystem ID and vendor ID table 15 vvnn d b005 04 00 0 Multimedia controller 0480 Texas Instruments Device 104c b005 01 Subsystem Advantech Co Ltd Device 13fe 8681 Control I 0 Mem BusMaster SpecCycle MemWINV VGASnoop ParErr Stepping SERR FastB2B DisINTx Status Cap 66MHz UDF FastB2B ParErr DEVSEL fast gt TAbort lt TAbort lt MAbort gt SERR lt PERR INTx Latency 0 Cache Line Size 64 bytes Interrupt pin A routed to IRQ 11 Region 0 Memory at f8800000 32 bit non prefetchable size 4K Region 1 Memory at df000000 32 bit prefetchable size 16M Region 2 Memory at de000000 32 bit prefetchable size 16M Region 3 Memory at dc000000 32 bit prefetchable size 32M Region 4 Memory at d8000000 32 bit prefetchable size 64M Capabilities lt access denied gt Trusted ePlatform Services AD ANTECH Advantech Confidential 1 9 Hardware Environment Setting The Lightning board supports two boot modes Emulation mode and 2 mode The user can select boot mode by Switch 1 which is shown in Figure 1 4 The Emulation mode is mainly for JTAG debug The 2 boot mode is usually selected by Switch 1 DSPC 8681E includes four 12 EEPROMs to support the TMS320C6678 DSPs and each 2 EEPROM contains program for 2 stage boot loader
47. vices AD ANTECH ok Advantech Confidential dsp_loader loadbinary chip address size transfer type bin file name The command is to write a bin file into DSP memory The detailed description of each parameter is shown below chip the chip are the number of DSPs attached to the PC address written data address size written data size 0 for all data of file transfer type 0 for CPU memcpy 1 for DMA bin file name bin file name is the full path of binary file name which is loaded into DSP The following example writes jpg file into DSP 1 at DDR beginning address 0x80000000 by using DMA Lightning_PCIE dsp_loader app bin dsp_loader loadbinary 1 0 80000000 0 1 home advantech test_image jpg Load Binary file home advantech test_image jpg to DSP1 start address 0x80000000 Size 0x00000000 Written to dsp 7496169 bytes Time measured 16225 us Load Binary OK 3 4 6 Save DSP Memory as a Binary File The command syntax is dsp_loader savebinary chip address size transfer type bin file name The command is to read a DSP memory section and save the data as a binary file The detailed description of each parameter is shown below chip the chip are the number of DSPs attached to the PC address read data address size read data size transfer type 0 for CPU memcpy 1 for DMA bin file name bin file name is the full path of binary file name which is saved

Lightning (DSPC-8681E) User Guide

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