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Arria V Avalon-MM Interface for PCIe Solutions User Guide

1. 2014 12 15 TLP Packet Formats with Data Payload A 5 Figure A 12 Configuration Write Request Root Port Type 1 Configuration Write Request Root Port Type 1 0 1 2 3 7 5 4 312 1 0 7 16151413 7 6 5 4 2 1 0 7 6 5 44 3 2 41 40 ByteO 0 1 0 0 0 1 0 14 0 0 0 0 0 TD EP 01 0 0 0 000000 0 071 Byte 4 Requester ID Tag 0 0 0 0 First BE Byte 8 Bus Number Device 0 0 0 0 Ext Reg Register No 0 0 Byte 12 Reserved Figure A 13 1 O Write Request 1 0 Write Request 0 1 2 3 7 5 4 312 1 0 7 16151413 7 6 5 4 2 1 0 7 6 5 4 3 2 41 0 Byte0 0 1 0 0 0 0 1 0 0 0 0 0 0 TD EP 01 0 0 0 000000 0 071 Byte 4 Requester ID Tag 0 0 0 0 First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Figure A 14 Completion with Data Completion with Data 0 1 2 3 7 5 4 3 2 1 0 7 6 5 4 3 7 6 5 4 2 1 0 7 6 5 4 4 3 424140 Byteo foli 0 0 101 olo zc Jo m fee fofo Length Byte 4 Completer ID Status B Byte Count Byte 8 Requester ID Tag 0 Lower Address Byte 12 Reserved Transaction Layer Packet TLP Header Formats G Send Feedback Altera Corporation UG 01105 A 6 TLP Packet Formats with Data Payload pees 2014 12 15 Figure A 15 Completion Locked with Data Completion Locked with Data 0 1 2 3 7 6 5 4 372 1 077 6 5 74 3 2 1 0 7
2. 2014 12 15 Transaction Layer Packet TLP Header Formats A 3 Figure A 6 I O Read Request 1 0 Read Request 0 1 2 3 716 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 l6 J5 4 342 1 0 7 6 5 4 3 2 41 0 Byte 0 0 0 0 0 0 0 1 O0J0J0 0 0 0j 0 0 0 TD EPJO 0 0j 0 0 000000 0 0 1 Byte 4 Requester ID Tag 0 0 0 0 First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Figure A 7 Message without Data Message without Data 0 1 2 3 716 5 4 3 2 1 0 7 6 5 4 342 1J0 7 16 5 4 3 72 1 0 7 6 5 4 43 2 1 40 Byte 0 ojo 1 1 0 4 4 a olo olo zo jer Joljojojojo 00000000 0 Byte 4 Requester ID Tag Message Code Byte 8 Vendor defined or all zeros Byte 12 Vendor defined or all zeros Note 1 Notsuppotedin Avalon MM Figure A 8 Completion without Data Completion without Data 0 1 2 3 7 6 5143 12 1 0 71615 4 312 11017 16 5 4 3 2 41 0 7 6 5 4 73 2 41 40 Att Byte 0 0 0 0 0 1 0 1 0 0 Tc 0 0 0 0 TD EP 0 0 Length Byte 4 Completer ID Status B Byte Count Byte 8 Requester ID Tag 0 Lower Address Byte 12 Reserved Transaction Layer Packet TLP Header Formats Altera Corporation LJ Send Feedback UG 01105_avmm A 4 TLP Packet Formats with Data Payload 2014 12 15 Figure A 9 Completion Locked without Data Completion Locked without Data 0 1 2 3 7 6 5 4 3 12 1 0 17 645 74 342 1 40 7 6 5 4 3 2 1 0 7 6 5 74 3 2 1 140
3. Vb1111 Write full 32 bits 4b0011 Write the lower 2 bytes 4 b1100 Write the upper 2 bytes 4 b0001 Write byte 0 only 4 b0010 Write byte 1 only 4 b0100 Write byte 2 only 4 b1000 Write byte 3 only In burst mode the Arria V Hard IP for PCI Express supports only byte enable values that correspond to a contiguous data burst For the 32 bit data width example valid values in the first data phase are 4 b1111 4 b1110 4 b1100 and 4 b1000 and valid values in the final data phase of the burst are 4 b1111 4 b0111 4 b0011 and 4 b0001 Intermediate data phases in the burst can only have byte enable value 4 b1111 PCI Express to Avalon MM Downstream Read Requests The PCI Express Avalon MM bridge sends PCI Express read packets to the interconnect fabric as burst reads with a maximum burst size of 512 bytes For Endpoints the bridge converts the PCI Express address to the Avalon MM address space based on the BAR hit information and address translation lookup table values The RX Avalon MM master port drives the received address to the fabric You can set up the Address Translation Table Configuration in the parameter editor Unsupported read requests generate a completer abort response Altera Corporation IP Core Architecture CJ Send Feedback UG 01105 a Avalon MM to PCI Express Read Completions 9 13 Related Information Minimizing BAR Sizes and the PCIe Address Space on page 9 15 Avalo
4. 10 Reserved 9 When set indicates a parity error was detected on the Configu RWI1CS ration Space to TX bus interface 8 When set indicates a parity error was detected on the TX to RWICS Configuration Space bus interface 7 When set indicates a parity error was detected in a TX TLP and RWI1CS the TLP is not sent 6 When set indicates that the Application Layer has detected an RWICS uncorrectable internal error 5 When set indicates a configuration error has been detected in RWI1CS CvP mode which is reported as uncorrectable This bit is set whenever a CVP_CONFIG_ERROR rises while in cvP_MODE 4 When set indicates a parity error was detected by the TX Data RWI1CS Link Layer 3 When set indicates a parity error has been detected on the RX RWI1CS to Configuration Space bus interface 2 When set indicates a parity error was detected at input to the RWICS RX Buffer 1 When set indicates a retry buffer uncorrectable ECC error RWI1CS 0 When set indicates a RX buffer uncorrectable ECC error RWI1CS Correctable Internal Error Mask Register Table 5 29 Correctable Internal Error Mask Register The Correctab le Internal Errors This register is for debug only wits Register Description Reset Value Error Mask register controls which errors are forwarded as Internal Correctable 31 7 Reserved 6 Mask for Corrected Internal Error reported by the Application RWS La
5. Note To meet the 100 ms system configuration time you must use the fast passive parallel configuration scheme with and a 32 bit data width FPP x32 Related Information e PCI Express Card Electromechanical Specification 2 0 e Device Datasheet for Arria V Devices Hard IP Status Refer to Reset and Clocks for more information about the reset sequence and a block diagram of the reset logic Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Hard IP Status 4 11 Table 4 6 Status and Link Training Signals O Sigal a Deseripton O derr_cor_ext_rcv Output Indicates a corrected error in the RX buffer This signal is for debug only It is not valid until the RX buffer is filled with data This is a pulse not a level signal Internally the pulse is generated with the 500 MHz clock A pulse extender extends the signal so that the FPGA fabric running at 250 MHz can capture it Because the error was corrected by the IP core no Application Layer intervention is required derr_cor_ext_rpl Output Indicates a corrected ECC error in the retry buffer This signal is for debug only Because the error was corrected by the IP core no Application Layer intervention is required derr_rpl dlup Output Output Indicates an uncorrectable error in the retry buffer This signal is for debug only The signal is not available for Arria V and Cyclone V devices W
6. Figure 6 4 TX Transceiver Reset Sequence npor pll_locked b 127 cycles gt npor_serdes tx_digitalreset The TX transceiver reset sequence includes the following steps 1 After npor is deasserted the IP core deasserts the npor_serdes input to the TX transceiver 2 The SERDES reset controller waits for p11_1ocked to be stable for a minimum of 127 pld_clk cycles before deasserting tx_digitalreset Altera Corporation Reset and Clocks GJ Send Feedback UG 01105_avmm 2014 12 15 Clocks 6 5 For descriptions of the available reset signals refer to Reset Signals Status and Link Training Signals Clocks The Hard IP contains a clock domain crossing CDC synchronizer at the interface between the PHY MAC and the DLL layers The synchronizer allows the Data Link and Transaction Layers to run at frequencies independent of the PHY MAC The CDC synchronizer provides more flexibility for the user clock interface Depending on parameters you specify the core selects the appropriate coreclkout_hip You can use these parameters to enhance performance by running at a higher frequency for latency optimization or at a lower frequency to save power In accordance with the PCI Express Base Specification you must provide a 100 MHz reference clock that is connected directly to the transceiver As a convenience you may also use a 125 MHz input reference clock as input to the TX PLL Related Information PC
7. Header 0 31 0 Data 63 32 Header 2 31 0 Programming Model for Avalon MM Root Port 5 27 Data Aligned to QWord Boundary Register 1 Header 1 63 32 Cycle 1 Cyce 2 Cycle 3 Register 0 Register 1 Register 0 Register 1 Register 0 Header 0 31 0 Unused but must be written Header 2 31 0 Unused but must be written Data 31 0 The following figure illustrates four dword TLPs with data that are aligned and unaligned to the qword Figure 5 11 Layout of Data with 4 Dword Headers Cycle 1 Cycle 2 Cycle 3 Registers Send Feedback Register 1 Register 0 Register 1 Register 0 Register 1 Register 0 Data Unaligned to QWord Boundary Header 1 63 32 Header 0 31 0 Header 3 63 32 Header 2 31 0 Data 63 32 Unused but must be written Cyde1 Cyde 2 Cycle 3 Register 1 Register 0 Register 1 Register 0 Register 1 Register 0 Data Aligned to QWord Boundary Header 1 63 32 Header 0 31 0 Header 3 63 32 Header 2 31 0 Unused but must be written Data 31 0 Altera Corporation 5 gt UG 01105_avmm 5 28 Sending a Write TLP 2014 12 15 The TX TLP programming model scales with the data width The Application Layer performs the same writes for both the 64 and 128 bit interfaces The Application Layer can on
8. _ gt MACL lg PHY ayer Interface ve a Se eee Plamen E a S i Bei L 1 eis Scrambler te S TX Packets E Wee i gt S a TE pel Eee TUB Transmit 25 E Laned en Data Path mak TX TX Scrambler I peau ete le ee ee ee a Uo a LTSSM o lt Control amp Status gt State Machine A Clen OOOO T O T a A E z i 8B10B 1 By RX RK Descrambler i qa Bg 2 Decoder z S 1 g RX Packets i 5 D g 1 m Recei S E O cg E A Oe EE 1 g eceive gt Rees nes a A Data Path 8B10B Elastic i FRA 1 Decoder Buffer S The Physical Layer is subdivided by the PIPE Interface Specification into two layers bracketed horizon tally in above figure e Media Access Controller MAC Layer The MAC layer includes the LTSSM and the scrambling descrambling and multilane deskew functions e PHY Layer The PHY layer includes the 8B 10B and 128b 130b encode decode functions elastic buffering and serialization deserialization functions The Physical Layer integrates both digital and analog elements Intel designed the PIPE interface to separate the MAC from the PHY The Arria V Hard IP for PCI Express complies with the PIPE interface specification IP Core Architecture Altera Corporation CJ Send Feedback UG 01105_avmm 9 8 32 Bit PCI Express Avalon MM Bridge 2014 12 15 The PHYMAC block comprises four main sub blocks e MAC Lane Both the RX and the TX path use this
9. e 1 cVP_MODE is active Signals to the FPGA control block active and all TLPs are routed to the Configuration Space This cvp_ MODE cannot be enabled if cvP_EN 0 e 0 The IP core is in normal mode and TLPs are routed to the FPGA fabric Table 5 9 CvP Data Registers The following table defines the cvP Data registers For 64 bit data the optional cvP Data2 stores the upper 32 bits of data Programming software should write the configuration data to these registers If you Every write to these register sets the data output to the FPGA control block and generates lt n gt clock cycles to the FPGA control block as specified by the cvp_num_cuxs field in the cvP Mode Cont rol register Software must ensure that all bytes in the memory write dword are enabled You can access this register using configuration writes alternatively when in CvP mode these registers can also be written by a memory write to any address defined by a memory space BAR for this device Using memory writes should allow for higher throughput than configuration writes its Register Description Reset Value 31 0 Upper 32 bits of configuration data to be transferred to the FPGA 0x00000000 control block to configure the device You can choose 32 or 64 bit data 31 0 Lower 32 bits of configuration data to be transferred to the FPGA 0x00000000 RW control block to configure the device Table 5 10 CvP Programming Control Register T
10. 1 2 Features UG 01105_avmm 2014 12 15 Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs Related Information PCI Express Base Specification 2 1 or 3 0 PCI Express High Performance Reference Design Creating a System with Qsys Features New features in the Quartus II 14 1 software release Reduced Quartus II compilation warnings by 50 The Arria V Hard IP for PCI Express with the Avalon MM interface supports the following features Complete protocol stack including the Transaction Data Link and Physical Layers implemented as hard IP Support for x1 x2 x4 and x8 configurations with Gen1 and Gen2 lane rates for Root Ports and Endpoints Dedicated 16 KByte receive buffer Optional hard reset controller for Gen2 Optional support for Configuration via Protocol CvP using the PCIe link allowing the I O and core bitstreams to be stored separately Qsys example designs demonstrating parameterization design modules and connectivity Extended credit allocation settings to better optimize the RX buffer space based on application type Optional end to end cyclic redundancy code ECRC generation and checking and advanced error reporting AER for high reliability applications Easy to use e Flexible configuration e No license requirement e Example designs to get started Table 1 2 Featu
11. Corrected connection for mgmt_clk_clk in Figure 3 2 Corrected definition of nPERSTL The device has 1 nPERSTL pin for each instance of the Hard IP for PCI Express in the device Corrected feature comparison table in Datasheet chapter The Avalon MM Hard IP for PCI Express IP Core does not support legacy endpoints How to Contact Altera To locate the most up to date information about Altera products refer to the following table Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Altera Corporation Additional Information CJ Send Feedback UG 01105_avmm 2014 08 18 Typographic Conventions C5 Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Related Information e Technical Support e Technical Training e Customer Training e Product Documentation e Non Technical Suport general e Licensing Typographic Conventions The following table shows the typographic conventions this document uses Table C 1 Visual CueMeaning a Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements
12. The lower 32 bits of the prefetchable base register of the Typel Configuration Space This register is only available in Root Port mode 14 h3C40 cfg_pr_bas_hi 43 32 The upper 12 bits of the prefetchable base registers of the Typel Configuration Space This register is only available in Root Port mode 14n3C44 cfg_pr_lim_low 31 0 The lower 32 bits of the prefetchable limit registers of the Typel Configuration Space Available in Root Port mode 14 h3C48 cfg_pr_lim_hi 43 32 The upper 12 bits of the prefetchable limit registers of the Typel Configuration Space Available in Root Port mode 14h3C4C CieGj_joumersie Sil 3 0 cfg_pmesr 31 16 is Power Management Control and cfg_pmcsr 15 0 is the Power Management Status register 14 h3C50 cfg_msixcsr 15 0 MSI X message control register 14 h3C54 crome iese 1530 MSI message control Altera Corporation Registers GJ Send Feedback UG 01105_avmm 2014 12 15 Control Register Access CRA Avalon MM Slave Port 5 2 14 h3C58 cfg_tcvcmap 23 0 Configuration traffic class TC virtual channel VC mapping The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet The following encodings are defined e cfg_tcvemap 2 0 Mapping for TCO always 0 3 Mapping for TC1 6 Mapping for TC2 e cfg_tcvcmap 11 9 Mapping for TC3
13. e Avalon ST packet error ready and BAR signals Avalon to PCIe Address Translation Settings Number of address pages Size of address pages 1 2 4 8 16 32 64 128 256 512 4 KBytes 4 GBytes Specifies the number of pages required to translate Avalon MM addresses to PCI Express addresses before a request packet is sent to the Transaction Layer Each of the 512 possible entries corresponds to a base address of the PCI Express memory segment of a specific size This parameter is only necessary when you select 32 bit addressing Specifies the size of each memory segment Each memory segment must be the same size Refer to Avalon MM to PCI Express Address Translation Algorithm for 32 Bit Bridge for more information about address translation This parameter is only necessary when you select 32 bit addressing Parameter Settings CJ Send Feedback Altera Corporation Interfaces and Signal Descriptions 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback 64 or 128 Bit Avalon MM Interface to the Application Layer This chapter describes the top level signals of the Arria V Hard IP for PCI Express using the Avalon MM interface to the Application Layer The Avalon MM bridge translates PCI Express read write and completion TLPs into standard Avalon MM read and write commands for the Avalon MM RX Master Port interface For the Avalon MM TX Slave Port interface the bridge translates Avalon MM reads and
14. 3 2 1 0 core xlIP z z 0 core Table B 2 Lane Assignments with Lane Reversal 8 4 2 1 8 4 2 Jl Slot Size 8 4 2 1 Lane 7 0 6 1 5 2 3 4 2 5 1 6 0 7 7 0 6 1 3 0 2 1 3 0 3 0 7 0 3 0 1 0 0 pairings T gt 0 7 5 2 4 3 2 1 1 6 0 7 1 6 0 7 1 2 0 3 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered JNO fe RYA 101 Innovation Drive San Jose CA 95134 a E UG 01
15. Altera Corporation Parameter Settings GJ Send Feedback UG 01105_avmm 2014 12 15 Base Address Register BAR Settings 3 3 Base Address Register BAR Settings You can configure up to six 32 bit BARs or three 64 bit BARs Table 3 2 BAR Registers Type Disabled Defining memory as prefetchable allows data in the region to be fetched ahead anticipating that the 64 bit prefetchable memory requestor may require more data from the same 32 bit non prefetchable memory gion than was originally requested If you specify that a memory is prefetchable it must have the 32 bit prefetchable memory following 2 attributes I O address space e Reads do not have side effects e Write merging is allowed The 32 bit prefetchable memory and I O address space BARs are only available for the Legacy Endpoint Size Not configurable Specifies the memory size calculated from other parameters you enter Table 3 3 Device ID Registers The following table lists the default values of the read only Device ID registers You can use the parameter editor to change the values of these registers Refer to Type 0 Configuration Space Registers for the layout of the Device Identification registers Vendor ID 16 bits 0x00000000 _ Sets the read only value of the vendor ID register This parameter cannot be set to OxFFFF per the PCI Express Specification Address offset 0x000 Device ID 16 bits 0x00000001 _ Sets the read only value of the Devi
16. Byteo lolo ojo 1011 0 tc Joljololo tp ep olo Length Byte 4 Completer ID Status B Byte Count Byte 8 Requester ID Tag 0 Lower Address Byte 12 Reserved TLP Packet Formats with Data Payload Figure A 10 Memory Write Request 32 Bit Addressing Memory Write Request 32 Bit Addressing 0 1 2 3 716 514 3 2 110 716 5141312 1 10 7 6 54 31211 0 17 61514113 2 41 0 Byteo ol olo 0 0 0 olo rc 0 0 0 0 1 z Jojo Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Figure A 11 Memory Write Request 64 Bit Addressing Memory Write Request 64 Bit Addressing 0 1 2 3 7 6 5413 1211 10 7 6 51411312 11 J0 7 6 5 4312 1 0 7 46 5 4 3 1274170 Byteo loli 1 0 000 0 o0 tc JololoJjo rp E in olo Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 63 32 Byte 12 Address 31 2 0 0 Altera Corporation Transaction Layer Packet TLP Header Formats GJ Send Feedback UG 01105_avmm
17. O Indicates the current speed of the PCIe link The following encodings are defined e 2b 00 Undefined e 2b01 Genl e 2b10 Gen2 e 2b11 Gen3 14h3C6C lane_act_reg 3 0 Lane Active Mode This signal indicates the number of lanes that configured during link training The following encodings are defined e 4b0001 1 lane e 40010 2 lanes e 450100 4 lanes e 41000 8 lanes Programming Model for Avalon MM Root Port The Application Layer writes the Root Port TLP TX Data registers with TLP formatted data for Configu ration Read and Write Requests Message TLPs I O Read and Write Requests or single dword Memory Read and Write Requests Software should check the Root Port Link Status register offset 0x92 to ensure the Data Link Layer Link Act ive bit is set to 1 b1 before issuing a Configuration request to downstream ports The Application Layer data must be in the appropriate TLP format with the data payload aligned to the TLP address Aligning the payload data to the TLP address may result in the payload data being either aligned or unaligned to the qword The following figure illustrates three dword TLPs with data that is aligned and unaligned to the qword Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Figure 5 10 Layout of Data with 3 Dword Headers Cycle 1 Cycle 2 Register 1 Register 0 Register 1 Register 0 Data Unaligned to QWord Boundary Header 1 63 32
18. RP RXCPL_REG1 RC Lower 32 bits of a Completion TLP Reading frees this entry in the FIFO 0x2018 Bio ACET RE RC Upper 32 bits of a Completion TLP Reading frees this entry in the FIFO Related Information Avalon MM Bridge TLPs on page 9 11 Uncorrectable Internal Error Mask Register Table 5 27 Uncorrectable Internal Error Mask Register The Uncorrectable Internal Error Mask register controls which errors are forwarded as internal uncorrectable errors With the exception of the configuration error detected in CvP mode all of the errors are severe and may place the device or PCIe link in an inconsistent state The configuration error detected in CvP mode may be correctable depending on the design of the programming software The access code RWS stands for Read Write Sticky meaning the value is retained after a soft reset of the IP core oB Register Description Reset Value 31 12 Reserved Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Uncorrectable Internal Error Status Register 5 33 its Register Description Reset Value 1b 1 11 Mask for RX buffer posted and completion overflow error 10 Reserved 1b 0 RO 9 Mask for parity error detected on Configuration Space to TX bus 1b 1 RWS interface 8 Mask for parity error detected on the TX to Configuration Space 1b 1 RWS bus interface 7 Mask for parity error detected at TX
19. Slave The above figure shows the that completer only single dword endpoint connects to a PCI Express root complex A bridge component includes the Arria V Hard IP for PCI Express TX and RX blocks an Avalon MM RX master and an interrupt handler The bridge connects to the FPGA fabric using an Avalon MM interface The following sections provide an overview of each block in the bridge RX Block The RX Block control logic interfaces to the hard IP block to process requests from the root complex It supports memory reads and writes of a single dword It generates a completion with Completer Abort CA status for read requests greater than four bytes and discards all write data without further action for write requests greater than four bytes The RX block passes header information to the Avalon MM master which generates the corresponding transaction to the Avalon MM interface The bridge accepts no additional requests while a request is being processed While processing a read request the RX block deasserts the ready signal until the TX block sends the corresponding completion packet to the hard IP block While processing a write request the RX block sends the request to the Avalon MM interconnect fabric before accepting the next request Avalon MM RX Master Block The 32 bit Avalon MM master connects to the Avalon MM interconnect fabric It drives read and write requests to the connected Avalon MM slaves performing the required address
20. TLPs into standard Avalon MM read and write commands typically used by master and slave interfaces This PCI Express to Avalon MM bridge also translates Avalon MM read write and read data commands to PCI Express read write and completion TLPs The following topics describe the Avalon MM bridges translations Avalon MM to PCl Express Write Requests The Avalon MM bridge accepts Avalon MM burst write requests with a burst size of up to 512 Bytes at the Avalon MM TX slave interface The Avalon MM bridge converts the write requests to one or more PCI Express write packets with 32 or 64 bit addresses based on the address translation configuration the request address and the maximum payload size The Avalon MM write requests can start on any address in the range defined in the PCI Express address table parameters The bridge splits incoming burst writes that cross a 4 KByte boundary into at least two separate PCI Express packets The bridge also considers the root complex requirement for maximum payload on the PCI Express side by further segmenting the packets if needed The bridge requires Avalon MM write requests with a burst count of greater than one to adhere to the following byte enable rules e The Avalon MM byte enables must be asserted in the first qword of the burst e All subsequent byte enables must be asserted until the deasserting byte enable e The Avalon MM byte enables may deassert but only in the last qword of the burst Note
21. This clock is used for PIPE simulation only and is derived from the refclk It is the PIPE interface clock used for PIPE mode simulation txswing0d Output When asserted indicates full swing for the transmitter voltage When deasserted indicates half swing tx_margin0 2 0 Output Transmit Vop margin selection The value for this signal is based on the value from the Link Control 2 Register Available for simulation only Notes 1 These signals are for simulation only For Quartus II software compilation these pipe signals can be left floating Interfaces and Signal Descriptions G Send Feedback Altera Corporation 4 32 Test Signals Test Signals Table 4 17 Test Interface Signals UG 01105_avmm 2014 12 15 The test_in bus provides run time control and monitoring of the internal state of the IP core O Sigal a Description O O test_in 31 0 Input The bits of the test_in bus have the following definitions e 0 Simulation mode This signal can be set to 1 to accelerate initialization by reducing the value of many initialization counters e 1 Reserved Must be set to 1 b0 e 2 Descramble mode disable This signal must be set to 1 during initialization in order to disable data scrambling You can use this bit in simulation for both Endpoints and Root Ports to observe descrambled data on the link Descrambled data cannot be used in open systems because the link partner typical
22. capitaliza tion matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets lt gt For example lt file name gt and lt project name gt pof file Additional Information Altera Corporation Send Feedback C 6 Typographic Conventions UG 01105_avmm 2014 08 18 a Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus II Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword suspeEsten and logic function names
23. 0 interrupt signal A e int_status 1 interrupt signal B e int_status 2 interrupt signal C e int_status 3 interrupt signal D kofeplisperdata NEON ko_cpl_spc_ header 7 0 Output Output The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion data Endpoints must advertise infinite space for completion data however RX buffer space is finite ko_cp1_spc_data is a static signal that reflects the total number of 16 byte completion data units that can be stored in the completion RX buffer The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion headers Endpoints must advertise infinite space for completion headers however RX buffer space is finite ko_cp1_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer I2 eie Output L2 exit This signal is active low and otherwise remains high It is asserted for one cycle changing value from 1 to 0 and back to 1 after the LTSSM transitions from 12 idle to detect When this pulse is asserted the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles lane_act 3 0 Output Lane Active Mode This signal indicates the number of lanes that configured during link training The following encodings are defined e 4b0001 1 lane e 4b0010 2 lanes e 450100 4 l
24. 16 57443 2 1 0 471615 4 3 2 4110 Byteo loli 0 0 101 1 0 c ojofojof ro z Jo fo Length Byte 4 Completer ID Status B Byte Count Byte 8 Requester ID Tag 0 Lower Address Byte 12 Reserved Figure A 16 Message with Data Message with Data 0 1 2 3 7 71615 0 7 6 15 4 7 6 5 4 3 42 170 Byte 0 0 210 0 TC 0 TD EP O0JO Length Byte 4 Requester ID Tag Message Code Byte 8 Vendor defined or all zeros for Slot Power Limit Byte 12 Vendor defined or all zeros for Slots Power Limit Transaction Layer Packet TLP Header Formats GJ Send Feedback Altera Corporation Lane Initialization and Reversal 2014 12 15 UG 01105_avmm s Subscribe G Send Feedback Connected components that include IP blocks for PCI Express need not support the same number of lanes The x4 variations support initialization and operation with components that have 1 2 or 4 lanes The x8 variant supports initialization and operation with components that have 1 2 4 or 8 lanes Lane reversal permits the logical reversal of lane numbers for the x1 x2 x4 and x8 configurations Lane reversal allows more flexibility in board layout reducing the number of signals that must cross over each other when routing the PCB Table B 1 Lane Assignments without Lane Reversal x8 IP core Lane 7 Number 7 6 5 4 3 2 1 0 x4IP
25. 19 0 are passed through and become PCI Express address bits 19 0 The address translation table is dynamically configured at run time The address translation table is implemented in memory and can be accessed through the CRA slave module Dynamic configuration is optimal in a typical PCI Express system where address allocation occurs after BIOS initialization For more information about how to access the dynamic address translation table through the CRA slave refer to the Avalon MM to PCI Express Address Translation Table 0x1000 0x1FFF on page 9 17 Altera Corporation IP Core Architecture GJ Send Feedback UG 01105_avmm 2014 12 15 Completer Only Single Dword Endpoint 9 19 Figure 9 10 Avalon MM to PCI Express Address Translation The following figure depicts the Avalon MM to PCI Express address translation process In this figure the variables represent the following paramers N the number of pass through bits M the number of Avalon MM address bits P the number of PCle address bits Q the number of translation table entries Sp 1 0 the space indication for each entry Low address bits unchanged Avalon MM Address Slave Base ities Hoh tow 31 M M 1 N N 1 PCI Express Address Avalon MM to PCI Express Address Translation Table P1 Q entries by P N bits wide PCle Address 0 N N 1 0 PCle Address 1 High Avalon MM Address PCI Express address from Table Ent
26. 23 0 cfg_msi_data 15 0 3 b00 0 cfg_busdev 12 0 Table 4 12 Configuration Space Register Descriptions es e e cfg_dev_ctrl_func lt n gt Output cfg_dev_ctrl_func lt n gt 15 0 is Device Control register for the PCI Express capability structure cfg_dev_ctrl2 16 Output cfg_dev2ctr1 15 0 is Device Control 2 for the PCI Express capability structure Interfaces and Signal Descriptions CJ Send Feedback Altera Corporation 4 22 Configuration Space Register Access UG 01105_avmm 2014 12 15 es E a e cfg_slot_ctrl Output cfg_slot_ctr1 15 0 is the Slot Status of the PCI Express capability structure This register is only available in Root Port mode Cig lans ciri 16 Output cfg_link_ctr1 15 0 is the primary Link Control of the PCI Express capability structure For Gen2 operation you must write a 1 b1 to the Retrain Link bit Bit 5 of the cf g_link_ctr1 of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 LO state Retraining directs the LTSSM to the Recovery state Retraining to a higher data rate is not automatic for the Arria V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate cfg_link_ctrl2 16 Output cfg_link_ctr12 31 16 is the secondary Link Control register of the PCI Express capability structure for Gen2 operation When tl_cfg_addr 4 b0010 tl_c
27. 64 or 128 for the full featured IP core lt w gt 32 for the completer only IP core Interfaces and Signal Descriptions Altera Corporation Send Feedback 4 4 RX Avalon MM Master Signals UG 01105_avmm 2014 12 15 RxmByteEnable_ lt n gt ol lt w gt 1 01 ii Output Byte enable for write data RXMBurstCount_ lt n gt _ol6 or Output The burst count measured in qwords of the RX write or anit read request The width indicates the maximum data that can be requested The maximum data in a burst is 512 bytes Bete eRe guest 27 Input _ Asserted by the external Avalon MM slave to hold data transfer PMR ease Output Asserted by the core to request a read BOI TNT cee eta Input Read data returned from Avalon MM slave in response to a read request This data is sent to the IP core through the TX interface lt w gt 64 or 128 for the full featured IP core lt w gt 32 for the completer only IP core RXMReadDataVvalid er Input Asserted by the system interconnect fabric to indicate that the read data on is valid RxmIrq_ lt n gt lt m gt 0 lt m gt lt 16 Input _ Indicates an interrupt request asserted from the system interconnect fabric This signal is only available when the CRA port is enabled Qsys generated variations have as many as 16 individual interrupt signals lt m gt lt 15 If rxm_irq_ lt n gt lt m gt 0 is asserted on consecutive cycles without the deassertion of all interrupt input
28. A2P_MB_IRQ4 request A2P_MAILBOX_INT3 enable A2P_MB_IROQ3 request A2P_MAILBOX_INT2 enable A2P_MB_IRQ2 request 4 A2P_MAILBOX_INT1 enable A2P_MB_IRQ1 request A2P_MAILBOX_INTO enable A2P_MB_IRQO request PCI Express Virtual INTA signalling When signal rises ASSERT_INTA Message Sent When signal falls DEASSERT_INTA Message Sent XL XL SET D 7 0 MSI Request CLR AV_IRQ_ASSERTED AVL_IRQ 4 oy apres MSI Enable Configuration Space Message Control Register 0 Related Information e Avalon MM to PCI Express Interrupt Enable Registers on page 5 16 e Avalon MM to PCI Express Interrupt Status Registers on page 5 15 Enabling MSI or Legacy Interrupts The PCI Express Avalon MM bridge selects either MSI or legacy interrupts automatically based on the standard interrupt controls in the PCI Express Configuration Space registers Software can write the Interrupt Disable bit which is bit 10 of the command register at Configuration Space offset 0x4 to disable legacy interrupts Software can write the MSI Enable bit which is bit 0 of the MSI control Status register in the MSI capability register bit 16 at configuration space offset 0x50 to enable MSI interrupts Software can only enable one type of interrupt at a time However to change the selection of MSI or legacy interrupts durin
29. Detected by the Physical Layer The following table describes errors detected by the Physical Layer Physical Layer error reporting is optional in the PCI Express Base Specification Receive port error Correctable This error has the following 3 potential causes e Physical coding sublayer error when a lane is in LO state These errors are reported to the Hard IP block via the per lane PIPE interface input receive status signals rxstatus lt lane_number gt 2 0 using the following encodings e 3 b100 8B 10B Decode Error e 3 b101 Elastic Buffer Overflow e 3 b110 Elastic Buffer Underflow e 3 b111 Disparity Error e Deskew error caused by overflow of the multilane deskew FIFO e Control symbol received in wrong lane Data Link Layer Errors Table 8 3 Errors Detected by the Data Link Layer a a Bad TLP Correctable This error occurs when a LCRC verification fails or when a sequence number error occurs Bad DLLP Correctable This error occurs when a CRC verification fails Replay timer Correctable This error occurs when the replay timer times out Replay num rollover Correctable This error occurs when the replay number rolls over Data Link Layer protocol Uncorrectable fatal This error occurs when a sequence number specified by the Ack Nak block in the Data Link Layer AckNak_Seq_ Num does not correspond to an unacknowledged TLP Altera Corporation Error Handling CJ Send Feedback UG 01105_avmm
30. Mapping for TC4 Mapping for TCS Mapping for TC6 Mapping for TC7 e cfg_tcvcmap 5 e cfg_tcvcmap 8 e cfg_tcvcmap 14 1 e cfg_tcvcmap 17 1 e cfg_tcvcmap 20 1 2 5 8 1 e cfg_tcvcmap 23 2 14 h3C5C eroen imdat ai 153 0 cfg_msi_data 15 0 is message data for MSI 14 h3C60 cfg_busdev 12 0 Bus Device Number captured by or programmed in the Hard IP 14 h3C64 Registers J send Feedback ltssm_reg 4 0 Specifies the current LTSSM state The LTSSM state machine encoding defines the following states e 00000 Detect Quiet e 00001 Detect Active e 00010 Polling Active e 00011 Polling Compliance e 00100 Polling Configuration e 00101 Polling Speed e 00110 config Linkwidthstart e 00111 Config Linkaccept e 01000 Config Lanenumaccept e 01001 Config Lanenumwait e 01010 Config Complete e 01011 Config Idle e 01100 Recovery Rcvlock e 01101 Recovery Rcvconfig e 01110 Recovery Idle e 01111 LO e 10000 Disable e 10001 Loopback Entry e 10010 Loopback Active Altera Corporation UG 01105_avmm 5 26 Programming Model for Avalon MM Root Port 2014 12 15 10011 Loopback Exit e 10100 Hot Reset e 10101 LOs e 11001 L2 transmit Wake e 11010 Speed Recovery e 11011 Recovery Equalization Phase 0 e 11100 Recovery Equalization Phase 1 e 11101 Recovery Equalization Phase 2 e 11110 recovery Equalization Phase 3 14h3C68 current_speed_reg 1 0
31. RX Avalon MM master forwards all RX TLPs to the Qsys interconnect The Avalon MM RX master module port has an 8 byte datapath in 64 bit mode and a 16 byte datapath in 128 bit mode The Qsys interconnect fabric manages mismatched port widths transparently As Memory Request TLPs are received from the PCIe link the most significant bits are used in the BAR matching as described in the PCI specifications The least significant bits not used in the BAR match process are passed unchanged as the Avalon MM address for that BAR s RX Master port For example consider the following configuration specified using the Base Address Registers in the parameter editor 1 BAR1 0 is a 64 bit prefetchable memory that is 4KBytes 12 bits System software programs BAR1 0 to have a base address of 0x0000123456789000 A TLP received with address 0x0000123456789870 The upper 52 bits 0x0000123456789 are used in the BAR matching process so this request matches The lower 12 bits 0x870 are passed through as the Avalon address on the Rxm_BARO Avalon MM Master port The BAR matching software replaces the upper 20 bits of the address with the Avalon MM base address a kW N Related Information Avalon MM to PCI Express Address Translation Algorithm for 32 Bit Addressing on page 9 17 Altera Corporation IP Core Architecture GJ Send Feedback UG 01105_avmm 2014 12 15 Minimizing BAR Sizes and the PCle Address Space 9 15 Minimizing BAR Sizes and the
32. Read Request 64 Bit Addressing Memory Read Request 64 Bit Addressing 0 1 2 3 7 6 5 4 3 2 1 0 7 6 5 4 1101017 6 5 4 2 1 71 6 5 4 3 42 1 40 Att Byte 0 0 0 0 0 0 0 0 0 0 TC 0 0 TD EP r 010 Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 63 32 Byte 12 Address 31 2 0 0 Figure A 4 Memory Read Request Locked 64 Bit Addressing Memory Read Request Locked 64 Bit Addressing 0 1 2 3 716 5 4 3 2 1 0 7 6 5 1 4 2 11017 6 5413121101 7615 4 3 4241 40 Byteo lolo 1 0 0 0 01 0 ve ololol r ep et lofo Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 63 32 Byte 12 Address 31 2 0 0 Figure A 5 Configuration Read Request Root Port Type 1 Configuration Read Request Root Port Type 1 0 1 2 3 71 6 5 4 3 2 1 0 7 6 5 4 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 11 10 Byte 0 0 0 0 0 0 10 1 0 0 0 0 0 TD EP 0 0 0 0 0 0000000 0 1 Byte 4 Requester ID Tag 0 0 0 0 First BE Byte 8 Bus Number Device No Func 0 O 0 0O Ext Reg Register No 0 0 Byte 12 Reserved Altera Corporation Transaction Layer Packet TLP Header Formats GJ Send Feedback UG 01105_avmm
33. Refer to Interrupts for Endpoints for the definitions of MSI MSI X and INTx buses For more information about implementing MSI or MSI X interrupts refer to the PCI Local Bus Specifica tion Revision 2 3 MSI X ECN For more information about implementing interrupts including an MSI design example refer to Handling PCIe Interrupts on the Altera wiki Related Information e Interrupts for Endpoints on page 7 1 e PCI Local Bus Specification Revision 2 3 Handling PCIe Interrupts Altera Corporation Interrupts for Endpoints GJ Send Feedback Error Handling 2014 12 15 UG 01105_avmm ZA Subscribe Send Feedback Each PCI Express compliant device must implement a basic level of error management and can optionally implement advanced error management The IP core implements both basic and advanced error reporting Error handling for a Root Port is more complex than that of an Endpoint Table 8 1 Error Classification The PCI Express Base Specification defines three types of errors outlined in the following table Correctable Hardware While correctable errors may affect system performance data integrity is maintained Uncorrectable non fatal Device software Uncorrectable non fatal errors are defined as errors in which data is lost but system integrity is maintained For example the fabric may lose a particular TLP but it still works without problems Uncorrectable fatal System software Errors generated by a los
34. are also available for Root Ports For more information about these TLPs refer to Avalon MM Bridge TLPs Table 5 26 Root Port TLP Data Registers 0x2000 0x2FFF Root Port Request Registers Address Range 0x2800 0x2018 e e e 0x2000 31 0 RP TX REGO Lower 32 bits of the TX TLP 0x2004 51 0 BRE IX RECI W Upper 32 bits of the TX TLP 31 2 Reserved 1 RP TE ONDE 28 W Write 1 b1 to specify the of end a packet 0x2008 Writing this bit frees the corresponding entry in the FIFO 0 RE TX CNTR SOP W Write 1 b1 to specify the start of a packet Registers Altera Corporation G Send Feedback UG 01105_avmm 2014 12 15 Root Port Request Registers Address Range 0x2800 0x2018 5 32 Uncorrectable Internal Error Mask Register a e e Reserved 15 8 RP RXCPL_STATUS R Specifies the number of words in the RX completion FIFO that contain valid data Reserved 1 RP_RXCPL_STATUS EOP R When 1 b1 indicates that the data for a Completion TLP is ready to be read by the Application Layer The Application Layer must poll this bit to determine when a Completion TLP is available 0x2010 0 Ss o HOP R When 1 b1 indicates that the final data for a Completion TLP is ready to be read by the Application Layer The Application Layer must poll this bit to determine when the final data for a Completion TLP is available 0x2014 31 0
35. at the PCI Express link level as opposed to component communication by TLP transmission in the interconnect fabric The DLL implements the following functions e Link management through the reception and transmission of DLL packets DLLP which are used for the following functions Altera Corporation Power management of DLLP reception and transmission To transmit and receive AcK NACK packets Data integrity through generation and checking of CRCs for TLPs and DLLPs TLP retransmission in case of nak DLLP reception using the retry buffer Management of the retry buffer Link retraining requests in case of error through the Link Training and Status State Machine LTSSM of the Physical Layer IP Core Architecture GJ Send Feedback UG 01105_avmm Ale 2014 12 15 Data Link Layer Figure 9 2 Data Link Layer To Transaction Layer To Physical Layer Tx Transaction Layer ae Packet Description amp Data Transaction Layer pare Packet Generator j gt Tx Packets Retry Buffer TR TX Datapath Ack Nack Packets Data Link Control a Fims Power and Management atus ag B gt Management State Machine Tx Flow Control Credits Function Rx Flow Control Credits E RX Datapath ecker lt Transaction Layer Packet Checker a Rx Packets Rx Transation Layer Packet Description amp Data The DLL has the following sub blocks e Data Link Control and Management
36. block e On the RX side the block decodes the Physical Layer packet and reports to the LTSSM the type and number of TS1 TS2 ordered sets received e On the TX side the block multiplexes data from the DLL and the LTSTX sub block It also adds lane specific information including the lane number and the force PAD value when the LTSSM disables the lane during initialization e LTSSM This block implements the LTSSM and logic that tracks TX and RX data on each lane e For transmission it interacts with each MAC lane sub block and with the LTSTX sub block by asserting both global and per lane control bits to generate specific Physical Layer packets e On the receive path it receives the Physical Layer packets reported by each MAC lane sub block It also enables the multilane deskew block This block reports the Physical Layer status to higher layers e LTSTX Ordered Set and SKP Generation This sub block generates the Physical Layer packet It receives control signals from the LTSSM block and generates Physical Layer packet for each lane It generates the same Physical Layer Packet for all lanes and PAD symbols for the link or lane number in the corresponding TS1 TS2 fields The block also handles the receiver detection operation to the PCS sub layer by asserting predefined PIPE signals and waiting for the result It also generates a SKP Ordered Set at every predefined timeslot and interacts with the TX alignment block to prevent the insertion o
37. can enter it as a parameter value in the Transceiver Reconfiguration Controller parameter editor The following figure illustrates the messages reported for a Gen2 x4 variant The variant requires five interfaces one for each lane and one for the TX PLL Figure 12 2 Number of External Reconfiguration Controller Interfaces ep_g2x4 DUT 5 reconfiguration interfaces are required for connection to the external reconfiguration controller and the reconfig driver ep_g2x4 DUT Credit allocation in the 16 KBytes receive buffer ep_g2x4 DUT Posted header 16 data 16 l ep_g2x4 DUT Non posted header 16 data 0 ep_g2x4 DUT Completion header 195 data 781 When you instantiate the Transceiver Reconfiguration Controller you must specify the required Number of reconfiguration interfaces as the following figure illustrates Figure 12 3 Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V Devices Transceiver Reconfiguration Controller alt_xcvwr_reconfig Parameters Device family Interface Bundles Number of reconfiguration interfaces 10 Optional interface grouping e g 2 2 or leave blank for a single bundle Transceiver Calibration functions NOTE please refer to the device handbook for reset sequence requirements between the reconfiguration controller and transceiver PHY yj Enable offset cancellati Enable duty cycle calib
38. data width number of lanes Application Layer clock frequency and data rate Specifies the address width for Avalon MM RX master ports that access Avalon MM slaves in the Avalon address domain When you select 32 bit addresses the PCI Express Avalon MM Bridge performs address translation When you specify 64 bits addresses no address translation is performed in either direction The destination address specified is forwarded to the Avalon MM interface without any changes For the Avalon MM interface with DMA this value must be set to 64 Peripheral mode Requester Completer Completer Only Specifies whether the Avalon MM Arria V Hard IP for PCI Express is capable of sending requests to the upstream PCI Express devices and whether the incoming requests are pipelined Requester Completer In this mode the Hard IP can send request packets on the PCI Express TX link and receive request packets on the PCI Express RX link Completer Only In this mode the Hard IP can receive requests but cannot initiate upstream requests However it can transmit completion packets on the PCI Express TX link This mode removes the Avalon MM TX slave port and thereby reduces logic utilization Parameter Settings CJ Send Feedback Altera Corporation 3 10 Avalon Memory Mapped System Settings UG 01105_avmm 2014 12 15 Single DW Completer On Off This is a non pipelined version of Completer Only mode At any time
39. files for synthesis lt your_ip gt v or vhd Top level IP variation synthesis file testbench Simulation testbench files 1 f lt testbench_hdl_files gt lt simulator_vendor gt Testbench for supported simulators lt simulation_testbench_files gt lt your_ip gt _tb Testbench for supported simulators f lt your_ip gt _tb v or vhd Top level HDL testbench file Notes 1 If supported and enabled for your IP variation 2 If functional simulation models are generated Programming a Device After you compile your design you can program your targeted Altera device and verify your design in hardware For more information about programming Altera FPGAs refer to Quartus II Programmer Getting Started with the Avalon MM Arria V Hard IP for PCI Express Altera Corporation G Send Feedback j z UG 01105_avmm 2 8 Programming a Device 2014 12 15 Related Information Quartus II Programmer Altera Corporation Getting Started with the Avalon MM Arria V Hard IP for PCI Express GJ Send Feedback Parameter Settings 2014 12 15 UG 01105_avmm amp Subscribe Send Feedback Avalon MM System Settings Table 3 1 System Settings for PCI Express Number of Lanes xl x2 x4 x8 Specifies the maximum number of lanes supported Lane Rate Gen1 2 5 Gbps Specifies the maximum data rate at which the link can operate Gen2 2 5
40. for example TRI 1 2 3 anda b c and so on An angled arrow instructs you to press the Enter key Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 The hand points to information that requires special attention h The question mark directs you to a software help system with related information f The feet direct you to another document or website with related information m The multimedia icon directs you to a related multimedia presentation c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work Altera Corporation Additional Information GJ Send Feedback UG 01105_avmm 2014 08 18 Typographic Conventions C 7 C w A warning calls attention to a condition or possible situation that can cause you injury The Subscribe button links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The Feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Related Information Email Subscription Management Center Additional Information Altera Corporation LJ Send Feedback
41. lower than the coreclkout_hip frequency Based on specific Application Layer constraints a PLL can be used to derive the desired frequency Clock Summary Table 6 3 Clock Summary coreclkout_hip 62 5 125 or 250 MHz Avalon ST interface between the Transaction and Application Layers pleLelk 62 5 125 or 250 MHz Application and Transaction Layers refclk 100 or 125 MHz SERDES transceiver Dedicated free running input clock to the SERDES block reconfig zevi cilk 10 125 MHz Transceiver Reconfiguration Controller Reset and Clocks G Send Feedback Altera Corporation Interrupts for Endpoints 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback The PCI Express Avalon MM bridge supports MSI or legacy interrupts The completer only single dword variant includes an interrupt handler that implements both INTX and MSI interrupts Support requires instantiation of the CRA slave module where the interrupt registers and control logic are implemented The PCI Express Avalon MM bridge supports the Avalon MM individual requests interrupt scheme multiple input signals indicate incoming interrupt requests and software must determine priorities for servicing simultaneous interrupts The RX master module port has up to 16 Avalon MM interrupt input signals Rxmirq_irq lt n gt 0 where lt n gt lt 15 Each interrupt signal indicates a distinct interrupt source Assertion of any of these signals or a PCI Express
42. lt variant gt _tb simulation submodules lt variant gt v 2 Search for the string hip_hard_reset_hwtcl 3 Ifhip_hard_reset_hwtcl 1 the hard reset controller is active Set hip_hard_reset_hwtcl 0 to change to the soft reset controller 4 Save variant v Use Third Party PCle Analyzer Debugging A third party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic saving you the trouble of translating the symbols yourself A third party logic analyzer can show the two way traffic at different levels for different requirements For high level diagnostics the analyzer shows the LTSSM flows for devices on both side of the link side by side This display can help you see the link training handshake behavior and identify where the traffic gets stuck A traffic analyzer can display the contents of packets so that you can verify the contents For complete details refer to the third party documentation Altera Corporation LJ Send Feedback UG 01105_avmm 13 4 BIOS Enumeration Issues 2014 12 15 BIOS Enumeration Issues Both FPGA programming configuration and the initialization of a PCIe link require time Potentially an Altera FPGA including a Hard IP block for PCI Express may not be ready when the OS BIOS begins enumeration of the device tree If the FPGA is not fully programmed when the OS BIOS begins its enumeration the OS does not include the Hard IP for PCI Express in its device map You c
43. only a single request can be outstanding Single dword completer uses fewer resources than Completer Only This variant is targeted for systems that require simple read and write register accesses from a host CPU If you select this option the width of the data for RXM BAR masters is always 32 bits regardless of the Avalon MM width For the Avalon MM interface with DMA this value must be Off Control register access CRA Avalon MM slave port On Off Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port This option is required for Requester Completer variants and optional for Completer Only variants Enabling this option allows read and write access to bridge registers except in the Completer Only single dword variations Enable multiple MSI MSI X support On Off When you turn this option On the core exports top level MSI and MSI X interfaces that you can use to implement a Customer Interrupt Handler for MSI and MSI X interrupts For more information about the Custom Interrupt Handler refer to Interrupts for End Points Using the Avalon MM Interface with Multiple MSI MSI X Support If you turn this option Off the core handles interrupts internally Auto enabled PCIe interrupt enabled at power on On Off Turning on this option enables the Avalon MM Arria V Hard IP for PCI Express interrupt register at power up Turning off this option disable
44. pps Name ecess Description O 31 5 Reserved N A NIA Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 PCI Express Mailbox Registers 5 17 LS O AVL_IRQ Vector 15 0 Stores the interrupt vector of the system interconnect fabric The host software should read this register after being interrupted and determine the servicing priority PCI Express Mailbox Registers The PCI Express Root Complex typically requires write access to a set of PCI Express to Avalon MM mailbox registers and read only access to a set of Avalon MM to PCI Express mailbox registers Eight mailbox registers are available The pct Express to Avalon MM Mailbox registers are writable at the addresses shown in the following table Writing to one of these registers causes the corresponding bit in the Avalon MM Interrupt Status register to be set to a one Table 5 16 PCI Express to Avalon MM Mailbox Registers 0x0800 0x081F ee ee 0x0800 P2A_MAILBOXO PCI Express to Avalon MM Mailbox 0 Ox0S04 P2e EE RW PCI Express to Avalon MM Mailbox 1 0x0808 P2A_MAILBOX2 RW _ PCI Express to Avalon MM Mailbox 2 Ox0S0G Paes E RW PCI Express to Avalon MM Mailbox 3 0x0810 P2A MAILBOX4 RW __ PCI Express to Avalon MM Mailbox 4 Ox09 145 AS RW PCI Express to Avalon MM Mailbox 5 0x0818 P2A MAILBOX6 RW PCI Express to Avalon MM Mailbox 6 CGC Pen aT Lees RW
45. slave port propagates requests from the interconnect fabric to the full featured Avalon MM Arria V Hard IP for PCI Express Requests from the interconnect fabric are translated into PCI Express request packets Incoming requests can be up to 512 bytes For better performance Altera recommends using smaller read request size a maximum of 512 bytes Interfaces and Signal Descriptions Altera Corporation G Send Feedback 4 6 64 or 128 Bit Bursting TX Avalon MM Slave Signals Table 4 3 Avalon MM TX Slave Interface Signals UG 01105_avmm 2014 12 15 TxsChipSelect_i Input The system interconnect fabric asserts this signal to select the TX slave port TxsRead_i Input Read request asserted by the system interconnect fabric to request a read TxsWrite_i Input Write request asserted by the system interconnect fabric to request a write TxsWriteData 127 or 63 0 Input Write data sent by the external Avalon MM master to the TX slave port TxsBurstCount 6 or 5 0 Input Asserted by the system interconnect fabric indicating the amount of data requested The count unit is the amount of data that is transferred in a single cycle that is the width of the bus The burst count is limited to 512 bytes TxsAddress_i lt w gt 1 0 Input Address of the read or write request from the external Avalon MM master This address translates to 64 bit or 32 bit PCI Express addresses based on the trans
46. terminal window a do msim_setup tcl b 1a_debug The debug suffix stops optimizations improving visibility in the ModelSim waveforms c run 140000 ns Getting Started with the Avalon MM Arria V Hard IP for PCI Express GJ Send Feedback UG 01105_avmm 2014 12 15 Understanding Channel Placement Guidelines 2 5 Understanding Channel Placement Guidelines Arria V transceivers are organized in banks The transceiver bank boundaries are important for clocking resources bonding channels and fitting Refer to the channel placement figures following Serial Interface Signals for illustrations of channel placement Generating Quartus II Synthesis Files 1 2 On the Generate menu select Generate HDL For Create HDL design files for synthesis select Verilog You can leave the default settings for all other items Click Generate to generate files for Quartus II synthesis Click Finish when the generation completes Compiling the Design in the Quartus II Software To compile the Qsys design example in the Quartus II software you must create a Quartus II project and add your Qsys files to that project Complete the following steps to create your Quartus II project 1 2 Click the New Project Wizard icon Click Next in the New Project Wizard Introduction The introduction does not appear if you previously turned it off On the Directory Name Top Level Entity page enter the following information a The working d
47. the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134 12 2 z z a UG 01105_avmm Connecting the Transceiver Reconfiguration Controller IP Core 2014 12 15 As this figure illustrates the reconfig_to_xcvr lt n gt 70 1 0 and reconfig_from_xcvr lt n gt 46 1 0 buses connect the two components You must provide a 100 125 MHz free running clock to the mgmt _clk_c1k clock input of the Transceiver Reconfiguration Controller IP Core Initially each lane and TX PLL require a separate reconfiguration interface The parameter editor reports this number in the message pane You must take note of this number so that you
48. translation The RX master supports all legal combinations of byte enables for both read and write requests For more information about legal combinations of byte enables refer to Avalon Memory Mapped Interfaces in the Avalon Interface Specifications Related Information Avalon Interface Specifications Altera Corporation IP Core Architecture G send Feedback UG 01105_avmm 2014 12 15 TX Block 9 21 TX Block The TX block sends completion information to the Avalon MM Hard IP for PCI Express which sends this information to the root complex The TX completion block generates a completion packet with Completer Abort CA status and no completion data for unsupported requests The TX completion block also supports the zero length read flush command Interrupt Handler Block The interrupt handler implements both INTX and MSI interrupts The msi_enable bit in the configura tion register specifies the interrupt type The msi_enable_bit is part of the MSI message control portion in the MSI Capability structure It is bit 16 of address 0x050 in the Configuration Space registers If the msi_en able bit is on an MSI request is sent to the Arria V Hard IP for PCI Express when received otherwise INTX is signaled The interrupt handler block supports a single interrupt source so that software may assume the source You can disable interrupts by leaving the interrupt signal unconnected in the IRQ column of Qsys When the MSI registers in the Con
49. writes into PCI Express TLPs The Avalon MM read and write commands are the same as those used by master and slave interfaces to access memories and registers Consequently you do not need a detailed understanding of the PCI Express TLPs to use this Avalon MM variant 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 4 2 32 Bit Non Bursting Avalon MM Control Register Access CRA Slave Signals 32 Bit Avalon MM CRA
50. 0 PCI Express Enhanced Capability Register 0x804 Uncorrectable Error Status Register 0x808 Uncorrectable Error Mask Register 0x80C Uncorrectable Error Severity Register 0x810 Correctable Error Status Register 0x814 Correctable Error Mask Register 0x818 Advanced Error Capabilities and Control Register 0x81C Header Log Register 0x82C Root Error Command Register 0x830 Root Error Status Register 0x834 Error Source Identification Register Correctable Error Source Identification Register Registers G Send Feedback Altera Corporation 5 8 PCI Express Capability Structures Figure 5 7 PCI Express Capability Structure Byte Address Offsets and Layout UG 01105_avmm 2014 12 15 In the following table showing the PCI Express Capability Structure registers that are not applicable to a device are reserved Altera Corporation 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 Ox0A4 Ox0A8 Ox0AC 0x0B0 0x0B4 Ox0B8 31 24 23 16 15 87 PCI Express Capabilities Register Next Cap Pointer aed Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status Slot Control Root Capabilities Root Control Root Status Device Compatibilities 2 Device Status 2 Device Control 2 Link Capabilities 2 Link Status 2 Link Control 2 Slot Capabilities 2 Slot Status 2 Slot Control 2 Registers GJ Send Fee
51. 1 20 Next Capability Offset Starting address of the next Capability Variable RO Structure implemented if any Registers GJ Send Feedback Altera Corporation UG 01105_avmm 5 10 CvP Registers 2014 12 15 Table 5 3 Altera Defined Vendor Specific Header You can specify these values when you instantiate the Hard IP These registers are read only at run time Register Description EET Access 15 0 VSEC ID A user configurable VSEC ID User entered RO 19 16 VSEC Revision A user configurable VSEC revision Variable RO 31 20 VSEC Length Total length of this structure in bytes 0x044 RO Table 5 4 Altera Marker Register 31 0 Altera Marker This read only register is an additional marker If you use the standard Altera Programmer software to configure the device with CvP this marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC A Device Value Table 5 5 JTAG Silicon ID Register 127 96 Te Seon Application Specific 95 64 TAG ilicom ID MiA Application RO Specific 63 32 JTAG SA DLGON LD DWL Application RO Specific 31 0 JTAG Silicon ID DWO This is the JTAG Silicon ID that CvP Application RO programming software reads to determine that the correct SRAM Specific object file sof is being used Table 5 6 User Device or Board Type ID Register 15 0 Configurable devi
52. 105_avmm B 2 Lane Initialization and Reversal 2014 12 15 Figure B 1 Using Lane Reversal to Solve PCB Routing Problems The following figure illustrates a PCI Express card with x4 IP Root Port and a x4 Endpoint on the top side of the PCB Connecting the lanes without lane reversal creates routing problems Using lane reversal solves the problem No Lane Reversal With Lane Reversal Results in PCB Routing Challenge Signals Route Easily Root Port Endpoint Root Port Endpoint 0 3 0 0 1 2 no lane 1 1 lane 2 1 reversal 2 2 reversal 3 0 3 3 Altera Corporation Lane Initialization and Reversal GJ Send Feedback Additional Information 2014 08 18 UG 01105_avmm ZA Subscribe G Send Feedback Revision History for the Avalon MM Interface 2014 12 15 14 1 Made the following changes to the user guide e Inthe figured titled Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V Devices removed the Calibrate duty cycle during power up Duty cycle calibration occurs during Gen1 to Gen2 speed changes This is no longer a parameter than you can turn on and off e Corrected discussion of soft and hard reset controllers The hardened reset controller is used for Arria V and Cyclone V devices e Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages For other package types the CvP functionality is in the bottom right bloc
53. 14 12 15 Serial Interface Signals 4 25 a 6 4 multiple message This field indicates permitted values for MSI signals For example enable if 100 is written to this field 16 MSI signals are allocated e 3 b000 1 MSI allocated e 3 b001 2 MSI allocated e 37b010 4 MSI allocated e 3 b011 8 MSI allocated e 3 b100 16 MSI allocated e 3 b101 32 MSI allocated e 3 b110 Reserved e 3b111 Reserved 3 1 multiple message This field is read by system software to determine the number of capable requested MSI messages e 3 b000 1 MSI requested e 3 b001 2 MSI requested e 37b010 4 MSI requested e 37 b011 8 MSI requested e 37b100 16 MSI requested e 3b101 32 MSI requested e 37b110 Reserved 0 MSI Enable If set to 0 this component is not permitted to use MSI Related Information e PCI Express Base Specification 2 1 or 3 0 e PCI Local Bus Specification Rev 3 0 Serial Interface Signals Table 4 14 Serial Interface Signals In the following table lt n gt 1 2 4 or 8 O Sioa O Direction Description O O tx_out lt n gt 1 0 Output Transmit input These signals are the serial outputs rx_in lt n gt 1 0 Input _ Receive input These signals are the serial inputs Refer to Pin out Files for Altera Devices for pin out tables for all Altera devices in pdf txt and xls formats Interfaces and Signal Descriptions Altera Corporation QJ Send Feedback g X UG 01105_a
54. 15 0 O cfg_devctr1 15 0 is device control for the PCI Express capability structure 14 h3C04 cfg_dev_ctrl2 15 0 O cfg_dev2ctrl 15 0 is device control 2 for the PCI Express capability structure Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Control Register Access CRA Avalon MM Slave Port 5 23 14 h3C08 cfg_link_ctrl1 15 0 efg_link_ctr1 15 0 is the primary Link Control of the PCI Express capability structure For Gen2 or Gen3 operation you must write a 1 b1 to Retrain Link bit Bit 5 of the cfg_link_ctrl of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 LO state Retraining directs the LTSSM to the Recovery state Retraining to a higher data rate is not automatic for the Arria V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate 14 h3C0C cfg_link_ctrl2 15 0 cfg_link_ctr12 31 16 is the secondary Link Control register of the PCI Express capability structure for Gen2 operation When t1_cfg_addr 2 tl_cfg_ct1 returns the primary and secondary Link Control registers tere lank crel L530 Cite Link ctr12 15 0 the primary Link Status register contents is available on t1_cfg_sts 46 31 For Gen1 variants the link bandwidth notification bit is always set to 0 For Gen2 variants this bit is set to 1 14 h3C10 cfg_prm cmd 15 0 Base Primary Command register
55. 2 cycles app_rstn This reset sequence includes the following steps 1 After pin_perst or npor is released the Hard IP reset controller waits for pl1d_clk_inuse to be asserted 2 csrt and srst are released 32 cycles after pld_clk_inuse is asserted The Hard IP for PCI Express deasserts the reset_status output to the Application Layer 4 The altpcied_ lt device gt v_hwtcl sv deasserts app_rstn 32 pld_clkcycles after reset_status is released W Reset and Clocks Altera Corporation G Send Feedback EREA UG 01105_avmm 6 4 Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 2014 12 15 Figure 6 3 RX Transceiver Reset Sequence busy_xcvr_reconfig rx_pll_locked rx_analogreset Itssmstate 4 0 01 txdetectrx_loopback pipe_phystatus pipe_rxstatus 2 0 3 0 rx_signaldetect rx_freqlocked rx_digitalreset The RX transceiver reset sequence includes the following steps 1 After rx_pl1_locked is asserted the LTSSM state machine transitions from the Detect Quiet to the Detect Active state 2 When the pipe_phystatus pulse is asserted and pipe_rxstatus 2 0 3 the receiver detect operation has completed The LTSSM state machine transitions from the Detect Active state to the Polling Active state The Hard IP for PCI Express asserts rx_digitalreset The rx_digitalreset signal is deasserted after rx_signaldetect is stable for a minimum of 3 ms A Ww
56. 20 PCI Express to Avalon MM Interrupt Status and Enable Registers for Endpoints 2014 12 15 a E ERB SEC Te READ FALLURE RWIC_ When set to 1 indicates the failure of a PCI Express read This bit can also be cleared by writing a 1 to the same bit in the Avalon MM to PCI Express Interrupt Status register 15 2 Reserved 16 PZA MATLBOX INTO RWIC 1 when the P2A_MAILBOXO is written 17 PZR MATEBOX TNEI RWIC 1 when the P2A_MAILBOX is written 18 PZA MATLEOX INTZ RWIC 1 when the P2A_MAILBOXZ2 is written 19 PZA MATLBOX INT3 RWIC_ 1 when the P2A_MAILBOX3 is written 20 ee INTA RWIC_ 1 when the P2A_MAILBOX4 is written 21 PZA MATEBOX INTS RWIC 1 when the P2A_MAILBOXS5 is written 22 PLA MATLEOH_ INTG RWIC_ 1 when the P2A_MAILBOX6 is written 23 PZA MA TEBOX TENT RWIC 1 when the P2A_ MAILBOX7 is written 31 24 Reserved An Avalon MM interrupt can be asserted for any of the conditions noted in the Avalon MM Interrupt Status register by setting the corresponding bits in the PCI Express to Avalon MM Interrupt Enable register PCI Express interrupts can also be enabled for all of the error conditions described However it is likely that only one of the Avalon MM or PCI Express interrupts can be enabled for any given bit Typically a single process in either the PCI Express or Avalon MM domain handles the condition reported by the interrupt Altera Corpo
57. 2014 12 15 packets can be transmitted If you encounter link training issues viewing the actual data in hardware should help you determine the root cause You can use the following tools to provide hardware visibility e SignalTap II Embedded Logic Analyzer e Third party PCIe analyzer You can use SignalTap II Embedded Logic Analyzer to diagnose the LTSSM state transitions that are occurring on the PIPE interface The 1tssmstate 4 0 bus encodes the status of LTSSM The LTSSM state machine reflects the Physical Layer s progress through the link training process For a complete description of the states these signals encode refer to Status Link Training and Reset Signals When link training completes successfully and the link is up the LTSSM should remain stable in the LO state When link issues occur you can monitor 1tssmstate 4 0 to determine the cause Related Information Reset Setting Up Simulation Changing the simulation parameters reduces simulation time and provides greater visibility Changing Between Serial and PIPE Simulation By default the Altera testbench runs a serial simulation You can change between serial and PIPE simulation by editing the top level testbench file The hip_ctrl_simu_mode_pipe signal and enable _pipe32_sim_hwtcl parameter specify serial or PIPE simulation When both are set to 1 b0 the simulation runs in serial mode When both are set to 1 b1 the simulation runs in PIPE mode Complete the followin
58. 32 bit qword aligned offset This field is read only PBA BAR Indicator Parameter Settings Send Feedback 2 0 Specifies the function Base Address registers located beginning at 0x10 in Configuration Space that maps the MSI X PBA into memory space This field is read only Legal range is 0 5 Altera Corporation UG 01105_avmm 3 8 Power Management 2014 12 15 Power Management Table 3 8 Power Management Parameters Endpoint LOs Maximum of 64ns__ This design parameter specifies the maximum acceptable acceptable Mannois latency that the device can tolerate to exit the LOs state for any latency links between the device and the root complex It sets the Maximum of 256 ns read only value of the Endpoint LOs acceptable latency field of Maximum of 512 ns the Device Capabilities Register 0x084 This Endpoint does not support the LOs or L1 states However in a switched system there may be links connected to switches Maximum of 2 us that have LOs and L1 enabled This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link No limit to determine which links can enable Active State Power Management ASPM This setting is disabled for Root Ports Maximum of 1 us Maximum of 4 us The default value of this parameter is 64 ns This is the safest setting for most designs Endpoint L1 Maximum oflus T
59. 5 0 Gbps Port type Root Port Specifies the port type Altera recommends Native Endpoint 2 for all new Endpoint designs The Legacy Endpoint is not Native Endpotnt available for the Avalon MM Arria V Hard IP for PCI Express The Endpoint stores parameters in the Type 0 Configuration Space The Root Port stores parameters in the Type 1 Configu ration Space RX Buffer credit Minimum Determines the allocation of posted header credits posted allocation Tae data credits non posted header credits completion header performance for credits and completion data credits in the 16 KByte RX buffer received requests Balanced The 5 settings allow you to adjust the credit allocation to optimize your system The credit allocation for the selected setting displays in the message pane Refer to the Throughput Optimization chapter for more information about optimizing performance The Flow Control chapter explains how the RX credit allocation and the Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits You can set the Maximum payload size parameter on the Device tab 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademar
60. Ae 2014 12 15 Transaction Layer Errors Transaction Layer Errors Table 8 4 Errors Detected by the Transaction Layer a a Poisoned TLP received Uncorrectable This error occurs if a received Transaction Layer packet non fatal has the EP poison bit set The received TLP is passed to the Application Layer and the Application Layer logic must take appropriate action in response to the poisoned TLP Refer to 2 7 2 2 Rules for Use of Data Poisoning in the PCI Express Base Specification for more information about poisoned TLPs ECRC check failed Uncorrectable This error is caused by an ECRC check failing despite non fatal the fact that the TLP is not malformed and the LCRC check is valid The Hard IP block handles this TLP automatically If the TLP is a non posted request the Hard IP block generates a completion with completer abort status In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer Unsupported Request for Uncorrectable This error occurs whenever a component receives any of Endpoints non fatal the following Unsupported Requests e Type 0 Configuration Requests for a non existing function e Completion transaction for which the Requester ID does not match the bus device and function number e Unsupported message e A Type 1 Configuration Request TLP for the TLP from the PCIe link e A locked memory read MEMRDLK on native Endpoint e A locked completio
61. Arria V Avalon MM Interface for PCle Solutions User Guide Last updated for Altera Complete Design Suite 14 1 x Subscribe UG 01105_avmm GJ Send Feedback 2014 12 15 101 Innovation Drive E San Jose CA 95134 N OTS PYA www altera com Datasheet 1 2014 12 15 UG 01105_avmm ZA Subscribe Send Feedback Avalon MM Interface for PCle Datasheet Altera Arria V FPGAs include a configurable hardened protocol stack for PCI Express that is compliant with PCI Express Base Specification 2 1 or 3 0 The Hard IP for PCI Express PCIe IP core using the Avalon Memory Mapped Avalon MM interface removes some of the complexities associated with the PCIe protocol For example it handles all of the Transaction Layer Protocol TLP encoding and decoding Consequently you can complete your design more quickly The Avalon MM interface is implemented as a bridge in FPGA soft logic It is available in Qsys The following figure shows the high level modules and connecting interfaces for this variant Figure 1 1 Arria V PCle Variant with Avalon MM Interface Serial Data Avalon MM PIPE Transmission Interface PCle Hard IP Interface PHYIP Core jq __ Block lt _ rle y PCS PMA a Table 1 1 PCI Express Data Throughput The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1 2 4 and 8 lanes The protocol specifies 2 5 giga transfers per second for Gen1 a
62. Avalon MM CRA Slave Interface Signals Signal Name Directio Description n crarrg Output Interrupt request A port request for an Avalon MM interrupt CrekeacMeta O12130 Output Read data lines CraWaitReguest o Output Wait request to hold off more requests Cranddress_i 12 0 Input An address space of 16 384 bytes is allocated for the control registers Avalon MM slave addresses provide address resolution down to the width of the slave data bus Because all addresses are byte addresses this address logically goes down to bit 2 Bits 1 and 0 are 0 CraByteEnable_i 3 0 Input Byte enable CraChipSelect i Input Chip select signal to this slave CraRead_i Input Read enable CraWrite_i Input Write request CraWriteData_i 31 0 Input Write data RX Avalon MM Master Signals This Avalon MM master port propagates PCI Express requests to the Qsys interconnect fabric For the full feature IP core it propagates requests as bursting reads or writes A separate Avalon MM master port corresponds to each BAR Table 4 2 Avalon MM RX Master Interface Signals Signals that include Bar number 0 also exist for BARI BARS5 when additional BARs are enabled hE eee Output Asserted by the core to request a write to an Avalon MM slave RemAddressa i oN 01 Output The address of the Avalon MM slave being accessed Ran prelate sero swede Output RX data being written to slave lt w gt
63. CI Express GJ Send Feedback UG 01105_avmm 2014 12 15 Programming a Device 2 7 Files Generated for Altera IP Cores Figure 2 3 IP Core Generated Files The Quartus II software generates the following output for your IP core lt Project Directory gt lt your_ip gt qip or qsys System or IP integration file re oe your_ip gt sopcinfo Software tool chain integration file lt your_ip gt IP core variation files f lt your_ip gt _bb v Verilog HDL black box EDA synthesis file gt lt your_ip gt _inst v or vhd Sample instantiation template lt your_ip gt _generation rpt IP generation report lt your_ip gt bsf Block symbol schematic file lt your_ip gt ppf XML 1 0 pin information file lt your_ip gt spd Combines individual simulation startup scripts 1 lt your_ip gt _syn v or vhd Timing amp resource estimation netlist 1 LAL AL ALALS lt your_ip gt html Contains memory map simulation IP simulation files f lt your_ip gt sip NativeLink simulation integration file f lt your_ip gt v hd vo vho HDL or IPFS models lt simulator vendor gt Simulator setup scripts f lt simulator_setup_scripts gt synthesis IP synthesis files P lt your_ip gt qip Lists files for synthesis f lt your_ip gt debuginfo Lists
64. CI Express to Avalon MM bridge supports both 32 and 64 bit addresses If you select 64 bit addressing the bridge does not perform address translation When you specify 32 bit addresses the Avalon MM address of a received request on the TX Avalon MM slave port is translated to the PCI Express address before the request packet is sent to the Transaction Layer You can specify up to 512 address pages and sizes ranging from 4 KByte to 4 GBytes when you customize your Avalon MM Arria V Hard IP for PCI Express as described in Avalon to PCIe Address Translation Settings This address translation process proceeds by replacing the MSB of the Avalon MM address with the value from a specific translation table entry the LSB remains unchanged The number of MSBs to be replaced is calculated based on the total address space of the upstream PCI Express devices that the Avalon MM Hard IP for PCI Express can access The number of MSB bits is defined by the difference between the maximum number of bits required to represent the address space supported by the upstream PCI Express device minus the number of bits required to represent the Size of address pages which are the LSB pass through bits N The Size of address pages N is applied to all entries in the translation table Each of the 512 possible entries corresponds to the base address of a PCI Express memory segment of a specific size The segment size of each entry must be identical The total size of all the me
65. Completer Only Single DWord 64 160 0 230 Note Soft calibration of the transceiver module requires additional logic The amount of logic required Datasheet depends on the configuration Related Information Fitter Resources Reports Recommended Speed Grades Table 1 6 Arria V Recommended Speed Grades for Link Widths and Application Layer Clock Frequencies Altera recommends setting the Quartus II Analysis amp Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz For information about optimizing synthesis refer to Setting Up and Running Analysis and Synthesis in Quartus II Help For more information about how to effect the Optimization Technique settings refer to Area and Timing Optimization in volume 2 of the Quartus II Handbook Link Rate Link Width Interface Application Clock Recommended Speed Grades Width Frequency MHz 64 bits 62 5 125 x2 64 bits 125 4 5 6 Genl x4 64 bits 125 4 5 6 x8 128 bits 125 4 5 6 This is a power saving mode of operation Altera Corporation G Send Feedback UG 01105_avmm 2014 12 15 Link Rate Link Width Interface Application Clock Recommended Speed Grades Width Frequency MHz Steps in Creating a Design for PCI Express 64 bits Gen2 x2 64 bits 125 A 5 128 bits Related Information e Area and Timing Optimization e Altera Software Installation and L
66. ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm A 2 Transaction Layer Packet TLP Header Formats 2014 12 15 Figure A 3 Memory
67. GACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 x UG 01105_avmm 7 2 Enabling MSI or Legacy Interrupts 2014 12 15 Figure 7 1 Avalon MM Interrupt Propagation to the PCI Express Link Interrupt Disable Configuration Space Command Register 10 Avalon MM to PCI Express Interrupt Status and Interrupt Enable Register Bits A2P_MAILBOX_INT7 enable A2P_MB_IRQ7 request A2P_MAILBOX_INT6 enable A2P_MB_IRQ6 request A2P_MAILBOX_INT5 enable A2P_MB_IRQS5 request A2P_MAILBOX_INT4 enable
68. I MSI X support under the Avalon MM System Settings banner in the parameter editor MsiIntfc_o 81 0 Output This bus provides the following MSI address data and enabled signals MsiIntf_o 81 Master enable MsilIntf_o 80 MSI enable MsiIntf_o 79 64 MSI data MsiIntf_o 63 0 MSI address Interfaces and Signal Descriptions QJ Send Feedback Altera Corporation UG 01105 4 14 Interrupts for Endpoints when Multiple MSI MSI X Support Is Enabled 3014 151E D Sigal O Direction Description O O Meitomtrol_ ol1s 0 Output Provides for system software control of MSI as defined in Section 6 8 1 3 Message Control for MSI in the PCI Local Bus Specifica tion Rev 3 0 The following fields are defined e MsiControl_o 15 9 Reserved e MsiControl_o 8 Per vector masking capable e MsiControl_o 7 64 bit address capable e MsiControl_o 6 4 Multiple Message Enable e MsiControl_o 3 1 MSI Message Capable e MsiControl_o 0 MSI Enable MsixInt re olta 0 Output Provides for system software control of MSI X as defined in Section 6 8 2 3 Message Control for MSI X in the PCI Local Bus Specification Rev 3 0 The following fields are defined e MsixIntfc_o 15 Enable 14 e MsixIntfc_o Mask e MsixIntfc_o 13 11 Reserved e MsixIntfc_o 10 0 Table size IntxReq_i Input When asserted the Endpoint is requesting attention from the interrupt service routine u
69. I Express Base Specification 2 1 or 3 0 Clock Domains Figure 6 5 Clock Domains and Clock Generation for the Application Layer refclk 100 MHz or 125 MHz The following illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the IP core The Altera provided example design connects coreclkout_hip to the pld_clk However this connection is not mandatory Hard IP for PCI Express pld_core_ready T serdes_pll_locked ransceiver re pld_clk 62 5 125 A or 250 MHz coreclkout_hip 250 or 500 MHz TX PLL pclk gt As this figure indicates the IP core includes the following clock domains The transceiver derives pc1k from the 100 MHz refc1k signal that you must provide to the device Reset and Clocks Altera Corporation Send Feedback UG 01105_avmm 6 6 coreclkout_hip 2014 12 15 The PCI Express Base Specification requires that the refc1k signal frequency be 100 MHz 300 PPM The transitions between Gen1 and Gen2 should be glitchless pc1k can be turned off for most of the 1 ms timeout assigned for the PHY to change the clock rate however pc1k should be stable before the 1 ms timeout expires Table 6 1 pclk Clock Frequency Genl 250 MHz Gen2 500 MHz The CDC module implements the asynchronous clock domain crossing between the PHY MAC pc1k domain and the Data Link Layer corec1k domain The transceiver pc1k clock is connected direct
70. I Express Link RP FP User Application Logic User Application Logic Figure 1 3 PCI Express Application Using Configuration via Protocol The Arria V design below includes the following components e A Root Port that connects directly to a second FPGA that includes an Endpoint e Two Endpoints that connect to a PCIe switch e A host CPU that implements CvP using the PCI Express link connects through the switch For more information about configuration over a PCI Express link below Altera Corporation Datasheet GJ Send Feedback UG 01105_avmm 2014 12 15 PCle Hard IP User Application Logic RP PCle Hard IP PCle Link User Application Logic Related Information Altera FPGA with Hard IP for PCI Express Eat Hard IP Altera FPGA with Hard IP for PCI Express PCle Link PCle Link Configuration via Protocol CvP using the PCI Express Link Altera FPGA with Hard IP for PCI Express Example Designs 1 7 User Application Logic Config Control Active Serial or Active Quad Device Configuration Download cable Configuration via Protocol CvP Implementation in Altera FPGAs User Guide Example Designs Datasheet The following example designs are available for the Avalon MM Arria V Hard IP for PCI Express IP Core You can download them from the lt install_dir gt p altera altera_pcie a
71. LTSSM Check PIPE Use PCle Soft Reset Ee aF to Status Interface Analyzer Ee aF Enumeration Link Training The Physical Layer automatically performs link training and initialization without software intervention This is a well defined process to configure and initialize the device s Physical Layer and link so that PCIe 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm 13 2 Setting Up Simulation
72. MSI uses the Transaction Layer s request acknowledge handshaking protocol to implement interrupts The MSI Capability structure is stored in the Configu ration Space and is programmable using Configuration Space accesses e MSI X The Transaction Layer generates MSI X messages which are single dword memory writes In contrast to the MSI capability structure which contains all of the control and status information for the interrupt vectors the MSI X Capability structure points to an MSI X table structure and MSI X PBA structure which are stored in memory Related Information Interrupts for Endpoints when Multiple MSI MSI X Support Is Enabled on page 4 13 PIPE The PIPE interface implements the Intel designed PIPE interface specification You can use this parallel interface to speed simulation however you cannot use the PIPE interface in actual hardware e The Genl Gen2 and Gen3 simulation models support PIPE and serial simulation e For Gen3 the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization However Gen3 variants can perform Phase 2 and Phase 3 equalization if instructed by a third party BFM IP Core Architecture Altera Corporation CJ Send Feedback 9 4 Data Link Layer UG 01105_avmm 2014 12 15 Related Information PIPE Interface Signals Data Link Layer The Data Link Layer is located between the Transaction Layer and the Physical Layer It maintains packet integrity and communicates by DLL packet transmission
73. NTD_RECEIVED RWIC The Root Port has received INTD from the Endpoint 2 ENC RECEIVED RWI1C The Root Port has received INTC from the Endpoint 1 INTE SECM VED RWI1C The Root Port has received INTB from the Endpoint 0 INIA RECEIVED RWIC _ The Root Port has received INTA from the Endpoint Table 5 25 INT X Interrupt Enable Register for Root Ports 0x3070 Access Description Mode 31 5 Reserved 4 DIR CPT RECT UVRD RW When set to 1 b1 enables the assertion of CraIrg_o when the Root Port Interrupt Status register RPRX_CPL_ RECEIVED bit indicates it has received a Completion for a Non Posted request from the TLP Direct channel 3 INTD_RECETVED ENA RW _ When set to 1 b1 enables the assertion of CraIrg_o when the Root Port Interrupt Status register INTD_ RECEIVED bit indicates it has received INTD Registers Altera Corporation G Send Feedback 5 30 Root Port TLP Data Registers Access Mode UG 01105_avmm 2014 12 15 Description 2 INTC_RECEIVED_ENA RW When set to 1 b1 enables the assertion of CraIrg_o when the Root Port Interrupt Status register INTC_ RECEIVED bit indicates it has received INTC 1 INTB_RECEIVED_ENA RW When set to 1 b1 enables the assertion of CraIrg_o when the Root Port Interrupt Status register INTB_ RECEIVED bit indi
74. Output When asserted indicates that the Hard IP Transaction Layer is using the pld_c1k as its clock and is ready for operation with the Application Layer For reliable operation hold the Application Layer in reset until p1d_clk_inuse is asserted pment oust Output Power management turn off status register Root Port This signal is asserted for 1 clock cycle when the Root Port receives the pme_turn_off acknowledge message Endpoint This signal is asserted for 1 cycle when the Endpoint receives the PME_turn_off message from the Root Port Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Hard IP Status Extension 4 17 O Sigal O Direction Description O O rx_st_bar 7 0 Output The decoded BAR bits for the TLP Valid for MRa Mwr IowR and toRD TLPs Ignored for the completion or message TLPs Valid during the cycle in which rx_st_sop is asserted The following encodings are defined for Endpoints e Bit0 BARO e Bitl BAR1 e Bit2 Bar 2 e Bit3 Bar 3 e Bit4 Bar 4 e Bit5 Bar5 e Bit 6 Reserved e Bit7 Reserved The following encodings are defined for Root Ports e Bit0 BARO e Bitl BAR1 e Bit 2 Primary Bus number e Bit 3 Secondary Bus number e Bit 4 Secondary Bus number to Subordinate Bus number window e Bit 5 1 O window e Bit 6 Non Prefetchable window e Bit 7 Prefetchable window Ex St Cacal lt r lt 0 Output R
75. PCI Express to Avalon MM Mailbox 7 The Avalon MM to PCI Express Mailbox registers are read at the addresses shown in the following table The PCI Express Root Complex should use these addresses to read the mailbox information after being signaled by the corresponding bits in the Avalon MM to PCI Express Interrupt Status register Table 5 17 Avalon MM to PCI Express Mailbox Registers 0x0900 0x091F 0x0900 A2P_MATLBOXO a a 0 Avalon MM to PCI Express Mailbox 0 Registers G Send Feedback Altera Corporation 18 Avalon MM to PCl Express Address Translation Table UG 01105_avmm 2014 12 15 Coe 0x0904 A2P_MAILBOX1 Avalon MM to PCI Express Mailbox 1 0x0908 A2P_MAILBOX2 RO Avalon MM to PCI Express Mailbox 2 0x090C a2P_MAILBOX3 RO Avalon MM to PCI Express Mailbox 3 0x0910 A2P_MAILBOX4 RO Avalon MM to PCI Express Mailbox 4 0x0914 A2P_MAILBOX5 RO Avalon MM to PCI Express Mailbox 5 0x0918 A2P_MATLBOX6 RO Avalon MM to PCI Express Mailbox 6 0x091C aA2P_MAILBOX7 RO Avalon MM to PCI Express Mailbox 7 Avalon MM to PCl Express Address Translation Table The Avalon MM to PCI Express address translation table is writable using the CRA slave port Each entry in the PCI Express address translation table is 8 bytes wide regardless of the value in the current PCI Express address width parameter Therefore register addresses are always the same width regardless of PCI Express addr
76. PCle Address Space For designs that include multiple BARs you may need to modify the base address assignments auto assigned by Qsys in order to minimize the address space that the BARs consume For example consider a Qsys system with the following components Offchip_Data_Mem DDR3 SDRAM Controller with UniPHY controlling 256 MBytes of memory Qsys auto assigned a base address of 0x00000000 Quick_Data_Mem On Chip Memory RAM or ROM of 4 KBytes Qsys auto assigned a base address of 0x10000000 Instruction_Mem On Chip Memory RAM or ROM of 64 KBytes Qsys auto assigned a base address of 0x10020000 PCIe Avalon MM Arria V Hard IP for PCI Express e Cra Avalon MM Slave auto assigned base address of 0x10004000 e Rxm_BARO connects to Offchip_Data_Mem DD R3 ayl e Rxm_BAR2 connects to Quick_Data_Mem s1 e Rxm_BAR4 connects to PCIe Cra Avalon MM Slave Nios2 Nios II Processor e data_master connects to PCIe Cra Offchip_Data_Mem DDR3 avl Quick_Data_Mem s1 Instruction_Mem s1 Nios2 jtag_debug_module e instruction_master connects to Instruction_Mem s1 IP Core Architecture Altera Corporation CJ Send Feedback 9 16 Minimizing BAR Sizes and the PCle Address Space Figure 9 6 Qsys System for PCI Express with Poor Address Space Utilization UG 01105_avmm 2014 12 15 The following figure uses a filter to hide the Conduit interfaces that are not relevant in this discussion System Contents Address Map Cloc
77. Registers for Endpoints on page 5 19 Interrupts for Endpoints Using the Avalon MM Interface with Multiple MSI MSI X Support If you select Enable multiple MSI MSI X support under the Avalon MM System Settings banner in the parameter editor the Hard IP for PCI Express exports the MSI MSI X and INTx interfaces to the Application Layer The Application Layer must include a Custom Interrupt Handler to send interrupts to the Root Port You must design this Custom Interrupt Handler The following figure provides an overview of the logic for the Custom Interrupt Handler The Custom Interrupt Handler should include hardware to perform the following tasks e An MSI MXI X IRQ Avalon MM Master port to drive MSI or MSI X interrupts as memory writes to the PCIe Avalon MM bridge e A legacy interrupt signal IntxReq_i to drive legacy interrupts from the MSI MSI X IRQ module to the Hard IP for PCI Express e An MSI MSI X Avalon MM Slave port to receive interrupt control and status from the PCIe Root Port e An MSI X table to store the MSI X table entries The PCIe Root Port sets up this table Interrupts for Endpoints Altera Corporation CJ Send Feedback UG 01105_avmm 7 4 Interrupts for Endpoints Using the Avalon MM Interface with Multiple MSI MSI X 2014 12 15 Support Figure 7 2 Block Diagram for Custom Interrupt Handler Custom Interrupt Handler Qsys PCle Avalon MM Interconnect Bridge MSI X Table Entries PCle Root Port MSI X PBA
78. Send Feedback Altera Corporation 16 Avalon MM to PCI Express Interrupt Enable Registers UG 01105_avmm 2014 12 15 oe 15 0 AVL_IRO_ASSERTE S40 Current value of the Avalon MM interrupt IRQ input ports to the Avalon MM RX master port e 0 Avalon MM IRQ is not being signaled e 1 Avalon MM IRQ is being signaled A Qsys generated IP Compiler for PCI Express has as many as 16 distinct IRQ input ports Each AVL_IRQ_ASSERTED bit reflects the value on the corresponding IRQ input port Avalon MM to PCI Express Interrupt Enable Registers A PCI Express interrupt can be asserted for any of the conditions registered in the Avalon MM to PCI Express Interrupt Status register by setting the corresponding bits in the Avalon MM to PCI Express Interrupt Enable register Either MSI or legacy interrupts can be generated as explained in the section Enabling MSI or Legacy Interrupts Table 5 14 Avalon MM to PCI Express Interrupt Enable Register 0x0050 SS EE 31 24 Reserved Dic RW Enables generation of PCI Express interrupts when a specified mailbox is written to by an external Avalon MM master 4 0 AVE_tRO 15 0 RW Enables generation of PCI Express interrupts when a specified Avalon MM interrupt signal is asserted Your Qsys system may have as many as 16 individual input interrupt signals Table 5 15 Avalon MM Interrupt Vector Register 0x0060
79. Slave Port Optional 64 Bit Avalon MM RX BAR Master Port 64 or 128 Bit Avalon MM TX Slave Port Clocks E Reset Hard IP Status 64 or 128 Bit Avalon MM Interface to Application Layer Cralrq_o CraReadData_o 31 0 CraWaitRequest_o CraAddress_i 13 0 CraByteEnable_i 3 0 CraChipSelect_i CraRead_i CraWrite_i CraWriteData_i 31 0 RxmWrite_ lt n gt o RxmAddress_ lt n gt 31 0 RxmWriteData_ lt n gt 0 lt w gt 1 0 RxmByteEnable_ lt n gt 0o lt w gt 1 8 0 RxmBurstCount_ lt n gt of6 or 5 0 RxmWaitRequest_ lt n gt o0 RxmRead_ lt n gt 0 RxmReadData_i lt n gt lt w RxmReadDataValid_i lt n gt Rxmlrql lt m gt 0 lt m gt lt 16 TxsChipSelect_i TxsRead_i TxsWrite_i TxsWriteData_i lt w gt 1 0 TxsBurstCount_i 6 or 5 0 TxsAddress_i lt w gt 1 0 TxsByteEnable_i lt w gt 1 8 0 TxsReadDataValid_o TxsReadData_o lt w gt 1 0 TxsWaitRequest_o refclk coreclkout npor nreset_status pin_perstn derr_cor_ext_rcv derr_ext_rpl derr_rpl dlup dlup_exit ev128ns evlus hotrst_exit int_status 3 0 ko_cpl_spc_data 11 0 ko_cpl_spc_header 7 0 12_ext lane_act 3 0 Itssmstate 4 0 Msilntfc_o 81 0 MsiControl_o 15 0 MsixIntfc_o 15 0 IntxReq_i IntxAck_o reconfig_fromxcvr lt n gt 69 1 0 reconfig_toxcvr lt n gt 45 1 0 busy_xcvr comig reconfig_clk_locke pld_clk_inuse pme_to_sr rx_st_bar 7 0 rx_st_data 127 0 rx_st_eop rx_st_err rx_st_sop rx_st_valid serr_out
80. State Machine This state machine is synchronized with the Physical Layer s LTSSM state machine and is also connected to the Configuration Space Registers It initializes the link and flow control credits and reports status to the Configuration Space e Power Management This function handles the handshake to enter low power mode Such a transition is based on register values in the Configuration Space and received Power Management PM DLLPs e Data Link Layer Packet Generator and Checker This block is associated with the DLLP s 16 bit CRC and maintains the integrity of transmitted packets e Transaction Layer Packet Generator This block generates transmit packets generating a sequence number and a 32 bit CRC LCRC The packets are also sent to the retry buffer for internal storage In retry mode the TLP generator receives the packets from the retry buffer and generates the CRC for the transmit packet e Retry Buffer The retry buffer stores TLPs and retransmits all unacknowledged packets in the case of NAK DLLP reception In case of ACK DLLP reception the retry buffer discards all acknowledged packets IP Core Architecture Altera Corporation CJ Send Feedback UG 01105_avmm 9 6 Physical Layer 2014 12 15 ACK NAK Packets The ACK NAK block handles ACK NAK DLLPs and generates the sequence number of transmitted packets Transaction Layer Packet Checker This block checks the integrity of the received TLP and generates a reque
81. To improve PCI Express throughput Altera recommends using an Avalon MM burst master without any byte enable restrictions Avalon MM to PCl Express Upstream Read Requests The PCI Express Avalon MM bridge converts read requests from the system interconnect fabric to PCI Express read requests with 32 bit or 64 bit addresses based on the address translation configuration the request address and the maximum read size The Avalon MM TX slave interface of a PCI Express Avalon MM bridge can receive read requests with burst sizes of up to 512 bytes sent to any address However the bridge limits read requests sent to the PCI Express link to a maximum of 256 bytes Additionally the bridge must prevent each PCI Express read request packet from crossing a 4 KByte address boundary Therefore the bridge may split an Avalon MM read request into multiple PCI Express read packets based on the address and the size of the read request Avalon MM bridge supports up to eight outstanding reads from Avalon MM interface Once the bridge has eight outstanding read requests the txs_waitrequest signal is asserted to block additional read requests When a read request completes the Avalon MM bridge can accept another request For Avalon MM read requests with a burst count greater than one all byte enables must be asserted There are no restrictions on byte enables for Avalon MM read requests with a burst count of one An invalid Avalon MM request can adversely affect sy
82. Transaction Layer error 1b 1 RWS 6 Reserved 1b 0 RO 5 Mask for configuration errors detected in CvP mode 1b 0 RWS 4 Mask for data parity errors detected during TX Data Link LCRC 1b 1 RWS generation 3 Mask for data parity errors detected on the RX to Configuration 1b 1 RWS Space Bus interface 2 Mask for data parity error detected at the input to the RX Buffer 1b 1 RWS 1 Mask for the retry buffer uncorrectable ECC error 1b 1 RWS 0 Mask for the RX buffer uncorrectable ECC error 1b 1 RWS Uncorrectable Internal Error Status Register Table 5 28 Uncorrectable Internal Error Status Register This register reports the status of the internally checked errors that are uncorrectable When specific errors are enabled by the Uncorrectable Internal Error Mask register they are handled as Uncorrectable Internal Errors as defined in the PCI Express Base Specification 3 0 This register is for debug only It should only be used to observe behavior not to drive custom logic The access code RWICS represents Read Write 1 to Clear Sticky Register Description Reset Access Value 31 12 Reserved 11 When set indicates an RX buffer overflow condition in a RWICS posted request or Completion Registers Altera Corporation CJ Send Feedback Correctable Internal Error Mask Register UG 01105_avmm 2014 12 15 Register Description Reset Access WELT
83. VR_VCCR_VCCT_VOLTAGE to 1 0 V for the pin specified set_instance_assignment name XCVR_VCCR_VCCT_VOLTAGE 1_0V to pin Related Information e Arria V GT GX ST and SX Device Family Pin Connection Guidelines e Arria V Device Datasheet Making Pin Assignments Before running Quartus II compilation use the Pin Planner to assign I O standards to the pins of the device Complete the following steps to bring up the Pin Planner and assign the 1 5 V pseudo current mode logic PCML I O standard to the serial data input and output pins 1 On the Quartus II Assignments menu select Pin Planner The Pin Planner appears 2 In the Node Name column locate the PCIe serial data pins 3 In the I O Standard column double click the right hand corner of the box to bring up a list of available I O standards 4 Select 1 5 V PCML I O standard Note The IP core automatically assigns other required PMA analog settings including 100 ohm internal termination Recommended Reset Sequence to Avoid Link Training Issues 1 Wait until the FPGA is configured as indicated by the assertion of conf 1G_DONE from the FPGA block controller 2 Deassert the mgmt_rst_reset input to the Transceiver Reconfiguration Controller IP Core Wait for tx_cal_busy and rx_cal_busy SERDES outputs to be deasserted 4 Deassert pin_perstn to take the Hard IP for PCle out of reset For plug in cards the minimum assertion time for pin_perstn is 100 ms Embedded
84. an use either of the following two methods to eliminate this issue e You can perform a soft reset of the system to retain the FPGA programming while forcing the OS BIOS to repeat its enumeration e You can use CvP to program the device Altera Corporation Debugging GJ Send Feedback Transaction Layer Packet TLP Header Formats 2014 12 15 UG 01105_avmm amp Subscribe os Send Feedback The following figures show the header format for TLPs without a data payload Figure A 1 Memory Read Request 32 Bit Addressing Memory Read Request 32 Bit Addressing 0 1 2 3 7 6 5 4 3 2 1 40 7 6 5 4 B Pf O 7 6 5 14 3 2 1 0 7 6 5 4 3 2 1 10 Byte 0 0 0 0 0 00 0 0 0 TC 0 0 00 TD EP Attr 0 0 Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Figure A 2 Memory Read Request Locked 32 Bit Addressing Memory Read Request Locked 32 Bit Addressing 0 1 2 3 716 5 4 3 2 11 0 7 76 5 74 3 2 1 0 7 6 5 473 2 1 0 7 6 5 4 73 1 10 Byte 0 0 0 0 0 0 0 0 1 01TC 0 0 0 0 TD EP Attr O 0 Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE
85. anagement Error Signaling Unlock and Set Power Slot Limit must be transmitted across the default traffic class The Hard IP block deletes the malformed TLP it is not presented to the Application Layer Note 1 Considered optional by the PCI Express Base Specification Revision Error Reporting and Data Poisoning How the Endpoint handles a particular error depends on the configuration registers of the device Refer to the PCI Express Base Specification 3 0 for a description of the device signaling and logging for an Endpoint The Hard IP block implements data poisoning a mechanism for indicating that the data associated with a transaction is corrupted Poisoned TLPs have the error poisoned bit of the header set to 1 and observe the following rules e Received poisoned TLPs are sent to the Application Layer and status bits are automatically updated in the Configuration Space e Received poisoned Configuration Write TLPs are not written in the Configuration Space e The Configuration Space never generates a poisoned TLP the error poisoned bit of the header is always set to 0 Altera Corporation Error Handling CJ Send Feedback UG 01105_avmm 2014 12 15 Uncorrectable and Correctable Error Status Bits 8 7 Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register Table 8 5 Parity Error Conditions a ocos O O Detected parity error status register bit 15 Se
86. anes e 4b1000 8 lanes ltssmstate 4 0 Altera Corporation Output LTSSM state The LTSSM state machine encoding defines the following states e 00000 Detect Quiet e 00001 Detect Active e 00010 Polling Active e 00011 Polling Compliance e 00100 Polling Configuration e 00101 Polling Speed Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Interrupts for Endpoints when Multiple MSI MSI X Support Is Enabled 4 13 O Signal O Direction O Deseripton O O 00110 00111 01000 01001 01010 01011 01100 01101 01110 O1111 10000 10001 10010 10011 10100 10101 11001 11010 11011 11100 11101 11110 config Linkwidthstart Config Linkaccept Config Lanenumaccept Config Lanenumwait Config Complete Config Idle Recovery Rcvlock Recovery Rcvconfig Recovery Idle LO Disable Loopback Entry Loopback Active Loopback Exit Hot Reset LOs L2 transmit Wake Speed Recovery Recovery Equalization Phase 0 Recovery Equalization Phase 1 Recovery Equalization Phase 2 recovery Equalization Phase 3 Related Information PCI Express Card Electromechanical Specification 2 0 Interrupts for Endpoints when Multiple MSI MSI X Support Is Enabled Table 4 7 Exported Interrupt Signals for Endpoints when Multiple MSI MSI X Support is Enabled The following table describes the IP core s exported interrupt signals when you turn on Enable multiple MS
87. arameters System Inspector HDL Example f Generation Offchip_Data_Mem avl PCle Rxm_BARO v PCle Rxm_BAR2 PCle Rxm_BAR4 Nios2 data_master Nios2 instruction_master Ox0000_0000 OxOfff_ffff 0x0000_0000 OxOFFT_TTtF PCle Cra 0x1000_4000 0x1000_7fff Ox1000_4000 0x1000_7fff Quick_Data_Mem s1 0x1000_0000 0x1000_Of ff 0x1000_0000 0x1000_Of ff Instruction_Mem sl Nios2 jtag_debug_module 0x1002_0000 0x1002_ffff 0x1002_0000 0x1002_ffff E 0x1000_1800 0x1000_1fff 0x1000_1800 _0x1000_1f FF The auto assigned base addresses result in the following three large BARs e BARO is 28 bits This is the optimal size because it addresses the Offchip_Data_Mem which requires 28 address bits e BAR2 is 29 bits BAR2 addresses the Quick_Data_Mem which is 4 KBytes It should only require 12 address bits however it is consuming 512 MBytes of address space e BAR4 is also 29 bits BAR4 address PCIe Cra is 16 KBytes It should only require 14 address bits however it is also consuming 512 MBytes of address space Altera Corporation IP Core Architecture G send Feedback UG 01105 2014 12 1 a Avalon MM to PCI Express Address Translation Algorithm for 32 Bit Addressing 9 17 This design is consuming 1 25 GB of PCIe address space when only 276 MBytes are actually required The solution is to edit the address map to
88. block diagram of the reset logic Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Table 4 5 Reset Signals Reset Signals 4 9 O Sigal a O Deseripton O npor Input Active low reset signal In the Altera hardware example designs npor is the OR of pin_perst and local_rstn coming from the software Application Layer If you do not drive a soft reset signal from the Application Layer this signal must be derived from pin_perst You cannot disable this signal Resets the entire IP Core and transceiver Asynchronous In systems that use the hard reset controller this signal is edge not level sensitive consequently you cannot use a low value on this signal to hold custom logic in reset For more information about the hard and soft reset controllers refer to the Reset and Clocks chapter nreset_status pin_perst Interfaces and Signal Descriptions G Send Feedback Output Input Active low reset signal It is derived from npor or pin_perstn Active low reset from the PCIe reset pin of the device pin_perst resets the datapath and control registers This signal is required for Configuration via Protocol CvP For more information about CvP refer to Configuration via Protocol CvP Arria V have 1 or 2 instances of the Hard IP for PCI Express Each instance has its own pin_perst signal You must connect the pin_perst of each Hard IP instance to the correspond
89. cates it has received INTB 0 INTA_RECEIVED_ENA RW When set to 1 b1 enables the assertion of CraIrg_o when the Root Port Interrupt Status register INTA_ RECEIVED bit indicates it has received INTA Root Port TLP Data Registers The TLP data registers provide a mechanism for the Application Layer to specify data that the Root Port uses to construct Configuration TLPs I O TLPs and single dword Memory Reads and Write requests The Root Port then drives the TLPs on the TLP Direct Channel to access the Configuration Space I O space or Endpoint memory Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Figure 5 12 Root Port TLP Data Registers Root Port TLP Data Registers 5 31 Avalon MM Bridge Root Port TLP Data Registers RP TX RX_TX_CNTL gt CTRL gt X CTRL RP_TX_RegO 32 gt a 64 RX_TX_Reg1 TLP Direct Channel 32 RP_TX_FIFO to Hard IP for PCle IRQ Control Avalon MM Register N Master Access 32 Slave RP_RXCPL_ lt 1 REGO Ke l RX 64 CTRL RP_RXCPL_FIFO L IRP_RXCPL_ g Z REG 32 gt RPCPL RP_RXCPL_ STATUS CTRL Note The high performance TLPs implemented by Avalon MM ports in the Avalon MM Bridge
90. cation or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 Iso 9001 2008 Registered JA DTE RYA gt Pett UG 01105_avmm 5 2 Correspondence between Configuration Space Registers and the PCle Specification 2014 12 15 Byte Address Hard IP Configuration Space Register Corresponding Section in PCle Specification 0x170 0x17C Reserved N A 0x180 0x1FC Virtual channel arbitration table Reserved VC Arbitration Table 0x200 0x23C Port VCO arbitration table Reserved Port Arbitration Table 0x240 0x27C Port VC1 arbitration table Reserved Port Arbitration Table 0x280 0x2BC Port VC2 arbitration table Reserved Port Arbitration Table 0x2C0 0x2FC Port VC3 arbitration table Reserved Port Arbitration Table 0x300 0x33C Port VC4 arbitration table Reserved Port Arbitration Table 0x340 0x37C Port VC5 arbitration table Reserved Port Arbitration Table 0x380 0x3BC Port VC6 arbitration table Reserved Port Arbitration Table 0x3C0 0x3FC Port VC7 arbitration table Reserved Port Arbitration Table 0x400 0x7FC Reserved PCle spec corresponding section name 0x800 0x834 Advanced Error Reporting AER optional Adva
91. ce 1D register This register is only valid in the Type 0 Endpoint Configu ration Space Address offset 0x000 Parameter Settings Send Feedback Altera Corporation Device Capabilities UG 01105_avmm 2014 12 15 Revision ID 8 bits 0x00000001 Sets the read only value of the Revision ID register Address offset 0x008 Class code 24 bits 0x00000000 Sets the read only value of the class Code register Address offset 0x008 Subsystem 16 bits 0x00000000 Sets the read only value of the Subsystem Vendor ID Vendor ID register in the PCI Type 0 Configuration Space This parameter cannot be set to OXFFFF per the PCI Express Base Specification This value is assigned by PCI SIG to the device manufacturer This register is only valid in the Type 0 Endpoint Configuration Space Address offset 0x02C Subsystem 16 bits 0x00000000 Sets the read only value of the subsystem Device ID Device ID register in the PCI Type 0 Configuration Space Address offset 0x02C Related Information PCI Express Base Specification 2 1 or 3 0 Device Capabilities Table 3 4 Capabilities Registers Maximum 128 bytes 128 bytes Specifies the maximum payload size supported This payload size 256 bytes parameter sets the read only value of the max payload y size supported field of the Device Capabilities register 0x084 2 0 Address 0x084 Completion ABCD ABCD Indicates device function support for the opt
92. ce or board type ID to specify to CvP the correct sof Variable CvP Registers Altera Corporation Registers GJ Send Feedback UG 01105_avmm 2014 12 15 CvP Registers 5 11 Table 5 7 CvP Status The CvP Status register allows software to monitor the CvP status signals Register Description Reset Value 31 26 Reserved 0x00 RO 25 PLD_CORE_READY From FPGA fabric This status bit is Variable RO provided for debug 24 PLD_CLK_IN_USE From clock switch module to fabric This Variable RO status bit is provided for debug 23 CVP_CONFIG_DONE Indicates that the FPGA control block has Variable RO completed the device configuration via CvP and there were no errors 22 Reserved Variable RO 21 USERMODE Indicates if the configurable FPGA fabric isin user Variable RO mode 20 cvp_EN Indicates if the FPGA control block has enabled CvP Variable RO mode 19 CVP_CONFIG_ERROR Reflects the value of this signal from the Variable RO FPGA control block checked by software to determine if there was an error during configuration 18 CVP_CONFIG_READY Reflects the value of this signal from the Variable RO FPGA control block checked by software during programming algorithm 17 0 Reserved Variable RO Table 5 8 CvP Mode Control The cvP Mode Control register provides global control of the CvP operation its Register Description Re
93. cks 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback The pin_perst signal from the input pin of the FPGA resets the Hard IP for PCI Express IP Core app_rstn which resets the Application Layer logic is derived from reset_status and pld_clk_inuse which are outputs of the core This reset controller is implemented in hardened logic The figure below provides a simplified view of the logic that implements the reset controller 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
94. click Save The following table lists the testbench and simulation directories Qsys generates Table 2 1 Qsys System Generated Directories Qsys system lt project_dir gt ep_g1x4 Testbench lt project_dir gt ep_g1x4 testbench lt cad_vendor gt Simulation Model lt project_dir gt ep_g1x4 testbench ep_g2x4_tb simulation The design example simulation includes the following components and software The Qsys system A testbench You can view this testbench in Qsys by opening lt project_dir gt ep_g2x4 testbench ep_g1x4_ tb qsys The ModelSim software Note You can also use any other supported third party simulator to simulate your design Complete the following steps to run the Qsys testbench 1 In a terminal window change to the lt project_dir gt ep_g1x4 testbench mentor directory 2 Start the ModelSim simulator 3 Type the following commands in a terminal window a do msim_setup tcl b 1d_debug C run 140000 ns Getting Started with the Avalon MM Arria V Hard IP for PCI Express Altera Corporation J send Feedback UG 01105_avmm 2 4 Running A Gate Level Simulation 2014 12 15 The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window 1 5 Various configuration accesses to the Avalon MM Arria V Hard IP for PCI Express in your system after the link is initialized Setup of the Address Translation Table for request
95. ct to the appropriate channels on the left side of the device and so on Corrected connection for the Transceiver Reconfiguration Controller IP Core reset signal alt_xcvr_reconfig_0 mgmt_ rst_reset Getting Started with the Avalon MM Arria V Hard IP for PCI Express This reset input connects to clk_0 clk_reset Altera Corporation C 4 How to Contact Altera UG 01105_avmm 2014 08 18 Added definition of nreset_status for variants using the Avalon MM interface In Transaction Layer Routing Rules and Programming Model for Avalon MM Root Port added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number Application Layer software must filter out requests for device number greater than 0 Added Recommended Reset Sequence to Avoid Link Training Issues to the Debugging chapter Added limitation for RxmIrq_ lt n gt _i lt m gt 0 when interrupts are received on consecutive cycles Updated timing diagram for t1_cfg_ct1 Removed I O Read Request and I O Write Requests from TLPs supported for Avalon MM interface Added note that the LTSSM interface can be used for SignalTap debugging Added restriction on the use of dynamic transceiver reconfigura tion when CvP is enabled 2014 05 06 Made the following changes Timing models are now final Added instructions for running the Single Dword variant Corrected definition of test_in 4 1 This vector must be set to 4 b0100
96. d into RP_RXCPL registers The Application Layer performs the following sequence to retrieve the TLP 1 Polls the RP_RXCPL_STA TUS SOP to determine when it is set to bl 2 Then RP_RXCPL_STATUS SOP 1 b l reads RP_RXCPL_REGO and RP_RXCPL_REG1 to retrieve dword 0 and dword 1 of the TLP 3 Read the RP_RXCPL_STATUS EOP e IfRP_RXCPL_STATUS EOP 1 b0 read RP_RXCPL_REGO and RP_RXCPL_REG1 to retrieve dword 2 and dword 3 of the TLP then repeat step 3 e IfRP_RXCPL_STATUS EOP l bl read RP_RXCPL_REGO and RP_RXCPL_REG1 to retrieve final dwords of TLP PCI Express to Avalon MM Interrupt Status and Enable Registers for Root Ports The Root Port supports MSI MSI X and legacy INTx interrupts MSI and MSI X interrupts are memory writes from the Endpoint to the Root Port MSI and MSI X requests are forwarded to the interconnect without asserting CraIrq_o Altera Corporation Registers GJ Send Feedback UG 01105_avmm 7 5 29 2014 12 15 PCI Express to Avalon MM Interrupt Status and Enable Registers for Root Ports z Table 5 24 Avalon MM Interrupt Status Registers for Root Ports 0x3060 Access Description Mode 31 5 Reserved 4 AUR CPL RECEIVED RWI1IC Setto 1 b1 when the Root Port has received a Completion TLP for an outstanding Non Posted request from the TLP Direct channel 3 I
97. dback UG 01105_avmm 2014 12 15 Altera Defined VSEC Registers Figure 5 8 VSEC Registers Altera Defined VSEC Registers 5 9 This extended capability structure supports Configuration via Protocol CvP programming and detailed internal error reporting Table 5 2 Altera Defined VSEC Capability Register 0x200 31 20 19 16 15 87 0 0x200 Next Capability Offset Version Altera Defined VSEC Capability Header ee VEC Length sah Altera Defined ey Header 0x208 Altera Marker 0x20 JTAG Silicon ID DWO JTAG Silicon ID 0x210 JTAG Silicon ID DW1 JTAG Silicon ID 0x214 JTAG Silicon ID DW2 JTAG Silicon ID 0x218 JTAG Silicon ID DW3 JTAG Silicon ID 0x21C CvP Status User Device or Board Type ID 0x220 CvP Mode Control 0x224 CvP Data2 Register 0x228 CvP Data Register 0x22C CvP Programming Control Register 0x230 Reserved 0x234 Uncorrectable Internal Error Status Register 0x238 Uncorrectable Internal Error Mask Register 0x23C Correctable Internal Error Status Register 0x240 Correctable Internal Error Mask Register The Altera Defined Vendor Specific Extended Capability This extended capability structure supports Configuration via Protocol CvP programming and detailed internal error reporting Register Description 15 0 PCI Express Extended Capability ID Altera defined value for 0x000B RO VSEC Capability ID 19 16 Version Altera defined value for VSEC version 0x1 RO 3
98. ders for products or services JAN DTE RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm C 2 Revision History for the Avalon MM Interface 2014 08 18 Added figure showing connectivity for the Transceiver Reconfigu ration Controller and Altera PCIe Reconfig Driver IP Cores to the Gettting Started chapter Removed Maximum and High settings from the RX Buffer credit allocation performance for received requests setting These settings are not available for the Avalon MM interface and could lead to data corruption Revised Receiving a Completion TLP under Programming Model for Avalon MM Root Port to cover read and non posted completions 2014 06 30 Altera Corporation 14 0 Added the following features to the Arria V Avalon MM Hard IP for PCI Express Added access to selected Configuration Space registers and link status registers through the optional Control Register Access CRA Avalon MM slave port Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core Added optional hard IP status extension bus which includes signals that are useful for debugging including link training status error and Configuration Space signals For TxsByteEnable_i lt w gt 1 0 added restrictions on the legal patterns of enabled and disabled bytes Clarified the behavior of the txswait request_o signal Made the following changes to the user g
99. eceive data bus Note that the position of the first payload dword depends on whether the TLP address is qword aligned The mapping of message TLPs is the same as the mapping of TLPs with 4 dword headers rx _st_eop Output Indicates that this is the last cycle of the TLP when rx_st_valid is asserted 1k Sie Sue Output Indicates that there is an ECC error in the internal RX buffer Active when ECC is enabled ECC is automatically enabled by the Quartus II assembler ECC corrects single bit errors and detects double bit errors on a per byte basis When an uncorrectable ECC error is detected rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted Altera recommends resetting the Arria V Hard IP for PCI Express when an uncorrectable double bit ECC error is detected Interfaces and Signal Descriptions G Send Feedback Altera Corporation 4 18 Hard IP Status Extension UG 01105_avmm 2014 12 15 O Sigal O Direction Description O O rx_st_sop Output Indicates that this is the first cycle of the TLP when rx_st_valid is asserted x SE valie Output Clocks rx_st_data into the Application Layer Deasserts within 2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send serr_out Output System Error This signal only applies to Root Port designs that report each system error detected assuming the proper
100. econfiguration Controller parameter editor Removed reference to Gen2 x1 62 5 MHz configuration in Application Layer Clock Frequency for All Combination of Link Width Data Rate and Application Layer Interface Widths table This configuration is not supported Added description of TxsWaitRequest signal which is asserted when the Avalon MM bridge has eight outstanding read requests Added sections on making analog QSF and pin assignments Enhanced definition of Device ID and Sub system Vendor ID to say that these registers are only valid in the Type 0 Endpoint Configuration Space Improved figure showing multiple MSI and MSI X support and added reference to example on Altera wiki Removed references to the ATX PLL This PLL is not available for Arria V Updated Power Supply Voltage Requirements table For Cyclone V devices changed speed grade recommendation to use GT devices for both the Gen1 and Gen2 data rate 2014 12 20 Additional Information Send Feedback Made the following changes Added constraints for refc1k when CvP is enabled Corrected location information for nPERSTL Corrected definition of test_in 4 1 In Debugging chapter under changing between soft and hard reset controller changed the file name in which the parameter hip_ hard_reset_hwtclmust be set to 0 to use the soft reset controller Added explanation of channel labeling for serial data The Hard IP on the left side of the device must conne
101. egistered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm 2 2 Running Qsys 2014 12 15 The design example transfers data between an on chip memory buffer located on the Avalon MM side and a PCI Express memory buffer located on the root complex side The data transfer uses the DMA component which is programmed by the PCI Express software application running on the Root Complex processor The example design also includes the Transceiver Reconfiguration Controller which allows you to dynamically reconfigure transceiver settings This component is necessary for high performance transceiver design
102. emory Read Request e Completion Message single dword e Completion with Data e Memory Write Request e Completion for Locked single dword Read without Data Payload size 128 512 bytes 128 or 256 bytes 128 or 256 bytes Number of tags 32 or 64 16 16 supported for non posted requests 62 5 MHz clock Supported Supported Not Supported Multi function Supports up to 8 functions Supports single function Supports single only function only Datasheet CJ Send Feedback Altera Corporation 1 4 Features UG 01105_avmm 2014 12 15 Feature Avalon ST Interface Avalon MM Interface Avalon MM DMA Out of order completions transparent to the Application Layer Not supported Supported Supported Requests that cross 4 KByte address boundary transparent to the Application Layer Not supported Supported Supported Polarity Inversion of PIPE interface signals Supported Supported Supported ECRC forwarding on RX and TX Supported Not supported Not supported Number of MSI requests MSI X 1 2 4 8 or 16 Supported 1 2 4 8 or 16 Supported 1 2 4 8 or 16 Supported Legacy interrupts Supported Supported Supported Expansion ROM Supported Not supported Not supported The purpose of the Arria VAvalon MM Interface for PCIe Solutions User Guide is to explain how to use this IP core and not to explain the PCI Express pro
103. enabling bits are asserted in the Root Control and Device Control registers If enabled serr_out is asserted for a single clock cycle when a system error occurs System errors are described in the PCI Express Base Specification 2 1 or 3 0 in the Root Control register jell ene scl Sko Output Address of the register that has been updated This signal is an index indicating which Configuration Space register information is being driven onto t1_cfg_ctl tli_cfg_sts 52 0 tx_st_ready Output Output Configuration status bits This information updates every p1d_ clk cycle The following table provides detailed descriptions of the status bits Indicates that the Transaction Layer is ready to accept data for transmission The core deasserts this signal to throttle the data stream tx_st_ready may be asserted during reset The Applica tion Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon ST TX interface The reset_status signal can also be used to monitor when the IP core has come out of reset If asserted by the Transaction Layer on cycle lt n gt tx_st_ready then lt n readyLatency gt is a ready cycle during which the Application Layer may assert tx_st_validand transfer data When tx_st_ready tx_st_valid and tx_st_dataare registered the typical case Altera recommends a readyLatency of 2 cycles to facilitate timing closure however a readyLatency
104. errupt Generator CRA Slave Module Control Register O Control amp Status Access Slave Reg CSR Address Translator Avalon MM Tx Slave PCI Express Tx Controller i Z Avalon MM 3 5 5 Tx Read HE S PCI Link E Response S 5 t TX Slave Module HHE E ARES gt Address Translator Avalon MM Rx Master PCI Express Rx Controller Avalon MM Rx Read Response RX Master Module The bridge has the following additional characteristics e Type 0 and Type 1 vendor defined incoming messages are discarded e Completion to a flush request is generated but not propagated to the interconnect fabric For End Points each PCI Express base address register BAR in the Transaction Layer maps to a specific fixed Avalon MM address range You can use separate BARs to map to various Avalon MM slaves connected to the RX Master port In contrast to Endpoints Root Ports do not perform any BAR matching and forwards the address to a single RX Avalon MM master port Altera Corporation IP Core Architecture CJ Send Feedback UG 01105_avmm 2014 12 15 Avalon MM Bridge TLPs 9 11 Related Information Avalon MM RX Master Block on page 9 20 Avalon MM Bridge TLPs The PCI Express to Avalon MM bridge translates the PCI Express read write and completion Transac tion Layer Packets
105. ess width These table entries are repeated for each address specified in the Number of address pages parameter If Number of address pages is set to the maximum of 512 0x1FF8 contains A2P_ADDR_MAP_LO511 and Ox1FFC contains A2P_ ADDR_MAP_HI511 Table 5 18 Avalon MM to PClI Express Address Translation Table 0x1000 0x1FFF 0x1000 0x1004 C 1 0 SPACEO Eo oo E A2P_ADDR_ Address space indication for entry 0 Refer to Table 9 31 for the definition of these bits 31 2 31 0 MAP_1LOO MAP_HIO A2P_ADDR_ A2P_ADDR_ RW RW Lower bits of Avalon MM to PCI Express address map entry 0 Upper bits of Avalon MM to PCI Express address map entry 0 Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 PCI Express to Avalon MM Interrupt Status and Enable Registers for Endpoints 5 19 a S 1 0 0x1008 A2P_ADDR_ SPACE1 Address space indication for entry 1 Refer to the following encodings are defined e 2 b00 Memory Space 32 bit PCI Express address 32 bit header is generated Address bits 63 32 of the translation table entries are ignored e 2 b01 Memory space 64 bit PCI Express address 64 bit address header is generated e 2 b10 Reserved e 2 b11 Reserved 31 2 A2P_ADDR_ MAP_LO1 RW Lower bits of Avalon MM to PCI Express address map entry 1 This entry is only implemented if the number of address trans
106. etchable Memory Base Memory Base 0x028 Reserved N A Prefetchable Base Upper 32 Bits Type 1 Configuration Space Header 0x02C Subsystem ID Subsystem Vendor ID Type 0 Configuration Space Header Prefetchable Limit Upper 32 Bits Type 1 Configuration Space Header 0x030 I O Limit Upper 16 Bits I O Base Upper 16 Type 0 Configuration Space Header pe Type 1 Configuration Space Header 0x034 Reserved Capabilities PTR Type 0 Configuration Space Header Type 1 Configuration Space Header 0x038 Reserved N A 0x03C Interrupt Pin Interrupt Line Type 0 Configuration Space Header Bridge Control Interrupt Pin Interrupt Line Type 1 Configuration Space Header 0x050 MSI Message Control Next Cap Ptr MSI and MSI X Capability Structures Capability ID 0x054 Message Address MSI and MSI X Capability Structures 0x058 Message Upper Address MSI and MSI X Capability Structures 0x05C Reserved Message Data MSI and MSI X Capability Structures Registers Altera Corporation J send Feedback 5 4 Correspondence between Configuration Space Registers and the PCle Specification Byte Address Hard IP Configuration Space Register Corresponding Section in PCle Specification 0x068 MSI X Message Control Next Cap Ptr MSI and MSI X Capability Structures Capability ID 0x06C MSI X Table Offset BIR MSI and MSI X Capability Structures 0x070 Pending Bit Array PBA Offset BIR MSI and MSI X Capability Structures 0x078 Capabilities Registe
107. etion timeout disable mechanism via the PCI Express Device Control Register 2 The Application Layer logic must implement the actual completion timeout mechanism for the required ranges Error Reporting Table 3 5 Error Reporting Advanced error reporting AER On Off When On enables the Advanced Error Reporting AER capability Parameter Settings Send Feedback Altera Corporation UG 01105_avmm Link Capabilities 2014 12 15 ECRC On Off When On enables ECRC checking Sets the read only checking value of the ECRC check capable bit in the Advanced Error Capabilities and Control Register This parameter requires you to enable the AER capability ECRC On Off Off When On enables ECRC generation capability Sets the generation read only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control Register This parameter requires you to enable the AER capability Not applicable for Avalon MM DMA Link Capabilities Table 3 6 Link Capabilities Link port 0x01 Sets the read only value of the port number field in the Link number Capabilities Register Slot clock On Off When On indicates that the Endpoint or Root Port uses the configuration same physical reference clock that the system provides on the connector When Off the IP core uses an independent clock regardless of the presence of a reference clock on the connector MSI and MSI X Capabili
108. f a SKP Ordered Set in the middle of packet e Deskew This sub block performs the multilane deskew function and the RX alignment between the number of initialized lanes and the 64 bit data path The multilane deskew implements an eight word FIFO buffer for each lane to store symbols Each symbol includes eight data bits one disparity bit and one control bit The FIFO discards the FTS COM and SKP symbols and replaces PAD and IDL with D0 0 data When all eight FIFOs contain data a read can occur When the multilane lane deskew block is first enabled each FIFO begins writing after the first COM is detected If all lanes have not detected a COM symbol after seven clock cycles they are reset and the resynchronization process restarts or else the RX alignment function recreates a 64 bit data word which is sent to the DLL 32 Bit PCI Express Avalon MM Bridge The Avalon MM Arria V Hard IP for PCI Express includes an Avalon MM bridge module that connects the Hard IP to the interconnect fabric The bridge facilitates the design of Endpoints and Root Ports that include Qsys components Altera Corporation IP Core Architecture GJ Send Feedback UG 01105_avmm 2014 12 15 32 Bit PCI Express Avalon MM Bridge 9 9 The Avalon MM bridge provides three possible Avalon MM ports a bursting master an optional bursting slave and an optional non bursting slave The Avalon MM bridge comprises the following three modules TX Slave Module This opt
109. face An Avalon MM interface connects the Application Layer and the Transaction Layer The Avalon MM interface implement the Avalon MM protocol described in the Avalon Interface Specifications Refer to this specification for information about the Avalon MM protocol including timing diagrams Altera Corporation IP Core Architecture GJ Send Feedback UG 01105_avmm 2014 12 15 Clocks and Reset 9 3 Related Information e 64 or 128 Bit Avalon MM Interface to the Application Layer on page 4 1 e Avalon Interface Specifications Clocks and Reset The PCI Express Base Specification requires an input reference clock which is called refc1k in this design The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz The PCI Express Base Specification also requires a system configuration time of 100 ms To meet this specification IP core includes an embedded hard reset controller This reset controller exits the reset state after the I O ring of the device is initialized Transceiver Reconfiguration The transceiver reconfiguration interface allows you to dynamically reconfigure the values of analog settings in the PMA block of the transceiver Dynamic reconfiguration is necessary to compensate for process variations Related Information Transceiver PHY IP Reconfiguration on page 12 1 Interrupts The Hard IP for PCI Express offers the following interrupt mechanisms e Message Signaled Interrupts MSI
110. fg_ct1 returns the primary and secondary Link Control registers cfg_link_ctr1 15 0 cfg_link_ ctrl2 15 0 The primary Link Status register contents are available on t1_cfg_sts 46 31 For Gen variants the link bandwidth notification bit is always set to 0 For Gen2 variants this bit is set to 1 cfg_prm_cmd_func lt n gt 16 Output Base Primary Command register for the PCI Configuration Space cfg_root_ctrl Output Root control and status register of the PCI Express capability This register is only available in Root Port mode ChGmSCCmC tall 16 Output Secondary bus Control and Status register of the PCI Express capability This register is available only in Root Port mode cfg_secbus Output Secondary bus number This register is available only in Root Port mode cfg_subbus Output Subordinate bus number This register is available only in Root Port mode Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Configuration Space Register Access 4 23 a es cfg_msi_addr Output cfg_msi_add 63 32 is the message signaled interrupt MSI upper message address cfg_msi_ add 31 0 is the MSI message address CHG io loes 20 Output The upper 20 bits of the I O limit registers of the Typel Configuration Space This register is only available in Root Port mode cfg_io_lim 20 Output The
111. figuration Space of the Completer Only Single Dword Arria V Hard IP for PCI Express are updated there is a delay before this information is propagated to the Bridge module shown in the following figure Figure 9 12 Qsys Design Including Completer Only Single Dword Endpoint for PCI Express Completer Only Single DWord Endpoint Qsys Component to Host CPU Avalon MM Slave Bridge Avalon MM RX Block Avalon MM x Master RX Hard IP PCle Link PCI Express for PCle Root Complex Interrupt Handler TX Block Avalon MM Slave You must allow time for the Bridge module to update the MSI register information Normally setting up MSI registers occurs during enumeration process Under normal operation initialization of the MSI registers should occur substantially before any interrupt is generated However failure to wait until the update completes may result in any of the following behaviors e Sending a legacy interrupt instead of an MSI interrupt e Sending an MSI interrupt instead of a legacy interrupt e Loss of an interrupt request IP Core Architecture Altera Corporation CJ Send Feedback UG 01105_avmm 9 22 Interrupt Handler Block 2014 12 15 According to the PCI Express Base Specification if Ms1_enable 0 and the Disable Legacy Interrupt bit 1 in the Configuration Space command register 0x004 the Hard IP should not send legacy interrupt messages when an interrupt is
112. for the PCI Configuration Space 14 h3C14 cfg_root_ctr1 7 0 Root control and status register of the PCI Express capability This register is only available in Root Port mode 14 h3C18 cfg_sec_ctrl 15 0 Secondary bus Control and Status register of the PCI Express capability This register is only available in Root Port mode 14 h3C1C cfg_secbus 7 0 Secondary bus number Available in Root Port mode 14 h3C20 cfg_subbus 7 0 Subordinate bus number Available in Root Port mode 14 h3C24 cfg_msi_addr_low 31 0 cfg_msi_add 31 0 is the MSI message address Registers GJ send Feedback Altera Corporation 24 Control Register Access CRA Avalon MM Slave Port UG 01105_avmm 2014 12 15 14 h3C28 cfg_msi_addr_hi 63 32 cfg_msi_add 63 32 is the MSI upper message address 14h3C2C cfg_io_bas 19 0 The IO base register of the Typel Configuration Space This register is only available in Root Port mode 14h3C30 cfg_ io lim 19 0 The IO limit register of the Typel Configuration Space This register is only available in Root Port mode 143C34 cfg_np_bas 11 0 The non prefetchable memory base register of the Typel Configuration Space This register is only available in Root Port mode 14 h3C38 cfg_np_lim 11 0 The non prefetchable memory limit register of the Typel Configuration Space This register is only available in Root Port mode 14h3C3C cfg_pr_bas_low 31 0
113. for the receive data stream and receiver detection sim_pipe_ ltssmstate0 4 0 Altera Corporation Input and Output LTSSM state The LTSSM state machine encoding defines the following states e 500000 Detect Quiet e 5 b 00001 Detect Active e 5 b00010 Polling Active e 5b 00011 Polling Compliance e 5b 00100 Polling Configuration e 5 b00101 Polling Speed e 5 b00110 config LinkwidthsStart e 5b 00111 Config Linkaccept e 5 b 01000 Config Lanenumaccept e 5 b01001 Config Lanenumwait e 5 b01010 Config Complete e 5 b 01011 Config Idle e 5b01100 Recovery Rcevlock e 5b01101 Recovery Rcvconfig e 5b01110 Recovery Idle e 5b01111 LO e 5 b10000 Disable e 5 b10001 Loopback Entry e 5 b10010 Loopback Active e 5b10011 Loopback Exit e 5b10100 Hot Reset Interfaces and Signal Descriptions GJ Send Feedback UG 01105_avmm 2014 12 15 PIPE Interface Signals 4 31 O Sigal i O Deseripton OO e 5b10101 LOs e 5b11001 L2 transmit Wake e 5b11010 Speed Recovery e 5b11011 Recovery Equalization Phase 0 e 5b11100 Recovery Equalization Phase 1 e 5b11101 Recovery Equalization Phase 2 e 5 b11110 Recovery Equalization Phase 3 e 5 b11111 Recovery Equalization Done sim_pipe_rate 1 0 Output The 2 bit encodings have the following meanings e 2 b00 Gen1 rate 2 5 Gbps e 2 b01 Gen2 rate 5 0 Gbps e 2 b1X Gen3 rate 8 0 Gbps sim_pipe_pclk_in Input
114. g operation software must ensure that no interrupt request is dropped Therefore software must first enable the new selection and then disable the old selection To set up legacy interrupts software must first clear the Interrupt Disable bit and then clear the MSI enable bit To set up MSI interrupts software must first set the MSI enable bit and then set the Interrupt Disable bit Altera Corporation Interrupts for Endpoints GJ Send Feedback UG 01105_avmm z 73 2014 12 15 Generation of Avalon MM Interrupts Generation of Avalon MM Interrupts The generation of Avalon MM interrupts requires the instantiation of the CRA slave module where the interrupt registers and control logic are implemented The CRA slave port has an Avalon MM Interrupt output signal cra_Irq_irq A write access to an Avalon MM mailbox register sets one of the P2A_MAILBOX_INT lt n gt bits in the Avalon MM to PCI Express Interrupt Status Register and asserts the cra_Irq_o or cra_Irq_irg output if enabled Software can enable the interrupt by writing to the INT_X Interrupt Enable Register for Endpoints through the CRA slave After servicing the interrupt software must clear the appropriate serviced interrupt status bit in the PCI Express to Avalon MM Interrupt Status register and ensure that no other interrupt is pending Related Information e Avalon MM to PCI Express Interrupt Status Registers on page 5 15 e PCI Express to Avalon MM Interrupt Status and Enable
115. g steps to enable PIPE simulation These steps assume that the actual testbench in Gen1 x4 with an Avalon MM 64 bit interface 1 In the top level testbench which is lt working_dir gt lt variant gt testbench lt variant gt _tb simulation lt variant gt _ tb v change the signal hip_ctr1_simu_mode_pipe to 1 b1 as shown pcie_de_genl_x4_ast64 pcie_de_genl_x4_ast64_x_inst dut_hip_ctrl_simu_mode_pipe 1 b1 2 In the top level HDL module for the Hard IP which is lt working_dir gt lt variant gt testbench lt variant gt _tb simulation submodules lt variant gt v change the parameter enable_pipe32_sim_hwtcl parameter to l bl as shown altpcie_ lt dev gt _hip_ast_hwtcl enable_pipe32_sim_hwtcl 1 Using the PIPE Interface for Gen1 and Gen2 Variants Running the simulation in PIPE mode reduces simulation time and provides greater visibility Complete the following steps to simulate using the PIPE interface 1 Change to your simulation directory lt work_dir gt lt variant gt testbench lt variant gt _tb simulation 2 Open lt variant gt _tb v 3 Search for the string serial_sim_hwtcl Set the value of this parameter to 0 if it is 1 4 Save lt variant gt _tb v Altera Corporation Debugging GJ Send Feedback UG 01105_avmm 2014 12 15 Reducing Counter Values for Serial Simulations 13 3 Reducing Counter Values for Serial Simulations You can accelerate simulation by reducing the value of counters w
116. generated IP Core Architecture GJ Send Feedback Altera Corporation Design Implementation 1 2014 12 15 UG 01105_avmm amp Subscribe Send Feedback Completing your design includes additional steps to specify analog properties pin assignments and timing constraints Making Analog QSF Assignments Using the Assignment Editor You specify the analog parameters using the Quartus II Assignment Editor the Pin Planner or through the Quartus II Settings File qsf Table 10 1 Power Supply Voltage Requirements Arria V GX Gen and Gen2 LIV 25V Arria V GT Gen1 and Gen2 1 2 V 25V The Quartus II software provides default values for analog parameters You can change the defaults using the Assignment Editor or the Pin Planner You can also edit your qsf directly or by typing commands in the Quartus II Tcl Console The following example shows how to change the value of the voltages required 1 On the Assignments menu select Assignment Editor The Assignment Editor appears 2 Complete the following steps for each pin requiring the Vccr gxp and V ccr cxp voltage a Double click in the Assignment Name column and scroll to the bottom of the available assignments b Select VCCR_GXB VCCT_GXB Voltage c In the Value column select 1_1V from the list 3 Complete the following steps for each pin requiring the Vcca_gxp voltage a Double click in the Assignment Name column and scroll to the bottom of the available assi
117. gnments b Select VCCA_GXB Voltage c In the Value column select 3_0V from the list The Quartus II software adds these instance assignments commands to the qsf file for your project 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN DO fs RYA 101 Innovation Drive San Jose CA 95134 z UG 01105_avmm 10 2 Making Pin Assignments 2014 12 15 You can also enter these commands at the Quartus II Tcl Console For example the following command sets the XC
118. he Correspondence between Configuration Space Registers and the PCle Specification on page 5 1 lists the appropriate section of the PCI Express Base Specification that describes these registers Registers Send Feedback 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 31 24 23 16 15 87 Device ID Vendor ID Status Command Class Code Revision ID 0x00 Header Type 0x00 Cache Line Size BAR Registers BAR Registers BAR Registers BAR Registers BAR Registers BAR Registers Reserved Subsystem Device ID Subsystem Vendor ID Expansion ROM Base Address Reserved Capabilities Pointer Reserved 0x00 Interrupt Pin Interrupt Line Altera Corporation 5 6 Type 1 Configuration Space Registers UG 01105_avmm 2014 12 15 Type 1 Configuration Space Registers Figure 5 2 Type 1 Configuration Space Registers Root Ports 31 24 23 16 15 87 0 0x0000 Device ID Vendor ID 0x004 Status Command 0x008 Class Code Revision ID 0x00 BIST Header Type Primary Latency Timer Cache Line Size 0x010 BAR Registers 0x014 BAR Registers 0x018 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 0x01C Secondary Status 1 0 Limit 1 0 Base 0x020 Memory Limit Memory Base 0
119. he cpl_err 0 signal Completer abort Uncorrectable non fatal The Application Layer reports this error using the cp1_ err 2 signal when it aborts receipt of a TLP Altera Corporation Error Handling G send Feedback UG 01105_avmm 2014 12 15 Transaction Layer Errors 8 5 A am Unexpected completion Uncorrectable non fatal This error is caused by an unexpected completion transaction The Hard IP block handles the following conditions e The Requester ID in the completion packet does not match the Configured ID of the Endpoint e The completion packet has an invalid tag number Typically the tag used in the completion packet exceeds the number of tags specified e The completion packet has a tag that does not match an outstanding request e The completion packet for a request that was to I O or Configuration Space has a length greater than 1 dword e The completion status is Configuration Retry Status CRS in response to a request that was not to Configuration Space In all of the above cases the TLP is not presented to the Application Layer the Hard IP block deletes it The Application Layer can detect and report other unexpected completion conditions using the cp1_ err 2 signal For example the Application Layer can report cases where the total length of the received successful completions do not match the original read request length Receiver overflow Uncorrectab
120. hen asserted indicates that the Hard IP block is in the Data Link Control and Management State Machine DLCMSM DL_ Up state dlup_exit Output This signal is asserted low for one p1a_c1k cycle when the IP core exits the DLCMSM DL_Up state indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state When this pulse is asserted the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles evl28ns Output Asserted every 128 ns to create a time base aligned activity evlus Output Asserted every lus to create a time base aligned activity hotrst_exit Output Hot reset exit This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset state This signal should cause the Application Layer to be reset This signal is active low When this pulse is asserted the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles 3 Debug signals are not rigorously verified and should only be used to observe behavior Debug signals should not be used to drive custom logic Interfaces and Signal Descriptions J send Feedback Altera Corporation 4 12 Hard IP Status UG 01105_avmm 2014 12 15 O Sigal O Direction Deseripton O O int_status 3 0 Output These signals drive legacy interrupts to the Application Layer as follows e int_status
121. his register is written by the programming software to control CvP programming wits Register Description Reset Value 31 2 Reserved 0x0000 RO Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 64 or 128 Bit Avalon MM Bridge Register Descriptions 5 13 EE Register Description Reset Value 1 b0 START_XFER Sets the CvP output to the FPGA control block indicating the start of a transfer 0 CVP_CONFIG When asserted instructs that the FPGA control 1 b0 RW block begin a transfer via CvP 64 or 128 Bit Avalon MM Bridge Register Descriptions The CRA Avalon MM slave module provides access control and status registers in the PCI Express Avalon MM bridge In addition it provides access to selected Configuration Space registers and link status registers in read only mode This module is optional However you must include it to access the registers The control and status register address space is 16 KBytes Each 4 KByte sub region contains a set of functions which may be specific to accesses from the PCI Express Root Complex only from Avalon MM processors only or from both types of processors Because all accesses come across the interconnect fabric requests from the Avalon MM Arria V Hard IP for PCI Express are routed through the interconnect fabric hardware does not enforce restrictions to limit individual processor access to specific regions However the regions are de
122. his value indicates the acceptable latency that an Endpoint acceptable can withstand in the transition from the L1 to LO state It is an latency MES SEATS ZC ad raac aagnaeroas ane Endpoint s internal buffering It sets Maximum of 4 us the read only value of the Endpoint L1 acceptable latency field Maximam OES as of the Device Capabilities Register 2 This Endpoint does not support the LOs or L1 states However Maximum of 16 us i a switched system may include links connected to switches Maximum of 32 us__ that have LOs and L1 enabled This parameter is set to allow No limit system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management ASPM This setting is disabled for Root Ports The default value of this parameter is 1 us This is the safest setting for most designs Altera Corporation Parameter Settings CJ Send Feedback UG 01105_avmm 2014 12 15 Avalon Memory Mapped System Settings 3 9 Avalon Memory Mapped System Settings Table 3 9 Avalon Memory Mapped System Settings Avalon MM data width 64 bit 128 bit Avalon MM address width 32 bit 64 bit Specifies the data width for the Application Layer to Transaction Layer interface Refer to Application Layer Clock Frequencies for All Combinations of Link Width Data Rate and Application Layer Interface Widths for all legal combinations of
123. hose default values are set for hardware not simulation Complete the following steps to reduce counter values for simulation 1 Open lt work_dir gt lt variant gt testbench lt variant gt _tb simulation submodules altpcie_tbed_ lt dev gt _hwtcl v 2 Search for the string test_in 3 To reduce the value of several counters set test_in 0 1 4 Save altpcietb_bfm_top_rp v Disable the Scrambler for Gen1 and Gen2 Simulations The encoding scheme implemented by the scrambler applies a binary polynomial to the data stream to ensure enough data transitions between 0 and 1 to prevent clock drift The data is decoded at the other end of the link by running the inverse polynomial Complete the following steps to disable the scrambler 1 Open lt work_dir gt lt variant gt testbench lt variant gt _tb simulation submodules altpcie_tbed_ lt dev gt _hwtcl v 2 Search for the string test_in 3 To disable the scrambler set test_in 2 1 4 Save altpcie_tbed_sv_hwtcl v Changing between the Hard and Soft Reset Controller The Hard IP for PCI Express includes both hard and soft reset control logic By default Gen1 devices use the Hard Reset Controller Gen2 devices use the soft reset controller For variants that use the hard reset controller changing to the soft reset controller provides greater visibility Complete the following steps to change to the soft reset controller 1 Open lt work_dir gt lt variant gt testbench
124. icensing Manual Setting up and Running Analysis and Synthesis Steps in Creating a Design for PCI Express Before you begin Select the PCIe variant that best meets your design requirements e Is your design an Endpoint or Root Port e What Generation do you intend to implement e What link width do you intend to implement e What bandwidth does your application require e Does your design require CvP 1 Select parameters for that variant 2 Simulate using an Altera provided example design All of Altera s PCI Express example designs are available under lt install_dir gt ip altera altera_pcie Alternatively create a simulation model and use your own custom or third party BFM The Qsys Generate menu generates simulation models Altera supports ModelSim Altera for all IP The PCle cores support the Aldec RivieraPro Cadence NCsim Mentor Graphics ModelSim and Synopsys VCS and VCS MxX simulators 3 Compile your design using the Quartus II software If the versions of your design and the Quartus II software you are running do not match regenerate your PCIe design 4 Download your design to an Altera development board or your own PCB Click on the All Develop ment Kits link below for a list of Altera s development boards 5 Test the hardware You can use Altera s SignalTap II Logic Analyzer or a third party protocol analyzer to observe behavior 6 Substitute your Application Layer logic for the Application Layer logic in Altera
125. ices Related Information Transceiver Architecture in Arria V Devices Channel Placement in Arria V Devices Figure 4 10 Arria V Gen1 and Gen2 Channel Placement Using the CMU PLL In the following figures the channels shaded in blue provide the transmit CMU PLL generating the high speed serial clock x1 5 PCle Hard IP ch4 h3 cha CMU PLL x8 ho lep ho hit PCle Hard IP Ch10 x2 Ch9 5 PCle Hard IP h8 lep ch CMU PLL thy le gt che h3 h6 lap h5 cha h5 lap h4 h e h CMU PLL hO lep cho h3 le h3 Cha la gt h x4 h e chi 5 PCle Hard IP ho lp cho CMU PLL 3 lap h Cha e gt h hM le h hO lep cho You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration PIPE Interface Signals These PIPE signals are available for Gen1 and Gen2 variants so that you can simulate using either the serial or the PIPE interface Simulation is much faster using the PIPE interface because the PIPE simulation bypasses the SERDES model By default the PIPE interface is 8 bits for Gen1 and Gen2 You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers However it is not possible to use the Hard IP PIPE interface in hardware including probing these signals using Sig
126. if TD is 1 the TLP includes an ECRC tp is the TL digest bit of the TL packet described in Appendix A Transaction Layer Packet TLP Header Formats The EcRC Check Enable field is in the configuration Space Advanced Error Capabilities and Control Register Optional Features Altera Corporation Send Feedback 11 4 ECRC on the TX Path Table 11 3 ECRC Generation and Forwarding on TX Path All unspecified cases are unsupported and the behavior of the Hard IP is unknown ECRC Forwarding ECRC Generation TLP on Applica TLP on Link Comments Enable tion UG 01105_avmm 2014 12 15 TD 0 without TD 0 without ECRC ECRC No TD 1 without TD 0 without ECRC ECRC No TD 0 without Tp 1 with ECRC ECRC Yes ECRC is generated TD 1 without Tp 1 with ECRC ECRC TD 0 without TD 0 without ECRC ECRC No TD 1 with TD 1 with ECRC ECRC Yes n O without oi Core forwards the ECRC ECRC without Yes ECRC TD 1 with TD 1 with ECRC ECRC Related Information Transaction Layer Packet TLP Header Formats on page 14 1 The ECRC Generation Control Register Altera Corporation Enable field is in the Configuration Space Advanced Error Capabilities and Optional Features GJ Send Feedback Transceiver PHY IP Reconfiguration 2014 12 15 UG 01105_avmm amp Subscribe Send Feedback As silicon progresses towards smaller process nodes c
127. ing nPERST pin of the device These pins have the following locations e nPERSTLO bottom left Hard IP and CvP blocks e nPERSTL1 top left Hard IP block For example if you are using the Hard IP instance in the bottom left corner of the device you must connect pin_perst to nPERSLO For maximum use of the Arria V device Altera recommends that you use the bottom left Hard IP first This is the only location that supports CvP over a PCIe link Refer to the appropriate device pinout for correct pin assignment for more detailed information about these pins The PCI Express Card Electromechanical Specification 2 0 specifies this pin requires 3 3 V You can drive this 3 3V signal to the nPERST Altera Corporation UG 01105_avmm 4 10 Hard IP Status 2014 12 15 O Sigal i Deseripton O O even if the Vyccpam of the bank is not 3 3V if the following 2 conditions are met e The input signal meets the Vy and Vj specification for LVTTL e The input signal meets the overshoot specification for 100 C operation as specified by the Maximum Allowed Overshoot and Undershoot Voltage in the Device Datasheet for Arria V Devices Figure 4 2 Reset and Link Training Timing Relationships The following figure illustrates the timing relationship between npor and the LTSSM LO state npor ooo 10_POF_Load PCle_LinkTraining_Enumeration dl_Itssm 4 0 detect detect activg polling activ LO
128. ink Protocol Error Status Undefined Error Handling Altera Corporation J send Feedback 8 8 Uncorrectable and Correctable Error Status Bits Figure 8 2 Correctable Error Status Register UG 01105_avmm 2014 12 15 The default value of all the bits of this register is 0 An error status bit that is set indicates that the error condition it represents has been detected Software may clear the error status by writing a 1 to the appropriate bit 31 16 15 14 13 1211 9 8 7 6 Rsvd Rsvd Rsvd Header Log Overflow Status Corrected Internal Error Status Advisory Non Fatal Error Status Replay Timer Timeout Status REPLAY_ NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Altera Corporation pr Error Handling GJ Send Feedback IP Core Architecture 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback The Avalon MM Arria V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification The protocol stack includes the following layers Transaction Layer The Transaction Layer contains the Configuration Space which manages communication with the Application Layer the RX and TX channels the RX buffer and flow contro
129. intend to use for simulation 10 Click Next to display the Summary page 11 Check the Summary page to ensure that you have entered all the information correctly 12 Click Finish to create the Quartus II project 13 Add the Synopsys Design Constraint SDC commands shown in the following example to the top level design file for your Quartus II project 14 To compile your design using the Quartus II software on the Processing menu click Start Compila tion The Quartus II software then performs all the steps necessary to compile your design 15 After compilation expand the TimeQuest Timing Analyzer folder in the Compilation Report Note whether the timing constraints are achieved in the Compilation Report 16 If your design does not initially meet the timing constraints you can find the optimal Fitter settings for your design by using the Design Space Explorer To use the Design Space Explorer click Launch Design Space Explorer on the tools menu Example 2 1 Synopsys Design Constraints create_clock period 100 MHz name refclk_pci_express refclk_ derive_pll_clocks derive_clock_uncertainty PHY IP reconfig controller constraints Set reconfig_xcvr clock Modify to match the actual clock pin name used for this clock and also changed to have the correct period set create_clock period 125 MHz name reconfig_xcvr_clk reconfig_xcvr_clk Altera Corporation Getting Started with the Avalon MM Arria V Hard IP for P
130. ional timeout completion timeout programmability mechanism This BCD f range mechanism allows system software to modify the ABC completion timeout value This field is applicable only to AB Root Ports and Endpoints that issue requests on their own behalf Completion timeouts are specified and B enabled in the Device Control 2 register 0x0A8 of the PCI Express Capability Structure Version For all other None Parameter Settings CJ Send Feedback Altera Corporation UG 01105_avmm 2014 12 15 Error Reporting functions this field is reserved and must be hardwired to 0x0000b Four time value ranges are defined e Range A 50 us to 10 ms e Range B 10 ms to 250 ms e Range C 250 ms to 4s e Range D 4s to 64s Bits are set to show timeout value ranges supported The function must implement a timeout value in the range 50 s to 50 ms The following values specify the range e None Completion timeout programming is not supported e 0001 Range A e 0010 Range B e 0011 Ranges A and B e 0110 Ranges B and C e 0111 Ranges A B and C e 1110 Ranges B C and D e 1111 Ranges A B C and D All other values are reserved Altera recommends that the completion timeout mechanism expire in no less than 10 ms Implement completion timeout disable On Off For Endpoints using PCI Express version 2 1 or 3 0 this option must be On The timeout range is selectable When On the core supports the compl
131. ional 64 or 128 bit bursting Avalon MM dynamic addressing slave port propagates read and write requests of up to 4 KBytes in size from the interconnect fabric to the PCI Express link The bridge translates requests from the interconnect fabric to PCI Express request packets RX Master Module This 64 or 128 bit bursting Avalon MM master port propagates PCI Express requests converting them to bursting read or write requests to the interconnect fabric Control Register Access CRA Slave Module This optional 32 bit Avalon MM dynamic addressing slave port provides access to internal control and status registers from upstream PCI Express devices and external Avalon MM masters Implementations that use MSI or dynamic address translation require this port The CRA port supports single dword read and write requests It does not support bursting When you select the Single dword completer for the Avalon MM Hard IP for PCI Express Qsys substitutes a unpipelined 32 bit RX master port for the 64 or 128 bit full featured RX master port The following figure shows the block diagram of a full featured PCI Express Avalon MM bridge IP Core Architecture Altera Corporation CJ Send Feedback 7 3 UG 01105_avmm 9 10 32 Bit PCI Express Avalon MM Bridge 2014 12 15 Figure 9 4 PCI Express Avalon MM Bridge PCI Express MegaCore Function PCI Express Avalon MM Bridge Avalon Clock Domain PCI Express Clock Domain MSI or Legacy Int
132. ircuit performance is affected by variations due to process voltage and temperature PVT Designs typically require offset cancellation to ensure correct operation At Gen2 data rates designs also require DCD calibration Altera s Qsys example designs all include Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP cores to perform these functions Connecting the Transceiver Reconfiguration Controller IP Core The Transceiver Reconfiguration Controller IP Core is available for V series devices and can be found in the Interface Protocols Transceiver PHY category in the IP Catalog When you instantiate the Transceiver Reconfiguration Controller the Enable offset cancellation block and Enable PLL calibration options are enabled by default Figure 12 1 Altera Transceiver Reconfiguration Controller Connectivity The following figure shows the connections between the Transceiver Reconfiguration Controller instance and the PHY IP Core for PCI Express instance for a x4 variant Hard IP for PCI Express Variant Hard IP for PCI Express Trans action PHY IP Core for PCI Express Unused 100 125 MHz Lane 3 Avalon MM lane Slave Interface gt to and from Embedded Controller 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in
133. irectory shown is correct You do not have to change it b For the project name browse to the synthesis directory that includes your Qsys project lt working_dir gt ep_g1x4 synthesis Select your variant name ep_g1x4 v Then click Open c Ifthe top level design entity and Qsys system names are identical the Quartus II software treats the Qsys system as the top level design entity Click Next to display the Add Files page Complete the following steps to add the Quartus II IP File qip to the project Click the browse button The Select File dialog box appears In the Files of type list select IP Variation Files qip Browse to the lt working_dir gt ep_g1x4 synthesis directory Click ep_g1x4 qip and then click Open On the Add Files page click Add then click OK ean oes Click Next to display the Device page On the Family amp Device Settings page choose the following target device family and options a In the Family list select Arria V GT GX ST SX b In the Devices list select Arria V GX Extended Features c In the Available Devices list select 5 AGXFB3H6F35C6 Click Next to close this page and display the EDA Tool Settings page Getting Started with the Avalon MM Arria V Hard IP for PCI Express Altera Corporation CJ Send Feedback 2 6 Compiling the Design in the Quartus II Software jik bere 9 From the Simulation list select ModelSim From the Format list select the HDL language you
134. k e Corrected bit definitions for CvP status register e Updated definition of cvp_NumcLKs in the cvP Mode Control register e Added definitions for test_in 2 test_in 6 and test_in 7 e Removed requirement that Txswrite_i be asserted continuously throughout a write burst txswrite_i may be deasserted and reasserted during a burst e Corrected Channel Utilization table for x1 instances Data is driven on Channel 0 The CMU clock is on Channel 1 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any Seh aa egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing or
135. k Settings l Project Settings Instance Parameters f System Inspector HDL Example f Generation Use Connections Name Description Base clk_0 Clock Source E PCle Avalon MM Stratix V Hard IP for PC corecikout Clock Output refclk Clock Input nreset_status Reset Output Rxm_BARO Avalon Memory Mapped Master IRQ O Rxm_BAR2 Avalon Memory Mapped Master Rxm_BAR4 Avalon Memory Mapped Master Cra Avalon Memory Mapped Slave 0x1000_4000 ll E Instruction Mem On Chip Memory RAM or ROM a cik1 Clock Input s1 Avalon Memory Mapped Slave 0x1002_0000 resetl Reset Input Y Quick_Data_Mem On Chip Memory RAM or ROM clkl Clock Input s1 Avalon Memory Mapped Slave 0x1000_0000 resetl Reset Input E Offchip_Data_Mem DDR3 SDRAM Controller with UniPHY pll_ref_cik Clock Input global_reset Reset Input soft_reset Reset Input afi_clk Clock Output afi_half_clk Clock Output afi_reset Reset Output avl Avalon Memory Mapped Slave 0x0000_0000 E Nios2 Nios Il Processor clk Clock Input reset_n Reset Input data_master Avalon Memory Mapped Master IRQ O instruction_master Avalon Memory Mapped Master jtag_debug_module_reset Reset Output jtag_debug_module Avalon Memory Mapped Slave 0x1000_13800 x custom_instruction_master Custom Instruction Master Figure 9 7 Poor Address Map The following figure illustrates the address map for this system System Contents Address Map Clock Settings I Project Settings Instance P
136. ks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm 2014 12 15 The Message window of the GUI dynamically updates the number of credits for Posted Non Posted Headers and Data and Completion Headers and Data as you change this selection 3 2 Avalon MM System Settings e Minimum RX Buffer credit allocation performance for received requests This setting configures the minimum PCle specification allowed for non posted and posted request credits leaving most of the RX Buffer space for received completion header and data Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link e Low This setting config
137. l credits e Data Link Layer The Data Link Layer located between the Physical Layer and the Transaction Layer manages packet transmission and maintains data integrity at the link level Specifically the Data Link Layer performs the following tasks e Manages transmission and reception of Data Link Layer Packets DLLPs e Generates all transmission cyclical redundancy code CRC values and checks all CRCs during reception e Manages the retry buffer and retry mechanism according to received ACK NAK Data Link Layer packets e Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the Transaction Layer e Physical Layer The Physical Layer initializes the speed lane numbering and lane width of the PCI Express link according to packets received from the link and directives received from higher layers 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 prod
138. lation table The lt w gt value is determined when the system is created Altera Corporation Interfaces and Signal Descriptions L3 Send Feedback UG 01105_avmm 2014 12 15 64 or 128 Bit Bursting TX Avalon MM Slave Signals 4 7 TxsByteEnable_i lt w gt 1 0 Input Write byte enable for data A burst must be continuous Therefore all intermediate data phases of a burst must have a byte enable value of OxFF The first and final data phases of a burst can have other valid values For the 128 bit interface the following restrictions apply e All bytes of a single dword must either be enabled or disabled e Ifmore than 1 dword is enabled the enabled dwords must be contiguous The following patterns are legal e 16 bF000 e 16 b0F00 e 16 b00F0 e 16 b000F e 16 bFFOO e 16 bOFFO e 16 b00FF e 16 bFFFO e 16 bOFFF e 16 bDFFFF TxsReadDataValid_o Output Asserted by the bridge to indicate that read data is valid TxsReadData_o 127 or 63 0 Output The bridge returns the read data on this bus when the RX read completions for the read have been received and stored in the internal buffer TxsWaitrequest_o Output Asserted by the bridge to hold off read or write data when running out of buffer space If this signal is asserted during an operation the master should maintain the TxsRead_i signal or TxsWrite_i signal and TxsWriteData stable until after Txswaitrequest_ o is deasserted tx
139. lation table entries is greater than 1 0x100C_ 31 0 A2P_ADDR_ MAP_HI1 RW Upper bits of Avalon MM to PCI Express address map entry 1 This entry is only implemented if the number of address translation table entries is greater than 1 PCI Express to Avalon MM Interrupt Status and Enable Registers for Endpoints The registers in this section contain status of various signals in the PCI Express Avalon MM bridge logic and allow Avalon interrupts to be asserted when enabled A processor local to the interconnect fabric that processes the Avalon MM interrupts can access these registers Note These registers must not be accessed by the PCI Express Avalon MM bridge master ports however there is nothing in the hardware that prevents a PCI Express Avalon MM bridge master port from accessing these registers The following table describes the Interrupt Status register when you configure the core as an Endpoint It records the status of all conditions that can cause an Avalon MM interrupt to be asserted Table 5 19 PCI Express to Avalon MM Interrupt Status Register for Endpoints 0x3060 ee E ERR_PCI_WRITE_FAILURE RWIC_ When set to 1 indicates a PCI Express write failure This bit can also be cleared by writing a 1 to the same bit in the Avalon MM to PCI Express Interrupt Status register Registers Send Feedback Altera Corporation UG 01105_avmm 5
140. le This error occurs when a component receives a TLP that fatal violates the FC credits allocated for this type of TLP In all cases the hard IP block deletes the TLP and it is not presented to the Application Layer Flow control protocol Uncorrectable This error occurs when a component does not receive error FCPE fatal update flow control credits with the 200 us limit Error Handling CJ Send Feedback Altera Corporation 8 6 Error Reporting and Data Poisoning UG 01105_avmm 2014 12 15 A e m Malformed TLP Uncorrectable fatal This error is caused by any of the following conditions The data payload of a received TLP exceeds the maximum payload size e The tp field is asserted but no TLP digest exists or a TLP digest exists but the TD bit of the PCI Express request header packet is not asserted e A TIP violates a byte enable rule The Hard IP block checks for this violation which is considered optional by the PCI Express specifications e A TLP in which the type and length fields do not correspond with the total length of the TLP e A TLP in which the combination of format and type is not specified by the PCI Express specification e A request specifies an address length combination that causes a memory space access to exceed a 4 KByte boundary The Hard IP block checks for this violation which is considered optional by the PCI Express specification e Messages such as Assert_INTX Power M
141. lication Layer should be held in reset until reconfig_clk_ locked is asserted The following table shows the number of logical reconfiguration and physical interfaces required for various configurations The Quartus II Fitter merges logical interfaces to minimize the number of physical interfaces configured in the hardware Typically one logical interface is required for each channel and one for each PLL Interfaces and Signal Descriptions Send Feedback Altera Corporation UG 01105_avmm 4 16 Hard IP Status Extension 2014 12 15 The x8 variants require an extra channel for PCS clock routing and control The x8 variants use channel 4 for clocking Table 4 9 Number of Logical and Physical Reconfiguration Interfaces Genl and Gen2 x1 2 Genl and Gen2 x2 3 Genl and Gen2 x4 5 Genl x8 10 For more information about the Transceiver Reconfiguration Controller refer to the Transceiver Reconfi guration Controller chapter in the Altera Transceiver PHY IP Core User Guide Related Information Altera Transceiver PHY IP Core User Guide Hard IP Status Extension Table 4 10 Hard IP Status Extension Signals This optional bus adds signals that are useful for debugging to the top level variant including e The most important native Avalon ST RX signals e The Configuration Space signals e The BAR e The ECC error e The signal indicating that the p1d_clk is in use O Sigal a Description O O pld clk_inuse
142. llel FPP or Active Quad Device Configuration Config Cntl Block PCle Port PCle Link used for i Hard IP Configuration via Protocol CvP for Pale Altera FPGA 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01105_avmm 11 2 ECRC 2014 12 15 CvP has the following advantages e Provides a simpler software model for configuration A smart host can use the PCIe protocol and the application
143. ltera_pcie_ lt dev gt __hip_avmm example_designs directory e ep_glxl qsys e ep_glx4 qsys e ep_g1x8 qsys e ep_g2xl qsys e ep_g2x4 qsys Click on the link below to get started with the example design provided in this user guide Related Information Getting Started with the Avalon MM Arria V Hard IP for PCI Express on page 2 1 CJ Send Feedback Altera Corporation UG 01105_avmm 1 8 Debug Features 2014 12 15 Debug Features Debug features allow observation and control of the Hard IP for faster debugging of system level problems Related Information Debugging on page 13 1 IP Core Verification To ensure compliance with the PCI Express specification Altera performs extensive verification The simulation environment uses multiple testbenches that consist of industry standard bus functional models BFMs driving the PCI Express link interface Altera performs the following tests in the simulation environment e Directed and pseudorandom stimuli are applied to test the Application Layer interface Configuration Space and all types and sizes of TLPs e Error injection tests that inject errors in the link TLPs and Data Link Layer Packets DLLPs and check for the proper responses e PCI SIG Compliance Checklist tests that specifically test the items in the checklist e Random tests that test a wide range of traffic patterns Altera provides the following two example designs that you can leverage to test your PCBs and co
144. ly have one outstanding non posted request at a time The Application Layer must use tags 16 31 to identify non posted requests Note For Root Ports the Avalon MM bridge does not filter Type 0 Configuration Requests by device number Application Layer software should filter out all requests to Avalon MM Root Port registers that are not for device 0 Application Layer software should return an Unsupported Request Completion Status Sending a Write TLP The Application Layer performs the following sequence of Avalon MM accesses to the CRA slave port to send a Memory Write Request 1 Write the first 32 bits of the TX TLP to RP_TX_REGO 2 Write the next 32 bits of the TX TLP to RP_TX_REG1 3 Write the RP_TX_CNTRL SOP to l b1 to push the first two dwords of the TLP into the Root Port TX FIFO 4 Repeat Steps 1 and 2 The second write to RP_TX_REG1 is required even for three dword TLPs with aligned data 5 Ifthe packet is complete write RP_Tx_CNTRL to 2 b10 to indicate the end of the packet If the packet is not complete write 2 b00 to RP_TX_CNTRL 6 Repeat this sequence to program a complete TLP When the programming of the TX TLP is complete the Avalon MM bridge schedules the TLP with higher priority than TX TLPs coming from the TX slave port Sending a Read TLP or Receiving a Non Posted Completion TLP The TLPs associated with the Non Posted TX requests are stored in the RP_RX_CPL FIFO buffer and subsequently loade
145. ly scrambles the data e 4 3 Reserved Must be set to 4 b01 e 5 Compliance test mode Disable force compliance mode When set prevents the LTSSM from entering compliance mode Toggling this bit controls the entry and exit from the compliance state enabling the transmission of compliance patterns e 6 Forces entry to compliance mode when a timeout is reached in the polling active state and not all lanes have detected their exit condition 7 Disable low power state negotiation Altera recommends setting thist bit e 31 8 Reserved Set to all Os simu_mode_pipe Input When high indicates that the PIPE interface is in simulation mode hip_currentspeed 1 0 Output Indicates the current speed of the PCIe link The following encodings are defined e 2b 00 Undefined e 2b01 Genl e 2b 10 Gen2 e 2b11 Gen3 Altera Corporation Interfaces and Signal Descriptions G send Feedback Registers 2014 12 15 UG 01105_avmm ZA Subscribe Send Feedback 5 Correspondence between Configuration Space Registers and the PCle Specification Table 5 1 Correspondence between Configuration Space Capability Structures and PCle Base Specification Description For the Type 0 and Type 1 Configuration Space Headers the first line of each entry lists Type 0 values and the second line lists Type 1 values when the values differ Byte Address Hard IP Configuration Space Register Corresponding Sectio
146. ly to the Hard IP for PCI Express and does not connect to the FPGA fabric Related Information PCI Express Base Specification 2 1 or 3 0 coreclkout_hip Table 6 2 Application Layer Clock Frequency for All Combinations of Link Width Data Rate and Application Layer Interface Widths The coreclkout_hip signal is derived from pc1k The following table lists frequencies for coreclkout_hip which are a function of the link width data rate and the width of the Application Layer to Transaction Layer interface The frequencies and widths specified in this table are maintained throughout operation If the link downtrains to a lesser link width or changes to a different maximum link rate it maintains the frequencies it was originally configured for as specified in this table The Hard IP throttles the interface to achieve a lower throughput x1 Genl 64 62 5 MHz xl Genl 64 125 MHz x2 Genl 64 125 MHz x4 Genl 64 125 MHz x8 Genl 128 125 MHz xl Gen2 64 125 MHz This mode saves power Altera Corporation Reset and Clocks CJ Send Feedback UG 01105_avmm 2014 12 15 pld_clk 6 7 Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip Gene 125 MHz x4 Gen2 128 125 MHz pld_clk coreclkout_hip can drive the Application Layer clock along with the p1a_c1k input to the IP core The pld_clk can optionally be sourced by a different clock than coreclkout_hip The pld_clk minimum frequency cannot be
147. mailbox register write access sets a bit in the Avalon MM to PCI Express Interrupt Status register Multiple bits can be set at the same time Application Layer software on the host side determines priorities for servicing simultaneous incoming interrupt requests Fach set bit in the Avalon MM to PCI Express Interrupt Status register generates a PCI Express interrupt if enabled when software determines its turn Software can enable the individual interrupts by writing to the Avalon MM to PCI Express Interrupt Enable Register through the CRA slave When any interrupt input signal is asserted the corresponding bit is written in the Avalon MM to PCI Express Interrupt Status Register Software reads this register and decides priority on servicing requested interrupts After servicing the interrupt software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending For interrupts caused by Avalon MM to PCI Express Interrupt Status Register mailbox writes the status bits should be cleared in the Avalon MM to PCI Express Interrupt Status Register For interrupts due to the incoming interrupt signals on the Avalon MM interface the interrupt status should be cleared in the Avalon MM component that sourced the interrupt This sequence prevents interrupt requests from being lost during interrupt servicing 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX ME
148. mory segments is used to determine the number of address MSB to be replaced In addition each entry has a 2 bit field IP Core Architecture Altera Corporation CJ Send Feedback i UG 01105_avmm 9 18 Avalon MM to PCI Express Address Translation Algorithm for 32 Bit Addressing 2014 12 15 Sp 1 0 that specifies 32 bit or 64 bit PCI Express addressing for the translated address The most significant bits of the Avalon MM address are used by the interconnect fabric to select the slave port and are not available to the slave The next most significant bits of the Avalon MM address index the address translation entry to be used for the translation process of MSB replacement For example if the core is configured with an address translation table with the following attributes e Number of Address Pages 16 e Size of Address Pages 1 MByte e PCI Express Address Size 64 bits then the values in the following figure are e N 20 due to the 1 MByte page size e Q 16 number of pages e M 24 20 4 bit page selection e P 64 In this case the Avalon address is interpreted as follows e Bits 31 24 select the TX slave module port from among other slaves connected to the same master by the system interconnect fabric The decode is based on the base addresses assigned in Qsys e Bits 23 20 select the address translation table entry e Bits 63 20 of the address translation table entry become PCI Express address bits 63 20 e Bits
149. mplete compliance base board testing CBB testing at PCI SIG Related Information e PCI SIG Gen3 x8 Merged Design Stratix V e PCI SIG Gen2 x8 Merged Design Stratix V Compatibility Testing Environment Altera has performed significant hardware testing to ensure a reliable solution In addition Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac turers All PCI SIG compliance tests are run with each IP core release Performance and Resource Utilization Because the PCle protocol stack is implemented in hardened logic it uses less than 1 of device resources The Avalon MM bridge is implemented in soft logic and functions as a front end to the hardened protocol stack The following table shows the typical device resource utilization for selected configura tions using the current version of the Quartus II software With the exception of M10K memory blocks the numbers of ALMs and logic registers in the following tables are rounded up to the nearest 50 Altera Corporation Datasheet GJ Send Feedback UG 01105_avmm 2014 12 15 Recommended Speed Grades 1 9 Table 1 5 Performance and Resource Utilization Avalon MM Hard IP for PCI Express Data Rate or Interface Memory M10K Logic Registers Width Avalon MM Bridge Genl x4 1250 27 1700 Gen2 x8 2100 35 3050 Avalon MM Interface Completer Only 64 600 11 900 128 1350 22 2300 Avalon MM
150. n Arria V SX and ST Devices GXB_L2 GXB_L1 GXB_LO Notes 30 Ch GXB_R1 GXB_RO 1 PCle HIP availability varies with device variants 2 Green blocks are 10 Gbps channels 3 Blue blocks are 6 Gbps channels With the exception of Ch0 to Ch2 in GXB_LO and GXB_RO the 6 Gbps channels can be used for TX only or RX only 10 Gbps channels Channel utilization for x1 x2 x4 and x8 variants is as follows Table 4 15 Channel Utilization x1 1 instance Channel 0 of GXB_LO Channel 1 of GXB_LO x1 2 instances Channel 0 of GXB_LO Channel 0 of GXB_RO Channel 1 of GXB_LO Channel 1 of GXB_RO x2 1 instance Channels 1 2 of GXB_LO Channel 4 of GXB_LO x2 2 instances x4 1 instance Channels 1 2 of GXB_LO Channels 1 2 of GXB_RO Channels 0 3 of GXB_LO Channel 4 of GXB_LO Channel 4 of GXB_RO Channel 4 of GXB_LO x4 2 instances Channels 0 3 of GXB_LO Channels 0 3 of GXB_RO Channel 4 of GXB_LO Channel 4 of GXB_RO x8 1 instance Channels 0 3 and 5 of GXB_LO0 and channels 0 2 of GXB_L1 Channel 4 of GXB_LO Interfaces and Signal Descriptions Send Feedback Altera Corporation UG 01105_avmm 4 28 Channel Placement in Arria V Devices 2014 12 15 For more comprehensive information about Arria V transceivers refer to the Transceiver Banks section in the Transceiver Architecture in Arria V Dev
151. n MM to PCI Express Read Completions The PCI Express Avalon MM bridge converts read response data from Application Layer Avalon MM slaves to PCI Express completion packets and sends them to the Transaction Layer A single read request may produce multiple completion packets based on the Maximum payload size and the size of the received read request For example if the read is 512 bytes but the Maximum payload size 128 bytes the bridge produces four completion packets of 128 bytes each The bridge does not generate out of order completions even to different BARs You can specify the Maximum payload size parameter on the Device tab under the PCI Express PCI Capabilities heading in the parameter editor Related Information Device Capabilities PCI Express to Avalon MM Address Translation for 32 Bit Bridge The PCI Express Avalon MM bridge translates the system level physical addresses typically up to 64 bits to the significantly smaller addresses required by the Application Layer s Avalon MM slave components Note Starting with the 13 0 version of the Quartus II software the PCI Express to Avalon MM bridge supports both 32 and 64 bit addresses If you select 64 bit addressing the bridge does not perform address translation It drives the addresses specified to the interconnect fabric You can limit the number of address bits used by Avalon MM slave components to the actual size required by specifying the address size in the Avalon MM slave com
152. n in PCle Specification 0x000 0x03C PCI Header Type 0 Configuration Registers Type 0 Configuration Space Header 0x000 0x03C PCI Header Type 1 Configuration Registers Type 1 Configuration Space Header 0x040 0x04C Reserved N A 0x050 0x05C MSI Capability Structure MSI Capability Structure 0x068 0x070 MSI X Capability Structure MSI X Capability Structure 0x070 0x074 Reserved N A 0x078 0x07C Power Management Capability Structure PCI Power Management Capability Structure 0x080 0x0B8 PCI Express Capability Structure PCI Express Capability Structure Ox0B8 0x0FC Reserved N A 0x094 0x0FF Root Port N A 0x100 0x16C Virtual Channel Capability Structure Virtual Channel Capability Reserved 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the appli
153. n transaction e A 64 bit memory transaction in which the 32 MSBs of an address are set to 0 e A memory or I O transaction for which there is no BAR match e A memory transaction when the Memory Space Enable bit bit 1 of the PCI Command register at Configuration Space offset 0x4 is set to 0 e A poisoned configuration write request cfgWr0 Error Handling Altera Corporation J send Feedback 8 4 Transaction Layer Errors UG 01105_avmm 2014 12 15 a In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer If the TLP is a non posted request the Hard IP block generates a completion with Unsupported Request status Unsupported Requests for Root Port Completion timeout Uncorrectable fatal Uncorrectable non fatal This error occurs whenever a component receives an Unsupported Request including e Unsupported message e A Type 0 Configuration Request TLP e A 64 bit memory transaction which the 32 MSBs of an address are set to 0 e A memory transaction that does not match the address range defined by the Base and Limit Address registers This error occurs when a request originating from the Application Layer does not generate a corresponding completion TLP within the established time It is the responsibility of the Application Layer logic to provide the completion timeout mechanism The completion timeout should be reported from the Transaction Layer using t
154. nalTap II Embedded Logic Analyzer Altera Corporation Interfaces and Signal Descriptions GJ Send Feedback UG 01105_avmm 2014 12 15 PIPE Interface Signals 4 29 Table 4 16 PIPE Interface Signals In the following table signals that include lane number 0 also exist for other lanes Direction eserntion OO Ceara tee Output Transmit data lt n gt 2 symbols on lane lt n gt This bus transmits data on lane lt n gt pada alt Output Transmit data control lt n gt This signal serves as the control bit for txdata lt n gt txdetectrx0 Output Transmit detect receive lt n gt This signal tells the PHY layer to start a receive detection operation or to begin loopback txelecidle0 Output Transmit electrical idle lt n gt This signal forces the TX output to electrical idle txcomp10 Output Transmit compliance lt n gt This signal forces the running disparity to negative in Compliance Mode negative COM character rxpolarity0 Output Receive polarity lt n gt This signal instructs the PHY layer to invert the polarity of the 8B 10B receiver decoding block powerdown0 1 0 Output Power down lt n gt This signal requests the PHY to change its power state to the specified state PO POs P1 or P2 ee we Output Transmit de emphasis selection The Arria V Hard IP for PCI Express sets the value for this signal based on the indication received from the other end of the li
155. nced Error Reporting Capability 0x838 0xFFF Reserved N A 0x000 Device ID Vendor ID Type 0 Configuration Space Header Type 1 Configuration Space Header 0x004 Status Command Type 0 Configuration Space Header Type 1 Configuration Space Header 0x008 Class Code Revision ID Type 0 Configuration Space Header Type 1 Configuration Space Header 0x00C BIST Header Type Primary Latency Timer Type 0 Configuration Space Header Sane Type 1 Configuration Space Header 0x010 Base Address 0 Base Address Registers 0x014 Base Address 1 Base Address Registers Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Correspondence between Configuration Space Registers and the PCle Specification 5 3 Byte Address Hard IP Configuration Space Register Corresponding Section in PCle Specification 0x018 Base Address 2 Base Address Registers Secondary Latency Timer Subordinate Bus Secondary Latency Timer Type 1 Number Secondary Bus Number Primary Configuration Space Header Primary Bus Number Bus Number 0x01C Base Address 3 Base Address Registers Secondary Status I O Limit I O Base Secondary Status Register Type 1 Configuration Space Header 0x020 Base Address 4 Base Address Registers Memory Limit Memory Base Type 1 Configuration Space Header 0x024 Base Address 5 Base Address Registers Prefetchable Memory Limit Prefetchable Prefetchable Memory Limit Pref
156. nd 5 giga transfers per second for Gen2 This table provides bandwidths for a single transmit TX or receive RX channel The numbers double for duplex operation Gen1 and Gen2 use 8B 10B encoding which introduces a 20 overhead Link Width in Gigabits Per Second Gbps PCI Express Gen1 2 4 8 16 2 5 Gbps PCI Express Gen2 4 8 16 N A 5 0 Gbps 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134
157. nk during the Training Sequences TS You do not need to change this value rxdata0 7 0 Input __ Receive data lt n gt 2 symbols on lane lt n gt This bus receives data on lane lt n gt rxdatako Input Receive data gt n gt This bus receives data on lane lt n gt rxvaliao Input _ Receive valid lt n gt This signal indicates symbol lock and valid data on rxdata lt n gt and rxdatak lt n gt phystatuso Input PHY status lt n gt This signal communicates completion of several PHY requests Interfaces and Signal Descriptions Altera Corporation G Send Feedback 4 30 PIPE Interface Signals UG 01105_avmm 2014 12 15 O Sigal O Direction Deseripton O O eidleinfersel0 2 0 Output Electrical idle entry inference mechanism selection The following encodings are defined e 3 bOxx Electrical Idle Inference not required in current LTSSM state e 3 b100 Absence of COM SKP Ordered Set in the 128 us window for Gen1 or Gen2 e 3 b101 Absence of TS1 TS2 Ordered Set in a 1280 UI interval for Genl or Gen2 e 3 b110 Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2 e 3 b111 Absence of Electrical idle exit in 128 us window for Genl rxelecidled cd Input Receive electrical idle lt n gt When asserted indicates detection of an electrical idle rxstatus0 2 0 Input Receive status lt n gt This signal encodes receive status and error codes
158. nk partner Avalon MM processors or both 0x2000 0x2FFF Root Port request registers An embedded processor such as the Nios II processor programs these registers to send the data for Configuration TLPs I O TLPs single dword Memory Read and Write requests and receive interrupts from an Endpoint 0x3000 0x3FFF Registers typically intended for access by Avalon MM processors only Provides host access to selected Configuration Space and status registers Note The data returned for a read issued to any undefined address in this range is unpredictable The following table lists the complete address map for the PCI Express Avalon MM bridge registers Note In the following table the text in green are links to the detailed register description Table 5 12 PCI Express Avalon MM Bridge Register Map 0x0040 Avalon MM to PCI Express Interrupt Status Register 0x0050 Avalon MM to PCI Express Interrupt Status Enable Register 0x0800 0x081F PCI Express to Avalon MM Mailbox Registers 0x0900 x091F Avalon MM to PCI Express Mailbox Registers 0x1000 0x1FFF 0x2000 0x2FFF Avalon MM to PCI Express Address Translation Table Root Port TLP Data Registers 0x3060 Avalon MM to PCI Express Interrupt Status Registers for Root Ports 0x3060 PCI Express to Avalon MM Interrupt Status Register for Endpoints Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 Aval
159. nless MSI or MSI X interrupts are enabled Remains asserted until the device driver clears the pending request Intx ck_o Output This signal is the acknowledge for Int xReq_i It is asserted for at least one cycle either when either of the following events occur e The Assert_INTA message TLP has been transmitted in response to the assertion of the IntxReq_i e The Deassert_INTA message TLP has been transmitted in response to the deassertion of the Int xReq_i signal Refer to the timing diagrams below The following figure illustrates interrupt timing for the legacy interface In this figure the assertion of IntxReq_i instructs the Hard IP for PCI Express to send an Assert_INTA message TLP Figure 4 3 Legacy Interrupt Assertion dk LJ LS LI LI LI o IntxReq_i i IntAck_o bE j The following figure illustrates the timing for deassertion of legacy interrupts The assertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message Altera Corporation Interfaces and Signal Descriptions L3 Send Feedback UG 01105_avmm 2014 12 15 Physical Layer Interface Signals 4 15 Figure 4 4 Legacy Interrupt Deassertion ck IntxReq_i IntAck_o LILI LI LE LS LILI Lee L M S Physical Layer Interface Signals Altera provides an integrated solution with the Transaction Data Link and Physical Layers The IP Parameter Editor generates a SERDES variation file l
160. of 1 cycle is possible If no other delays are added to the read valid latency the resulting delay corresponds to a readyLa tency of 2 Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 2014 12 15 Hard IP Status Extension 4 19 Table 4 11 Mapping Between tl_cfg_sts and Configuration Space Registers 52 49 Device Status Register 3 0 Records the following errors Bit 3 unsupported request detected Bit 2 fatal error detected Bit 1 non fatal error detected Bit 0 correctable error detected 48 Slot Status Register 8 Data Link Layer state changed 47 Slot Status Register 4 Command completed The hot plug controller completed a command Note For Root Ports you enable the Slot register by turning on Use Slot Power Register in the parameter editor When enabled access to Command Completed Interrupt Enable bit of the Slot Control register remains Read Write This bit should be hardwired to 1b 0 You should not write this bit 46 31 Link Status Register 15 0 Records the following link status informa tion Bit 15 link autonomous bandwidth status Bit 14 link bandwidth management status Bit 13 Data Link Layer link active Bit 12 Slot clock configuration Bit 11 Link Training Bit 10 Undefined Bits 9 4 Negotiated Link Width Bits 3 0 Link Speed 30 Link Status 2 Register 0 Current de emphasis level Interface
161. on MM to PCI Express Interrupt Registers 5 15 0x3070 INT X Interrupt Enable Register for Root Ports 0x3070 INT X Interrupt Enable Register for Endpoints 0x3 A00 0x3A1F Avalon MM to PCI Express Mailbox Registers 0x3B00 0x3B1F PCI Express to Avalon MM Mailbox Registers Host Avalon MM master access to selected Configuration Space and status registers 0x3C00 0x3C6C Avalon MM to PCI Express Interrupt Registers Avalon MM to PCI Express Interrupt Status Registers These registers contain the status of various signals in the PCI Express Avalon MM bridge logic and allow PCI Express interrupts to be asserted when enabled Only Root Complexes should access these registers however hardware does not prevent other Avalon MM masters from accessing them Table 5 13 Avalon MM to PCI Express Interrupt Status Register 0x0040 a n 31 24 Reserved 23 AZP_MAILEOX_ INT RWIC 1 when the A2P_MAILBOX7 is written to 22 AZP _MATEBOX INT RWIC 1 when the A2P_MAILBOX6 is written to 21 Be II INT RWIC 1 when the A2P_MAILBOXS is written to 20 AAE MATEBOX INI RWIC 1 when the A2P_MAILBOX4 is written to 19 Ba INE IO INT RWIC 1 when the A2P_MAILBOX3 is written to 18 A2P_MATLBOX_INT RWIC 1 when the A2P_MAILBOX2 is written to 17 BAU NEI INT RWIC 1 when the A2P_MAILBOX1 is written to 16 A2P_MAILBOX_INT RWIC 1 when the A2P_MAILBOX0 is written to Registers G
162. on MM to PCI Express mailbox 3 0x3A10 P2 MAILBOX4 RW Avalon MM to PCI Express mailbox 4 CAA A eee RW Avalon MM to PCI Express mailbox 5 0x3A18 22P MAILBOX6 RW Avalon MM to PCI Express mailbox 6 TAIC Per a teen RW ___ Avalon MM to PCI Express mailbox 7 Registers Altera Corporation G Send Feedback 5 22 Control Register Access CRA Avalon MM Slave Port UG 01105_avmm 2014 12 15 The PCI Express to Avalon MM Mailbox registers are read only at the addresses shown in the following table The Avalon MM processor reads these registers when the corresponding bit in the pcr Express to Avalon MM Interrupt Status register is set to 1 Table 5 22 PCI Express to Avalon MM Mailbox Registers 0x3B00 0x3B1F Address Access Description Mode Ox3B00 2A_MAILEOKO RO PCI Express to Avalon MM mailbox 0 0o BOA EE 29S Pees RO PCI Express to Avalon MM mailbox 1 0x3B08 P23 MAILBOX2 RO PCI Express to Avalon MM mailbox 2 OO BOCR E RO PCI Express to Avalon MM mailbox 3 0x3B10 P2A AILBOX4 RO PCI Express to Avalon MM mailbox 4 COBA P2A MAIES RO PCI Express to Avalon MM mailbox 5 0x3B18 P2A MAILBOX6 RO PCI Express to Avalon MM mailbox 6 OBICEI a on RO PCI Express to Avalon MM mailbox 7 Control Register Access CRA Avalon MM Slave Port Table 5 23 Configuration Space Register Descriptions For registers that are less than 32 bits the upper bits are unused 14 h3C00 cfg_dev_ctr1l
163. oooo CY oooooooo f0 joo Altera Corporation Interfaces and Signal Descriptions GJ Send Feedback UG 01105_avmm 2014 12 15 Configuration Space Register Access Configuration Space Register Access 4 21 The t1_cfg_ct1 signal is a multiplexed bus that contains the contents of Configuration Space registers as shown in the figure below Information stored in the Configuration Space is accessed in round robin order where t 1_cfg_add indicates which register is being accessed The following table shows the layout of configuration information that is multiplexed on t1_cfg_ct1l Figure 4 6 Multiplexed Configuration Register Information Available on tl_cfg_ctl Fields in blue are available only for Root Ports 31 24 23 16 15 87 0 cfg_dev_ctrl 15 0 cfg_dev_ctrl2 15 0 0 cfg_dev_ctrl 14 12 cfg_dev_ctrl 7 5 Max Read Req Size Max Payload 1 16 h0000 cfg_slot_ctrl 15 0 2 cfg_link_ctrl 15 0 cfg_link_ctrl2 15 0 3 8 h00 cfg_pgm_cmd 15 0 cfg_root_ctrl 7 0 4 cfg_sec_ctrl 15 0 cfg_secbus 7 0 cfg_subbus 7 0 5 cfg_msi_addr 11 0 cfg_io_bas 19 0 6 cfg_msi_addr 43 32 cfg_io_lim 19 0 7 8 h00 cfg_np_bas 11 0 cfg_np_lim 11 0 8 cfg_pr_bas 31 0 9 cfg_msi_addr 31 12 cfg_pr_bas 43 32 A cfg_pr_lim 31 0 B cfg_msi_addr 63 44 cfg_pr_lim 43 32 C cfg_pmcsr 31 0 D cfg_msixcsr 15 09 cfg_msicsr 15 0 E bates th cfg_tcvcmap
164. ore information about error handling refer to Error Signaling and Logging in Section 6 2 of the PCI Express Base Specification ECRC on the RX Path When the ECRC generation option is turned on errors are detected when receiving TLPs with a bad ECRC If the ECRC generation option is turned off no error detection occurs If the ECRC forwarding option is turned on the ECRC value is forwarded to the Application Layer with the TLP If the ECRC forwarding option is turned off the ECRC value is not forwarded Altera Corporation Optional Features GJ Send Feedback UG 01105 2014 1 a ECRC on the TX Path 11 3 Table 11 2 ECRC Operation on RX Path ECRC Forwarding ECRC Check Enable ECRC Status Ee TLP Forward to Application Layer 5 none Forwarded No good No Forwarded without its ECRC bad No Forwarded without its ECRC No none No Forwarded Yes good No Forwarded without its ECRC bad Yes Not forwarded none No Forwarded No good No Forwarded with its ECRC bad No Forwarded with its ECRC Yes none No Forwarded Yes good No Forwarded with its ECRC bad Yes Not forwarded ECRC on the TX Path When the ECRC generation option is on the TX path generates ECRC If you turn on ECRC forwarding the ECRC value is forwarded with the TLP The following table summarizes the TX ECRC generation and forwarding All unspecified cases are unsupported and the behavior of the Hard IP is unknown In this table
165. place the base address of each BAR at 0x0000_0000 The following figure illustrates the optimized address map Figure 9 8 Optimized Address Map System Contents Address Map I Clock Settings Project Settings Instance Parameters System Inspector HDL Example Generation PCle Rxm_BARO PCle Rxm_BAR2 PCle Rxm_BAR4 Offchip_Data_Mem avl O0x0000_0000 OxOfff_ftTf PCle Cra 0x0000_0000 0x0000_3 Quick_Data_Mem s1 0x0000_0000 0x000 Instruction_Mem s1 Nios2 jtag_debug_module i Nios2 instruction_master 0x1002_ff fT 000 Figure 9 9 Reduced Address Bits for BAR2 and BAR4 The following figure shows the number of address bits required when the smaller memories accessed by BAR2 and BAR4 have a base address of 0x0000_0000 Base Address Registers F Base Address Registers BARO BAR1 BAR2 BAR3 BAR4 BARS ARO BARI BAR2 BARS BAR4 BARS TYPE 32 bit non prefetchable memory ly Type 32 bit non prefetchable memory ha Size Size For cases where the BAR Avalon MM RX master port connects to more than one Avalon MM slave assign the base addresses of the slaves sequentially and place the slaves in the smallest power of two sized address space possible Doing so minimizes the system address space used by the BAR Related Information Address Map Tab Qsys Avalon MM to PCl Express Address Translation Algorithm for 32 Bit Addressing Note The P
166. ponent parameter editor You can specify up to six BARs for address translation when you customize your Hard IP for PCI Express as described in Base Address Register BAR and Expansion ROM Settings When 32 bit addresses are specified the PCI Express Avalon MM bridge also translates Application Layer addresses to system level physical addresses as described in Avalon MM to PCI Express Address Translation Algorithm for 32 Bit Addressing The following figure provides a high level view of address translation in both directions IP Core Architecture Altera Corporation CJ Send Feedback UG 01105 9 14 PCI Express to Avalon MM Address Translation for 32 Bit Bridge esr eta Figure 9 5 Address Translation in TX and RX Directions For Endpoints Qsys Generated Endpoint with DMA Controller and On Chip RAM On Avalon MM Hard IP for PCI Express chip RAM Interconnect PCI Express Avalon MM Bridge Transaction Avalon MM to PCle Address Translation Data Link Address Translation Table Parameters and PHY TX Avalon MM PCle TLP Number of address pages 1 512 32 Bit Byte Address Size of address pages Address DMA PCle to Avalon MM Address Translation RX Avalon MM PCI Base Address Registers BAR PCle TLP PCle 32 Bit Byte Address BAR 0 5 Address Link BAR Type BAR Size E TX Avalon MM Slave m RX Avalon MM Master Note When configured as a Root Port a single
167. r Next Cap PTR Cap ID PCI Power Management Capability Structure 0x07C Data PM Control Status Bridge Extensions PCI Power Management Capability Power Management Status amp Control Structure 0x800 PCI Express Enhanced Capability Header Advanced Error Reporting Enhanced Capability Header 0x804 Uncorrectable Error Status Register Uncorrectable Error Status Register 0x808 Uncorrectable Error Mask Register Uncorrectable Error Mask Register 0x80C Uncorrectable Error Severity Register Uncorrectable Error Severity Register 0x810 Correctable Error Status Register Correctable Error Status Register 0x814 Correctable Error Mask Register Correctable Error Mask Register 0x818 Advanced Error Capabilities and Control Advanced Error Capabilities and Control Register Register 0x81C Header Log Register Header Log Register 0x82C Root Error Command Root Error Command Register 0x830 Root Error Status Root Error Status Register 0x834 Error Source Identification Register Correct Error Source Identification Register able Error Source ID Register Related Information PCI Express Base Specification 2 1 or 3 0 Altera Corporation Registers CJ Send Feedback UG 01105_avmm 2014 12 15 UG 01105_avmm 2014 12 15 Type 0 Configuration Space Registers Figure 5 1 Type 0 Configuration Space Registers Byte Address Offsets and Layout Type 0 Configuration Space Registers 5 5 Endpoints store configuration data in the Type 0 Configuration Space T
168. ration Create optional calibration status ports 4 gt nalog Features x Enable Analog controls Reconfiguration Features Enable channel PLL reconfiguration Enable PLL reconfiguration support block The Transceiver Reconfiguration Controller includes an Optional interface grouping parameter Transceiver banks include six channels For a x4 variant no special interface grouping is required because all 4 lanes and the TX PLL fit in one bank Note Although you must initially create a separate logical reconfiguration interface for each lane and TX PLL in your design when the Quartus II software compiles your design it reduces the original Altera Corporation Transceiver PHY IP Reconfiguration CJ Send Feedback UG 01105_avmm 2014 12 15 Transceiver Reconfiguration Controller Connectivity for Designs Using CvP 12 3 number of logical interfaces by merging them Allowing the Quartus II software to merge reconfi guration interfaces gives the Fitter more flexibility in placing transceiver channels Note You cannot use SignalTap to observe the reconfiguration interfaces Transceiver Reconfiguration Controller Connectivity for Designs Using CvP If your design meets the following criteria e It enables CvP e It includes an additional transceiver PHY that connect to the same Transceiver Reconfiguration Controller then you must connect the PCIe refc1k signal to the mgm
169. ration Registers GJ Send Feedback UG 01105_avmm Sy 2014 12 15 Avalon MM Mailbox Registers Fi Table 5 20 INT X Interrupt Enable Register for Endpoints 0x3070 SE SS 31 0 Papress To Avalorn MM When set to 1 enables the interrupt for eee Enap le the corresponding bit in the pcr Express to Avalon MM Interrupt Status register to cause the Avalon Interrupt signal cra_Irq_o to be asserted Only bits implemented in the pcr Express to Avalon MM Interrupt Status register are implemented in the Enable register Reserved bits cannot be set toa 1 Avalon MM Mailbox Registers A processor local to the interconnect fabric typically requires write access to a set of Avalon MM to PCI Express Mailbox registers and read only access to a set of PCI Express to Avalon MM Mailbox registers Eight mailbox registers are available The avalon MM to PCI Express Mailbox registers are writable at the addresses shown in the following table When the Avalon MM processor writes to one of these registers the corresponding bit in the Avalon MM to PCI Express Interrupt Status register is set to 1 Table 5 21 Avalon MM to PCI Express Mailbox Registers Ox3A00 0x3A1F a e E E 0x3A00 22P MAILBOX0 Avalon MM to PCI Express mailbox 0 TOA Renee ree RW Avalon MM to PCI Express mailbox 1 0x3A08 22 MAILBOX2 RW Avalon MM to PCI Express mailbox 2 TANC AP MATEOK RW Aval
170. re Comparison for all Hard IP for PCI Express IP Cores The table compares the features of the four Hard IP for PCI Express IP Cores Feature Avalon ST Interface Avalon MM Interface Avalon MM DMA IP Core License Free Free Free Native Endpoint Supported Supported Supported Legacy Endpoint Supported Not Supported Not Supported Not recommended for new designs Altera Corporation Datasheet CJ Send Feedback UG 01105_avmm 2014 12 15 Features 1 3 Feature Avalon ST Interface Avalon MM Interface Avalon MM DMA Root port Supported Supported Not Supported Genl x1 x2 x4 x8 x1 x2 x4 x8 x8 Gen2 x1 x2 x4 x1 x2 x4 x4 64 bit Application Supported Supported Not supported Layer interface 128 bit Application Supported Supported Supported Layer interface Transaction Layer e Memory Read Request e Memory Read Request e Memory Read Packet type TLP e Memory Read Request e Memory Write Request Request Locked I O Read Request e Memory Write e Memory Write Request Root Port only Request e I O Read Request e I O Write Request e Completion e I O Write Request Root Port only Message e Configuration Read e Configuration Read Completion with Request Root Port Request Root Port Data e Configuration Write e Configuration Write Request Root Port Request Root Port e Message Request e Completion Message e Message Request with e Completion with Data Data Payload e M
171. reclkout Cra 0x0000_0000 Ox0000_3TTT DUT _corecikout Cralrq a B dma 0 clk control_port_slave 0x0000_4000 0x0000_401F DUT_coreclkout irq clk P 0 read_master clk write master clk v B alt_xcvr_reconfig_0 mgmt_clk_clk reconfig_busy reconfig_mgmt Ox0000 OxO1tt clk_O reconfig_to_xcwr reconfig_from_xcwr m E pcie_reconfig_driver_0 DUT_corecikout reconfig_mgmt clk_0 hip_currentspeed reconfig_busy hip_status_drv wj onchip_memory2_0 clk1 s1 0x0020_0000 0x0020_0fff DUT_corecikout Altera Corporation Getting Started with the Avalon MM Arria V Hard IP for PCI Express GJ Send Feedback UG 01105_avmm 2014 12 15 Generating the Example Design 2 3 Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about how to use Qsys For an explanation of each Qsys menu item refer to About Qsys in Quartus II Help Related Information Creating a System with Qsys About Qsys Generating the Example Design Vv oA w On the Generate menu select Generate Testbench System The Generation dialog box appears Under Testbench System set the following options a For Create testbench Qsys system select Standard BFMs for standard Qsys interfaces b For Create testbench simulation model select Verilog You can retain the default values for all other parameters Click Generate After Qsys reports Generation Completed click Close 6 On the File menu
172. rria V GZ Avalon ST Interface for PCIe Solutions User Guide Arria 10 Avalon MM Interface for PCIe Solutions User Guide Arria 10 Avalon MM DMA Interface for PCIe Solutions User Guide Arria 10 Avalon ST Interface for PCIe Solutions User Guide Cyclone V Avalon MM Interface for PCIe Solutions User Guide Cyclone V Avalon ST Interface for PCIe Solutions User Guide IP Compiler for PCI Express User Guide Stratix V Avalon MM Interface for PCIe Solutions User Guide Stratix V Avalon ST Interface for PCIe Solutions User Guide Stratix V Avalon ST Interface with SR IOV for PCIe Solutions User Guide G Send Feedback Altera Corporation UG 01105_avmm 1 6 Configurations 2014 12 15 Configurations The Avalon MM Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers e Physical PHY including e Physical Media Attachment PMA e Physical Coding Sublayer PCS e Media Access Control MAC e Data Link Layer DL e Transaction Layer TL When configured as an Endpoint the Arria V Hard IP for PCI Express using the Avalon MM supports memory read and write requests and completions with or without data Figure 1 2 PCI Express Application with a Single Root Port and Endpoint The following figure shows a PCI Express link between two Arria V FPGAs One is configured as a Root Port and the other as an Endpoint Altera FPGA Altera FPGA PCle PCle Hard IP Hard IP PC
173. ry Bits Index table becomes High PCI Express address bits Table updates from control register port Space Indication PCle Address Q 1 SpQ 1 Completer Only Single Dword Endpoint The completer only single dword endpoint is intended for applications that use the PCI Express protocol to perform simple read and write register accesses from a host CPU The completer only single dword endpoint is a hard IP implementation available for Qsys systems and includes an Avalon MM interface to the Application Layer The Avalon MM interface connection in this variation is 32 bits wide This endpoint is not pipelined at any time a single request can be outstanding The completer only single dword endpoint supports the following requests IP Core Architecture Read and write requests of a single dword 32 bits from the Root Complex Completion with Completer Abort status generation for other types of non posted requests INTX or MSI support with one Avalon MM interrupt source Altera Corporation CJ Send Feedback UG 01105_avmm 9 20 RX Block 2014 12 15 Figure 9 11 Qsys Design Including Completer Only Single Dword Endpoint for PCI Express Completer Only Single DWord Endpoint Qsys Component to Host CPU Avalon MM Slave Bridge Avalon MM RX Block Avalon MM Master RX Hard IP PCle Link PCI Express for PCle Root Complex Int t londi TX Block Avalon MM
174. s Related Information e Generating the Example Design on page 2 3 e Creating a System with Qsys This document provides an introduction to Qsys Running Qsys 1 Choose Programs gt Altera gt Quartus II gt lt version_number gt Windows Start menu to run the Quartus II software Alternatively you can also use the Quartus II Web Edition software 2 On the File menu select New then Qsys System File 3 Open the ep_g1x4 qsys example design The following figure shows a Qsys system that includes the Transceiver Reconfiguration Controller and the Altera PCIe Reconfig Driver IP Cores The Transceiver Reconfiguration Controller performs dynamic reconfiguration of the analog transceiver settings to optimize signal quality You must include these components to the Qsys system to run successfully in hardware Figure 2 2 Qsys Avalon MM Design for PCle with Transceiver Reconfiguration Components System ep_g2x4 Path jesd204_0 use Connections Name Base End Clock Export IRQ v DUT exported npor pcie_av_hip_avmm_O_npor hip_ctrl pcie_av_hip_avmm_O_hip_ctrl Rxm_BARO DUT _corecikout Rxm_BAR2 DUT _corecikout Rxmirq IRQ 0 IRQ 15 DUT_coreclkout hip_status hip_currentspeed reconfig_to_xcwr reconfig_busy dut_reconfig_busy reconfig_from_xcvwr reconfig_clk_locked pcie_av_hip_avmm_0O_reconfig_clk_locked hip_serial pcie_av_hip_avmm_O_hip_serial hip_pipe pcie_av_hip_avmm_O_hip_pipe TXS 0x0000_0000 Ox001T_TTtt DUT _co
175. s no MSI message is sent for subsequent interrupts To avoid losing interrupts software must ensure that all interrupt sources are cleared for each MSI message received The following figure illustrates the RX master port propagating requests to the Application Layer and also shows simultaneous DMA read and write activity Altera Corporation Interfaces and Signal Descriptions GJ send Feedback UG 01105_avmm g A 2014 12 15 64 or 128 Bit Bursting TX Avalon MM Slave Signals 5 Figure 4 1 Simultaneous DMA Read DMA Write and Target Access RxmRead_o N RxmReadDataalid NANA W V AA RumReadData_i 63 0 A n RxmResetRequest_o RxmAddress_o 31 0 I MN 80000100 80000180 memvattequest_ LAA AVWA M RxmWrite_o AAN U RxmBurstCount_o 9 0 010 RxmByteEnable_o 7 0 i M MANY FF M FF ih Rxmlrq_i A J TxsWrite_i TxsWriteData_i 63 0 TxsBurstCount_i 9 0 K 001 080 TxsByteEnable_i 7 0 TusAddress_i 17 0 04000 Y o4os0 Y 04000 a ee ee ee ee ee TxsWaitRequest_o sma ee ie ie ie _ sie ee see TxsRead_i OOO a Y U V yV N LE oooo AACN OCO OOOO o AO J TxsReadDataValid_o TxsReadData_0 63 0 tt al bal ee ee AA peAa TxsChipSelect_i 64 or 128 Bit Bursting TX Avalon MM Slave Signals This optional Avalon MM bursting
176. s and Signal Descriptions G Send Feedback Altera Corporation UG 01105_avmm 4 20 Configuration Space Register Access Timing 2014 12 15 29 25 Status Register 15 11 Records the following 5 primary command status errors e Bit 15 detected parity error e Bit 14 signaled system error e Bit 13 received master abort e Bit 12 received target abort e Bit 11 signalled target abort 24 Secondary Status Register 8 Master data parity error 23 6 Root Status Register 17 0 Records the following PME status informa tion e Bit 17 PME pending e Bit 16 PME status e Bits 15 0 PME request ID 15 0 5 1 Secondary Status Register 15 11 Records the following 5 secondary command status errors e Bit 15 detected parity error e Bit 14 received system error e Bit 13 received master abort e Bit 12 received target abort e Bit 11 signalled target abort 0 Secondary Status Register 8 Master Data Parity Error Related Information PCI Express Card Electromechanical Specification 2 0 Configuration Space Register Access Timing Figure 4 5 tl_cfg_ctl Timing The following figure shows typical traffic on the t1_cfg_ct1 bus The t1_cfg_add index increments on the rising edge of the p1d_c1k The address specifies which Configuration Space register data value is being driven onto t1_cfg_ctl pld_clk S iaol 2 3 a s oe 7 fs fo Ja Yu Ws lo a ew ec Yo fe I tLefg_ctif31 0 00 00 00 7F J oooo
177. s of data and system failure are considered uncorrectable and fatal Software must determine how to handle such errors whether to reset the link or implement other means to minimize the problem Related Information PCI Express Base Specification 2 1 and 3 0 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of RYA 101 Innovation Drive San Jose CA 95134 7 UG 01105_avmm 8 2 Physical Layer Errors 2014 12 15 Physical Layer Errors Table 8 2 Errors
178. s testbench Then repeat Steps 3 6 In Altera s testbenches the PCIe core is typically called the DUT device under test The Application Layer logic is typically called APPS Related Information e Parameter Settings on page 3 1 e Getting Started with the Avalon MM Arria V Hard IP for PCI Express e All Development Kits Altera Corporation Datasheet G send Feedback Getting Started with the Avalon MM Arria V Hard IP for PCI Express 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback You can download a design example for the Avalon MM Arria V Hard IP for PCI Express from the lt install_dir gt ip altera altera_pcie altera_pcie lt dev gt _hip_avmm example_designs directory This walkthrough uses the a Gen1 x4 Endpoint ep_g1x4 qsys The design examples contain the following components e Avalon MM Arria V Hard IP for PCI Express IP core e On Chip memory e DMA controller e Transceiver Reconfiguration Controller e Two Avalon MM pipeline bridges Figure 2 1 Qsys Generated Endpoint Qsys System Design for PCI Express Avalon MM Hard IP for PCI Express g PCI Transaction d a S Express Data Link 4 Avalon MM and PHY E Bridge Layers Transceiver Reconfiguration Controller 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and r
179. s that are coming from the DMA component Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared memory Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory Data comparison and report of any mismatch Related Information Simulating Altera Designs Running A Gate Level Simulation The PCI Express testbenches run simulations at the register transfer level RTL However it is possible to create you own gate level simulations Contact your Altera Sales Representative for instructions and an example that illustrate how to create a gate level simulation from the RTL testbench Simulating the Single DWord Design You can use the same testbench to simulate the Completer Only Single Dword IP core by changing the settings in the driver file 1 a Altera Corporation In a terminal window change to the lt project_dir gt lt variant gt testbench lt variant gt _tb simulation submodules directory Open altpcietb_bfm_driver_avmm v in your text editor To enable target memory tests and specify the completer only single dword variant specify the following parameters a parameter RUN_TGT_MEM_TST 1 b parameter RUN_DMA_MEM_TST 0 C parameter AVALON_MM_LITE 1 Change to the lt project_dir gt variant testbench mentor directory Start the ModelSim simulator To run the simulation type the following commands in a
180. s the interrupt register at power up The setting does not affect run time configuration of the interrupt enable register For the Avalon MM interface with DMA this value must be Off Altera Corporation Parameter Settings CJ Send Feedback UG 01105_avmm 2014 12 15 Avalon Memory Mapped System Settings 3 11 Enable hard IP status bus On Off When you turn this option on your top level variant includes the signals necessary to connect to the Transceiver Reconfiguration Controller IP Core your variant including e Link status signals e ECC error signals e TX and RX parity error signals e Completion header and data signals indicating the total number of Completion TLPs currently stored in the RX buffer Altera recommends that you include the Transceiver Reconfiguration Controller IP Core in your design to improve signal quality Enable hard IP status extension bus On Off When you turn this option on your top level variant includes signals that are useful for debugging including link training and status error and the Transaction Layer Configuration Space signals The top level variant also includes signals showing the start and end of packets error ready and BAR signals for the native Avalon ST interface that connects to the Transaction Layer The following signals are included in the top level variant e Link status signals e ECC error signals e Transaction Layer Configuration Space signals
181. s_Read must be deasserted when TxsWaitrequest_o is deasserted Interfaces and Signal Descriptions Send Feedback Altera Corporation UG 01105_avmm 4 8 Clock Signals 2014 12 15 Clock Signals Table 4 4 Clock Signals O Sigal i Description O O TEELE Input Reference clock for the IP core It must have the frequency specified under the System Settings heading in the parameter editor This is a dedicated free running input clock to the dedicated REFCLK pin If your design meets the following criteria e Enables CvP e Includes an additional transceiver PHY connected to the same Transceiver Reconfiguration Controller then you must connect refclk to the mgmt_c1k_c1k signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY In addition if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA they all must share the mgmt _clk_c1lk signal Borer rout Output This is a fixed frequency clock used by the Data Link and Transaction Layers To meet PCI Express link bandwidth constraints this clock has minimum frequency requirements as listed in Application Layer Clock Frequency for All Combination of Link Width Data Rate and Application Layer Interface Width in the Reset and Clocks chapter Related Information Clocks on page 6 5 Reset Signals Refer to Reset and Clocks for more information about the reset sequence and a
182. services JNO TS RYA 101 Innovation Drive San Jose CA 95134 6 2 Figure 6 1 Reset Controller Block Diagram Altera Corporation Reset and Clocks mgmt_rst_reset reconfig_clk Chaining DMA APPs Transceiver Reconfiguration Controller reconfig_busy mgmt_rst_reset gt reconfig_xcvr_clk pcie_reconfig_ al driver_0 reconfig_busy reconfig_xcvr_rst reconfig_xcvr_clk UG 01105_avmm 2014 12 15 Hard IP for PCI Express altpcie_dev_hip lt if gt hwtd v altpcie_ lt dev gt _hip_256_pipentb v Transceiver Hard Reset Logic Soft Reset Controller altpcie_rs_serdes v tx_digitalrst rx_analogrst ak rx_digitalrst SERDES Configuration Space Sticky Registers Configuration Space Non Sticky Registers Datapath State Machines of Hard IP Core coreclkout_hip Reset and Clocks GJ Send Feedback UG 01105_avmm 2014 12 15 Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6 3 Reset Sequence for Hard IP for PCI Express IP Core and Application Layer Figure 6 2 Hard IP for PCI Express and Application Logic Reset Sequence Your Application Layer can instantiate a module similar to the one in this figure to generate app_rstn which resets the Application Layer logic pin_perst pld_clk_inuse 32 cycles crst srst serdes_pll_locked reset_status b 3
183. set Value 31 16 Reserved 0x0000 RO 15 8 CVP_NUMCLKS 0x00 RW This is the number of clocks to send for every CvP data write Set this field to one of the values below depending on your configura tion image e 0x01 for uncompressed and unencrypted images e 0x04 for uncompressed and encrypted images e 0x08 for all compressed images 7 3 Reserved 0x0 RO 2 CVP_FULLCONFIG Request that the FPGA control block bO RW reconfigure the entire FPGA including the Arria V Hard IP for PCI Express bring the PCIe link down Registers Altera Corporation G Send Feedback UG 01105_avmm 2014 12 15 e Register Description Reset Value 1 b0 HIP_CLK_SEL Selects between PMA and fabric clock when uUSsER_ MODE 1 and PLD_CORE_READY 1 The following encodings are defined e 1 Selects internal clock from PMA which is required for cvP_ MODE e 0 Selects the clock from soft logic fabric This setting should only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock 5 12 CvP Registers To ensure that there is no clock switching during CvP you should only change this value when the Hard IP for PCI Express has been idle for 10 us and wait 10 us after changing this value before resuming activity 0 CVP_MODE Controls whether the IP core is in cvP_MODE or normal 1 b0 RW mode The following encodings are defined
184. signed to enable straight forward enforcement by processor software The following figure illustrates accesses to the Avalon MM control and status registers from the Host CPU and PCI Express link Figure 5 9 Accesses to the Avalon MM Bridge Control and Status Register Qsys Generated Endpoint Altera FPGA Interconnect Avalon MM Hard IP for PCI Express PCI Express Avalon MM Bridge Transaction Data Link Control Register Access CRA and PHY Avalon MM Slave Control and Status Registers 0x0000 Ox0FFF PCle processors RX PCle Host Avalon MM PCle TLP Address Link CPU 32 Bit Byte Address 0x1000 0x1FFF Addr translation 0x2000 0x2FFF Root Port TLP Data 0x3000 0x3FFF Avalon MM processors Registers Altera Corporation G Send Feedback UG 01105_avmm 5 14 64 or 128 Bit Avalon MM Bridge Register Descriptions 2014 12 15 The following table describes the four subregions Table 5 11 Avalon MM Control and Status Register Address Spaces AddressRange Address Space Usage 0x0000 0x0FFF 0x1000 0x1FFF Registers typically intended for access by PCI Express link partner only This includes PCI Express interrupt enable controls write access to the PCI Express Avalon MM bridge mailbox registers and read access to Avalon MM to PCI Express mailbox registers Avalon MM to PCI Express address translation tables Depending on the system design these may be accessed by the PCI Express li
185. ss of the packet e cfg_tcvcmap 2 0 Mapping for TCO always 0 e cfg_tcvcmap 5 3 Mapping for TC e cfg_tcvcmap 8 6 Mapping for TC2 e cfg_tcvcmap 11 9 Mapping for TC3 e cfg_tcvemap 14 12 Mapping for TC4 e cfg_tcvcmap 17 15 Mapping for TCS e cfg_tcvcmap 20 18 Mapping for TC6 e cfg_tcvcmap 23 21 Mapping for TC7 cfg_msi_data 16 Output cfg_msi_data 15 0 is message data for MSI efg_busdev 13 Output Bus Device Number captured by or programmed in the Hard IP Figure 4 7 Configuration MSI Control Status Register Field and Bit Map 15 9 8 7 6 4 3 1 0 mask 64 Dit MSI reserved ais address multiple message enable multiple message capable capability a enable capability Table 4 13 Configuration MSI Control Status Register Field Descriptions a 15 9 Reserved N A 8 mask capability Per vector masking capable This bit is hardwired to 0 because the function does not support the optional MSI per vector masking using the Mask_Bits and Pending_Bits registers defined in the PCI Local Bus Specification Per vector masking can be implemented using Application Layer registers 7 64 bit address 64 bit address capable 7 eee e 1 function capable of sending a 64 bit message address e 0 function not capable of sending a 64 bit message address Altera Corporation Interfaces and Signal Descriptions CJ Send Feedback UG 01105_avmm 20
186. st for transmission of an ACK NAK DLLP TX Arbitration This block arbitrates transactions prioritizing in the following order e Initialize FC Data Link Layer packet e ACK NAK DLLP high priority e Update FC DLLP high priority e PM DLLP e Retry buffer TLP e TLP e Update FC DLLP low priority e ACK NAK FC DLLP low priority Physical Layer The Physical Layer is the lowest level of the PCI Express protocol stack It is the layer closest to the serial link It encodes and transmits packets across a link and accepts and decodes received packets The Physical Layer connects to the link through a high speed SERDES interface running at 2 5 Gbps for Gen1 implementations and a5 2 5 or 5 0 Gbps for Gen2 implementations The Physical Layer is responsible for the following actions Altera Corporation Initializing the link Scrambling descrambling and 8B 10B encoding decoding for 2 5 Gbps Gen1 and 5 0 Gbps Gen2 per lane Serializing and deserializing data Operating the PIPE 3 0 Interface Implementing auto speed negotiation Gen2 and Gen3 Transmitting and decoding the training sequence Providing hardware autonomous speed control Implementing auto lane reversal IP Core Architecture GJ Send Feedback UG 01105_avmm 2014 12 15 Physical Layer 9 7 Figure 9 3 Physical Layer Architecture To Data Link Layer To Link lt q _
187. stem functionality resulting in a completion with the abort status set An example of an invalid request is one with an incorrect address IP Core Architecture Altera Corporation CJ Send Feedback 9 12 PCI Express to Avalon MM Read Completions UG 01105_avmm 2014 12 15 PCI Express to Avalon MM Read Completions The PCI Express Avalon MM bridge returns read completion packets to the initiating Avalon MM master in the issuing order The bridge supports multiple and out of order completion packets PCI Express to Avalon MM Downstream Write Requests The PCI Express Avalon MM bridge receives PCI Express write requests it converts them to burst write requests before sending them to the interconnect fabric For Endpoints the bridge translates the PCI Express address to the Avalon MM address space based on the BAR hit information and on address translation table values configured during the IP core parameterization For Root Ports all requests are forwarded to a single RX Avalon MM master that drives them to the interconnect fabric Malformed write packets are dropped and therefore do not appear on the Avalon MM interface For downstream write and read requests if more than one byte enable is asserted the byte lanes must be adjacent In addition the byte enables must be aligned to the size of the read or write request As an example the following table lists the byte enables for 32 bit data Table 9 2 Valid Byte Enable Configurations
188. systems do not have a minimum assertion time for pin_perstn 5 Wait for thereset_status output to be deasserted 6 Deassert the reset output to the Application Layer Ww Related Information Reset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 6 3 Altera Corporation Design Implementation TE Send Feedback Optional Features 2014 12 15 UG 01105_avmm amp Subscribe CJ Send Feedback Configuration via Protocol CvP The Hard IP for PCI Express architecture has an option to configure the FPGA and initialize the PCI Express link In prior devices a single Program Object File pof programmed the I O ring and FPGA fabric before the PCIe link training and enumeration began The pof file is divided into two parts e The I O bitstream contains the data to program the I O ring the Hard IP for PCI Express and other elements that are considered part of the periphery image e The core bitstream contains the data to program the FPGA fabric When you select the CvP design flow the I O ring and PCI Express link are programmed first allowing the PCI Express link to reach the LO state and begin operation independently before the rest of the core is programmed After the PCI Express link is established it can be used to program the rest of the device The following figure shows the blocks that implement CvP Figure 11 1 CvP in Arria V Devices Host CPU Active Serial Fast Passive Para
189. t variation gt _serdes v or vhd in addition to the Hard IP variation file lt variation gt v or vhd The SERDES entity is included in the library files for PCI Express Transceiver Reconfiguration Dynamic reconfiguration compensates for variations due to process voltage and temperature PVT Among the analog settings that you can reconfigure are Vop pre emphasis and equalization You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog settings For Gen2 operation you must turn on Enable duty cycle calibration in the Transceiver Reconfi guration Controller GUI Arria V devices require duty cycle calibration DCD for data rates greater than 4 9152 Gbps For more information about instantiating the Altera Transceiver Reconfiguration Controller IP core refer to Hard IP Reconfiguration Table 4 8 Transceiver Control Signals In this table lt n gt is the number of interfaces required reconfig_from_ Output Reconfiguration signals to the Transceiver Reconfiguration xcevr lt n gt 46 1 0 Controller reconfig_to_xcvr lt n gt Input Reconfiguration signals from the Transceiver Reconfiguration 70 1 0 Controller busy_xcvr_reconfig Input When asserted indicates that the a reconfiguration operation is in progress reconfig clk locked Output When asserted indicates that the PLL that provides the fixed clock required for transceiver initialization is locked The App
190. t when any received TLP is poisoned Master data parity error status register bit 8 This bit is set when the command register parity enable bit is set and one of the following conditions is true e The poisoned bit is set during the transmission of a Write Request TLP e The poisoned bit is set on a received completion TLP Poisoned packets received by the Hard IP block are passed to the Application Layer Poisoned transmit TLPs are similarly sent to the link Related Information PCI Express Base Specification 2 1 and 3 0 Uncorrectable and Correctable Error Status Bits The following section is reprinted with the permission of PCI SIG Copyright 2010 PCI SIG Figure 8 1 Uncorrectable Error Status Register The default value of all the bits of this register is 0 An error status bit that is set indicates that the error condition it represents has been detected Software may clear the error status by writing a 1 to the appropriate bit 31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 65 4 3 1 0 Rsvd Rsvd Rsvd A A AAAA A A A TLP Prefix Blocked Error Status AtomicOp Egress Blocked Status MC Blocked TLP Status Uncorrectable Internal Error Status ACS Violation Status Unsupported Request Error Status ECRC Error Status Malformed TLP Status Receiver Overflow Status Unexpected Completion Status Completer Abort Status Completion Timeout Status Flow Control Protocol Status Poisoned TLP Status Surprise Down Error Status Data L
191. t_c1k_c1k signal of the Transceiver Reconfigu ration Controller and the additional transceiver PHY In addition if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA they all must share the mgmt_clk_clk signal For more information about using the Transceiver Reconfiguration Controller refer to the Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY IP Core User Guide Related Information Altera Transceiver PHY IP Core User Guide Transceiver PHY IP Reconfiguration Altera Corporation G Send Feedback Debugging 1 3 2014 12 15 UG 01105_avmm amp Subscribe cJ Send Feedback As you bring up your PCI Express system you may face a number of issues related to FPGA configura tion link training BIOS enumeration data transfer and so on This chapter suggests some strategies to resolve the common issues that occur during hardware bring up Hardware Bring Up Issues Typically PCI Express hardware bring up involves the following steps 1 System reset 2 Link training 3 BIOS enumeration The following sections describe how to debug the hardware bring up flow Altera recommends a systematic approach to diagnosing bring up issues as illustrated in the following figure Figure 13 1 Debugging Link Training Issues Does Link Successful system reset gt Tain Yes 05 BI0S Yes Check oe Correctly Enumeration pace Check
192. ties Table 3 7 MSI and MSI X Capabilities MSI messages 1 2 4 8 16 Specifies the number of messages the Application Layer can requested request Sets the value of the Multiple Message Capable field of the Message Control register 0x050 31 16 MSI X Capabilities Implement MSI X On Off When On enables the MSI X functionality Bit Range Altera Corporation Parameter Settings CJ Send Feedback UG 01105_avmm 2014 12 15 MSI and MSI X Capabilities 3 7 Table size 10 0 System software reads this field to determine the MSI X Table size lt n gt which is encoded as lt n 1 gt For example a returned value of 2047 indicates a table size of 2048 This field is read only Legal range is 0 2047 211 Address offset 0x068 26 16 Table Offset 31 0 Points to the base of the MSI X Table The lower 3 bits of the table BAR indicator BIR are set to zero by software to form a 32 bit qword aligned offset This field is read only Table BAR Indicator 2 0 Specifies which one of a function s BARs located beginning at 0x10 in Configuration Space is used to map the MSI X table into memory space This field is read only Legal range is 0 5 Pending Bit Array PBA Offset 31 0 Used as an offset from the address contained in one of the function s Base Address registers to point to the base of the MSI X PBA The lower 3 bits of the PBA BIR are set to zero by software to form a
193. tl_cfg_add 3 0 tx_cfg_sts 52 0 tx_st_ready tx_out0kn gt 10 rx_in0kn gt 10 txdata0 7 0 txdatak0 txdetectrx0 txelectidle0 txcompl0 rxpolarityO powerdown0 1 0 tx_deemph0 rxdata0 7 0 rxdatak0 rxvalid0 phystatusO eidleinfersel0 2 0 rxelectidle0 rxstatus0 2 0 sim_Itssmstate 4 0 sim_pipe_rate0 1 0 sim_pipe_pdk_in txswingO txmarginO 2 0 test_in 31 0 simu_mode_pipe hip_currentspeed 1 0 lt _ UG 01105_avmm 2014 12 15 Multiple MSI MSI X Transceiver Reconfiguration Hard IP Status Extension 1 Bit Serial 8 Bit PIPE PIPE Interface Simulation Only Test Note Signals listed for BARO are the same as those for BARI BAR5 when those BARs are enabled in the parameter editor Variations using the Avalon MM interface implement the Avalon MM protocol described in the Avalon Interface Specifications Refer to this specification for information about the Avalon MM protocol including timing diagrams Related Information Avalon Interface Specifications 32 Bit Non Bursting Avalon MM Control Register Access CRA Slave Signals The optional CRA port for the full featured IP core allows upstream PCI Express devices and external Avalon MM masters to access internal control and status registers Altera Corporation Interfaces and Signal Descriptions GJ Send Feedback UG 01105_avmm 2014 12 15 RX Avalon MM Master Signals 4 3 Table 4 1
194. tocol Although there is inevitable overlap between these two purposes this document should be used in conjunction with an understanding of the PCI Express Base Specification Note This release provides separate user guides for the different variants The Related Information provides links to all versions Related Information e V Series Avalon MM DMA Interface for PCIe Solutions User Guide e Arria V Avalon MM Interface for PCIe Solutions User Guide e Arria V Avalon ST Interface for PCIe Solutions User Guide Altera Corporation Datasheet G send Feedback UG 01105_avmm 2014 12 15 Release Information 1 5 Release Information Table 1 3 Hard IP for PCI Express Release Information ee Oo oooi O Version 14 1 Release Date December 2014 Ordering Codes No ordering code is required Product IDs There are no encrypted files for the Arria V Hard IP Vendor ID license for PCI Express The Product ID and Vendor ID are not required because this IP core does not require a Device Family Support Table 1 4 Device Family Support Arria V Other device families in production designs Final The IP core is verified with final timing models The IP core meets all functional and timing requirements for the device family and can be used Refer to the Related Information below for other device families Datasheet Related Information Arria V GZ Avalon MM Interface for PCIe Solutions User Guide A
195. topology to initialize and update the FPGA fabric e Enables dynamic core updates without requiring a system power down e Improves security for the proprietary core bitstream e Reduces system costs by reducing the size of the flash device to store the pof e Facilitates hardware acceleration e May reduce system size because a single CvP link can be used to configure multiple FPGAs Table 11 1 CvP Support CvP is available for the following configurations Gen1 128 bit interface to Application Layer Supported Gen2 128 bit interface to Application Layer Contact your Altera sales representative Note You cannot use dynamic transceiver reconfiguration for the transceiver channels in the CvP enabled Hard IP when CvP is enabled Related Information Configuration via Protocol CvP Implementation in Altera FPGAs User Guide ECRC ECRC ensures end to end data integrity for systems that require high reliability You can specify this option under the Error Reporting heading The ECRC function includes the ability to check and generate ECRC In addition the ECRC function can forward the TLP with ECRC to the RX port of the Application Layer When using ECRC forwarding mode the ECRC check and generation are performed in the Application Layer You must turn on Advanced error reporting AER ECRC checking and ECRC generation under the PCI Express PCI Capabilities heading using the parameter editor to enable this functionality For m
196. ucts and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 9 2 Top Level Interfaces UG 01105_avmm 2014 12 15 Figure 9 1 Arria V Hard IP for PCI Express Using the Avalon MM Interface Clock amp Reset Selection Configuration Block PHY IP Core for Hard IP for PCI Express Configuration via PCle Link PCI Express PIPE Avalon MM Physical Layer Transaction TX Master Application Transceivers e Layer TL Layer D RX Buffer Avalon MM PIPE in a Avalon MM TX Slave PHYMAC omain n i F Crossing Layer Configuration AA a MM PMA PCS CDC DLL Space mais optional Reconfiguration Table 9 1 Application Layer Clock Frequencies x1 125 MHz 64 bits or 125 MHz 64 bits 62 5 MHz 64 bits X2 125 MHz 64 bits 125 MHz 64 bits x4 125 MHz 64 bits 125 MHz 128 bits x8 125 MHz 128 bits N A Related Information PCI Express Base Specification 2 1 or 3 0 Top Level Interfaces Avalon MM Inter
197. uide Created separate user guides for variants using the Avalon MM Avalon ST and Avalon MM with DMA interfaces to the Applica tion Layer Corrected frequency range for hip_reconfig_clk It should be 100 125 MHz Simplified the Getting Started chapter It copies the Gen1 x4 example from the install directory and does not include step by step instructions to recreate the design Added Next Steps in Creating a Design for PCI Express to Datasheet chapter Removed references to the MegaWizard Plug In Manager In 14 0 the IP Parameter Editor Powered by Qsys has replaced the MegaWizard Plug In Manager Added definition for test_in 6 and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus Additional Information CJ Send Feedback UG 01105_avmm 2014 08 18 Revision History for the Avalon MM Interface C3 Clarified that the Avalon MM Bridge does not generate out of order Avalon MM to PCI Express Read Completions even to different BARs Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCle Reconfig Driver Added fact that DCD calibration is required for Gen2 data rate in the description of the transceiver reconfiguration signals Updated figure showing Transceiver R
198. upper 20 bits of the IO limit registers of the Typel Configuration Space This register is only available in Root Port mode cfg_np_bas 12 Output The upper 12 bits of the memory base register of the Typel Configuration Space This register is only available in Root Port mode cfg_np_lim etg or bas 12 44 Output Output The upper 12 bits of the memory limit register of the Typel Configuration Space This register is only available in Root Port mode The upper 44 bits of the prefetchable base registers of the Typel Configuration Space This register is only available in Root Port mode cfg_pr_lim 44 Output The upper 44 bits of the prefetchable limit registers of the Typel Configuration Space Available in Root Port mode cfg_pmcsr 32 Output cfg_pmesr 31 16 is Power Management Control and cfg_pmcsr 15 0 is the Power Management Status register cfg_msixcsr 16 Output MSI X message control CilC _MSLeESic 16 Output MSI message control Refer to the following table for the fields of this register Interfaces and Signal Descriptions G Send Feedback Altera Corporation UG 01105_avmm 4 24 Configuration Space Register Access 2014 12 15 SS Es E E cfg_tcvcmap Output Configuration traffic class TC virtual channel VC mapping The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic cla
199. ures a slightly larger amount of RX Buffer space for non posted and posted request credits but still dedicates most of the space for received completion header and data Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCle link This option is recommended for typical endpoint applications where most of the PCle traffic is generated by a DMA engine that is located in the endpoint application layer logic e Balanced This setting allocates approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions Select this option for variations where the received requests and received completions are roughly equal Reference clock 100 MHz The PCI Express Base Specification requires a frequency 100 MHz 300 ppm reference clock The 125 MHz reference 125 MHz i i clock is provided as a convenience for systems that include a 125 MHz clock source Use 62 5 MHz On Off This mode is only available only for Gen1 x1 application clock Enable configu On Off When On the Quartus II software places the Endpoint in the ration via PCIe location required for configuration via protocol CvP For link more information about CvpP click the Configuration via Protocol CvP link below CvP is not supported for Gen3 variants Related Information PCI Express Base Specification 2 1 or 3 0
200. vmm 4 26 Physical Layout of Hard IP in Arria V Devices 2014 12 15 Related Information Pin out Files for Altera Devices Physical Layout of Hard IP in Arria V Devices gt Arria V devices include one or two Hard IP for PCI Express IP cores The following figures illustrate the placement of the PCIe IP cores transceiver banks and channels Note that the bottom left IP core includes the CvP functionality The other Hard IP blocks do not include the CvP functionality Transceiver channels are arranged in groups of six For GX devices the lowest six channels on the left side of the device are labeled GXB_LO the next group is GXB_L1 and so on Channels on the right side of the device are labeled GXB_RO GXB_RI and so on Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device as specified in the Pin out Files for Altera Devices Figure 4 8 Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria V GX and GT Devices GXB_L2 GXB_R2 GXB_L1 GXB_R1 GXB_LO GXB_RO Notes 1 Green blocks are 10 Gbps channels 2 Blue blocks are 6 Gbps channels Altera Corporation Interfaces and Signal Descriptions GJ Send Feedback UG 01105_avmm 2014 12 15 Physical Layout of Hard IP in Arria V Devices 4 27 Figure 4 9 Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations i
201. x024 Prefetchable Memory Limit Prefetchable Memory Base 0x028 Prefetchable Base Upper 32 Bits 0x02C Prefetchable Limit Upper 32 Bits 0x030 1 0 Limit Upper 16 Bits 1 0 Base Upper 16 Bits 0x034 Reserved Capabilities Pointer 0x038 Expansion ROM Base Address 0x03C Bridge Control Interrupt Pin Interrupt Line PCI Express Capability Structures Figure 5 3 MSI Capability Structure Altera Corporation 31 24 23 16 15 87 0 Message Control 0x050 Configuration MSI Control Status Next Cap Ptr Capability ID Register Field Descriptions 0x054 Message Address 0x058 Message Upper Address 0x05C Reserved Message Data Registers GJ Send Feedback UG 01105_avmm 2014 12 15 Figure 5 4 MSI X Capability Structure 31 24 23 16 15 PCI Express Capability Structures 87 32 0 0x068 Message Control Next Cap Ptr Capability ID 0x06C MSI X Table Offset MSI X Table BAR Indicator 0x070 MSI X Pending Bit Array PBA MSI X Pending Bit Array BAR Indicator Offset Figure 5 5 Power Management Capability Structure Byte Address Offsets and Layout 31 24 23 16 15 87 0 0x078 Capabilities Register Next Cap Ptr Capability ID 0x07C Data iy Control Sta tus Power Management Status and Control Bridge Extensions Figure 5 6 PCI Express AER Extended Capability Structure Byte Offset 31 24 23 16 15 8 7 0 0x80
202. yer Registers Altera Corporation CJ Send Feedback UG 01105_avmm 2014 12 15 Correctable Internal Error Status Register 5 35 a Register Description Reset Value Mask for configuration error detected in CvP mode 4 2 Reserved 0 RO 1 Mask for retry buffer correctable ECC error 1 RWS 0 Mask for RX Buffer correctable ECC error 1 RWS Correctable Internal Error Status Register Table 5 30 Correctable Internal Error Status Register The Correctable Internal correctable When these specific errors are enabled by the Correctable Internal forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3 0 This register is for Error Status register reports the status of the internally checked errors that are Error Mask register they are debug only It should only be used to observe behavior not to drive logic custom logic oB Register Description Reset Value 31 6 Reserved 0 RO 5 When set indicates a configuration error has been detected in 0 RWICS CvP mode which is reported as correctable This bit is set whenever a CVP_CONFIG_ERROR occurs while in CVP_MODE 4 2 Reserved 0 RO 1 When set the retry buffer correctable ECC error status indicates 0 RWI1CS an error 0 When set the RX buffer correctable ECC error status indicates an 0 RWI1CS error Registers G Send Feedback Altera Corporation Reset and Clo

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