Si8920ISO-EVB User's Guide
Contents
1. Materials Part Reference Description Manufacturer Manufacturer Part Number C4 C10 CAP 10 pF 10 V 20 X7R 1206 Venkel C1206X7R100 106M C5 C12 CAP 0 1 uF 10 V 10 X7R 0603 Venkel C0603X7R100 104K C7 CAP 0 01 pF 16 V 10 X7R 0603 Venkel C0603X7R160 103K D20 D23 DIO ZENER 28 V 500 mW S0D 123 On Semi MMSZ5255BT1G D21 D22 LED RED 631 nM 20 mA 2 V 54mcd 0603 Lite On LTST C190KRKT J1 J2 CONN TERM BLOCK 2POS 5MM PCB Phoenix Contact 1729018 JP8 JP10 JP11 JP12 Header 2x1 0 1 pitch Tin Plated Samtec TSW 102 07 T S MH1 MH2 MH3 HDW Screw 4 40 x 1 4 Pan Head Richco Plastic Co NSS 4 4 01 MH4 Slotted Nylon R9 R10 RES 20 0 Q 1 10 W 1 ThickFilm 0603 Venkel CR0603 10W 20ROF R21 R22 RES 10 K 1 10 W 15 ThickFilm 0603 Venkel CR0603 10W 103J R23 R24 RES 0 O 1A ThickFilm 0603 Venkel CR0603 16W 000 SO1 SO2 SO3 HDW STANDOFF 1 4 HEX 4 40x3 4 NYLON Keystone 1902D S04 TP1 TP2 TP3 TESTPOINT BLACK PTH Kobiconn 151 203 RC TP4 TP5 TP6 TP7 TP8 U1 IC ISOLATED AMPLIFIER FOR CURRENT Silicon Labs Si8920BC IP SHUNT MEASUREMENT 8PIN SMD GULL WING Rev 0 1 SILICUN LABS Si8920ISO EVB 5 Ordering Guide Table 5 Si8920ISO EVB Ordering Guide Ordering Part Number OPN Description Si8920ISO KIT Si8920 Analog isolator evaluation board kit Rev 0 1 9 SILICON LABS Si8920IS2. 24 not populated between each input pin and GNDA Placing a small capacitor at C23 and C24 can assist with charge swapping between the inputs and GNDA during common mode transients However any mismatch between C23 and C24 will result as a gain error at the output 1 4 Observing Si8920 Outputs Use a differential probe when observing the output using an oscilloscope Most differential oscilloscope probes will connect to the 2x1 headers JP12 without adapters If only single ended oscilloscope probes are available use two and set oscilloscope to subtract the two channels as one channel will only show half of the output gt Rev 0 1 3 SILICON LABS Si8920ISO EVB 1 5 Output Configuration By default R23 and R24 are populated with 0 O resistors that pass the output signal to the output connectors If low pass filtering at the output is required replace R23 and R24 and populate C22 R25 can be populated to measure the differential output drive strength R26 and R27 can be populated to measure the common mode drive strength to GNDB Table 2 Test Point Descriptions Test Point Description Reference TP1 VDDA GNDA TP2 GNDA N A TP3 VDDB GNDB TP4 GNDB N A TP5 AOP GNDB TP6 AON GNDB TP7 AIP GNDA TP8 AIN GNDA TP13 GNDA N A TP14 GNDB N A Table 3 Jumper Descriptions Jumper PIN 1 PIN 2 Default Position Description JP8 AIN AIP Not Installed Analog Input
3. Connector Short to Measure Offset JP10 VDDA GNDA Not Installed DO NOT SHORT test points only JP11 VDDB GNDB Not Installed DO NOT SHORT test points only JP12 AON AOP Not Installed DO NOT SHORT test points only 4 Rev 0 1 SILICUN LABS Si8920ISO EVB 2 Si8920ISO EVB Schematics OL AS OI AE E eDuei plen Aiddng amod apis Indyno z 40 9newayss gA3 OSIOZ68 S 311514 SIOPSUUOQ jndjno IN NOV pous YON OG ziar A ee eee amp 10 99UU0D Ndu IN NIV OL AG 01 NEE eDue plen K ddng 1amod apis Indu sn nn in Rev 0 1 SILICON LABS Si8920ISO EVB z 40 Z oyewayss gA3 OSIO0Z68 S z 9INBIY VAN sans C ZN IN Ley 0 Nov 5 IN IN red S ecco Sau 0 doy Z EZH 5 493114 3ndjno im jeuondo Ano anyo OLD c dno nor Go san vand ooz Cow anoo ora gt ooz div 6N ZHX00p 18 HONO Jejl4 ssed MOT vaar Rev 0 1 SILICON LABS Si8920ISO EVB 3 Si8920ISO EVB Layout GNDB VDDB Output TP4 TP3 p22 m m J2 VDDA GNDA TP1 TP2 mme Do not short TP9 i Sa mes ech m m ma SR fim TP8 TP10 S e 5 MM Ag AON JP12 p dd SILICON LABS e SiLabs Si8920ISO EVB REV 1 0 Top Silkscreen Bottom Silkscreen Top Bottom Figure 3 Si8920ISO EVB Layout Rev 0 1 7 SILICON LABS Si8920ISO EVB 4 Bill of Materials Table 4 Si8920ISO EVB Bill of
4. O EVB CONTACT INFORMATION Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Tel 1 512 416 8500 Fax 1 512 416 9669 Toll Free 1 877 444 3032 Please visit the Silicon Labs Technical Support web page https www siliconlabs com support pages contacttechnicalsupport aspx and register to submit a technical support request Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low power small size analog intensive mixed signal solutions Silicon Labs extensive patent portfolio is a testament to our unique approach and world class engineering team The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed fea tures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warran ty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any a
5. Si89201SO EVB SILICON LABS Si8920ISO EVB USER S GUIDE Description Si8920ISO EVB Overview This document describes the operation of the Si8920ISO EVB Kit Contents Input melon g m The Si8920ISO Evaluation Kit contains the following items m Si8920ISO EVB m Si8920BC IP installed on the evaluation board TP9 AIP o GE Oo rais uni AN GNDA Q TP13 SILICON LABS SiLabs Si8920ISO EVB REV 1 0 Rev 0 1 8 15 Copyright 2015 by Silicon Laboratories Si8920ISO EVB Si8920ISO EVB 1 Hardware Overview and Setup 1 1 Connecting to the EVB Power the EVB by applying isolated 3 0 to 5 5 Vpc supplies to terminal blocks J1 and J2 LEDs D21 and D22 will light up Use separate test points TP1 TP2 TP3 and TP4 for observing VDDA GNDA VDDB and GNDB respectively Note DO NOT place jumpers across JP10 JP11 or JP12 These are redundant test points for VDDA VDDB and AOP AON respectively There are three connection points for applying and observing differential signals to the inputs of Si8920 1 Through a two conductor ribbon cable to 2x1 header JP8 2 Clipping wires to test points TP7 and TP8 3 Soldering wires directly to through holes located at TP9 and TP10 The same connector options are available for observing and taking the output signals off circuit board 1 Through a two conductor ribbon cable at 2x1 header JP12 2 Clipping wires to test points TP5 and TP6 3 Soldering wi
6. nd all liability including without limitation consequential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intend ed to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 10 Rev 0 1 SILICUN LABS
7. res directly through holes located at TP11 and TP12 1 2 Driving Si8920 Inputs Drive the inputs with a low impedance source The Si8920 has a typical input impedance of 37 2 kO A high source impedance will affect the gain error of the amplifier The maximum specified differential voltage is 200 mV and the common mode must be within 250 mV to 1 V with respect to GNDA Note When driving inputs from a single ended source short the unused input to GNDA If driving AIP input install O O resistor across C23 pads If driving AIN input install a O Q resistor across C24 pads 2 Rev 0 1 SILICUN LABS Si8920ISO EVB 1 3 Input Configuration To measure input offset install a jumper not provided at JP8 to short AIP and AIN together and measure the difference voltage between AOP and AON Si8920 has a channel bandwidth of approximately 750 kHz R9 C7 R10 are populated providing low pass filtering with cutoff frequency of approximately 400 kHz If a different cutoff frequency is desired replace C7 per Table 1 If it is necessary to replace R9 and R10 for a specific cutoff frequency ensure that R9 R10 lt 33 Q Table 1 Input Filter Cutoff Frequency for Common Capacitor Values with R9 R10 2 200 C7 nF Cutoff Frequency kHz 10 398 15 265 22 181 33 121 47 85 Note Installed value Si8920 has excellent immunity to common mode transients This EVB provides provisions for capacitors C23 and C
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