EVBUM2249 - AD984X Timing Generator Board User's Manual
Contents
1. om o O E o http onsemi com 9 EVBUM2249 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Timing Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the Truesense 1964 Lake Avenue Imaging Evaluation Board Kits Rochester New York 14615 When programming the Timing Board the Imager Board Phone 6 85 784 55 00 E mail info truesenseimaging com must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a an Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the Y are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks2. copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its office
3. code The digital input interface also includes a serial interface to the delay lines and AFE parts on the Timing Generator Board so that adjustments may be made to their default operating conditions Z CHI LINE AD9845A gt 48 SMB eo RECEIVER gt 12 bits E OP AMP E 2 p E LVDS 3 DRIVERS S 3V 5V TO 3V REGULATOR gt a TRANSLATORS e Ls 8 GRABBER TIMING 4 S AFE SHP SHD Q AND DATACLK Z PROGRAMMABLE z DELAY IC S Z LVDS TIMING GENERATOR IHAL O Q lt DRIVERS ALTERA 7000S NO 5 E k ccDHI H2 AND BREE BUFFERS Z E RESET CLOCK K O 4 PROGRAMMABLE a 2 DELAY IC S e 5 e JUMPERS sa INT JTAG MASTER INT SYNC ISP ape POWER CONNECTOR CLOCK CLOCK HEADER Figure 1 3E8092 Timing Generator Board Block Diagram Semiconductor Components Industries LLC 2014 August 2014 Rev 2 Publication Order Number EVBUM2249 D EVBUM2249 D TIMING GENERATOR BOARD INPUT REQUIREMENTS Table 1 POWER SUPPLY INPUT REQUIREMENTS Power Supplies Minimum Typical Yan um CE EEE SEE S po ma 5 V Supply TIMING GENERATOR BOARD ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the Timing Generator Board see Figu
4. process a VOUT_CCD signal that is input from a CCD Imager Board in the following way The analog input signal from the Imager Board is buffered by an operational amplifier This amplifier is in a non inverting configuration with a gain of 1 25 The output Integration Output Connector This output provides a signal that is high during the integration time period This signal can be used to synchronize an external shutter or LED light source with the integration time period Output Connector The output connector interfaces directly to the National Instruments PCI 1424 framegrabber The output connector provides two channels of 12 bit output data in parallel in LVDS differential format The connector also provides the three necessary PCI 1424 frame grabber synchronization signals in LVDS differential format of the amplifier is then AC coupled into the AFE chip The AFE chip processes the VOUT_CCD signal then performs the A D conversion and outputs 12 bits of digital information per pixel The AFE device operates at 3 3 V and therefore requires the 5 V supply be regulated down to meet this requirement Also the AFE timing signals are buffered and translated from 5 V levels to 3 V levels before being sent to the device CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J1 and J2 J1 and J2 allow connection of VOUT_CCD video signal s from the CCD Imager Boards Table 9 DIGITAL INPUT CONNECTOR J3 SLOAD SERIAL PORT Altera Code De
5. EVBUM2249 D AD984X Timing Generator Board User s Manual Timing Generator Board Description This Timing Generator Board is designed to be used as part of a two board set used in conjunction with an ON Semiconductor CCD Imager Evaluation Board ON Semiconductor offers a variety of CCD Imager Boards that have been designed to operate with this Timing Generator Board For more information on the available Imager Evaluation Boards see the ON Semiconductor contact information at the end of this document The Timing Generator Board generates the timing signals necessary to operate ON Semiconductor area array Imager Boards and also provides the power required by these Imager Boards via the board interface connector J5 In addition the Timing Generator Board performs the signal processing and digitization of the analog output of the Imager Board The analog output of the Imager Board is connected to the Timing Generator Board via coaxial cable ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL The Timing Generator Board contains an Altera Programmable Logic Device PLD that can be In System Programmed ISP with code that is imager specific This provides flexibility to operate many different Imager Boards with the same Timing Generator Board The Timing Generator Board has a digital Input interface to the Altera device that can be used to support various modes of operation depending on imager specific Altera
6. and AUX2 MODE The Timing Generator Board only supports the CCD MODE and the AUX1 MODE In order to configure the board for AUX1 MODE operation remove R74 and R75 and instead populate R65 and R66 This will route the VOUT_CCD to the AUXIIN pin of the AFE Table 8 AFE REGISTERS The Timing Generator PLD programs the AFE IC s to the default conditions upon power up or when the BOARD_RESET button is depressed The AFE registers can be adjusted by re programming the registers using the 3 wire serial interface provided on the Digital Input Connector Each AFE can be adjusted independently because they each have their own serial load control line CH1_SLOAD CH2_SLOAD The Timing Generator PLD programs the AFE IC s to the default conditions upon power up or when the BOARD_RESET button is depressed The AFE registers can be adjusted by re programming the registers using the 3 wire serial interface provided on the Digital Input Connector Each AFE can be adjusted independently because they each have their own serial load control line CH1_SLOAD CH2_SLOAD Register Address Register Description Notes SES 0 Operation 1 1 VGA gain 1 1 See the AD984X specifications sheet Reference 2 for details R W AO Al A2 Test DO D1 D2 D3 D4 D5 D6 D7 D8 D9 DIO CHX_SLOAD Figure 3 Register Serial Load Timing http onsemi com EVBUM2249 D VOUT CCD Signal Processing Each of the two signal processing channels is designed to
7. gnals AFE timing signals and Frame Grabber synchronization signals The Timing Generator PLD programs the 10 silicon delay IC s on the AFE Timing Generator Board to their default delay settings via a 3 wire serial interface upon power up or by depressing the BOARD_RESET button The Timing Generator PLD programs the registers of the two AFE chips on the AFE Timing Generator Board to their default settings via a 3 wire serial interface upon power up or by depressing the BOARD_RESET button Programmable Delay IC s There are 10 silicon delay lines on the Timing Generator Board They are used to properly align the pixel rate CCD clock signals with respect to one another as well as properly align the AFE signals timing with respect to the VOUT_CCD signal that is input from the CCD Imager Board The Timing Generator PLD programs the 10 delay IC s to their experimentally determined default conditions upon power up or when the BOARD_RESET button is pressed Data for Delay IC 1 D7 DO Figure 2 Delay Serial Load Timing The signal delays can be adjusted by re programming the delay IC s using the 3 wire serial interface provided on the Digital Input Connector SLOAD SDATA SCLOCK For programming purposes the silicon delay lines are daisy chained together cascaded the serial output pin of device 1 is tied to the serial input pin of the device 2 and so on Therefore when making an adjustment to one or more delay lines all
8. ly held low by pull down resistors to GND Therefore with no digital inputs the default level of the Timing Generator Board control lines is all zeros http onsemi com 2 EVBUM2249 D A three wire serial interface is also provided on the input connector This interface really consists of five lines a serial clock serial data and three separate serial load signals Therefore the delays lines on the Timing Generator Board and each of the two AFE chips can be adjusted independent of one another via the serial interface Jumpers There are four jumpers on the board that can be used to adjust the operating mode of the Timing Generator Board The functions of the jumpers depend on how the Altera device is programmed and is detailed in the associated Altera Code Timing Specification JTAG Header This 10 pin header provides the user with the ability to reprogram the Altera PLD in place via Altera s BYTEBLASTER programming hardware Timing Generator PLD The Programmable Logic Device PLD is an Altera 7000S series part This device is In System Programmable ISP via a 10 pin JTAG header located on the board In this way the Altera device is programmed with imager specific code to operate the Imager Board to which the Timing Generator Board will be connected Data for Delay IC 10 D7 DO SLOAD The Timing Generator PLD controls the overall flow of the evaluation board operation The PLD outputs include the CCD clocks si
9. ming Board PN Master Clock Pixel Clock Max 3E8090 40 MHz 20 MHz 3E8091 80 MHz 40 MHz 3E8092 56 MHz 28 MHz 3E8180 60 MHz 30 MHz Unit Integration Clock The unit integration clock is used for KAF series devices as a means for varying the integration time This clock is not used for KAI series devices The clock circuit consists of a 555 timer configured to oscillate at a frequency of 1 kHz The output of this circuit the INTEGRATE CLK has a 1 ms period which is used by the Altera PLD as the unit integration time When the Timing Generator Board is configured to operate in the internal integration mode the integration time is controlled by the Timing Generator Board and will be a multiple of this unit integration time The actual integration time is dependent on how the integration control lines on the digital input connector are configured as well as on how the Altera PLD is programmed Digital Input Connector Remote Digital Input Control The digital input connector can be used to input control signals to the evaluation board These control signals can be used to adjust the operating mode of the evaluation board The functions of the digital inputs depend on what code the Altera device is programmed with This is an optional feature No external digital inputs are required for board operation The digital input control lines to the board are buffered The input pins to the buffer IC s are weak
10. pendent o o o o o o o Altera Code Dependent G G G Altera Code Dependent bios ater Doone C oo tac peer Table 10 JTAG CONNECTOR J4 9 GND GND 0 O O ojo 9 RE fey pei a a 17 18 19 20 21 22 http onsemi com 6 EVBUM2249 D Table 10 JTAG CONNECTOR J4 TMS TDI E IEA E E ENE EEN O A EA RA A http onsemi com 7 A 5 N C GND N C N C GND N C N C EVBUM2249 D Table 11 BOARD INTERFACE CONNECTOR J5 Assignment Function INTEGRATE Signal is High during Integration Time Period AGND Table 13 POWER CONNECTOR J7 Pin Assignment 1 VMINUS P1 1 9 AGND 5 JMP3 VCC Altera Code Dependent P2 2 AGND 6 JMP2 10 VCC Altera Code Dependent P3 3 AGND 7 JMP1 11 VCC Altera Code Dependent 8 P4 4 AGND JMPO 12 VCC Altera Code Dependent Table 15 OUTPUT CONNECTOR J9 Pin Assignment Signal Level Pin Assignment Signal Level IEC IE FENICIA IE o e o os AOUT5 LVDS AOUT5 LVDS 13 AOUT6 LVDS AOUT6 LVDS 15 AOUT7 LVDS AOUT7 LVDS eo om w o FI CI Es Ds http onsemi com 8 EVBUM2249 D Table 15 OUTPUT CONNECTOR J9 Fin Assignment CC Pn Avstnment Signaliav 0 A Ce f pm one o Ca ewe re Ce f omw q e o oe Ce we e we Coa f we J e o e A e BOUT2 BOUT3 BOUT4 e som mos e som ums E som mos e som ums Ce
11. re 1 for a block diagram Power Connector This connector provides the necessary power supply inputs to the Timing Generator Board The connector also provides the VPLUS and VMINUS power supplies These supplies are not used by the Timing Generator Board but are needed by the CCD Imager Boards The Timing Generator Board simply routes these power supplies from the power connector to the board interface connector Power Supply Filtering Power supplied to the board is de coupled and filtered with ferrite beads and capacitors in order to suppress noise For best noise performance linear power supplies should be used to provide power to the boards Table 2 TIMING BOARD CLOCK RATES Power On Clear Board Reset The Altera Programmable Logic Device PLD resets and initializes the board on power up or when the BOARD RESET button in pressed The ten silicon delay ICs are programmed to their default configuration and the AFE device registers are programmed to their default configuration The default configuration is defined separately for each particular CCD Image Sensor and is detailed in the associated Altera Code Timing Specification Master Clock The master clock is used to generate the pixel rate clocks The pixel rate timing signals operate at a frequency that is divided down from the master clock frequency The exact pixel rate frequency is Altera code dependent but is limited to 1 2 the frequency of the master clock Ti
12. rs employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 chief ee Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2249 D
13. s always held low P 1 0 can be tied high or low to achieve the desired pulse width by populating the resistors on the board accordingly Default OUT OUT Default R61 Default OUT OUT Default AD984X Analog Front End AFE Device The Timing Generator Board has one or two analog input channels each consisting of an operational amplifier buffer and an Analog Front End AFE device The Timing Generator Board supports the AD984X family of AFE devices offered by Analog Devices Inc There are several variants in the AD984X family The Timing Generator Board is populated differently depending on which AFE device is being used http onsemi com 4 EVBUM2249 D Table 7 TIMING BOARD CONFIGURATION OPTIONS Timing Board PN Analog Devices PN Sampling Rate Bit Depth 3E8090 AD9844AJST 20 MSPS When using the AD9840 10 bit 40 MSPS AFE R81 R87 R88 and R89 are installed to tie what would be the least significant bits in a 12 bit system to AGND Otherwise these components are not installed When using a part that does not support Analog Devices PXGA modes R68 R69 R71 and R72 are installed and R79 and R80 are not installed By doing so what would have been the VD and HD inputs to the AFE for an AFE supporting PXGA are not connected but instead those AFE pins are connected to AGND The AD984X family of parts has three modes of operation with respect to the analog input signal CCD MODE AUX1 MODE
14. the delay lines must be reprogrammed The total number of serial bits must be eight times the number of units daisy chained and each group of 8 bits must be sent in MSB to LSB order See Reference 3 The programming order of the delay line IC s is as follows 1 AFE DATACLK AFE2 SHP AFEI SHP AFE2 SHD AFE1 SHD HIA CLOCK H1B CLOCK H2A CLOCK H2B CLOCK RESET CLOCK SeEMIADNARWHY a http onsemi com EVBUM2249 D Programmable One Shots The pulse width of the AFE SHP and SHD clocks are set by programmable One Shots The One Shots can be configured to provide clock signals with pulse widths from 5 ns to 15 ns Table 3 SHP1 PULSEWIDTH Ds 9 5 o om Table 4 SHD1 PULSEWIDTH MIO ro m ae mw Ae Ds e 5 5 om Dm 1 o o O Due o o 8 Table 5 SHP2 PULSEWIDTH Ds 0 5 5 om Table 6 SHD2 PULSEWIDTH Dm o fe O om ss fe e or om pm Due 0 o 8 LVDS Drivers Timing signals are sent to the Imager Board via the board interface connector using Low Voltage Differential Signaling LVDS drivers LVDS combines high speed connectivity with low noise and low power Board Interface Connector This 80 pin connector provides both the timing signals and the necessary power to the CCD Imager Boards from the Timing Generator Board The pulse width of the SHP and SHD clocks is set by configuring P 2 0 the inputs to the programmable one shots P2 i
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