TIP-VBY1HS Transmitter Core User Manual
Contents
1. 24 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium W Schedule of Tables Table 2 1 General Use Signal 9 Table 2 2 Mode Setting Signal 9 Table 2 3 User Data Interface Signal 10 Table 2 4 Transceiver Interface Signal Descriptions 11 Table 2 5 Link Status Signal Descriptions 12 Table 3 1 TX GEN Signal Descriptions 13 Table 5 1 Parameterization Table of Wrapper file 15 Table 5 2 Byte mode Data Mapping 15 Table 5 3 Parametarization Table 18 Table 7 1 RGB YCbCr444 RGBW RGBY color data mapping 21 Table 7 2 YCbCr422 color data mapping 22 Table 8 1 Virtex 6 GTX REFCLK Characteristics 24 Table 8 2 Spartan 6 GTP REFCLK 24 Table 8 3 PLL Divider Attribute and Common Values 25 Table 8 4 Virtex 6 GTX Transceiver 25 Table 8 5 S2. _ vu j wv wy 2038 mod j B L p WYU _ 4byte mode 3byte mode 5byte mode Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium Table 7 2 YCbCr422 color data mapping Packer input amp 32bpp 24bpp 20bpp 16bpp Unpacker output YCbCr422 YCbCr422 YCbCr422 YCbCr422 ByteO Bytel s Byte2 3byte mode 4byte mode pel j j J opo 221 _ 022 LIS _ _ _ I C __ opg va Does avo Lob evotn vi Popa 1 1 1 Lope ovo wd w4 D ws Lope ovot Lope 5byte mode Rev1 00 TOKYO ELECTRON DEVICE LIMITED 22 inrevium 7 2 Allocation of pixel to Data Lane Depend on the data rate and pixel color depth it is permitted to increase the Data Lanes About the multiple Data Lanes combination Refers to Figure 7 1 The V by One HS compliant components must be implemented with at least one Data Lane If the data rate of the required color depth and timing is higher tha
3. So it is also recommended to add appropriate placement constraints to clock sources such as PLL BUFG and BUFIO2 at a good balance with the user logic Rev1 00 TOKYO ELECTRON DEVICE LIMITED 20 inrevium W 7 Appendix 1 7 1 Byte length and Color mapping The V by One HS can be used to various types of color video format allocating D 39 0 to pixel data in packer and un packer mapping The color data mapping should refer to Table 7 1 and Table 7 2 Table 7 1 RGB YCbCr444 RGBW RGBY color data mapping ud Unpacker output YCbCr444 YCbCr444 YCbCr444 YCbCr444 RGBY RGBY D mot mot RJ RJ _ DJ R C RBI RU BUS 018 cvv c2 Goo 019 c v Gau _ Bytei 016 B CM4 2 Bo 207 B CM3 BB B od Rs _ 225 j RH _ 0026 B c2 B H _ GO _ 221 dU _ 008 cv BW _ 0029 cvs avi Diso modd Di mot _ _ _ __ 2032 wv png j ww Disa cH _ Bytes PESI Ww 2136 evo
4. Symbol Description Mim Te Units Reference dock Jitter toleranca 60 180 ps TDCREF Reference clock duty as so s Data REFCLK PPM offset tolerance 200 200 ppm Figure 8 1 shows the construction of the Transmitter FPGA board It has the external PLL IC to clean up the jitter of the pixel clock or synthesize the frequency that is required for the REFCLK input M D block in the FPGA generates the appropriate frequency to the external PLL IC s input so this block is optional Transmitter FPGA TXn_P Pixel Clock TXn_N Transmitter PLL Main Links Clock Synthesizer amp Jitter Cleaner MGTREF CLK pin Figure 8 1 Transmitter FPGA Recommended Board Design Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium W 8 2 PLL configuration of Transceiver To make the Reference Clock MGTREFCLK of the GTX GTP transceiver equal to the Pixel clock of the V by One HS standard this core requires the tuning of transceivers PLL settings in the relation to the Byte mode and should have the limitation of clock rate according to the transceiver s specification Equation 8 1 shows how to determine the PLL output frequency GHz means the frequency of the Reference Clock FPLLCKout FPLLCikin N1 Equation 8 1 Equation 8 2 shows how to determine the line rate Gbps FLineRate 2 D Equa
5. 6 734ns HIGH 50 E Data Path Constraints between the other clock domains TIMESPEC TS PXCLK 2 LCLK FROM TN PXCLK TO TNLCLK 5 000ns TIMESPEC TS LCLK 2 PXCLK FROM TNLCLK TO TN PXCLK 5 000ns TIMESPEC TS TXUSRCLK 2 LCLK FROM TXUSRCLK TO TN LCLK 5 000ns TIMESPEC TS 2 TXUSRCLK FROM TN_LCLK TO TN TXUSRCLK 5 000ns TIMESPEC TS TXUSRCLK 2 TXUSRCLK2 FROM TN TXUSRCLK TO TN TXUSRCLK2 5 500ns TIMESPEC TS TXUSRCLK2 2 TXUSRCLK FROM TN TXUSRCLK2 TO TN TXUSRCLK 5 500ns TIMESPEC TS PXCLK 2 FROM TN PXCLK TO TNLCLK 5 000ns TIMESPEC TS LCLK 2 PXCLK FROM TNLCLK TO TN PXCLK 5 000ns TIMESPEC TS PXCLK 2 FROM TN PXCLK TO TN LCLK 5 500ns TIMESPEC TS LCLK 2 PXCLK FROM TNLCLK TO TN PXCLK 5 500ns T Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium 6 2 Placement The following is a placement constraint for Virtex 6 GTX Transceiver These positions are only an example so it should be changed according with the GTX port to use Placement for GTX of Data Lane 0 INST U_TX_MAIN_LINKO1 U_TX_GTX_WRAPO gtx0_tx_gtx_wrap_i gtxel_i LOC GTXE1 0 0 Placement for GTX of Data Lane 1 INST U_TX_MAIN_LINKO1 U_TX_GTX_WRAP1 gtx0_tx_gtx_wrap_i gtxel_i LOC GTXE1_X0Y1 Placement for GTX of Data Lane 2 INST TX MAIN LINK32 U TX GTX WRAPO gtxO tx gtx wrap i gtxel i L
6. customized by editing RTL source TX VX1HS and User Constraint File UCF TX FPGA TOP ucf and merging and implementing them TX FPGA TX VX1HS TOP v TX CLK RST GEN v Sample Design TX FORMATTER v FIELD BET v TX FPGA TOP ucf FIELD BET ngc FORMAT BUF v S6 AFIFO F v V6 AFIFO F v V6 AFIFO F ngc S6 TX MAIN LINK ngc S6 AFIFO F ngc TX LANE X v S6 TX MAIN LINK v Zz NGC Netlist I V6 TX MAIN LINK v V6 TX MAIN LINK ngc Figure 4 2 TIP VBY1HS TX Source File Hierarchy Construction Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM inreviun 5 Parameterization 5 1 Wrapper File TX VX1HS is a wrapper file that can be regarded as a single hierarchy or used by merging it into the top hierarchy of user logic Table 5 1 shows the parameters that are defined in wrapper file TX VX1HS TOP v Table 5 1 Parameterization Table of Wrapper file Select the target FPGA P FPGA TYPE 0 1 0 Virtex 6 1 Spartan 6 parameter P FPGA TYPE integer 1 Spartan6 0 Virtex6 This parameter is used to select a target FPGA type Based on this parameter a dedicated module for Virtex 6 or Spartan 6 is called in merge routine parameter P LANE NUM integer TX Lane Number 1 2 4 8 This parameter is used to set the number of Data Lanes parameter P BYTE MD integer Byte mode Select 3 4 5 This parameter is used to set Byte Mode for user data interface Table 5
7. 2 provides a mapping table between Byte Mode setting and DI CTL input effective bit width Table 5 2 Byte mode Data Mapping P BYTE MD DI 39 0 CTL 23 0 Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM inreviun parameter P PXCLK PERIOD real PXCLK Period This parameter is used to set frequency period of PXCLK Pixel clock that is input from user logic parameter P PXCLK MULT integer MULT This parameter is used to set frequency multiplication ratio of the PLL top side PLL of Figure 3 1 that generates an internal clock from the PXCLK input This value should be observed the following rule Depending on the VCO specification In the case of Spartan 6 the value in is corresponded 600 400MHz lt P PXCLK MULT lt 1200 10000MHz Example PXCLK Pixel clock frequency 148 5MHz for Spartan 6 400MHz lt 148 5MHz P PXCLK MULT lt 1000MHz P PXCLK MULT 23 6 value within this range is available parameter P REFCLK PERIOD MGT Reference clock Period This parameter is used to set frequency period of a REFCLK that is input as a reference clock for the GTP GTX Transceiver parameter P GTPCLKOUT PERIOD real GTP clock out Period This parameter is used to set frequency period of a clock that is output from the GTP GTX Transceiver This value can be calculated by following equation Refer to chapter 5 2 Constraint File about PLL DIVSE
8. 85 2 1 2 1 62GHz D z 1 Flinerate 1 485GHz 2 1 2 97Gbps 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457 Gbps 3 125Gbps Rev1 00 TOKYO ELECTRON DEVICE LIMITED 26 TIP VBY1HS TX_UM inreviun Table 8 6 shows the correspondence list for the video data formats Table 8 6 Video data format vs FPGA GTP GTP Resolution pere rate noo Color depth EUN Spartan 6 Spartan 6 Pixel Clock Lane Virtex 6 sp 3 sp 2 18 24 bit 60Hz 74 25MHz 30 bit fw 18 24 bit fe 9 _ 120Hz 36 bit 18 240 G _ 240Hz awe 4 w v 36bt v 1824bt vo G 60Hz 485 2 wv w _ 18 24 bit e 9 _ 120Hz 36 bit 18 240 wo G GG 3bt ww wv v v 1824bt G 60Hz 594MHz v v _ MT 18 24 bit 7 2 1188 2 16 30 bit 36bit 2 18 24 bit 7 2376MHz 30bt 36bit 1 Frequency of the GTX s REFCLK should not be integer dividing ratio to the pixel clock ones 2 Requires the double number of Data lanes gt 2lanes 2lanes gt 4lanes 4lanes gt 8lanes 3 Although Data rate of the lane will be higher than it needs the 30bit color depth mode is able to cover the 18 24bit color depth Rev1 00 TOKYO ELECTRON DEVICE LIMITED 2 gt lt n V
9. APDET PICS uuu 15 5 2 Constraint 1 18 p x 19 O L Ti __ s 19 LAM 5400 20 r eei u ____________ _________ ______ 21 7 1 Byte length and Color 21 7 2 Allocation of pixel to Data Lane 23 WMluo pebQOT H 24 8 1 Reference 1 rra memet tererererereremerererererii 24 8 2 PLL configuration Of Transceiver 25 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium W Schedule of Figures Figure 2 1 Transmitter Core Top Level Block 8 Figure 2 2 User Data Interface Timing 10 Figure 2 3 Control Data Active 10 Figure 3 1 TX CLK RST GEN 13 Figure 4 1 TIP VBY1HS Folder Hierarchy Construction 14 Figure 4 2 TD BX1HSip TX Source File Hierarchy 14 Figure 7 1 Allocation of pisel to Data 23 Figure 8 1 Transmitter FPGA Recommended Board
10. BY1HS TIP 2 p p o p o p o p l LLI gt am H O LLI LLI O gt x Rev1 00 TIP VBY1HS TX_UM inreviun TOKYO ELECTRON DEVICE LIMITED Tokyo Electron Device Limited Inrevium Division Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa 221 0056 Japan 81 45 443 4031 81 45 448 4059 URL http www inrevium jp eng Email inrevium contact teldevice co jp Your Local Contact The Information described in this document will be changed from time to time without prior notice If you plan to buy and use this device product described herein please contact the sales person or address specified herein Tokyo Electron Device Limited shall not be liable for any claim by third party alleging an infringement of patent right or any other intellectual property right where alleged liability of Users arises by reason of using the information and drawing described in this document Tokyo Electron Device Limited shall not be liable for any claim by third party alleging an infringement of the patent right utility model right circuit layout use right copyright or any other intellectual property right where alleged liability of Users arises by reason of using this device product in combination with other products or of any derivative products integrating this device
11. Constraint the Core A constraint file TX VX1HS TOP ucf contains timing and placement constraints of major dedicated blocks It is needed to enter TX VX1HS TOP ucf directly as a constraint file with the same hierarchy with TX VX1HS TOP v or load it into a constraint file for the top hierarchy of the user logic 6 1 Timing The following are the timing constraints on clocks associated with the TIP VBY1HS Transmitter Core in the case of 4 byte mode 148 5MHz pixel clock frequency 2 Data Lanes To make explanation plain the constraint values are matched with real movement speed So the value with the margin is recommended in the development Generating the clock groups and period constraints for each clock domain Pixel clock NET PXCLK TNM NET TN PXCLK TIMESPEC TS PXCLK PERIOD TN PXCLK 6 734 HIGH 50 GTPOUTCLK refer to Chapter 5 1 NET GTPCLKOUT_BUF TNM TN GTPCLKOUT TIMESPEC TS GTPCLKOUT PERIOD TN GTPCLKOUT 3 367ns HIGH 50 Lane clock Pixel clock period No of Data Lanes TNM NET TNLCLK TIMESPEC TS PERIOD TNLCLK 13 468ns HIGH 50 TXUSRCLK for GTP GTX GTPCLKOUT period NET TXUSRCLK TNM NET TN TXUSRCLK TIMESPEC TS TXUSRCLK PERIOD TN TXUSRCLK 3 367ns HIGH 50 TXUSRCLK2 for GTP GTX GTPCLKOUT period 2 NET TXUSRCLK2 TNM NET TN TXUSRCLK 2 TIMESPEC TS TXUSRCLK2 PERIOD TN TXUSRCLK2
12. K RST GEN Signal Descriptions PXCLK Input f Pixel clock from User Data Interface GTPCLKOUT ERES Clock from GTPCLKOUT port of GTP GTX Locked signal from GTPPLLLKDET port of Release of reset from RESETDONE port of GTPTX_SYNC_DONE n 0 GTP GTX Output Pixel clock for TX internal logic Clock for adjustment of the signal rate between ia Cl EN FORMATTER and TX MAIN LINK Clock to TXUSRCLK port of GTP GTX and ES parallel clock for MAIN LINK internal logic TXUSRCLK2 Output Clock to TXUSRCLK2 port of GTP GTX XRST Output System reset for internal logic Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM 4 File Hierarchy Construction 4 1 Folders Figure 4 1 shows the design folder hierarchy in Transmitter Core folder contains the all wrapper sources and ISE folder contains the all NGC Netlists Constraint files and ISE project of sample design TIP VBY1HS DOC Documentations RTL RTL designs Wrapper files of the Macros ISE MACRO Macros NGC Netlists UCF Constraint files i E J PRJ Pra est ransmitter 15 project sample design Receiver ISE project Prope sample design 2 4 s SIM RTL Simulation Figure 4 1 TIP VBY1HS Folder Hierarchy Construction 4 2 Source Files Figure 4 2 shows the RTL source and NGC Netlist hierarchy in Transmitter Core Transmitter Core can be
13. L parameter for Virtex 6 GTPCLKOUT PERIOD PXCLK PERIOD P BYTE MD 8 1 25 P LANE NUM Z PLL DIVSEL OUT PLL DIVSEL REF PLL DIVSEL FB 5 for Spartan 6 GTPCLKOUT PERIOD PXCLK PERIOD P BYTE MD 8 1 25 P LANE NUM PLL DIVSEL OUT 2 PLL DIVSEL REF PLL DIVSEL FB 5 Example PXCLK PERIOD 6 734ns 148 5MHz 4 byte mode 2 data lanes for Spartan 6 PLL DIVSEL REF 1 PLL DIVSEL FB 2 DIVSEL OUT 1 GTPCLKOUT PERIOD 6 734 4 8 1 25 2 1 1 2 5 3 367 Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM inreviun parameter P GTPCLKOUT MULT integer GTP clock out PLL CLKFBOUT MULT parameter P GTPCLKOUT DIVIDE integer GTP clock out PLL DIVCLK DIVIDE This parameter is used to set frequency multiplication and dividing ratio of PLL bottom side PLL of Figure 3 1 that generates an internal clock from the output clock of the GTP GTX Transceiver in the MAIN LINK block These values should be observed the following rules 600 400 MHz lt P GTPCLKOUT MULT P GTPCLKOUT DIVIDE lt 1200 1000 MHz PI L DIVSEL REF PLL DIVSEL OUT GTPCLKOUT MULT PLL DIVSEL FB P GTPCLKOUT DIVIDE must be integer 1 128 Example GTPCLKOUT frequency 297MHz for Virtex 6 PLL DIVSEL REF 1 PLL DIVSEL FB 2 DIVSEL OUT 1 600MHz lt 297MHz P GTPCLKOUT MULT P GTPCLKOUT DIVIDE lt 1200MHz 1 1 P GTPCLKOUT MULT 2 P GTPCLKO
14. LICR IAN NIRA RAL ew qQ g Le X g ew LL Oe LL 0 1I 0170100 Active DI Active Active CTL Active Active Active Figure 2 2 User Data Interface Timing Chart As shown in Figure 2 3 as the number of data lanes increases the effective period for Control data is shortened since the ineffective period at both ends increases considered when using Control data Active 21 cycle Active e cycle Alanes 3cycle Active Slanes x Active Rev1 00 Figure 2 3 Control Data Active Term TOKYO ELECTRON DEVICE LIMITED This should be lt lt lt lt 2 4 8 16 Minimum DE low cycle without TIP VBY1HS TX_UM inreviun Transceiver Interface Table 2 4 describes the Transceiver Interface signals Table 2 4 Transceiver Interface Signal Descriptions Signal Name Becton REFCLK P1 REFCLK of GTX GTP Transceiver positive optional P n 0 Output iti TXO N n 0 Output CLKOUT Output Clock output to External PLL optional DRV 3 0 Drive Strength Select PRE 3 0 Input Pre Emphasis Select TXO P N n 0 0 1 3 7 These are external pins of the FPGA for serial video data transmission Output pins of Virtex 6 GTX Trans
15. OC GTXE1 X0Y2 Placement for GTX of Data Lane 3 INST TX MAIN LINK32 U TX GTX WRAP 1 gtxO tx gtx wrap i gtxel i LOC GTXE1 X0Y3 Placement for GTX of Data Lane 4 INST TX MAIN LINK54 U TX GTX WRAPO gtxO tx gtx wrap i gtxel i LOC GTXE1 0 4 Placement for GTX of Data Lane 5 INST TX MAIN LINK54 U TX GTX WRAP 1 gtxO tx gtx wrap i gtxel i LOC GTXE1 X0Y5 Placement for GTX of Data Lane 6 INST TX MAIN LINK76 U TX GTX WRAPO gtxO tx gtx wrap i gtxel i LOC GTXE1 X0Y6 Placement for GTX of Data Lane 7 INST TX MAIN LINK76 U TX GTX WRAP 1 gtxO tx gtx wrap i gtxel i LOC GTXE1 X0Y7 The following is a placement constraint for Spartan 6 GTP Transceiver These positions are only an example so it should be changed according with the GTP port to use Placement for GTP of Data Lanes 0 1 INST TX MAIN LINKO1 tileO tx wrap i gtpal duali LOC GTPA1 DUAL XOYO Placement for GTP of Data Lanes 2 3 INST TX MAIN LINK32 tileO tx wrap i gtpal dual i LOC GTPA1 DUAL X1YO Placement for GTP of Data Lanes 4 5 INST TX MAIN LINK54 tileO tx wrap i gtpal dual i LOC GTPA1 DUAL Placement for GTP of Data Lanes 6 7 INST TX MAIN LINK76 tileO tx wrap i gtpal dual i LOC GTPA1 DUAL X1Y1 The contents mentioned above are the constraints necessary to a minimum
16. UT DIVIDE must be integer 1 128 P GTPCLKOUT MULT 4 P GTPCLKOUT DIVIDE 1 Simulation attributes parameter P SIMSPEEDUP 0 Set to 1 for speed sim reset parameter P_SIMULATION 0 II Set to 1 for simulation These parameters are set to 1 for RTL Simulation oet 0 for Normal Merging Rev1 00 TOKYO ELECTRON DEVICE LIMITED 17 TIP VBY1HS TX_UM inreviun 5 2 Constraint File A constraint file TX VX1HS TOP ucf also contains some important parameters Table 5 3 shows the parameterization that can be defined within the User Constraint File TX VX1HS TOP ucf Table 5 3 Parameterization Table of UCF P PLL DIVSEL REF PLL Reference clock input Divider of GTX GTP Transceiver P PLL DIVSEL FB 1 2 4 5 PLL Feedback Dividers of PLL Feedback Dividers of GPXIGTP Transceiver 00 Transceiver P_PLL_DIVSEL_OUT PLL Output Divider of GTX GTP Transceiver These parameter settings have a close relation with device specifications and characteristics of Virtex 6 GTX and Spartan 6 GTP Transceiver For more information about the meaning and the effectiveness of these setting values refer to Chapter 8 2 of this document The attached TIP VBY1HS Transceiver PLL Settings Estimate Sheet Exel Sheet is helpful for calculating a setting value It is important to understand the basic idea of these parameters before calculating a setting value Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium 6
17. able TIP VBY1HS Data Sheet TIP VBY1HS Receiver Core User Manual TIP VBY1HS Transceiver PLL Setting Estimate Sheet Excel TIP VBY1HS CVK Reference Design User Manual 1 4 Technical Support For technical support go to ipg support teldevice co jp Tokyo Electron Device Ltd TED provides technical support for this IP Core when used as described in the product documentations TED cannot guarantee timing functionality or support of product if implemented in devices that are not defined in the documentation if customized beyond that allowed in the product documentation TED also offers a contract based development service for customized design or additional function design ex more than 16 data lanes for Virtex 6 1 5 References The following V by One amp HS Standard and FPGA documentations were referenced when developing the TIP VBY1HS V by One HS Standard Version 1 2 Jan 15 2009 by THine Electronics Inc Virtex 6 FPGA GTX Transceivers User Guide UG366 v2 2 Feb 23 2010 Virtex 6 FPGA Data Sheet DC and Switching Characteristics 05152 v2 2 Feb 9 2010 Spartan 6 FPGA GTP Transceivers User Guide UG386 v2 1 Mar 30 2010 Spartan 6 FPGA Data Sheet DC and Switching Characteristics 05162 v1 4 Mar 10 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 7 TIP VBY1HS TX_UM inreviun 2 Core Architecture This chapter provides and overview of the TIP VBY1HS Transmitter Core architecture The TIP VBY1HS is a
18. ceivers or Spartan 6 GTP Transceivers are used In the case of using the output pins of Spartan 6 GTP Transceiver the TX MAIN LINK module shown in Figure 2 1 Block Diagram section 2 1 Block Diagram is definitely mapped to a single DUAL Tile Two exist in GTP DUAL Tile So in the case of 1 Data Lane and 2 Data Lanes GTP DUAL Tile should be used in the case of 4 Data Lanes two GTP DUAL Tiles should be used and in the case of 8 Data Lanes four GTP DUAL Tiles should be used As for Virtex 6 there are no above constraints REFCLK 0 REFCLK P N1 Two external reference clock input pins are provided for Spartan 6 GTP Transceiver They are used to provide a clock to each GTP DUAL Tile on the top and bottom sides of FPGA If only either side of GTP DUAL Tile is used it is not needed to have two clock pins For more information about GTP DUAL Tile refer to the Spartan 6 FPGA GTP Transceivers User Guide As for Virtex 6 there are no above constraints DRV 3 0 PRE 3 0 These signal pins are used to set Swing control and Pre Emphasis control for TXO P N They correspond to the following GTX GTP port name DRV 3 0 TXDIFFCTRL 3 0 PRE 3 0 TXPREEMPHASIS 3 0 In case of Spartan 6 GTP Transceiver only PRE 2 0 is valid For characteristics corresponding to these setting values refer to the associated FPGA Transceiver User Guide and determine an appropriate value to match the characteristics of
19. device and transmission line to the receiving side Rev1 00 TOKYO ELECTRON DEVICE LIMITED 11 TIP VBY1HS TX_UM inreviun Link Status Signals Table 2 5 describes the Link Status signals Table 2 5 Link Status Signal Descriptions HTPDN Hot plug detect RDY Link Status Ready HTPDN This is an external pin connecting to the equivalent output pin of a receiving end device It notifies that the receiving end device has been connected This is external connecting to the equivalent output pin of a receiving end device It notifies that the clock data recovery CDR of the receiving end device has been locked RDY This indicates a Link up with the receiving end device It can be used for a variety of purposes by user logic Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM inreviun 3 Clock Construction Figure 3 1 shows the construction of the clock module TX CLK RST GEN TX CLK RST GEN PLL ADV MMCM ADV PXCLK I CLKOUTO gt PXCLK O CLKINSTOPPED CLKOUT1 LCLK RST GTPPLLLKDET LOCKED s PLL_LOCKED 0 PLL ADV MMCM ADV GTPCLKOUT CLKOUTO gt TXUSRCLK CLKINSTOPPED CLKOUT 1 TXUSRCLK2 LOCKED s PLL_LOCKED 1 GTPTX SYNC DONE N 1 0 s PLL LOCKEDL I 0 XRST Figure 3 1 TX CLK RST GEN Construction Table 3 1 describes the TX CLK RST GEN signals About the connection of each clock refer to the Figure 2 1 Top Level Block Diagram Table 3 1 TX CL
20. full featured soft IP core that is provided in the form of a NGC Netlist for V by One HS compliant components and a Verilog RTL for other components 2 1 Block Diagram The Transmitter Core is partitioned into three major blocks as shown in Figure 2 1 TX LANE X Provides for the delivery of the video stream This block contains major functional blocks called TX MAIN LINKs based on the number of data lanes Each TX MAIN LINK has two data lanes one data lane is valid in single data lane setting TX FORMATTER This block formats signals from user logic and sends them to the TX LANE X block TX GEN This block generates all clocks needed for the above blocks FPGA TX VX1HS TOP TX FORMATTER MGTREFCLK P N AFIFO F NGC Netlist us TX_MAIN_LINK_0 1 m EN NGC Netlist LOCKN HTPDN TX0O P N TX1 P N AFIFO F NGC Netlist s LN VSYNC N 1 0 HSYNC s LNO HSYNC N 1 0 DE s LNO DE N 1 0 D1 39 0 s LNO DI N 40 1 0 s LNO 24 1 0 CTL 23 0 Number of Data Lanes TX_MAIN_LINK_n 1 n TXn 1_P N NGC Netlist TXn P N FIELD_BET FIELD_BET NGC Netlist TX_CLK_RST_GEN PXCLK PDN Figure 2 1 Transmitter Core Top Level Block Diagram Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM inreviun 2 2 Transmitter Core Interfaces General Signals Table 2 1 describes the General Use signals Table 2 1 General Use Signal Descriptions Th
21. inrevium W Preliminary TIP VBY1HS Transmitter Core User Manual V by One9 HS Standard IP for Xilinx FPGA Rev 1 00 High speed and Reduced digital connection concept Tokyo Electron Device Ltd Rev1 00 TOKYO ELECTRON DEVICE LIMITED 1 inrevium W Revision History The following table shows the revision history for this document Revision Dae Rev 1 0 0E 2010 04 12 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium Table of Contents L 6 1 1 About the 6 1 2 Recommended Design Experience 7 1 3 Additional Core Resources 7 e 7 1 5 RENTRER 7 2 Core eres esses enn 8 2 1 Block Diagram 8 2 2 Transmitter Core Interfaces 9 Clock 13 A File Hierarchy gic a6 TT 14 l l gt 14 4 2 Source eis 14 5 0 006 rra stre emereri rere eter rni 15 O la
22. is signal clears all functional blocks Mode Setting Signals Table 2 2 describes the Mode Setting signals Table 2 2 Mode Setting Signal Descriptions FIELD BET Field BET Mode Enable In the mode to check the quality of high speed serial data lines Field BET Mode enables FIELD BET input to generate a data pattern like BET Bit Error Tester internally and output it to data lanes Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS TX_UM User Data Interface Table 2 3 describes the User Data Interface signals me _ Table 2 3 User Data Interface Signal Descriptions VSYNC HSYNC Input Input DI 39 0 Input Video data Input L Horizontal sync pulse Figure 2 2 shows the timing chart of the User data interface In V by One HS architecture Video data enable DE input signal is very important because Video DI and Control CTL data that are input from user logic are framed using them as Video data is transmitted as effective pixel region when DE is High On the other hand Control data is transmitted as effective data region when DE is Note that there is a timing reference signals active Low inactive excluding a period of 1cycle before and after that period inreviun NE Vertical sync pulse Control data limitation on this effective period dependent on number of lanes used For more information refer to the subsequent description
23. n the components maximum supported data rate additional Data Lane can be used The maximum data rate of V by One HS Data Lane is 3 5Gbps per lane In this case total lane count should be even number under the condition of the fewer lane number The pixel number for the horizontal active and blanking term H active H blank should be adjusted to become the multiple number of the lane count Lane 1 Lane 2 Lane 3 Lane N _ s Blanking End amp System Reset Gets 514 Blank Lo __ s _ _ __ __ _ EE NN ___ ol _ Figure 7 1 Allocation of pixel to Data Lane Rev1 00 TOKYO ELECTRON DEVICE LIMITED 23 TIP VBY1HS TX_UM inreviun 8 Appendix 2 8 1 Reference clock When GTX GTP Transceiver requires the different frequency reference clock to the pixel clock transmitter side requires the external PLL to generate the REFCLK In addition REFCLK is recommended to be supplied by the exclusive differential port and to be satisfied the specification shown in Table 8 1 and Table 8 2 Table 81 Virtex 6 GTX REFCLK Characteristics Symbo Description Max Units Reference clock frequency ange 625 650 MHz TDCREF Reference clock duty cycle Rxppmtol Data REFCLK PPM offset tolerance Table 8 2 Spartan 6 GTP REFCLK Characteristics
24. partan 6 GTP Transceiver Performance 25 Table 8 6 Video data format vs 27 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 5 TIP VBY1HS TX_UM Inreviun 1 Introduction This chapter introduces the Tokyo Electron Device Ltd TED s Transmitter Core that makes up V by One HS standard IP Core TIP VBY1HS designed for Xilinx FPGAs It also describes design environment for development and other related information V by One HS standard has been developed by THine Electronics Inc to offer capabilities for Flat Panel Display FPD markets that are requiring ever higher frame rates and higher resolutions This manual provides information about how to edit the TIP VBY1HS Transmitter Core s wrapper files and constraint files and so on 1 1 About the Core TIP VBY1HS Transmitter Core is a Soft IP designed for Verilog HDL design environment It can be implemented in any suitable arrangement with the user logic for the following FPGA family Hardware Validation The TIP VBY1HS Core has acquired a connectivity certification from THine electronics Inc by successfully completing a connectivity test between an FPGA board with the Core and a V by One HS evaluation board Target Device Target devices of the TIP VBY1HS Core include the Virtex 6 family with GTX Transceiver and the Spartan 6 family with GTP Transceiver Note that dependent on FPGA transcei
25. product This device product is not designed manufactured or intended for use 1 in hazardous environment requiring extremely high safety including without limitation in operation of nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system in which the failure of this device product could have a serious effect to the public and lead directly to death personal injury severe physical damage or other loss or 2 in any other environment requiring extremely high reliability including without limitation in operation of submarine transmissions or space satellite 2010 Tokyo Electron Device Limited printed in Japan Apr 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 29
26. tion 8 2 Table 8 3 shows the actual attribute and commonly used divider values Table 8 3 PLL Divider Attribute and Common Values Attribute Name Valid Settings TXPLL_DIVSEL_REF RXPLL_ DIVSEL_REF N1 TXPLL_DIVSEL45 FB 4 5 1 RXPLL DIVSEL45 FB TXPLL DIVSEL FB RXPLL DIVSEL FB 1 2 4 9 TXPLL DIVSEL OUT RXPLL DIVSEL OUT 1 DIVSELA5 FB 5 when INTDATAWIDTH is High 10bit mode 8B 10B encoding Table 8 4 and Table 8 5 show the GTX GTP Transceiver Performance Table 8 4 Virtex 6 GTX Transceiver Performance sme M E _ Maximum GTP Transceiver data Am PLL frequency range 1 23 3 1272 7 FGCLK Reference clock frequency range 62 5 650 Table 8 5 Spartan 6 GTP Transceiver Performance Speed Grade Symbol Description _______ Units 3 2 FGTPMAX Maximum GTP Transceiver data rate 3 125 FGPLL PLL frequency range 1 2 1 62 FGCLK Reference clock frequency range 60 160 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 25 inrevium Example Byte mode 4byte Pixel Clock frequency 148 5MHz No of Data Lanes 2 Data rate 32bit 148 5MHz 1 25 2 2 97bps Virtex 6 GTX peed grade 2 M 1 5 must be this value 4 Fpliclkout 148 5MHz 5 x 4 2 9 GHz 1 2 3 3GHz D 2 Flinerate 2 97GHz 2 2 2 97Gbps 3 75Gbps Spartan 6 GIP speed grade 3 M 1 N1 5 must be this value N2 2 Fpliclkout 148 5MHz 5 x 2 1 4
27. ver specifications the following limitations are imposed on high speed data lane s transmission bandwidth that is provided by the transceiver 600Mbps 3 75Gbps per data lane same as the standard Virtex 6 LXT XC6VxxxLXT all speed grade Virtex 6 SXT XC6VxxxSXT speed grade 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457Gbps 3 125Gbps per data lane 6 LXT XC6SxxxLXT speed grade 3 4 speed grade 2 Maximum rate is less than 2 7Gbps Following equation shows how to determine the data rate of the lane Gbps FDataRata BI ByteMode FPixelCik 1 25 8B 10B Example Byte mode 4byte Pixel Clock frequency 148 5MHz Number of data lanes 2 Data rate per lane 32bits x 148 5MHz x 1 25 2 2 97Gbps Besides the above there are other limitations and cautions that are attributed to FPGA specifications and characteristics For more information refer to the relevant chapters of this document and the FPGA data sheets Rev1 00 TOKYO ELECTRON DEVICE LIMITED 6 TIP VBY1HS TX_UM inreviun 1 2 Recommended Design Experience The following development environments are required to develop TIP VBY1HS Core Implement ISE 11 4 Logic Edition and above Synthesis Xilinx XST 11 4 and above Simulation Mentor Graphics amp 6 5a and above for Verilog HDL 1 3 Additional Core Resources Besides this document the following support documentation is avail
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