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ST10F269 User's manual

1. Name Physical address Description Reset value RTCCON ECOOH RTC Control Register 00h RTCPL ECO6h RTC Prescaler Register Low Byte XXXXh RTCPH ECO8h RTC Prescaler Register High Byte XXXXh RTCDL ECOAh RTC Divider Counter Low Byte XXXXh RTCDH ECOCh RTC Divider Counter High Byte XXXXh RTCL ECOEh RTC Programmable Counter Low Byte XXXXh RTCH EC10h RTC Programmable Counter High Byte XXXXh RTCAL EC12h RTC Alarm Register Low Byte XXXXh RTCAH EC14h RTC Alarm Register High Byte XXXXh CAN2CSR EE00h CAN2 Control Status Register XXOth CAN2IR EE02h CAN2 Interrupt Register XXh CAN2BTR EE04h CAN2 Bit Timing Register XXXXh CAN2GMS EE06h CAN2 Global Mask Short XFXXh CAN2UGML EE08h CAN2 Upper Global Mask Long XXXXh CAN2LGML EEOAh CAN2 Lower Global Mask Long XXXXh CAN2UMLM EEOCh CAN2 Upper Mask Last Message XXXXh CAN2LMLM EEOEh CAN2 Lower Mask Last Message XXXXh CAN2MCR1 15 EE10 EEFOh CAN2 Message Control Register 1 to 15 XXXXh CAN2UAR1 15 EE12 EEF2h CAN2 Upper Arbitration Register 1 to 15 XXXXh CAN2LAR1 15 EE14 EEF4h CAN2 Lower Arbitration register 1 to 15 XXXXh CAN2MO1 15 EE1x EEFxh CAN2 Message Object 1 to 15 XXXXh CAN1CSR EFOOh CAN1 Control Status Register XXOth CAN1IR EFO2h CAN1 Interrupt Register XXh CAN1BTR EFO4h CANT Bit Timing Register XXXXh CAN1GMS EFO6h CAN1 Global Mask Short XFXXh CAN1UGML EFO8h CAN1 Upper Global Mask Long XX
2. CCMO FF52h A9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC3 CCMOD3 ACC2 CCMOD2 ACC CCMOD1 ACCO COMODO RW RW RW RW RW RW RW RW CCM1 FF54h AAh SFR Reset Value 0000h me 2 143 2 E as O 7 6 5 4 3 2 8 Des CCMOD7 ACC6 CCMOD6 ACCS comops acca ccmop4 RW RW RW RW RW RW RW RW CCM2 FF56h ABh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acci1 ccmopi1 accio oouopmg acca _ccmops accs CCMOD8 RW RW RW RW RW RW RW RW CCM3 FF58h ACh SFR Reset Value 0000h 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 accis ccmopis acci4 ccmopi4 accis ccmopis acci2 ccmoni2 RW RW RW RW RW RW RW RW Capture compare mode registers for the CAPCOM2 unit CC16 CC31 CCM4 FF22h 91h SFR Reset Value 0000h 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 accio ccmopi9 accis ccmopis acciz ccmopi7 accie ccmoD16 RW RW RW RW RW RW RW RW CCM5 FF24h 92h SFR Reset Value 0000h is i 13 42 44 Yo 9 8 7 6 5 4 3 2 4 0 acc23 ccmop23 acc22 ccmop22 accz21 ccmop21 acczo ccmoD2o RW RW RW RW RW RW RW RW CCM6 FF26h 93h SFR Reset Value 0000h e Aa 143 142 om 10 9 8 7 6 5 4 3 2 4 0 Acc27 ccmop27 acc26 CCMOD26 ACC25 ccmop25 Acc24 ccmop24 RW RW RW RW RW RW RW RW DI 221 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL CCM7 FF28h 94h SFR Reset Value 0000h 15 14 13 12 411 10 9 8 7 6 5 4 a 2 1 0 aCCal ccmon31 aceso CC
3. Instruction Pointer L 4 Stage Pipeline 16 bit PSW Barrel Shift SYSCON CP BUSCON 0 BUSCON 1 ADDRSEL 1 10 Kbyte BUSCON 2 ADDRSEL 2 XRAM BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Code Segment Pointers Pointer 2 1 1 High Instruction Bandwidth Fast Execution Most of the ST10F269 s instructions are executed in one instruction cycle For example shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted Multiple cycle instructions have been optimized branches are carried out in 2 CPU clock cycles 16 x 16 bit multiplication in 5 CPU clock cycles and a 32 16 bit division in 10 CPU clock cycles The jump cache reduces the execution time of repeatedly performed jumps in a loop from 2 CPU clock cycles to 1 CPU clock cycle The instruction cycle time has been reduced by instruction pipelining This technique allows the core CPU to process in parallel portions of multiple sequential instruction stages The following four stage pipeline provides the optimum balancing for the CPU core Fetch In this stage an instruction is fetched from the internal Flash or RAM or from the external memory based on the current IP value Decode In this stage the previously fetched instruction is decoded and the required operands are
4. Code Segment 15 CSP Register 0 15 IP Register 0 FFFEFFh E 255 254 FE 0000h LIT 1 01 0000h e 24 20 18 bit Physical Code Address 00 0000h l AA SA SR Sg eg De e Se e a al Note When segmentation is disabled the IP value is used directly as the 16 bit address Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in the Figure 14 In case of the segmented memory mode the selected number of segment address bit 7 0 3 0 or 1 0 of register CSP is output on the segment address pins A23 A16 of Port4 for all external code accesses For non segmented memory mode the content of this register is not significant because all code accesses are automatically restricted to segment 0 The CSP register can only be read but not written by data operations lt is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to zero ky 49 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL 4 4 6 The Data Page Pointers DPP0 DPP1 DPP2 DPP3 These four non bit addressable registers select up to four different data pages being active simultaneously at run time The lower 10 bits of each D
5. a 160 340 ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Timer 3 Run bit The timer can be started or stopped by software through bit T3R Timer T3 Run bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active high or low as programmed Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bit T3UD and T3UDE in control register T3CON When the up down control is done by software bit T3UDE 0 the count direction can be altered by setting or clearing bit T3UD When T3UDE 1 pin T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in the Table 29 If T3UD 0 and pin T3EUD is at low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as input its corresponding direction control
6. BIT HANDLING AND BIT PROTECTION A INSTRUCTION EXECUTION TIMES CPU SPECIAL FUNCTION REGISTERS cococcoicconicononnnnncnanccnnnonan conc cnn coronar rca The System Configuration Register SYSCON o eececeeeececeeeeeeeeeeeeeneeeeeeeeeeseaeeeeenees X Peripherals Control Register GPERDCON A The Processor Status word PSW The Instruction Pointer IP The Code Segment Pointer CSP The Data Page Pointers DPPO DPP1 The Context Pointer Ch The Stack Pointer SP ou The Stack Overflow Pointer STKOV The Stack Underflow Pointer STKUN O The Multiply Divide High Register MDH oooocccinccccniccconoccnnonconanona rancio nnncananrccnnnnn The Multiply Divide Low Register MDL 0ooconcccinnccconncccnonccnnonncononoca rancio conca nan nca nn The Multiply Divide Control Register The Constant Zeros Register ZEROS The Constant Ones Register ONES Exam pl ek seeenn R MDG euer eet ere MULTIPLY ACCUMULATE UNIT MAC occcococcccionccccccccncanocanacannnanncn nana conca nanacnnnno os MAC FEATURES An MAC OPERATION A Instruction Pipelining eee Particular Pipeline Effects with the MAC Un Address Generation 16 x 16 Signed unsigned Parallel Multtpoller 40 bit Signed Arithmetic Unit The 40 bit Adder Subtracter Data Limiter cceeeeeeeeeeeeeeeeees The Accumulator Shifter Repeat Unit ek MAC in
7. Name Wies Description SE CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register 00h CC4IC b FF80h CAPCOM Register 4 Interrupt Control Register 00h CC5IC b FF82h CAPCOM Register 5 Interrupt Control Register 00h CC6IC b FF84h Ch CAPCOM Register 6 Interrupt Control Register 00h CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control Register 00h CC8IC b FF88h CAPCOM Register 8 Interrupt Control Register 00h CC9IC b FF8Ah CAPCOM Register 9 Interrupt Control Register 00h CC10IC b FF8Ch CAPCOM Register 10 Interrupt Control Register 00h CC11IC b FF8Eh CAPCOM Register 11 Interrupt Control Register 00h CC12IC b FF90h CAPCOM Register 12 Interrupt Control Register 00h CC b FF92h CAPCOM Register 13 Interrupt Control Register 00h CC141C b FF94h CAPCOM Register 14 Interrupt Control Register 00h CC15IC b FF96h CAPCOM Register 15 Interrupt Control Register 00h ADCIC b FF98h cch A D Converter End of Conversion Interrupt Control Register 00h ADEIC b FF9Ah A D Converter Overrun Error Interrupt Control Reg 00h TOIC b FF9Ch CAPCOM Timer 0 Interrupt Control Register 00h T1IC b FF9Eh CAPCOM Timer 1 Interrupt Control Register 00h ADCON b FFAOh A D Converter Control Register 0000h P5 b FFA2h Port5 Register read only XXXXh TFR b FFACh Trap Flag Register 0000h WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh SOCON b FFBOh Serial C
8. 317 3040h 318 0040h 318 0000h 68 0000h 68 XX oe 259 0000h 50 UUUUh 264 UUUUh 261 UUUUh 261 0000h 68 0000h 69 0000h 70 0000h 58 0000h 57 0000h 58 UUR 264 UUUUh 262 0000h 70 0200h 69 0000h 107 0000h 111 QOR 115 00h seen 122 00h 126 00h we 129 o sites 59 00h occ 102 00h 101 00h 104 00h 104 OOOOh 106 0000h 110 DON eeen 114 XXXXN wees 119 0000h_ 121 00h een 121 00h 125 00h een 129 0000h 80 DON en 97 00h we 101 0000h 100 DO 100 0000h 48 0000h 79 0000h 241 ST10F269 USER S MANUAL PWMCON1 FF32h 99h PWMIC F17Eh BFh QRO F004h 02h QR1 FOO6h 03h QXO F000h 00h QX1 F002h 01h REG_NAME A16h A8h REG_NAME A16h A8h RPOH F108h 84h RPOH F108h 84h RTCAH EC14h RTCAL EC12h RTCCON ECOOh RTCDH ECOCH RTCDL ECOAh RTCH EC10h RTCL ECOEh RTCPH ECOSh RTCPL ECO6h SOBG FEB4h 5Ah SOCON FFBOh D8h SOEIC FF70h B8 SORBUF FEB2h 59h SORIC FF6Eh B7h SOTBIC F19Ch CE
9. 80 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS Classes with up to 4 members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be established by using a number of adjacent interrupt priorities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now and no request of this class will be accepted The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case The 24 interrupt sources excluding PEC requests are so assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do Table 15 Example software controlled interrupt classes ILVL Priority Interpretation 15 PEC service on up to 8 channels 14 13 12 Interrupt Class 1 8 sources on 2 levels 11 10 A AAA 9 8 Interrupt Class 2 10 source
10. In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable pre scaler which is selected by bit field TSI ky 161 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL The input frequency frg for timer T3 and its resolution ry3 are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula Figure 70 Core timer T3 in timer mode CPU Interrupt Clock Core Timer T3 Request Up Down RER SE T3OUT P3 3 T30E P3 4 T3UDE me fcpu 8 x 2013 8 x 20190 rra us Ke MHz The timer resolutions which result from the selected pre scaler option are listed in the Table 30 This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Table 30 GPT1 timer resolutions Timer Input Selection T2I T31 T41 000b 001b 010b 011b 100b 101b 110b 111b Pre scaler factor 8 16 32 64 128 256 512 1024 Resolution in CPU clock cycles 8 16 32 64 128 256 512 1024 Refer to the device datasheet for a table of timer input frequencies resolution and periods for the range of pre scaler options Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 010b or 011b Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the i
11. 1514131211109876543210 1514131211109876543210 ADCON Y YY YYYYYY YYYYYY ADCIC YYYYYYYY ADEIC WW WWW WWW P5 Port5 Data Register ADCIC A D Converter Interrupt Control Register ADDAT A D Converter Result Register End of Conversion ADDAT2 A D Converter Channel Injection Result Register ADEIC A D Converter Interrupt Control Register ADCON A D Converter Control Register Overrun Error Channel Injection Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space The external analog reference voltages Varner and Vacnp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time as well as the conversion time is programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply 242 340 ky ST10F269 USER S MANUAL ANALOG DIGITAL CONVERTER Figure 129 Analog digital converter block diagram Conversion Interrupt ANO Control Request P5 0 16 Result Register ADDAT Analog Input Channels Converter AN15 P5 15 Varer VAGND 17 1 Mode Selection and Operation The analog input channels ANO AN15 are alternate functions of Port5 which is a 16 bit input only port The Port5 lines may either be used as analog or digital inputs No special action is required to configure the Port5 lines as analo
12. ADDAT Full Read ADDAT axe x 2 4x3 Temp Latch Full ity Channel Injection Request by CC31 GER A E Pe et Write ADDAT2 Wait until ADDAT2 is read ADDAT2 Full Interrupt Request ADEINT Read ADDAT2 a 248 340 ST10F269 USER S MANUAL ANALOG DIGITAL CONVERTER 17 2 Conversion Timing Control The time that the two different actions during conversion take sampling and converting can be programmed within a certain range in the ST10F269 relative to the CPU clock The absolute time that is consumed by the different conversion steps therefore is independent of the general speed of the controller This allows adjusting the A D converter of the ST10F269 to the properties of the system Fast conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and analog supply must be sufficiently low however High internal resistance can be achieved by programming the respective times to a higher value or the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion times are programmed via the upper four bit of register ADCON bit field ADCTC conversion time control selects the basic conversion clock us
13. Accesses to the on chip Real Time Clock are disabled external access performed Address range 00 EC00h 00 ECFFh is only directed to external memory if CAN1EN and CAN2EN are 0 also 1 The on chip Real Time Clock is enabled and can be accessed When both CAN are disabled via XPERCON setting then any access in the address range 00 EEOOh 00 EFFFh will be directed to external memory interface using the BUSCONx register corresponding to address matching ADDRSELx register P4 4 and P4 7 can be used as General Purpose l O when CAN2 is not enabled and P4 5 and P4 6 can be used as General Purpose I O when CAN1 is not enabled The default XPER selection after Reset is identical to XBUS configuration of ST10C167 XCAN1 is enabled XCAN2 is disabled XRAM1 2 Kbytes compatible XRAM is enabled XRAM2 new 8 Kbytes XRAM is disabled Register XPERCON cannot be changed after the global enabling of XPeripherals i e after setting of bit XPEN in SYSCON register In EMUlation mode all the XPERipherals are enabled KPERCON bit are all set When the Real Time Clock is disabled RTCEN 0 the clock oscillator is switch off if ST10 enters in power down mode Otherwise when the Real Time Clock is enabled the bit RTCOFF of the RTCCON register allows to choose the power down mode of the clock oscillator ky 45 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL 4 4 3 The Processor Status word PSW This bit addressab
14. P2 11 CC1110 EX3IN Fast External Interrupt 3 Input P2 12 Ccc1210 EX4IN Fast External Interrupt 4 Input P2 13 CC1310 EX5IN Fast External Interrupt 5 Input P2 14 CC141O EX6IN Fast External Interrupt 6 Input P2 15 CC1510 EX7IN Fast External Interrupt 7 Input T7IN Timer T7 External Count Input Figure 33 Port2 I O and alternate functions Alternate Functions gt a b c P2 15 CC1510 EX7IN T7IN P2 14 Ccc1410 EX6IN P2 13 CC1310 EXSIN P2 12 cc1210 EX4IN P2 11 cc1110 EX3IN P2 10 CC101I0 EX2IN P2 9 Cccolo EX1IN P2 8 ccsio EXOIN Port2 P2 7 cc7lo P2 6 Ccc6lo P2 5 ccsio P2 4 cc4io P2 3 cc3lo P2 2 cc2i0 P2 1 cc1lo P2 0 ccoo General Purpose CAPCOM1 Fast External CAPCOM2 Input Output Capture Input Compare Output Interrupt Input Timer T7 Input a 107 340 PARALLEL PORTS ST10F269 USER S MANUAL The pins of Port2 combine internal capture input bus data with compare output alternate data output before the port latch input Figure 34 Block diagram of a Port2 pin Write ODP2 y Open Drain Latch Read ODP2 y Write DP2 y Direction Latch Read DP2 y Internal Bus Alternate Data Output P2 y po gt N ccylo Output 52 EXxIN Buffer Write Port P2 y Compare Trigger Read P2 y Alternate data input lt 4 Fast external interrupt input 7 5 Port3 If this 15 bit port is used for general purpose I
15. THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL 15 5 3 Compare Mode 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 110b When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to 1 The corresponding Port2 pin is not affected and can be used for general purpose UO However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period In the example below the compare value in register CCx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Figure 117 Compare mode 2 and 3 block diagram Interrupt Capture Register CCx CCxIR Request Comparator CCMODx Input y Interrupt Clock CAPCOM Timer Ty e TyIR Request x 31 0 y 0 1 7 8 Note The port latch and pin remain unaffected in compare mode 2 Figure 118 Timing example for compare mod
16. The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no interrupt requests are accepted by the CPU When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bit in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit 6 2 Operation of the PEC Channels The Peripheral Event Controller PEC of the MCU provides 8 PEC service channels which move a single byte or word between two locations in segment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request from serial channels A D converter etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECC
17. There are two different operating power down modes Protected Power Down Mode Interruptible Power Down Mode The power down mode is selected by bit 5 PWDCFG in SYSCON register SYSCON FF12h 89h SFR Reset Value Oxx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STKSZ ROM SGT BYT CLK WR CS PWD OWD BDR XPEN VISI XPER EN DIS DIS EN CFG CFG CFG Dis STEN BLE SHARE RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no effect To exit Power Down Mode an external reset must occurs by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled Fast External Interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled EXxIN pin Note Register SYSCON cannot be changed after execution of the EINIT instruction 21 2 1 Protected Power Down Mode This mode is selected by setting bit PWDCFG in the SYSCON register to 0 Entering power down mode can only be achieved if the NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontrol
18. User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both byte and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from user stack This mode is available to most instructions with some restrictions For MOV instructions any word GPR can be used as user stack pointer For arithmetic logical and compare instructions only GPRs RO R3 can be used Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer 23 2 Register Banking Register banking provides the user with an extremely fast method to switch user context A single instruction cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated
19. Compare register CC31 of the CAPCOM2 Unit which also sets bit ADCRQ Triggering a channel injection at a specific time on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC31 This can be either the positive negative or both the positive and the negative edge of an external signal In addition this option allows recording the time of occurrence of this signal Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injection mode is enabled or not It is recom mended to always clear bit ADCRQ before enabling the channel injection mode While an injected conversion is in progress no further channel injection request can be triggered The Channel Injection Request flag ADCRQ remains set until the result of the injected conversion is written to the ADDAT2 register If the converter was idle before the channel injection and during the injected conversion the converter is started by software for normal conversions the channel injection is aborted and the converter starts in the selected mode as described above This can be avoided by check ing the busy bit ADBSY before starting a new operation 246 340 ky ST10F269 USER S MANUAL ANALOG DIGITAL CONVERTER After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel Whe
20. However if a crystal is used the emulator device s oscillator can use this crystal only if at least XTAL2 of the original device is disconnected from the circuitry the output XTAL2 will still be active in Adapt Mode Bootstrap loader mode Pin POL 4 BSL activates the on chip bootstrap loader when low during hardware reset The bootstrap loader allows moving the start code into the internal RAM of the ST10F269 via the serial interface ASCO The MCU will remain in bootstrap loader mode until a hardware reset with POL 4 high or a software reset The bootstrap loader acknowledge byte is D5h Default The ST10F269 starts fetching code from location 00 0000h the bootstrap loader is off External bus type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start is selected via pin EA This allows the configuration of the external bus interface of the ST10F269 even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or de multiplexed This bit field may be changed via software after reset if required BTYP Encoding External Data Bus Width External Address Bus Mode 00 8 bit Data De multiplexed Addresses 01 8 bit Data Multiplexed Addresses 10 16 bit Data De multiplexed Addresses 11 16 bit Data Multiplexed Addresses 290 340 ky ST10F269 USER S M
21. Internal Bus 187 340 a ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL Asynchronous Data Frames 8 bit data frames either consist of 8 data bit D7 DO SOM 001b or of 7 data bit D6 DO plus an automatically generated parity bit SOM 011b Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 7 data bit is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 7 Figure 94 Asynchronous 8 bit data frames 1st Start Do D7 bit LSB Parity oa E 9 bit data frames either consist of 9 data bit D8 DO SOM 100b of 8 data bit D7 DO plus an automatically generated parity bit SOM 111b or of 8 data bit D7 DO plus wake up bit SOM 101b Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bit is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in
22. The default XPER selection after Reset is identical to XBUS configuration of ST10C 167 XCAN1 is enabled XCAN2 is disabled XRAM1 2 Kbyte compatible XRAM is enabled XRAM2 new 8 Kbyte XRAM is disabled Register XPERCON cannot be changed after the global enabling of XPeripherals i e after the setting of bit XPEN in the SYSCON register a 253 340 ON CHIP CAN INTERFACES Figure 135 CAN module address map ST10F269 USER S MANUAL EEFOh EEEOh EEDOh EECOh EEBOh EEAOh EE90h EE80h EE70h EE60h EE50h EE40h EE30h EE20h EE10h EE0Oh CAN2 EFFOh EFEOh EFDOh EFCOh EFBOh EFAOh EF90h EF80h EF70h EF60h EF50h EF40h EF30h EF20h EF10h EFOOh CAN1 Message Object 15 Message Object 14 Message Object 13 Message Object 12 Message Object 11 Message Object 10 Message Object 9 Message Object 8 Message Object 7 Message Object 6 Message Object 5 Message Object 4 Message Object 3 Message Object 2 Message Object 1 General Registers CAN Address Area Mask of Last Message EFOCh Global Mask Long EFO8h Global Mask Shion EFO6h Bit Timing Register EFO4h Interrupt Register EFO2h Control Status Regist egister EFOOh General Registers CAN1 EEOCh EE08h EE06h EE04h EE02h EE0Oh CAN2 Control Status Register EE00h EF00h XReg Reset Value XX01h 15 14 13 12 11 10 9 8 7
23. The output of the arithmetic unit goes to the Accumulator It is also possible to saturate the Accumulator on a 32 bit value automatically after every accumulation Automatic saturation is enabled by setting the saturation bit MS in the MCW register When the Accumulator is in the saturation mode and an 32 bit overflow occurs the accumulator is loaded with either the most positive or the most negative value representable in a 32 bit value depending on the direction of the overflow The value of the Accumulator upon saturation is 00 7fff ffffh positive or ff 8000 0000h negative in signed arithmetic Automatic saturation sets the SL flag MSW This flag is a sticky flag which means it stays set until it is explicitly reset by the user 40 bit overflow of the Accumulator sets the SV flag in MSW This flag is also a sticky flag 5 2 6 The 40 bit Adder Subtracter The 40 bit Adder Subtracter allows intermediate overflows in a series of multiply accumulate operations The Adder Subtracter has two input ports One input is the feedback of the 40 bit Signed Accumulator 62 340 ky ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC output through the ACCU Shifter The second input is the 32 bit operand coming from the One bit Scaler The 32 bit operands are sign extended to 40 bit before the addition subtraction is performed The output of the Adder Subtracter goes to the 40 bit Signed Accumulator It is also possible to round and to saturat
24. Timer Counter x is disabled 1 Timer Counter x is enabled Note 1 This selection is available for timers TO and T7 Timers T1 and T8 will stop at this selection The run flags TOR T1R T7R and T8R enable or disable the timers The following description of the timer modes and operation always applies to the enabled state of the timers the respective run flag is assumed to be set to 1 In all modes the timers are always counting upward The current timer values are accessible for the CPU in the timer registers Tx which are non bit addressable SFRs When the CPU writes to a register Tx in the state immediately before the respective timer increment a reload is to be performed the CPU write operation has priority and the increment or reload is disabled to garantee correct timer operation Timer Mode The bit TxM in SFRs TO1CON and T78CON selects the timer mode or the counter mode In timer mode TxM 0 the input clock of a timer is derived from the internal CPU clock divided by a programmable pre scaler The different options of the pre scaler of each timer are selected separately by the bit fields Txl The input frequencies frx for Tx are determined as a function of the CPU clock as follows where Tx represents the contents of the bit field Txl fcpu 21 1 3 fTx E When a timer overflows from FFFFh to 0000h it is reloaded with the value stored in its respective reload register TXREL 218 340 ky ST10F
25. operating mode The busy flag read only ADBSY is set as long as a conversion is in progress The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bit field CHNR of register ADDAT is loaded by the ADC to indicate which channel the result refers to Bit field CHNR of register ADDAT2 is loaded by the CPU to select the analog channel which is to be injected ADDAT FEAORh 50h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES RW RW ADDAT2 FOA0h 50h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES RW RW Bit Function ADRES A D Conversion Result 10 bits CHNR Channel Number 4 bits identifies the converted analog channel A conversion is started by setting bit ADST 1 The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete the 10 bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR is set If bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the current conversion sequen
26. 001 Positive transition rising edge on T5IN 010 Negative transition falling edge on T5IN 011 Any transition rising or falling edge on T5IN 101 Positive transition rising edge of output toggle latch T6OTL 110 Negative transition falling edge of output toggle latch T6OTL 111 Any transition rising or falling edge of output toggle latch T6OTL ky 179 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer Depending on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative transition of T6OTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T6 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T6 can operate in timer gated timer or counter mode in this case see
27. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 196 340 oy ST10F269 USER S MANUAL HIGH SPEED SYNCHRONOUS SERIAL INTERFACE SSCCON FFB2h D9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SSCBM EN 0 MS AREN BEN PEN REN TEN PO PH HB RW RW RW RW RW RW RW RW RW RW RW Bit Function Programming Mode SSCEN 0 SSCBM SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit SSCBM 1 SSCHB SSC Heading Control bit O Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control bit 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control bit 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable bit 0 Ignore receive errors 1 Check receive errors SSCPEN SSC Phase Error Enable bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable bit 0 Ignore baudrate errors 1 Check baudrate errors SSCAREN SSC Automatic Reset Enable bit 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudra
28. Figure 88 GPT2 Capture Reload Register CAPREL in Capture Mode This 16 bit register can be used as a capture register for the auxiliary timer T5 This mode is selected by setting bit T5SC 1 in control register T5CON Bit CT3 selects the external input pin CAPIN or the input pins of timer T3 as the source for a capture trigger Either a positive a negative or both a positive and a negative transition at this pin can be selected to trigger the capture function or transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by bit field Cl in register T5CON The maximum input frequency for the capture trigger signal at CAPIN is fcpy 4 To ensure that a transition of the capture trigger signal is correctly recognized its level should be held for at least 4 CPU clock cycles before it changes When the timer T3 capture trigger is enabled CT3 1 the CAPREL register captures the contents of T5 upon transitions of the selected input s These values can be used to measure T3 s input signals This is useful when T3 operates in incremental interface mode in order to derive dynamic information speed acceleration deceleration from the input signals When a selected transition at the external input pin CAPIN T3IN T3EUD is detected the contents of the auxiliary timer T5 is latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 0000h Th
29. IDX 9 Rwm8 No CoMACMu CoMULus Rwp Rw No CoMACMus CoMULsu CoMACMsu CoMUL CoMACM CoMULu CoMACMu CoMULus CoMACMus CoMULsu CoMACMsu CoMUL rnd CoMACM rnd CoMULu rnd CoMACMu rnd CoMULus rnd CoMACMus rnd CoMULsu rnd CoMACMsu rnd CoMAC Rwy RW No CoMACMR CoMACu IDX 8 Rw 9 Yes CoMACMRu CoMACus Rw RWm Yes CoMACMRus CoMACsu CoMACMRsu CoMAC CoMACMR rnd CoMACu CoMACMRu rnd CoMACus CoMACMRus rnd CoMACsu CoMACMRsu rnd CoMAC rnd CoADD Rwy RWm No CoMACu rnd CoADD2 IDX RW Yes CoMACus rnd CoSUB Rw Rw Yes CoMACsu rnd CoSUB2 CoMACR CoSUBR CoMACRu CoSUB2R CoMACRus CoMAX CoMACRsu CoMIN CoMACR rnd CoLOAD Rwy RWm No CoMACRu rnd CoLOAD IDX RW No CoMACRus rnd CoLOAD2 Rwy RW No CoMACRsu rnd CoLOAD2 CoNOP RWm Yes CoCMP IDX 8 Yes CoSHL RWm Yes IDX Rwm9 Yes CoSHR data4 No CoNEG No CoASHR Rwn8 Yes CoNEG rnd CoASHR rnd CoRND CoABS No CoSTORE Rw CoReg No RW RWm No Rw 8 Coreg Yes I1DX 89 Rwm No CoMOV IDX RWm Yes Rw Rwn9 No 70 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS 6 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10F269 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller These mechanisms include Normal interrupt processing The CPU temporarily suspends the current pro
30. ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal word Operand Access Flag A word operand access read or write to an odd address has been attempted PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid ST10F269 opcode STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN STKOF Stack Overflow Flag The current stack pointer value falls below the content of register STKOV NMI Non Maskable Interrupt Flag A negative transition falling edge has been detected on pin NMI Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware The reset functions hardware software watchdog may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority Trap Priority Il on the 3rd rank are class B traps so a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap on t
31. Indirect addressing provides a mechanism of accessing data referenced by data pointers which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead The PCALL push and call instruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note It is possible to use CALLS within the same segment but still two words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate bank of registers Upon entry into a subroutine it is possible to specify a new set of loc
32. Interrupt Request Reload Register T4 Note 1 Lines only affected by over underflows of T3 but NOT by software modifications of T3OTL Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 101b In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TXIN The capture trigger signal can be a positive a negative or both a positive and a negative transition The two least significant bit of bit field Txl are used to select the active transition see table in the counter mode section while the most significant bit Txl 2 is irrelevant for capture mode It is recommended to keep this bit cleared TxI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops indepen dent of its run flag T2R or TAR ES TA DI 171 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Figure 81 GPT1 auxiliary timer in capture mode Select Capture Register Tx TxIN P3 7 gt Interrupt P3 5 MA Request Txl Input van Interrupt Clock Core Timer T3 T3IR Request Up Down T30UT P3 3 T30E x 2 4 Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are l
33. Latch 7 Read DP3 y Alternate Data Input Write P3 y Port Data P3 Output 5 Output y Port Output Latch Read P3 y Buffer Clock 4 Input z i Alternate Data Input a y 13 11 0 Pin P3 12 BHE WRH is another pin with an alternate output function however its structure is slightly different see Figure 37 After reset the BHE or WRH function must be used depending on the system start up configuration In either of these cases there is no possibility to program any port latches before Thus the appropriate alternate function is selected automatically If BHE WRH is not used in the system this pin can be used for general purpose I O by disabling the alternate function BYTDIS 1 WRCFG 0 Note Enabling the BHE or WRH function automatically enables the P3 12 output driver Setting bit DP3 12 1 is not required During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 Keep DP3 12 0 in this case to ensure floating in hold mode ky 111 340 PARALLEL PORTS ST10F269 USER S MANUAL Figure 37 Block diagram of P3 15 CLKOUT and P3 12 BHE WRH pins Write DP3 x Se bi 1 MUX Direction R 0 Latch Read DP3 x Alternate Function e Enable no a Write P3 x Alternate g Data 3 Output Se P3 12 BHE P3 15 CLKOUT Read P3 x Clock a x 15
34. MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc_SGT LOOP Test whether target has not been found The last entry in the table must be greater than the largest possible target MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc_NET LOOP Test whether target is not found AND the end of table j has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000h a 324 340 ST10F269 USER S MANUAL SYSTEM PROGRAMMING 23 5 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the ST10F269 all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bit in SFRs
35. MUX Read ODP4 x Kegel A lt 4 Write DP4 x q 1 MUX Direction Li Ee T Read DP4 x 5 g 1 Alternate MUX P Function 0 Enable won Write P4 x Alternate 1 Data gt Output MUX Port Output Pax ke P4 x Read P4 x 1 a MUX 0 CANy TxD Data output XPERCON a CANyEN BE y 1 2 CAN Channel 8 z 2 1 XPERCON b A pane GANSEN tO 7 7 Port5 This 16 bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 FFA2h D1h SFR Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function P5 y Port data register P5 bit y Read only ky 117 340 PARALLEL PORTS 7 7 1 Alternate Functions of Port5 Each line of Port5 is also connected to the input multiplexer of the Analog Digital Converter All port lines P5 15 P5 0 can accept analog signals AN15 ANO that can be converted by the ADC No special programming is required for pins that shall be used as analog inputs The upper 6 pins of Port5 also serve as external timer control lines for GPT1 and GPT2 The Table 22 summarizes the alternate functions of Port5 Table 22 Port5 alternate functions Port5 Pin Alternate Function a ST10F269 USER S MANUAL Alternate Function b P5 0 P5 1 P5 2 P5 3 P5 4 P5 5 P5 6 P5 7 P5 8 P5 9 P5 10 P5 11 P5 12 P5 13 P5 14 P5 15 Analog Input ANO Analog Input AN1 Analog Input AN2 Analog Input AN3
36. Note For BUSCONO BTYP is defined via PORTO during reset ALECTLx ALE Lengthening Control 0 Normal ALE signal 1 Lengthened ALE signal BUSACTx Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL RDYENx READY Input Enable 0 External bus cycle is controlled by bit field MCTC only 1 External bus cycle is controlled by the READY input signal RDYPOLx Ready Active Level Control 0 Active level on the READY pin is low bus cycle terminates with a 0 on READY pin 1 Active level on the READY pin is high bus cycle terminates with a 1 on READY pin CSRENx Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is independent of the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command Note BUSCOND is initialized with 0000h if pin EA is high during reset If pin EA is low during reset bit BUSACTO and ALECTLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO a 149 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL ADDRSEL1 FE18h oCh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ RW RW ADDRSEL2 FE1Ah 0Dh
37. PT3E Y Y Y Y Y Y YY YY YYYYYY POUTO P7 0 POUT1 P7 1 POUT2 P7 2 POUT3 P7 3 ODP7 Port7 Open Drain Control Register PPx PWM Period Register x DP7 Port7 Direction Control Register PWx PWM Pulse Width Register x P7 Port7 Data Register PTx PWM Counter Register x PWMIC PWM Interrupt Control Register PWMCONx PWM Control Register 0 1 Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space a 232 340 ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE Figure 122 PWM channel block diagram PPx Period Register A Match Comparator A Clock 1 Input PTx j Up Down Clock 2 oF 16 bit Up Down Counter Clear Control Run E S Math Comparator gt Output Control Lef POUTx A Enable Shadow Register Write Control A III User readable amp writeable register PWx Pulse Width Register x 3 0 16 1 Operating Modes The PWM module provides four different operating modes Mode 0 standard PWM generation edge aligned PWM available on 4 channels Mode 1 Symmetrical PWM generation center aligned PWM available on all four channels Burst mode combines channels 0 and 1 Single shot mode available on channels 2 and 3 Note The output signals of the PWM module are XORed with the outputs of the respective port output latches After reset these latches are cleared so the PWM signals are dir
38. Shift Register Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames so two bytes transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly 12 2 1 Port Control The SSC uses three pins of Port3 to communicate with the external world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operation of these pins depends on the selected operating mode master or slave In order to enable the alternate output functions of these pins
39. Timer PTx is disconnected from its input clock 1 Timer PTx is running PTIx PWM Timer x Input Clock Selection 0 Timer PTx clocked with CLKcpy 1 Timer PTx clocked with CLKcpy 64 PIEx PWM Channel x Interrupt Enable Flag 0 Interrupt from channel x disabled 1 Interrupt from channel x enabled PIRx PWM Channel x Interrupt Request Flag 0 No interrupt request from channel x 1 Channel x interrupt pending must be reset via software ky 239 340 PULSE WIDTH MODULATION MODULE ST10F269 USER S MANUAL PWM Control Register PWMCON1 Register PWMCON1 controls the operating modes and the outputs of the four PWM channels The basic operating mode for each channel standard edge aligned or symmetrical center aligned PWM mode is selected by the mode bit PMx Burst mode channels 0 and 1 and single shot mode channel 2 or 3 are selected by separate control bit The output signal of each PWM channel is individually enabled by bit PENx If the output is not enabled the respective pin can be used for general purpose I O and the PWM channel can only be used to generate an interrupt request PWMCON1 FF32h 99h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS3 PS2 PBO1 PM3 PM2 PM1 PMO PEN3 PEN2 PEN1 PENO RW RW RW RW RW RW RW RW RW RW RW Bit Function PENx PWM Channel x Output Enable bit 0 Channel x output signal disabled generate interru
40. To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via software by setting or clearing user specific bit and conditionally branching based on these specific bit It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur when BCLR BSET or AND OR instruction sequences are used 23 6 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow f
41. as described below mov R13 mem mem gt R13 add R13 1 R13 1 mov mem R13 R13 gt mem DI 57 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL 5 MULTIPLY ACCUMULATE UNIT MAC The MAC is a specialized co processor added to the ST10F269 CPU core to improve the performance of signal processing algorithms It includes A multiply accumulate unit An address generation unit able to feed the MAC unit with 2 operands per cycle A repeat unit to execute a series of multiply accumulate instructions New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per instruction cycle MAC instructions multiply multiply accumulate 32 bit signed arithmetic operations and the CoMOV transfer instruction have been added to the standard instruction set Full details are provided in the ST10 Family Programming Manual 5 1 MAC features Enhanced addressing capabilities Double indirect addressing mode with pointer post modification Parallel Data Move allows one operand move during Multiply Accumulate instructions without penalty CoSTORE instruction for fast access to the MAC SFRs and CoMOV for fast memory to memory table transfer General Two cycle execution for all MAC operations 16 x 16 signed unsigned parallel multiplier 40 bit signed arithmetic unit with automatic saturation mode 40 bit accumulator 8 bit left right shi
42. associated Trap Flag in the TFR register is MACTRP bit 6 of the TFR Remember that this flag must also be reset by the user in the case of an MAC interrupt request As the MAC status flags are updated or eventually written by software during the Execute stage of the pipeline the response time of a MAC interrupt request is 3 instruction cycles see Figure 3 It is the number of instruction cycles required between the time the request is sent and the time the first instruction located at the interrupt vector location enters the pipeline Note that the IP value stacked after a MAC interrupt does not point to the instruction that triggers the interrupt Figure 20 Pipeline diagram for MAC interrupt response time Response Time FETCH DECODE TRAP 1 TRAP 2 ul EXECUTE TRAP 1 TRAP 2 WRITEBACK S Neo TRAP MAC Interrupt Request 5 2 11 Number Representation amp Rounding The MAC supports the two s complement representation of binary numbers In this format the sign bit is the MSB of the binary word This is set to zero for positive numbers and set to one for negative numbers Unsigned numbers are supported only by multiply multiply accumulate instructions which specifies whether each operand is signed or unsigned In two s complement fractional format the N bit operand is represented using the 1 N 1 format 1 signed bit N 1 fractional bits Such a format can represent numbers between 1 a
43. refers to a set of SFRs associated to the peripheral including the port pins which may be used for alternate input output functions including their direction control bits 214 340 ky THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL SFRs and Port Pins associated with the CAPCOM units Figure 110 soeds Aiowaw ua Y4SF U SI Jose pajueuwajduu jou s Jo UoNOUN ou sey 4g uonoun e 0 payu AMAAAALAA 757 ooo oo A KA KK Ae E A ose AAA AAA AA ee en E AE EA OS AMAAMAALAA 757 ooo o 7 AAA AAA AA dek SAO A REA AAA AAA AA AAA AAA AA AMAAAALAA 75 ooo o AAA AAA AA AMAAAALAA 757 ooo co 0OLlLZetps94 860LLL lt LELpLSL 011409 neu la 3 91Le 918299 3 91Z3 91PZI0 3 Ol 910Z99 3 9161 919199 OISL DIZLIO OIL L 91899 RR OIE D1099 39181 A OIZL on SIOL LEQ Je sibay 014 U00 dng ZAOOdVOOILE LO S 0 48 siBay OUD dng LINODAWO 9191009 A Ly 19181694 101 U00 SPON ZNODAVOI 770 J8 SIB9Y jo1U0D POW LNODAVO Leg jete ZINODAVO GU 0 eisen LINODAVO Jetsife X Jeu WOOdVO 19 s 4 peojay x Jaw NODAVO J8 s B9y o1uoy jdneju 8 2 Jeu ZNOOdVO OIBL OIZL 18 siBay Jo1uog Wine 1 0 JOWLL LNOOdVO OILL DIOL ZL YW99 J8 s 69y O1JUOJ 81 pue Seu ZNOOdVO NOOSZL ONOO JaysiBay JOMUOD LL pue OL Seu LWIOOdVO NOOLOL LE oO 31099 19 s B9y eyeq X Od Xd XL 19 sI69y JO1JUOD UO OEIG X HO xda REIH AAA AAA AAA A A A A AAA ZINOO
44. signal High byte Enable alternate function of P3 12 depends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO and PORT1 will operate in the selected bus mode Port4 will output the selected number of segment address lines all zero after reset and Port6 will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 Kbytes are to be performed segmentation may be disabled When the on chip bootstrap loader is activated and sampled during reset pin TxDO alternate function of P3 10 is switched to output mode after the reception of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation Application specific initialization routine After the internal reset condition is removed the ST10F269 fetches the first instruction from location 00 0000h which is the first vector in the trap interrupt vector table the reset vector 4 Words locations 00 0000h through 00 0007h are provided in this table to start the initialization after reset As a rule this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode is activated and sampled during a hardware reset the ST10F269 does not fetch instructions from location 00 0000h but it wait
45. 0 0 Fast external interrupts disabled standard mode EXxIN pin not taken in account for entering exiting Power Down mode O 1 Interrupt on positive edge rising Enter Power Down mode if EXilN 0 exit if EXxIN 1 ref as high active level 1 0 Interrupt on negative edge falling Enter Power Down mode if EXilN 1 exit if EXxIN 0 ref as low active level 1 1 Interrupt on any edge rising or falling Always enter Power Down mode exit if EXxIN level changed EXISEL F1DAh EDh ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXIOSS RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection x 7 0 00 Input from associated Port 2 pin 01 Input from alternate source 10 Input from Port 2 pin ORed with alternate source 11 Input from Port 2 pin ANDed with alternate source EXIxSS Port 2 pin Alternate Source 0 P2 8 CAN1_RxD 1 P2 9 CAN2_RxD 2 P2 10 RTCSI Timed 3 P2 11 RTCAI Alarm 4 7 P2 12 15 Not used zero Exiting Power Down Mode During power down mode the CPU the peripheral clocks and the oscillator and PLL clock are stopped Power down mode can be exited by asserting either RSTIN or one of the enabled EXxIN pins Fast External Interrupt RSTIN must be held low until the oscillator and PLL have stabilized EXxIN inputs are normally sampled interrupt input
46. 0002h if the reset was triggered by the watchdog timer overflow It will be 0000h otherwise The text and the note have been removed Page 247 Row 12 The bit timing is derivated from the XCLK XCLK Fcpu Text has been added Page 270 Row 6 interrupt every RTC basic clock tick instead of second Row 14 from the on chip oscillator clock XTAL1 input instead of high frequency CPU clock Page 278 and 279 In note 4 if a synchronous reset is used as a power up reset must be maintained to 0 at least during two reset sequences 2x 1024 TCL 25 6usat 40MHz CPU clock The sentences have been removed Page 300 Table 56 IDCHIP register reset value is 10DXh instead of 10D1h Page 302 Table 56 QRO QR1 QX0 QX1 registers are ESFR registers E added in Physical address column Page 304 Table 57 QRO QR1 QX0 QX1 registers are ESFR registers E added in Physical address column Page 307 Table 57 QX0 QX1 registers are removed moved to page 303 Page 308 Table 57 ONES register is bit addressable b is added in the name column Page 309 Table 57 WDTCON register is bit addressable b is added in the name column Page 312 REVID bit field is added to the IDCHIP register description ky 337 340 ST10F269 USER S MANUAL REVISION HISTORY 26 2 User s Manual revision 1 2 of 2nd of November 2001 Page 42 Page 95 The reset value of SYSCON register has been changed from 0X00h to Oxx0h some bits of the nibble are
47. 00b However general purpose l O is possible in all cases Note The fast external interrupt inputs are sampled every 8 CPU clock cycles The interrupt request arbitration and processing is executed every 4 CPU clock cycles EXISEL F1DAh EDh ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection x 7 0 00 Input from associated Port 2 pin 01 Input from alternate source 10 Input from Port 2 pin ORed with alternate source 11 Input from Port 2 pin ANDed with alternate source DI 87 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL EXIxSS Port 2 pin Alternate Source 0 P2 8 CAN1_RxD 1 P2 9 CAN2_RxD 2 P2 10 RTCSI Timed 3 P2 11 RTCAI Alarm 4 7 P2 12 15 Not used zero 6 7 Trap Functions Traps interrupt the current execution like standard interrupts do However trap functions offer the possibility to bypass the interrupt system prioritization process in cases where immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The ST10F269 provides two different kinds of trap mechanisms Hardware traps are triggered by events that occur during program execution like illegal access or undefined opcode software traps are initiated via an instruction within the current e
48. 10 9 8 7 6 5 4 3 2 1 0 P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI DIS 15 DIS 14 DIS 13 DIS 12 DIS 11 DIS 10 DIS 9 DIS 8 DIS 7 DIS 6 DIS 5 DIS 4 DIS 3 DIS 2 DIS 1 DIS O RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P5DIDIS y Port 5 Digital Disablel register bit y P5DIDIS y 0 Port line P5 y digital input is enabled Schmitt trigger enabled P5DIDIS y 1 Port line P5 y digital input is disabled Schmitt trigger disabled necessary for input leakage current reduction 7 8 Port6 If this 8 bit port is used for general purpose UO the direction of each line can be configured via the corresponding direction register DP6 Each port line can be switched into push pull or open drain mode via the open drain control register ODP6 P6 FFCCh E6h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function P6 y Port data register P6 bit y ky 119 340 PARALLEL PORTS ST10F269 USER S MANUAL DP6 FFCEh E7h SFR Reset Value 00h 15 144 13 12 WH 10 9 8 7 6 5 4 3 2 41 0 f HIE Ra _ DPe 7 DP6 6 DP6 5 DP6 4 pP6 3 DP6 2 DP6 1 DP6 0 RW RW RW RW RW RW RW PW Bit Function DP6 y Port direction register DP6 bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output ODP6 F1CEh E7h ESFR Reset Va
49. 57 QRO QR1 QX0 QX1 word registers reset value changed from 00h to 0000h IDCHIP reset value has been changed from 10DXh to 10Dnh and n is the device revision text has been added single byte registers changed from 0000h to 00h mentions to ST10F167 have been removed Table 57 b added PICON register as bit addressable EXISEL register physical address has been changed from F1C6h to F1DAh single byte registers changed from 0000h to 00h Table 57 BUSCONO reset value has been changed from OXX0h to 0xx0h SOTBUF reset value changed from 00h to 0000h Table 57 single byte registers changed from 0000h to 00h Table 57 single byte registers changed from 0000h to 00h and MCW register has been added The IDCHIP REVID bit field has been changed from X4 to Xh Index of registers CC10IC CC11IC registers have been added Index of registers SOBG SORBUF SOTBUF SSCBR SSCRB SSCTB registers have been added and reset value of SYSCON register has been changed from OX00h to O0xx0h 26 3 User s Manual revision 1 3 of 6th of November 2001 Page 118 Figure 41 ODP6 DP6 P6 have been changed to ODP4 DP4 P4 respectively 26 4 User s Manual revision 1 4 of 21st of November 2001 Page 17 Page 23 Page 27 Page 243 Page 275 to 280 Page 288 Page 291 Page 317 Page 318 Page 319 Page 329 Section 2 3 2 The memory space of the ST10F269 is organized as a unified memory instead of is configured in a Von Neumann
50. 9 8 7 6 5 4 3 2 1 0 RESERVED INTID R Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt When no interrupt is pending the value will be 00 Table 47 INTID values and Corresponding Interrupt Sources INTID Cause of the Interrupt 00 01 Interrupt Idle There is no interrupt request pending Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a mes sage RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read 02 Message 15 Interrupt bit INTPND in the Message Control Register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 1 2 N Message N Interrupt bit INTPND in the Message Control Register of message object N has been set N 1 14 02 Notes 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to updat
51. A19 A16 on Port4 and A15 A0 on PORTO or PORT1 8 bit segmented mode 16 Mbytes with A23 A16 on Port4 and A15 A0 on PORTO or PORT1 Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks ky 33 340 MEMORY ORGANIZATION ST10F269 USER S MANUAL The ST10F269 also supports four different bus types Multiplexed 16 bit Bus with address and data on PORTO Default after Reset Multiplexed 8 bit Bus with address and data on PORTO POL De multiplexed 16 bit Bus with address on PORT1 and data on PORTO De multiplexed 8 bit Bus with address on PORT1 and data on POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control See Chapter 9 The External Bus Interface External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address For PEC data transfers the external memory in segment O can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore it is not bit addressable 3 5 Crossing Memory Boundaries The address space of the ST10F269 is implicitly di
52. AA AAA AAA AAA A AAA A 9NIO AA AAA AAA AAA A AAA A SINOO AA AAA AAA AAA A AAA A PWC AAA AAA AAA A A A A AAA ECO AA AAA AAA AAA A AAA A rojo AA AAA AAA AAA A AAA A HNO AAAAAAAAAAAAAAAA OC AAA AAA AAA AA A A A A A NOOBZL AAA AAA AA AAA A A A A A NOOLOL OLCEVGILBEOLIECLEL VI SL sJa si6ay o1uoy S9 860L LLcLEL VISE s19 sib9y gq 19 sIB9y 04JUOJ ueq uedO X Hod Xdqdo b 8299 Daa 2 02990 61 999 GL 11 899 2799 099 37398 381 37348241 341 META LL 73840 OL LLd OILED0 P Ld Ol8ZO9 LHId OIZZ99 VHF d Olve99 8d O1 299 0 8d O19199 GL 3d 01SL99 0 2d4 010909 8d 8da 3 8ddo ld dd 34400 Ed Ed 3 ddo Zd AAAAAAAAAAAAAAAA zda AAAAAAAAAAAAAA A A 32dd0 ios ARAA p o po e Hi r AAAA coco aHa OLZets9Z8560LLL lt LELpLSL SUOOUD aJeusay 04JUOD UOOA Y SHOq 215 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL A CAPCOM unit handles high speed I O tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 16 software timers The maximum resolution of the CAPCOM units is calculated with the formula in Chapter Section 15 1 CAPCOM Timers and is specified in the device datasheet Each CAPCOM unit consists of tw
53. ASCO Transmit Interrupt Control Register SORIC ASCO Receive Interrupt Control Register SOTBIC ASCO Transmit Buffer Interrupt Control Register SOEIC ASCO Error Interrupt Control Register Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space The operating mode of the serial channel ASCO is controlled by its bit addressable control register SOCON This register contains control bit for mode and error check selection and status flags for error identification 184 340 iy ST10F269 USER S MANUAL ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE SOCON FFBOh D8h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOR SOLB SOBRS S0ODD SOOE SOFE SOPE SOOEN SOFEN SOPEN SOREN SOSTP SOM RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function SOM ASCO Mode Control 000 8 bit data synchronous operation 001 8 bit data asynchronous operation 010 Reserved Do not use this combination 7 bit data parity asynchronous operation 9 bit data asynchronous operation 8 bit data wake up bit asynchronous operation Reserved Do not use this combination 8 bit data parity asynchronous operation ch sch ch CH 200 2010 SOSTP Number of Stop bit Selection asynchronous operation O One stop bit 1 Two stop bit SOREN Receiver Enable bit O Receiver disabled 1 Receiver enabled Reset by hardware
54. All three timers of block GPT1 T2 T3 T4 can run in 3 basic modes timer gated timer and counter mode and all timers can count either up or down Each timer has an associated alternate input function pin on Port3 which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down can be programmed by software or can be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 can be indicated on an alternate output function pin The auxiliary timers T2 and T4 can additionally be concatenated with the core timer or used as capture or reload registers for the core timer In incremental interface mode the GPT1 timers T2 T3 T4 can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD Direction and count signals are internally derived from these two input signals so the contents of the respective timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 located in the non bit addressable SFR space When any of the timer registers is written to by the CPU in the state immediately before a timer increment decrement reload or capture the CPU write operation has priority This is to guara
55. Analog Input AN4 Analog Input AN5 Analog Input ANG Analog Input AN7 Analog Input AN8 Analog Input AN9 Analog Input AN10 Analog Input AN11 Analog Input AN12 Analog Input AN13 Analog Input AN14 Analog Input AN15 T6EUD Timer 6 external Up Down Input T5EUD Timer 5 external Up Down Input T6IN Timer 6 Count Input T5IN Timer 5 Count Input T4EUD Timer 4 external Up Down Input T2EUD Timer 2 external Up Down Input Figure 42 Port5 UO and alternate functions Alternate Functions gt P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 P5 9 P5 8 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 General Purpose Input 118 340 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 ANG ANS ANA AN3 AN2 AN1 ANO A D Converter Input Timer Inputs a ST10F269 USER S MANUAL PARALLEL PORTS Port5 pins have a special port structure see Figure 43 first because it is an input only port and second because the analog input channels are directly connected to the pins rather than to the input latches Figure 43 Block diagram of a Port5 pin Channel Select Analog to Sample Hold Switch ve Circuit P5 y ANy a 3 Read Port P5 y Clock S Read dE y 15 0 7 7 2 Port 5 Schmitt Trigger Analog Inputs A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register P5DIDIS P5DIDIS FFA4h D2h SFR Reset Value 0000h 15 14 13 12 11
56. Bus idle no Received frame with same identifier as this message object yes yes MSGLST 1 be Store message NEWDAT 1 TXRQ 0 RMTPND 0 INTPND 1 O reset 1 set a 265 340 ON CHIP CAN INTERFACES Figure 141 CPU handling of the last message object ST10F269 USER S MANUAL 266 340 Power Up Initialisation Process Start Process Process End All bit undefined RXIE application specific INTPND 0 RMTPND 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific 0 reset 1 set Process message contents NEWDAT 0 Restart Process ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Figure 142 CPU handling of message objects in receive direction Power Up All bit undefined TXIE application specific O reset RXIE application specific 1 set INTPND 0 RMTPND 0 TXRQ 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 Initialisation XTD application specific NEWDAT 0 Process message contents Process Start Process Process End Restart Process Request update 267 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL Figu
57. Current TRAP Instruction 00 01FCh 00h 7Fh CPU in steps of 4h Priority The Table 13 lists the vector locations for hardware traps and the corresponding status flags in register TFR It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000h Reset conditions have priority over every other system activity and therefore have the highest priority trap priority III Software traps may be initiated to any vector location between 00 0000h and 00 01F Ch A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests 6 1 1 Normal Interrupt Processing and PEC Service At each instruction cycle among all the sources which require a PEC or an interrupt processing only the one with the highest priority is selected The priority of interrupts and PEC requests is programmable in two levels Each requesting source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous re
58. ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S e S S 4 T8IR T8IE ILVL GLVL RW RW RW RW Note Refer to the General Interrupt Control Register description for an explanation of the control fields 15 3 Capture Compare Registers The 16 bit capture compare registers CCO through CC31 are used as data registers for capture or compare operations with respect to timers TO T1 and T7 T8 The capture compare registers are not bit addressable Each of the registers CCO CC31 may be individually programmed for capture mode or one of 4 different compare modes except for CC24 CC27 and may be allocated individually to one of the two timers of the respective CAPCOM unit TO or T1 and T7 or T8 respectively A special combination of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage The functions of the 32 capture compare registers are controlled by the 8 mode control registers named CCMO0 CCM7 which are all organized identically see description below These 16 bit registers are bit addressable Each register contains bit for mode selection and timer allocation of four capture compare registers 220 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS Capture compare mode registers for the CAPCOM1 unit CCO CC15
59. FFFFh 02 0000h to 02 FFFFh 64K 5 03 0000h to 03 FFFFh 03 0000h to 03 FFFFh 6 04 0000h to 04 FFFFh 04 0000h to 04 FFFFh ST10F269 USER S MANUAL MEMORY ORGANIZATION Code fetches are always made on even byte addresses The highest possible code storage location in the internal Flash is either xx xxFEh for single word instructions or xx xxFCh for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal Flash to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for internal Flash operands Any word data access is made to an even byte address The highest possible word data storage location in the internal Flash is xx xxFEh For PEC data transfers the internal Flash can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The internal Flash is not provided for single bit storage and therefore it is not bit addressable The internal Flash may be mapped into segment 0 or segment 1 under software control Handling the internal Flash Section 23 10 Handling the Internal Flash describes the mapping procedures and precautions 3 2 Internal RAM and SFR Area The RAM SFR area is located within data page 3 and provides access to the 2 Kbyte Internal
60. For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate additional 4 bit value Figure 16 Register bank selection via register CP Internal RAM CP 30 CP 28 Context Pointer CP 2 CP 52 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Figure 17 Implicit CP use by short GPR addressing modes Specified by register or bitoff 1111 4 bit GPR Address Internal Control Must be within the internal RAM area For byte GPR For word GPR accesses accesses 4 4 8 The Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of register SP is tied to 0 and bit 15 through 12 are tied to 1 by hardware the SP register can only contain values from FOOOh to FFFEh This allows to access a physical stack within the internal RAM of the MCU A virtual stack usually bigger can be realized via software This mechanism is supported by registers STKOV and STKUN see respective descriptions below The SP reg
61. Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 16 Mbytes of external memory can be connected to the microcontroller via its external bus interface The integrated External Bus Controller EBC allows flexible access to external memory and or peripheral resources For up to five address areas the bus mode multiplexed de multiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle wait states signal delays can be selected independently This allows access to a variety of memory and peripheral components directly and with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following four different external access modes 16 18 20 24 bit Addresses and 16 bit data de multiplexed 16 18 20 24 bit Addresses and 8 bit data de multiplexed 16 18 20 24 bit Addresses and 16 bit data multiplexed 16 18 20 24 bit Addresses and 8 bit data multiplexed The de multiplexed bus modes use PORT1 for addresses and PORTO for data input output The multiplexed bus modes use PORTO for both addresses and data input output All modes use Port 4 for the upper address lines A16 if selected Important timing characteristics of the external bus interface wait states ALE length and Read Write Delay have been made programmable to give the user
62. O the direction of each line can be configured by the corresponding direction register DP3 Most port lines can be switched into push pull or open drain mode by the open drain control register ODP3 pins P3 15 P3 14 and P3 12 do not support open drain mode Due to pin limitations register bit P3 14 is not connected to an output pin P3 FFC4h E2h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P3 15 P3 13 P3 12 P3 11 P3 10 P3 9 P3 8 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function 108 340 oy ST10F269 USER S MANUAL PARALLEL PORTS DP3 FFC6h E3h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP3 15 DP3 13 DP3 12 DP3 11 DP3 10 DP3 9 DP3 8 DP3 7 DP3 6 DP3 5 DP3 4 DP3 3 DP3 2 DP3 1 DP3 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function DP3 y Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output ODP3 F1C6h E3h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function ODP3 y Port3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in open drain mode 7 5 1 Alternate Functions of Port3 The pins of Port3 are used for various functions which include e
63. P8 FFD4h EAh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function P8 y Port data register P8 bit y DP8 FFD6h EBh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function DP8 y Port direction register DP8 bit y DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output ODP8 F1D6h EBh ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function ODP8 y Port8 Open Drain control register bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode 7 10 1 Alternate Functions of Port8 All Port8 lines P8 7 P8 0 support capture inputs or compare outputs CC2310 CC1610 for the CAPCOM2 unit see Table 25 The use of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port2 lines As all other capture inputs the capture input function of pins P8 7 P8 0 can also be used as external interrupt inputs with a sample rate of 8 CPU clock cycles Table 25 Port8 alternate functions Port8 Pin Alternate Function P8 0 CC16l0 Capture input compare output channel 16 P8 1 CC17I0 Capture input compare output channel 17 P8 2 CC18IO Capture input compare out
64. RW RW RW RW RW RW RW Notes 1 EXI2ES and EXI3ES must be configured as 01b because RCT interrupt request lines are rising edge active 2 Alarm interrupt request line RTCAI is linked with EXI3ES 3 Timed interrupt request line RTCSI is linked with EXI2ES EXISEL ESFR enables the Port2 alternate sources RTC interrupts are alternate sources 2 and 3 EXISEL F1DAh ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS 2 EXI2SS 3 EXI1SS EXI0SS RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection x 7 0 00 Input from associated Port 2 pin 01 Input from alternate source 1 1 10 Input from Port 2 pin ORed with alternate source 11 Input from Port 2 pin ANDed with alternate source Notes 1 Advised configuration 2 Alarm interrupt request RTCAI is linked with EXI3SS 3 Timed interrupt request RTCSI is linked with EXI2SS DI 277 340 REAL TIME CLOCK ST10F269 USER S MANUAL Interrupt control register are common with CAPCOM1 Unit CC10IC RTCSI and CC11IC RTCAI CC10IC CC111C SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCxIR CCxIE ILVL GLVL RW RW RW RW CC10IC FF8Ch C6h CC111C FF8Eh C7h Source of interrupt Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External interrupt 2 CC10IR CC10lE CC10INT 00 0068h 1Ah 26 External inter
65. SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ RW RW ADDRSEL3 FE1Ch 0Eh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Presa TI nee O RW RW ADDRSEL4 FE1Eh 0Fh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ RW RW Bit Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See Table 27 RGSAD Range Start Address Defines the upper bit of the start address A23 of the respective address area See Table 27 Note Register BUSCONO controls the complete external address space except for the 4 windows supported by BUSCON1 to BUSCON4 So there is no need of ADDRSELO register 9 4 1 Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow to define 4 separate address areas within the address space of the ST10F269 Within each of these address areas external accesses can be controlled by one of the four different bus modes independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register in a way cuts out an address window within which the parameters in register BUSCONx are used to control external accesses The range start address of such a window defines the upper address bit which are not used within the address window of the specified size see Table 27 150 340 OI ST10F269 USER S MANUAL THE EXTERNAL B
66. ST10F269 uses timer T6 to measure the length of the initial zero byte The quantization uncertainty of this measurement implies the first deviation from the real Baud rate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association f T6 36 9 CPU 75 16 x By ost For a correct data transfer from the host to the ST10F269 the maximum deviation between the internal initialized Baud rate for ASCO and the real Baud rate of the host should be below 2 5 The deviation Fp in percent between host Baud rate and ST10F269 Baud rate can be calculated via the formula below SOBRL Bcontr e BHost Face B Bcontr x 100 Fn lt 2 5 B Note Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This Baud rate deviation is a nonlinear function depending on the CPU clock and the Baud rate of the host The maxima of the function Fg increase with the host Baud rate due to the smaller Baud rate pre scaler factors and the implied higher quantization error see Figure 109 The minimum Baud rate Dy ow in the Figure 109 is determined by the maximum count capacity of timer T6 when measuring the zero byte and it depends on the CPU clock Using the maximum T6 count 216 in the formula the minimum Baud rate can be calculated The lowest standard Baud rate in this case would be 1200 Baud Ba
67. The asynchronous READY READY AREADY AREADY is less restrictive but requires additional wait states caused by the internal synchronization As the asynchronous READY READY is sampled earlier see Figure 62 programmed wait states may be necessary to provide proper bus cycles see also notes on normally ready peripherals below Figure 62 READY READY controlled bus cycles Bus Cycle with active READY or READY Bus Cycle Extended via READY or READY lt gt lt gt l l l l l l 1WS 2WS 1WS 2WS ALE A a ESA Pa RD WR E pe al e vow TINA Ga A A A A Sa E ES d AREADY A y a a A pa LITIO EA A A A AREADY HITA UA AA EE l l A A A A Evaluation sampling of the READY READY input A READY READY signal especially asynchronous READY READY that has been activated by an external device may be deactivated in response to the trailing rising edge of the respective command RD or WR Note When the READY READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY READY signal Otherwise the con troller hangs until the next reset A time out function is only provided by the watchdog timer Combining the READY function with predefined wait states is advantageous in two cases Memory components with a fixed access time
68. These execution times apply to most of the ST10F269 instructions except some of the branches the multiplication the division and a special move instruction In case of internal Memory program execution there is no execution time dependency on the instruction length except for some special branch situations Because of the short execution time execution from internal RAM is flexible for loadable and modifiable code Execution from external memory depends on the selected bus mode and the programming of the bus cycles wait states The operand and instruction accesses listed below can extend the execution time of an instruction Internal Flash Memory operand reads same for byte and word operand reads Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Jumps to non aligned double word instructions in the internal Flash Memory space Testing Branch Conditions immediately after PSW writes 4 4 CPU Special Function Registers The CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU operations code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs
69. Timer T6 Run bit If T R 0 the timer stops Setting T6R to 1 will start the timer In gated timer mode the timer will only run if T R 1 and the gate is active high or low as programmed Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T6EUD Timer T6 External Up Down Control Input which is the alternate input function of port pin P5 10 These options are selected by bit T6UD and T6UDE in control register T6CON When the up down control is done by software bit T6 UDE 0 the count direction can be altered by setting or clearing bit T6UD When T6UDE 1 pin T6EUD is selected to be the controlling source of the count direction However bit T6UD can still be used to reverse the actual count direction as shown in the Table 34 If T6UD 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is counting down If T6UD 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not Table 34 GPT2 core timer T6 count direction control Pin TxEUD Bit TXUDE Bit TxUD Count Direction Xx 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T6
70. Timers TO T1 T7 T8 10 2 1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bit addressable control register T6CON T6CON FF48h A4h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6SR s S S T6OTL T6OE T6UDE T6UD T6R TOM Tei RW RW RW RW RW RW RW RW Bit Function T6l Timer 6 Input Selection Depends on the Operating Mode see respective sections T6M Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XxX Reserved Do not use this combination T6R Timer 6 Run bit T6R 0 Timer Counter 6 stops T6R 1 Timer Counter 6 runs T6UD Timer 6 Up Down Control T6UDE Timer 6 External Up Down Enable 174 340 ky ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Bit Function T6OE Alternate Output Function Enable T6OE 0 Alternate Output Function Disabled T6OE 1 Alternate Output Function Enabled T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software T6SR Timer 6 Reload Mode Enable T6SR 0 Reload from register CAPREL Disabled T6SR 1 Reload from register CAPREL Enabled Note 1 For the effects of bit T6UD and T6UDE refer to the direction Table 34 Timer 6 run bit The timer can be started or stopped by software through bit T6R
71. Timing Control 148 9 4 CONTROLLING THE EXTERNAL BUS CONTROLLER A 149 9 4 1 Definition of Address Areas oooomoccccnnnnncccccncnnncnccnnannnnnnnn naar nn cnn nne rre 152 9 4 2 Address Window Arbitration 153 9 4 3 Precautions and Him EE ote seed 154 9 5 EBC IDLE E A ET 155 9 6 EXTERNAL BUS ARBITRATION icciccccccnnccnonnnnnnnncnnonnnanonnnnnnnn nn cnn rca nan cn rare na rinnnncnnnss 155 9 6 1 Connecting Bus Masters 0 cccceceeeceeeeneeeeeeeee tees eeeeaeeeeeeeeseaeeseaeeseaeeeseaeeetiaeeeneaeeens 156 9 6 2 Entering the Hold State cti tee eaten a 156 9 6 3 Exiting the Hold State ooocoonccconincccnnncccnncccnonnncconananonn cnn rannn nro carac narnia 157 9 7 THE XBUSINTERFACE oir radar ida arias 158 10 THE GENERAL PURPOSE TIMER UNITS ooooocccocccccccccccnonncccnnncccnnnnoncnannnnnnannnnnnnenennnns 160 10 1 TIMER BLOCK GETT ster EEN NENNEN 160 10 1 1 GPTT Core Timer T3 TEE 162 10 1 2 GPT1 Auxiliary Timers T2 and TA 169 10 1 3 Interrupt Control for GPT1 Times 174 10 2 TIMER BLOCK GP Tata a Aliado ae 175 10 2 1 GPT2 Core Timer Orusco a 176 10 2 2 Interrupt Control for GPT2 Timers and CAPEL 185 5 340 ky ST10F269 USER S MANUAL 11 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ecccccnccciccccccinnnncnancnnnnnos 186 11 1 ASYNCHRONOUS OPERATION coran ca rann cn narrar r cc nnnnnn 189 11 2 SYNCHRONOUS OPERATION A 192 11 3 HARDWARE ERROR DETECTION nc nana aaah iaai 193 11 4 ASCO BAUD RATE GENERATION 193 11 5 ASCO INTERRUPT C
72. architecture Rows the CAPCOM2 unit instead of CPACOM2 Row 1 the memory space of the ST10F269 is organized as a unified memory instead of is configured in a Von Neumann architecture Row 15 This Flash area can be remapped instead of this ROM area Figure 127 PWMCON1 PENx bits are added The chapter title at the top of the page is REAL TIME CLOCK instead of ON CHIP INTERFACES Reset value of SYSCON and BUSCONO is 0xx0h instead of OXXOh Footnotes of RPOH register description have been updated or modified note 3 and 4 have been added IDMANUF description has been updated 020h instead of 0400h and IDCHIP is mentionned for ST10F269 instead of ST10F269 Q3 IDMEM is mentionned for ST10F269 instead of ST10F269 Q3 Row 17 External memory data access the ST10F269 provides a unified memory architecture instead of the ST10F269 provides a Von Neumann Row 26 Mapping the internal Flash area instead of Mapping the internal ROM area 26 5 User s Manual revision 2 of 25th of September 2013 Page 340 ky Updated Disclaimer 339 340 ST10F269 USER S MANUAL Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST
73. are ordered in two ways Ordered by address to check which register a given address references Ordered by register name to find the location of a specific register 22 1 Register Description Format In the following chapters the function and the layout of the SFRs is described in a specific format The example below explains this format A word register looks like this REG_NAME A16h A8h SFR ESFR XReg Reset Value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res write hw read std hw bitfield bitfield Bit Function bit field name Explanation of bit field name Description of the functions controlled by this bit field A byte register looks like this REG_NAME A16h A8h SFR ESFR XReg Reset Value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MN E stabit hw bit bit field bit field RW RW RW RW Elements REG_NAME Name of this register A16h A8h Long 16 bit address Short 8 bit address SFR ESFR XReg Register space SFR ESFR or External XBUS Register OP a Register contents after reset 0 1 defined X undefined undefined X after power up U unchanged hwbit bit that are set cleared by hardware are written in bold ky 299 340 REGISTER SET ST10F269 USER S MANUAL 22 2 General Purpose Registers GPRs The GPRs form the register bank that the CPU works with This register bank may be located anywhere within
74. are used for general purpose l O The two bits are latched in register RPOH Default All 5 chip select lines active CS4 C SO CSSEL Chip Select Lines Note 11 Five CS4 CSO Default without pull downs 10 None Port6 pins free for I O 01 Two CS1 CSO 00 Three CS2 CSO Note The selected number of CS signals cannot be changed via software after reset Segment address lines Pins POH 4 and POH 3 SALSEL define the number of active segment address lines during reset This determines which pins of Port4 are used as address line or as l O line The two bits are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior programming The required pins of Port4 are automatically switched to address output mode SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 Kbytes Default without pull downs 10 Eight A23 A16 16 Mbytes Maximum 01 None 64 Kbytes Minimum 00 Four A19 A16 1 Mbyte Even if not all segment address lines are enabled on Port4 the ST10F269 internally uses its complete 24 bit addressing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A16
75. byte and bit in a byte organized memory xxxx6h 15 14 Bit 8 Xxxx5h 716 se Bit 0 xxxx4h Byte xxxx3h Byte xxxx2h Word high byte xxxx1h Word low byte xxxx0h XXXXFh ia va Note Byte units forming a single word or a double word must always be stored within the same phys ical internal external Flash RAM and organizational page segment memory area 3 1 Internal Flash The ST10F269 reserves an address area of 256 Kbytes for on chip Flash memory In standard mode the normal operating mode the Flash appears like an on chip ROM with the same timing and functionality The Flash module offers a fast access time allowing zero wait state access with CPU frequency up to 40 MHz Instruction fetches and data operand reads are performed with all addressing modes of the ST10F269 instruction set In order to optimize the programming time of the internal Flash blocks of 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes can be used But the size of the blocks does not apply to the whole memory space see details in Table 3 Table 3 256 Kbyte Flash memory block organization 26 340 Block Addresses Segment 0 Addresses Segment 1 Size byte 0 00 0000h to 00 3FFFh 01 0000h to 01 3FFFh 16K 1 00 4000h to 00 5FFFh 01 4000h to 01 5FFFh 8K 2 00 6000h to 00 7FFFh 01 6000h to 01 7FFFh 8K 3 01 8000h to 01 FFFFh 01 8000h to 01 FFFFh 4 02 0000h to 02
76. can only contain values from FOOOh to FFFEh STKUN FE16h 0Bh SFR Reset Value FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 STKUN 0 R R R R RW R Bit Function STKUN Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP gt STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine 54 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are given in Chapter 23 System Programming Scope of stack limit control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit CALL or RET instructions This control mechanism is not triggered and no stack trap is generated when the stack pointer SP is directly updated via MOV instructions the limits of the stack area STKOV STKUN are chan
77. complete systems for testing or calibration or to load a programming routine for Flash devices The BSL mechanism can be used for standard system startup as well as for special occasions like system maintenance firmer update or end of line programming or testing Entering the bootstrap loader The ST10F269 enters BSL mode when pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM No part of the standard mask Memory or Flash Memory area is required for this After entering BSL mode and the respective initialization the ST10F269 scans the RXDO line to receive a zero byte one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the corresponding Baud rate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this Baud rate an identification byte is returned to the host that provides the loaded data This identification byte identifies the device to be booted Refer to the datasheet for specific device information Figure 106 Bootstrap loader sequence Internal Boot Memory BSL routine 32 byte user software 4 2 Zero byte 1 start bit eight 0 data bits 1 stop bit sent by host 3 4 BSL initialization time Identification byte D5h sent by ST10
78. configuration and the accessibility of the ST10F269 s memory areas after reset in Bootstrap Loader mode differs from the standard case Pin EA is not evaluated when BSL mode is selected and accesses to the internal Flash area are partly redirected while the ST10F269 is in BSL mode see Figure 108 All code fetches are made from the special Boot ROM while data accesses read from the internal user Flash Data accesses will return undefined values on ROMless devices The code in the Boot ROM is not an invariant feature of the ST10F269 User software should not try to execute code from the internal Flash area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal Flash area is mapped to segment 1 see Figure 108 Figure 107 Hardware provisions to activate the BSL 4 External l Signal l r 1 O Normal Boot O O BSL l RpoL 4 Baak l 8kQ max 8kQ max L E EA f hall 7 Circuit 2 Circuit 1 210 340 ky ST10F269 USER S MANUAL BOOTSTRAP LOADER Figure 108 Memory configuration after reset 16 Mbyte 16 Mbyte 16 Mbyte N N N access to access to external Z external Depends on reset bus bus configuration disabled enabled ado int int 4 RAM RAM RAM o 0 0 8 E ES to g SI
79. description for each available package are not covered in this manual but are listed in the specific device Data Sheets Before starting on a new design verify the device characteristics and pinout with an up to date copy of the device Data Sheet The ST10F269 software and hardware development tools include Compilers C C Macro Assemblers Linkers Locators Library Managers Format Converters from Tasking amp Keil HLL debuggers Real Time operating systems In Circuit Emulators based on bondout ST chips from Hitex Lauterbach Nohau Logic Analyzer disassemblers Evaluation Boards with monitor programs from FORTH Industrial embedded flash programming software from PLS Network driver software CAN September 2013 9 340 ST10F269 USER S MANUAL 1 1 Abbreviations The following abbreviations and acronyms are used in this User s Manual ADC ALE ALU ASC BRG CAN CAPCOM CISC CMOS CPU EBC ESFR Flash GPR GPT HLL IRAM 1 0 PEC PLA PLL PWM RAM RISC ROM SFR SSC XBUS XRAM 10 340 Analog Digital Converter Address Latch Enable Arithmetic and Logic Unit Asynchronous synchronous Serial Controller Baud Rate Generator Controller Area Network License Bosch CAPture and COMpare unit Complex Instruction Set Computing Complementary Metal Oxide Silicon Central Processing Unit External Bus Controller Extended Special Function Register Non volatile memory that may be ele
80. different interfaces within the same system while optimizing accesses to each of them Note BUSCON4 BUSCONO bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and interrupts SYSCON FF12h 89h SFR Reset Value Oxx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STKSZ ROM SGT ROM BYT CLK WR CS PWD OWD BDR XPEN VISI XPER S1 DIS EN DIS EN CFG CFG CFG DIS STEN BLE SHARE RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable bit 0 Accesses to the on chip XRAM are disabled external bus cycles instead 1 External bus cycles are executed for accesses to the XRAM area BDRSTEN Bidirectional Reset Enable 0 RSTIN pin is an input pin only SW Reset or WDT Reset have no effect on this pin 1 RSTIN pin is a bidirectional pin This pin is pulled low during 1024 TCL during reset sequence OWDDIS Oscillator Watchdog Disable Control 0 Oscillator Watchdog OWD is enabled If PLL is bypassed the OWD monitors XTAL1 activity If there is no activity
81. during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 322 340 ky ST10F269 USER S MANUAL SYSTEM PROGRAMMING 23 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the system stack before and after a subroutine is executed Procedures may be called conditionally with instructions CALLA or CALLI or be called unconditionally using instructions CALLR or CALLS Note Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine
82. execute single predefined data transfers there are no conditional PEC trans fers PEC service can only be used if the respective request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN Module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request The Interrupt Identifier INTID a number in the Interrupt Register indicates the cause of an interrupt When no interrupt is pending the identifier will have the value OOh If the value in INTID is not 00h then there is an interrupt pending If bit IE in the Control Register is set also the interrupt line to the CPU is activated The interrupt line remains active until either INTID gets OOh after the interrupt requester has been serviced or until IE is reset if interrupts are disabled The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one The Table 47 lists the valid values for INTID and their corresponding interrupt sources 256 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Interrupt Register EF02h EE02h XReg Reset Value XXh 15 14 13 12 11 10
83. external bus cycle if this bus cycle either does not use READY or if READY is sampled active low after the programmed wait states When READY is sampled inactive high after the programmed wait states the running external bus cycle is aborted Then the internal reset sequence is started At the end of the internal reset sequence 1024 TCL only P0 12 P0 6 bit are latched while previously latched values of PO 5 P0 2 are cleared 20 5 RSTOUT Pin and Bidirectional Reset The RSTOUT pin is driven active low level at the beginning of any reset sequence synchronous asynchronous hardware software and watchdog timer resets RSTOUT pin stays active low beyond the end of the initialization routine until the protected EINIT instruction End of Initialization is completed The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin because RSTOUT signal lasts during initialisation It is for instance the case of external memory running initialization routine before the execution of EINIT instruction Bidirectional reset function is enabled by setting bit 3 BDRSTEN in SYSCON register It only can be enabled during the initialization routine before EINIT instruction is completed 282 340 ky ST10F269 USER S MANUAL SYSTEM RESET When enabled the open drain of the RSTIN pin is activated pulling down the reset signal for the duration of the internal reset
84. external bus interface is enabled but no external access is currently executed the EBC is idle As long as only internal resources from an architecture point of view like IRAM GPRs or SFRs etc are used the external bus interface does not change see Table 28 Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see Table 28 The address mentioned above includes Port Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals on Port 6 are driven inactive high because the EBC switches to an internal XCS signal The external control signals RD and WR or WRL WRH if enabled remain inactive high see Table 28 Table 28 Status of the external bus interface during EBC idle state Pins Internal accesses only XBUS accesses PORTO Tristate floating Tristate floating for read accesses XBUS write data for write accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface Port A Last used external segment address Last used XBUS segment address on selected pins on selected pins Port6 Active external CS signal corresponding to last Inactive
85. external device has released the bus after deactivation of the read command RD The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducing a wait state after the previous bus cycle see Figure 60 During this memory tri state time wait state the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tri state time wait state requires one CPU clock and is controlled via the MTTCx bit of the BUSCON registers A wait state will be inserted if bit MTTCx is 0 default after reset External bus cycles in multiplexed bus modes implicitly add one tri state time wait state in addition to the programmable MTTC wait state Any MTTC wait states are applicable to both read and write cycles Figure 60 Memory tri state time VW Bus Cycle gt Segment l l I I Address I I I l E I l I I I l l ALE VA i e ee l I l I WW I I I I I I Bus Po TX as XL TE T_T I oi A e E Mk co ee ee A ees mee A MTTC Wait State ky 143 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL 9 3 4 Read Write Signal Delay The ST10F269 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the
86. failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset The Watchdog Timer is a 16 bit timer clocked with the system clock divided either by 2 or by 128 The high byte of the watchdog Timer register can be set to a pre specified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded 2 5 9 Capture Compare CAPCOM Units The two CAPCOM units support generation and control of timing sequences on up to 32 channels The CAPCOM units are typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PMW Digital to Analog D A conversion software timing or time recording relative to external events Four 16 bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several pre scaled values of the internal system clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external count inputs for CAPCOM timers TO and
87. flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bit For the prioritize ALU operation the Z flag indicates if the second operand was zero or not E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000h for the word data type or 80h for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must
88. for identifiers of 11 bits and one for identifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system 250 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Figure 134 CAN Block Diagram CAN1 TxD P4 6 CAN1 RxD P4 5 CAN_TxD CAN_RxD CAN2 TxD P4 7 4 7N CAN2 RxD P4 4 A BTL Configuration CRC Timing Generator Tx Rx Shift Register Messages Clocks Intelligent Memory to all Messages Handlers Control Interrupt Register BSP Status Control Status gt EML Register to XBUS Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to give parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory
89. high for selected CS signals used address BHE Level corresponding to last external access Level corresponding to last XBUS access ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR WARL Inactive high Inactive high WRH Inactive high Inactive high 9 6 External Bus arbitration In high performance systems it may be efficient to share external resources like memory banks or peripheral devices among more than one controller The ST10F269 supports this approach with the possibility to arbitrate the access to its external bus and to the external devices This bus arbitration allows an external master to request the ST10F269 s bus via the HOLD input The ST10F269 acknowledges this request via the HLDA output and will float its bus lines in this case The CS outputs provide internal pull up devices The new master may now access the peripheral devices or memory banks via the same interface lines as the ST10F269 During this time the ST10F269 can keep on executing as long as it does not need access to the external bus All actions that just require internal resources like instruction or data memory and on chip peripherals may be executed in parallel When the ST10F269 needs access to its external bus while it is occupied by another bus master it demande it via the BREQ output The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1 In this case the three
90. in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled by means of any instruction which is able to address the SFR memory space a lot of flexibility has been gained without creating a set of system specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The instruction pointer IP and code segment pointer CSP cannot be accessed directly They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Notes 1 Note that any explicit write request via software to an SFR supersedes a simultaneous mod ification of the same register by hardware 2 Any write operation to a single byte of an SFR clears the non addressed complementary byte within the specified SFR Non implemented reserved SFR bit cannot be modified and will always supply a read value of IO 42 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Table 6 Minimum execution times Instruction Fetch Memory Area Word Instruction Doubleword Instruction CPU clock cycles CPU clock cycles Internal Memory 2 2 Internal RAM 6 8 16 bit De multiplex Bus 2 4 16 bit Multiplexed Bus 3 6 8 bit De multiplex Bus 4 8 8 bit Multiplexed Bus 6 12 4 4 1 The S
91. input low After synchronizing this signal the ST10F269 will complete a current external bus cycle if any is active release the external bus and grant access to it by driving the HLDA output low During hold state the ST10F269 treats the external bus interface as follows Address and data bus es float to tri state ALE is pulled low by an internal pull down device Command lines are pulled high by internal pull up devices RD WR WRL BHE WRH CSx outputs are pulled high push pull mode or float to tri state open drain mode 154 340 51 ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE Should the ST10F269 require access to its external bus during hold mode it activates its bus request output BREA to notify the arbitration circuitry BREQ is activated only during hold mode It will be inactive during normal operation see Figure 66 Figure 65 Sharing external resources using slave mode HOLD HOLD HLDA gt HLDA ST10F269 in ST10F269 in Master Mode Slave Mode BREQ BREQ Figure 66 External bus arbitration releasing the bus mm A oe i 1 HL DA N O A EER y BREQ 1 1 1 Other bt Signals ____________y Note The ST10F269 will complete the currently running bus cycle before granting bus access as indi cated by the broken lines This may delay hold acknowledge compared to this figure The figure above shows the first possibility for BREQ to get active Duri
92. integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared A division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as Sticky bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see Figure 13 For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical ORing of the two specified bit Figure 13 Shift right rounding error evaluation C Flag V Flag Rounding Error Quantity 0 0 No rounding error 0 1 O lt Rounding error lt LSB 1 0 Rounding error gt LSB 1 1 Rounding error gt 1 LSB Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z
93. into the data portion of this message object by CPU trans mit objects or CAN controller receive objects since this bit was last reset or not a 260 340 ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Bit Function MSGLST Message Lost This bit applies to receive objects only Receive Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set Le the previously stored message is lost CPUUPD CPU Update This bit applies to transmit objects only Transmit Indicates that the corresponding message object may not be transmitted now The CPU sets this bit in order to inhibit the transmission of a message that is currently updated or to control the auto matic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD 1 3 RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the message object has been successfully transmitted Notes 1 In message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data in
94. is an alternate function of P5 12 see Figure 85 If T6 M 0 0 the timer is enabled when T6IN shows a low level A high level at this pin stops the timer If T6M 0 1 pin T6IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T6R The timer will only run if T6R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note A transition of the gate signal at pin T6IN does not cause an interrupt request 176 340 ky ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON to 001b In counter mode timer T6 is clocked by a transition at the external input pin T6IN which is an alternate function of P5 12 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field Tel in control register T6CON selects the triggering transition see Table 36 Figure 85 Block diagram of core timer T6 in gated timer mode T6l Gate Control Interrupt Request T6OUT P3 1 0 MUX P5 10 KA T6UDE Figure 86 Block diagram of core timer T6 in counter mode Edge Select Interrupt Request T6EUD P5 10 T6UDE T6l 000 None Counter T6 is disabled 001 Positive transition ris
95. is cleared T5CLR 1 Thus register CAPREL always contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of Lou 4 uses the value in register CAPREL to perform a reload on underflow This means the value in register CAPREL represents the time between two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow the interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of T6OTL may be output on pin T6OUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibility to set compare events based on a finer resolution than that of the external events Figure 91 GPT2 register CAPREL in capture and reload mode Up Down gt Interrupt Auxiliary Timer T5 Request A Edge Select CAPIN S P3 2 NY Interrupt Request Y CAPREL Register Input g Interrupt Clock gt Core Timer T6 Request To CAPCOM Timers Up Down TO T1 T7 T8 182 340 iy ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS 10 2 2 Inte
96. memory always occupies an address area of 256 Kbytes Configuration During Reset The default memory configuration of the ST10F269 Memory is determined by the state of the EA pin at reset This value is stored in the Internal ROM Enable bit named ROMEN of the SYSCON register When the EA pin is high during reset default value the internal Flash is globally enabled and the first 32 Kbytes are mapped in segment 0 The first instruction are fetched from the internal Flash from locations 00 0000h When the EA pin is low during reset ROMEN 0 the internal Flash is disabled and external ROM is used for startup control Mapping the Internal Flash Area When internal Flash is disabled on reset the first instructions are fetched from external memory locations 00 0000h The Flash memory can later be enabled by setting the ROMEN bit of SYSCON to 1 The code performing this setting must not run from a segment of the external ROM to be replaced by a segment of the Flash memory otherwise unexpected behaviour may occur For example if external ROM code is located in the first 32 Kbytes of segment 0 the first 32 Kbytes of the Flash must then be enabled in segment 1 This is done by setting the ROMS1 bit of SYSCON to O before or simultaneously with setting of ROMEN bit This must be done in the externally supplied program before the execution of the EINIT instruction If program execution starts from external memory but access to the Flash mem
97. memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM via hardware This virtual stack area covers all possible locations that SP can point to from 00 FOOOh through 00 FFFEh STKOV and STKUN accept the same 4 Kbyte address range The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via bit field STKSZ in register SYSCON see below Table 60 Stack size selection STKSZ Stack Size Internal RAM Addresses words Significant bit of words of Physical Stack Stack Pointer SP 000b 256 00 FBFEh 00 FAOOh Default after Reset SP 8 SP 0 001b 128 00 FBFEh 00 FBOOh SP 7 SP 0 010b 64 00 FBFEh 00 FB80h SP 6 SP 0 011b 32 00 FBFEh 00 FBCOh SP 5 SP 0 100b 512 00 FBFEh 00 F800h not for 1 Kbyte IRAM SP 9 SP 0 101b Reserved Do not use this combin
98. message object will be overwritten by non specified values Message Configuration Register EFn6h EEn6h XReg Reset Value UUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 4 0 Data byte 0 we ESA W RW R R RW RW R Bit Function XTD Extended Identifier Indicates if this message object will use an extended 29 bit identifier or a standard 11 bit identifier DIR Message Direction DIR 1 transmit On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bit of this message object are set DIR 0 receive On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object DLC Data Length Code Valid values for the data length are 0 8 Note The first data byte occupies the upper half of the message configuration register Data Area The data area of message object n covers locations 00 EFn7h through 00 EFnEh for CANT and 00 EEn7h through 00 EEnEh respectively for CAN2 locations 00 EFnFh and 00 EEnFh are reserved Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one 262 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Handling of Message Objects Th
99. more detail in Stack Operations see Section 23 1 Stack Operations 44 340 AT ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU 4 4 2 X Peripherals Control Register KPERCON XPERCON F024h 12h ESFR Reset Value 05h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN RW RW RW RW RW CAN1EN CAN1 Enable bit 0 Accesses to the on chip CAN1 XPeripheral and its functions are disabled P4 5 and P4 6 pins can be used as general purpose I Os Address range 00 EFO0h 00 EFFFh is only directed to external memory if CANZ2EN is also 0 1 The on chip CAN1 XPeripheral is enabled and can be accessed CAN2EN CAN2 Enable bit 0 Accesses to the on chip CAN2 XPeripheral and its functions are disabled P4 4 and P4 7 pins can be used as general purpose I Os Address range 00 EE00h 00 EEFFh is only directed to external memory if CAN1EN is also 0 1 The on chip CAN2 XPeripheral is enabled and can be accessed XRAM1EN XRAM1 Enable bit 0 Accesses to external memory within space 00 E000h to 00 E7FFh The 2 Kbytes of internal XRAM1 are disabled 1 Accesses to the internal 2 Kbytes of XRAM1 XRAM2EN XRAM2 Enable bit 0 Accesses to the external memory within space 00 CO00h to 00 DFFFh The 8 Kbytes of internal XRAM2 are disabled 1 Accesses to the internal 8 Kbytes of XRAM2 RTCEN RTC Enable bit 0
100. movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bit are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000h to 7FFFh for the word data type or from 80h to 7Fh for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XOR of the two specified bit C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a compar
101. occupied by the peripheral thus the peripheral is not visible and not available Refer to Chapter 22 Register Set 156 340 oy ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE XPERCON F024h 12h ESFR Reset Value 05h 15 APA cia RW RW 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW CAN1EN CAN1 Enable Bit 0 Accesses to the on chip CAN1 XPeripheral and its functions are disabled P4 5 and P4 6 pins can be used as general purpose I Os Address range 00 EFO0h 00 EFFFh is only directed to external memory if CANZ2EN is also 0 1 The on chip CAN1 XPeripheral is enabled and can be accessed CAN2EN CAN2 Enable Bit 0 Accesses to the on chip CAN2 XPeripheral and its functions are disabled P4 4 and P4 7 pins can be used as general purpose I Os Address range 00 EE00h 00 EEFFh is only directed to external memory if CAN1EN is also 0 1 The on chip CAN2 XPeripheral is enabled and can be accessed XRAMIEN XRAM1 Enable Bit 0 Accesses to external memory within space 00 E000h to 00 E7FFh The 2 Kbytes of internal XRAM1 are disabled 1 Accesses to the internal 2 Kbytes of XRAM1 XRAM2EN XRAM2 Enable Bit 0 Accesses to the external memory within space 00 CO00h to 00 DFFFh The 8 Kbytes of internal XRAM2 are disabled 1 Accesses to the internal 8 Kbytes of XRAM2 Note RTCEN RTC Enable Bit 0 Accesses t
102. of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intra segment address While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active The Figure 32 shows the structure of a PORT1 pin Figure 32 Block diagram of a PORT1 pin Write DP1H y DP1L y Direction Latch Read DP1H y DP1L y Alternate Function e Enable Alternate Data Output vin 1 no pa D Write P1H y P1L y E Port Data a de Port Output Output GE l Latch Anel Read P1H y P1L y Clock Latch e y 7 0 If this 16 bit port is used for general purpose UO the direction of each line can be configured via the corresponding direction register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 P2 FFCOh E0h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 4 Port2 P2 15 P2 14 P2 13 P2 12 P2 11 P2 10 P2 9 P2 8 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 RW RW RW RW RW RW RW RW R
103. of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Figure 116 Note If the port output latch is written to by software at the same time it would be altered by a com pare event the software write will have priority In this case the hardware triggered change will not become effective If compare mode 1 is programmed for one of the registers CCO CC7 or CC16 CC23 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 0 see section Double Register Compare Mode Note If the port output latch is written to by software at the same time it would be altered by a com pare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided Figure 116 Timing example for compare modes 0 and 1 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt e i i 0000h Interrupt Requests J TyIR Accoun count TyIR open Zeck TyIR t gt Event 1 Event 2 Event 3 Event 4 CCx cv2 CCx cv1 CCx cv2 CCx cv1 x 31 0 Output pin CCxIO only effected in mode 1 No changes in mode 0 y 0 1 7 8 ky 225 340
104. on XTAL1 for at least 1 us the CPU clock is switched automatically to PL Us base frequency around 5MHz 1 OWD is disabled If the PLL is bypassed the CPU clock is always driven by XTAL1 signal The PLL is turned off to reduce power supply current PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no effect To exit Power Down Mode an external reset must occurs by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset CSCFG Chip Select Configuration Control 0 Latched Chip Select lines CSx change 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx change with rising edge of ALE WRCFG Write Configuration Control Inverted copy of WRC bit of RPOH 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH a 147 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL Bit Function CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose I O 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set
105. or of up to 16 byte GPRs RLO RHO RL7 RH7 and 8 word registers R8 R15 The sixteen byte GPRs are mapped onto the first eight word GPRs see Table 5 In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the context pointer CP register as base address independent of the current DPP register contents Additionally each bit in the currently active register bank can be accessed individually The ST10F269 supports fast register bank context switching Multiple register banks can physically exist within the internal RAM at the same time Only the register bank selected by the Context Pointer register CP is active at a given time Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and an automatic saving of the previous context The number of implemented register banks arbitrary sizes is only limited by the size of the available internal RAM ky 29 340 MEMORY ORGANIZATION ST10F269 USER S MANUAL Details on using switching and overlapping register banks are described in Register Banking Section 23 2 Register Banking Table 5 Mapping of general purpose registers to RAM addresses Internal RAM Address Byte Registers Word Register E
106. outputs 0 0 4 bit segment address A19 A16 0 1 No segment address lines at all 1 0 8 bit segment address A23 A16 1 1 2 bit segment address A17 A16 Default without pull downs CLKCFG POH 7 5 CPU Frequency Notes fopu era X F 111 Default configuration Direct drive CPU clock via prescaler Notes 1 In ST10F269 RPOH 7 0 bit are loaded only during a long hardware reset 2 The maximum depends on the duty cycle of the external clock signal The maximum input frequency is 25MHz when using an external crystal oscillator however higher frequencies can be applied with an external clock source 9 4 3 Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set PORT1 will output the intra segment address as long as at least one of the BUSCON registers selects a de multiplexed external bus even for multiplexed bus cycles Not all address areas defined via registers ADDRSELx may overlap each other The operation of the EBC will be unpredictable in such a case See Section 9 4 2 The address areas defined via registers ADDRSELx may overlap internal address areas Internal accesses will be executed in this case For any access to an internal address area the EBC will remain inactive see EBC Idle State a 152 340 ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE 9 5 EBC Idle State When the
107. pin P3 0 or T7IN alternate input function of port pin P2 15 respectively can be selected to cause an increment of TO T7 When T1 or T8 is programmed to run in counter mode bit field Txl is used to enable the overflows underflows of timer T6 as the count source This is the only option for T1 and T8 and it is selected by the combination Txl X00b When bit field Txl is programmed to any other combination the respective timer T1 or T8 will stop When TO or T7 is programmed to run in counter mode bit field Txl is used to select the count source and transition if the source is the input pin which should cause a count trigger see description of TxyCON for the possible selections Note In order to use pin TOIN or T7IN as external count input pin the respective port pin must be con figured as input and the corresponding direction control bit DP3 0 or DP2 15 must be cleared 05 If the respective port pin is configured as output the associated timer may be clocked by modify ing the port output latches P3 0 or P2 15 via software for example for testing purposes The maximum external input frequency to TO or T7 in counter mode is fcpy 16 To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least 8 CPU clock cycles before it changes its level again The incremented count value appears in SFR TO T7 within 8 CPU clock cycles after the signal transition at pi
108. purpose I O Chip select CS4 P6 5 HOLD External hold request input P6 6 HLDA Hold acknowledge output Bus request output 120 340 ky ST10F269 USER S MANUAL PARALLEL PORTS Figure 44 Port6 I O and alternate functions Alternate Function gt lt gt Port6 2 81 8 2 8 5 0 vj oj W O T a a NI ol al Fl ojm ol gt i o o a o General Purpose Input Output The chip select lines of Port6 have an internal weak pull up device This device is switched on under the following conditions Always during reset If the Port6 line is used as a chip select output and the ST10F269 is in Hold mode invoked through HOLD and the respective pin driver is in push pull mode ODP6 x 0 This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection and to allow another master to access the external memory via the same chip select lines AND wired while the ST10F269 is in Hold mode With ODP6 x 1 open drain output selected the internal pull up device will not be active during Hold mode external pull up devices must be used in this case When entering Hold mode the CS lines are actively driven high for one clock phase then the output level is controlled by the pull up devices if activated After reset the CS function must be used if selected so In this case there is no possibility to program any port latches before Thu
109. register value which is to be updated by an immediately preceding instruction Therefore to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the example In MOV DPPO 4 select data page 4 via DPPO Inet A must not be an instr using DPPO In 2 MOV DPP0 0000H R1 move contents of R1 to address loc 01 0000h in dp 4 supposed segmentation is enabled Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions are capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Therefore in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicit SP writing and any subsequent of the just mentioned implicitly SP using instructions as shown in the example In MOV SP 0FA40H select a new top of stack Tan Bees must not be an instruction popping Operands from the system stack In 2 POP RO pop Word value from new top of stack into RO DI 39 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL External Memory Access Sequences The effect described here will only become noticeable when watching the external memory access sequences on the external bus b
110. registers must be added to the SP to restore the allocated local space back to the system stack The system stack is growing downwards while the register bank is growing upwards ky 323 340 SYSTEM PROGRAMMING ST10F269 USER S MANUAL Figure 162 Local registers Old Stack Area Old SP Newly Allocated Register Bank New CP New SP Old CP Contents PO New e Stack v Area The software to provide the local register bank for the example above Figure 162 is very compact After entering the subroutine SUB SP 10D Free 5 Words in the current system stack SCXT CP SP Set the new register bank pointer Before exiting the subroutine POP CP Restore the old register bank ADD SP 10D Release the 5 Word of the current system stack 23 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively
111. releasing the reset signal for the external peripherals of the system Note RSTOUT will float as long as pins POL O and POL 1 select emulation mode or adapt mode Watchdog timer operation after reset The watchdog timer starts running after the internal reset has completed It will be clocked with the internal system clock divided by 2 and its default reload value is 00h so a watchdog timer overflow will occur 131072 CPU clock cycles after completion of the internal reset unless it is disabled serviced or reprogrammed meanwhile When the system reset is triggered a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON is set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset or by servicing the watchdog timer After the internal reset has completed the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect ky 285 340 SYSTEM RESET ST10F269 USER S MANUAL Reset values for the ST10F269 registers During the reset sequence the registers of the ST10F269 are preset with a default
112. respective timer is cleared because it is below the pulse width shadow register Thus starting a PWM timer in single shot mode produces one single pulse on the respective port pin provided that the pulse width value is between 0000h and the period value In order to generate a further pulse the timer has to be started again via software by setting bit PTRx see Figure 126 Figure 126 Operation and output waveform in single shot mode PPx Period 7 PTx Count Value PWx Pulse Width 4 Set PTRx ers Set PTRx LSR by Software b ha dee by Software Eer for Next Pulse PTx stopped PPx Period 7 PTx Count Value PWx Pulse Width 4 Retrigger after Trigger before Pulse has started Pulse has started Write PWx value to PTx Write PWx value to PTx Shortens Delay Time tp DI 237 340 PULSE WIDTH MODULATION MODULE ST10F269 USER S MANUAL After starting the timer with PTRx 1 the output pulse may be modified via software Writing to timer PTx changes the positive and or negative edge of the output signal depending on whether the pulse has already started the output is high or not the output is still low This multiple re triggering is always possible while the timer is running after the pulse has started and before the timer is stopped Loading counter PTx directly with the value in the respective PPx shadow register will abort the current PWM pulse upon the next clock pulse counter is cleared and
113. sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the ST10F269 will still run in BSL mode that means with the watchdog timer disabled and limited access to the internal Flash area All code fetches from the internal Flash area 00 0000h 00 7FFFh or 01 0000h 01 7FFFh if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal Boot ROM of the ST10F269 if any is available but will return undefined data on ROMless devices Exiting Bootstrap Loader Mode In order to execute a program in normal mode the BSL mode must be terminated first The ST10F269 exits BSL mode upon a software reset ignores the level on POL 4 or a hardware reset POL 4 must be high After a reset the ST10F269 will start executing from location 00 0000h of the internal Flash or the external memory as programmed via pin EA ky 211 340 BOOTSTRAP LOADER ST10F269 USER S MANUAL Choosing the Baud rate for the BSL The calculation of the serial Baud rate for ASCO from the length of the first zero byte that is received allows the operation of the bootstrap loader of the ST10F269 with a wide range of Baud rates However the upper and lower limits have to be kept in order to insure proper data transfer E a fopu ST10F269 32x SOBRL 1 The
114. service routines of different priority levels level O cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 ILVL 111Xb will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will instead be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000b is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000b will terminate the ST10F269 s Idle mode and reactivate the CPU For interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see Figure 21 So programming a source to priority level 15 ILVL 1111b selects the PEC channel group 7 4 programming a source to priority level 14 ILVL 1110b selects the PEC channel group 3 0 The actual PEC channel number is then determined by the group priority field GLVL see Figure 21 Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority All sources that request PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be activ
115. such fast interrupt driven data transfer capabilities 2 3 2 Memory Areas The memory space of the ST10F269 is organized as a unified memory which means that code memory data memory registers and UO ports are organized within the same linear address space which covers up to 16 Mbytes The entire memory space can be accessed byte wise or word wise Particular portions of the on chip memory have additionally been made directly bit addressable A 2 Kbyte 16 bit wide internal RAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data The CPU contains an actual register context consisting of up to 16 word wide and or byte wide GPRs which are physically located within the on chip RAM area ky 15 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing one register bank may overlap others A system stack of up to 1024 words is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two
116. such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted after the data byte and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff ky 251 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters
117. takes at least one instruction cycle any isolated instruction takes at least four instruction cycles to be completed Pipelining however allows parallel simultaneous processing of up to four instructions Therefore as soon as the pipeline has been filled most instructions appear to be processed during one instruction cycle see Figure 10 Specification of instruction execution time always refers to the average execution time for pipelined parallel instruction processing see Figure 10 4 1 2 Standard Branch Instruction Processing When a branch is taken it is necessary to perform the branched target instruction before the current instruction in the pipeline Therefore at least one additional instruction cycle is required to fetch the branch target instruction This extra instruction cycle is provided by means of an injected instruction see Figure 11 If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next instruction cycle after decode of the conditional branch instruction 4 1 3 Cache Jump Instruction Processing The ST10F269 incorporates a jump cache This minimizes the time taken for conditional jumps which are repeatedly processed in a loop Whenever a cache jump instruction passes through the decode stage of the pipeline for
118. the ST10F269 address space The external bus interface gives access to external peripherals and additional volatile and non volatile memory It provides a number of configurations and can be tailored to fit perfectly into a given application system see Figure 53 Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONx registers specify the external bus cycles in terms of address mux demux data 16 bit 8 bit chip selects and length wait states READY control ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to define four independent address windows while all external accesses outside these windows are controlled via register BUSCONO 9 1 Single Chip Mode Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 0000h which also resets bit BUSACTO so no external bus is enabled In single chip mode the ST10F269 operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in single chip mode however external access may b
119. the controller from malfunctioning for longer than a user specified time The watchdog timer provides two registers Read only timer register that contains the current count Control register for initialization The watchdog timer is a 16 bit up counter which can be clocked with the CPU clock fcpy either divided by 2 or divided by 128 This 16 bit timer is realized as two concatenated 8 bit timers see Figure 105 The upper 8 bits of the watchdog timer can be preset to a user programmable value by a watchdog service access in order to program the watchdog expire time The lower 8 bits are reset on each service access Figure 104 SFRs and port pins associated with the watchdog timer Reset Indication Pin Data Registers Control Registers 1514131211109876543210 1514131211109876543210 RSTOUT WDT Y Y Y Y Y Y YYYYYYYYYY WDTCON ly Y Y YYYYY YYYYYY Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space Figure 105 Watchdog timer block diagram WDT Low Byte WDT High Byte RSTOUT Reset WDT Control 13 1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a bit addressable read only register The operation of the Watchdog Timer is controlled by its bit addressable Watchdog Timer Control Register WDTCON This register specifies the reload
120. the error interrupt request is due to an overrun error Asynchronous and synchronous mode 11 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 bit Baud rate generator with 13 bit reload capability allowing Baud rate generation independent of the GPT timers The Baud rate generator is clocked by fcpy 2 The timer is counting downwards and can be started or stopped through the Baud rate Generator Run bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 bit reload register each time it underflows The resulting clock is again divided according to the operating mode and controlled by the Baud rate Selection bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the Baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchronous Register SOBG is the dual function Baud rate Generator Reload register Reading SOBG returns the content of the timer bit 15 13 return zero while writing to SOBG always updates the reload register bit 15 13 are insignificant An auto reload of the timer with the content of the reload register is performed each time SOBG is written to However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until t
121. the first time provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one instruction cycle If the instruction is repeated in a loop the target instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache For execution of the repeated cache jump instruction the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the decode stage of the pipeline see Figure 12 DI 37 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless an instruction which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Figure 11 Standard branch instruction pipelining 1 instruction Injection cycle de time _ gt Figure 12 Cache jump instruction pipelining Injection of cached Target Instruction ITaRGET 1 TaARGET 2 ache Jm Itarcet tarGeT 1 FETCH eee AE AA A E 1st loop iteration gt Repeated loop iteration _ gt 4 1 4 Particular Pipeline Effects Since up to four different instruc
122. the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can only reside within the internal RAM All GPRs are bit addressable Table 54 General purpose registers GPRs Physical 8 bit TEF Reset RO OO R1 2 CPU General Purpose word Register R1 R2 CPU General Purpose word Register R2 R3 CPU General Purpose word Register R3 ES OO R5 F5h CPU General Purpose word Register R5 UUUUh R6 F6h CPU General Purpose word Register R6 UUUUh Ar DEn OO R8 F8h CPU General Purpose word Register R8 R9 F9h CPU General Purpose word Register R9 R10 CPU General Purpose word Register R10 R11 CPU General Purpose word Register R11 R12 CPU General Purpose word Register R12 R13 CPU General Purpose word R14 R15 CP 30 FFh CPU General Purpose word Register R15 UUUUh The first 8 GPRs R7 RO may also be accessed byte wise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halves of the byte accessible registers receive special names Table 55 General purpose registers GPRs bit wise addressing Physical 8 bit rr Reset Name Address Address Description Value RLO CPU General Purpose byte Register RLO RHO CPU General Purpose byte Register RHO RL1 CPU General Purpose byte Register RL1 RH1 F3h CPU General Purpose byte Register RH1 UUh RL2 F4h CPU General Purpose byte Register RL2 UU
123. the power supply The Table 26 summarizes the dedicated pins of the ST10F269 Table 26 Summary of dedicated pins Pin s Function ALE Address Latch Enable controls external address latches that provide a stable address in multi plexed bus modes ALE is activated for every external bus cycle independent of the selected bus mode It is also activated for bus cycles with a de multiplexed address bus When an external bus is enabled if one or more of the BUSACT bit is set also X Peripheral accesses will generate an active ALE signal ALE is not activated for internal accesses like accesses to Flash to the internal RAM and to the special function registers In single chip mode when no external bus is enabled no BUSACT bit set ALE will also remain inactive for X Peripheral accesses RD External Read Strobe controls the output drivers of external memory or peripherals when the ST10F269 reads data from these external devices During reset and during Hold mode an internal pull up ensures an inactive high level on the RD output WR WRL External Write Write Low Strobe controls the data transfer from the ST10F269 to an external memory or peripheral device This pin may either provide an general WR signal activated for both byte and word write accesses or specifically control the low byte of an external 16 bit device WRL together with the signal WRH alternate function of P3 12 BHE During reset and during Hold mode an internal pull up en
124. the programmable PRESCALER register the new value is loaded in the DIVIDER RTCDL ECOAh XBUS Reset Value XXXXh 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RTCDL R DI 275 340 REAL TIME CLOCK ST10F269 USER S MANUAL RTCDH ECOCh XBUS Reset Value Xh 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 RESERVED RTCDH R Note Those registers are not reset and are read only When RTCD increments to reach 00000h The 20 bit word stored into RTCPH RTCPL registers is loaded in RTCD Figure 150 DIVIDER counters 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O n V RTCDH RTCDL 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20 bit word internal value of the prescalar divider Bit 15 to bit 4 of RTCPH and RTCDH are not used When reading the return value of those bit will be zeros 19 1 4 RTCH amp RTCL RTC Programmable COUNTER Registers The RTC has 2 x 16 bit programmable counters which count rate is based on the basic time reference for example 1 second As the clock oscillator may be kept working even in power down mode the RTC counters may be used as a system clock In addition RTC counters and registers are not modified at any system reset The only way to force their value is to write them via the XBUS Those counters are write protected as well The bit RTOFF of the RTCCON register must be set RTC dividers and counters are stopped to enable a write operation on RTCH or RTCL A write opera
125. the reception of the next byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set if the overrun check has been enabled by SOOEN 11 3 Hardware Error Detection To improve the safety of serial data exchange the serial channel ASCO provides an error interrupt request flag which indicates the presence of an error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one or more of the following conditions are met If the framing error detection enable bit SOFEN is set and any of the expected stop bit is not high the framing error flag SOFE is set indicating that the error interrupt request is due to a framing error Asynchronous mode only If the parity error detection enable bit SOPEN is set in parity bit receive modes and the parity check on the received data bit proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only If the overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that
126. the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again 134 340 OI ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started Figure 54 Multiplexed bus cycle Bus Cycle lt gt 9 2 2 De multiplexed Bus Modes In the de multiplexed bus modes the 16 bit intra segment address is permanently output on PORT1 while the data uses PORTO 16 bit data or POL 8 bit data The upper address lines are permanently output on Port4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read
127. time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock cycle after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the ST10F269 s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay The read write delay is controlled via the RWDCx bit in the BUSCON registers The command s will be delayed if bit RWDCx is 0 default after reset Figure 61 Read write delay 4 Bus Cycle gt l I I I I l l l ALE y IN l l l y l I Read Write I 1 1 Delay 1 The data drivers from the previous bus cycle should be disabled when the RD signal becomes active 9 3 5 READY Polarity The active level of the ready pin can be set to READY or READY by the RDYPOL bit 13 in the BUSCON register 9 3 6 READY READY Controlled Bus Cycles The active level of the ready pin can be set to READY or READY by the RDYPOL bit in the BUSCON register For situations where the programmable wait states are not enough or where the response access time of a peripheral is not constant the
128. time overflow only one compare event per timer period is generated Double Two registers operate on one pin pin toggles on each compare match Register Mode several compare events per timer period are possible 15 5 1 Compare Mode 0 This is an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100b In this mode the interrupt request flag CCxIR is set each time a match is detected between the content of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding port pin CCxIO is not affected by compare events in this mode and can be used as general purpose UO pin If compare mode O is programmed for one of the registers CC8 CC15 or CC24 CC31 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see section Double Register Compare Mode Interrupt CCxIR Request N Port Latch CCxIO Toggle A Figure 115 Compare mode 0 and 1 block diagram Capture Register CCx Mode 1 CCMODx Input Interrupt Clock CAPCOM Timer Ty TyIR Request x 31 0 y 0 1 7 8 Note The port latch and pin remain unaffe
129. to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latch is set upon a compare event and cleared upon a timer overflow see Figure 118 However when compare value and reload value for a channel are equal the respective interrupt requests will be generated only the output signal is not changed set and clear would coincide in this case Note If the port output latch is written to by software at the same time it would be altered by a com pare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided 15 5 5 Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 16 capture compare registers of each CAPCOM unit are regarded as two banks of 8 registers each Registers CCO CC7 and CC16 CC23 form bank1 while registers CC8 CC15 and CC24 CC31 form bank 2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this register pair operate on the pin associated with the bank 1 register pins CCOIO C
130. to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802h Set SP before last entry of physical stack of 256 Words SP F802h Physical stack address FAO2h PUSH R1 SP F800h Physical stack address FAOOh PUSH R2 SP F7FEh Physical stack address FBFEh The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that portion of stack data which is really to be re used the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000b to 100b it does not work with option STKSZ 111b which uses the complete internal RAM for system stack In the latter case the address transformation mechanism is deactivated When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the in
131. transmit and receive behavior of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition The Figure 100 is a summary 12 1 Full Duplex Operation The different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 0 The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The s
132. traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the system stack External interrupt processing Although the ST10F269 does not provide dedicated interrupt pins it allows to connect external interrupt sources and provides several mechanisms to react on external events including standard inputs non maskable interrupts and fast external interrupts These interrupt functions are alternate port functions except for the non maskable interrupt and the reset input 6 1 Interrupt System Structure The ST10F269 provides 56 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent software design techniques each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is activated by one specific event depending on the selected operating mode of the respective device The only exceptions are the two serial channels of the ST10F269 where an error interrupt request can be generated by different kinds of error However specific status flags which identify the type of error
133. value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 0001h points to data page 1 DPP2 0002h points to data page 2 DPP3 0003h points to data page 3 CP FCOOh STKUN FCOOh STKOV FAOOh SP FCOOh WDTCON 0002h if reset was triggered by a watchdog timer overflow 0000h otherwise SORBUF XXh undefined SSCRB XXXXh undefined SYSCON OxxOh set according to reset configuration BUSCONO Oxx0h set according to reset configuration RPOH XXh reset levels of POH ONES FFFFh fixed value The internal ram after reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 RO and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset Ports and external bus configuration during reset During the internal reset sequence all of the ST10F269 s port pins are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high impedance state T
134. versa ky 63 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL 5 2 9 Repeat unit The MAC includes a repeat unit allowing the repetition of some co processor instructions up to 213 8192 times The repeat count may be specified either by an immediate value up to 31 times or by the content of the Repeat Count bits 12 to 0 in the MAC Repeat Word MRW If the Repeat Count equals N the instruction will be executed N 1 times At each iteration of a cumulative instruction the Repeat Count is tested for zero If it is zero the instruction is terminated else the Repeat Count is decremented and the instruction is repeated During such a repeat sequence the Repeat Flag in MRW is set until the last execution of the repeated instruction The syntax of repeated instructions is shown in the following examples 1 Repeat 24 times CoMAC IDX0 RO repeated 24 times In example 1 the instruction is repeated according to a 5 bit immediate value The Repeat Count in MRW is automatically loaded with this value minus one MRW 23 1 MOV MRW 00FFh load MRW NOP instruction latency Repeat MRW times CoMACM IDX1 R2 repeated 256 times In this example the instruction is repeated according to the Repeat Count in MRW Notice that due to the pipeline processing at least one instruction should be inserted between the write of MRW and the next repeated instruction Repeat sequences may be interrupted When an interrupt o
135. 0 2 Timer Block GPT2 From a programmer s point of view the GPT2 block is represented by a set of SFRs The l O of port and direction registers which are used for alternate functions by the GPT2 block are noted Y in Figure 82 Timer block GPT2 supports high precision event control with a maximum resolution of 4 CPU clock cycles It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Each timer has an alternate associated input pin which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin An overflow underflow of T6 is indicated by the output toggle bit T6OTL whose state may be output on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 with auxiliary timer T5 while concatenation of T6 with the timers of the CAPCOM units is provided through a direct connection Triggered by an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bit addressable SFRs T5 and T6 Figure 82 SFRs and port pi
136. 0 9 8 7 6 5 4 3 2 1 0 MAH RW Bit Function MAH MAC Unit Accumulator High bits 31 16 66 340 ky ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC MAL FE5Ch 2Eh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAL RW Bit Function MAL MAC Unit Accumulator Low bits 15 0 MSW FFDEh EFh SFR Reset Value 0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIR SL E sv C Z N MAE R RW RW RW RW RW RW RW Bit Function MIR MAC Interrupt Request Set when the MAC Unit generates an interrupt request SL Sticky Limit Flag Set when the result of a MAC operation is automatically saturated Also used for COMIN COMAX instructions to indicate that the Accumulator has changed It remains set until it is explicitly reset by software E Extension Flag Set when MAE contains significant bits at the end of a MAC operation SV Sticky Overflow Flag Set when a MAC operation produces a 40 bit arithmetic overflow It remains set until it is explicitly reset by software MAE Accumulator Extension bits 39 32 Note The MAC condition flags are evaluated if required by the instruction being executed In particu lar they are not affected by any instruction of the regular instruction set In consequence their values may not be consistent with the Accumulator content For example loading the Accumu lator with MOV instructions will not modify the condition flags a 67 340 MULT
137. 1 High Register Upper half of PORT1 00h BUSCONO b FFOCh Bus Configuration Register 0 Oxx0h MDC b FFOEh CPU Multiply Divide Control Register 0000h 310 340 ky ST10F269 USER S MANUAL REGISTER SET Table 57 Registers ordered by address continued Physical 8 bit E Reset Name Address Description Value PSW b Frion ssh CPU Program Status word 0000h SYSCON b FF12h CPU System Configuration Register Oxx0h BUSCON1 b FF14h Bus Configuration Register 1 0000h BUSCON2 b FF16h sBh Bus Configuration Register 2 0000h BUSCON3 b FF18h Bus Configuration Register 3 0000h BUSCON4 b FF1Ah Bus Configuration Register 4 0000h ZEROS b FF1Ch Constant Value 0 s Register read only 0000h ONES b FF1Eh Constant Value 1 s Register read only FFFFh T78CON b FF20h CAPCOM Timer 7 and 8 Control Register 0000h CCM4 b FF22h CAPCOM Mode Control Register 4 0000h CCM5 b FF24h CAPCOM Mode Control Register 5 0000h CCM6 b FF26h CAPCOM Mode Control Register 6 0000h CCM7 b FF28h CAPCOM Mode Control Register 7 0000h PWMCONO b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h PWM Module Control Register 1 0000h T2CON b FF40h GPT1 Timer 2 Control Register 0000h T3CON b FF42h GPT1 Timer 3 Control Register 0000h T4CON b FF44h GPT1 Timer 4 Control Register 0000h T5CON b FF46h GPT2 Timer 5 Control Register 0000h T6CON b FF48h GPT2 Timer 6
138. 1 or 2 stop bit Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last bit of a frame is transmitted that means before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 188 340 51 ST10F269 USER S MANUAL ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bit SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected Baud rate A majority decision of the 7th 8th and 9th sample determines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register Figure 95 As
139. 12 7 6 Port4 If this 8 bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP4 P4 FFC8h E4h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function P4 y Port data register P4 bit y 112 340 OI ST10F269 USER S MANUAL PARALLEL PORTS DP4 FFCAh E5h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function DP4 y Port direction register DP4 bit y DP4 y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an output ODP4 F1CAh E5h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP4 y Port 4 Open drain control register bit y ODP4 y 0 Port line P4 y output driver in push pull mode ODP4 y 1 Port line P4 y output driver in open drain mode H P4 y is not a segment address line output Only bit 6 and 7 are implemented all other bit will be read as 0 7 6 1 Alternate Functions of Port4 During external bus cycles that use segmentation for address space above 64 Kbytes a number of Port4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port4 if any may be used for general purpose I O If segment address lines are
140. 2 2 5 4 Parallel Ports unicidad 22 2 5 5 Serial Channels unirnos adri ta a 23 2 5 6 The on chip CAN Modules 23 2 5 7 General Purpose Timer GPT Unit o eeececececeeeeeeeeeeeneeeeeeeeeeeeeseaeeeseaeeseaeeeseaeeens 23 2 5 8 Watchdog Timer dut a te iene eet ee eee 24 2 5 9 Capture Compare CAPCOM Unit 24 2 5 10 Pulse Width Modulation Unit 25 2 5 11 A D Converter iii A ie A SCENE bad 25 2 6 PROTECTED BITS isso el eee eel tee 26 3 MEMORY ORGANIZATION cccccsseceeeeeeeeeeeeeeeeeeeceeseseeeeeseaeeeeseeeeseneeseseeeeeseeeeeeeeeeenes 27 3 1 INTERNAL FLASH o aan ae ea a eet 28 3 2 INTERNAL RAM AND SFR AREA 29 3 2 1 system Stack ici eta a aa 31 3 2 2 General Purpose Registers A 31 3 2 3 PEC Source and Destination Pointers conc n nano ncnnan cnc 32 3 2 4 Special Function Registers cacao canon nn nana nn can nca rancia 33 3 3 THE ON CHIP XRAM oiriin e aaa aei aeaaea a i ae ae i aeit 34 3 3 1 XRAM Access Via External Masters AAA 34 3 4 EXTERNAL MEMORY SPACE dyha ta aaa a ia ranma 35 3 5 CROSSING MEMORY BOUNDARIES 36 ky 2 340 ST10F269 USER S MANUAL 4 1 1 THE CENTRAL PROCESSING UNIT CPU cnconcccinncccnnonccccncccninnccnnnccnnnnnononacnnna nacos INSTRUCTION PIPELINES Sequential Instruction Processing Standard Branch Instruction Processing cooococinoccconoccccnocccnnnnccnanaca nono nnnnnnnnnannnnnnanncnns Cache Jump Instruction Processing Particular Pipeline Effects
141. 269 USER S MANUAL 24 KEY WORD INDEX ten KE Adapt Mode ND neger Ae 25 Adder Subtracter MAC Adder Subtracter Address Arbitration Area Definition ooooccccnnncncncnnncnnnnnnos Boundaries Segment TT 140 ADDRSELX cocccccccnncoconnncncnnnnnncnncninnnaccnnnos 152 ALE length Analog Digital Converter a se 25 Arbitration Address External Bus ASCO Interrupts Auto Scan conversion ccooooccccconocccnncononnncnncnnns Baudrate ASCO srt dla GAN ebe ee niet nein addressable Memory coocooccccccnnoccccncnnnnnnos Handling A ee a aR timing register Bootstrap Loader ooooccccccnnncccccconccccnnnnnn 211 Boundaries mecanica Burst mode PWM Bus Arbitration CAN aia ta 23 252 Demultiplexed AAA Idle State Mode Configuration Multiplexed ky KEY WORD INDEX C CAN Interface eiin 23 252 CAPCOM Ma Soe ek Ge a 24 IM OTTUPE scee eee eee dnde 231 A ee he eee 219 HR euer OAK eee 216 Capture mode cococccccccncccnoncncnnnncnnnancnnnanacananan 224 Capture Mode GPT seee 173 182 Capture Compare unit cccceeceeeeeeteeeeetees 216 CCMO CCM1 CCM2 COM3 nnaaiiesssseeneeeseen 223 CCM4 CCM5 CCM6 COM cccceeee 223 Center aligned PWM oneee 236 Chip Selection ca acia 140 293 Clock Generator cccccccnnnccooononcccnnnnncncnnnnnnnans 294 Compare modes cnnccccnoccconoccnnnnncnnanncananncnnnncns 225 Concatenation of Timers 00000000e 170 182 Configuration ARES m
142. 269 USER S MANUAL THE CAPTURE COMPARE UNITS The reload value determines the period Py between two consecutive overflows of Tx as follows 218 TxREL x 210 0 3 fcpu The timer resolutions against pre scaler option in Txl are listed in the table below Pry Timer Input Selection Txl 000b 001b 010b 011b 100b 101b 110b 111b Pre scaler for CPU 8 16 32 64 128 256 512 1024 Resolution in 8 16 32 64 128 256 512 1024 CPU clock cycles Refer to the device datasheet for a table of timer input frequencies resolution and periods for each pre scaler option in Txl After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of a CAPCOM unit are to be incremented or reloaded at the same time TO is always serviced one CPU clock before T1 T7 before T8 respectively Counter Mode The bit TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In Counter mode TxM 1 the input clock for a timer can be derived from the overflows underflows of timer T6 in block GPT2 In addition timers TO and T7 can be clocked by external events Either a positive a negative or both a positive and a negative transition at pin TOIN alternate input function of port
143. 39 26 1 THIS IS REVISION 1 1 OF THIS DOCUMENT RELEASED ON 25TH OF SEPTEMBER 2001 339 26 2 USER S MANUAL REVISION 1 2 OF 2ND OF NOVEMBER 20071 340 26 3 USER S MANUAL REVISION 1 2 OF 6TH OF NOVEMBER 2007 341 26 4 USER S MANUAL REVISION 1 2 OF 21TH OF NOVEMBER 2001 341 ky 8 340 ky ST10F269 USER S MANUAL 1 INTRODUCTION This manual describes the functionality of the ST10F269 device An architectural overview describes the CPU performance the on chip system resources the on chip clock generator the on chip peripheral blocks and the protected bits The operation of the CPU and the on chip peripherals and the different operating modes such as system reset power reduction modes interrupt handling and system programming are described in individual chapters The explanation of memory configuration has been restricted to that of the internal addressable memory space The ST10F269 flash configurations are not discussed in this manual Refer to the ST10F269 datasheet for detailed information The Special Functional Registers are listed both by name and hexadecimal address The instruction set is covered in full in the ST10 Family Programming Manual and is therefore not discussed in this manual However software programming feature including constructs for modularity loops and context switching are described in Chapter 23 System Programming The DC and AC electrical specifications of the device and the pin
144. 3h XP1IC F18Eh C7h XPERCON F024h 12h XPERCON F024h 12h XPERCON F024h 12h xxIC yyyyh zzh ZEROS FF1Ch 8Eh 336 340 SFR SFR SFR SFR SFR ESFR ESFR SFR XReg XReg XReg SFR ESFR Area ESFR Area ESFR ESFR ESFR SFR Area SFR ST10F269 USER S MANUAL Reset Value 0000h 180 Reset Value OOh 185 Reset Value OOOOh 176 Reset Value OOR 185 Reset Value 0000h 220 Reset Value OOh 222 Reset Value 00h 222 Reset Value 0000h 92 Reset Value UUUUR 264 Reset Value UUUU 260 Reset Value UUUU 261 Reset Value OOxxh 209 Reset Value 00h 258 Reset Value 00h 258 Reset Value 05h 159 Reset Value 05h 255 Reset Value 05h 47 Reset Value OOh 77 Reset Value 0000h 59 REVISION HISTORY ST10F269 USER S MANUAL 26 REVISION HISTORY 26 1 This is revision 1 1 of this document released on 25th of September 2001 Page 17 Section 2 4 1 PLL Operation in this case the PLL will run on its basic frequency of 2 to 10 MHz instead of 5 MHz Page 18 Section 2 4 3 Direct Drive row 5 The PLL runs on its basic frequency of 2 to 10 MHz instead of 5 MHz Row 6 except for ST10C167 or ST10R167 where if bit OWDDIS is set the PLL is
145. 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output 7 2 1 Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit de multiplexed bus only uses POL while POH is free for I O provided that no other bus mode is enabled PORTO is also used to select the system start up configuration During reset PORTO is configured to input and each line is held high through an internal pull up device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pull down device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pull up devices are designed such that an external pull down resistors see Data Sheet specification can be used to apply a correct low level These external pull down resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong With t
146. 4IR GPT1 timer interrupt request flags T5IC T6IC T5IR T6IR GPT2 timer interrupt request flags CRIC CRIR GPT2 CAPREL interrupt request flag T3CON T6CON T3OTL T6OTL GPTx timer output toggle latches T7IC T8IC T7IR T8IR CAPCOM2 timer interrupt request flags SOTIC SOTBIC SOTIR SOTBIR ASCO transmit buffer interrupt request flags SORIC SOEIC SORIR SOEIR ASCO receive error interrupt request flags SOCON SOREN ASCO receiver enable flag SSCTIC SSCRIC SSCTIR SSCRIR SSC transmit receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBE SSCPE SSC error flags SSCCON SSCRE SSCTE SSC error flags ADCIC ADEIC ADCIR ADEIR ADC end of conversion overrun interrupt request flag ADCON ADST ADCRQ ADC start flag injection request flag CC31IC CC16IC CC31IR CC16IR CAPCOM2 interrupt request flags CC15IC CCOIC CC15IR CCOIR CAPCOM1 interrupt request flags Pan TFR TFR 15 14 13 Class A trap flags TFR TFR 7 3 2 1 0 Class B trap flags S P7 P7 7 P7 0 All bit of Port7 P8 P8 7 P8 0 All bit of Port8 XPyIC y 3 0 XPyIR y 3 0 X Peripheral y interrupt request flag ST10F269 USER S MANUAL MEMORY ORGANIZATION 3 MEMORY ORGANIZATION The memory space of the ST10F269 is organized as a unified memory Code memory data memory registers and l O ports are organized within the same linear address space All of the physically separated memory areas including internal Flash internal RAM the internal Special Functio
147. 6 5 4 3 2 1 0 BOFF E RXOK TXOK LEC TST CCE 0 0 EIE SIE IE INIT WRN R R RW RW RW RW RW R R RW RW RW RW Table 46 CAN Control Status register Bit INIT Initialization 1 Software initialization of the CAN controller While init is set all message transfers are stopped Setting init does not change the configuration registers and does not stop transmission or recep tion of a message in progress The init bit is also set by hardware following a busoff condition the CPU then needs to reset init to start the bus recovery sequence see Figure 144 0 Disable software initialization of the CAN controller on INI completion the CAN waits for 11 con secutive recessive bits before taking part in bus activities IE Interrupt Enable Does not affect status updates 1 Global interrupt enable from CAN module 0 Global interrupt disable from CAN module 254 340 ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Bit Function Control bit SIE Status Change Interrupt Enable 1 Enables interrupt generation when a message transfer reception or transmision is successfully completed or CAN bus error is detected and registered in LEC is the status partition O Disable status change interrupt EIE Error Interrupt Enable 1 Enables interrupt generation on a change of bit BOFF or EWARN in the status partition O Disable error interrupt CCE Configuration Change Enable 1 Allows CPU access to the bit timing registe
148. 69 the associated interrupt vectors their locations and the associated trap numbers lt also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR Interrupt Request flag E Interrupt Enable flag Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 bytes per entry Table 12 Interrupt and PEC service request sources Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number CAPCOM Register 0 CCOIR CCOIE CCOINT 00 0040h 10h CAPCOM Register 1 CC1INT 00 0044h 11h CAPCOM Register 2 CC2INT 00 0048h 12h CAPCOM Register 3 CC3INT 00 004Ch 13h CAPCOM Register 4 CC4INT 00 0050h 14h CAPCOM Register 5 CC5INT 00 0054h 15h CAPCOM Register 6 CC6INT 00 0058h 16h CAPCOM Register 7 CC7INT 00 005Ch 17h CAPCOM Register 8 CC8INT 00 0060h 18h CAPCOM Register 9 CC9INT 00 0064h 19h CAPCOM Register 10 CC10INT 00 0068h 1Ah CAPCOM Register 11 CC11INT 00 006Ch 1Bh CAPCOM Register 12 CC12INT 00 0070h 1Ch CAPCOM Register 13 CC13INT 00 0074h 1Dh CAPCOM Register 14 CC14IR CC141E CC14INT 00 0078h 1Eh CAPCOM Register 15 CC15IR CCI5IE CC15INT 00 00
149. 7 T2IN Auxiliary timer T2 input pin T2CON P3 5 T4IN Auxiliary timer T4 input pin T4CON P3 2 CAPIN GPT2 capture input pin T5CON The active edge of the external input signal is determined by bit fields T2I or TA When these fields are programmed to X01b interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or T4IN respectively When T2l or T4l are programmed to X10b then a negative external transition will set the corresponding request flag When T2l or T4l are programmed to X11b both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bit T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON is cleared to 0 signal transitions on pin CAPIN will only set the interrupt request flag CRIR in register CRIC and the capture function of register CAPREL is not activated So register CAPREL can still be used as reload register for GPT2 timer T5 while pin CAPIN serves as external interrupt input Bit field Cl in register T5CON se
150. 7Ch 1Fh CAPCOM Register 16 CC16IR CCI6IE CC16INT 00 00COh 30h CAPCOM Register 17 CC17IR CCI7IE CC17INT 00 00C4h 31h CAPCOM Register 18 CC18IR CC18lE CC18INT 00 00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CCh 33h CAPCOM Register 20 CC20INT 00 00DOh 34h CAPCOM Register 21 CC21INT 00 00D4h 35h CAPCOM Register 22 CC22INT 00 00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00 00DCh 37h CAPCOM Register 24 CC24IR CC241E CC24INT 00 00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E4h 39h CAPCOM Register 26 CC26IR CC26lE CC26INT 00 00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00ECh 3Bh CAPCOM Register 28 CC28IR CC28lE CC28INT 00 00E0h 3Ch 72 340 ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS Table 12 Interrupt and PEC service request sources continued Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00 0114h 45h CAPCOM Register 31 CC31IR CC311E CC31INT 00 0118h 46h CAPCOM Timer 0 TOIR TOIE TOINT 00 0080h 20h CAPCOM Timer 1 T1INT 00 0084h 21h CAPCOM Timer 7 T7INT 00 00F4h 3Dh CAPCOM Timer 8 T8INT 00 00F8h 3Eh GPT1 Timer 2 T2INT 00 0088h 22h GPT1 Timer 3 T3INT 00 008Ch 23h GPT1 Timer 4 TAINT 00 0090h 24h GPT2 Timer 5 T5INT 00 0094h 25h GPT2 Timer 6 T6INT 00 0098h 26h GPT2 CAP
151. 7LIN P4LIN P3HIN P3LIN P2HIN P2LIN RW RW RW RW RW RW Bit Function PxLIN Port x Low Byte Input Level Selection O Pins Px 7 Px 0 switch on standard TTL input levels 1 Pins Px 7 Px 0 switch on special threshold input levels PXHIN Port x High Byte Input Level Selection O Pins Px 15 Px 8 switch on standard TTL input levels 1 Pins Px 15 Px 8 switch on special threshold input levels DI 95 340 PARALLEL PORTS ST10F269 USER S MANUAL All options for individual direction and output mode control are available for each pin independent of the selected input threshold The input hysteresis provides stable inputs from noisy or slowly changing external signals Figure 28 Hysteresis for special input thresholds Hysteresis Input level Bit state 7 1 3 Alternate Port Functions Each port line has one associated programmable alternate input or output function PORTO and PORT1 may be used as the address and data lines when accessing external memory Port4 outputs the additional segment address bit A23 19 17 A16 in systems where more than 64K bytes of memory are to be accessed directly Port6 provides the optional chip select outputs and the bus arbitration lines Port2 Port7 and Port8 are associated with the capture inputs or compare outputs of the CAPCOM units and or with the outputs of the PWM module Port2 is also used for fast external interrupt inputs and for timer 7 input Port3 inclu
152. 91 6 7 3 External NMI TAD cintia ii 93 6 7 4 Stack Overfl Ww Trap viii a ea ai End CN 93 6 7 5 StacK UndertloW Trap woo atlante Eed 93 6 7 6 Undefined Opcode Trap 93 6 7 7 Protection Fault TTaP ausu dai dis 93 6 7 8 Illegal word Operand ACCESS Trap 93 6 7 9 Illegal Instruction ACCESS Trap 94 6 7 10 Illegal External BUS ACCESS Trap 94 7 PARALLEL PORTS uni fc 95 7 1 INTRODUCTION coi ENEE eae dee 95 7 1 1 Open Drain Mode AE 95 7 1 2 Input Threshold Control A 97 7 1 3 Alternate Port FUNC ONS oooonmccccn nonccccnnnonncnccnnonnnnncn nro AEE Ea 98 7 1 4 Output Driver Control atinada tati 99 7 2 PORTO Lt EE Be fe cert A ee eto es ee 101 7 2 1 Alternate Functions of PORTO 102 7 3 POR Tina dd Net 104 7 3 1 Alternate Functions of POT 105 7 4 PORT 2 iiien Mint aioe heen eT en ev DEE aa E ea 106 7 4 1 Alternate Functions of Porta srren ne euen EKE i A EEE EENET NA 107 7 4 2 External ul e ee cionado da init 108 7 5 PORTS EE 110 7 5 1 Alternate Functions of Ports areeni ee aA ER a Eo AE aa TRR 111 7 6 POR TA ll a gees 114 7 6 1 Alternate Functions of Port 115 7 7 POR Tamarit didas 119 7 7 1 Alternate Functions of Port 120 7 7 2 Port 5 Schmitt Trigger Analog Inpute cnn 121 ky 4 340 ST10F269 USER S MANUAL 7 8 POR TB A AAA ia io 121 7 8 1 Alternate Functions Of Porco ica 122 7 9 PORT Ee EE Ee 125 7 9 1 Alternate Functions of Port AAA 126 7 10 POR TB eet Eege 128 7 10 1 Alternate Functions of Port 129 8 DEDIGATE
153. AAA AAA AAA AA AAA 3 HIdO AAA AA AAA 3 Wda AAA AA AAA 3 HOdd WAA AA AAA 3 10da AAA AA AAA OLZEv S S9Z86OLLLZLEL LSL si9a siBay o uoy U09311 0OLZgEetvs9Z860LLL lt CLEL MSL Jajsibay yndyno indu eea 8d ld 9d Sd bd d Zd Hld Wd HOd 10d 94 340 ST10F269 USER S MANUAL PARALLEL PORTS Figure 27 Output drivers in push pull mode and in open drain mode 1 1 External Pull up Big on o z 77 Push Pull Output Driver Open Drain Output Driver Ol 7 1 2 Input Threshold Control The standard inputs of the ST10F269 determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port2 Port3 Port4 Port7 and Port8 These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds The Port Input Control register PICON is used to select these thresholds for each byte of the indicated ports the 8 bit ports P4 P7 and P8 are controlled by one bit each while ports P2 and P3 are controlled by two bits each PICON F1C4h E2h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P8LIN P
154. ADDAT Full Channel 0 Result Lost Read of ADDAT Result of Channel X 3 2 1 3 Overrun Error Interrupt Request 17 1 3 Wait for ADDAT Read Mode If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in register ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new result is stored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is started This mechanism applies to both single and continuous conversion modes While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT Read Mode there may be delays due to suspended conversions ky 245 340 ANALOG DIGITAL CONVERTER ST10F269 USER S MANUAL However this only affect
155. ANUAL SYSTEM RESET PORTO and PORT1 are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 bit intra segment address and the output data while PORT1 remains in high impedance state as long as no de multiplexed bus is selected via one of the BUSCON registers In de multiplexed bus modes PORT1 drives the 16 bit intra segment address while PORTO or POL according to the selected data bus width drives the output data For a 16 bit data bus BHE is automatically enabled for an 8 bit data bus BHE is disabled via Bit BYTDIS in register SYSCON Default 16 bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and bit field BTYP of register BUSCONO is cleared Write configuration Pin POH O WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the standard function which is WR control and BHE When low it selects the alternate configuration WRH and WRL Thus even the first access after a reset can go to a memory controlled via WRH and WRL This bit is latched in register RPOH and its inverted value is copied into bit WRCFG in register SYSCON Default Standard function WR control and BHE Chip select lines Pins POH 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows to select which pins of Port6 drive external CS signals and which
156. APPLICATION INTERFACE AA 273 19 REAL TIME CL fO CK oca a 275 19 1 RTG REGISTERS aaa A As 276 19 1 1 RTCCON RTC Control Heglster nn nc conc canon nn rancia rannnnnann 276 19 1 2 RTCPH 8 RTCPL RTC PRESCALER RegisterS A 277 19 1 3 RTCDH A RTCDL RTC DIVIDER Counters cooocccccocccononcccnonnnnnanacononananinnncnnanacaninnnccannos 277 19 1 4 HITCH amp RTCL RTC Programmable COUNTER Registers AAA 278 19 1 5 RTCAH 8 RTCAL RTC ALARM Registers A 279 19 2 PROGRAMMING THE BIC 279 20 SYSTEM RESE lt a is 281 20 1 ASYNCHRONOUS RESET LONG HARDWARE RESET ereere 281 20 2 SYNCHRONOUS RESET WARM RESET cceccceceeeeeeeeeeeeeeeeeeeaeeeeeeeesenaeeeseaeeens 282 20 3 SOFTWARE RESET ugeet ageet Eege a 284 20 4 WATCHDOG TIMER RESET aeeoea e naneta aren ea aaiae reen CAE aao deer tana AKu aaan tiaraa AHi 284 20 5 RSTOUT PIN AND BIDIRECTIONAL DEGET 284 20 6 RESET CIRCUITRY detrei sei eii aea aaa ei eaa ENEE ENEE 285 20 7 PINSAFTERRE SE unio A nc 287 20 7 1 System Start up Configuration ooococonncccnnncccnnnoccnoncnnnonrnonono conan ca nonn nana ocn rra nn rana cc cannncnnns 290 21 POWER REDUCTION MODES eoccooncccccccccnoncninnnccninnnncnnnnnnanannnnnnn nc cnn rn nnnnc rre 295 21 1 IDLE MODE uc A ee tet 295 7 340 ky ST10F269 USER S MANUAL 21 2 POWER DOWN MODE aiten iin ti 296 21 2 1 Protected Power Down Mode ccecceeseeceeeeeeeeeeeeeeseaneeeeeneaeeeesesseeneeeeessaneeeteneees 296 21 3 INTERRUPTIBLE POWER DOWN MODE coccococcconocccc
157. Blocks The ST10 family of devices separates peripherals from the core This allows peripherals to be added or deleted without modifications to the core Each functional block processes data independently and com municates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within the standard SFR area 00 FEOOh 00 FFFFh or within the extended ESFR area 00 FOOOh 00 F1FFh The built in peripherals are used for interfacing the CPU to the external world or to provide on chip functions The ST10F269 generic peripherals are Two General Purpose Timer Blocks GPT1 and GPT2 Two Serial Interfaces ASCO and SSC A Watchdog Timer Two 16 channel Capture Compare units CAPCOM1 and CAPCOM2 A 4 channel Pulse Width Modulation unit A 10 bit Analog Digital Converter Nine UO ports with a total of 111 I O lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock 2 5 1 Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hard
158. C7IO and CC1610 CC23I10 The relationship between the bank 1 and bank 2 register of a pair and the effected output pins for double register compare mode is listed in the Table 41 Table 41 Register pairs for double register compare mode CAPCOM1 Unit CAPCOM2 Unit Register Pair Associated Output Pin Register Pair Associated Output Pin cco CColO CC24 CC1610 CC110 CC1710 CC1810 CC1910 CC2010 CC2110 CC2210 CC7 CC31 CC2310 227 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL The double register compare mode can be programmed individually for each register pair In order to enable double register mode the respective bank 1 register see Table 41 must be programmed to compare mode 1 and the corresponding bank 2 register see Table 41 must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxIO corre
159. C7h in the ESFR range The associated interrupt vector is called XP1INT at location 104h trap number 41h With this configuration the user has all control options available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below XPOIC F186h C3h ESFR Area Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ee ee ILVL GLVL RW RW RW RW XP1IC F18Eh C7h ESFR Area Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1IR X11E ILVL GLVL RW RW RW RW Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests Fh Highest priority level Oh Lowest priority level xxlE Interrupt Enable Control bit individually enables disables a specific source 0 Interrupt Request is disabled 1 Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request As for all other interrupts the interrupt request flag XPXIR in register XPXIC is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can
160. Code accesses to the new address area must be made after an absolute branch to this area Note As a rule instructions that change external bus properties must not be executed from the respective external memory area Timing Pipeline architecture drastically reduces the average instruction processing time The mean ratio is about four to one instruction cycle Some peculiar cases of pipeline configuration extend the instruction processing time by half or by one cycle These cases have to be taken in account for the time critical software routines Besides a general execution time description the following section provides some hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities 4 2 Bit handling and bit protection The ST10F269 provides several mechanisms for bit manipulation These mechanisms either handle software flags within the internal RAM control on chip peripherals via control bit in their respective SFRs or control I O functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV and BMOVN explicitly set or clear specific bit The instructions BFLDL and BFLDH make it possible to change up to 8 bit of a specific byte at a time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the
161. Control Register 00h CC23IC b Fi6Eh E CAPCOM Register 23 Interrupt Control Register 00h CC24IC b F170h E CAPCOM Register 24 Interrupt Control Register 00h CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register 00h CC26IC b F174h E CAPCOM Register 26 Interrupt Control Register 00h CC27IC b F176h E CAPCOM Register 27 Interrupt Control Register 00h CC28IC b F178h E CAPCOM Register 28 Interrupt Control Register 00h T7IC b F17Ah E CAPCOM Timer 7 Interrupt Control Register 00h T8IC b F17Ch E CAPCOM Timer 8 Interrupt Control Register 00h PWMIC b F17Eh E BFh PWM Module Interrupt Control Register 00h CC29IC b F184h E CAPCOM Register 29 Interrupt Control Register 00h XPOIC b F186h E CAN Module Interrupt Control Register 00h CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register 00h XP1IC b F18Eh E C7h X Peripheral 1 Interrupt Control Register 00h CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register 00h XP2IC b F196h E CBh X Peripheral 2 Interrupt Control Register 00h SOTBIC b F19Ch E CEh Serial Channel O Transmit Buffer Interrupt Control Register 00h XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register 00h EXICON b F1C0h E External Interrupt Control Register 0000h ODP2 b F1C2h E Port2 Open Drain Control Register 0000h PICON b F1C4h E Port Input Threshold Control Register 00h ODP3 b F1C6h E Port3 Open Drain Control Reg
162. Control Register 0016 SC CC16IC b F160h E Boh CAPCOM Register 16 Interrupt Control Register 00h CC17 FE62h CAPCOM Register 17 0000h COMIC CC18 32h CAPCOM Register 18 CC18IC b B2h CAPCOM Register 18 Interrupt Control Register CC19 33h CAPCOM Register 19 CC19IC b B3h CAPCOM Register 19 Interrupt Control Register CC20 34h CAPCOM Register 20 CC20IC b B4h CAPCOM Register 20 Interrupt Control Register 001 CC21IC b Fi6Ah E B5h CAPCOM Register 21 Interrupt Control Register 00h ES CC23 37h CAPCOM Register 23 CC23IC b B7h CAPCOM Register 23 Interrupt Control Register CC24 38h CAPCOM Register 24 ES CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC b F172h E CAPCOM Register 25 Interrupt Control Register 00h GC SCH CC26IC b BAh CAPCOM Register 26 Interrupt Control Register CC27 3Bh CAPCOM Register 27 CC27IC b BBh CAPCOM Register 27 Interrupt Control Register CC28 3Ch CAPCOM Register 28 CC28IC b BCh CAPCOM Register 28 Interrupt Control Register CC29 3Dh CAPCOM Register 29 SSC CC30 FE7Ch 3Eh CAPCOM Register 30 0000h CC31 CAPCOM Register 31 CC31IC b CAh CAPCOM Register 31 Interrupt Control Register CCMO b A9h CAPCOM Mode Control Register O CCM1 b AAh CAPCOM Mode Control Register 1 302 340 ky ST10F269 USER S MANUAL REGISTER SET Table 56 Special function registers listed by name continued Physical 8 bit Name address address Description CCM2 b FF56h ABh CAPCOM Mode Control Reg
163. Control Register 0000h TO1CON b FF50h CAPCOM Timer 0 and Timer 1 Control Register 0000h CCMO b FF52h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h CAPCOM Mode Control Register 1 0000h CCM2 b FF56h CAPCOM Mode Control Register 2 0000h CCM3 b FF58h CAPCOM Mode Control Register 3 0000h T2IC b FF60h GPT1 Timer 2 Interrupt Control Register 00h T3IC b FF62h GPT1 Timer 3 Interrupt Control Register 00h T4IC b FF64h GPT1 Timer 4 Interrupt Control Register 00h T5IC b FF66h GPT2 Timer 5 Interrupt Control Register 00h T6IC b FF68h GPT2 Timer 6 Interrupt Control Register 00h CRIC b FF6Ah GPT2 CAPREL Interrupt Control Register 00h SOTIC b FF6Ch Serial Channel 0 Transmit Interrupt Control Register 00h SORIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register 00h SOEIC b FF70h Serial Channel O Error Interrupt Control Register 00h SSCTIC b FF72h SSC Transmit Interrupt Control Register 00h SSCRIC b FF74h SSC Receive Interrupt Control Register 00h SSCEIC b FF76h SSC Error Interrupt Control Register 00h CCOIC b FF78h CAPCOM Register 0 Interrupt Control Register 00h CC1IC b FF7Ah CAPCOM Register 1 Interrupt Control Register 00h CC2IC b FF7Ch CAPCOM Register 2 Interrupt Control Register 00h ky 311 340 REGISTER SET ST10F269 USER S MANUAL Table 57 Registers ordered by address continued
164. D PINS coi ro EEN 132 9 THE EXTERNAL BUS INTERFACE ccccsseeceseeceeeeeeeeeeeeesseeeeeeeeeeeeseeeeeeeeeeeseeeeenees 134 9 1 SINGLE CHIP MODE an 134 9 2 EXTERNAL BUS MODES oiie ceececccceeceeeeeeeeeeneeeeeaeeeeeeeeeeeeaeeeeaeeseaeeescaeeeseaeeesenaeeseaas 136 9 2 1 Multiplexed Bus Modes kk 136 9 2 2 De multiplexed BUS Modes coooocccccnnonocccccnonnncnnnnnnnnnnnnnnnnnnnn rn nn 137 9 2 3 Switching Between the BUS Modes 0cocococccccooccconoccconancconnncncnnocanancnnnnn oca nann ca nanacanannccnns 138 9 2 4 External Data Bus Width AAA 139 9 2 5 Disable Enable Control for Pin BHE BYTDIS oonncicnnnccconnccccnnncccnnannncnnnnnnanccnnananananos 140 9 2 6 Segment Address Generation 140 9 2 7 CS Signal Generation 140 9 2 8 Segment Address Versus Chip Select ccccceeeeeeeeeeneeeeeneeeseeeeseaeeeeeeeeeeaeeeseaeeens 141 9 3 PROGRAMMABLE BUS CHARACTERISTICS ooncccnccccnnccncnnonnncnnnncnnonnnananannncnnnccnnnos 142 9 3 1 AE Length Control uti dida 143 9 3 2 Programmable Memory Cycle Time 0 cccccececeeeeeeeeeeeeeeeeeaeeeseaeeeseaeeeeeeaeeseeaeeeneaeeeneas 144 9 3 3 Programmable Memory Tri state Time ooooocccccnnniccccnnnnnonnnononanancnnnonnnn conc nnnnn cnn rra 145 9 3 4 Read Write Signal Delay oooonncccnnnccinnnccononcccnonccnnoncconancnn nono ca nan c nr anna rra 146 9 3 5 READY el aane IG AORE sagas Socata wats EEE A EaR 146 9 3 6 READY READY Controlled Bus Cycles 146 9 3 7 Programmable Chip Select
165. EDUCTION MODES 21 POWER REDUCTION MODES Two different power reduction modes have been implemented in the ST10F269 Idle mode the CPU is stopped while the peripherals continue their operation Idle mode can be terminated by any reset or interrupt request Power down mode both the CPU and the peripherals are stopped Power Down mode can only be terminated by a hardware reset in protected mode or by an external interrupt Note All external bus actions are completed before Idle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not been activated driven low during the last bus access 21 1 Idle Mode The power consumption of the ST10F269 microcontroller can be decreased by entering Idle mode In this mode all peripherals including the watchdog timer continue to operate normally only the CPU operation is halted Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed To prevent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 bit instruction Idle mode is terminated by interrupt request from any enabled interrupt source whose individual Interrupt Enable flag has been set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority lev
166. ERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL 10 THE GENERAL PURPOSE TIMER UNITS The general purpose timer units GPT1 and GPT2 are flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes They incorporate five 16 bit timers that are grouped into the two timer blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters with a maximum resolution of 8 CPU clock cycles while block GPT2 contains 2 timers counters with a maximum resolution of 4 CPU clock cycles and a 16 bit Capture Reload register CAPREL Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or as capture registers for the core timer In the GPT2 block the additional CAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with timers of the CAPCOM units TO T1 T7 and T8 Each block has alternate input output functions and specific interrupts associated with it 10 1 Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs Those portions of port and direction registers which are used for alternate functions by the GPT1 block are named by Y in Figure 68
167. ES CP 1Ch R14 CP 1Ah CP 18h CP 16h R11 CP 14h R10 CP 12h R9 m OSS CP OEh RH7 RL7 R7 CP OCh RH6 RL6 R6 ER CP 08h R4 CP 06h R3 CP 04h R2 ER CP 00h RHO RLO RO 3 2 3 PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00 FCEOh to 00 FCFEh are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 see Figure 7 Whenever a PEC data transfer is performed the pair of source and destination pointers selected by the specified PEC channel number is accessed independently of the current DPP register contents The locations referred to by these pointers are accessed independently of the current DPP register contents If a PEC channel is not used the corresponding pointer locates the area available and can be used for word or byte data storage For more details about the use of the source and destination pointers for PEC data transfers see Chapter 23 System Programming 30 340 ky ST10F269 USER S MANUAL MEMORY ORGANIZATION Figure 7 Location of the PEC pointers 00 FDOOh 00 FCFEh DSTP7 00 FCFCh SRCP7 00 FCDEh Internal PEC RAM source amp destination pointers 00 FCE2h D
168. F269 32 bytes of code data sent by host 5 Caution TXDO is only driven a certain time after reception of the zero byte 6 Internal Boot ROM ky 209 340 BOOTSTRAP LOADER ST10F269 USER S MANUAL When the ST10F269 has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Register SYSCON 0E00h Context Pointer CP FAOOh Register STKUN FA40h Stack Pointer SP FA40h Register STKOV FAOCh 0 lt gt C Register SOCON 8011h Register BUSCONO acc to startup configuration Register SOBG acc to 00 byte P3 10 TXDO T DP3 10 Y In this case the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TXDO is configured as output so the ST10F269 can return the identification byte Even if the internal Flash is enabled no code can be executed out of it The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 for systems that use this feature upon every hardware reset A switchable solution via jumper or an external signal can be used for systems that only temporarily use the bootstrap loader see Figure 107 After sending the identification byte the ASCO receiver is enabled and is ready to receive the initial 32 bytes from the host A half duplex connection is therefore sufficient to feed the BSL Memory Configuration After Reset The
169. FF1Ah 8Dh Bus Configuration Register 4 0000h 40h C CCo FE80h 40h CAPCOM Register 0 0000h CCOIC b h CAPCOM Register O Interrupt Control Register CC 41h CAPCOM Register 1 CC1IC b Dh CAPCOM Register 1 Interrupt Control Register 002 CC2IC b Eh CAPCOM Register 2 Interrupt Control Register 00h SSES Fh CC4 CAPCOM Register 4 CC4IC b CAPCOM Register 4 Interrupt Control Register CC5 CAPCOM Register 5 CC5IC b CAPCOM Register 5 Interrupt Control Register CC6 CAPCOM Register 6 CC6IC b CAPCOM Register 6 Interrupt Control Register CC7 CC7IC b CAPCOM Register 7 Interrupt Control Register CC8 CAPCOM Register 8 CC8IC b CAPCOM Register 8 Interrupt Control Register CC9 CAPCOM Register 9 CC9IC b CAPCOM Register 9 Interrupt Control Register CC10 CAPCOM Register 10 CC10IC b CC11 FE96h 4Bh CAPCOM Register 11 0000h CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register 00h ky 301 340 REGISTER SET ST10F269 USER S MANUAL Table 56 Special function registers listed by name continued 8 bit Physical Name address address Description CC12 FE98h 4Ch CAPCOM Register 12 ES CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC13zIC b CC14 FE9Ch CAPCOM Register 14 CC14IC b CAh CAPCOM Register 14 Interrupt Control Register CC15 4Fh CAPCOM Register 15 CC151C b CBh CAPCOM Register 15 Interrupt
170. FFO6h 83h P1L FFO4h 82h P2 FFCOh EOh P3 FFC4h E2h P4 FFC8h E4h P5 FFA2h Dth P5DIDIS FFA4h D2h P6 FFCCh E6h P7 FFDOh E8h P8 FFD4h EAh PECCx FECyh 6zh see Table 14 PICON F1C4h E2h POCON20 FOAAh 55h POCONx FOyyh zzh for 16 bit Ports POCONx FOyyh zzh for 8 bit Ports PSW FF10h 88h PSW FF10h 88h PWMCONO FF30h 98h 334 340 ESFR XReg ESFR ESFR ESFR ESFR SFR SFR XReg XReg XReg XReg SFR SFR SFR SFR SFR SFR XReg XReg SFR SFR ESFR ESFR ESFR ESFR ESFR ESFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR ESFR ESFR ESFR SFR SFR SFR ST10F269 USER S MANUAL Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value OOOOh 279 UFUUh 260 10DXh o 317 0401h
171. GLVL RW RW RW RW SOEIC FF70h B8 SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOEIR SOEIE ILVL GLVL RW RW RW RW SOTBIC F19Ch CEh ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOTBIR SOTBIE ILVL GLVL RW RW RW RW Note Please refer to Section 6 1 3 Interrupt Control Registers for an explanation of the control fields Using the ASCO Interrupts For normal operation besides the error interrupt the ASCO provides three interrupt requests to control data exchange via this serial channel SOTBIRis activated when data is moved from SOTBUF to the transmit shift register SOTIRis activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted SORIRis activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame For multiple back to back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted In asynchronous mode this leaves just one bit time for the handler to respond to t
172. HITECTURAL OVERVIEW Port4 outputs the additional segment address bit A16 to A23 in systems where segmentation is enabled to access more than 64 Kbytes of memory Port5 is used as analog input channels of the A D converter or as timer control signals Port6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals Port7 provides the output signals from the PWM unit and inputs outputs for the CAPCONZ2 unit Port8 provides inputs outputs for the CAPCOM2 unit Four pins of PORT1 may also be used as inputs only for the CAPCOM2 unit All port lines that are not used for alternate functions may be used as general purpose I O lines 2 5 5 Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Asynchronous Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC They support full duplex asynchronous communication and half duplex synchronous communication The SSC may be configured so it interfaces with serially linked peripheral components Two dedicated Baud rate generators allow to set up all standard Baud rates without oscillator tuning For transmission reception and error handling 3 separate interrupt vectors are provided on channel SSC 4 vectors are provided on channel ASCO In asynchronous mode 8 or 9 bit data frames are tran
173. HRONOUS SERIAL INTERFACE Figure 103 SSC error interrupt control Register SSCCON Register SSCEIR SSCTE oe SSCTE rror SSCRE Receive SSCEIE Error Error SSCRE Interrupt SSCEIR SSCEINT SSCPE Phase Error SSCPE SSCBE Baudrate Error SSCBE SSCTIC FF72h B9h SFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssc SSC ILVL GLVL TIR TIE RW RW RW RW SSCRIC FF74h BAh SFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC ILVL GLVL RIR RIE RW RW RW RW SSCEIC FF76h BBh SFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssc SSC ILVL GLVL EIR ElE RW RW RW RW Note Please refer to Section 6 1 3 Interrupt Control Registers for an explanation of the control fields DI 205 340 WATCHDOG TIMER ST10F269 USER S MANUAL 13 WATCHDOG TIMER The watchdog timer WDT provides recovery from software or hardware failure If the software fails to service this timer before an overflow occurs an internal reset sequence is initiated This internal reset will also pull the RSTOUT pin low this resets the peripheral hardware which might have caused the malfunction When the watchdog timer is enabled and is serviced regularly to prevent overflows the watchdog timer supervises program execution Overflow only occurs if the program does not progress properly The watchdog timer will time out if a software error was due to hardware related failures This prevents
174. IPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL MCW FFDCh EEh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIE LM EM VM CM MP MS RW RW RW RW RW RW RW Bit Function MIE MAC Interrupt Enable 0 MAC interrupt globally disabled 1 MAC interrupt globally enabled LM SL Mask When set the SL Flag can generate a MAC interrupt request EM E Mask When set the E Flag can generate a MAC interrupt request VM SV Mask When set the SV Flag can generate a MAC interrupt request CM C Mask When set the C Flag can generate a MAC interrupt request MP Product Shift Mode When set enables the one bit left shift of the multiplier output in case of a signed signed multiplica tion MS Saturation Mode When set enables automatic 32 bit saturation of the result of a MAC operation MRW FFDAh EDh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW Bit Function MR Repeat Flag Set when a repeated instruction is executed Repeat Count 13 bit unsigned integer value Indicates the number of time minus one a repeated instruction must be executed Note As for the CPU Core SFRs any write operation with the regular instruction set to a single byte of a MAC SFR clears the non addressed complementary byte within the specified SFR Non implemented SFR bits cannot be modified and will always supply a read value of 0 a 68 340
175. L PORTS 7 1 Introduction The ST10F269 has up to 111 parallel I O lines organized into Eight 8 bit I O ports PORTO made of POH and POL PORT1 made of P1H and P1L Port4 Port 6 Port 7 Port8 One 15 bit I O port Port3 One 16 bit input port Port5 One 16 bit I O port Port2 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly by ST10F269 s integrated peripherals or the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers except Port5 The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of five I O ports 2 3 6 7 8 can be configured pin by pin for push pull operation or open drain operation via control registers The logic level of a pin is clocked into the input latch once per CPU clock cycle regardless whether the port is configured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the writ
176. L THE GENERAL PURPOSE TIMER UNITS Figure 74 Connection of the encoder to the ST10F269 T3input T3input ENCODER ST10F269 Interrupt Signal Conditioning For incremental interface operation the following conditions must be met Bit field T3M must be 110b Both pins T3IN and T3EUD must be configured as input at the respective direction control bit with O Bit T3EUD must be 1 to enable automatic direction control The maximum allowed input frequency in incremental interface mode is fepy 16 To ensure correct recognition of the transition of any input signal its level should be held high or low for at least 8 CPU clock cycles In incremental interface mode the count direction is automatically derived from the sequence in which the input signals change This corresponds to the rotation direction of the connected sensor The table below summarizes the possible combinations y T3IN Input T3EUD Input Level on respective ther i t E Rising Falling Rising Falling High Down Up Up Down Low Up Down Down Up ky 165 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL The Figure 75 gives examples of T3 s operation visualizing count signal generation and direction control It also shows how input jitter is compensated This might occur if the sensor stays near to one of the switching points Figure 75 Evaluation of the incremental encoder signa
177. M 0 Leos l Latch P7 0 Pin P7 0 PWMCON1 PENO car BBU DI 241 340 ANALOG DIGITAL CONVERTER ST10F269 USER S MANUAL 17 ANALOG DIGITAL CONVERTER The ST10F269 provides an Analog Digital Converter with 10 bit resolution and a sample A hold circuit on chip A multiplexer selects between up to 16 analog input channels alternate functions of Port5 either via software fixed channel modes or automatically auto scan modes The ADC supports the following conversion modes Fixed channel single conversion produces just one result from the selected channel Fixed channel continuous conversion repeatedly converts the selected channel Auto scan single conversion produces one result from each of a selected group of channels Auto scan continuous conversion repeatedly converts the selected group of channels Wait for ADDAT read mode start a conversion automatically when the previous result was read Channel injection mode insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Figure 128 SFRs and port pins associated with the A D converter Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 P5 IN YYYYYYYYYYYYYYY ADDAT YYYY e YYYYYYYYNYY ANO P5 0 AN15 P5 15 ADDAT2E Y YY Y YY Y YY YYYYY Control Registers Interrupt Control
178. MANUAL ANALOG DIGITAL CONVERTER 17 1 2 Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10 single conversion or to 11 continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in bit field ADCH and ending with channel 0 without requiring software to change the channel number After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel ADCIR will be set after each completed conversion After conversion of channel O the current sequence is complete In single conversion mode the converter will automatically stop and reset bits ADBSY and ADST In continuous conversion mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH When bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and reset bit ADBSY Figure 130 Auto scan conversion mode example Conversion of Chamnel Write ADDAT ADDATFul A VL PP fe LS LiL d Generate Interrupt 5 5 4 5 4 4 al Request
179. MOD30 ACC29 ccmop29 acces CcmMOD28 RW RW RW RW RW RW RW RW Bit Function CCMODx Mode Selection for Capture Compare Register CCx The available capture compare modes are listed in the table below ACCx Allocation bit for Capture Compare Register CCx 0 CCx allocated to Timer TO CAPCOM1 Timer T7 CAPCOM2 1 CCx allocated to Timer T1 CAPCOM1 Timer T8 CAPCOM2 15 3 1 Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode 000 Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage 001 Capture on Positive Transition Rising Edge at Pin CCxlO 010 Capture on Negative Transition Falling Edge at Pin CCxlO 011 Capture on Positive and Negative Transition Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC8 CC15 and CC24 CC31 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer period This mode is required for double register compare mode for registers CCO CC7 and CC16 CC23 110 Compare Mode 2 Interrupt Only Only one interrupt per timer period 111 Compare Mode 3 Set Output Pin on each Match Reset output pin on each timer overflow Only one interrupt per timer period The detailed discussion of the capture and compare modes is valid for all the capture compar
180. NT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to respond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware 6 1 4 Interrupt Priority Level and Group Level The four bits of ILVL bit field specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000b is the lowest and 1111b is the highest priority level When more than one interrupt request on a specific level gets active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced Again the group priority increases with the numerical value of GLVL so 00b is the lowest and 11b is the highest group priority Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt service routine the priority level of the source that wins the arbitration and who s priority level is higher than the current CPU level is copied into ILVL bit field of register PSW after pushing the old PSW contents on the stack The interrupt system of the ST10F269 allows nesting of up to 15 interrupt
181. NVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FORMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States
182. O56h E CAPCOM Timer 8 Reload Register 0000h WDT 57h Watchdog Timer Register read only WDTCON D7h Watchdog Timer Control Register XPOIC C3h CAN1 Module Interrupt Control Register XP1IC C7h CAN2 Module Interrupt Control Register XP2IC CBh Flash ready busy interrupt control register XP3IC CFh PLL unlock Interrupt Control Register XPERCON 12h XPER Configuration Register ZEROS 8Eh Constant Value 0 s Register read only Notes 1 The system configuration is selected during reset 2 Bit WDTR indicates a watchdog timer triggered reset 3 The XPnIC Interrupt Control Registers control interrupt requests from integrated X Bus peripherals Some software controlled interrupt requests may be generated by setting the XPnIR bits of XPnIC register of the unused X peripheral nodes 306 340 a ST10F269 USER S MANUAL REGISTER SET 22 4 Registers Ordered by Address The following table lists all SFRs which are implemented in the ST10F269 ordered by their physical address Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals CAN are marked with the letter X in column Physical Address Table 57 Registers ordered by address Name Address Address Description Value QXO FOO
183. ONTROL dcccccccccnnncnnnoncnnnnnnnnonnnnnnnn cnn non coran ora rann nr rra cc naar rna nn 194 12 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE cooncccccccccconcnccnnnnnnnnncnnanenanans 197 12 1 FULE DUPLEX OPERATION coast latas 201 12 2 HALF DUPLEX OPERATION ista ds litio 203 12 2 1 Port Control asumir ir riera 204 12 3 BAUD RATE GENERATION 205 12 4 ERROR DETECTION MECHANISMS 206 12 5 SSC INTERRUPT CONTROL cooccccccocccconononcnnnccnonnnnnonnnononnnnnnnnncnnnnnnn nano ca rann nn rannncnnnnncins 206 13 WATCHDOG TIMER ege ENEE NEE DEA ve dE ES tawara anaras EE EN 208 13 1 OPERATION OF THE WATCHDOG TIMER 208 14 BOOTSTRAP LOADER iv cccessccccsscesesacsdesenucesexseceeccstecsecereastecs ennerieeneedescieedseceavaceeets 211 15 THE CAPTURE COMPARE UNITS cccssseeceseeeeeeseeeeeeeeeeeeeeeeeeeeeeseseeeeeeeeeeeeseeeeeenes 216 15 1 CAPCOM TIMERS iia teria 219 15 2 CAPCOM UNIT TIMER INTERRUPTS sieeseeseeesseeerresirrsrrnsrrrrsrirssrissrrnnerintsrrnsens 222 15 3 CAPTURE COMPARE REGISTERS A 222 15 3 1 Selection of Capture Modes and Compare Modes A 224 15 4 CAPTURE MODE 2 2 400 2 fas a aaa he Weleda adidas 224 15 5 COMPARE A 225 15 5 1 Compare Mode Ocotal airada 226 15 5 2 Compare Mode Tinaco a A a Ad 227 15 5 3 Compare Mode Zari aine a idad 228 15 5 4 Compare Mode 3 229 15 5 5 Double Register Compare Mode 229 15 6 CAPTURE COMPARE INTERRUPTS AA 231 16 PULSE WIDTH MODULATION MODULE coconccccccnnnccncnccninnnncnnncncnnnnnnnannnnn
184. OOh 223 OOOOh 223 OOOOh 223 OOOOh 224 OOh 231 XXO1h 256 FCOOh coco 53 OOh 185 D000h 51 D0h 102 D0h 102 D0h 105 D0h 105 0000h 107 0000h 111 OOh 115 OOh 122 D0h 126 OOh 129 0101010 52 01010 i 52 0002h 52 0003h 52 0000h 297 OOOOh 89 0000h 279 0000h 297 0101010 108 OOOOh 89 333 340 INDEX OF REGISTERS EXISEL F1DAh Global Mask Short EFO6h EE06h IDCHIP FO7Ch 3Eh IDMANUF FO7Eh 3Fh IDMEM FO7Ah 3Dh IDPROG F078h 3Ch IDXO FFO8h 84h IDX1 FFOAh 85h Interrupt Register EFO2h EE02h IP Lower Arbitration Reg EFn4h EEn4h Lower Global Mask Long EFOAh EEOAh Lower Mask of Last Message EFOEh EEOEh MAH FES5Eh 2Fh MAL FE5Ch 2Eh MCW FFDCh EEh MDC FFOEh 87h MDH FEOCh 06h MDL FEOEh 07h Message Configuration Register EFn6h EEn6h Message Control Register EFnOh EEn0h MRW FFDAh EDh MSW FFDEh EFh ODP2 F1C2h Eth ODP3 F1C6h E3h ODP4 F1CAh E5h ODP6 F1CEh E7h ODP7 F1D2h E9h ODP8 F1D6h EBh ONES FEIER 8Fh POH FFO2h 81h POL FFOOh 80h P1H
185. Oh E MAC Unit Offset Register XO 0000h OX FOO2h E MAC Unit Offset Register X1 0000h QRO Fo04h E MAC Unit Offset Register RO 0000h QR1 FOO6h E MAC Unit Offset Register R1 0000h XPERCON Fo24h E XPER Configuration Register 05h PTO FO30h E PWM Module Up Down Counter O 0000h PT1 F032h E PWM Module Up Down Counter 1 0000h PT2 F034h E PWM Module Up Down Counter 2 0000h PT3 Fo36h E PWM Module Up Down Counter 3 0000h PPO FO38h E PWM Module Period Register 0 0000h PP1 FO3Ah E PWM Module Period Register 1 0000h PP2 FO3Ch E PWM Module Period Register 2 0000h PP3 FO3Eh E PWM Module Period Register 3 0000h T7 FO50h E CAPCOM Timer 7 Register 0000h T8 FO52h E CAPCOM Timer 8 Register 0000h T7REL Fo54h E CAPCOM Timer 7 Reload Register 0000h T8REL Fos6h E CAPCOM Timer 8 Reload Register 0000h IDPROG FO78h E Programming Voltage Identifier Register 0040h IDMEM FO7Ah E On chip Memory Identifier Register 3040h IDCHIP FO7Ch E 3Eh Device Identifier Register n is the device revision 10Dnh IDMANUF FO7Eh E Manufacturer Identifier Register 0401h POCONOL FO80h E PORTO Low Outpout Control Register 8 bit 00h POCONOH FO82h E PORTO High Output Control Register 8 bit 00h POCONIL FO84h E PORT1 Low Output Control Register 8 bit 00h POCON1H FO86h E PORT1 High Output Control Register 8 bit 00h POCON2 FO88h E Port2 Output Control Register 0000h POCON3 FO8Ah E 45h Port3 Output Control Register 0000h POCON4 FO8Ch E Port4 Output Control Register 8 bit 00h
186. POCON6 FO8Eh E Port6 Output Control Register 8 bit 00h POCON7 FO9Oh E 48h Port7 Output Control Register 8 bit 00h POCON8 FO92h E Port8 Output Control Register 8 bit 00h ADDAT2 FOAOh E A D Converter 2 Result Register 0000h POCON20 FOAAh E ALE RD WR Output Control Register 8 bit 0000h SSCTB FOBOh E SSC Transmit Buffer write only 0000h SSCRB FOB2h E SSC Receive Buffer read only XXXXh SSCBR FOB4h E SSC Baud rate Register 0000h DI 307 340 REGISTER SET ST10F269 USER S MANUAL Table 57 Registers ordered by address continued Name Wees Description SE DPOL b F100h E POL Direction Control Register 00h DPOH b F102h E POH Direction Control Register 00h DP1L b F104h E P1L Direction Control Register 00h DP1H b F106h E P1H Direction Control Register 00h RPOH b F108h E 84h System Start up Configuration Register Read only XXh CC16IC b F160h E BOh CAPCOM Register 16 Interrupt Control Register 00h CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register 00h CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register 00h CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register 00h CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register 00h CC21IC b F16Ah E CAPCOM Register 21 Interrupt Control Register 00h CC22IC b Fi6Ch E CAPCOM Register 22 Interrupt
187. POL y Clock Latch y 7 0 The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halves of PORT1 can be written for example via a PEC transfer without effecting the other half If this port is used for general purpose I O the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L FF04h 82h SFR Reset Value 00h 7 3 Port1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW P1H FFO6h 83h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW P1X y Port data register P1H or P1L bit y 102 340 OI ST10F269 USER S MANUAL PARALLEL PORTS DP1L F104h 82h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1L 7 DP1L 6 DP1L 5 DP1L 4 DP1L 3 DP1L 2 DP1L 1 DP1L 0 RW RW RW RW RW RW RW RW DP1H F106h 83h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1H 7 DP1H 6 DP1H 5 DP1H 4 DP1H 3 DP1H 2 DP1H 1 DP1H 0 RW RW RW RW RW RW RW RW Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output 7 3 1 Alternate Functions of PORT1 When a de multiplexed external bus is enabled PORT1 is used as address bus Note that de multiplexed bus modes use PORT1 as a 16 bit port Otherwise al
188. PORTO for system start up configuration Internal e Reset Signal Notes 1 RSTIN rising edge to internal latch of PORTO is 3CPU 6TCL clock cycles if the PLL is bypassed and the prescaler is on fcpy Lena 2 else it is 4 CPU clock cycles 8TCL 2 If during the reset condition RSTIN low Vapp voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered 3 RSTIN pin is pulled low if bit BDRSTEN bit 5 of SYSCON register was previously set by soft ware Bit BDRSTEN is cleared after reset 20 3 Software Reset The reset sequence can be triggered at any time using the protected instruction SRST software reset This instruction can be executed deliberately within a program for example to leave bootstrap loader mode or upon a hardware trap that reveals a system failure Upon execution of the SRST instruction the internal reset sequence 1024 TCL is started The microcontroller behaviour is the same as for a Short Hardware reset except that only P0 12 P0 6 bit are latched at the end of the reset sequence while PO 5 P0 2 bit are cleared 20 4 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or when it is not regularly serviced during program execution it will overflow and it will trigger the reset sequence Unlike hardware and software resets the watchdog reset completes a running
189. PP register select one of the 1024 possible 16 Kbyte data pages while the upper 6 bits are reserved for future use The DPP registers make it possible to access the entire memory space in pages of 16 Kbytes each The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows makes it possible to access data pages 3 0 within segment 0 as shown in the figure below If the user does not want to use any data paging no further action is required DPPO FE00h 00h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Atar DPPOPN RW DPP1 FE02h 01h SFR Reset Value 0001h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ESTA e RW DPP2 FE04h 02h SFR Reset Value 0002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ear TS EE RW DPP3 FE06h 03h SFR Reset Value 0003h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HENARES RW Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx Only the 2 least signifi cant bits of DPPx are used when segmentation is disabled Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit addres
190. PU Clock Request T2 hi 2n n 3 10 si Mode e Control Capture gt CPU Clock 2n n 3 10 T3 Mode Control U D Capture Reload Interrupt Mode Request Control GPT1 Timer T4 interrupt Request T4EUD A P5 14 U D 10 1 1 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bit addressable control register T3CON T3CON FF42h Ath SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T30TL T30E T3UDE T3UD T3R T3M Ta RW RW RW RW RW RW RW RW RW RW RW TSI Timer 3 Input Selection Depends on the operating mode see respective sections T3M Timer 3 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 110 Incremental interface mode 1 XX Reserved Do not use other combination except 110 T3R Timer 3 Run bit T3R 0 Timer Counter 3 stops T3R 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable T3OE Alternate Output Function Enable T30E 0 Alternate Output Function Disabled T3OE 1 Alternate Output Function Enabled T3OTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by soft ware Note 1 For the effects of bit T3UD and T3UDE refer to the direction Table 29
191. RAL PROCESSING UNIT CPU ST10F269 USER S MANUAL Protected bit As mentioned in Section 2 6 Protected bits hardware set are not modified during a read modify write sequence even if an interrupt request rises between read and write time The hardware protection logic guarantees that only the intended bit s is are effected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit See Section 2 6 Protected bits 4 3 Instruction Execution Times Instruction execution time depends on where the instruction is fetched from and where operands are read from or written to When a program is fetched from internal memory most of the instructions can be processed in one instruction cycle All external memory accesses are performed by the on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times A detailed description of the execution times for the various instructions and the specific exceptions can be found in the ST10 Family Programming Manual Table 6 shows the minimum execution times required to process a ST10F269 instruction fetched from the internal Flash the internal RAM or from external memory The values are in CPU clock cycles and assume no wait states Two CPU clock cycles are equal to one instruction cycle
192. RAM organized as 1K x 16 and to two 512 byte blocks of Special Function Registers SFRs The internal RAM is used as System Stack programmable size General Purpose Register Banks GPRs Source and destination pointers for the Peripheral Event Controller PEC Variable and other data storage or Code storage ky 27 340 MEMORY ORGANIZATION ST10F269 USER S MANUAL Figure 6 Internal RAM and SFR ESFR areas l RAM SFR and X pheripherals are 14 050000 l mapped into the address space 00 FFFF E Block6 64 Kbytes SFR 512 bytes 10 04 0000 00 FE00 00 FDFF eg Block5 64 Kbytes IRAM 2 Kbytes DC 03 0000 00 F600 x Is Block4 64 Kbytes op GE 00 F1FF Segment 2 ISegment 3 Segment 4 07 ESFR 512 bytes Block3 32 Kbytes 00 F000 E 06 lorsooo OD EFFF E F AN 256 byt 2 05 Block2 C 56 bytes S E Block1 00 EF00 Di oroo00 P00 00 EEFF CAN2 256 bytes mF 00 EE00 00 C000 y A 00 EC14 2 o H E Real Time Clock o E 00 EC00 3 00 6000 Block2 8 Kbytes J 01 7 Block1 8 Kbytes 00 4000 00 E7FF XRAM1 2 Kbytes 00 E Block0 16 Kbytes 00 0000 00 E000 00 DFFF XRAM2 8 Kbytes 00 C000 Data Absolut Internal Page Memory Flash Number Address Memory Block O 1 2 may be remapped from segment 0 to segment 1 by setting SYSCON ROMS1 before EINIT Data Page Number and Absolut Memo
193. RC check sum was incorrect in the message received TXOK Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK Received Message Successfully Indicates that a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change a Interrupt value in the Interrupt Register if it is pending Use byte accesses to the lower half to avoid this 255 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL 18 3 CAN Interrupt Handling The CAN Modules have one interrupt output which is connected through a synchronization stage to a standard interrupt node in the ST10F269 in the same manner as all other interrupts of the standard on chip peripherals The CAN1 control register interrupt is XPOIC located at address F186h C3h in the ESFR range The associated interrupt vector is called XPOINT at location 100h trap number 40h The CAN2 control register interrupt is XP11C located at address F18Eh
194. REL Register CRINT 00 009Ch 27h A D Conversion Complete ADCINT 00 00A0h 28h A D Overrun Error ADEINT 00 00A4h 29h ASCO Transmit SOTINT 00 00A8h 2Ah ASCO Transmit Buffer SOTBINT 00 011Ch 47h ASCO Receive SORIR SORIE SORINT 00 00ACh 2Bh ASCO Error SOEIR SOEIE SOEINT 00 00B0h 2Ch SSC Transmit SSCTIR SSCTIE SSCTINT 00 00B4h 2Dh SSC Receive SSCRIR SSCRIE SSCRINT 00 00B8h 2Eh SSC Error SSCEIR SSCEIE SSCEINT 00 00BCh 2Fh PWM Channel 0 3 PWMIR PWMIE PWMINT 00 00FCh 3Fh CAN Interface XPOIR XPOIE XPOINT 00 0100h 40h CAN2 Interface XP1IR XP11E XP1INT 00 0104h 41h Flash Ready Busy Flag XP2INT 00 0108h 42h PLL Unlock XP3INT 00 010Ch 43h DI 73 340 INTERRUPT AND TRAP FUNCTIONS Table 13 Vector locations and status for hardware traps ST10F269 USER S MANUAL A ww Trap Trap Vector Trap Trap Exception Condition Flag Vector Location Number Priority Reset Functions MAXIMAL Hardware Reset RESET 00 0000h 00h II Software Reset RESET 00 0000h 00h II Watchdog Timer Overflow RESET 00 0000h 00h II Class A Hardware Traps Non Maskable Interrupt NMITRAP 00 0008h Stack Overflow STOTRAP 00 0010h Stack Underflow STUTRAP 00 0018h Class B Hardware Traps Undefined Opcode UNDOPC 00 0028h Protected Instruction PRTFLT 00 0028h Fault Illegal word Operand ILLOPA 00 0028h Access Illegal Instruction Access ILLINA 00 0028h Illegal External Bus ILLBUS 00 0028h Access MINIMAL Reserved 2Ch 3Ch OBh OFh Software Traps Any 00 0000h Any
195. RPOH F108h 84h 15 14 13 12 11 10 SYSTEM RESET Reset Value XXh 4 3 2 1 0 CLKCFG SALSEL CSSEL WRC Bit R Function R2 R2 R2 WRC CSSEL SALSEL CLKCFG Write Configuration Control 0 Pins WR acts as WRL pin BHE acts as WRH 4 Pins WR and BHE retain their normal function Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CSO 0 1 2 CS lines CS1 CSO 1 0 No CS lines at all 1 1 5 CS lines CS4 CSO Default without pull downs Segment Address Line Selection Number of active segment address outputs 0 0 4 Bit segment address A19 A16 0 1 No segment address lines at all 1 0 8 Bit segment address A23 A16 1 1 2 Bit segment address A17 A16 Default without pull downs POH 7 5 111 110 101 100 011 010 001 000 fopu fxraL X F vm X 4 vm X 3 vm X 2 xTaL X 5 XTAL XTAL X 1 5 vm X 0 5 f f f f f f f f vm X 2 5 Notes Default configuration Direct drive CPU clock via prescaler 3 Notes 1 RPOH 7 to RPOH 5 bits are loaded only during a long hardware reset As pull up resistors are on each POH port pins during reset RPOH default value is FFh 2 These bits are set according to PortO configuration during any reset sequence 3 Using an external crystal with the internal oscillator of 25MHz maximum frequency internal serial resisto
196. SER S MANUAL The internal Flash can still be used for fixed software routines like I O drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memory with the advantage of a flexible adaptable software system Enabling and Disabling the Internal Flash Area After Reset If the internal Flash does not contain an appropriate start up code the system may be booted from external memory while the internal Flash is enabled afterwards to provide access to library routines tables etc If the internal Flash only contains the start up code and or test software the system may be booted from internal Flash which may then be disabled after the software has switched to executing from external memory in order to free the address space occupied by the internal Flash area which is now unnecessary 23 11 Pits Traps and Mines Although handling the internal ROM or Flash provides powerful means to enhance the overall performance and flexibility of a system extreme care must be taken in order to avoid a system crash Instruction memory is the most crucial resource for the ST10F269 and it must be made sure that it never runs out of it The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal Flash access after reset When the first instructions are to be fetched from internal Flash EA the memory must co
197. ST10F269 USER S MANUAL ST10F269 USER S MANUAL TABLE OF CONTENTS Page 1 INTRODUCTION cooonnotoniaiaa ci aia 11 1 1 ABBREVIATION G ee a dad 12 2 ARCHITECTURAL OVERVIEW eoncccconccccccccconnnccnnnnncnananccnnnn nn nnnnr cananea 13 2 1 BASIC CPU CONCEPTS AND OPTIMIZATIONS A 13 2 1 1 High Instruction Bandwidth Fast Execution seeeseeseeeseiesrresrrrserriserrsrrrsrrrrerens 14 2 2 HIGH FUNCTION 8 BIT AND 16 BIT ALL 15 2 2 1 Extended bit Processing and Peripheral Control 15 2 2 2 High Performance Branch Call and Loop Processing coooccconocccinoccccnnnccconnaninnnccnnnos 15 2 2 3 Consistent and Optimized Instruction Formats ccccceeceeeceeeeeeeneeeeeeeeeseneeeeeeeeens 16 2 2 4 Programmable Multiple Priority Interrupt System ccccceeeeeeeeeeeeeseeeeeeeeeeeeeneeetees 16 2 3 ON CHIP SYSTEM RESOURCES aseene irantan inen panen ienaa kanaaro ona da aseni iaaiaee iii 17 2 3 1 Peripheral Event Control and Interrupt Control 17 2 3 2 Memory EE 17 2 3 3 External Bus Interface ek 18 2 4 CLOCK GENERATOR comi e ee te 19 2 4 1 ei BEE ale EE 20 2 4 2 Prescaler Operation wi ccc ooo id lA idad eet 20 2 4 3 Direct Kl 21 2 4 4 Oscillator Watchdog OWD ooconccccnoccconoccccnoncnononcncononcnnancncnnnn co nonn na nann cnn nana n naar ncanannnanas 21 25 ON CHIP PERIPHERAL BLOCK 21 2 5 1 Peripheral lntenaces ine0a ease eege ide tend edit ents 21 2 5 2 Peripheral Timing EE 22 2 5 3 Programming Hi ceci it ita 2
198. ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC These registers are mapped in the SFR space and can addressed by the regular instruction set like any SFR As mentioned previously they can also be addressed by the new instruction COSTORE This instruction allows the user to access the MAC registers without any pipeline side effect COSTORE uses a specific 5 bit addressing mode called CoReg The following table gives the address of the MAC registers in this CoReg addressing mode Table 10 MAC register address in CoReg addressing mode 5 4 MAC Instruction Set Summary The following table gives an overview of the MAC instruction set All the mnemonics are listed with the addressing modes that can be used with each instruction For each combination of mnemonic and addressing mode this table indicates if it is repeatable or not Registers Description Address MSW MAC Unit Status Word 00000b MAH MAC Unit Accumulator High 00001b MAS limited MAH signed 00010b MAL MAC Unit Accumulator Low 00100b MCW MAC Unit Control Word 00101b MRW MAC Unit Repeat Word 00110b 69 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL For full details of the MAC instruction set refer to the ST10 Family Programming Manual Table 11 MAC instruction set summary Mnemonic Addressing Modes Rep Mnemonic Addressing Modes Rep CoMUL RWn RWm No CoMACM IDX 8 Rwm Yes CoMULu
199. ST10F269 provides external bus cycles that are terminated by a READY or READY input signal synchronous or asynchronous In this case the ST10F269 first inserts a programmable number of wait states 0 7 and then monitors the READY or READY line to determine the actual end of the current bus cycle The external device drives READY or READY low in order to indicate that data has been latched write cycle or are available read cycle 144 340 AT ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE When the READY or READY function is enabled for a specific address window each bus cycle in this window must be terminated with the active level defined by the RDYPOL bit in the associated BUSCON register see Figure 62 The READY READY function is enabled by the RDYENx bit in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted wait states 0 7 while the MSB of bit field MCTC selects the READY operation MCTC 3 0 Synchronous READY READY the READY READY signal must meet setup and hold times MCTC 3 1 Asynchronous READY READY the READY READY signal is synchronized internally The synchronous READY READY SREADY SREADY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal should be enabled and may be used by the peripheral logic to control the READY READY timing in this case
200. STPO 00 FCEOh SRCPO 00 F600h 00 F5FEh 3 2 4 Special Function Registers The functions of the CPU the bus interface the UO ports and the on chip peripherals of the ST10F269 are controlled via a number of so called Special Function Registers SFRs These SFRs are arranged within two areas each of 512 byte size The first register block is called the SFR area and is located in the 512 byte above the internal RAM 00 FFFFh 00 FEOOh the second register block the Extended SFR ESFR area is located in the 512 byte below the internal RAM 00 F 1FFh 00 FOOOh Special function registers can be addressed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address makes it possible to address word SFRs and their respective low byte This does not work for the respective high byte Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bit can be directly modified or checked by using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs R15 RO are duplicated and they are acce
201. Section 6 1 Interrupt System Structure PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction The eight hardware trap functions of the ST10F269 are divided into two classes Class A traps These traps share the same trap priority but have an individual vector address External Non Maskable Interrupt NMI Stack Overflow Stack Underflow trap Class B traps These traps share the same trap priority and the same vector address Undefined Opcode Protection Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access Trap The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 DI 89 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL TFR FFACh D6h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMI STK STK UND PRT ILL ILL ILL OF UF OPC FLT OPA INA BUS RW RW RW RW RW RW RW RW Bit Function
202. T10 chip enters power down mode the clock oscillator will be switch off The RTC has 2 interrupt sources one is triggered every basic clock period the other one is the alarm RTCCON includes an interrupt request flag and an interrupt enable bit for each of them This register is read and written via the XBUS RTCCON ECO00h XBUS Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 8 2 1 0 cl PPP oo RTCAEN RTCAIR ATCSEN RTCSIR RW RW RW RW RW RTCOFF RTC Switch Off bit 0 clock oscillator and RTC keep on running even if ST10 in power down mode 1 clock oscillator is switch off if ST10 enters power down mode RTC dividers and counters are stopped and registers can be written RTCAEN RTC Alarm Interrupt ENable 0 RTCAI is disabled 1 RTCAI is enabled it is generated every n seconds RTCAIR RTC Alarm Interrupt Request flag when the alarm is triggered 0 the bit was reseted less than a n seconds ago 1 the interrupt was triggered RTCSEN RTC Second interrupt ENable 0 RTCSI is disabled 1 RTCSI is enabled it is generated every second RTCSIR RTC Second Interrupt Request flag every second 0 the bit was reseted less than a second ago 1 the interrupt was triggered Notes 1 As RTCCON register is not bit addressable the value of these bits must be read by checking their associated CCxIC register The 2 RTC interrupt s
203. T7 allow event scheduling for the capture compare registers relative to external events Both of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 T7 or T8 respectively and programmed for capture or compare function Each register has one port pin associated with it which is an input pin for triggering the capture function or is an output pin except for CC24 CC27 to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers 22 340 ky ST10F269 USER S MANUAL ARCHITECTURAL OVERVIEW When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode 2 5 10 Pulse Width Modulation Unit The Pulse Width Modula
204. Times concoccccccnococcniconanancnnnnnanns 84 TEE 74 SYO EE 16 73 O a aa a raaa a Edit 74 Pr oa lb al 50 L Lower Arbitration REQ sesser 264 Lower Global Mask Long sses 261 Lower Mask of Last Message ace 261 M Master mode arrett iei annainne eekanna 156 MDC canina dla 58 MD it ia oa cies 57 Mk ee ee EE 58 Memory wise stich ieee tel KENE AA 17 bit addressable cccccccccccncncnnccncncncnncnnnnns 30 External 222 EE EES 35 RAMS R casio ira 29 XRAM eege Eege 34 Memory Cycle Time cooccoccccconocccccnoccconanininnncn no 144 Message Configuration Register 264 Message Control Register o oocnncccinnccccnncccco 262 ST10F269 USER S MANUAL Multiplexed BUS cocoooooocccnconccncccconanancnnnonannnos 136 Multiplication ooooonccccninnnccccccccccnnnnccccnnns 57 319 N NMI ien O O 73 93 O ODP 27 td o to 107 ODPI eeni e id of 111 ODRE cc e ies 115 ODPO ici siii 122 OBR Fa E E O as 126 EIERE aere ds anne 129 ONES ee hd i eee ik 59 Open Drain Mode 95 Output Driver Control sessies 99 P POL POM til cis 101 102 PAL Plata detal 291 Eege E 106 PO E 110 PAD eseu Edel 114 115 121 EE eee et 119 PODIDO vsti dee hee ee ee et 121 A Pe Ba Meee 121 Patada india incida 125 Pl tot tere ocio 129 PEC unica loteo dosel 16 17 32 80 RESPONSE TIMES scce 86 PECOX ui 80 Peripheral ne iaai araa AA AA 21 PICON uri da ld e 97 PINS A ee 132 in Idle and Power Down mode aaaa 300 Pipeline ecc i
205. To ensure a proper reset sequence the RSTIN pin and the RPD pin must be held at low level until the MCU clock signal is stabi lized and the system configuration value on PORTO is settled Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application It may be triggerred by the hardware of the application Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 154 155 and 156 ky 279 340 SYSTEM RESET ST10F269 USER S MANUAL Exit of asynchronous reset state When the RSTIN pin is pulled high the MCU restarts The system configuration is latched from PORTO and ALE RD and WR WRL pins are driven to their inactive level The MCU starts program execution from memory location 00 0000h in code segment 0 This starting location will typically point to the general initialization routine Timing of asynchronous reset sequence are summarized in Figure 151 Figure 151 Asynchronous reset timing 3 or 4 CPU Clock evos N RSTIN Asynchronous Reset Condition RPD l RSTOUT N ALE pije PORTO A Reset Configuration INST 1 Latching point of PORTO l Internal for system start up Reset configuration l Signal I Note 1 RSTIN rising edge to internal latch of PORTO is 3CPU clock cycles if the PLL is bypassed and the prescaler is on f cpy f xraL 2 el
206. U Multiply Divide Register Low Word 0000h MRW b FFDAh MAC Unit Repeat Word 0000h MSW o ODP2 b Eth Port 2 Open Drain Control Register ODP3 b E3h Port 3 Open Drain Control Register ODP4 b E5h Port 4 Open Drain Control Register DI 303 340 REGISTER SET ST10F269 USER S MANUAL Table 56 Special function registers listed by name continued Physical 8 bit Name address address Description ODP6 b F1CEh E E7h Port 6 Open Drain Control Register ODP7 b rien E Eon Port7 Open Drain Control Register mr ODP8 b F1D6h E EBh Port 8 Open Drain Control Register 00h ONES b Constant Value 1 s Register read only POL b FFOOh 80h PORTO Low Register Lower half of PORTO POH b 81h PORTO High Register Upper half of PORTO P1L b PORT1 Low Register Lower half of PORT1 P1H b 83 PORT1 High Register Upper half of PORT1 pe FFCOn en Pon Regster L P3 b FFC4h Port 3 Register 0000h P4 b FFC8h EN Port 4 Register 8 bit 00h P6 b E6h Port 6 Register 8 bit P7 b Port 7 Register 8 bit P8 b EAh Port 8 Register 8 bit P5DIDIS b D2h Port 5 Digital Disable Register PORTO Low Outpout Control Register 8 bit 41h PORTO High Output Control Register 8 bit A POCONOL E POCONOH E POCON1L F084h E 42h PORT1 Low Output Control Register 8 bit POCON1H FO86h E PORT1 High Output Control Register 8 bit 00h POCON2 FO88h E 4 Port2 Output Control Register 0000
207. U activity to perform a single data transfer via the on chip PEC System errors detected during program execution so called hardware traps or an external non maskable interrupt are also processed as high priority standard interrupts There is a close conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Therefore the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but if necessary it can be disabled via software Beside its normal operation there are the following particular CPU states Reset state Any reset hardware software watchdog forces the CPU into a predefined active state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running POWER DOWN state All of the on chip clocks are switched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular ST10F269 system control instructions A set of Special Function Registers is dedicated to the functions of the CPU core General System Configuration SYSCON RPOH CPU Status Indication and Control PSW Code Acce
208. US INTERFACE For a given window size only those upper address bit of the start address are used marked R which are not implicitly used for addresses inside the window The lower bit of the start address marked x are disregarded Table 27 Definition of address areas Bit field RGSZ Resulting Window Size Relevant bit R of Start Address A23 A12 A23 A12 0000 4 Kbytes R R R R R R R R R R R R 0001 8 Kbytes R R R R R R R R R R R x 0010 16 Kbytes R R R R R R R R R R x x 0011 32 Kbytes R R R R R R R R R x x x 0100 64 Kbytes R R R R R R R RX Xx X x 0101 128 Kbytes R R R R R R R x X X x x 0110 256 Kbytes R R R R R R x X xXx xXx X x 0111 512 Kbytes R R R R R x X XK XK Xx XX 1000 1 Mbyte R R R R X X X X X Xx xX X 1001 2 Mbytes R R Rx X X X X xX xX XxX X 1010 4 Mbytes H R xX xX xX xX X X xX X XxX xX 1011 8 Mbytes R xX xX X X xX xX xX xX x Xx X 11xx Reserved 9 4 2 Address Window Arbitration For each access the EBC compares the current address with all address select registers programmable ADDRSELx and hardwired XADRSx This comparison is done in four levels The hardwired XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSEL3 respectively A match with one of these registers dire
209. UUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW 258 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Lower Global Mask Long EFOAh EE0Ah XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1D4 0 0 0 0 1D12 5 RW R R R RW Bit Function 1D28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier Upper Mask of Last Message EFOCh EE0Ch XReg Reset Value VUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1D20 18 1D17 13 1D28 21 RW RW RW Lower Mask of Last Message EFOEh EE0Eh XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1D4 0 0 0 0 1D12 5 RW R R R RW Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured 18 4 The Message Object The message object is the primary means of communication between CPU and CAN controller Each of the 15 message objects uses 15 consecutive bytes see Figure 137 and starts at an address that is a multiple of 16 Note All message objects must be initialized by the CPU even those which are not going to be used before clearing the INIT bit Each element of the Message Control Register is made of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements wi
210. VIEW Interruptible Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptible With an interrupt response time within a range from just 150ns to 250ns in case of internal program execution the ST10F269 is capable of fast reaction to non deterministic events The ST10F269 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number 2 3 On chip System Resources The ST10F269 controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family 2 3 1 Peripheral Event Control and Interrupt Control The Periphera
211. W RW RW RW RW RW RW BUSCON1 FF14h 8Ah SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN1 CSREN1 RDYPOL1 RDYEN1 BUSACT1 ALECTL1 BTYP MTTC1 RWDC1 MCTC RW RW RW RW RW RW RW RW RW RW BUSCON2 FF16h 8Bh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN2 CSREN2 RDYPOL2 RDYEN2 BUSACT2 ALECTL2 z BTYP MTTC2 RWDC2 MCTC RW RW RW RW RW RW RW RW RW BUSCON3 FF18h 8Ch SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN3 CSREN3 RDYPOL3 RDYEN3 BUSACT3 ALECTL3 e BTYP MTTC3 RWDC3 MCTC RW RW RW RW RW RW RW RW RW a 148 340 ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE BUSCON4 FF1Ah 8Dh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWEN4 CSREN4 RDYPOL4 RDYEN4 BUSACT4 ALECTL4 BTYP MTTC4 RWDC4 MCTC RW RW RW RW RW RW RW RW RW Bit Function MCTC Memory Cycle Time Control Number of memory cycle time wait states 0000 15 wait states Number of wait states 15 MCTC 111 1 No wait states RWDCx Read Write Delay Control for BUSCONx 0 With read write delay the CPU inserts 1 TCL after falling edge of ALE 1 No read write delay RW is activated after falling edge of ALE MTTCx Memory Tristate Time Control 0 1 wait state 1 No wait state BTYP External Bus Configuration 0 0 8 bit De multiplexed Bus O 1 8 bit Multiplexed Bus 1 0 16 bit De multiplexed Bus 1 1 16 bit Multiplexed Bus
212. W RW RW RW RW RW RW RW Bit Function P2 y Port data register P2 bit y 104 340 iy ST10F269 USER S MANUAL PARALLEL PORTS DP2 FFC2h E1h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP2 15 DP2 14 DP2 13 DP2 12 DP2 11 DP2 10 DP2 9 DP2 8 DP2 7 DP2 6 DP2 5 DP2 4 DP2 3 DP2 2 DP2 1 DP2 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function DP2 y Port direction register DP2 bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output ODP2 F1C2h Eth ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 15 14 13 12 AN 10 9 8 7 6 5 4 3 2 AW D RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function ODP2 y Port2 Open Drain control register bit y ODP2 y 0 Port line P2 y output driver in push pull mode ODP2 y 1 Port line P2 y output driver in open drain mode 7 4 1 Alternate Functions of Port2 All Port2 lines P2 15 P2 0 can be configured capture inputs or compare outputs CC1510 CCOIO for the CAPCOM1 unit When a Port2 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external cap
213. WR High High High High RSTOUT 1 1 1 1 POL Port Latch Data Floating POH Port Latch Data A15 A8 Float Port Latch Data A15 A8 Float PORT1 Port Latch Data Last Address 3 Port Latch Data Last Address Port Latch Data Port Latch Data Port 4 Port Latch Data Port Latch Data Last Port Latch Data Port Latch Data Last segment segment BHE Port Latch Data Last value Port Latch Data Last value HLDA Port Latch Data Last value Port Latch Data Last value BREQ Port Latch Data High Port Latch Data High CSx Port Latch Data Last value 4 Port Latch Data Last value 4 Other Port Port Latch Data Port Latch Data Port Latch Data Port Latch Data Output Pins Alternate Function Alternate Function Alternate Function Alternate Function Notes 1 High if EINIT was executed before entering Idle or Power Down mode Low otherwise 2 For multiplexed buses with 8 bit data bus 3 For de multiplexed buses 4 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inactive high By accessing an on chip X Periperal prior to entering a power save mode all external CS signals can be deactivated 298 340 ky ST10F269 USER S MANUAL REGISTER SET 22 REGISTER SET This section summarizes all registers implemented in the ST10F269 and explains the description format used in the chapters describing the function and layout of the SFRs For easy reference the registers except for GPRs
214. XISEL F1DAh EDh EXISEL F1DAh EDh ky SFR SFR SFR ESFR SFR SFR SFR SFR SFR XReg SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR XReg SFR SFR SFR ESFR ESFR ESFR ESFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR ESFR ESFR ESFR ESFR ESFR INDEX OF REGISTERS Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value OOh 251 0000h 245 0000h 246 OOOOh 246 OOOOh 152 OOOOh 152 OOOOh 152 OOOOh 152 OOh 251 UUUU 260 OxxOh 150 OOOOh 150 OOOOh 150 OOOOh 150 OOOOh 151 OOh 280 OOOOh 223 0101010 223 0101010 223 OOOOh 223 OO
215. XXh CAN1LGML EFOAh CAN1 Lower Global Mask Long XXXXh CAN1UMLM EFOCh CAN1 Upper Mask Last Message XXXXh CAN1LMLM EFOEh CAN1 Lower Mask Last Message XXXXh CAN1MCR1 15 EF10 EFFOh CAN1 Message Control Register 1 to 15 XXXXh CAN1UAR1 15 EF12 EFF2h CAN1 Upper Arbitration Register 1 to 15 XXXXh CAN1LAR1 15 EF14 EFF4h CAN1 Lower Arbitration register 1 to 15 XXXXh CAN1MO1 15 EF1x EFFxh CAN1 Message Object 1 to 15 XXXXh 314 340 ky ST10F269 USER S MANUAL REGISTER SET 22 7 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any short reset the PEC pointers are preserved The PEC and its registers are described in chapter Interrupt and Trap Functions GPR Access in the ESFR Area The locations 00 FOOOh 00 FO1Eh within the ESFR area are reserved and provide access to the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Byte to SFRs All special function registers may be accessed word wise or byte wise some of them even bit wise Reading byte from word SFRs is a non crit
216. a Manual Hardware Reset gt 7 b For Automatic Power up Reset and interruptible power down mode Vop RPD a 284 340 ST10F269 USER S MANUAL SYSTEM RESET Figure 156 External reset hardware circuitry External Hardware ST10F269 External Reset Source 20 7 Pins After Reset After the reset sequence the different groups of pins of the ST10F269 are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can take place or the external control signals are inactive The general purpose I O pins remain in input mode high impedance until reprogrammed via software see Figures 152 and 153 The RSTOUT pin remains active low until the end of the initialization routine see Section 20 5 RSTOUT Pin and Bidirectional Reset Reset output pin The RSTOUT pin generates a reset signal for the system components besides the controller itself RSTOUT is driven active low at the beginning of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed see Figures 152 and 153 This allows the complete configuration of the controller including its on chip peripheral units before
217. a 8 bit Left Right Limiter Shifter Control Unit Shared with standard ALU 5 2 1 Instruction Pipelining All MAC instructions use the 4 stage pipeline During each stage the following tasks are performed FETCH All new instructions are double word instructions DECODE If required operand addresses are calculated and the resulting operands are fetched IDX and GPR pointers are post modified if necessary EXECUTE Performs the MAC operation At the end of the cycle the Accumulator and the MAC condition flags are updated if required Modified GPR pointers are written back during this stage if required WRITEBACK Operand write back in the case of parallel data move 5 2 2 Particular Pipeline Effects with the MAC Unit Because the registers used by the MAC are shared with the standard ALU and because of the MAC instructions pipelining some care must be taken when switching from the standard instruction set to the MAC instruction set DI 59 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL Initialization of the Pointers and Offset Registers The new MAC instructions which use IDXi pointer is mostly not capable of using a new IDXi register value which is to be updated by an immediately preceding instruction Thus to make sure that the new IDXi register value is used at least one instruction must be inserted between a IDXi changing instruction and one MAC instruction whi
218. able control registers T2CON and T4CON which are both organized identically Note that functions which are present in all the 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers T2CON FF40h AOh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gt T2UDE T2UD T2R T2M T2I RW RW RW RW RW T4CON FF44h A2h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 s T4UDE T4UD T4R T4M TA RW RW RW RW RW Bit Function Txl Timer x Input Selection Depends on the Operating Mode see respective sections TxM Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Capture Mode 110 Incremental interface mode 11X Reserved Do not use this combination TxR Timer x Run bit TxR 0 Timer Counter x stops TxR 1 Timer Counter x runs TxUD Timer x Up Down Control TxUDE Timer x External Up Down Enable 1 Note 1 For the effects of bit TXUD and TxUDE refer to the direction Table 32 in T3 section Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply accordingly Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxi
219. able flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is globally enabled IEN 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Figure 157 Transitions between Idle mode and active mode denied Active Mode Executed PEC Request ky 293 340 POWER REDUCTION MODES ST10F269 USER S MANUAL Note An interrupt request which is individually enabled and assigned to priority level O will terminate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable duration interval before Idle mode is entered 21 2 Power Down Mode To reduce power consumption the microcontroller can be switched to Power Down mode Clocking of all internal blocks is stopped The contents of the internal RAM are preserved by the voltage supplied by the Vpp Pins The watchdog timer is stopped
220. access to S x internal Flash El internal Flash Depends on reset 5 g enabled 3 5 enabled a configuration a Bl a El Boy BSL mode active Yes POL 4 0 Yes POL 4 0 No POL 4 1 EA pin High Low Access to application Code fetch from Test Flash access Test Flash access User Flash access internal Flash area Data fetch from User Flash access User Flash access User Flash access internal Flash area Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 bytes via ASCO These bytes are stored sequentially into locations 00 FA40h through 00 FA5Fh of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40h which is the first loaded instruction The bootstrap loading sequence is now terminated the ST10F269 remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code
221. according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose I O ROMEN Internal Memory Enable Set according to pin EA during reset 0 Internal memory disabled accesses to the Flash Memory area use the external bus 1 Internal memory enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal Memory Mapping 0 Internal memory area mapped to segment O 00 0000h 00 7FFFh 1 Internal memory area mapped to segment 1 01 0000h 01 7FFFh STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words The layout of the five BUSCON registers is identical Registers BUSCON4 BUSCON1 which control the selected address windows are completely under software control while register BUSCONO which is also used for the very first code access after reset is partly controlled by hardware and it is initialized via PORTO during the reset sequence This hardware control allows to define an appropriate external bus for systems where no internal program memory is provided BUSCONO FFOCh 86h SFR Reset Value Oxx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSWENO CSRENO RDYPOLO RDYENO BUSACTO ALECTLO BTYP MTTCO RWDCO MCTC RW RW R
222. after reception of byte in synchronous mode SOPEN Parity Check Enable bit asynchronous operation O Ignore parity 1 Check parity SOFEN Framing Check Enable bit asynchronous operation O Ignore framing errors 1 Check framing errors SOOEN Overrun Check Enable bit O Ignore overrun errors 1 Check overrun errors SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection bit 0 Even parity parity bit set on odd number of 1 s in data 1 Odd parity parity bit set on even number of 1 s in data SOBRS Baud rate Selection bit 0 Divide clock by reload value constant depending on mode 1 Additionally reduce serial clock to 2 3rd SOLB Loopback Mode Enable bit 0 Standard transmit receive mode 1 Loopback mode enabled SOR Baud rate Generator Run bit 0 Baud rate generator disabled ASCO inactive 1 Baud rate generator enabled ky 185 340 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer Only the number of data bit which is determined by the selected operating mode will actually be transmitted Bit written to positions 9 through 15 of r
223. al registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and restoring of registers To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two instruction cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the system stack for local registers It is possible to use the SP and CP to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two instruction cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local regist er is then accessed as if it was a normal register Upon exit from the subroutine first the old CP must be restored by popping it from the stack and then the number of used local
224. al communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud rate Generator Run bit SOR is set to 1 Otherwise the serial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combina tions to avoid unpredictable behavior of the serial interface SOTBUF FEBOh 58h SFR Reset Value 0000h 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 E S Baud Rate RW SORBUF FEB2h 59h SFR Reset Value OOXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 g R s Baud Rate RW 186 340 SZA ST10F269 USER S MANUAL ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE 11 1 Asynchronous Operation Asynchronous mode supports full duplex communication where both transmitter and receiver use the same data frame format and the same Baud rate Data is transmitted on pin TXDO P3 10 and received on pin RXDO P3 11 These signals are alternate functions of Port 3 pins Figure 93 Asynchronous mode of serial channel ASCO Reload Register Baud Rate Timer SOR SOM SOSTP SOFE SOPE SOOE Receive Interrupt SOREN Clock Request SOFEN SOPEN Serial Port Control Transmit Interrupt Request RXDO Input SOOEN P3 11 SOLB Shift Clock Error Interrupt S Request TXDO Output P3 10
225. allowing access to 256 Kbytes Note The selected number of segment address lines cannot be changed via software after reset ky 291 340 SYSTEM RESET ST10F269 USER S MANUAL Clock generation control Pins POH 7 POH 6 and POH 5 CLKCFG select the clock generation mode on chip PLL during reset The oscillator clock either directly feeds the CPU and peripherals direct drive or it is fed to the on chip PLL which then provides the CPU clock signal selectable multiple of the oscillator frequency These bits are latched in register RPOH Table 52 CPU frequency generation POH 7 POH 6 POH SI CPU Frequency fcpy fxraL X F External Clock Input Range Notes 1 1 1 2 5 to 10 MHz Default configuration 1 1 0 3 33 to 13 33 MHz 1 0 1 5 to 20 MHz 0 1 1 Fa X 1 1 to 40 MHz Direct drive 0 1 0 Eet x1 5 6 66 to 26 66 MHz 0 0 1 FxraL X 0 5 2 to 80 MHz CPU clock via prescaler 0 0 0 FxraL X 2 5 4 to 16 MHz Notes 1 The external clock input range refers to a CPU clock range of 1 40 MHZ 2 The maximum depends on the duty cycle of the external clock signal 3 The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator providing that internal serial resistance of the crystal is less than 40 Q However higher frequencies can be applied with an external clock source but in this case the input clock signal must reach the defined levels Vu and Vip2 292 340 ky ST10F269 USER S MANUAL POWER R
226. also processed sequentially during compare mode When any two compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 CPU clock cycles after the allocated timer is incremented to the compare value Further compare events on the same compare value are disabled until the timer is incremented again or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register ky 223 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register In the following each of the compare modes including the special double register mode is discussed in detail Table 40 Summary of compare modes Compare Modes Function Mode 0 Interrupt only compare mode several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match several compare events per timer period are possible Mode 2 Interrupt only compare mode only one compare interrupt per timer period is generated Mode 3 Pin set 1 on match pin reset 0 on compare
227. alue is not yet usable for GPR address cal culations of the instruction immediately following the instruction updating the CP register The Switch Context instruction SCXT makes it possible to save the content of register CP on the stack and updating it with a new value in just one instruction cycle Several addressing modes use register CP implicitly for address calculations Short 4 bit GPR addresses mnemonic Rw or Rb specify an address relative to the memory location specified by the contents of the CP register which is the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see Figure 17 Thus both byte and word GPR accesses are possible in this way GPRs used as indirect address pointers are always accessed word wise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physical address calculation is identical to that for the short 4 bit GPR addresses Short 8 bit register addresses mnemonic reg or bitoff within a range from FOh to FFh interpret the four least significant bit as short 4 bit GPR address while the four most significant bit are ignored The respective physical GPR address calculation is identical to that for the short 4 bit GPR addresses
228. and should never be modified by the user in another way than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in Chapter 23 System Programming 4 4 14 The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register addressable constant of all zeros for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS FF1Ch 8Eh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAE cs PON SAO SOS SUK Se eae IEA EA Pe R R R R R R R R R R R R R R R R 4 4 15 The Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES FF1Eh 8Fh SFR Reset Value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e EES R R R R R R R R R R R R R R R R 4 4 16 Example Mask for FFFFh values use to increment or decrement memory sub mem ones mem mem 1 increments the memory location in one instruction instead of three
229. and for auxiliary timer T5 Therefore the pins and bit are named Tx Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON T6OTL can also be set or reset by software Bit T6OE Alternate Output Function Enable in register T6CON enables the state of T6OTL to be an alternate function of the external output pin T6OUT P3 1 For that purpose a 1 must be written into port data latch P3 1 and pin T6OUT P3 1 must be configured as output by setting direction control bit DP3 1 to 1 If T6OE 1 pin T6OUT then outputs the state of T6OTL If T6OE 0 pin T6OUT can be used as general purpose l O pin In addition T6OTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the state of T6OTL does not have to be available at pin T6OUT because an internal connection is provided for this option An overflow or underflow of timer T6 can also be used to clock the timers in the CAPCOM units For this purpose there is a direct internal connection between timer T6 and the CAPCOM timers ky 175 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register TECON to 000b In this mode T6 is clocked with the internal system clock divided by a programmable pre scaler which is selected by bit
230. and peripherals operating with READY READY may be grouped into the same address window The external wait state control logic in this case would activate READY READY either upon the memory s chip select or with the peripheral s READY READY output After the predefined number of wait states the ST10F269 will check its READY READY line to determine the end of the bus cycle For a memory access it will below already see Figure 62 for a peripheral access it may be delayed As memories tend to be faster than peripherals there should be no impact on system performance ky 145 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL When using the READY READY function with so called normally ready peripherals it may lead to erroneous bus cycles if the READY READY line is sampled too early These peripherals pull their READY READY output low while they are idle When they are accessed they deactivate READY READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY READY after the first sample point of the ST10F269 the controller samples an active READY READY and terminates the current bus cycle which of course is too early By inserting predefined wait states the first READY READY sample point can be shifted to a time where the peripheral has safely controlled the READY READY line after 2 wait states in the Figure 62 9 3 7 Programmable Chip Selec
231. arable instructions 327 Upper Arbitration Reg eesis 264 Upper Global Mask Long sessen 260 Upper Mask of Last Message 000 261 Ww Waitstate Memory Cycle conoccccccccccnaccccanccconancnnannnnnns 144 A eene 145 MEA 24 208 287 WDTECON Nina a 208 X ABUS NEE 18 158 XPERCON riin ei RRDA 159 XRAM on chip een 34 Z ZEROS roe ea a e AAE 59 ST10F269 USER S MANUAL 25 INDEX OF REGISTERS ADCIC FF98h CCh ADCON FFAOh DOh ADDAT FEAOh 50h ADDAT2 FOA0h 50h ADDRSEL1 FE18h OCh ADDRSEL2 FE1Ah 0Dh ADDRSEL3 FE1Ch OEh ADDRSEL4 FEIER OFh ADEIC FF9Ah CDh Bit Timing Register EFO4h EE04h BUSCONO FFOCh 86h BUSCON1 FF14h 8Ah BUSCON2 FF 16h 8Bh BUSCONS FF 18h 8Ch BUSCON4 FF1Ah 8Dh CC10IC CC111C CCMO FF52h AQh CCM1 FF54h AAh CCM2 FF56h ABh CCM3 FF58h ACh CCM4 FF22h 91h CCM5 FF24h 92h CCM6 FF26h 93h CCM7 FF28h 94h CCxIC see Table 42 Control Status Register EEOQOh EFOOh CP FE10h 08h CRIC FF6Ah B5h CSP FE08h 04h DPOH F102h 81h DPOL F100h 80h DP1H F106h 83h DP1L F104h 82h DP2 FFC2h Eth DP3 FFC6h E3h DP4 FFCAh E5h DP6 FFCEh E7h mama a see ee DP7 FFD2h E9h DP8 FFD6h EBh DPPO FEOOh 00h DPP1 FEO2h 01h DPP2 FE04h 02h DPP3 FEO6h 03h EXICON F1COh EOh EXICON F1COh EOh EXICON F1COh EXISEL F1DAh EDh E
232. are implemented in the serial channels control registers The ST10F269 provides a vectored interrupt system In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only exceptions are the class B hardware traps which all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the ST10F269 s address space segment 0 The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere within the address space ky 71 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL The entries of the jump table are located at the lowest addresses in code segment O of the address space Each entry occupies 2 words except for the reset vector and the hardware trap vectors which occupy 4 or 8 words The Table 12 lists all sources that are capable of requesting interrupt or PEC service in the ST10F2
233. as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken Execute An operation is performed on the previously fetched operands in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too 36 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Write back All external operands and the remaining operands within the internal RAM space are written back Injected instructions are generated internally by the machine to provide extra time for instructions that require more than one instruction cycle Instructions are automatically injected into the decode stage of the pipeline they pass through the remaining stages like every standard instruction Program interrupts are performed by the same method of injecting instructions Figure 10 Sequential instruction pipelining FETCH l4 lb la l4 l5 le 4 1 1 Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage
234. ata Input Port3 pins with alternate input functions are TOIN T2IN T3IN T4IN T3EUD and CAPIN When the on chip peripheral associated with a Port3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port output latch is cleared When the alternate output functions are not used the Alternate Data Output line is in its inactive state which is a high level 1 Port3 pins with alternate output functions are TEOUT T3OUT TxDO BHE and CLKOUT When the on chip peripheral associated with a Port3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly Port3 pins with alternate input output functions are MTSR MRST RxDO and SCLK Note Enabling the CLKOUT function automatically enables the P3 15 output driver Setting bit DP3 15 1 is not required 110 340 ay ST10F269 USER S MANUAL PARALLEL PORTS Figure 36 Block diagram of Port3 pins Write ODP3 y Open Drain Latch Read ODP3 y Write DP3 y Internal Bus Direction
235. ate DI 141 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL 9 3 2 Programmable Memory Cycle Time The ST10F269 allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change The external bus cycles of the ST10F269 can be extended for a memory or a peripheral which cannot keep pace with the controllers maximum speed some wait states are introduced during the access see Figure 59 During these memory cycle time wait states the CPU is idle if this access is required for the execution of the current instruction The memory cycle time wait states can be programmed in increments of one CPU clock within a range from 0 to 15 default after reset via the MCTC fields of the BUSCON registers 15 MCTC wait states will be inserted Figure 59 Memory cycle time L Bus Cycle gt ALE 1 l l Wu OD Q 3 oO 2 o o o 2 n 1 4 l Il A MCTC Wait States 1 15 142 340 AT ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE 9 3 3 Programmable Memory Tri state Time The ST10F269 allows the user to adjust the time between two subsequent external accesses to address slow external device The tri state time MTTC starts when the
236. ate Data Output via a multiplexer The alternate data can be the 16 bit intra segment address or the 8 16 bit data information The incoming data on PORTO is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active Figure 29 PORTO I O and alternate functions Alternate Functions gt a b c d POH 7 D15 A15 AD15 POH 6 D14 A14 AD14 POH 5 D13 A13 AD13 POH 4 D12 A12 AD12 POH POH 3 D11 A11 AD11 POH 2 D10 A10 AD10 POH 1 D9 A9 AD9 POH 0 D8 A8 AD8 PORTO POL 7 D7 D7 AD7 AD7 POL 6 D6 D6 AD6 AD6 POL 5 D5 D5 AD5 AD5 POL A D4 D4 AD4 AD4 POL POL 3 D3 D3 AD3 AD3 POL 2 D2 D2 AD2 AD2 POL 1 D1 D1 AD1 AD1 POL O DO DO ADO ADO General 8 bit 16 bit 8 bit 16 bit Purpose De multiplexed De multiplexed Multiplexed Multiplexed Input Output Bus Bus Bus Bus ky 101 340 PARALLEL PORTS ST10F269 USER S MANUAL The Figure 30 shows the structure of a PORTO pin Figure 30 Block diagram of a PORTO pin Write DPOH y DPOL y Alternate 1 Direction MUX Direction 0 Read DPOH y DPOL y Alternate Function e Enable Alternate Data Output Write POH y POL y Internal Bus Port Data E Port Output Output SE Latch uffer Read POH y
237. ated Figure 21 Priority levels and PEC channels 5 4 3 2 1 0 Interrupt T T T Control Register ILVL GLVL l d v 2 1 0 PEC Control PEC Channel 76 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS The table below shows in a few examples which action is executed with a given programming of an interrupt control register Priority Level Type of Service ILVL GLVL COUNT 00h COUNT 00h 1111 CPU interrupt level 15 group BE 3 PEC service channel 7 1110 CPU SECH level 4 group priority 2 PEC service channel 2 1101 CPU interrupt level 13 group priority 2 CPU interrupt level 13 group priority 2 0001 CPU interrupt level 1 group priority 3 CPU interrupt level 1 group priority 3 0001 00 CPU interrupt level 1 group priority O CPU interrupt level 1 group priority O 0000 XX No service No service Note All requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine No PECC register is associated and no COUNT field is checked 6 1 5 Interrupt Control Functions in the PSW The Processor Status word PSW is functionally divided into 2 parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the ST10F269 and the arbitration mechanism for the external bus interface Note Pipeline effects have to be
238. ation 110b Reserved Do not use this combination 111b 1024 00 FDFEh 00 F600h Note No circular stack SP 11 SP 0 The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bit of the stack pointer register SP see table with the complementary most significant bit of the upper limit of the physical stack area 00 FBFEh This transformation is done via hardware see Figure 161 320 340 ky ST10F269 USER S MANUAL SYSTEM PROGRAMMING The reset values STKOV FA00h STKUN FCOOh SP FCOOh STKSZ 000b map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 word area is not exceeded Figure 161 Physical stack address generation H FBFEh 1111 1011 1111 1110 FBFEh 1111 1011 11111110 FB80h 1111 1011 1000 0000 Phys A FAOOh 1111 101000000000 FB80h 1111 1011 1000 0000 SP Fsoon 1111 1000 0000 0000 After PUSH After PUSH FBFEh 111110111111 1110 FBFEh 1111 1011 1111 1110 FBFEh 1111 1011 1111 1110 Phys A FBFEh 1111 1011 1111 1110 FB7Eh 111110110111 1110 SP F7FEh 111101111111 1110 64 Words Stack Size 256 Words The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according
239. be continued or not after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environment When the interrupting service routine does not return to the interrupted multiply divide instruction for example in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the task environ ment and must be updated accordingly for the new task before this task is entered ky 47 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon entry into an interrupt service routine but it can also be modified via software to prevent other interrupts from being acknowledged In case an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to Chapter 6 Interrupt and Trap Functions After reset all interrupts are globally disabled and the lo
240. bit 8 of SORBUF In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in multi processor system when the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 for a data byte so no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode by clearing bit SOM 0 which enables it to also receive the data byte that will be coming having the wake up bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data byte see Figure 95 Asynchronous transmission begins at the next overflow of the divide by 16 counter see Figure 95 provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements the start bit the data field 8 or 9 bit LSB first including a parity bit if selected the delimiter
241. bit DP3 4 must be set to 0 Table 29 GPT1 core timer T3 count direction control Pin TxXEUD Bit TXUDE Bit TxUD Count Direction Xx 0 0 Count Up X 0 1 Count Down 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON T3OTL can also be set or reset by software Bit T3OE Alternate Output Function Enable in register T3CON enables the state of T3OTL to be an alternate function of the external output pin T3OUT P3 3 For that purpose a 1 must be written into port data latch P3 3 and pin T3OUT P3 3 must be configured as output by setting direction control bit DP3 3 to 1 If T3OE 1 pin T3OUT then outputs the state of T3OTL If T30E 0 pin T3IOUT can be used as general purpose UO pin In addition T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4 For this purpose the state of T3OTL does not have to be available at pin T3OUT because an internal connection is provided for this option Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 000b
242. bus The output is sign extended and then feeds a scaler that shifts the multiplier output according to the shift mode bit MP specified in the co processor Control Word MCW The product can be shifted one bit left to compensate for the extra sign bit gained in multiplying two 16 bit signed 2 s complement fractional numbers if bit MP is set 5 2 5 40 bit Signed Arithmetic Unit The arithmetic unit over 32 bits wide to allow intermediate overflow in a series of multiply accumulate operations The extension flag E contained in the most significant byte of MSW is set when the Accumulator has overflowed beyond the 32 bit boundary that is when there are significant non sign bits in the top eight signed arithmetic bits of the Accumulator The 40 bit arithmetic unit has two 40 bit input ports A and B The A input port accepts data from 4 possible sources 00 0000 0000h 00 0000 8000h round the sign extended product or the sign extended data conveyed by the 32 bit bus resulting from the concatenation of MA and MB buses Product and Concatenation can be shifted left by one according to MP for the multiplier or to the instruction for the concatenation The B input port is fed either by the 40 bit shifted not shifted and inverted not inverted accumulator or by 00 0000 0000h A input and B input ports can receive 00 0000 0000h to allow direct transfers from the B source and A source respectively to the Accumulator case of Multiplication Shift
243. bus arbitration pins HOLD HLDA and BREQ are automatically controlled by the EBC independent of their UO configuration Bit HLDEN may be cleared during the execution of program sequences where the external resources are required but cannot be shared with other bus masters In this case the ST10F269 will not answer to HOLD requests from other external masters If HLDEN is cleared while the ST10F269 is in hold state code execution from internal RAM Flash this hold state is left only after HOLD has been deactivated again In this case the current hold state continues and only the next HOLD request is not answered ky 153 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL Connecting two ST10F269 s in this way would require additional logic to combine the respective output signals HLDA and BREQ This can be avoided by switching one of the controllers into slave mode where pin HLDA is switched to input This allows to directly connect the slave controller to another master controller without glue logic The slave mode is selected by setting bit DP6 7 to 1 DP6 7 0 default after reset selects the Master Mode Note The pins HOLD HLDA and BREQ keep their alternate function bus arbitration even after the arbitration mechanism has been switched off by clearing HLDEN All three pins are used for bus arbitration after bit HLDEN was set once 9 6 1 Connecting Bus Masters When multiple ST10F269 s or a ST10F269 and an
244. can be made to memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system performance Enabling 4 segment address lines and 5 chip select lines to give access to five memory banks of 1 Mbyte each so the available address space is 5 Mbytes without glue logic Note Bit SGTDIS of register SYSCON defines whether the CSP register is saved during interrupt entry segmentation active or not segmentation disabled ky 139 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL 9 3 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE control defines the ALE signal length and the address hold time after its falling edge Memory cycle time extendable with 1 15 wait states defines the allowable access time Memory tri state time extendable with 1 wait state defines the time for a data driver to float Read write delay time defines when a command is activated after the falling edge of ALE READY polarity is programmable READY control defines if a bus cycle is terminated internally or externally Programmable chip select timing control Note Internal accesses are ex
245. ccurs during a repeat sequence the sequence is stopped and the interrupt routine is executed The repeat sequence resumes at the end of the interrupt routine During the interrupt MR remains set indicating that a repeated instruction has been interrupted and the Repeat Count holds the number minus 1 of repetition that remains to complete the sequence If the Repeat Unit is used in the interrupt routine MRW must be saved by the user and restored before the end of the interrupt routine Note The Repeat Count should be used with caution In this case MR should be written as 0 In gen eral MR should not be set by the user otherwise correct instruction processing can not be guar anteed 64 340 ky ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC 5 2 10 MAC interrupt The MAC can generate an interrupt according to the value of the status flags C carry SV overflow E extension or SL limit of the MSW The MAC interrupt is globally enabled when the MIE flag in MCW is set When it is enabled the flags C SV E or SL can triggered a MAC interrupt when they are set provided that the corresponding mask flag CM VM EM or LM in MCW is also set A MAC interrupt request set the MIR flag in MSW this flag must be reset by the user during the interrupt routine otherwise the interrupt processing restarts when returning from the interrupt routine The MAC interrupt is implemented as a Class B hardware trap trap number Ah trap priority l The
246. ce auto scan modes Setting bit ADST while a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Stop and restart see above are triggered by bit ADST changing from 0 to 1 ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection field ADCH may be changed ADM will be evaluated after the current conversion ADCH will be evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes 17 1 1 Fixed Channel Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 00b single conversion or to 01b continuous conversion After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set In single conversion mode the converter will automatically stop and reset bit ADBSY and ADST In continuous conversion mode the converter will automatically start a new conversion of the channel specified in ADCH ADCIR will be set after each completed conversion When bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop and reset bit ADBSY 244 340 ky ST10F269 USER S
247. ch are not selected for double register compare mode may be used for general purpose UC Figure 120 Timing example for double register compare mode Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000h Interrupt Requests Taas CCxIR CCxIR TyIR CCxIR CCxIR TyIR State of CCxIO l l l t gt x 23 16 7 0 y 0 1 7 8 z 31 24 15 8 15 6 Capture Compare Interrupts Upon a capture or compare event the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also section External Interrupts Note Each of the 32 capture compare registers CCO CC31 has its own bit addressable interrupt control register CCOIC CC31IC and its own interrupt vector CCOINT CC31INT These registers are organized the same way as all other interrupt control registers The figure below shows the basic register layout and the table lists the associated addresses CCxIC see Table 42 SFR ESFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTT T EE ocean RW RW RW RW Note Refer to Interrupt control register
248. ch explicitly uses IDXi in its addressing mode as shown in the following example In MOV IDX0 0F200h Update IDXO register IP must not be an CoXXX IDX0 Rw instruction Ingo CoXXX IDX0 QX1 R2 first operand read at IDX0O address to provide the MAC function parallel data move to IDX0 QX1 address if CoXXX is COMACM move R2 content to IDX0 address if CoXXX is CoMOV IDXO lt IDXO QX1 post modification of the pointer Same requirements between the update of one of the offset reg QXi amp QRi and their next use Read Access to MAC registers CoReg At least one instruction which does not use the MAC must be inserted between two instructions that read from a MAC register This is because the accumulator and the status of the MAC are modified during the execute stage Example 1 Code MSW before MSW after Comment MOV MSW 0 S 0000h MOV RO 0 CoADD RO RO 0000h 0200h MSW Z set at execute BFLDL MSW FFh FFh 0200h OOFFh Error In this example the BFLDL instruction performs a read access to the MSW during the decode stage while the MSW Z flag is only set at the end of the execute stage of the CoADD 5 2 3 Address Generation MAC instructions can use some standard ST10 addressing modes such as GPR direct or data4 for immediate shift value New addressing modes have been added to supply the MAC with two new operands per instruction cycle These allow indirect addres
249. ched 10 Low Current mode Driver always operates with reduced strength 11 Reserved PN1EC ALE Edge Characteristic rise fall time 00 Fast edge mode rise fall times depend on the size of the driver 01 Slow edge mode rise fall times 60 ns 10 Reserved 11 Reserved PN1DC ALE Driver Characteristic output current 00 High Current mode Driver always operates with maximum strength 01 Dynamic Current mode Driver strength is reduced after the target level has been reached 10 Low Current mode Driver always operates with reduced strength 11 Reserved 7 2 PortO The two 8 bit ports POH and POL represent the higher and lower part of PORTO respectively Both halves of PORTO can be written for example via a PEC transfer without effecting the other half If this port is used for general purpose I O the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL FFOOh 80h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW ky 99 340 PARALLEL PORTS ST10F269 USER S MANUAL POH FF02h 81h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function POX y Port data register POH or POL bit y DPOL F100h 80h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW DPOH F102h 81h ESFR Reset Value 00h 15 1
250. cing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if segmented mode and fetches the first instruction 11 from the respective vector location All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine Figure 24 Pipeline diagram for interrupt response time Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 11 DECODE N 1 N TRAP 1 TRAP 2 EXECUTE N 2 N 1 N TRAP WRITEBACK N 3 N 2 N 1 N IR Flag i Interrupt Response Time The minimum interrupt response time is 5 CPU clock cycles This requires program execution from the internal Flash no external operand read requests and setting the interrupt request flag during the last CPU clock cycle of an instruction When the interrupt request flag is set during the first CPU clock cycle of an instruction the minimum interrupt response time under these conditions is 6 CPU clock cycles The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 CPU cl
251. ck via prescaler 0 0 0 ExtaL X 2 5 4 to 16 MHz Notes 1 The external clock input range refers to a CPU clock range of 1 40 MHz 2 The maximum depends on the duty cycle of the external clock signal 3 The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator providing that internal serial resistance of the crystal is less than 40 Q However higher frequencies can be applied with an external clock source but in this case the input clock signal must reach the defined levels Vu and Vip2 2 4 1 PLL Operation The PLL is enabled except when POH 7 5 011 or 001 during reset On power up the PLL provides a stable clock signal within 1ms after Vpp has reached 5V 10 even if there is no external clock signal in this case the PLL will run on its basic frequency of 2 to 10 MHz The PLL starts synchronizing with the external clock signal as soon as it is available Within 1ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F x fxtaL and the PLL locks to the external clock Note If the ST10F269 is required to operate on the desired CPU clock directly after reset make sure that RSTIN remains active until the PLL has locked approx 1ms The PLL constantly synchronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequenc
252. cleared at reset only Row 9 The 8 bit ports P4 P7 and P8 are controlled by P4 has been added Pages 107 110 121 122 124 125 and 128 Page 109 Page 110 Figure 34 36 45 46 48 49 and 51 naming of ODPx y bits has been changed from ODPx y to ODPx y Table 20 row P3 11 RDxO ASCO Receive Data Input Output in synchronous mode Text has been added Figure 35 RDXO has been changed to input output row 13 T6OUT T3OUT TXDO BHE and CLKOUT BHE has been added Page 115 and 116 Figure 40 and 41 have been added structure of Port4 with CANx_RxD and Page 147 Page 148 Page 190 Page 207 Page 209 Page 210 Page 211 Page 278 Page 279 Page 280 Page 288 Page 294 Page 295 Page 301 Page 302 Page 303 Page 304 Page 305 Page 306 338 340 CANx_TxD The reset value of SYSCON register has been changed from 0X00h to Oxx0Oh only some bits of the nibble are cleared at reset The reset value of BUSCONO register has been changed from OXX0h to 0xxOh only some bits of the nibble are cleared at reset Figure 94 RXDO Input Output text has been added The reset value of WDTCON register has been changed from 000Xh to 00xxh only some bits of the nibble are cleared at reset Internal ROM memory has been changed to internal Flash memory Internal ROM memory has been changed to internal Flash memory Figure 106 ROM has been changed to Flash and Boot Rom to Test Flash In
253. cnnnnnanannn canos 233 16 1 OPERATING MODERN 235 16 1 1 Mode 0 Standard PWM Generation Edge Aligned PWM 235 16 1 2 Mode 1 Symmetrical PWM Generation Center Aligned PWM 0ooonocccnnnccnnnccccinnccc n 236 16 1 3 eg OH 238 16 1 4 O 239 16 2 PWM MODULE REOGIGTERG A 240 16 3 INTERRUPT REQUEST GENERATION 242 ky 6 340 ST10F269 USER S MANUAL 16 4 PWM OUTPUT SIGNALS iii di 243 17 ANALOG DIGITAL CONVERTER enccccccccconnnccnnnnncnnnncrnnnnnn nana ncnnanc rca nr rnnnr rca 244 17 1 MODE SELECTION AND OPERDATION 245 17 1 1 Fixed Channel Conversion Modes ccccccceseeeeeneeeeeneeeeeeeeeeeeneeeecaeeeseaeeeseeeeeeneeenaas 246 17 1 2 Auto Scan Conversion Modes oocoooccccnocccononccconocononocononnconano cnn ran cn cnn canaria 247 17 1 3 Wait for ADDAT Read Mode AAA 247 17 1 4 Channel Injection Mode vsessareea aa e aara eea E ae EE EE 248 17 2 CONVERSION TIMING CONTROL cooccncccconcncnnonnnnonncncnnnnnnanncnnonnnanannnnnannnnrannnncinnncnans 251 17 3 A D CONVERTER INTERRUPT CONTROL oocccccccccconnccnnnncnnnnnnoninnnnnonnncnranncnnnn aca ninnnn 251 18 ON CHIP CAN INTERFACES geet REENEN erences 252 18 1 THE CAN CONTROLLER i aa aaa er es aea aanita nano n nr rnn cn ran cnn nr rra nn 252 18 2 REGISTER AND MESSAGE OBJECT ORGANIZATION A 254 18 3 CAN INTERRUPT HANDLING A 258 18 4 THE MESSAGE OBJECT ica ias 261 18 5 ARBITRATION DEOGIGTERG non nc nran cnn rra 263 18 6 INITIALIZATION AND RESET cc nana ca nan rn nan aN arera 272 18 7 CAN
254. considered when enabling disabling interrupt requests via modifications of register PSW see Chapter 4 The Central Processing Unit CPU PSW FF10h SFR Reset Value 0000h 15 14 12 ie rel EN IP RW Bit Function N C V Z E CPU status flags Described in section The Central Processing Unit MULIP USRO Define the current status of the CPU ALU multiplication unit HLDEN HOLD Enable Enables External Bus Arbitration 0 Bus arbitration disabled P6 7 P6 5 may be used for general purpose UO 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD respectively ILVL CPU Priority Level Defines the current priority level for the CPU Fh Highest priority level Oh Lowest priority level IEN Interrupt Enable Control bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled a 77 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL CPU Priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority level that will be serviced Any request on the same or a lower level will not be acknowledged
255. cted from other peripherals for example the CANx controller receive signal CANx_RxD can be used to interrupt the system This new function is controlled using the External Interrupt Source Selection register EXISEL EXISEL F1DAh EDh ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection x 7 0 00 Input from associated Port 2 pin 01 Input from alternate source 10 Input from Port 2 pin ORed with alternate source 117 Input from Port 2 pin ANDed with alternate source EXIxSS Port 2 pin Alternate Source 0 P2 8 CAN1_RxD 1 P2 9 CAN2_RxD 2 P2 10 RTCSI Timed 3 P2 11 RTCAI Alarm 4 7 P2 12 15 Not used zero The upper eight Port2 lines P2 15 P2 8 also support Fast External Interrupt inputs EX7IN EXOIN P2 15 in addition is the input for CAPCOM2 timer T7 T7IN 106 340 ay ST10F269 USER S MANUAL PARALLEL PORTS The Table 19 summarizes the alternate functions of Port2 Table 19 Port2 alternate functions P 2 Pin Alt Function a Alternate Function b Alternate Function c P2 0 CCOlO P2 1 cai lo S P2 2 CC210 S P2 3 CC3I0 P2 4 CC4IO P2 5 Casio P2 6 CC6lO P2 7 CC710 gt P2 8 CC8lO EXOIN Fast External Interrupt 0 Input P2 9 CC9olo EX1IN Fast External Interrupt 1 Input P2 10 CC10IO EX2IN Fast External Interrupt 2 Input
256. cted in compare mode 0 In the example below the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 see Figure 116 224 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS 15 5 2 Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101b When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 and in addition the corresponding output pin CCxIO alternate port output function is toggled For this purpose the state of the respective port output latch not the pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 1 this port pin must be configured as output and the corresponding direction control bit must be set to 1 With this configuration the initial state
257. cted to RPD pin If Bidirectional Reset function is not used the simplest way to reset ST10F269 Q3 is to connect external components as shown in Figure 155 It works with reset from application hardware or manual and with power on The value of C1 capacitor connected on RSTIN pin with internal pull up resistor 50kQ to 250kQ must lead to a charging time long enought to let the internal or external oscillator and or the on chip PLL to stabilize The RO CO components on RPD pin are mainly implemented to provide a time delay to exit Power down mode see Chapter 21 Power Reduction Modes Nervertheless they drive RPD pin level during resets and they lead to different reset modes as explained hereafter On power on CO is totaly discharged a low level on RPD pin forces an asynchronous hardware reset CO capacitor starts to charge throught RO and at the end of reset sequence ST10F269 restarts RPD pin threshold is typically 2 5V Depending on the delay of the next applied reset the MCU can enter a synchronous reset or an asynchronous reset If RPD pin is below 2 5V an asynchronous reset starts if RPD pin is above 2 5V a synchronous reset starts see Section 20 1 Asynchronous Reset Long Hardware Reset and Section 20 2 Synchronous Reset Warm Reset Note that an internal pull down is connected to RPD pin and can drive a 100A to 200uA current This Pull down is turned on when RSTIN pin is low In order to properly use the Bidirectiona
258. ction Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baud rate Error only apply to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable bit is set also an error interrupt request will be generated by setting SSCEIR see figure below The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically like SSCEIR but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is irretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latc
259. ctions can access the PSW register so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required External memory data access does not require special instructions to load data pointers or explicitly load and store external data The ST10F269 provides a unified memory architecture and its on chip hardware automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing a Booth algorithm Each instruction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on bit instructions Multiplication or division is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is t
260. ctor also points to an external location In this case the interrupt response time is the time to perform 9 word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated When the above example has the interrupt vector pointing into the internal Flash the interrupt response time is 7 word bus accesses plus 2 CPU clock cycles because fetching of instruction 11 from internal Flash can start earlier When instructions N N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 word bus accesses When the above example has the interrupt vector pointing into the internal Flash the interrupt response time is 1 word bus access plus 4 CPU clock cycles After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it rea
261. ctrically erased General Purpose Register General Purpose Timer unit High Level Language On chip Internal RAM Input Output Peripheral Event Controller Programmable Logic Array Phase Locked Loop Pulse Width Modulation Random Access Memory Reduced Instruction Set Computing Read Only Memory Special Function Register Synchronous Serial Controller Internal representation of the External Bus On chip extension RAM ST10F269 USER S MANUAL ARCHITECTURAL OVERVIEW 2 ARCHITECTURAL OVERVIEW ST10F269 architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem The following block diagram gives an overview of the different on chip components and of the advanced high bandwidth internal bus structure of the ST10F269 see Figure 1 2 1 Basic CPU Concepts and Optimizations The main core of the CPU includes a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter See Figure 2 Several areas of the processor core have been optimized for performance and flexibility Functional blocks in the CPU core are controlled by signals from the instruction decode logic The core improvements are summarized below and described in detail in the following sections High instruction bandwidth fast execution High function 8 bit and 16 bit arithm
262. cts the access to the respective external area using the corresponding BUSCONx register and ignoring registers ADDRSEL1 3 see Figure 64 A match with registers ADDRSEL1 or ADDRSEL3 directs the access to the respective external area using the corresponding XBCONx register If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO Figure 64 Address window arbitration XBCONO E E Active BUSCON2 WAS I BUSCON4 TI mundo e BUSCON1 C ZZA Buscon3 1 27 Window BUSCONO LILIT ILLIA CLL LST Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined non overlapping ky 151 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL RPOH F108h 84h SFR Reset Value XXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL WRC R R R R WRC 1 Write Configuration Control Set according to pin POH O during reset 0 Pins WR acts as WRL pin BHE acts as WRH 1 Pins WR and BHE retain their normal function CSSEL Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CSO 0 1 2 CS lines CS1 CSO 1 0 No CS lines at all 1 1 5 CS lines CS4 CSO Default without pull downs SALSEL Segment Address Line Selection Number of active segment address
263. cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again ky 135 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started Figure 55 De multiplexed bus cycle Bus Cycle SC i i ALE y 9 2 3 Switching Between the Bus Modes The EBC allows dynamic switching between different bus modes this means that subsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or de multiplexed buses or use READY control or predefined wait states A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONSs are available on the expense of the overhead for changing the registers and keeping appropriate tables Switching between predefined address windows automatically selects the bus mode that is associated with the respective window Pr
264. d and can be accessed CAN2EN CAN2 Enable Bit 0 Accesses to the on chip CAN2 XPeripheral and its functions are disabled P4 4 and P4 7 pins can be used as general purpose I Os Address range 00 EE00h 00 EEFFh is only directed to external memory if CAN1EN is also 0 1 The on chip CAN2 XPeripheral is enabled and can be accessed XRAM1EN XRAM1 Enable Bit 0 Accesses to external memory within space 00 E000h to 00 E7FFh The 2 Kbytes of internal XRAM1 are disabled 1 Accesses to the internal 2 Kbytes of XRAM1 XRAM2EN XRAM2 Enable Bit 0 Accesses to the external memory within space 00 CO00h to 00 DFFFh The 8 Kbytes of internal XRAM2 are disabled 1 Accesses to the internal 8 Kbytes of XRAM2 RTCEN RTC Enable Bit 0 Accesses to the on chip Real Time Clock are disabled external access is performed Address range 00 EC00h 00 ECFFh is only directed to external memory if CAN1EN and CAN2EN are 0 also 1 The on chip Real Time Clock is enabled and can be accessed Note When both CAN are disabled via XPERCON setting then any access in the address range 00 EE00h 00 EFFFh will be directed to external memory interface using the BUSCONx register corresponding to address matching ADDRSELx register P4 4 and P4 7 can be used as General Purpose I O when CAN2 is disabled and P4 5 and P4 6 can be used as General Purpose UO when CANT is disabled
265. d or modified with just one instruction When accessing interrupt control registers through instructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxIC register where xx stands for the mnemonic for the respective source xxIC yyyyh zzh SFR Area Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxIR xxlE ILVL GLVL RW RW RW RW Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests Fh Highest priority level Oh Lowest priority level xxlE Interrupt Enable Control bit individually enables disables a specific source 0 Interrupt Request is disabled 1 Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request DI 75 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs lt is cleared automatically upon entry into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COU
266. des alternate input output functions of timers serial interfaces the optional bus control signal BHE WRH and the system clock output CLKOUT Port5 is used for the analog input channels to the A D converter or timer control signals If the alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a 1 because its output is ANDed with the alternate output data except for PWM output signals If the alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by se
267. details on peripheral timing are included in the specific sections about each peripheral 2 5 3 Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addressing mechanisms are used to access the SFRs Indirect or direct addressing with 16 bit mem addresses it must be guaranteed that the used data page pointer DPPO DPP3 selects data in memory space page 3 accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 byte area short 8 bit reg addresses to the extended ESFR area require switching to the 512 byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bit in either byte of an SFR without disturbing the non addressed byte and the unselected bit Reserved bit some of the bit which are contained in the ST10F269 s SFRs are marked as Reserved User soft
268. ds an operand from internal Flash or if it is executed out of the internal RAM Note A bus access in this context also includes delays caused by an external READY signal or by bus arbitration HOLD mode 6 5 1 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started The basic PEC response time for the ST10F269 is 2 instruction cycles Figure 25 Pipeline diagram for PEC response time Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 N 2 DECODE N 1 N PEC N 1 EXECUTE N 2 N 1 N PEC WRITEBACK N 3 N 2 N 1 N IR Flag PEC Response Time In the Figure the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N 1 All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of prioritization this round is repeated and
269. dth 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose I O ROMEN Internal Memory Enable Set according to pin EA during reset 0 Internal memory disabled accesses to the Flash Memory area use the external bus 1 Internal memory enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal Memory Mapping 0 Internal memory area mapped to segment O 00 0000h 00 7FFFh 1 Internal memory area mapped to segment 1 01 0000h 01 7FFFh STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bit XPER SHARE VISIBLE WRCFG BYTDIS ROMEN and ROMS1 is described in more detail in Section 9 4 Controlling the External Bus Controller System Clock Output Enable CLKEN The system clock output function is enabled by setting bit CLKEN in register SYSCON to 1 If enabled port pin P3 15 takes on its alternate function as CLKOUT output pin The clock output is a 50 duty cycle clock whose frequency equals the CPU operating frequency four feru Note The output driver of port pin P3 15 is switched on automatically when the CLKOUT function is enabled The port directio
270. dule Pulse Width Register 0 0000h PW1 FE32h PWM Module Pulse Width Register 1 0000h Name Description PW2 1Ah PWM Module Pulse Width Register 2 PW3 1Bh PWM Module Pulse Width Register 3 PWMCONO b 98h PWM Module Control Register O PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E B PWM Module Interrupt Control Register 00h QRO F004h E MAC Unit Offset Register RO 0000h E QXO MAC Unit Offset Register XO OX 01h MAC Unit Offset Register X1 RPOH b System Start up Configuration Register read only SOBG 5 Serial Channel 0 Baud Rate Generator Reload Register SOCON b Serial Channel 0 Control Register SOEIC b Serial Channel 0 Error Interrupt Control Register SORBUF gt Ir son Serial Channel 0 Receive Buffer Register read ony 0n SORIC b FF6Eh Serial Channel 0 Receive Interrupt Control Register 00h D SOTBUF FEBOh 58h Serial Channel 0 Transmit Buffer Register write only 0000h B D 99h Fh 02h 03h 00h 84h Ah 8h B8h 59h B7h Eh 58h 6h 09h Ah SSC Baud Rate Register 9h Bh 59h Ah 58h B9h Ah Bh 89h 28h 8h Eh Ah 29h Fh Bh 20h SOTIC b Serial Channel 0 Transmit Interrupt Control Register SP CPU System Stack Pointer Register SSCBR 5 SSCCON b In Doh SSCControlRegister foom SSCEIC b FF76h B SSC Error Interrupt Control Register 00h SSCRB FOB2h E a SSC Receive Buffer read o
271. e INTID or to reset INTID to 00h idle state 2 A message interrupt code is only displayed if there is no other interrupt request with a higher priority Bit Timing Configuration According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Each segment is a multiple of the time quantum tg with ty BRP 1 x2xXtyorK The Synchronization Segment Sync seg is always 1 t long The Propagation Time Segment and the Phase Buffer Segment1 combined to Tseg1 defines the time before the sample point while Phase Buffer Segment2 Tseg2 defines the time after the sample point The length of these segments is programmable except Sync Seg Note For exact definition of these segments please refer to the CAN Specification Figure 136 Bit timing definition 1 bit time __ ____ __ Sync TSeg1 tH d TSeg2 gt T 1 time quantum sample point transmit point a 257 340 ON CHIP CAN INTERFACES Bit Timing Register EF04h EE04h ST10F269 USER S MANUAL Reset Value UUUUh 15 14 13 12 11 10 9 6 2 1 0 0 TSEG2 TSEG1 SJW BRP R RW RW RW RW Bit Function BRP Baud Rate Prescaler For generating the bit time quanta the CPU frequency is divided by 2 x BRP 1 SJW Re Synchronization Jump Width Adjust the bit time by maximum SJW 1 time quanta for re synchron
272. e 22 Mapping of PEC pointers into the internal RAM DSTP7 00 FCFEh SRCP7 00 FCFCh DSTP6 00 FCFAh SRCP6 00 FCF8h DSTP5 00 FCF6h SRCP5 00 FCF4h DSTP4 00 FCF2h SRCP4 00 FCFOh DSTP3 00 FCEEh SRCP3 00 FCECh DSTP2 00 FCEAh SRCP2 00 FCE8h DSTP1 00 FCE6h SRCP1 00 FCE4h DSTPO 00 FCE2h SRCPO 00 FCEOh PEC data transfers do not use the data page pointers DPP3 DPPO The PEC source and destination pointers are used as 16 bit intra segment addresses within segment 0 so data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If word data transfer is selected for a specific PEC channel BWT 0 the respective source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal word Access trap will be invoked when this channel is used 6 3 Prioritizing Interrupt amp PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disregarded and not serviced 6 3 1 Enabling and Disabling Interrupt Requests This may be done in three ways Control bit allow to switch each individual source ON or OFF so it may generate a request or
273. e 79 GPT1 auxiliary timer in reload mode Source Edge Select Reload Register Tx TxIN P3 7 0 gt Interrupt P35 KA S Request Txl 1 Input Interrupt Clock Core T3 Request T30UT Up Down T30TL i Ve T30E x 2 4 Note 1 Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using this single transition mode for both auxiliary t
274. e Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle to detect transitions 6 7 4 Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Otherwise a system reset should be generated 6 7 5 Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and t
275. e channel interrupt request flags PIRx in register PWMCONDO are not automatically cleared by hardware upon entry into the interrupt service routine so they must be cleared via software The module interrupt request flag PWMIR is cleared by hardware upon entry into the service routine regardless of how many channel interrupts were active However it will be set again if during execution of the service routine a new channel interrupt request is generated PWMIC F17Eh BFh ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM PWM ILVL GLVL IR IE RW RW RW RW Note Refer to the general Interrupt Control Register description for an explanation of the control fields 240 340 ky ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE 16 4 PWM Output Signals The output signals of the four PWM channels POUT3 POUTO are alternate output functions on Port7 P7 3 P7 0 The output signal of each PWM channel is individually enabled by control bit PENx in register PWMCON1 The PWM signals are XORed with the respective port latch outputs before being driven to the port pins This allows driving the PWM signal directly to the port pin P7 x 0 or drive the inverted PWM signal P7 x 1 see Figure 127 Note Using the open drain mode on Port 7 allows the combination of two or more PWM outputs through a AND Wired configuration using an external pull up device This provides sort of a burst mode for a
276. e channels so registers bits and pins are only referenced by the place holder x Note Capture compare channels 24 27 generate an interrupt request but do not provide an output signal The resulting exceptions are indicated in the following subsections A capture or compare event on channel 31 may be used to trigger a channel injection on the ST10F269 s A D converter if enabled 15 4 Capture Mode In response to an external event the content of the associated timer TO T1 or T7 T8 depending on the used CAPCOM unit and the state of the allocation control bit ACCx is latched into the respective capture register CCx The external event causing a capture can be programmed to be either a positive a negative or both a positive or a negative transition at the respective external input pin CCxIO The triggering transition is selected by the mode bit CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled see Figure 114 222 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS In order to use the respective port pin as external capture input pin CCxIO for capture register CCx this port pin must be configured as input the corresponding direction control bit by setting to 0 To ensure that a signal transition is properly recognized an external capture in
277. e enabled by configuring an external bus under software control Single chip mode allows the ST10F269 to start execution out of the internal Flash program memory Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS 132 340 oy ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE Figure 53 SFRs and port pins associated with the external bus interface Ports amp Direction Control Alternate Functions Control Registers 1514131211109876543210 1514131211109876543210 POL POH Y Y Y Y Y Y YY YYYYYYYY SYSCON IN Y Y Y Y YYYYYYYYYYY PIUPIH Y Y Y Y Y Y Y Y YY YYYYVYY RPOH YYYYYYYY DP3 EEN A P3 EEN A P4 YYYYYYYYYYYYYYYY ODP6E Y YY YYYYYYYYYYYYY DP6 YYYYYYYYYYYYYYYY P6 YYYYYYYYYYYYYYYY Address Registers Mode Registers 15141312111098 76543210 1514131211109876543210 acid IME YE YE ER ADDRSEL1 Y YYYYYYYYYYYYYYY BUSCON1 Y Y YY YY YY YYYYYY ADDRSEL2 Y Y Y Y Y YYYYYYYYYYY BUSCON2 Y Y YY YY YY YYYYYY ADDRSEL3 Y Y Y Y Y YYYYYYYYYYY BUSCON3 Y Y YY YY YY YYYYYY ADDRSEL4 Y Y Y Y Y YYYYYYYYYYY BUSCON4 Y Y YY YY YY YYYYYY POL POH PORTO Data Registers PORTO EA P1L P1H PORT1 Data Registers PORT1 RSTIN DP3 Port3 Direction Control Register ALE READY P3 Port3 Data Register RD P4 Port4 Data Register WR WRL ODP6 Port6 Open Drain Control Register BHE WRH DP6 Port6 Direction Control Regis
278. e following diagrams summarize the necessary actions to transmit and receive data over the CAN bus The CAN and CPU activities are described including the servicing program Figure 138 CAN controller handling of message objects in transmit direction yes no Received remote frame with same identifier as this message object no NEWDAT 0 load message into buffer Transmission successful INTPND 1 yes no TXRQ 0 RMTPND 0 yes yes O reset 263 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL Figure 139 CPU handling of message objects in transmit direction Power Up all bit undefined TXIE application specific O reset RXIE application specific 1 set INTPND 0 RMTPND 0 TXRQ 0 CPUUPD 1 Identifier application specific Initialisation NEWDAT 0 Direction transmit DLC application specific MSGVAL 1 XTD application specific CPUUPD 1 Update Start NEWDAT 1 Update write calculate message contents Update End CPUUPD 0 no yes update message 264 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES Figure 140 CAN controller handling of message objects in receive direction NEWDAT 0 load identifier and control into buffer Send remote frame no Transmission successful es TXRQ 0 RMTPND 0 yes INTPND 1
279. e number of interrupt sources Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers between any two locations in segment O with an optional increment of either the PEC source or the destination pointer Just one cycle is stolen from the current CPU activity to perform a PEC service Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bit field Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one instruction cycle instruction is used to switch register banks from one task to another 14 340 AT ST10F269 USER S MANUAL ARCHITECTURAL OVER
280. e output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space see Figure 27 ky 93 340 ST10F269 USER S MANUAL PARALLEL PORTS SFRs and pins associated with the parallel ports Figure 26 juo seul JIV YM GH AMAALAAAA KAKAO TR E EA vk A KKK AS oR e ee A AAA AAAAe a AAA AA AAA AA AAA AA AAA A AAA AA AA AAA AAA AA AAA OLZEv S9Z86O0LLLZLEL LSL 1 8S1 4 OJuOg Jong MANO 3 OC NOOOd 8NO90d NO9Od 9NO90d vNO9Od ENOOOd NOJOd HINO9Od INODOd HONO9Od IONODOd A AAA AA AA AAA AAA AA AAA AAA AA ns AA AAA AAA AA AA AA Ar AAA AA AAA AAA AA AAA MARA AE Abee OLZCEVSGOIOLEEOLIICLEL HSL ouoy UE uedo pjoysay L 3 3 3 8ddO daO 9dd0 sialasd bado ddo ddo eale y483 0 sBuojaq ajsibay 3 pajuaue duu jou si JO uogoun Deepen O I OU sey yg uonounj O UB sey yg A NI18d NIZd pajuawejdul aq oU NI94 Nid NIHEd NNEd NIH d N Zd NODld Ss 8dd AAA AA AAA dd AAA AA AAA SC e 9dd AAA A AH AAA 722 22 7 MAALMAAAA AAA AA AA AAA A AAA A tdd IA AA AA AAA AA AAA AA AAA A AAA AAA AAA A dd IA AAA AAA AAA A AAA dd WA A AAA AAA AA AAA A AA AAA AAA AAA AA AAA AA
281. e the minimum values for the clock phases TCLs must be reselected The PLL runs on its basic frequency of 2 to 10 MHz and delivers the clock signal for the Oscillator Watchdog 2 4 4 Oscillator Watchdog OWD In order to provide a fail safe mechanism for the instance of a loss of the external clock an oscillator watchdog is implemented when the selected clock option is direct drive or direct drive with prescaler The oscillator watchdog operates as follows The Oscillator WatchDog OWD is enabled by default after reset To disable the OWD set bit OWDDIS of the SYSCON register When the OWD is enabled the PLL runs on its free running frequency and increments the Oscillator Watchdog counter On each transition of XTAL1 pin the Oscillator Watchdog is cleared If an external clock failure occurs then the Oscillator Watchdog counter overflows after 16 PLL clock cycles The CPU clock signal will be switched to the PLL clock signal in this case the PLL will run on its basic frequency of 2 to 10 MHz and the Oscillator Watchdog Interrupt Request XP3INT is flagged The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin Only a hardware reset can switch the CPU clock source back to external clock input When the OWD is disabled the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current 2 5 On chip Peripheral
282. e the result to 32 bit automatically after every accumulation before to be loaded into the accu mulator The round operation is performed by adding 00 00008000h to the result Automatic saturation is enabled by setting the MCW MS saturation bit When the 40 bit Signed Accumulator is in the overflow saturation mode and an overflow occurs the accumulator is loaded with either the most positive or the most negative possible 32 bit value depending on the direction of the overflow as well as the arithmetic used The value of the accumulator upon saturation is 00 7FFF FFFFh positive or FF 8000 0000h negative 5 2 7 Data Limiter Saturation arithmetic is also provided to selectively limit overflow when reading the accumulator by means of a CoSTORE lt destination gt MAS instruction Limiting is performed on the MAC Accumulator If the contents of the Accumulator can be represented in the destination operand size without overflow the data limiter is disabled and the operand is not modified If the contents of the accumulator cannot be represented without overflow in the destination operand size the limiter will substitute a limited data as explained in the following table Table 9 Limiter output using COSTORE instruction ME flag MN flag MAS value saturated MAH value 0 x Unchanged 1 1 0 7FFFh 2 1 1 8000h Note 1 When data limiter is disabled a reading with CoSTORE lt destination gt lt MAH g
283. ection to the CAN bus This must be provided externally The module s CAN controller is connected to this physical layer the CAN bus via two signals CAN Signal Port Pin Function CAN1 RXD Port4 5 Receive data from the physical layer of the CAN1 bus CANT TXD Port4 6 Transmit data to the physical layer of the CAN1 bus CAN2 RXD Port4 4 Receive data from the physical layer of the CAN2 bus CAN2 TXD Port4 7 Transmit data to the physical layer of the CAN2 bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level DI 271 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL Note If CAN module is used Port 4 cannot be programmed to output all the 8 segment address lines Thus only up to 4 or 2 segments address lines can be used reducing the external memory space to 5 Mbytes 1 Mbyte per CS line Figure 146 Connection to the CAN bus CAN_TxD CAN ST10F269 Interface E km z q EAN _ Physical o Layer 272 340 ST10F269 USER S MANUAL REAL TIME CLOCK 19 REAL TIME CLOCK The Real Time Clock is an independent timer which clock is directly derived from the clock oscillator so that it can keep on running even in Idle or Power down mode if enabled to Registers access is implemented onto the XBUS This module is designed for the following purposes Generate the current time and date for the sy
284. ectly driven to the port pins By setting the respective port output latch to 1 the PWM signal may be inverted XORed with 1 before being driven to the port pin The descriptions below refer to the standard case after reset which is direct drive 16 1 1 Mode 0 Standard PWM Generation Edge Aligned PWM Mode 0 is selected by clearing the respective bit PMx in register PWMCON1 to 0 In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is reset to 0000h and continues counting up with subsequent count pulses The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is reset to 0000h that means below the pulse width shadow register The period of the resulting PWM signal is determined by the value of the respective PPx shadow register plus 1 counted in units of the timer resolution PWM_Peri0dmodeo PPX 1 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register This mechanism allows the selection of duty cycles from 0 to 100 including the boundaries For a value of 0000h the output will remain at a high level representing a duty cycle of 100 For a value higher than the value in the p
285. ecuted with maximum speed and therefore are not programmable External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software Figure 57 Programmable external bus cycle 140 340 kyy ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE 9 3 1 ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bit in the BUSCON registers When bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock cycle Also the address hold time after the falling edge of ALE on a multiplexed bus will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual the data transfer is delayed by one CPU clock cycle This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Figure 58 ALE length control Normal Multiplexed Bus Cycle Lengthened Multiplexed Bus Cycle lt gt lt gt l l l l l l Segment P4 C nares 1 Setup l l l 1 Setup l l l gt gt ae ZN I ZH b be 2 Hold 2 Hold Lb b F l BUS Po CR UCA KEDAN AC sey wares Xba QUIN KX o
286. ed access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time to perform 7 word bus accesses When instructions N and N 1 are executed out of external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 CPU clock cycles Once a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 CPU clock cycles plus the additional time it might take to fetch the source operand from internal Flash or external memory and to write the destination operand over the external bus in an external program environment Note A bus access in this context also includes delays caused by an external READY signal or by bus arbitrat
287. ed bus mode without wait state or read write delay 50 ns access at 40 MHz CPU clock Byte and word accesses are allowed As the XRAM is connected to the internal XBUS it is accessed like external memory however no external bus cycles are executed for these accesses XRAM accesses are globally enabled or disabled via bit XPEN in the SYSCON register This bit is cleared after reset and may be set via software during the initialization to allow accesses to the on chip XRAM When the XRAM is disabled default after reset all accesses to the XRAM area are mapped to external locations Code fetches are always made on even byte addresses The highest possible code storage location in the XRAM is either 00 E7FEh for single word instructions or 00 E7FCh for double word instructions The XRAM1 address range is 00 E000h 00 E7FFh if XPEN bit 2 of SYSCON register and XRAM1EN bit 2 of XPERCON register are set If XRAM1EN or XPEN is cleared then any access in the address range 00 E000h 00 E7FFh will be directed to external memory interface using the BUSCONx register corresponding to address matching ADDRSELx register The XRAM2 address range is 00 CO00h 00 DFFFh if XPEN bit 2 of SYSCON register and XRAM2 bit 3 of XPERCON register are set If bit XRAM2EN or XPEN is cleared then any access in the address range 00 CO00h 00 DFFFh will be directed to external memory interface using the BUSCONx register corresponding to address ma
288. ed for the 14 steps of converting The sample time is a multiple of this conversion time and is selected by bit field ADSTC sample time control The table below lists the possible combinations The timings refer to the unit TCL where fcpy 1 2TCL Table 45 ADC Sampling and Conversion Timing Conversion Clock tcc Sample Clock tsc ADCTC TCL 1 2 x fy TAL At fepu 40MHz At feru 40MHz 00 TCL x 24 0 3us 0 6us 01 Reserved do not use Reserved 10 TCL x 96 1 2 us 11 TCL x 48 0 6 us 11 toc X 16 4 8us A complete conversion will take 14tc tsc 4TCL fastest convertion rate 4 85us at 40MHz This time includes the conversion itself the sample time and the time required to transfer the digital value to the result register Note The ST10F269 ADC does not implement any auto calibration feature 17 3 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT it can be stored it into a table in the internal RAM for later evaluation The interrupt request flag ADEIR in register ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored in
289. ed without the ST10F269 requesting the bus 9 7 The XBUS Interface The ST10F269 provides an on chip interface the XBUS interface which allows to connect integrated costumer application specific peripherals to the standard controller core The XBUS is an internal representation of the external bus interface it works in the same way The current XBUS interface is prepared to support up to 3 X Peripherals For each peripheral on the XBUS X Peripheral there is a separate address window controlled by an XBCON and an XADRS register As an interface to a peripheral in many cases is represented by just a few registers the XADRS registers select smaller address windows than the standard ADDRSEL registers As the register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be byte wide or word wide with or without a separate address bus Visibility of XBUS Peripherals In order to keep the ST10F269 compatible with the ST10C167 and with the ST10F167 the XBUS peripherals can be selected to be visible and or accessible on the external address data bus CAN1EN and CAN2EN bit of XPERCON register must be set If these bit are cleared before the global enabling with XPEN bit in SYSCON register the corresponding address space port pins and interrupts are not
290. edefined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONs However as BUSCONO controls all address areas which are not covered by the other BUSCONs this allows to have gaps between these windows which use the bus mode of BUSCONO PORT1 will output the intra segment address when any of the BUSCON registers selects a de multiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This means that an external address decoder can be connected to PORT1 only while using it for all kinds of bus cycles Note Never change the configuration for an address area that currently supplies the instruction stream Due to the internal pipelines it is very difficult to determine the first instruction fetch that will use the new configuration Only change the configuration for address areas that are not currently accessed This applies to BUSCON registers as well as to ADDRSEL registers The use of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting the physical address No additional switching or selecting is necessary during r
291. egister SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 0000h Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bit in the upper half of SORBUF which are not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit SOOEN When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test seri
292. eir execution to allow very fast interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of byte for word wide arithmetic operations The internal bus structure also allows transfers of byte or words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single instruction cycle Rotate and arithmetic shifts are also supported 2 2 1 Extended bit Processing and Peripheral Control A large number of instructions are dedicated to bit processing These instructions provide efficient control and testing of peripherals and they enhance data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without the need to move them into temporary flags The same logical instructions available for words and byte are also supported for bit This allows the user to compare and modify a control bit for a perip
293. el of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction For a request which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and if the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Otherwise if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction see Figure 157 Idle mode can also be terminated by a Non Maskable Interrupt with a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt En
294. elected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T30OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case see Figure 78 Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 100b In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register triggered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see Table 33 A transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Figure 78 Concatenation of core timer T3 and an auxiliary timer k Interrupt Core Timer T3 Request e T30UT Up Down P3 3 T3l o VI T3R 1 T30E Edge 30 Select Interrupt Request Note 1 Line only affected by over underflows of T3 but NOT by software modifications of T3OTL ky 169 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Figur
295. elevant in the respective mode how ever it is recommended to set these bits to 1 so they are already in the correct state when switching between master and slave mode 12 3 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit Baud rate generator with 16 bit reload capability allowing Baud rate generation independent from the timers The Baud rate generator is clocked by fcpy 2 The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled The formulas below calculate the resulting Baud rate for a given reload value and the required reload value for a given Baud rate fopu 2 x SSCBR 1 fopu Baud ratessc BR 23 ear l 2 x Baud ratessc SSCBR represents the content of the reload register taken as unsigned 16 bit integer Refer to the device datasheet for a table of Baud rates reload values and resulting bit times SSCBR F0B4h 5Ah ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW ky 203 340 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL 12 4 Error Dete
296. equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit Bit Timing Logic This block BTL monitors the bus line input CAN_RxD and handles the bus line related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant bus line transition at Start of Frame hard synchronization and on any further recessive to dominant bus line transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the Baud rate and on external physical delay times Intelligent Memory The Intelligent Memory CAN RAM Array provides storage for up to 15 message objects of maximum 8 data byte length Each of these objects has a unique identifier and its own set of control and status bit After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions 18 2 Register and Message Object Organization All registers and message objects of the CAN controller are located in the special CAN address area of 256 bytes which is mapped into segment 0 The CAN1 address range is 00 EFOOh EFFFh and the CAN2 range is 00 EEOOh EEFFh All registers are organized as 16 b
297. er to be clocked in reference to external events via TxIN Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TXIN The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate for example position tracking The core timers T3 and T6 have output toggle latches TxOTL which change their state on each timer overflow underflow The state of these latches may be output on port pins TxOUT or may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32 33 bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch TxOTL 2 5 8 Watchdog Timer The Watchdog Timer is a fail safe mechanism It limits the maximum malfunction time of the controller The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed In this way the chip s start up procedure is always monitored The software must be designed to service the Watchdog Timer before it overflows If due to hardware or software related
298. eriod register the output will remain at a low level which corresponds to a duty cycle of 0 The Figure 123 illustrates the operation and output waveforms of a PWM channel in mode 0 for different values in the pulse width register This mode is referred to as Edge Aligned PWM because the value in the pulse width shadow register only effects the positive edge of the output signal The negative edge is always fixed and related to the clearing of the timer ky 233 340 PULSE WIDTH MODULATION MODULE ST10F269 USER S MANUAL Figure 123 Operation and output waveform in mode O PPx Period 7 rd 7 7 7 6 6 6 5 5 PTx Count 4 4 Value 3 3 2 2 1 1 1 0 Duty Cycle Seng AS mn en ZELLE eam PWx 2 SE Y 75 Pwx 4 7777 y 50 PWx 7 12 5 PWx 8 0 LSR LSR LSR Latch Shadow Registers Interrupt Request 16 1 2 Mode 1 Symmetrical PWM Generation Center Aligned PWM Mode 1 is selected by setting the respective bit PMx in register PWMCON1 to 1 In this mode the timer PTx of the respective PWM channel is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the count direction is reversed and the timer starts counting down now with subsequent count pulses until it reaches the value 0000h Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses The PWM output signal is switched to a high level when
299. ers and processor status for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Byte must either be converted to word or the respective other byte must be disregarded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD i
300. es 2 and 3 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 l Reload Value lt TyREL gt i 0000h Interrupt i i Requests A TyIR A CCxIR A TyIR Accxn TyIR State of Ccxlo l Ll 0 Ll i 0 Event 1 Event 2 t gt CCx cv2 CCx cv1 x 31 0 Output pin CCxIO only effected in mode 3 No changes in mode 2 y 0 1 7 8 226 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS 15 5 4 Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODXx of the corresponding mode control register to 111b In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 and also the output pin CCxIO alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 3 this port pin must be configured as output and the corresponding direction control bit must be set
301. ese external accesses must use the same configuration as the internally programmed No wait states are required 32 340 ky ST10F269 USER S MANUAL MEMORY ORGANIZATION The configuration in register SYSCON cannot be changed after the execution of the EINIT instruction Figure 8 On chip XRAM area RAM SFR and X pheripherals are mapped into the address space 00 FFFF SFR 512 bytes 00 FE00 00 FDFF IRAM 2 Kbytes 00 F600 4 00 F1FF ESFR 512 bytes 00 F000 00 EFFF CANT 256 bytes DO EFOO 00 EEFF CAN2 256 bytes 00 EE00 4 00 EC14 Real Time Clock 00 EC00 ba 00 E7FF XRAM1 2 Kbytes 00 E000 00 DFFF XRAM2 8 Kbytes 00 C000 Note The address area 00 E800h to 00 EBFFh is mapped to external memory but should be reserved for reasons of upward compatibility 3 4 External Memory Space The ST10F269 is capable of using an address space of up to 16 Mbytes Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory Flash or for registers may refer to external memory locations This external memory is accessed via the ST10F269 s external bus interface Four memory bank sizes are supported Non segmented mode 64 Kbytes with A15 A0 on PORTO or PORT1 2 bit segmented mode 256 Kbytes with A17 A16 on Port4 and A15 A0 on PORTO or PORT1 4 bit segmented mode 1 Mbyte with
302. eset Value Reset Value Reset Value Reset Value 0000h 242 OOH 242 OOOOh 68 OOOOh 68 OOOOh 68 OOOOh 68 A 301 age EE 301 XXh wee 154 XXh wee 291 0 CA 279 0 0 CIA 279 OOR 276 Ah 278 XXXXN eee 277 XXXXN eee 278 XXXXN ee 278 Ah 277 XXXXN 1 eee 277 OOOOh 193 OOOOh 187 OOh 195 OOXXh 188 OOH 195 OOH 195 OOOOh 188 OOh 195 FCOOh 55 OOOOh 205 OOOOh 199 OOOOh 200 OOh 207 XXXXN uu 198 OOh 207 OOOOh 198 OOR 207 FAOOh 56 FCOOh 56 OxxOh 0 45 OxxOh 149 OxxOh 296 OOOOh 220 OOh 222 OOH 222 OOOOh 169 OOH 174 OOOOh 162 OOH 174 OOOOh 169 OOH 174 335 340 INDEX OF REGISTERS T5CON FF46h ASh T5IC FF66h B3h T6CON FF48h A4h T6IC FF68h B4h T78CON FF20h 90h T7IC F17Ah BEh T8IC F17Ch BFh TFR FFACh D6h Upper Arbitration Reg EFn2h EEn2h Upper Global Mask Long EFO8h EE08h Upper Mask of Last Message EFOCh EEOCh WDTCON FFAEh D7h XPOIC F186h C
303. etic and logic unit Extended bit processing and peripheral control High performance branch call and loop processing Consistent and optimized instruction formats Programmable multiple priority interrupt structure Figure 1 ST10F269 functional block diagram OO Go M 32 16 2 Kbyt 256 Kbyte lt 16 Internal Flash Memory CPU Core and MAC Unit A RAM 16 Watchdog 10 Kbyte Lu gt PEC E Gees GE scillator SR and PLL gt 2 gt P4 5 CAN1_RXD gt e P4 6 CAN1_TXD a CAN NA XTALI TAL Interrupt Controller 16 P4 4 CAN2_RXD gt 3 3V Voltage P4 7 CAN2_TXD CAN2 NT i 4 Regulator us ie WR EE EE EE DELETE o E o lt oy SE o o gi S s oo Q 3 oO Q Q e BO lt O ON O O o cb ke E ZS YN OO a a A v e s5 2 lt lt lt 15 xO o NA oO O eg 16 l E lt a 5 gt T SS Es Port 6 Port 5 Port 3 Port 7 Port 8 Je Hie 15 8 He 11 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL Figure 2 CPU block diagram 2 Kbyte Internal RAM MDL Multiplication 256 Kbyte Division Hardware Bit Mask _ General Generator Purpose Execution Unit Registers
304. ferred to as CPU clock Two separated clock signals are generated for the CPU itself and the peripheral part of the chip While the CPU clock is stopped during idle mode the peripheral clock keeps running Both clocks are switched off when the power down mode is entered The on chip PLL circuit allows operation of the ST10F269 on a low frequency external clock while still providing maximum performance The PLL multiplies the external clock frequency by a selectable factor of 1 F and generates a CPU clock signal with 50 duty cycle The PLL also provides fail safe mechanisms which allows the detection of frequency deviations and the execution of emergency actions in case of an external clock failure even when PLL is by passed see Chapter 13 Watchdog Timer Figure 3 PLL block diagram POH 7 POH 6 POH 5 SE Prescaler fopu Oscillator Circuit PLL Circuit eu F x fin Factor reset sleep Unlock XP3INT Y MUX Oscillator Watchdog SZA 17 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL The Table 1 lists all the possible selections for the on chip clock generator Table 1 On chip clock generator selections POH 7 POH 6 POH 5 External Clock Input Range Notes 1 1 1 2 5 to 10 MHz Default configuration 1 1 0 3 33 to 13 33 MHz 1 0 1 5 to 20 MHz 1 0 0 2 to 8 MHz 0 1 1 Fam X 1 1 to 40 MHz Direct drive 0 1 0 Extra X 1 5 6 66 to 26 66 MHz 0 0 1 FxraL X 0 5 2 to 80 MHz CPU clo
305. fetched Execute In this stage the specified operation is performed on the previously fetched operands Write back In this stage the result is written to the specified location If this technique is not used each instruction would require four instruction cycles Pipelining offers increased performance 12 340 ky ST10F269 USER S MANUAL ARCHITECTURAL OVERVIEW 2 2 High Function 8 bit and 16 bit ALU All standard arithmetic and logical operations are performed in a 16 bit ALU In addition the condition flags for byte operations are provided from the sixth and seventh bit of the ALU result Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most of the internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit data Once the pipeline has been filled one instruction is completed per instruction cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow 4 bits to be multiplied and 2 bits to be divided per instruction cycle Thus these operations use two coupled 16 bit registers MDL and MDH and require four and nine instruction cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one instruction cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during th
306. ffers for the maximum message length of 8 bytes The bit timing is derived from the XCLK fepy and is programmable up to a data rate of 1M Baud for CPU clock higher than 16 MHz A CAN Module uses two pins of Port 4 to interface to a bus transceiver The CAN1 transmit line is connected to Port 4 6 and the receive line to Port 4 5 The CAN2 transmit line is connected to Port 4 7 and the receive line to Port 4 4 18 1 The CAN Controller The CAN modules combine several functional blocks that work in parallel These units and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bit Each object can be configured for transmit or receive direction except the last message which is a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bit giving the CPU full flexibility in detecting when a remote data frame has been sent or received Two acceptance filtering masks can be programmed for general purpose one
307. field Tel The input frequency fre for timer T6 and its resolution rre are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula Figure 84 Block diagram of core timer T6 in timer mode Edge Select T6IN ir Interru P5 12 H Core Timer T6 Request Up Down p Dow T6OUT T l T6R ds T6UD T6OE T6EUD P5 10 T6UDE ee fcpu SN 4 x 2116 ee T6 ee 4 x 21161 fopy MHZ The timer resolutions which result from the selected pre scaler option are listed in the Table 35 This table also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in timer and gated timer mode Table 35 GPT2 timer resolution Timer Input Selection T5l T6l 000b 001b 010b 011b 100b 101b 110b 111b Pre scaler factor 4 8 16 32 64 128 256 512 Resolution in CPU clock cycles 4 8 16 32 64 128 256 512 Refer to the device datasheet for a table of timer input frequencies resolution and periods for the range of pre scaler options Timer 6 in Gated Mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to 010b or 011b Bit T6M 0 T6CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T6IN Timer T6 External Input which
308. from the service routine Figure 23 Task status saved on the system stack High Status of Addresses Interrupted Task Low Addresses a System stack before b System stack after b System stack after Interrupt Entry Interrupt Entry unsegmented Interrupt Entry segmented The interrupt request flag of the source that is being serviced is cleared The IP is loaded with the vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched from the respective vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS 6 4 1 Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted with saving and restoring The ST10F269 allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New_Bank pushes the content of the context pointer CP on the system stack and loads CP with the immediate value New_Bank wh
309. from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is emptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly Linear Stack The ST10F269 also offers a linear stack option STKSZ 111b where the system stack may use the complete internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bit of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 FOOOh up to 00 FFFEh the physical system stack must be located within the internal RAM and therefore may only use the address range 00 F600h to 00 FDFEh It is the user s responsibility to restrict the system stack to the internal RAM range Note Avoid stack accesses below the IRAM area ESFR space and reserved area and within address range 00 FEOOh and 00 FFFEh SFR space Otherwise unpredictable results will occur User Stacks
310. fter Scaler one bit left shifter Data limiter Full instruction set with multiply and multiply accumulate 32 bit signed arithmetic and compare instructions Three 16 bit status and control registers MSW MAC Status Word MCW MAC Control Word MRW MAC Repeat Word The working register of the MAC Unit is a dedicated 40 bit wide Accumulator register A set of consistent flags is automatically updated in the MSW register see Section 5 3 2 Accumulator amp Control Registers after each MAC operation These flags allow branching on specific conditions Unlike the PSW flags these flags are not preserved automatically by the CPU upon entry into an interrupt or trap routine All dedicated MAC registers must be saved on the stack if the MAC unit is shared between different tasks and interrupts Program control Repeat Unit allows some MAC co processor instructions to be repeated up to 8192 times Repeated instructions may be interrupted MAC interrupt Class B Trap on MAC condition flags 58 340 ky ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC 5 2 MAC Operation Figure 18 MAC architecture Operand 1 Operand 2 16 x 16 signed unsigned s Multiplier Concatenation 32 32 Mux Oh Repeat Unit Interrupt Controller 4 ST10 CPU 40 bit Signed Arithmetic Unit 40 Flags MAE MAH MAL 40 Dat
311. g inputs The functions of the A D converter are controlled by the bit addressable A D Converter Control Register ADCON Its bit fields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter Result Register ADDAT2 ADCON FFAOh DOh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCTC ADSTC AD AD AD AD ADST ADM ADCH CRQ CIN WR BSY RW RW RW RW RW R RW RW RW Bit Function ADCH ADC Analog Channel Input Selection ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST ADC Start bit ADBSY ADC Busy Flag ADBSY 1 a conversion is active ADWR ADC Wait for Read Control ADCIN ADC Channel Injection Enable ADCRQ ADC Channel Injection Request Flag ADSTC ADC Sample Time Control ADCTC ADC Conversion Time Control Note ADSTC and ADCTC control the conversion timing Refer to Section 17 2 ky 243 340 ANALOG DIGITAL CONVERTER ST10F269 USER S MANUAL Bit field ADCH specifies the analog input channel which is to be converted first channel of a conversion sequence in auto scan modes Bit field ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting bit ADST Clearing ADST stops the A D converter after a certain operation which depends on the selected
312. ged so that SP is outside of the new limits 4 4 11 The Multiply Divide High Register MDH This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bit of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division register MDH represents the 16 bit remainder MDH FE0Ch 06h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDH RW MDH Specifies the high order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in Chapter 23 System Programming DI 55 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL 4 4 12 The Multiply Divide Low Register MDL This register is a part of the 32 bi
313. gister 0 0000h CC FE82h CAPCOM Register 1 0000h CC2 FE84h CAPCOM Register 2 0000h CC3 FE86h CAPCOM Register 3 0000h CC4 FE88h CAPCOM Register 4 0000h CC5 FE8Ah CAPCOM Register 5 0000h CC6 FESCH CAPCOM Register 6 0000h CCT FE8Eh CAPCOM Register 7 0000h CC8 FE90h CAPCOM Register 8 0000h CC9 FE92h CAPCOM Register 9 0000h CC10 FE94h CAPCOM Register 10 0000h CC11 FE96h CAPCOM Register 11 0000h CC12 FE98h CAPCOM Register 12 0000h CC13 FE9Ah CAPCOM Register 13 0000h CC14 FE9Ch CAPCOM Register 14 0000h CC15 FEQEh CAPCOM Register 15 0000h ADDAT FEAOh A D Converter Result Register 0000h WDT FEAEh 57h Watchdog Timer Register read only 0000h SOTBUF FEBOh Serial Channel 0 Transmit Buffer Register write only 0000h SORBUF FEB2h Serial Channel 0 Receive Buffer Register read only XXh SOBG FEB4h Serial Channel 0 Baud Rate Generator Reload Reg 0000h PECCO FECOh PEC Channel 0 Control Register 0000h PECC1 FEC2h PEC Channel 1 Control Register 0000h PECC2 FEC4h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh PEC Channel 7 Control Register 0000h POL b FFOOh Port Low Register Lower half of PORTO 00h POH b FFO2h PortO High Register Upper half of PORTO 00h P1L b FFO4h Port Low Register Lower half of PORT1 00h P1H b FFO6h Port
314. gment Address A17 Segment Address A18 Segment Address A19 GPIO CAN2_RxD GPIO CAN1_RxD GPIO CAN1_TxD GPIO CAN2_TxD A23 A22 A21 A20 A19 A18 A17 A16 Alternate Function SALSEL 10 16 Mbytes Segment Address A16 Segment Address A17 Segment Address A18 Segment Address A19 Segment Address A20 Segment Address A21 Segment Address A22 Segment Address A23 CAN2_TxD CAN1_TxD CAN1_RxD CAN2_RxD A19 A18 A17 A16 CAN I O and Segment Address Lines a ST10F269 USER S MANUAL PARALLEL PORTS Figure 39 Block diagram of a Port4 pin Write DP4 y Direction Latch Read DP4 y Alternate Function e Enable Write P4 y Alternate Data Output Port Output ISS Output Read P4 y Internal Bus Input Latch a 115 340 PARALLEL PORTS ST10F269 USER S MANUAL Figure 40 Block diagram of P4 4 and P4 5 pins Write DP4 x Direction Latch Read DP4 x o Alternate Function Enable Write P4 x Alternate Data _ Output Port Output Latch Output Buffer Internal Bus DO XPERCON a CANyEN CAN Channel CA A h E XPERCON b CANZEN OYN gt Hou Ww wet a 116 340 ST10F269 USER S MANUAL PARALLEL PORTS Figure 41 Block diagram of P4 6 and P4 7 pins Write ODP4 x Open Drain i
315. gram execution and branches to an interrupt service routine in order to service an interrupt requesting device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt processing via the peripheral event controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the ST10F269 s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in segment O data pages O through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers share the 2 highest priority levels Trap functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction Hardware
316. h SOTBUF FEBOh 58h SOTIC FF6Ch B6h SP FE12h 09h SSCBR FOB4h 5Ah SSCCON FFB2h D9h SSCCON FFB2h D9h SSCEIC FF76h BBh SSCRB FOB2h 59h SSCRIC FF74h BAh SSCTB FOBOh 58h SSCTIC FF72h B9h STKOV FE14h OAh STKUN FE16h OBh SYSCON FF12h 89h SYSCON FF12h 89h SYSCON FF12h 89h TO1CON FF50h ASh TOIC FF9Ch CEh T1IC FF9Eh CFh T2CON FF40h AOh T2IC FF60h BOh T3CON FF42h Ath T3IC FF62h B1h T4CON FF44h A2h T4IC FF64h B2h ky SFR ESFR ESFR ESFR ESFR ESFR SFR ESFR XReg SFR ESFR XReg SFR SFR XBUS XBUS XBUS XBUS XBUS XBUS XBUS XBUS XBUS SFR SFR SFR SFR SFR ESFR SFR SFR SFR ESFR SFR SFR SFR ESFR SFR ESFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR INDEX OF REGISTERS Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value R
317. h E F7h UUh CPU General Purpose byte Register RH3 RH3 RL4 F8h CPU General Purpose byte Register RL4 UUh RH4 F9h CPU General Purpose byte Register RH4 UUh RL5 CPU General Purpose byte Register RL5 RH5 CPU General Purpose byte Register RH5 RL6 CPU General Purpose byte Register RL6 RL7 FEh CPU General Purpose byte Register RL7 UUh RH7 FFh CPU General Purpose byte Register RH7 UUh 300 340 ky ST10F269 USER S MANUAL REGISTER SET 22 3 Special Function Registers Ordered by Name The following table lists all SFRs which are implemented in the ST10F269 in alphabetical order Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Table 56 Special function registers listed by name ene Leg La Description ADCIC FF98h A D Converter end of Conversion Interrupt Control Register ADCON A D Converter Control Register ADDAT2 50h A D Converter 2 Result Register 0000h ADDRSEL3 OEh Address Select Register 3 ADDRSEL4 OFh Address Select Register 4 ADEIC CDh__ A D Converter Overrun Error Interrupt Control Register BUSCONO 86h Bus Configuration Register 0 BUSCON1 8Ah Bus Configuration Register 1 BUSCON2 8Bh Bus Configuration Register 2 BUSCON3 Bus Configuration Register 3 0000h 8Ch i i BUSCON4
318. h POCON4 E 4 Port4 Output Control Register 8 bit POCON6 E 4 Port6 Output Control Register 8 bit POCON7 E 4 Port7 Output Control Register 8 bit E POCON8 Fo92h POCON20 FOAAh E PECCO FECOh SC PECC2 PECC3 PECC4 PECC5 PECC6 Port8 Output Control Register 8 bit ALE RD WR Output Control Register 8 bit 00h PEC Channel O Control Register 0000h 61h PEC Channel 1 Control Register 0000h E 8 8 5 6 6 6 6 6 6 6 PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PECC7 PEC Channel 7 Control Register PICON b F1C4h E Port Input Threshold Control Register PPO FO38h E 1Ch PWM Module Period Register 0 0000h PP1 FO3Ah E 1Dh PWM Module Period Register 1 0000h E f E E E E 4 4 4 4 4 E 9h B Fh Oh 2h h Oh 2h 4h 8h 2 Oh 2h 3h h POCONS 6h 7h 8h 9h 5h Oh 2h 3h 4h 5h 6h 7h 2h h PP2 FO3Ch PWM Module Period Register 2 0000h PP3 1Fh PWM Module Period Register 3 PSW b 88 CPU Program Status Word PTO 18h PWM Module Up Down Counter 0 304 340 ky ST10F269 USER S MANUAL REGISTER SET Table 56 Special function registers listed by name continued Physical 8 bit address address PT1 F032h E 19h PWM Module Up Down Counter 1 PT2 F034h E PWM Module Up Down Counter 2 0000h PT3 FO36h E 1Bh PWM Module Up Down Counter 3 0000h Pwo FE30h 18h PWM Mo
319. h double indirect addressing mode Parallel Data Move allows the operand pointed by IDX to be moved to a new location in parallel with the MAC operation The write back address of Parallel Data Move is calculated depending on the post modification of IDX It is obtained by the reverse operation than the one used to calculate the new value of IDX The following table shows these rules Table 8 Parallel data move addressing Instruction Writeback Address CoMACM IDX lt IDX 2 gt CoMACM IDX lt IDX 2 gt CoMACM IDX QX lt IDX QX gt CoMACM IDX QX lt IDX QX gt ky 61 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL The Parallel Data Move shifts a table of operands in parallel with a computation on those operands lts specific use is for signal processing algorithms like filter computation The following figure gives an example of Parallel Data Move with CoMACM instruction Figure 19 Example of parallel data move CoMACM IDX0 R2 16 bit n 2 n 2 lt IDXO n X lt IDXO n X n 2 n 2 D Parallel Data Move n 4 n 4 Before Execution After Execution 5 2 4 16 x 16 Signed unsigned Parallel Multiplier The multiplier executes 16 x 16 bit parallel signed unsigned fractional and integer multiplies The multiplier has two 16 bit input ports and a 32 bit product output port The input ports can accept data from the MA bus and from the MB
320. h the frequency fcpy 2 The input frequency may be switched to fcpy 128 by setting bit WDTIN The watchdog timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFh the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR Watchdog Timer Reset Indication Flag of register WDTCON will be set A hardware reset or the SRVWDT instruction will clear this bit Bit WDTR can be examined by software in order to determine the cause of the reset A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the programmed wait states Otherwise the external bus cycle will be aborted After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled To prevent the watchdog time
321. hannel O Control Register 0000h SSCCON b FFB2h SSC Control Register 0000h P2 b FFCOh Port2 Register 0000h DP2 b FFC2h Port2 Direction Control Register 0000h P3 b FFC4h Port3 Register 0000h DP3 b FFC6h Port3 Direction Control Register 0000h P4 b FFC8h Port4 Register 8 bit 00h DP4 b FFCAh Port4 Direction Control Register 00h P6 b FFCCh Port6 Register 8 bit 00h DP6 b FFCEh Port6 Direction Control Register 00h P7 b FFDOh Port7 Register 8 bit 00h DP7 b FFD2h Ep Port7 Direction Control Register 00h P8 b FFD4h Port8 Register 8 bit 00h DP8 b FFD6h EBh Port8 Direction Control Register 00h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MCW b FFDCh EEh MAC Unit Control Word 0000h MSW b FFDEh EFh MAC Unit Status Word 0200h 312 340 ky ST10F269 USER S MANUAL REGISTER SET 22 5 Xregisters Listed Name Table 58 X registers Listed by Name Name Physical address Description Reset value CAN1BTR EFO4h CANT Bit Timing Register XXXXh CAN1CSR EFOOh CAN1 Control Status Register XXOth CAN1GMS EFO6h CAN1 Global Mask Short XFXXh CAN1IR EFO2h CANT Interrupt Register XXh CAN1LAR1 15 EF14 EFF4h CAN1 Lower Arbitration register 1 to 15 XXXXh CAN1LGML EFOAh CAN1 Lower Global Mask Long XXXXh CAN1LMLM EFOEh CAN1 Lower Mask Last Message XXXXh CAN1MCR1 15 EF10 EFFOh CAN1 Message Con
322. he CPU clock is switched automatically to PLUs base frequency from 2 to 10MHz 1 OWD is disabled If the PLL is bypassed the CPU clock is always driven by XTAL1 signal The PLL is turned off to reduce power supply current PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no effect To exit Power Down Mode an external reset must occurs by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset CSCFG Chip Select Configuration Control 0 Latched Chip Select lines CSx change 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx change with rising edge of ALE a 43 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL Bit Function WRCFG Write Configuration Control Inverted copy of WRC bit of RPOH 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose I O 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus wi
323. he CPU will enter the stack underflow trap routine Again the IP value pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction 6 7 6 Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid ST10F269 opcode the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate non implemented instructions The trap service routine can examine the faulting instruction to decode operands for non implemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed 6 7 7 Protection Fault Trap The format of the protected instructions is 4 byte wide Byte 1 and 2 are complementary values Byte 3 and 4 are identical to byte 1 For example the format of SRST instruction is B7h 48h B7h B7h If the format of a protected instruction going to be executed does not fulfill this c
324. he end of reset the selected bus configuration will be written to the BUSCONO register The configuration of the high byte of PORTO will be copied into the special register RPOH This read only register holds the selection for the number of chip selects and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pull up devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data 100 340 OI ST10F269 USER S MANUAL PARALLEL PORTS In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address During external accesses in de multiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word see Figure 29 When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Altern
325. he first instruction cycle after SOR 1 SOBG FEBA4h 5Ah SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S Baud Rate RW ky 191 340 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL Asynchronous Mode Baud rates For asynchronous operation the Baud rate generator provides a clock with 16 times the rate of the established Baud rate Every received bit is sampled at the 7th 8th and 9th cycle of this clock The Baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given Baud rate can be determined by the following formulas feru Basyne 16 x 2 SOBRS x SOBRL 1 fcpu SOBRL 6 x12 SOBRS x Bayo an SOBRL represents the content of the reload register taken as unsigned 13 bit integer SOBRS represents the value of bit SOBRS 0 or 1 taken as integer Using the above equation the maximum Baud rate can be calculated for any given clock speed The device datasheet gives a table of values for Baud rate vs reload register value for SOBRS 0 and SOBRS 1 Synchronous Mode Baud Rates For synchronous operation the Baud rate generator provides a clock with 4 times the rate of the established Baud rate The Baud rate for synchronous operation of serial channel ASCO can be determined by the following formula 3 fopu Syne 24 x 2 SOBRS x SOBRL 1 fopu SOBRL 4 x 2 SOBRS x Bsync d SOBRL rep
326. he highest priority followed by the stack overflow trap and the stack underflow trap has the lowest priority All class B traps have the same trap priority Trap Priority 1 When several class B traps get active at a time the corresponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority to service simultaneous class B traps is determined by the software in the trap service routine If a class A trap occurs during the execution of a class B trap service routine class A trap will be serviced immediately During the execution of a class A trap service routine no class B trap will be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost If an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap 90 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS 6 7 3 External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskabl
327. he master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be already used to clock in the first data bit So the slave s first data bit must already be valid at this time Note A transmission and a reception takes place at the same time regardless whether valid data has been transmitted or received This is different from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence Select the clock idle level SSCPO x Load the port output latch with the desired clock idle level P3 13 x Switch the pin to output DP3 13 1 Enable the SSC SSCEN 1 If SSCPO 0 enable alternate data output P3 13 1 The same mechanism as for selecting a slave for transmission separate select lines or special commands may also be used to move the role of the master to another device in the network In this case the previous master and the future master p
328. he state of SSCEN prior to the access Writing CO57h to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1 When writing to SSCCON make sure that reserved locations receive zeros The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic See Figure 99 Transmission and reception of serial data is synchronized and takes place at the same time so the same number of transmitted bit is also received Transmit data is written into the Transmit Buffer SSCTB It is moved to the shift register as soon as this is empty An SSC master SSCMS 1 immediately begins transmitting while an SSC slave SSCMS 0 will wait for an active shift clock When the transfer starts the busy flag SSCBSY is set and a transmit interrupt request SSCTIR will be generated to indicate that SSCTB may be reloaded again When the programmed number of bit 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request SSCRIR will be generated If no further transfer is to take place SSCTB is empty SSCBSY will be cleared at the same time Software should not modify SSCBSY as this flag is hardware controlled Only one SSC can be master at a given time The transfer of serial data bit can be programmed in the following ways The data width can be chosen from 2 bits to 16 bi
329. he transmitter interrupt request in synchronous mode it is impossible at all Using the transmit buffer interrupt SOTBIR to reload transmit data gives the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted ky 193 340 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL As shown in the Figure 97 SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted Figure 97 ASCO interrupt generation SOTIR SOTIR SOTIR Idle Idle Synchronous Mode SORIR leis A 194 340 OI ST10F269 USER S MANUAL HIGH SPEED SYNCHRONOUS SERIAL INTERFACE 12 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the ST10F269 and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit Baud
330. hen stored in register MD The overflow flag V is set if the result from a multiply or divide instruction is greater than 16 bit This flag can be used to determine whether both word halves must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state ky 317 340 SYSTEM PROGRAMMING ST10F269 USER S MANUAL The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only req for interrupted multiply divide instructions BSET SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL IZ OD system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc_NV COPYL Test for only 16 Bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE The above save sequence and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multip
331. heral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single instruction cycle In addition bit field instructions have been provided to allow the modification of multiple bit from one operand in a single instruction 2 2 2 High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra instruction cycle only when a branch is taken This is implemented by pre calculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided 1 Single cycle branch execution is provided after the first iteration of a loop Therefore only one instruction cycle is lost during the execution of the entire loop In loops which fall through upon completion no instruction cycle is lost when exiting the loop No special instruction is required to perform loops and loops are automatically detected during execution of branch instructions 2 Detection of the end of a table avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The termi
332. herals In synchronous mode data are transmitted or received synchronously to a shift clock which is generated by the ST10F269 In asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism to distinguish address from data byte is included Testing is supported by a loop back option A 13 bit Baud rate generator provides the ASCO with a separate serial clock signal Figure 92 SFRs and port pins associated with ASCO Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 EE E A OR eee a E SOBG ses YYYYYYYYYYYYFYY O II E SOTBUF Y Y Y Y Y Y YYYYYYYYYY O O GECEEEEEEE SORBUF Y Y Y Y Y Y YYYYYYYYYY Control Registers Interrupt Control 1514131211109876543210 1514131211109876543210 SOCON IY Y Y Y Y YY YYYYYYYY SOTIC re er ee ee d d Y YY Y YY SORIC YY Y YY Y YY SOEIC ee we YYYYYYYY SOTBICE YYYYYYYY RXDO P3 11 TXDO P3 10 ODP3 Port3 Open Drain Control Register DP3 Port3 Direction Control Register P3 Port3 Data Register SOBG ASCO Baud rate Generator Reload Register SOCON ASCO Control Register SOTBUF ASCO Transmit Buffer Register SORBUF ASCO Receive Buffer Register read only SOTIC
333. hich is applied to TxIN is correctly recognized its level should be held for at least 8 CPU clock cycles before it changes Figure 77 Auxiliary timer in counter mode Edge Select Interrupt Request TxUDE Table 33 GPT1 auxiliary timer counter mode input edge selection T2I T4I Triggering Edge for Counter Increment Decrement X00 None Counter Tx is disabled 001 Positive transition rising edge on TxIN 010 Negative transition falling edge on TxIN 011 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of output toggle latch T3OTL 110 Negative transition falling edge of output toggle latch T3OTL 111 Any transition rising or falling edge of output toggle latch T3OTL Timer Concatenation Using the toggle bit T3IOTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter 168 340 OI ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS 32 bit timer counter If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer 33 bit timer counter If either a positive or a negative transition of T3OTL is s
334. hift direction shown in the Figure 101 applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SGSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Section 12 2 1 Port Control Figure 100 Serial clock phase and polarity options Serial Clock sou PLELEI Ge EST e le TTT Pins MTSR MRST A Ae CX X X First T Last bit A Transmit Data bit Latch Data Shift Data ky 199 340 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL Figure 101 SSC full duplex configuration Master Device 1 Device 2 Slave Shift Register Shift Register Transmit Receive Device 2 Slave The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line it enables the driver of its MRST pin All the other slaves have to program there MRST pins to input So only one slave can put its data onto the master s receive line Only receiving of data from
335. hing edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed Baud rate by more than 100 it either is more than double or less than half the expected Baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requires that the slave s Baud rate generator is programmed to the same Baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SSCAREN 1 an automatic reset of the SSC will be per formed in case of this error This is done to re initialize the SSC if too few or too many clock pulses have been detected A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead
336. his ensures that the ST10F269 and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pull down and pins RD and WR are held high through internal pull ups Also the pins selected for CS output will be pulled high The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO The reset configurations are summarized in Table 50 and Table 51 When an external start is selected pin EA 0 The Bus Type field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 Bit BUSACTO in register BUSCONDO is set to 1 Bit ALECTLO in register BUSCONO is set to 1 Bit ROMEN in register SYSCON will be cleared to 0 Bit BYTDIS in register SYSCON is set according to the data bus width When an internal start is selected pin EA 1 Register BUSCONO is cleared to 0000h Bit ROMEN in register SYSCON will be set to 1 Bit BYTDIS in register SYSCON is cleared and BHE is disabled The other bits of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type The Ready function is disabled at the end of the internal system reset 286 340 ky ST10F269 USER S MANUAL SYSTEM RESET When the internal reset has completed the configuration of PORTO PORT1 Port4 Port6 and of the BHE
337. iated counter PTx The shadow register is loaded from the respective PWx register at the beginning of every new PWM cycle or upon a write access to PWx while the timer is stopped When the counter value is greater than or equal to the shadow register value the PWM signal is set otherwise it is reset The output of the comparators may be described by the boolean formula PWM output signal PTx gt PWx shadow latch This type of comparison allows a flexible control of the PWM signal For the register locations refer to the Table 44 Table 44 PWM module channel specific register addresses Register Address Reg Space Register Address Reg Space Pwo SFR PTO FO3Oh 18h ESFR PW1 FE32h 19h SFR PT1 FO32h 19h ESFR PW2 FE34h 1Ah SFR PT2 FO34h 1Ah ESFR PW3 FE36h 1Bh SFR PT3 FO36h 1Bh ESFR PPO Fo38h 1Ch ESFR PP1 FO3Ah 1Dh ESFR PP2 FO3Ch 1Eh ESFR These registers are not bit addressable PP3 FO3Eh 1Fh ESFR PWM Control Register PWMCONO Register PWMCONO controls the function of the timers of the four PWM channels and the channel specific interrupts Having the control bit organized in functional groups allows to start or to stop all the 4 PWM timers simultaneously with one bit field instruction PWMCONO FF30h 98h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PRs il Pes pez Pet Pe Tre Pre er oe re rr RW RW Bit Function PTRx PWM Timer x Run Control bit 0
338. ical operation However when writing byte to word SFRs the complementary byte of the respective SFR is cleared with the write operation 22 8 Identification Registers The ST10F269 have four Identification registers mapped in ESFR space These registers contain A manufacturer identifier A chip identifier with its revision A internal Flash and size identifier Programming voltage description IDMANUF F07Eh 3Fh ESFR Reset Value 0401h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MANUF 0 0 0 0 1 R Bit Function MANUF Manufacturer Identifier 020h STMicroelectronics manufacturer JTAG worldwide normalization IDCHIP F07Ch 3Eh ESFR Reset Value 10DXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDCHIP REVID R Bit Function IDCHIP Device Identifier 10Dh ST10F269 REVID Device Revision Identifier Xh According to revision number ky 315 340 REGISTER SET ST10F269 USER S MANUAL IDMEM F07Ah 3Dh ESFR Reset Value 3040h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEMTYP MEMSIZE R R Bit Function MEMSIZE Internal Memory Size Internal Memory size is 4 x MEMSIZE in Kbyte 040h for ST10F269 256 Kbytes MEMTYP Internal Memory Type 3h for ST10F269 Flash memory IDPROG F078h 3Ch ESFR Reset Value 0040h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R PROGVDD Programming Vpp Voltage Vpp voltage when programming EPROM or FLASH devices is calcu
339. ich selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPR Resources that are used by the interrupting program must eventually be saved and restored the DPPs and the registers of the MUL DIV unit 6 5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The basic interrupt response time for the ST10F269 is 3 instruction cycles see Figure 24 82 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS All instructions in the pipeline including instruction N during which the interrupt request flag is set are completed before entering the service routine The actual execution time for these instructions wait states therefore influences the interrupt response time In the Figure 24 the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline repla
340. ide powerful instructions to perform operations which currently require sequences of instructions and which are frequently used To avoid transfer into and out of temporary registers such as accumulators and carry bit To perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines To avoid complex encoding schemes by placing operands in consistent fields for each instruction Also to avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers To provide most frequently used instructions with one word instruction formats All other instructions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex alignment hardware It also has the benefit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be used by a programmer via the highly functional ST10F269 instruction set Possible operand types are bits bytes and words Specific instruction support the conversion extension of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands 2 2 4 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a larg
341. idth Register 1 0000h PW2 FE34h PWM Module Pulse Width Register 2 0000h Pw3 FE36h PWM Module Pulse Width Register 3 0000h T2 FE40h GPT1 Timer 2 Register 0000h T3 FE42h GPT1 Timer 3 Register 0000h T4 FE44h GPT1 Timer 4 Register 0000h T5 FE46h GPT2 Timer 5 Register 0000h T6 FE48h GPT2 Timer 6 Register 0000h CAPREL FE4Ah GPT2 Capture Reload Register 0000h TO FE50h CAPCOM Timer 0 Register 0000h T1 FE52h CAPCOM Timer 1 Register 0000h TOREL FE54h CAPCOM Timer 0 Reload Register 0000h T1REL FE56h CAPCOM Timer 1 Reload Register 0000h MAL FE5Ch MAC Unit Accumulator Low Word 0000h MAH FE5Eh MAC Unit Accumulator High Word 0000h CC16 FE60h oe CAPCOM Register 16 0000h CC17 FE62h CAPCOM Register 17 0000h CC18 FE64h CAPCOM Register 18 0000h CC19 FE66h 33h CAPCOM Register 19 0000h CC20 FE68h CAPCOM Register 20 0000h CC21 FE6Ah CAPCOM Register 21 0000h CC22 FE6Ch CAPCOM Register 22 0000h CC23 FE6Eh CAPCOM Register 23 0000h CC24 FE70h CAPCOM Register 24 0000h CC25 FE72h CAPCOM Register 25 0000h CC26 FE74h CAPCOM Register 26 0000h ky 309 340 REGISTER SET ST10F269 USER S MANUAL Table 57 Registers ordered by address continued Name Taa Description SE CC27 FE76h z n CAPCOM Register 27 0000h CC28 FE78h CAPCOM Register 28 0000h CC29 FE7Ah CAPCOM Register 29 0000h CC30 FE7Ch 3Eh CAPCOM Register 30 0000h CC31 FE7Eh CAPCOM Register 31 0000h CC FE80h CAPCOM Re
342. ift clock These signals are alternate functions of Port3 pins Synchronous mode is selected with SOM 000b 8 data bits are transmitted or received synchronous to a shift clock generated by the internal Baud rate generator The shift clock is only active as long as data bits are transmitted or received Figure 96 Synchronous mode of serial channel ASCO Reload Register Baud Rate Timer SOM 000b Receive Interrupt Clock Request Transmit Serial Port Control Interrupt Output Request TDX P310 Shift Clock Error Interrupt Request Receive Input Output RXDO Receive Shift Transmit Shift P3 11 Register Register Transmit Receive Buffer Transmit Buffer Register SORBUF Register SOTBUF Internal Bus Synchronous transmission begins within 4 CPU clock cycles after data has been loaded into SOTBUF provided that SOR is set and SOREN 0 half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data bits are transmitted synchronous with the shift clock After the bit time for the 8th data bit both pins TXDO and RXDO will go high the t
343. igh At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CS signals will not be updated for an access to any internal address area for example when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An access to an on chip X Peripheral deactivates all external CS signals Upon accesses to address windows without a selected CS line all selected CS lines are deactivated The chip select signals allow to operate in four different modes which are selected via bit CSWENx and CSRENx in the respective BUSCONx register CSWENx CSRENx Chip Select Mode 0 0 Address Chip Select Default after Reset mode for CS0 0 1 Read Chip Select 1 1 Read Write Chip Select Address chip select signals remain active until an access to another address window An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area No spikes will be generated on the chip select lines Read or write chip select signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read wr
344. ignals are connected to Port2 in order to trigger an external interrupt that wake up the chip when in power down mode 2 All the bit of RTCCON are active high 274 340 ky ST10F269 USER S MANUAL REAL TIME CLOCK 19 1 2 RTCPH 8 RTCPL RTC PRESCALER Registers The 20 bit programmable prescaler divider is loaded with 2 registers The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in RTCPL In order to keep the system clock those registers are not reset They are write protected by bit RTOFF of RTCCON register write operation is allowed if RTOFF is set RTCPL ECO6h XBUS Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCPL RW RTCPH ECO8h XBUS Reset Value Xh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RTCPH RW Figure 149 PRESCALER Register 3 2 1 0 15 14 13 12 11109 8 7 6 5 4 3 2 1 O V V d A RTCPH RTCPL y V 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 20 bit word counter The value stored into RTCPH RTCPL is called RTCP coded on 20 bit The dividing ratio of the prescalar divider is ratio 64 x RTCP 19 1 3 RTCDH amp RTCDL RTC DIVIDER Counters Every basic reference clock the DIVIDER counters are reloaded with the value stored RTCPH and RTCPL registers To get an accurate time measurement it is possible to read the value of the DIVIDER reading the RTCDH RTCDL Those counters are read only After any bit changed in
345. ilar to the Port2 lines description As all other capture inputs the capture input function of pins P7 7 P7 4 can also be used as external interrupt inputs with a sample rate of 8 CPU clock cycles The lower 4 lines of Port7 P7 3 P7 0 supports outputs of the PWM module POUTS POUTO At these pins the value of the respective port output latch is XORed with the value of the PWM output rather than ANDed as the other pins do This allows to use the alternate output value either as it is port latch holds a 0 or invert its level at the pin port latch holds a 1 Note that the PWM outputs must be enabled via the respective PENx bit in PWMCON1 The Table 24 summarizes the alternate functions of Port7 Table 24 Port7 alternate functions Port7 Pin Alternate Function P7 0 POUTO PWM mode channel 0 output P7 1 POUT1 PWM mode channel 1 output P7 2 POUT2 PWM mode channel 2 output P7 3 POUT3 PWM mode channel 3 output P7 4 CC28 I O Capture input compare output channel 28 P7 5 CC29 I O Capture input compare output channel 29 P7 6 CC30 I O Capture input compare output channel 30 P7 7 CC31 I O Capture input compare output channel 31 124 340 ST10F269 USER S MANUAL PARALLEL PORTS Figure 47 Port7 UO and alternate functions General Purpose Input Output Alternate Function The structure of Port7 differ in the way the output latches are connected to the internal bus and to the pin driver see Figure 48 a
346. imers allows to perform very flexible pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers Figure 80 shows an example for the generation of a PWM signal using the alternate reload mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on T3OUT with T3OE 1 P3 3 1 and DP3 3 1 With this method the high and low time of the PWM signal can be varied in a wide range Note The output toggle latch T3OTL is software accessible and may be changed if required to modify the PWM signal However this will NOT trigger the reload of T3 Avoid selecting the same reload trigger event for both auxiliary timers as both reload registers will try to load the core timer at the same time If this happens T2 is disregarded and the contents of T4 is reloaded 170 340 ky ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Figure 80 GPT1 timer reload configuration for PWM generation Reload Register T2 Interrupt sf T2IR Request T2l lt q Input Clock Core Timer T3 Up Down T30E Interrupt Trap P Request A D elt em gt
347. ing edge on T6IN 010 Negative transition falling edge on T6IN 011 Any transition rising or falling edge on T6IN 1XX Reserved Do not use this combination DI 177 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL The maximum input frequency which is allowed in counter mode is fopy 8 To ensure that a transition of the count input signal which is applied to T6IN is correctly recognized its level should be held high or low for at least 4 CPU clock cycles before H changes GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T6 In addition to these 3 counting modes the auxiliary timer can be concatenated with the core timer The auxiliary timer has no output toggle latch and no alternate output function The individual configuration for timer T5 is determined by its bit addressable control register T5CON Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers T5CON FF46h A3h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5SC T5CLR Cl CT3 T5UDE T5UD T5R T5M T RW RW RW RW RW RW RW RW RW Bit Function T5l Timer 5 Input Selection Depends on the Operating Mode see respective sections T5M Timer 5 Mode Con
348. input signal is connected to the input lines of both TO and T7 these timers count the input signal synchronously Thus the two timers can be regarded as one timer whose contents can be compared with 32 capture registers The functions of the CAPCOM timers are controlled via the bit addressable 16 bit control registers TO1CON and T78CON The high byte of TO1CON controls T1 the low byte of TO1CON controls TO the high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for all four timers except for external input DI 217 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL TO1CON FF50h A8h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAR T1M T1I TOR TOM TOI RW RW RW RW RW RW T78CON FF20h 90h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T8R T8M T8l T7R T7M T71 RW RW RW RW RW RW Bit Function Tax Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fopy EN See also table below for examples Counter Mode TxM 1 X00 Overflow Underflow of GPT2 Timer 6 X01 Positive rising edge on pin TxIN 1 X10 Negative falling edge on pin TxIN H X11 Any edge rising and falling on pin TxIN 1 Tx1 3 TxM Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock 1 Counter Mode Input from External Input or T6 TxR Timer Counter x Run Control 0
349. instead of the general purpose l O operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing I O operations via the port latch The direction of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the tables 202 340 ky ST10F269 USER S MANUAL HIGH SPEED SYNCHRONOUS SERIAL INTERFACE Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines In this case it is not always necessary to switch the direction of a port pin The table below summarizes the required values for the different modes and pins Master Mode Slave Mode Pin Function Port Latch Direction Function Port Latch Direction P3 13 SCLK P3 9 MTSR P3 8 MRST Serial Data Input Serial Clock Output P3 13 1 DP3 13 1 P3 13 X DP3 13 0 P3 9 1 DP3 9 1 Serial Data Input P3 9 x DP3 9 0 P3 8 X DP3 8 0 Serial Data Output P3 8 1 DP3 8 1 Serial Clock Input Serial Data Output Note In the table above an x means that the actual value is irr
350. inters are not modified INC 00 the respective channel will always move data from the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware Do not to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the content of bit field COUNT at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes how the COUNT field itself the interrupt requests flag IR and the PEC channel action depend on the previous content of COUNT Previous Modified IR after PEC Action of PEC Channel COUNT COUNT service and Comments FFh FFh Move a byte word Continuous transfer mode COUNT is not modified FEh 02h FDh 01h VK 2 fl Move a byte word and decrement COUNT 01h 00h Sak Move a byte word Leave request flag set which triggers another request 00h 00h 1 No action Activate interrupt service routine rather than PEC channel The PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00h activate the interrupt service routine which is associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced Continuous transfer
351. ion HOLD mode 6 6 External Interrupts Although the ST10F269 has no dedicated interrupt input pins it provides many possibilities to react on external asynchronous events by using a number of I O lines for interrupt input The interrupt function may either be combined with the pin s main function or may be used instead of it if the main pin function is not required Interrupt signals may be connected to CC3110 CCOIO the capture input compare output lines of the CAPCOM units T4IN T2IN the timer input pins CAPIN the capture input of GPT2 For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request ky 85 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL Note In order to use any of the listed pins as external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control reg
352. ion of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 5 P3 13 is still input the read modify write reads pin P3 13 RIGHT BSET DP3 13 change direction of P3 13 to output NOP any instruction not accessing Port3 BSET P3 5 P3 13 is now output the read modify write reads the P3 13 output latch 40 340 kyy ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON like the mapping of the internal memory like segmentation like stack size cannot use the new resources Memory or stack This instruction must not access the new ressources Code accesses to the new Memory area are only possible after an absolute branch to this area As a rule instructions that change Memory mapping must be executed from internal RAM or external memory BUSCON ADDRSEL The I 4 4 instruction following an lp instruction that changes the properties of an external address area cannot access operands within the new area This instruction I 1 must not access this memory area
353. iras iia 140 293 Bliss Mole sanss io tt 136 292 Ghip Select idas 140 293 PEL oieee ee 294 RESET ne aro eee irea e eneas 288 Write Control cccccccnnnnnccononcccnnnonononos 293 Context Switching oooococonnccconnncccnnncinonaccnnanncinn 84 Control Status Register ceeeeeeeees 256 Conversion analog digital cccceeseeseseessteeeteees 244 AULO SCAN eent e td As 247 timing Control 251 Count direction cccccccnnnonnnnnnnnmm mo 163 177 Counter ceceeceeseeeeeees 165 170 179 181 240 L ett al ath Meek tLe tls Mave ee Sie 53 CRU sat cil katie Merete tals a Stake Ar 13 CRI Cie civesueaiesde e ea eae eeii 185 GSP arai is tala aei 51 D Data Page erie ish aa 52 328 boundaries ssiri aris taataa iiaia 36 Delay Read Write occcnnonicocococccncncccnnnnnnccnrnnanoss 146 Demultiplexed BUS 0oooococccnnoccccncconcccccnnnncnncnnos 137 Direction A EE 163 177 Disable A dectiele slit eaten eves 82 329 340 KEY WORD INDEX Segmentation 46 DIVISION ivan irte 57 319 Double Register Compare secsec 229 DROE OO teta caine da 102 DPALY DPA ifinitta areae 105 291 DR atar taa 107 o E 111 DP Act eee ita ae 115 121 DIP beieis EE eeh 122 DPF e RO wen 126 DPS A E E 2s 129 DPP e e Miedo al ee ae ir 52 328 E Edge aligned PWM AAA 235 Emulation Mode cccccccseceseeeeeesessesseseeeeees 292 Enable INTO FUE A itt en ietteeesci is 82 Segmentation 46 E
354. irects accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction 326 340 ky ST10F269 USER S MANUAL SYSTEM PROGRAMMING Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal extension counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows the construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence 23 10 Handling the Internal Flash The ST10F269 provides and controls a 256 Kbytes internal on chip Flash memory that may store code as well as data Access to this internal Flash area is controlled during the reset configuration and via software The Flash area may be mapped to segment 0 to segment 1 or may be disabled at all Note The Flash
355. is option is controlled by bit T5CLR in register T5CON If T5CLR 0 the contents of timer T5 are not affected by a capture If T5CLR 1 timer T5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls whether a capture is performed or not If T5SC 0 the input pin CAPIN can still be used to clear timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt control register CRIC see Figure 89 Figure 88 Concatenation of core timer T6 and auxiliary timer T5 T6l T T6R Interrupt gt Request gt T6OUT MY P3 1 Core Timer T6 Up Down 1 SC T6OE Select Interrupt Request Note 1 Line only affected by over underflows of T6 but NOT by software modifications of T6OTL 180 340 OI ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Figure 89 GPT2 register CAPREL in capture mode Up Down Auxiliary Timer T5 Interrupt Request Edge Select CAPIN P3 2 MY T3IN V N T3EUD P3 4 Cl ee Interrupt CRIR Request CAPREL Register GPT2 Capture Reload Register CAPREL in Reload Mode This 16 bit register can be used as a reload register for the core timer T6 This mode is selected by setting bit TOSR 1 in register TO6CON The event causing a reload in this mode is an overflow or underflow of the core timer T6 When timer T6 overflows from FFFFh to 0000h
356. ison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry anyhow 46 340 AT ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU For shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bit V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are representable by either 16 bit for word operations 8000h to 7FFFh or by 8 bit for byte operations 80h to 7Fh otherwise the V flag is cleared The result of an integer addition
357. ister 0000h ODP4 b FiCAh E E5h Port4 Open Drain Control Register 00h ODP6 b FiCEh E E7h Port6 Open Drain Control Register 00h ODP7 b FiD2h E E9h Port7 Open Drain Control Register 00h ODP8 b F1D6h E EBh Port8 Open Drain Control Register 00h EXISEL b FiDAh E EDh External Interrupt Source Selection Register 0000h DPPO FEOOh 00h CPU Data Page Pointer O Register 10 bit 0000h DPP1 FEO2h CPU Data Page Pointer 1 Register 10 bit 0001h 308 340 ky ST10F269 USER S MANUAL REGISTER SET Table 57 Registers ordered by address continued Name Paa Description SE DPP2 FE04h 02h CPU Data Page Pointer 2 Register 10 bit 0002h DPP3 FEo6h 03h CPUData Page Pointer 3 Register 10 bit 0003h CSP Feosh 04h CPU Code Segment Pointer Register read only 0000h MDH FEOCh EC CPU Multiply Divide Register High word 0000h MDL FEOEh CPU Multiply Divide Register Low word 0000h CP FE10h CPU Context Pointer Register FCOOh SP FE12h CPU System Stack Pointer Register FCOOh STKOV FE14h CPU Stack Overflow Pointer Register FAOOh STKUN FE16h CPU Stack Underflow Pointer Register FCOOh ADDRSEL1 FE18h Address Select Register 1 0000h ADDRSEL2 FE1Ah op ___ Address Select Register 2 0000h ADDRSEL3 FE1Ch Address Select Register 3 0000h ADDRSEL4 FE1Eh Address Select Register 4 0000h Pwo FE30h PWM Module Pulse Width Register 0 0000h PW1 FE32h PWM Module Pulse W
358. ister 2 coms CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h SS CCM7 b 94h CAPCOM Mode Control Register 7 CP 08h CPU Context Pointer Register CRIC b B5h GPT2 CAPREL Interrupt Control Register Ce DPOL b F100h E 80h POL Direction Control Register 00h DPOH b F102h E POh Direction Control Register 00h DP1H b 83h P1h Direction Control Register DP2 b Eth Port 2 Direction Control Register DP3 b Port 3 Direction Control Register DP4 b Port 4 Direction Control Register DP6 b Port 6 Direction Control Register DP7 b Port 7 Direction Control Register DPP2 FE04h 02h CPU Data Page Pointer 2 Register 10 bit 0002h DPPO FEOOh CPU Data Page Pointer 0 Register 10 bit 0000h DPP1 CPU Data Page Pointer 1 Register 10 bit E3h E5h E7h E9h EBh 00h 02h DPP3 03h CPU Data Page Pointer 3 Register 10 bit EXICON b E E0h External Interrupt Control Register EXISEL b E EDh External Interrupt Source Selection Register iDGHIP Forch E IDMANUF FO7Eh E 3Fh Manufacturer Identifier Register 0401h IDMEM FO7Ah E On chip Memory Identifier Register 3040h IDPROG Programming Voltage Identifier Register IDXO b 84h MAC Unit Address Pointer 0 IDX1 b 85h MAC Unit Address Pointer 1 MAH 2Fh MAC Unit Accumulator High Word MAL 2Eh MAC Unit Accumulator Low Word MCW EEh MAC Unit Control Word MDC b 87h CPU Multiply Divide Control Register MDH CPU Multiply Divide Register High Word MDL FEOEh 07h CP
359. ister DPx see Table 16 When port pins CCxl O are used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 001b the interrupt request flag CCxIR in register CCxIC will be set on a positive external transition at pin CCxI O When CCMODx is programmed to 010b a negative external transition will set the interrupt request flag When CCMODx 011b both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent whether the timer is running or not When the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated see Table 16 Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or T4CON to 101b Table 16 Pins to be used as external interrupt inputs Port Pin Original Function Control Register P2 0 15 CC0 151 0 CAPCOM Register 0 15 Capture Input CC0 CC15 P8 0 7 CC16 231 0 CAPCOM Register 16 23 Capture Input CC16 CC23 P1H 4 7 CC24 271 0 CAPCOM Register 24 27 Capture Input CC24 CC27 P7 4 7 CC28 311 0 CAPCOM Register 28 31 Capture Input CC28 CC31 P3
360. ister can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately fol low an instruction updating the SP register SP FE12h 09h SFR Reset Value FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E ENEE R R R 4 R RW R Bit Function SP Modifiable portion of register SP Specifies the top of the internal system stack ky 53 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL 4 4 9 The Stack Overflow Pointer STKOV This non bit addressable register is compared against the SP register after each operation which pushes data onto the system stack PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 and bit 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from FOOOh to FFFEh STKOV FE14h 0Ah SFR Reset Value FAOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 STKOV 0 R R R R RW R Bit Function STKOV Modifiable portion of register STKOV Specifies the lower limit of the internal system stack The Stack Overflow Trap entered when SP lt STKOV may be used in two different ways Fatal error indication treat
361. ists the defined POCON registers and the allocation of control bit fields and port pins Table 18 Port control register allocation Control Physical 8 bit Controlled Port Nibble Register Address Address 3 2 4 0 POCONOL FO80h 40h POL 7 4 POL 3 0 POCONOH FO82h 4th POH 7 4 POH 3 0 POCONIL F084h 42h P1L 7 4 P1L 3 0 POCON1H FO86h 43h P1H 7 4 P1H 3 0 POCON2 FO88h 44h P2 15 12 P2 11 8 P2 7 4 P2 3 0 POCON3 FO8Ah 45h P3 15 3 13 3 12 P3 11 8 P3 7 4 P3 3 0 POCON4 FO8Ch 46h P4 7 4 P4 3 0 POCON6 FO8Eh 47h P6 7 4 P6 3 0 POCON7 FO90h 48h P7 7 4 P7 3 0 POCON8 FO92h 49h P8 7 4 P8 3 0 Dedicated Pins Output Control Programmable pad drivers also are supported for the dedicated pins ALE RD and WR For these pads a special POCONZ20 register is provided 98 340 ky ST10F269 USER S MANUAL PARALLEL PORTS POCON20 FOAAh 55h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PN1DC PN1EC PNODC PNOEC RW RW RW RW PNOEC RD WR Edge Characteristic rise fall time 00 Fast edge mode rise fall times depend on the size of the driver 01 Slow edge mode rise fall times 60 ns 10 Reserved 11 Reserved PNODC RD WR Driver Characteristic output current 00 High Current mode Driver always operates with maximum strength 01 Dynamic Current mode Driver strength is reduced after the target level has been rea
362. it registers located on word addresses However all registers may be accessed byte wise in order to select special actions without effecting other mechanisms Note The address map shown in Figure 135 lists the registers which are part of the CAN controller There are also ST10F269 specific registers that are associated with the CAN Modules These registers however control the access to the CAN Modules rather than their function Visibility of XBUS Peripherals In order to keep the ST10F269 compatible with the ST10C167 and with the ST10F167 the XBUS peripherals can be selected to be visible and or accessible on the external address data bus CAN1EN and CAN2EN bit of XPERCON register must be set If these bit are cleared before the global enabling with XPEN bit in SYSCON register the corresponding address space port pins and interrupts are not occupied by the peripheral thus the peripheral is not visible and not available Refer to Chapter 22 Register Set 252 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES XPERCON F024h 12h ESFR Reset Value 05h 15 12 11 14 13 10 9 8 7 6 5 4 3 2 1 0 EE ES MES RW RW RW RW RW CAN1EN CAN1 Enable Bit 0 Accesses to the on chip CAN1 XPeripheral and its functions are disabled P4 5 and P4 6 pins can be used as general purpose I Os Address range 00 EFOOh 00 EFFFh is only directed to external memory if CANZ2EN is also 0 1 The on chip CAN1 XPeripheral is enable
363. ite chip select is activated for both read and write cycles write cycles are assumed if any of the signals WRH or WRL becomes active These modes save external glue logic when accessing external devices like latches or drivers that only provide a single enable input Note CSO provides an address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pull up devices hold all CS lines high during reset After the end of a reset sequence the pull up devices are switched off and the pin drivers control the pin levels on the selected CS lines Not selected CS lines will enter the high impedance state and are available for general purpose I O The pull up devices are also active during bus hold on the selected CS lines while HLDA is active and the respective pin is switched to push pull mode Open drain outputs will float during bus hold In this case external pull up devices are required or the new bus master is responsible for driving appropriate levels on the CS lines 9 2 8 Segment Address Versus Chip Select The external bus interface supports many configurations for the external memory By increasing the number of segment address lines a linear address space of 256 Kbytes 1 Mbyte or 16 Mbytes can be addressed It is possible to implement a large memory area and to access a great number of external devices using an external decoder By increasing the number of CS line accesses
364. ivide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task for example when a scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task that is switched to BCD Calculations No direct support for BCD calculations is provided in the ST10F269 BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10d Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types while no additional hardware is required 23 1 Stack Operations The ST10F269 supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is provided to store return vectors segment point
365. ization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 TSEG2 Time Segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 Note This register can only be written if the configuration change enable bit CCE is set Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines whether the standard 11 bit mask in Global Mask Short or the 29 bit extended mask in Global Mask Long is to be used Bit holding a 0 mean don t care so do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message Global Mask Short EF06h EE06h XReg Reset Value UFUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1D20 18 1 1 1 1 1 1D28 21 RW R R R R R RW Bit Function 1D28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier Upper Global Mask Long EF08h EE08h XReg Reset Value V
366. jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not effect the respective bit location All instructions that change single bit or bit groups internally use a read modify write sequence that accesses the whole word containing the specified bit s This method has several consequences Bit can only be modified within the internal specific address areas IRAM SFRs External locations cannot be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the internal RAM are bit addressable see Chapter 3 Memory Organization Those register bits located within the respective sections can be directly manipulated using bit instructions The other SFRs must be accessed byte or word wise Note All GPRs are bit addressable independently of the allocation of the register bank via the context pointer CP Even GPRs which are allocated in not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bit In these cases the hardware may change specific bit while the read modify write operation is in progress where the writeback would overwrite the new bit value generated by the hardware The solution is either the implemented hardware protection see below or realized through special programming see Section 4 1 4 Particular Pipeline Effects SZA 41 340 THE CENT
367. l 16 port lines can be used for general purpose I O The upper four pins of PORT1 P1H 7 P1H 4 also are capture input lines for the CAPCOM2 unit CC27 24 I O As all other capture inputs the capture input function of pins P1H 7 P1H 4 can also be used as external interrupt inputs with a sample rate of 8 CPU clock cycles As a side effect the capture input capability of these lines can also be used in the address bus mode Hereby changes of the upper address lines could be detected and trigger an interrupt request in order to perform some special service routines External capture signals can only be applied if no address output is selected for PORT1 During external accesses in de multiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a de multiplexed bus mode PORT1 is not used and is available for general purpose I O Figure 31 PORT1 I O and alternate functions Alternate Functions a b PINT A15 cc2710 EE A14 CC2610 Ea A13 CC2510 P1H 4 P1H P1H 3 SC SE P1H 2 Aio P1H 1 AO P1H 0 a PORT P4L 7 pa P4L 6 Ke P4L 5 KE P1L 4 EES P1L P1L 3 A3 P1L 2 Fe PIA e P1L 0 ae General Purpose 8 16 bit CAPCOM2 Input Output De multiplexed Bus Capture Inputs ky 103 340 PARALLEL PORTS ST10F269 USER S MANUAL When an external bus mode is enabled the direction of the port pin and the loading
368. l Event Controller makes it possible to respond to an interrupt request with a single data transfer word or byte which only consumes one instruction cycle and does not require a save and restore of the machine status Each interrupt source is prioritized in every instruction cycle in the interrupt control block If a PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bit for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similarly to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to move register contents to from a memory table The ST10F269 has 8 PEC channels each of which offers
369. l Register SSCTB SSC Transmit Buffer Register write only SSCRB SSC Receive Buffer Register read only SSCTIC SSC Transmit Interrupt Control Register SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 195 340 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL Figure 99 Synchronous serial channel SSC block diagram Slave Clock CPU Clock Baud Rate Generator Clock Control SCLK P3 13 Master Clock Receive Interrupt Request SSC Control i t R t Transmit Interrupt Reques Block Error Interrupt Request Status Control N MTSR A P3 9 C MRST A P3 8 Pin Control 16 bit Shift Register Transmit Buffer Receive Buffer Register SSCTB Register SSCRB The operating mode of the serial channel SSC is controlled by its bit addressable control register SSCCON This register serves for two purposes During programming SSC disabled by SSCEN 0 it provides access to a set of control bit During operation SSC enabled by SSCEN 1 it provides access to a set of status flags Register SSCCON is shown below in each of the two modes Internal Bus SSCRB F0B2h 59h ESFR Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW SSCTB FOBOh 58h ESFR Reset Value 0000h
370. l reset features the schematic or equivalent of Figure 156 must be implemented R1 C1 only work for power on or manual reset in the same way as explained previously D1 diode brings a faster discharge of C1 capacitor at power off during repetitive switch on switch off sequences D2 diode performs an OR wired connection it can be replaced with an open drain buffer R2 resistor may be added to increase the pull up current to the open drain in order to get a faster rise time on RSTIN pin when bidirectional function is activated The start up configurations and some system features are selected on reset sequences as described in Table 50 and Table 51 Table 50 describes what is the system configuration latched on PORTO in the five different reset ways Table 51 summarizes the bit state of PORTO latched in RPOH SYSCON BUSCONO registers ky 283 340 SYSTEM RESET ST10F269 USER S MANUAL Figure 154 Internal simplified reset circuitry EINIT Instruction Cir RSTOUT Set Reset State Machine Clock Voc SRST instruction watchdog overflow TS RSTIN BDRSTEN Reset Sequence 512 CPU Clock Cycles Asynchronous Reset Internal Reset Signal Trigger Cir RPD From to Exit Weak pull down Powerdown 2001A Circuit Figure 155 Minimum external reset circuitry RSTOUT External EE Hardware RSTIN R ST10F269 C1 lt
371. lag and the carry flag are then used to round the floating point result based on the desired rounding algorithm 23 7 Trap Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred 23 8 Inseparable Instruction Sequences The instructions of the ST10F269 are very efficient most instructions execute in one instruction cycle and even the multiplication and division are interruptible in order to minimize the response latency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences like semaphore handling to be non interruptible to function properly This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC inst
372. lated using the following formula Vpp 20 x PROGVDD 256 volts 40h for ST10F269 5V PROGVPP Programming Vpp Voltage no need of external Vpp 00h Note 1 All identification words are read only registers 316 340 ky ST10F269 USER S MANUAL SYSTEM PROGRAMMING 23 SYSTEM PROGRAMMING Constructs for modularity loops and context switching have been built into the ST10F269 instruction set Many commonly used instruction sequences have been simplified The following programming features are available to the programmer Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the ST10F269 This provides the same functionality while decreasing the hardware requirement and decreasing decode complexity These instructions can be built in macros to aid assembly programming Directly substitutable instructions are known instructions from other microcontrollers that can be replaced by the following instructions of the ST10F269 Substituted Instruction ST10F269 Instruction Function CLR Rn AND Rn 0h Clear register CPLB Bit BMOVN Bit Bit Complement bit DEC Rn SUB Rn 1h Decrement register INC Rn ADD Rn 1h Increment register SWAPB Rn ROR Rn 8h Swap byte within word Modification of system flags is performed by using bit set or bit clear instructions BSET BCLR All bit and word instru
373. le register reflects the current state of the microcontroller Two groups of bit represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag PSW FF10h 88h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN HLD USRO MUL E Z V c N EN IP RW RW RW RW RW RW RW RW RW RW N Negative Result Set when the result of an ALU operation is negative C Carry Flag Set when the result of an ALU operation produces a carry bit V Overflow Result Set when the result of an ALU operation produces an overflow Z Zero Flag Set when the result of an ALU operation is zero E End of Table Flag Set when the source operand of an instruction is 8000h or 80h MULIP Multiplication Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted USRO User General Purpose Flag May be used by the application software HLDEN Interrupt and EBC Control Fields ILVL IEN Define the response to interrupt requests and enable external bus Arbitration Described in Chapter 6 Interrupt and Trap Functions ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data
374. lects the effective transition of the external interrupt input signal When Cl is programmed to 01b a positive external transition will set the interrupt request flag Cl 10b selects a negative transition to set the interrupt request flag and with Cl 11b both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an interrupt request for vector CRINT or a PEC request will be generated Note The non maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an external input signal NMI and RSTIN are dedicated input pins which cause hardware traps 86 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS 6 6 1 Fast External Interrupts The input pins that may be used for external interrupts are sampled every 8 CPU clock cycles this means that the external events are scanned and detected in timeframes of 8 CPU clock cycles The ST10F269 provides 8 interrupt inputs that are sampled every CPU clock cycle so external events are captured faster than with standard interrupt inputs The upper 8 pins of Port2 CC8 15 I O on P2 8 P2 15 can individually be programmed to this fast interrupt mode In this mode the trigger transition rising falling or both can also be selected The External Interrupt Control register EXICON controls this feature for all 8 pins In addition these fast interrupt inputs feature programmable edge detecti
375. led the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases 4 4 7 The Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 word wide and or byte wide GPRs CP FE10h 08h SFR Reset Value FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALEA EN A E R R R R RW R Bit Function CP Modifiable portion of register CP Specifies the word base address of the current register bank When writing a value to register CP with bit CP 11 CP 9 000 bit CP 11 CP 10 are set to 11 by hardware in all other cases all bit of bit field cp receive the written value It is the user s responsibility to ensure that the physical GPR address specified via the CP register plus the short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur Do not set CP below the IRAM start address 00 F600h 2 Kbytes Do not set CP above 00 FDFEh Be careful using the upper GPRs with CP above 00 FDEOh The CP register can be updated via any instruction which is capable of modifying an SFR ky 51 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL Note Due to the internal instruction pipeline a new CP v
376. ler will enter the NMI trap routine this routine can save the internal state into the RAM After the internal state has been saved the trap routine may set a flag or write a certain bit pattern into specific RAM locations and then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered otherwise program execution continues Exiting power down mode can only be achieved by external hardware reset The initialization routine executed upon reset checks the identification flag or bit pattern within the RAM to determine whether the controller was initially switched on or whether it was properly restarted from power down mode 21 3 Interruptible Power Down Mode This mode is selected by setting the bit PWDCFG in register SYSCON to 1 Entering power down mode can only be achieved if enabled Fast External Interrupt pins 0 to 3 EXxIN pins alternate functions of Port2 pins with x 7 0 are in their inactive level This inactive level is configured with the EXIxES bit field in the EXICON register as follows 294 340 ky ST10F269 USER S MANUAL POWER REDUCTION MODES EXICON F1C0h E0h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXIOES RW RW RW RW RW RW RW RW Bit Function EXIxES External Interrupt x Edge Selection Field x 7 0 x 7 0
377. liary timers T2 and T4 are programmed to timer mode or gated timer mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T2 and T4 ky 167 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXxCON to 001b In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN or by a transition of timer T3 s output toggle latch T3OTL see Figure 77 The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TxCON selects the triggering transition see Table 33 Note Only transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 For counter operation pin TxIN must be configured as input the respective direction control bit must be 0 The maximum input frequency which is allowed in counter mode is fcpy 8 To ensure that a transition of the count input signal w
378. lize the controller before the external circuitry is activated XTAL1 XTAL2 Oscillator Input Output connect the internal clock oscillator to the external crystal An external clock signal may be fed to the input XTAL1 leaving XTAL2 open Vpp Vss Digital Power Supply and Ground 6 pins each provides the power supply for the digital logic of the ST10F269 All Vpp pins and all Vgg pins must be connected to the power supply and ground respectively RPD Exit from powerdown If a Fast External Interrupt pin EX3IN EXOIN is used to exit from Power Down mode an external RC circuit should be connected to the RPD pin The discharging of the external capacitor causes a delay that allows the oscillator and PLL circuits to stabilize before the clock signal is delivered to the CPU and peripherals see Figure 52 For more information on exiting power down mode refer to Chapter 21 DC1 3 3V Decoupling pin a decoupling capacitor of gt 330 nF must be connected between this pin and DC2 nearest Vgg pin 130 340 OI ST10F269 USER S MANUAL DEDICATED PINS Figure 52 RPD external RC circuit 200KQ 1MQ typical 1uF typical RPD external RC circuit is used for exiting power down mode with external interrupt and for power up asynchronous reset ky 131 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL 9 THE EXTERNAL BUS INTERFACE The on chip peripherals and on chip RAM and Flash Memory only cover a small fraction of
379. ll be affected by reset ky 259 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL The Table 48 shows how to use and to interpret these 2 bit fields Figure 137 Message object address map Object Start Address 4 Message Control 0 2 Arbitration 4 Data0 Message Config 6 Data2 Data1 8 Data 10 12 Reserved 14 Table 48 Functions of complementary bits of message control register Value Function on Write Meaning on Read 00 Reserved Reserved 01 Reset element Element is reset 10 Set element Element is set 11 Leave element unchanged Reserved Message Control Register EFn0h EEn0h XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND CPUUPD RW RW RW RW RW RW RW RW INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if bit INTPND is set after successful transmission of a frame 1 MSGVAL Message Valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates if new data has been written
380. low STKOV and the stack underflow STKUN registers should be initialized After reset the CP SP and STKUN registers all contain the same reset value 00 FCOOh while the STKOV register contains 00 FAOOh With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFEh while the register bank selected by the CP grows upwards from 00 FCOOh Based on the application the user may wish to initialize portions of the internal memory before normal program operation Once the register bank has been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing At the end of the initialization the interrupt system may be globally enabled by setting bit IEN in register PSW Care must be taken not to enable the interrupt system before the initialization is complete The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Execution of the EINIT instruction disables the action of the DISWDT instruction disables write accesses to register SYSCON see note and causes the RSTOUT pin to go high This signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware Note All configurations regarding register SYSCON enable CLKOUT s
381. ls forward jitter backward jitter forward Contents of T3 Note This example shows the timer behavior assuming that T3 counts upon any transition on any input T3l 011b Figure 76 Evaluation of the incremental encoder signals forward jitter backward jitter forward Contents of T3 l l Note This example shows the timer behavior assuming that T3 counts upon any transition on T3IN input T3I 001b Note Timer 3 operating in incremental interface mode automatically provides information on the sen sor s current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods This is facilitated by an additional special capture mode for timer T5 166 340 OI ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS 10 1 2 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured like timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 3 counting modes the auxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The auxiliary timers have no output toggle latch and no alternate output function The individual configuration for timers T2 and T4 is determined by their bit address
382. lue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function ODP6 y Port6 Open Drain control register bit y ODP6 y 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode 7 8 1 Alternate Functions of Port6 A programmable number of chip select signals CS4 CSO derived from the bus control registers BUSCON4 BUSCONO can be output on 5 pins of Port6 The other 3 pins may be used for bus arbitra tion to accommodate additional masters in a ST10F269 system The number of chip select signals is selected via PORTO during reset The selected value can be read from bit field CSSEL in register RPOH read only in order to check the configuration during run time The Table 23 summarizes the alternate functions of Port6 depending on the number of selected chip select lines coded via bit field CSSEL Table 23 Port6 alternate functions Alternate Function CSSEL 10 General purpose I O Alternate Function Alternate Function Alternate Function Port6 Pin CSSEL 01 CSSEL 00 CSSEL 11 Chip select CSO Chip select Chip select P6 1 General purpose I O Chip select CS1 Chip select CS1 Chip select CS1 P6 2 General purpose UO General purpose UO Chip select CS2 Chip select CS2 P6 3 General purpose I O General purpose I O General purpose I O Chip select CS3 P6 4 General purpose I O General purpose I O General
383. ly in message objects with XTD 1 standard frames only in message objects with XTD 0 For matching the corresponding global mask has to be considered in case of message object 15 also the Mask of Last Message If a received message data frame or remote frame matches with more than one valid message object it is stored into that with the lowest message number When the CAN controller stores a data frame not only the data byte but the whole identifier and the data length code are stored into the corresponding message object standard identifiers have bit 1D17 O filled with 0 This is implemented to keep the data byte connected with the identifier even if arbitration mask registers are used When the CAN controller stores a remote frame only the data length code is stored into the corresponding message object The identifier and the data byte remain unchanged There must not be more than one valid message object with a particular identifier at any time If bit are masked by the Global Mask Registers don t care then the identifiers of the valid message objects must differ in the remaining bit which are used for acceptance filtering If a received data frame is stored into a message object the identifier of this message object is updated If some of the identifier bit are set to don t care by the corresponding mask register these bit may be changed in the message object If a remote frame is received the ide
384. ly or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 by 16 bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds the divisor JMPR cc_V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU a 318 340 ST10F269 USER S MANUAL SYSTEM PROGRAMMING Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the multiply d
385. ment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modified by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap 6 7 2 Hardware Traps Hardware traps are issued by faults or specific system states that occur during the runtime of a program not identified at assembly time A hardware trap may also be triggered intentionally for example to emulate additional instructions by generating an Illegal Opcode trap The ST10F269 distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have priority over every other CPU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see
386. n There is no output toggle latch and no alternate output pin for T5 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to 001b In counter mode timer T5 can be clocked either by a transition at the external input pin T5IN or by a transition of timer T6 s output toggle latch T6OTL The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the input pin or at the toggle latch T6OTL see Figure 87 Bit field T5l in control register T5CON selects the triggering transition see Table 37 Note Only state transitions of T6OTL which are caused by the overflows underflows of T6 will trigger the counter function of T5 Modifications of T6OTL via software will NOT trigger the counter function of T5 The maximum input frequency allowed in counter mode is fcpy 4 To ensure that a transition of the count input signal which is applied to T5IN is correctly recognized its level should be held high or low for at least 4 CPU clock cycles before it changes Figure 87 Block diagram of auxiliary timer T5 in counter mode E A Interrupt Auxiliary Timer T5 TSIR Request Up Down T5EUD V YN XOR P5 11 NY Table 37 GPT2 auxiliary timer counter mode input edge selection T Triggering Edge for Counter Increment Decrement X00 None Counter T5 is disabled
387. n Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals like XRAM or CAN module and external memory are mapped into one common address space The ST10F269 provides a total addressable memory space of 16 Mbytes This address space is arranged as 256 segments of 64 Kbytes each and each segment is again subdivided into four data pages of 16 Kbytes each see Figure 4 Most of the internal memory areas are mapped into segment 0 named system segment The upper 4 Kbytes of segment 0 00 F000h 00 FFFFh hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32 Kbytes of segment 0 00 0000h 00 7FFFh can be occupied by a part of the on chip Flash Memory and is called the internal memory area This Flash area can be remapped to segment 1 01 0000h 01 7FFFh to enable external memory access in the lower half of segment 0 or the internal ROM may be disabled Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Figure 4 Memory areas and address space l RAM SFR and X pheripherals are ez Block4 64 Kbytes o 02 0000 00 FIFF L _105 0000 l mapped into the address space T 00 FFFF E E Block6 64 Kbytes SFR 512 bytes d 10 04 0000 00 FE00 E 00 FDFF o 5 F Block5 64 Kbytes IRAM 2 Kbytes DC 03 0000 00 F600 N E o E E
388. n TXIN Reload A reload of a timer with the 16 bit value stored in its associated reload register in both modes is performed each time a timer would overflow from FFFFh to 0000h In this case the timer does not wrap around to 0000h but rather is reloaded with the contents of the respective reload register TXREL The timer then resumes incrementing starting from the reloaded value The reload registers TxREL are not bit addressable ky 219 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL 15 2 CAPCOM Unit Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the respective interrupt enable bit TxIE Each timer has its own bit addressable interrupt control register TxIC and its own interrupt vector TxINT The organization of the interrupt control registers TxIC is identical with the other interrupt control registers TOIC FF9Ch CEh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 TOIR TOIE ILVL GLVL RW RW RW RW T11C FF9Eh CFh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIR TIE ILVL GLVL RW RW RW RW T7IC F17Ah BEh ESFR Reset Value 00h 15 12 11 5 4 3 2 1 0 14 13 10 9 8 7 6 CT OS O O e ee o a RW RW RW RW T8IC F17Ch BFh
389. n bit is disregarded After reset the clock output function is disabled CLKEN 0 Segmentation Disable enable Control SGTDIS Bit SGTDIS allows to select either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64 Kbytes segment 0 and thus 16 bit are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the whole address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt ser vice routine is left again System Stack Size STKSZ This bit field defines the size of the physical system stack which is located in the internal RAM of the ST10F269 An area of 32 1024 words or all of the internal RAM may be dedicated to the system stack A so called circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of bit field STKSZ are described in
390. n the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated which uses the interrupt request flag ADEIR for this reason the Wait for ADDAT Read Mode is required Figure 132 Channel injection example Conversion X x 1 x 2 y y Write ADDAT x 1 x xt ADDAT Full 77 7 1777 Read ADDAT x 1 tx x 1 Channel Injection gt Injected Conversion Request by CC31 of Channel y ADDAT2 Full TTT Interrupt Request ADEINT Read ADDAT2 e Write ADDAT2 d x 3 247 340 ANALOG DIGITAL CONVERTER ST10F269 USER S MANUAL If the temporary data register used in Wait for ADDAT Read Mode is full the respective next conversion standard or injected will be suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion Figure 133 Channel injection example with wait for read Conversion X x 1 x 2 x 3 of Channel Wait until d y d SE is y Write ADDAT x 1 x x 1 x 2 Hx 3 ADDAT Full Read ADDAT x 1 Hx xX 2 Hx 3 Injected Conversion Channel Injection gt of Channel y Request by CC31 Write ADDAT2 Z y ADDAT2 Full Interrupt 5 Request ADEINT Read ADDAT2 Temp Latch Full Conversion X x 1 x 2 x 3 Ho of Chamnel y Y Write ADDAT x 1 Hx x 1 x 2 X 3
391. n this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal So T3 is modified automatically according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder s current position The incremental encoder can be connected directly to the MCU without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs as A and A to digital signals as A digital signals this greatly increases noise immunity The third encoder output TO TO which indicates the mechanical zero position may be connected to an external interrupt input and trigger a reset timer T3 for example via PEC transfer from ZEROS see Figure 74 Figure 73 Core timer T3 in incremental interface mode T3R ray Ta T3IR gt FN T3OUT T3OTL Ve T30E T3IN P3 6 T3EUD P3 4 phase detect T3UD Table 32 GPT1 core timer T3 incremental interface mode input edge selection T Triggering Edge for Counter Increment Decrement 000 None Counter stops 001 Any transition rising or falling edge on T3IN 010 Any transition rising or falling edge on T3EUD 011 Any transition rising or falling edge on T3 input T3IN or T3EUD 1XX Reserved Do not use this combination 164 340 51 ST10F269 USER S MANUA
392. nating condition can then be tested ky 13 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL 3 The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range This is particularly powerful in table searching Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages 2 2 3 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipeline design an instruction set has been designed using concepts of Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set To prov
393. nd 1 2 11 This format is supported when MP of MOW is set The MAC implements two s complement rounding With this rounding type one is added to the bit to the right of the rounding point bit 15 of MAL before truncation MAL is cleared DI 65 340 MULTIPLY ACCUMULATE UNIT MAC ST10F269 USER S MANUAL 5 3 MAC Register Set 5 3 1 Address Registers The new addressing modes require new E SFRs 2 address pointers IDXO IDX1 and 4 offset registers QXO QX1 and QRO QR1 IDXO FFO08h 84h SFR Reset Value 0000h IDX1 FFOAh 85h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDXy RW Bit Function IDXy 16 bit IDXy address QXO0 F000h 00h ESFR Reset Value 0000h QX1 F002h 01h ESFR Reset Value 0000h QRO F004h 02h ESFR Reset Value 0000h QR1 F006h 03h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QXz QRz 0 RW R Bit Function QRz QXz 16 bit address offset for IDXy pointers QXz or GPR pointers QRz As MAC instructions handle word operands bit O of these offset registers is hardwired to O 5 3 2 Accumulator amp Control Registers The MAC unit SFRs include the 40 bit Accumulator MAL MAH and the low byte of MSW and 3 control registers the status word MSW the control word MCW and the repeat word MRW MAH and MAL are located in the non bit addressable SFR space MAH FE5Eh 2Fh SFR Reset Value 0000h 15 14 13 12 11 1
394. nd Figure 49 Pins P7 3 P7 0 POUT3 POUTO XOR the alternate data output with the port latch output which allows to use the alternate data directly or inverted at the pin driver Figure 48 Block diagram of Port7 pins P7 3 P7 0 Write ODP7 y Open Drain Latch Read ODP7 y Write DP7 y Direction Latch Read DP7 y Internal Bus Alternate Write P7 y Port Output Output S d Cuil A P7 y POUTy Latch Buffer Read P7 y ky 125 340 PARALLEL PORTS ST10F269 USER S MANUAL Pins P7 7 P7 4 CC3110 CC2810 combine internal bus data and alternate data output before the port latch input as do the Port2 pins Figure 49 Block diagram of Port7 pins P7 7 P7 4 Write ODP7 y Open Drain Latch Read ODP7 y Write DP7 y Direction Latch Read DP7 y Internal Bus SZ v gt V N P7y Alternate Output N A CCzlO Data Buffer Output Write Port P7 y Compare Trigger Read P7 y Clock 1 Ge Input ae oe 0 z 28 31 Alternate Latch Data Input lt Alternate Pin Data Input 7 10 Port8 If this 8 bit port is used for general purpose UO the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 126 340 ky ST10F269 USER S MANUAL PARALLEL PORTS
395. ng bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 Keep DP3 12 0 in this case to ensure floating in hold mode 9 6 3 Exiting the Hold State The external bus master returns the access rights to the ST10F269 by driving the HOLD input high After synchronizing this signal the ST10F269 will drive the HLDA output high actively drive the control signals and resume executing external bus cycles if required Depending on the arbitration logic the external bus can be returned to the ST10F269 under two circumstances The external master does no more require access to the shared resources and gives up its own access rights The ST10F269 needs access to the shared resources and demands this by activating its BREQ output The arbitration logic may then deactivate the other master s HLDA and so free the external bus for the ST10F269 depending on the priority of the different masters Note The Hold State is not terminated by clearing bit HLDEN ky 155 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL Figure 67 External bus arbitration regaining the bus Other Note The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry Please note that HOLD may also be deactivat
396. nitialization and Reset The on chip CAN Module is connected to the XBUS Reset signal XRESET This signal is activated when the ST10F269 s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN Module s reset line triggers a hardware reset This hardware reset Sets the CAN_TXD output to 1 recessive Clears the error counters Resets the busoff state Switches the Control Register s low byte to 01h Leaves the Control Register s high byte and the Interrupt Register undefined Does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state The value 01h in the Control Register s low byte prepares for software initialization Software Initialization The Software Initialization is enabled by setting bit INIT in the Control Register This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set All message transfer from and to the CAN bus is stopped The CAN bus output CAN_TXD is 1 recessive The control bit NEWDAT and RMTPND of the last message object are reset 270 340 ky ST10F269 USER S MANUAL ON CHIP CAN INTERFACES The counters of the EML are left unchanged Setting bit CCE in additi
397. nly XXXXh SSCRIC b FF74h SSCTB SSC Transmit Buffer write only SSCTIC b SSC Transmit Interrupt Control Register STKOV 0 CPU Stack Overflow Pointer Register STKUN 0 CPU Stack Underflow Pointer Register FCOOh SYSCON b CPU System Configuration Register Oxx0h 1 TO CAPCOM Timer 0 Register 0000h TOICON b TOIC b FF9Ch C CAPCOM Timer 0 Interrupt Control Register 00h T1 FE52h 29n CAPCOM Timer 1 Register T1IC b C CAPCOM Timer 1 Interrupt Control Register T1REL 2 CAPCOM Timer 1 Reload Register T2 GPT1 Timer 2 Register DI 305 340 REGISTER SET ST10F269 USER S MANUAL Table 56 Special function registers listed by name continued Physical 8 bit Name address address Description T2CON FF40h AOh GPT1 Timer 2 Control Register Talo T3 FE42h 21h GPT1 Timer 3 Register 0000h Talo T4 22h GPT1 Timer 4 Register T4CON A2h GPT1 Timer 4 Control Register T4IC B2h GPT1 Timer 4 Interrupt Control Register Ts T5CON FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC FF66h GPT2 Timer 5 Interrupt Control Register 00h Te T6CON A4h GPT2 Timer 6 Control Register T6IC B4h GPT2 Timer 6 Interrupt Control Register T7 28h CAPCOM Timer 7 Register T78CON 90h CAPCOM Timer 7 and 8 Control Register T7IC E BEh CAPCOM Timer 7 Interrupt Control Register T7REL E 2Ah CAPCOM Timer 7 Reload Register T8IC F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register 00h T8REL F
398. noncncnnnnnnnnnncnonnncnnonnco nana canannncnnnnss 296 21 4 OUTPUT PIN STATUEN 300 22 REGISTER SET valiosa nana 301 22 1 REGISTER DESCRIPTION FORMAT 301 22 2 GENERAL PURPOSE REGISTERS GPRS occcccnococinoncninancnnanannnanannnonnnncanacacinnccnnns 302 22 3 SPECIAL FUNCTION REGISTERS ORDERED BY NAME eeren 303 22 4 REGISTERS ORDERED BY ADDRESS seeieeeeesiieerrrerrresrrnsrrrrerrrserrssrrrsrrrrsnre 309 22 5 XREGISTERS LISTED NAME A 315 22 6 X REGISTERS ORDERED BY ADDRESS concccccccccccnnncncnnnnnnnancnnnnnnaninnnn cnn nn nana nanannnos 316 22 7 SPECIAL NOME eier IR ies 317 22 8 IDENTIFICATION REGISTERS A 317 23 SYSTEM PROGRAMMING cicle e 319 23 1 STACK OPERATIONS gt tic ai ENEE 321 23 2 REGISTER BANKING sie ipinia aa ei iae a ea a eta a aa ai aea 324 23 3 PROCEDURE CALL ENTRY AND ENIT na ranacanannncnnnnos 325 23 4 TABLE SEARCHING hess tsiera ii ia ENEE ad e ai 326 23 5 PERIPHERAL CONTROL AND INTERFACE ccccccccccconnncconnnoncnnnnnnonnnacinnnncnannnnnanacanannss 327 23 6 FLOATING POINT SUPPORTEREN 327 23 7 TRAP INTERRUPT ENTRY AND ENIT ccc ceeeeceeeceeeeeeneeeeeneeeeeeeeseaeeeeeaeeeseeeeseaeees 327 23 8 INSEPARABLE INSTRUCTION SEQUENCES A 327 23 9 OVERRIDING THE DPP ADDRESSING MECHANISM 328 23 10 HANDLING THE INTERNAL FLASH coccccccocccccnccconnncncnnncnnonnnnnnnn nc nono cnn ran rca rancia rannnncannss 329 23 11 PITS TRAPS AND MINES A 330 24 KEY WORD INDEX ocio ds 331 25 INDEX OF REGISTERS cin a 335 26 REVISION HISTORY iii ate 3
399. not The control bit xxlE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not In order to be arbitrated both dedicated and global enable bit of the interrupt source must be set The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged disclosing all other requests The priority level of the source that wins the arbitration is compared against the CPU s current level and only this source is serviced If its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level 0 will be disabled and never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful for semaphore handling and does not require to re enable the interrupt system after the inseparable instruction sequence see Chapter 23 System Programming 6 3 2 Interrupt Class Management An interrupt class covers a set of interrupt sources with the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The ST10F269 supports this function with two features
400. nput frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input which is an alternate function of P3 6 To enable this operation pin T3IN P3 6 must be configured as input and direction control bit DP3 6 must contain 0 see Figure 71 If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request 162 340 oy ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 001b In counter mode timer T3 is clocked by a transition at the external input pin T3IN which is an alternate function of P3 6 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T3I in control register T3CON selects the triggering transition see Table 31 Figure 71 Core timer T3 in gated timer mode Interrupt Request P3 4 NY Figure 72 Co
401. ns associated with timer block GPT2 Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 ODP3 E T5 YY YY YY YY YY YY YY YY DP3 T6 YYYYYYYYYYYYYYYY P3 CAPREL Y Y Y Y Y Y YY YYYYYYYY P5 Control Registers Interrupt Control 1514131211109876543210 1514131211109876543210 T5CON Y YY YY YYYYYYYYYYY T5IC YYYYYYYY T6CON Y YY YYYYYYYYYYYYY T6IC YYYYYYYY CRIC YY YY VV VV T5IN P5 13 T5EUD P5 11 T6IN P5 12 T6EUD P5 10 CAPIN P3 2 T6OUT P3 1 ODP3 Port 3 Open Drain Control Register TS GPT2 Timer 5 Register DP3 Port 3 Direction Control Register T6 GPT2 Timer 6 Register P3 Port 3 Data Register CAPREL GPT2 Capture Reload Register P5 Port 5 Data Register T5IC GPT2 Timer 5 Interrupt Control Register T5CON GPT2 Timer 5 Control Register T6IC GPT2 Timer 6 Interrupt Control Register T6CON GPT2 Timer 6 Control Register CRIC GPT2 CAPREL Interrupt Control Register ky 173 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Figure 83 GPT2 block diagram T5EUD P5 11 U D de GPT2 Timer T5 interrupt TSIN Ger Request P5 13 Clear J Capture CAPIN Interrupt P32 KA Request GPT2 CAPREL Reload Interrupt y Request T6IN P5 12 T6 Mode GPT2 Timer T6 T6OUT CPU Clock 1 2n n 2 9 Control P3 1 gesoet e Up Down to CAPCOM P5 10 A
402. nstruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow regis ters is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below ky 319 340 SYSTEM PROGRAMMING ST10F269 USER S MANUAL Circular Virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack empties upward to higher
403. ntain a valid reset vector and valid code at its destination Mapping the internal Flash to segment 1 Due to instruction pipelining any new Flash mapping will at the earliest become valid for the second instruction after the instruction which has changed the Flash mapping To enable accesses to the Flash after mapping a branch to the newly selected Flash area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal Flash to segment 0 Enabling the internal Flash after reset When enabling the internal Flash after having booted the system from external memory note that the ST10F269 will then access the internal Flash using the current segment offset rather than accessing external memory Disabling the internal Flash after reset When disabling the internal Flash after having booted the system from there note that the ST10F269 will not access external memory before a jump to segment O in this case is executed General Rules When mapping the Flash no instruction or data accesses should be made to the internal Flash otherwise unpredictable results may occur To avoid these problems the instructions that configure the internal Flash should be executed from external memory or from the internal RAM Whenever the internal Flash is disabled enabled or re mapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal Flash and or external memory 328 340 ky ST10F
404. ntation is disabled only one 64 Kbyte segment can be used and accessed Otherwise additional address lines may be output on Port4 and or several chip select lines may be used to select different memory banks or peripherals These functions are selected during reset via bit fields SALSEL and CSSEL of register RPOH respectively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not Segmentation disabled 9 2 1 Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra segment address and data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width an 8 bit data bus requires a byte latch the address bit A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word latch the least significant address line AO is not relevant for word accesses The upper address lines An A16 are permanently output on Port4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates
405. ntee correct results 158 340 iy ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Figure 68 SFRs and port pins associated with timer block GPT1 1514131211109876543210 Ports A Direction Control Alternate Functions Data Registers 1514131211109876543210 a ODP3E T2 Y Y YY YYYYYYYYYYYY DP3 TIY YY YYYYYYYYYYYYY P3 T41Y Y YY YYYYYYYYYYYY P5 Control Registers Interrupt Control 1514131211109876543210 1514131211109876543210 T2CON Y Y Y Y Y Y YYYYYYYYYY T2iIC YYYYYYYY T3CON JY Y Y Y Y Y Y YYYYYYYYY TSIC YYYYYYYY T4CON Y Y Y Y Y Y YYYYYYYYYY T4IC YYYYYYYY T2IN P3 7 T2EUD P5 15 T3IN P3 6 T3EUD P3 4 T4IN P3 5 T4EUD P5 14 T3OUT P3 3 ODP3 Port 3 Open Drain Control Register T2 GPT1 Timer 2 Register DP3 Port 3 Direction Control Register T3 GPT1 Timer 3 Register P3 Port 3 Data Register T4 GPT1 Timer 4 Register T2CON GPT1 Timer 2 Control Register T2IC GPT1 Timer 2 Interrupt Control Register T3CON GPT1 Timer 3 Control Register T3IC GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register T4IC GPT1 Timer 4 Interrupt Control Register Y Bitis linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 159 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL Figure 69 GPT1 block diagram T2EUD G P5 15 y U D GPT1 Timer T2 gt Interrupt C
406. ntifier in transmit object remain unchanged except for the last message object which cannot start a transmission Here the identifier bit corresponding to the don t care bit of the last message object s mask may be overwritten by the incoming message a 261 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL Upper Arbitration Reg EFn2h EEn2h XReg Reset Value VUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1D20 18 1D17 13 1D28 21 RW RW RW Lower Arbitration Reg EFn4h EEn4h XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID4 0 aa ID12 5 RW R R R RW Bit Function 1D28 0 Identifier 29 bits Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bit ID17 0 are don t care Message Configuration and Data The following fields hold a description of the message within this object The data field occupies the following 8 byte positions after the Message Configuration Register Note There is no don t care option for bit XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data byte into a message object If the data length code was less than 8 the remaining byte of the
407. ny PWM channel Software Control of the PWM Outputs In an application the PWM output signals are generally controlled by the PWM module However it may be necessary to influence the level of the PWM output pins via software either to initialize the system or to react on some extraordinary condition like a system fault or an emergency Clearing the timer run bit PTRx stops the associated counter and leaves the respective output at its current level The individual PWM channel outputs are controlled by comparators according to the formula PWM output signal PTx gt PWx shadow latch So whenever software changes registers PTx the respective output will reflect the condition after the change Loading timer PTx with a value greater than or equal to the value in PWx immediately sets the respective output a PTx value below the PWx value clears the respective output By clearing or setting the respective Port7 output latch the PWM channel signal is driven directly or inverted to the port pin Clearing the enable bit PENx disconnects the PWM channel and switches the respective port pin to the value in the port output latch Note To prevent further PWM pulses from occurring after such a software intervention the respective counter must be stopped first Figure 127 PWM output signal generation PWM 3 A L PWMCON1 PEN3 Latch P7 3 Pin P7 3 PWM 2 A g Latch P7 2 Pin P7 2 PWM 1 Latch P7 1 Pin P7 1 PW
408. o a ESFR 512 bytes 07 E Block3 32 Kbytes 00 F000 06 lorsoo0 00 EFFF o CANT 256 bytes 05 Block2 y Block1 00 EF0O 04 Block0 00 EEFF Segment 1 CAN2 256 bytes 03 00 EE00 00 EC14 02 F Real Time Clock 00 ECOO Block2 8 Kbytes Segment 0 01 Block1 8 Kbytes 00 E7FF XRAM1 2 Kbytes 00 Block0 16 Kbytes 00 E000 00 DFFF Data Absolut Internal Page Memory Flash Number Address Memory XRAM2 8 Kbytes 00 C000 Block O 1 2 may be remapped from segment 0 to segment 1 by setting SYSCON ROMS1 before EINIT Data Page Number and Absolut Memory Address are hexadecimal values DI 25 340 MEMORY ORGANIZATION ST10F269 USER S MANUAL Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address Double words code only are stored in ascending memory locations as two subsequent words Single bit are always stored in the specified bit position at a word address Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers Figure 5 Storage of words
409. o 16 bit timers TO T1 in CAPCOM1 T7 T8 in CAPCOM2 each with its own reload register TxREL and a bank of sixteen dual purpose 16 bit capture compare registers CCO through CC15 in CAPCOM1 CC16 through CC31 in CAPCOM2 The input clock for the CAPCOM timers is programmable to several pre scaled values of the CPU clock or it can be derived from an overflow underflow of timer T6 in block GPT2 TO and T7 may also operate in counter mode from an external input where they can be clocked by external events Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer of the associated unit Each capture compare register has one port pin associated with it which serves as an input pin for the capture function or as an output pin for the compare function except for CC27 CC24 on P1H 7 P1H 4 which only provide the capture function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow Figure 111 shows the basic structure of the two CAPCOM units Figure 111 CAPCOM unit block diag
410. o 38 Elec ui ls aid 40 a E EEEE E A B ad ahead ee 294 POCONO Teni eaa E a aTa KaTa 100 A aiaa aeee ee tanet ddaa iig 22 input threshold 2 c eeeeeeeeeeeeees 97 99 Power Down Mode 296 Protected Bits ia A Ae ets 44 PO Winslet dla 48 79 Pulse Width Modulation 0000sseeeeeeees 25 PWM Legosteng ee 25 KEY WORD INDEX PWM Module coooooconnnnnnnccccccccccncnnnncnnncnccccnononons 233 PWMCONO cocccccccnccconnncnnononnnnnncnnnnnonononnnonnnnnnos 241 PWMGONT cc 242 R RAM GK EL EE 34 internal iii ici 29 Read Write Delay ooooooconccccnnociconoccconacncnanacannnos 146 READ lie aaa iaa 146 Register AA 301 303 309 Reset Configuration concccnnnnccnnnnccnnncccninnccinannns 288 Output rancia Dee ene 287 VUE 288 RPOH A addy ade ai 291 A auton ies eenig deet ed 276 S A EA ES 193 SOCON escitas Aes Sletten Ez 187 SORBUE sstunsstansnla lc 191 193 cl dE ite Stee een ts 195 SOTBIC SOEIC uxecrcrocicitcisandrracina rosario curada sis 195 SOTBUP ad ean 190 192 SOT ii A A e 195 Segment o ae eera teen lel as 140 293 boundaries 36 Segmentation Enable Disable cc cccccccccccccsesssesssteees 46 Serial Interface pnis aniraa inier 23 ASYNCHIONOUS conccccccccnncnnnnnnnananccnnnnnnn cnn 189 A ed tins oees tes acetate 23 252 SYNCHIONOUS conoccccccoonnncnnnonannncnnninnos 192 197 SER ara 33 303 309 Single Chip Mode sses 134 Single shot mode PWM sesse 239 Slave mode c
411. o the on chip Real Time Clock are disabled external access is performed Address range 00 EC00h 00 ECFFh is only directed to external memory if CAN1EN and CAN2EN are 0 also 1 The on chip Real Time Clock is enabled and can be accessed When both CAN are disabled via XPERCON setting then any access in the address range 00 EE00h 00 EFFFh will be directed to external memory interface using the BUSCONx register corresponding to address matching ADDRSELx register P4 4 and P4 7 can be used as General Purpose I O when CAN2 is disabled and P4 5 and P4 6 can be used as General Purpose UO when CANT is disabled The default XPER selection after Reset is identical to XBUS configuration of ST10C167 XCAN1 is enabled XCAN2 is disabled XRAM1 2 Kbyte compatible XRAM is enabled XRAM2 new 8 Kbyte XRAM is disabled Register XPERCON cannot be changed after the global enabling of XPeripherals i e after the setting of bit XPEN in the SYSCON register In EMUlation mode all the XPERipherals are enabled XPERCON bit are all set The access to external memory and or XBus is controlled by the bondout chip When the Real Time Clock is disabled RTCEN 0 the clock oscillator is switch off if the ST10 enters in power down mode Otherwise when the Real Time Clock is enabled the bit RTCOFF of the RTCCON register allows to choose the power down mode of the clock oscillator See Chapter 19 Real Time Clock 157 340 THE GEN
412. oaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Note The direction control bit DP3 7 for T2IN and DP3 5 for T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 CPU clock cycles before it changes to ensure correct edge detection 10 1 3 Interrupt Control for GPT1 Timers When a timer overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down its interrupt request flag T2IR T3IR or T4IR in register TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger a PEC service if the respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers T2IC FF60h BOh SFR Reset Value 00h 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 e e T2IR T2IE ILVL GLVL DW RW RW RW T3IC FF62h B1h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 z S i z z T3IR T3IE ILVL GLVL DW RW RW RW T4IC FF64h B2h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z E TAIR T4E ILVL GLVL DW RW RW RW Note Please refer to the general Interrupt Control Register description for an explanation of the con trol fields 172 340 ky ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS 1
413. occoccccccccnnnncccnnnnncnononononnnonononinananans 156 Software BR 91 Source lee 74 SP tela bn 55 A A ees Big elei e 197 Baudrate generation eee 205 Error Detection ooccnccccccncncnnnnnncnncnnnnno 206 Full Duplex caos tati 201 331 340 KEY WORD INDEX Half Duplex cooooccccncnocccccconannccnnnnnnncnnnnnnns 203 SOSGBR ui ta 205 SSCCON inncccnnnnnnnnnnnnnnnnnnancnnnnnn nn ran nn cnn rra 198 E O EE E entered 207 SSCRB SSCTB NEEN 203 SSOR aeaii eea nen etin a aE kadaa eiiean 207 e NEE 207 TEE 31 55 321 Startup Configuration oooconcccnnncccnncicinncccnannno 288 SKOV Gnas cate etna nals erie a nets 56 STKUN ciar il mee dde 56 SUDOVE iii 325 Synchronous Serial Interface 197 SYSCON EE 45 System Reset Startup Configurations ooooccnocccnnnccccnnnns 290 T WO traida 219 TOAGON A T 219 Tv eo idos 219 120 ON stato todita 169 Tela anand ee ae tec 174 TR CON tenes a 162 HRC GE 174 TACON cenccccoccnnonnnnnannnnnonnno nono nnnnnnnc naar ca nnnnncnnnne 169 A E 174 HESE E WEE lena 180 A gies iene Nai ete ae 185 JEON taa 176 TOO teaa e a 185 332 340 ST10F269 USER S MANUAL WEA AA Aa 219 MLBGON veen elatieciietcatel dst 219 HK 219 A Seet et a A 97 99 Meda aa 23 160 175 Auxiliary Timer seese 169 180 CAPCOM tacones dietas 219 Concatenation ccccccccccccccccccccnnnnnos 170 182 Core TIME ainia ice daa 162 176 HRC E APRO CO 76 90 Tri State Time errietara s a aas 145 U Unsep
414. ock cycle for each of these conditions When instruction N reads an operand from the internal memory or when N is a CALL RETURN TRAP or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 CPU clock cycles during internal Flash program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 CPU clock cycles The worst case interrupt response time during internal Flash program execution adds to 12 CPU clock cycles Any reference to external locations increases the interrupt response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay ky 83 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL A few examples illustrate these delays The worst case interrupt response time including external accesses occurs when instructions N N 1 and N 2 are executed from external memory instructions N 1 and N require external operand read accesses instructions N 3 to N write back external operands and the interrupt ve
415. oding the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT When the protection fault trap occurs the IP value pushed onto the system stack is the address of the faulty instruction 6 7 8 Illegal word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap ky 91 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL 6 7 9 Illegal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction 6 7 10 Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap 92 340 ky ST10F269 USER S MANUAL PARALLEL PORTS 7 PARALLE
416. of 8TCL 4 CPU clock cycles No tristate wait state is used The CANS address area starts at 00 EFOOh 00 EEOOh and covers 256 bytes A dedicated hardwired XADRS XBCON register pair selects the respective address window so none of the programmable register pairs must be sacrificed in order to access the on chip CAN Modules Locating the CAN address area to address 00 EFO0h 00 EE00h in segment 0 has the advantage that the CAN Modules are accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space Power Down Mode If the ST10F269 enters Power Down Mode the XCLK signal will be turned off which will stop the operation of the CAN Module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down Mode The CPU can check if a transmission is in progress by reading bit TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down Mode via hardware reset the CAN Modules have to be reconfigured 18 7 CAN Application Interface The on chip CAN Module of the ST10F269 does not incorporate the physical layer conn
417. of America www st com a 340 340 DoclD8456 Rev 2
418. on allows changing the configuration in the bit Timing Register To initialize the CAN Controller the following actions are required Configure the bit Timing Register CCE required Set the Global Mask Registers Initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL so it is defined as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears the INIT bit To change the configuration of a message object during normal operation the CPU first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again Accessing the On chip CAN Module The CAN Modules are implemented as an X Peripheral and are therefore accessed like an external memory or peripheral so the registers of the CAN Module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Since the XBUS to which the CAN Module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN Modules use de multiplexed addresses and a 16 bit data bus byte accesses possible Two wait states give an access time
419. on rising edge falling edge or both edges Fast external interrupts may also have interrupt sources selected from other peripherals for example the CANx controller receive signal CANx_RxD can be used to interrupt the system This new function is controlled using the External Interrupt Source Selection register EXISEL The EXxIN pins can also be used to exit power down mode if bit PWDCFG in the SYSCON register is set Power reduction modes are detailled in Chapter 21 Power Reduction Modes EXICON F1C0h E0h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXIOES RW RW RW RW RW RW RW RW Bit Function EXIxES External Interrupt x Edge Selection Field x 3 0 x 7 0 0 0 Fast external interrupts disabled standard mode EXxIN pin not taken in account for entering exiting Power Down mode 0 1 Interrupt on positive edge rising Enter Power Down mode if EXilN 0 exit if EXxIN 1 ref as high active level 1 0 Interrupt on negative edge falling Enter Power Down mode if EXilN 1 exit if EXxIN 0 ref as low active level 1 1 Interrupt on any edge rising or falling Always enter Power Down mode exit if EXxIN level changed These fast external interrupts use the interrupt nodes and vectors of the CAPCOM channels CC8 CC15 so the capture compare function cannot be used on the respective Port2 pins with EXIxES
420. or when it underflows from 0000h to FFFFh the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow of T6 Figure 90 GPT2 register CAPREL in reload mode CAPREL Register A T6OUT P3 1 T6SR T6OE Core Timer T6 Interrupt EES Request p To CAPCOM Up Down Timers ky 181 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL GPT2 Capture Reload Register CAPREL in Capture and Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bit T5SC and T6SR the two functions can be enabled simultaneously by setting both bits This feature can be used to generate an output frequency that is a multiple of the input frequency see Figure 91 This combined mode can be used to detect consecutive external events which may occur periodically but where a finer resolution that means more ticks within the time between two external events is required For this purpose the time between the external events is measured using timer T5 and the CAPREL register For example Timer T5 runs in timer mode counting up with a frequency of fepy 32 The external events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5
421. ory mapped in segment 0 is later required then the code that performs the setting of ROMEN bit must be executed either in the segment O but above address 00 8000h or from the internal RAM Bit ROMS1 only affects the mapping of the first 32 Kbytes of the Flash memory All other parts of the Flash memory addresses 01 8000h 04 FFFFh remain unaffected The SGTDIS Segmentation Disable Enable must also be set to 0 to allow the use of the full 256 Kbytes of on chip memory in addition to the external boot memory The correct procedure on changing the segmentation registers must also be observed to prevent an unwanted trap condition Instructions that configure the internal memory must only be executed from external memory or from the internal RAM An Absolute Inter Segment Jump JMPS instruction must be executed after Flash enabling to the next instruction even if this next instruction is located in the consecutive address Whenever the internal Memory is disabled enabled or remapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal memory and or external memory When starting from external memory the interrupt trap vector table which uses locations 00 0000h through 00 01FFh of the external memory and may therefore be modified so the system software may now change interrupt trap handlers according to the current condition of the system ky 327 340 SYSTEM PROGRAMMING ST10F269 U
422. other bus master shall share external resources some glue logic is required that defines the currently active bus master and also enables a ST10F269 which has surrendered its bus interface to regain control of it in case it must access the shared external resources This glue logic is required if the other bus master does not automatically remove its hold request after having used the shared resources When two ST10F269 are connected in this way the external glue logic can be left out In this case one of the controllers must be operated in its master mode default after reset DP6 7 0 while the other one must be operated in its slave mode selected with DP6 7 1 In slave mode the ST10F269 inverts the direction of its HLDA pin and uses it as an input while the master s HLDA pin remains an output This approach does not require any additional glue logic for the bus arbitration see Figure 65 When the bus arbitration is enabled HLDEN 1 the three corresponding pins are automatically controlled by the EBC Normally the respective port direction register bit retain their reset value which is 0 This selects master mode where the device operates compatible with earlier versions slave mode is enabled by intentionally switching pin BREQ to output DP6 7 1 which is neither required for Master Mode nor for earlier devices 9 6 2 Entering the Hold State Access to the ST10F269 s external bus is requested by driving its HOLD
423. ows the PWRDN instruction is executed before the CPU performs a call of the interrupt service routine Figure 158 Delay with RC on RPD pin VDD ST10F269 R1 220 k 1MQ Typ RPD C1 1uF Typ 296 340 ky ST10F269 USER S MANUAL POWER REDUCTION MODES Figure 159 Simplified powerdown exit circuitry VDD f sto pa D Q gt stop Pscillator Q1 VDD enter powerdown gt cdQ exit_pwrd weak pull down external 200 uA en_clk_n mame CPU and Peripherals clocks System clock Figure 160 Powerdown exit sequence when using an external interrupt PLL x 2 XTAL1 CPU clk internal Powerdown signal Bae External Interrupt RPD ExitPwrd internal delay for oscillator pll stabilization 297 340 POWER REDUCTION MODES ST10F269 USER S MANUAL 21 4 Output Pin Status During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function WR or to a defined state which is based on
424. peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external address space If possible the CPU continues to operate while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in The External Bus Interface see Chapter 9 The External Bus Interface The on chip peripheral units of the ST10F269 are almost independent of the CPU with a separate clock generator Data and control information is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chip Interrupt Controller compares all pending peripheral interrupt requests and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt service will occur There are two types of interrupt processing 1 Standard interrupt processing forces the CPU to save the current program status and return address on the stack before branching to the interrupt vector jump table 2 PEC interrupt processing steals just one instruction cycle from the current CP
425. products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR E
426. pt only 1 Channel x output signal enabled PMx PWM Channel x Mode Control bit 0 Channel x operates in mode 0 i e edge aligned PWM 1 Channel x operates in mode 1 i e center aligned PWM PBO1 PWM Channel 0 1 Burst Mode Control bit 0 Channels O and 1 work independently in respective standard mode 1 Outputs of channels O and 1 are ANDed to POUTO in burst mode PSx PWM Channel x Single Shot Mode Control bit 0 Channel x works in respective standard mode 1 Channel x operates in single shot mode 16 3 Interrupt Request Generation Each of the four channels of the PWM module can generate an individual interrupt request Each of these channel interrupts can activate the common module interrupt which actually interrupts the CPU This common module interrupt is controlled by the PWM Module Interrupt Control register PWMIC The interrupt service routine can determine the active channel interrupt s from the channel specific interrupt request flags PIRx in register PWMCONO The interrupt request flag PIRx of a channel is set at the beginning of a new PWM cycle when loading the shadow registers This indicates that registers PPx and PWx are now ready to receive a new value If a channel interrupt is enabled via its respective PIEx bit also the common interrupt request flag PWMIR in register PWMIC is set provided that it is enabled via the common interrupt enable bit PWMIE Note Th
427. put channel 18 P8 3 CC19IO0 Capture input compare output channel 19 P8 4 CC20I0 Capture input compare output channel 20 P8 5 CC2110 Capture input compare output channel 21 P8 6 CC22IO Capture input compare output channel 22 P8 7 CC23I0 Capture input compare output channel 23 127 340 PARALLEL PORTS ST10F269 USER S MANUAL Figure 50 Port8 I O and alternate functions Alternate Function gt lt W gt General Purpose Input Output 128 340 ky ST10F269 USER S MANUAL PARALLEL PORTS The pins of Port8 combine internal bus data and alternate data output before the port latch input as do the Port2 pins Figure 51 Block diagram of Port8 pins Write ODP8 y Open Drain Latch Read ODP8 y E Write DP8 y Direction Latch Read DP8 y dn Internal Bus 1 yv v MUX Output _ gt N P8y Alternate Latch Output MJ CCzIO Data 0 Buffer Output Write Port P8 y Compare Trigger Read P8 y Clock 4 a MUX y 0 7 0 Input z 16 23 Latch Alternate Latch Data Input a Alternate Pin Data Input ky 129 340 DEDICATED PINS ST10F269 USER S MANUAL 8 DEDICATED PINS Most of the input output or control signals of the ST10F269 are realized as alternate functions of pins of the parallel ports There is however a number of signals that use separate pins including the oscillator special control signals and
428. put signal should be held for at least 8 CPU clock cycles before it changes its level During these 8 CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence If pin CCxIO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software like for testing purposes Figure 114 Capture mode block diagram Edge Capture Register CCx Select V N CCxIO Interrupt Y Es CCxIR Request CCMODx Input Interrupt Clock CAPCOM Timer Ty TyIR Request x 31 0 y 0 1 7 8 15 5 Compare Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to as compare value is continuously compared with the contents of the allocated timer TO T1 or T7 T8 If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding output pin CCxlO except for CC2410 CC2710 and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled As for capture mode the compare registers are
429. quests from a group of different sources on the same priority level At the end of each instruction cycle the request with the highest current priority will be determined by the interrupt system The request will be serviced If its priority is higher than the current CPU priority which is stored in the register PSW 74 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS 6 1 2 Interrupt System Register Description Interrupt processing is globally controlled by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different interrupt sources are individually controlled by their specific interrupt control registers 1C Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW PEC services are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel 6 1 3 Interrupt Control Registers All interrupt control registers are identically organized The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization the upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software This allows each interrupt source to be programme
430. r O Disables CPU access to the bit timing register TST Test Mode bit 7 Make sure that bit 7 is cleared when writing to the Control Register Writing a 1 during normal operation may lead erroneous device behaviour LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus Ifa message has been transferred reception or transmission without error this field will be cleared Code 7 is unused and may be written by the CPU to check for updates 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed Form Error A fixed format part of a received frame has the wrong format AckError The message this CAN controller transmitted was not acknowledged by another node Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominant Bit0Error During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been mon itored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continuously disturbed CRCError The C
431. r by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the Baud rate generator transmission only starts if SSCEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the pre programmed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift register It will not wait for the next clock from the Baud rate generator as t
432. r from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog time register WDT with the preset value in bit field WDTREL which is the high byte of register WOTCON Servicing the watchdog timer will also reset bit WDTR ky 207 340 WATCHDOG TIMER ST10F269 USER S MANUAL After being serviced the watchdog timer continues counting up from the value WDTREL x 2 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer eg by fetching and executing a bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than the instruction be executed The PONR flag of WDTCON register is set if the output voltage of the internal 3 3V supply falls below the threshold typically 2V of the power on detection circuit This circuit is efficient to detect major failures of the external 5V supply but if the internal 3 3V supply does not drop under 2 volts the PONR flag is not set This could be the case on fast switch off switch on of the 5V supply The time needed for such a sequence to activate the PONR flag depends on the value of the capacitors connected to the supply and on the exac
433. r is buffered with a shadow register The shadow register is loaded from the respective PPx register at the beginning of every new PWM cycle or upon a write access to PPx while the timer is stopped The CPU accesses the PPx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx When a match is found between counter and PPx shadow register the counter is either reset to 0000h or the count direction is switched from counting up to counting down depending on the selected operating mode of that PWM channel For the register locations refer to the Table 44 Table 43 PWM frequencies Mode Counter 8 bit PWM 10 bit PWM 12 bit PWM 14 bit PWM 16 bit PWM resolution resolution resolution resolution resolution resolution fopu Mode 0 ou fopu 2 fopu 64 Mode fopu 64x28 fopu 64x2 fopu 64x2 fopu 64x2 fopu 64x2 9 fopu Mode 1 fopy 2x2 fopu 2x2 fopy 2x2 fopu 2x2 4 fopu 2x2 fopu 64 Mode 1 f pu 2x64x28 fopy 2x64x2 0 fopy 2x64x212 fopy 2x64x214 fgg y 2x64x2 238 340 ky ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE Pulse Width Registers PWx This 16 bit register holds the actual PWM pulse width value which corresponds to the duty cycle of the PWM signal This register is buffered with a shadow register The CPU accesses the PWx register while the hardware compares the contents of the shadow register with the contents of the assoc
434. r of the crystal must be less than 409 However higher frequencies can be applied with an external clock source the maximum depends on the duty cycle of the external clock signal Refer to product data sheet 4 The external clock input range refers to a CPU clock range of 1 to 40MHz The PLL free running frequency is from 2 to 10MHz If the PLL factor or the input clock frequency is changed when PortO is transparent the PLL needs a synchronization time to lock typical value is 500us Pins controlling the operation of the internal logic and the reserved pins are evaluated only during a hardware triggered reset sequence The pins that influence the configuration of the ST10F269 are evaluated during any reset Sequence even during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in chapter The External Bus Interface ky 289 340 SYSTEM RESET ST10F269 USER S MANUAL Note The reserved pins named R in the row Pot Bit Name of Table 51 must remain high during reset in order to ensure proper operation of the ST10F269 The load on those pins must be small enough for the internal pull up device to keep their level high or external pull up devices must ensure the high level The following describes the different selections that are offered for reset configuration The default modes refer to pins at high level without exte
435. r power transistors however a stable high output current may still be required as described below This rise fall time of 4 I O pads a nibble is selected using 2 bit named PNxEC That means Port Nibble x nibble number it could be 3 as for Port 2 15 to 2 12 Edge Characteristic The sink source capability of the same 4 I O pads is selected using 2 bit named PNxDC That means Port Nibble x nibble number Drive Characteristic See Table 18 DI 97 340 PARALLEL PORTS ST10F269 USER S MANUAL POCONx FOyyh zzh for 8 bit Ports ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S PN1DC PN1EC PNODC PNOEC RW RW RW RW POCONx FOyyh zzh for 16 bit Ports ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PN3DC PNZEO RW RW RW RW RW RW RW RW Bit Function PNxEC Port Nibble x Edge Characteristic rise fall time 00 Fast edge mode rise fall times depend on the size of the driver 01 Slow edge mode rise fall times 60 ns 10 Reserved 11 Reserved PNxDC Port Nibble x Driver Characteristic output current 00 High Current mode Driver always operates with maximum strength 01 Dynamic Current mode Driver strength is reduced after the target level has been reached 10 Low Current mode Driver always operates with reduced strength 11 Reserved Note In case of reading an 8 bit POCONX register high byte bit 15 8 is read as 00h The table l
436. r the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC FFOEh 87h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z z z z MS MS MS MDR MS MS MS MS IU RW RW RW RW RW RW RW RW Bit Function MDRIU Multiply Divide Register In Use 0 Cleared when register MDL is read via software 1 Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed MS Internal Machine Status The multiply divide unit uses these bit to control internal operations Never modify these bit without saving and restoring register MDC 56 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared prepare it for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware
437. ram Reload Register TXREL x 0 7 Interrupt Tx Request TxIN Input CAPCOM Timer Tx Control GPT2 Timer T6 Over Underflow S Mode S 16 Control Sixteen 16 bit 16 Capture inputs Capture Capture Compare Capture Compare Compare outputs or Registers Interrupt Requests S Compare S Interrupt Ty Request Input CAPCOM Timer Ty Control GPT2 Timer T6 Over Underflow y 1 8 Reload Register TyREL Note The CAPCOM2 unit provides 16 capture inputs but only 12 compare outputs 216 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS 15 1 CAPCOM Timers The primary use of the timers TO T1 and T7 T8 is to provide two independent time bases for the capture compare registers of each unit but they may also be used independent of the capture compare registers The basic structure of the four timers is identical while the selection of input signals is different for timers TO T7 and timers T1 T8 Figure 112 Block diagram of CAPCOM timers TO and T7 Tal Reload Register TXREL Input Control CPU Clock GPT2 Timer T6 a Interrupt Over Underflow P CAPCOM Timer Tx Request Edge Select TxR SIN S Tal TxM Txl x 0 7 Figure 113 Block diagram of CAPCOM timers T1 and T8 Tv Reload Register TXREL cru KA Clock GPT2 Timer T6 Interrupt Over Underflow CAPCOM Timer Tx Request TxM TxR x 1 8 Note When an external
438. ransmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must also be configured for output P3 11 1 and DP3 11 1 during transmission 190 340 OI ST10F269 USER S MANUAL ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the receiver enable bit SOREN is reset and serial data reception stops Pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must be configured as alternate data input DP3 11 0 Synchronous reception is stopped by clearing bit SOREN A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of the receive buffer register at the time
439. rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in three ways it can be used with other synchronous serial interfaces the ASCO in synchronous mode or configured in like master slave or multimaster interconnections or operate like the popular SPI interface It can communicate with shift registers 1 O expansion peripherals EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port3 pins Figure 98 SFRs and port pins associated with the SSC Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 ODP3E Y LAY SSCBRE Y Y Y Y Y YY YYYYYYYYY DP3 Y YY SSCTBE Y Y Y Y Y YYYYYYYYYYY P3 Y LAY SSCRBE Y Y Y Y Y Y YYYYYYYYYY Control Registers Interrupt Control 1514131211109876543210 1514131211109876543210 SSCCON Y Y Y Y Y YY YY YYYYY SSCTIC YYYYYYYY SSCRIC YYYYYYYY SSCEIC YYYYYYYY SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port3 Open Drain Control Register DP3 Port3 Direction Control Register P3 Port3 Data Register SSCBR SSC Baud Rate Generator Reload Register SSCCON SSC Contro
440. re 143 Handling of the last message object s alternating buffer Reset CPU releases Buffer 2 YYY Buffer 1 released Buffer 2 released CPU access to Buffer 2 CPU releases Buffer 1 CPU allocates Buffer 2 Buffer 1 released Buffer 2 allocated CPU access to Buffer 2 Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 allocated CPU access to Buffer 2 CPU releases Buffer 2 Store received message into Buffer 1 MSGLST is set Allocated NEWDAT 1 OR Released NEWDAT 0 AND 268 340 Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 released CPU access to Buffer 1 Store received Message into Buffer 2 Buffer 1 allocated Buffer 2 allocated CPU access to Buffer 1 CPU releases Store received Buffer 1 message into Buffer 2 MSGLST is set RMTPND 1 RMTPND 0 ST10F269 USER S MANUAL Figure 144 CAN controller handling of bus recovery sequence ON CHIP CAN INTERFACES No busoff 1 received 1 sequence of 11 recessive bit 4 Yes BitO error 1 128 occurence of idle bus Yes busoff 0 269 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL Figure 145 CPU handling of bus recovery busoff 1 and init 1 init 0 LEC 7 BitO error 1 No y busisstuck wait end of recovery 18 6 I
441. re timer T3 in counter mode Edge Select Interrupt Core Timer T3 gt Request Up Down oo d T3OUT P3 3 Table 31 GPT1 core timer T3 counter mode input edge selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 001 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 011 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination DI 163 340 THE GENERAL PURPOSE TIMER UNITS ST10F269 USER S MANUAL For counter operation pin T3IN P3 6 must be configured as input and direction control bit DP3 6 must be 0 The maximum input frequency which is allowed in counter mode is fcpy 16 To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized its level should be held high or low for at least 8 CPU clock cycles before it changes Timer 3 in Incremental Interface Mode Incremental interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 110b In incremental interface mode the two inputs associated with timer T3 T3IN T3EUD are used to interface to an incremental encoder T3 is clocked by each transition on one or both of the external input pins which gives 2 fold or 4 fold resolution to the encoder input see Figure 73 Bit field T3I in control register T3CON selects the triggering transitions see Table 32 I
442. register see Table 4 For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesses are supported by the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also allow to implement a circular stack with hardware supported system stack flushing and filling except for the 2 Kbyte stack option The technique of implementing this circular stack is described in Section 23 1 Stack Operations Circular virtual Stack Table 4 Stack size STKSZ Stack Size words Internal RAM Addresses words 000b 00 FBFEh 00 FAOOh Default after Reset 001b 00 FBFEh 00 FBOOh 0 10b 00 FBFEh 00 FB80h 011b 00 FBFEh 00 FBCOh 100b 00 FBFEh 00 F800h 101b Reserved Do not use this combination 110b Reserved Do not use this combination 111b 00 FDFEh 00 F600h Note No circular stack 3 2 2 General Purpose Registers The general purpose registers GPRs use a block of 16 consecutive words within the internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and
443. rent segment Data Pages are contiguous blocks of 16 Kbytes each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper bit of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 Kbytes data page boundaries therefore will use different data page pointers while the physical locations need not be subsequent within memory 34 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU 4 THE CENTRAL PROCESSING UNIT CPU The CPU is used to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results A four stage pipeline is implemented where up to four instructions can be processed in parallel Most instructions of the ST10F269 are executed in one instruction cycle due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump instructions in particular The general instruction timing is described including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself external
444. resents the content of the reload register taken as unsigned 13 bit integers SOBRS represents the value of bit SOBRS CO or 1 taken as integer Using the above equation the maximum Baud rate can be calculated for any given clock speed 11 5 ASCO Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrary to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software 192 340 oy ST10F269 USER S MANUAL ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE SOTIC FF6Ch B6h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOTIR SOTIE ILVL GLVL RW RW RW RW SORIC FF6Eh B7h SFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SORIR SORIE ILVL
445. revious slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above 12 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver The non transmitting devices use open drain output and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By these means any corruptions on the common data exchange line are detected where the received data is not equal to the transmitted data ky 201 340 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL Figure 102 SSC half duplex configuration Master Device 1 Device 2 Slave Shift Register Shift Register Common Transmit i Receive Device 3 Slave Line
446. rnal pull down devices connected Emulation mode When low during reset pin POL O EMU selects the Emulation Mode This mode allows the access to integrated XBus peripherals via the external bus interface pins in application specific version of the ST10F269 In addition also the RSTOUT pin floats to tristate rather to be driven low When the emulation mode is latched the CLKOUT output is automatically enabled This mode is used for special emulator purposes and is not used in basic ST10F269 devices so in this case POL O should be held high Default Emulation Mode is off Adapt mode Pin POL 1 ADP selects the Adapt Mode when low during reset In this mode the ST10F269 goes into a passive state which is similar to its state during reset The pins of the ST10F269 float to tristate or are deactivated via internal pull up pull down devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low and the on chip oscillator is switched off This mode allows switching a ST10F269 that is mounted to a board virtually off so an emulator may control the board s circuitry even though the original ST10F269 remains in its place The original ST10F269 also may resume to control the board after a reset sequence with POL 1 high Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device
447. roups see examples below Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not reference the respective port see Particular Pipeline Effects in chapter The Central Processing Unit SINGLE_Bit BSET P4 7 Initial output level is high BSET DP4 7 Switch on the output driver Bit_GROUP BFLDH P4 24H 24H Initial output level is high BFLDH DP4 24H 24H Switch on the output drivers 7 1 4 Output Driver Control The port output control registers POCONx allow to select the port output driver characteristics of a port The aim of these selections is to adapt the output drivers to the application s requirements and to improve the EMI behaviour of the device Two characteristics may be selected Edge characteristic defines the rise fall time for the respective output Slow edges reduce the peak currents that are sinked sourced when changing the voltage level of an external capacitive load For a bus interface or pins that are changing at frequency higher than 1MHz however fast edges may still be required Driver characteristic defines either the general driving capability of the respective driver or if the driver strength is reduced after the target output level has been reached or not Reducing the driver strength increases the output s internal resistance which attenuates noise that is imported via the output line For driving LEDs o
448. rror Detection CAN a an eee ss 253 SSC Aire ie ae cies A et ee es 206 EXIGON WEE 89 External BUS ill liliana 18 Bus Characteristics cooccconnnnnccnnns 142 Bus Idle State cconnncccccccccccnncnccccnnnnnccnns 155 Bus Modes cooocoocccnncnncncocenenennninnnnnnos 136 140 Ipterrupte ee 87 F Fast external interrupts eeren 89 A ante hate a atte 49 PASM ciedad 28 REEI cnc 201 G Global Mask Short ccccccccncnonocononcnoconnnnccnnnos 260 GPR EE 31 302 EE 23 ET KEE 160 EE Eer e Ee 175 H Half Duplex cer eee eeeeeeeeeeeeeeeeeeeetneeeeeeeeaaes 203 Hardware TADS iz 17 91 Hold State rss cess tice terest diodos 156 330 340 ST10F269 USER S MANUAL l Idle State BUS srania ean enanat 155 Idle Mode 295 Incremental Interface Mode 166 182 Input threshold cccccceeeeeeeeeeeeeeeteeeeeees 97 99 Instruction oooocccccccacananancncnnnnnnnonononnnnnnnnnnnnnnnon 319 BranGh aenta tabla 39 Pipeline iS 38 TIMING RE 44 unseparable ccocccccocccccccnonnncncnanannnincnannnos 327 Interface CAN canalla 23 252 serial SYNC eerren 197 The External Bus Interface 134 Internal RAM eisein neniani ieaie deiei ia 29 Interrupt CAPCOM EE 231 Enable Disable ooooooooccccccncccccnnnnnccconnnnnnos 82 extemal ee eg Ee deeg 87 fast External issc cinien 89 Handling CAN nsee 258 Praia E 78 Processing cccccccccnnnonononnoncnnnncncnnnanannnns 73 76 Regis a ias 259 Response
449. rrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down its interrupt request flag T5IR or T6IR in register TxIC will be set Whenever a transition according to the selection in bit field Cl is detected at pin CAPIN interrupt request flag CRIR in register CRIC is set Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC service if the respective interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register for each of the two timers and for the CAPREL register T5IC FF66h B3h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSIR TSIE ILVL GLVL RW RW RW RW T6IC FF68h B4h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6IR T6IE ILVL GLVL RW RW RW RW CRIC FF6Ah B5h SFR Reset Value 00h 15 12 11 5 4 3 2 1 0 14 13 10 9 8 7 6 LIT O E CA CS am RW RW RW RW Note Please refer to Interrupt Control Registers for explanation of the control fields ky 183 340 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL 11 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the ST10F269 and other microcontrollers micropro cessors or external perip
450. rter of the ST10F269 supports four different conversion modes Standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention For the Auto Scan mode the analog levels on a pre specified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the number of pre specified channels is repeatedly sampled and converted In addition the conversion of a specific channel can be inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without the overhead of interrupt routines for each data transfer ky 23 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL 2 6 Protected bits The ST10F269 MCU provide 106 protected bits These bits are modified by the on chip hardware during special events like power on reset power failure application hardware etc These bits cannot be modified by some wrong software accesses Table 2 Protected bit Note 106 protected bit 24 340 Register Bit Name Notes T2IC T3IC T4IC T2IR T3IR T
451. ruction which allows locking 1 4 instructions to an inseparable code sequence during which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem ky 325 340 SYSTEM PROGRAMMING ST10F269 USER S MANUAL The interrupt inhibit caused by an ATOMIC instruction gets active immediately and no other instruction will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense example MUL is one instruction Any instruction type can be used within an inseparable code sequence EXAMPLE ATOMIC 3 The following 3 instructions are locked No NOP required MOV RO 1234H Instruction 1 no other instr enters the pipeline MOV R1 5678H Instruction 2 MUL RO R1 Instruction 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the scope of the ATOMIC instruction sequence 23 9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16 Kbytes data page and a 14 bit offset within this data page The four DPPs allow immediate access to up
452. rupt 3 CC11IR CC11IE CC11INT 00 006Ch 1Bh 27 278 340 ky ST10F269 USER S MANUAL SYSTEM RESET 20 SYSTEM RESET Table 49 Reset event definition Reset Source Short cut Conditions Power on reset PONR Power on Long Hardware reset asynchronous reset LHWR t rstin gt 1032 TCL Short Hardware reset synchronous reset SHWR 4 TCL lt tprstin lt 1032 TCL Watchdog Timer reset WDTR WDT overflow Software reset SWR SRST execution System reset initializes the MCU in a predefined state There are five ways to activate a reset state The system start up configuration is different for each case as shown in Table 49 20 1 Asynchronous Reset Long Hardware Reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level Then the MCU is immediately forced in reset default state It pulls low RSTOUT pin it cancels pending internal hold states if any it waits for any internal access cycles to finish it aborts external bus cycle it switches buses data address and control signals and I O pin drivers to high impedance it pulls high PORTO pins and the reset sequence starts Power on reset The asynchronous reset must be used during the power on of the MCU Depending on crystal frequency the on chip oscillator needs about 10ms to 50ms to stabilize The logic of the MCU does not need a stabilized clock signal to detect an asynchronous reset so it is suitable for power on conditions
453. rvicing the watchdog timer and the next overflow can therefore be determined by the following formula 2 1 WDTIN x 6 x 216 S WDTREL x 28 PwprT fcpu Refer to the device datasheet for a table of watchdog timer ranges For security you are advised to rewrite WDTCON each time before the watchdog timer is serviced The Table 39 shows the watchdog time range for 40 MHz CPU clock Table 39 WDTREL Reload Value Prescaler for fcpy 40MHz Reload value in WDTREL 2 WDTIN 0 128 WDTIN 1 FFh 12 8us 819 2ms 00h 3 276ms 209 7ms 208 340 ky ST10F269 USER S MANUAL BOOTSTRAP LOADER 14 BOOTSTRAP LOADER The built in bootstrap loader of the ST10F269 provides a mechanism to load the startup program through the serial interface after reset In this case no external or internal Flash Memory is required for the initialization code starting at location 00 0000h The bootstrap loader moves code data into the internal RAM but can also transfer data via the serial interface into an external RAM using a second level loader routine Flash Memory internal or external is not necessary but it may be used to provide lookup tables or core code like a set of general purpose subroutines for I O operations number crunching system initialization etc see Figure 106 The bootstrap loader can be used to load the complete application software into ROMless systems to load temporary software into
454. ry Address are hexadecimal values 1 The upper 256 bytes of SFR area ESFR area and internal RAM are bit addressable 2 Read or write access in reserved locations may cause unexpected behaviour Code accesses are always made on even byte addresses The highest possible code storage location in the internal RAM is either 00 FDFEh for single word instructions or 00 FDFCh for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal RAM to the SFR area is not supported and can causes erroneous results Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the internal RAM is 0O0 FDFEh For PEC data transfers the internal RAM can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The upper 256 bytes of the internal RAM 00 FDOOh through 00 FDFFh and the GPRs of the current bank are provided for single bit storage and therefore they are bit addressable see Figure 6 a 28 340 ST10F269 USER S MANUAL MEMORY ORGANIZATION 3 2 1 System Stack The system stack may be defined within the internal RAM The size of the system stack is controlled by bit field STKSZ in the SYSCON
455. s However the power down mode circuitry uses them as level sensitive inputs An EXxIN x 3 0 Interrupt Enable bit bit CCxIE in respective CCxIC register need not to be set to bring the device out of power down mode An external RC circuit must be connected as shown Figure 158 To exit Power Down mode with external interrupt an EXxIN pin has to be asserted for at least 40 ns x 7 0 ky 295 340 POWER REDUCTION MODES ST10F269 USER S MANUAL This signal enables the internal oscillator and PLL circuitry and also turns on the weak pull down see Figure 159 The discharging of the external capacitor provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and peripheral clocks are enabled When the RPD voltage drops below the threshold voltage about 2 5 V the Schmitt trigger clears Q2 flip flop therefore enabling the CPU and peripheral clocks the device resumes code execution If the Interrupt was enabled bit CCxIE 1 in the respective CCxIC register before entering Power Down mode the device executes the interrupt service routine and then resumes execution after the PWRDN instruction see note below If the interrupt was disabled the device executes the instruction following PWRDN instruction and the Interrupt Request Flag bit CCxIR in the respective CCxIC register remains set until it is cleared by software Note Due to internal pipeline the instruction that foll
456. s chapter for more details of the control fields ky 229 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL Table 42 CAPCOM unit interrupt control register addresses CAPCOM1 Unit CAPCOM2 Unit Register Address Register Space Register Address Register Space CCOIC FF78h BCh SFR CC16IC F160h BOh ESFR CC1IC FF7Ah BDh SFR CC17IC F162h Bih ESFR CC2IC FF7Ch BER SFR CC18IC F164h B2h ESFR CC3IC FF7Eh BER SFR CC19IC F166h B3h ESFR CC4IC FF80h COh SFR CC20IC F168h B4h ESFR CC5IC FF82h Cth SFR CC21IC F16Ah B5h ESFR CC6IC FF84h C2h SFR CC22IC F16Ch B6h ESFR CC7IC FF86h C3h SFR CC23IC F16Eh B7h ESFR CC8iC FF88h C4h SFR CC24IC F170h B8h ESFR CCgIC FF8Ah C5h SFR CC25IC F172h B9h ESFR CC10IC FF8Ch C6h SFR CC26IC F174h BAh ESFR CC11IC FF8Eh C7h SFR CC27IC F176h BBh ESFR CC12IC FF90h C8h SFR CC28IC F178h BCh ESFR CC13IC FF92h C9h SFR CC29IC F184h C2h ESFR CC14IC FF94h CAh SFR CC30IC F18Ch C6h ESFR CC15IC FF96h CBh SFR CC31IC F194h CAh ESFR 230 340 ky ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE 16 PULSE WIDTH MODULATION MODULE The Pulse Width Modulation PWM Module of the ST10F269 generates up to 4 independent PWM signals The minimum PWM signal frequency depends on the width 16 bits and the resolution CLK 1 or CLK 64 of the PWM timers The maximum PWM signal frequency assumes that the PWM output signal changes with every c
457. s with the contents of the DDP register selected by the upper two bits of the 16 bit address The content of the selected DPP register specifies one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 20 18 bit address In case of non segmented memory mode only the two least significant bit of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected because otherwise unexpected results could occur In case of the segmented memory mode the selected number of segment address bit 9 2 5 2 or 3 2 of the respective DPP register is output on the segment address pins A23 A19 A17 A16 of Port4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR 50 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register Figure 15 Addressing via the data page pointers Data Pages 16 bit Data Address 15 14 13 0 DPP Registers v 9 142 0 v v DPP register concatenated with 14 bit Intra Page Address gives 24 bit address After reset or with segmentation disab
458. s are selected by the value FFh in bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01h to 00h after a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 00h the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows to choose if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine Note PEC transfers are only executed if their priority level is higher than the CPU level for example only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different chan nels Otherwise only one transfer will be performed for all simultaneous requests When COUNT is decremented to 00h and the CPU is to be interrupted an incorrect interrupt vector will be generated DI 79 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL The source and destination pointers specify the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the ST10F269 just below the bit addressable area see Figure 22 Figur
459. s data via serial inter face ASCO If single chip mode is selected during reset the first instruction is fetched from the internal Flash Otherwise it is fetched from external memory When internal Flash access is enabled after reset in single chip mode Bit ROMEN 1 in register SYSCON the software initialization routine may enable and configure the external bus interface before the execution of the EINIT instruction When external access is enabled after reset it may be desirable to reconfigure the external bus characteristics because the SYSCON register is initialized during reset to the slowest possible memory configuration To decrease the number of instructions required to initialize the ST10F269 each peripheral is programmed to a default configuration upon reset but is disabled from operation These default configurations can be found in the descriptions of the individual peripherals During the software design phase portions of the internal memory space must be assigned to register banks and system stack When initializing the stack pointer SP and the context pointer CP it must be ensured that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completion of the internal reset and should remain disabled until the SP is initialized Note Traps NMI may occur even though the interrupt system is still disabled In addition the stack overf
460. s lines on Port4 which extend the 16 bit address output on PORTO or PORT1 and so increase the accessible address space The number of segment address lines is selected during reset and coded in bit field SALSEL in register RPOH see table below SALSEL Segment address lines Directly accessible address space 11 Two A17 A16 256 Kbytes Default without pull downs 10 Eight A23 A16 16 Mbytes Maximum 01 None 64 Kbytes Minimum 00 Four A19 A16 1 Mbyte Note The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals 9 2 7 CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port6 which allows to directly select external peripherals or memory banks without requiring an external decoder The number of CS lines is selected during reset and coded in bit field CSSEL in register RPOH see table below CSSEL Chip Select Lines Note 11 Five CS4 CSO Default without pull downs 10 None Port6 pins free for I O 01 Two CS1 CSO 00 Three CS2 CSO The CS outputs are associated with the BUSCONx registers and are driven active low for any access within the address area defined for the respective BUSCON register 138 340 OI ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE For any access outside this defined address area the respective CS signal will go inactive h
461. s on 3 levels 7 3 6 5 Interrupt Class 3 6 sources on 2 levels 4 3 2 1 0 O ene 6 4 Saving the Status During Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with the location where the execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON control how the return location is stored The system stack receives the PSW first followed by the IP unsegmentea or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled ky 81 340 INTERRUPT AND TRAP FUNCTIONS ST10F269 USER S MANUAL The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning
462. s the alternate function CS is selected automatically in this case Note The open drain output option can only be selected via software earliest during the initialization routine at least signal CSO will be in push pull output driver mode directly after reset see Figure 45 The bus arbitration signals HOLD HLDA and BREQ are selected with bit HLDEN in register PSW When the bus arbitration signals are enabled via HLDEN also these pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BREQ are automatically enabled while the pin driver for HOLD is automatically disabled see Figure 46 DI 121 340 PARALLEL PORTS ST10F269 USER S MANUAL Figure 45 Block diagram of Port6 pins Write ODP6 y Open Drain Latch Read ODP6 y Write DP6 y Direction Latch Read DP6 y o 3 a E oO 2 Alternate Function e Enable Write P6 y Alternate Data Output Port Output Output Buffer Read P6 y y 0 4 6 7 a 122 340 ST10F269 USER S MANUAL PARALLEL PORTS Figure 46 Block diagram of P6 5 pin HOLD Write ODP6 5 Open Drain Latch Read ODP6 5 Write DP6 5 Direction Latch Read DP6 5 di Write P6 5 Port Output Latch Read P6 5 El Alternate Data Input Internal Bus Pesmo P6 5 HOLD Outpu
463. s the conversions if the CPU or PEC cannot keep track with the conversion rate Figure 131 Wait for read mode example Conversion 3 2 1 0 3 of Channel Write ADDAT ADDAT Full Temp Latch Full Hold Result in Generate Interrupt Temp Latch Request Read of ADDAT Ao ASA H PE A Result of Channel x 3 2 1 0 17 1 4 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection mode is enabled by setting bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1 The channel to be converted in this mode is specified in bit field CHNR of register ADDAT2 These 4 bits in ADDAT2 are not modified by the A D converter but only the ADRES bit field Since the channel number for an injected conversion is not buffered bit field CHNR of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number with no injected conversion running see Figure 132 A channel injection can be triggered in two ways Setting the Channel Injection Request bit ADCRQ via software a compare or a capture event of Capture
464. s the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in Chapter 23 System Programming 4 4 10 The Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each operation which pops data from the system stack POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Since the least significant bit of register STKUN is tied to 0 and bit 15 through 12 are tied to 1 by hardware the STKUN register
465. se it is 4 CPU clock cycles 20 2 Synchronous Reset Warm Reset A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level In order to properly activate the internal reset logic of the MCU the RSTIN pin must be held low at least during 4 TCL 2 periods of CPU clock The I O pins are set to high impedance and RSTOUT pin is driven low After RSTIN level is detected a short duration of 12 TCL approximately 6 periods of CPU clock elapes during which pending internal hold states are cancelled and the current internal access cycle if any is completed External bus cycle is aborted The internal pull down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software This bit is always cleared on power on or after a reset sequence 280 340 ky ST10F269 USER S MANUAL SYSTEM RESET Exit of synchronous reset state The internal reset sequence starts for 1024 TCL 512 periods of CPU clock and RSTIN pin level is sampled The reset sequence is extended until RSTIN level becomes high Then the MCU restarts The system configuration is latched from PORTO and ALE RD and WR WRL pins are driven to their inactive level The MCU starts program execution from memory location 00 0000h in code segment 0 This starting location will typically point to the general initialization routine Timing of synchronous reset sequence are summarized in Figure 152 and Figure 153 Figure 152 S
466. see Figures 151 152 and 153 To avoid unexpected behavior the level of the PORTO configuration input pins should not change while PORTO is transparent Table 50 Por latched configuration for the different resets X Pin is sampled Pin is not sampled Reserved BSL Reserved Emu Mode WR config Reserved Clock Options Segm Addr Lines Chip Selects Adapt Mode Sample event 1 x POH 1 x x x gt lt POH 0 x POL 6 POL 5 Software Reset x gt lt P0H 3 x x gt lt x POH 2 Watchdog Reset X Short Hardware Reset X X X Long Hardware Reset X X X X X X X Power On Reset xX X X xX xX X X xX X X xX xX xX X Porto BIC h7 h6 h5 h4 h h2 mt ho np 16 15 4 13 12 n 10 Port0 Bit CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU Name SYSCON x1 x x1 x1 x1 xt xt xt WRCFG vi x x1 x x yd Tag RPOH CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSCONO BUS ALE BUSTYP BUSTYP Internal To Clock Generator To Port4 Logic To Port6 Logic a S Internal Internal Internal Logic Notes 1 Not latched from Porto 2 Bit set if EA pin is 1 3 Only the RPOH low byte is used and the CLKCFG bit field is latched from PortO high byte to RPOH low byte 288 340 ky ST10F269 USER S MANUAL
467. selected the alternate function of Port4 may be necessary to access for external memory directly after reset For this reason Port4 will be switched to this alternate function automatically The number of segment address lines is selected via PORTO during reset The selected value can be read from bit field SALSEL in register RPOH read only in order to check the configuration during run time The CAN interfaces use 2 or 4 pins of Port4 to interface the CAN modules to the external CAN transceiver In this case the number of possible segment address lines is reduced ky 113 340 PARALLEL PORTS ST10F269 USER S MANUAL The Table 21 summarizes the alternate functions of Port4 depending on the number of selected segment address lines coded via bit field SALSEL Table 21 Port4 alternate functions Port 4 P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P4 6 P4 7 114 340 Standard Function SALSEL 01 64 Kbytes GPIO GPIO GPIO GPIO GPIO CAN2_RxD GPIO CAN1_RxD GPIO CAN1_TxD GPIO CAN2_TxD Alternate Function SALSEL 11 256 Kbytes Segment Address A16 Segment Address A17 GPIO GPIO GPIO CAN2_RxD GPIO CAN1_RxD GPIO CAN1_TxD GPIO CAN2_TxD Figure 38 Port4 I O and alternate functions Alternate Functions gt lt gt P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Port4 General Purpose Input Output Segment Address Lines Alternate Function SALSEL 00 1 Mbyte Segment Address A16 Se
468. seo TO a LT lt ky 137 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL Transfer Rate Bus Mode Speed factor for byte word Dword access System Requirements Free I O Lines 8 bit multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L 8 bit de multiplexed Low 1 2 4 Very low no latch byte bus POH 16 bit multiplexed High 1 5 1 5 3 High 16 bit latch word bus P1H PiL 16 bit de multiplexed Very high 1 1 2 Low no latch word bus Note PORT1 gets available for general purpose I O when none of the BUSCON registers selects a de multiplexed bus mode 9 2 5 Disable Enable Control for Pin BHE BYTDIS Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise it is disabled and the pin can be used as standard I O pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the ST10F269 via a word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and the BHE signal is not used 9 2 6 Segment Address Generation During external accesses the EBC generates a programmable number of addres
469. separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions A 10 Kbyte 16 bit wide on chip XRAM provides fast access to user data variables user stacks and code The on chip XRAM is an X Peripheral and appears to the software as an external RAM Therefore it cannot store register banks and is not bit addressable The XRAM allows 16 bit accesses with maximum speed A 256 Kbyte internal Flash provides for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one instruction cycle Program execution from the on chip Flash is the fastest of all possible alternatives For Special Function Registers 1024 bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Register area ESFR uses the other 512 bytes E SFRs are word wide registers which are used for controlling and monitoring functions of the different on chip units Unused ESFR addresses are reserved for future members of the ST10F269 family 2 3 3 External Bus
470. sequence synchronous asynchronous hardware software and watchdog timer resets At the end of the internal reset sequence the pull down is released and the RSTIN pin is sampled 8 TCL periods later If signal is sampled low a hardware reset is triggered again If it is sampled high the chip exits reset state according to the running reset way synchronous asyn chronous hardware software and watchdog timer resets Note The bidirectional reset function is disabled by any reset sequence Bit BDRSTEN of SYSCON is cleared To be activated again it must be enabled during the initialization routine 20 6 Reset Circuitry The internal reset circuitry is described in Figure 154 An internal pull up resistor is implemented on RSTIN pin 50kQ minimum to 250kQ maximum The minimum reset time must be calculated using the lowest value In addition a programmable pull down bit BDRSTEN of SYSCON register drives the RSTIN pin according to the internal reset state as explained in Section 20 5 RSTOUT Pin and Bidirectional Reset The RSTOUT pin provides a signals to the application as described in Section 20 5 A weak internal pull down is connected to the RPD pin to discharge external capacitor to Vss at a rate of 100uA to 20014 This Pull down is turned on when RSTIN pin is low If bit PWDCFG of SYSCON register is set an internal pull up resistor is activated at the end of the reset sequence This pull up charges the capacitor conne
471. sing with address pointer post modification Double indirect addressing requires two pointers Any GPR can be used for one pointer the other pointer is provided by one of two specific SFRs IDXO and IDX1 Two pairs of offset registers QRO QR1 and QX0 QX1 are associated with each pointer GPR or IDX The GPR pointer allows access to the entire memory space but IDX are limited to the internal Dual Port RAM except for the CoMOV instruction 60 340 ky ST10F269 USER S MANUAL MULTIPLY ACCUMULATE UNIT MAC The following table shows the various combinations of pointer post modification for each of these 2 new addressing modes In this document the symbols Rw and IDX refer to these addressing modes Table 7 Pointer post modification combinations for IDXi and Rwn Symbol Mnemonic Address Pointer Operation IDX 8 stands for IDXi IDX lt IDX no op IDX IDX IDX 2 i 0 1 IDX IDX lt IDX 2 i 0 1 IDX QXj IDX lt IDX IO i j 0 1 IDX QXj IDX lt IDXj Qxj i j 0 1 Rw 97 stands for Rwn Rwn lt Rwn no op Rwn Rwn Rwn 2 n 0 15 Rwn Rwn Rwn 2 k 0 15 Rwn QRj Rwn Rwn QR n 0 15 j 0 1 Rwn QRJj Rwn Rwn QR n 0 15 j 0 1 For the CoMACM class of instruction Parallel Data Move mechanism is implemented This class of instruction is only available wit
472. smitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism to distinguish address from data byte has been included 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or receives byte 8 bit synchronously to a shift clock which is generated by the ASCO The SSC transmits or receives characters of 2 16 bit length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB while the ASCO always shifts the LSB first A loop back option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bit An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete 2 5 6 The on chip CAN Modules The integrated CAN Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active The on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bi
473. sponding to bank 1 register CCx is toggled The generated interrupt always corresponds to the register that caused the match Note If a match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in double register compare mode this port pin must be configured as output and the corresponding direction control bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1 Figure 119 Double register compare mode block diagram Interrupt Request CCMODx Compare Register CCx Mode 1 Comparator Input CAPCOM Timer Ty interrupt Request YN NA Comparator ant CCxIO Mode 0 Compare Register CCz CCMODz Interrupt Request x 23 16 7 0 y 0 1 7 8 z 31 24 15 8 In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to one of the two timers of the respective CAPCOM unit In the timing example for this compare mode below the compare values in registers CCx and CCz are not modified 228 340 ky ST10F269 USER S MANUAL THE CAPTURE COMPARE UNITS The pins CCzlO whi
474. ss Control IP CSP Data Paging Control DPP0 DPP1 DPP2 DPP3 GPRs Access Control CP System Stack Access Control SP STKUN STKOV DI 35 340 THE CENTRAL PROCESSING UNIT CPU ST10F269 USER S MANUAL Multiply and Divide Support MDL MDH MDC ALU Constants Support ZEROS ONES Figure 9 CPU block diagram 2 Kbyte Internal RAM MDL Multiplication 256 Kbyte Division Hardware of Flash Memory Bit Mask _ General Generator Purpose Execution Unit Registers Instruction Pointer BS 4 Stage Pipeline 16 bit PSW Barrel Shift SYSCON CP BUSCON 0 BUSCON 1 ADDRSEL 1 10 Kbyte BUSCON 2 ADDRSEL 2 XRAM BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Code Segment Pointers Pointer 4 1 Instruction Pipelines The instruction pipeline breaks down CPU processing into the four following stages Fetch An instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal memory internal RAM or external memory Decode Instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions which implicitly access the system stack the SP register is either decremented or incremented
475. ssible within both register blocks via short 2 4 or 8 bit addresses without switching Example EXTR 4 Switch to ESFR area for the next 4 instructions MOV ODP2 fdatal6 ODP2 uses 8 Bit reg addressing BFLDL DP6 data8 Bit addressing for Bit fields mask BSET DP1h 7 Bit addressing for single Bit MOV T8REL R1 T8REL uses 16 Bit address R1 is duplicated and also accessible via the ESFR mode EXTR is not required for this access dee AA The scope of the EXTR 4 instruction ends here MOV T8REL R1 T8REL uses 16 Bit address R1 is duplicated and does not require switching ky 31 340 MEMORY ORGANIZATION ST10F269 USER S MANUAL In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are required for initialization and mode selection Wherever possible registers that need to be accessed frequently are allocated in the standard SFR area Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions 3 3 The On chip XRAM The 10 Kbytes of on chip extension RAM single port XRAM is provided as a storage for data user stack and code lt is located within data page 3 The XRAM is divided into 2 areas the first 2 Kbytes named XRAM1 and the second 8 Kbytes named XRAM2 connected to the internal XBUS and are accessed like an external memory in 16 bit de multiplex
476. stem Cyclic time based interrupt provides Port 2 external interrupts every RTC basic clock tick and every n RTC basic clock tick n is programmable if enabled 58 bit timer for long term measurement Capable to exit the ST10 chip from power down mode if PWDCFG of SYSCON set after a programmed delay The real time clock is base on two main blocks of counters The first block is a prescaler which generates a basic reference clock for example a 1 second period This basic reference clock is coming out of a 20 bit DIVIDER 4 bit MSB RTCDH counter and 16 bit LSB RTCDL counter This 20 bit counter is driven by an input clock derivated from the on chip oscillator clock XTAL1 input predivided by a 1 64 fixed counter see Figure 148 This 20 bit counter is loaded at each basic reference clock period with the value of the 20 bit PRESCALER register 4 bit MSB RTCPH register and 16 bit LSB RTCPL register The value of the 20 bit RTCP register determines the period of the basic reference clock A timed interrupt request RTCSI may be sent on each basic reference clock period The second block of the RTC is a 32 bit counter 16 bit RTCH and 16 bit RTCL This counter may be initialized with the current system time RTCH RTCL counter is driven with the basic reference clock signal In order to provide an alarm function the contents of RTCH RTCL counter is compared with a 32 bit alarm register 16 bit RTCAH register and 16 bit RTCAL regi
477. ster The alarm register may be loaded with a reference date An alarm interrupt request RTCAI may be generated when the value of RTCH RTCL counter matches the reference date of RTCAH RTCAL register The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake up the ST10 chip when running power down mode Using the RTCOFF bit of RTCCON register the user may switch off the clock oscillator when entering the power down mode Figure 147 ESFRs and port pins associated with the RTC EXISEL CCxIC eae a Bin SRY YEO es ce WW Y Y YY YY EXISEL External Interrupt Source Selection register Port 2 1 second timed interrupt request RTCSI triggers firq 2 and alarm interrupt request RTCAI triggers firq 3 RTC data and control registers are implemented onto the XBUS ky 273 340 REAL TIME CLOCK ST10F269 USER S MANUAL Figure 148 RTC block diagram RTCAI RTCSI Clock Oscillator V Programmable ALARM Register Basic Clock IT RTCAH RTCAL Programmable PRESCALER Register RTCPH RTCPL AlarmIT RTCDH RTCDL 32 bit COUNTER 20 bit DIVIDER 19 1 RTC registers 19 1 1 RTCCON RTC Control Register The functions of the RTC are controlled by the RTCCON control register If the RTOFF bit is set the RTC dividers and counters clock is disabled and registers can be written when the S
478. stopped by hardware By setting the period PPx the timer start value PTx and the pulse width value PWx appropriately the pulse width tw and the optional pulse delay td may be varied in a wide range see Figure 126 16 2 PWM Module Registers The PWM module is controlled via two sets of registers The waveforms are selected by the channel specific registers PTx timer PPx period and PWx pulse width Three common registers control the operating modes and the general functions PWMCONO and PWMCON1 of the PWM module as well as the interrupt behavior PWMIC Up down Counters PTx Each counter PTx of a PWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64 Bit PTIx in register PWMCONDO selects the respective clock source A PWM counter counts up or down controlled by hardware while its respective run control bit PTRx is set A timer is started PTRx 1 via software and is stopped PTRx 0 either via hardware or software depending on its operating mode Control bit PTRx enables or disables the clock input of counter PTx rather than controlling the PWM output signal Table 43 summarizes the PWM frequencies that result from various combinations of operating mode counter resolution input clock and pulse width resolution Period Registers PPx The 16 bit period register PPx of a PWM channel determines the period of a PWM cycle and the frequency of the PWM signal This registe
479. sures an inactive high level on the WR WRL output READY READY Ready Input receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle provided that this function is enabled for the current bus cycle READY READY may be used as synchronous READY READY or may be evaluated asynchro nously For the ST10F269 the polarity can be set to READY or READY by setting bit 13 in the BUSCON register EA External Access Enable determines if the ST10F269 after reset starts fetching code from the internal Memory area EA 1 or via the external bus interface EA 0 NMI Non Maskable Interrupt Input allows to trigger a high priority trap via an external signal It can be used as power fail input or to validate the PWRDN instruction that switches the ST10F269 into power down mode RSTIN Reset Input puts the ST10F269 into the reset default configuration either at power up or external events like a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input RSTOUT Reset Output provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to ini tia
480. switched off The text has been removed Section 2 4 4 Oscillator Watchdog OWD row 17 The PLL runs on its basic frequency of 2 to 10 MHz instead of 5 MHz Page 24 Figure 4 banks have been removed note is updated accordingly with blocks Page 27 Figure 6 banks have been removed note is updated accordingly with blocks Page 43 Description of SYSCON register XPEN bit O Accesses to the on chip X Peripherals and XRAM are disabled 1 The on chip X Peripherals are enabled The text has been added modified Page 52 Row 9 For some instructions via short 2 bit GPR addresses sentences are put in bold Page 58 Row 29 The working register of the MAC tasks and interrupts text has been added page 59 Section 5 2 2 Particular Pipeline Effects with the MAC Unit with 3 examples has been added Page 62 and 63 Section 5 2 6 text has been completed Section 5 2 7 table 9 has been updated and notes added Section 5 2 8 text has been completed Page 86 Table 17 the footnote is removed the class A hardware traps are detailed in page 88 Page 89 Row 8 highest priority followed by the stack overflow trap and the stack underflow trap has the lowest priority the text has been completed Page 94 Description of Picon bit 4 is added P4LIN Page 204 Bits PONR LHWR SHWR SWR are added to WDTCON description Page 205 Row 1 from the value WDTREL x 28 The 28 factor has been corrected Note The reset value will be
481. t identifiers The module provides Full CAN functionality on up to 15 message objects Message object 15 may be configured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1M Baud The CAN Module uses two pins to interface to a bus transceiver 2 5 7 General Purpose Timer GPT Unit The GPT unit is a flexible multifunctional timer counter structure which may be used for time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The five 16 bit timers are organized into two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenated with another timer of the same module SZA 21 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL Each timer can be configured individually for one of three basic modes of operation which are Timer Gated Timer and Counter Mode In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a tim
482. t instruction or CoSTORE lt destination gt lt MAS gt instruction gives the same result 2 If data limiter is activated a read with CoSTORE lt destination gt lt MAH gt instruction or CoS TORE lt destination gt lt MAS gt instruction gives different results MAS gives the saturated value of MAH The reading of MAL and MSW MAE are not saturated 5 2 8 The Accumulator Shifter The accumulator shifter is a parallel shifter with a 40 bit input and a 40 bit output The source accumulator shifting operation are No shift Unmodified Up to 8 bit Arithmetic Left Shift Up to 8 bit Arithmetic Right Shift Notice that MSW ME MSW MSV and MSW MSL bits See MSW register description are affected by left shifts therefore if the saturation detection is enabled MCW MS bit is set the behavior is similar to the one of the Adder Subtracter Some precautions are required in case of left shift with enabled saturation If MSW MAE bit field most significant byte of the 40 bit Signed Accumulator contains significant bits then the 32 bit value in the accumulator is generally saturated However it is possible that a left shift may move out of the Accumulator some significant bits The 40 bit result will be misinterpreted and will be either not saturated or saturated wrong There is a chance that the result of a left shift may produce a result which can saturate an original positive number to the minimum negative value or vice
483. t NA Buffer Clock 7 9 Port7 If this 8 bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP7 Each port line can be switched into push pull or open drain mode via the open drain control register ODP7 P7 FFDOh E8h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function P7 y Port data register P7 bit y ky 123 340 PARALLEL PORTS ST10F269 USER S MANUAL DP7 FFD2h E9h SFR Reset Value OOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 be7 7 oe7 6 0P75 op7 4 DP7 3 DP7 2 DP7 1 DP7 0 RW RW RW RW RW RW RW RW Bit Function DP7 y Port direction register DP7 bit y DP7 y 0 Port line P7 y is an input high impedance DP7 y 1 Port line P7 y is an output ODP7 F1D2h E9h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Bit Function ODP7 y Port7 Open Drain control register bit y ODP7 y 0 Port line P7 y output driver in push pull mode ODP7 y 1 Port line P7 y output driver in open drain mode 7 9 1 Alternate Functions of Port7 The upper 4 lines of Port7 P7 7 P7 4 are used as capture inputs or compare outputs CC3110 CC 2810 for the CAPCOM2 unit How CAPCOM2 unit is connected to Port7 lines and how to handle them by software is sim
484. t Timing Control The position of the CS lines can be changed By default after reset the CS lines change half a CPU clock cycle after the rising edge of ALE With the CSCFG bit set in the SYSCON register the CS lines change with the rising edge of ALE therefore the CS lines change at the same time that the address lines are changed Figure 63 Chip select delay Normal De multiplexed ALE Lengthen De multiplexed Bus Cycle Bus Cycle Address P1 Segment P4 ALE Normal CS Early cs cx CH EACH ES z A be lt Read Write Read Write lt gt gt Delay Delay 146 340 AT ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE 9 4 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features like the usage of interface pins WR BHE segmentation and internal Memory mapping are controlled by the SYSCON register The properties of a bus cycle like chip select mode usage of READY length of ALE external bus mode read write delay and wait states are controlled by BUSCON4 BUSCONO registers Four of these registers BUSCON4 BUSCON1 have an associated address select register ADDRSEL4 ADDRSEL1 which allows to specify up to four address areas and the individual bus characteristics within these areas All accesses that are not covered by these four areas are then controlled via BUSCONO This allows to use memory components or peripherals with
485. t multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division register MDL represents the 16 bit quotient MDL FEOEh 07h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDL RW MDL Specifies the low order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in Chapter 23 System Programming 4 4 13 The Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information fo
486. t value of the internal threshold of the detection circuit Table 38 WDTCON Bits Value on Different Resets Reset Source SWR WDTR Power On Reset Power on after partial supply failure Long Hardware Reset Short Hardware Reset Software Reset Watchdog Reset Notes 1 PONR bit may not be set for short supply failure 2 For power on reset and reset after supply partial failure asynchronous reset must be used In case of bi directional reset is enabled and if the RSTIN pin is latched low after the end of the internal reset sequence then a Short hardware reset a software reset or a watchdog reset will trigger a Long hardware reset Thus Reset Indications flags will be set to indicate a Long Hardware Reset The Watchdog Timer is 16 bit clocked with the system clock divided by 2 or 128 The high byte of the watchdog timer register can be set to a pre specified reload value stored in WDTREL Each time it is serviced by the application software the high byte of the watchdog timer is reloaded For security rewrite WDTCON each time before the watchdog timer is serviced The time period for an overflow of the watchdog timer is programmable in two ways The input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fcpy 2 or tcp uy 128 The reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pwpr between se
487. tacksize etc must be selected before the execution of EINIT ky 287 340 SYSTEM RESET ST10F269 USER S MANUAL 20 7 1 System Start up Configuration Although most programmable features are either selected during the initialization phase or repeatedly during program execution there are some features that must be selected earlier because they are used for the first access of the program execution for example internal or external start selected via EA These selections are made during reset by the pins of PORTO which are read at the end of the internal reset sequence During reset internal pull up devices are active on the PORTO lines so their input level is high if the respective pin is left open or is low or if the respective pin is connected to an external pull down device With the coding of the selections as shown below in many cases the default option high level can be used The value on the upper byte of PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the ST10F269 Not all Pom bits are latched after the end of an internal reset Depending on the reset type different bits are latched When RSTIN goes active the PORTO configuration input pins are not transparent for the first 1024 TCL After that time only the PORTO pins are transparent and will be latched when internal reset signal becomes inactive
488. tching ADDRSELx register As the XRAM appears like external memory it cannot be used as system stack or as register banks The XRAM is not provided for single bit storage and therefore is not bit addressable The respective location must contain a branch instruction unconditional because sequential boundary crossing from XRAM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for XRAM operands Any word data access is made to an even byte address The highest possible word data storage location in the XRAM is 00 E7FEh For PEC data transfers the XRAM can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The on chip XRAM is accessed without any wait states using 16 bit de multiplexed bus cycles which takes one instruction cycle Even if the XRAM is used as external memory it does not occupy BUSCONx ADDRSELx registers but is selected via additional dedicated XBCON XADRS registers These registers are mask programmed and are not user accessible With these registers the address area 00 E000h to 00 E7FFh is reserved for XRAM accesses 3 3 1 XRAM Access Via External Masters When bit XPER SHARE in register SYSCON is set the on chip XRAM of the ST10F269 can be accessed by an external master during hold mode via the ST10F269 s bus interface Th
489. te error SSCMS SSC Master Select bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable bit 0 Transmission and reception disabled Access to control bits a 197 340 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL SSCCON FFB2h D9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC z S SSCBC EN 1 MS BSY BE PE RE TE RW RW RW RW RW RW RW R Bit Function Operating Mode SSCEN 1 SSCBC SSC bit Count Field Shift counter is updated with every shifted bit Do not write to SSCTE SSC Transmit Error Flag 1 Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag 1 Reception completed before the receive buffer was read SSCPE SSC Phase Error Flag 1 Received data changes around sampling clock edge SSCBE SSC Baud rate Error Flag 1 More than factor 2 or 0 5 between Slave s actual and expected Baud rate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable bit 1 Transmission and reception enabled Access to status flags and M S control Note The target of an access to SSCCON control bit or flags is determined by t
490. ten value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin 7 1 1 Open Drain Mode Some of I O Ports of ST10F269 provide Open Drain Control It is used to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the upper transistor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output enters a high impedance state The high level must then be provided by an external pull up device With this feature it is possible to connect several port pins together to a AND wired configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is implemented for ports P2 P3 P6 P7 and P8 see respective sections and is controlled through the respective Open Drain Control Registers ODPx These registers allow the individual bit wise selection of the open drain mode for each port line If the respective control bit ODPx y is 0 default after reset th
491. ter P6 Port 6 Data Register ADDRSELx Address Range Select Register 1 4 BUSCONx Bus Mode Control Register 0 4 Y Bitis linked to a function SYSCON System Control Register Bit has no function or is not implemented RPOH Port POH Reset Configuration Register E Register is in ESFR internal memory space a 133 340 THE EXTERNAL BUS INTERFACE ST10F269 USER S MANUAL 9 2 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 of BUSCONx register and configured bit field BTYP the ST10F269 uses a subset of its port lines together with some control lines to build the external bus BTYP Encoding External Data Bus Width External Address Bus Mode 00 8 bit Data De multiplexed Addresses 01 8 bit Data Multiplexed Addresses 10 16 bit Data De multiplexed Addresses 11 16 bit Data Multiplexed Addresses The bus configuration BTYP for the address windows BUSCON4 BUSCON1 is selected by software usually during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 Mbyte address space of the ST10F269 is divided into 256 segments of 64 Kbytes each The 16 bit intra segment address is output on PORTO for multiplexed bus modes or on PORT1 for de multiplexed bus modes When segme
492. ternal ROM has been changed to internal Flash in the text CCxIC CCIR bit has been put in Bold hardware modified 3rd row ALE RD and WR WRL instead of R W 3rd row ALE RD and WR WRL instead of R W Table 51 Note 3 on RPH has been added The reset value of SYSCON register has been changed from 0X00h to Oxx0Oh only some bits of the nibble are cleared at reset Title of Figure 156 Delay with RC on RPD pin instead of Vpp pin Table 56 BUSCONO reset value has been changed from OXX0h to 0xx0h and single byte registers changed from 0000h to 00h Table 56 single byte registers changed from 0000h to 00h Table 56 IDCHIP reset value has been changed from 10DXh to 10Dnh and n is the device revision text has been added single byte registers changed from 0000h to 00h b added MCW register as bit addressable Table 56 b added ONES register as bit addressable and single byte registers changed from 0000h to OOh Table 56 QRO QR1 QX0 QX1 word registers reset value changed from OOh to 0000h the reset value of SYSCON register has been changed from 0X00h to 0xx0h only some bits of the nibble are cleared at reset and single byte registers changed from 0000h to 00h Table 56 single byte registers changed from 0000h to 00h and foot notes 1 to 3 has been added ky REVISION HISTORY ST10F269 USER S MANUAL Page 307 Page 308 Page 310 Page 311 Page 312 Page 315 Page 333 Page 335 Table
493. ternal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism Specify the size of the physical system stack area within the internal RAM bit field STKSZ in register SYSCON ky 321 340 SYSTEM PROGRAMMING ST10F269 USER S MANUAL Define two pointers which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting
494. terrupt cccooccccnncccconaccninnccnnananinns Number Representation amp Rounding MAC REGISTER SET eee Address Registers AN Accumulator amp Control Registers MAC INSTRUCTION SET SUMMARY AAA INTERRUPT AND TRAP FUNCTIONS cooocccccocccccooccccoccccncanonanacnnnnn arc nnnnccn nan on nnnccnnano os INTERRUPT SYSTEM STRUCTURE Normal Interrupt Processing and PEC Service ooocnococinocccinacccnonnccnanncnnonnncnnnrnnn nana cnnnnos Interrupt System Register Description ST10F269 USER S MANUAL 6 1 3 Interrupt Control Registers A 77 6 1 4 Interrupt Priority Level and Group Level c cccceceeeeeeeseeeeeeeeeeseneeeeseeeeeeeaeeeseaeeeteas 78 6 1 5 Interrupt Control Functions in the PSW eccccecseeeeeeeeeeeneeeeeeeeeeeeeeeeeaeeseeaeeeseaeeeteas 79 6 2 OPERATION OF THE PEC CHANNELS o cececeeeeeeeeeeeeeeeeneeeceeeeeseaeeeseaeeeseaeeeeeneeeee 80 6 3 PRIORITIZING INTERRUPT 8 PEC SERVICE REQUESTS A 82 6 3 1 Enabling and Disabling Interrupt Requests AAA 82 6 3 2 Interrupt Class Management 82 6 4 SAVING THE STATUS DURING INTERRUPT SERVICE A 83 6 4 1 Context Switching cocida a a EZ 84 6 5 INTERRUPT RESPONSE TIMES cccececceeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeeaaeeeseaeesseaeeeseaeeessaas 84 6 5 1 PEC Response MT 86 6 6 EXTERNAL INTERRUPTS ee iia ia 87 6 6 1 Fast External Interrupts cursi rr Giants 89 6 7 TRAP FUNCTIONS o bid lili tioned chines 90 6 7 1 Software NET ici a aa eld deed ede 91 6 7 2 Hardware RT CEET
495. the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be accessed individually In this case the upper byte is selected with the BHE signal while the lower byte is selected with the AO signal So the two bytes of the memory can be enabled independent from each other or together when accessing words When writing byte to an external 16 bit device which has a single CS input but two WR enable inputs for the two bytes the EBC can directly generate these two write control signals This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL write low byte and pin BHE serves as WRH write high byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halves When reading byte from an external 16 bit device whole words may be read and the ST10F269 automatically selects the byte to be input and discards the other However care must be taken when reading devices that change state when being read like FIFOs interrupt status registers etc In this case individual byte should be selected using BHE and AO Figure 56 Switching from de multiplexed to multiplexed bus mode De multiplexed Multiplexed Bus Cycle e Idle State G Bus Cycle Adaress P ares X es O Segment P4 Address Address ALE e E ee E Se E A Bu
496. the PEC data transfer is started one cycle later 84 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS The minimum PEC response time is 3 CPU clock cycles This requires program execution from the internal Flash no external operand read requests and setting the interrupt request flag during the last CPU clock cycle of an instruction When the interrupt request flag is set during the first CPU clock cycle of an instruction the minimum PEC response time under these conditions is 4 CPU clock cycles The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 CPU clock cycle for each of these conditions When instruction N reads an operand from the internal Flash or when N is a CALL RETURN TRAP or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 CPU clock cycles during internal Flash program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 CPU clock cycles The worst case PEC response time during internal Flash program execution adds to 9 CPU clock cycles Any reference to external locations increases the PEC response time due to pipeline relat
497. the choice of a wide range of different types of memories and or peripherals Access to very slow memories or peripherals is supported via a particular Ready function For applications which require less than 64 Kbytes of address space a non segmented memory model can be selected where all locations can be addressed by 16 bit Port4 is not needed for the upper address bit A23 A19 A17 A16 as is the case when using the segmented memory model The on chip XBUS is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals The on chip XRAM and the on chip CAN Modules are examples for these X Peripherals 16 340 OI ST10F269 USER S MANUAL ARCHITECTURAL OVERVIEW 2 4 Clock Generator The on chip clock generator provides the ST10F269 with its basic clock signal that controls the activities of the controller hardware Its oscillator can run with an external crystal and appropriate oscillator circuitry see Chapter 8 Dedicated Pins or can be driven by an external oscillator The oscillator can directly feed the external clock signal to the controller hardware through buffers and divides the external clock frequency by 2 or feeds an on chip phase locked loop PLL which multiplies the input frequency by a selectable factor F The resulting internal clock signal is also re
498. the last bus access BHE Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions POH outputs the high byte of the last address if a multiplexed bus mode with 8 bit data bus is used otherwise POH is floating POL is always floating in Idle mode PORT1 outputs the lower 16 bits of the last address if a de multiplexed bus mode is used otherwise the output pins of PORT1 represent the port latch data PORT4 outputs the segment address for the last access on those pins that were selected during reset otherwise the output pins of Port4 represent the port latch data During power down mode the oscillator and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off The Table 53 summarizes the state of all ST10F269 output pins during Idle and Power Down mode Table 53 Output pin state during idle and powerdown modes Idle Mode Power Down Mode ST10F269 Output Pin s No External bus No External bus external bus enabled external bus enabled ALE Low Low Low RD
499. the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a de selection signal or command The slaves use open drain output on MRST This forms a AND wired connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave 200 340 ky ST10F269 USER S MANUAL HIGH SPEED SYNCHRONOUS SERIAL INTERFACE After performing all necessary initialization of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfe
500. the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register So in mode 1 this PWM value controls both edges of the output signal Note that in mode 1 the period of the PWM signal is twice the period of the timer PWM_Peri0dmode1 2 X PPx 1 234 340 ky ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE The Figure 124 illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register This mode is referred to as Center Aligned PWM because the value in the pulse width shadow register effects both edges of the output signal symmetrically Figure 124 Operation and output waveform in mode 1 PPx Period 7 PTx Count Value 2 7 0 0 PWx Pulse Duty Cycle Width 0 EE EE 4 100 Pwx 1 L_ LL LLL EMILE 87 5 pwx 2 ZE 7777 UNLU JJ 75 PWx 4 o V M 50 PWx 6 VII LY 25 PWx 7 V V 12 5 PWx 8 0 LSR Change Count LSR Latch Shadow Registers Direction Interrupt Reques Kn 235 340 PULSE WIDTH MODULATION MODULE ST10F269 USER S MANUAL 16 1 3 Burst Mode Burst mode is selected by setting bit PBO1 in register PWMCON1 to 1 This mode combines the signals from PWM channels 0 and 1 onto the port pin of channel 0 The ou
501. tion Module can generate up to four PWM output signals using edge aligned or centre aligned PWM In addition the PWM module can generate PWM burst signals and single shot outputs In Burst Mode two channels can be combined with their output signals ANDed where one channel gates the output signal of the other channel In Single Shot Mode a single output pulse is generated retriggerable under software control Each PWM channel is controlled by an up down counter with associated reload and compare registers The polarity of the PWM output signals may be controlled via the respective port output latch combination via EXOR 2 5 11 AID Converter A 10 bit A D converter with 16 multiplexed input channels and a sample and hold circuit has been inte grated on chip for analog signal measurement It uses a Successive approximation method The sample time for loading the capacitors and conversion time is programmable and can be modified for the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT When the result of a previous conversion has not been read from the result register at the time the next conversion is complete either an interrupt request is generated or the next conversion is suspended until the previous result has been read For applications which require less than 16 analog input channels the remaining channel inputs can be used as digital input port pins The A D conve
502. tion on RTCH or RTCL register loads directly the corresponding counter When reading the current value in the counter system date is returned The counters keeps on running while the clock oscillator is working RTCL ECOEh XBUS Reset Value XXXXh 15 14 143 12 1 10 9 8 7 6 5 4 3 2 1 0 RTCL RW RTCH EC10h XBUS Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCH RW Note Those registers are nor reset 276 340 ky ST10F269 USER S MANUAL REAL TIME CLOCK 19 1 5 RTCAH amp RTCAL RTC ALARM Registers When the programmable counters reach the 32 bit value stored into RTCAH amp RTCAL registers an alarm is triggered and the interrupt request RTAIR is generated Those registers are not protected RTCAL EC12h XBUS Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCAL RW RTCAH EC14h XBUS Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCAH RW Note Those registers are not reset 19 2 Programming the RTC RTC interrupt request signals are connected to Port2 pad 10 RTCSI and pad 11 RTCAI An alternate function Port2 is to generate fast interrupts firq 7 0 To trigger firq 2 and firq 3 the following configuration has to be set EXICON ESFR controls the external interrupt edge selection RTC interrupt requests are rising edge active EXICON F1C0h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES 12 EXI2ES 19 EXI1ES EXIOES RW
503. tions are processed simultaneously additional hardware has been included in the ST10F269 to take into account dependencies between instructions in different stages of the pipeline This extra hardware like a forwarding operand read and write values resolves most of the possible conflicts like multiple usage of buses This prevents delays that would cause the pipeline to become noticeable to the user However there are some cases where allowances must be made by the programmer for the pipeline architecture of the ST10F269 In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance 38 340 ky ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is generally not capable of using a new CP value which is to be updated by an immediately preceding instruction Therefore to make sure that the new CP value is used at least one instruction must be inserted between a CP changing and a subsequent GPR using instruction as shown in the example SES SCXT CP HOFCOOh select a new context Tiri LK tb must not be an instruction using a GPR Thee MOV RO datax write to GPR 0 in the new context Data Page Pointer Updating An instruction which calculates a physical operand address via a particular DPPn n 0 to 3 register is generally not capable of using a new DPPn
504. to 64 Kbytes of data In applications with big data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without having to change the current DPPs EXAMPLE EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 Bit page offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme The EXTS extend segment instruction allows switching to a 64 Kbyte segment oriented data access scheme for 1 4 instructions without having to change the current DPPs In this case all 16 bits of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with continuous data like huge arrays in C EXAMPLE EXTS 15 1 The override seg is 15 OF 0000h 0F FFFFh MOV RO R14 The 16 Bit segment offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC Short Addressing in the Extended SFR ESFR Space The short addressing modes of the ST10F269 REG or bitOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction red
505. to ADDAT2 end of injected conversion interrupt This interrupt request may be used to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer ADCIC FF98h CCh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC ADC ILVL GLVL IR IE RW RW RW RW ADEIC FF9Ah CDh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADE ADE ILVL GLVL IR IE RW RW RW RW Note Refer to Section 6 1 3 Interrupt Control Registers for explanation of the control fields ky 249 340 ON CHIP CAN INTERFACES ST10F269 USER S MANUAL 18 ON CHIP CAN INTERFACES The ST10F269 provides 2 CAN modules with identical features The integrated CAN Modules handles the autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active the on chip CAN Modules can receive and transmit standard frames with 11 bit identifiers and extended frames with 29 bit identifiers The CANS provide Full CAN functionality on up to 15 full sized message objects 8 data byte each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object Full CAN and Basic CAN modes both provide separate masks for acceptance filtering accepting identifiers in Full CAN mode and disregarding identifiers in Basic CAN mode All message objects can be updated independently from the other objects and are equipped with bu
506. to the corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones so their transmit buffers must be loaded with FFFFh prior to any transfer Note A slave with push pull output drivers which is not selected for transmission will normally have its output drivers switched However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer see Figure 103 12 5 SSC Interrupt Control Three interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase Baud rate transmit error can be identified by the error status flags in control register SSCCON Note In contrary to the error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by soft ware 204 340 ky ST10F269 USER S MANUAL HIGH SPEED SYNC
507. to the message object unused message byte will be overwritten by non specified values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual data has been transferred 3 When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first 18 5 Arbitration Registers The arbitration Registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message is stored into the valid message object with a matching identifier and DIR 0 data frame or DIR 1 remote frame Extended frames can be stored on
508. tput of channel 0 is replaced with the logical AND of channels O and 1 The output of channel 1 can still be used at its associated output pin if enabled Each of the two channels can either operate in mode 0 or 1 Note It is guaranteed by design that no spurious spikes will occur at the output pin of channel O in this mode The output of the AND gate will be transferred to the output pin synchronously to internal clocks XORing of the PWM signal and the port output latch value is done after the ANDing of channel O and 1 see Figure 125 Figure 125 Operation and output waveform in burst mode PPO Period Value PTO Count Value Channel 0 PP1 PT1 Channel 1 VAN AV ON VW ALY Sr mm TI 236 340 ky ST10F269 USER S MANUAL PULSE WIDTH MODULATION MODULE 16 1 4 Single Shot Mode Single shot mode is selected by setting the respective bit PSx in register PWMCON1 to 1 This mode is available for PWM channels 2 and 3 In this mode the timer PTx of the respective PWM channel is started via software and is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is cleared to 0000h and stopped via hardware the respective PTRx bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the
509. trol Basic Operating Mode 00 Timer Mode 01 Counter Mode 10 Gated Timer with Gate active low 11 Gated Timer with Gate active high T5R Timer 5 Run bit T5R 0 Timer Counter 5 stops T5R 1 Timer Counter 5 runs T5UD Timer 5 Up Down Control 1 T5UDE Timer 5 External Up Down Enable il CT3 Capture Trigger 3 0 Inactive 1 Capture on Timer3 events Cl Register CAPREL Input Selection 00 Capture disabled 01 Positive transition rising edge on CAPIN 10 Negative transition falling edge on CAPIN 11 Any transition rising or falling edge on CAPIN T5CLR Timer 5 Clear bit T5CLR 0 Timer 5 not cleared on a capture T5CLR 1 Timer 5 is cleared on a capture T5SC Timer 5 Capture Mode Enable T5SC 0 Capture into register CAPREL Disabled T5SC 1 Capture into register CAPREL Enabled Note 1 For the effects of bit TXUD and TxUDE refer to the direction Table 34 Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6 The description and the table apply accordingly a 178 340 ST10F269 USER S MANUAL THE GENERAL PURPOSE TIMER UNITS Timer T5 in Timer Mode or Gated Timer Mode When the auxiliary timer T5 is programmed to timer mode or gated timer mode its operation is the same as described for the core timer T6 The descriptions figures and tables apply accordingly with one exceptio
510. trol Register 1 to 15 XXXXh CAN1MO1 15 EF1x EFFxh CAN1 Message Object 1 to 15 XXXXh CAN1UAR1 15 EF12 EFF2h CAN1 Upper Arbitration Register 1 to 15 XXXXh CAN1UGML EFO8h CAN1 Upper Global Mask Long XXXXh CAN1UMLM EFOCh CAN1 Upper Mask Last Message XXXXh CAN2BTR EE04h CAN2 Bit Timing Register XXXXh CAN2CSR EE00h CAN2 Control Status Register XXOth CAN2GMS EEO6h CAN2 Global Mask Short XFXXh CAN2IR EE02h CAN2 Interrupt Register XXh CAN2LAR1 15 EE14 EEF4h CAN2 Lower Arbitration register 1 to 15 XXXXh CAN2LGML EEOAh CAN2 Lower Global Mask Long XXXXh CAN2LMLM EEOEh CAN2 Lower Mask Last Message XXXXh CAN2MCR1 15 EE10 EEFOh CAN2 Message Control Register 1 to 15 XXXXh CAN2MO1 15 EE1x EEFxh CAN2 Message Object 1 to 15 XXXXh CAN2UAR1 15 EE12 EEF2h CAN2 Upper Arbitration Register 1 to 15 XXXXh CAN2UGML EE08h CAN2 Upper Global Mask Long XXXXh CAN2UMLM EEOCh CAN2 Upper Mask Last Message XXXXh RTCAH EC14h RTC Alarm Register High Byte XXXXh RTCAL EC12h RTC Alarm Register Low Byte XXXXh RTCCON ECOOH RTC Control Register 00h RTCDH ECOCh RTC Divider Counter High Byte XXXXh RTCDL ECOAh RTC Divider Counter Low Byte XXXXh RTCH EC10h RTC Programmable Counter High Byte XXXXh RTCL ECOEh RTC Programmable Counter Low Byte XXXXh RTCPH ECO8h RTC Prescaler Register High Byte XXXXh RTCPL ECO6h RTC Prescaler Register Low Byte XXXXh DI 313 340 REGISTER SET ST10F269 USER S MANUAL 22 6 X Registers Ordered by Address Table 59 Xregisters ordered by address
511. ts Transfer may start with the LSB or the MSB The shift clock may be idle low or idle high Data bit may be shifted with the leading or trailing edge of the clock signal The Baud rate may be set for a range of values refer to Section 12 3 Baud Rate Generation for the formula to calculate values or to the device datasheet for specific values The shift clock can be generated master or received slave This allows the adaptation of the SSC to a wide range of applications where serial data transfer is required 198 340 SZA ST10F269 USER S MANUAL HIGH SPEED SYNCHRONOUS SERIAL INTERFACE The data width selection supports the transfer of frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SSCHB 0 allows communication with ASCO devices in synchronous mode like serial interfaces Starting with the MSB SSCHB 1 allows operation compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer data in bit 0 of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine The clock control allows the adaptation of
512. tting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output 96 340 ky ST10F269 USER S MANUAL PARALLEL PORTS There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose l O lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the output pins This applies to single pins as well as to pin g
513. ture Figure 34 the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch the write operation of the user software has priority Each time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost ky 105 340 PARALLEL PORTS ST10F269 USER S MANUAL As all other capture inputs the capture input function of pins P2 17 P2 0 can also be used as external interrupt inputs with a sample rate of 8 CPU clock cycles For pins 2 15 to 2 8 the sampling rate is 8 CPU clock cycle When used as capture input and 1 CPU clock cycle if used as fast external input 7 4 2 External Interrupts These interrupt inputs are provided to service external interrupts with high precision requirements These fast interrupt inputs feature programmable edge detection rising edge falling edge or both edges Fast external interrupts may also have interrupt sources sele
514. ture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port2 line is used as a compare output compare modes 1 and 3 the compare event or the timer overflow in compare mode 3 directly effects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the port struc
515. ud rates below B yy would cause T6 to overflow In this case ASCO cannot be initialized properly The maximum Baud rate B y gn in the Figure 109 is the highest Baud rate where the deviation still does not exceed the limit so all Baud rates between Dr y and Byigh are below the deviation limit The maximum standard Baud rate that fulfills this requirement is 19200 Baud 212 340 ky ST10F269 USER S MANUAL BOOTSTRAP LOADER Higher Baud rates however may be used as long as the actual deviation does not exceed the limit A certain Baud rate marked TT in Figure 109 may violate the deviation limit while an even higher Baud rate marked IT in Figure 109 stays very well below it This depends on the host interface Figure 109 Baud rate deviation between host and ST10F269 2 5 ky 213 340 THE CAPTURE COMPARE UNITS ST10F269 USER S MANUAL 15 THE CAPTURE COMPARE UNITS The ST10F269 provides two almost identical Capture Compare CAPCOM units which differ only in the way they are connected to the I O pins They provide 32 channels which interact with 4 timers The CAPCOM units capture the contents of a timer on specific internal or external events or they compare a timer s content with given values and modify output signals in case of a match They support generation and control of timing sequences on up to 16 channels per unit with a minimum of software intervention For programming the term CAPCOM unit
516. un time except when more than the four address windows plus the default is to be used 136 340 iy ST10F269 USER S MANUAL THE EXTERNAL BUS INTERFACE Switching from de multiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to Port4 and PORT1 as usual if another BUSCON register selects a de multiplexed bus However in the multiplexed bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete multiplexed bus cycle and extends the corresponding ALE signal see Figure 56 This extra time is required to allow the previously selected device via de multiplexed bus to release the data bus which would be available in a de multiplexed bus cycle 9 2 4 External Data Bus Width The EBC can operate on 8 bit or 16 bit wide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory cost on the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of byte to words and the disassembly of words into byte is handled by
517. value for the high byte of the timer selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow 206 340 ky ST10F269 USER S MANUAL WATCHDOGTIMER WDTCON FFAEh D7h SFR Reset Value OOxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTREL A PONR LHWR SHWR SWR WDTR WDTIN RW RW RW RW RW RW RW WDTIN Watchdog Timer Input Frequency Selection 0 Input Frequency is fcpy 2 1 Input Frequency is fcpy 128 WDTR Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow Cleared by a hardware reset or by the SRVWDT instruction SWR Software Reset Indication Flag Set by the SRST execution Cleared by the EINIT instruction SHWR Short Hardware Reset Indication Flag Set by the input RSTIN Cleared by the EINIT instruction LHWR Long Hardware Reset Indication Flag Set by the input RSTIN Cleared by the EINIT instruction PONR 2 Power On Asynchronous Reset Indication Flag Set by the input RSTIN if a power on condition has been detected Cleared by the EINIT instruction Notes 1 More than one reset indication flag may be set After EINIT all flags are cleared 2 Power on is detected when a rising edge from Vcc 0 V to Vcc gt 2 0 V is recognized After any software reset external hardware reset See note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000h wit
518. vided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the internal RAM SFR area the internal Flash Memory the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment 0 Segments are contiguous blocks of 64 Kbytes each They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment to prevent the prefetcher from trying to leave the cur
519. ware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests are generated by the peripherals based on specific events which occur during their operation like end of task new event error ky 19 340 ARCHITECTURAL OVERVIEW ST10F269 USER S MANUAL Specific pins of the parallel ports are used for interfacing with external hardware when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose UO pin 2 5 2 Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock fcpy The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further
520. ware must write 0 s to reserved bit These bit are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be 0 Therefore writing only 0 s to reserved locations provides portability of the current software to future devices Read accesses to reserved bit return Oe 2 5 4 Parallel Ports The ST10F269 provides up to 111 I O lines which are organized into eight input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three I O ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All pins of UO ports also support an alternate programmable function PORTO and PORT1 may be used as data and address lines respectively when accessing external memory Port2 accepts the fast external interrupt inputs and provides inputs outputs for CAPCOM1 unit Port3 includes the alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT a 20 340 ST10F269 USER S MANUAL ARC
521. west priority ILVL 0 is assigned to the initial CPU activity 4 4 4 The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the MCU address space and thus it is not directly accessible by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations IP Reset Value 0000h Function Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment SEGNR 48 340 AT ST10F269 USER S MANUAL THE CENTRAL PROCESSING UNIT CPU 4 4 5 The Code Segment Pointer CSP This non bit addressable register selects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up to 256 segments of 64 Kbytes each while the upper 8 bits are reserved for future use CSP FE08h 04h SFR Reset Value 0000h 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 E E e e SEGNR Bit Function SEGNR Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored when segmentation is disabled Figure 14 Addressing Via the Code Segment Pointer
522. x and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is performed by the respective PEC channel PECCx FECyh 6zh see Table 14 SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D INC BWT COUNT RW RW RW Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see table below BWT Byte Word Transfer Selection 0 Transfer a word 1 Transfer a byte INC Increment Control Modification of SRCPx or DSTPx 0 0 Pointers are not modified 0 1 Increment DSTPx by 1 or 2 BWT 1 0 Increment SRCPx by 1 or 2 BWT 1 1 Reserved Do not use this combination changed to 10 by hardware Table 14 PEC control register addresses Register Address Reg Space Register Address Reg Space PECCO FECOh 60h SFR PECC4 FEC8h 64h PECC1 FEC2h 61h SFR PECC5 FECAh 65h PECC2 FEC4h 62h SFR PECC6 FECCh 66h PECC3 FEC6h 63h SFR PECC7 FECEh 67h 78 340 ky ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS Byte word Transfer bit BWT controls if a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Increment Control Field INC controls if one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both pointers however If the po
523. xecution flow The Traps priorities are summarized in Table 17 Table 17 Trap priorities 3 D Trap Trap Vector Trap Trap Reset Functions MAXIMAL Hardware Reset RESET 00 0000h 00h HT Software Reset RESET 00 0000h 00h II Watchdog Timer Overflow RESET 00 0000h 00h II Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 0008h 02h Il Stack Overflow STKOF STOTRAP 00 0010h 04h II Stack Underflow STKUF STUTRAP 00 0018h 06h II Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 0028h OAh Protected Instruction PRTFLT BTRAP 00 0028h OAh l Fault Illegal word Operand ILLOPA BTRAP 00 0028h OAh l Access Illegal Instruction Access ILLINA BTRAP 00 0028h OAh l Illegal External Bus ILLBUS BTRAP 00 0028h OAh Access MINIMAL a 88 340 ST10F269 USER S MANUAL INTERRUPT AND TRAP FUNCTIONS 6 7 1 Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000h through 00 01FCh will be branched to Executing a TRAP instruction causes the same effect as servicing the interrupt at the same vector PSW CSP in segmentation mode and IP are pushed on the internal system stack and a jump is taken to the specified vector location When segmentation is enabled and a trap is executed the CSP for the trap service routine is set to code seg
524. xternal timer control lines the two serial interfaces and the control lines BHE WRH and CLKOUT Table 20 Port3 alternative functions Port3 Pin Alternate Function P3 0 TOIN CAPCOM1 Timer 0 Count Input P3 1 T6OUT Timer 6 Toggle Output P3 2 CAPIN GPT2 Capture Input P3 3 T30UT Timer 3 Toggle Output P3 4 T3EUD Timer 3 External Up Down Input P3 5 T4IN Timer 4 Count Input P3 6 T3IN Timer 3 Count Input P3 7 T2IN Timer 2 Count Input P3 8 MRST SSC Master Receive Slave Transmit P3 9 MTSR SSC Master Transmit Slave Receive P3 10 TxDO ASCO Transmit Data Output P3 11 RxDO ASCO Receive Data Input Output in synchronous mode P3 12 BHE WRH Byte High Enable Write High Output P3 13 SCLK SSC Shift Clock Input Output P3 14 No pin assigned P3 15 CLKOUT System Clock Output ky 109 340 PARALLEL PORTS ST10F269 USER S MANUAL Figure 35 Port3 UO and alternate functions Alternate Functions gt a b P3 15 CLKOUT P3 13 SCLK P3 12 BHE WRH P3 11 RxDO P3 10 TxDO P3 9 MTSR P3 8 MRST P3 7 T2IN P3 6 T3IN P3 5 T4IN P3 4 T3EUD P3 3 T30UT P3 2 CAPIN P3 1 T6OUT P3 0 TOIN General Purpose Input Output The structure of the Port3 pins depends on their alternate function see Figure 36 When the on chip peripheral associated with a Port3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate D
525. y the output frequency may be slightly higher or lower than the desired frequency This jitter is irrelevant for longer time periods For short periods 1 4 CPU clock cycles it remains below 4 When the PLL detects that it is no longer locked no longer stable it generates an interrupt request on PLL Unlock XP3INT interrupt node This occurs when the input clock is unstable and especially when the input clock fails completely for example due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLLs basic frequency 2 to 10 MHz The basic frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock 2 4 2 Prescaler Operation When pins POH 7 5 001 during reset the CPU clock is derived from the internal oscillator input clock signal by a 2 1 prescaler The frequency of fcpy is half the frequency of fxtaL The PLL is still running on its basic frequency of 2 to 10 MHz and delivers the clock signal for the Oscillator Watchdog except if bit OWDDIS is set the PLL is switched off 18 340 iy ST10F269 USER S MANUAL ARCHITECTURAL OVERVIEW 2 4 3 Direct Drive When pins POH 7 5 0117 during reset the CPU clock is directly driven from the internal oscillator with the input clock signal this means fcpy fosc The maximum input clock frequency depends on the clock signal s duty cycle becaus
526. y means of a Logic Analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses 1st Write Data 2nd Fetch Code 3rd Read Data Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase of the respective instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes For example an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Time critical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the example INT_OFF BCLR IEN globally disable interrupts Iy 1 non critical instruction CRIT_1ST Iy start of non interruptible critical sequence CRIT_LAST Inix end of non interruptible critical sequence INT_ON BSET IEN globally re enable interrupts Note The described delay of 1 instruction also applies for enabling the interrupts system that means no interrupt requests are acknowledged until the instruction following the enabling instruction Initialization of Port Pins Modifications of the direct
527. ycle of the respective timer In a real application the maximum PWM frequency will depend on the required resolution of the PWM output signal The pulse width modulation module has 4 independent PWM channels Each channel has a 16 bit up down counter PTx a 16 bit period register PPx with a shadow latch a 16 bit pulse width register PWx with a shadow latch two comparators and the necessary control logic The operation of all four channels is controlled by two common control registers PWMCONO and PWMCON1 and the interrupt control and status is handled by one interrupt control register PWMIC which is also common for all channels see Figure 122 ky 231 340 PULSE WIDTH MODULATION MODULE ST10F269 USER S MANUAL Figure 121 SFRs and port pins associated with the PWM module Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 PPOE Y Y Y Y Y YY YYYYYYYYY PWO Y Y Y Y Y YY YYYYYYYYY PPIE IY Y Y Y YYYY YYYY YYYY PW1 YY Y Y Y YY YY YYYYYYY PP2E IY Y Y Y Y YY YY YYYYYYY PW2 Y Y Y Y Y YY YY YYYYYYY PP3E Y Y Y Y Y YY YY YYYYYYY PW3 Y Y YY Y YYYYYYYYYYY Control Registers Interrupt Control 1514131211109876543210 1514131211109876543210 PTOEJY Y Y Y Y Y YY Y YY YY YY Y PWMCONO Y Y Y Y Y Y YYYYYYYYYY PWMCON1 Y Y Y Y Y YYYYYYYYYYY PTIEJY Y Y YY YYYYYYYYYYY PT2E Y Y Y Y Y Y YY YYYYYYYY PWMICE ee ee YY YY YYYY
528. ynchronous 9 bit data frames 1st 2nd Stop Stop bit bit e Data bit D8 e Parity e Wake up bit When the last stop bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bit have been received or not The receive circuit then waits for the next start bit 1 to O transition at the receive data input pin The receiver input pin RXDO P3 11 must be configured for input using direction control register DP3 11 0 Asynchronous reception is stopped by clearing bit SOREN A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Start bit that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred ky 189 340 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE ST10F269 USER S MANUAL 11 2 Synchronous Operation Synchronous mode supports half duplex communication basically for simple I O expansion via shift registers Data is transmitted and received via pin RXDO P3 11 while pin TXDO P3 10 outputs the sh
529. ynchronous warm reset Short low pulse on RSTIN 4TCL 12TCL 1024 TCL 6 or 8 TCL min max lt M Ah dN 4 cruce TLL LULL UUUL UU ITA RSTIN 1 Internally pulled low RPD Ms AAA E AAA 2001A Discharge Vopp gt 2 5V lasynchronous Reset not entered RSTOUT PORTO SN Reset Configuration INST 1 Latching point of PORTO l for system start up donfiguration Internal Reset Signal Notes 1 RSTIN assertion can be released there 2 If during the reset condition RSTIN low Vpgpp voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered 3 RSTIN rising edge to internal latch of PORTO is 3CPU clock cycles 6TCL if the PLL is bypassed and the prescaler is on fcpy fxraL else it is 4 CPU clock cycles 8TCL 4 RSTIN pin is pulled low if bit BDRSTEN bit 5 of SYSCON register was previously set by software Bit BDRSTEN is cleared after reset a 281 340 SYSTEM RESET ST10F269 USER S MANUAL Figure 153 Synchronous warm reset Long low pulse on RSTIN 4TCL 12TCL 1024 TCL 6 or 8 TCL gt lt gt lt gt gt I CPU Clock RSTIN Internally pulled low PS EE l 2004A Discharge l w 2 VapD P 2 5V Asynchronous Reset not enterkd RSTOUT ALE PORTO HA Reset Configuration Latching point of
530. ystem Configuration Register SYSCON This bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardware affectable bit SYSCON FF12h 89h SFR Reset Value Oxx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STKSZ ROM SGT ROM BYT CLK WR CS PWD OWD BDR XPEN VISI XPER S1 DIS EN DIS EN CFG CFG CFG DIS STEN BLE SHARE RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable bit 0 Accesses to the on chip X peripherals and XRAM are disabled 1 The on chip X peripherals are enabled BDRSTEN Bidirectional Reset Enable 0 RSTIN pin is an input pin only SW Reset or WDT Reset have no effect on this pin 1 RSTIN pin is a bidirectional pin This pin is pulled low during 1024 TCL during reset sequence OWDDIS Oscillator Watchdog Disable Control 0 Oscillator Watchdog OWD is enabled If PLL is bypassed the OWD monitors XTAL1 activity If there is no activity on XTAL1 for at least 1 us t

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