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1. DEBUG PORT ON if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp KA PON RESET DBPC PON DEFAULT DEBUG PORT ON JTAG KA PON RESET amp DBPC PON DEFAULT DEBUG PORT NON EXISTANT then DEBUG PORT NON EXISTANT else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT RESERVED amp PON RESET DBPC PON DEFAULT DEBUG PORT ON JTAG KA PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG PORT RESERVED else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT ON DEBUG PINS amp KA PON RESET 4 DBPC PON DEFAULT DEBUG PORT ON JTAG KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS then DEBUG PORT ON DEBUG PINS else DEBUG PORT ON DEBUG PORT NON EXISTANT if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp KA PON RESET DBPC PON DEFAULT DEBUG PORT NON EXISTANT
2. Pins declaration WK lt KKK x lt x KKK KKK KKK x x x lt KK clock generator SYSCLK PIN 15 pda clkout WK ck KKK KK KKK x x x lt KKK KKK KKK K
3. System Hard Reset Configuration IP BDIS RSV2 BPSO BPS1 RSV6 ISBO ISB1 DBGCO DBGC1 DBPCO DBPC1 RSV13 RSV14 RSV15 DataOe NODI NODI NODI NODI NODI NODI NODI NODI NODI NODI NODI NODI NODI E istype reg buffer External Arbitration E istype reg buffer Interrupt Prefix in MSR E istype reg buffer Boot Disable E istype reg buffer reserved config bit 2 E istype reg buffer Boot Port Size E istype reg buffer reserved config bit 6 E istype reg buffer Internal Space Base E istype reg buffer Debug pins Config E istype reg buffer Debug Port pins Config E istype reg buffer reserved config bit 13 E istype reg buffer reserved config bit 14 E istype reg buffer reserved config bit
4. Dram Address lines These lines are connected to the dram high order address lines A9 and A10 if available These lines change value according to the dram size and port size The dram size is encoded from the presence detect lines s definitions above and the port size is determined by the control register VE ck ck kk CC KKK x x x k x lt x lt KKK equations DramAdd oe 3 when IS HALF WORD 4 IS HALF WORD amp SIMM36400 SIMM36800 then DramAdd9 A20 else DramAdd9 A30 when SIMM36400 4 SIMM36800 amp IS HALF WORD then DramAdd10 A19 else when SIMM36400 SIMM36800 amp IS HALF WORD then DramAdd10 A30 else DramAdd10 0 RAS generation
5. DSDI_ ENABL E Logic definitions DSDI_ENABLED 1 DSDI_DISABLED 0 STATE_DSDI_ENABLED En fb DSDI_ ENABL ED Release 1 3a MPCS21ADS Revision A User s Manual Support Information Tx enable state machine X_E
6. Signal groups AdsSel AdsSel2 AdsSell AdsSel0 AdsAddr AdsAddr2 AdsAddri1 AdsAddr0 AdsRst AdsHardReset AdsSoftReset Rst PdaHardReset PdaSoftReset Clkout Clkout2 Clk4 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO VFLS VFLSO VFLS1 BndDly BundleDelayl BundleDelay0 bundle delay compensation timer TxReg TxReg7 TxReg0 RxReg xReg6 TxReg5 TxReg4 TxReg3 TxReg2 TxReg1 0 RxReg0 AdiCtrlReg Delayl Delay0 StatusRequest DiagLoopBack DebugEntry AdiStatReg PdaRst TxError InDebugMode Delayl DelayO StatusRequest DiagLoopBack DebugEntry BundleDelayField Delayl Delay0 TxWordLen TxWordLen3 TxWordLen2 TxWordLenl TxWordLen0 PortEn AdsSel2 AdsSell AdsSel0 AdsAddr2 AdsAddr1 AdsAddrO0
7. KEEP_ALIVE_PON_RESET_ACTIVE 0 REGULAR PON RESET ACTIVE 0 HARD RESET ACTIVE 0 SOFT RESET ACTIVE 0 HARD CONFIG HOLD VALUE 4 KEEP ALIVE POWER ON RESET KAPORIn KEEP ALIVE PON RESET ACTIVE DRIVE MODCK TO PDA HardReset HARD RESET ACTIVE have modck stable during hard reset REGULAR POWER ON RESET RegPORIn REGULAR PON RESET ACTIVE HARD RESET ASSERTED SyncHardReset fb HARD RESET ACTIVE HARD RESET NEGATES SyncHardReset fb HARD RESET ACTIVE amp DSyncHardReset fb HARD RESET detecting hard reset negation data buffers enable
8. state_diagram EthEn state ETH_ENABLED if PDA WRITE CONTROL REG1 6 ETH_ENABLE_DATA_BIT pin ETH_ENABLED amp KA PON RESET ETH ENABLE PON DEFAULT ETH ENABLED KA PON RESET amp ETH ENABLE PON DEFAULT ETH ENABLED then ETH ENABLED ETH ENABLED state ETH ENABLED if PDA WRITE CONTROL amp ETH ENABLE DATA BIT pin ETH ENABLED amp KA PON RESET ETH ENABLE PON DEFAULT ETH ENABLED KA PON RESET amp ETH ENABLE PON DEFAULT ETH ENABLED then ETH ENABLED else ETH ENABLED
9. TA PIN 6 transfer Acknowledge EA PIN 47 Transfer Error Acknowledge FlashCfgEn PIN 17 flash configuration enable from control register PccEn PIN 4 PCMCIA channel enable from control reg 1 16 2 43 UpperHalfEn PIN 3 istype com invert pits 0 15 data buffer enable LowerHalfEn PIN 5 istype com invert bits 16 31 data buffer enable PccEvenEn PIN 14 istype com invert pcc upper byte data buffer enable PccOddEn PIN 37 istype com invert pcc lower byte data buffer enable PccR W PIN 62 istype com pcmcia data buffers direction x FERE ETHER LE THE 5 THE THE x THE THERE 2 ud eH THE PET ui
10. 130 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Reset amp Interrupt Logic Pins RstDeb1 NODE 1 NODE HardResetEn NODE SoftResetEn NODE ConfigHold2 ConfigHoldl ConfigHold0 NODE ConfigHoldEnd istype istype istype istype reset push button debouncer abort push button debouncer enables T S hard reset pin enables T S soft reset pin istype reg buffer supplies data hold time for NODI hard istype com reset configuration
11. equations PccDataBufEn oe 3 1 amp ENABLED amp HARD RESET ASSERTED 6 ED amp HOLD OFF PERIOD STATE HOLD OFF CONSIDE STATE NO HOLD OFF PccOddEn PccCE2 6 PCC ENABLED amp HARD RESET ASSERTED 6 STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF pcc data buffers direction equations 139 Release 1 3a MPCS21ADS Revision A User s Manual Support Information PccR_W oe H PccR_W R W
12. INT SPACE BASE OxFF000000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE OxFFF00000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE 0x00F00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFFF00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE 0x00F00000 state INT SPACE BASE OxFF000000 if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE 0x00000000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE OxFF000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE 0 00 00000 6 PON RESET ISB PON DEFAULT INT SPACE BASE OxFF000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F00000 then INT SPACE BASE 0 00 00000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE OxFFF00000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE OxFF000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFFF00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE OxFF000000 state INT SPACE BASE OxFFF00000
13. Equations state diagrams gt me HEEE HEHEH K f d EREHE f T f dg x gt THE THE THE Configuration Register Gets its default pon reset values which are driven to the data bus when during hard reset configuration If other values are required this register may be written with new values to become active for the next hard reset The state machines are built in a way that its power on value is changed in one plac the declarat
14. Pda ADS Debug Port Controller Mach controller for interface between Sun ADI port at one side to debug port at the other x x lt lt lt lt lt ck x x x In this file 6 RUN signal polarity was changed to active high this to support other changes for revision PILOT of the ads this file 5 added protection against spikes on the reset lines so that the interface will not be reset by an accidental spike D_C signal was synchronized to avoid accidental write to control during data write DSDI is given value H prior to negation of SRESET to comply with 5 VN family x lt x lt lt x x x x lt x x lt x ck Ck Ck Ck x
15. PDA pins Including debug port PdaHardReset PIN 40 Pda s hard reset input I O o d PdaSoftReset PIN 65 Pda s soft reset output 1 0 o d VFLSO VFLS1 PIN 10 11 Debug Trap mode report IN DSCK PIN 48 istype com Pda s debug port clock Out DSDI PIN 47 istype com Pda s debug serial data in Out DSDO PIN 4 Pda s debug serial data output In Mach to ADI data bus W ck k k x k KKK k x lt x lt
16. x TK PR OFTHE EREHE THE E THE THE TK THE TREES dog x TEE PEE 2 Pins declaration K x System i f pins
17. Rx Control Logic 5 DsdiEn NODE istype reg enables dsdi towards 106 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ADI control amp status register bits StatusRequest DebugEntry DiagLoopBack Delayl Delay0 InDebugMode TxError
18. Signal groups WK KKK KKK x lt KKK KKK KKK KK KKK KK x x lt x lt KKK PdaAdd DramAdd DramCS RAS SD Flas Rese Rese 132 hCsOut L tEn A9 A10 A19 A20 A301 DramAdd10 DramAdd9 DramBank2Cs DramBank1Cs Rasl Ras1DD Ras2 Ras2DD SizeDetectl SizeDetectO0 FlashCs4 FlashCs3 FlashCs2 FlashCs1 HardReset SoftReset HardReset En SoftReset Release 1 3a RS Abr Debounce DramCs Cs PccCs LocDataBu PccDataBu oduleEn SyncReset RstCause Stp odck ConfigHol F PD f 5 Gl 5 MPCS21ADS Revision A User s Manual Support Information Rstl Rst0 Abr1 Abr0 RstDeb1 AbrDeb1 DramBank2Cs DramBank1Cs ContRegCs FlashCs DramBanklCs DramBank2Cs PccCE1 PccCE2 UpperHalfEn LowerHalfEn PccEvenEn PccOddEn DramEn FlashEn PccEn ContRegEn SyncHardReset DSyncHardReset Rstl RstO Abrl Abr0 KAPORIn RegPORIn TA o
19. equations Reset oe ResetEn Reset 0 open drain RstDeb1 Rstl amp RstDebl fb amp RstO Reset push button debouncer 1 Abrl amp AbrDebl fb 6 Abort push button debouncer HardResetEn RstDebl fb 6 AbrDebl fb both buttons are depressed REGULAR_POWER_ON_RESET SoftReset RstDebl fb amp AbrDebl fb only reset button depressed 5 ll Power On reset configuration equations Modck oe ModckOe ModckOe DRIVE MODCK TO PDA Modck2 L ifndef SLOW 32K LOCK Modck2 ModIn support for 1 513 32KHz crystal or 1 ModIn 1 5 5MHz clock gen via CLK4IN ifdef SLOW 32
20. FLASH ENABLE ACTIVE 0 FLASH ENABLED FlashEn FLASH ENABLE ACTIVE MCM29020 F PD 0 MCM29040 F_PD 7 MCM29080 F_PD 6 SM732A1000A F_PD 2 133 Release 1 3a SM732A2000 FLASH_BANK1 FLASH_BANK2 FLASH_BANK3 FLASH BANK4 F_P D 5 C CM29080 amp A9 M C MPCS21ADS Revision User s Manual 29040 amp 10 SM732A2000 amp A A9 29040 amp A10 amp 732A2000 amp A9 4 9 Support Information 10 29080 amp 9 amp 10 amp A10 6 29080 A9 amp 10 amp 29080 29020 SM732A1000A Reset Declarat Wk KK KKK KKK KKK ions
21. state_diagram IP state IP AT OxFFF00000 if PDA WRITE CONFIG REG amp DATA BIT pin AT 0 00000000 6 KA PON RESET PON DEFAULT IP AT OxFFF00000 KA PON RESET amp PON DEFAULT IP AT 0x00000000 then IP AT 0x00000000 else IP AT OxFFF00000 state IP AT 0x00000000 if PDA WRITE CONFIG REG amp DATA BIT pin IP AT OxFFF00000 6 KA PON RESET PON DEFAULT IP AT 0x00000000 KA PON RESET amp PON DEFAULT AT OxFFF00000 then IP AT OxFFF00000 else IP AT 0x00000000 154 Release 1 3a MPCS21ADS Revision A User s Manual Support Information WK ck ck lt CC CK x x lt KKK KKK KKK x KKK KK KK state diagram 2 state RSV2 ACTIVE if PDA WRITE CONFIG REG amp RSV2 DATA BIT pin RSV2 ACTIVE KA PON RESET RSV2 PON DEFAULT KA PON RESET amp RSV2 PON DEFAUL RSV2 ACTIVE else RSV2 ACTIVE state
22. Run 23 istype com external indication 104 Release 1 3a MPCS21ADS Revision A User s Manual Support Information KK KKK lt lt ck kk x lt lt x x KKK CC CK VE ck ck Wx gt gt Wx gt gt gt THE THE THE THE 0 oGH 2 THE THE THERE 5 x x x x lt lt x x KKK Reset active Active when at least one of the reset sources is active x
23. data buffers enable SyncHardRes DSyncHardRe SyncTEA HoldOffConsideredNODE istype D FlashOe DD FlashOe TD FlashOe IO D FlashOe PD FlashOe ere sets NODE istype reg buffer synchronized hard reset NODE istype reg buffer double synchronized hard reset NODE istype reg buffer needed since TEA is O D reg buffer data drive hold off state machine NODE istype com delayed flash output enable NODE istype com double delayed flash output enable NODE istype com triple delayed flash output enable NODE istype com quad delayed NODE istype com penta delayed KeepPinsConnected NODE istype 131 Release 1 MPCS21ADS Revision A User s Manual Support Information
24. Device declaration U07 device mach220a 102 Release 1 3a MPCS21ADS Revision A User s Manual Support Information VE ck ck ck CC lt x x lt kk kk x x x lt x lt KK EHEHE n i n HEE n n HEHE THE THE THE THE THE THERE THE THE EERE
25. Pins declaration ADI Port pins HstReq AdsAck AdsReq HstAck AdsHardReset AdsSoftReset HstEn HostVcc AdsSel0 AdsSell AdsSe12 103 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 22 20 31 2 54 50 LP 49 51 215 93 Host to ADS write pulse reg OUT 35 Host to ADS buffer card addr ADS to host IN E reg buffer ADS to host write signal OUT 3s Host to ADS write ack IN Host to ADS Hard reset IN Host to ADS Soft reset IN Host connected to ADS IN Host to ADS host is on IN Host to ADS select data or control access IN IN write ack Release 1 3a MPCS21ADS Revision A User s Manual Support Information AdsAddr0 AdsAddrl AdsAddr2 PIN 7 6 5 ADS board address switch IN AdsSelect NODE ISTYPE com buffer ADS selection indicator OUT
26. equations 167 Release 1 3a MPCS21ADS Revision A User s Manual Support Information CntRegEnProtect clk SYSCLK state_diagram CntRegEnProtect state CNT_REG_EN_PROTECT if PDA WRITE CONTROL REG2 6 CNT REG EN PROTECT DATA BIT pin CNT REG EN PROTECT amp KA PON RESET CNT REG EN PROTECT PON DEFAULT CNT REG EN PROTECT KA PON RESET amp CNT REG EN PROTECT PON DEFAULT CNT REG EN PROTECT then CNT REG EN PROTECT else CNT REG EN PROTECT state CNT REG EN PROTECT if PDA WRITE CONTROL REG2 amp CNT REG EN PROTECT DATA BIT pin CNT REG EN PROTECT amp KA PON RESET 4 CNT REG EN PROTECT PON DEFAULT CNT REG EN PROTECT KA PON RESET amp CNT REG EN PROTECT PON DEFAULT CNT REG EN PROTECT PDA WRITE CONTROL REG1 then any write to control reg 1 CNT REG EN PROTECT else REG EN PROTECT WK ck CC
27. state_diagram BPS state BOOT_PORT_32 if 155 PDA_WRITE_CONFIG_RE amp Release 1 3a MPCS21ADS Revision A User s Manual Support Information BPS DATA BIT pin BOOT PORT 8 amp KA PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 16 amp KA PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT RESERVED amp KA PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT RESERVED then BOOT PORT RESERVED else BOOT PORT 32 state BOOT PORT 8 if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 32 amp KA PON RESET BPS PON DEFAULT BOOT PORT 8 KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 else if PDA WRITE CONFIG REG amp BPS DATA BI
28. Wx Wx gt gt gt gt Wx gt gt gt Wx gt Wx gt gt THEE THEE EEEH T T THE THE TRO THE EEEH THE THE THE THE THE T THE Th THER THE THREE THE H L 1 0 Uv SLOW 32K LOCK 1
29. Equations state diagrams x T HEEE THE 5 f d EREHE THE x me f 2 Tx f dg 2 THE ig x 135 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Reset Logic
30. Reset PdaRst PrimReset D_PrimReset DD_PrimReset NODE NODE NODE NODE NODE istype com istype istype istype istype reg Primary Reset Host initiated delayed Reset double delayed primary reset Interface reset buffer pda continued initiated part of the status register ADS_ACK ADS_RI FQ auxiliary internal control signals Wk ck KKK x x lt lt KK KKK k x KK KK S HstReq DS HstReq S DC S HstAck DS HstAck Bundle Bundle BndTmr PDOe 105 Delayl DelayO EXp NODE NODE NODE NODE NODE NODE NODE NODE istype reg istype reg istype reg istype reg istype reg istype reg istype com istype com sync host req doubl
31. SYSCLK PIN 15 RGPORIn PIN 49 ResetConf PIN 16 142 Release 1 3a BrdContRegCs TA R_W A28 A29 DO D1 D2 D3 D4 D5 D6 D7 D8 D9 J gt PE PI PI PI PI MPCS21ADS Revision A User s Manual 50 UR 20 513 54 28 29 30 Joy 36 Support Information lt lt Board Control Pins Read Write FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEn RS232En PccEn PccVccOn PccVppO PccVppl HalfWord 143 PI PI PI PIN PIN PIN PI PI PIN PI PI PIN 44 55 46 59 25 13 48 40 39 is is is is is is
32. Add Data ConfigReg 146 A28 A29 0 15 ERB IP RSV2 BDIS BPSO BPS1 RSV6 ISBO ISB1 DBGC0 DBGC1 DBPCO DBPC1 RSV13 RSV14 RSV15 Release 1 3a MPCS21ADS Revision A User s Manual Support Information BPS BPSO BPS1 boot port size ISB ISBO ISB1 Initial Internal Space Base DBGC DBGCO DBGC1 Debug Pins Configuration DBPC DBPCO DBPC1 Debug port location ContReg FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect ReadContRegl F CntRegEn RS232En PccEn PccVccOn PccVpp0 PccVpp1 HalfWord lashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect fb CntRegEn RS232En PccEn PccVccOn PccVpp0 PccVppl HalfWord 0 0 0 DrivenContReg FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEn RS232En PccEn PccVccOn PccVpp0 PccVpp1 HalfWord PccVccOn PccVpp 0 11 WideContReg Fl ashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect CntRegEn RS232En PccEn PccVccOn PccVpp0 PccVpp1 HalfWord StatRegIn FlashPD4 FlashPD3 FlashPD2 FlashPD1 DramPdEdo DramPD4 DramPD3 FlashPdHigh
33. equations PdaHardReset H PdaHardReset oe PdaHardResetEn open drain 113 Release 1 3a MPCS21ADS Revision A User s Manual Support Information PdaHardResetEn ADS IS SELECTED amp AdsHardReset ADS HARD RESET ACTIVE PdaSoftReset H PdaSoftReset oe PdaSoftResetEn needs to be open drain PdaSoftResetEn ADS IS SELECTED 6 AdsSoftReset ADS_SOFT_RESET_ACTIVE Clock generator Divides the system clock and generates 2 clocks 1 Clkout2 which is used for all state machines connected to Clk2 2 4 which is used to generate DSCK and for shift registers control ifndef SIMULATION equations ClkOut clk SYSCLK ClkOut oe h3 Clkout2 Clkout2 amp HOST IS ON divide by
34. U1 1 SOFT 5 ERR RED du e 1 2 RDI PORT 1 8 2 5 RS232 RUN P2 ETHERNET U5 7 P5 U6 IM 75 68 34 P4 PCMCIA PORT 35 1 5 ON 9 DEBUG 50 52 44 52 44 8 B ORT eg 2 END Y 2 Ej LDS 106 107 61 43 n 39 192 6 Y4 U12 EM on 40 26 SW2 ABORT RX TX 8 1 35 018 e LD9 LD11 52 14 x CLSN PLR LIL 1 3 SN RS232 25 GND U10 1 7 P6 ADDRESS amp STROBES 10 18 m 2 8 8 D Motorola I U16 SK1 015 821 5 B 1 1995 A U13 U14 1 5 18 15 2 25 30 D U18 B C D Ba T1 5 POWER 1 U19 5y T2 GND GND 10 GND wey ves M 12V 15 P11 GND 9 10 20 19 28 SP1 1 DATA amp CONTROL 25 212 COMMUNICATION 0 3i FLRSH gt COMM PORTS EXPANSION B 1 5 18 5 20 25 30 6 B 13 1 5 18 15 28 25 Release 1 3a MPCS82I1ADS Revision A User s Manual Hardware Preparation and Installation 2 3 1 ADI Port Address Selection The MPC821ADS can have eight possible slave addresses set for its ADI port enabling up to eight MPC821ADS boards to be connected to the same ADI board in the host computer The selection of the slave address is done by setting switches 1 2 amp 3 in the Dip Switch DS1 Switch 1 stands for the most significant bit of the address and switch 3 stands for the least significant bit If the
35. ADI Data Bus The Adi data bus is driven towards the host when the host reads the i f When D_C line is high data the Rx shift register contents is driven If D C is low control the status register contents is driven The status register contains all control register s bits 4 0 with the addition of the following InDebugMode Bit 5 When this bit is active the pda is in debug mode i e VFLS 0 1 lines are driven high TxError Bit 6 When this bit is active H it signals that the pda was reset internally during data transmission i e data received during that transmission is corrupted This bit is reset L when either happens 1 The interface is reset by the host both AdsHardReset and AdsSoftReset are asserted H by the host while the board is selected 2 The host writes the interface with D C signal low control and with data bit 6 high 3 a new data word is written to the Tx shift register I e error is not kept indefinitely PdaRst Bit 7 When this bit is active it means that either SRESET or HRESET or both are driven by the pda The host have to wait until this bit negates so that data may be written to the debug port VE ck kk CC
36. BUFF DISABLI _ 134 BUFF ER_DISABL Release 1 3a MPCS21ADS Revision A User s Manual Support Information CONTROL REG ENABLE ACTIVE 0 FLASH CONFIG ENABLED ACTIVE 0 PCMCIA ENABLE ACTIVE 0 GPL ACTIVE 0 TEA ASSERTS TEA amp SyncTEA fb first clock of TEA asserted CONTROL REG ENABLED ContRegEn CONTROL REG ENABLE ACTIVE FLASH CONFIGURATION ENABLED FlashCfgEn FLASH CONFIG ENABLED ACTIVE PCC ENABLED PccEn PCMCIA ENABLE ACTIVE NO HOLD OFF 0 HOLD OFF CONSIDERED 1 STATE HOLD OFF CONSIDERED HoldOffConsidered fb HOLD OFF CONSIDERED STATE NO HOLD OFF HoldOffConsidered fb NO HOLD OFF END OF FLASH READ TA amp FlashCs amp W end of flash read cycle END OF OTHER CYCLE TA 6 FlashCs another access or ITA amp FlashCs 6 W flash write HOLD OFF PERIOD R_W amp PD_FlashOe fb
37. equations FlashCsOut oe hf FlashCsl FLASH ENABL ED FlashCs FlashCs2 FLASH ENABL ED FlashCs FlashCs3 FLASH ENABL ED FlashCs FlashCs4 FLASH ENABL ED FlashOe oe H FlashOe FLASH FlashCs ENABLED amp R_W LASH BANK1 LASH BANK2 LASH_BANK3 LASH KK KKK kk Ck CC CC lt lt VE ck ck ck Auxiliary functions equations KeepPinsConnected TA amp KAPORIn end brd ct19 141 Release 1 3a MPCS82I1ADS Revision A User s Manual Support Information U11 Board Control amp Status Register
38. DBPC DATA BIT pin DEBUG PORT ON DEBUG PINS amp KA PON RESET DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS then DEBUG PORT ON DEBUG PINS else 09 UG PORT RESERVED state DEBUG PORT ON DEBUG PINS if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp PON RESET DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON JTAG then DEBUG PORT ON JTAG else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp KA PON RESET 4 DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS KA PON RESET amp DBPC PON DEFAULT DEBUG PORT NON EXISTANT then DEBUG PORT NON EXISTANT else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT RESERVED amp KA PON RESET 4 DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS KA PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG POR ESERVED else DEBUG PORT ON WwW UG_PINS 1
39. Flash Associated Pins PDi F PD2 F PD3 FlashCs FlashEn FlashCsl FlashCs2 FlashCs3 FlashCs4 128 PI PI PI PT PI PI PL 7 65 41 49 flash bank chip select 50 flash enable from control reg 12 istype com Flash bankl chip select 22 istype com Flash bank2 chip select 57 istype com Flash bank3 chip select 24 istype com Flash bank4 chip select Release 1 3a MPCS21ADS Revision A User s Manual Support Information FlashOe PIN 58 istype com Flash output enable Control Register pins
40. 2 4 4 5V Power Supply Connection The MPC821ADS requires 5 Vdc 5 power supply for operation Connect the 5V power supply to connector P7 as shown below FIGURE 2 10 P7 5V Power Connector V 109 GND 20 GN w 30 P7 is 3 terminal block power connector with power plug The plug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires To provide solid ground two Gnd terminals are supplied It is recommended to connect both Gnd wires to the common of the power supply while VCC is connected with a single wire NOTE Since hardware applications may be connected to the MPC821ADS using the expansion connectors P6 P9 P10 P12 or P13 the additional power consumption should be taken into consideration when a power supply is connected to the MPC821ADS 2 4 5 8 12V Power Supply Connection The MPC821ADS requires 12 Vdc max power supply for the PCMCIA channel Flash programming capability The MPC821ADS can work properly without the 12V power supply if there is no need to program a 12V programmable PCMCIA flash card Connect the 12V power supply to connector P6 as shown below 14 Release 1 3a MPCS82I1ADS Revision A User s Manual Hardware Preparation and Installation FIGURE 2 11 P8 12V Power Connector 12V GND P8 is a 2 terminal block power connector with power p
41. lt lt ContRegCs PIN 59 control register cs from pda ContRegEn PIN 56 control register enable from control register Reset amp Interrupt Logic Pins RstO PIN 13 connected to N C of Reset P B Rst1 PIN 21 connected to N O of Reset KAPORIn PIN 25 Keep Alive Power On Reset In H RegPORIn PIN 9 Regular Power On Reset In H HardReset PIN 48 istype com Actual hard reset output O D SoftReset PIN 40 istype com Actual soft reset output O D ResetConfig PIN 67 istype com Drives the RSTCONF signal of the pda DriveConfig PIN 63 istype com Drives configuration data to the pda Abro PIN 10 connected to N C of Abort P B Abr1 PIN 11 connected to N O of Abort NMIEn NODE istype
42. Pin No Signal Name Attribute Description B11 N C Not Connected B12 GND B13 GND B14 CLKAIN External Clock Input Driven by on board 4MHz clock generator B15 GND B16 HRESET I O L MPC Hard Reset Driven by on board logic and may be driven by O D off board logic with Open Drain gate only B17 RSTCNF Hard Reset Configuration Input Driven during Hard Reset to sample Hard Reset configuration from the data bus B18 GND B19 BCD1 Buffered PCMCIA slot A Card Detect 1 In fact A4 Input Port 4 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD2 When the PCMCIA port is disabled via BCSR may be used off board B20 BCD2 Buffered PCMCIA slot Card Detect 2 In fact Input Port 4 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD1 When the PCMCIA port is disabled via BCSR may be used off board B21 GND B22 DP1 DP1 IRQ4 Data Parity line1 or Interrupt Request 4 Generates and receives parity data for D 8 15 bits May not be configured as IRQ4 B23 N C Not Connected B24 N C Not Connected B25 N C Not Connected C1 GND C2 SYSCLK System Clock In fact the CLKOUT of the MPC Should be used carefully off board otherwise might disrupt proper operation of the ADS C3 GND C4 GND C5 IRQ6 FRZ IRQ6 Freeze debug mode indication or Interrupt Request 6 Configured on the ADS a
43. M Fm Recommended Hole for MPC Socket Access P10 5 N x Y im N D 8 DX Dd Dd P12 27 k 0 2 4 gt lt 0 7 gt TABLE 5 6 P6 Interconnect Signals Pin No Signal Name Attribute Description Al VCC MPC821ADS 5V VCC plane A2 VCC VCC i A4 VCC A5 TEA I O L Transfer Error Acknowledge Pulled up not driven on board O D A6 GND MPC821ADS Ground plane 69 Release 1 3a MPCS21ADS Revision A User s Manual Support Informa
44. Motorola Semiconductor Israel Ltd OMMUNICATIONS amp ADVANCED CONSUMER TECHNOLOGY GROUP MPC821 APPLICATION DEVELOPMENT SYSTEM ADS USER S MANUAL Board Revision A Issue 0 1 Draft 8 24 95 ENG Issue 1 1a 2 9 96 ENG Revision Issue 1 2a 5 6 96 PILOT Revision Issue 1 3a 6 26 96 A Revision SIX SIGMA 21 2 3 2 2 3 2 1 2 3 3 24 2 3 5 2 41 2 4 2 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 4 9 3 1 3 2 3 2 1 3 2 2 323 3 2 4 3 2 5 3 2 6 3 2 7 3 2 8 3 2 9 3 2 10 3 2 11 3 2 12 3 2 13 3 2 14 3 2 15 3 2 16 3 2 17 MPCS21ADS Revision User s Manual TABLE OF CONTENTS General Information Introduction Abbreviations List Related Documentation SPECIFICATIONS MPC821ADS Features Revision Pilot to Revision A Changes Revision ENG to Revision PILOT Changes Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION ADI Port Address Selection Clock Source Selection Clock Generator Replacement U17 Power On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection INSTALLATION INSTRUCTIONS Host Controlled Operation Debug Port Controller For Target System Stand Alone Operation 5V Power Supply Connection P8 12V Power Supply Connection ADI Installation Host computer to MPC821ADS Connection Terminal to MPC821AD
45. EEEH THERE THE Fett EEEH EEEH EEEH 112 Release 1 3a MPCS21ADS Revision A User s Manual Support Information AdsSelect x ADS selection indicator At low state when host accesses the ADS equations AdsSelect HOST IS ON amp AdsSel AdsAddr AdsAddr is already inverted lt x x kk Ck
46. Tx Control Logic TxWordLen3 TxWordLen2 TxWordLenl TxWordLen0 NODE istype reg buffer Counter counts on fast clock to gain 1 2 clock resolution transmission length TxWordEnd NODE istype com Terminal count sets transmission length xEn NODE istype reg buffer Transmit Enable TxClkSns NODE istype reg buffer transmit clock polarity Rx Shift Register RxReg0 NODE istype reg buffer receive shift register latch
47. kk WK ck ck Internal Logic Reset equations PrimReset HOST_IS_OFF internal logic reset AdsHardReset ADS HARD RESET 1 AdsSoftReset ADS_SOFT_RESET_ACTIVE amp ADS_IS_SELECTED D PrimReset PrimReset fb DD PrimReset D PrimReset fb Reset PrimReset fb amp D PrimReset fb amp DD PrimReset fb spike filter reset status PdaRst clk Clk2 PdaRst PdaHardReset PdaSoftReset amp AdsSelect fb BOARD IS SELECTED synchronized inside lt lt Reset PDA Connected to PDA hard and reset inputs Asynchronous
48. lt lt kk x KK x lt x KKK DATA_BUFFERS_ ENABLE STATUS_WORD_ON_ADI_BUS READ DATA WORD ON ADI BUS AdsSelect fb BOARD IS SELECTED 6 HsCACk HOST ACTIVE amp HstReq HOST REQ ACTIVE AdsSelect fb BOARD IS SELECTED amp HStACk HOST ACTIVE 8 HstReq HOST REQ ACTIVE amp D_C CONTROL AdsSelect fb BOARD IS SELECTED 6 HsStACk HOST ACTIVE amp HstReq HOST REQ ACTIVE amp D_C DATA Wx Equations state diagrams gt gt Wx Wx 4 gt Wx Wx HEHEH gt THE f HH
49. x x lt kk KKK KKK KKK KKK KK KK equations PDOe DATA_BUFFERS_ENABLE PD oe PDOe when READ DATA WORD ON ADI BUS then PD RxReg fb elsewhen STATUS WORD ON ADI BUS then PD PdaRst fb TxError fb InDebugMode fb Delayl fb Delay0 fb StatusRequest fb DiagLoopBack fb DebugEntry fb InDebugMode clk C1k2 InDebugMode VFLS1 6 VFLSO synchronized Run oe H Run IS IN DEBUG MODE when 1 lits a led 123 Release 1 3a MPCS21ADS Revision A User s Manual Support Information III K K K K K KOK KOK ko kc KOK kc koc Kok ko III III II III 6 II III I gt I k DSCK PDA debug port gated serial clock equations DSCK oe ADS IS SELECTED when ADS IS SELEC I D amp PdaSoftReset then DSCK H debug mode enable else when ADS IS SELECTED amp TxEn fb amp PdaSoftReset then DSCK DebugEntry fb debug mode direc
50. Pin No Signal Name Attribute Description D19 BVS2 Buffered PCMCIA slot A Voltage Sense 2 In fact IP_A1 Used in conjunction with BVS1 to determine the operation voltage of a PCMCIA card When the PCMCIA port is disabled via BCSR1 may be used off board D20 GND D21 BBVD2 Buffered PCMCIA slot A Battery Voltage Detect 2 In act 5 Used in conjunction with BBVD1 to determine the battery status of a PC Card When the PCMCIA port is disabled via BCSR1 may be used off board D22 DP2 DP2 IRQ5 Data Parity line 2 or Interrupt Request 5 Generates and receives parity data for D 16 23 bits May not be configured as IRQ5 D23 V2 2V Power Rail Optional for driving MPC VDDL D24 V2 2 025 V2 TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description Al GND A2 PA11 PA11 L1TXDB Not used on the ADS Appears also at P13 PA10 PA10 L1RXDB Not used on the ADS Appears also at P13 A4 GND 5 9 PA9 L1TXDA Not used on the ADS Appears also at P13 A6 8 PA8 L1RXDA Not used the ADS Appears also at P13 A7 GND 8 Ethernet Port Transmit Clock In fact PA7 CLK1 TIN1 L1RCLKA BRGO1 When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function Appears also at P13 AQ ETHRCK Ethernet Port Receive Clock fact PA7 CLK2 TOUT1 BRGCLK1 When the Ethernet port is disabled via BCSR1 may
51. state_diagram HalfWord state HALF_WORD if PDA_WRITE_CONTROL_REG1 amp HALF_WORD_DATA_BIT pin HALF_WORD amp PON RESET HALF WORD PON DEFAULT HALF WORD KA PON RESET amp HALF WORD PON DEFAULT HALF WORD then HALF WORD else HALF WORD state HALF WORD if PDA WRITE CONTROL amp HALF WORD DATA BIT pin HALF WORD amp PON RESET 4 HALF WORD PON DEFAULT HALF WORD KA PON RESET amp HALF WORD PON DEFAULT HALF WORD then HALF WORD else HALF WORD Read Registers All registers have read capabilty equations DataOe PDA_READ RESET_CONFIG_DRIVEN Data oe DataOe when PDA READ CONFIG REG 172 Release 1 3a MPCS21ADS Revision A User s Manual Support Information RESET CONFIG DRIVEN then Data ERB fb IP fb
52. Reference Designation Part Description Manufacturer Part Y1 Crystal resonator 20 MHz MEC Modern HC 49 U SM 3 Fundamental Oscillation mode Enterprise Frequency tolerance 50 ppm Corporation Drive level 1mW 0 2 mW Shunt capacitance 7pF Max Load capacitance 32pF Equivalent Series Resistance 50Q Max Insulation Resistance 500 MQ at 100 VDC Y2 Crystal resonator 32 768 KHz RALTRON RSM 200 32 768 KHZ Frequency tolerance 30 ppm Drive level 10uW Max Shunt capacitance 2pF Max Load capacitance 12 5pF Max Equivalent Series Resistance 35 Max 3 X Socket 68 Pin PLCC AMP 822279 1 14 pin PC Socket PD 110 93 314 72 pin SIMM Socket AMP 822032 4 80 pin SIMM Socket AMP 822032 5 357 pin 19 X 19 BGA Socket 3M 2 0357 08268 000 019 a Not Assembled 100 002 Release 1 3a MPCS82I1ADS Revision A User s Manual Support Information APPENDIX A Programmable Logic Equations The MPC821ADS has 3 programmable logic devices on it Use is done with MACH220 12 by AMD These device support the following function on the ADS 1 U7 Debug Port Controller 2 U10 auxiliary board control functions e g buffers control local interrupter reset logic etc 3 U11 the 101 Release 1 3a MPCS21ADS Revision A User s Manual Support Information 1 U7 Debug Port Controller
53. TABLE 5 5 TABLE 5 5 P5 Interconnect Signals Pin No Signal Name Attribute Description 1 VFLSO Visible history FLushes Status 0 Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alternate function 2 SRESET Soft Reset line of the Active low Open Drain 3 GND Ground 4 DSCK Debug Serial Clock Over the rising edge of which serial date is sampled by the MPC from DSDI signal Over the falling edge of which DSDI is driven towards the MPC and DSDO is driven by the MPC Configured on the MPC s JTAG port When the debug port controller is on the local MPC or when the ADS is a debug port controller for a target system OUTPUT when the ADI bundle is disconnected from the ADS INPUT 5 GND Ground 6 VFLS1 See VFLSO 7 HRESET yo Hard Reset line of the MPC Active low Open Drain 8 DSDI Debug Serial Data In of the debug port Configured on the MPC s JTAG port When the debug port controller is on the local MPC or when the ADS is a debug port controller for a target system OUTPUT when the ADI bundle is disconnected from the ADS INPUT 9 V3 3 3 3V Power indication This line is merely for indication No significant power may be drawn from this line 10 DSDO Debug Serial Data Output from the Configured on the MPC s JTA
54. In this file 6 Added board revision at BCSR3 0 ENG UN 1 BILOT x 2 m A Flash Presence detect lines added FlashPD 7 5 Changed polarity of Power On Reset now active high DramEn becomes active low to enhance debug station support changes module cnt_reg6 title MPC821ADS Board Control and Status Register x Device declaration U11 device mach220a
55. CC Ck KKK KK k k x lt KK Data Bits Assignments WK lt KKK KKK k k k x KK ERB DATA D0 DATA BIT D1 RSV2 DATA BIT D2 BDIS DATA BIT D3 BPS DATA BIT D4 D5 RSV6 DATA BIT D6 ISB DATA BIT D7 D8 DBGC DATA BIT D9 D10 DBPC DATA BIT D11 D12 RSV13 DATA BIT D13 RSV14 DATA BIT D14 RSV15 DATA BIT D15 Control Register 1 definitions 150 Release 1 3a MPCS21ADS Revision A User s Manual Support Information WK ck lt CC CC KKK KKK KKK KK KK KKK KK HALF WORD 0 ETH ENABLED DRAM_ENABLED ETH LOOP 1 PSQEL 0 TP_FULL_DUP
56. Capacitor 10nF 50V 10 NPO VITRAMNON VJ1210A103KXAT SMD 1210 Ceramic 95 Release 1 3a Support Information TABLE 5 14 MPC821ADS Part List MPCS21ADS Revision A User s Manual Reference Designation Part Description Manufacturer Part C3 Capacitor 4 7uF 20V 1096 SMD SIEMENS B45196 H4106 K30 Size B Tantalum C6 C13 C15 C17 C18 C90 C91 Capacitor 10uF 20V 10 SMD SIEMENS B45196 H4475 K20 C98 Size C Tantalum C7 Capacitor 100pF 50V 10 SMD SIEMENS B37871 K5101K 1206 Ceramic C9 C11 C55 C97 Capacitor 100uF 10V 10 SMD SIEMENS B45196 H2107 K10 Size D Tantalum C20 C61 C80 C92 Capacitor 1uF 25V 10 SMD SIEMENS B45196 H5105 K10 Size A Tantalum C31 C37 Capacitor 68pF 50V 5 SMD SIEMENS B37871 K5680J 1206 Ceramic C43 Capacitor 3900pF 50V 5 SIEMENS B37949 K5392J COG SMD 1210 Ceramic C44 Capacitor 0 039uF 50V 5 SMD SIEMENS B37872 K5393J 1206 Ceramic C75 C79 Capacitor 10pF 50V 10 COG AVX AV12065A100KATOOJ SMD 1206 Ceramic C85 Capacitor 5000pF 50V 10 AVX AV12065C 502K A700J SMD 1206 Ceramic C86 Capacitor 0 680 20V 10 SIEMENS 45196 4684 9 SMD Size Tantalum D1 D2 D3 D4 Diode SMD Motorola LL4004G D5 Zener Diode 5V SMD Motorola 1SMC5 0AT3 D6 D7 Diode Pair common cathode Motorola MBRD620CT D8 Zener Diode 12V SMD Motorola 1SMC12AT3 DS1 DS2 Dip Switc
57. 4 FFFFCC85 6 X OOFFECOC X 5 7 X 03FFEC00 X X 8 OOFFEC44 X 9 33BFCC47 X A OCFFCC44 X X B OOFFEC04 X X OOFFECOO X D 3FFFEC47 X E X X X X 25 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 6 UPMA Initializations for 0 EDO DRAMs 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 8FFBEC24 8FFFEC24 8FFFCC24 8FFFCC24 COFFCC84 33FFCCO7 SERES 1 4 OFFBEC04 OFEFCC04 OFEFCC04 OOFFCC04 X 2 OCF3EC04 OCF3EC04 OCAFCCOO OCAFCCOO 07FFCC04 X 3 00F3EC04 11BFCC47 SFFFCCO6 X 4 00F3EC00 OCFSECOO X OCAFCCOO FFFFCC85 5 7 OOF3EC4C X 03AFCC4C FFFFCC05 6 X OCFSECOO X OCAFCCOO X 7 X OOF3EC4C X 03AFCC4C X 8 OCFSECOO OCAFCCOO X 9 00F3EC44 33BFCC4F X A 03F3EC00 X X B 3FF7EC47 X X C X X D X X E X X F X X 20 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 7 UPMA Initializations for 70 EDO DRAMs 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C Contents 0 8FFBC
58. RS232_ENABLE PCC_ LE ENABLE PCC_VCC_ON PCC_VCC_OFF PCC VPP 0 0 12 VPP 5 1 MPE TS FLASH ENABLED 0 PCC VCC ON INF_RED_ENABL ded to be defined arlier FLASH CFG ENABLE 0 DRAM_5V 0 DRAM_3V DRAM 5V CNT REG EN PROTECT 0 151 n inadvertant write protect Release 1 3a MPCS21ADS Revision A User s Manual Support Information Power On Defaults Assignments ifdef DRAM 8 BIT OPERATION HALF WORD PON DEFAULT HALF WORD ifndef DRAM 8 OPERATION HALF WORD PON DEFAULT HALF WORD ETH ENABLE PON DEFAULT ETH ENABLED DRAM NABLE PON DEFAULT DRAM ENAB 11 CONT REG ENABLE PON DEFAULT CONT REG ENABLE RS232 ENABLE PON DEFAULT RS232 ENABLE PCC ENABLE PON DEFAULT
59. Ck W ck k Ck Ck k k In this file 4 the polarity of address selection lines is reversed so that ON the switch represent address line at high and vice versa W ck KKK KKK KKK KKK KKK KKK x lt x x lt lt KK KKK In this file 3 the 2 is not reset at all so it can be used to sync pda reset signals inside Added consideration for reset generated by the pda x when pda is reset 1 its hard soft reset signals are asserted it is not allowed for the host to initiate data transfer towards the It can however access the control status register to either change parameters or check for status The status of reset signals is added to the status register so it can be polled by the host module dbg prt6 title MPC821ADS Debug Port Controller
60. KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON JTAG then DEBUG PORT ON JTAG else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT RESERVED amp KA PON RESET 4 DBPC PON DEFAULT DEBUG PORT NON EXISTANT KA PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG PORT RESERVED else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT ON DEBUG PINS amp KA PON RESET 4 DBPC PON DEFAULT DEBUG PORT NON EXISTANT KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS then DEBUG PORT ON DEBUG PINS else Release 1 3a MPCS21ADS Revision A User s Manual Support Information EBUG PORT NON EXISTANT state DEBUG PORT RESERVED if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp PON RESET DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON JTAG then DEBUG PORT ON JTAG else if PDA WRITE CONFIG REG amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp PON RESET 4 DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT NON EXISTANT then DEBUG PORT NON EXISTANT else if PDA WRITE CONFIG REG amp
61. enables T S NMI pin NMI 44 istype com Actual NMI pin O D Power On Reset Configuration Support ModIn PIN 64 MODCK dip switch Modck2 PIN 60 istype com MODCK2 output Modck1 PIN 66 istype com MODCK1 output ModckOe NODE istype com enables MODCKs towards PDA during Hard Reset 129 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Data Buffers Enables and Reset configuration support
62. state_diagram InfRedEn state RED ENABL if PDA_WRITE_CONTROL_REG1 6 166 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ENABLE DATA BIT pin INF RED ENABLE amp PON RESET INF RED ENABLE PON DEFAULT INF RED ENABLE 4 KA PON RESET amp INF RED ENABLE PON DEFAULT INF RED ENABLE then INF RED ENABLE else INF RED ENABLE state INF RED ENABLE if PDA WRITE CONTROL amp INF RED ENABLE DATA BIT pin INF RED ENABLE amp KA PON RESET INF RED ENABLE PON DEFAULT RED ENABLE KA PON RESET amp INF RED ENABLE PON DEFAULT INF RED ENABLE then INF RED ENABLE else INF RED ENABLE W lt k k C Ck lt x x k Ck x
63. ADS REQ ACTIVE 1 The other state is ADS_REQ ACTIVE HOST_READ_ADT AdsSelect fb BOARD IS SELECTED 8 DS HstAck fb HOST ACK ACTIVE amp AdsReq ADS REQ ACTIVE amp HstReq HOST REQ ACTIVE HOST READ ADI DATA AdsSelect fb BOARD IS SELECTED amp DS HstAck fb HOST ACK ACTIVI gt HstReq HOST REQ ACTIVE 6 AdsReq ADS REQ ACTIVE amp D_C DATA HOST READ ADI CONTROL AdsSelect fb BOARD IS SELECTED amp DS HstAck fb HOST ACK ACTIVE amp HstReq HOST ACTIVE amp AdsReq ADS REQ ACTIVE amp D_C CONTROL 111 Release 1 3a ADS_SEND_STATUS MPCS21ADS Revision A User s Manual Support Information ECT AdsSelect fb BOARD IS SEL ED DS HstReq fb HOST REO ACTI D_C CONTROL amp AdsACk ADS ACTIVI 1 IS_STATUS_REQUEST ADI Data Bus definitions VE ck ck lt CC Ck KKK
64. KKK x KKK KK KK ADS HARD RESET ACTIVE 1 ADS_SOFT_RESET_ACTIVE 1 AdsAck Logic definitions HOST REQ ACTIVE 1 ADS ACK ACTIVE 1 The other state is ADS ACK ACTIVI HOST ACK ACTIVE 1 HOST WRITE ADI AdsSelect fb BOARD IS SELECTED amp DS HstReq fb HOST REQ ACTIVE amp AdsAck ADS ACK ACTIVE amp HstAck HOST ACK ACTIVE HOST WRITE ADI CONTROL AdsSelect fb BOARD IS SELECTED amp DS HstReq fb 5 REO ACTIVE gt AdsAck ADS ACK ACTIVE amp D_C CONTROL amp S CONTROL 6 HstAck HOST_ACK_ACTIVI GI 109 Release 1 3a HOST WRITI HOST WRIT E COMPL MPCS21ADS Revision A User s Manual E ADI DATA Support Information AdsSelect fb BOARD
65. PCMCIA Address line 0 30 PCCDO PCMCIA Data line 0 31 PCCD1 PCMCIA Data line 1 32 PCCD2 PCMCIA Data line 2 33 WP Write Protect indication from the PC Card 34 GND Ground 35 GND Ground 36 CD1 Card Detect 1 Active low Indicates in conjunction with CD2 that a PC Card is placed correctly in socket 37 PCCD11 PCMCIA Data line 11 38 PCCD12 PCMCIA Data line 12 39 PCCD13 PCMCIA Data line 13 40 PCCD14 PCMCIA Data line 14 41 PCCD15 PCMCIA Data line 15 42 BCE2A PCMCIA Chip Enable 2 Active low Enables ODD numbered address bytes 43 VS1 Voltage Sense 1 from PC Card Indicates in conjunction with VS2 the operation voltage for the PC Card 44 IORD Read Active low Drives data bus during I O Cards read cycles 45 IOWR Write Active low Strobes data to the PC Card during Card write cycles 46 PCCA17 0 PCMCIA Address line 7 47 PCCA18 0 PCMCIA Address line 18 48 PCCA19 PCMCIA Address line 19 49 PCCA20 PCMCIA Address line 20 65 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 50 PCCA21 PCMCIA Address line 21 51 PCCVCC VCC for the PC Card Switched by the MPC821ADS via BCSR1 52 PCCVPP 12V 5V VPP for the PC Ca
66. ResetConf RESET CONFIG ACTIVE FlashCfgEn FLASH ENABLE Register Access definitions CONFIG REG ADD 0 CONTROL REG ADD 1 STATUS_REG1_ADD 2 PDA WRITE CONFIG REG BrdContRegCs 6 TA amp R_W amp 28 amp A29 6 CntRegEn PDA_WRITE_CONTROL_REG1 BrdContRegCs amp TA amp R_W amp A28 amp A29 amp CntRegEn PDA WRITE CONTROL REG2 BrdContRegCs 6 TA amp R_W 6 228 6 29 6 CntRegEn PDA READ BrdContRegCs amp R_W amp CntRegEn PDA READ CONFIG REG BrdContRegCs 6 R W amp A28 amp A29 amp CntRegEn PDA_READ_CONTROL_REG1 BrdContRegCs amp R_W amp A28 amp A29 6 CntRegEn PDA_READ_STATUS_REG1 BrdContRegCs amp
67. x lt lt lt state_diagram FlashCfgEn state FLASH CFG ENABLE if PDA WRITE CONTROL 1 amp FLASH CFG ENABLE DATA BIT pin FLASH CFG ENABLE amp PON RESET FLASH ENABLE PON DEFAULT FLASH ENABLE KA PON RESET amp FLASH CFG ENABLE PON DEFAULT FLASH CFG ENABLE then FLASH ENABLE else FLASH CFG ENABLE state FLASH CFG ENABLE if PDA WRITE CONTROL 6 FLASH CFG ENABLE DATA BIT pin FLASH CFG ENABLE amp KA PON RESE FLASH CFG ENABLE PON DEFAULT FLASH CFG ENABLE 4 KA PON RESET amp FLASH CFG ENABLE PON DEFAULT FLASH CFG ENABLE then FLASH CFG ENABLE else FLASH CFG ENABLE To avoid in advertant wri gt d te to the Control Register result inan In order of writing the C gt must b gt again to protected mode ontrol Register Enable thi Enable bit which might power the board protection logic is provided s bit in the status register negated After any write to the control register this bit asserts
68. x lt kk ck KKK x x x x lt KKK state_diagram PccEn state PCC_ENABLE if PDA_WRITE_CONTROL_REG1 amp PCC ENABLE DATA BIT pin PCC ENABLE 6 KA PON RESET 4 PCC ENABLE PON DEFAULT PCC ENABLE KA PON RESET amp PCC ENABLE PON DEFAULT PCC ENABLE then PCC ENABLE else PCC ENABLE state PCC ENABLE if PDA WRITE CONTROL 6 PCC ENABLE DATA BIT pin PCC ENABLE amp PON RESET ENABLE PON DEFAULT PCC ENABLE KA PON RESET amp PCC ENABLE PON DEFAULT PCC ENABLE then PCC ENABLE else ENABLE 169 Release 1 3a MPCS21ADS Revision A User s Manual Support Information KK x k x KKK KKK KKK KKK CC CC Ck lt VE ck ck state diagram PccVccOn state PCC VCC ON if PDA WRITE CONTROL 1 amp PCC VCC DATA BIT pin PCC VCC ON amp KA PON RESET PCC VCC PON DEFAULT PCC VCC ON
69. 1 Host write to adi In that case AdsAck is ASSERTED only after that timer expired 2 Host read from adi In that case AdsReq is NEGATED after that timer 1 expired ensuring enough time for data propagation over the bundle The timer is async reset when both soft and hard reset is applied to the i f The timer is sync reset a clock after it expires Count starts when either HstReq or HstAck are detected asserted after proper synchronization The value upon which the terminal count is asserted is in the control register When the interface is reset by the host this value defaults to its upper bound Using the diagnostic loop back mode this value may be re established for optimal performance by means of test amp error VE ck ck CC Ck x x KKK Ck kk KKK x x x x lt KK equations BndDly ar Reset BndDly clk 2 when HOST WRITE ADI CONTROL HOST READ ADI CONTROL I HOST WRITE ADI DATA HOST READ ADI DATA amp PdaRst fb amp BndTmrExp fb then BndDly BndDly fb 1 else BndDly 0 BndTmrExp BndDly fb 3 BundleDelayField fb amp AdsAck delay field active low 115 Release 1 3a MPCS21ADS Revision A U
70. state_diagram TxError state TX_DONE_OK if STATE_TX_ENABLED amp PdaRst fb then TX_INTERRUPTED else TX_DONE_OK state TX_INTERRUPTED if HOST_WRITE_ADI_CONTROL amp BndTmrExp fb amp PD6 pin HOST_WRITE_ADI_DATA amp BndTmrExp fb amp PdaRst fb then TX_DONE_OK else TX_INTERRUPTED dbg prt6 125 Release 1 3a MPCS21ADS Revision A User s Manual Support Information 2 U10 Auxiliary Board Control In this file 5 1 The use of BCLOSE is removed This due to the assignment us BCLOSE to GPL4A In order of using of GPL4A bit in the upm to determine data sampling edge GPL4A may not be used as a GPL Therefore DramBankXCs or must envelope the cycle so that data buffers remain open throughout the TA cycle 2 Removed CS support for flash configuration I e FlashCsl will not be TK asserted during hard reset Flash configuration will be supported on Ns Silicon next revisions e data buffers will still open for flash configuration when hard reset asserted and
71. CC lt x KKK KKK KK x x lt KKK protected by CntRegEnProtect to prevent from inadvertant write state_diagram CntRegEn state CONT_REG_ENABLE if PDA_WRITE_CONTROL_REG1 amp CntRegEnProtect fb CNT_REG_EN_PROTECT amp 16 CONT REG ENABLE DATA CONT REG ENABLE 6 PON RESET CONT REG ENABLE PON DEFAULT CONT REG ENABLE KA PON RESET amp CONT REG ENABLE PON DEFAULT CONT REG ENABLE then CONT REG ENABLE else CONT REG ENABLE state CONT REG ENABLE in fact not applicable if PDA WRITE CONTROL 6 CONT REG ENABLE DATA BIT pin CONT REG ENABLE amp PON RESET CONT REG ENABLE PON DEFAULT CONT REG ENABLE KA PON R
72. HostVcc HstEn Select Logic definitions VE ck ck ck lt lt CK Ck lt CK x KKK KKK KKK KK KK x lt x KKK 108 Release 1 3a MPCS21ADS Revision A User s Manual Support Information HOST 000 ACTIVE e n HOST_EN _ACTIVE HOST_IS_ON HstEn HOST EN ACTIVE amp HostVcc HOST VCC ACTIVE HOST IS OFF HOST IS ON BOARD IS SELECTED 0 ADS IS SELECTED AdsSelect fb BOARD IS SELECTED Data Cntrl line levels DATA 1 CONTROL DATA lt lt Reset Logic definitions WK lt KKK KKK x x lt lt KKK
73. LD2 When the yellow FLASH ON led is lit it indicates that the FLASH module is enabled in the BCSR1 register l e any access done to the 50 address space will hit the flash memory When it is dark the flash is disabled and CS0 may be used off board via the expansion connectors 3 2 9 DRAM ON LD3 When the yellow DRAM ON led is lit it indicates the DRAM is enabled in BCSR1 Therefore any access made to CS1 or CS2 will hit on the DRAM When it is dark it indicates that either the DRAM is disabled in BCSR1 enabling the use of CS1 and CS2 off board via the expansion connectors 3 2 10 ETHON LD4 When the yellow ETH ON led is lit it indicates that the ethernet port transceiver the MC68160 EEST connected to SCC1 is active When it is dark it indicates that the EEST is in power down mode enabling the use of SCC1 pins off board via the expansion connectors 3 2 11 Ethernet RX Indicator LD5 The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the Ethernet port 3 2 12 Ethernet TX Indicator LD6 The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet port 3 2 13 Ethernet JABB Indicator LD7 The red Ethernet TP Jabber LED indicator JABB lights whenever a jabber condition is detected on the TP ethernet port 3 2 14 IRD LD8 A By a skilled technician only 18 Release 1 3a MPCS82I1ADS Revision A User s Ma
74. Since the dram simm requires RAS signals to be split due to high capacitive load and to allow 16 bit operation When working with 16 bit port size the double drive RAS signals are disabled equations RAS oe hf 1 DramBanklCs 8 DramBank2Cs amp DRAM ENABLED 140 Release 1 3a MPCS21ADS Revision A User s Manual Support Information IRas2 DramBank2Cs amp DramBankl1Cs 6 DRAM ENABLED amp SIMM36200 SIMM36800 1 DramBank1Cs 6 DramBank2Cs amp DRAM ENABLED 2 DramBank2Cs 6 DramBanklCs amp DRAM ENABLED amp SIMM36200 SIMM36800 Flash Chip Select
75. T S MPC s Address line 23 A29 A5 T S MPC s Address line 5 A30 GND B1 VCC MPC821ADS VCC plane B2 VCC MPC821ADS VCC plane B3 VCC MPC821ADS VCC plane 70 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 6 P6 Interconnect Signals Pin No Signal Name Attribute Description B4 DRM W O L In fact GPLOA GPLOB General Purpose Line 0 for UPMA or UPMB Used as a Write signal for the Dram B5 GND B6 TA VO L Transfer Acknowledge Not driven by on board logic B7 TS O L MPC Transfer Start driven only when the MPC is bus master T S B8 GND B9 BI I O L Burst Inhibit Not used on board T S B10 CS5 O L Chip Select 5 Not used on the ADS B11 GND 12 DRMCS1 O L In fact CS2 of the MPC Used for Dram bank 1 selection B13 GPL3 O L In fact GPL3A GPL3B CSSDD General Purpose Line 3 for UPMA or UPMB May also be used as Chip Select 3 Double Drive Not used within the ADS B14 GND B15 WEO O L In fact WEO BS B0 IORD GPCM Write Enable 0 or UPMB Byte Select 0 or PCMCIA I O Read Used to qualify write cycles to the Flash memory and as I O Read for the PCMCIA channel B16 EDOOE O L In fact OE GPL1A GPL1B GPCM Output Enable or UPMA General Purpose Line 1 or UPMB General Purpose Line 1 Used as an Output Enable for EDO Drams controlled by UPMA B17 GND B18 REG A
76. T S In fact TSIZO REG Transfer Size 0 or PCMCIA slot A REG Used with the PCMCIA port as Attribute memory select or I O space select B19 A30 T S MPC s Address line 30 B20 GND B21 A6 O T S MPC s Address line 6 B22 A12 O T S MPC s Address line 12 B23 GND B24 A16 O T S MPC s Address line 16 B25 A29 T S MPC s Address line 29 B26 GND B27 N C Not Connected B28 A3 O T S MPC s Address line 3 71 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 6 P6 Interconnect Signals 72 Signal Name Attribute Description B29 GND B30 AO O T S MPC s Address line 0 C1 VCG MPC821ADS VCC plane C2 VCG MPC821ADS VCC plane C3 VCG MPC821ADS VCC plane C4 VCG MPC821ADS VCC plane C5 BURST O T S Burst Transaction Indicator C6 GPL4A VO L UPWAITA GPL4A UPMA Wait signal UPMA General Purpose Line 4 Not used on ADS C7 GND C8 BCSRCS O L In fact Chip Select 1 Used as a Chip Select for the BCSR controlled by the GPCM May be used off board when BCSR is disabled C9 GPL5A O L UMPA General Purpose Line 5 Not used on the ADS C10 GND C11 CS6 O L in fact CS6 CE1 B Chip Select 6 or PCMCIA slot B CE1 Not used on the ADS C12 DRMCS2 O L In fact CS3 Selects the upper bank if exists of the Dram May be used off board if eithe
77. THE EEEH THE THE THE HEHEH T THE THERE THE THE Hy 7 C D 1 SC 0 D 7 U SIMULATION SLOW PLL LOCK DRAM 8 BIT OP 1 1 ERATION 1 Signal groups
78. the Infra Red transceiver connected to SCC2 is enabled When negated the Infra Red transceiver is put in shutdown mode And SCC2 pins are available for off board use via the expansion connectors RW 4 FLASH CFG EN Flash Configuration Enable When this bit is asserted low A the Hard Reset configuration held in BCSRO is NOT driven on the data bus during Hard Reset and B configuration data held at the 1 st word of the flash memory is driven to the data bus during Hard Reset P RW 5 CNT REG EN P ROTECT Control Register Enable Protect When this bit is active low the BCSR EN bit in that register can not be written When in active BCSR EN may be written to remove the BCSR from the memory map After any write to 1 this bit becomes active again This bit is a read only bit on that register 6 BCSR EN BCSR Enable When this bit is active low the Board Control amp Status Register is enabled on the local memory map When inactive the BCSR may not be read or written and its associated CS1 is available for off board use via the expansion connectors This bit may be written with 1 only if CNT REG EN PROTECT bit is negated 1 When the BCSR is disabled it still continues to configure the board according the last data held in it even during Hard Reset RW 7 RS232EN RS232 port Enable When asserted low the RS232 transceiver is enabled When negated the RS232 transceiver is in stan
79. 2 of J2 VDDL is supplied with 3 3V When a jumper is placed between positions 2 3 of J2 VDDL is supplied by 2V power source The jumper on J2 is factory set between positions 1 2 to supply 3 3 to VDDL FIGURE 2 5 VDDL Source Selection J2 J2 c X 1 VDDL 3 3V VDDL 2V 2 3 5 Keep Alive Power Source Selection J3 selects the Keep Alive power source of the MPC When a jumper is placed between positions 1 2 of J3 the Keep Alive power is fed from the main 3 3V bus When an external power source is to be connect ed to the Keep Alive power rail it should be connected between positions 2 the positive pole and position 3 GND of J3 A E g a battery 11 Release 1 3a MPCS82I1ADS Revision A User s Manual Hardware Preparation and Installation F IGURE 2 6 Keep Alive Power Source Selection J3 33V 1 3 3 1 x KAPWR KAPWR z o BR KAPWR From 3 3V KAPWR From Ext Ext Power Supply Power Supply 2 4 INSTALLATION INSTRUCTIONS When the MPC821ADS has been configured as desired by the user it can be installed according to the required working environment as follows Host Controlled Operation 2 4 1 Debug Port Controller for Target System Stand Alone Host Controlled Operation F In this configuration the MPC821ADS is controlled by a host computer via the ADI through the debug port IGURE 2 7 Host Controlled
80. Configured on the ADS as AT2 May be configured to alternate function A3 VF2 B3 IWP2 VF2 PCMCIA slot B Input Port 3 or Instruction Watch Point 2 or Visible Instruction Queue Flushes Status 2 Configured on the ADS as VF2 May be configured to alternate function A4 GND 5 IP_B7 PTR AT3 PCMCIA slot Input Port 7 Program Trace instruction fetch indication or Address Type 3 Configured on the ads as AT3 May be configured to alternate function A6 SPKROUT KR IRQ4 SPKROUT Kill Reservation input or Interrupt Request 4 input or PCMCIA Speaker Output Configured on the ADS as SPKROUT May be configured to alternate function A7 GND A8 POE_A O L In fact OP1 of the PCMCIA I F Enables address buffers towards the PC Card AQ BADDR29 Burst Address Line 29 Dedicated for external master support Used to generate Burst address during external master burst cycles A10 GND A11 KAPWR Keep Alive Power rail A12 WAIT_B This signal is PCMCIA slot wait signal Pulled up Not used otherwise A13 GND 74 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 7 P9 Interconnect Signals Pin No Signal Name Attribute Description A14 GND A15 GND A16 GND A17 BWP Buffered PCMCIA slot A Write Protect In fact IP A2 IOIS16A Used as PC card write protect indication or as
81. DI RSV6_ACTIVE PFA l EN RSV6_PON_DEFAUL RSV6 ACTIVE RSV6 ACTIVE Release 1 3a MPCS21ADS Revision A User s Manual Support Information state RSV2 ACTIVE if PDA WRITE CONFIG REG amp RSV6 DATA BIT pin RSV6 ACTIVE KA PON RESET RSV6 PON DEFAU KA PON RESET amp RSV6 PON DEFAULT RSV6 ACTIVE else RSV6 ACTIVE iT amp RSV6_AC F RSV6_AC E 4 then KK KKK x x KKK KKK KK Wk ck ck state_diagram ISB state INT_SPAC 5 0 00000000 if PDA WRITE CONFIG REG 6 ISB DATA BIT pin INT SPACE BASE 0x00F00000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE 0x00000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F00000 then INT SPACE BASE 0
82. Fl WK KK KKK ck ck Power On Reset Wk KKK lt lt lt KK KK FLASH_CFG_ENABLE K A PON RESET ACT DramPD2 DramPD1 ExtToolI0 ExtToolIl1 ExtToolI2 ExtToolIl3 PccVppG ashPD7 FlashPD6 FlashPD5 definitions K changed due ifndef SLOW_PLL KA_PON_RESET 147 0 1 0 to long lock delay of the pda 17 7 95 LOCK RGPORIn A PON RESET ACTIVI 1 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Qifdef SLOW PLL LOCK PON DEFAULT ACTIVE 0 KA PON RESET PonDefault PON DEFAULT 1 end of change amp RESET CONFIG DRIVEN
83. KA PON RESET amp PCC VCC PON DEFAULT PCC VCC ON then MG O else PCC_VCC_ON state PCC_VCC_ON if PDA_WRITE_CONTROL_REG1 amp PCC_VCC_DATA_BIT pin PCC_VCC_ON amp KA PON RESET 4 PCC VCC PON DEFAULT PCC VCC ON KA PON RESET amp PCC VCC PON DEFAULT PCC VCC ON then PCC VCC ON else PCC VCC ON state_diagram PccVpp state _ _0 if PDA WRITE CONTROL 6 PCC VPP DATA BIT pin PCC VPP 12 amp KA PON RESET VPP PON DEFAULT VPP 0 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 12 then PCC VPP 12 else if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP 5 amp KA PON RESET PCC VPP PON DEFAULT PCC VPP 0 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 5 then PCC VPP 5 else if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP TS amp KA PON RESET PCC VPP PON DEFAULT PCC VPP 0 KA
84. L p Parallel lt gt Serial Converter 4 DSDO To allow for an external debug port controller to be incorporated with the MPCADS and to allow target system debug by the ADS a standard 10 pin debug port connector P5 is provided and the local debug port controller may be disabled by removing the ADI bundle from the its connector P1 When the ADI s 37 lead cable is disconnected from either the ADI connector or from the MPCADS s 37 pin connector the debug port controller is disabled allowing either the connection of an external debug port controller or independent s w run i e the MPC boots from the flash memory to run user s application without debug port controller intervention This feature becomes especially handy regarding demo s The ADI I F supports upto 8 boards connected on the same bundle Address selection is done via 051 2 3 1 ADI Port Address Selection on page 9 The debug port I F has two registers a control status register and a data register The control status register hold I F related control status functions while the data register serves as the parallel side of the Transmit Receive shift register The control status register is accessed when D C bit is low while the data register is accessed when D C is driven high by the host via the ADI port See APPENDIX B ADI I F page 174 4 151 MPC821ADS As Debug Port Controller For Target System The MPCADS may be used
85. PCC ENABLE PCC VCC PON DEFAUL PCC VCC OFF PCC VPP PON DEFAUL PCC VPP TS FLASH ENABLE PON DEFAULT FLASH ENABLED INF RED ENABLE PON DEFAULT INF RED ENABLE FLASH CFG ENABLE PON DEFAULT FLASH CFG ENABLE CNT REG EN PROTECT PON DEFAULT CNT REG EN PROTECT Data Bits Assignments WK ck lt KKK KKK KKK KKK k k KK KK FLASH ENABLE DATA BIT 00 DRAM ENABLE DATA BIT D1 152 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ETH ENABLE DATA BIT D2 INF RED ENABLE DATA BIT D3 FLASH CFG ENABLE DATA BIT D4 CNT REG EN PROTECT DATA BIT D5 CONT REG ENABLE DATA BIT D6 RS232 ENABLE DATA BIT D7 PCC ENABLE DATA BIT D8 PCC VCC DATA BIT D9 PCC_VPP DATA D10 D11 HALF WORD DATA BIT D12
86. PCC VPP 5 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 12 then PCC VPP 12 else if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP TS amp KA PON RESET 4 PCC VPP PON DEFAULT PCC VPP 5 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP TS then PCC VPP TS else PCC VPP 5 state PCC VPP TS if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP 0 amp KA PON RESET 4 PCC VPP PON DEFAULT PCC VPP TS KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 0 then PCC VPP 0 171 Release 1 3a MPCS21ADS Revision A User s Manual Support Information else if PDA WRITE CONTROL 1 amp PCC VPP DATA BIT pin PCC VPP 12 amp KA PON RESET PCC VPP PON DEFAULT PCC VPP TS KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 12 then PCC VPP 12 else if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP 5 amp KA PON RESET PCC VPP PON DEFAULT PCC VPP TS KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 5 then PCC VPP 5 else PCC VPP TS
87. be used off board for any alternate function Appears also at P13 A10 GND 11 5 PA5 CLK3 TIN2 L1TCLKA BRGOUT2 Not used the ADS Appears also at P13 12 4 PA4 CLK4 TOUT2 Not used on the ADS Appears also at P13 79 Release 1 3 MPCS21ADS Revision A User s Manual Support Information TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description A13 GND A14 PA3 PA3 CLK5 TIN3 BRGOUTS Not used on the ADS A15 PA2 PA2 CLK6 TOUTS3 L1RCLKB BRGCLK2 Not used on the ADS A16 GND A17 PA1 PA1 CLK7 TIN4 BRGO4 Not used on the ADS A18 PAO PAO CLK8 TOUTA4 L1TCLKB Not used on the ADS A19 GND A20 SHIFT C 821 PD3 SHIFT CLK Not used on the ADS Appears also at P11 for convenient LCD connection A21 LDO MPC821 s PD7 LDO Not used on the ADS Appears also at P11 for convenient LCD connection A22 LD8 821 PD15 LD8 Not used on the ADS Appears also at P11 for convenient LCD connection A23 LD6 821 5 PD13 LD6 Not used on the ADS Appears also at P11 for convenient LCD connection A24 GND A25 NMI VO L Non Makable Interrupt In fact IRQO of the MPC Driven by on board logic by O D gate May be driven off board by O D gate only B1 GND B2 ETHRX Ethernet port Receive Data In fact PA15 RXD1 When the Ethernet port
88. e Card VCC appliance Card VPP appliance 11 Dram Type Size and Delay Identification 12 Flash Size Delay Identification 13 External off board tools identification or S W option selection switch DS2 status 1 Since most of the MPCADS s modules are controlled via the BCSR and since they be disabled in favor of external hardware the enable signals for these modules are presented at the expansion connector so that off board hardware may be exclusive or enabled with on board modules 4 141 Disable Protection Logic The BCSR itself may be disabled in favor of off board logic To avoid accidental disable of the BCSR an event from which only power down recovers a protection logic is provided The BCSR_EN bit resides on BCSR1 This bit wakes up active low during power up and may not be changed unless BCSR_EN_PROTECT bit BCSR3 is written with 1 previously After the BCSR_EN_PROTECT is written with 1 to unprotect the BCSR_EN bit there is only one shot at disabling the BCSR since immediately after any write to BCSR1 BCSR_EN_PROTECT is re activat ed BCSR EN is re protected and the disabling procedure has to be repeated if desired 4 14 2 BCSRO Hard Reset Configuration Register BCSRO is located at offset 0 on BCSR space It may be read or written at any time BCSRO gets its defaults upon MAIN Power On reset During Hard Reset data contained in BCSRO is driven on
89. x x PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PIN 66 60 67 59 58 57 56 55 data bus 1 0 Clock gen pins SYSCLK PIN 15 System clock IN Clkout2 12 istype reg buffer System clock divided by 2 Clk4 PIN 14 istype reg buffer System clock divided by 4 Out Out for testing may be node C1k2 PIN 16 Connected to Clkout externally In x Misc
90. 00 00000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE OxFF000000 amp KA PON RESET 4 ISB PON DEFAULT INT SPACE BASE 0x00000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFF000000 then INT SPACE BASE OxFF000000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE OxFFF00000 amp KA PON RESET 4 ISB PON DEFAULT INT SPACE BASE 0x00000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFFF00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE 0x00000000 state INT SPACE BASE 0x00F00000 if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE 0x00000000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE 0 00 00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE OxFF000000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE 0x00F00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFF000000 then 158 Release 1 3a MPCS21ADS Revision A User s Manual Support Information
91. 2 3 12 Added 3 Flash memory Presence Detect lines F PD 5 7 to BCSR U11 65 67 ENG U10 to support varying flash memory delays Sh 3 4 11 Added support for SMART flash simms e 12 VPP connected to SIMM BA10 connected also to the SIMM to support 1M X 8 devices Sh 4 BCSR power on reset logic was changed to support board s power up recovery when keep alive power remained active Sh 3 9 Power on reset logic changes power on reset is not driven by 010 ENG U9 but directly to the MPC e Added 14 023 powered by KAPWR to support this AC14 s s t is required for mach connection due to slow rise time of PORST D3 and R12 powered from from the same reason Added option for PON reset by main 3 3V bus J1 Release 1 3a MPCS82I1ADS Revision A User s Manual General Information Sh 3 9 9 BA9 and 10 are connected to 010 ENG U9 instead of BA11 and 12 for flash bank se lection Bug correction Sh 3 10 Renewed support for 32Khz crystal e CLKAIN is gated UA38 so when working with 32768 Hz crystal CLK4IN is driven constantly to 0 This to avoid clock jitter with this mode of operation Parallel resistor increased to 20MQ Sh 7 11 PLL s XFC capacitors were changed to react for formula change Lower MF range capacitor is changed to 5nF to cover 1 5 to 1 10 MF range while higher MF range capacitor was changed to 0 68uF to cover 1 4
92. ACK ACTIVE else ADS ACK ACTIVI BJ ET state ADS ACK ACTIVE if DS_HstReq fb HOST_REQ_ACTIVE then ADS ACK ACTIVI else ADS_ACK_ACTIV ET 116 Release 1 3a MPCS21ADS Revision A User s Manual Support Information WK ck Ck x KKK KKK KKK KK lt x lt KKK Transmit Enable logic Enables transmit of serial data over DSDI and generation of serial clock over DSCK Transmission begins immediately after data written by the host is latched into the transmit shift register and ends after 7 shifts were made to th tx shift register Termination is done using a 4 bit counter TxWordLength which has a terminal count and reset TxWordEnd equations xEn ar Reset xEn clk 1 2 to provide 1 2 clock resolution state_diagram TxEn state TX_DISABLED if HOST_WRITE_ADI_DATA amp BndTmrExp fb amp PdaRst fb then TX_ENABLED else TX_DISAB state TX_ENABLE
93. Appears also at P13 A10 ETHRCK Ethernet Port Receive Clock In fact PA7 CLK2 TOUT1 BRGCLK1 When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function Appears also at P13 11 5 PA5 CLK3 TIN2 L1TCLKA BRGOUT2 Not used on the ADS Appears also at P13 A12 PA4 PA4 CLK4 TOUT2 Not used on the ADS Appears also at P13 A13 PA3 PAS CLKS TINS BRGOUTS Not used the ADS A14 PA2 PA2 CLK6 TOUT3 L1RCLKB BRGCLk2 Not used on the ADS A15 PA1 PA1 CLK7 TIN4 BRGO4 Not used on the ADS A16 PAO y o PAO CLK8 TOUT4 L1TCLKB Not used on the ADS A17 VCG i A18 PA11 PA11 L1TXDB Not used on the ADS Appears also at P13 A19 PA10 PA10 L1RXDB Not used on the ADS Appears also at P13 A20 9 PA9 L1TXDA Not used on the ADS Appears also at P13 91 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 13 P13 Interconnect Signals Pin No Signal Name Attribute Description A21 PA8 PA8 L1RXDA Not used on the ADS Appears also at P13 A22 GND A23 GND A24 IRQ7 Interrupt Request 7 The lowest priority interrupt request line Not used on the ADS A25 IRQ6 FRZ IRQ6 Freeze debug mode indication or Interrupt Request 6 Configured on the ADS as IRQ6 Not by ADS logic may be configured to alternate function if IRQ6 is n
94. BRG Clock gt gt gt As seen in FIGURE 4 1 Refresh Scheme above the BRG clock is twice divided once by the Pe riodic Timer Prescaler and again by another prescaler the PTA dedicated for each UPM If there are more than one dram banks than refresh cycles are performed for consecutive banks therefore refresh should be made faster The formula for calculation of the PTA is given below Refresh Period X Number Of Beats Per Refresh Cycle Number Of Rows To Refresh X T BRG XMPTPR X Number Of Banks PTA Where PTA Periodic Timer A filed in MAMR The value of the 2 nd divider Refresh Period is the time usually in msec required to refresh a dram bank Number Of Beats Per Refresh Cycle using the looping capability it is possible to perform more than one refresh cycle per refresh burst in fact upto 16 Number Of Rows To Refresh the number of rows in a dram bank T BRG the cycle time of the BRG clock MPTPR the value of the periodic timer prescaler 2 to 64 Number Of Banks number of dram banks to refresh If we take for example a MCM36200 SIMM which has the following data Refresh Period 16 msec e Number Of Beats Per Refresh Cycle on the ADS it is 4 Number Of Rows To Refresh 1024 T 40 nsec 1 2 system clock 50 M
95. HardReset drives RSTCONF to pda DriveConfig ConfigHoldEnd fb drives configuration data on the bus NMI generation equations NMI oe NMIE 5 NMI 0 O D NMIEn RstDebl fb amp AbrDebl fb only abort button depressed local data buffers enable Wk ck ck KKK x lt KKK KKK KK KKK KK KKK KK KK equations 137 R
96. Inc 15 Release 1 3a MPCS21ADS Revision A User s Manual Hardware Preparation and Installation FIGURE 2 13 P3 RS 232 Serial Port Connector CD TX RX DTR GND DSR RTS CTS N C OON ON NOTE The RTS line 7 is not connected the MPC821ADS 2 4 9 Memory Installation The MPC821ADS is supplied with two types of memory SIMM Dynamic Memory SIMM Flash Memory SIMM To avoid shipment damage these memories are packed aside rather than being installed in their sockets Therefore they should be installed on site To installa memory SIMM it should be taken out of its package put diagonally in its socket no error can be made here since the Flash socket has 80 contacts while the DRAM socket has 72 and then twisted to a vertical position until the metal lock clips are locked See FIGURE 2 14 Memory SIMM Installation below CAUTION The memory SIMMs have alignment nibble near their 1 pin It is important to align the memory correctly before it is twisted otherwise damage might be inflicted to both the memory SIMM and its socket FIGURE 2 14 Memory SIMM Installation 1 2 Memory Metal Lock SIMM Socket 16 Release 1 3a MPCS21ADS Revision A User s Manual OPERATING INSTRUCTIONS 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides necessary information to use the MPC821ADS in host controlled and stand alone configurations This inc
97. Operation Scheme This configuration allows for extensive debugging using on host debugger 5V Power Suppl E 2 4 2 Debug Port Controller For Target System This configuration resembles the previous but here the local MPC is removed from its socket while the ADS is connected via a 10 lead Flat Cable between P5 and a matching connector on a target system 12 Release 1 3a MPCS82I1ADS Revision A User s Manual Hardware Preparation and Installation WARNING When connecting the ADS to a target system via P5 and a 10 lead flat cable the MPC MUST be REMOVED from its SOCKET U18 Otherwise PERMANENT DAMAGE might be inflicted to either the Local MPC or to the Tar get MPC With this mode of operation all on board modules are disabled and can not be accessed in anyway except for the debug port controller Also all indications except for 5V power 3 3V power and RUN are darkened All debugger commands and debugging features are available in this mode including s w download breakpoints etc The target system may be reset or interrupted by the debug port or reset by the ADS s RESET switches It is the responsibility
98. RSV2 ACTIVE if PDA WRITE CONFIG REG amp RSV2 DATA BIT pin RSV2 ACTIVE KA PON RESET RSV2 PON DEFAULT KA PON RESET RSV2 PON DEFAUL RSV2 ACTIVE else RSV2 ACTIVE ET RSV2 ACTIVE RSV2 ACTIVE then amp RSV2 ACTIVE RSV2 ACTIVE then state_diagram BDIS state BOOT_ENABLE if PDA_WRITE_CONFIG_REG amp BDIS_DATA_BIT pin BOOT_DISABLE amp KA_PON_RESET BDIS_PON_DEFAULT BOOT_ENABLE KA PON RESET BDIS PON DEFAULT BOOT DISABLE then BOOT DISABLE else BOOT ENABLE state BOOT DISABLE if PDA WRITE CONFIG REG amp BDIS DATA BIT pin BOOT ENABLE KA PON RESET BDIS PON DEFAULT BOOT DISABLE KA PON RESET amp BDIS PON DEFAULT BOOT ENABLE then BOOT ENABLE else BOOT DISABLE
99. RSV2 fb BDIS fb BPSO fb BPS1 fb RSV6 fb ISBO fb ISBl fb DBGCO fb DBGCl1 fb DBPCO fb DBPCl fb RSV13 fb RSV14 fb RSV15 fb else when PDA READ CONTROL REG1 then Data ReadContRegl1 else when PDA_READ_STATUS_REG1 then Data FlashPD4 FlashPD3 FlashPD2 FlashPD1 DramPdEdo DramPD4 DramPD3 DramPD2 DramPD1 ExtToolI0 ExtToolIl ExtToolI2 ExtToolI3 PccVppG 0 0 else when PDA READ STATUS REG2 then Data 0 0 0 0 0 0 0 0 0 FlashPD7 FlashPD6 FlashPD5 0 0 1 0 revision number 1 pilot end cnt reg6 173 Release 1 3a MPCS21ADS Revision A User s Manual Support Information APPENDIX B ADI I F The ADI parallel port supplies parallel link from the MPCADS to various host computers This port is con nected via a 37 line cable to a special board called ADI Application Development Interface installed in the host computer Four versions of the ADI board are available to support connection to IBM PC XT AT MAC VMEbus computers and SUN 4 SPARC stations It is possible to connect the MPC281ADS board to these computers provided that the appropriate software drivers are installed on them Each MPC281ADS can have 8 possible slave addresses set for its ADI port enabling up to 8 MPC281ADS boards to be connected to the same ADI board The ADI port connector is a 37 pin male D type connector The connection between the MPC281ADS and the host computer is by a 37 line
100. Serial Port Connector DCD 1 7 2 6 DSR 7 RTS le alors 9 N C GND 5 4 11 1 RS 232 Port Signal Description In the list below the directions O and 1 are relative to the MPCADS board l e means input to the MPCADS e CD O Data Carrier Detect This line is always asserted by MPCADS TX O Transmit Data 1 Receive Data e 1 Data Terminal Ready This signal be used by the software in the MPCADS to 44 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description detect if a terminal is connected to the MPCADS board DSR O Data Set Ready This line is always asserted by the MPCADS e 1 Request To Send This line is not connected on MPCADS e CTS O Clear To Send This line is always asserted by MPCADS 4412 PCMCIA Port To enhance PCMCIA i f development a dedicated PCMCIA port is provided with the MPCADS Support is given to 5V only PC Cards PCMCIA standard 2 1 compliant All the necessary control signals are gen erated by the MPC itself To protect MPC signals from external hazards and to provide sufficient drive ca pability a set of buffers and latches is provided over address data amp strobe lines To conform with the design spirit of the ADS i e making as much as possible MPC resources available for external application development input buffers are provided for input control signa
101. allow for external hardware development via dedicated expansion connectors P6 P9 P10 amp P12 4 2 Reset amp Reset Configuration There are several reset sources on the MPCADS 1 Keep Alive Power On Reset 2 Main Power On Reset 3 Manual Soft Reset 4 Manual Hard Reset 5 Debug Port Soft Reset 6 Debug Port Hard Reset 7 MPC Internal Sources 4 2 1 Keep Alive Power On Reset The Keep Alive Power On Reset on the MPC821ADS is generated by a dedicated voltage detector made by Seiko the S 8051HN CD X with detection voltage range of 1 795 to 2 005V This voltage detector is con nected to the Keep Alive power input of the MPC and during keep alive power on or when there is a voltage drop of that input into the above range and J1 is set accordingly see 2 3 3 Power On Reset Source Se lection on page 10 Power On Reset is generated i e PORESET input of the MPC is asserted for period of approximately 4 sec When PORESET is asserted to the MPC the Power On reset configuration is made available to MPC See 4 2 6 1 Power On Reset Configuration on page 35 4 2 2 The Main power on reset generates HARD reset and optionally PON reset when the MAIN 3 3V bus is powered on or there is a drop of voltage level over this bus The reset is generated by a dedicated voltage detector made by Seiko the S 8052ANY NH X with detection voltage range of 2 595 to 2 805V When regular power on r
102. among the internal banks is done via on board programmable logic according to the Presence Detect lines of the Flash SIMM inserted to the ADS FIGURE 4 3 Flash Memory SIMM Architecture Flash Presence Detect Lines M29F040 M29F040 M29F040 M29F040 or 1 8 1M X8 1 8 1 8 29 040 M29F040 M29F040 M29F040 X8 F_CS1 F_CS2 1 8 1MX8 1 8 1M CS0 gt U09 CS3 M29F040 I M29F040 29 040 M29F040 F CS4 29 040 29 040 M29F040 M29F040 L gt DATA MCM29F020 MCM29F040 MCM29F 080 SM732A1000A SM732A2000 The access time of the Flash memory supplied with the ADS is 120 nsec however 90 nsec devices may 42 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description be used Reading the delay section of the Flash SIMM Presence Detect lines the debugger establishes via ORO the correct number of wait states considering 50MHz system clock frequency The Motorola parts which built of 29 0 0 devices are 5V programmable i e there is no need for external programming voltage and the flash may be written almost as a regular memory The SMART parts however require 12V 0 596 programming
103. as a debug port controller for a target system provided that the target system A The debug port location is determined by the HARD Reset configuration B See APPENDIX B ADI I F on page 174 for further information 56 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description has a 10 pin header connector matching P5 See TABLE 5 5 P5 Interconnect Signals on page 67 WARNING When connecting the ADS to a target system via P5 and a 10 lead flat cable the MPC MUST be REMOVED from its SOCKET U18 Otherwise PERMANENT DAMAGE might be inflicted to either the local MPC or to the Target MPC In this mode of operation the on board debug port controller is connected to the target system s debug port connector see 4 15 1 1 Debug Port Connection Target System Requirements below Since DSDO signal is driven by the MPC it is a must to remove the local MPC from its socket to avoid contention over this line When the local MPC is removed from its socket all ADS s modules are inaccessible except for the debug port controller All module enable indications are darkened regardless of their associated enable bits in the BCSR Pull up resistor are connected to Chip Select lines so they do not float when the MPC is removed from its socket avoiding possible contention over data bus lines 4 15 1 1 Debug Port Connection Target System Requirements In order for a target system may be connected to the
104. of the target system designer to provide Power On Reset and HARD Reset configurations while SOFT Reset configuration is provided by the debug port controller See also 4 15 1 MPC821 860ADS As Debug Port Controller For Target System on page 56 FIGURE 2 8 Debug Port Controller For Target System Operation Scheme Target System 10 Wire Flat Cable 5V Power Suppl AR MPC Removed From Socket 2 4 3 Stand Alone Operation In this mode the board is not controlled by the host via the ADI Debug port It may connect to host via one of its other ports e g RS232 port I R port Ethernet port etc Operating in this mode requires an appli cation program to be programmed into the board s Flash memory while with the host controlled operation no memory is required at all Release 1 3a MPCS21ADS Revision A User s Manual Hardware Preparation and Installation FIGURE 2 9 Stand Alone Configuration Host Computer dn 5V Power Suppl
105. power consumption and increasing flexibility To enhance off board ap plication development memory modules including the BCSRx be disabled via BCSR1E in favor of an external memory connected via the expansion connectors That way a CS line may be used off board via the expansion connectors while its associated local memory is disabled When a CS region is disabled via BCSR1 the local data transceivers are not open during access to that A Approximately 45dB 5KHz An address which is covered in a Chip Select region and that CS region is enabled via BCSRI C To allow a configuration word stored in Flash memory become active D And off board See further E After the BCSR is removed from the local memory map there is no way to access it but to remove and re apply power to the ADS 37 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description region avoiding possible contention over data lines The MPC s chip selects assignment to the various memories registers on the MPCADS are as follows 1 CSO0 Flash memory CS1 BCSR CS2 DRAM Bank 1 CS3 DRAM Bank 2 if exists CS 4 7 Unused user available RO 5 4 7 DRAM The MPC821ADS is supplied with 4 MBytes of DRAM with access time of 60 or 70 nsec Support is given to memory capacity from 4 MByte with no parity upto 32MByte with parity Support is given to and only to the following devices made by Motorola MCM36100AS
106. push button is depressed in conjunction with the ABORT push button the HRESET line is asserted gen erating a HARD RESET sequence The button sharing is for economy and board space saving and does not effect in any way functionality 4 2 5 MPC Internal Sources Since the HRESET and SRESET lines of the are open drain and the on board reset logic drives these lines with open drain gates the correct operation of the internal reset sources of the MPC is facilitat ed As a rule an internal reset source will assert HRESET or SRESET for a minimum time of 512 system clocks It is beyond the scope of this document to describe these sources however Debug Port Soft Hard Resets which are part of the development support systemP are regarded as such 4 2 6 Reset Configuration During reset sequences to their kinds the MPC device samples the state of some external pins to deter mine its operation modes and pin configuration There are 3 kinds of reset levels to the MPC each level having its own configuration sampled 1 Power On Reset configuration 2 Hard Reset configuration 3 Soft Reset Configuration 4 2 6 1 Power On Reset Configuration Just before PORESET is negated by the external logic the power on reset configuration which include the MODCK 1 2 pins is sampled These pins determine the clock operation mode of the MPC Two clock modes are supported within the MPC821ADS 1 1 5 PLL operation via on board cl
107. switch is in the ON state it stands for logical 1 In FIGURE 2 2 051 is shown to be configured to address 0 FIGURE 2 2 Configuration Dip Switch DS1 ADR2 ADR2 ADR1 ADR1 ADR0 ADR0 3 5 MHz Generator via CLK4IN 32 678 KHz Crystal Resonator DS1 Table 2 1 describes the switch settings for each slave address Table 2 1 ADI Address Selection ADDRESS Switch 1 Switch 2 Switch 3 OFF OFF OFF O oO O ON ON ON 2 3 2 Clock Source Selection Switch 4 DS1 selects the clock source for the MPC When it is in the ON position while the ADS is powered up the on board 32 768 KHz crystal resonator becomes the clock source and the PLL multiplication factor becomes 1 513 When switch 4 is in the OFF position while the ADS is powered up the on board 4 MHz clock generator U17 becomes the clock source while the PLL multiplication factor becomes 1 5 2 3 2 1 Clock Generator Replacement 017 When replacing U17 with another clock generator it should be noticed that there are 2 supply level available at U17 1 supply at pin 14 A A 5MHz clock generator is provided as well Release 1 3a MPCS21ADS Revision A User s Manual Hardware Preparation and Installation 2 3 3V supply available at pin 11 FIGURE 2 3 U17 Power Sources 3 3V U17 From looking at FIGURE 2 3 U17 Power Sources above we see that 5V oscillator may
108. the status request bit in the control register is active during a previous host write to the control register When the host detects AdsReq asserted it asserts HstAck in return HstAck 120 Release 1 3a gt gt Wx gt gt Wx gt MPCS21ADS Revision A User s Manual Support Information double synchronized from the ADI port and delayed using the bundle delay compensation timer to negate AdsReq When the host detects AdsReq negated it knows that data is valid to be read After the host reads the data it negates HstAck The machine steps through these states 0 ADS REO ACTIVE 1 ADS REQ ACTIVE x KKK KK lt lt x x lt kk x CC VE ck ck equations AdsReq clk Clk2 AdsReq ar Reset AdsReq oe ADS IS SELECTED S HstAck clk C1k2 DS_HstAck clk C1k2 S_HstAck HstAck DS_HstAck HstAck amp S_HstAck double synced state_diagram AdsReq state ADS REO ACTIVE if TxEn fb amp TxWordEnd end of data shift to PDA ADS SEND STATUS then end of control write and status required ADS REQ ACTIVE else ADS REO ACTIVI EN ET State ADS REQ ACTIVE if HOST READ ADI amp BndTmrEx
109. this bit becomes active again This bit is a write only bit on that register Reserved Un Implemented E BREVNO Board Revision Number 0 This is the MS bit of the Board Revision R Number See TABLE 4 14 MPC821 860ADS Revision Number Conversion Table on page 54 for the interpretation of the Board Revision Number FLASH PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket U15 There are additional 4 presence detect lines which encode the SIMM s Type but appear in BCSR2 For the encoding of FLASH PD 7 5 see TABLE 4 15 FLASH Presence Detect 7 5 Encoding on page 55 BREVN1 Board Revision Number 1 Second bit of the Board Revision Number See R TABLE 4 14 MPC821 860ADS Revision Number Conversion Table on page 54 for the interpretation of the Board Revision Number Reserved Un Implemented BREVN 2 3 Board Revision Number 2 3 The 2 LS bits of the Board Revision R Number See TABLE 4 14 MPC821 860ADS Revision Number Conversion Table on page 54 for the interpretation of the Board Revision Number TABLE 4 14 MPC821ADS Revision Number Conversion Table MPC821ADS Revision Hex ENG Engineering 0 PILOT 1 A 2 3 F Reserved Release 1 3a 55 MPCS21ADS Revision A User s Manual Functional Description TABLE 4 15 FLASH Pres
110. voltage to be applied If on boards program ming of such device is required a 12V supply needs to be connected to the ADS See 2 4 5 12V Power Supply Connection on page 14 The control over the flash is done using the GPCM and a dedicated CS0 region controlling the whole bank During hard reset initializations the debugger reads the Flash Presence Detect lines via BCSR2 and decided how to program BRO amp ORO in which the size and the delay of the region are determined The performance of the flash memory is shown in TABLE 4 4 Flash Memory Performance Figures below TABLE 4 4 Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 Flash Delay nsec 90 120 90 120 Read Write Access Clocks 8 10 4 5 a The figures in the table refer to the actual write access The write operation continues internally and the device has to be polled for completion The programming of the associated registers is shown in 3 4 1 Memory Controller Registers Program ming on page 21 The Flash module may disabled enabled at any time by writing 1 0 the FlashEn bit in BCSR1 4 9 Ethernet Port An Ethernet port with 10 Base T I F is provided on the MPC821ADS This port resides over SCC1 of the MPC Use is done with Motorola s MC68160 EEST Enhanced Ethernet Serial Transceiver to mediate between the SCC and the Ethernet medium To all
111. 0 16 bit 711 reserved 6 Reserved Implemented 0 RW 7 8 ISB 0 1 Initial Space Base Value during Hard Reset determines the initial base 10 RW address of the internal MPC memory map When 00 initial space at 0 when 01 initial space at 0x00F00000 when 10 initial space at OxFF000000 when 11 initial space at OxFFFOOOOO 9 10 DBGC 0 1 Debug Pins Configuration Value during Hard Reset determines the 11 RW function of the PCMCIA channel Il pins When 00 these pins function as PCMCIA channel II pins when 01 they serve as Watch Points 10 Reserved when 11 they become show cycle attribute pins e g VFLS VF 11 12 DBPC 0 1 Debug Port Pins Configuration Value during Hard Reset determines the 00 RW location of the debug port pins When 00 debug port pins are on the JTAG port when 01 debug port non existent 10 Reserved when 11 debug port is on PCMCIA channel II pins 13 14 EBDF 0 1 External Bus Division Factor Value during Hard Reset determines the 400 R W factor upon which the CLKOUT of the MPC external bus is divided with respect to its internal MPC clock When 00 CLKOUT is GCLK divided by 1 when 01 CLKOUT is GCLK2 divided by 2 15 Reserved Implemented 0 R W 16 31 Reserved Un Implemented a May be read and written as any other fields and are presented at their associated data pins during Hard Reset b Applicable for MPC s revisi
112. 1 E CLSN Ethernet Port Collision indication signala In fact PC11 CTS1 When the ethernet port is disabled via BCSR1 may be used off board for any alternate function C12 E_RENA Ethernet Receive Enable In fact PC10 CD1 TGATE1 Active when there is network activity When the ethernet port is disabled via BCSR1 may be used off board for any alternate function C13 GND C14 PC9 PC9 CTS2 Not used on the ADS C15 PC8 PC8 CD2 TGATE2 Not used on the ADS C16 PC7 PC7 L1TSYNCB SDACK2 Not used on the ADS C17 C18 C19 GND ETHLOOP TPFLDL H L Ethernet port Diagnostic Loop Back In fact PC4 L1RSYNCA When active the MC68160 EEST is configured into diagnostic Loop Back mode where the transmit output is internally fed back into the receive section Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value When the ethernet port is disabled via BCSR1 may be used off board for any alternate function Twisted Pair Full Duplex In fact PC5 L1TSYNCA SDACK1 When active the MC68160 EEST is put into full duplex mode where simultaneous receive and transmit are enabled Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value When the ethernet port is disabled via BCSR1 may be used off bo
113. 1 as well Connecting an application board to the expansion connectors requires the following connectors to match the ADS s connectors B units of Socket strip double row Wire Wrap 50 pin 25 X 2 rows female straight E g 5501252490 by Samtec 2units of Socket strip double row Wire Wrap 60 pin 30 X 2 rows female straight E g SSQ13024GD by Samtec Using WW connectors even on a printed card retains logic analyzer connection capability Release 1 3a MPCS21ADS Revision A User s Manual Support Information FIGURE 5 1 Expansion Connector Assembly 0 4 0 5 gt lt 2 9 lt EE Hm D Pd Dd DA P6 s s s s sss sss Y 0 1 X 40 35 Dd Dd DX bd Pd DX DX A gt lt 0 3 gt lt 7 m
114. 11 for convenient LCD connection 83 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description D23 LD4 MPC821 s PD11 LD4 Not used on the ADS Appears also at P11 for convenient LCD connection D24 GND D25 IRQ1 LL Interrupt Request 1 Pulled up but otherwise not used on the ADS a There is also a visible collision indication b Be aware that TRST is connected to GND with a zero ohm resistor TABLE 5 9 P12 Interconnect Signals Pin No Signal Name Attribute Description A1 GND 2 GND A3 GND A4 GND E A5 GND A6 GND GND 5 8 D3 data line 3 AQ DO MPC s data line 0 A10 GND 11 D19 data line 19 12 D16 data line 16 A13 GND 14 011 MPC s data line 11 15 D8 MPC s data line 8 A16 GND 5 7 027 data line 27 18 D25 data line 25 A19 GND 20 EXTOLI1 External Tool Identification 1 Connected to 5 2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 21 EXTOLIO External Tool Identification 0 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 84 Release 1 3a MPCS21ADS Revision A User s Manual Support Informa
115. 15 E istype com data bus output enable on read Control Register Enable Protection CntReg 145 EnProtect NODI E istype reg buffer Release 1 3a MPCS21ADS Revision A User s Manual Support Information x PREFE gt HEHE x x Wx Wx PHE x dH x gt HEHHE gt d d T T THEE THE T T THE THE THE
116. 15 ACTIVE KA PON RESET amp RSV15 PON DEFAULT RSV15 ACTIVE then RSV15 else RSV15_ACTIVE Control Register equations WideContReg clk SYSCLK DrivenContReg oe hfff state_diagram FlashEn state FLASH_ENABLED if PDA_WRITE_CONTROL_REG1 amp FLASH ENABLE DATA BIT pin FLASH ENABLED amp KA PON RESET FLASH ENABLE PON DEFAULT FLASH ENABLED 4 KA PON RESET amp FLASH ENABLE PON DEFAULT FLASH ENABLED then FLASH ENABLED else FLASH ENABLED state FLASH ENABLED if PDA WRITE CONTROL amp FLASH ENABLE DATA BIT pin FLASH ENABLED amp KA PON RESET 4 FLASH ENABLE PON
117. 16 bit I O capability indication for PCMCIA slot A When the PCMCIA port is disabled via 2051 this line be used off board A18 BRDY I H Buffered PCMCIA slot A Ready signal In fact IP_A7 Used as PCMCIA port A Card Ready indication When the PCMCIA port is disabled via BCSR1 this line may be used off board A19 GND A20 N C Not Connected A21 V3 3 3 3V Power Rail A22 V3 3 A23 V3 3 24 V3 3 A25 V3 3 1 GND B2 GND B3 GND B4 IRQ3 LL CR IRQ3 Cancel Reservation input or Interrupt Request line 3 Pulled up but otherwise unused on the ADS B5 IRQ2 L RSV IRQ2 Reservation output or Interrupt Request line 2 input Pulled up but otherwise unused on the ADS B6 GND B7 VF1 IP_B5 LWP1 VF1 Input Port B 5 or Load Store Watchpoint 1 output or Visible Instruction Queue Flushes Status 1 Configured on the ADS as VF1 May be used for alternate function B8 ATO IP_B6 DSDI ATO Input Port 6 or Debug Serial Data Input or Address Type 0 Configured on the as ATO May be used for alternate function 9 GND B10 MODCK1 OP2 MODCK1 STS PCMCIA Output Port 2 or Mode Clock 1 input or Special Transfer Start output Used at Power On reset as MODCK1 and configured afterwards as a STS be used with alternate function 75 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 7 P9 Interconnect Signals
118. 1612 connector TABLE 5 13 P13 Interconnect Signals Pin No Signal Name Attribute Description A1 ETHRX Ethernet port Receive Data In fact PA15 RXD1 When the Ethernet port is disabled via BCSR1 may be used off board A2 ETHTX Ethernet port Transmit Data In fact PA14 TXD1 When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function IRDRXD InfraRed Port Receive Data In fact PA13 RXD2 When the Infra Red port is disabled may be used off board for any alternate function A4 IRDTXD InfraRed Port Transmit Data In fact PA12 TXD2 When the Infra Red port is disabled via BCSR1 may be used off board for any alternate function 5 LD4 MPC821 s PD11 LD4 or MPC860 s PD11 RXD3 Not used on the ADS Appears also at P11 for convenient LCD connection A6 LD3 MPC821 s PD10 LD3 or MPC860 s PD10 TXD3 Not used on the ADS Appears also at P11 for convenient LCD connection 7 LD2 MPC821 s PD9 LD2 MPC860 s PD9 RXD4 Not used on the ADS Appears also at P11 for convenient LCD connection A8 LD1 MPC821 s PD8 LD1 MPC860 s PD8 TXD4 Not used on the ADS Appears also at P11 for convenient LCD connection 9 Ethernet Port Transmit Clock In fact PA7 CLK1 TIN1 L1RCLKA BRGO1 When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function
119. 2 Clk4 Clkout2 Clk4 amp HOST IS ON divide by 4 For simulation purpose only Clk4 is generated using Clk2 only no use of sysclk ifdef SIMULATION equations Clkout2 clk SYSCLK Clkout2 Clkout2 amp HOST_IS_ON divide by 2 114 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Clk4 clk 2 ClkOut oe 3 ClkOut ar Reset Clk4 4 amp HOST IS ON divide by 2 Bundle delay timer This timer ensures data validity in the following cases
120. 3 Interconnect Signals Pin No Signal Name Attribute Description C23 SRESET VO L MPC Soft Reset Driven by on board logic and may be driven by off board logic with Open Drain gate only C24 N C Not Connected C25 VCG C26 SHIFT_C MPC821 s PD3 SHIFT CLK MPC860 s PD3 RRJECT4 Not used on the ADS Appears also at P11 for convenient LCD connection C27 VPPIN 12V input for PCMCIA flash programming Parallel to P8 C28 VPPIN 12V input for PCMCIA flash programming Parallel to P8 C29 GND C30 HSYNC MPC821 s PDA LOAD HSYNC MPC860 s PD4 RRJECT3 Not used on the ADS Appears also at P11 for convenient LCD connection C31 GND C32 VSYNC MPC821 s PD5 FRAME VSYNC MPC860 s PD5 RRJECT2 Not used on the ADS Appears also at P11 for convenient LCD connection 5 2 MPC821ADS Part List In this section the MPC821ADS s bill of material is listed according to their reference designation Reference Designation TABLE 5 14 MPC821ADS Part List Part Description Manufacturer Part C1 C4 C5 C8 C10 C12 C14 C16 C19 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C32 C33 C34 C35 C36 C38 C39 C40 C41 C42 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C56 C57 C58 C59 C60 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C76 C77 C78 C81 C82 C83 C84 C87 C88 C89 C93 C94 C95 C96 C99 Capacitor Ceramic 0 1uF SMD 1206 SIEMENS B37872 K5104K C2
121. 3CC0C 4 08AFCCOO 13FFCC04 X 2 00F3CC00 09F3CC0C 00AFCCOO 07AFCCA48 FFFFCC87 X 7 09F3CC0C OFBFCC47 O8AFCC48 FFFFCC05 X 4 X 08F3CC00 X O8AFCC48 X 5 X 3FF7CC47 X 39BFCC47 X 6 X X X X 7 X X X X 8 X X 9 X X A X X X B X X X X X D X X E X X F X X 32 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 12 Initializations for 70 EDO DRAMs 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM O 8 18 20 30 3C Contents 0 0FFBCC04 OFFBEC04 OFEFCC04 OFEFCC04 COFFCC84 33FFCC07 1 OCF3CC04 08F3ECOA 4 08AFCCOO 01FFCC04 X 2 00F3CC00 03F3EC48 00AFCCOO 07AFCC4C 7FFFCC86 X 3 33F7CC47 08F3CC00 OFBFCC47 08 5 X 4 X OFF3CC4C X 07 X 5 X 08F3CC00 X 08AFCCOO X 6 X OFF3CC4C X 07 X 7 X 08 00 X 08AFCCOO X 8 3FF7CC47 37BFCC47 X 9 X X X A X X X B X X X C X X D X X E X X F X X 33 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 4 Functional Description In this chapter the various modules combining the MPC821 ADS are described to their design details 4 1 MPC821 The 821 runs frequencies from 15 50 MHz and is buffered from the rest of the board s logic this to
122. 58 to 1 12208 MF range Sh 7 12 PCMCIA power controller is changed to LTC1315 by Linear Technologies PCCVPPG signal and indication are removed not supported by this device VPP selection code is changed DRAMEN no longer controls power to the dram Old 12V voltage pump remains as contingency for possible unavailability of the device although the device switching outputs drive 12V R55 R56 amp R59 are therefore not as sembled Sh 3 9 Added ADS board revision tag in BCSR 14 Added signals RS EN and ETHEN to P13 Quads Compatible connector for tool designer benefit Sh 16 15 Added 4 switches dip switch DS2 connected over EXTOLI 0 3 lines to provide s w option se lection capability 9 A Lowest MF allowed with 32768 Hz crystal due to 15MHz minimal PLL frequency B Highest MF allowed with 32768 Hz crystal considering 40MHz rated MPC Release 1 3a MPCS82I1ADS Revision A User s Manual Hardware Preparation and Installation 2 Hardware Preparation and Installation 2 1 INTRODUCTION This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC821ADS 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt request carriers agent to be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packin
123. 60 MCM36100AS70 MCM36100ASG60 MCM36100ASG70 MCMS36100ASH60 MCM36100ASH70 MCM36100ASHG60 MCM36100ASHG70 MCM36200AS60 MCM36200AS70 MCM36200ASG60 MCM36200ASG70 MCM36400AS60 MCM36400AS70 MCM36400ASG60 MCM36400ASG70 MCM36400ASH60 MCM36800S60 MCM36800S70 MCM36800SG60 MCM36800SG70 MCM36100ASH70 MCM36100ASHG60 MCM36100ASHG70 Also supported are 5V EDO memory SIMMs made by Micron MT8D132M 6X 4 MByte MT16D232M 6X 8 MByte MT8D432M 6X 16Mbyte MT16D832M 6X 32 MByte MT8D432M 7X and MT16D832M 6X All dram configurations are supported via the Board Control amp Status Register BCSR i e DRAM size 4M to 32M and delay 60 70 nsec are read from BCSR2 and the associated registers including the UPM are programmed accordingly Dram timing control is performed by UPMA of the MPC via CS2 and CS3 for 2 bank SIMM region s i e RAS and CAS signals generation during normal access as well as during refresh cycles and the neces sary address multiplexing are performed using UPM1 CS2 and CS3 signals are buffered from the DRAM and each split to 2 to overcome the capacitive load over the dram SIMM RAS lines The program ming of and other associated registers to perform that task is described in 3 4 1 Memory Controller Registers Programming on page 21 The DRAM module may enabled disabled at any time by writing the DRAMEN bit BCSR1 See TABLE 4 6 BCSR1 Description page 50 4 7 1 DRAM 16 Bit O
124. 63 Release 1 3a MPCS21ADS Revision A User s Manual Support Information VE ck ck CC CK KKK x KKK KKK KKK KK k k x lt KK KK state_diagram RSV13 pin RSV13_ACTIVE RSV13_PON_DEFAUL RSV13_PON_DEFAUL state RSV13_ACTIVE if PDA_WRITE_CONFIG_REG amp RSV13_DATA_BIT KA PON RESE KA PON RESET amp RSV13 ACTIVE else RSV13 pu lt state RSV13_ACTIVE T RSV13 ACTIVI amp amp if PDA WRITE CONFIG REG amp RSV13 DATA BIT pin RSV13 ACTIVE KA PON RESET RSV13 PON DEFAULT KA PON RESET amp RSV13 PON DEFAULT RSV13 ACTIVE else RSV13 ACTIVE RSV13 ACTIVE RSV13 AC RSV13 AC then E state_diagram RSV14 pin RSV14_ACTIVE RSV14_PON_DEFAU RSV14_PON_DEFAULT RSV14_ACTIVI state RSV14_AC
125. 71 Resistor 243 Q 1 SMD 1206 1 RODERSTEIN D25 243R FCS 8W R29 R30 R33 R34 R35 Resistor 330 Q 5 SMD 1206 RODERSTEIN D25 332R FC5 1 8W R40 Resistor 294 O 196 SMD 1206 TYOHM 1206 294E 1 1 8W R55 R56 R59 R70 Resistor 124 KO 5 SMD 1206 RODERSTEIN D25 124K FCS 1 8W R60 Resistor 510 Q 1 SMD 1206 BOURNS CR1206 JW 472bE 1 8W R65 Resistor 20 MO 596 SMD 1206 RODERSTEIN D25 020MJS 1 8W R67 Resistor 0 O SMD 1206 1 8W TYOHM RMC 1206 OE 1 R68 Resistor 200 KO 5 SMD 1206 RODERSTEIN D25 200K FCS 1 8W R72 Resistor 143 Q 5 SMD 1206 1 RODERSTEIN 025 1438 FCS 8W RN1 RN2 RN4 RN5 RN6 RN7 Resistor Network 10 5 13 DALE SOMC 14 01 103J resistors 14 pin RN3 Resistor Network 22 Q 5 8 DALE SOMC 16 03 220J resistors 16 pin SK1 Speaker piezo Sealed SOUNDTECH SEP 1162 SWI1 SPDT push button RED Sealed C amp K KS12R22 CQE SW2 SPDT push button BLACK C amp K KS12R23 CQE Sealed T1 T2 T3 Transistor TMOS Dual 3A Motorola MMDFSNOSHD U1 Infra Red Transceiver Telefunken TFDS3000 98 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 14 MPC821ADS Part List Reference Designation Part Description Manufacturer Part U2 Buffer Schmitt Trigger Motorola MC74LS244D U3 10 Base T Filter network Pulse PE 68026 Engineering U4 RS232 Transceiver 3 X 3 Motorola MC145707D
126. ABLE 3 4 UPMA Initializations for 60nsec DRAMs 50MHz MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 8FFFEC24 8FFFEC24 8FAFCC24 8FAFCC24 COFFCC84 33FFCC07 1 OFFFECO4 OFFFEC04 OFAFCC04 OFAFCC04 OOFFCC04 X 2 OCFFECO4 08FFEC04 OCAFCCOO OCAFCCOO 07FFCC04 X 4 OOFFECOC 11BFCC47 03AFCC4C 3FFFCC06 X 4 00FFEC00 X OCAFCCOO FFFFCC85 5 7 OOFFEC44 X FFFFCC05 6 X 00FFCC08 X OCAFCCOO X 7 X OCFFCC44 X 03AFCC4C X 8 OOFFECOC OCAFCCOO X 9 33BFCC4F X A OOFFEC44 X X B 00FFCCOO X X C 3FFFC847 X D X X E X X F X X 24 Release 1 3a TABLE 3 5 UPMA Initializations for 70 DRAMs 50MHz MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C Contents 0 8FFFCC24 8FFFCC24 8FAFCC24 8FAFCC24 EOFFCC84 33FFCC07 ore 1 04 OFFFCC04 OFAFCC04 OFAFCCO4 OOFFCC04 X 2 OCFFCCOA OCFFCC04 OOFFCC04 X 4 OOFFCC04 11BFCC47 OSAFCCAC OFFFCCO4 X 4 0 00FFCC08 X 7FFFCC06 5 37FFCC47 OCFFCC44 X
127. ADS as a debug port controller few measures need to be taken on the target system 1 10 pin header connector should be made available with electrical connections matching TA BLE 5 5 P5 Interconnect Signals on page 67 2 Pull down resistors of app 2KQ should be connected over DSDI and DSCK signals These resistors are to provide normal operation when a debug port controller is not connected to the target system 3 The debug port should be enabled and routed to the desired pins See the DBGC and DBPC fields within the HARD RESET configuration word 4 15 2 Debug Port Control Status Register The control status register is an 8 bit register bit 7 stands for MSB For the description of the ADI control status register see TABLE 4 16 Debug Port Control Status Register on page 57 TABLE 4 16 Debug Port Control Status Register VF BIT MNEMONIC Function js ATT DEF 7 MpcRst Mpc Reset When this status only bit indicates when active high that R either a SOFT or a HARD reset is driven by the MPC 6 TxError Transmit Error When this status only bit is active high it indicates that R the last transmission towards the MPC was cut by an internal PDA reset source This bit is updated for each byte sent 5 InDebug In Debug Mode When this status only bit is active high it indicates that R the MPC is in debug mode A Remember that the location of DSDI and DSCK is dete
128. B 253200253 P9 P10 P12 Connector Header 2 X 50 pin SAMTEC TSM 125 03 S DV A P Quad In line SMD P11 Connector Header 30 pin Dual SAMTEC TSM 115 03 S DV In line SMD P13 Connector 96 pin Female DIN ELCO 268477096002025 41612 90 P13 Counterpart Connector 96 pin Male DIN ELCO 168457096004025 41612 90 WW R1 R2 R3 R4 R5 R16 R17 R18 Resistor 10 KO 1 SMD 1206 RODERSTEIN D25 010K FC5 R19 R20 R27 R36 R38 R41 1 8W R42 R43 R44 R46 R48 R49 R50 R51 R52 R57 R58 R63 R64 R73 R74 R77 R78 R79 R80 R6 Resistor 10 Q 1 SMD 1206 1 RODERSTEIN D25 10R FCS 8W R7 R15 Resistor 2 kQ 1 SMD 1206 1 BOURNS CR1206 FX 2001E 8W R8 R13 R21 R53 Resistor 100 0 1 SMD 1206 1 RODERSTEIN D25 100R FCS 8W 97 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 14 MPC821ADS Part List Reference Designation Part Description Manufacturer Part R9 Resistor 5 1 KO 196 SMD 1206 RODERSTEIN D25 5K1 FCS 1 8W R10 R12 Resistor 47 KO 1 SMD 1206 KYOCERA CR32 473JT 1 8W R11 R14 R26 R32 R39 R45 R47 Resistor 150 Q 5 SMD 1206 1 BOURNS CR1206 JW 151 E R61 R62 8W R22 R23 Resistor 39 1 1 SMD 1206 TYOHM RMC 12061 8W 39E 1 8W R24 R31 R37 Resistor 22 O 5 SMD 1206 1 RODERSTEIN D25 24R FCS 8W R25 R54 R66 R69 R75 R76 Resistor 1 KQ 5 SMD 1206 1 AVX CR32 102F T 8W R28 R
129. BOOT PORT RESERVED amp KA PON RESET 4 BPS PON DEFAULT BOOT PORT 16 KA PON RESET amp BPS PON DEFAULT BOOT PORT RESERVED then BOOT PORT RESERVED else BOOT PORT 16 State BOOT PORT RESERVED if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 32 amp KA PON RESET BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 16 amp KA PON RESET 4 BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 8 amp KA PON RESET 4 BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else BOOT PORT RESERVED state diagram RSV6 state RSV6 ACTIVE if PDA WRI RSV6 DATA BIT KA PON KA PON R RSV6 ACTIVI else RSV6 ACTIVE 157 F _ 0 FIG_REG amp pi ES ET RSV6 PON ES amp
130. BUG PINS WATCH POINTS then DEBUG PINS WATCH POINTS else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS FOR SHOW amp KA PON RESET DBGC PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DEBUG PINS FOR SHOW then DEBUG PINS FOR SHOW else DEBUG PINS RESREVED state DEBUG PINS FOR SHOW if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp KA PON RESET DBGC PON DEFAULT DEBUG PINS FOR SHOW KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS WATCH POINTS amp KA PON RESET 4 DBGC PON DEFAULT DEBUG PINS FOR SHOW KA PON RESET amp DBGC PON DEFAULT DEBUG PINS WATCH POINTS then DEBUG PINS WATCH POINTS else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS RESREVED amp KA PON RESET 4 DBGC PON DEFAULT DEBUG PINS FOR SHOW KA PON RESET amp DBGC PON DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED 161 Release 1 3a MPCS82I1ADS Revision A User s Manual Support Information else D EBUG PINS FOR SHOW state_diagram DBPC state state 162
131. C24 8FFFCC24 8FFFCC24 8FFFCC24 EOFFCC84 33FFCC07 ore 1 OFF3CC04 OFFBCC04 OFEFCC04 OFEFCC04 OOFFCC04 X 2 0 04 0CF3CC04 OCAFCC00 OOFFCC04 X 3 00F3CC04 00 11 47 OSAFCCAC OFFFCC04 X 4 00F3CC00 03F3CC00 X 7FFFCC04 5 37F7CC47 00F3CC44 X 03AFCC4C FFFFCC86 6 X X 5 7 X X 4 X 8 00F3EC4C X 9 0 00 33BFCC47 X A 00F3EC44 X X B 00 00 X X C 33F7CC47 X D X X E X X X X TABLE 3 8 Memory Controller Initializations For 25Mhz Register Device Type Init Value hex Description BRO All Flash SIMMs 02200001 Base at 2200000 32 bit port size no parity GPCM supported 27 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 8 Memory Controller Initializations For 25Mhz Register Device Type Init Value hex Description ORO MCM29F020 90 FFE00D20 2MByte block size all types access CS early negate 2 w S MCM29F040 90 FFC00D20 4MByte block size all types access CS early negate SM732A1000A 9 2 w s MCM29F080 90 FF800920 8MByte block size all types access CS early negate SM732A2000 9 2 w s Timing relax MCM29F020 12 FFE00D30 2MByte block size all types access CS early negate 3 w s MCM29F040 12 FFC00D30 4MByte block size all typ
132. D if TxWordEnd PdaRst fb then TX DISABLED else X ENABLED Transmit Length Counter This counter determines the length of transmission towards the MPC The fast clock is used here to allow 1 2 clock resolution with the negation of TxEn which enables DSCK outside k KKK KKK KKK KKK KK 4 KKK lt x x x equations TxWordLen ar Reset TxWordLen clk Clk2 TxWordEnd TxWordLen fb TX WORD LENGTH when STATE TX ENABLED amp TxWordEnd amp PdaRst fb then TxWordLen d TxWordLen fb 1 else TxWordLen d 0 117 Release 1 3a MPCS21ADS Revision A User s Manual Support Information VE ck ck CC CC x x lt lt KKK x x x x lt KK KK TxClkSns Transmit Clock Sense Since Host req is synced acc to Clk2 and may be detected active when Clk4 is either 1 or 0 DSCK
133. DEFAULT FLASH ENABLED KA PON RESET amp FLASH ENABLE PON DEFAULT FLASH ENABLED then FLASH ENABLED else FLASH ENABLED 165 Release 1 3a MPCS21ADS Revision A User s Manual Support Information state diagram DramEn state DRAM ENABLED if PDA_WRITE_CONTROL_REG1 DRAM ENABLE DATA BIT pin DRAM ENABLED 6 PON RESET 4 DRAM ENABLE PON DEFAULT DRAM ENABLED KA PON RESET amp DRAM ENABLE PON DEFAULT DRAM ENABLED then DRAM ENABLED else DRAM ENABLED state DRAM ENABLED if PDA WRITE CONTROL 6 DRAM ENABLE DATA BIT pin DRAM ENABLED amp PON RESET DRAM ENABLE PON DEFAULT DRAM ENABLED KA PON RESET amp DRAM ENABLE PON DEFAULT DRAM ENABLED then DRAM ENABLED else DRAM ENABLED
134. E 0 00 00000 1 INT SPACE BASE OxFF000000 2 2 INT SPACE BASE OxFFF00000 3 DEBUG PINS PCMCIA 2 0 DEBUG PINS WATCH POINTS 1 DEBUG PINS RESREVED 2 DEBUG PINS FOR SHOW 3 DEBUG PORT ON JTAG 0 DEBUG PORT NON EXISTANT 1 DEBUG PORT RESERVED 2 DEBUG PORT ON DEBUG PINS 3 RSV13 ACTIVE 1 RSV14 ACTIVE 1 RSV15 ACTIVE 1 Wk KKK kk Dp Wk KKK KK KK ower On Defaults Assignments ERB_PON_DE 149 FAULT INTERNAL_ARBITRATION Release 1 3a MPCS21ADS Revision A User s Manual Support Information PON DEFAULT IP AT 0x00000000 RSV2 PON DEFAUL RSV2 ACTIVE BDIS PON DEFAUL BOOT ENABLE BPS PON DEFAUL BOOT PORT 32 RSV6 PON DEFAULT 6 ACTIVE ISB_PON_DEFAUL INT SPACE BASE OxFF000000 DBGC PON DEFAULT DEBUG PINS FOR SHOW DBPC PON DEFAULT DEBUG PORT ON JTAG RSV13 PON DEFAULT RSV13 ACTIVE RSV14 PON DEFAULT RSV14 ACTIVE RSV15 PON DEFAULT RSV15 ACTIVE WK ck
135. ESET amp CONT REG ENABLE PON DEFAULT CONT REG ENABLE then CONT REG ENABL else 168 Release 1 3a MPCS21ADS Revision A User s Manual Support Information CONT REG ENABLE state_diagram RS232En state RS232 ENABLE if PDA WRITE CONTROL RS232 ENABLE DATA BIT pin RS232 ENABLE amp KA PON RESET RS232 ENABLE PON DEFAULT RS232 ENABLE KA PON RESET amp RS232 ENABLE PON DEFAULT RS232 ENABLE then RS232 ENABLE else RS232 ENABLE state RS232 ENABLE if PDA WRITE CONTROL 6 RS232 ENABLE DATA BIT pin RS232 ENABLE amp KA PON RESET RS232 ENABLE PON DEFAULT RS232 ENABLE KA PON RESET amp RS232 ENABLE PON DEFAULT RS232 ENABLE then RS232 ENABLE else RS232 ENABLE VE ck ck CC
136. Enable for TFT displays Passive panels LCD_AC signal Not used on the ADS 6 GND 7 HSYNC Display Line beginning mark Not used on the ADS 8 GND 9 VSYNC New Frame beginning mark Not used on the ADS 10 GND 11 GND 12 GND 13 LDO LCD Data Line 0 Not used on the ADS 14 GND 5 15 LD1 LCD Data Line 1 Not used the ADS 16 GND 17 LD2 LCD Data Line 2 Not used on the ADS 18 GND 19 LD3 LCD Data Line 3 Not used on the ADS 20 GND 21 LD4 LCD Data Line 4 Not used on the ADS 22 GND 23 LD5 y o LCD Data Line 5 Not used on the ADS 24 GND 25 LD6 LCD Data Line 6 Not used the ADS 26 GND 27 LD7 LCD Data Line 7 Not used the ADS 28 GND 29 LD8 LCD Data Line 8 Not used on the ADS 89 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 12 P11 Interconnect Signals Pin No Signal Name Attribute Description 30 GND 5 1 10 P13 QUADS Compatible Communication Connector The QUADS compatible Communication connector P13 is for the benefit of those who developed commu nication tools for the M68360QUADS or M68360QUADS 040 boards All SCC pins are routed to the same 90 Release 1 3a MPCS21ADS Revision A User s Manual Support Information locations as they existed on those boards That way it is easy to migrate from the QUICC to the MPC821 P13 is a 96 pin Female DIN 4
137. G port When the debug port controller is on the local MPC or when the ADI bundle is disconnected from the ADS OUTPUT when the ADS is a debug port controller for a target system INPUT 5 1 6 P6 P9 P10 amp P12 Expansion and Logic Analyzer Connectors Each of these connectors is composed of quad SMD pin rows P6 has a 120 pin count while the rest have 100 pin count All MPC pins appear in these connectors plus few auxiliary control pins These connectors are arranged in a quadratic assembly around the MPC to provide short PCB routs The connectors assembly is shown in FIGURE 5 1 Expansion Connector Assembly on page 69 The interconnect signals of the connectors are described in TABLE 5 5 P5 Interconnect Signals on page 67 in TABLE 5 5 P5 Interconnect Signals on page 67 in TABLE 5 8 P10 Interconnect Signals on page 79 and in TABLE 5 9 P12 Interconnect Signals on page 84 5 1 6 1 Connecting Application Boards to the Expansion Connectors The expansion connectors P6 P9 P10 amp P12 are arranged in a way that allows for wire wrap boards to be connected to it i e connectors pins are located on a 0 1 snap grid as shown in FIGURE 5 1 Any board that is to be attached to these connectors should have a rectangle hole in its center so that the MPC 67 Release 1 3a 68 MPCS21ADS Revision A User s Manual Support Information Socket may be accessed The recommended hole size is shown in FIGURE 5
138. IA Address line 10 9 OE O PCMCIA Output Enable signal Active low Enables data outputs from PC Card during memory read cycles 10 PCCA11 PCMCIA Address line 11 11 PCCA9 PCMCIA Address line 9 12 PCCA8 PCMCIA Address line 8 13 PCCA13 PCMCIA Address line 13 14 PCCA14 PCMCIA Address line 14 15 WE PGM PCMCIA Memory Write Strobe Active low Strobes data to PC Card during memory write cycles 16 RDY Ready Busy signal from PC Card Allows PC Card to stall access from the host in case a previous 55 5 processing is not completed 17 5V VCC for the PC Card Switched by the MPC821ADS via BCSR1 18 PCCVPP O 12V 5V VPP for the PC Card programming 12V available only if12V is applied to P8 Controlled by the MPC821ADS via BCSR1 19 PCCA16 PCMCIA Address line 16 20 PCCA15 O PCMCIA Address line 15 64 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 21 PCCA12 PCMCIA Address line 12 22 PCCA7 PCMCIA Address line 7 23 PCCA6 PCMCIA Address line 6 24 5 PCMCIA Address line 5 25 PCCA4 PCMCIA Address line 4 26 PCCA3 PCMCIA Address line 3 27 PCCA2 PCMCIA Address line 2 28 1 PCMCIA Address line 1 29
139. IS SEL CT ED DS HstReq fb HOST REQ ACTIVI 1 AdsAck ADS ACK ACTIVE amp D_C DATA amp S D 6 0 DATA 6 HstAck HOST_ACK_ACTIVI AdsSelect fb BOARD_IS_SEL ECT DS HstReq fb HOST REO ACTIVE AdsAck ADS ACK ACTIVE Control amp Status register definitions STATUS_REQUEST 0 DEBUG_ENTRY 0 DIAG_LOOP_BACK 0 IN_DEBUG_MODE 1 TX_DONE_OK 0 TX INTERRUPTED TX DONE OK IS STATUS REQUEST StatusRequest fb STATUS REQUEST DEBUG MODE ENTRY DebugEntry fb DEBUG ENTRY IN DIAG LOOP BACK DiagLoopBack fb DIAG LOOP BACK IS IN DEBUG MODE InDebugMode fb IN DEBUG MODE
140. K KKK KK KK Dram Associated Pins 9 PIN 55 10 PIN 39 19 PIN 38 A20 PIN 2 127 Release 1 3a MPCS21ADS Revision A User s Manual Support Information A30 PIN 36 pda address lines inputs IN 23 SizeDetectl 26 SizeDetectO 20 dram simm size detect lines IN HalfWord PIN 51 dram port width selection from control register T gt ot 16 bit DramBank1Cs PIN 45 115 bank chip select IN L DramBank2Cs PIN 46 2 nd bank chip select IN L DramEn PIN 54 Dram enable from control reg IN H Active DramAdd10 DramAdd9 1 1 Ras2 Ras2DD PI PI PI PI high to support power control 32 istype com 33 istype com dram address lines 28 istype com 30 istype com 29 istype com 31 istype com dram RAS lines
141. K LOCK Modck2 ModIn support for 1 1 or 1 5 from CLK4IN only 1 H no support for 32K oscillator 136 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Hard reset configuration equations ResetConfig oe zm DriveConfig oe H Configuration hold counter Since the rise time of the HARD RESET signal is relatively slow there is a need to provide a hold time for reset configuration ConfigHold clk SYSCLK when SyncHardReset fb amp ConfigHoldEnd fb then ConfigHold ConfigHold fb 1 else when SyncHardReset fb amp ConfigHoldEnd fb then ConfigHold ConfigHold fb else when SyncHardReset fb then ConfigHold 0 ConfigHoldEnd ConfigHold fb HARD CONFIG HOLD VALUE terminal count ResetConfig
142. LCD port 10 P13 Serial Expansion connector 5 1 1 P1 ADI Port Connector The ADI port connector P1 is a 37 pin Male 90 D Type connector signals of which are described in TABLE 5 1 P1 ADI Port Interconnect Signals below TABLE 5 1 P1 ADI Port Interconnect Signals Pin No Signal Name Description 1 Not connected with this application 2 D C Data Control selection When 1 the debug port controller s data register is accessed when 0 the debug port controller s control register is accessed 3 HST ACK Host Acknowledge input signal from the host 4 ADS SRESET When asserted 1 and the ads is selected by the host generates Soft Reset to the MPC 5 ADS HRESET When asserted 1 and the ads is selected by the host generates Hard Reset to the MPC 6 ADS SEL2 ADI I F address line 2 MSB 7 ADS SEL1 ADI I F address line 1 8 ADS SELO ADI I F address line 0 LSB 9 HOST_REQ HOST Request input signal from the host 10 ADS_REQ ADS Request output signal from the MPC821ADS to the host 11 ADS_ACK ADS Acknowledge output signal from the MPC821ADS to the host 12 Not connected with this application 13 Not connected with this application 14 Not connected with this application 15 Not connected with this application 16 PD1 Bit 1 of the ADI port data bus 17 PD3 Bit 3 of the ADI port data bus 62 Release 1 3a MPCS21ADS Revision A User s Manual Su
143. NABLED 1 TX_DISABLED 0 STATE TX ENABLED TxEn fb TX ENABLED STATE TX DISAB ll Hd X En fb TX DISABLED TX WORD LENGTH 14 In 1 2 Clk2 clocks TxClkSns state machine x KKK KKK KKK 4 KKK KKK x ck x lt x lt lt x x x x lt TX_ON_RISING 0 TX_ON_FALLING 1 STATE_TX_ON_RISING TxClkSns fb TX_ON_RISING STATE TX ON FALLING TxClkSns fb TX ON FALLING AdsReq machine definitions x x k lt KK lt lt KKK KKK x x lt KKK KKK KKK KKK WK KKK
144. NODI NODE istype NODE istype NODE istype NODE istype NODE istype reg E istype reg buffer buffer reg buffer reg buffer reg buffer reg buffer Status request Debug nabl after reset L diagnostic loopback mode L bundle delay field sync VFLSs became pin L tx interrupted by pda internal reset Wx THE HEHEHE THE x HHEH x Wx gt HE gt gt H x HH d d HEHEHE T T T THE THE THE THEE THE THE T THE THE THE EEEH THE THE THE H L 107 Release 1 3 MPCS21ADS Rev
145. ON RESET amp DBGC PON DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS FOR SHOW amp 160 Release 1 3a MPCS21ADS Revision A User s Manual Support Information KA PON RESET 4 DBGC PON DEFAULT DEBUG PINS WATCH POINTS KA PON RESET amp DBGC PON DEFAULT DEBUG PINS FOR SHOW then DEBUG PINS FOR SHOW else DEBUG PINS WATCH POINTS state DEBUG PINS RESREVED if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp KA PON RESET DBGC PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS WATCH POINTS amp KA PON RESET 4 DBGC PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DE
146. PCS21ADS Revision A User s Manual Support Information while the receptacle is connected to the power supply That way fast connection disconnection of power is facilitated and physical efforts are avoided on the solders which therefore maintain solid connection over time TABLE 5 10 P7 Interconnect Signals REN Signal Name Description 1 5V 5V input from external power supply 2 GND GND line from external power supply 3 GND GND line from external power supply 5 1 8 P8 12V Power Connector The 12V power connector P8 is a two lead 2 part terminal block connector identical in type to the 5V connector P8 supplies when necessary programming voltage to the PCMCIA slot TABLE 5 11 P8 Interconnect Signals Pin 2275 Number Signal Name Description 1 12V 12V input from external power supply 2 GND GND line from external power supply 5 1 9 11 LCD Connector The LCD connector P11 is a 30 Male Header SMD connector meant to ease connection to LCD s 88 Release 1 3a MPCS21ADS Revision A User s Manual Support Information to their various types All P11 signals exist also at P10 and P13 TABLE 5 12 P11 Interconnect Signals Pin No Signal Name Attribute Description 1 SHIFT C LCD Shift Clock Not used the ADS 2 GND 3 GND 4 GND 5 LOE Output
147. PON RESET amp PCC VPP PON DEFAULT PCC VPP TS then VPP TS else PCC VPP 0 state PCC VPP 12 if PDA WRITE CONTROL 6 170 Release 1 3a MPCS21ADS Revision A User s Manual Support Information PCC VPP DATA BIT pin PCC VPP 0 amp KA PON RESET 4 PCC VPP PON DEFAULT PCC VPP 12 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 0 then PCC VPP 0 else if PDA WRITE CONTROL REG1 amp PCC VPP DATA BIT pin PCC VPP 5 amp KA PON RESET 4 PCC VPP PON DEFAULT PCC VPP 12 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 5 then PCC VEPS else if PDA WRITE_CONTROL_REG1 amp PCC_VPP_DATA_BIT pin PCC_VPP_TS amp KA PON RESET 4 PCC_VPP_PON_DEFAULT PCC VPP 12 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP TS then PCC VPP TS else PCC VPP 12 state PCC VPP 5 if PDA WRITE CONTROL 6 PCC VPP DATA BIT pin PCC VPP 0 amp KA PON RESET 4 PCC VPP PON DEFAULT PCC VPP 5 KA PON RESET amp PCC VPP PON DEFAULT PCC VPP 0 then PCC VPP 0 else if PDA WRITE CONTROL amp PCC VPP DATA BIT pin PCC VPP 12 amp KA PON RESET 4 PCC VPP PON DEFAULT
148. R W 6 28 amp A29 amp CntRegEn PDA READ STATUS REG2 BrdContRegCs 6 R W 6 A28 amp 29 6 CntRegEn Config Reg definitions INTERNAL 0 EXTERNAL ARBITRATION INTERNAL ARBITRATION 148 Release 1 3a 1 OxFFF00000 1 0 00 000000 RSV2_ACTIVE 1 MPCS21ADS Revision A User s Manual Support Information 0 active low IP AT OxFFF00000 BOOT DISABLE 1 BOOT ENABLE BOOT DISABLE PORT 32 0 BOOT PORT 8 1 PORT 16 2 BOOT PORT RESERVED 3 RSV6 ACTIVE 1 INT SPACE BASE 0x00000000 0 INT SPACE BAS
149. R1 may be used off board for any alternate function B10 PB22 PB22 SMSYN2 SDACK2 Not used on the ADS B11 PB21 PB21 SMTXD2 L1CLKOB Not used on the ADS 92 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 13 P13 Interconnect Signals Pin No Signal Name Attribute Description B12 PB20 PB20 SMRXD2 L1CLKOA Not used the ADS B13 E Ethernet Transmit Enable In fact PB19 RTS1 L1ST1 When active transmit is enabled via the MC68160 EEST When the ethernet port is disabled via BCSR1 may be used off board for any alternate function B14 PB18 PB18 RTS2 L1ST2 Not used on the ADS B15 PB17 PB17 L1RQB L1ST3 Not used on the ADS B16 PB16 PB16 L1RQA L1ST4 Not used on the ADS B17 PB15 PB15 BRGOS Not used on the ADS B18 PB14 PB14 RSTRT1 Not used the ADS B19 GND B20 BINPAK PCMCIA port Input Port Acknowledge In fact PC15 DREQ1 RTS1 L1ST1 When the PCMCIA port is disabled via BCSR1 may be used off board for any alternate function B21 PC14 PC14 DREQ2 RTS2 L1ST2 Not used on the ADS B22 PC13 PC13 L1RQB L1ST3 Not used on the ADS B23 PC12 y o PC12 L1RQA L1ST4 Not used on the ADS B24 E CLSN Ethernet Port Collision indication signal In fact PC11 CTS1 When the ethernet port is disabled via BCSR1 may be used off board for a
150. RAM SIMM MCM36400 MCM36800 32 01000000 01 FFFFFF DRAM SIMM MCM36800 32 02000000 020FFFFF Empty Space 02100000 02103FFF BCSR 0 3 8 325 02104000 021FFFFF Empty Space 02200000 02207FFF MPC Internal 32 02208000 027FFFFF Empty Space 02800000 029FFFFF Flash SIMM MCM29F020 MCM29F040 MCM29F080 32 SM732A1000A SM732A2000 02A00000 02BFFFFF MCM29F040 MCM29F080 32 SM732A1000A SM732A2000 02000000 O2FFFFFF MCM29F080 32 SM732A2000 a The device appears repeatedly in multiples of its size E g BCSRO appears at memory locations 2100000 2100010 2100020 while BCSR1 appears at 2100004 2100014 2100024 and so on b Only upper 16 bit are in fact used Refer to the MPC821 User s Manual for complete description of the MPC internal memory map 3 4 Programming The MPC Registers The MPC provides the following functions on the MPC821ADS 1 DRAM Controller Inm 6 20 Chip Select generator Ethernet controller Infra Red Port Controller General Purpose I O signals UART for terminal or host computer connection Release 1 3a MPCS21ADS Revision A User s Manual OPERATING INSTRUCTIONS The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in hexadecimal base For better understanding the of the following initializations refer to the MPC821 Users Manual for more
151. RESS CONNECTIONS Flash Memory Performance Figures BCSRO Description BCSR 1 Description PCCVPP 0 1 Assignment 0532 Description Flash Presence Detect 4 1 Encoding DRAM Presence Detect 2 1 Encoding DRAM Presence Detect 4 3 Encoding EXTOOLI 0 3 Assignment BCSR3 Description MPC821ADS Revision Number Conversion Table FLASH Presence Detect 7 5 Encoding Debug Port Control Status Register Off board Application Maximum Current Consumption P1 ADI Port Interconnect Signals P2 Ethernet Port Interconnect Signals P3 Interconnect Signals P4 PCMCIA Connector Interconnect Signals P5 Interconnect Signals P6 Interconnect Signals P9 Interconnect Signals P10 Interconnect Signals P12 Interconnect Signals P7 Interconnect Signals P8 Interconnect Signals P11 Interconnect Signals P13 Interconnect Signals MPC821ADS Part List Release 1 3a MPCS82I1ADS Revision A User s Manual General Information 1 General Information 1 1 Introduction This document is an operation guide for the MPC821ADS board It contains operational functional and general information about the ADS The MPC821ADS is meant to serve as a platform for s w and h w de velopment around the MPC821 Using its on board resources and its associated debugger a developer is able to load his code run it set breakpoints display memory and registers and connect his own proprietary h w via the expansion connectors to be incorporated to a desi
152. Rx shift register on the Rising edge DSCK DSCK terms are constant in that regard equations RxReg0 clk 7 0 Reset when STATE TX ENABLED amp STATE TX ON RISING amp Clk4 STATE TX ENABLED amp STATE TX ON FALLING amp Clk4 amp IN DIAG LOOP BACK then RxReg0 d DSDO shift in ext data else when STATE TX ENABLED 6 STATE TX ON RISING amp Clk4 STATE TX ENABLED amp STATE TX ON FALLING amp Clk4 amp IN DIAG LOOP BACK then RxReg0 d TxReg7 fb shift in from transmit reg else RxReg0 d RxRegQ fb hold value AdsReq Host from ads read acknowledge This state machine generates an automatic ADS read request from the host when either a byte of data is received in the Rx shift register or
153. S RS 232 Connection Memory Installation OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS SOFT RESET Switch SW1 ABORT Switch SW2 HARD RESET Switches SW1 SW2 DS2 Software Options Switch J4 Power Bridge GND Bridges RUN Indicator LD1 FLASH ON LD2 DRAM ON LD3 ETH ON LD4 Ethernet RX Indicator LD5 Ethernet TX Indicator LD6 Ethernet JABB Indicator LD7 IRD ON LD8 Ethernet CLSN Indicator LD9 Ethernet PLR Indicator LD10 Ethernet LIL Indicator LD11 Release 1 3a Go INOOO 3 2 18 3 2 19 3 2 20 392921 3 3 344 3 4 1 441 4 2 4241 4 2 2 4 2 3 4 2 4 4 25 426 4 26 41 452 62 4 2 6 3 4 3 4 4 4 4 1 4 5 4 6 4 7 4 7 1 4 7 2 4 7 3 4 7 4 4 8 4 9 4 10 4411 441141 4 12 4 12 1 4 13 4 14 4 14 41 4 14 2 4 14 3 4 14 4 4 14 5 4 15 4 15 1 4 15 1 1 4 15 2 4 15 3 MPCS82I1ADS Revision A User s Manual TABLE OF CONTENTS RS232 ON LD12 PCMCIA ON 1013 5V Indicator LD14 3 3V Indicator LD15 MEMORY MAP Programming The MPC Registers Memory Controller Registers Programming Functional Description MPC821 Or MPC860 Reset amp Reset Configuration Keep Alive Power On Reset Main Power On Reset Manual Soft Reset Manual Hard Reset MPC Internal Sources Reset Configuration Power On Reset Configuration Hard Reset Configuration Soft Reset Configuration Local Interrupter Clock Generator SPLL Support Buffering Ch
154. T pin BOOT PORT 16 amp KA PON RESET BPS PON DEFAULT BOOT PORT 8 f KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT RESERVED amp KA PON RESET BPS PON DEFAULT BOOT PORT 8 KA PON RESET amp BPS PON DEFAULT BOOT PORT RESERVED then BOOT PORT RESERVED else BOOT PORT 8 state BOOT PORT 16 if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 32 amp KA PON RESET BPS PON DEFAULT BOOT PORT 16 KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 156 Release 1 3a MPCS21ADS Revision A User s Manual Support Information else if PDA WRITE CONFIG REG amp BPS DATA BIT pin BOOT PORT 8 amp KA PON RESET BPS PON DEFAULT BOOT PORT 16 KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else if PDA WRITE CONFIG REG amp BPS DATA BIT pin
155. TIONS Width 32 Bit 16 Bit Depth Dram ADD 4M 1M AO BA29 BA29 Al BA28 BA28 A2 BA27 BA27 A3 BA26 BA26 A4 BA25 BA25 5 24 24 6 BA23 BA23 A7 BA22 BA22 BA22 BA22 A8 BA21 BA21 BA21 BA21 A9 BA20 BA20 BA20 BA30 A10 BA19 BA30 As can seen from the table above most of the address lines remain fixed while only 2 lines the shaded cells need switching The switching scheme is shown in FIGURE 4 2 DRAM Address Lines Switching on page 42 The switches on that figure are implemented by active multiplexers controlled by the BCSR1 Dram Half Word bit A Consequent addresses lead to adjacent memory cells 41 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description FIGURE 4 2 DRAM Address Lines Switching DRAM BA 21 29 BA20 0 19 0 4 8 Flash Memory The MPC821ADS support Flash non volatile memory SIMMs of the following types MCM29F020 MCM29F040 and MCM29F080 volume of which is 2Mbytes 4Mbytes and 8Mbytes correspondingly These devices are internally composed of 1 2 or 4 banks of 4 Am29F040 devices The flash SIMM U15 resides on an 80 pin SIMM socket Also supported are SMART s SM732A1000A 4Mbytes 1Meg X 32 or SM732A2000 2 X 1Meg X 32 To minimize use of MPC s chip select lines only one chip select line CS0 is used to select the flash as a whole while distributing chip select lines
156. TIVE if PDA_WRITE_CONFIG_REG amp RSV14 DATA KA PON RESE KA PON RESET amp RSV14 ACTIVE else RSV14 ACTIVI ET state RSV14 ACTIVE 124 RSV14_PON_DEFAUL RSV14_PON_DEFAULT if PDA_WRITE_CONFIG_REG amp RSV14 DATA KA PON RESE KA PON RESET amp RSV14 ACTIVE else RSV14 ACTIVE pin RSV14_ACTIVE iT T amp amp RSV14 ACTIVE RSV14 AC RSV14 AC then E state diagram RSV15 RSV15_ACTIVE state if 164 PDA WRITE CONFIG REG amp Release 1 3a MPCS21ADS Revision A User s Manual Support Information RSV15 DATA BIT pin RSV15 ACTIVE amp KA PON RESET 4 RSV15 PON DEFAULT RSV15 ACTIVE KA PON RESET amp RSV15 PON DEFAULT RSV15 ACTIVE then RSV15 ACTIVE else RSV15 ACTIVE state RSV15 ACTIVE if PDA WRITE CONFIG REG amp RSV15 DATA BIT pin RSV15 ACTIVE amp PON RESET RSV15 PON DEFAULT RSV
157. W U5 Voltage level detector Range Seiko S 8052ANY NH X 2 595V to 2 805V O D output U6 Schmitt Trigger Hex Inverter Motorola 74ACT14D U7 910 U11 MACH220 programmable logic AMD MACH220 12JC device U8 Clock generator 20MHz Jauch VX 3A 100ppM 5V HCMOS output SMD 09 Enhanced Ethernet Serial Motorola MC68160FB Transceiver U12 Dual Channel PCMCIA Power Linear LTC1315cG Controller Technology U13 U19 U24 U29 U30 U32 U33 Octal CMOS Buffer Motorola 74ACT541D U34 U35 U37 U14 U27 U28 U31 Octal CMOS Latch Motorola 74ACT373D U15 2 MByte Flash SIMM Motorola MCM29020 U16 4 MByte DRAM SIMM organized Motorola MCM36100 70 as 1 M X 4 70 nsec delay U17 4 MHz Clock generator 3 3V MGR Tech MH14FAD 3 3V 4 00MHz CMOS levels U18 MPC821 19 X 19 BGA Motorola PPC821ZP25 or PPC821ZP40 or PPC821ZP50 U20 Variable Output Voltage regulator Motorola LM317MDT U21 3 3V Voltage regulator 1 5A Linear LT1086 output U22 Quad CMOS buffer with individual Motorola 74ACT125D Output Enable U23 Schmitt Trigger Hex Inverter Motorola 74AC14D U25 U26 U39 U40 U41 U42 Octal CMOS Bus Transceiver Motorola 74ACT245D U36 Voltage level detector Range Seiko S 8051HN CD X 1 795V to 2 005V O D output U38 Dual CMOS 4 gt 1 MUX Motorola 74ACT158D UA38 Quad CMOS AND Gate Motorola 74AC08D 99 Release 1 3a Support Information TABLE 5 14 MPC821ADS Part List MPCS21ADS Revision A User s Manual
158. X 08FFCC00 X O8AFCC44 5 X 4 X 03FFCC4C X OFAFCCOB X 5 X 08FFCC00 X O8AFCC44 X 6 X 03FFCC4C X OCAFCCO8 X 7 X 08FFCC00 X 38BFCC46 X 8 33FFCC47 FFFFCC45 X 9 X X X A X X X B X X X C X X D X X E X X F X X 30 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 10 UPMA Initializations for 70 DRAMs 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C Contents 0 OFFFECO4 OFFFCC24 OFAFCC04 OFAFCC04 COFFCC84 33FFCC07 one 1 O8FFECO4 OFFFCC04 O8AFCCOO 01FFCC04 X 2 OOFFECOO 08FFCCOO 47 01AFCC4C 7FFFCC86 X 3 SFFFEC47 O3FFCCAC X OCAFCCOO FFFFCC05 X 4 X 08FFCCOO X 01AFCC4C X 5 X O3FFCCAC X OCAFCCOO X 6 X 08FFCC00 X 01AFCC4C X 7 X 03FFCC4C X X 8 08FFCCOO 31BFCC43 X 9 33FFCC47 X X A X X X B X X X C X X D X X E X X X X 31 Release 1 MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 11 UPMA Initializations for 0 EDO DRAMs 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 OFFBCC04 OFFBCC04 OFEFCC04 OFEFCCOA 80FFCC84 33FFCCO7 ore 1 OCF3CC04 09F
159. aken is determined by TxClkSns The Tx shift register operates according to Clk2 The Tx shift register is 1 st written by the host data cycle and along with write being acknowledged to the host data is shifted out via DSDI In order of saving logic the Tx shift register is shared with the Receive shift register this due to the fact that when a bit is shifted out a FF becomes available Since the Tx shift register is shifted MSB first its LSB FFs are gradually becoming available for received data To provide a 1 2 DSCK hold time for DSDI a single FF receive SR is used which is the source for the Tx shift register if 0 hold is required for DSDI this FF may be omitted equations TxReg clk 2 xReg ar Reset when HOST_WRITE_ADI_DATA amp BndTmrExp fb amp STATE_TX_ENABLED then 7 1 PD7 PD1 pin latching ADI data else when STATE TX ENABLED 6 STATE TX ON RISING 6 Clk4 I STATE TX ENABL D amp STATE TX ON FALLING amp Clk4 then TxReg7 TxRegl TxReg6 TxReg0 fb s
160. and the clock according to which DSDI is sent and DSDO is sampled should be changed When TxClkSns 0 DSCK will be Clk4 while transmit will be done nes according to Clk4 and receive by Clk4 When TxClkSns is 1 DSCK will be 1 4 while transmit will be done mx according to Clk4 and receive by equations TxClkSns clk Clk2 TxClkSns ar Reset state diagram TxClkSns state TX ON RISING if HOST WRITE ADI DATA amp BndTmrExp fb amp Clk4 then TX ON FALLING else TX ON RISING state TX ON FALLING if HOST WRITE ADI DATA amp BndTmrExp fb amp Clk4 then TX ON RISING else TX ON FALLING 118 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Ck Ck x lt Ck ck k x lt x kk lt x ck x x x x lt x x x Tx shift Register 8 bits shift register which either shifts data out MSB first or holds its data The edge in 1 4 terms upon which the above actions are t
161. anual Support Information APPENDIX C ADI Installation 1 INTRODUCTION This appendix describes the hardware installation of the ADI board into various host computers The installation instructions cover the following host computers 1 2 SUN 4 SBus interface C 2 IBM PC XT AT to MPC821ADS Interface The ADI board should be installed in one of the IBM PC XT AT motherboard system expansion slots A single ADI can control up to eight MPC821ADS boards The ADI address in the computer is configured to be at I O memory addresses 100 102 hex but it may be reconfigured for an alternate address space CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE IBM PC XT AT COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD C 2 1 ADI Installation in IBM PC XT AT Refer to the appropriate Installation and Setup manual of the IBM PC XT AT computer for instructions on removing the computer cover The ADI board address block should be configured at a free I O address space in the computer The address must be unique and it must not fall within the address range of another card installed in the computer The ADI board address block can be configured to start at one of the three following addresses 100 This address is unassigned in the IBM PC 200 This address is usually used for the game port 300 This address is defined as a prototype port The ADI board is factory configured for address dec
162. anual Support Information TABLE 5 9 P12 Interconnect Signals Pin No Signal Name Attribute Description D2 GND 5 D3 GND D4 GND 5 D5 GND D6 GND D7 GND 2 D8 D5 MPC s data line 5 D9 D2 MPC s data line 2 D10 GND D11 D21 data line 21 D12 D18 MPC s data line 18 D13 GND D14 D13 MPC s data line 13 D15 D10 MO MPC s data line 10 D16 GND D17 D29 MPC s data line 29 D18 GND i D19 D24 MPC s data line 24 D20 RS_EN O L 85232 port Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 D21 DRMH_W O L Dram Half Word Connected to BCSR1 See 4 14 3 BCSH1 Board Control Register on page 49 D22 DRMPD1 Dram Presence Detect line 1 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 D23 F_EN O L Flash Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 D24 BCSREN O L Board Control Status Register Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 D25 DRMPD2 Dram Presence Detect line 2 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 5 1 7 7 5V Power Connector The 5V power connector P7 is a 3 lead two part terminal block The male part is soldered to the pcb 87 Release 1 3a M
163. ard for any alternate function C20 TPSQEL L Twisted Pair Signal Quality Error Test Enable In fact PC6 L1RSYNCB When active a simulated collision state is generated within the EEST so the collision detection circuitry within the EEST may be tested Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value When the ethernet port is disabled via BCSR1 may be used off board for any alternate function C21 GND C22 VSYNC MPC821 s PD5 FRAME VSYNC Not used on the ADS Appears also at P11 for convenient LCD connection C23 LD7 MPC821 s PD14 LD7 Not used on the ADS Appears also at P11 for convenient LCD connection C24 LD3 MPC821 s PD10 LD3 Not used on the ADS Appears also at P11 for convenient LCD connection 82 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description C25 IRQ7 LL Interrupt Request 7 The lowest priority interrupt request line Not used on the ADS D1 VCC MPC821ADS VCC plane D2 VCC MPC821ADS VCC plane D3 VCC MPC821ADS VCC plane D4 PB31 PB31 SPISEL RRJECT1 Not used on the ADS D5 PB30 PB30 SPICLK Not used on the ADS D6 PB29 PB29 SPIMOSI Not used
164. be used with 14 pins only form factor while 3 3V oscillators may be used with 8 pins only form factor WARNING IF A 14 Pin Form Factor 3 3V Clock Generator is insert ed to U17 PERMANENT DAMAGE Might Be Inflicted To The Device WARNING Since the MPC clock input is NOT 5V FRIENDLY any clock generator inserted to U17 MUST BE 3 3V compat ible If a 5V output clock generator is inserted to U17 PERMANENT DAMAGE might be inflicted to the MPC 2 3 3 Power On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power On Reset logic it is therefore necessary to select different sources for Power ON reset generation J1 on the ADS is used to select Power On Reset source when a jumper is placed between positions 1 2 of J1 Power On reset to the MPC is generated by the Keep Alive power rail When KAPWR goes below 2 005V Power On reset is generated When a jumper is place between position 2 3 of J1 Power On reset to the MPC is generated from the MAIN 3 3V power rail l e when the MAIN 3 3V power rail goes below 2 805V Power On reset is generated 10 Release 1 3a MPCS21ADS Revision A User s Manual Hardware Preparation and Installation FIGURE 2 4 Power On Reset Source Selection J1 x x lt KA Power Rail MAIN Power Rail 2 3 4 VDDL Source Selection J2 serves as a Selector for VDDL MPC internal logic supply When a jumper is placed between positions 1
165. cal data buffers disable data contention protection equations HoldOffConsidered clk SYSCLK D FlashOe FlashOe DD FlashOe D FlashOe fb TD FlashOe DD FlashOe fb OD FlashOe TD FlashOe fb PD FlashOe QD FlashOe fb 138 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ifdef DEBUG equations HoldOffConsidered HOLD OFF CONSIDERED ifndef DEBUG state_diagram HoldoffConsidered state NO_HOLD_OFF if END OF FLASH READ amp DSyncHardReset fb then HOLD OFF CONSIDERED else NO HOLD OFF state HOLD OFF CONSIDERED if END OF OTHER CYCLE DSyncHardReset fb then NO HOLD OFF else HOLD OFF CONSIDERED pcc data buffers enable
166. configured for alternate function D8 GND D9 BADDR30 O Burst Address Line 30 Dedicated for external master support Used to generate Burst address during external master burst cycles Valid only when 16 bit memory is being accessed by the external master D10 AS Asynchronous external master Address Strobe signal When asserted L by the external master the MPC recognizes an asynchronous cycle in progress D11 GND D12 BADDR28 Burst Address Line 28 Dedicated for external master support Used to generate Burst address during external master burst cycles D13 MODCK2 OP3 MODCK2 DSDO PCMCIA Output Port 3 or Mode Clock 2 input or Special Transfer Start output Used at Power On reset as MODCk2 and configured afterwards as a May be used with alternate function D14 GND D15 SRESET I O L MPC Soft Reset Driven by on board logic and may be driven by O D off board logic with Open Drain gate only D16 KAPORO LL Keep Alive Power On Reset Output In fact Power On Reset Input of the MPC Driven by the on board reset logic D17 GND D18 DP3 DP3 IRQ6 Data Parity line 3 or Interrupt Request 6 Generates and receives parity data for D 24 31 bits May not be configured as IRQ6 IRQ6 is already configured on the FRZ 78 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 7 P9 Interconnect Signals
167. ctors External Tools Identification Capability via BCSR Soft Hard Reset Push Button ABORT Push Button Single 5V Supply Reverse Over Voltage Protection for Power Inputs 3 3V 2V MPC Internal Logic Operation 3 3V MPC I O Operation A Available only if supported also on chip B Unless a 12V supply is required for a PCMCIA card Release 1 3a MPCS21ADS Revision A User s Manual General Information External Keep Alive Power Source Option Q Power Indications for Each Power Bus Software Option Switch provides 16 S W options via BCSR FIGURE 1 1 MPC821ADS Block Diagram Expansion amp Logic Analyzer Connectors DATA amp ADDRESS Reset BUFFERS FLASH Mem Interrupts 2 8MByte amp Clock Dram Width 4 32 Mbyte x amp Size Logic li DRAM EEST Control amp Status Register PORT 1 MPC821 Infra Red Port QQ LJ PORT Debug Port PCMCIA Connector Buffering amp Control LCD PCMCIA RS232 PORT DEBUG PORT PORT CONTROLLER ADI I F ADI PORT Release 1 3a 1 6 MPCS21ADS Revision User s Manual General Information Revision Pilot to Revision A Changes DS2 which on PILOT revision was connected on SP2 with blue wires is now integrated into the PCB located nearby SP2 UA38 which on revision PILOT was glued and connected with blue wires is now in
168. d DramEn becomes active low to support debug station support changes Added F PD 1 3 to support SMART Flash SIMMs Support for 32KHz crystal renewed In this file 8 Added protection against data contention for write cycles after Flash read cycle This is achieved using state machine which identifies end of flash read and a chain of internal gates serving as a delay line or This kind of solution guaranties a fixed delay over the data buffer enable signal that is only after a flash read cycle In this file 9 126 Release 1 3a MPCS21ADS Revision A User s Manual Support Information The addressing scheme of the flash is changed so that the bank does Ts not occupy a space bigger than its real size I e A9 and A10 use is conditioned with the mod
169. d Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 3 Memory Controller Initializations For 502 Register Device Type Init Value hex Description MAMR MCM36100 60 70 40 21114 refresh clock divided by 408 or 60 or periodic 604211149 timer enabled type 2 address multiplexing scheme 1 C0A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MCM36200 60 70 223 refresh clock divided by 208 or 30 or 60 periodic 304211140 timer 60A21114 enabled type 2 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MCM36400 60 70 408211142 refresh clock divided by 408 or 60 periodic MT8D432X 6 7 608211140 timer 0 211142 enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MCM36800 60 70 20 211148 refresh clock divided by 208 or 30 60 periodic MT16D832 6 7 308211140 timer 60B21114 enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst a Assuming 16 67 MHz BRGCLK b Assuming 25MHz BRGCLK For 50MHz BRGCLK 23 Release 1 3 T
170. d is a slave only board and thus will function in any available SBus slot Slide the ADI board at an angle into the back panel of the system unit Make sure that the mounting plate on the ADI board hooks into the holes on the back panel of the system unit Release 1 3a 179 MPCS21ADS Revision A User s Manual Support Information Push the ADI board against the back panel and align the connector with its mate and gently press the corners of the board to seat the connector firmly Close the system unit Connect the 37 pin interface flat cable to the ADI board and secure Turn power on to the system unit and check for proper operation Release 1 3a
171. dby mode and SMC1 pins are available for off board use via the expansion connectors RW A Provided that BCSR is not disabled 50 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description TABLE 4 6 BCSR1 Description PON BIT MNEMONIC Function ATT DEF 8 PCCEN PC Card Enable When asserted low the on board PCMCIA channel is 1 RW enabled i e address and strobe buffers are enabled to from the card When negated all buffers to from the PCMCIA channel are disabled allowing off board use of its associated lines 9 PCCVCCON Pc Card VCC ON When this bit is active low 5V supply is applied to the 1 RW PCMCIA socket When inactive VCC to the PCMCIA channel is tri stated 10 11 PCCVPP 0 1 PC Card VPP These signals determine the voltage applied to the PCMCIA 1 RW card s VPP Possible values are 0 5 12 V For the encoding of these lines and their associated voltages see TABLE 4 7 PCCVPP 0 1 Assignment on page 51 12 Dram Half Word Dram Half Word When this bit is active low and the steps listed in 4 7 1 1 RW DRAM 16 Bit Operation on page 38 are taken the DRAM becomes 16 bit wide When inactive the DRAM is 32 bit wide 13 31 Reserved Un implemented a In case a Single Bank DRAM SIMM is used CS3 is free as well b Provided that this option is supported by the MPC by driving address lines low and asserting CSO during Hard Rese
172. dck2 1 ConfigHold2 ConfigHoldl ConfigHold0 PD3 PD2 PD1 Dram Declarations DRAM ENABLE ACTIVE 0 DRAM ENABLED DramEn DRAM ENABLE ACTIVE SIMM36100 SD 0 SIMM36200 SD 3 SIMM36400 SD 2 SIMM36800 SD 1 IS_HALF_WORD HalfWord 0 Flash Declarations
173. detect lines DramPdEdo PIN 12 DramPD4 PIN 10 DramPD3 PIN 60 DramPD2 PIN 56 DramPD1 PIN 45 Dram SIMM Identification pins ExtToolI0 PIN 57 ExtToolIl PIN 58 ExtToolI2 PIN 47 ExtToolI3 PIN 11 External Tools Identification pins PccVppG PIN 4 PCMCIA VPP GOOD indication Auxiliary Pins 144 Release 1 3a MPCS21ADS Revision A User s Manual Support Information KK KKK lt lt ck kk x lt lt x x KKK CC CK VE ck ck Wx gt gt gt gt Wx Wx FERE ETHER THE 0 oGH 2 THE THE THE THERE 5 THE
174. e If not the debug port can not be operated correctly FIGURE 4 7 Standard Debug Port Connector SRESET DSCK GND VFLS1 HRESET DSDI VDD 4315 3 Standard MPCXXX Debug Port Connector Pin Description The pins on the standard debug port connector are the maximal group needed to support debug port con trollers for both the MPC5XX and MPC8XX families Some of the pins are redundant for the MPC8XX family but are necessary for the MPC5XX family 4415321 5 0 1 These pins indicate to the debug port controller whether or not the is in debug mode When both VFLS 0 1 are at 1 the MPC is in debug mode These liens may serve alternate functions with the MPC but are needed for proper debug port operation 4 15 3 2 HRESET This is the Hard Reset bidirectional signal of the MPC When this signal is asserted low the MPC enters hard reset sequence which include hard reset configuration This signal is made redundant with the 8 debug port controller since there is a hard reset command integrated within the debug port pro 58 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description tocol However the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s w 4 15 3 3 SRESET This is the Soft Reset bidirectional signal of the MPC8XX On the MPC5XX it is an output The debug port configuration is sampled and determined on the rising edge of SRESET
175. e block size all types access CS early negate SM732A1000A 9 6 w s Timing relax MCM29F080 90 FF800D34 8MByte block size all types access CS early negate SM732A2000 9 6 w s Timing relax MCM29F020 12 FFE00D44 2MByte block size all types access CS early negate 8 w s Timing relax MCM29F040 12 FFC00D44 4MByte block size all types access CS early negate SM732A1000A 12 8 w s Timing relax MCM29F080 12 FF800D44 8MByte block size all types access CS early negate SM732A2000 12 8 w s Timing relax BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 BCSR FFFF8110 32 KByte block size all types access CS early negate 1 w s BR2 All Dram SIMMs 00000081 Base at 0 32 bit port size no parity UPMA Supported OR2 36100 200 60 70 00800 4MByte block size all types access initial address multiplexing according to AMA MCM36400 800 60 70 FF000800 16MByte block size all types access initial address MT8 16D432 832X 6 7 multiplexing according to AMA BR3 MCM36200 60 70 00400081 Base at 400000 32 bit port size no parity UPMA MCM36800 60 70 01000081 Base at 1000000 32 bit port size no parity UPMA 160832 6 7 OR3 MCM36200 60 70 FFC00800 4MByte block size all types access initial address multiplexing according to AMA MCM36800 60 70 FF000800 16MByte block size all types access initial address MT16D832X 6 7 multiplexing according to AMA MPTPR All Dram SIMMs 0400 Divide by 16 decimal Supporte
176. e lowest frequency at which the ADS may wake up Since the ADS may be made to wake up at 25MHzA as well the initializations are not efficient since there are too many wait states inserted Therefore additional set of initialization is provided to support efficient 25MHz operation The reason for initializing the ADS for 50Mhz is to allow proper although not efficient ADS operation through all available ADS clock operation frequencies A The only parameter which is initialized to the start up frequency is the refresh rate which would have been inad equate if initialized to 50Mhz while board is running at a lower frequency Therefore for best bus bandwidth avail ability refresh rate should be adapted to the current system clock frequency 21 Release 1 3a MPCS21ADS Revision A User s Manual OPERATING INSTRUCTIONS Warning Due to availability problems with few of the supported memory components the below initializations were not tested with all parts Therefore the below initializations are liable to CHANGE throughout the testing period TABLE 3 3 Memory Controller Initializations For 50Mhz 22 Register Device Type Init Value hex Description BRO All Flash SIMMs 02200001 Base at 2200000 32 bit port size no parity GPCM supported ORO MCM29F020 90 FFE00D34 2MByte block size all types access CS early negate 6 w s Timing relax MCM29F040 90 FFC00D34 4MByt
177. e sync host req buffer synchronized data control selection buffer sync host ack buffer double sync host ack buffer delay counter for bundle delay compensation terminal count for bundle delay timer Mach to ADI data OE Release 1 3a MPCS21ADS Revision A User s Manual Support Information PdaHardResetl NOD 5 istype com enables hard reset buffer PdaSoftReset NOD 5 istype com enables soft reset buffer KK KKK KK lt lt KKK KKK KK KKK lt WK Tx Shift Register lt x x lt x 4 kk lt k Ck Ck k C W lt ck k k Ck 7 45 xReg4 xReg3 TxReg2 xRegl xReg0O NODI istype reg buffer Transmit latch and shift register
178. e to the control register Nox will be followed by a status read cycle initiated by the debug port controller i e AdsReq will be asserted after the write cycl nds When inactive a write to the control register will not be followed by a read from status register 1 1 0 Bits 4 3 The contents of this field is the 1 s gt complement of the number of wait states 1 2 system clock noe terms Clk2 inserted during a host write read cycles ud After the interface has been reset these bits wake up at 0 TS meaning 3 wait states are inserted Important All bits wake up active L after reset n W lt k k Ck k k Ck Ck lt x lt ck ck ck x lt x lt x lt x x equations AdiCtrlReg clk Clk2 AdiCtrlReg ar Reset All active low when HOST WRITE ADI CONTROL amp BndTmrExp fb then AdiCtrlReg d PD4 pin PD3 pin PD2 pin 1 PDO pin else AdiCtrlReg d AdiCtrlReg fb 122 Release 1 3a MPCS21ADS Revision A User s Manual Support Information
179. ed to change data buffers direction D9 GND D10 CS7 O L CS7 CE2_B Chip Select 6 or PCMCIA slot B CE2 Not used on the ADS D11 F_CS O L In fact CS0 Used as a main chip select for the Flash memory from which the individual banks chip selects are derived May be used off board when the Flash is disabled via BCSR1 D12 GND D13 CS4 O L Chip select 4 Not used on the ADS D14 WE3 WE3 BS3_B PCWE GPCM Write Enable 3 or UPMB Byte Select 3 or PCMCIA Write Enable signal Used as WE3 for the Flash memory or as WE D15 GND D16 SPARE1 MPC spare pin 1 D17 A31 5 MPC s Address line 31 D18 GND D19 A20 5 MPC s Address line 20 D20 A15 5 MPC s Address line 15 D21 GND D22 A19 T S MPC s Address line 19 D23 A18 T S MPC s Address line 18 73 Release 1 3 MPCS21ADS Revision A User s Manual Support Information TABLE 5 6 P6 Interconnect Signals Pin No Signal Name Attribute Description D24 GND D25 A8 T S MPC s Address line 8 D26 A28 O T S MPC s Address line 28 D27 GND D28 A22 T S MPC s Address line 22 D29 A4 T S MPC s Address line 4 D30 GND TABLE 5 7 P9 Interconnect Signals Pin No Signal Name Attribute Description A1 GND A2 AT2 B2 IOIS16 AT2 PCMCIA slot B Input Port 2 or PCMCIA 16 bit capability indication or Address Type 2
180. elease 1 3a MPCS21ADS Revision A User s Manual Support Information SyncHardReset clk SYSCLK DSyncHardReset clk SYSCLK SyncHardReset HardReset DSyncHardReset SyncHardReset fb SyncTEA clk SYSCLK SyncTEA TEA LocDataBufEn oe 3 UpperHalfEn DramBanklCs amp DRAM ENABLED i DramBank2Cs amp SIMM36200 4 SIMM36800 amp DRAM ENABLED FlashCs amp FLASH ENABLED ContRegCs 6 CONTROL REG ENABLED 1 6 PCC ENABLED PccCE2 6 PCC ENABLED 4 ConfigHoldEnd fb amp STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF LowerHalfEn DramBanklCs amp DRAM ENABLED amp IS HALF WORD DramBank2Cs amp SIMM36200 4 SIMM36800 amp IS HALF WORD 6 DRAM ENABLED FlashCs 868 FLASH ENABLED ConfigHoldEnd fb amp FLASH CONFIGURATION ENABLED 6 STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF lo
181. ence Detect 7 5 Encoding FLASH PD 7 5 Flash Delay nsec 000 001 Not Supported 010 120 Motorola s SIMMs 011 90 Motorola s SIMMs 100 90 SMART s SIMMs 101 120 SMART s SIMMs 110 150 SMART s SIMMs 111 Not Supported Release 1 3a MPCS82I1ADS Revision A User s Manual Functional Description 4 15 Debug Port Controller The debug port of the MPC821ADS is implemented on board connected to the MPC via the JTAG port Since the location of the debug port is determined via the Hard Reset configuration It is important that the relevant configuration bits see 4 2 6 Reset Configuration on page 35 are not changed if working with the local debug port is desired The debug port controller is interfaced to host computer via Motorola s ADIP port which is an 8 bit wide parallel port Since the debug port is serial conversion is done by hardware between the parallel and serial protocols The debug port is configured at SOFT Reset to Asynchronous Clock Mode i e the debug port drives the debug clock DSCK which may be asynchronous with the MPC system clock FIGURE 4 6 Debug Port Controller Block Diagram ADI Port Connector P5 Debug Port Conn MPC8XX ADI Address Selection HRESET ADI Handshake Logic lt SRESET amp Port Control VFLS1 x lt VFLS0 Control Status Register Data Register DSDI DSCK
182. ener diode and high current diodes If the PCMCIA channel is not used or if a card which doesn t require a 12V VPP is being used or the flash memory available on board does not require 12V for programming or both of them do not require program ming the 12V input to the MPCADS may be omitted 4 16 5 Keep Alive Power The reason for the existence of the KAPWR bus is to allow current measurements over that bus and to allow the connection of an external power source to the KAPWR input of the MPC As seen in FIGURE 4 8 MPC821 860ADS Power Scheme on page 60 it is possible to connect an external power source to the KAPWR rail This can be done by removing the fabricated jumper from J3 and connected an external power source between J3 2 and J3 3 A At full speed When lower performance is needed the internal logic may be powered from the 2V bus 61 Release 1 3a MPCS21ADS Revision A User s Manual Support Information 5 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC821ADS is pro vided 5 1 6 0 Interconnect Signals The MPC821ADS interconnects with external devices via the following set of connectors P1 ADI Port connector P2 Ethernet port P3 RS232 port P4 PCMCIA port P5 External Debug port controller input P6 P9 P10 amp P12 Expansion amp Logic Analyzer connection P7 5V Power In P8 12V Power In P11
183. es access CS early negate SM732A1000A 12 3 w s MCM29F080 12 FF800930 8MByte block size all types access CS early negate SM732A2000 12 3 w s BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 BCSR FFFF8110 32 KByte block size all types access CS early negate 1 w s BR2 All Dram SIMMs 00000081 Base at 0 32 bit port size no parity UPMA Supported OR2 36100 200 60 70 00800 4MByte block size all types access initial address multiplexing according to AMA MCM36400 800 60 70 FF000800 16MByte block size all types access initial address MT8 16D432 832X 6 7 multiplexing according to AMA BR3 MCM36200 60 70 00400081 Base at 400000 32 bit port size no parity UPMA MCM36800 60 70 01000081 Base at 1000000 32 bit port size no parity UPMA MT16D832X 6 7 OR3 MCM36200 60 70 00800 4MByte block size all types access initial address multiplexing according to AMA MCM36800 60 70 FF000800 16MByte block size all types access initial address MT16D832X 6 7 multiplexing according to AMA MPTPR All Dram SIMMs 0400 Divide by 16 decimal Supported 28 Release 1 3a MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS TABLE 3 8 Memory Controller Initializations For 25Mhz Register Device Type Init Value hex Description MAMR MCM36100 60 70 MCM36200 60 70 60A21114 30A21114 refresh clock divided by 60 periodic timer enabled type 2 address mul
184. eset conditions exist the HRESET signal of the MPC is asserted for a period of approx imately 4 sec In addition if J1 is set accordingly see 2 3 3 Power On Reset Source Selection on page 10 Power On Reset is generated i e PORESET input of the MPC is asserted for a period of approxi mately 4 sec When HRESET signal is asserted the HARD reset configuration is made available to the MPC See 4 2 6 2 Hard Reset Configuration on page 35 When is asserted to the MPC Power On reset configuration is made available to MPC See 4 2 6 1 Power On Reset Configuration on page 32 4 2 3 Manual Soft Reset To support resident application development and debuggers a soft reset push button is provided De pressing that button asserts the SRESET pin of the MPC generating a SOFT RESET sequence This A The PLL minimal frequency is 15MHz Below that Low Power Divider must be incorporated during the operation of which CLKOUT is no longer 50 duty cycle distorting UPM timing 34 Release 1 3 MPCS21ADS Revision A User s Manual Functional Description button is debounced to avoid spikes over the SRESET line When SRESET is signal is asserted the SOFT reset configuration is made available to the MPC See 4 2 6 3 Soft Reset Configuration on page 36 4 2 4 Manual Hard Reset To support resident application development a hard reset push button is provided When the soft reset
185. eset for the MPC When an ads is selected and this line is asserted by the host computer Soft Reset will be generated to the MPC along with the Soft Reset configuration applied during that sequence HOST ENABLE F This line is always driven low by the ADI board When an ADI is connected to the MPCADS this signals enabled the operation of the debug port controller Otherwise the debug port controller is disabled and its outputs are tri stated ADS HRESET When a host is connected this line is used in conjunction with the addressing lines to generate a Hard Reset to the MPC821ADS board When this signal is driven in conjunction with the ADS SRESET signal the ADI I F state machines and registers are reset HOST REQ l This signal initiates a host to MPC821ADS write cycle ADS ACK O This signal is the MPC821ADS response to the HOST REQ signal indicating that the board has detected the assertion of HOST ADS REQ O This signal initiates an MPC821ADS to host write cycle HST_ACK l This signal serves as the host s response to the ADS_REQ signal HOST_VCC three lines These lines are power lines from the host computer In the MPC821ADS these lines are used by the hardware to determine if the host computer is powered on PD 0 7 I O These eight I O lines are the parallel data bus This bus is used to transmit and receive data from the host computer 175 Release 1 3a MPCS21ADS Revision A User s M
186. figured into diagnostic Loop Back mode where the transmit output is internally fed back into the receive section Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value B32 GND C1 VCC C2 VCG C3 VCC C4 VCC C5 VCG C6 N C Not Connected C7 GND C8 GND C9 GND C10 GND C11 GND C12 GND C13 GND C14 GND C15 LD8 MPC821 s PD15 LD8 MPC860 s PD15 L1TSYNCA Not used on the ADS Appears also at P11 for convenient LCD connection C16 LD7 MPC821 s PD14 LD7 MPC860 s PD14 L1RSYNCA Not used on the ADS Appears also at P11 for convenient LCD connection C17 LD6 MPC821 s PD13 LD6 MPC860 s PD13 L1TSYNCB Not used on the ADS Appears also at P11 for convenient LCD connection C18 LD5 MPC821 s PD12 LD5 MPC860 s PD12 L1RSYNCB Not used on the ADS Appears also at P11 for convenient LCD connection C19 LDO MPC821 s PD7 LDO MPC860 s PD7 RTS3 Not used on the ADS Appears also at P11 for convenient LCD connection C20 LOE MPC821 s PD6 LCD_AC LOE 8605 PD6 RTS4 Not used on the ADS Appears also at P11 for convenient LCD connection C21 VCG C22 HRESET L MPC Hard Reset Driven by on board logic and may be driven by off board logic with Open Drain gate only 94 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 13 P1
187. flash configuration option bit asserted 3 Since Bclose is no longer available the data buffers will open asynchronously I e driven directly by the various chip selects to provide data hold 0 on write cycles to flash CSNT bit in the OR S should be programmed active while ACS 00 In This file 6 Al2 and All are removed from the flash selection equation since they can select only a 1 2 Mbyte of flash rather then 2Mbyte selection needed Therefore only one bank of 2 Mbyte flash may be used MCM29F020 The rest of the CS are driven high constantly In this file 7 Pon Reset Out is removed Pon Reset is driven directly to MPC Modck0 becomes Modck2 A9 and A10 replace A11 and A12 in flash bank selection Optional BufClose is remove
188. flat cable supplied with the ADI board FIGURE A 1 below shows the pin configuration of the connector FIGURE A 1 ADI Port Connector Gnd 2 1 N C Gnd 21 2 D C Gnd 22 3 HST_ACK Gnd 23 4 ADS_SRESET Gnd 24 5 ADS HRESET Gnd 25 6 2 12 26 7 ADS SELI HOST VOC 9 HOST REQ HOST VCC 28 10 ADS REQ HOST VCC 29 11 ADS HOST ENAB d 30 n 14 NC Gnd 33 15 NC PDO 34 16 PD1 PD2 35 PD4 36 17 PDS 37 19 7 ci NOTE Pin 26 on the ADI is connected to 12 v power supply but it is not used in the MPC281ADS Bel ADI Port Signal Description The ADI port on the MPC281ADS was slightly modified to generate either hard reset or soft reset This feature was added to comply with the MPC s reset mechanism In the list below the directions O and I O are relative to the MPC821ADS board I E l means input to the MPC821ADS NOTE Since the ADI was originated for the DSP56001ADS some of its signals throughout the boards it was used with were designated with the prefix ADS This convention is kept with this design also ADS SEL 0 2 1 174 Release 1 3a MPCS21ADS Revision A User s Manual Support Information These three input lines determine the slave address of the MPC821ADS being accessed by the host computer Up to 8 boards can be addressed by one ADI board ADS 53557 This input line is used to generate Soft R
189. for both processor families On the MPC8XX it is a bidirectional signal which may be driven externally to generate soft reset sequence This signal is in fact redundant regarding the MPC8XX debug port controller since there is a soft reset command integrated within the debug port protocol However the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s w 4 15 3 4 0501 Debug port Serial Data In Via the DSDI signal the debug port controller sends its data to the MPC The DSDI serves also a role during soft reset configuration See 4 2 6 3 Soft Reset Configuration on page 36 4153 5 DSCK Debug port Serial Clock During asynchronous clock mode the serial data is clocked into the MPC according to the DSCK clock The DSCK serves also a role during soft reset configuration See 4 2 6 3 Soft Reset Configuration on page 36 4153 6 0500 Debug port Serial Data Out DSDO is clocked out by the MPC according to the debug port clock in parallel with the DSDI being clocked in The DSDO serves also as READY signal for the debug port controller to indicate that the debug port is ready to receive controller s command or data 4 16 Power There are 4 power buses with the MPC 1 2 Internal Logic 3 Keep Alive 4 PLL and there are 4 power buses on the MPCADS 1 5V bus 2 3 3V bus 3 2 0V bus 4 12V bus A In fact that configuration is divided into 2 parts the fi
190. ft Reset configuration is provided by the debug port controller U7 via the ADI I F When an ADI bundle is connected i e a debug station is connected debug mode is always enabled while immediate entry is determined by the debug station When a bundle is not connected to the ADI port or disconnected from the host computer debug mode is disabled by means of pulling DSCK low via a pull down resistor 4 3 Local Interrupter The only external interrupt applied to the MPC via its interrupt controller is the ABORT NMI which is gen erated by a push button SW2 When this button is depressed the NMI input to the MPC is asserted low The purpose of this type of interrupt is support the use of resident debuggers if any is made available to the MPCADS All other interrupts to the MPC are generated internally by the MPC s peripherals and by the debug port To support external off board generation of an NMI the IRQO line which drives the MPC s NMI is driven by an open drain gate This allows for external h w to also drive this line If an external h w indeed does so it is compulsory that IRQO is driven by an open drain or open collector gate 4 4 Clock Generator There are 2 ways to clock the MPC on the MPC821ADS 1 3 5MHz Clock generator connected to CLK4IN input 1 5 PLL mode A May be supported on future revisions of the MPC B I e AT VF VFLS C DSCK is configured at hard reset to reside on the JTAG port D With par
191. g material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 2 3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC821ADS board changes of the Dip Switch settings may be required before installation The location of the switches LEDs Dip Switches and connectors is illustrated in FIGURE 2 1 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions ADI port address e Clock Source Power On Reset Source e MPC Keep Alive Power Source e Internal Logic Supply Source Release 1 3a A User s Manual MPC821ADS Rev Hardware Preparation and Installation FIGURE 2 1 MPC821ADS Top Side Part Location diagram
192. h 4 7 2 DRAM Performance Figures The performance figures for the dram as reflected from the initializations given in 3 4 1 Memory Controller Registers Programming on page 21 are shown in TABLE 4 1 Regular DRAM Performance Figures on page 39 and in TABLE 4 2 EDO DRAM Performance Figures on page 39 TABLE 4 1 Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 3 3 Burst Read 6 2 3 2 6 3 2 3 3 2 2 2 4 2 2 2 Burst Write 4 2 2 2 4 2 2 2 3 1 2 2 3 2 2 2 Refresh 212P 25a 9 13ab 1398 a Four beat refresh burst b Not including arbitration overhead TABLE 4 2 EDO DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 2 3 Burst Read 6 2 2 2 6 3 2 2 3 1 1 1 4 1 2 2 Burst Write 4 2 2 2 4 2 2 2 2 1 1 1 3 2 2 2 Refresh 2145 25a b 13 0 132P 39 Release 1 3a MPCS82I1ADS Revision A User s Manual Functional Description a Four beat refresh burst b Not including arbitration overhead 4 7 3 Refresh Control The refresh to the dram is a CAS before RAS refresh which is controlled by UPMA as well The refresh logic is clocked by the BRG clock which is not influenced by the low power divider FIGURE 4 1 Refresh Scheme
193. h 4 X SPST SMD GRAYHILL 90 045 F1 Fuse 5A 250V Miniature 5 X 20mm Fast blow F2 Fuse 1A 250V Miniature 5 X 20mm Fast blow H1 H2 H4 Gnd Bridge Gold Plated PRECIDIP 999 11 112 10 J1 J2 J3 Jumper Header 3 Pole with Fabricated Jumper J4 Jumper Soldered L1 Inductor 8 2 mH BOURNS PT12133 LD1 LD5 LD6 LD14 LD15 Led Green SMD SIEMENS LG T670 HK 96 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 14 MPC821ADS Part List Reference Designation Part Description Manufacturer Part LD2 LD3 LD4 LD8 LD11 LD12 Led Yellow SMD SIEMENS LY T670 HK LD13 LD7 LD9 LD10 Led Red SMD SIEMENS LS T670 HK P1 Connector 37 pin Male DType KCC DN 37 P RCZ 90 2 Connector 8 pin RJ45 KCC 90015 8P8C Receptacle 90 P3 Connector 9 pin Female DType KCC DN 09 S RCZ 90 4 Connector 68 pin Male SMD MOLEX 53380 6810 PCMCIA P5 Connector header 10 pin dual in SAMTEC TSM 105 03 S DV line SMD P6 Connector Header 2 X 60 pin SAMTEC TSM 130 3 S DV A P Quad In line SMD P7 Male Part Connector 3 pin Power Straight WB 8113S 253303353 with false insertion protection P7 Female Part Connector 3 pin Power Plug WB 8113B 253200353 P8 Male Part Connector 2 pin Power Straight WB 81135 253303253 with false insertion protection P8 Female Part Connector 2 pin Power Plug WB 8113
194. hifting out MSB 1 else IxReg7 TxRegl TxReg7 TxRegl fb Holding value when HOST WRITE ADI DATA 6 BndTmrExp fb amp 5 TX ENABLED then TxRegO PDO pin E TX ENABLED amp STATE TX ON RISING amp Clk4 else when S A STATE TX ENABLED amp STATE TX ON FALLING amp Clk4 then TxRegQ RxRegQ fb else TxRegO TxRegQ fb 119 Release 1 3a MPCS21ADS Revision A User s Manual Support Information Wk Ck Ck CK x KK Kk Kk Ck Ck CC Sk Kk Ck KC lt IC kk SI Ck KC x CK I lt lt lt I Ck lt lt I lt x e lt x lt x lt Receive Shift Register A single stage shift register used as a source for the Tx shift register In normal mode the input for the Rx shift register is the pda s DSDO while in diagnostic loopback mode data is taken directly from the Tx shift serial output The output of the Rx shift register is fed to the input of the Tx shift register When transmission and reception is done the received data word is composed of the Rx shift register LSB concatenated with the 7 LSBs of the Tx shift register nx The edge in Clk4 terms upon which data is shifted in is determined by TxClkSns as with the Tx shift register but on opposite edges i e data is shifted Out from the Tx shift register on the Falling edge of DSCK while is shifted In to the
195. hz arbitrarily chosen to be 8 Number Of Banks 2 for that SIMM If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex The programming of the appropriate registers and UPM s memory controlling this function is shown in 3 4 1 Memory Controller Registers Programming on page 21 40 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 4 7 4 Variable Bus Width Control Since a port s width determines its address connections i e the number of address lines required for byte selection varies 1 for 16 bit port and 2 for 32 bit port according to the port s width it is necessary to change address connections to a memory port if its width is to be changed E g if a certain memory is initially configured as a 32 bit port the list significant address line which is connected to that memory s 0 line should be the MPC s ADD29 Now if that port is to be reconfigured as a 16 bit port the LS address line becomes ADD30 If a linear address scheme is to be maintained all address lines connected to that memory are to be shifted one bit this obviously involves extensive multiplexing passive or active If linear addressing scheme is not a must than only minimal multiplexing is required to support variable port width In TABLE 4 3 DRAM ADDRESS CONNECTIONS below the MPCADS s address connection scheme is presented TABLE 4 3 DRAM ADDRESS CONNEC
196. if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE 0x00000000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 else if PDA WRITE CONFIG REG amp ISB DATA BIT pin INT SPACE BASE 0 00 00000 amp KA PON RESET 4 ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F00000 then INT SPACE BASE 0 00 00000 else if PDA WRITE CONFIG REG amp 159 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ISB DATA BIT pin INT SPACE BASE OxFF000000 amp KA PON RESET ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE OxFF000000 then INT SPACE BASE OxFF000000 else INT SPACE BASE OxFFF00000 state_diagram DBGC state DEBUG_PINS_PCMCIA_2 if PDA_WRITE_CONFIG_REG amp DBGC_DATA_BIT pi
197. information TABLE 3 2 SIU REGISTERS PROGRAMMING Register Init Value hex Description SIUMCR 01632440 Internal arbitration External master arbitration priority 0 External arbitration priority 0 PCMCIA channel Il pins debug pins Debug Port on JTAG port pins FRZ IRQ6 IRQ6 debug register locked No parity for non CS regions DP 0 3 IRQ 3 6 pins DP 0 3 reservation disabled SPKROUT Tri stated BS_A 0 3 and WE 0 3 are driven just on their dedicated pins GPL B5 enabled GPL A B 2 3 function as GPLs SYPCR FFFFFF88 Software watchdog timer count FFFF Bus monitor timing FF Bus monitor Enabled S W watch dog Freeze S W watch dog disabled S W watch dog if enabled causes NMI S W if enabled not prescaled TBSCR 00C2 No interrupt level reference match indications cleared interrupts disabled no freeze time base disabled RTCSC 01C2 Interrupt request level 1 32768 Hz source second interrupt disabled Alarm interrupt disabled Real time clock FREEZE Real time clock disabled PISCR 0082 No level for interrupt request Periodic interrupt disabled clear status interrupt disabled FREEZE periodic timer disabled 3 4 1 Memory Controller Registers Programming The memory controller on the MPC821ADS is initialized to 50 MHz operation l e registers programming is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16 67Mhz th
198. ion B17 GND B18 PB16 PB16 L1RQA L1ST4 Not used the ADS B19 PB15 PB15 BRGOS Not used on the ADS B20 PB14 PB14 RSTRT1 Not used the ADS B21 GND B22 LOE MPC821 s PD6 LCD_AC LOE Not used on the ADS Appears also at P11 for convenient LCD connection B23 LD2 MPC821 s PD9 LD2 Not used on the ADS Appears also at P11 for convenient LCD connection B24 LD1 MPC821 s PD8 LD1 Not used on the ADS Appears also at P11 for convenient LCD connection B25 SPARE3 MPC spare pin 3 C1 VCC MPC821ADS VCC plane C2 VCG MPC821ADS VCC plane C3 IRDRXD InfraRed Port Receive Data In fact PA13 RXD2 When the Infra Red port is disabled may be used off board for any alternate function C4 IRDTXD InfraRed Port Transmit Data In fact PA12 TXD2 When the Infra Red port is disabled via BCSR1 may be used off board for any alternate function C5 GND C6 BINPAK PCMCIA port Input Port Acknowledge In fact PC15 DREQ1 RTS1 L1ST1 When the PCMCIA port is disabled via BCSR1 may be used off board for any alternate function C7 PC14 PC14 DREQ2 RTS2 L1ST2 Not used on the ADS C8 PC13 PC13 L1RQB L1ST3 Not used on the ADS C9 GND 81 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description C10 PC12 PC12 L1RQA L1ST4 Not used on the ADS C1
199. ion CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE SUN 4 COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD C 3 1 ADI Installation in the SUN 4 There are no jumper options on the ADI board for the Sun 4 computer The ADI board can be inserted into any available SBus expansion slot on the motherboard Refer to the appropriate Installation and Setup manual for the Sun 4 computer for instructions on removing the computer cover and installing the board in an expansion slot FIGURE A 3 ADI board for SBus SBus Connector ADI Connector Following is a summary of the Instructions in the Sun manual 178 1 Turn off power to the system but keep the power cord plugged in Be sure to save all open files and then the following steps should shut down your system hostname bin su Password mypasswd usr etc halt wait for the following messages Syncing file systems done Halted Program Terminated Type b boot c continue n new command mode When these messages appear you can safely turn off the power to the system unit Open the system unit Be sure to attach a grounding strap to your wrist and to the metal casing of the power supply Follow the instructions supplied with your system to gain access to the SBus slots Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel of the system unit Note that the ADI boar
200. ions area equations ifdef SLOW PLL LOCK PonDefault ResetConf RGPORIn 153 Release 1 3a MPCS21ADS Revision A User s Manual Support Information ConfigReg clk SYSCLK ERB state_diagram state INTERNAL ARBITRATION if PDA_WRITE_CONFIG_REG amp ERB DATA EXTERNAL ARBITRATION amp KA PON RESET ERB PON DEFAULT INTERNAL ARBITRATION KA PON RESET amp ERB PON DEFAULT EXTERNAL ARBITRATION then EXTERNAL ARBITRATION else INTERNAL ARBITRATION state EXTERNAL ARBITRATION if PDA WRITE CONFIG REG amp ERB DATA BIT pin INTERNAL ARBITRATION amp KA PON RESET ERB PON DEFAULT EXTERNAL ARBITRATION KA PON RESET amp ERB PON DEFAULT INTERNAL ARBITRATION then INTERNAL ARBITRATION else EXTERNAL ARBITRATION
201. ip Select Generator DRAM DRAM 16 Bit Operation DRAM Performance Figures Refresh Control Variable Bus Width Control Flash Memory Ethernet Port Infra Red Port RS232 Port RS 232 Port Signal Description PCMCIA Port PCMCIA Power Control LCD Port Board Control amp Status Register BCSR BCSR Disable Protection Logic BCSRO Hard Reset Configuration Register BCSR1 Board Control Register BCSR2 Board Status Register 1 BCSR3 Auxiliary Control Status Register Debug Port Controller MPC821ADS As Debug Port Controller For Target System Debug Port Connection Target System Requirements Debug Port Control Status Register Standard MPCXXX Debug Port Connector Pin Description Release 1 3a 5 2 APPENDIX Act 2 As3 APPENDIX B Bet APPENDIX C C 1 2 C 2 1 C 3 1 MPCS21ADS Revision A User s Manual TABLE OF CONTENTS VFLS 0 1 HRESET SRESET DSDI Debug port Serial Data In DSCK Debug port Serial Clock DSDO Debug port Serial Data Out Power 5V Bus 3 3V Bus 2V Bus 12V Bus Keep Alive Power Support Information Interconnect Signals P1 ADI Port Connector P2 Ethernet Port Connector P3 RS232 Port Connector PCMCIA Port Connector P5 External Debug Port Controller Input Interconnect P6 P9 P10 amp P12 Expansion and Logic Analyzer Connectors Connecting Application Boards to the Expansion Connectors P7 5V Power Connector P8 12V Power Connecto
202. is is is type type type type type type type type type reg buffer reg buffer reg buffer reg buffer reg buffer reg buffer reg buffer reg buffer reg buffer 5 istype reg buffer 3 istype reg buffer 38 istype reg buffer flash enable dram enable ethernet port enable infra red port enable flash configuration enable control register access enabl RS232 port enable PCMCIA port enable PCMCIA operation voltage select PCMCIA programming voltage select PCMCIA programming voltage select 32 16 bit dram operation select Release 1 3a MPCS21ADS Revision A User s Manual Support Information Board Status Pins Read only FlashPD7 PIN 66 FlashPD6 PIN 65 FlashPD5 PIN 67 FlashPD4 PIN 43 FlashPD3 PIN 23 FlashPD2 PIN 22 FlashPD1 PIN 21 Flash presence
203. is disabled via BCSR1 may be used off board B3 GND 4 Ethernet port Transmit Data In fact PA14 TXD1 When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function B5 GND B6 RSTXD RS232 port Transmit Data In fact PB25 SMTXD1 When the RS232 port is disabled via BCSR1 may be used off board for any alternate function B7 RSRXD RS232 Receive Data In fact PB24 SMRXD1 When the RS232 port is disabled via BCSR1 may be used off board for any alternate function B8 RSDTR RS232 port DTR signal In fact PB23 SMSYN1 SDACK1 When the RS232 port is disabled via BCSR1 may be used off board for any alternate function B9 GND B10 PB20 PB20 SMRXD2 L1CLKOA Not used on the ADS 80 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 8 P10 Interconnect Signals Pin No Signal Name Attribute Description B11 PB21 PB21 SMTXD2 L1CLKOB Not used on the ADS B12 PB22 PB22 SMSYN2 SDACK2 Not used on the ADS B13 GND B14 PB17 PB17 L1RQB L1ST3 Not used on the ADS B15 PB18 PB18 RTS2 L1ST2 Not used on the ADS B16 E_TENA H Ethernet port Transmit Enable In fact PB19 RTS1 L1ST1 When active transmit is enabled via the MC68160 EEST When the ethernet port is disabled via BCSR1 may be used off board for any alternate funct
204. ision A User s Manual Support Information Since all state machines operate at 1 2 system clock Clk2 there is no need to have SYSCLK driven during simulation it will double the number of vectors required Therefore an alternative clock generator was built with which the 1 2 clock is the 1 st in the chain This alternative clock is compiled in if the SIMULATION variable is defined If not the original clock generator design is compiled however simulation will not pass then SIMULATION 1
205. ith BVS2 to determine the operation voltage of a PCMCIA card When the PCMCIA port is disabled via BCSR1 may be used off board C19 GND C20 BBVD1 Buffered PCMCIA slot A Battery Voltage Detect 1 In fact IP_A6 Used in conjunction with BBVD2 to determine the battery status of a PC Card When the PCMCIA port is disabled via BCSR1 may be used off board C21 DPO DPO IRQ3 Data Parity line 0 or Interrupt Request 3 Generates and receives parity data for D 0 7 bits May not be configured as IRQ3 C22 GND C23 N C Not Connected C24 N C Not Connected C25 N C Not Connected 77 Release 1 3 MPCS21ADS Revision A User s Manual Support Information TABLE 5 7 P9 Interconnect Signals Pin No Signal Name Attribute Description D1 GND D2 GND D3 GND D4 VF1 IP_B5 LWP1 VF1 PCMCIA slot Input Port 5 or Load Store Watch Point 1 or Visible Instruction Queue Flushes Status 1 Configured on the ADS as VF1 May be configured to alternate function D5 GND D6 SPARE4 MPC spare pin 4 D7 VFLS1 B1 IWP1 VFLS1 PCMCIA slot B Input Port 1 or Instruction Watchpoint 1 or Visible history FLushes Status 1 Configured on the ADS as VFLS1 Indicates in conjunction with VFLSO the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be
206. ive input to the MPC821ADS 7 Not connected 8 Not connected 5 1 3 P3 RS232 Port Connector The RS232 port connector P3 is a 9 pin 90 female D Type connector signals of which are presented in TABLE 5 1 TABLE 5 3 Interconnect Signals Pin No Signal Name Description 1 CD Carrier Detect output from the MPC821ADS 2 TX Transmit Data output from the MPC821ADS 3 RX Receive Data input to the MPC821ADS 4 DTR Data Terminal Ready input to the MPC821ADS 5 GND Ground signal of the MPC821ADS 6 DSR Data Set Ready output from the MPC821ADS 7 RTS N C Request To Send This line is not connected in the MPC821ADS 63 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 3 P3 Interconnect Signals Pin No Signal Name Description 8 CTS Clear To Send output from the MPC821ADS 9 Not connected 5 1 4 PCMCIA Port Connector The PCMCIA port connector P4 is a 68 pin Male 90 PC Card type signals of which are presented in TABLE 5 4 TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 1 GND Ground 2 PCCD3 PCMCIA Data line 3 3 PCCD4 PCMCIA Data line 4 4 PCCD5 PCMCIA Data line 5 5 PCCD6 PCMCIA Data line 6 6 PCCD7 PCMCIA Data line 7 7 BCE1A PCMCIA Chip Enable 1 Active low Enables EVEN numbered address bytes 8 PCCA10 PCMC
207. ls controlled by the EN bit BCSR1 so the PCMCIA port may be Disabled Enabled at any time by writing 1 0 to that bit When the PCMCIA channel is disabled its associated pins are available off board via the expan sion connectors A loudspeaker SK1 is provided on board and connected to SPKROUT line of the MPC The speaker is buffered from the MPC and low pass filtered When the bit in BCSR1 is negated high the speaker buffer is tri stated so the SPKROUT signal of the MPC may be used for alternate function 4 12 1 PCMCIA Power Control To support hot insertion the socket s power is controlled via a dedicated PCMCIA power controller the LTC1315 made by LINEAR TECHNOLOGY This device controlled by BCSR1 switches 12V VPP for card programming and controls gates of external MOSFET transistors through which the PC Card VCC is switched When a card is inserted and the channel is enabled via BCSR1 i e both of the CD 1 2 Card Detect lines are asserted low the status of the voltage select lines VS 1 2 should be read to determine the PC Card s operation voltage level and then if the PC Card is found to be 5V operated the BCSR1 may be written to turn on power 5V only to the PC Card s VCC If a 3 3V card is inserted power should never be switched on When a card is being removed from the socket while the channel is enabled via BCSR1 the negation of CD1 and CD2 is sensed by the MPC and power supply t
208. ludes controls and indicators memory map details and software initialization of the board 3 2 CONTROLS AND INDICATORS The MPC821ADS has the following switches and indicators 3 2 1 SOFT RESET Switch SW1 The SOFT RESET switch SW1 performs Soft reset to the MPC internal modules maintaining MPC s configuration clocks amp chip selects and dram contents The switch signal is debounced and it is not possible to disable it by software At the end of the Soft Reset Sequence the Soft Reset Configuration is sampled and becomes valid 3 2 2 ABORT Switch SW2 The ABORT switch is normally used to abort program execution this by issuing a level 0 interrupt to the If the ADS is in stand alone mode it is the responsibility of the user to provide means of handling the interrupt since there is no resident debugger with the MPC821ADS The ABORT switch signal is debounced and can not be disabled by software 3 2 3 HARD Switches SW1 8 SW2 When BOTH switches SW1 and SW2 are depressed simultaneously HARD reset is generated to the MPC When the MPC is HARD reset all its configuration is lost including data stored in the DRAM and the MPC has to be re initialized At the end of the Hard Reset sequence the Hard Reset Configuration stored in BCSRO becomes valid 3 2 4 DS2 Software Options Switch DS2 is a 4 switches Dip Switch mounted over SP2 This switch is connected over EXTOLI 0 3 lines and since EXTOLI 0 3 line
209. lug The plug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires 2 4 6 ADI Installation For ADI installation on various host computers refer to APPENDIX C ADI Installation on page 176 2 4 7 Host computer to MPC821ADS Connection The MPC821ADS ADI interface connector P1 is a 37 pin male D type connector The connection between the MPC821ADS and the host computer is by a 37 line flat cable supplied with the ADI board FIGURE 2 12 below shows the pin configuration of the connector FIGURE 2 12 P1 ADI Port Connector VNE Gnd 20 Gnd 21 2 DC Gnd 22 3 HST Gnd 25 4 ADS SRESET Gnd 124 5 ADS HRESET Gnd 25 6 ADS SEL2 42 NO 29 HOST 00 27 oy 9 HOST_REQ HOST VCC 28 10 ADS REQ HOST VCC 29 11 ADS 30 n 14 NC Gnd 33 15 NC PDO 34 16 PD1 PD2 35 PD4 36 2502 pos 9 18 RD NOTE Pin 26 on the ADI is connected to 12 v power supply but it is not used in the MPC821ADS 2 4 8 Terminal to MPC821ADS RS 232 Connection A serial RS232 terminal or any other RS232 equipment may be connected to the RS 232 connector P3 The RS 232 connector is a 9 pin female D type connector as shown in FIGURE 2 13 The connector is arranged a manner that allows for 1 1 connection with the serial port of an IBM AT or compatibles i e via a flat cable A IBM AT is a trademark of International Business Machines
210. n DEBUG_PINS_WATCH_POINTS amp KA_PON_RESET DBGC_PON_DEFAULT DEBUG_PINS_PCMCIA_2 KA_PON_RESET amp DBGC_PON_DEFAULT DEBUG_PINS_WATCH_POINTS then DEBUG_PINS_WATCH_POINTS else if PDA_WRITE_CONFIG_REG amp DBGC_DATA_BIT pin DEBUG_PINS_RESREVED amp KA PON RESET DBGC PON DEFAULT DEBUG PINS PCMCIA 2 KA PON RESET amp DBGC PON DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS FOR SHOW amp PON RESET 4 DBGC PON DEFAULT DEBUG PINS PCMCIA 2 KA PON RESET amp DBGC PON DEFAULT DEBUG PINS FOR SHOW then DEBUG PINS FOR SHOW else DEBUG PINS PCMCIA 2 state DEBUG PINS WATCH POINTS if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp PON RESET DBGC PON DEFAULT DEBUG PINS WATCH POINTS 4 KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if PDA WRITE CONFIG REG amp DBGC DATA BIT pin DEBUG PINS RESREVED amp KA PON RESET DBGC PON DEFAULT DEBUG PINS WATCH POINTS KA P
211. n Debug Port Controller Block Diagram Standard Debug Port Connector MPC821ADS Power Scheme ADI Port Connector Physical Location of jumper JG1 and JG2 JG1 Configuration Options ADI board for SBus Release 1 3a TABLE 1 1 TABLE 3 1 TABLE 3 2 TABLE 3 3 TABLE 3 4 TABLE 3 5 TABLE 3 6 TABLE 3 7 TABLE 3 8 TABLE 3 9 TABLE 3 10 TABLE 3 11 TABLE 3 12 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 4 4 TABLE 4 5 TABLE 4 6 TABLE 4 7 TABLE 4 8 TABLE 4 9 TABLE 4 10 TABLE 4 11 TABLE 4 12 TABLE 4 13 TABLE 4 14 TABLE 4 15 TABLE 4 16 TABLE 4 17 TABLE 5 1 TABLE 5 2 TABLE 5 3 TABLE 5 4 TABLE 5 5 TABLE 5 6 TABLE 5 7 TABLE 5 8 TABLE 5 9 TABLE 5 10 TABLE 5 11 TABLE 5 12 TABLE 5 13 TABLE 5 14 MPCS82I1ADS Revision A User s Manual LIST OF TABLES MPC821ADS Specifications MPC821ADS Main Memory Map SIU REGISTERS PROGRAMMING Memory Controller Initializations For 50Mhz UPMA Initializations for 60nsec DRAMs 50MHz UPMA Initializations for ZOnsec DRAMs 50MHz UPMA Initializations for 60nsec EDO DRAMs 50MHz UPMA Initializations for 70 EDO DRAMs 50MHz Memory Controller Initializations For 25Mhz UPMA Initializations for 60nsec DRAMs 25 2 UPMA Initializations for ZOnsec DRAMs 25MHz UPMA Initializations for 60nsec EDO DRAMs 25MHz UPMA Initializations for 70 EDO DRAMs 25MHz Regular DRAM Performance Figures EDO DRAM Performance Figures DRAM ADD
212. n its lines with no damage The 5V bus is connected to an external power connector via a fuse F1 of 5A fast blow To protect against reverse voltage or over voltage being applied to the 5V inputs a set of high current diodes and zener diode are connected between the 5V bus GND When either over or reverse voltage is applied to the MPCADS the protection logic will blow the fuse while limiting the momentary effects on board 4 16 2 3 3V Bus The MPC itself is powered by the 3 3 bus which is produced from the 5V bus using a special low voltage drop linear voltage regulator made by Linear Technology the LT1086 which is capable of driving upto 1 5A Since the local 3 3V current consumption might be around 1 5A no power should be drawn from the 3 3V bus via the expansion connectors 4 16 3 2V Bus To support evaluation of the MPC operating with two supply levels i e internal logic is powered with 2V and the I O is powered with 3 3 dedicated 2V voltage regulator LM317 is provided That regulator is also powered by the 5V bus The internal logic s VDD may be switched between the 3 3V bus and the 2V bus by means of a fabricated jumper 4 16 4 12V Bus The sole purpose of the 12V bus is to supply VPP programming voltage for the PCMCIA card and or to a FLASH memory residing on U15 It is connected from a dedicated input connector P8 via a fuse F2 1A fast blow and protected from over reverse voltage application by means of Z
213. n towards the PCMCIA card 2 Data buffers may be driven to from the PCMCIA card depending on the CE1A and CE2A signals and transfer direction 3 Card status lines are driven towards the MPC from the PCMCIA card When it is dark it indicates that all the above buffers are tri stated and the pins associated with PCMCIA channel A may be used off board via the expansion connectors 3 2 20 5V Indicator LD14 The yellow 5V led indicates the presence of the 5V supply at P7 3 2 21 3 3V Indicator LD15 The yellow 3 3V led indicates that the 3 3V power bus is powered 19 Release 1 3a MPCS21ADS Revision A User s Manual OPERATING INSTRUCTIONS 3 3 All accesses to MPC821ADS s memory slaves are controlled by the MPC s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks to see the size delay and type of the DRAM and FLASH memory mounted on board and initializes the chip selects accordingly The DRAM and the FLASH memory respond to all types of memory access i e user supervisory program data and DMA TABLE 3 1 MPC821ADS Main Memory Map ADDESS RANGE Memory Type Device Type 00000000 003FFFFF DRAM SIMM MCM36100 MCM36200 MCM36400 MCM36800 32 00400000 007FFFFF DRAM SIMM MCM36200 MCM36400 MCM36800 32 00800000 OOFFFFFF D
214. normal operation For additional information on the EEST refer to the MC68160 Technical Data document 4 10 Infra Red Port An infra red communication port is provided with the MPCADS the Temic s TFDS 3000 integrated trans ceiver which incorporates both the receiver and transmitter optical devices with the translating logic This port resides on SCC2 of the MPC This device conforms to the IRDA standard which is supported by the MPC allowing for glueless connection between the TFDS3000 and the MPC To allow SCC2 s off board use the infra red transceiver may be disabled enabled at any time by writing 1 0 to the IrdEn bit in BCSR1 4 11 RS232 Port To assist user s applications and to provided convenient communication channel with a host computer an RS232 port is provided via SMC1 port Support is given upto 19200 baud rate via an RS232 transceiver Use is done with MC145707 transceiver which generates RS232 levels internally using a single 5V supply and is equipped with OE and shutdown mode When the RS232EN bit in BCSR1 is asserted low the transceiver is enabled When negated the transceiver enters standby mode in which the receiver outputs tri stated enabling use of the SMC1 port off board via the expansion connectors In order of saving board space 9 pins female D Type connector is used configured to be directly via a flat cable connected to a standard IBM PC like RS232 connector FIGURE 4 4 RS232
215. nual OPERATING INSTRUCTIONS When the yellow IRD ON led is lit it indicates that the Infra Red transceiver the TFDS3000 connected to SCC2 is active and enables communication via that medium When it is dark the I R transceiver is in shutdown mode enabling the use of SCC2 pins off board via the expansion connectors 3 2 15 Ethernet CLSN Indicator LD9 The red Ethernet Collision LED indicator CLSN blinks whenever a collision condition is detected on the ethernet port i e simultaneous receive and transmit 3 2 16 Ethernet PLR Indicator LD10 The red Ethernet TP Polarity LED indicator PLR lights whenever the wires connected to the receiver input of the ethernet port are reversed The LED is lit by the EEST and remains on while the EEST has automatically corrected for the reversed wires 3 2 17 Ethernet LIL Indicator 1 The yellow Ethernet Twisted Pair Link Integrity LED indicator LIL lights to indicate good link integrity on the TP port The LED is off when the link integrity fails 3 2 18 RS232 ON LD12 When the yellow RS232 ON led is lit it designates that the RS232 transceiver connected to SMC1 is active and communication via that medium is allowed When dark it designates that the transceiver is in shutdown mode so SMC1 pins may be used off board via the expansion connectors 3 2 19 PCMCIA ON LD13 When the yellow PCMCIA ON led is lit it indicates the following 1 Address amp strobe buffers are drive
216. ny alternate function B25 E RENA Ethernet Receive Enable In fact PC10 CD1 TGATE1 Active when there is network activity When the ethernet port is disabled via BCSR1 may be used off board for any alternate function B26 PC9 y o PC9 CTS2 Not used on the ADS B27 PC8 PC8 CD2 TGATE2 Not used on the ADS B28 PC7 PC7 L1TSYNCB SDACK2 CTS3 for MPC860 Not used the ADS B29 TPSQEL Twisted Pair Signal Quality Error Test Enable In fact PC6 L1RSYNCB CD3 for MPC860 When active simulated collision state is generated within the EEST so the collision detection circuitry within the EEST may be tested Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value B30 TPFLDL Twisted Pair Full Duplex In fact PC5 L1TSYNCA SDACK1 CTS4 for MPC860 When active the MC68160 EEST is put into full duplex mode where simultaneous receive and transmit are enabled Since after hard reset this line wakes up tri stated it should be initialized as output and given the desired value 93 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 13 P13 Interconnect Signals Pin No Signal Name Attribute Description B31 ETHLOOP Ethernet port Diagnostic Loop Back In fact PC4 L1RSYNCA CD4 for MPC860 When active the MC68160 EEST is con
217. o the card may be cut WARNNING Any application S W handling the PCMCIA channel must check the Voltage Sense lines before Power is applied to the PC Card Otherwise if power is applied to a 3 3V Only card permanent damage might be inflicted to the PC Card The LTC1315 may control power and VPP for 2 PC Cards Since there is only one PCMCIA socket on the ADS the power control lines for the 2 nd socket are used for optional 3 3V supply to the DRAM simm When the DRMPD5 signal is connected to GND the DRAM is powered with 3 3V VCC 4 13 LCD Port Since the I F to the LCD is glueless the only support given by the MPCADS for LCD display connection is a dedicated 30 pin header connector from which a flat cable may be drawn to any kind of screen available A Since there are only 3 RS232 transmitters available DSR will be connected to CD B Le card insertion when the MPCADS is powered 45 Release 1 3a 46 MPCS21ADS Revision A User s Manual Functional Description All LCD Port D pins appear also at P10 and P13 which are the communication connectors It is important to remember that the levels issued by the MPC over the LCD lines are between 0 3 3V Some screens have 5V CMOS compatible inputs for which 3 3V level leaves very small noise margin For this kind of screen it is advised to use CMOS buffers with TTL compatible inputs so that the screen gets its appropriate levels Release 1 3a MPCS21ADS Revision A User
218. ock generator In this mode MODCK 1 2 are driven with 11 during power on reset 2 1 513 PLL operation via on board clock generator In this mode MODCK 1 2 are driven with 10 during power on reset 42 62 Reset Configuration During HARD reset sequence when RSTCONF pin is asserted the data bus state is sampled to acquire the MPC s hard reset configuration The reset configuration word is driven by BCSRO register defaults of which are set during power on reset The BCSRO drives the half configuration word i e data bits D 0 15 in which the reserved bits are designated RSRVxx If the hard reset configuration is to be changed BCSRO may be written with new values which become valid after HARD reset is applied to the ADS On the MPCADS the RSTCONF line is always driven during HARD reset i e no use is possible with the MPC s internal HARD reset configuration defaults To allow user programmable full word hard reset configuration i e D 0 31 lines being driven during HARD reset an option is provided for Flash memory driven hard reset configuration l e the desired hard A It is not a dedicated button B And therefore mentioned C The MODCK lines are in fact driven longer by HRESET line D With respect the ADS s power on defaults 35 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description reset configuration word is taken from the first word of the Flash memory During hard re
219. oding at 100 102 hex in the IBM PC XT AT I O address map These are undefined peripheral addresses 176 Release 1 3a MPCS21ADS Revision A User s Manual Support Information FIGURE A 1 Physical Location of jumper JG1 and JG2 JG1 JG2 NOTE Jumper JG2 should be left unconnected The following figure shows the required jumper connection for each address configuration Address 0 hex is not recommended and its usage might cause problems FIGURE A 2 JG1 Configuration Options O 8 O O O O O 0 hex 100 hex 200 hex 300 hex To properly install the ADI board position its front bottom corner in the plastic card guide channel at the front of the IBM PC XT AT chassis Keeping the top of the ADI board level and any ribbon cables out of the way lower the board until its connectors are aligned with the computer expansion slot connectors Using evenly distributed pressure press the ADI board straight down until it seats in the expansion slot Secure the ADI board to the computer chassis using the bracket retaining screw Refer to the computer Installation and Setup manual for instructions on reinstalling the computer cover C 3 SUN 4 to MPC821ADS Interface The ADI board should be installed in one of the SBus expansion slots in the Sun 4 SPARCstation computer A single ADI can control up to eight MPC821ADS boards 177 Release 1 3a MPCS21ADS Revision A User s Manual Support Informat
220. on A or above Otherwise have no influence 4 143 BCSR1 Board Control Register The BCSR1 serves as main control register on the MPCADS It is accessed at offset 4 from BCSR base 49 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description address It may be read or written at any time BCSR1 gets its defaults upon Power On reset Most of BCSR1 pins are available at the expansion connectors providing visibility towards external logic BCSR1 fields are described in TABLE 4 6 BCSR1 Description on page 50 TABLE 4 6 BCSR1 Description BIT MNEMONIC Function PON DEF ATT 0 FLASH EN Flash Enable When this bit is active low the Flash memory module is enabled on the local memory map When in active the Flash memory is removed from the local memory map and CS0 to which the Flash memory is connected may be used off board via the expansion connectors RW 1 DRAM EN 2 ETHEN Dram Enable When this bit is active low the DRAM module is enabled on the local memory map When in active the DRAM is removed from the local memory map and CS2 and CS3 to which the DRAM is connected may be used off board via the expansion connectors Ethernet Port Enable When asserted low the EEST connected to SCC1 is enabled When negated high that EEST is in standby mode while all its System i f signals are tri stated RW RW 3 IRDEN Infra Red Port Enable When asserted low
221. on the ADS D7 GND D8 PB28 PB28 SPIMISO BRGO4 Not used on the ADS 09 27 PB27 I2CSDA BRGO Not used the ADS D10 PB26 PB26 I2CSCL BRGO2 Not used on the ADS D11 GND D12 SPARE2 MPC spare pin 2 D13 DSDO DSDO TDO Debug Port Serial Data Output JTAG port Data Output Used on the ADS as debug port serial data If the ADI bundle is not connected to the ADS may be used by an external debug JTAG port controllers D14 GND D15 DSCK DSCK TCK Debug Port Serial Clock input or JTAG port serial clock input Used on the ADS as debug port serial clock driven by the debug port controller If the ADI bundle is not connected to the ADS may be driven by an external debug JTAG port controller D16 GND D17 DSDI DSDI TDI Debug Port Serial Data Input or JTAG port serial Data Input Used on the ADS as debug port serial data driven by the debug port controller If the ADI bundle is not connected to the ADS may be driven by external debug JTAG port controller D18 TMS JTAG port Test Mode Select input Used to select test through the JTAG port Pulled up but otherwise not used on the ADS D19 TRST JTAG port Reset Pulled down with a zero ohm resistor so that the JTAG logic is constantly reset D20 GND D21 HSYNC MPC821 s PD4 LOAD HSYNC Not used the ADS Appears also at P11 for convenient LCD connection D22 LD5 MPC821 s PD12 LD5 Not used the ADS Appears also at P
222. ot required A26 ETHEN O L Ethernet Port Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 A27 IRQ3 CR IRQ3 Cancel Reservation input or Interrupt Request line 3 Pulled up but otherwise unused on the ADS A28 IRQ2 VO L RSV IRQ2 Reservation output or Interrupt Request line 2 input Pulled up but otherwise unused on the ADS A29 IRQ1 LL Interrupt Request 1 Pulled up but otherwise not used on the ADS A30 NMI Non Makable Interrupt In fact IRQO of the MPC Driven by on board logic by O D gate May be driven off board by O D gate only 1 RS EN O L 85232 Port Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 A32 GND B1 PB31 PB31 SPISEL RRJECT1 Not used the ADS B2 PB30 PB30 SPICLK Not used on the ADS B3 PB29 PB29 SPIMOSI Not used on the ADS B4 PB28 PB28 SPIMISO BRGO4 Not used the ADS B5 PB27 PB27 I2CSDA BRGO Not used on the ADS B6 PB26 PB26 lI2CSCL BRGO2 Not used the ADS B7 RSTXD RS232 port Transmit Data In fact PB25 SMTXD1 When the RS232 port is disabled via BCSR1 may be used off board for any alternate function B8 RSRXD RS232 Receive Data In fact PB24 SMRXD1 When the RS232 port is disabled via BCSR1 may be used off board for any alternate function B9 RSDTR 85232 port DTR signal In fact PB23 SMSYN1 SDACK1 When the RS232 port is disabled via BCS
223. ound plane of the ads Bypassing capacitors pairs of 0 1uF and 0 01uF are connected as close as possible between VDDSYN and GNDSYN VDDSYN is filtered from the digital supply using a LC filter with a double pole app 500 hz to provide satisfactory attenuation of switching regulators noise over PLL supply lines 4 5 Buffering As the MPCADS is meant to serve also as a hardware development platform it is necessary to buffer the MPC from the local bus so the MPC s capacitive drive capability is not wasted internally and remains avail able for user s off board applications via the expansion connectors Since the total capacitive load over the address lines of all local memory slaves is significant two parallel sets of buffers are provided for address a dedicated group for the Flash memory and PCMCIA U29 U33 amp U34 and a dedicated group for the DRAM part of U30 and U32 Strobe lines are also buffered U30 U35 amp U37 while transceivers are provided for data U39 U42 The data transceivers open only if there is an access to a valid board address or during Hard Reset con figurationC That way data conflicts are avoided in case an off board memory is read provided that it is not mapped to an address valid on board It is the users responsibility to avoid such errors 4 6 Chip Select Generator The memory controller of the MPC is used as a chip select generator to access on board memories saving board s area reducing cost
224. ow external use of SCC1 its pins appear at the expansion connectors and the ethernet transceiver may be Disabled Enabled at any time by writing 1 0 to the EthEn bit in BCSR1 The EEST is configured constantly to Twisted Pair I F with automatic polarity correction enabled There are few control lines which control the EEST function and are driven by parallel I O lines 1 TPSQEL Twisted Pair Signal Quality Error Test Enable This active low signal enables testing of the internal TP collision detect circuitry after each transmit to the TP media It is connected to PC6B of the and should be driven to 1 during normal operation A A manufacturer specific dedicated programming algorithm should be implemented during flash programming B After Hard reset this line wakes up as Tri state For proper operation it should be initialized as Output 43 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 2 TPFLDL Twisted Pair Full Duplex Mode Select This active low signal allows simultaneous transmit and receive over the twisted pair lines without indicated collision This signal is connect ed to PC5 of the MPC and should be driven to 0 during normal operation 3 ETHLOOP Diagnostic Loopback This active high signal puts the EEST in diagnostic loopback mode regardless of the I F type it is configured to This line is connected to PC4 of the MPC and should be driven to 0 during
225. p fb then ADS REO ACTIVE else ADS REO ACTIVI KK KKK KKK lt lt x x KKK WK KKK Wx Wx gt Wx 121 ADI control register The ADI control register is written upon host to ADI write with a D_C line is in control mode It also may be read when StatusRequest bit is active Control register bits description Release 1 3a MPCS21ADS Revision A User s Manual Support Information DebugEntry Bit 0 When this bit is active L the pda will enter debug mode immediately after reset i e DSCK will be held high TE after the rising edge of SRESET When negated DSCK will be held low after the rising edge of SRESET so the pda will start noe running instantly DiagLoopBack Bit 1 When active L the interface is in Diagnostic se Loopback mode I e the source for the Rx shift register is the output of the Tx shift register During that mode x and DSDI are tri stated so no arbitrary data is sent to the n debug port When inactive the interface is in normal mode DSCK and DSDI are driven and the source of the Rx shift as register is DSDO StatusRequest Bit 2 When active L any writ
226. peration To enhance evaluation capabilities support is given to 16 bit and 32 bit data bus width That way users can tailor dram configuration to get best fit to their application requirements When the DRAM is in 16 bit mode half of it is not used i e memory portion that is connected to data lines D 16 31 is not used at all To configure the DRAM for 16 bit data bus width operation the following steps should be taken 1 Setthe Dram Half Word bit in BCSR1 to Half Word See TABLE 4 6 BCSR1 Description on page 50 2 The Port Size bits of BR2 and of BR3 for a 2 bank DRAM SIMM should be set to 16 bits A During read cycles B Normal i e Single Read Single Write Burst Read amp Burst Write C Taking into account support for narrower bus widths 38 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 3 The AM bits in OR2 register should be set to 1 2 of the nominal single bank DRAM simm vol ume or to 1 4 of the nominal dual bank DRAM simm volume If a Dual Bank DRAM simm is being used 4 The Base Address bits in BR3 register should be set to DRAM BASE 1 4 Nominal Volume that is if a contiguous block of memory is desired 5 The bits of ORG register should be set to 1 4 Nominal Volume If the above is executed out of running code than this code should not reside on the DRAM while execut ing otherwise erratic behavior is likely to be demonstrated resulting in a system cras
227. pport Information TABLE 5 1 P1 ADI Port Interconnect Signals Pin No Signal Name Description 18 PD5 Bit 5 of the ADI port data bus 19 PD7 Bit 7 of the ADI port data bus 20 25 GND Ground 26 Not connected with this application 27 29 HOST VCC HOST VCC input from the host Used to qualify ADS selection by the host When host is off the debug port controller is disabled 30 HOST ENABLE HOST Enable input signal from the host Active low Indicates that the host computer is connected to ADS Used in conjunction with HOST VCC and ADS SEL 2 0 to qualify ADS selection by the host 31 33 GND Ground 34 PDO Bit 0 of the ADI port data bus 35 PD2 Bit 2 of the ADI port data bus 36 PD4 Bit 4 of the ADI port data bus 37 PD6 Bit 6 of the ADI port data bus 5 1 2 P2 Ethernet Port Connector The Ethernet connector on the MPCADS P2 is a Twisted Pair 10 Base T compatible connector Use is done with 909 8 pin RJ45 connector signals of which are described in TABLE 5 1 TABLE 5 2 P2 Ethernet Port Interconnect Signals Pin No Signal Name Description 1 TPTX Twisted Pair Transmit Data positive output from the MPC821ADS 2 TPTX Twisted Pair Transmit Data negative output from the MPC821ADS 3 TPRX Twisted Pair Receive Data positive input to the MPC821ADS 4 Not connected 5 Not connected 6 TPRX Twisted Pair Receive Data negat
228. r P11 LCD Connector P13 QUADS Compatible Communication Connector MPC821ADS Part List Programmable Logic Equations U7 Debug Port Controller U10 Auxiliary Board Control U11 Board Control amp Status Register ADI I F ADI Port Signal Description ADI Installation INTRODUCTION IBM PC XT AT to MPC821ADS Interface ADI Installation in IBM PC XT AT SUN 4 to MPC821ADS Interface ADI Installation in the SUN 4 Release 1 3a FIGURE 1 1 FIGURE 2 1 FIGURE 2 2 FIGURE 2 3 FIGURE 2 4 FIGURE 2 5 FIGURE 2 6 FIGURE 2 7 FIGURE 2 8 FIGURE 2 9 FIGURE 2 10 FIGURE 2 11 FIGURE 2 12 FIGURE 2 13 FIGURE 2 14 FIGURE 3 1 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 4 5 FIGURE 4 6 FIGURE 4 7 FIGURE 4 8 FIGURE A 1 FIGURE A 1 FIGURE A 2 FIGURE A 3 MPCS21ADS Revision A User s Manual LIST OF FIGURES MPC821ADS Block Diagram MPC821ADS Top Side Part Location diagram Configuration Dip Switch DS1 U17 Power Sources Power On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection Host Controlled Operation Scheme Debug Port Controller For Target System Operation Scheme Stand Alone Configuration P7 5V Power Connector 12V Power Connector P1 ADI Port Connector P3 RS 232 Serial Port Connector Memory SIMM Installation DS2 Description Refresh Scheme DRAM Address Lines Switching Flash Memory SIMM Architecture RS232 Serial Port Connector PCMCIA Port Configuratio
229. r exist a the on board Dram SIMM is a single bank SIMM or b the Dram is disabled from local memory map via BCSR1 C13 GND C14 WE2 O L In fact WE2 BS2_B PCOE Used as Write Enable 2 for the Flash memory and as a PCMCIA Output Enable C15 BS2A O L Byte Select 2 for UPMA Used for Dram access C16 GND C17 BS1A O L Byte Select 1 for UPMA Used for Dram access C18 TSIZ1 O T S Transfer Size 1 Used in conjunction with TSIZO to indicate the number of bytes remaining in an operand transfer Not used on the ADS C19 GND C20 14 O T S MPC s Address line 14 C21 A13 O T S MPC s Address line 13 C22 GND C23 A10 O T S MPC s Address line 10 C24 A17 O T S MPC s Address line 17 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 6 P6 Interconnect Signals Pin No Signal Name Attribute Description C25 GND C26 A26 T S MPC s Address line 26 C27 A24 T S MPC s Address line 24 C28 GND C29 A2 T S MPC s Address line 2 C30 Al T S MPC s Address line 1 D1 VCC MPC821ADS VCC plane D2 VCC MPC821ADS VCC plane D3 VCC MPC821ADS VCC plane D4 BB VO L Bus Busy Pulled up Not used on the ADS D5 BR VO L Bus Request Pulled Up Not used on the ADS D6 GND D7 BG VO L Bus Grant Pulled Up Not used on the ADS D8 R_W O T S Read Write Us
230. rd programming 12V available only if12V is applied to P8 Controlled by the MPC821ADS via BCSR1 53 PCCA22 PCMCIA Address line 22 54 PCCA23 PCMCIA Address line 23 55 PCCA24 PCMCIA Address line 24 56 PCCA25 PCMCIA Address line 25 57 VS2 Voltage Sense 2 from PC Card Indicates in conjunction with VS1 the operation voltage for the PC Card 58 RESET Reset signal for PC Card 59 WAITA Cycle Wait from PC Card Active low 60 INPACK Input Port Acknowledge Active low Indicates that the Pc Card can respond to I O access for a certain address 61 PCREG Attribute Memory or I O Space Select Active low Used to select either attribute card configuration memory or I O space 62 BVD2 Battery Voltage Detect 2 Used in conjunction with BVD1 to indicate the condition of the PC Card s battery 63 BVD1 Battery Voltage Detect 1 Used in conjunction with BVD2 to indicate the condition of the PC Card s battery 64 PCCD8 PCMCIA Data line 8 65 PCCD9 PCMCIA Data line 9 66 PCCD10 PCMCIA Data line 10 67 CD2 Card Detect 2 Active low Indicates in conjunction with CD1 that a PC Card is placed correctly in socket 68 GND Ground 5 1 5 P5 External Debug Port Controller Input Interconnect The debug port connector P5 is a 10 pin Male header connector signals of which are described in 66 Release 1 3a MPCS82I1ADS Revision A User s Manual Support Information
231. re Relative humidity 25 C to 85 C 5 to 90 non condensing Dimensions Height 9 173 inches 233 mm Depth 7 08 inches 180 mm Thickness 0 063 inches 1 6 mm 2 Release 1 34 MPCS82I1ADS Revision A User s Manual General Information 1 5 MPC821ADS Features d MPC821 running up to 50 MHz mounted on ZIF BGA socket 4 MBytes of 60 nsec DRAM support is given to various types of memory varying from 4MByte configured as 1M X 32 upto 32MByte configured as 8M X 32 Support for EDO page mode DRAM SIMMs made by Micron the MT8D432X and the MT16D832X Automatic Dram SIMM identification 2 MByte Flash SIMM Support for upto 8 MByte Automatic Flash SIMM identification Memory Disable Option for all local memory map slaves Board Control amp Status Register BCSR Controlling Board s Operation Programmable Hard Reset Configuration via BCSR Ethernet port via MC68160 EEST on 5001 with Standby Mode Infra Red Transceiver on SCC2 with Shutdown Option 5V only PCMCIA Socket With Full Buffering Power Control and Port Disable Option Com plies with PCMCIA 2 14 Standard Module Enable Indications RS232 port on SMC1 with Low Power Option On Board Debug Port Controller with ADI I F MPC821 ADS Serving as Debug Station for Target System option LCD Display Connector Optional Hard Reset Configuration Burned in Flash All MPC Pins Available At Expansion amp Logic Analyzer Conne
232. red system with the pda This board could also be used as a demonstration tool i e application s w may be burned into its flash memory and ran in exhibitions etc 1 2 Abbreviations List e PDA Personal Digital Assistant the MPC821 UPM User Programmable Machine GPOM General Purpose Chip select Machine e General Purpose Line associated with the I R Infra Red MPCADS the MPC821ADS the subject of this document Board Control 8 Status Register ZIF Zero Input Force Ball Grid Array 1 3 Related Documentation MPC821 User s Manual MC68160 Data Sheet ADI Board Specification 1 4 SPECIFICATIONS The MPC821ADS specifications are given in TABLE 1 1 TABLE 1 1 MPC821ADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached 5Vdc 1 7 A typical 3 A maximum 12Vdc 1A Microprocessor MPC821 50 MHz A Either on or off board 1 Release 1 3a MPCS21ADS Revision A User s Manual General Information TABLE 1 1 MPC821ADS Specifications CHARACTERISTICS SPECIFICATIONS Addressing Total address range Flash Memory Dynamic RAM 4 GigaBytes 2 MByte 32 bits wide expandable to 8 MBytes 4 MByte 36 bits wide SIMM 32 bit data 4 bit parity option to use higher density SIMM up to 32 MByte Operating temperature 0 C 30 C Storage temperatu
233. rmation equations DSDI oe ADS IS SELECTED amp IN DIAG LOOP BACK avoid junk driven on DSDI input during diagnostic loop back mode when ADS IS SELECTED amp PdaSoftReset then DSDI H else when ADS IS SELECTED amp STATE DSDI ENABLED amp PdaSoftReset then DSDI L else when ADS IS SELECTED amp STATE DSDI ENABLED then DSDI TxReg7 fb else DSDI L TxError This bit of the status register is set 1 when the pda internally resets during data transmission over the debug port When this bit is written 1 by the adi port control the status bit is cleared Writing 0 has no influence on that bit equations Error clk C1k2 Error ar Reset
234. rmined by the HARD Reset configuration B Normal i e boot via CSO 57 Release 1 3 MPCS21ADS Revision A User s Manual Functional Description TABLE 4 16 Debug Port Control Status Register VF BIT MNEMONIC Function Pa ATT DEF 4 3 Reserved Should be always written with 007 00 R W 2 StatusRequest Status Request When the host writes this bit active low the I F will issue 0 R W a status read request to the host by asserting ADS_REQ line to the host When the host writes the control register with this bit negated no status read request is issued Upon I F reset this bit wakes up active 1 DiagLoopBack Diagnostic Loopback Mode When this control bit is active low the I F is 0 R W placed in Diagnostic Loopback Mode l e DSDI is connected internally to DSDO DSDl is tri stated and each data byte sent to the I F data register is sampled back into the receive shift register Using this bit allows to check the I F upto transmit and receive shift registers Upon I F reset this bit wakes up active 0 DebugEntry Debug Mode Entry When this bit is active low the MPC will enter debug 0 R W mode instantly after SOFT reset When inactive the MPC will start executing normally and will enter debug mode only after exception Upon I F reset this bit wakes up active a Provided that the PCMCIA channel II pins are configured as debug pins i e VFLS 0 1 signals are availabl
235. ron 32 MByte SIMM 10 MCM36400 by Motorola or MT8D432X by Micron 16 MByte SIMM 11 MCM36200 by Motorola or MT16D832X by Micron 8 MByte SIMM TABLE 4 11 DRAM Presence Detect 4 3 Encoding DRAM PD 4 3 DRAM DELAY 00 Reserved 01 Reserved 10 70 nsec 11 60 nsec TABLE 4 12 EXTOOLI 0 3 Assignment EXTTOOLI 0 3 External Tool 0000 0111 Reserved 1000 1110 User Available 1111 Non Existent WARNING Since EXTOLI 0 3 lines be DRIVEN LOW 07 by DS2 OFF BOARD tools should NEVER DRIVE them HIGH Failure in doing so might result in PERMANENT DAMAGE to the ADS and or to OFF BOARD logic 4 14 5 BCSR3 Auxiliary Control Status Register BCSR3 is an additional control status register which may be accessed at offset OxC from BCSR base address BCSR3 gets its defaults during Power On reset and may be read or written at any time The de 53 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description scription of BCSR3 is shown in TABLE 4 13 BCSR3 Description on page 54 TABLE 4 13 BCSR3 Description PON MNEMONIC Function ATT DEF Reserved Un Implemented CNT_REG_EN_P Control Register Enable Protect When this bit is active low the 0 ROTECT BCSR EN bit in that register can not be written When in active BCSR EN may be written to remove the BCSR from the memory map After any write to BCSR1
236. rst is sampled 3 system clock cycles prior to the rising edge of SRESET and the second is sampled 8 clocks after that edge B Le DSDI must meat setup hold time to from rising edge of the DSCK C Le full duplex communication 59 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description FIGURE 4 8 MPC821ADS Power Scheme F1 EE 0 38 Expansion Con P7 ANAS PCMCIA lt Buffers ADS Logic amp Peripherals PCMCIA vec F2 Power Control VPP y P8 12V Fe PCMCIA Socket To support off board application development the power buses are connected to the expansion connec tors so that external logic may be powered directly from the board The maximum current allowed to be drawn from the board s various power buses is as follows TABLE 4 17 Off board Application Maximum Current Consumption Power BUS Current 5V 2A 3 3V 0 2V 0 5A 12V 100 mA To protect on board devices against supply spikes decoupling capacitors typically 0 1uF are provided between the devices power leads and GND located as close as possible to the power leads Special care is taken for PLL power leads which has isolated clean ground and filtered VDD 60 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 4 16 1 5V Bus All of the MPCADS peripherals reside on the 5V bus Since the MPC is 5V friendly it may operate with 5V levels o
237. s IRQ6 Not by ADS logic may be configured to alternate function if IRQ6 is not required 76 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 7 P9 Interconnect Signals Pin No Signal Name Attribute Description C6 VFLSO BO IWPO VFLSO PCMCIA slot B Input Port 0 or Instruction Watchpoint 0 or Visible history FLushes Status 0 Configured on the ADS as VFLSO Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alternate function C7 GND C8 AT1 ALE_B DSCK AT1 Address Latch Enable for PCMCIA slot or Debug Serial Clock or Address Type 1 Configured on the ADS as AT1 Not used on the ADS May be configured to alternate function C9 ALE_A Address Latch Enable for PCMCIA slot A Latches address in external latches at the beginning of access to a PC Card C10 GND C11 RESETA O H In fact OPO Serves as PC Card reset signal C12 TEXP O H Timer Expired Not used on the ADS C13 GND C14 GND C15 GND C16 GND C17 BWAITA Buffered PCMCIA slot A WAIT signal Used to prolong cycles to slow PC Cards When the PCMCIA port is disabled via BCSR1 may be used off board C18 BVS1 Buffered PCMCIA slot A Voltage Sense 1 In fact IP_AO Used in conjunction w
238. s Manual Functional Description FIGURE 4 5 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC PCCVPP MCIA POWER NTROL Power Logic From LTC1315 or equiv 5V 12V Data A 15 8 Data A 7 0 lt ANS From BCSR PCMCIA EN MPC821 Transparent latch with OE Address A 25 0 WAIT A lOIS16 RDY BSY A BVD 1 2 A CD 1 2 A VS 1 2 A SPKROUT Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 4 14 Board Control 8 Status Register Most of the hardware options on the MPCADS are controlled or monitored by the BCSR which is a 32 bit wide read write register The BCSR is accessed via the MPC s CS1 region and in fact includes 4 registers 0050 to BCSR3 Since the minimum block size for a CS region is 32KBytes BCSRO BCSR3 are multiply duplicated inside that region See also 3 3 MEMORY on page 20 The following functions are controlled monitored by the BCSR 1 Hard Reset Configuration Flash Module Enable Disable Dram Module Enable Disable Dram port width 32 bit 16 bit Ethernet port Enable Disable Infra Red port Enable Disable 0 Im 85232 port Enable Disable BCSR Enable Disable Hard Reset Configuration Source BCSRO Flash Memory PCMCIA control which include Channel Enable Disable
239. s are available at BCSR S W options may be manually selected according to DS2 state FIGURE 3 1 DS2 Description EXTOLIO Pulled to EXTOLIO Driven to 0 EXTOLI1 Pulled to 1 EXTOLI1 Driven to 0 EXTOLI2 Pulled to EXTOLI2 Driven to 40 EXTOLIS Pulled to 1 EXTOLI3 Driven to 40 DS2 A I e detached from a debug station 17 Release 1 3a MPCS21ADS Revision A User s Manual OPERATING INSTRUCTIONS 3 2 5 44 Power Bridge is soldered jumper which is in series with the 3 3V power bus This jumper may be removed if current measurements on the 3 3V bus are to be held Warning There are also GND bridges on board which physically resemble J4 Do not mistake J4 to be a GND jumper oth erwise permanent damage might be inflicted to the MPC821ADS 3 2 6 GND Bridges There are 4 GND bridges on the MPC821ADS They are meant to assist general measurements and logic analyzer connection Warning When connecting to a GND bridge use only INSULATED GND clips Failure in doing so might result in perma nent damage to the MPC821ADS 3 2 7 RUN Indicator LD1 When the green RUN led LD1 is lit it indicates that the MPC is not in debug mode i e VFLSO amp VFLS1 0 It is important to remember that if the VFLS 0 1 pins are programmed for alternative use rather than function as VFLS lines this indication is meaningless 3 2 8 FLASH ON
240. ser s Manual Support Information Ck k k Ck Ck x Ck ck k x lt x x lt lt x x x AdsAck Host write to ads ack This state machine generates an automatic ADS_ACK during a host to ADS write When the host access the ADS data control register an automatic acknowledge is generated after data has been latched into either the tx shift register or the control register Acknowledge is released when the host removes its write control line HstReq The machine steps through these states 0 ADS ACTIVI 1 ADS ACK ACTIVE x x K lt x lt x lt lt lt equations AdsAck clk C1k2 AdsAck ar Reset AdsAck oe ADS IS SELECTED S HstReq clk Clk2 DS HstReq clk Clk2 5 HstReq HstReq DS HstReq 5 HstReq fb amp HstReq double synced S D C clk C1k2 synchronizing D selector 5 D state_diagram AdsAck state ADS ACK ACTIVI EH if HOST WRITE ADI CONTROL HOST WRITE ADI DATA amp PdaRst fb amp BndTmrExp fb then ADS
241. set this word drives the data bus to set the desired configuration To support this option CS0 of the MPC should be asserted during HARD reset and the ADDRESS lines should be driven low The selection of this option is done via BCSR1 See TABLE 4 6 BCSR1 Description on page 50 The system parameters to which BCSRO defaults during power on reset and are driven at hard reset are listed below 1 Arbitration internal arbitration is selected 2 Interrupt Prefix The internal default is interrupt prefix at OxFFFOOOOO It is overridden to provide interrupt prefix at address 0 which is located within the DRAM 3 Boot Disable Boot is enabled 4 Boot Port Size 32 bit boot port size is selected 5 Initial Internal Space Base Immediately after HARD reset the internal space is located at FF000000 6 Debug pins configuration PCMCIA port B pins become debug support pins 7 Debug port pins configuration Debug port pins are on the JTAG port 8 External Bus Division Factor 1 1 internal to external clocks ratio is selected 4 2 6 3 Soft Reset Configuration The rising edge of SRESET is used to configure the development port Before the negation of SRESET DSCKC is sampled to determine for debug mode enable disable After SRESET is negated if debug mode was enabled DSCK is sampled again for debug mode entry non entry DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET P The So
242. t c It is written in BCSR3 4 14 4 TABLE 4 7 PCCVPP 0 1 Assignment PccvPP o 1 VPR a Provided that a 12V power supply is applied BCSR2 Board Status Register 1 BCSR2 is a status register which is accessed at offset 8 from the BCSR base address Its a read only register which may be read at any time BCSR2 s various fields are described in TABLE 4 8 BCSR2 De A Provided that BCSR is not disabled 51 Release 1 3a scription on page 52 MPCS82I1ADS Revision A User s Manual Functional Description TABLE 4 8 BCSR2 Description BIT MNEMONIC Function PON DEF ATT FLASH_PD 4 1 DRAM_EDO DRAM_PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket U15 There are additional 3 presence detect lines which encode the SIMM s delay but appear in BCSR3 For the encoding of FLASH PD 4 1 see TABLE 4 9 Flash Presence Detect 4 1 Encoding on page 52 Dram Is EDO When this bit is active low it indicates that the DRAM SIMM is capable of EDO burst read When inactive the DRAM SIMM is regular Dram Presence Detect These lines are connected to the DRAM SIMM presence detect lines which encode the size and the delay of the DRAM SIMM mounted on the DRAM SIMM socket U15 For the encoding of DRAM PD 4 1 see TABLE 4 10 DRAM Presence Detec
243. t 2 1 Encoding on page 53 and TABLE 4 11 DRAM Presence Detect 4 3 Encoding on page 53 EXTTOLI 0 3 External Tolls Identification These lines which are available at the expansion connectors are intended to serve as tools identifier or as S W option selection On board s w may check these lines to detect The presence of various tools h w expansions at the expansion connectors or the state of DS2 see FIGURE 3 1 DS2 Description on page 17 or a combination of both Half of the available combinations are reserved while the other half is available to users applications For the external tools codes and their associated combinations see TABLE 4 12 EXTOOLI 0 3 Assignment on page 53 13 31 Reserved Un implemented 52 TABLE 4 9 Flash Presence Detect 4 1 Encoding FLASH_PD 4 1 FLASH TYPE SIZE Reserved MCM29080 8 MByte SIMM by Motorola 29040 4 MByte SIMM by Motorola MCM29020 2 MByte SIMM by Motorola Reserved SM732A1000A 4 Mbyte SIMM by SMART Modular Technologies SM732A2000 8Mbyte SIMM by SMART Modular Technologies Reserved Release 1 3a MPCS21ADS Revision A User s Manual Functional Description TABLE 4 10 DRAM Presence Detect 2 1 Encoding DRAM PD 2 1 DRAM TYPE SIZE 00 MCM36100 by Motorola or MT8D132X by Micron 4 MByte SIMM 01 MCM36800 by Motorola or MT16D832X by Mic
244. t Signals Pin No Signal Name Attribute Description B25 PCCVPPO PCMCIA Card VPP control 0 Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 C1 GND C2 GND C3 GND C4 GND C5 GND C6 GND C7 D7 MPC s data line 7 C8 GND C9 D1 MPC s data line 1 C10 D23 data line 23 C11 GND C12 D17 data line 17 C13 D15 data line 15 C14 GND 15 D9 MPC s data line 9 C16 D31 data line 31 C17 GND x C18 D26 MPC s data line 26 19 ETHEN O L Ethernet Port Enable Connected to BCSR1 5089 93 BCSR1 Board Control Register on page 49 C20 DRAMEN O H DRAM Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 C21 PCCEN O L PCMCIA port Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 C22 GND C23 DRMPD5 Dram Presence Detect line 5 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 C24 DRMPD4 Dram Presence Detect line 4 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 C25 DRMPD3 Dram Presence Detect line 3 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 D1 GND i 86 Release 1 3a MPCS21ADS Revision A User s M
245. t entry else when ADS IS SELECTED amp TxEn fb amp STATE TX ON RISING then DSCK Clk4 debug port clock else when ADS IS SELECTED amp TxEn fb amp STATE TX ON FALLING then DSCK Clk4 debug port inverted clock else when ADS IS SELECTED then DSCK H default value infact X KKK KKK KKK x ck x x x lt lt x x x Debug Port Serial Data in from Pda To provide better hold time for DSDI from the last rising edge of DSCK a dedicated enable for DSDI is provided DSDI_ENABLE x x x x lt lt lt x x lt x KKK KKK KKK KKK equations DsdiEn ar Reset DsdiEn clk Clk2 state diagram DsdiEn state DSDI DISABLED if HOST WRITE ADI DATA amp BndTmrExp fb amp PdaRst fb then DSDI ENABLED else DSDI DISABLED state DSDI ENABLED if STATE TX DISABLED PdaRst fb then DSDI DISABLED else DSDI ENABLED 124 Release 1 3a MPCS21ADS Revision A User s Manual Support Info
246. tegrated into the PCB Gate allocation within UA38 is different from revision PILOT to provide better PCB routing Revision code in BCSR is changed to 2 Added optional RA21 0 ohm 0 01uF for 10 Base T interface network Some SMD pads were enlarged to assist manufacturing Revision ENG to Revision PILOT Changes Added support for ads to function as debug station Added independent 20MHz clock generator for debug port controller Added MUX U38 so that internal logic is clocked by the above generator e Removed pervious debug clock logic derived from CLKOUT of the MPC Added signal named CHINS CHip In Socket active low which is connected to one of the MPC s GND pins isolated from GND layer This signal controls the above mux and the indication LEDs illumination Added pull up resistors on the Chip Select lines to avoid possible data bus contention when MPC is off socket DRAMEN becomes active low to allow buffer manipulation supporting LEDs dark ness when MPC off socket Signal RUN becomes active high from the same reason Sh 1 7 8 9 11 14 Signals EXTM 1 4 changed to BADDR 28 30 AS correspondingly to support future external master support Sh 1 11 13 MODCKO renamed to 2 to comply with MPC s spec convention Sh 1 3 13 Signal BCLOS which was optional for data buffers enable logic is found redundant and re moved from ADS logic Renamed to GPL4A Sh 1
247. the data A In fact only the upper 16 bits D 0 15 are used but the BCSR is mapped as a 32 bit wide register and should be accessed as such B Provided that support is provided also within the MPC C It may be written but will not be influenced D Provided that BCSR is not disabled 48 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description bus to provide the Hard Reset configuration for the MPC this if the Flash Configuration Enable bit in BCSR1 is not active BCSRO may be written at any time to change the Hard Reset configuration of the MPC The new values will become valid when Hard Reset is issued to the MPC regardless of the Hard Reset source The description of BCSRO bits is shown in TABLE 4 5 BCSRO Description on page 49 TABLE 4 5 BCSRO0 Description PON BIT MNEMONIC FUNCTION ATT DEF 0 ERB External Arbitration When 0 during Hard Reset Arbitration is performed 0 RW internally When 1 during Hard Reset Arbitration is performed externally 1 IP Interrupt Prefix When 0 during Hard Reset Interrupt prefix set to 0 RW OxFFF00000 if 1 Interrupt Prefix set to 0 2 Reserved Implemented 0 RW 3 BDIS Boot Disable When 0 during Hard Reset 50 region is enabled for boot 0 RW When 1 CSO region is disabled for boot 4 5 BPS 0 1 Boot Port Size Determines the port size for CSO at boot 00 32 bit 01 700 RW 8 bit 1
248. tion TABLE 5 6 P6 Interconnect Signals Pin No Signal Name Attribute Description A7 GPL5B O L General Purpose Line 5 of UPMB Not used within the ADS 8 GPL4B O L General Purpose Line 4 of UPMB Not used within the ADS AQ GND A10 CE1A O L PC Card Enable 1 for PCMCIA slot A Enables the EVEN address bytes Used by on board PCMCIA port My be used off board when PCMCIA port in disabled 11 CE2A O L PC Card Enable 2 for PCMCIA slot A Enables the ODD address bytes Used by on board PCMCIA port My be used off board when PCMCIA port in disabled 12 GND A13 GPL2 O L In fact GPL2A GPL2B CS2DD General Purpose Line 2 for UPMA or UPMB May also be used as Chip Select 2 Double Drive Not used within the ADS A14 WE1 O L In fact WE1 BS_B1 IOWR GPCM Write Enable1 or UPMB Byte Select 1 or PCMCIA I O Write Used to qualify write cycles to the Flash memory and as Write for the PCMCIA channel A15 GND A16 BS0A O L Byte Select 0 for UPMA Used for Dram access A17 BS3A O L Byte Select 3 for UPMA Used for Dram access A18 GND A19 21 O T S MPC s Address line 21 A20 A7 O T S MPC s Address line 7 A21 GND A22 11 T S MPC s Address line 11 A23 AQ T S MPC s Address line 9 A24 GND A25 A27 T S MPC s Address line 27 A26 A25 TS MPC s Address line 25 A27 GND A28 A23
249. tion TABLE 5 9 P12 Interconnect Signals 85 Pin No Signal Name Attribute Description A22 EXTOLI3 External Tool Identification 3 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 A23 GND i A24 GND 2 25 GND B1 GND B2 GND B3 GND B4 GND B5 GND 5 B6 GND E B7 D6 MPC s data line 6 B8 D4 MO MPC s data line 4 B9 GND B10 D22 data line 22 B11 D20 MPC s data line 20 B12 GND B13 D14 data line 14 B14 D12 MPC s data line 12 B15 GND B16 D30 MPC s data line 30 B17 D28 MO MPC s data line 28 B18 GND B19 EXTOLI2 External Tool Identification 2 Connected to BCSR2 See 4 14 4 BCSR2 Board Status Register 1 on page 51 B20 FCFGEN O L Flash Configuration Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 B21 PCVCCON O L PCMCIA VCC ON Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 B22 GND B23 IRD_EN O L Infra Red Enable Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 B24 PCCVPP1 PCMCIA Card VPP control 1 Connected to BCSR1 See 4 14 3 BCSR1 Board Control Register on page 49 Release 1 3a MPCS21ADS Revision A User s Manual Support Information TABLE 5 9 P12 Interconnec
250. tiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst refresh clock divided by 30 periodic timer enabled type 2 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MCM36400 60 70 MT8D432X 6 7 MCM36800 60 70 MT16D832 6 7 60B21114 30B21114 refresh clock divided by 60 periodic timer enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst refresh clock divided by 30 periodic timer enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst a BR3 is not initialized for 36100 or 36400 DRAM SIMMs 29 Release 1 3a TABLE 3 9 UPMA Initializations for 607566 DRAMs 25MHz MPCS82I1ADS Revision A User s Manual OPERATING INSTRUCTIONS Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 OFFFCCO4 OFFFCC24 OFAFCC24 OFAFCC04 80FFCC84 33FFCC07 1 O8FFCCOO 08FFCC00 08 08AFCCOO 13FFCC04 X 2 33FFCC47 O3FFCCAC 3FBFCC47 01AFCC48 FFFFCC87 X 3
251. ts from the MPC5XX family DSDI is sampled prior 3 system clock cycles to the negation of SRESET to determine the part s configuration source internal default or external via data bus 36 Release 1 3a MPCS21ADS Revision A User s Manual Functional Description 2 32 768 KHz crystal resonator via EXTAL XTAL pair of the MPC 1 513 initial PLL multiplication factor The clock generator 1 above is a 3 3V operated or 5V operated with 3 3V compatible output The selection between the above modes is done using switch 4 of DS1 See 2 3 2 Clock Source Selec tion on page 9 See also 4 2 6 Reset Configuration on page 35 DS1 4 has dual functionality it is re sponsible to the combination driven to the MODCK lines during power on reset and to the connection of the appropriate capacitor between XFC and VDDSYN lines to match the PLL s multiplication factor When 1 5 mode is selected a capacitor of 5nF is connected while when 1 513 mode is selected a 0 68uF capac itor is connected parallel to it via a TMOS gate The capacitors values are calculated to support a wider range of multiplication factors as possible When mode 2 above is selected the output of the clock generator is gated from CLK4IN and driven to 0 constantly so that a jitter free system clock is generated 4 4 1 SPLL Support Since the SPLL requires quiet supplies GNDSYN and GNDSYN have a dedicated ground plane connect ed only in one point to the global gr
252. ule type module 19 title MPC821ADS Board Misc Control Functions x Device declaration 010 device mach220a WK Ck lt KKK Ck x lt lt KKK KK KK lt x KKK 4 mA PEE HERRE LE THE A THE THE 2 Tx THE i dog A 4 5

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