NB3N1200K/NB3W1200L Evaluation Board User's Manual
Contents
1. LOOM_133M Frequency Selection J55 The 100M_133M frequency selection pin can be controlled manually with the High Low header jumper J55 H 100 MHz L 133 MHz 100M_133M_N Figure 7 100M_133M Pin Schematic PCB Configuration PWRGD PWRDNG J56 The PWRGD PWRDN pin can be controlled manually with the High Low header jumper J56 H PWRGD L PWRDN PWRGD oO E TY D lt lt Figure 8 PWRGD PWRDN Pin Schematic PCB Configuration http onsemi com 4 NB3N1200KMNGEVB NB3W1200LMNGEVB Differential Clock Inputs and Outputs Six of the twelve differential outputs are designed to have equal length metal traces from the device pins to the SMA connectors The other six differential outputs have shortened metal traces do not have SMA connectors and can be observed with a high impedance probe on the metal pads provided traces Each DIF_n DIF_n output has a provision for CLoad CLK_IN amp CLK_IN have resistor pads R51 amp R52 to 2 pF capacitors are installed on all outputs GND to terminate a signal generator if used 50 ohm Rs amp Rp pads are located close to the DUT Rs 33 Q is resistors are installed Remove these resistors if CLK_IN installed for both the NB3N1200K and NB3W1200L amp CLK_IN are driven by another IC device NB3N1200K HCSL Outputs CLK_IN amp CLK_IN Differential Clock Inputs The differential Clock input traces CLK_IN CLK_IN are equal length routed straight from the SMA2. e 4 Bottom Power Supply By pass Capacitors Control Pin Traces and Banana Jacks 4 LAYER STACK UP oO ca C4 Ca C4 C4 Ca C4 OC C4 O 10 0 001 0 0007 0 0007 0 5 OZ COPPER ADJUST CORE 0 0014 1 0 OZ COPPER ADJUST PREPREG 0 0014 ADJUST 0 0007 0 0007 0 001 PRIMARY SILK SCREEN PRIMARY SOLDER MASK PRIMARY SURFACE PLATING L1 TOP 0 062 L2 GROUND PLANE L3 POWER PLANE L4 BOTTOM SECONDARY SURFACE PLATING SECONDARY SOLDER MASK SECONDARY SILK SCREEN Figure 11 NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board Layer Stack Up http onsemi com NB3N1200KMNGEVB NB3W1200LMNGEVB NB3N1200K NB3W1200L EVALUATION BOARD SCHEMATIC 01410 oldid 6410 6410 9510 9310 FS310 SAld cA 10 oA ld 1410 e aC er ES er Ir ER Lr C Ti SY Lr aC Ir DO HS or a sr EN br er 964 064 v84 8 4 994 osy 9ry cry ccd 8ly vid Olu OLN LNO O bud OLLNO 6N LNO OC Hd 6LNO 9N LNO OO 9LNO SN LNO OO SLno cN LNO o 2ud O cLNO IN LNO OHO LLNO ely ely O lY 6clu Solu zely 9cly cold bola cl old old 9 d10 Scd D vedl O Ezd D ccdl O 3d D Ocdl1 D 6ldLo 8ldLo Zld1 D 9ldLo SldLo A300Z LE0 TIN INO 300 2 929 EMO a 300 2 ezo cado z
3. 10 FB1 FB2 FB3 FB4 J3 J6 J11 J14 J19 J22 J37 J38 J43 J44 J47 J48 J51 J52 J56 J55 J63 J70 LED1 M1 M8 M10 M12 M14 M17 M19 M21 M23 M25 M9 M11 M13 M15 N N NO R1 R5 R9 R13 R17 R21 R25 R29 R33 R37 R41 R45 R49 R55 R61 R65 R69 R73 R77 R83 R89 R95 R99 R103 NB3N1200KMNGEVB NB3W1200LMNGEVB Table 3 BILL OF MATERIALS FOR THE NB3N1200KMNGEVB EVALUATION BOARD continued Substi Manufacturer tution Designator Qty Description Value Tolerance Part Number Allowed R3 R7 R11 24 Resistor 49 9 Q 1 0402 Panasonic ERJ 2RKF49R9X Yes Yes R15 R19 R23 R27 R31 R35 R39 R43 R47 R53 R59 R63 R67 R71 R75 R80 R86 R91 R97 R101 R105 R10 R14 R18 12 Resistor 0 Q Jumper 0402 Vishay CRCW04020000Z0ED Yes Yes R22 R42 R46 R50 R56 R78 R84 R90 R96 R57 R58 R79 Resistor 4 7 kQ 0603 Panasonic ERJ 3GEYJ472V R82 R85 R88 5 R94 R93 EME Resistor MES 20 MEN 0803 Panasonic ERJ SGEYJ2R2V 3GEYJ2R2V R108 R109 Resistor 8259 5 Q OO Panasonic ERJ 2RKF82R5X 2RKF82R5X E SE R110 R111 E 10 ESE a a 2GEJ103X R114 R116 R118 R112 R113 Resistor Jumper oe ee 1GEOROOC R121 R132 1 MIE Resistor 12 29 s ERJ 2RKF1202X sss isi TP1 TP2 TP3 Test Point Test Point TP_5015 KEY Keystone 5015 TP4 TP5 TP6 SMT STONE TP13 TP14 U3 1 93LC46B 8 TSSOP 93
4. 125 300 2 029 300 2 619 o 819 8N LINO 3002 219 Sino 5 zado 919 ZN IMO 400 2 GLO ZM 2 zado vlO 400 2 49 400 2 319 adoz H3 400 2 049 YN INO d0 2 69 vino d0 2 89 EN INO d0 2 LO ELNO paa 99 30028 S9 pa vO gee pai Z ON INO A 19 0LNO S z8 6014 LNOGs CO 028 vidl 80lu LNOGs O Sp EldL ZOLY 6 6r OLY ge Pon OLY OLY se Et 66H 16 se oip G6Y L6H se Pa 68H 98H se nee 8y 084 se ER LLH GZH se siat H IZH ge ae 69H 194 ge st SOU 69H se So L9H 6SH se T SSH ESH se m 6vy vu ge SE SrH ery se Lyd 6 H se N eu Seu ge P ESH LEH se wey 6zH 34 ge gas Gey EZH ee gies Leu 6LY se AE 18 GLY se TA ely LLY cf tap 6H ZY ge i SH H se LY LN 30 Ltda OLN dd OlAIG 6NdIG 8NdIGd 2N310 9N310 SN310 VNAIC EN3Id N31d LNdIG GIIA LLN Ald 88H MY Z8u aDUMA adn _ N Weel WOO daa N dla MY N81 dA8 MEH gsu MEH N NTO 66h gt NOTO HN 30 OLN 30 6N 30 8N 30 N 30 9N 30 GN 30 YN 30 EN 30 ZN 30 f LN 30 MOO LNEGN ING LN 43u00 4u00 1 4u001 Z 9 989 GeO veo e89 OVS u00 ES 4u00 1 Lu001 E R po 0 9 629 829 L29 Our IH WS gor hes ae Zor 628 aaa a4 rater z Le Ip SSr OMSH po 99 Yzy 5 IMSH 258 Gor A m N NITO 6 6y F 80130 00130 NITO aN9 Lor AQ a ao we OldaA s oor cd
5. connectors on the left side directly to the DUT there are no vias on metal DIF_n and DIF_n Differential Outputs RP is not installed on the six output pair with long metal NB3N1200KMNGEVB and NB3W1200LMNGEVB traces to SMA connectors Use 50 Q to GND of the were designed with a flexible PCB layout configuration to oscilloscope head for RP measure the differential HCSL 1200K or Push Pull Rp is installed 50 42 to GND on the short metal traces 1200L outputs with a 50 ohm scope head or without SMA connectors and will use Hi Z probes high impedance FET probe See Output Layout in Figures 8 and 9 NB3W1200L Push Pull Outputs Rp is not installed Table 2 NB3N1200KMNGEVB AND NB3W1200LMNGEVB OUTPUT LOAD AND TERMINATION VS OSCILLOSCOPE MEASUREMENT 1200K Open DN R33 OUT4 pir 4 84 DIF A 1 2 eee EA 33 1 2 35 DIF_N4 1 R37 2 49 9 c9 2 0pF OUT_N4 DIF_4 T R39 2 O TP20 DIF_4 33 1 2 49 9 2E 33 1 R43 o 4 2 1 R125 2 0 499 l 0 PR amp Q DIE 5 39 DIF_N5 1 R45 D C11 2 0pF T OUT_N5 1 R46 o aii me DIE 5 ETE T 1 R126 2 0 33 ww 2 i C12 2 0pF 0 DIF_4 DIF_4 From DUT Output gt Fron DUT ouput gt DIF_4 DIF 4 Figure 9 Differential Outputs Schematic PCB Configuration Long vs Short Metal Traces http onsemi com 5 NB3N1200KMNGEVB NB3W1200LMNGEVB HCSL Output Measurement HCSL outputs are typically terminated with 50 Q to ground Measuring
6. http onsemi com EVAL BOARD USER S MANUAL e The NB3W1200LMNGEVB does not have RP resistors installed on its differential Push Pull outputs e The NB3W1200LMNGEVB does not have FB_OUT FB_OUT resistors installed e The NB3W1200LMNGEVB does not have RREF resistor R107 installed This manual should be used in conjunction with the device datasheet which contains full technical details on the device specifications and operation This evaluation board manual contains e Information on the NB3N1200K NB3W 1200L Evaluation Board e Assembly Instructions e Test and Measurement Setup Procedures e Board Schematic and Bill of Materials AN III II igu I x9403 0K 30716002 Bottom View Figure 1 NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board Semiconductor Components Industries LLC 2013 December 2013 Rev 0 Publication Order Number EVBUM2216 D NB3N1200KMNGEVB NB3W1200LMNGEVB QUICK START LAB SET UP USER S GUIDE Pre Power Up 1 The NB3N1200K and NB3W1200L have positive power supply pins VDD and VDDIO Connect power supply cables to VDD VDDIO and GND banana jacks do not turn power on yet 2 Connect a signal generator to the SMA connectors for the CLK_IN amp CLK_IN inputs 3 50 ohm termination resistors are installed for a signal generator on the board Set appropriate input signal levels HCSL input VIL 0 V VIH 700 mV Frequency 100 or 133 33 MHz 4 Ensure the PWRGD PWRDN pin
7. 00K or NB3W1200L e The single board design and layout accommodates the electrical characterization of either the NB3N1200K standard HCSL outputs or the NB3W1200L HCSL Push Pull outputs e Incorporates on board I2C SMBus interface circuitry powered from a USB connection minimizing cabling e Convenient and compact board layout e 3 3 V power supply device operation e Differential inputs outputs signals are accessed via SMA connectors or high impedance probes Other Board Features There are no vias on the high speed differential I O metal traces so as to eliminate via impedance and stub affects Board stand offs are installed Board Layout The NB3N1200K QFN 64 Evaluation Board provides ahigh bandwidth 50 controlled trace impedance environment 100 92 line to line differential and is implemented in four layers e All layers are constructed with FR4 dielectric material e The first layer is the primary signal layer including all of the differential inputs and outputs e The second layer is the ground plane It is dedicated for the DUT ground SMA ground plane e The third layer is dedicated as the power plane A portion of this 3 layer is designated for the device VDD and VDDIO power planes e The fourth layer contains control lines power supply banana jacks and device power pin bypass capacitors Layer Stack e Ll Top Signal e 2 Device Ground and SMA Ground e L3 VDD VDDIO Separate Device Power Supplies
8. 200L 64 64 QFN9mm 9 64 QFN9mm ON Semiconductor Semiconductor x NBSW1200LMNG FT2232H 64 QEN AA FT2232HQ REEL i 93LC46B 8 TSSOP Microchip x SBLC46BT ST P a MON U4 1 NCP4586 SOT 23 5 ON Semiconductor 3 3 V ca TP1 TP6 Test Point Test Point TP_5015_ TP13 TP14 SMT KEYSTONE U2 ON Semiconductor and ON are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights o
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10. HCSL outputs can be easily accomplished by NB3N1200K HCSL Outputs 50 Q Oscilloscope Head With Rp removed from board connect the HCSL outputs through the SMA connectors to the 50 Q internal impedance of the oscilloscope sampling head NB3N1200K HCSL Outputs Use Hi Z Probe With Rp installed use a high impedance probe on the output s metal trace Holes for headers to connect to Hi Z probes are available but the header pins are not installed e Single ended Hi Z probes or e Differential Hi Z probe see layout below NB3W1200L Push Pull Outputs Use Hi Z Probe Rp is not installed e A 0 Q series resistor is installed between the end of the transmission line and the SMA connector This resistor can be removed if needed to eliminate any SMA impedance stub when using Hi Z probes e Asa feature an optional component can be installed on each output 1e additional capacitance loading etc The following figures describe the boards output features Figure 10 Differential Outputs Schematic PCB Configuration Use Hi Z Probe Scope for NB3W1200L Misc Pins FB_OUT amp FB_OUT External Termination of Feedback Pins FB_OUT amp FB_OUT have convenient test point anvils to monitor these pins with Hi Z probe NB3N1200K HCSL Since the FB_OUT amp FB_OUT pins do not drive transmission lines no SMAs the board layout has these pins loaded terminated at the DUT per datasheet 83 2 to GND i
11. LC46BT I ST 3 3 V MT http onsemi com 11 NB3N1200KMNGEVB NB3W1200LMNGEVB Table 4 BILL OF MATERIALS FOR THE NB3W1200LMNGEVB EVALUATION BOARD Substi Manufacturer tution Lead w Description Value Tolerance Part Number Allowed Free E J Board E J Board mae C21 C23 Capacitor 2 0 pF 12 a C1005C0G1H020C C26 C31 C24 C25 Capacitor 100 nF 10 0402 0402ZD104KAT2A C28 C30 C34 C41 C43 C45 C47 C49 C52 C58 INC 2 ose s s owe TI ESO ve ves MEE o owe 2 m ren A se Ys ESD PACDN004 SOT 143 ON Semiconductor PACDN004SR Suppressor 4 CHANNEL PROTECTION EMI Filter 600 Q 0603 Murata BLM18KG601SN1D Bead Bead RF Connectors SMA_END_LA Johnson 142 0701 801 Yes Yes PC END MT UNCH_0 062 Components JCK GLD 062 Header Header FCI 67996 206HLF Yes Yes Thru Hole 2 x 3 Header Header 3 pin Header 3M 961103 6404 AR Yes Yes 3 pin thru hole 0 1 Banana Jack CON2_ 571 050 Deltron 571 0500 Yes Yes Thru Hole 0 DELTRON Red Banana Jack CON2_ 571 050 Deltron 571 0700 Yes Yes Thru Hole O DELTRON Yellow Banana Jack CON2_571 050 Deltron 571 0100 Yes Yes Thru Hole O DELTRON Black CONN USB SMT USB On Shore USB B1SMHSW6 Yes Yes TYPE B R A Conn B Technology HORIZ SMD Header Header 2 pin Header 3M 961102 6404 AR Yes Yes 2 pin thru hole 0 1 LED GREEN LED Green 0603 LED Lite On LTST C190KGKT CLEAR 0603 SMD CONN Shunt 2 54 x 5 97 Sullins QPCO2SXGN RC JUMPER mm SHORTING 100 GOLD STANDOFF
12. NB3N1200KMNGEVB NB3W1200LMNGEVB NB3N1200K NB3W1200L Evaluation Board User s Manual Introduction The NB3N1200KMNGEVB and the NB3W1200LMNG EVB evaluation boards were developed with a common PCB layout design to accommodate the NB3N1200K standard HCSL outputs and the NB3W1200L HCSL Push Pull outputs devices Each board comes fully assembled and tested and is ready to evaluate in the lab This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the operation of the NB3N1200K or NB3W1200L devices To minimize the board size six differential outputs are accessed with SMA connectors The other six differential outputs are loaded terminated and can be monitored with a high impedance probe as explained later in the manual The NB3N1200K Evaluation Board schematic is the same as the NB3W1200L schematic except the 1200L has some components depopulated DNI per the 1200L BOM 3 s 1 paa E El a y A i 1 Laos ae b MT L 4 2 eq kata E gt a A 293 Y H e iso la y tw a 3 33 EFS OE 9 OE xo H DS AS x 1 HA sh bd an Y ae AT ws a DSA w H REF l a CLKIN L a wakaq 13 ICLKINF SIDE lt lt voor UE e E sE 0 pias be de H 33 i ss NB3N1200K N83W1200L sde AWW DEMO BOARD Top View ON Semiconductor
13. Standoff Keystone 1808 4 40 4 40 ALUMINUM 1 4 x 5 8 5 8 Screw Building Fasteners PMS 440 0025 PH 4 40 x 0 25 PHP Resistor 0402 Panasonic ERJ 2RKF33ROX http onsemi com 12 FB1 FB2 FB3 FB4 J3 J6 J11 J14 J19 J22 J37 J38 J43 J44 J47 J48 J51 J52 J56 J55 N J63 J70 LED1 M1 M8 M10 M12 M14 M17 M19 M21 M23 M25 M9 M11 M13 M15 N N R1 R5 R9 R13 R17 R21 R25 R29 R33 R37 R41 R45 R49 R55 R61 R65 R69 R73 R77 R83 R89 R95 R99 R103 NB3N1200KMNGEVB NB3W1200LMNGEVB Table 4 BILL OF MATERIALS FOR THE NB3W1200LMNGEVB EVALUATION BOARD continued Substi Manufacturer tution Designator Qty Description Value Tolerance Part Number Allowed R3 R7 R11 DNI 0402 Yes R15 R19 R23 R27 R31 R35 R39 R43 R47 R53 R59 R63 R67 R71 R75 R80 R86 R91 R97 R101 R105 R10 R14 R18 12 Resistor 0 Q Jumper 0402 Vishay CRCW04020000Z0ED Yes Yes R22 R42 R46 R50 R56 R78 R84 R90 R96 R57 R58 R79 Resistor 4 7 kQ 5 0603 Panasonic ERJ 3GEYJ472V R82 R85 R88 NE x R93 R94 R94 x Resistor MEN 20 x OO Panasonic ERJ 8GEYJ2R2V 3GEYJ2R2V R108 R109 NOT R110 R111 10 lt eo 2GEJ103X R114 R116 R118 R112 R113 Resistor Jumper a See 1GEORO0C R121 R132 F 1 MIE Resistor 12 29 6 ERJ 2RKF1202X E R120 E E 22 KQ 0402 Panasonic ERJ 2GEJ222X 2GEJ222X 1 NB3W1
14. d opt a ad Es Ht esr lgd vas gt TOS EP i NI3 19 QF NIM gt Lolo 30 Z Figure 12 NB3N1200KMNGEVB amp NB3W1200LMNGEVB Board Schematic I com ionsemi http NB3N1200KMNGEVB NB3W1200LMNGEVB aNd cI dl aNd bkdL aN9 OldL aNd d AOL AOL 4uool des ON OND 969 dnt l Ba LNO NI A amp E 98StrdON eA CI PN 8dl EAE AS gsn Co dl taal OLY y 6LLY asn L E vOONGOVd Ld 1831 En N N3EMd N qN3dSnS 3d01 ESO pO ZHN cl LJ LA 2 4do 199 ASL AZL 059 N 13938 llu N 1SH gSn EAE qNSV aND aND aND GNS GNS qNS aND qNS Vivdaa 11933 s934 sngog 9Sndod gsnada vsnada esnadg snada ISN osngog snada e9snada gsnadg vsnada esnada snada isnada osnada ZHOld9 9HOId9 SHOId9 vHOIdO HOldS cHOId9 LHOIdD OHOId9 10ld9 210ld9 L1OIdS 0101d9 SNL oal IdQ1 MOL Hzezzld EAE on a q I q O q MS EN N a 6S 8G S OL G 8 Lu VG G L S Op r rr r v OV 6 801 30 AE 00l 30 q od O 01 Li 7 01 2 Lu EAE vor cor g9v0 1 6 1nNOA NIG 119 S vas C_ 9d1 qos C_ Gdl en GNS EAE gt LL olol 30 gt WAS 22 10S Figure 13 USB Circuitry Schematic I com ionsemi http NB3N1200KMNGEVB NB3W1200LMNGEVB Table 3 BILL OF MATERIALS FOR THE NB3N1200KMNGEVB EVALUATION BOARD Substi Manufacturer
15. f others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 e I f Fax 303 6
16. is in the Low state before power up PWRDN There is a jumper on pin 6 to easily select between High and Low See Figure 8 5 The 1OOM_133M and HBW_BYPASS_LBW pins need to be hardware selected with jumpers See Figures 4 and 7 6 To monitor the DIF_n DIF_n outputs connect the DIF_n DIF_n outputs to the appropriate oscilloscope Signal Generator cies T TH piris Table 1 POWER SUPPLY CONNECTIONS Device Pin Power Supply Connector Power Supply VDD VDDIO 1 05 V to 3 3 V Dual Power Supplies a 105Vto33V OV Single Power Supply 3 3 V F VDD VDDIO GND VDD GND I J 1 05 V to 3 3 V J 3 3 V 3 3 V Figure 2 Power Supply Connections Oscilloscope Figure 3 Typical Lab Test Set Up Power Up Sequence 1 Turn on power supply 3 3 V VDD VDDIO 2 Move PWRGD PWRDN jumper from Low to logic High PWRGD position 3 Turn on the Differential Clock Signal for the CLK_IN inputs The differential Clock signal for the CLK_IN inputs can be ON or active before or after PWRGD is set HIGH 4 Monitor DIF_n DIF_n outputs on oscilloscope Optional Graphical User Interface see page 7 There is a stand alone Graphical User Interface software package and user s manual that will interface with the DUT via the USB connector 1 Connect the USB port on the evaluation board to a USB port on the PC via cable 2 See the stand alone GUI instructions document 3 Allow Windows
17. s installed for the 100 2 board NB3W1200L Push Pull FB_OUT amp FB_OUT resistors are not installed IREF Pin NB3N1200K HCSL The Rpgr resistor R107 to GND for the HCSL output part device Ree 475 4 is installed for the 100 Q board NB3W1200L Push Pull RrEF is not installed for the NB3W1200L device http onsemi com NB3N1200KMNGEVB NB3W1200LMNGEVB Graphical User Interface GUI USB amp I C SMBus Interface The NB3N1200K EVB has an on board 12C SMBus interface circuitry located in the upper left section of the board This circuitry will interface with the software program and the device via the SDA and SCL input pins and can control all twelve of the OE_n pins PLL Mode and Frequency Select directly from the GUI SCL amp SDA The SMBus Clock SCL and Data SDA pins are exercised through the on board I C interface In order to enable the IC control of the DUT header jumpers J63 amp J64 must be shorted The I2C SMBus interface circuitry is powered separately from the USB type B connection and is isolated from device VDD and VDDIO The SDA and SCL pins can also be externally accessed by an off board programmer allowing other SMBus emulators to be used to program the DUT If used remove both jumpers J63 amp J64 Test point anvils TPS amp TP6 are available for external control of the device with the use with mini grabber cables BOARD FEATURES Single Board Design Layout for NB3N12
18. to install the necessary drivers for the eval board USB interface hardware 4 Start the GUI program http onsemi com 2 NB3N1200KMNGEVB NB3W1200LMNGEVB Power Supplies Each VDD VDDIO and GND power supply has a separate side launch banana jack located on bottom side This board is capable of measuring device IDD amp IDDIO separately Board Layer 2 SMA Ground Device GND 0 V GND Banana Jack negative power supply for DUTGND and SMAGND Exposed Pad EP The exposed pad footprint on the board is soldered to the exposed pad of the QFN 64 package and is electrically connected to GND power supply Board Layer 3 VDD and VDDIO Power Supplies VDD positive power supply for core and inputs VDD VDDA VDDR pins 1 8 24 40 57 VDDIO positive power supply for outputs VDDIO pins 25 32 49 56 VDD amp VDDIO have the power supply filtering per datasheet by the banana jacks All VDD VDDA VDDR VDDIO device pins have a 0 1 uF bypass capacitor installed on top side next to package pins Control Pins Each control pin can be managed manually with a H L jumper header H VDD L GND Tri Level Input Pins HBW_BYPASS_LBW7 SAO and SA1 The three tri level input pins HBW_BYPASS_LBW3 SAO and SAI have selectable with jumper 4 7 k ohm pull up to VDD and 4 7 k ohm pull down to GND resistors No jumper defaults to open float e For a HIGH Level Put Jumper to High e For a LOW Level Put J
19. tution Lead w Description Value Tolerance Part Number Allowed Free E J Board E J Board mae C21 C23 Capacitor 2 0 pF 12 a C1005C0G1H020C C26 C31 C24 C25 Capacitor 100 nF 10 0402 0402ZD104KAT2A C2 C30 C34 C41 C43 C45 C47 C49 C52 C58 INC 2 ose s s owe TI ESO ve ves MEE o owe 2 m ren A se Ys ESD PACDN004 SOT 143 ON Semiconductor PACDN004SR Suppressor 4 CHANNEL PROTECTION EMI Filter 600 Q 0603 Murata BLM18KG601SN1D Bead Bead RF Connectors SMA_END_LA Johnson 142 0701 801 Yes Yes PC END MT UNCH_0 062 Components JCK GLD 062 Header Header FCI 67996 206HLF Yes Yes Thru Hole 2 x 3 Header Header 3 pin Header 3M 961103 6404 AR Yes Yes 3 pin thru hole 0 1 Banana Jack CON2_ 571 050 Deltron 571 0500 Yes Yes Thru Hole 0 DELTRON Red Banana Jack CON2_ 571 050 Deltron 571 0700 Yes Yes Thru Hole O DELTRON Yellow Banana Jack CON2_571 050 Deltron 571 0100 Yes Yes Thru Hole O DELTRON Black CONN USB SMT USB On Shore USB B1SMHSW6 Yes Yes TYPE B R A Conn B Technology HORIZ SMD Header Header 2 pin Header 3M 961102 6404 AR Yes Yes 2 pin thru hole 0 1 LED GREEN LED Green 0603 LED Lite On LTST C190KGKT CLEAR 0603 SMD CONN Shunt 2 54 x 5 97 Sullins QPCO2SXGN RC JUMPER mm SHORTING 100 GOLD STANDOFF Standoff Keystone 1808 4 40 4 40 ALUMINUM 1 4 x 5 8 5 8 Screw Building Fasteners PMS 440 0025 PH 4 40 x 0 25 PHP Resistor 0402 Panasonic ERJ 2RKF33ROX http onsemi com
20. umper to Low e For a MID Level Put Jumper to both High and Low this will Enable both Pull up and Pull down Resistors HBW_BYPASS_LBW At J65 and J66 headers there is a 4 7 KQ pull up to VDD and a 4 7 KQ pull down resistor to GND for manual control See Figure 4 SAO amp SA At J67 and J69 headers there are 4 7 KQ pull ups to VDD and at J68 and J70 there are 4 7 k62 pull down resistors to GND for manual control See Figure 5 HBW_BYP_LBW HBW LO Figure 4 HBW_BYPASS_LBW Schematic PCB Configuration SAO SA1 SAD LO mam R82 a R79 Jeg JM SAO HI e ES mr VDD R85 pr on SA1 HI J69 J67 1 2 SAO Cl J68 R82 E dls SAO HI 1 2 1 2 EE SA0 LO 4 7K J69 SA1 oo a 14 SA1 SA1 HI 1 2 1 2 EE SA1 LO 4 7K Figure 5 SAO amp SA1 Schematic PCB Configuration http onsemi com NB3N1200KMNGEVB NB3W1200LMNGEVB Control Pins Continued OE_n Pins Output Enable Disable Function All twelve of the OE_n s can be controlled individually Six of the twelve differential outputs that have metal automatically by using the software GUI GUI control is traces going to SMA connectors have OE_n pins on the left accomplished via the USB when the OE_n jumper is side of the board that can be controlled manually using the installed on the middle header position See Figure 6 convenient High Low OE_n jumpers See Figure 6 OE USB GUI Figure 6 OE_n Pins Schematic PCB Configuration
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