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Internal Memory (RAM and ROM) User Guide

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1. TriMatrix Memory Blocks Valid Range 7 M144K 4 096 13 1072 M9K 128 8 192 MLAB 32 64 2 M512 32 64 M4K 128 4 096 M RAM 4 096 65 536 Notes to Table 5 1 The maximum block depth must be in a power of two 2 The maximum block depth setting for MLAB is not available for Stratix III devices The MegaWizard interface prompts an error message if you enter an invalid value for the maximum block depth You are advised to set the value to Auto if you are not sure of the appropriate maximum block depth to set or the setting is not important for your design This setting enables the compiler to select the maximum block depth with the appropriate port width configuration for the type of TriMatrix memory block of your memory Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Clocking Modes and Clock Enable Page 11 Clocking Modes and Clock Enable Altera memory supports various types of clocking modes depending on the memory mode you select Table 6 shows the supported types of clocking modes in most Altera devices Table 6 Supported Types of Clocking Modes in Most Altera Devices Clocking Modes a ind ua True mut Tri port RAM us ul Ed Single clock v v v v v v Read Write X v X v X X Input Output v v v v v v Independent X X v X X v La Asynchronous clock mode is only supported in MAX series of devices and not November 2009 Altera
2. Parameter Name indata aclr a indata aclr b address aclr a address aclr b byteena aclr a byteena aclr b wrcontrol aclr a wrcontrol aclr b Type String Required Optional Description Optional parameters to specify which input registered ports are affected by asynchronous clear Values are CLEARO and NONE The following list shows the respective parameters and controlled ports m indata aclr a data a port m indata aclr b data b port m address aclr a address a port m address aclr b address b port m byteena aclr a byteena a port m byteena aclr b byteena b port m wrcontrol aclr a wren a port L wrcontrol aclr b wren b port The asynchronous clear might not affect all the input registered ports and thus some of the parameters might not be applicable For Stratix Il Stratix Il GX Cyclone Il and Arria GX devices all the parameters are not applicable For Stratix Ill Cyclone III Arria Il GX and newer devices the CLEARO is only applicable for m address aclr_b parameter if operation mode is set t0 DUAL PORT m address aclr_a parameter if operation_mode is set to ROM Set the parameters to NONE whenever the parameters are not applicable For more information about registered input ports that can be affected by the asynchronous clear port for different target devices memory mode and memory block refer to Asynchronous Clear on page 14 outdata aclr a outdata aclr b eccstatus
3. Figure 3 shows the block diagrams of a true dual port RAM Figure 3 True Dual Port RAM gt data a data b address a address b 4e wren a wren b 4 byteena a byteena b V addressstall a addressstall b 4 clock a clock b lt lt dena gt ara 4 R q_al gt November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 4 In a tri port RAM two read address ports and one write address port are available two read ports and one write port Figure 4 shows the block diagrams of a tri port RAM Figure 4 Tri Port RAM data rdaddress a e wraddress rden a 44 qal rdaddress b 44 wrclocken rden b 4 rdclocken 4 acl 4 In single port ROM only one address port is available for read operation Figure 5 shows the block diagrams of a typical single port ROM The dual port ROM has almost similar functional ports as single port ROM The difference is dual port ROM has an additional address port for read operation Figure 5 Single Port ROM address addressstall a outclocken al inclocken outaclr Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Memory Block Types Page 5 Me
4. Port Width Configuration Memory Depth x Data Width Internal Memory RAM and ROM User Guide The port width configuration is defined as the memory depth number of words x the width of the data input bus Table 3 shows the supported port width configuration per memory block for TriMatrix memory blocks in Stratix III devices Table 3 Port Width Configuration for TriMatrix Memory Blocks in Stratix III Devices MLABs M9K M144K 16 x8 8Kx1 16Kx8 16x9 4Kx2 16Kx9 16 x 10 2Kx4 8Kx 16 16 x 16 1Kx8 8Kx18 16 x 18 1Kx9 4Kx 32 16 x 20 512 x 16 4Kx 36 512 x 18 2K x 64 1 256 x 32 1 2K x 72 1 256 x 36 1 Note to Table 3 1 Only applicable for single port RAM simple dual port RAM and single port ROM For more information about the supported port width configuration for different TriMatrix memory blocks refer to the TriMatrix Embedded Memory Blocks chapter in your target device handbook If your port width configuration either the depth or the width is more than the amount a TriMatrix memory block can support additional memory blocks of the same type are used For example if you configure your M9K as 512 x 36 which exceeds the supported port width of 512 x 18 two M9Ks are used to implement your RAM In addition to the supported configuration provided you can set the memory depth to a non power of two but the actual memory depth allocated can vary The variation depends on
5. Power Up Conditions and Memory Initialization on page 17 Error Correction Code ECC on page 18 Design Example External ECC Implementation with True Dual Port RAM on page 19 Ports and Parameters on page 28 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 2 Memory Modes Memory Modes Altera provides the following memory modes that you can create using the corresponding MegaWizard interfaces listed in brackets m Single port RAM RAM 1 Port m Simple dual port RAM RAM 2 Port True dual port RAM RAM 2 Port Tri port RAM RAM 3 Port Single port ROM ROM 1 Port Dual port ROM ROM 2 Port You can find these MegaWizard interfaces under the Memory Compiler category when you launch the MegaWizard Plug In Manager In general the memory block contains two address port port A and port B with their respective output data ports and you can use them for read and write operations depending on your memory modes This section shows the different memory modes with their input and output ports in a block diagram La The input and output ports shown in the block diagrams are referring to the ports of the wrapper that contains the memory megafunction instantiated in it The port name reflects the usage related to the memory features you created For example byteena relates to the byte enable feature addresstall relates to the address clock enable features and so on You can find
6. The read during write RDW occurs when a read and a write target the same memory location at the same time You can use the RAM MegaWizard interface to configure the RDW output behavior of your RAM There are two types of RDW operations available same port and mixed port The same port RDW occurs when the input and output of the same port access the same address location with the same clock The mixed port RDW occurs when one port reads and another port writes to the same address location with the same clock The available output choices for the RDW behavior vary depending on the types of RDW and TriMatrix memory block in use Table 9 shows the available output choices for the same port and mixed port RDW for different TriMatrix memory blocks Table 9 Output Choices for the Same Port and Mixed Port Read During Write Simple dual port RAM 2 True dual port RAM Single port RAM 7 Memory Block Types Same port RDW Mixed port RDW Same port RDW 3 Mixed port RDW 4 M512 No MW 5 Old Data NA M4K Don t Care No MW 5 Old Data Don t Care M RAM Don t Care Don t Care MLAB Don t Care Old Data NA Don t Care MLAB is not supported in tdp RAM M9K Don t Care Old Data New Data 6 Old Data M144K New Data 6 Don t Care Old Data Don t Care Old Data LCs No MW 5 NA Notes to Table 9 2 wo 5 6 1 Single port RAM only supports same port R
7. For more information about TriMatrix memory blocks and the specifications refer to the TriMatrix Embedded Memory Blocks chapter in your target device handbook From the MegaWizard interface you can implement your memory in any of the supported TriMatrix memory blocks available based on your target device You can also choose to implement the memory using logic cells or allow the software to automatically select the appropriate TriMatrix memory resource If you want to specifically select the TriMatrix memory block obtain more information about the features of your selected TriMatrix memory block in your target device such as the maximum performance supported configurations depth x width byte enable power up condition and the write and read operation triggering As compared to TriMatrix memory resources using logic cells to create memory reduces the design performance and utilizes more area This implementation is normally used when you have used up all the TriMatrix memory resources When logic cells are used the MegaWizard provides you with the following two types of logic cell implementations m Default logic cell style the write operation triggers internally on the rising edge of the write clock and have continuous read This implementation uses less logic cells and is faster but it is not fully compatible with the Stratix M512 emulation style m Stratix M512 emulation logic cell style the write operation triggers interna
8. The ecc decoder v is a design variation file for the ALTECC DECODER megafunction that is pre configured with the settings shown in Table 13 Table 13 ALTECC_DECODER Megafunction Settings functions MegaWizard Page Available Options Configured Settings Currently selected device family Stratix Ill How do you want to configure this Configure this module as an ECC module decoder How wide should the data be 13 bits 3 Do you want to pipeline the Yes want an output latency of 1 clock cycle Create an aclr asynchronous clear port Not selected Create a clocken clock enable clock Not selected For more information about the options available from the ALTECC MegaWizard Plug In Manager refer to Integer Arithmetic Megafunctions User Guide Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Design Example External ECC Implementation with True Dual Port RAM Page 21 The true_dp_ram v is a design variation file for the true dual port RAM instantiated through the ALTSYNCRAM megafunction that is pre configured with the settings shown in Table 14 Table 14 RAM 2 PORT MegaWizard Plug In Settings MegaWizard Page Available Options Configured Settings Currently selected device family Stratix III How will you be using the dual port With two read write ports 3 ram How do you want to specify the As
9. Internal Memory RAM and ROM ANU S RYA User Guide November 2009 UG 01068 1 0 Introduction Altera provides various internal memory RAM and ROM features to address the memory requirements of today s system on a programmable chip SOPC designs You can use the following methods to create the memory with the features you desire m Quartus II MegaWizard Plug In Manager m Memory inferring from HDL code m Manualinstantiation of memory megafunctions Altera recommends you to use MegaWizard Plug In Manager to create internal memory compared to other methods SS For general information about the Quartus II MegaWizard Plug In Manager refer to the Megafunction Overview User Guide For more information about memory inferring from HDL code refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook The following sections describe the various memory features that you can configure through the MegaWizard interface Memory Modes on page 2 Memory Block Types on page 5 Write and Read Operations Triggering on page 6 Port Width Configuration Memory Depth x Data Width on page 8 Mixed width Port on page 9 Maximum Block Depth on page 9 Clocking Modes and Clock Enable on page 11 Address Clock Enable on page 12 Byte Enable on page 13 Asynchronous Clear on page 14 Read Enable on page 15 Read During Write on page 16
10. refer to the ModelSim Altera Software Support page on the Altera website On the support page there are links to such topics as installation usage and troubleshooting The following design example provides you with the necessary steps to run the functional simulation even if you are not familiar with the ModelSim Altera software Set up and simulate the design in the ModelSim Altera software by performing the following steps 1 Unzip the Internal_Memory_DesignExample zip file to any working directory on your PC Start the ModelSim Altera software On the File menu click Change Directory Select the folder in which you unzipped the files Click OK Dn FTF WON On the Tools menu point to TCL and click Execute Macro The Execute Do File dialog box appears 7 Select the true_dp do file and click Open The true_dp do file is a script file that automates all the necessary settings compiles and simulates the design files and displays the simulation waveform 8 Verify the result shown in the Waveform Viewer window You can rearrange signals remove signals add signals and change the radix by modifying the script in true_dp do accordingly Understanding the Simulation Results The top level contains the input and output ports shown in Table 15 Table 15 Top Level Input and Output Ports Representations Part 1 of 2 Ports Name Ports Type Descriptions clock Input System Clock for the encoders RAM and decoders
11. Corporation supported by Stratix and newer devices However Stratix III and newer devices support asynchronous read memory for simple dual port RAM mode if you choose MLAB memory block with unregistered rdaddress port In the single clock mode a single clock can be used together with a clock enable to control all registered ports or selected registered ports of the memory blocks In the read write clock mode a separate clock is available for each read and write port The read clock controls all the registered read ports data output read address and read enable ports and the write clock controls all the registered write ports data input write address write enable and byte enable ports In input output clock mode a separate clock is available for each input and output port The input clock controls all registered input ports data input addresses byte enables read enables and write enables ports to the memory and the output clock controls the output registered ports data output In the independent clock mode a separate clock is available for each port A and B Clock A controls all registered ports of port A while clock B controls all registered ports of port B You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes From the MegaWizard interface click More Options beside the clock enable option to set the available ind
12. PORT for true dual port RAM or dual port ROM m ROM for single port ROM For more information about various memory modes refer to Memory Modes on page 2 width a width b widthad a widthad b Integer Integer Optional Optional Optional parameters depending on the port usage to specify the width of the following data input port and data output port m width afordata aandq a ports m width bfordata bandq b ports Mixed width port is supported when the value for width aand width pb parameter is different The mixed width port is only supported when operation mode is set to the following values m DUAL PORT m BIDIR DUAL PORT excluding the following conditions m the implement in les parameter is set to ON m the ram block type parameter is set to MLAB For more information about mixed width port feature refer to Mixed width Port on page 9 Optional parameters depending on the port usage to specify the width of the following address input ports m widthad_aforaddress a port m widthad bforaddress b port The parameters are related to numwords a and numwords b parameters as follows m widthad a lo0go numwords a m widthad b logonumwords b Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Table 17 ALTSYNCRAM Megafunction Parameters Description Page 35 Parameter Name numwords a numwords b byte size Type I
13. The design examples in this user guide utilize the MegaWizard Plug In Manager in the Quartus II software and are available on the Literature and Technical Documentation page of the Altera website The files are located under the following sections m Onthe Quartus II Development Software Literature page expand the Using Megafunctions section and then expand the Memory Compiler section m Literature User Guides section November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 20 Design Example External ECC Implementation with True Dual Port RAM The following design files can be found in Internal_Memory_DesignExample zip m ecc_encoder v ecc_decoder v true_dp_ram v top_dpram v true_dp do Configuration Settings true_dp_ram vt true dp qar Quartus II design file The ecc encoder v is a design variation file for the ALTECC ENCODER megafunction that is pre configured with the settings shown in Table 12 Table 12 ALTECC ENCODER Megafunction Settings functions MegaWizard Page Available Options Configured Settings Currently selected device family Stratix Ill How do you want to configure this Configure this module as an ECC module encoder How wide should the data be 8 bits 3 Do you want to pipeline the Yes want an output latency of 1 clock cycle Create an aclr asynchronous clear port Not selected Create a clocken clock enable clock Not selected
14. aclr String Optional Optional parameters to specify which output registered ports are affected by asynchronous clear The values are CLEARO CLEAR1 and NONE The clearo affects the registers clocked by clocko while clear affects the registers clocked by clock1 The following list shows the respective parameters and controlled ports m outdata aclr a q a port m outdata aclr b q b port m eccstatus_aclr eccstatus port Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Table 17 ALTSYNCRAM Megafunction Parameters Description Page 39 Parameter Name indata reg b address reg b byteena reg b wrcontrol wraddress reg b Type String Required Optional Description Optional parameter to specify the clock used by port B The values are CLOCKO and CLOCK1 The following list shows the respective parameters and controlled ports m indata reg b data pb port m address reg b address b port address reg b Serves as the reference for the clock source of port B if other parameters are not specified or are different from address reg b m byteena reg b byteena b port m wrcontrol wraddress reg b wren b port outdata reg a outdata reg b eccstatus reg String Optional Optional parameters to specify the clock used for the output ports The values are CLOCKO CLOCK1 and UNREGISTERED The following list shows the respect
15. are not affected Registered input address port can be affected Dual port ROM Registered address input port can be affected All registered input ports are not affected All registered input ports are not affected Notes to Table 7 1 When LCs are implemented in this memory mode registered output port is not affected 2 For MRAM only the read address input ports can be affected L During a read operation clearing the input read address asynchronously corrupts the memory contents The same effect applies to a write operation if the write address is cleared You can select the ports that are affected by the asynchronous clear signal using the MegaWizard interface Click More Options located next to the asynchronous clear option and the asynchronous clear page appears The page shows you the ports that are disabled These disabled ports are not affected by the asynchronous clear signal On the same page you can turn on the available ports that can be affected by the asynchronous clear signal The TriMatrix memory blocks in the Stratix III Cyclone III HardCopy III Arria II GX and newer device families support the asynchronous clear feature used on the output latches and output registers The asynchronous clear feature allows you to clear the outputs even if the q output port is not registered This feature however is not supported in MLAB memory blocks Internal Memory RAM and ROM User Guide N
16. corrupt _dataa_bito Input Registered active high control signal that twist the Zero bit LSB of input encoded data at port A before writing into the RAM 7 address a Input Address input data input write enable and read enable to port A of the RAM 7 data_a wren a rden a Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Design Example External ECC Implementation with True Dual Port RAM Page 23 Table 15 Top Level Input and Output Ports Representations Part 2 of 2 Ports Name Ports Type Descriptions data B enable to port B of the RAM 1 wren b rden b rdatal Output Output data read from port A of the RAM and the err correctedi ECC status signals reflecting the data read 2 err detectedl err fatall rdata2 Output Output data read from port B of the RAM and the ECC status signals reflecting the data read 2 err corrected2 err detected2 err fatal2 Notes to Table 15 1 Forinput ports only data signal goes through the encoder others bypass the encoder and directly go to the RAM block Since the encoder uses one pipeline those signal that bypass the encoder require additional pipeline before going to the RAM This has been implemented in the top level 2 The encoder and decoder each use one pipeline while the RAM uses two pipelines making the total pipeline equal to four Therefore read data is only shown at output ports f
17. more details about the various memory features in the following sections In a single port RAM the read and write operations share the same address at port A and the data is read from output port A Figure 1 shows a block diagram of a typical single port RAM Figure 1 Single Port RAM gt data mop address wren byteenal _ gt addressstall gt gt inclock outclock c clockena 9 den gt ar Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Memory Modes Page 3 In simple dual port RAM mode a dedicated address port is available for each read and write operation one read port and one write port A write operation uses write address from port A while read operation uses read address and output from port B Figure 2 shows the block diagram of a simple dual port RAM Figure 2 Simple Dual Port RAM gt lata rdaddress 4 wraddress rden 4 wren all byteena rd addressstall 4g M wr addressstall rdclock lt Je ps wrclock rdclocken wrclocken ecc_status aclr In true dual port RAM mode two address ports are available for read or write operation two read write ports In this mode you can write to or read from the address of port A or port B and the data read is shown at the output port with respect to the read address port
18. ram block type parameter to MLAB if you want to create an asynchronous read RAM Ifthe use eab parameter is set to OFF set the parameter based on whether the rdaddress and rden ports are clocked by inclock port or out clock port A required parameter to specify the clock used by the q port Values are UNREGISTERED OUTCLOCK and INCLOCK Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Page 47 Table 19 ALTDPRAM Megafunction Parameters Description Parameter Name Type Required Description maximum depth Integer Optional An optional parameter to specify the slicing depth of the RAM slices The valid values are 32 and 64 when ram block type parameter is set to MLAB The default value is 0 This parameter is not applicable in the following conditions m For Stratix Ill MLAB m lfuse eap parameter is set to OFF For more information about the usage of slicing the memory block refer to Maximum Block Depth on page 9 lpm file String Optional An optional parameter to specify the name of the Memory Initialization File mif or Hexadecimal Intel Format Output File hex containing RAM initialization data lt file name gt The default value is UNUSED If omitted the default value for all contents is 0 The wren port must be registered to support memory initialization intended device family String Optional An optional parameter to specify the target dev
19. the registered ports can be controlled through their corresponding asynchronous clear parameter such as indata aclr wraddress aclr and so on For more information about the asynchronous clear parameters refer to Table 19 Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Page 45 Table 19 shows the parameters for the ALTDPRAM megafunction Table 19 ALTDPRAM Megafunction Parameters Description Parameter Name Type Required Description width Integer Yes A required parameter to specify the widths of data port and q port widthad Integer Yes A required parameter to specify the widths of rdaddress port and wraddress port numwords Integer Yes A required parameter to specify the memory depth The value must be within the range gwidthadl lt numwords lt 2vidthad and must be more than 1 For more information about the effect on having the memory depth in non power of two refer to Port Width Configuration Memory Depth x Data Width on page 8 byte size Integer Optional An optional parameter depending on the byte enable usage to specify the byte size for the byte enable mode The values are 5 8 9 and 10 This parameter is not applicable when use eap parameter is set to OFF For more information refer to Byte Enable on page 13 width byteena Integer Optional An optional parameter depending on the byte enable usage to specify the width of the by
20. the type of resource implemented If the memory is implemented in TriMatrix memory blocks setting a non power of two for the memory depth reflects the actual memory depth If the memory is implemented in logic cells and not using Stratix M512 emulation logic cell style that can be set through the MegaWizard interfaces setting a non power of two for the memory depth does not reflect the actual memory depth In this case you write to or read from up to 2 44 ess_vidth memory locations even though the memory depth you set is less than 2 39re55 vist For example if you set the memory depth to 3 and the RAM is implemented using logic cells your actual memory depth is 4 When you implement your memory using TriMatrix memory blocks you can check the actual memory depth by referring to the fitter report November 2009 Altera Corporation Mixed width Port Page 9 Mixed width Port Only dual port RAM and dual port ROM support mixed width port configuration for all memory block types except when they are implemented with LEs The support for mixed width port depends on the width ratio between port A and port B In addition the supporting ratio varies for various memory modes memory blocks and target devices MLABs do not have native support for mixed width operation thus the option to select MLABs is disabled in the MegaWizard interface However the Quartus II software can implement mixed width memories in MLABs by using more than o
21. 27 30 and so on If the width of the data input port is 10 you can only define the size of a byte as 5 In this case you get a 2 bit byte enable port each bit controls 5 bits of data input written If the width of the data input port is 20 then you can define the size of a byte as either 5 or 10 If you define 5 bits of input data as a byte you get a 4 bit byte enable port each bit controls 5 bits of data input written If you define 10 bits of input data as a byte you get a 2 bit byte enable port each bit controls 10 bits of data input written Figure 10 shows the results of the byte enable on the data that is written into the memory and the data that is read from the memory Figure 10 Byte Enable Functional Waveform inclock wren address an ad X al a2 a0 X al X a2 X data XXXX X ABCD X XXXX byteena XX X 10 X 01 X 11 X Xx contents at a0 FFFF X ABFF contents at a1 FFFF X FFCD contents at a2 FFFF X ABCD don t care q asynch X doutn ABXX X XXCD 4 ABCD X ABFF FFCD X ABCD current data q asynch X doutn ABFF X FFCD X ABCD X ABFF FFCD X ABCD When a byte enable bit is deasserted during a write cycle the corresponding masked byte of the q output can appear as a Don t Care value or the current data at that location This selection is only available if you set the read during write output behavior to New Data For more information about the maske
22. DW and the clocking mode must be either single clock mode or input output clock mode Simple dual port RAM only supports mixed port RDW and the clocking mode must be either single clock mode or input output clock mode The clocking mode must be either single clock mode input output clock mode or independent clock mode 4 The clocking mode must be either single clock mode or input output clock mode There is no option page available from the MegaWizard interface in this mode By default the new data flows through to the output There are two types of new data behavior for same port RDW that you can choose from the MegaWizard interface When byte enable is applied you can choose to read old data or X on the masked byte The respective parameter values are m NEW DATA WITH NBE READ for old data on masked byte m NEW DATA NO NBE READ for x on masked byte Ls IF Internal Memory RAM and ROM User Guide The RDW old data mode is not supported when the Error Correction Code ECC is engaged or when you configure your memory as tri port RAM If you are not concerned about the output when RDW occurs you can select Don t Care Selecting Don t Care increases the flexibility in the type of memory block being used provided you do not assign block type when instantiating the memory block You also get a potential performance gain by selecting Don t Care November 2009 Altera Corporation Power Up Conditions and Memory Initializa
23. Description Port Name data Type Required Description Input Yes Data input to the memory The data port is required and the width must be equal to the width of the q port wraddress Input Yes Write address input to the memory The wraddress port is required and must be equal to the width of the raddress port wren Input Yes Write enable input for wraddress port The wren port is required raddress rden Input Yes Read address input to the memory The rdaddress port is required and must be equal to the width of wraddress port Input Optional Read enable input for rdaddress port The raden port is supported when the use eab parameter is set to OFF The rden port is not supported when the ram block type parameter is set to MLAB Instantiate the ALTSYNCRAM megafunction if you want to use read enable feature with other memory blocks byteena Input Optional Byte enable input to mask the data port so that only specific bytes nibbles or bits of data are written The byteena port is not supported when use eab parameter is set to OFF It is supported in Arria II GX Stratix IIl Cyclone IIl and newer devices with the zam block type parameter set to MLAB For more information about byte enable feature and the criterion that you must follow to use the feature correctly refer to Byte Enable on page 13 Internal Memory RAM and ROM User Guide November 2009 Altera Corporati
24. alization via the Memory Initialization File mif or Hexadecimal Intel format file hex You can include the files using the MegaWizard interface when you configure and build your RAM For RAM beside using the mif file or the hex file you can initialize the memory to zero or X To initialize the memory to zero select No leave it blank To initialize the content to X turn on Initialize memory content data to XX X on power up in simulation Turning on this option does not change the power up behavior of the RAM but initializes the content to X For example if your target memory block is M4K the output is cleared during power up based on Table 10 on page 17 The content that is initialized to X is shown only when you perform the read operation November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 18 Error Correction Code ECC Error Correction Code ECC The ECC features single error correction double error detection SECDED implementation in which it can detect and fix a single bit error or detect two bit errors without fixing The Stratix III and Stratix IV M144K memory blocks have built in support for the ECC up to a data width of x64 for the simple dual port mode However this feature is not supported if the m mixed width port feature is used m byte enable feature is engaged The Mixed port RDW for old data mode is not supported when the ECC feature is engaged The re
25. ameter might increase the number of LEs and affects the design performance Table 4 shows the estimated dynamic power usage for different slice type that is applied to an 8K x 36 M9K RAM block design in a Stratix III EP3SE50 device Table 4 Power Usage Setting for 8K x 36 M9K Design of a Stratix IIl Device M9K Slice Type Dynamic Power mW ALUT Usage M9Ks 8K x 1 default setting 51 49 0 36 4K x 2 20 28 39 38 36 2K x 4 10 80 21 44 36 1Kx9 6 08 12 125 32 512 x 18 4 51 9 212 32 256 x 36 6 36 12 467 32 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 10 Maximum Block Depth When the RAM is sliced shallower the dynamic power usage decreases However for a RAM block with a depth of 256 the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices You can also use this option to reduce the total number of memory blocks used but at the expense of LEs From Table 4 the 8K x 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K x 1 By setting the maximum block depth to 1K the 8K x 36 RAM can fit into 32 M9K blocks The maximum block depth must be in a power of two and the valid values vary among different TriMatrix memory blocks Table 5 shows the valid range of maximum block depth for different TriMatrix memory blocks Table 5 Valid Range of Maximum Block Depth for Different TriMatrix Memory Blocks
26. anumber of words memory size How many 8 bit words of memory 16 Use different data widths on different Not selected ports 4 How wide should the q a output bus 13 be What should the memory block type M9K be Set the maximum block depth to Auto Which clocking method do you want to Single clock use 5 Create rden a and rden b read Not selected enable signals Byte Enable Ports Not selected Which ports should be registered All write input ports and read output ports 6 Create one clock enable signal for each Not selected signal Create an aclr asynchronous clear for Not selected the registered ports 7 Mixed Port Read During Write for Old memory contents appear Single Input Clock RAM 8 Port A Read During Write Option New Data Port B Read During Write Option Old Data The top_dpram v is a design variation file that contains the top level that instantiates two encoders a true dual port RAM and two decoders To simulate the design a testbench true_dp_ram vt is created for you to run in the ModelSim Altera software November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 22 Design Example External ECC Implementation with True Dual Port RAM Functional Simulation in the ModelSim Altera Software Simulate the design in the ModelSim Altera software to generate a waveform that displays the functional behavior of the design example If you are unfamiliar with the ModelSim Altera software
27. ard interface Turn on the option to create the addressstall port to enable the feature gt The address clock enable feature is only supported by Stratix II and newer devices and for all memory modes excluding tri port RAM Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Byte Enable Page 13 Byte Enable All TriMatrix memory blocks that are implemented as RAMs support byte enables that mask the input data so that only specific bytes nibbles or bits of data are written The unwritten bytes or bits retain the previously written value Byte enable port operates in a one hot fashion with the least significant bit LSB of the byte enable port corresponding to the least significant byte of the data bus For example if you use a RAM block in x18 mode and the byte enable port is 01 data 8 0 isenabled and data 17 9 is disabled Similarly if the byte enable port is 11 both data bytes are enabled You can specifically define and set the size of a byte for the byte enable port The valid values are 5 8 9 and 10 depending on the type of TriMatrix memory blocks The values of 5 and 10 are only supported by MLAB To create a byte enable port the width of the data input port must be a multiple of the size of a byte for the byte enable port For example if you use an MLAB memory block the byte enable is only supported if your data bits are multiples of 5 8 9 or 10 that is 10 15 16 18 20 24 25
28. ation also affects the memory performance If embedded memory block is sufficient you must ignore the implement in les parameter and set the ram block type parameter to AUTO For more information about the embedded memory block and their advantages over logic cells implementation refer to Memory Block Types on page 5 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 42 e Ports and Parameters Altera recommends you to use ALTDPRAM megafunction when you want to create simple dual port RAM true dual port RAM does not support the following conditions in any of the following conditions m when you implement memory using MLAB with un registered rdaddress port only MLAB supports asynchronous read operation m when you implement memory using logic element with no M512 emulation 9 Logic element with M512 emulation behave like M512 memory block in which write operation triggers at falling clock edge Use the ALITSYNCRAM megafunction if your memory specification does not meet any of the conditions mentioned in the previous list The ports and parameters description for the ALTDPRAM megafunction in the following sections only include information that is applicable to any of the mentioned conditions that are also recommended for the ALTDPRAM megafunction Table 18 shows the input and output ports for the ALTDPRAM megafunction Table 18 ALTDPRAM Megafunction Input and Output Ports
29. by clock1 clock The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter such as outdata aclr a address aclr a and so on For more information about the asynchronous clear parameters refer to Table 17 eccstatus November 2009 Altera Corporation Output Optional A 3 hit wide error correction status port Indicate whether the data that is read from the memory has an error in single bit with correction fatal error with no correction or no error bit occurs The eccstatus port is supported if all the following conditions are met m operation mode parameter is set to DUAL PORT m ram block type parameter is set to M144K m width aand width b parameter have the same value m Byte enable is not used For more information about the ECC features restrictions and the output status definitions refer to Error Correction Code ECC on page 18 Internal Memory RAM and ROM User Guide Page 34 Ports and Parameters Table 17 shows the parameters for the ALTSYNCRAM megafunction Table 17 ALTSYNCRAM Megafunction Parameters Description Parameter Name operation mode Type String Required Yes Description A required parameter to specify the operation of the memory depending on the following memory modes that you want to create m SINGLE PORT for single port RAM m DUAL PORT for simple dual port RAM m BIDIR DUAL
30. clr wren port m rdaddress aclr rdaddress port m rdcontrol aclr rden port The parameters are only applicable when use eab parameter is set to oFF and depends on the target devices m For Stratix Stratix GX and Cyclone devices all parameters are applicable m For Arria GX Stratix Il Stratix Il GX and Cyclone Il all parameters are not applicable m For Arria GX Stratix IIl Cyclone III and newer devices only rdaddress_aclr parameter is applicable Set the parameter to OFF if it is not applicable outdata aclr String Optional An optional parameter to specify whether the aclr port affects the registered q port Values are ON and OFF indata reg String Yes wraddress reg wrcontrol reg A required parameter to specify the clock used by the write ports Values are UNREGISTERED and INCLOCK The following list shows the respective parameters and controlled ports indata_reg data port wraddress reg wraddress port wrcontrol reg wren port For Stratix Stratix GX Cyclone and newer devices the legal value is only INCLOCK rdaddress reg String Optional rdcontrol reg outdata reg String Yes An optional parameter to specify the clock used by the read ports Values are UNREGISTERED OUTCLOCR and INCLOCK The following list shows the respective parameters and controlled ports rdaddress_reg rdaddress port rdcontrol_reg rden port Set the parameters to UNREGISTERED and set the
31. d byte and the q output refer to Read During Write on page 16 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 14 Asynchronous Clear Table 7 shows the asynchronous clear effects on the input ports for different devices in different memory settings Asynchronous Clear Table 7 Asynchronous Clear Effects on the Input Ports for Different Devices in Different Memory Settings Memory Mode Single port RAM Single dual port Stratix Stratix GX and Cyclone All registered input ports can be affected except for the following ports and conditions m wren port for M512 m data wren address ports for MRAM byteena port can be affected m LCs are implemented 7 All input registered ports Stratix II Stratix Il GX HardCopy Il Cyclone Il and Arria GX All registered input ports are not affected 7 All registered input ports are Stratix Ill HardCopy Ill Cyclone Ill Arria Il GX and newer devices All registered input ports are not affected 7 Only registered input read can be affected 2 All registered input ports are not affected RAM and True can be affected except for not affected address port can be affected dual port RAM MRAM Tri port RAM All registered input ports Only registered input read address port can be affected excluding M144K Single port ROM Registered address input port can be affected All registered input ports
32. different types of TriMatrix memory blocks Table 2 shows the write and read operations triggering for different TriMatrix memory blocks Table 2 Write and Read Operations Triggering for TriMatrix Memory Blocks TriMatrix Memory Blocks M144K M9K Write Operation 7 Rising clock edges Rising clock edges Read Operation Rising clock edges Rising clock edges MLAB Falling clock edges Rising clock edges 2 M RAM Rising clock edges Rising clock edges M4K Falling clock edges Rising clock edges M512 Falling clock edges Rising clock edges Notes to Table 1 1 Write operation triggering is not applicable to ROMs 2 MLAB supports continuos reads For example when you write a data at the write clock rising edge and after the write operation is complete you see the written data at the output port without the need for a read clock rising edge November 2009 Altera Corporation Write and Read Operations Triggering Page 7 It is important that you understand the write operation triggering to avoid potential write contentions that can result in unknown data storage at that location Figure 6 and Figure 7 show the valid write operation that triggers at the rising and falling clock edge respectively clock_a address a wren a data a clock b address b wren b data b Figure 6 Valid Write Operation that Triggers at Rising Clock Edges Figure 7 Va
33. dth a byte size width_byteena_b Integer Optional Optional parameter depending on byte enable usage on data_b port to specify the width of the byteena_b port The width byteena b parameter value must be equal to width b byte size November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 36 Table 17 ALTSYNCRAM Megafunction Parameters Description Ports and Parameters Parameter Name ram_block_type Type String Required Optional Description Optional parameter to specify the TriMatrix Memory Block type to use depending on your target device The following list are the available values M512 BH M144K m AUTO By choosing AUTO the compiler has the flexibility to decide on the suitable memory block that results in optimum resource usage and best performance For more information on the availability of the memory block in different memory modes and the benefit of choosing AUTO refer to Memory Block Types on page 5 read during write mode mixed ports Internal Memory RAM and ROM User Guide String Optional Optional parameter to specify the behavior when the read and write operations occur at different ports on the same RAM address The values are m OLD DATA m NEW DATA only supported by MLAB m DONT CARE The parameter and values are applicable depending on the memory mode and target memory block that you
34. ependent clock enable that you prefer Internal Memory RAM and ROM User Guide Page 12 Address Clock Enable Address Clock Enable The address clock enable addressstall port is an active high asynchronous control signal used to hold the previous address value for as long as the signal is enabled For dual port RAMs and dual port ROMs you can create independent address clock enable for each address port Figure 8 and Figure 9 show the results of address clock enable signal during the read and write operations respectively Figure 8 Address Clock Enable During Read Operation inclock N X rdaddress X a0 X al x a2 X a3 X a4 X a5 X rden addressstall N latched address inside memory an X a0 x at xX au x Ho X q synch doutn 1 X doutn X doutO X dout1 X dout4 X q asynch doutn doutO dout1 dout4 dout5 Figure 9 Address Clock Enable During Write Operation inclock N wraddress X a0 Y al X a2 X a3 X a4 X ab X a6 data 00 01 02 03 04 05 06 wren addressstall N latched address zm X a0 X al X a4 X a5 X inside memory contents at a0 XX X 00 contents at a1 XX X 01 X 02 xX 03 contents at a2 XX contents at a3 XX contents at a4 XX X 04 contents at a5 XX X 05 La To configure the address clock enable feature click More Options located beside the clock enable option on the RAM MegaWiz
35. f A port m clock enable output b output egisters of B port m clock enable eccstatus output registers of eccstatus port Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Table 17 ALTSYNCRAM Megafunction Parameters Description Page 41 Parameter Name enable ecc Type String Required Optional Description Optional parameter to specify whether the ECC feature is on or off The values are m TRUE m FALSE For more information about the ECC features restrictions and the output status definitions refer to Error Correction Code ECC on page 18 power up uninitialized String Optional Optional parameter to specify whether to initialize memory content data to X on power up simulation The value are m TRUE m FALSE For M RAM only the TRUE value is valid The init file parameter has higher priority than the power up uninitialized parameter implement in les String Optional Optional parameter to specify the usage of RAM blocks The implement in les parameter is only applicable if the operation mode is set to any of the following values m SINGLE PORT m DUAL PORT The valid values forthe implement in les parameter are m ON m OFF Set the value to OFF will implement your RAM using logic cells that has write triggering at the falling clock edge as M512 memory block The logic cells implement
36. ice family This parameter is used for modeling and behavioral simulation purposes use eab String Optional An optional parameter to specify whether to implement memory using TriMatrix Memory Block or logic cells Legal values are ON and OFF Setting the use eab parameter to OFF will result in memory implemented in logic cells and this affects the performance Logic cells that are implemented have the write triggering at rising clock edge If you intend to implement logic cells that have write triggering at falling clock edge as M512 memory block use the ALTSYNCRAM megafunction The use eap parameter has higher priority than the ram block type parameter November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Revision History Revision History Table 20 Table 20 table shows the revision history for this user guide November 2009 Date Version Changes Made Initial release ND S RYA 101 Innovation Drive San Jose CA 95134 www altera com Technical Support www altera com support Copyright 2009 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All othe
37. ive parameters and controlled ports m outdata reg a q a port m outdata reg b q b port m eccstatus_reg eccstatus port init file November 2009 Altera Corporation String Optional Optional parameter to specify the name of the Memory Initialization File mif or Hexadecimal Intel Format Output File hex containing memory initialization data lt file name gt The default is UNUSED If omitted the default value for all contents is 0 If you want to initialize the content to x on power up simulation refer to power up uninitialized parameter The following list the restrictions for this parameter m Theinit file parameter is no applicable when the ram block type parameter is set t0 M RAM m The init file parameter is no applicable for HardCopy series of devices m Whenthe operation mode parameter is set to DUAL PORT the Compiler uses only the width b parameters to read the initialization file m Theinit file parameter is required if you want to create single port or dual port ROM Internal Memory RAM and ROM User Guide Page 40 Table 17 ALTSYNCRAM Megafunction Parameters Description Ports and Parameters Parameter Name init_file layout Type String Required Optional Description Optional parameter to specify the layout port that is used with the initialization file The values are m PORT A m PORT B m UNUSED The initialized memory content will have the
38. lid Write Operation that Triggers at Falling Clock Edge 01 address_a i 01 i i wren_a i H ds F4 i 06 qatana 2 A 96 X i 1 ML ous e a twc Valid Write i twe Valid Write Actual Write Y clock b T address b 01 wren b See Seco Figure 6 assumes that t is the maximum write cycle time interval Write operation of data 03 through port B does not meet the criteria and causes write contention with the write operation at port A which result in unknown data at address 01 The write operation at the next rising edge is valid because it meets the criteria and data 04 replaces the unknown data Figure 7 assumes that tw is the maximum write cycle time interval Write operation of data 04 through port B does not meet the criteria and therefore causes write contention with the write operation at port A that result in unknown data at address 01 The next data 05 is latched at the next rising clock edge that meets the criteria and is written into the memory block at the falling clock edge Data and addresses are latched at the rising edge of the write clock regardless of the different write operation triggering November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 8 Port Width Configuration Memory Depth x Data Width
39. lly on the falling edge of the write clock and performs read only on the rising edge of the read clock November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 6 Write and Read Operations Triggering To obtain proper implementation based on the memory configuration you set allow the Quartus II software to automatically choose the memory type This gives the compiler the flexibility to place the memory function in any available memory resources based on the functionality and size To identify the type of memory block that the software selects to create your memory refer to the fitter report after compilation When you set the memory block type to Auto the compiler favors larger block types that can support the memory capacity you require in a single TriMatrix memory block This setting gives the best performance and requires no logic elements LEs for glue logic When you create the memory with specific TriMatrix memory blocks such as M9K the compiler is still able to emulate wider and deeper memories than the block type supported natively The compiler spans multiple TriMatrix memory blocks only of the same type with glue logic added in the LEs as needed Write and Read Operations Triggering Internal Memory RAM and ROM User Guide The TriMatrix memory blocks vary slightly in its supported features and behaviors One important variation is the difference in the write and read operations triggering for
40. mory Block Types The embedded memory blocks in Altera devices feature the TriMatrix memory structure that provides three different sizes of embedded SRAM Different device families support different sizes of the TriMatrix embedded memory blocks Table 1 shows the type of TriMatrix memory blocks in various device families Table 1 TriMatrix Embedded Memory Blocks in Altera Devices Stratix Stratix GX Stratix Il Stratix II GX Cyclone Cyclone II 7 HardCopy II 2 and Arria GX Device Family Types of TriMatrix Memory Blocks M512 blocks 512 bits 5 M4K blocks 4 Kbits M RAM blocks 512 Kbits 6 MLAB blocks 640 bits 7 8 Stratix Ill HardCopy III Cyclone III 3 Arria II GX 4 and newer devices M9K blocks 9 Kbits M144K blocks 144 Kbits Notes to Table 1 Cyclone and Cyclone II devices do not have M512 blocks and M RAM blocks HardCopy Il devices do not have M512 blocks Cyclone III devices do not have MLAB blocks and M144K blocks Arria Il GX devices do not have M144K blocks M512 blocks are not supported in true dual port RAM mode and dual port ROM mode M RAM blocks are not supported in ROM mode For Stratix IIl devices MLAB blocks are 320 bit in RAM mode and 640 bit in ROM mode MLAB blocks are not supported in simple dual port RAM mode with mixed width port feature true dual port RAM mode and dual port ROM 1 2 3 4 5 6 7 8 mode
41. nd the ECC status signal remains unknown La The decoders only correct the single bit error of the data shown at rdata1 and rdata2 ports The actual data stored at address 0 in the RAM remains corrupted until new data is written At 37500 ps the same condition happens to port A and port B The difference is port B reads the corrupted old data e from address 0 After four clock cycles at 52500 ps the rdata2 port shows the old data f that has been corrected by the decoder and the ECC status signals err corrected2 and err_detected2 are asserted to show the data has been corrected November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 28 Ports and Parameters Ports and Parameters The ports and parameters details are important if you bypass the MegaWizard Plug In Manager interface and use the megafunction as a directly parameterized instantiation in your design The details of the parameters are hidden from the MegaWizard Plug In Manager interface The following list are two commonly used megafunctions if you decide to instantiate the megafunctions m ALTSYNCRAM megafunction Refer to Table 16 on page 28 for the input and output ports and Table 17 on page 34 for the parameters information m ALTDPRAM megafunction Refer to Table 18 on page 42 for the input and output ports and Table 19 on page 45 for the parameters information Altera recommends you to use ALISYNCRAM megafunction to build synchr
42. ne MLAB Therefore if you select AUTO for your memory block type it is still possible to implement mixed width port memory using multiple MLABs For more information about width ratio that supports mixed width port refer to your relevant device handbook Memory depth of 1 word is not supported in simple dual port and true dual port RAMs with mixed width port The RAM MegaWizard interface prompts an error message when the memory depth is less than 2 words For example if the width for port A is 4 bits and the width for port B is 8 bits the smallest depth supported by the RAM is 4 words This configuration results in memory size of 16 bits 4x4 and can be represented by memory depth of 2 words for port B If you set the memory depth to 2 words that results in memory size of 8 bits 2x4 it can only be represented by memory depth of 1 word for port B and therefore the width of the port is not supported Maximum Block Depth You can limit the maximum block depth of the TriMatrix memory block you use The memory block can be sliced to your desired maximum block depth For example the capacity of an M9K block is 9 216 bits and the default memory depth is 8K in which each address is capable of storing 1 bit 8K x 1 If you set the maximum block depth to 512 the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits 512 x 18 You can use this option to save power usage in your devices However this par
43. nteger Integer Required Optional Optional Description Optional parameters depending on the port usage to specify the memory depth according to the following address ports m numwords aas memory depth for port A This parameter also represents the actual memory depth m numwords bas memory depth for port B For same width port the parameters must have the same value For mixed width port numwords_b parameter has a different value from the numwords a parameter and is derived as follows m lfwidth b width a then numwords b numwords a width b width a m lfwidth a width b then numwords b numwords aX width a width Lb The parameter that represents the memory depth can be in non power of two but the actual memory depth might be different For more information about the effects on having the memory depth in non power of two refer to Port Width Configuration Memory Depth x Data Width on page 8 Optional parameter depending on the byte enable usage to specify the byte size for the byte enable mode The supported values are 5 8 9 and 10 Values 5 and 10 are only supported if ram block type is set to MLAB For more information about the byte size refer to Byte Enable on page 13 width_byteena_a Integer Optional Optional parameter depending on the byte enable usage on data_a port to specify the width of the byteena_a port The width byteena a parameter value must be equal to wi
44. ock port All registered ports related to write operation such as data port wraddress port wren port and byteena port are synchronized by the write clock Input Output Connect your input clock to inclock port All registered input ports are synchronized by the input clock November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 44 Ports and Parameters Table 18 ALTDPRAM Megafunction Input and Output Ports Description Port Name Type Required Description outclock Input Yes The following table describes which of your memory clock must be connected to the out clock port and port synchronization in different clocking modes Clocking Mode Descriptions Single clock Connect your single source clock to inclock port and outclock port All registered ports are synchronized by the same source clock Read Write Connect your read clock to outclock port All registered ports related to read operation such as rdaddress port rdren port and q port are synchronized by the read clock Input Output Connect your output clock to outclock port The registered q port is synchronized by the output clock inclocken Input Optional Clock enable input for inclock port outclocken Input Optional Clock enable input for out clock port aclr Input Optional Asynchronously clear the registered input and output ports The asynchronous clear effect on
45. om port B of the memory The q_b port is required if the operation mode is set to the following values m DUAL PORT m BIDIR DUAL PORT The width of q_b port must be equal to the width of Gata b port Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Table 16 ALTSYNCRAM Megafunction Input and Output Ports Description Page 31 Port Name clocko Type Input Required Yes Description The following table describes which of your memory clock must be connected to the clocko port and port synchronization in different clocking modes Clocking Mode Single clock Descriptions Connect your single source clock to clocko port All registered ports are synchronized by the same source clock Read Write Input Output Connect your write clock to clocko port All registered ports related to write operation such as data_a port address_a port wren_a port and byteena a port are synchronized by the write clock Connect your input clock to clocko port All registered input ports are synchronized by the input clock Independent clock Connect your port A clock to clocko port All registered input and output ports of port A are synchronized by the port A clock November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 32 Table 16 ALTSYNCRAM Megafunction Input and Output Ports Desc
46. on Ports and Parameters Page 43 Table 18 ALTDPRAM Megafunction Input and Output Ports Description Port Name Type Required Description wraddressstall Input Optional Write address clock enable input to hold the previous write address of wraddress port for as long as the wraddressstall portis high The wraddressstall port is only supported in Stratix Il Cyclone II Arria GX and newer devices For more information about address clock enable feature refer to Address Clock Enable on page 12 rdaddressstall Input Optional Read address clock enable input to hold the previous read address of rdaddress port for as long as the wraddressstall portis high The xdaddressstall port is only supported in Stratix II Cyclone II Arria GX and newer devices except when the rdaddress reg parameter is set t0 UNREGISTERED For more information about address clock enable feature refer to Address Clock Enable on page 12 q Output Yes Data output from the memory The q port is required and must be equal to the width data port inclock Input Yes The following table describes which of your memory clock must be connected to the inclock port and port synchronization in different clocking modes Clocking Mode Descriptions Single clock Connect your single source clock to inclock port and outclock port All registered ports are synchronized by the same source clock Read Write Connect your write clock to incl
47. onous memory function for single port RAM dual port RAM single port ROM and dual port ROM Use ALTDPRAM megafunction if you want to create a asynchronous read dual port RAM support Table 16 shows the input and output ports for the ALTSYNCRAM megafunction Table 16 ALTSYNCRAM Megafunction Input and Output Ports Description Port Name data_a Type Required Description Input Optional Data input to port A of the memory The data a port is required if the operation_mode is set to any of the following values m SINGLE PORT m DUAL PORT m BIDIR DUAL PORT address a Input Yes Address input to port A of the memory The address a port is required for all operation modes wren a Input Optional Write enable input for address a port The wren a portis required if the operation mode is set to any of the following values m SINGLE PORT m DUAL PORT m BIDIR DUAL PORT rden a Input Optional Read enable input for address a port The rden a port is supported depending on your selected memory mode and memory block For more information about the read enable feature refer to Read Enable on page 15 Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Page 29 Table 16 ALTSYNCRAM Megafunction Input and Output Ports Description Port Name byteena_a Type Input Required Optional Description Byte enable input to mask the da
48. our clock cycles after the read enable is initiated Figure 11 shows the expected simulation waveform results in the ModelSim Altera software Figure 11 Simulation Results l i e S S he ERIM I tdata2 November 2009 Altera Corporation Now 100 ps 7 aa 00 CC 00 Oil ff fo ff Jr SR UIE ME Internal Memory RAM and ROM User Guide Page 24 Design Example External ECC Implementation with True Dual Port RAM Figure 12 shows the magnified portion of when the same port read during write occurs for each port A and port B of the RAM Figure 12 Same Port Read During Write clock 0 d d d l l Now 65000 ps 5000 ps 10000 ps 5000 ps At 2500 ps same port read during write occurs for each port A and port B Since the true dual port RAM configured to port A is reading the new data and port B is reading the old data when the same port read during write occurs the rdata1 port shows the new data aa and the rdata2 port shows the old data 00 after four clock cycles at 17500 ps When the data is read again from the same address at the next rising clock edge at 7500 ps the rdata2 port shows the recent data bb at 22500 ps Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Design Example External ECC Implementation with True Dual Port RAM Page 25 Figure 13 shows the magnified portion of when the mixed po
49. ovember 2009 Altera Corporation Page 15 Support for the read enable feature depends on the target device memory block type and the memory mode you select Table 8 shows the memory configurations for the different device families that support the read enable feature Table 8 Read Enable Support in Different Device Families Stratix Ill HardCopy Ill Cyclone Ill Arria Il GX and newer Devices Other Stratix and Cyclone Devices Memory Modes M9K M144K MLAB M512 M4K M RAM Single port v X X X RAM Simple v X v X dual port RAM True v X X X dual port RAM Tri port RAM v X v X Single port v X X X ROM Dual port X X X X ROM If you create the read enable port and perform a write operation with the read enable port deasserted the data output port retains the previous values that are held during the most recent active read enable If you activate the read enable during a write operation or if you do not create a read enable signal the output port shows the new data being written the old data at that address or a Don t Care value when read during write occurs at the same address location You can set the output behavior from the MegaWizard interface For more information about the read during write output behavior refer to the Read During Write on page 16 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 16 Read During Write Read During Write
50. port The wren_b port is required if operation mode is set to BIDIR DUAL PORT rden b November 2009 Altera Corporation Input Optional Read enable input for address p port The rden_b port is supported depending on your selected memory mode and memory block For more information about the read enable feature refer to Read Enable on page 15 Internal Memory RAM and ROM User Guide Page 30 Ports and Parameters Table 16 ALTSYNCRAM Megafunction Input and Output Ports Description Port Name byteena_b Type Input Required Optional Description Byte enable input to mask the data_b port so that only specific bytes nibbles or bits of the data are written The byteena_b port is not supported in the following conditions m lfimplement in les parameter is set to ON m lfoperation mode parameter is set to SINGLE PORT DUAL PORT Or ROM For more information about byte enable feature and the criterion that you must follow to use the feature correctly refer to Byte Enable on page 13 addresstall b Input Optional Address clock enable input to hold the previous address of address bportforaslongasthe addressstall b portis high The addressstall b portis only supported in Stratix Il Cyclone Il Arria GX and newer devices For more information about address clock enable feature refer to Address Clock Enable on page 12 Output Yes Data output fr
51. r product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are NSAI advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services LS EN ISO 9001
52. ription Ports and Parameters Port Name Type Required Description clocki Input Optional The following table describes which of your memory clock must be connected to the clock1 port and port synchronization in different clocking modes Clocking Mode Descriptions Single clock Not applicable All registered ports are synchronized by clocko port Read Write Connect your read clock to clock1 port All registered ports related to read operation such as address b port rden b port and q_b port are synchronized by the read clock Input Output Connect your output clock to clock1 port All the registered output ports are synchronized by the output clock Independent Connect your port B clock to clock clock1 port All registered input and output ports of port B are synchronized by the port B clock clockeno Input Optional Clock enable input for c1ocko port clockenl Input Optional Clock enable input for c1ock1 port Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Ports and Parameters Page 33 Table 16 ALTSYNCRAM Megafunction Input and Output Ports Description Port Name aclro aclri Type Input Required Optional Description Asynchronously clear the registered input and output ports The aclro port affects the registered ports that are clocked by clocko clock while the aclr1 port affects the registered ports that are clocked
53. riting the data into the RAM while the ALTECC DECODER megafunction decodes the data output from the RAM before transferring the data out to other parts of the logic In this design example the raw data width is 8 bits and is encoded by the ALTECC ENCODER megafunction block to produce a 13 bit width data that is written into the true dual port RAM when write enable signal is asserted Because the RAM mode has two dedicated write ports another encoder is implemented for the other RAM input port Two ALTECC DECODER megafunction blocks are also implemented at each of the data output ports of the RAM When the read enable signal is asserted the encoded data is read from the RAM address and decoded by the ALTECC DECODER megafunction blocks respectively The decoder shows the status of the data as no error detected single bit error detected and corrected or fatal error more than 1 bit error This example also includes a corrupt zero bit control signal at port A of the RAM When the signal is asserted it changes the state of the zero bit LSB encoded data before it is written into the RAM This signal is used to corrupt the zero bit data storing through port A and examines the effect of the ECC features This design example describes how ECC features can be implemented with the RAM for cases in which the ECC is not supported internally by the RAM However the design examples might not represent the optimized design or implementation
54. rt read during write occurs Figure 13 Mixed Port Read During Write gt clock 0 SS Ee ES ey ee ee ee SS eS ey ees en ruc St tn tp ts tt tt i td E C qd po 3 ee 100 d Now 65000 ps 5000 ps 10000 ps 5000 ps At 12500 ps mixed port read during write occurs when data cc is both written to port A and is reading from port B simultaneously targeting the same address 1 Because the true dual port RAM that is configured to mixed port read during write is showing the old data the rdata2 port shows the old data bb after four clock cycles at 27500 ps When the data is read again from the same address at the next rising clock edge at 17500 ps the rdata2 port shows the recent data cc at 32500 ps November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 26 Design Example External ECC Implementation with True Dual Port RAM Figure 14 shows the magnified portion of when the write contention occurs Figure 14 Write Contention clock 1 d tt tt tt ee ee E write contention 22500 ps 5000 ps 10000 ps 5000 ps At 22500 ps the write contention occurs when data dd and ee are written to address 0 simultaneously Besides that the same port read during write also occurs for port A and port B The setting for port A and port B for same port read during write takes effect when the rdata1 port shows the ne
55. same width as the width of the port assigned If omitted the default value is UNUSED If the operation mode is set to DUAL PORT mode the default value is PORT B If the operation mode is set to other modes the default value is PORT A maximum depth Integer Optional Optional parameter to specify the slicing depth of the RAM slices The values must be in power of two and the range of the values depends on the target memory block For more information about the supported value range for different target memory block and the usage of slicing the memory block refer to Maximum Block Depth on page 9 intended device family String Optional Optional parameter to specify the target device family This parameter is used for modeling and behavioral simulation purposes lpm type String Optional Identifies the library of parameterized modules LPM entity name in VHDL Design Files clock enable input a clock enable input b clock enable output a clock enable output b clock enable eccstatus String Optional Optional parameters to specify the clock enable for the ports The values are m NORMAL clock enable is used m BYPASS clock enable is not used The following list shows the respective parameters and controlled ports m clock enable input a input registers of A port m clock enable input b input registers of B port m clock enable output _a output registers o
56. sult for RDW is don t care The M144K ECC status is communicated via a three bit status flag eccstatus 2 0 Table 11 shows the truth table for the ECC status flags Table 11 Truth Table for ECC Status Flags Status Eccstatus 2 0 No error 000 Single error and fixed 011 Double error and no fix 101 001 Illegal di 100 11X You can also use the ALTECC ENCODER and the ALTECC DECODER megafunctions to implement the ECC external to your memory blocks For more information refer to the Integer Arithmetic Megafunctions User Guide Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Design Example External ECC Implementation with True Dual Port RAM Page 19 Design Example External ECC Implementation with True Dual Port RAM Design Files The ECC features are only supported internally in simple dual port RAM by Stratix III and Stratix IV devices when the M144K is implemented Therefore this design example describes how ECC features can be implemented in other RAM modes regardless of the type of device memory block used It also demonstrates the features of the same port and the mixed port read during write behaviors This design example uses a true dual port RAM and illustrates how the ECC feature can be implemented external to the RAM The ALTECC ENCODER and ALTECC DECODER megafunctions are required as the ALTECC ENCODER megafunction encodes the data input before w
57. ta_a port so that only specific bytes nibbles or bits of the data are written The byteena_a port is not supported in the following conditions m lfimplement in les parameter is set to ON m lfoperation mode parameter is set to ROM For more information about byte enable feature and the criterion that you must follow to use the feature correctly refer to Byte Enable on page 13 addressstall a Input Optional Address clock enable input to hold the previous address of address a port for as long as the addressstall a portis high The addressstall a portis only supported in Stratix Il Cyclone Il Arria GX and newer devices For more information about address clock enable feature refer to Address Clock Enable on page 12 qa Output Yes Data output from port A of the memory The q_a port is required if the operation mode parameter is set to any of the following values m SINGLE PORT m BIDIR DUAL PORT mg ROM The width of q_a port must be equal to the width of Gata a port data b Input Optional Data input to port B of the memory The data p port is required if the operation mode parameter is set to BIDIR DUAL PORT address b Input Optional Address input to port B of the memory The address p port is required if the operation mode parameter is set to the following values m DUAL PORT m BIDIR DUAL PORT wren b Input Yes Write enable input for address b
58. teena port This parameter has the following conditions m Must be equal to width byte size m Notapplicable when use eab parameter is set to OFF ram block type String Optional An optional parameter to specify the TriMatrix Memory Block type to be used Set the following parameters if you want to create an asynchronous read RAM m ram block type MLAB m rdaddress reg UNREGISTERED m rdcontrol reg UNREGISTERED m outdata_reg UNREGISTERED Use the ALTSYNCRAM megafunction if you want to use other memory blocks or if you want to create a synchronous RAM read during write mode String Optional An optional parameter to specify the output behavior of the mixed ports read write mode when the read and write operations occur at different ports on the same RAM address This parameter is only applicable when the use eab parameter is set to OFF November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 46 Table 19 ALTDPRAM Megafunction Parameters Description Ports and Parameters Parameter Name Type Required indata_aclr String Optional wraddress aclr rdaddress aclr wrcontrol aclr rdcontrol aclr Description An optional parameter to specify which input registered ports are affected by aclr port Values are ON and OFF The following list shows the respective parameters and controlled ports m indata aclr data port m wraddress aclr wraddress port m wrcontrol a
59. tion Page 17 Power Up Conditions and Memory Initialization Power up conditions depend on the type of TriMatrix memory blocks in use and whether or not the output port is registered Table 10 shows the power up conditions in the different types of TriMatrix memory blocks Table 10 Power Up Conditions for Different TriMatrix Memory Blocks TriMatrix Memory Blocks Power Up Conditions M512 Outputs cleared M4K Outputs cleared M RAM Outputs cleared if registered otherwise unknown MLAB Outputs cleared if registered otherwise reads memory contents M9K Outputs cleared M144K Outputs cleared The outputs of M512 M4K M9K and M144K blocks always power up to zero whether the output registers are used or bypassed Even if a memory initialization file is used to pre load the contents of the memory block the output is still cleared MLAB and M RAM blocks power up to zero only if output registers are used If output registers are not used MLAB blocks power up to read the memory contents while M RAM blocks power up to an unknown state L gt When the memory block type is set to Auto in the MegaWizard interface the compiler is free to choose any memory block type in which the power up value depends on the chosen memory block type To identify the type of memory block the software selected to implement your memory refer to the fitter report after compilation All memory blocks excluding M RAM support memory initi
60. use For more information about when mixed port read during write behavior is supported and the applicable values refer to Read During Write on page 16 November 2009 Altera Corporation Ports and Parameters Table 17 ALTSYNCRAM Megafunction Parameters Description Page 37 Parameter Name read during write mode port a read during write mode port b Type String Required Optional Description Use the read during write mode port a parameter to specify the output behavior of port A when the read and write operations occur at the same port A and on the same RAM address The same way is applied to the output of port B using the read during write mode port b parameter The valid values differs for different memory modes and target memory block used In general the values are m OLD DATA m DONT CARE m NEW DATA NO NBE READ the output port shows x for write masked bytes instead of old data when byte enable is used m NEW DATA WITH NBE READ the output port shows old data for write masked bytes when byte enable is used For more information about same port read during write behavior and the values applicable for a particular memory mode and memory block refer to Read During Write on page 16 November 2009 Altera Corporation Internal Memory RAM and ROM User Guide Page 38 Table 17 ALTSYNCRAM Megafunction Parameters Description Ports and Parameters
61. w data dd and the rdata2 port shows the old data aa after four clock cycles at 37500 ps When the data is read again from the same address at the next rising clock edge at 27500 ps rdata1 and rdata2 ports show unknown values at 42500 ps Apart from that the unknown data input to the decoder also results in an unknown ECC status Internal Memory RAM and ROM User Guide November 2009 Altera Corporation Design Example External ECC Implementation with True Dual Port RAM Page 27 Figure 15 shows the magnified portion of the effect when an error is injected to twist the LSB of the encoded data at port A by asserting corrupt_dataa_bito Figure 15 Error Injection Asserting corrupt_dataa_bito i 1 i te te te tt SS SES VS V V cd i rdata2 ff 5000 ps 10000 ps 5000 ps7 rdatal new data corrected rdata2 old data corrected 52500 ps At 32500 ps same port read during write occurs at port A while mixed port read during write occurs at port B The corrupt dataa bito is also asserted to corrupt the LSB of encoded data at port A therefore the storing data has the LSB corrupted in which the intended data f is corrupted becomes e and stored at address 0 After four clock cycles at 47500 ps the rdata1 port shows the new data ff that has been corrected by the decoder and the ECC status signals err_corrected1 and err detectedl are asserted For rdata2 port old data which is unknown is shown a

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