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32” TFT TV SERVICE MANUAL - Page de test

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5. Al44 El I analog input 44 VDDA4A E2 P analog supply voltage for analog inputs Al4x 3 3 V AI31 E3 l analog input 31 Vssa3 E4 P ground for analog inputs Al3x HPD1 E11 1 0 MSB 6 of host port data I O extended Cg Cr input for expansion port extended Ce Cr output for image port HPD3 E12 VO MSB 4 of host port data I O extended Cg Cr input for expansion port extended Cs CR output for image port HPD2 E13 1 0 MSB 5 of host port data I O extended Cg CR input for expansion port extended Ce Cr output for image port HPD4 E14 I O MSB 3 of host port data I O extended Cg Cr input for expansion port extended Ce Cr output for image port AISD F1 1 0 differential input for ADC channel 3 pins Al31 to Al34 2 F2 I analog input 32 3 F3 l analog input 33 VDDA3 F4 P analog supply voltage for analog inputs Al3x 3 3 V Vsspe F11 P digital ground 6 core Vpppe F12 P digital supply voltage 6 core HPD5 F13 1 10 MSB 2 of host port data I O extended Cg CR input for expansion port extended Ce Cr output for image port HPD6 F14 I O MSB 1 of host port data I O extended Cg CR input for expansion port extended Ce Cr output for image port 4 G1 l analog input 34 VDDA3A G2 P analog supply voltage for analog inputs Al3x 3 3 V Al22 G3 l analog input 22 1 G4 analog input 1 Vssp7 G11 P digital ground 7 peripheral cells IPD1 G12 0 MSB 6 of image port data
6. 12 9 4 Pin Description PIN NUMBER SYMBOL DESCRIPTION 1 3 5 9 11 13 1 GA Data inputs 2 4 6 8 10 12 1Y 6Y Data outputs 7 GND Ground 0V 14 Voc Positive supply voltage 12 10 LM1117 12 10 1 General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1 2V at 800mA of load current It has the same pin out as National Semiconductor s industry standard LM317 The LM1117 is available in an adjustable version which can set the output voltage from 1 25V to 13 8V with only two external resistors In addition it is also available in five fixed voltages 1 8V 2 5V 2 85V 3 3V and 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packages A minimum of 10pF tantalum capacitor is required at the output to improve the transient response and stability 12 10 2 Features Available in 1 8V 2 5V 2 85V 3 3V 5V and Adjustable Versions Space Saving SOT 223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0 2 Max Load Regulation 0 4 Max e Temperature Range LM1117 0 C to 125 C 1111171 40 C to 125 C 12 10 3 Applications e 2 85V Model for SCSI 2 Active Termination Post Regulator for Switching DC DC Converter e High Efficiency Li
7. Symbol Vos Ves I IDM EAS IAR EAR dv dt Ty TsTG Ta 25 C Ta 70 C Ta 25 C Drain Source Voltage Gate Source Voltage Continuous Drain Current Pulsed Drain Current Continuous Source Current Diode Conduction Maximum Power Dissipation Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv dt Junction and Storage Temperature Range Absolute Maximum Ratings TA 25 C Unless Otherwise Noted IRF7316 Maximum 30 20 4 9 3 9 30 2 5 2 0 1 3 140 2 8 0 20 5 0 Symbol Vos Ves 14 Ta 25 C Ta 70 C TA 25 C Ta 70 C Drain Source Voltage Gate Source Voltage Continuous Drain Current Pulsed Drain Current Continuous Source Current Diode Conduction Maximum Power Dissipation Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv dt 32 TFT TV Service Manual Junction and Storage Temperature Range TJ TSTG 55 to 150 C 12 12 MC34063A 1 5 A Step Up Down Inverting Switching Regulators The MC34063A Series is a monolithic control circuit containing the primary functions required for DC to DC converters These devices consist of an internal temperature compensated reference comparator controlled duty cycle oscillator with an active current limit ci
8. TEST19 P13 l pu do not connect reserved for future extensions and for testing scan input Notes 1 input O output P power NC not connected st strapping pu pull up pd pull down od open drain 2 In accordance with the IEEE1149 1 standard the pads TDI TMS TCK and TRST are input pads with an internal pull up transistor and TDO is a 3 state output pad 3 For board design without boundary scan implementation connect the TRST pin to ground 4 This pin provides easy initialization of the Boundary Scan Test BST circuit TRST can be used to force the Test Access Port TAP controller to the TEST LOGIC RESET state normal operation at once 5 Pin strapping is done by connecting the pin to the supply via a 3 3 kQ resistor During the power up reset sequence the corresponding pins are switched to input mode to read the strapping level For the default setting no strapping resistor is necessary internal pull down 6 Pin RTCO operates as 2 C bus slave address pin RTCO O slave address 42H 43H default RTCO 1 slave address 40H 41H 7 Pin ALRCLK 0 24 576 MHz crystal default Philips order number 4322 143 05291 1 0 MHz crystal 9000000004304 DODODDDDODOCODC oDODODODODOCOd aoa a z zrEz o a BAATTIBE 30 lt 12 21 TPS72501 12 21 1 General Description The TPS725xx family of 1 A low dropout LDO linear regulators has fixed vol
9. 8 12 4 3 Pin Connections and Short Descriptions eee eee eee en n 8 12 5 EMI O dor LE i ie dii ie 10 12 5 1 General Description ii 10 12 5 2 Features PANDA AR DER RR ILL 10 12 64 E A NA 10 12 6 1 10 12 6 2 Features een eine a ead eed ee eel eds 10 12 6 3 Pin connections nn a ea ad 11 IZT TECTITI 3 POR NRO RE tee RR RAR ae ee OR RO lot 11 12 7 1 11 12 0 SA A 2 edge da dad ite 12 12 8 1 Features iaia iaia 12 12 8 2 Description u hand nk ed ene ed 12 12 8 3 Pin Description iaia 12 12 9 VAEVCI4A ia lita 12 12 9 1 Features cti idad diia 12 12 9 2 APPLIC cortando ne ela 12 12 9 3 12 12 9 4 PinDescriptioN ccoo italia 13 12 10 JM Tia iii aio 13 12 10 1 General Description ieina nea nali sei 13 12 10 2 Features himaalaja laduma 13 12 10 3 13 12 10 4 GConnection Diagrams scodella adele 13 12 11 AREFSTA RETO Occitan ibi 14 12 12 MC34068 Ancud 15 12 13 LM2576 52kHz Simple 3A Buck Regulator ii 16 12 14 290030 17 12 14 1 General een ei aaa 17 i 32 TFT TV Service Manual 26 07 2005 26 07 2005 12142 12 14 3 Pin DeSCrFIP OM 8er 42m 12 15 MSPSAXTG ica ae een aa i 12 15 16 Introduction sessi Maier aidata eko oa Ta 12 19 24 03 dentada 12 15 3 Pin conne
10. 12 4 3 Pin Connections and Short Descriptions SYMBOL PIN TYPE DESCRIPTION Port 2 8 bit programmable bidirectional port with alternative functions P2 0 PWM 1 VO output for 14 bit high precision Pulse Width Modulator PWM P2 1 PWMO 2 VO outputs for 6 bit PWMs 0 to 6 P2 2 PWM1 3 I O P2 3 PWM2 4 I O P2 4 PWM3 5 I O P2 5 PWM4 6 I O P2 6 PWM5 7 I O P2 7 PWM6 8 I O Port 3 8 bit programmable bidirectional port with alternative functions P3 0 ADCO 9 I O inputs for the software Analog to Digital Converter ADC facility P3 1 ADC1 10 I O 8 32 TFT TV Service Manual 26 07 2005 P3 2 ADC2 11 VO P3 3 ADC3 12 1 0 P3 4 PWM7 30 I O output for 6 bit PWM7 Vssc 13 I O core ground Port 0 8 bit programmable bidirectional port SCL NVRAM 14 I C bus Serial Clock input to Non Volatile RAM SDA NVRAM 15 1 0 l C bus Serial Data input output Non Volatile RAM P0 2 16 I O input output for general use P0 3 17 I O input output for general use P0 4 18 I O input output for general use P0 5 19 I O 8 mA current sinking capability for direct drive of Light Emitting Diodes LEDs P0 6 20 I O P0 7 21 I O input output for general use Vssa 22 analog ground CVBSO 23 Composite Video Baseband Signal CVBS input a positive going 1V CVBS1 24 peak to peak input is required connected via a 100 nF capacitor SYNC FILTER 5 sync pulse filter input for CVBS this pin should be connected to Vssa
11. 12 7 3 12 7 1 Description The TLC77xx family of micropower supply voltage supervisors are designed for reset control primarily in microcomputer and microprocessor systems During power on RESET is asserted when Von reaches 1 V After minimum Voo 2 V is established the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage Visense remains below the threshold voltage An internal timer delays return of the output to the inactive state to ensure proper system reset The delay time tu is determined by an external capacitor ta 2 1x104x Cr where Cris in farads ty is in seconds The TLC77xx has a fixed SENSE threshold voltage set by an internal voltage divider When SENSE voltage drops below the threshold voltage the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time ty has expired In addition to the power on reset and undervoltage supervisor function the TLC77xx adds power down control support for statc RAM When CONTROL is tied to GND RESET will act as active high The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure By driving the chip select CS of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal CSH1 of the microprocessor see Figure 10 the memory circuit is automatically disabl
12. DEEM 5 de emphasis output for capacitor AFD 6 AF decoupling input for capacitor DGND 7 digital ground AUD 8 audio output TOP 9 tuner AGC TakeOver Point TOP SDA 10 PC bus data input output SCL 11 I2C bus clock input SIOMA 12 sound intercarrier output and MAD select n c 13 not connected TAGC 14 tuner AGC output REF 15 4 MHz crystal or reference input VAGC 16 VIF AGC for capacitor note 1 CVBS 17 video output AGND 18 analog ground VPLL 19 VIF PLL for loop filter Vp 20 supply voltage 5 V AFC 21 AFC output 32 TFT TV Service Manual 26 07 2005 OP2 22 output 2 open collector SIF1 23 SIF differential input 1 SIF2 24 SIF differential input 2 12 2 TEA6415C 12 2 1 General Description The main function of the IC is to switch 8 video input sources on 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of synch top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 500 For D2MAC or Chroma signal the alignment is switched off by forcing with an external resistor bridge 5 Voc on the input Each input can be used as a normal input or as a MAC or Chroma input with external resistor bridge All the switching possibilities are changed through the BUS Driving 750 load needs an external transistor It is possi
13. PLL Vcc PLL GND LVDS Vcc LVDS GND NC 32 TFT TV Service Manual 12 15 MSP34X1G MSP3411G Multistandard Sound Processor Family 12 15 1 Introduction The MSP 34x1G family of single chip Multistandard Sound Processors covers the sound processing of all analog TV Standards worldwide as well as the NICAM digital sound standards The full TV sound processing starting with analog sound IF signal in down to processed analog AF out is performed on a single chip Figure shows a simplified functional block diagram of the MSP 34x1G The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature Surround sound can be reproduced to a certain extent with two loudspeakers The MSP 34x1G includes the Micronas virtualizer algorithm 3D PANORAMA which has been approved by the Dolby 1 Laboratories for with the Virtual Dolby Surround technology In addition the MSP 34x1G includes the PAN ORAMA algorithm These TV sound processing ICs include versions for processing the multichannel television sound MTS signal conforming to the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively Micronas Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Ra
14. 27 MHz nominal reset output active LOW MSB of direct analog to digital converted output data VSB MSB 4 of direct analog to digital converted output data VSB MSB 7 of direct analog to digital converted output data VSB 31 26 07 2005 0 P P O st pd 0 O OU ol O 0 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 NG N7 N8 N9 N10 N11 N12 N13 N14 P2 P3 P4 P5 P6 P7 P8 ADP3 Vssp11 Vssp12 RTCO Vssp13 ITRI IDQ IGPO AOUT Vssao Vopao Vpppg Vopp10 ADP7 ADP2 VDDD11 VDDD12 RTSO VDDD13 AMXCLK FSW ICLK TEST13 TEST14 TEST15 CE LLC2 CLKEXT ADP5 ADPO SCL RTS1 ASCLK ITRDY TEST16 TEST17 TEST18 EXMCLR LLC RES ADP8 ADP4 ADP1 32 TFT TV Service Manual INT_A P9 O od IC bus interrupt flag LOW if any enabled status bit has changed SDA P10 I O od serial data input output 2 C bus AMCLK P11 0 audio master clock output up to 50 of crystal clock ALRCLK P12 O st pd audio left right clock output can be strapped to supply via a 3 3 kW resistor to indicate that the default 24 576 MHz crystal ALRCLK 0 internal pull down has been replaced by a 32 110 MHz crystal ALRCLK 1 see notes 5 and 7
15. and 9 Data Output Clock This is the main clock output signal used to strobe the output data and HSOUT into external logic It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock When the sampling time is changed by adjusting the PHASE register the output timing is shifted as well The Data DATACK and HSOUT outputs are all moved so the timing relationship among the signals is maintained Analog Input for Red Channel Analog Input for Green Channel Analog Input for Blue Channel High impedance inputs that accept the Red Green and Blue channel graphics signals respectively The three channels are identical and can be used for any colors but colors are assigned for convenient reference They accommodate input signals ranging from 0 5 V to 1 0 V full scale Signals should be ac coupled to these pins to support clamp operation Horizontal Sync Input This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation The logic sense of this pin is controlled by serial register OEH Bit 6 Hsync Polarity Only the leading edge of Hsync is active the trailing edge is ignored When Hsync Polarity 0 the falling edge of Hsync is used When Hsync Polarity 1 the rising edge is active The input includes a Schmitt trigger for noise immunity with a nominal input threshold of 1 5 V Vertical Sync Input Thi
16. 6 6 0 6 9 9 5 a a a C O E E L LL m rue VCLAMPR RINNG2 0 as MODE OUT RINP a 34 MODE V2P5 IB Ace LINP 5 VAROUTR LINN Je 310 VAROUTL TPA3002D2 AVppREF 07 30 AGND VREF 8 290 AVpo VARDIFF 9 28 COSC VARMAX 10 Dl o ou 28 AGND REFGND 12 N BSLN L PVCCL L LOUTN La LOUTP LI vd gt o a 12 17 TDA 8 12 17 1 General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications It gets its input from two analog audio outputs DACA L and DACA R of MSP 34x0G The gain of the output is adjustable by the feedback resistor between the inputs and outputs 22 32 TFT TV Service Manual 26 07 2005 12 17 2 Features e Wide temperature range No switch ON OFF clicks Excellent power supply ripple rejection Low power consumption Short circuit resistant High performance high signal to noise ratio High slew rate Low distortion Large output voltage swing 12 17 3 Pinning IN DESCRIPTION Output A INA neg Inverting input A INA pos Non inverting input A SYMBOL P 1 2 3 Vss 4 Negative supply 5 6 7 8 OUTA INB pos Non inverting input B INB neg Inverting input B OUTB Output B Vbo Positive supply 12 18 0 12 18 1 Gene
17. LCD Monitors and Projectors Plasma Display Panels Scan Converters e Microdisplays e Digital TV 12 19 3 Pin Descriptions Complete Pinout list Function Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal SYNC Input Vertical SYNC Input Input for Sync on Green Clamp Input External CLAMP Signal PLL COAST Signal Input Outputs of Converter Red Bit 7 is the MSB Outputs of Converter Green Bit 7 is the MSB Outputs of Converter Blue Bit 7 is the MSB Data Output Clock HSYNC Output Phase Aligned with DATACK VSYNC Output Phase Aligned with DATACK Sync on Green Slicer Output Internal Reference Bypass Internal Midscale Voltage Bypass Connection for External Filter Components for Internal PLL Analog Power Supply Output Power Supply PLL Power Supply Ground Serial Port Data I O Serial Port Data Clock 100 kHz Maximum Serial Port Address Input 1 Function Horizontal Sync Output 24 Mnemonic RAIN GAIN BAIN HSYNC VSYNC SOGIN CLAMP COAST Red 7 0 Green 7 0 Blue 7 0 DATACK HSOUT VSOUT SOGOUT REF BYPASS MIDSCV FILT VD VDD PVD GND SDA SCL AO Pin Type Inputs Outputs References Power Supply Control Pin Function Descriptions Pin Name OUTPUTS HSOUT 32 TFT TV Service Manual 26 07 2005 A reconstructed and phase aligned version of the Hsync input Both the polarit
18. LM2576 series offers a high efficiency replacement for popular three terminal adjustable linear regulators It substantially reduces the size of the heat sink and in many cases no heat sink is required A standard series of inductors available from several different manufacturers are ideal for use with the LM2576 series This feature greatly simplifies the design of switch mode power supplies The feedback voltage is guaranteed to 2 tolerance for adjustable versions and the output voltage is guaranteed to 3 for fixed versions within specified input voltages and output load conditions The oscillator frequency is guaranteed to 10 External shutdown is included featuring less than 200 A standby current The output switch includes cycle bycycle current limiting and thermal shutdown for full protection under fault conditions Features 3 3V 5V 12V and adjustable output versions Voltage over specified line and load conditions Fixed version 33 max output voltage Adjustable version 2 max feedback voltage Guaranteed 3A output current e Wide input voltage range 4V to 40V 16 32 TFT TV Service Manual 26 07 2005 Wide output voltage range 1 23V to 37V Requires only 4 external components 52kHz fixed frequency internal oscillator Low power standby mode la typically gt 200 A 80 efficiency adjustable version typically gt 80 Uses readily available standard inductors Thermal shutdown and current limi
19. SOCKET DVI DVI RXC ANA VS DVI DDC DATA DVI INTO PW181 DDC CLK DVI 52 32 TFT TV Service Manual VIDEO 8 IMAGE PROCESSING ROM VxtoSAA7118_MP gt SVIDEOI C gt SAA TXT CC FB gt DE INTERLACER TXT CC R gt MP TXT CC G gt TXT CC B gt PW181 Progressive or VxtoSAA7118 PIP De interlacer Interlaced SVIDEO1 C gt SAA FRC en ae RGB FB PI5 SC FB gt Z OSD SCART2 SCR PIP G RGBFB gt V330 CS AA i SC B gt Correction PC R IN gt PC G IN gt 24 bit RGB PC B IN gt AD9883 PC HS gt PC VS gt 48 bit RGB DVI Input SIL151 53 32 TFT TV Service Manual 26 07 2005 TELETEXT DECODING 8 PIN8 SWITCHING TELETEXT CVBS e aA Li gt SAA5264 PHILIPS TXT CC FB TXT CC R INTO SAA7118 TXT CC G RGB FB PORTS TXT CC B SCI PINS gt SC2 PINS gt PIN 8 SWITCHING PCF8591 DC COMMUNICATION 32 TFT TV Service Manual 26 07 2005 INPUT 8 OUTPUTS 1 SCART 1 CVBS INPUT 2 SCART 2 CVBS INPUT 1 SCART 1 CVBS OUT 2 SCART 2 CVBS OUT 3 SCART 1 RGB FB INPUT 3 AUDIO LINE OUT 4 SCART 2 RGB FB INPUT 5 FAV IN 6 FRONT SVHS IN 7 VGA INPUT 8 DVI INPUT 9 PC AUDIO INPUT 10 MAIN TUNER 11 PIP TUNER 55 32 TFT TV Service Manual 26 07 2005 15 CIRCUIT DIAGRAMS 1 gt 17
20. TV Service Manual 26 07 2005 Unlike some regulators that have a minimum current requirement the TPS725 family is stable with no output load current The low noise capability of this family coupled with its high current operation and ease of power dissipation make it ideal for telecom boards modem banks and other noise sensitive applications 12 21 2 Features e 1 A Output Current Available in 1 5 V 1 6 V 1 8 V 2 5 V Fixed Output and Adjustable Versions 1 2 V to 5 5 V Input Voltage Down to 1 8 V Low 170 mV Dropout Voltage at 1 A TPS72525 Stable With Any Type Value Output Capacitor Integrated Supervisor SVS With 50 ms RESET Delay Time e Low 210 uA Ground Current at Full Load TPS72525 e Less than 1 uA Standby Current 2 Output Voltage Tolerance Over Line Load and Temperature 40C to 125C Integrated UVLO e Thermal and Overcurrent Protection 5 Lead SOT223 5 or DDPAK and 8 Pin SOP TPS72501 only Surface Mount Package KTT PACKAGE DDPAK TOP VIEW D PACKAGE DCQ PACKAGE TOP VI SOT223 5 M TOP VIEW 1 1j ON ENABLED TO FB T 21 T GND GND I al TI GND NC TI 4 T ENABLE RESETFBLTAS NC No internal connection 33 32 TFT TV Service Manual 26 07 2005 12 22 6 Description The TSOP11 series are miniaturized receivers for nfrared remote control systems PIN diode and preamplifier are assembled on lead frame the epoxy package is designed
21. and handshake signals Discontinuous data streams supported e 32 word 4 byte FIFO register for video output data e 28 word 4 byte FIFO register for decoded VBI data output Scaled 4 2 2 4 1 11 4 2 0 4 1 0 Y Cg Ca output Scaled 8 bit luminance only and raw CVBS data output Sliced decoded VBl data output Miscellaneous Power on control 5 V tolerant digital inputs and I O ports Software controlled power saving standby modes supported Programming via serial 2 C bus full read back ability by an external controller bit rate up to 0 kbits s Boundary scan test circuit complies with the IEEE Std 1149 b1 1994 e BGA156 package 12 20 3 Pinning SYMBOL PIN TYPE DESCRIPTION XTOUT 2 0 crystal oscillator output signal auxiliary signal XTALO A3 0 24 576 MHz 32 11 MHz crystal oscillator output not connected if TTL clock input of XTALI is used V Ss xtal A4 P ground for crystal oscillator 28 32 TFT TV Service Manual 26 07 2005 29 26 07 2005 TDO A5 O test data output for boundary scan test note 2 XRDY A6 0 task flag or ready signal from scaler controlled by XRQT XCLK AT 1 0 clock I O expansion port XPDO A8 1 0 LSB of expansion port data XPD2 A9 1 0 MSB 5 of expansion port data XPD4 A10 1 0 MSB 3 of expansion port data XPD6 A11 1 0 MSB 1 of expansion port data TEST1 A12 l pu do not connect reserved for future extensions and for tes
22. the same way as a ROM or EPROM The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory Program and Erase commands are written to the Command Interface of the memory An on chip Program Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents The end of a program or erase operation can be detected and any error conditions identified The command set required to control the memory is consistent with JEDEC standards The blocks in the memory are asymmetrically arranged ee Figures 5 and 6 Block Addresses he first or last 64 KBytes have been divided into our additional blocks The 16 KByte Boot Block can be used for small initialization code to start the microprocessor the two 8 KByte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored Chip Enable Output Enable and Write Enable signals control the bus operation of the memory They allow simple connection to most microprocessors often without additional logic The memory is offered TSOP48 12 x 20mm and TFBGA48 0 8mm pitch packages The memory is supplied with all the bits erased set to 1 12 28 2 FEATURES SUMMA
23. via a 100 nF capacitor IREF 26 reference current input for analog circuits for correct operation a 24 Q resistor should be connected to Vssa FRAME 27 0 Frame de interlace output synchronized with the VSYNC pulse to produce a non interlaced display by adjustment of the vertical deflection circuits TEST 28 not available connect this pin to Vssa COR 29 0 contrast reduction open drain active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display 30 I O P3 4 PWM7 described above VpDA 31 analog supply voltage 3 3 V B 32 0 Blue colour information pixel rate output G 33 0 Green colour information pixel rate output R 34 0 Red colour information pixel rate output VDS 35 0 video data switch push pull output for pixel rate fast blanking HSYNC 36 horizontal sync pulse input Schmitt triggered for a Transistor Transistor Level TTL version the polarity of this pulse is programmable by register bit TXT1 H POLARITY VSYNC 37 I vertical sync pulse input Schmitt triggered for a TTL version the polarity of this pulse is programmable by register bit TXT1 V POLARITY Vssp 38 periphery ground 6 39 core supply voltage 3 3 V OSCGND 40 crystal oscillator ground XTALIN 41 12 MHz crystal oscillator input XTALOUT 42 0 12 MHz crystal oscillator output RESET 43 reset input if this pin is HIGH for at least 2 machine cycles 24 oscillator periods while the oscillator is runn
24. 00K and user user color temp By pressing 4 w button select user color temp Press button to increase the user color temperature Press button to decrease the user color temperature User color temperature can be adjusted between 5000K and 9300K video format By pressing 4 w button select video format Press lt gt button to set the video format The options are auto ntsc pal secam and ntsc japan color space Displays the current color space used RGB YPbPr SMPTE240 YPbPr REC709 and YCbCr REC601 test pattern By pressing 4 w button select test pattern Press lt gt button to set the test pattern The options are none solid color and vert bars DE calibration colorspace 00 RGB test pattern none solid color vert bars color components all red green blue solid field level MNE adc calibration initial APS on off factory reset lt ok gt to activate A right left to adjust item 43 32 TFT TV Service Manual 26 07 2005 color components By pressing 4 w button select color components Press lt gt button to set the color components The options are all red green and blue solid field level By pressing 4 w button select solid field level Press button to increase or button to decrease the solid field level Solid field level can be adjusted between 0 and 64 adc calibration Not used for
25. 12 6 1 Description The ST24LC21 is a 1K bit electrically erasable programmable memory EEPROM organized by 8 bits This device can operate in two modes Transmit Only mode and IPC bidirectional mode When powered the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK The device will switch to the 1 C bidirectional mode upon the falling edge of the signal applied on SCL pin The ST24LC21 can not switch from the I C bidirectional mode to the Transmit Only mode except when the power supply is removed The device operates with a power supply value as low as 2 5V Both Plastic Dual in Line and Plastic Small Outline packages are available 12 6 2 Features 1 million Erase Write cycles 40 years data retention e 2 5 5 5 single supply voltage 400 Hz compatibility over the full range of supply voltage e Two wire serial interface PC bus compatible Page Write Up To 8 Bytes Byte random and sequential read modes Self timed programming cycle Automatic address incrementing Enhanced ESD Latch up Performances 10 32 TFT TV Service Manual 26 07 2005 12 6 3 Pin connections DIP Pin connections CO Pin connections ST24LC21 ST24LC21 NC NC NC AW1489 Vss NC Not connected Signal names SDA Serial data Address Input Output SCL Serial Clock I7C mode Voc Supply voltage Vss Ground VCLK Clock transmit only mode
26. 2 input right SCART 2 input left Analog Shield Ground 2 SCART 3 input right SCART 3 input left Analog Shield Ground 4 SCART 4 input right SCART 4 input left Not connected Analog reference voltage Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8V Volume capacitor AUX SCART output 1 left SCART output 1 right Reference ground 1 SCART output 2 left SCART output 2 right Not connected Not connected Subwoofer output Not connected Loudspeaker out left Loudspeaker out right Reference ground 2 Headphone out left Headphone out right Not connected Not connected Power on reset Not connected Not connected Not connected I S2 data input Digital ground Digital ground Digital ground Digital power supply 5V Digital power supply 5V Digital power supply 5V ADR clock 26 07 2005 OBL OBL LV LV OBL OBL LV LV OBL LV LV AHVSS LV LV AHVSS LV LV AHVSS LV LV LV or AHVSS OBL OBL OBL LV LV OBL OBL OBL LV LV OBL LV LV LV LV LV LV LV LV OBL LV LV LV LV OBL LV LV LV LV OBL OBL OBL OBL OBL OBL LV IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT AVSUP AVSUP NC NC AVSS AVSS MONO IN NC VREFTOP 5061 IN R SC1 IN L ASG1 SC2 IN R SC2 IN L ASG2 SC3 IN R SC3 IN L ASG4 SC4 IN R SC4 IN L NC AGNDC AHVSS AHVSS NC NC CAPL M AHVSUP
27. 32 TFT TV SERVICE MANUAL TABLE OF CONTENTS 1 NTRODU 1 2 ee cod dici ia i i dii nie ill da 1 3 F PARTITDA9886 bolide rei ile etnie eli dn a eil br an 1 4 MULTI STANDARD SOUND PROCESSOR i 2 5 4VIDEO SWITCH TEAG415 nirvana ateo dna a dod aada ie A 2 6 AUDIO AMPLIFIER STAGE WITH TPA3002D2 i 2 7 MAIN POWER SUPPLY SMPS AND POWER INTERFACE 050 3 8 MICROCONTROLLER sita ciate matsi O le ze a o brne r e dobovou boob 3 9 SERIAL ACCESS CMOS 4K x 8 32K bit EEPROM 24C32A eee eee een 3 10 CLASS AB STEREO HEADPHONE DRIVER TDA1308 aeee 3 fila SAW EIETERS ra are ole re dd te ob teten Delete 3 12 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM rear 4 12 42 TDA QB GO tale talenti alii a aan epee a sia 5 12 1 1 General Description fb cutee eins dot oi ee einen 5 12 1 2 Features u ee a 5 12 1 3 PINANG 340507 ii mee na ka AD tai aada ata 5 12 20 1 te tae de Peka u iaia naro 6 12 2 1 General Description 2 5 6 12 2 2 Features aee lenire aaa 6 12 2 3 A 6 12 A O Aderire i e in io 7 12 3 1 Features Dina E AA E A 7 12 3 2 DeSCcriptlON casais praias AE 7 12 3 3 Pin Eunetion table 5 52 7 12 3 4 Functional DESCrIpLIONS 8 12 47 SAAD2B4 ro ivo e re tit dl O o Ui AS A dor AA o oo io 8 12 4 1 aspas diavola 8 12 4 2 General Description
28. 4C32A devices on the same bus for up to 256K bits address space Advanced CMOS technology and broad voltage range make this device ideal for low power low voltage non volatile code and data applications The 24C32A is available in the standard 8 pin plastic DIP and both 150 mil and 26 07 2005 200 mil SOIC packaging 12 3 3 Pin Function table Name Function A0 A1 A2 User Configurable Chip Selects Vss Ground SDA Serial Address Data I O SCL Serial Clock WP Write Protect Input Vee 4 5V to 5 5V Power Supply 32 TFT TV Service Manual 12 3 4 Functional Descriptions The 24C32A supports a Bi directional 2 wire bus and data transmission protocol A device that sends data onto the bus is defined as transmitter and a device receiving data as receiver The bus must be controlled by a master device which generates the Serial Clock SCL controls the bus access and generates the START and STOP conditions while the 24C32A works as slave Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated 12 4 SAA5264 12 4 1 Features The following features apply to both SAA5264 and SAA5265 Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost Automatic detection of transmitted fastext links or service information packet 8 30 On Screen Display OSD for user interface menus using teletext and dedica
29. BWOOFER LEVEL AGC COLOR TEMPERATURE COLOR TEMPERATURE USER VIDEO FORMAT COLOR SPACE TEST PATTERN COLOR COMPONENTS SOLID FIELD LEVEL INITIAL APS BLACK EXPANSION DCTI DLTI LUMINANCE PEAKING FILM MODE FILM MODE SPEED VOF BAD CUT NR THRESHOLD NOISE REDUCTION LAI LEVEL SHARPNESS SPARKLE 47 DISPLAY CALIBRATION DEINTERLACER 32 TFT TV Service Manual 26 07 2005 AUDIO AMPL BOARD 2 LAYER AUDIO AMPLIFIER TPA3002D DS090C385 LVDS Tx NATIONAL 14 BLOCK DIAGRAM GENERAL BLOCK DIAGRAM AUDIO DECODING MSP34XX MICRONAS SAA7118E VIDEO PROCESSOR MAIN PICTURE PW1231 PHILIPS SAA7118E VIDEO PROCESSOR PIP PICTURE PHILIPS SILICON IMAGE AD9883 ANALOG DEVICE ADC 48 32 TFT TV Service Manual TUNER amp IF BLOCK PROZIA SC3_V_OUT 6 layer SCI V OUT TO TEA6415 kalk IF 1 PHILIP TUNI CVBS VIDEO SWITCH 4 Tuner 1 SIF IC 1 TO MSP3411G Philips TDA988 TUNI_QSSI AUDIO PROCESSOR FOR MAIN SOUND TO TEA6415 PIP uner IF IC 2 sa aie TO MSP3411G TDA9886 TUN2_QSS2 AUDIO PROCESSOR FOR PIP SOUND 49 32 TFT TV Service Manual 26 07 2005 SELECTED VIDEO vn TO SAA7118 MP MP FOR MAIN PICTURE SELECTED VIDEO VatoSAA7118 i gt TO 54A7118 PIP FOR PIP PIP PICTURE SELECTABLE V OUT VIDEO OUT e FOR SCART 2 26 07 2005 VIDEO MATRIXING TEA6415C VIDE
30. C Thermal Resistance o a E 160 150 n N V V V Vi V n Operating Junction Temperature Operating Ambient Temperature Range MC34063A MC33063AV NCV33063A MC33063A Storage Temperature Range 40 to 125 40 to 85 65 to 150 EE Maximum ratings are those values beyond which device damage can occur Maximum ratings applied to the device are individual stress limit values not normal operating conditions and are not valid simultaneously If these limits are exceeded device functional operation not implied damage may occur and reliability may be affected 1 Maximum package power dissipation limits must be observed 2 ESD data available upon request 3 NCV prefix is for automotive and other applications requiring site and change control EE temo at al a gt gt s 12 13 LM2576 52kHz Simple 3A Buck Regulator General Description The LM2576 series of monolithic integrated circuits provide all the active functions for a step down buck switching regulator Fixed versions are available with a 3 3V 5V or 12V fixed output Adjustable versions have an output voltage range from 1 23V to 37V Both versions are capable of driving a 3A load with excellent line and load regulation These regulators are simple to use because they require a minimum number of external components and include internal frequency compensation and a fixed frequency oscillator The
31. CAPL A SC1 OUT L SC1 OUT R VREF1 562 OUT L SC2 OUT R NC NC DACM SUB NC DACM L DACM R VREF2 DACA L DACA R NC NC RESETQ NC NC NC 125 DA IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP ADR CL 21 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47 46 45 44 43 42 41 20 39 38 37 36 35 34 33 32 31 30 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 11 10 32 TFT TV Service Manual 12 16 020 12 16 1 Description The TPA3002D2 is a 9 W per channel efficient Class D audio amplifier for driving bridged tied stereo speakers The TPA3002D2 can drive stereo speakers as low as 8 amp The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music FEATURES 9 W Ch Into an 8 0 Load From 12 V Supply Efficient Class D Operation Eliminates Heatsinks and Reduces Power Supply Requirements 32 Step DC Volume Control From 40 dB to 36 dB Line Outputs For External Headphone Amplifier With Volume Control Regulated 5 V Supply Output for Powering TPA6110A2 Space Saving Thermally Enhanced PowerPAD Packaging Thermal and Short Circuit Protection 12 16 2 Pin Connection TOP VIEW om amp amp E ZSSEESSEE SS a 5 292050
32. FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 SDRAM 12 27 2 Features PC66 PC100 and PC133 compliant Fully synchronous all signals registered on positive edge of system clock Internal pipelined operation column address can be changed every clock cycle Internal banks for hiding row access precharge Programmable burst lengths 1 2 4 8 or full page Auto Precharge includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes Self Refresh Modes standard and low power 64ms 4 096 cycle refresh e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply 12 27 3 Pin Descriptions PIN NUMBERS SYMBOL TYPE DESCRIPTION 38 CLK Input Clock CLK is driven by the system clock All SDRAM input signals are sampled on the positive edge of CLK CLK also increments the internal burst counter and controls the output registers 37 CKE Input Clock Enable CKE activates HIGH and deactivates LOW the CLK signal Deactivating the clock provides PRECHARGE POWER DOWN and SELF REFRESH operation all banks idle ACTIVE POWER DOWN row active in any bank or CLOCK SUSPEND operation burst access in progress CKE is synchronous except after the device enters power down and self refresh modes where CKE becomes asynchronous until after exiting the same mode The input buffers including CLK are disabled during power down and self refresh modes providing low standby power CKE may be tied HIGH 19 CS Input Chip Select CS e
33. Ground 20 Input Max 2Vpp Input Current 1mA Max 3MA 6 26 07 2005 32 TFT TV Service Manual 12 3 24C32A 12 3 1 Features Voltage operating range 4 5V to 5 5V Maximum write current 3 mA at 5 5V Standby current 1 mA typical at 5 0V e 2 wire serial interface bus 1 C compatible 100 kHz and 400 kHz compatibility Self timed ERASE and WRITE cycles Power on off data protection circuitry Hardware write protect e 1 000 000 Erase Write cycles guaranteed 32 byte page or byte write modes available Schmitt trigger filtered inputs for noise suppression Output slope control to eliminate ground bounce 2 ms typical write cycle time byte or page Up to eight devices may be connected to the same bus for up to 256K bits total memory Electrostatic discharge protection gt 4000V Data retention gt 200 years 8 pin PDIP and SOIC packages Temperature ranges Commercial C 0 C to 70 C Industrial 1 40 C to 85 C Automotive E 40 C to 125 C 12 3 2 Description The Microchip Technology Inc 24C32A is a 4K x 8 32K bit Serial Electrically Erasable PROM It has been developed for advanced low power applications such as personal communications or data acquisition The 24C32A also has a page write capability of up to 32 bytes of data The 24C32A is capable of both random and sequential reads up to the 32K boundary Functional address lines allow up to eight 2
34. Hz Terminals e Tinned CuFe alloy Pin configuration 1 Input 2 Switching input 3 Chip carrier ground 4 Output 5 Output 32 TFT TV Service Manual 26 07 2005 26 07 2005 K3953M Standard B G D K e L L Features TV IF video filter with Nyquist slopes at 33 90 MHz and 38 90 MHz Constant group delay Suitable for CENELEC EN 55020 Terminals Tinned CuFe alloy Pin configuration 1 Input 2 Input ground 3 Chip carrier ground 4 Output 5 Output 12 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM TDA9886 TEA6415C 24C32 SAA5264 LM317T ST24LC21 TLC7733 74LVC257A TALVC14A LM1117 IRF7314 IRF7316 MC34063A LM2576 DS90C385 MSP3411G TPA3002D TDA1308 PI5V330 AD9883A SAA7118E TPS72501 TSOP1136 PCF8591 PW1231 PW181 SIL151B SDRAM 4M 16 MT48LC4M16A2TG 75 FLASH 32 TFT TV Service Manual 12 1 6 12 1 1 General Description The TDA9885 is an alignment free single standard without positive modulation vision and sound IF signal PLL 12 1 2 Features 5 supply voltage Gain controlled wide band Vision Intermediate Frequency VIF amplifier AC coupled Multistandard true synchronous demodulation with active carrier regeneration very linear demodulation good intermodulation figures reduced harmonics excellent pulse response Gated phase detector for L L accent standard Fully integrated VIF Voltage Controlled Oscillator VCO alignment free frequencies switc
35. O SWITCH ST SCI VIN y SC2 VIN TUNI CVBS x gt PIP CVBS __ FAV CVES gt gt 50 32 TFT TV Service Manual AUDIO MATRIXING SC1 AUDIO LR IN HEADPHONE SC2 AUDIO LR IN gt 561 AUDIO LR OUT PC AUDIO LR IN gt SC AUDIO LR OUT FAV AUDIO LR IN LINE LR OUT 51 32 TFT TV Service Manual 26 07 2005 VESTEL sca ping INTOPCF8591 gt sc V IN JINTO TEA6415 VIDEO SWITCH SCI OUT gt SC2 AUDIO IFRIOM TEA6415 VIDEO SWITCH SCI AUDIO R IN INTO FROM i 502 AUDIO L OUT SCI AUDIO ROUT SVHSiromSC2 C INTO VPC3230D SC FB 625 NTORGB SCIG kat 5 SWITCH INTO TEA6415 ANI CRS LINE R OUT 6 AVI VIN OM AVI AUDIO L IN LINE L OUT CM AVI AUDIO R IN 4 INTO MSP3411G PERN PC GIN INTO ADC 0883 DSUB Eu 15 gt 3 peys INTO ADC9883 DDC CLE PC DDC DATA PC INTO PW181 Th mm ll Ti 26 07 2005 k A V BOARD l sr PINE INTO PCF8391 SCI VIN SCI VIOUT JFROM TUNI _CVBS SCI FB SCT E res COM 0 TMDS SIGNAL INTO 1 NOUT SWITCH SCI AUDIO L IN SCI AUDIO R IN SCI AUDIO L OUT Bee CLAI OU INTO FROM 5C1 AUDIO R OUT AUDIO MATRIX S VIDEO gt CIN INTO SAA7118 gt s Y IN A PC AUDIO R IN 0 DVI RX DVI RX0 DVI RXI i DYLRXI FORDECODINGINTO DV RVI A PIXELCLK 48 BIT RGB
36. RY SUPPLY VOLTAGE Vcc 2 7 to 3 6 for Program Erase and Read ACCESS TIMES 70 8 PROGRAMMING TIME 10ps per Byte Word typical 35 MEMORY BLOCKS 1 Boot Block Top or Bottom Location 2 Parameter and 32 Main Blocks PROGRAM ERASE CONTROLLER Embedded Byte Word Program algorithms ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend m UNLOCK BYPASS PROGRAM COMMAND Faster Production Batch Programming TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE 64 bit Security Code LOW POWER CONSUMPTION Standby and Automatic Standby m 100 000 PROGRAM ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE Manufacturer Code 0020h Top Device Code M29W160ET 22C4h Bottom Device Code M29W160EB 2249h 40 32 TFT TV Service Manual 26 07 2005 13 SERVICE MENU SETTINGS All system geometry and white balance alignments are performed in production service mode Before starting the production mode alignments make sure that all manual adjustments are done correctly To start production mode alignments enter the MENU by pressing M button and then press the digits 4 7 2 and 5 respectively The following menu appears on the screen a displa blank color black red green blue panel 0 8620080 0 power on time A backlight on time 330 Vestel V1 0 10 Release Build scart prescale a 00 2 nicam prescale down to change display sett
37. as IR filter The demodulated output signal can directly be decoded by 3 microprocessor The main benefit is the operation with short burst transmission codes e g RECS 80 and high data rates GND Features Special Features e Photo detector and preamplifier in one package e Enhanced data rate of 2500 bit s e Internal filter for PCM frequency e Operation with short bursts possible e Improved shielding against electrical field 25 cycles burst disturbance TTL and CMOS compatibility Output active low Low power consumption High immunity against ambient light Block Diagram Demodu lator mas 12 23 PCF8591 12 23 1 General Description The PCF8591 is a single chip single supply low power 8 bit CMOS data acquisition device with four analog inputs one analog output and a serial 1 C bus interface Three address pins AO A1 and A2 are used for programming the hardware address allowing the use of up to eight devices connected to the I C bus without additional hardware Address control and data to and from the device are transferred serially via the two line bidirectional PC bus The functions of the device include analog input multiplexing on chip track and hold function 8 bit analog to digital conversion and an 8 bit digital to analog conversion The maximum conversion rate is given by the maximum speed of the I C bus 12 23 2 Features Single power supply Operating supply voltage 2 5 V to 6 V Low standby cur
38. be select Positive LVDS differential clock output Negative LVDS differential clock output TTL level input Assertion low input TRI STATES the outputs ensuring low current at power down Power supply pins for TTL inputs Ground pins for TTL inputs Power supply pin for PLL Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs Description TTL level input Positive LVDS differential data output Negative LVDS differential data output level clock input The rising edge acts as data strobe Pin name TxCLK IN Programmable strobe select HIGH rising edge LOW falling edge Positive LVDS differential clock output Negative LVDS differential clock output TTL level input Assertion low input TRI STATES the outputs ensuring low current at power down Power supply pins for TTL inputs Ground pins for TTL inputs Power supply pin for PLL Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs Pins not connected 18 26 07 2005 No 28 4 4 1 1 1 1 1 3 4 1 2 1 3 No 28 4 4 1 1 1 1 1 3 5 1 2 2 4 6 VO 7717000007700 5 Pin Name TxOUT TxOUT TxCLKIN R FB TxCLK OUT TxCLK OUT PWR DOWN Vec GND PLL Vcc PLL GND LVDS Vcc LVDS GND Pin Name TXOUT TxOUT TxCLKIN R FB OUT TxCLK OUT PWR DOWN Vec GND
39. ble to have the same input connected to several outputs The starting configuration upon power on power supply 0 to 10V is undetermined In this case 6 words of 16 bits are necessary to determine one configuration In other case 1 word of 16 bits is necessary to determine one configuration 12 2 2 Features 20MHz Bandwidth Cascadable with another TEA6415C Internal address can be changed by pin 7 voltage 8 Inputs CVBS RGB MAC CHROMA 6 Outputs Possibility of MAC or chroma signal for each input by switching off the clamp with an external resistor bridge Bus controlled 6 5dB gain between any input and output 55dB crosstalk at 5mHz e Fully ESD protected 12 2 3 Pinning 1 Input Max 2Vpp Input Current 1mA Max 3mA Data Low level 0 3V Max 1 5V High level 3 0V Max Vcc 0 5V A Input Max 2Vpp Input Current 1mA Max 3mA 4 Clock Low level 0 3V Max 1 5V High level 3 0V Max Vcc 0 5V 5 Input Max 2Vpp Input Current 1mA Max 3mA 6 Input Max 2Vpp Input Current 1mA Max 3mA 7 Prog 8 Input Max 2Vpp Input Current 1mA Max 3mA 9 Vcc 12V 10 Input Max 2Vpp Input Current 1mA Max 3mA 11 Input Max 2Vpp Input Current 1mA Max 3mA 12 Ground 13 Output 5 5Vpp Min 4 5Vpp 14 Output 5 5Vpp Min 4 5Vpp 15 Output 5 5Vpp Min 4 5Vpp 16 Output 5 5Vpp Min 4 5Vpp 17 Output 5 5Vpp Min 4 5Vpp 18 Output 5 5Vpp Min 4 5Vpp 19
40. connected 3 15 13 8 7 ADR DA OUT LV ADR Data Output 4 14 12 7 6 I2S DA IN1 IN LV S1 data input 5 13 11 6 5 25 DA OUT OUT LV FS data output 6 12 10 5 4 I2S WS IN OUT LV IFS word strobe 7 11 9 4 3 I2S CL IN OUT LV FS clock 8 10 8 3 2 2C DA INOUT OBL FC data 9 9 7 2 1 I2C CL INOUT OBL PC clock 10 8 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand by low active 12 6 5 79 62 ADR_SEL IN OBL IC bus address select 13 5 4 78 61 DCTRIO 0 INOUT LV D CTRI O 0 14 4 3 77 60 D CTR O 1 IN OUT LV D CTR 1 0 1 15 3 76 59 NC LV Not connected 16 2 75 58 NC LV Not connected 17 NC LV Not connected Audio clock output 18 1 2 74 57 AUD CL OUT OUT LV 18 432 MHz 19 64 1 73 66 TP LV Test pin 20 63 52 72 55 XTAL OUT OUT OBL Crystal oscillator 21 62 51 1 54 XTAL IN IN OBL Crystal oscillator 22 61 50 70 53 TESTEN IN OBL Test pin IF Input 2 can be left 23 60 49 69 52 ANA IN2 IN 2 3 vacant only if IF input 1 is also not in use IF common can be left 24 59 48 68 51 ANA IN IN a N vacant only if IF input 1 is also not in use 25 58 47 67 50 ANA_IN1 IN LV IF input 1 20 32 TFT TV Service Manual 26 07 2005 Analog power supply 5V Analog power supply 5V Not connected Not connected Analog ground Analog ground Mono input Not connected Reference voltage IF A D converter SCART 1 input right SCART 1 input left Analog Shield Ground 1 SCART
41. ctions eee eee eee eee eee nenene 1216 PRA3002D E E LI eee eee eee eee eee nenene nenne 12 16 2 Pin Connection rare 12T TDAT3088 sat dose ee ei ae TES 12 17 1 General Description 1212 A ian a 121 94 ERT I PE E ET elia 128 330 12 18 1 General Description eee eee nen 12 19 ii Sal ia 12 19 1 General Description rrenan 12 19 2 Features nee ela 12 19 3 Pin Descriptions iaia iaia 12 20 SAATTIBE u Ras heen ae ee ees 12 20 1 General Description sie 12 20 2 Features ole ala al e ara 12 203 PINO aan aio 1221 0 12 21 1 General Description eee eee nen 12 21 27 Features ea a a ak 12 22 TSOP1136 2 2 2322 eae eee 1229 POFO8D9T zoo risos seve en NO aaa ona 12 23 1 General Description i 12 23 25 OAO S sitial drid 12 23 90 PIO Irratia doit 12 24 00 2300 1224 22 12243 12 25 2 O liniozalali 12 25 1 General Description arena 12 25 2 Features uil ibernazione 12 25 32 12 26 SIE151B ar 2er arte neun 12 26 1 General Description rrenan 12 26 2 Features nern engere 12 27 SDRAM 4M x 16 MT48LC4M16A2TG 75 nen 12 27 1 General Description eee eee nen 12272 A Sa ARENS ALE TE inne 12 27 3 Pin DESCHIPUONS estao tuner ze 200 neah ag sand une 12 28 FLASH TOMBI 2 12 28 1 De
42. data especially for compression and video phone applications with 6 bit phase accuracy 1 2 ns step width e Two independent programming sets for scaler part to define two ranges per field or sequences over frames Fieldwise switching between decoder part and expansion port X port input Brightness contrast and saturation controls for scaled outputs Vertical Blanking Interval VBI data decoder and slicer Versatile VBl data decoder slicer clock regeneration and byte synchronization e g for World Standard Teletext WST North American Broadcast Text System NABTS close caption Wide Screen Signalling WSS etc Audio clock generation Generation of a field locked audio master clock to support a constant number of audio clocks per video field Generation of an audio serial and left right channel Digital I O interfaces Real time signal port R port inclusive continuous line locked reference clock and real time status information supporting RTC level 3 1 refer to document RTC Functional Specification for details e Bidirectional expansion port X port with half duplex functionality D1 8 bit Y Cg CR Output from decoder part real time and unscaled Input to scaler part e g video from MPEG decoder extension to 16 bit possible e Video image port l port configurable for 8 bit data extension to 16 bit possible in master mode own clock or slave mode external clock with auxiliary timing
43. dio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP 34x1G has optimum stereo performance without any adjustments The MSP 34x1G has built in automatic functions The IC is able to detect the actual sound standard automat ically Automatic Standard Detection Furthermore pilot levels and identification signals can be evaluated internally with subsequent switching between mono stereo bilingual no 2 C interaction is necessary Automatic Sound Selection Sound 1 n Loud Loud re speaker speaker E 0 28 e processing a Sound DAC E Sound 1F2 Processing Subwoofer Headphone Sound Headphone Psi e Processing Source Select o PS SCARTI Select O ca SCART4 Select Mono 7 SCART2 PAE Source Select 1 S bus interface consists of five pins 1 1 S_DA_IN1 25 DA IN2 For input four channels two channels per line 2 16 bits per sampling cycle 32 kHz are transmitted 2 1 2 _DA_OUT For output two channels 2 16 bits per sampling cycle 32 kHz are transmitted 3 17 A _CL Gives the timing for the transmission of PS serial data 1 024 MHz 4 PS WS The I S WS word strobe line defines the left and right sample 19 32 TFT TV Service Manual 26 07 2005 12 15 2 Features 3D PANORAMA virtualizer approved by Dolby Laboratories with noise generator PANORAMA virtualizer algorithm Standard Selection with sing
44. e internal midscale voltage reference It should be connected to ground through a 0 1 uF capacitor The exact voltage varies with the gain setting of the Blue channel FILT External Filter Connection For proper operation the pixel clock generator PLL requires an external filter Connect the filter shown in Figure 6 to this pin For optimal performance minimize noise and parasitics on this node POWER SUPPLY VD Main Power Supply These pins supply power to the main elements of the circuit They should be filtered and as quiet as possible VDD Digital Output Power Supply A large number of output pins up to 25 switching at high speed up to 110 MHz generates a lot of power supply transients noise These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry If the AD9883A is interfacing with lower voltage logic V DD may be connected to a lower supply voltage as low as 2 5 V for compatibility PVD Clock Generator Power Supply The most sensitive portion of the AD9883A is the clock generation circuitry These pins provide power to the clock PLL and help the user design for optimal performance The designer should provide quiet noise free power to these pins GND Ground The ground return for all circuitry on chip It is recommended that the AD9883A be assembled on a single solid ground plane with careful attention given to ground curr
45. e sync and sync on green applications A clamp signal is generated internally or may be provided by the user through the CLAMP input pin This interface is fully programmable via a 2 wire serial interface Fabricated in an advanced CMOS process the AD9883A is provided in a space saving 80 lead LQFP surface mount plastic package and is specified over the 40 C to 85 C temperature range 12 19 2 Features Industrial Temperature Range Operation e 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0 5 V to 1 0 V Analog Input Range 500 ps p p PLL Clock Jitter at 110 MSPS 3 3 V Power Supply 23 32 TFT TV Service Manual 26 07 2005 Pin No 54 48 43 30 49 38 29 70 77 2 9 12 19 67 66 65 58 37 33 39 42 45 46 51 52 59 62 11 22 23 69 78 79 26 27 34 35 1 10 20 21 24 25 28 32 36 40 41 44 47 50 53 60 61 63 68 80 57 55 26 07 2005 Value 0 0 V to 1 0 V 0 0 V to 1 0 V 0 0 V to 1 0 V 3 3 V CMOS 3 3 V CMOS 0 0 V to 1 0 V 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 1 25 V 3 3 V 3 3 V 3 3 V OV 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS e Full Sync Processing Sync Detect for Hot Plugging Midscale Clamping Power Down Mode Low Power 500 mW Typical 4 2 2 Output Format Mode APPLICATIONS RGB Graphics Processing
46. ed during a power loss In this application the TLC77xx power has to be supplied by the battery The TLC77xxQ is characterized for operation over a temperature range of 40 C to 125 C and the 077 is characterized for operation over a temperature range of 40 C to 85 C 11 32 TFT TV Service Manual 26 07 2005 12 8 74LVC257A 12 8 1 Features Wide supply voltage range of 1 2 to 3 6 V In accordance with JEDEC standard no 8 1A CMOS lower power consumption Direct interface with TTL levels Output drive capability 50 _ transmission lines at 85 C 5 Volt tolerant inputs outputs for interfacing with 5 Volt logic 12 8 2 Description The 74LVC257A is a high performance low power low voltage Si gate CMOS device and superior to most advanced CMOS compatible TTL families Inputs can be driven from either 3 3V or 5 0V devices In 3 State operation outputs can handle 5V This feature allows the use of these devices as translators in a mixed 3 3V 5V environment The 74LVC257A is a quad 2 input multiplexer with 3 state outputs which select 4 bits of data from two sources and are controlled by a common data select input S The data inputs from source 0 11 0 to 4l O are selected when input S is LOW and the data inputs from source 1 11 1 to 4l 1 are selected when 5 in HIGH Data appears at the outputs 1Y to 4Y in true non inverting form from the selected inputs The 74LVC257A is the logic impl
47. ementation of a 4 pole 2 position switch where the position of the switch is determined by the logic levels applied to S The outputs are forced to a high impedance OFF state when OE is HIGH 12 8 3 Pin Description PIN NUMBER SYMBOL DESCRIPTION 1 S Common data select input 2 5 11 14 1loto 0 Data inputs from source 0 3 6 10 13 1 to 4 Data outputs from source 1 4 7 9 12 1Y to 4Y 3 State multiplexer outputs 8 GND Ground OV 15 OE 3 State output enable input active LOW 16 Voc Positive supply voltage 12 9 74LVC14A 12 9 1 Features e Wide supply voltage range of 1 2 to 3 6 V In accordance with JEDEC standard no 8 1A Inputs accept voltages up to 5 5 V CMOS low power consumption e Direct interface with TTL levels 12 9 2 Applications e Wave and pulse shapers for highly noisy environments Astable multivibrators Monostable multivibrators 12 9 3 Description The 74LVC14A is a high performance low power low voltage Si gate CMOS device and superior to most advanced CMOS compatible TTL families Inputs can be driven from either 3 3 V or 5 V devices This feature allows the use of these devices as translators in a mixed 3 3 V 5 V environment The 74LVC14A provides six inverting buffers with Schmitt trigger action It is capable of transforming slowly changing input signals into sharply defined jitter free output signals 12 32 TFT TV Service Manual 26 07 2005
48. ent paths 26 32 TFT TV Service Manual 26 07 2005 12 20 5 12 20 1 General Description The SAA7118E is a video capture device for applications at the image port of VGA controllers Philips X VIP is a new multistandard comb filter video decoder chip with additional component processing providing high quality optionally scaled video The SAA7118E is a combination of a four channel analog preprocessing circuit including source selection anti aliasing filter and ADC an automatic clamp and gain control a Clock Generation Circuit CGC a digital multistandard decoder containing two dimensional chrominance luminance separation by an adaptive comb filter and a high performance scaler including variable horizontal and vertical up and downscaling and a brightness contrast and saturation control circuit It is a highly integrated circuit for desktop video and similar applications The decoder is based on the principle of line locked clock decoding and is able to decode the colour of PAL SECAM and NTSC signals into ITU 601 compatible colour component values The SAA7118E accepts CVBS or S video Y C as analog inputs from TV or VCR sources including weak and distorted signals as well as baseband component signals Y Pg PR or RGB An expansion port X port for digital video bidirectional half duplex D1 compatible is also supported to connect to MPEG or video phone codec At the so called image port l port the SAA7118E suppor
49. erate with a Falling edge strobe Receiver DS90CF386 DS90CF366 without any translation logic The DS90C385 is also offered in a 64 ball 0 8mm fine pitch ball grid array FBGA package which provides a 44 reduction in PCB footprint compared to the TSSOP package This chipset is an ideal means to solve EMI and cable size problems associated with wide high speed TTL interfaces 12 14 2 Features e 20 to 85 MHz shift clock support Best in Class Set 4 Hold Times TxINPUTs TX power consumption lt 130 mW typ 85MHz Grayscale Tx Power down mode lt 200uW max Supports VGA SVGA XGA and Dual Pixel SXGA e Narrow bus reduces cable size and cost 17 32 TFT TV Service Manual 26 07 2005 Up to 2 38 Gbps throughput Up to 297 5 Megabytes sec bandwidth 345 mV typ swing LVDS devices for low EMI PLL requires no external components Compatible with TIA EIA 644 LVDS standard Low profile 56 lead or 48 lead TSSOP package DS90C385 also available in a 64 ball 0 8mm fine pitch ball grid array FBGA package 12 14 3 Pin Description DS90C385 MTD56 TSSOP Package Pin Description FPD Link Transmitter Description TTL level input This includes 8 Red 8 Green 8 Blue and 4 control lines FPLINE FPFRAME and DRDY also referred to as HSYNC VSYNC Data Enable Positive LVDS differential data output Negative LVDS differential data output TTL level clock input Pin name TxCLK IN Programmable stro
50. erlacer vof bad cut nr threshold noise reduction lai level sharpness sparkle right left to adjust item 45 26 07 2005 32 TFT TV Service Manual film mode speed By pressing 4 w button select film mode speed Film mode speed can be set to 0 1 2 or 3 by pressing lt gt button vof video on film By pressing 4 w button select vof VOF can be set to on or off by pressing lt gt button bad cut By pressing 4 w button select vof Bad cut can be set to on or off by pressing lt gt button nr threshold By pressing 4 w button select nr threshold Nr threshold can be set to low or high by pressing lt gt button noise reduction By pressing 4 w button select noise reduction Noise reduction can be adjusted between 0 and 255 by pressing lt gt button lai level By pressing 4 w button select lai level Lai level can be set to 0 1 or 2 by pressing 4 button sharpness By pressing 4 w button select sharpness Sharpness can be adjusted between 0 and 255 by pressing lt gt button sparkle By pressing 4 w button select sparkle Sparkle can be adjusted between 0 and 255 by pressing lt gt button 46 32 TFT TV Service Manual 26 07 2005 26 07 2005 These values are not recorded for this reason they are adjusted to a specified value 13 4 Service menu factory reset values SERVICE MENU BLANK COLOR SCART PRESCALE NICAM PRESCALE FM AM PRESCALE SUBWOOFER CORNER SU
51. hable for all negative and positive modulated standards via 1 C bus Digital acquisition help VIF frequencies of 33 4 33 9 38 0 38 9 45 75 and 58 75 MHz 4 MHz reference frequency input signal from Phase Locked Loop PLL tuning system or operating as crystal oscillator e VIF Automatic Gain Control AGC detector for gain control operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals Precise fully digital Automatic Frequency Control AFC detector with 4 bit digital to analog converter AFC bits via C bus readable e TakeOver Point TOP adjustable via I C bus or alternatively with potentiometer Fully integrated sound carrier trap for 4 5 5 5 6 0 and 6 5 MHz controlled by FM PLL oscillator Sound IF SIF input for single reference Quasi Split Sound QSS mode PLL controlled e SIF AGC for gain controlled SIF amplifier single reference ASS mixer able to operate in high performance single reference ASS mode and in intercarrier mode switchable via C bus AM demodulator without extra reference circuit Alignment free selective FM PLL demodulator with high linearity and low noise e C bus control for all functions C bus transceiver with pin programmable Module Address MAD 12 1 3 Pinning SYMBOL PIN DESCRIPTION VIF 1 1 VIF differential input 1 VIF2 2 VIF differential input 2 01 3 output 1 open collector FMPLL 4 FM PLL for loop filter
52. hip RAM of up to 64 Kbytes is available A complete microprocessor system can be implemented simply by adding external ROM The on chip processor can be disabled to allow external processor control of all internal functions 9 SERIAL ACCESS CMOS 4K x 8 32K bit EEPROM 24C32A The Microchip Technology Inc 24C32A is a 4K x 8 32K bit Serial Electrically Erasable PROM It has been developed for advanced low power applications such as personal communications or data acquisition The 24C32A also has a page write capability of up to 32 bytes of data The 24C32A is capable of both random and sequential reads up to the 32K boundary Functional address lines allow up to eight 24C32A devices on the same bus for up to 256K bits address space Advanced CMOS technology and broad voltage range make this device ideal for low power low voltage non volatile code and data applications 10 CLASS AB STEREO HEADPHONE DRIVER TDA1308 The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications 11 SAW FILTERS K9656M Standard B G D K e L L Features IF audio filter with two channels e Channel 1 L with one pass band for sound carriers at 40 40 MHz L and 39 75 MHz L NICAM e Channel 2 B G D K L 1 with one pass band for sound carriers between 32 35 MHz and 33 40 M
53. icam prescale 2 fm am prescale 5 subwoofer comer TTT je subwoofer layer E ago adjustment AN right left to adjust scart prescale fm am prescale By pressing 4 w button select fm am prescaler Press lt gt button to set the fm am prescaler Fm am prescale can be adjusted between 0 and 127 subwoofer corner By pressing 4 w button select subwoofer corner Press lt gt button to set the subwoofer corner Subwoofer corner can be adjusted between 0 and 7 subwoofer level By pressing 4 w button select subwoofer level Press lt gt button to set the subwoofer level Subwoofer level can be adjusted between 0 and 32 300 adjustment Adjustment for automatic gain control of tuner By pressing 4 w button select agc adjustment Press lt gt button to set the agc adjustment Agc adjustment can be adjusted between 0 and 31 42 32 TFT TV Service Manual 26 07 2005 13 2 calibration menu By pressing buttons select the second icon calibration menu appears on the screen calibration color temp 5500K 6500K 7500K 9300K user user color temp m 0 6500ki video format auto colorspace Lo RGB test pattern none solid color vert bars color components all red green blue solid field level down to change cal settings scrolling menu color temp By pressing 4 w button select color temp Press button to set the color temperature The options are 5500K 6500K 7500K 93
54. in order to achieve good stereo separation for BTSC and EIA J The MSP34x1G has optimum stereo performance without any adjustments 5 4 VIDEO SWITCH TEA6415 In case of three or more external sources are used the video switch IC TEA6415 is used The main function of this device is to switch 8 video input sources on the 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of sync top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 5dB For D2MAC or Chroma signal the alignment is switched off by forcing with an external resistor bridge 5VDC on the input Each input can be used as a normal input or as a MAC or Chroma input with external Resistor Bridge All the switching possibilities are changed through the BUS Driving 750hm load needs an external resistor It is possible to have the same input connected to several outputs 6 AUDIO AMPLIFIER STAGE WITH TPA3002D2 The TPA3002D2 is a 9 W per channel efficient Class D audio amplifier for driving bridged tied stereo speakers The TPA3002D2 can drive stereo speakersas low as 8 amp The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music 32 TFT TV Service Manual 26 07 2005 7 MAIN POWER SUPPLY SMPS AND POWER INTERFACE BOARD The DC voltages required at various parts of the chassis and inverters are provided by an
55. ing the device resets this pin should be connected to Vppp via a capacitor Vopp 44 periphery supply voltage 3 3 V Port 1 8 bit programmable bidirectional port P1 0 45 I O input output for general use P1 1 46 1 0 input output for general use P1 2 47 I O input output for general use P1 3 48 I O input output for general use SCL 49 I 12C bus Serial Clock input from application 32 TFT TV Service Manual 26 07 2005 SDA 50 VO PC bus Serial Data input from application P1 4 1 YO input output for general use P1 5 52 VO input output for general use 12 5 7 12 5 1 General Description The LM117 LM217 LM317 are monolithic integrated circuit in TO 220 ISOWATT220 TO 3 and D 2 PAK packages intended for use as positive adjustable voltage regulators They are designed to supply more than 1 5A of load current with an output voltage adjustable over a 1 2 to 37V range The nominal output voltage is selected by means of only a resistive divider making the device exceptionally easy to use and eliminating the stocking of many fixed regulators 12 5 2 Features e Output voltage range 1 2 To 37V Output current In excess of 1 5A 0 1 Line and Load Regulation Floating Operation for High Voltages Complete Series of Protections Current Limiting Thermal Shutdown And Soa Control 12 6 1
56. ings There are 3 submenu in service menu These are display calibration and deinterlacer menus Press lt gt buttons to select a menu title and then A W buttons to select a menu item and lt gt or OK buttons to set the menu item to the desired option To exit the service menu press M button Entire service menu parameters of Plasma TV are listed below 13 1 display menu By pressing lt gt buttons select the first icon display menu appears on the screen displa blank color black red green blue panel 0 8620680 0 power on time A backlight on time 330 Vestel V1 0 10 Release Build scart prescale MH O nicam prescale a eae down to change display settings blank color By pressing 4 w button select blank color Press 4 button to set the blank color The options are black red green and blue panel Displays panel resolution power on time Displays total working time of the set backlight on time Displays total backlight on time of the set 41 32 TFT TV Service Manual 26 07 2005 scart prescale By pressing 4 w button select scart prescaler Press 4 lt button to set the scart prescaler Scart prescale can be adjusted between 0 and 127 nicam prescale By pressing 4 w button select nicam prescaler Press 4 button to set the nicam prescaler Nicam prescale can be adjusted between 0 and 127 display scart prescale mm Bf n
57. inputs Al1x 3 3 V AGNDA L2 P analog signal ground 4 3 analog input 4 Vsspg L4 P digital ground 9 peripheral cells Vsspio L5 P digital ground 10 core ADP6 L6 0 MSB 2 of direct analog to digital converted output data VSB 30 26 07 2005 32 TFT TV Service Manual MSB 5 of direct analog to digital converted output data VSB digital ground 11 peripheral cells digital ground 12 core real time control output contains information about actual system clock frequency field rate odd even sequence decoder status subcarrier frequency and phase and PAL sequence the RTCO pin is enabled via 1 C bus bit RTCE see notes 5 6 digital ground 13 peripheral cells image port output control signal affects all input port pins inclusive ICLK enable and active polarity is under software control bits IPE in subaddress 87H output path used for testing scan output output data qualifier for image port optional gated clock output general purpose output signal 0 image port controlled by subaddresses 84H and 85H analog test output do not connect ground for internal Clock Generation Circuit CGC analog supply voltage 3 3 V for internal clock generation circuit digital supply voltage 9 peripheral cells digital supply voltage 10 core MSB 1 of direct anal
58. le PC transmission Automatic Sound Selection mono stereo bilingual Automatic Carrier Mute function Interrupt output programmable indicating status change e Loudspeaker Headphone channel with volume balance bass treble loudness AVC Automatic Volume Correction Subwoofer output with programmable low pass and complementary high pass filter e 5 band graphic equalizer for loudspeaker channel Spatial effect for loudspeaker channel processing of all deemphasis filtering e Two selectable sound IF SIF inputs Four Stereo SCART line inputs one Mono input two Stereo SCART outputs e Complete SCART in out switching matrix Two PS inputs one PS output Automatic Standard Detection of terrestrial TV standards Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction BTSC stereo separation MSP 34416 also EIA J significantly better than specification SAP and stereo detection for BTSC system Demodulation of the FM Radio multiplex signal 12 15 83 Pin connections NC not connected leave vacant LV if not used leave vacant OBL obligatory connect as described in circuit diagram DVSS if not used connect to DVSS AHVSS connect to AHVSS Pin No Pin Name Type ine Ba Short Description PLCC PSDIP PSDIP PQFP PLQFP 68 pin 64 pin 52 pin 80 pin 64 pin 1 16 14 9 8 ADR WS OUT LV ADR word strobe 2 NC LV Not
59. ly controlled IC bus PLL Below you will find info on one of the Tuners in use General description of UV1316 The UV1316 tuner belongs to the UV 1300 family of tuners which are designed to meet a wide range of applications It is a combined VHF UHF tuner suitable for CCIR systems B G H L L and I The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient Features of UV1316 1 Member of the UV1300 family small sized UHF VHF tuners 2 Systems CCIR B G H L L and l OIRT D K 3 Digitally controlled PLL tuning via 1 C bus 4 Off air channels S cable channels and Hyperband 5 World standardised mechanical dimensions and world standard pinning 6 Compact size 7 Complies to CENELEC EN55020 and EN55013 Pinning 1 Gain control voltage AGC 4 0V Max 4 5 2 Tuning voltage 3 FC bus address select i Max 5 5V 4 I2C bus serial clock Min 0 3V Max 5 5V 5 12C bus serial data i Min 0 3V Max 5 5V 6 Not connected 7 PLL supply voltage 5 0V Min 4 75V Max 5 5 8 ADC input 9 Tuner supply voltage 33V Min 30V Max 35V 10 Symmetrical IF output 1 11 Symmetrical IF output 2 3 IF PART TDA9886 The TDA9886 is an alignment free multistandard PAL SECAM and NTSC vision and sound IF signal PLL Both devices can be used for TV VTR PC and set top box applications The following figure
60. main power supply unit and power interface board The main power supply unit is designed for 24V and 12V DC supply Power interface board generates 12V for audio amplifier 5V and 3 3V stand by voltage and 8V 12V 5V and 3V3 supplies for other different parts of the chassis An optocoupler is used to control the regulation of line voltage and stand by power consumption There is a regulation circuit in secondary side During the switch on period of the transistor energy is stored in the transformer During the switch off period energy is fed to the load via secondary winding By varying switch on time of the power transistor it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations 8 MICROCONTROLLER The microprocessor is embedded inside PW181 chip which also handles scaling frame rate conversion and OSD generation The on chip 16 bit microprocessor is a Turbo x86 compatible processor core with on chip peripherals timers interrupt controller 2 wire serial master slave interface UART I O ports and more Special peripherals such as Infrared IR pulse decoders and a digital pulse width modulator PWM are also included There are two independent 2 wire serial master slave interface modules that can be multiplexed to control up to five 2 wire serial ports The slave 2 wire interface is designed for HDCP use only and requires the use of HDCP Image Processors On c
61. nables registered LOW and disables registered HIGH the command decoder All commands are 38 32 TFT TV Service Manual 26 07 2005 masked when CS is registered HIGH CS provides for external bank selection on systems with multiple banks CSF is considered part of the command code Command Inputs WE CASH and RAS along with CS define the command being entered Input Output Mask DQM is an input mask signal for write accesses and an output enable signal for read accesses Input data is masked when DQM is sampled HIGH during a WRITE cycle The output buffers are placed in a High Z state two clock latency when DQM is sampled HIGH during a READ cycle On the x4 and x8 DQML Pin 15 is a NC and DQMH is DQM On the x16 DQML corresponds to DQ0 DQ7 and DQMH corresponds to DQ8 DQ15 DQML and DQMH are considered same state when referenced as DQM Bank Address Inputs BAO and BA1 define to which bank the ACTIVE READ WRITE or PRECHARGE command is being applied Address Inputs A0 A11 are sampled during the ACTIVE command row address A0 A11 and READ WRITE command column address AO A9 x4 40 38 x8 AO A7 x16 with A10 defining auto precharge to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged A10 HIGH or bank selected by BAO 1 A1 LOW The address inputs also provide the op code duri
62. near Regulators Battery Charger Battery Powered Instrumentation 12 10 4 Connection Diagrams TO 252 SOT 223 TO 220 Jin input byv po a peas ni ru O Sn et se m Ab ORD ADI Fand Kur 4 i 131090 ta A Top View Top View Top View 13 32 TFT TV Service Manual 26 07 2005 12 11 IRF7314 IRF7316 Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on resistance per silicon area This benefit combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for provides the designer with an extremely efficient and reliable device for use in a wide variety of applications The SO 8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple die capability making it ideal in a variety of power applications With these improvements multiple devices can be used in an application with dramatically reduced board space The package is IRF7316 Voss 30V designed for vapor phase infra red or wave soldering techniques IRF7314 HEXFET Power MOSFET Voss 20V Rpsion 0 0580 Top View Absolute Maximum Ratings TA 25 C Unless Otherwise Noted IRF7314 Units V mJ mJ V ns C Units V mJ mJ V ns 26 07 2005 Maximum 20 12 5 3 4 3 21 2 5 2 0 1 3 150 2 9 0 20 5 0 55 to 150
63. ng a LOAD MODE REGISTER command Data Input Output Data bus for x16 4 7 10 13 42 45 48 and 51 are NCs for x8 and 2 4 7 8 10 13 42 45 47 48 51 and 53 are NCs for x4 Data Input Output Data bus for x8 2 8 47 53 are NCs for x4 Data Input Output Data bus for x4 No Connect These pins should be left unconnected Address input A12 for the 256Mb and 512Mb devices DQ Power Isolated DQ power on the die for improved noise immunity DQ Ground Isolated DQ ground on the die for improved noise immunity Power Supply 3 3V 0 3V Ground 39 26 07 2005 Input Input Input Input x16 I O x8 I O x4 1 0 Supply Supply Supply Supply WE CAS RAS x4 x8 DQM x16 DQML DQMH BAO BA1 A0 A11 DQ0 DQ15 DQ0 DQ7 DQ0 DQ3 NC NC VopQ VssQ Vpo Vss 16 17 18 39 15 39 20 21 23 26 29 34 22 35 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 2 5 8 11 44 47 50 53 5 11 44 50 40 36 3 9 43 49 6 12 46 52 1 14 27 28 41 54 32 TFT TV Service Manual 12 28 FLASH 16MBit 12 28 1 Description The M29W160E is a 16 Mbit 2Mb x8 or 1Mb x16 non volatile memory that can be read erased and reprogrammed These operations can be performed using a single low voltage 2 7 to 3 6V supply On power up the memory defaults to its Read mode where it can be read in
64. ng techniques Third generation advanced scaling techniques Second generation Automatic Image Optimization Frame rate conversion e Video processing e On Screen Display OSD On chip microprocessor e JTAG debugger and boundary scan Picture in picture PIP Multi region non linear scaling Hardware 2 wire serial bus support 12 25 3 Applications Multimedia Displays 36 32 TFT TV Service Manual 26 07 2005 Plasma Displays Digital Television 12 26 SIL151B 12 26 1 General Description The Sil 151B receiver uses PanelLink Digital technology to support high resolution displays up to SXGA 25 112MHz This receiver supports up to true color panels 24 bit pixel 16M colors with both one and two pixels per clock All PanelLink products are designed on a scaleable CMOS architecture ensuring support for future performance enhancements while maintaining the same logical interface System designers can be assured that the interface will be stable through a number of technology and performance generations PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high speed mixed signal design providing the system designer with a digital interface solution that is quicker to market and lower in cost 12 26 2 Features e Low Power Operation 201mA max current consumption at 3 3V core operation Time staggered data output for reduced gr
65. og to digital converted output data VSB MSB 6 of direct analog to digital converted output data VSB digital supply voltage 11 peripheral cells digital supply voltage 12 core real time status or sync information controlled by subaddresses 11H and 12H digital supply voltage 13 peripheral cells audio master external clock input fast switch blanking with internal pull down inserts component inputs into CVBS signal clock output signal for image port or optional asynchronous back end clock input do not connect reserved for future extensions and for testing do not connect reserved for future extensions and for testing do not connect reserved for future extensions and for testing chip enable or reset input with internal pull up line locked 1 a2 clock output 13 5 MHz nominal external clock input intended for analog to digital conversion of VSB signals 36 MHz MSB 3 of direct analog to digital converted output data VSB LSB of direct analog to digital converted output data VSB serial clock input 2 C bus real time status or sync information controlled by subaddresses 11H and 12H audio serial clock output target ready input for image port data do not connect reserved for future extensions and for testing do not connect reserved for future extensions and for testing do not connect reserved for future extensions and for testing external mode clear with internal pull down line locked system clock output
66. on enables simple flexible cost 26 07 2005 effective solutions featuring fewer required components Digital 1231 Video Output PW1231 System Block Diagram 12 24 2 Features Built In Memory Controller e Motion Adaptive Deinterlace Processor Intelligent Edge Deinterlacing e Digital Color Luminance Transient Improvement DCTI DLTI Interlaced Video Input Options including NTSC and PAL Independent horizontal and vertical scaling Copy Protection e Two Wire Serial Interface 12 24 3 Applications For use with Digital Displays Flat Panel LCD DLP TVs 35 32 TFT TV Service Manual Rear Projection TVs e Plasma Displays LCD Multimedia Monitors e Multimedia Projectors 12 25 PW181 12 25 1 General Description The PW181 ImageProcessor is a highly integrated system on a chip that interfaces computer graphics and video inputs in virtually any format to a fixed frequency flat panel display Computer and video images from NTSC PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed frequency target display device with any resolution up to WUXGA Video data from 4 3 aspect ratio NTSC or PAL and 16 9 aspect ratio HDTV or SDTV is supported Multi region nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display Advanced scaling techniques are supported such a
67. ound bounce and lower EMI Sync Detect feature for Plug amp Display IMHot Plugginglo Cable Distance Support over 5m with twisted pair fiber optics ready e Compliant with DVI 1 0 DVI is backwards compatible with VESA P amp D and DFP e HSYNC de jitter circuitry enables stable operation even when HSYNC contains jitter Low power standby mode Automatic entry into standby mode with clock detect circuitry Standard and Pb free packages 12 27 SDRAM 4M x 16 MT48LC4M16A2TG 75 12 27 1 General Description The Micron 64Mb SDRAM is a high speed CMOS dynamic random access memory containing 67 108 864 bits It is internally configured as a quad bank DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal CLK Each of the x4 s 16 777 216 bit banks is organized as 4 096 rows by 1 024 columns by 4 bits Each of the x8 s 16 777 216 bit banks is organized as 4 096 rows by 512 columns by 8 bits Each of the x16 s 16 777 216 bit banks is organized as 4 096 rows by 256 columns by 16 bits Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed BAO BA1 selec
68. oundary scan test with internal pull up notes 2 3 and 4 XRH C7 I O horizontal reference I O expansion port Vppp2 C8 P digital supply voltage 2 core VDDD3 C9 P digital supply voltage 3 peripheral cells VDDD4 C10 P digital supply voltage 4 core XPD7 C11 1 0 MSB of expansion port data TESTO C12 NC do not connect reserved for future extensions and for testing TEST10 C13 NC do not connect reserved for future extensions and for testing TEST11 C14 l pu do not connect reserved for future extensions and for testing scan input Al43 D1 analog input 3 12 D2 analog input 2 Al4D D3 differential input for ADC channel 4 pins 41 to Al44 VDDA4 D4 P analog Supply voltage for analog inputs Al4x 3 3 V Vssp1 D5 P digital ground 1 peripheral cells TMS D6 l pu test mode select input for boundary scan test or scan test note 2 Vssp2 D7 P digital ground 2 core substrate connection XRV D8 1 0 vertical reference I O expansion port Vssp3 D9 P digital ground 3 peripheral cells Vssp4 D10 P digital ground 4 core Vssps D11 P digital ground 5 peripheral cells VpoD5 D12 P digital supply voltage 5 peripheral cells TEST12 D13 l pu do not connect reserved for future extensions and for testing scan input HPDO D14 1 0 LSB of host port data I O extended Cp Cr input for expansion port extended Ce Cr output for image port 32 TFT TV Service Manual
69. output HPD7 G13 VO MSB of host port data I O extended Cg Cr R input for expansion port extended Cs CR output for image port IPDO G14 0 LSB of image port data output ADD H1 differential input for ADC channel 2 pins AI24 to AI21 3 2 l analog input 23 Vssa2 H3 P ground for analog inputs Al2x VDDA2 H4 P analog supply voltage for analog inputs Al2x IPD2 1 0 MSB 5 of image port data output Vppp7 H12 P digital supply voltage 7 peripheral cells IPD4 H13 0 MSB 3 of image port data output IPD3 H14 O MSB 4 of image port data output VDDA2A J1 P analog supply voltage for analog inputs Al2x 1 J2 analog input 1 AI24 J3 l analog input 24 Vssa1 J4 P ground for analog inputs Al1x Vsspg J11 P digital ground 8 core VDDD8 J12 P digital supply voltage 8 core IPD6 J13 O MSB 1 of image port data output IPD5 J14 0 MSB 2 of image port data output Al12 K1 analog input 2 3 2 l analog input 13 AND K3 l differential input for ADC channel 1 pins Al14 to Al11 VDDA1 K4 P analog Supply voltage for analog inputs Al1x 3 3 V IPD7 K11 O MSB of image port data output IGPH K12 0 multi purpose horizontal reference output signal image port controlled by subaddresses 84H and 85H IGP1 K13 0 general purpose output signal 1 image port controlled by subaddresses 84H and 85H IGPV K14 0 multi purpose vertical reference output signal image port controlled by subaddresses 84H and 85H VDDA1A L1 P analog supply voltage for analog
70. ral Description The PI5V330 is well suited for video applications when switching composite or RGB analog A picture in picture application will be described in this brief The pixel rate creates video overlays so two or more pictures can be viewed at the same time An inexpensive NTSC titler can be implemented by superimposing the output of a character generator on a standard composite video background 12 19 AD9883A 12 19 1 General Description The AD9883A is a complete 8 bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA 1280 1024 at 75 Hz The AD9883A includes a 140 MHz triple ADC with internal 1 25 V reference a PLL and programmable gain offset and clamp control The user provides only a 3 3 V power supply analog input and Hsync and COAST signals Three state CMOS outputs may be powered from 2 5 V to 3 3 V The AD9883A s on chip PLL generates a pixel clock from the Hsync input Pixel clock output frequencies range from 12 MHz to140 MHz PLL clock jitter is 500 ps p p typical at 140 MSPS When the COAST signal is presented the PLL maintains its output frequency in the absence of Hsync A sampling phase adjustment is provided Data Hsync and clock output phase relationships are maintained The AD9883A also offers full sync processing for composit
71. rcuit driver and high current output switch This series was specifically designed to be incorporated in Step Down and Step Up and Voltage Inverting applications with a minimum number of external components Refer to Application Notes AN920A D and AN954 D for additional design information Features e Operation from 3 0 V to 40 V Input Low Standby Current Current Limiting Output Switch Current to 1 5 A Output Voltage Adjustable Frequency Operation to 100 kHz Precision 2 Reference Pb Free Packages are Available PIN CONNECTIONS Switch 8 Driver Collector Collector Switch Emiter Lx Sense Bottom View Timing Y Capacitor O 00 Comparator This device contains 51 active transistors n 4 a a Input Figure 1 Representative Schematic Diagram Top View 15 32 TFT TV Service Manual 26 07 2005 MC34063A MC33063A NCV33063A MAXIMUM RATINGS Symbol Power Supply Voltage Vee Comparator Input Voltage Range Vir 0 3 to 40 Switch Collector Voltage Ve switch Switch Emitter Voltage Vpin 4 40 V Ve switch E BE E RE ve ESA E EEH EES EEE de de de de de n A W C SC C Switch Collector to Emitter Voltage VcE switch Driver Collector Voltage 40 40 40 40 Veidriver 40 00 Driver Collector Current Note 1 1 C driver Switch Current Power Dissipation and Thermal Characteristics Plastic Package P P1 Suffix Ta 25 C Thermal Resistance SOIC Package D Suffix Ta 25
72. rent Serial input output via 2 C bus Address by 3 hardware address pins Sampling rate given by 2 C bus speed 4 analog inputs programmable as single ended or differential inputs Auto incremented channel selection Analog voltage range from vss to vDD On chip track and hold circuit 34 32 TFT TV Service Manual 26 07 2005 8 bit successive approximation A D conversion Multiplying DAC with one analog output 12 23 3 Pinning SYMBOL PIN DESCRIPTION AINO 1 analog inputs A D converter AIN1 2 AIN2 3 AIN3 4 AO 5 hardware address A1 6 A2 7 Vss 8 negative supply voltage SDA 9 I C bus data input output SCL 10 IFC bus clock input OSC 1 oscillator input output EXT 12 external internal switch for oscillator input AGND 13 analog ground VREF 14 voltage reference input AOUT 15 analog output D A converter Vpop 16 positive supply voltage 12 24 PW1231 12 24 1 General Description The PW1231 is a high quality digital video signal processor that incorporates Pixelworks patented deinterlacing scaling and video enhancement algorithms The PW1231 accepts industry standard video formats and resolutions and converts the input into any desired output format The video algorithms are highly efficient providing excellent quality video The PW1231 Video SignalProcessor combines many functions into a single device including memory controller auto configuration and others This high level of integrati
73. s format conversion using multiple programmable regions Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows without user intervention Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on chip A separate memory is dedicated to storage of on screen display images and CPU general purpose use Advanced video processing techniques are supported using the internal frame buffer including motion adaptive temporal deinterlacing with film mode detection When used in combination with the new third generation scaler this advanced video processing technology delivers the highest quality video for advanced displays Both input ports support integrated DVI 1 0 content protection using standard DVI receivers A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications such as on screen programming guides When coupled with the new faster integrated microprocessor this OSD Generator supports advanced OSD animation techniques Programmable features include the user interface custom start up screen all automatic imaging features and special screen effects Video Input Computer A Ud Os play Computer Decoder Video input PW181 System Block Diagram 12 25 2 Features Third generation two dimensional filteri
74. s is the input for vertical sync Sync on Green Input This input is provided to assist with processing signals with embedded sync typically on the Green channel The pin is connected to a high speed comparator with an internally generated threshold The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak 25 VSOUT SOGOUT SERIAL PORT 2 WIRE SDA SCL AO DATA OUTPUTS RED GREEN BLUE DATA CLOCK OUTPUT DATACK INPUTS RAIN GAIN BAIN HSYNC VSYNC SOGIN 32 TFT TV Service Manual of the input signal The default voltage threshold is 150 mV When connected to an ac coupled graphics signal with embedded sync it will produce a noninverting digital output SOGOUT This is usually a composite sync signal containing both vertical and horizontal sync infor mation that must be separated before passing the horizontal sync signal to Hsync When not used this input should be left unconnected For more details on this function and how it should be configured refer to the Sync on Green section CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground It should be exercised when the reference dc level is known to be present on the analog input channels typically during the back porch of the graphics signal The CLAMP pin is enabled by setting control bit Clamp F
75. scription re ee rn 12 28 22 FEATURES SUMMARY ir 13 SERVICE MENU SETTINGS rena PO A Diga T a aa aa 13 2 13 3 deinterlacer MENU 13 4 Service menu factory reset values 14 BLOCK DIAGRAMS eee eee nenene nenene 15 CIRCUIT DIAGRAMS cece erect 32 TFT TV Service Manual 1 INTRODUCTION 32 TFT TV is a progressive TV control system with built in de interlacer and scaler It uses a 1366 768 panel with 16 9 aspect ratio The TV is capable of operation in PAL SECAM NTSC playback colour standards and multiple transmission standards as B G D K I I and L L including German and NICAM stereo Sound system output is supplying 2x8W 10 THD for stereo 80 speakers The chassis is equipped with many inputs and outputs allowing it to be used as a center of a media system It supports following peripherals 2 SCART s with all of them supporting full SCART features including RGB input 1 AV input CVBS Stereo Audio 1 SVHS iput 1 Stereo Headphone output 1 D Sub 15 PC input 1 DVI input Optional 1 Audio line out 1 Stereo audio input for PC DVI Other features include 10 pg Teletext Picture In Picture PIP Picture And Picture PAP Picture And Text PAT 2 TUNER The tuners used in the design are combined VHF UHF tuners suitable for CCIR systems B G H L L I P and D K The tuning is available through the digital
76. shows the simplified block diagram of the integrated circuit The integrated circuit comprises the following functional blocks 32 TFT TV Service Manual 26 07 2005 VIF amplifier Tuner and VIF AGC VIF AGC detector Frequency Phase Locked Loop FPLL detector VCO and divider Digital acquisition help and AFC Video demodulator and amplifier Sound carrier trap SIF amplifier SIF AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant I C bus transceivers and MAD module address Internal voltage stabilizer oder 19397 MEP mierna To Po 4 MULTI STANDARD SOUND PROCESSOR The MSP34x1G family of single chip Multistandard Sound Processors covers the sound processing of all analog TV Standards worldwide as well as the NICAM digital sound standards The full TV sound processing starting with analog sound IF signal in down to processed analog AF out is performed on a single chip These TV sound processing ICs include versions for processing the multichannel television sound MTS signal conforming to the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively Micronas Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures
77. t protection 100 electrical thermal limit burn in Pin Configurations 5 LEAD TO 220 T an 5 ON OFF 4 FEEDBACK 3 GROUND 2 OUTPUT 1 Vin Absolute Maximum Ratings Note 1 Maximum Supply Voltage 45V ON OFF Pin Input Voltage 0 3V lt V lt 40V Output Voltage to Ground Steady State 1V Power Dissipation Internally Limited Storage Temperature Range 55 C to 150 C Minimum ESD Rating C 100pF R 2 kV FB Pin 1 kv Lead Temperature soldering 10 sec 260 C Maximum Junction Temperature 150 C 12 14 DS90C385 12 14 1 General Description The DS90C385 transmitter converts 28 bits of LVCMOS LVTTL data into four LVDS Low Voltage Differential Signaling data streams A phase locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link Every cycle of the transmit clock 28 bits of input data are sampled and transmitted At a transmit clock frequency of 85 MHz 24 bits of RGB data and 3 bits of LCD timing and control data FPLINE FPFRAME DRDY are transmitted at a rate of 595 Mbps per LVDS data channel Using an 85 MHz clock the data throughput is 297 5 Mbytes sec Also available is the DS90C365 that converts 21 bits of LVCMOS LVTTL data into three LVDS Low Voltage Differential Signaling data streams Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin A Rising edge or Falling edge strobe transmitter will interop
78. t the bank A0 A11 select the row The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access The SDRAM provides for programmable READ or WRITE burst lengths of 1 2 4 or 8 locations or the full page with a burst terminate option An auto precharge function may be enabled to provide a self timed row precharge that is initiated at the end of the burst sequence The 64Mb SDRAM uses an internal pipelined architecture to achieve high speed operation This architecture is compatible with the 2n rule of prefetch architectures but it also allows the column address to be changed on every clock cycle to achieve a high speed fully random access Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high speed random access operation The 64Mb SDRAM is designed to operate in 3 3V memory systems An auto refresh mode is provided along with a power saving power down mode All inputs and outputs are LVTTL compatible SDRAMs offer substantial advances in DRAM operating performance including the ability to synchronously burst data at a high data rate with automatic column address generation the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access 37 32 TFT TV Service Manual 26 07 2005
79. tage options available that are commonly used to power the latest DSPs FPGAs and microcontrollers An adjustable option ranging from 1 22 V to 5 5 V is also available The integrated supervisory circuitry provides an active low RESET signal when the output falls out of regulation The no capacitor any capacitor feature allows the customer to tailor output transient performance as needed Therefore compared to other regulators capable of providing the same output current this family of regulators can provide a stand alone power supply solution or a post regulator for a switch mode power supply These regulators are ideal for higher current applications The family operates over a wide range of input voltages 1 8 V to 6 V and has very low dropout 170 mV at 1 A Ground current is typically 210 pA at full load and drops to less than 80 yA at no load Standby current is less than 1 pA Each regulator option is available in either a SOT223 5 TPS72501 only or DDPAK package With a low input voltage and properly heatsinked package the regulator dissipates more power and achieves higher efficiencies than similar regulators requiring 2 5 V or more minimum input voltage and higher quiescent currents These features make it a viable power supply solution for portable battery powered equipment Although an output capacitor is not required for stability transient response and output noise are improved with a 10 uF output capacitor 32 32 TFT
80. ted menu icons Video Programming System VPS decoding Wide Screen Signalling WSS decoding Pan European Cyrillic Greek Turkish and French Arabic character sets in each chip High level command interface via 1 C bus gives easy control with a low software overhead e High level command interface is backward compatible to Stand Alone Fastext And Remote Interface SAFARI 625 and 525 line display RGB interface to standard colour decoder ICs current source Versatile 8 bit open drain Input Output I O expander 5 V tolerant Single 12 MHz crystal oscillator 3 3 V supply voltage SAA5264 features Automatic detection of transmitted pages to be selected by page up and page down 8 Page fastext decoder Table Of Pages TOP decoder with Basic Top Table BTT and Additional Information Tables AlTs 4 Page user defined list mode 12 4 2 General Description The SAA5264 is a single chip ten page 625 line World System Teletext decoder with a high level command interface and is SAFARI compatible The device is designed to minimize the overall system cost due to the high level command interface offering the benefit of a low software overhead in the TV microcontroller The SAA5264 has the following functionality 10 page teletext decoder with OSD Fastext TOP default and list acquisition modes Automatic channel installation support Closed caption acquisition and display Violence Chip VChip support
81. this model initial APS By pressing 4 w button select initial APS Initial aps is selected on or off If initial aps is wanted on startup this item should be made on factory reset By pressing 4 w button select factory reset Press OK button to return to the factory setting values 44 32 TFT TV Service Manual 26 07 2005 13 3 deinterlacer menu By pressing lt gt buttons select the third icon deinterlacer menu appears on the screen e deinterlacer blank expansion off on deti om dlti 00 64 luminance peaking off on film mode off on film mode speed vof off on down for deinterlacer settings scrolling menu blank expansion By pressing 4 w button select blank expansion Blank expantion can be set to on or off by pressing lt gt button dcti Digital colour transition improvement By pressing 4 w button select deti DCTI can be adjusted between 0 and 255 by pressing lt gt button diti Digitial luma transition improvement By pressing 4 w button select diti DLTI can be adjusted between 0 and 255 by pressing lt gt button luminance peaking By pressing 4 w button select luminance peaking Luminance peaking can be set to on or off by pressing lt gt button film mode By pressing 4 w button select film mode Film mode speed can be set to on or off by pressing lt gt button JE off on off on high deint
82. ting scan input TEST2 A13 l pu do not connect reserved for future extensions and for testing scan input Al41 B1 analog input 1 TEST3 B2 0 do not connect reserved for future extensions and for testing V DD xtal B3 P supply voltage for crystal oscillator XTALI B4 I input terminal for 24 576 MHz 32 11 MHz crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal TDI B5 I pu test data input for boundary scan test note 2 TCK B6 I pu test clock for boundary scan test note 2 XDQ B7 1 0 data qualifier for expansion port XPD1 B8 1 0 MSB 6 of expansion port data XPD3 B9 1 0 MSB 4 of expansion port data XPD5 B10 1 0 MSB 2 of expansion port data XTRI B11 I X port output control signal affects all X port pins XPD7 to XPDO XRH XRV XDQ and XCLK enable and active polarity is under software control bits XPE in subaddress 83H TEST4 B12 O do not connect reserved for future extensions and for testing scan output TEST5 B13 NC do not connect reserved for future extensions and for testing B14 NC do not connect reserved for future extensions and for testing 6 VSSA4 C1 P ground for analog inputs Al4x AGND C2 P analog ground TEST C3 NC do not connect reserved for future extensions and for testing TEST8 C4 NC do not connect reserved for future extensions and for testing VDDD1 C5 P digital supply voltage 1 peripheral cells TRST C6 I pu test reset input active LOW for b
83. ts 8 or 16 bit wide output data with auxiliary reference data for interfacing to VGA controllers The target application for the SAA7118E is to capture and scale video images to be provided as digital video stream through the image port of a VGA controller for capture to system memory or just to provide digital baseband video to any picture improvement processing 12 20 2 Features Video acquisition clock Up to sixteen analog CVBS split as desired all of the CVBS inputs optionally can be used to convert e g Vestigial Side Band VSB signals Up to eight analog Y C inputs split as desired Up to four analog component inputs with embedded or separate sync split as desired e Four on chip anti aliasing filters in front of the Analog to Digital Converters ADCs e Automatic Clamp Control ACC for CVBS Y and C or VSB and component signals Switchable white peak control Four 9 bit low noise CMOS ADCs running at twice the oversampling rate 27 MHz Fully programmable static gain or Automatic Gain Control AGC matching to the particular signal properties On chip line locked clock generation in accordance with ITU 601 Requires only one crystal 32 11 or 24 576 MHz for all standards Horizontal and vertical sync detection Video decoder Digital PLL for synchronization and clock generation from all standards and non standard video sources e g consumer grade VTR e Automatic detection of any supported colo
84. unction to 1 register OFH Bit 7 default is 0 When disabled this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the Hsync input The logic sense of this pin is controlled by Clamp Polarity register OFH Bit 6 When not used this pin must be grounded and Clamp Function programmed to 0 COAST Clock Generator Coast Input Optional This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval The COAST signal is generally not required for PC generated signals The logic sense of this pin is controlled by Coast Polarity register OFH Bit 3 When not used this pin may be grounded and Coast Polarity programmed to 1 or tied HIGH to VD through a 10 k resistor and Coast Polarity programmed to 0 Coast Polarity defaults to 1 at power up REF BYPASS Internal Reference BYPASS Bypass for the internal 1 25 V band gap reference It should be connected to ground through a 0 1 uF capacitor The absolute accuracy of this reference is 4 and the temperature coefficient is 50 ppm which is adequate for most AD9883A applications If higher accuracy is required an external reference may be employed instead MIDSCV Midscale Voltage Reference BYPASS Bypass for th
85. ur standard e Luminance and chrominance signal processing for PAL B G D H and N combination PAL N PAL M NTSC M NTSC Japan NTSC 4 43 and SECAM e Adaptive 2 4 line comb filter for two dimensional chrominance luminance separation also with VTR signals Increased luminance and chrominance bandwidth for all PAL and NTSC standards Reduced cross colour and cross luminance artefacts PAL delay line for correcting PAL phase errors Brightness Contrast Saturation BCS adjustment separately for composite and baseband signals User programmable sharpness control e Detection of copy protected signals according to the macrovision standard indicating level of protection Independent gain and offset adjustment for raw data path Component video processing 27 32 TFT TV Service Manual 26 07 2005 RGB component inputs e Y Pg Pr component inputs Fast blanking between CVBS and synchronous component inputs Digital RGB to Y Cg Cr matrix Video scaler e Horizontal and vertical downscaling and upscaling to randomly sized windows Horizontal and vertical scaling range variable zoom to 1 64 icon note H and V zoom are restricted by the transfer data rates Anti alias and accumulating filter for horizontal scaling Vertical scaling with linear phase interpolation and accumulating filter for anti aliasing 6 bit phase accuracy Horizontal phase correct up and downscaling for improved signal quality of scaled
86. y and duration of this output can be pro grammed via serial bus registers By maintaining alignment with DATACK and Data data timing with respect to horizontal sync can always be determined Vertical Sync Output A reconstructed and phase aligned version of the video Vsync The polarity of this output can be controlled via a serial bus bit The placement and duration in all modes is set by the graphics transmitter Sync On Green Slicer Output This pin outputs either the signal from the Sync on Green slicer comparator or an unprocessed but delayed version of the Hsync input See the Sync Processing Block Diagram Figure 12 to view how this pin is connected Note Besides slicing off SOG the output from this pin gets no other additional processing on the AD9883A Vsync separation is performed via the sync separator Serial Port Data I O Serial Port Data Clock Serial Port Address Input 1 For a full description of the 2 wire serial register and how it works refer to the 2 Wire Serial Control Port section Data Output Red Channel Data Output Green Channel Data Output Blue Channel The main data outputs Bit 7 is the MSB The delay from pixel sampling time to output is fixed When the sampling time is changed by adjusting the PHASE register the output timing is shifted as well The DATACK and HSOUT outputs are also moved so the timing relationship among the signals is maintained For exact timing information refer to Figures 7 8

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32” TFT TV SERVICE MANUAL - Page de test