February 6, 2006 Rev 060206 User's Manual
Contents
1. 6 2 EIS aaa 6 2 2 ALOT E a 6 2 3 Characteristics and 7 3 0 Camera Configuration and Control 8 RR 0 4 LVDS Camera 9 4 2 Power and IO ConnectforS eren nennt tenerse rera 12 4 2 1 Power Connector for OEM Board Set 12 4 2 2 Connector for OEM Board Set 13 4 2 3 Power Connector for Boxed Unlt 13 4 2 4 Connector for Boxed Unlt a ennemi 14 HANE 15 5 1 GPIO Control Block 15 3 2 GPIO PTOS anane u a aaa aaa a 17 5 3 Camera Interface a 18 C pi ccm 15 53 2 Cam ri u l u 18 5 3 3 Pixel Bus Deflntition 18 6 0 Mechanical Dimensions2. N EGT Pleora Technologies User s Manual The iPORT PT1000 LV IP Engine February 6 2006 Rev 060206 Pleora Technologies Inc 359 Terry Fox Drive Suite 230 Kanata Ontario Canada K2K 2E7 Tel 613 270 0625 www pleora com sui Pleora Technologies These products are not intended for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Pleora Technologies Inc Pleora customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Pleora for any damages resulting from such improper use or sale O 2004 2006 Pleora Technologies Inc All information provided in this manual 1s believed to be accurate and reliable No responsibility 15 assumed by Pleora for its use Pleora reserves the right to make changes to this information without notice Redistribution of this manual in whole or in part by any means 15 prohibited without obtaining prior permission from Pleora Copyright 2004 2006 Pleora Technologies Inc Page 2 Rev 060206 Pleora Technologies Table of Contents EO TAGS UO RENTRER 5 1 1 The Scope of this User s Manual a 5 1 2 Related Documents a 5 2 0 Overview of the IPORT PT1000 LV
3. 2 12 2 lt lt 2 E 5 5 s S TE 5 0 o timers nput Debouncing lt D o gt 5 on oftware Controlled IO lt D o 2 1 x RS232 Cam Note 6 1 x RS232 GPIO Min 4 5 V Typ 5 V Max 16 V Serial Ports UART PT1000 LV Supply Voltage Power Consumption measured at 10V EIA 644 Typ 3 1 W Max 3 1 W RS 422 Typ 3 0 W Max 3 0W Max 70 C Max 125 C x xx Available since firmware version x xx NA Not applicable All features supported by iPORT S W 2 2 0 1 RGB supported as single tap 24 bits 6 Single UART available multiplexed via SDK Operating Temperature Storage Temperature Notes Video Input 644 Std RS 422 Opt Grayscale Bayer RGB Pixel Depth bits 8 10 12 14 16 24 Min 1 MHz Min 4 Default 640 Max 16 380 Min 1 Default 480 Max 16 383 Windowing Yes Others Yes Yes 3 14 PT1000 LV Data Output Formats Image Width pixels must be multiple of 4 Image Height pixels Table 11 iPORT PT1000 LV Characteristics and Features Copyright 2004 2006 Pleora Technologies Inc Page 26 Rev 060206 ui Pleora Technologies 8 2 GPIO Control Block TTL IN O S D ld TTL OUT O TTL ING a TTL_OUTI1 Q 2 LUT Q 2 OPT_IN S D FVAL CC4 LVAL CC2
4. 20 6 1 Mechanical Drawings of OEM Board Set 20 6 2 Mechanical Drawings of Boxed Untlt 22 uuu nan gaga gan 24 7 1 Ro 8 08 24 80 Appendix Legacy Modekls 25 8 1 Characteristics and Features a nn nasse narras 26 8 2 GPIO Control Block a nnnes 27 Copyright 2004 2006 Pleora Technologies Inc Page 3 Rev 060206 Pleora Technologies Pigure L LVDS Camera C OBDEDIOE Figure 2 Power and IO Connector Locations for OEM Board Set Figure 3 Power Connector for Boxed Unl t Pigure 4 IO Connector for Boxed Unit u uuu owe zx Rer Ege dee Figure 5 IPORT PT1000 LV V2 GPIO Control Block Figure 6 Isometric View of the OEM Board Figure 7 Side View of the OEM Board Set Figure 8 Top View of the OEM Board Set Figure 9 Front View of the Boxed Uni Figure 10 Rear View of the Bo
5. ui Pleora Technologies 7 0 Additional Support Additional support can be obtained by contacting Applications Support at Pleora Technologies Inc at 613 270 0625 or by sending an email to support pleora com 7 1 Revision History Rei Dae Den _ 2 1 3 November 2004 Updated GPIO diagram Modified text to reflect IPORT Software 2 1 3 060206 February 2006 Modified text to reflect PORT Software V2 2 0 Added Characteristics and Features table Added pixel bus definition Reordered sections Updated formatting to comply with new Pleora template Added Revision History table Created Appendix for legacy models Copyright 2004 2006 Pleora Technologies Inc Page 24 Rev 060206 ui Pleora Technologies 8 0 Appendix Legacy Models This appendix 15 a brief overview of the features and GPIO block in the first generation version of the PT1000 LV IP Engine known simply as the IPOR T PT1000 LV This model is not available to new customers and 15 no longer being upgraded with new features Table 11 lists its key characteristics and features and Figure 13 shows its GPIO Control Block Copyright 2004 2006 Pleora Technologies Inc Page 25 Rev 060206 Pleora Technologies 8 1 Characteristics and Features Available as Available as Boxed 16 MB Std 64 MB Opt 128 MB Opt Onboard Memory Inputs Outputs TTL Inputs TTL Outputs 4 x LVDS Programmable Logic Control
6. 26 27 28 29 30 31 32 33 Table 2 Camera Connector Pin Out Copyright 2004 2006 Pleora Technologies Inc Page 10 Rev 060206 ui Pleora Technologies DATA 23 0 IN LVDS Data In When interfacing to 2 tap cameras please refer to Table 10 for the Pixel Bus Definition A 11 0 is for the first tap B 11 0 is for the second DATA 19 16 are input signals when configured as inputs They are not available when the GC 3 0 GPIO CTRL signals are used as outputs Refer to the GC 3 0 signal entry in this table for details on how to use them as outputs FVAL IN LVDS Frame Valid Polarity high or low and mode level or edge can be programmed via the SDK LVAL IN LVDS Line Valid Polarity high or low and mode level or edge can be programmed via the SDK DVAL IN LVDS Data Valid Polarity high or low and mode level or edge can be programmed via the SDK IN LVDS Clock In Data and control signals are latched on rising edge Max 66 MHz CLK IN LVDS Camera Control These outputs come from the Look Up Table Q 7 4 in the CC 4 1 OUT GPIO Control Block The Look Up Table is programmable via a dialog in the SDK GC 3 0 OUT LVDS GPIO Control These outputs come from the GPIO_CTRL 3 0 register in the GPIO Control Block They can be individually set and cleared via a dialog in the SDK GC 3 0 are only available if the DATA 19 16 signals are not used as inputs RS232 TXO RS 232 Transmit signal from the internal UA
7. CPU capacity The iPORT SDK gives users the building blocks needed to quickly and easily enable third party or custom video applications For more information about the iPORT Connectivity Solution see User s Manual Shared Features of iPORT IP Engines 2 2 Models The standard model of the iPORT PT1000 LV IP Engine 15 known as the IPOR T PT1000 LV V2 It is available in two variants each of which has its own order code The LV644 variant which accepts the signaling levels defined in the TIA EIA 644 interface standard 1 e traditional LVDS signaling on its LVDS camera connector and The RS422 variant which accepts the signaling levels defined in TIA EIA 422 B RS 422 interface standard on its LVDS camera connector Aside from camera connector signaling levels these variants are exactly the same Note Information about the first generation version of the IPORT PT1000 LV known simply as the iPORT PT1000 LV is described in the Appendix This model is not available to new customers and 15 no longer being upgraded with new features Copyright 2004 2006 Pleora Technologies Inc Page 6 Rev 060206 ui Pleora Technologies 2 3 Characteristics and Features Table 1 lists key characteristics and features of the iPORT PT1000 LV V2 Hardware Available as OEM Available as Boxed 16 MB Std 64 MB Opt 128 MB Opt Pulse Generators timers Rescaler 16 bit Delayers Onboard Memory General Purpos
8. Development Kit Copyright 2004 2006 Pleora Technologies Inc Page 18 Rev 060206 Pleora Technologies Port AO Port Port 2 Port Port A4 Port 5 Port A6 Port A7 Port BO Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port CO Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Signa PixelBus 8 bit 10 bit 12 bit Loewe m Lowe NO we 9 owmen wc 9 AO 2 4 5 A6 AT 14 bit AO A1 A2 A3 A4 A5 A6 AT A8 A9 Table 10 Grabber Interface Pixel Bus Definition Copyright 2004 2006 Pleora Technologies Inc Rev 060206 16 bit AO A1 A2 A3 A4 A5 A6 AT A8 A9 RGB RO R1 R2 R3 R4 R5 R6 R6 GO G1 G2 G3 G4 G5 G6 G7 BO B1 B2 B3 B4 B5 B6 B7 Page 19 ui Pleora Technologies 6 0 Mechanical Dimensions This section provides mechanical drawings and measurements of the boxed and OEM versions of the IPORT PT1000 LV V2 IP Engine The measurements are in inches unless otherwise noted The measurements have the following tolerances depending on the number of significant digits provided X 0 1 XX 0 01 0 005 6 1 Mechanical Drawings of OEM Board Set Figure 6 to Figure 8 are mechanical drawings of the iPORT PT1000 LV V2 OEM board set The main board and daughter board are both 0 063 inches thick The maximum seconda
9. V2 panels in the dialog are auto generated by the SDK based on the engine s firmware version and model This is explained in more detail in the Camera Configuration Dialog section of the User s Manual Shared Features of IPOR T IP Engines The application is equipped with camera modules for a range of different LVDS models Check the list in the Select Camera Dialog of the Camera Library Controls If a camera module is available for your LVDS model then the Camera Configuration Dialog will auto generate a panel to control your camera Internally the camera module converts the controls of that panel to the actual serial port command of the camera If no camera specific module exists for your LVDS model then you must select the standard LVDS camera module instead In this case you have to find the camera s serial port command information in the camera documentation and type it in the Port Communication Panel For more information read the User s Manual Shared Features of iPORT IP Engines and the CyDeviceExtensionConstants h file in the Reference Guide C software Development Kit Copyright 2004 2006 Pleora Technologies Inc Page 8 Rev 060206 ui Pleora Technologies 4 0 Connectors This section describes the LVDS camera connector and the power and IO connectors on the iPORT PT1000 LV V2 The Ethernet connector 15 a standard RJ 45 plug 4 1 LVDS Camera Connector The OEM and boxed versions
10. of IPOR T IP Engines for more details Refer to camera documentation for information on the polarity and type of the signals required to support specific camera models 5 3 2 Camera Controls The iPORT PT1000 LV V2 can send commands to cameras through the Camera Control signals For information on the availability and function of camera controls refer to camera documentation The labels of the control outputs to the camera in the GPIO Control Block programming language are 04 for Camera Control 1 CC1 Q5 for Camera Control 2 CC2 Q6 for Camera Control 3 CC3 Q7 for Camera Control 4 5 3 3 Pixel Bus Definition Table 10 shows the pixel bus definition for the grabber interface including all the configurations supported Note that when interfacing to 2 tap cameras A 11 0 15 for the first tap and B 11 0 15 for the second O O 0 The grabber input should be configured to match the camera head pixel bus using the CY GRABBER PARAM PIXEL DEPTH and CY GRABBER PARAM TAP QUANTITY parameters of the CyGrabber class in the SDK For the RGB configuration the grabber should be set to tap and 24 bits The grabber output can reformat the data using the CY GRABBER PARAM NORMALIZED and CY GRABBER PARAM PACKED parameters of the CyGrabber class The structure of the resulting buffer 1s described in the Derived Pixel Type Classes of the Imaging Library section of the Reference Manual IPOR T C Software
11. of the PT1000 LV V2 IP engine both use the same LVDS connector the Hirose 68 pin female MDR shown in Figure 1 The part number is DX10GM 68SE The part number for the mating cable is DX30AM 68P and for the shell is DX30M 68 CV Table 2 shows how the 68 pins on the connector map to signals and Table 3 describes the function of each type of signal Mark display V 2 6 0 45 Figure 1 LVDS Camera Connector Copyright 2004 2006 Pleora Technologies Inc Page 9 Rev 060206 ui Pleora Technologies Signal Name wo Signal Name I O DATA 0 OoN 3 DATA 16 GC 0 IN OUT DATA 0 DATA 17 GC 1 IN OUT DATA 14 oN 3 DATA 17 GC 1 IN OUT DATA 1 in 3 DATA 18 GC 24 IN OUT DATA 24 oN 40 DATA 18 GC 2 IN OUT DATA 2 OoN 4 DATA 19 GC 3 IN OUT DATA 34 No 42 DATA 19 GC 3 IN OUT Comae n omae ata Lower W Lower Pt Far NN _ Lomas N _ omes mw omm m s we mM _ omes mw Dar m Comano con o cn s own o oe oa oara Comas omen m c oa 1 7 10 11 12 19 14 15 16 17 18 19 20 21 22 23 24 we N _ omm Nf or MN
12. DUVAL I CC3 SPARE Q 7 DATA 23 CC4 GPIO_CTRLIO pos GPIO FVAL GPIO_CTRL 1 E Q 13 Ni GPIO CTRL 2 9 8 Pulser PG OUT 0 8 gt 3 Pulse 66 PG LUT Q 2 c QI17 0 OPT OUT D 4 B Q 17 16 11 10 9 8 7 3 c 8 1 input Rescaler OUT 0 gt RSL OUT 0 0 P Mult 12 bit PG OUT 1 Y Q 17 16 11 10 9 8 7 3 8 1 input PG OUT 3 0 RSL OUT Delayer DEL OUT 5 1 reference x RSL OUT Q 15 niemi 6 CNT 31 0 ti Interrupt TIME 31 0 DEL OUT ONTBtO time EFO 31 0 LL LI 7 0 mask 1 MASK 7 0 GP CNT EQ General GP CNT 31 0 GP CNT GT P d a aUe up Purpose GP CNT EQ TS TRIG 0 down Counter CNT GT TS TRIG 1 GP CNTI31 0 34 Timestamp Trigger TRIG 3 0 TS TRIG 2 TS 10 gt Generator TS TRIG 3 Q 17 16 11 10 9 8 7 3 Counter TS_CNT 31 0 8 1 set Interrupt Frame Timestamp Source Selection Synchronization Block CNT 31 0 GPIO CNT S D Synchronization and Debouncing Block CNT 91 0 Figure 13 IPORT PT1000 LV GPIO Control Block Copyright 2004 2006 Pleora Technologies Inc Page 27 Rev 060206 sui Pleora Technologies Copyright 2004 2006 Pleora Technologies Inc Page 28 Rev 060206
13. PIO IRQ D GPIO_CNT 31 0 Nterrupt TIME 31 0 DEL OUT ONIBtO time FO 31 0 LL LI 7 0 mask MASK 7 0 GP CNT EQ Q 17 16 11 10 9 8 7 3 General 0 GP CNT GT 8 1 clear E I a up Purpose GP_CNT_EQ TS_TRIG O down Counter TS_TRIG 1 cNT31 gt Timestamp Trigger TS TRIG 3 0 TS TRIG 2 31 0 Generator TS TRIG 3 Q 17 16 11 10 9 8 7 3 dear imestam Q 17 16 11 10 9 8 7 3 gt IS CNT 31 0 1 set Interrupt and Frame Timestamp Source Selection S Synchronization Block GP CNT 31 0 GPIO CNT S D Synchronization and Debouncing Block TS CNT 31 0 31 0 Figure 5 iPORT PT1000 LV V2 GPIO Control Block Copyright 2004 2006 Pleora Technologies Inc Page 16 Rev 060206 ui Pleora Technologies 5 2 GPIO Programming Signals Table 8 lists the input programming signals that are specific to the IPORT PT1000 LV V2 The labels for these signals in the GPIO Look Up Table depend on the configuration of the GPIO Look Up Table dialog in the iPORT SDK See the User s Manual Shared Features of IPORT IP Engines for details about other GPIO programming signals used by the engine Table 9 lists the output programming signals that are specific to the iPORT PT1000 LV V2 as well as the GPIO labels for these signals in the GPIO Look Up Table Input Signal Description FVAL Frame Valid signal Refer to camera documentation to find out how sp
14. RTO RS232 RXO RS 232 Receive signal to the internal UARTO Table 3 LVDS Signal Description Copyright 2004 2006 Pleora Technologies Inc Page 11 Rev 060206 ui Pleora Technologies 4 2 Power and IO Connectors 4 2 1 Power Connector for OEM Board Set The PT1000 LV V2 OEM board set accepts power supply voltages of from 4 5 V to 16 V regulated The connector shown as J2 on the left hand side of Figure 2 is a Molex 4 pin 6373 Series 22 23 2041 The part mates with the Molex 4 pin shell 22 01 3047 and the Molex crimp pin 08 55 0102 Table 4 lists the four pins in this connector and describes the function of each Ethernet Table 4 Power Connector Pin Out for OEM Board Set Copyright 2004 2006 Pleora Technologies Inc Page 12 Rev 060206 ui Pleora Technologies 4 2 2 IO Connector for OEM Board Set The IO connector for the IPORT PT1000 LV V2 OEM board set 15 a 16 pin Samtec 2 mm male header TMM 108 01 G D SM The mating connectors are in the Samtec MMS 108 02 xx xx series The mating flat cables are in the Samtec TCSD series TCSD 08 xxxxxxx The IO connector 15 shown as J12 on the right hand side of Figure 2 Table 5 lists the 16 pins in the connector and describes the function of each Signainame Beh _ 5 s mm mma s s s s 3 3 V at 250 mA max Table 5 Connector Pin Out for OEM Board Set 4 2 3 Power Connect
15. a few minor differences which are described in this section 5 1 GPIO Control Block The Programmable Logic Controller PLC in the PT1000 LV V2 routes signals through a sophisticated GPIO Control Block Figure 5 shows the GPIO Control Block for the iPORT PT1000 LV V2 For further details on how the engines handle IO signals see the User s Manual Shared Features of iPORT IP Engines Copyright 2004 2006 Pleora Technologies Inc Page 15 Rev 060206 Pleora Technologies TTL_IN D _IN 0 5 TTL TTL IN 1 5 5 H gt Q 1 INE TTL_OUT 1 Q 2 LUT Q 2 Q 3 OPT IN S D OPT OUT FVAL 5 LVAL B s Q 5 a 2 DVAL B s Q 6 SPARE Mies DATA 23 Q 12 1 Q 13 GPIO CTRL 1 GPIO LVAL Q 14 GPIO CTRL 2 CTRL 3 QI9 _ Pulser_Gen0 PG_OUTI0 Q 8 8 Pulse Geni gt PG LUT Q 2 us 22 gt Pulse Gen2 EE PG OUT 2 OPT OUT e Q 10 D 8 Pulse Gen3 PG OUT 3 B Q 17 16 11 10 9 8 7 3 NJ PUL Rescaler PG RSL OUT PG OUT 3 0 lt rack Mult 16 bit PG_OUT 1 Q 17 16 11 10 9 8 7 3 NJ PG_OUT 2 8 1 input Delayer gt DEL OUT x PG OUT 3 MM 5 1 reference a RSL_OUT 5 p interrupt G
16. e Counters nput Debouncing Software Controlled IO GPIO Interrupts FIFO 1 x RS232 Cam Note 6 1 x RS232 GPIO Min 4 5 V Typ 5V Max 16V Serial Ports UART PT1000 LV V2 Supply Voltage Power Consumption measured at 10V EIA 644 Typ 3 1 W Max 3 1 W RS 422 Typ 3 0 W Max 3 0 W Min 0 C Max 70 C Min 40 C Max 125 C Notes x xx Available since firmware version x xx NA Not applicable All features supported by iPORT S W 2 2 0 1 RGB supported as single tap 24 bits 4 NRE or other charges may apply Contact Pleora 6 Single UART available multiplexed via SDK Frame Grabber Ethernet Bandwidth 1 Gb s Yes Multicast Yes tatic Configuration Yes 4 01 BOOTP Yes DHCP Yes 4 06 Number of Data Channels Video Sources per Data Channel Up to 3 Video Input 644 Std RS 422 Opt PT1000 LV V2 Data Output Bayer Formats RGB Pixel Depth bits 8 10 12 14 16 24 I Min 1 MHz Min 4 Default 640 Max 16 380 Min 1 Default 480 Max 16 383 Image Width pixels must be multiple of 4 Image Height pixels Table 1 iPORT PT1000 LV V2 Characteristics and Features Copyright 2004 2006 Pleora Technologies Inc Page 7 Rev 060206 ui Pleora Technologies 3 0 Camera Configuration and Control Both the PT1000 LV V2 and the camera to which it 1s attached are configured by the Camera Configuration Dialog of the iPORT SDK The PT1000 LV
17. ecific cameras handle this signal LVAL Line Valid signal Refer to camera documentation to find out how specific cameras handle this signal DVAL Data Valid signal Refer to camera documentation to find out how specific cameras handle this signal SPARE DATA 23 Spare signal Data In bit 23 Can be used as either a camera control in signal or a data in bit Refer to camera documentation to find out how specific cameras handle this signal Table 8 iPORT PT1000 LV V2 GPIO Input Signals krv mamaxa cora mo _ _ 1 4 Camera control 1 Refer to camera documentation to find out how specific cameras handle this signal CC2 Q5 Camera control 2 Refer to camera documentation to find out how specific cameras handle this signal CC3 Camera control 3 Refer to camera documentation to find out how specific cameras handle this signal CC4 Q7 Camera control 4 Refer to camera documentation to find out how specific cameras handle this signal Table 9 iPORT PT1000 LV V2 GPIO Output Signals Copyright 2004 2006 Pleora Technologies Inc Page 17 Rev 060206 ui Pleora Technologies 5 3 Camera Interface 5 3 Camera Inputs Most LVDS cameras have three standard signals frame valid FVAL line valid LVAL and data valid DVAL FVAL and LVAL can be activated by positive or negative signal edges or by high or low levels DVAL can be activated by high or low levels See the User s Manual Shared Features
18. or for Boxed Unit The boxed version of the IPORT PT1000 LV V2 uses a Hirose 6 pin power connector as shown in Figure 3 The part number for this connector is HR10A 7R 6P its mating part number is HR10A 7P 65 Table 6 lists the six pins in the connector and describes the function of each v 8 Figure 3 Power Connector for Boxed Unit These VCC supplies are not recommended for analog circuitry Analog circuitry should be driven from a separate 3 3 V supply Copyright 2004 2006 Pleora Technologies Inc Page 13 Rev 060206 Pleora Technologies Pin Deseription ____ VIN 4 5 V to 16 V regulated VIN 4 5 V to 16 V regulated VIN 4 5 V to 16 V regulated s ewe Table 6 Power Connector Pin Out for Boxed Unit 4 2 4 IO Connector for Boxed Unit The boxed version of the PT1000 LV V2 uses a Hirose 12 pin connector as shown in Figure 4 The part number for this connector is HRIOA 10R 12S the mating part number is HR10A 10P 12P Table 7 lists the 12 pins in the connector and describes the function of each Figure 4 Connector for Boxed Unit Pin Signainame 7 I Table 7 Connector Pin Out for Boxed Unit Copyright 2004 2006 Pleora Technologies Inc Page 14 Rev 060206 ui Pleora Technologies 5 0 Signal Handling The 1PORT PT1000 LV V2 handles the signals in much the same way as other IPOR T IP engine models There are
19. ore set of features offered in all iPORT IP Engines plus a connector and extended functions tailored specifically for LVDS cameras The engine interfaces to a range of LVDS cameras including both 1 tap and 2 tap models The PT1000 LV streams up to Gb s of imaging data to PCs in real time over either point to point Gigabit Ethernet GigE links or standard GigE LANs A built in frame grabber removes horizontal and vertical blank times which helps maximize bandwidth usage In the GigE connection The PT1000 LV also handles control signals from the PC and other system elements These signals are routed through a PLC programmable logic controller that allows users to precisely measure and control the operation of conveyors encoders cameras and other components either independently from or in conjunction with the host PC on the network LVDS cameras do not have a standard cable pin out As a result a custom cable may be required to ensure that signals from the camera feed into the correct inputs on the IPOR T PT1000 LV IP Engine Refer to Section 4 1 of this manual which describes the LVDS camera connector for further details As one element of Pleora s end to end iPORT Connectivity Solution the PT1000 LV 15 shipped with two powerful PC applications The iPORT IP Device Driver users can choose from two versions the iPORT High Performance IP Device Driver or the iPORT Universal IP Filter Driver streams data to PC memory using minimal
20. ry component height on both boards 1s 0 08 inches unless otherwise specified in the drawings CYIBI2AI DAUGHTER BOARD CYIBO4BI MAIN BOARD ISOMETRIC VIEW Figure 6 Isometric View of the OEM Board Set Copyright 2004 2006 Pleora Technologies Inc Page 20 Rev 060206 Pleora Technologies INA HEADER Y IBI2AI PRIMARY SIDE PULSE 0x8 HEADER MDR 68 PIN JK0654219 MINI D A IHi 368 54 ke EX MAIN BOARD Tmm SECONDARY SIDE SIDE VIEW BOARD TO BOARD Figure 7 Side View of the OEM Board Set 20 9 015 2 PLACES 002 6 PLACES 302 OT 1 455 2 996 PLATED HOLES 2902 TOP VIEW Figure 8 Top View of the OEM Board Set Copyright 2004 2006 Pleora Technologies Inc Page 21 Rev 060206 Pleora Technologies 6 2 Mechanical Drawings of Boxed Unit The drawings in Figure 9 to Figure 12 show views the boxed version of the IP engine The enclosure Is made from anodized aluminum and provides four mounting holes The mounting hole diameter and slot width are both 0 17 0 01 inches FRONT VIEW Figure 9 Front View of the Boxed Unit REAR VIEW Figure 10 Rear View of the Boxed Unit Copyright 2004 2006 Pleora Technologies Inc Page 22 Rev 060206 nmm Pleora Technologies SIDE VIEW Figure 11 Side View of the Boxed Unit TOP VIEW Figure 12 Top View of the Boxed Unit Copyright 2004 2006 Pleora Technologies Inc Page 23 Rev 060206
21. s one for each form factor of the engine 1 2 Related Documents The PT1000 LV IP Engine is a member of Pleora s growing family of iPORT IP Engines For information about other available engine models visit www pleora com AII the engines share one set of core features described in a document entitled User s Manual Shared Features of iPORT IP Engines The PT1000 LV IP Engine is one element of the iPORT Connectivity Solution As such it 15 shipped with two PC applications the iPORT IP Device Driver and the IPOR T Software Development Kit SDK available in C or Visual Basic These software applications have their own documentation The Connectivity Solution also includes the PORT High Memory Manager which is described in the iPORT IP Device Drivers manual As an option the solution can also include IPOR T Hydra PC Communications Software described in the SDK C manual In summary this User s Manual complements and should be used in conjunction with up to four other documents User s Manual Shared Features of IPOR T IP Engines User s Manual IPORT IP Device Drivers Reference Manual The IPORT C Software Development Kit and Reference Manual The iPORT Visual Basic Software Development Kit Copyright 2004 2006 Pleora Technologies Inc Page 5 Rev 060206 ui Pleora Technologies 2 0 Overview of the iPORT PT1000 LV 2 1 Highlights The iPORT PT1000 LV delivers the c
22. xed Unit Figure 11 Side View of the Boxed Unit Figure 12 Top View of the Boxed Unit Figure 13 IPORT PT1000 LV GPIO Control Block Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 List of Figures List of Tables PT1000 LV V2 Characteristics and Features Camera Connector Pin Outl IV DS Signal u uuu uu Power Connector Pin Out for OEM Board 5 IO Connector Pin Out for OEM Board 5 Power Connector Pin Out for Boxed Unlt IO Connector Pin Out for Boxed Unlt IPORT PT1000 LV V2 GPIO Input Signals IPORT PT1000 LV V2 GPIO Output Signals Table 10 Grabber Interface Pixel Bus Definition Table 11 1 PT1000 LV Characteristics and Features Copyright 2004 2006 Pleora Technologies Inc Rev 060206 Page 4 ui Pleora Technologies 1 0 Introduction 1 1 The Scope of this User s Manual This User s Manual describes how to access and use features specific to Pleora s IPORT PT1000 LV IP Engine The engine 15 available as both a boxed unit and an OEM board set Therefore some of the descriptions in the manual particularly those dealing with physical aspects have two section
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