USER'S MANUAL
Contents
1. 18 Reset Register TT 19 Interrupt Status Clear Digital VO Sua TAA KISA 19 Data Input Output Registers 20 Direction Control Register 21 Interrupt Enable Registers 21 Interrupt Type Configuration Registers 22 Interrupt Polarity Registers 22 Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 3 DMA REGISTERS eee nene 23 DMA Control Register KATAA SASA 23 TABLE OF DMA Transfer Size Registers E 23 STATIC RAM MEMORY mH n 23 CONTENTS PCI9056 REGISTERS Tudu usa te dere 23 PCI9056 USERo CLOCK CONTROL E TT 24 4 0 THEORY OF OPERATION PCI INTERFACE LOGIC 25 NOT USED PCI9056 FUNCTIONS 25 LVDS INPUT OUTPUT LOGIC ses 26 SYNCHRONOUS SRAM nme 26 SERIAL EEPROM 1er eren 27 CLOCK CONTROL eene 27 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 28 PRELIMINARY SERVICE PROCEDURE 28 WHERE TO GET HELP eee 28 6 0 SPECIFICATIONS PHYSICAL ette EDI 29 ENVIRONMENTAL een HH 29 LVDS INPUT OUTPUT ueteris Dee cn ds 31 PCI LOCAL BUS INTERFACE EE 31 APPENDIX C2. Cable connector The board I O is accessed via a 68 pin SCSI front panel connector SIGNAL INTERFACE PRODUCT A cable is available to interface with this board OD SIS Model 5028 432 A 2 meter round 68 conductor shielded cable with a See the Appendix for male SCSI 3 connector at both ends and 34 twisted pairs The cable is further information on these used for connecting the board to a SCSI 3 destination For optimum products performance use the shortest possible length of shielded cable Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board ENGINEERING DESIGN KIT BOARD DLL CONTROL SOFTWARE BOARD VxWORKS SOFTWARE BOARD QNX SOFTWARE Acromag provides an engineering design kit for the DX boards sold separately a must buy for first time DX module purchasers The design kit model PMC DX EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The DX modules are intended for users fluent in the use of Xilinx FPGA design tools Acromag provides a software product sold separately to facilitate the development of Windows 98 Me 2000 XPG applications accessing Acromag PMC I O board products PCI I O Cards and Comp
3. C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com LVDS I O Reconfigurable Board 3 3 966 10Grv SH3AIHG 99019 MIAS MOT NVSSVIO 49018 32012 lt M3X3ldlblQW 2010 GALVYANAD sna 1v201 39019 WOd II XALUIA 990619d Dl lt WNONd33 1VIuas NOILVYNDIANOO ISOTA A 9S0610d ZHWee dE 01901 Ld HS3LLNI WOSdd3 1Vvld3s 55015 WE ID 1V1SAHO L ANY 0 HO YNG P p 21901 10H1NOO 39010 v9d4 ZHW 99 dIHO Lig ze FOVAYSLNI SN 10d 1VN9IS IONLNOOD YSN 9S0610d ouasn 3AV1S H31S VW 30VdH31NI 906199 sna 19d Ag e sna 1v9012 c 1901 1081N OTHO NOS 91901 39 V3H3 NI sng 1v901 9S0619d ado hi SWYO 004 0 13NNVHO gt J20 SIE JOE NOLO STANNVHO 0 TANNVHO ILNdINO LNdNI 1I8 8 X WZ II XSLUIA od AYOWAW NOILVENDISNOO e HSY ce 3 c 91901 gt gt LANYYALNI LAdLNO LAdNI 1VLIOIG n suluo 004 o L TANNVHO fo gt 72 9 X 9Sc 1OHINOO NOILO3HIG WVYS SNONOYHONAS 31901 LE TANNWHO ed s 39VJ3H31NI Nas 39VdH31NI eo On o N VOd4 Il X31ulA gt Q st O LO gt Q Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www
4. 1 Register Flash Status 2 Register Flash Status 1 Read Only PCIBAR2 2000H This read only register is used to read the DQ5 and DQ3 status of the flash chip A Flash Status 1 register is at base address plus 2000H Bits FUNCTION Not Used bits are read as logic 1 or 0 5 DQ5 Chip enabled for reading array data goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation Not Used bits are read as logic 1 or 0 The system must issue the Flash Reset command to 1 re enable the device for reading array data if DQ5 Flash Status 2 Read Only PCIBAR2 2800H This read only register is used to read the ready or busy status of the flash chip A Flash Status 2 register is at base address plus 2800H The system must first verify that that Flash Chip is not busy before executing a new Flash command The Flash Chip is busy if bit 7 of this register is set to logic 1 The Flash will always be Busy while bit O of the Configuration Control register is set to logic 0 Bits FUNCTION Not Used bits are read as logic 0 Busy Ready Set bit 0 of the Configuration Control register to logic 1 before monitoring this busy bit 0 Flash Chip is Ready Flash Chip is Busy Flash Read Read Only PCIBAR2 3800H A Flash Read command is executed by reading this register at base address plus 3800H Prior to issue of a Flash Read the Flash Addre
5. Chip Write Only PCIBAR2 5800H This write only register is used to erase the entire contents of the flash chip A flash bit cannot be programmed from logic 0 back to logic 1 Only an erase chip operation can convert logic 0 back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip command must be performed A Flash Erase Chip command is executed by writing logic 1 to bit O of this register at base address plus 5800H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is implemented by reading bit O as logic 1 of the Flash Status 2 register The Flash Erase Chip operation will take 14 seconds to complete The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 0 of the Flash Status 2 register at base address plus 2800H will read as logic O when chip erase is completed Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 8 DK504 DK2004 User s Manual LVDS I O Reconfigurable Board FLASH REGISTERS Any other flash commands written to the flash chip during execution of the flash erase chip operation will be ignored Note that a hardware reset during the chip erase operation will immediately terminate the operation Flash Data Register Write Only PCIBAR2 6000H This write only register holds the data byte which is sent to the flash chip upon issue of a Flash Start
6. In Big Endian the lower order byte is stored at odd byte addresses Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 1 3 The DX board uses a flash configuration device to store programming Flash Configuration information for the Xilinx FPGA The flash configuration device and FPGA are hardwired together so that during power up the contents of the configuration device are downloaded to the FPGA The flash configuration data can be reprogrammed using the PCI bus interface The following is the general procedure for reprogramming the flash memory and reconfiguration of the Xilinx FPGA 1 Disable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx of its previous configuration by setting the Configuration Control register bit 2 to logic high Software must also keep bit 0 set to a logic high 3 Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated This can take up to 3 7m seconds for the Xilinx XC2V500 FPGA and 5 82m seconds for the Xilinx XC2V2000 FPGA 4 Verify Flash Chip is not busy by reading bit 7 as logic 0 of the Flash Status 2 register at base address plus 2800H before starting a new Flash operation 5 Erase the current flash contents by setting bit O of the Flash Erase Chip register to logic high The Fla
7. Write command Bits 3 to 0 of this register can be read Flash Address 7 gt 0 Write Only PCIBAR2 6800H This write only register holds the least significant byte of the address to which the flash chip is written upon issue of a Flash Start Write command Flash Address 15 58 Write Only PCIBAR2 7000H This write only register sets bits 15 to 8 of the address to which the flash chip is written upon issue of a Flash Start Write command Flash Address 20 gt 16 Write Only PCIBAR2 7800H This write only register sets bits 20 to 16 of the address to which the flash chip is written upon issue of a Flash Start Write command The most significant 3 bits of this register are not used Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual Reset Register Write Only PCIBAR2 8000H This write only register is used to issue a software reset Bit 15 when set to logic 1 will issue a software Xilinx FPGA This register can be read or written with either 8 bit 16 bit or 32 bit data transfers Interrupt Status Clear Read Write PCIBAR2 8004H This read write register is used to determine the pending status of 1 0 interrupts and release pending l O interrupts The interrupt status clear registers reflect the status of each of the I O channels Read of this bit reflects the interrupt pending status Read of a 1 indic
8. Xilinx FPGA for applications requiring a custom user specified clock frequency Clock generation can be programmed to any desired frequency between 10MHz and 100MHz Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 5 Power Up and System Reset is Failsafe For safety the LVDS PCI INTERFACE channels are configured for input upon power up FEATURES PCI Bus Master The PCI9056 PCI interface chip becomes the bus master to perform DMA transfers DMA Operation The PCI9056 supports two independent DMA channels capable of transferring data from the PCI to Local bus and Local to PCI bus The example design implements DMA block and demand modes of operation Field Connections All digital 1 0 and power connections are made through a single 68 pin SCSI front panel I O connector 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCI memory space All registers can be accessed via 32 16 or 8 bit data transfers Compatibility Complies with PCI Local Bus Specification Revision 2 2 Provides one multifunction interrupt Board is 5V or 3 3V signaling compliant The voltage provided on PCI connector VIO pins determines the operating voltage of the PCI bus Supply Voltage Requirement The board requires that 3 3 volts external power be provided on the 3 3 volt signal lines of the PCI bus
9. will take 0 16 seconds for the Xilinx XC2V500 and 0 45 seconds for the Xilinx XC2V2000 FPGA 10 Thereafter at power up the configuration file will automatically be loaded into the FPGA Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board Direct PCI bus to Xilinx Configuration of the Xilinx FPGA can be implemented directly from the fi 8 PCI bus The following is the general procedure for re configuration of the Configuration Xilinx FPGA via the PCI bus 1 Disable auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx of its previous configuration by setting the Configuration Control register bit 2 to logic high 3 Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated This can take up to 3 7m seconds for the Xilinx XC2V500 FPGA and 5 82m seconds for the Xilinx XC2V2000 FPGA 4 Download the Configuration file directly to the Xilinx FPGA by writing to the Configuration Data register The entire configuration file must be written to the Xilinx FPGA one byte at a time to the Configuration Data register at base address plus 1000H 5 Verify configuration complete by reading DONE bit 0 of Configuration Status Register as logic high DONE is expected to be logic high immediately after the last byte of the configuratio
10. 04 DX2004 User s Manual LVDS I O Reconfigurable Board CONFIGURATION The PCI specification requires software driven initialization and REGISTERS configuration via the Configuration Address space This board provides 512 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request kea D31 D24 D23 D16 D15 D8 D7 DO Device ID 0504 DX504 Vendor ID 16D5 Table 3 1 Configuration 2004 DX2004 Registers Command Class Code 118000 Rev ID 00 Cache 32 bit Memory Base Address for Memory Accesses to Local Runtime DMA and Messaging Aueue Registers PCIBARO PCI Base Address for 1 0 Accesses to Local Runtime DMA and Messaging Queue Registers PCIBAR1 32 bit Memory Base Address for Memory Accesses to Local Address Space 0 2M Space FPGA Space PCIBAR2 7 10 Not Used 11 Subsystem ID 0504 DX504 Subsystem Vendor ID 16D5 2004 DX2004 12 Not Used 13 14 Reserved 15 Inter Line This board is allocated memory space address PCIBARO to access the PCI9056 runtime DMA and messaging queue registers
11. 2 16 and 8 bit data transfer types supported Signaling 5V or 3 3V Compliant INTA Interrupt A is used to request an interrupt Source of interrupt can be from the Digital I O or PCI9056 Functions LVDS Propagation Delay Maximum Data Rate Termination Resistors PCI Local Bus Interface Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 2 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board APPENDIX CABLE MODEL 5028 Type Round shielded cable 68 wires SCSI 3 male connector at both 432 SCSI 3 to Round ends The cable length is 2 meters 6 56 feet This shielded cable is Shielded recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 288 termination panel to the board Length Standard length is 2 meters 6 56 feet Consult factory for other lengths It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 68 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors SCSI 3 68 pin male connector with backshell Keying The SCSI 3 connector has a D Shell Schematic and Physical Attributes See Drawing 4501 919 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum at 5096 energized SCSI 3 connector spec s Operating Temperature 30
12. ABLE MODEL 5028 432 eee 32 DRAWINGS 4501 996 BLOCK DIAGRAM m 33 4501 919 CABLE 5028 432 SHIELDED SA b eere ras 34 Trademarks are the property of their respective owners RELATED PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the DX board Virtex II Data Book http www xilinx com PCI 9056 Data Book http www plxtech com IDT71V65603 Specification http www idt com CY2305 Specification http www cypress com Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 1 0 GENERAL The re configurable DX504 DX2004 board has 32 LVDS low voltage differential signaling input output channels Re configuration of the FPGA INFORMATION is possible via a direct download into the Xilinx FPGA over the PCI bus In addition on board flash memory can be loaded with FPGA configuration data for automatic Xilinx configuration on power up Flash programming is also implemented over the PCI bus The data direction input output for each LVDS channel can be independently controlled Eight change of state interrupt channels are provided on the least significant eight channels Also the example design includes an interface to the 256K x 36 bit SRAM Table 1 1 The DX502 and OPERATING DX2002 boards are available MODEL Board Form Factor I O Typ
13. Acromag 4M Series PMC DX504 DX2004 Reconfigurable 32 LVDS I O USER S MANUAL ACROMAG INCORPORATED Tel 248 624 1541 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2004 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 733 A04D000 2 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATURES unum 4 may change without notice PCI INTERFACE FEATURES 5 Acromag makes no warranty SIGNAL INTERFACE PRODUCTS 5 of any kind with regard to this Board DLL Control Software 6 material including but not Board VXWORKS Software 6 limited to the implied Board QNX Software 6 warranties of merchantability and fitness for a particular 2 0 PREPARATION FOR USE purpose Further Acromag 195085 no rOspon
14. IAL EEPROM up configuration information required by the PCI9056 device The stored data in the EEPROM contains PCI device and vendor ID information In addition the PCI interrupt line PCI base address size and user options such as burst enabled are specified in this memory device The contents of the serial EEPROM can be changed using the PCI 9056 VPD function Acromag software also provides the functions needed to implement read and write operation to the serial EEPROM The DX board clock is routed to the PCI9056 Local bus pin SRAM CLOCK CONTROL CPLD and FPGA using a low skew clock driver Cypress CY2305 The input to the CY2305 can be one of two sources The on board 33MHz crystal oscillator is input to the CY2305 upon power up as the default condition After the FPGA is configured an FPGA generated clock signal PLL CLK can be selected as the board clock The PLL CLK signal is selected as the board clock by setting the USERo PCI9056 output signal to logic low See the PCI9056 USERo CLOCK CONTROL section of chapter 3 for additional details Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 8a DX504 DX2004 User s Manual 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP WWW acromag com LVDS I O Reconfigurable Board Surface Mounted Technol
15. MA Control Register Read Write PCIBAR2 8028H The DMA Control Register is used to request a DMA Demand mode transfer The transfer must include the Static RAM Memory as either the Source or the destination Bit 0 is used to request a DMA channel 0 transfer while bit 1 is used to request a channel 1 DMA transfer The bit must to set to logic high to request a transfer Once set the bit will remain set until the DMA transfer has completed The size of the DMA transfer must be set in the DMA Transfer Size register corresponding to the channel handling the transfer See the description of the DMA Transfer Size registers in the following paragraphs In addition the DMA transfer size direction source and destination must be set in the PCI9056 DMA control registers The PCI9056 DMA registers are at PCIBARO base address offset 80H to B8H See the PCI9056 user s manual and Acromag s software source code which provides an example for further details The DMA Control and DMA Transfer Size registers are only used to initiate DMA Demand Mode transfers These registers are used to illustrate DMA Demand Mode data transfers Writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 3 DMA Transfer Size Registers Read Write PCIBAR2 802CH and 8030H The DMA
16. S Table 3 3 Board Interrupt Status Clear 1 All bits labeled Not Used will return logic 0 when read DMA INTERRUPT REGISTERS Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 0 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board DIGITAL LVDS Input Output Registers Read Write INPUT OUTPUT PCIBAR2 8008H REGISTERS Thirty two LVDS channels numbered 0 through 31 may be individually accessed via this register Channels 0 to 31 are accessed at the carrier base address 8008H via data bits 0 to 31 Each channel is controlled by its corresponding data bit as shown below Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register Note that the data direction input or output must first be set via the Direction register at base address plus 8010H LVDS I O Channel and Corresponding Register Bits D7 pe D5 D4 D3 D2 D1 DO Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 D15 D14 D13 D12 D11 D10 D9 D8 Ch23 Ch22 Ch21 Ch20 Ch 19 Ch 18 Ch 16 Ch31 Ch 30 Ch29 Ch28 Ch26 Ch25 Ch24 Channel read write operations use 8 bit 16 bit or 32 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs following a power on or softwar
17. The PCI9056 decodes 512 bytes for these memory space registers These registers can also be accessed by an I O cycle with the PCI bus address matching the I O Base Address PCIBAR1 In addition this board is allocated a 2M byte block of memory PCIBAR2 that is addressable in the PCI bus memory space to control the board s multiple functions included in the virtex II FPGA Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual The memory space address map for the board is shown in Table 3 2 Note that the base address for the board PCIBAR2 in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 16 and 8 bit in memory space are permitted Rest no m 000 Rai 0003 Not Used CERE aa Status 0000 0803 Not Used Regis Braten Control 0800 1003 Not Used Configuration Data 1000 2003 Not Used Flash Status 1 Register 2000 2803 3803 4003 4803 5003 5803 6003 6803 7003 7803 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Flash Status 2 Register Flash Read Flash Reset Flash Start Write Flash Erase Sector Flash Erase Chip Flash Data Register Flash Address 7 20 Flash Address 15 58 Flash Address 20 2516 LVDS I O Reconfigurable Board 1 1 MEMORY MAP Table 3 2 Memory Map Configurati
18. Transfer Size Register is used to set the size of the DMA Demand mode data transfer that moves data to or from the on board Static RAM memory The on board static RAM has 256K memory locations As such the maximum value that can be written to this register is 3FFFFH which corresponds to 2 5 A value of 3FFFFH would specify the move of 256K long words DMA REGISTERS The DMA Transfer Size Register at base address 802CH is used to set the DMA channel 0 data transfer size The register at base address 8030H is used to set the DMA channel 1 data transfer size Writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Static RAM Memory Read Write STATIC RAM MEMORY PCIBAR2 100000H to 1FFFFFH The Static RAM memory space is used to provide read or write access to on board SRAM memory The Static RAM device has a 256K x 36 bit memory configuration Reading or writing to this memory space is possible via 32 bit 16 bit or 8 bit data transfers PCI9056 Registers Read Write PCIBARO PCI9056 REGISTERS The PCI9056 is configured for PLX PCI9056 chip C Mode Local bus operation The PCI9056 User s Manual references to C Mode configuration only apply to the DX boards The DX boards use the C Mode generic 32 bit non multiplexed address and data bus interface for communication between the PCI9056 and the Xilinx FPGA Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag
19. acromag com 8 DK504 DK2004 User s Manual LVDS I O Reconfigurable Board The data direction of LVDS channels 0 to 31 are independently controlled via the Direction Register Table 2 1 Board Field VO Pin Pin Description Pm Pin Description Pin Connections 1vosc 1 vso 35 vso 2 1VDSCh 36 vosch 6 ilVDSCh 40 ivoscm 8 ilvoscn 4 voschk 9 1VDSCh a LVDSCh23 26 LVDSCh2S 60 LVbSCh20 32 LVDSCh2 66 LVbSCh is 34 vos crs o Non Isolation The board is non isolated since there is electrical continuity between the Considerations logic and field 1 0 grounds As such the field 1 0 connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board O This Section provides the specific information necessary to program and operate the board 3 0 PROGRAMMING This board is a PCI Specification version 2 2 compliant PCI bus INFORMATION master target board The PCI bus is defined to address three distinct address spaces O memory and configuration space This board can be accessed via the PCI bus 1 0 memory and configuration spaces The card s configurat
20. acromag com LVDS I O Reconfigurable Board 3 4 DX504 DX2004 User s Manual O616 LOSV Q3q13lHS A18NW3SSV 318VO Nid 89 ISOS oO N S NId nnnanannunnunununnnunununununnnni poponar 89 NId F Nid 7 ld L Nid WA c v 8c08 1300W M3IA LNO4J N a S Nid L Nid WA pongan 00000000000000000000000000000000 89 Nid F Nid 7 CT M3IA dO S3HONI 0 0 004 SIHONI 284 cd SYSALAW 7 g OILVNAHOS ma g 8 SSSSSSSSSBRERBSLHTEBLSSLLILYS SBS 5993 GS LSSERNKKAKRANKOSLOOrONLOOoronsow RA ld cd T1SHSMOWE g3G13IHS Zd ld OL SI23NNOO 318vO NO G1SIHS GNNOYD Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 3 5 Notes Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 36 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board Notes Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com
21. actPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI boards Acromag provides a software product sold separately consisting of board QNX software This software Model PMCSW API QNX is composed of QNX real time operating system libraries for all Acromag PMC I O board products PCI I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI boards Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual Upon receipt of this produ
22. annels 0 7 of this model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions on all channels The interrupt is released via a write to the corresponding bit of the Interrupt Status Clear register LVDS channels 0 31 to the FPGA are buffered using Multipoint LVDS line driver and receivers Field inputs to these receivers include a 100 ohm termination resistor Signals received are converted from the required TIA EIA 899 LVDS voltages to the TTL levels required by the FPGA Likewise TTL signals are converted to the TIA EIA 899 LVDS voltages for data output transmission The direction control of the LVDS channels is independently controlled Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board T A 256K x 36 bit synchronous SRAM is provided on the DX board The address data and control signals are directly connected to the FPGA To ME RONOUS identify the pins corresponding to these signals see the Constraints UCF file provided in the engineering design kit Address and control signals are applied to the SRAM during one clock cycle and two clock cycles later the associated read or write data cycle occurs Please refer to the IDT71V65603 Data Sheet See Related Publications for more detailed information A 128 x 16 bit Serial EEPROM is wired to the PCI9056 to provide power SER
23. ates that an interrupt is pending for the corresponding channel Write of a logic 1 to this bit to release the corresponding channel s pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending Channel 0 interrupt status is identified via data bit O while I O channel 7 status is identified via data bit 7 at base address plus 8004H 0 ChameiOimemupPendngiCear l Channel 3 Interrupt Pending Glear E E 6 Channel 6 Interrupt Pending Ciea Interrupts must be enabled via the PCI9056 control registers and the Interrupt Enable register at base address offset 8014H in order to generate interrupts The PCI9056 Interrupt Control Status register at PCIBARO base address offset 68H must have bits 8 and 11 set to a logic high in order for interrupts to occur DMA interrupts must be enabled and controlled through the PCI9056 registers The PCI9056 Interrupt Control Status register at PCIBARO base address offset 68H must have bits 18 and 19 set to a logic high in order for DMA interrupts to occur on DMA channels 0 and 1 respectively DMA transfers are configured and controlled via PCI9056 DMA registers The PCI9056 DMA registers are at PCIBARO base address offset 80H to B8H These registers control the transfer direction size source address and destination address for DMA channels 0 and 1 LVDS I O Reconfigurable Board 1 O RESET REGISTER FPGA INTERRUPT REGISTER
24. com 2 4 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board PCI9056 USERo CLOCK A DX on board clock is used to clock the PCI9056 Local bus SRAM CONTROL interface CPLD operation and FPGA operation The DX Board clock can be one of two sources The Board clock can be either 33MHz or the frequency provided by the Xilinx FPGA on the PLL_CLK signal Clock Note the PCI9056 USERo signal selection is controlled via the PCI9056 USERo signal signal is a general purpose output controlled from the The default power up condition of the DX board enables the on board PCI9056 Configuration 33MHz crystal as the active clock However after the FPGA is configured registers The o at the to drive the PLL_CLK signal with a user defined frequency the PLL_CLK AA E signal can be selected as the board clock output signal The USERo control signal output from the PCI9056 is used to select between the 33MHz clock and the user defined clock PLL_CLK The user defined clock must be defined in the FPGA and output from the FPGA on signal PLL_CLK The Digital Clock Manager of the FPGA offers a wide range of clock management features including clock multiplication and division for generation of a user defined clock PLL_CLK A 33MHz crystal generated clock signal FPGA CLK PLL is input to the FPGA for use in generation of the user defined clock signal PLL_CLK The PLL_CLK can be a minimum of 10MHz and a maximum of 100MHz Since the PLL_CLK signal is gen
25. control registers of the PCI9056 chip can be configured for DMA block mode and demand mode The example device driver can be used to exercise DMA block and demand modes of operation For other DMA modes of operation see the PLX Technology PCI9056 user manual The DMA demand mode requires Xilinx FPGA hardware to drive two PCI9056 signals active to request the DMA transfer of data The signal DREQO is driven active to request a DMA channel 0 transfer The signal DREQ 1 is driven active to request a DMA channel 1 transfer To identify the pins corresponding to these signals see the Constraints UCF file provided in the engineering design kit This DX board does not utilize the PCI9056 PCI power management functions The power management request signal PME is not used and is tied high with an external pullup resistor The internal PCI Arbiter is not used External pull up resistors are tied to the REQ 6 1 input and GNT 6 1 output signals of the PCI9056 chip Many features of the PCI9056 are not used in the example design but NOT USED PCI9056 are available if enabled It is beyond the scope of this document to FUNCTIONS duplicate the PCI9056 User s Manual Please refer to the PCI9056 User s Manual See Related Publications for more detailed information The PCI9056 is hardwired for C bus mode This is a generic 32 bit non multiplexed address and data bus interface Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acro
26. ct inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Remove power from the system before install
27. d by the input channel Interrupt Polarity Register Channel read or write operations use 8 bit 16 bit or 32 bit data transfers Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 2 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board INTERRUPT Interrupt Polarity Register Read Write REGISTERS PCIBAR2 801C The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts A 0 bit specifies that an interrupt will occur when the corresponding input channel is low i e a 0 in the input channel data register A 1 bit means that an interrupt will occur when the input channel is high i e a 1 in the input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the PCIBAR2 base address offset 801CH is used to control channels 0 through 7 All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are logic low provided they are enabled for interrupt on level DMA REGISTERS D
28. ding the hardware of the board A description of the basic functionality of the circuitry used on the board is also 4 0 THEORY OF provided Refer to the Block Diagram shown in Drawing 4501 996 as you OPERATION review this material A PLX Technology PCI9056 IC installed on the board provides a 66MHz PCI INTERFACE LOGIC 32 bit interface to the carrier CPU board per PCI Local Bus Specification 2 2 The interface to the carrier CPU board allows complete control of all board functions The PCI9056 is compliant with both 5V and 3 3V signaling The PCI bus VIO signals are tied directly to the PCI9056 chip which monitors the voltage present on VIO to automatically implement the matching signaling voltage Note that the DX board requires that system 3 3 volts be present on the PCI bus 3 3V pins There are some older systems that do not provide 3 3 Volts on the PCI bus 3 3 volt pins The DX boards will not work in these systems This is a master target board with the PCI bus interface logic contained within the PCI9056 This logic includes support for PCI commands including configuration read write and memory read write In addition the PCI interface performs parity error detection uses a single 2Meg base address register PCIBAR2 and implements target abort retry and disconnect The logic also implements interrupt requests via interrupt line INTA The PCI9056 becomes the PCI bus master to perform DMA transfers on channels 0 and 1 The DMA
29. e TEMPERATURE in standard and extended RANGE temperature ranges PMC DX504 PCI Mezzanine Card 32LVDS 0 C to 70 C PMC DX2004 PCI Mezzanine Card 32LVDS 0 C to 70 C PMC DX504E PCI Mezzanine Card 32LVDS 40 C to 85 C PMC DX2004E PCI Mezzanine Card 32LVDS 40 C to 85 C KEY FEATURES e Reconfigurable Xilinx FPGA In system configuration of a 500K DX504 or 2Meg DX2004 system gate FPGA is implemented through a flash configuration device or via the PCI bus This provides a means for implementation of custom user defined digital designs e 32LVDS Input Output Channels 32 channels of low voltage differential signaling can be configured for input or output with independent direction control at up to 200 Mbps data rates or 100MHz Clock rates e Programmable Change of State Level Interrupts Interrupts are software programmable for any bit Change Of State or level on 8 channels e 256K x 36 SRAM A 256K x 36 bit static random access memory SRAM is directly accessed by the Xilinx device Custom user defined design logic for the Xilinx FPGA will permit use of the SRAM as FIFO memory or single port memory as required by the application e Example Design Provided The example VHDL design includes implementation of the PCI9056 Local bus interface control of LVDS I O eight Change Of State interrupts and SRAM read write interface logic e Programmable Clock Generation Clock generation logic is provided by the
30. e reset Direction Control Register Read Write PCIBAR2 8010H The data direction input or output of the 32 LVDS channels is selected via this register Channels 0 to 31 are accessed at the carrier base address 8010H via data bits 0 to 31 The direction of each channel is controlled by its corresponding data bit Data bit O controls channel 0 up to data bit 31 controlling channel 31 Independent channel direction control is provided for each LVDS channel Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The default power up state of these registers is logic low Thus all channels are configured for data input following system reset or power up Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 1 Interrupt Enable Register Read Write INTERRUPT PCIBAR2 8014H REGISTERS The Interrupt Enable Register provides a mask bit for each channel from 0 to 7 A 0 bit will prevent the corresponding input channel from generating an external interrupt A 1 bit will allow the corresponding channel to generate an interrupt The Interrupt Enable register at the PCIBAR2 base address offset 8014H is
31. erated and driven by the FPGA it will only be available after the FPGA is configured See the example VHDL file included in the engineering design kit and the Xilinx documentation on the Digital Clock Manager for more information The USERo signal is controlled via a PCI9056 device register over the PCI bus The PCI9056 User I O Control register at PCIBARO base address offset 6CH must have bit 19 set to a logic high to select USERo to be an output from the PCI9056 In addition User I O Control register at PCIBARO base address offset 6CH must control bit 16 to select the DX board clock frequency Bit 16 set to logic high causes the Board clock to be 33MHz Bit 16 set to logic low will select the PLL CLK as the Board clock frequency PCI Bit 16 PCI9056 Runtime Register Address USERo User I O Control PCIBARO Board clock becomes PLL_CLK 6CH Board clock 33MHz Default Note that the Xilinx FPGA can not be reconfigured with the PLL_CLK signal selected The first step in FPGA reconfiguration is to clear the FPGA device and this will disable the PLL_CLK signal Without a board clock the DX board will lock up and require a system power down to reactivate The USERo clock control signal must be set to logic high prior to FPGA reconfiguration Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 5 This section contains information regar
32. g s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board O Single PMC Board Height 13 5 mm 0 531 in 6 0 Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in SPECIFICATIONS Width 74 0 mm 2 913 in Board Thickness 1 59 mm 0 062 in PHYSICAL e PMC PCI Local Bus Interface Two 64 pin female receptacle header Connectors AMP 120527 1 or equivalent e Field I O 68 pin SCSI 3 female receptacle header AMP 787082 7 or equivalent Power PMC Modules Table 6 1 Power Requirements Requirements for Example Design Can 100mA 5V Maximum rise time of Typical 700mA 100m seconds 3V x59 L CNN On Board 1 5V Power to Current Rating Virtex Il FPGA Operating Temperature 0 to 70 C 40 C to 85 C E Version ENVIRONMENTAL Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 3V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no register upsets Conducted R F Immunity CRFI Complies with EN61000 4 6 3V rms 150KH
33. ing board cables termination panels and field wiring The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows e The default configuration of the programmable software control register bits at power up are described in section 3 e The control registers must be programmed to the desired configuration before starting data input or output operation The front panel connector provides the field 1 0 interface connections It is a SCSI 3 68 pin female connector AMP 787082 7 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to SCSI 3 destination from the front panel via round shielded cable Model 5028 432 LVDS I O Reconfigurable Board T 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION r Wy CAUTIO SENSITIVE ELECTRONIC DEVICES DO NOT SHI OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Configuration Front Panel Field I O Connector Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www
34. ion registers are initialized by system software at power up to configure the card The board is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to read write the PCI card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCI bus to determine what PCI devices are PCI Configuration present The software also determines the configuration requirements of Address Space the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address The configuration registers are also used to indicate that the board requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the board Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space and which interrupt line will be used Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 Q DX5
35. mag com http www acromag com 2 6 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board THEORY OF OPERATION CONTINUED LVDS INPUT OUTPUT LOGIC The example design implements the PCI9056 as the local bus master The local bus is the bus interface between the PCI9056 and the Xilinx FPGA As the local bus master the PCI9056 responds to BREQi assertion to relinquish local bus ownership The example design has BREQi tied low The Xilinx FPGA does not request the local bus However the FPGA may drive BREQi high if the FPGA must take control of the local bus The example design implements single cycle mode In single cycle mode the PCI9056 issues one ADS per data cycle The starting address for a single cycle data transfer can be any address Burst read and write cycles can be implemented but must be enabled in the PCI9056 and supported in the logic of the FPGA The PCI9056 Local Address Space 0 Expansion ROM Bus Region Descriptor register at PCIBARO base address offset 18H must have bit 24 set to a logic high to enable bursting Thirty two LVDS low voltage differential signaling I O are provided through the Field I O Connector refer to Table 2 1 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Ch
36. n file is written to the Xilinx FPGA 6 At power up the configuration file will need to be reloaded into the FPGA Configuration Status Register Read Only PCIBAR2 0000H This read only register reflects the status of configuration complete and Xilinx configuration clear This Configuration Status register is read at base address plus OH Bits FUNCTION Configuration Status DONE Register 0 Xilinx FPGA is not configured Xilinx FPGA configuration is complete INIT INIT is held low until the Xilinx is clear of its current configuration INIT transitions high when the clearing of the Xilinx current configuration is complete 0 Not Used bits are read as logic Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 1 5 Configuration Control Register Read Write Only PCIBAR2 0800H CONFIGURATION CONTROL REGISTERS This read write register is used to stop Xilinx configuration clear Xilinx configuration memory and set Local Bus Hold control This Configuration Control register is accessed at base address plus 0800H Bits FUNCTION Configuration Control Stop Xilinx Configuration Register 0 Enable Xilinx FPGA configuration Stop Xilinx FPGA configuration Not Used bit is read as logic 0 2 Clear Current Xilinx Configuration 59 Logic low has no effect Logic high resets the Xili
37. nx configuration logic Re configuration can begin after INIT transitions high Not Used bits are read as logic 0 Local Bus Hold Control CPLD controls generation of Local Hold Acknowledge The CPLD logic will always grant control of the local bus to the PCI9056 device Xilinx FPGA controls generation of the Local Hold Acknowledge signal Configuration Data Write Only PCIBAR2 1000H This write only register is used to write Xilinx configuration data directly to the Xilinx FPGA from the PCI bus This Configuration Data register is accessed at base address plus 1000H The entire configuration file must be written to the Xilinx FPGA one byte at a time Configuration complete is verified by reading DONE bit 0 of Configuration Status Register as logic high A write to this Configuration Data register while auto configuration from Flash is active will cause the Xilinx configuration to fail Auto configuration is stopped by writing logic 1 to bit O0 of the Configuration Control register at base address plus 800H The Xilinx FPGA should also be cleared of its current configuration prior to loading of a new configuration file The FPGA is cleared of its current configuration by writing logic 1 to bit 2 at address plus 800H Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board FLASH CONTROL REGISTERS Flash Status
38. ocks e 8 Digital Clock Managers 256K x 36 bit Integrated Devices Technology IDT71V65603 e 133 Megahertz Speed Channel Configuration 32 Bi directional LVDS signals are independently direction controlled e 480m V Min 650mV Max LVDS Driver Output Voltage with 50O load e 1 2 V Max Common Mode Output Voltage e 50 mV Min to 50mV Max LVDS Input Threshold Voltage e 25mV Typical Input Hysteresis e Meets or Exceeds the LVDS Starndard TIA EIA 644 Also meets or exceeds the M LVDS Starndard TIA EIA 899 for Multipoint Data Interchange Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 3 1 e Driver Propagation Delay Time 2 4ns Maximum e Driver Output Signal Transition Time 1 6ns Maximum e Receiver Propagation Delay Time 6ns Maximum e Receiver Output Signal Transition Time 2 3ns Maximum e Maximum Data Rate 200 Mbps e Maximum Clock Rate 100MHz Termination Resistors Non removable 100Q termination resistor is in place for each of the 32 LVDS channels Board Crystal Oscillator 33MHz Frequency Stability 0 01 PMC Compatibility Conforms to PCI Bus Specification Revision 2 2 and PMC Specification P1386 1 PCI Master Target Implemented by PLX Technology PCI9056 Chip 2M Memory Space Required One Base Address Register for this 2M space PCI commands Supported Configuration Read Write memory Read Write 3
39. ogy SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed ina burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Choose Bus Board Products then go to the Support tab in the Acromag banner to access e Application Notes Frequently Asked Questions FAQ s Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acroma
40. on Registers 1 The board will return O for all addresses that are Not Used 2 Address space 0 gt 7FFF is not contiguous because the least significant address lines are not decoded by the CPLD Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board MEMORY MAP Base D31 D15 Base Addr D16 D00 Addr Not Used Software Reset Register Not Used Interrupt Stat iClear Table 3 2 Memory Map Xilinx Registers 31 0 LVDS I O Register 1 The board will return 0 for 800F 1 all addresses that are Not Nonne 300 Used 8013 Direction Register Channels 31 0 8010 8017 1 Interrupt Enable iid Channels 7 0 8014 ome 1 Interrupt Type NOUS RO Channels 7 0 8018 801F 1 Interrupt Polarity nobus Channels 7 0 801C 8023 Not Used 8020 8027 Not Used 8024 802B DMA Control Register 8028 802F DMA Transfer Size Channel 0 802C 8033 DMA Transfer Size Channel 1 8030 8037 Not Used 8034 FFFFF Not Used FFFFC 100003 Static RAM Memory 100000 41FFFFF Static RAM Memory 1FFFFC This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention
41. sh Erase Chip operation will take 14 seconds to complete 6 Verify Flash Chip is not busy by reading bit 7 as logic 0 of the Flash Status 2 register at base address plus 2800H before going to the next step 7 Download the Configuration file to the flash configuration chip via the PCI bus i Write the byte to be sent to the Flash Data register at base address plus 6000H ii Write the address of the Flash Chip to receive the new data byte to the Flash Address registers at base address plus 6800H 7000H and 7800H Issue of a Flash Start Write will automatically increment this address after the issued Flash Write has completed Thus the address will not need to be set prior to issue of the next Flash Start Write The first byte of the configuration file should be written to address O of the Flash Chip The Flash Start Write operation will take 9u seconds to complete iil Issue a Flash Start Write command to the Flash Chip by writing logic 1 to bit O of base address plus 4800H iv Verify the Flash Chip is not busy by reading bit 7 as logic 0 of the Flash Status 2 register at base address plus 2800H before going back to step i to write the next byte 8 Enable auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic low 9 Verify configuration complete by reading DONE bit 0 of Configuration Status Register as logic high The auto configuration process of moving Flash data to the Xilinx FPGA
42. sioiiy tor UNPACKING AND INSPECTION aaa aaa 7 any errors that may appear in this manualahid imakes hio CARD CAGE CONSIDERATIONS 7 commitment to update or BOARD CONFIGURATION O 7 keep current the information Default Hardware Configuration 7 contained in this manual No Front Panel l O Ie pue 8 part of this manual may be Non Isolation Considerations 9 copied or reproduced in any form without the prior written consent of Acromag Inc 3 0 PROGRAMMING INFORMATION PCI CONFIGURATION ADDRESS SPACE 10 Configuration registers 11 MEMORY MAP enhn 12 Flash Configuration eese 14 PCI bus to Xilinx Configuration 14 Configuration Status Register 14 Configuration Control Register 15 Configuration Data eene 15 Flash Status1 Register 16 Flash Status2 bid pud ED 16 Flash Read 16 Flash Ree MORAN CIPAEHA ME UAE NOUS Me 17 Flash Start Wito eese 17 Flash Erase Sector 17 Flash Erase Chip 17 Flash Data Register ees 18 Flash Address Register
43. ss registers must be set with the desired address to be read See the Flash Address registers at base address plus 6800H 7000H and 7800H The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation DQ5 can be monitored via the Flash Status 1 register at base address plus 2000H Flash Reset Write Only PCIBAR2 4000H This write only register is used to initiate a reset of the flash chip A Flash Reset command is executed by writing logic 1 to bit O of this register at base address plus 4000H Writing the flash reset command resets the chip to reading data mode Once an erase or programming operation begins the chip ignores reset commands until the operation is complete Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com DX504 DX2004 User s Manual LVDS I O Reconfigurable Board 1 T FLASH CONTROL Flash Start Write Write Only PCIBAR2 4800H REGISTERS This write only register is used to initiate the write of a byte to the flash chip A Flash Start Write command is executed by writing logic 1 to bit O of this register at base address plus 4800H Prior to issue of a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base addre
44. ss plus 6000H 6800H 7000H and 7800H Flash Erase Sector Write Only PCIBAR2 5000H A Flash Erase Sector command is executed by writing logic 1 to bit 0 of this register at base address plus 5000H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 0 as logic 1 of the Flash Status 2 register There are 32 flash sectors which are addressed via the most significant five flash address lines The most significant five flash address lines are set via the Flash Address 23 16 register at base address plus 7800H Issue of a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified A flash bit cannot be programmed from logic 0 back to logic 1 Only an erase chip operation can convert logic 0 back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip or Flash Erase Sector command must be performed The Flash Erase Chip operation will take 14 seconds to complete The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 0 of the Flash Status 2 register at base address plus 2800H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase sector operation are ignored Note that a hardware reset during the erase sector operation will immediately terminate the operation Flash Erase
45. used to control channels 0 through 7 via data bits 0 to 7 All channel interrupts are disabled set to 0 following a power on or software reset Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers In addition to this register interrupts must be enabled via the PCI9056 control registers in order to generate interrupts The PCI9056 Interrupt Control Status register at PCIBARO base address offset 68H must have bits 8 and 11 set to a logic high in order for interrupts to occur Interrupt Type COS or H L Configuration Register Read Write PCIBAR2 8018 The Interrupt Type Configuration Register determines the type of input channel transition that will generate an interrupt for each of the eight possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at PCIBAR2 base address offset 8018H is used to control channels 0 through 7 For example channel 0 is controlled via data bit 0 All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specifie
46. z to 80MHz and European Norm EN50082 1 with no register upsets Electromagnetic Interference Immunity EMI No register upsets occur under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com 30 DX504 DX2004 User s Manual LVDS I O Reconfigurable Board SPECIFICATIONS Reliability Prediction FPGA DX504 FPGA DX2004 Synchronous SRAM LVDS I O Electrical Characteristics for Channels 0 to 31 Electric Fast Transient EFT Immunity Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclosure port contact discharge Level 1 2KV I O terminals contact discharge and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure are required to meet compliance Mean Time Between Failure TBD hours 25 C Using MIL HDBK 217F Notice 2 Xilinx XC2V500 4F G456 e 500K System Gates e 32 Multiplier Blocks e 32 18Kbit SelectRAM Blocks e 8 Digital Clock Managers Xilinx XC2V2000 4F G676 e 2Meg System Gates e 56 Multiplier Blocks e 56 18Kbit SelectRAM Bl
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