USER'S MANUAL - Oho
Contents
1. 19 FB1MC11 PLD30 pinf9 Connection to the 24pin DIL plug to pin19 via serial resistor CON1 pin19 pin15 Connection to the 20pin DIL plug to pin15 via serial resistor 20 FB1MC10 PLD31 pin20 Connection to the 24pin DIL plug to pin20 via serial resistor CON1 pin20 pin16 Connection to the 20pin DIL plug to pin16 via serial resistor 21 FB1MC8 PLD33 pin21 Connection to the 24pin DIL plug to pin21 via serial resistor CON1 pin21 pin17 Connection to the 20pin DIL plug to pin17 via serial resistor 22 FB1MC2 PLD34 pin22 Connection to the 24pin DIL plug to pin22 via serial resistor CON1 pin22 pin18 Connection to the 20pin DIL plug to pin18 via serial resistor 23 FB1MC1 PLD35 pin23 Connection to the 24pin DIL plug to pin23 via serial resistor GOP XCR3064XL USER S MANUAL V0 9 Page 17 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de CON1 pin23 Connection to the 20pin DIL plug to pin19 via serial resistor 24 PIN 24 5V input voltage to the module 8 CON4 Test Connector Pinout Table Pin CPLD pin Schema UCF function net name port Comment routed to name 1 GND GND Power ground plane connection 2 FB4MC10 PLD13 tp2 Test connector pin2 CON4 pin2 3 FB4MC11 PLD14 tp3 Test connector pin3 CON4 pin3 4 FB4MC12 LED_R tp4 Test connector pin42. 34 FB1MC2 PLD34 pin22 Connection to the 24pin DIL plug to pin22 via serial CON1 pin22 pin18 resistor Connection to the 20pin DIL plug to pin18 via serial resistor 35 FB1MC1 PLD35 pin23 Connection to the 24pin DIL plug to pin23 via serial CON1 pin23 pin19 resistor Connection to the 20pin DIL plug to pin19 via serial resistor 36 GND Power GND Connection to the GND Layer of the PCB 37 IN3 CLK3 OSC osc Crystal oscillator input to global clock net CLK3 XOSC1 38 IN2 CLK2 RC_OUT rcout Output from an RC network this is for demonstration that RC network rc oscillators do not work reliably with XCR3064XL but on CoolRunner ll devices with Schmitt Trigger inputs 39 INT CLK1 PLD43 pin2 Connection to the 20 24pin DIL plug to pin2 via serial CONI pin2 pin2 resistor Access to global clock net CLK1 40 INO CLKO PLD42 pint Connection to the 20 24pin DIL plug to pin1 via serial CON1 pin1 pint resistor Access to global clock net CLKO 41 VCC Power VCC Power supply 3 3V from regulator TPS76333 GOP XCR3064XL USER S MANUAL V0 9 Page 15 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 42 FB2MC16 PLD42 pint Connection to the 20 24pin DIL plug to pin1 via serial CON1 pin1 pint resistor Access to global clock net CLKO 43 FB2MC2 PLD43 pin2 Connection to the 20 24pin DIL plug to pin2 via serial CON1 pin2 pin2 resistor Access to global cl
3. CON ping pin8 resistor 9 FB4MC5 PLD11 pind Connection to the 20 24pin DIL plug to pin9 via serial CON 1 pin9 pind resistor 10 FBAMC9 PLD12 pin10 Connection to the 24pin DIL plug to pin10 via serial resistor CON1 pin10 Short to GND by CONS for 20pin DIL plug 11 FB4MC2 PLD8 pin11 Connection to the 24pin DIL plug to pin11 via serial resistor CON1 pin11 Not used for the 20pin DIL plug 12 GND GND Power ground plane connection 13 FB3MC11 PLD20 pin13 Connection to the 24pin DIL plug to pin13 via serial resistor CON1 pin13 Not used for the 20pin DIL plug 14 FB3MC10 PLD21 pin14 Connection to the 24pin DIL plug to pin14 via serial resistor CON1 pin14 Not used for the 20pin DIL plug 15 FB3MC9 PLD22 pin15 Connection to the 24pin DIL plug to pin15 via serial resistor CON1 pin15 pin11 Connection to the 20pin DIL plug to pin11 via serial resistor 16 FB3MCA PLD23 pin16 Connection to the 24pin DIL plug to pin16 via serial resistor CON1 pin16 pin12 Connection to the 20pin DIL plug to pin12 via serial resistor 17 FB3MC2 PLD25 pin17 Connection to the 24pin DIL plug to pin17 via serial resistor CON1 pin17 pin13 Connection to the 20pin DIL plug to pin13 via serial resistor 18 FB1MC15 PLD27 pin18 Connection to the 24pin DIL plug to pin18 via serial resistor CON1 pin18 pin14 Connection to the 20pin DIL plug to pin14 via serial resistor
4. the bottom side of the module These shorts should be soldered via a stereo microscope to insure that there are no other invalid connections GOP XCR3064XL USER S MANUAL V0 9 Page 11 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 4 CPLD Design Support As for CPLD design 3 and 8 are very recommended readings VHDL and UCF design templates for 20 and 24 pin configurations are availlable GOP XCR3064XL USER S MANUAL V0 9 Page 12 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 GOP XCR3064XL I O Voltage Levels Since CPLD 1 O s can be inputs or outputs or bidirectional we have to distinguish between voltage levels driven from the outputs of the CPLD and voltage levels that are applied to their inputs The XCR3xxx XPLA3 series inputs can accept input voltage levels from O to 5V so they are 5V tolerant However they can not deal with analog input voltages The maximum low input voltage VIL where the CPLD sees a logical 0 must be 0 8V The minimum high input voltage VIH where the CPLD sees a logical 1 must be 2 0V and must not exceed 5 5V Voltage levels in between VIL and VIH should change very fast transition times should be lower than 100ns although Xilinx makes no recommendations about them in this CPLD family Unused I O pins always have an enabled internal pullup see 10 Buskeepers are not availlable on
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6. CON4 pin4 Red led of the duo led 0 gt led off 1 gt led on 5 FB3MC13 LED G tp5 Test connector pin5 CONA pin4 Green led of the duo led 0 gt led off 1 gt led on 6 FB3MC12 PLD19 tp6 Test connector pin6 CONA pin6 R46 could be soldered to the 5V supply voltage for generation of an 5V rail on tp6 Use 6800 to 10kQ E i Be i 5V input voltage protected by a polyfuse 9 CON3 Configuration Jumper options Enable 20pin PAL GAL Emulation put GND to pin 10 of CON1 Enable XOSC1 crystal oscillator 49 152 MHz GOP XCR3064XL USER S MANUAL V0 9 Page 18 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 10 DIL Connector Layout GOP XCR3064XL module top view for 24 pin and 20 pin emulation mode 20mm lt 20mm O O O O O O O O oN Se OO 0 lt 40 Bmm 40 5mm GOP XCR3064XL USER S MANUAL V0 9 Page 19 of 25 LO N Be 5 Ka o E o CN n n a n n D o x T T s 99US Hz CH DD HL TE Sie 4AOie TI2S0 SIGLUI lt Uld D o 4012e8uu0j 31A Q urdgz lt Z T Uld D ZGTEEX IXb9BENIX dO9 ise asdunr uonco o 48qunN iueunoo q iS S IXr9Qg42x doB 37111 ENOI 193208
7. Dachau Germany www oho elektronik de Power Suppy The module can be powered at DIL pin 24 from 3 5 to 5 5 Volts Module GND pin is pin 12 in 24 pin mode and pin 10 in 20 pin mode An onboard voltage regulator produces the CPLD core and I O voltage of 3 3V The regulator 4 can source up to 150mA The module has a protection against reverse insertion or reverse power connection In that case the protection shorts the power supply by a polyfuse device The polyfuse recovers after deactivation of the power supply Burn through cycles of the polyfuse are limited For more information please consult the data sheet Even so care should be taken when plugging the module Consider that a short pulse of several amps can damage the environment in which the module is inserted 3 3 PAL GAL Emulation Of 24 Pin And 20 Pin Devices As a general hint the DIL plug should be protected mechanically with the supplied DIL sockets as an adaptor In 24 pin mode of the module a 24 pin socket should be used In 20 pin mode of the module a 20 pin socket should be used Please insure that pin 1 of the module is always pin 1 of a socket In the 20 pin mode an additional GND connection must be done via a 2mm jumper on jumper block CONS at position 1 2 see Layout Top View This adds GND to pin 10 In rare cases additional GND connections are desired Pins 3 14 and 23 can be shorted to GND with solder jumpers JP1 JP3 JP2 respectively on
8. Rapid Prototyping Fast evaluation of Xilinx CPLD s Battery operated equipment Hardware platform for VHDL VERILOG digital design introductory courses GOP XCR3064XL USER S MANUAL V0 9 Page 5 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 3 Xilinx XCR3064XL CPLD Features Document 1 and 2 lists lots of goodies here are the best facts Fast and modern low power CPLD quiescent current is 18uA typ at 25 C gt 4 logic arrays 16V40 each offers 40 array inputs with 16 macrocells and a 48 product term PLA Macrocells offer D T and Latch type memory elements with dedicated CE input Flipflops can toggle on rising and falling edges but not on both gt 4 global clocks and product term clock gt Inputs are 5V tolerant Input registers with little setup time of 2 5ns typ gt JTAG port is multiplexed with user I O 36 I O pins in a VQ44 package in contrast to 34 I O s in other CPLD families with the same package Free powerful VHDL VERILOG schematics simulation design software availlable Webpack 10000 reprogramming cycles 20 years data retention Widely used CPLD lots of information availlable by XILINX Inc and on the web 2 4 Xilinx XCR3064XL CPLD Disadvantages The following items are not relevant in most cases However they should be used as a checklist wheather an application is affected Despite the PLA architecture le
9. VE Wo 22 14 Technical Species 23 A e AAA An TN DI PA MA NP E EEE EE 24 I6 USER S MANUAL ReVISEDUS do eir nia na Eege 25 GOP XCR3064XL USER S MANUAL V0 9 Page 3 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de GOP XCR3064XL USER S MANUAL V0 9 Page 4 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 Introduction The GOP XCR3064XL is a mini module composed of a CPLD device with a PAL GAL compatible 24 pin DIL footprint Many additional features make it useful and flexible 2 1 GOP XCR3064XL Features gt XCR3064XL 10VQ44C CPLD a member of the XILINX CoolRunner XPLA3 family with a 24 or 20 pin PAL GAL compatible DIL footprint Xilinx Parallel Cable IV or Platform USB compatible download connector 14pin 2mm an OHO Elektronik low cost programmer is also availlable Operating voltage from 3 5V to 5 5V Serial resistors in the I O and test connector pins helps to decrease ringing Onboard Clock oscillator with 49 152 MHz for audio or RS232 applications Reverse plug in protection Ared green dual led gt A T pin test connector for probing internal signals or interconnecting several GOP s Solder jumpers for additional ground connections gt Easy to reuse Professional design manufactured on a 4 layer PCB Made in Germany 2 2 GOP XCR3064XL Applications Replacement of PAL GAL devices
10. CONS for 20pin DIL plug 13 FB4MC10 PLD13 tp2 Test connector pin2 CON4 pin2 14 FB4MC11 PLD14 tp3 Test connector pin3 CON4 pin3 15 FBAMC12 LED_R tp4 Test connector pin4 CON4 pin4 Red led of the duo led 0 gt led off 1 gt led on 16 GND Power GND Connection to the GND Layer of the PCB 17 VCC Power VCC Power supply 3 3V from regulator TPS76333 18 FB3MC13 LED G tp5 Test connector pin5 CONA pin4 Green led of the duo led 0 gt led off 1 gt led on 19 FB3MC12 PLD19 tp6 Test connector pin6 CONA pin6 R46 could be soldered to the 5V supply voltage for generation of an 5V rail on tp6 Use 6800 to 10kQ 20 FB3MC11 PLD20 pin13 Connection to the 24pin DIL plug to pin13 via serial CONI pin13 resistor Not used for the 20pin DIL plug 21 FB3MC10 PLD21 pin14 Connection to the 24pin DIL plug to pin14 via serial CONI pin14 resistor Not used for the 20pin DIL plug 22 FB3MC9 PLD22 pin15 Connection to the 24pin DIL plug to pin15 via serial CON pin15 pin11 resistor Connection to the 20pin DIL plug to pin11 via serial GOP XCR3064XL USER S MANUAL V0 9 Page 14 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de resistor 23 FB3MC4 PLD23 pin16 Connection to the 24pin DIL plug to pin16 via serial CON pin16 pin12 resistor Connection to the 20pin DIL plu
11. GOP XCR3064XL USER S MANUAL V 0 9 OHO Elektronik www oho elektronik de Author M Randelzhofer OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO Elektronik Michael Randelzhofer Rudolf Diesel Str 8 85221 Dachau Germany WEB www oho elektronik de EMAIL info oho elektronik de Phone 49 8131 339230 FAX 49 8131 339294 2005 OHO Elektronik Michael Randelzhofer All rights reserved Disclaimer Under no circumstances OHO Elektronik Michael Randelzhofer is liable for consequential costs losses damages lost profits Any schematics pcb or program parts are under the copyright of OHO Elektronik Michael Randelzhofer and can only be reproduced by permission of this company The contents of this USER S MANUAL are subject to change without notice However the main changes are listed in the revision table at the end of this document Products of OHO Elektronik Michael Randelzhofer are not designed for use in life support systems where malfunction of these products could result in personal injury The products of OHO Elektronik Michael Randelzhofer are intended for use in a laboratory test environment only They can generate radio frequency energy depending on the downloaded design and application which can disturb local radio or TV equipment and so they have not been tested to be CE compliant If you encounter any technical problems or mistakes in this docum
12. ast amount of product terms per macrocell of all Xilinx CPLD families gt Flipflops can not clock on both edges like CoolRunner ll No global tristate net or set reset net gt In rare cases reprogramming is only possible if no running clocks are applied to any CPLD pin GOP XCR3064XL USER S MANUAL V0 9 Page 6 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 5 GOP XCR3064XL Board Picures Top And Bottom View E ray Whi TT 14 MET n e j 3 gt y a oe AN l ER E xd s kees LEER NN 6 LEI 1 GE uM RH GA ei H em C OM J a Zeg Ir LESE 39 EE ES DU DU n p E 4 we e 55 GIL Silke ECK A X Lax d GOP XCR3064XL USER S MANUAL V0 9 Page 7 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 6 GOP XCR3964XL Board In A Lab Environment GOP XCR3064XL USER S MANUAL V0 9 Page 8 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 GOP XCR3964XL Board Overview 2mm 14pin JTAG PORT CON2 00000090 00000090 le Gin e 2 54mm 24 Pin nd DIL M 9 socket 9 PLUG o JP1 JP2 JP3 O CoN E E E e BH E E e Access y Solder Jumper e To 22 e For Additional Ground 2 4 CPLD Connections ee e P
13. d XCR3064XL 10VQ44 CPLD Pinout Table CPLD pin Schema UCF port Pin function net name 24pin 1 Comment 2 routed to 20 pin 1 FB2MC9 TDI ptdi Dual function pin JTAG port TDI or user I O TDI If PORT EN 1 force JTAG port otherwise user UO 2 FB2MC10 PLD2 pin4 Connection to the 20 24pin DIL plug to pin4 via serial CONI pin4 pin4 resistor 3 FB2MC11 PLD3 pin5 Connection to the 20 24pin DIL plug to pin5 via serial CONI pin7 pin5 resistor 4 PORT EN PORT EN If PORT EN 1 force JTAG port otherwise user I O 5 FB2MC14 PLD5 pin6 Connection to the 20 24pin DIL plug to pin6 via serial CON1 pin6 pinG resistor 6 FB2MC15 PLD6 pin7 Connection to the 20 24pin DIL plug to pin7 via serial CON1 ping pin7 resistor 7 FB4MC1 TDI ptms Dual function pin JTAG port TMS or user I O TMS If PORT EN 1 force JTAG port otherwise user I O 8 FB4MC2 PLD8 pint 1 Connection to the 24pin DIL plug to pin11 via serial CON1 pin11 resistor Not used for the 20pin DIL plug 9 VCC Power VCC Power supply 3 3V from regulator TPS76333 10 FBAMCA PLD10 pin8 Connection to the 20 24pin DIL plug to pin8 via serial CON1 ping pin8 resistor 11 FBAMC5 PLD11 pin9 Connection to the 20 24pin DIL plug to pin9 via serial CON1 pin9 pin9 resistor 12 FB4MC9 PLD12 pinfO Connection to the 24pin DIL plug to pin10 via serial CONI pin10 resistor Short to GND by
14. ent please contact mrandelzhofer oho elektronik de serious hints are very appreciated Trademarks All brand names or product names mentioned are trademarks or registered trademarks of their respective holders PAL and GAL are registered trademarks of Lattice Semiconductor Corp GOP_XCR3064XL USER S MANUAL V0 9 Page 2 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 1 Table of contents l Tabl of Contents RR 3 2 rale TOM TES mmm 5 2 SOP ie xcii T 5 2 2 GOP IT EA pa EE 5 2 3 Xilinx XCR3064XL CPLD Feature m 6 ZA Xilinx XCR3064XL CPLD Disadvantages ani mamanya inna 6 2 5 GOP_XCR3064XL Board Picures Top And Bottom View T 2 6 GOP XCR3964XL Board In A Lab Environmetnt 8 2 GOP XCR3964XL Board E 9 CS PEE Ori elio m T NU ANA NN 9 DC NEM dU bu qo sim 10 PUWEE SUD E 11 33 PAL GAL Emulation Of 24 Pin And 20 Pin Devices oooco Woooommuwaws 11 4 CPLD DESIRE Spot on T A Mme 12 5 GOP XCR3064XL I O Voltage Levels nana an hasan 13 6 Detailed XCR3064XL 10VQ44 CPLD Pinout Table 14 A CONIL DIL Connector Pino t KEE 17 B CON4 Test Connector Pino t Table aio iii 18 9 CONS Configuration Jumper OPIO na RR BR BN 18 10 DIL Connector bayouh o 19 11 Schematics samba anu BAR REM 20 12 Mod le Layout Top VIEW emban lid 21 I3 Module Kater
15. g to pin12 via serial resistor 24 GND Power GND Connection to the GND Layer of the PCB 25 FB3MC2 PLD25 pin17 Connection to the 24pin DIL plug to pin17 via serial CON pin17 pin13 resistor Connection to the 20pin DIL plug to pin13 via serial resistor 26 FB3MC1 TCK ptck Dual function pin JTAG port TCK or user I O TCK If PORT EN 1 force JTAG port otherwise user I O 27 FB1MC15 PLD27 pinf8 Connection to the 24pin DIL plug to pin18 via serial CON pin18 pin14 resistor Connection to the 20pin DIL plug to pin14 via serial resistor 28 FB1MC14 RC_IN rcin Input to an RC network this is for demonstration that rc RC network oscillators do not work reliably with XCR3064XL but on CoolRunner ll devices with Schmitt Trigger inputs 29 VCC Power VCC Power supply 3 3V from regulator TPS76333 30 FB1MC11 PLD30 pin19 Connection to the 24pin DIL plug to pin19 via serial CON pin19 pin15 resistor Connection to the 20pin DIL plug to pin15 via serial resistor 31 FB1MC10 PLD31 pin20 Connection to the 24pin DIL plug to pin20 via serial CON1 pin20 pin16 resistor Connection to the 20pin DIL plug to pin16 via serial resistor 32 FB1MC9 TDO ptdo Dual function pin JTAG port TDO or user I O TDO If PORT EN 1 force JTAG port otherwise user UO 33 FB1MC8 PLD33 pin21 Connection to the 24pin DIL plug to pin21 via serial CONI pin21 pin17 resistor Connection to the 20pin DIL plug to pin17 via serial resistor
16. ins 1 3 2mm 4pin 0 3 GAP 6 Jumper Block CON3 1 2 20 Pin Ground 3 4 XOSC Supply 2 54mm 7pin Test Connector CON4 3 1 NO Distribution 22 Xilinx XCR3064XL 10VQ44C CPLD I O s are wired to a 24 pin DIL socket plug CON1 on the bottom of the module through 220 serial resistors These resistors primarily reduces ringing Pin 1 and 2 of the DIL plug accesses global clock nets CLKO and CLK1 inside the CPLD 5 remaining I O s are availlable to the front side test connector CON4 also through 220 series resistors GOP_XCR3064XL USER S MANUAL V0 9 Page 9 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de Pin 2 of CON4 has a pullup resistor to VCC R40 A 2 54mm jumper can be used to short pin 2 to GND at pin 1 of the testconnector as a simple status input Pin 7 of the testconnector has an unmounted pullup resistor to the 5V supply voltage If a 5V rails is needed on this pin a resistor between 6800 and 10kQ could be soldered on position R46 Please note that 5V rails can be produced only by tristating outputs A logical 1 output on an XCR3064XL is clamped to VCCIO which is 3 3V on this module A crystal oscillator with an output frequency of 49 152MHz is connected to another I O of the CPLD This oscillator can be disabled completely by removing its power supply at jumper block CONS position 3 4 Please note
17. k Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 15 Literature 1 D8012 CoolRunner XPLA3 CPLD Family http direct xilinx com bvdocs publications ds012 pdf 2 DSO17 XCR3064XL 64 Macrocell CoolRunner CPLD http direct xilinx com bvdocs publications ds017 pdf 3 XAPP444 CPLD Fitting Tips and Tricks http direct xilinx com bvdocs appnotes xapp444 pdf 4 TPS76333 Low Power 150mA Low Dropout Linear Regulators http focus ti com lit ds symlink tps76333 paf 5 DS097 Xilinx Parallel Cable IV http direct xilinx com bvdocs publications ds097 pdf 6 DS300 Platform Cable USB http direct xilinx com bvdocs publications ds300 pdf 7 XAPP150 I V Curves for Xilinx FPGA and CPLD Families http direct xilinx com bvdocs appnotes xapp150 pdf 8 XAPP784 Bulletproof CPLD Design Practices http direct xilinx com bvdocs appnotes xapp784 pdf 9 XAPP805 Driving Leds with Xilinx CPLD s http direct xilinx com bvdocs appnotes xapp805 pdf 10 XAPP342 XPLA3 I O Cell Characteristics http direct xilinx com bvdocs appnotes xapp342 pdf GOP XCR3064XL USER S MANUAL V0 9 Page 24 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 16 USER S MANUAL Revisions Version Date Comments V0 9 23 10 2005 Prerelease GOP XCR3064XL USER S MANUAL V0 9 Page 25 of 25
18. ock net CLK1 44 FB2MC3 PLD44 pin3 Connection to the 20 24pin DIL plug to pin3 via serial CON1 pin3 pin3 resistor FB1MC11 denotes function block1 macrocell 11 There is an UCF file definition for 24pin and another one for 20pin device usage GOP XCR3064XL USER S MANUAL V0 9 Page 16 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 7 CON1 DIL Connector Pinout Table Pin CPLD pin Schema UCF function net name port Comment routed to name 1 FB2MC16 PLD42 pin1 Connection to the 20 24pin DIL plug to pin1 via serial CONI pin1 pint resistor Access to global clock net CLKO 2 FB2MC2 PLD43 pin2 Connection to the 20 24pin DIL plug to pin2 via serial CON pin2 pin2 resistor Access to global clock net CLK1 3 FB2MC3 PLD44 pin3 Connection to the 20 24pin DIL plug to pin3 via serial CON1 pin3 pin3 resistor 4 FB2MC10 PLD2 pin4 Connection to the 20 24pin DIL plug to pin4 via serial CON1 pin4 pin4 resistor 5 FB2MC11 PLD3 pin5 Connection to the 20 24pin DIL plug to pin5 via serial CONI pin7 pin5 resistor 6 FB2MC14 PLD5 pin6 Connection to the 20 24pin DIL plug to pin6 via serial CON1 pin6 pin6 resistor 7 FB2MC15 PLD6 pin7 Connection to the 20 24pin DIL plug to pin7 via serial CON1 ping pin7 resistor 8 FB4MC4 PLD10 pin8 Connection to the 20 24pin DIL plug to pin8 via serial
19. that this clock must be routed inside the CPLD to a global clock net to insure proper synchronous circuit operation Furthermore 2 I O s are connected to a dual led having a red and a green chip in it s case These leds can be lighted by driving a logical 1 to these I O s Finally 2 I O s are connected to an RC network for demontration purpose A simple RC oscillator can be evaluated However it can be observed that an XCR3xxx RC oscillator does t produce a stable clock If a global clock net wants to be accessed by a macrocell removing of C8 of the RC filter is recommended 3 2 JTAG Port The CPLD JTAG signals are routed directly to the Xilinx standard 2mm 14pin JTAG port connector CON2 supported from the Parallel cable IV and Platform USB cable see 5 6 Pin 1 of the port is connected to GND which allows high speed programming with the above cables Pins 12 and 14 of the JTAG port are not used on this module Pin 13 is used to enable the JTAG port of the CPLD If this pin is low the port is enabled Since the JTAG pins also can be l O s a logical high on pin 13 enables the GOP XCR3064XL module to communicate with the PC with an SPI interface Therefore an adaptor must be used between a download cable type III and the module to set pin 13 to 1 Please notice the pin orientation of JTAG port CON2 CONTI GOP_XCR3064XL USER S MANUAL V0 9 Page 10 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221
20. this CPLD family It is remarkable that because of the 5V tolerant inputs there is no diode between the inputs and VCC So the devices can be used in hot plugging applications The XCR3xxxXL series outputs delivers 2 7V 3 3V voltage levels only The GOP XCR3064XL module supports 3 3V only The CPLD drives a low output 0 with a maximum of 0 4V at 8mA sink current If the CPLD sources current on a logical 1 output the voltage is guaranteed to be 2 4V minimum at 8mA So sourcing and sinking current is symmetrical If more output current is desired 7 shows appropriate I V curves Another important fact is that a bidirectional UO with a pullup to 5V can not drive to 5V on the output but 3 3V only The output driver stage clamps the voltage to VCCIO in that case As an example driving bright leds with relatively high current consumption is best done by sinking current or in other words the cathode of the led should be connected to a CPLD UO the anode to the led s supply voltage If the leds have forward voltages beyond 3 3V e g blue leds the 5V tolerance can be used to completely turn off the led by tristating the output For driving leds with CPLD s see also 9 Please consider that there are 220 series resistors between GOP XCR3064XL pin connections and the CPLD GOP XCR3064XL USER S MANUAL V0 9 Page 13 of 25 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 6 Detaile
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