TB-FMCH-HDMI2 Hardware User Manual 1 IN/OUT +
Contents
1. FMC HPC FPGA ENC 0 HDMI 0 TX TX 0_DI35 0 TX 0 0 2 TX 0_VS HS DE TX 0 SCL LA 33 00 P N TX 0 SDA HA 23 00 P N TX 0 DSD 5 0 CECHO CLK 3 0 M2C P N TX 0_DSDCLK TX 0_SPDIF HEACHO TX 0 MCLK me TO SISO 500254 1927 TX 0_SCLK TX O LRCLK 8 SCL 0 PD DDCOSDA CLK TXHO INT CLK T 8 255057 SYSCLK P TX O SCL SDA 503227000 ADVIBII KC5032C12 000 8 5000 GND 5 TX 0 HPD IO 2500 ASP 134488 01 5 41 LED 7 0 ENC 1 HDMI 1 TX 7 TX D 35 0 TX 1_C TX 0 0 2 P dit DSW 7 VS HS DE TX 1_DDCA SCL 77 TX 1 DDCA SDA D RSW 3 TX 1_DSD 5 0 CECHI m 77 TX 1 DSDCLK JTAG TX 1_SPDIF HEAC 1 FPGA TCK TMS TDI TDO a HPD 1 500254 1927 PROM TX 1_SCLK FPGA D 7 0 TX 1_LRCLK 8 DDOFESOE FPGA DONE 1 PD 8 DDOI SDA FPGAJNITB TX 1INT CLK T 8 pporsv FPGA PROGB TX 1_SCL SDA Pomen FPGA CCLK ADVIBII KC5032C12 000 8 DDOTGND a XCF16PFSG48C2. DDC SCL Figure 6 2 DDC Connection Structure Through select DDC connection Through connect RX board J4 and TX board J1 or RX board J2 and TX board J3 using an attached cable 1 00 TOKYO ELECTRON DEVICE LIMITED 52 inreviun 7 Default Switch Setting Figure 7 1 shows default TB FMCH HDMI2 RX switch settings portions enclosed by dotted lines JP7 JP12 10 JP11 en JP1 III JP17 15 JP13 Figure 7 1 TB FMCH HDMI2 RX Default Switch Settings component side Table 7 1 TB FMCH HDMI2 RX Default Settings JP pin Silk No Initial Setting Function SCLO 1 2 HDMI 2 3 FPGA SDAO 1 2 HDMI 2 3 FPGA DDCO 5 1 2 Normal 2 3 Through DDCO HPD 1 2 Normal 2 3 Through DDCO SDA 1 2 Normal 2 3 Through DDCO SCL 1 2 Normal 2 3 Through DDCO GND 1 2 Normal 2 3 Through 1 2 3 4 5 6 7 8 SCL1 1 2 2 3 FPGA SDA1 1 2 HDMI 2 3 FPGA DDC1_5V 1 2 Normal 2 3 Through DDC1 HPD 1 2 Normal 2 3 Through DDC1 SDA 1 2 Normal 2 3 Through DDC1 SCL 1 2 Normal 2 3 Through DDC1 GND 1 2 Normal 2 3 Through 12VIN SEL 1 2 FMC connector 2 3 Externa
3. Cr6 R6 Cr7 R7 Cr8 R8 Cr9 R9 Cr10 R10 Cr11 R11 LA31_N LVCMOS25 TX 0_P34 signal FMC to FPGA LA32_N LVCMOS25 TX 0_P35 signal FMC to FPGA LA33_N LVCMOS25 Unused CLK2_M2C_P LVCMOS25 Unused CLK3_M2C_P LVCMOS25 Unused P LVCMOS25 Unused HA01 CC LVCMOS25 Unused HA02 P LVCMOS25 Unused HA03 P LVCMOS25 Unused HA04 P LVCMOS25 Unused HA05 P LVCMOS25 Unused gt ae 1 00 TOKYO ELECTRON DEVICE LIMITED 43 inreviun Pin 2 Description HAO06 P LVCMOS25 Unused HA07 P LVCMOS25 Unused HAO08 P LVCMOS25 Unused 09 P LVCMOS25 Unused HA10 P LVCMOS25 Unused HA11 P LVCMOS25 Unused HA12 P LVCMOS25 Unused HA13 P LVCMOS25 Unused HA14 P LVCMOS25 Unused HA15 P LVCMOS25 Unused HA16 P LVCMOS25 Unused HA17 P CC LVCMOS25 Unused HA18 P LVCMOS25 Unused HA19 P LVCMOS25 Unused HA20 P LVCMOS25 Unused HA21 P LVCMOS25 Unused HA22 P LVCMOS25 Unused HA23 P LVCMOS25 Unused CLK2 M2C N LVCMOS25 Unused CLK3 M2C N LVCMOS25 Unused 00 CC LVCMOS25 Unused HA01 CC LVCMOS25 Unused 02 LVCMOS25 Unused LVCMOS25 Unused 04 LVCMOS25 Unused 05 LVCMOS25 Unused 06 LVCMOS25 Unused HAO07 LVCMOS25 Unused HAO08 LVCMOS25 Unused
4. ale 20 4 9 Control 21 4 9 1 ADV7612 Configuration ROM selection 21 4 10 FPGA PIrvAssignment ista du dedu d ua 22 4 11 FPGA Output Data Phase 29 4 12 Audio I2S format incen Lee tee aaa od esi Lue ave bua SELLER Que LIE PRA 29 4 13 Size A 30 44371 20 IMAGE e saa S aiar 30 413 2 3D Image SER nnb rata d 30 5 2 77 31 5 1 Block MIB e rz To 31 5 2 External View of the Board ete t de te ERN eis 32 5 3 Board Specification ii 33 5 4 Power Supply to the 34 5 5 35 5 6 AE 36 5 7 Other Interfaces 39 5 7 1 JTAG 39 5 7 2 General Purpose Clock Interface 2 2 11 39 5 8 LED 40 5 9 Control 8 41 5 9
5. 5 Ww gt Color Space RGB Color Depth 8bit Color Space RGB Color Depth 10bit Color Space RGB Color Depth 12bit 1 00 TOKYO ELECTRON DEVICE LIMITED 41 inreviun 5 10 Pin Assignment Table 5 8 shows the FPGA pin assignment In case of 8 bit signal format active bits are assigned to MSB 8 bit of each RGB pin of FMC LSB 2 bit are always 2 b00 in 8 bit signal format Table 5 8 FPGA Pin Assignment Pin Name 3 Spec Description CLKO M2C P LVCMOS25 TX 0_DCLK Signal to FPGA CLK1 M2C P LVCMOS25 Unused 00 P CC LVCMOS25 TX 0_VSYNC Signal FMC FPGA LAO1 P CC LVCMOS25 TX 0_HSYNC Signal FMC to FPGA LA02_P LVCMOS25 TX 0_DE Signal FMC to FPGA LA03_P LVCMOS25 TX 0_DO Signal FMC to FPGA Cb0 B0 04 P LVCMOS25 TX 0_D1 Signal to FPGA Cb1 B1 05 P LVCMOS25 D2 Signal FMC to FPGA Cb2 B2 LAO6 P LVCMOS25 D3 Signal FMC to FPGA Cb3 B3 07 LVCMOS25 D4 Signal to FPGA Cb4 B4 08 P LVCMOS25 TX 0_D5 Signal FMC to FPGA Cb5 B5 09 P LVCMOS25 Cb6 B6 LA10 P LVCMOS25 D7 Signal to FPGA Cb7 B7 11 P LVCMOS25 TX 0_D6 Signal FMC to FPGA TX 0_D8 Signal FMC to FPGA Cb8 B8 LA12 P LVCMOS25
6. TX 0_D9 Signal FMC to FPGA Cb9 B9 LA13 P LVCMOS25 TX 0_D10 Signal FMC to FPGA Cb10 B10 LA14 P LVCMOS25 TX 0_D11 Signal FMC to FPGA Cb11 B11 LA15 P LVCMOS25 TX 0_D12 Signal FMC to FPGA YO G0 LA16_P LVCMOS25 TX 0_D13 Signal FMC to FPGA Y1 G1 LA17_P_CC LVCMOS25 TX 0_D14 Signal FMC to FPGA Y2 G2 LA18_P_CC LVCMOS25 TX 0_D15 Signal FMC to FPGA Y3 G3 LA19 P LVCMOS25 TX 0_D16 Signal FMC to FPGA Y4 G4 LA20 P LVCMOS25 TX 0_D17 Signal FMC to FPGA Y5 G5 LA21 P LVCMOS25 TX 0_D18 Signal FMC to FPGA Y6 G6 LA22 P LVCMOS25 TX 0_D19 Signal to FPGA Y7 G7 LA23 P LVCMOS25 TX 0_D20 Signal FMC to FPGA Y8 G8 LA24 P LVCMOS25 TX 0_D21 Signal FMC to FPGA Y9 G9 LA25 P LVCMOS25 TX 0_D22 Signal FMC to FPGA Y10 G10 LA26_P LVCMOS25 TX 0_D23 Signal FMC to FPGA Y11 G11 LA27 P LVCMOS25 TX 0_D24 Signal FMC to FPGA CrO RO LA28 P LVCMOS25 TX 0_D25 Signal FMC to FPGA Cr1 R1 LA29 P LVCMOS25 TX 0_D26 Signal FMC to FPGA Cr2 R2 LA30 P LVCMOS25 TX 0_D27 Signal FMC to FPGA Cr3 R3 LA31 P LVCMOS25 TX 0_D28 Signal FMC to FPGA Cr4 R4 LA32 P LVCMOS25 gt TX 0_D29 Signal FMC to FPGA Cr5 R5
7. e e ERE gt Li c I lt gt M 5 LE ed T TT Bm ae ole 1 e z e 20 50 Figure 5 4 TB FMCH HDMI2 TX Board Dimensions 1 00 TOKYO ELECTRON DEVICE LIMITED 33 inreviun 5 4 Power Supply to the Board Figure 5 5 shows the TB FMCH HDMI2 TX power supply structure 12V IN LT3503EDCB VCC_5V i ADG702 0 001mAx2 0 002mA 134mA 0 671W LT3568EDD VCC 12V _ 34 FPGA VCCINT 503mA 349 LT3503EDCB VCC_3 3V clc C DERE m FPGA VCAUX 68mA FPGA_VCCIO 311mA ADV7511 x2 0 6 I gt _ 1 437mA KC3225A 6mA x3 18mA 144271 1 1326 004 I XCF16 VCCIO 40mA e St i ati I LT3503EDCB VCC_2 5V Wo eee tea i _ FPGA 26 663 1 6575W LTC3026EMSE VCC 1 8V0 e 7511 19 1 XCFIGVCCINT 10mA 1 LTC3026EMSE VCC 1 8V1 Figure 5 5 TB FMCH HDMI2 TX Power Supply Structure 1 00 TOKYO ELECTRON DEVICE LIMITED 34 inreviun 5 5 HDMI Transmitter
8. ie ne e Pe e d di ded 16 Table 4 4 FMC Connector Pin Assignment 17 Table 4 5 JTAG Connector lia 19 JTable 4 6 LED Status C 20 Table 4 7 SWC ES uu tet entr dal ine 21 Table 4 8 ADV7612 configuration 21 Table 4 9 FPGA Pin 22 Table 5 1 HDMI Connector transmit 35 Table 5 2 4P3 Jumper Setting dd Gee 36 Table 5 3 FMC Connector Pin 37 Ro E EI 39 Table 5 5 LED 40 Table 5 6 Switch Function ra eril 41 Table 5 7 ADV7511 configuration 41 Table 5 8 FPGA Pin Assignment 42 Table 6 1 DDC Jumper Setting Normal sse 51 Table 6 2 DDC Jumper Setting ThFOUGhN emen 52 Table 7 1 TB FMCH HDMI2 RX Default Settings JP pin 53 Table 7 2 TB FMCH HDMI2 RX Default Setting 5 54 Table 7 3 TB FMCH2 TX Default Settings JP 55 Table 7 4 TB FMCH HDMI2 TX Default Switch Settings 56 Table g Seting Example iini d rr ed ert P sir Eb ir td 57 1 00
9. HPD1O 3 5561 T SHLDI 9 XC6SLX45 3FGG484C Figure 5 1 TB FMCH HDMI2 TX Block Diagram Main Function 1 HDMI Transmit FPGA to ADV7511 FMC Connector Interface FMC HPC to FPGA JTAG Interface General purpose Clock Interface 27MHz General purpose Switch General purpose LED DDC Connection Normal Through Doo PF O N Note This design uses HDMI 0 TX only Because of limited pin number of FMC LPC Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 31 TB FMCH HDMI2 Hardware User Manual 1 IN OUT Audio 5 2 External View of the Board Figures 5 2 and 5 3 show the external view of the TB FMCH HDMI2 TX board 4 Transmitter Connector Figure 5 2 TB FMCH HDMI2 TX component side ne SE wh qe 5 NE FMC HPC Figure 5 3 TB FMCH HDMI2 TX solder side 1 00 TOKYO ELECTRON DEVICE LIMITED 74 eee eee YT LT 32 inreviun 5 3 Board Specification Figure 5 4 shows the TB FMCH HDMI2 TX board specification External Dimensions W 160mm x H 69mm Number of Layers 8 Layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 Ln eoo 0 ooo ooo e ceo rui D as se e B E
10. 18 inreviun 4 7 Other Interfaces The board also has the following interfaces 4 7 1 EEPROM Interface 2 interface used to control the EEPROM from the FPGA EEPROM device 24LCS22A SN Micro Chip 4 7 2 JTAG Interface JTAG connector for FPGA configuration JTAG connector 87832 1420 Molex Table 4 5 JTAG Connector 4 7 3 General Purpose Clock Interface General purpose clock for FPGA 27MHz crystal oscillator KC5032C027 0000C30E00 Kyocera 1 00 TOKYO ELECTRON DEVICE LIMITED 19 inreviun 4 8 LED Status Table 4 6 shows the onboard LEDs Circuit Table 4 6 LED Status Purpose Description DS1 General purpose LEDO RX0 I2C config state Off CFG done On CFG active DS2 General purposeLED1 RX0 I2C read back Off Error On No error DS3 General purposeLED2 DS4 General purposeLED3 RXO Video status LED2 OFF LED3 OFF 2D Video LED2 ON LED3 OFF 3D SideBySide LED2 OFF LED3 ON 3D TopAndBottom LED2 ON LED3 ON 3D FramePacking LED4 General purposeLED4 Unused On LED5 General purposeLED5 RX0 Input video image clock monitor Flashing Clock Off No clock LED6 General purposeLED6 Unused On LED7 General purposeLED7 System reset monitor On Reset active Off Reset released HPDO RXO hot plug display On Connected state HPD1 RX1 hot
11. CC 02 P 02 P 04 P GND 02 GND 2 04 LAO3 P GND 07 P GND GND LAO3 N LAO4 P 07 06 P 8 P GND 04 GND 06 HAO8_N LA08_P GND HA11_P GND GND LAO8 N 07 P HA11 HA10 P HA12 P GND LA07_N GND HA10_N HA12_N LA12 P GND HA14 P GND GND LA12 LA11 P HA14 N 17 P CC HA15 P GND LA11 GND HA17 CC HA15 N LA16 P GND HA18 P GND GND LA16 N LA15 P HA18 N HA21 P HA19 P GND LA15 N GND HA21 N HA19 N LA20 P GND HA22 P GND GND LA20 N LA19 P 22 HA23 P 02 P GND LA19 N GND HA23 N LA22 P GND HB01_P GND GND LA22_N LA21_P HB01 P CC HB04 P GND LA21 N GND HBOO N CC 04 25 P GND P GND GND LA25 N LA24 P 07 06 08 GND LA24 N GND HB06 N CC 08 LA29 P GND HB11 P GND GND LA29 N LA28 P HB11_N HB10 P HB12 P GND LA28 N GND HB10 N HB12 N LA31 P GND HB15 P GND GND LA31 N LA30 P HB15 N HB14 P 16 P GND LA30 N GND HB14 N HB16 N
12. 1 00 TOKYO ELECTRON DEVICE LIMITED 55 inreviun Table 7 4 TB FMCH HDMI2 TX Default Switch Settings DSW RSW 2 OO N gt Silk No Default Setting Function S1 1 OFF ADV7511 config ROM selection 51 2 OFF Please see Table 5 7 51 3 OFF 51 4 OFF 51 5 Unused to ON 51 6 Unused to ON 51 7 OFF Unused set to ON 51 8 Unused to ON 52 0 Unused to 0 1 00 TOKYO ELECTRON DEVICE LIMITED 56 inreviun 8 Usage Example Figure 8 1 shows a usage example Be careful about the jumper setting of the TB 6S LX150T IMG2 main board If the image is not output push the S3 of the TB FMCH HDMI2 RX or TB FMCH HDMI2 TX for only a short period of time idi TB FMCH HDMI2 RX Pi 3 SE TB 6S 1 X150T IMG2 E x it T TB FMCH HDMI2 RX connects to TB FMCH HDMI2 RX are initial setting JP6 JP7 5 6 Short JP1 122 Short Figure 8 1 Usage Example Table 8 1 Setting Example Silk No Setting Function Bank3 voltage setting 2 5V 3 3V FMC LPC2VAD J voltage setting 2 5V 3 3V none Two jumpers must be always the same voltage setting 2 5V 3 3V FMC LPC1 voltage setting 2 5V 3 3V none Two jumpers must be always the same Note The bold characters are the sett
13. HA11_P GND GND LAO8 N 07 P HA11 HA10 P HA12 P GND LA07_N GND HA10_N HA12_N LA12 P GND HA14 P GND GND LA12 LA11 P HA14 N 17 P CC HA15 P GND LA11 GND HA17 CC HA15 N LA16 P GND HA18 P GND GND LA16 N LA15 P HA18 N HA21 P HA19 P GND LA15 N GND HA21 N HA19 N LA20 P GND HA22 P GND GND LA20 N LA19 P 22 HA23 P 02 P GND LA19 N GND HA23 N LA22 P GND HB01_P GND GND LA22_N LA21_P HB01 P CC HB04 P GND LA21 N GND HBOO N CC 04 25 P GND P GND GND LA25 N LA24 P 07 06 08 GND LA24 N GND HB06 N CC 08 LA29 P GND HB11 P GND GND LA29 N LA28 P HB11_N HB10 P HB12 P GND LA28 N GND HB10 N HB12 N LA31 P GND HB15 P GND GND LA31 N LA30 P HB15 N HB14 P 16 P GND LA30 N GND HB14 N HB16 N LA33 P GND HB18 P GND GND LA33 N LA32 P HB18 N HB17 P CC HB20 P GND LA32 N GND 17 CC 20 GND VIO B M2C GND VADJ Rev 1 00 GND VADJ GND TOKYO ELECTRON DEVICE LIMITED VIO B M2C
14. LA33 P GND HB18 P GND GND LA33 N LA32 P HB18 N HB17 P CC HB20 P GND LA32 N GND 17 CC 20 GND VIO B M2C GND VADJ Rev 1 00 GND VADJ GND TOKYO ELECTRON DEVICE LIMITED VIO B M2C 38 inreviun 5 7 Other Interfaces The board also provides the following interfaces 5 7 1 JTAG Interface The board has a JTAG connector FPGA configuration JTAG Connector Molex s 87832 1420 Table 5 4 JTAG Connector Signal Name 5 7 2 General Purpose Clock Interface The board has a general purpose clock on FPGA 27MHz crystal oscillator KC5032C027 0000C30E00 Kyocera 1 00 TOKYO ELECTRON DEVICE LIMITED 39 inreviun 5 8 LED Status Table 5 5 shows the onboard LED function Circuit Table 5 5 LED Status Purpose Description DS3 General purpose LEDO TX0 I2C config state Off CFG done On CFG active DS4 General purpose LED1 TX0 I2C read back Off Error On No error DS5 General purpose LED2 DS6 General purpose LED3 TXO Video status LED2 OFF LED3 OFF 2D Video LED2 LED3 OFF 3D SideBySide LED2 OFF LED3 ON 3D TopAndBottom LED2 ON LED3 ON 3D FramePacking LED4 General purpose LED4 Unused On LED5 General purpose LED5 TXO input video image clock monitor Flashing Active cl
15. TB FMCH HDMI2 Hardware User Manual 1 IN OUT Audio inreviun TB FMCH HDMI2 Hardware User Manual 1 IN OUT Audio support Rev 1 00 1 00 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History Version Date Description Publisher Rev 1 00 2011 03 29 Initial release Yoshioka 1 00 TOKYO ELECTRON DEVICE LIMITED 2 inreviun Table of Contents 1 Related Documents and Board Accessories 1 9 2 OVERVIEW 50 M 9 3 10 A TB FMGH HDBMI2 RX antes e ine e n ene RE 11 4 1 Block 7 3 11 4 2 External View of the 12 4 3 Board SpeciflcatlOn 13 4 4 Supplying Power to the Board 14 4 5 A edie iene eed ec eee Ferien Pee 15 4 6 a 16 Other Interfaces 19 4 7 1 EEPROM Interface aaa 19 4 7 2 JTAG Interface iii 19 4 7 3 General Purpose Clock Interface i 19 4 8 5
16. LA33_P LVCMOS25 Unused CLKO M2C N LVCMOS25 Unused CLK1 M2C N Rev 1 00 LVCMOS25 Unused TOKYO ELECTRON DEVICE LIMITED 42 inreviun Description 00 CC LVCMOS25 input video status 0 FPGA to FMC LAO1 N CC LVCMOS25 input video status 1 FPGA to FMC Please see Note LAO2 N LVCMOS25 Unused LAO3 N LVCMOS25 Unused LA04_N LVCMOS25 Unused LAO5 LVCMOS25 Unused LAO6 LVCMOS25 Unused LAO7 LVCMOS25 Unused LAO8 N LVCMOS25 Unused LAO9 N LVCMOS25 Unused LA10 N LVCMOS25 Unused LA11 N LVCMOS25 Unused LA12 N LVCMOS25 Unused LA13 N LVCMOS25 Unused LA14 N LVCMOS25 Unused LA15 N LVCMOS25 Unused LA16 N LVCMOS25 Unused LA17 N CC LVCMOS25 Unused LA18 N CC LVCMOS25 Unused LA19 N LVCMOS25 TX 0_MCLK signal FMC to FPGA LA20 N LVCMOS25 SCLK signal FMC to FPGA LA21 N LVCMOS25 APO signal FMC to FPGA LA22 N LVCMOS25 signal FMC to FPGA LA23 N LVCMOS25 signal FMC to FPGA LA24 N LVCMOS25 signal FMC to FPGA LA25 N LVCMOS25 APA signal FMC to FPGA LA26 N LVCMOS25 AP5 signal FMC to FPGA LA27 N LVCMOS25 TX 0_P30 signal to FPGA LA28 N LVCMOS25 TX 0_P31 signal to FPGA LA29 N LVCMOS25 TX 0_P32 signal FMC to FPGA LA30_N LVCMOS25 TX 0_P33 signal FMC to FPGA
17. O O O O O O O O O O O O O O O O O O LVCMOS33 TX 1 serial clock FPGA to TX TX 1_SDA LVCMOS33 TX 1 serial data FPGA to from TX RSWO LVCMOS33 Rotary switch 0 RSW1 Rev 1 00 LVCMOS33 Rotary switch 1 TOKYO ELECTRON DEVICE LIMITED 47 inreviun Description RSW2 LVCMOS33 Rotary switch 2 RSW3 LVCMOS33 Rotary switch 3 DSWO LVCMOS33 DIP switch 0 DSW1 LVCMOS33 DIP switch 1 DSW2 LVCMOS33 DIP switch 2 DSW3 LVCMOS33 DIP switch 3 DSW4 LVCMOS33 DIP switch 4 DSW5 LVCMOS33 DIP switch 5 DSW6 LVCMOS33 DIP switch 6 DSW7 LVCMOS33 DIP switch 7 LEDO LVCMOS33 LEDO LED1 LVCMOS33 LED1 LED2 LVCMOS33 LED2 LED3 LVCMOS33 LED3 LED4 LVCMOS33 LED4 LED5 LVCMOS33 LED5 LEDG LVCMOS33 LED6 LVCMOS33 Note Input Video Status 1 0 This status shows 2D 3D video format 1 0 00 1 0 01 1 0 10 1 0 11 Rev 1 00 2D video video SideBySide format 3D video TopAndBottom format 3D video FramePacking format LED7 TOKYO ELECTRON DEVICE LIMITED 48 inreviun 5 11 Input Data Phase Figure 5 6 shows the input data phase of t
18. The HDMI connector uses MOLEX s 5002541927 The HDMI transmitter uses Analog Devices s ADV7511KSTZ P The following device is used for ESD protection ESD protection Semtech s RCLAMP0524 and RCLAMP0504 Table 5 1 shows the HDMI connector pin assignment Table 5 1 HDMI Connector transmit side Name Description TMDS DATA2 TMDS Transmit Data 2 TMDS SHLD2 TMDS Transmit Data 2 Shield TMDS DATA2 TMDS Transmit Data 2 TMDS DATA1 TMDS Transmit Data 1 TMDS SHLD1 TMDS Transmit Data 1 Shield TMDS DATA1 TMDS Transmit Data 1 TMDS TMDS Transmit Data 0 TMDS SHLDO TMDS Transmit Data 0 Shield TMDS DATAO TMDS Transmit Data 0 TMDS CLK TMDS Transmit Clock TMDS CLK SHLD TMDS Transmit Clock Shield TMDS TMDS Transmit Clock CEC CEC Signal UTILITY HEAC HEAC Signal DDC_SCL DDC Serial Clock DDC_SDA DDC Serial Data DDC CEC GND DDC CEC Ground DDC_ 5V 5V HPD HEAC Rev 1 00 Hot Plug Detection HEAC Signal TOKYO ELECTRON DEVICE LIMITED 35 inreviun 5 6 Connector connector connecting to the High Pin Count uses SAMTEC s ASP 134488 01 Power to the TB FMCH HDMI2 TX is supplied from a 12V on the main board An external power source can also be used Table 5 2 shows JP3 jumper setting for power supply Table 5 2 JP3 Jumper Setting
19. 125 Format Audio Timing Chart 1 00 TOKYO ELECTRON DEVICE LIMITED 29 inreviun 4 13 Image Size 4 13 1 2D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format and part of secondary format 1080p 60Hz Supported image size 640x480p 59 94 60Hz 1280x720p 59 94 60Hz 1920x1080i 59 94 60Hz 720x480p 59 94 60Hz 720 1440 x480i 59 94 60Hz 1280x720 50Hz 1920x1080i 50Hz 720x576p 50Hz 720 1440 x576i 50Hz 1920x1080p 59 94 60Hz 1920x1080p 50Hz 4 13 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported image size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing Side by Side Half 1920x1080i 50Hz Frame Packing Side by Side Half 1920x1080p 23 98 24Hz Frame Packing Side by Side Half Top and Bottom 1920x1080p 29 97 30Hz Frame Packing Top and Bottom 1920x1080p 59 94 60Hz Top and Bottom 1920x1080p 50Hz Top and Bottom 1 00 TOKYO ELECTRON DEVICE LIMITED 30 inreviun 5 TB FMCH HDMI2 TX 5 1 Block Diagram Figure 5 1 shows a TB FMCH HDMI2 TX block diagram The FMC HPC connector is mounted on the solder side of the board
20. Detect Signal RX to FPGA FPGA_SRSTN LVCMOS33 FPGA Reset RX 1_P35 LVCMOS33 RX 1 Video Data 35 RX to FPGA RX 1_P34 LVCMOS33 RX 1 Video Data 34 RX to FPGA RX 1_P33 LVCMOS33 RX 1 Video Data 33 RX to FPGA RX 1_P32 LVCMOS33 RX 1 Video Data 32 RX to FPGA RX 1_P31 LVCMOS33 RX 1 Video Data 31 RX to FPGA RX 1_P30 LVCMOS33 RX 1 Video Data 30 RX to FPGA RX 1_P29 LVCMOS33 RX 1 Video Data 29 RX to FPGA RX 1_P28 LVCMOS33 RX 1_P27 LVCMOS33 RX 1 Video Data 27 RX to FPGA RX 1_P26 LVCMOS33 RX 1 Video Data 28 RX to FPGA RX 1 Video Data 26 RX to FPGA RX 1_P25 LVCMOS33 RX 1 Video Data 25 RX to FPGA RX 1_P24 LVCMOS33 RX 1 Video Data 24 RX to FPGA RX 1_P23 LVCMOS33 RX 1 Video Data 23 RX to FPGA RX 1_P22 LVCMOS33 RX 1 Video Data 22 RX to FPGA RX 1_P21 LVCMOS33 RX 1 Video Data 21 RX to FPGA RX 1_P20 LVCMOS33 RX 1 Video Data 20 RX to FPGA RX 1_P19 LVCMOS33 RX 1 Video Data 19 RX to FPGA RX 1_P18 LVCMOS33 RX 1 Video Data 18 RX to FPGA RX 1_P17 LVCMOS33 RX 1 Video Data 17 RX to FPGA RX 1_P16 LVCMOS33 RX 1 Video Data 16 RX to FPGA RX 1_P15 LVCMOS33 RX 1 Video Data 15 RX to FPGA RX 1_P14 Rev 1 00 LVCMOS33 RX 1 Video Dat
21. LVCMOS25 unused 09 LVCMOS25 unused HA10 N LVCMOS25 unused HA11 N LVCMOS25 unused HA12 N LVCMOS25 unused HA13 N LVCMOS25 unused HA14 N LVCMOS25 unused HA15 N LVCMOS25 unused HA16_N LVCMOS25 unused HA17_N_CC LVCMOS25 unused HA18_N LVCMOS25 unused HA19_N LVCMOS25 unused 20 LVCMOS25 unused HA21 N LVCMOS25 unused 1 00 TOKYO ELECTRON DEVICE LIMITED 24 Pin Name Spec Description inreviun HA22 N LVCMOS25 unused HA23 N LVCMOS25 unused RX 0_P35 LVCMOS33 RX 0 Video data 35 RX to FPGA RX 0_P34 LVCMOS33 RX 0 Video data 34 RX to FPGA RX 0_P33 LVCMOS33 RX 0 Video data 33 RX to FPGA RX 0_P32 LVCMOS33 gt gt gt RX 0 Video data 32 RX to FPGA RX 0_P31 LVCMOS33 RX 0 Video data 31 RX to FPGA RX 0_P30 LVCMOS33 RX 0 Video data 30 RX to FPGA RX 0_P29 LVCMOS33 RX 0 Video data 29 RX to FPGA RX 0_P28 LVCMOS33 RX 0 Video data 28 RX to FPGA RX 0_P27 LVCMOS33 RX 0 Video data 27 RX to FPGA RX 0_P26 LVCMOS33 RX 0 Video data 26 RX to FPGA RX 0_P25 LVCMOS33 RX 0 Video data 25 RX to FPGA RX 0_P24 LVCMOS33 RX 0 Video data 24 RX to FPGA RX 0_P23 LVCMOS33 RX 0 Video data 23 RX to FPGA
22. LVCMOS33 DIP Switch 7 LEDO LVCMOS33 LEDO LED1 LVCMOS33 LED1 LED2 LVCMOS33 LED2 LED3 LVCMOS33 LED3 LED4 LVCMOS33 LED4 LED5 LVCMOS33 LED5 LED6 LVCMOS33 LED6 LED7 LVCMOS33 Note Input Video Status 1 0 This status shows 2D 3D video format 1 0 00 1 0 01 1 0 10 1 0 11 Rev 1 00 2D video video SideBySide format SD video TopAndBottom format 3D video FramePacking format TOKYO ELECTRON DEVICE LIMITED 28 inreviun 4 11 FPGA Output Data Phase Figure 4 6 shows the output data phase of FPGA on TB FMCH HDMI2 RX FPGA to FMC data is output at the falling edge of the video clock The data should be latched at the rising edge on the main board side gt HDMIRX VSYNC HSYNC Y Output data are synchronous with down edge of HDMIRX Figure 4 6 FPGA Output Data Timing 4 12 Audio I2S format This design supports 125 format audio Figure 4 7 shows audio output timing chart FPGA does not synchronaise audio signals from ADV7612 64 SCLK Bene sum sum 5 Left Right S S S 50 LM 24bit 7bit 48 2 AP1 SDATA Figure 4 7
23. P GND LA27 P LA26 P GND DP2 C2M N GND 27 LA26 N 09 P GND DP2 C8M P GND GND 09 GND DP2 C8M N GND TCK GND DP3 C2M P GND SCL TDI HB13 P DP3 C2M N GND SDA TDO HB13 N GND DP2 C7M P GND 3 3VAUX GND GND DP2_C7M_N GND TMS 19 P GND GAO TRST HB19_N DP4_C2M_N GND 12V GA1 GND GND DP2 C6M P GND 3 3V HB21 P GND DP2 C6M N 12V GND HB21 N DP5 C2M P GND GND 3 3V GND DP5 C2M N GND 3 3V GND VADJ GND Rev 1 00 RESO GND 3 3V TOKYO ELECTRON DEVICE LIMITED GND 17 inreviun F row G row H row J row K row PG M2C GND VREF A M2C GND VREF B M2C GND CLK1 M2C P PRSNT M2C L CLK3 M2C P GND GND CLK1 M2C N GND CLK3 M2C N GND HAO0 P CC GND CLKO M2C P GND CLK2 M2C P 00 CC GND CLKO M2C N GND CLK2 M2C N GND 00 P CC GND P GND GND 00 CC 02 P 02 P 04 P GND 02 GND 2 04 LAO3 P GND 07 P GND GND LAO3 N LAO4 P 07 06 P 8 P GND 04 GND 06 HAO8_N LA08_P GND
24. Purpose Silk Jumper Setting FMC Connector 12VIN SEL JP3 1 2 short External Power Source 12VIN SEL JP3 2 3 short The following test pin is used to connect an external power source TP14 12VIN 1 00 TOKYO ELECTRON DEVICE LIMITED 36 inreviun A row Table 5 3 shows the FMC connector pin assignment Table 5 3 FMC Connector Pin Assignment B row C row D row E row GND RES1 GND PG C2M GND DP1 M2C P GND DPO C2M P GND HA01 P CC DP1 M2C GND DPO C2M N GND 1 CC GND DP9 M2C P GND GBTCLKO M2C P GND GND DP9 M2C N GND GBTCLKO M2C N GND DP2 M2C P GND DPO M2C P GND 05 P DP2 M2C N GND DPO M2C N GND 05 OO N GND DP8_M2C_P GND LA01_P_CC GND GND DP8 M2C N GND 01 CC 09 P DP3 M2C P GND 06 P GND 09 DP3 2 GND 06 05 P GND GND DP7 M2C P GND 05 HA13 P GND DP7 M2C N GND GND HA13 N M2C GND LA10 P LAO9 P GND DP4 M2C GND LA10 N 09 HA16 P GND DP6 M2C P GND GND HA16 N GND DP6 M2C N GND LA13 P GND DP5 M2C P GND LA14 P LA13 N HA20 P DP5 M2C GND LA14 GND HA20 N GND GBTCLK4 M2C P GND LA1
25. plug display On Connected state DONE Config display On Config done Rev 1 00 12VLED TOKYO ELECTRON DEVICE LIMITED 12V display On 12V active 20 inreviun 4 9 Control Function Table 4 7 shows the onboard switch function 2 Circuit Table 4 7 Switches Function S1 1 ADV7612 config ROM selection 51 2 Please refer to Table 4 8 51 3 51 4 51 5 Unused to 51 6 Unused to 51 7 Unused to 51 8 Unused to 1 2 3 4 5 6 7 8 9 52 Unused to 0 53 reconfig long push 3 seconds FPGA reset short push 4 9 1 ADV7612 Configuration ROM selection Table 4 8 shows the configuration ROM function and settings for ADV7612 2 Table 4 8 ADV7612 configuration ROM Color format Color Space YCbCr 444 422 Color Depth 8bit Color Space YCbCr 444 422 Color Depth 10bit Color Space YCbCr 444 422 Color Depth 12bit Color Space RGB Color Depth 8bit Color Space RGB Color Depth 10bit Color Space RGB Color Depth 12bit CO N Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 21 inreviun 4 10 FPGA Pin Assignment Table 4 9 shows the FPGA pin assignment In case of 8 bit signal format active bits are assigned to MSB 8 bit o
26. 09 LVCMOS25 Unused HA10 N LVCMOS25 Unused HA11 N LVCMOS25 Unused HA12 N LVCMOS25 Unused HA13 N LVCMOS25 Unused HA14 N LVCMOS25 Unused HA15 N LVCMOS25 Unused HA16 N LVCMOS25 Unused HA17 N CC LVCMOS25 Unused HA18 N LVCMOS25 Unused HA19 N LVCMOS25 Unused HA20 N LVCMOS25 Unused HA21 N LVCMOS25 Unused 1 00 TOKYO ELECTRON DEVICE LIMITED 44 inreviun Description HA22 N LVCMOS25 Unused HA23 N LVCMOS25 Unused TX 0_D35 LVCMOS33 TX 0 Video data 35 FPGA to TX TX 0_D34 LVCMOS33 0 Video data 34 FPGA to TX TX 0_D33 LVCMOS33 TX 0 Video data 33 FPGA to TX TX 0_D32 LVCMOS33 0 Video data 32 FPGA to TX TX 0_D31 LVCMOS33 TX 0 Video data 31 FPGA to TX TX 0_D30 LVCMOS33 TX 0_D29 LVCMOS33 TX 0 Video data 29 FPGA to TX TX 0_D28 LVCMOS33 TX 0 Video data 30 FPGA to TX TX 0 Video data 28 FPGA to TX TX 0_D27 LVCMOS33 TX 0 Video data 27 FPGA to TX TX 0_D26 LVCMOS33 TX 0 Video data 26 FPGA to TX TX 0_D25 LVCMOS33 TX 0 Video data 25 FPGA to TX TX 0_D24 LVCMOS33 TX 0 Video data 24 FPGA to TX TX 0_D23 LVCMOS33 TX 0 Video data 23 FPGA to TX TX 0_D22 LVCMO
27. 1 ADV7511 Configuration ROM 41 5 10 FPGA Pin 42 5 11 FPGA Input Data Phase cde sce aaa baee 49 5 12 25 Ute alal 49 5 13 IMAGE Siz uuu iii 50 5131 20 Image 8 26 22000 C 50 5 13 2 Image 5 50 6 DDC Connection Normal 51 6 1 DDC Connection Normal icta des aod de dunt ua 51 6 2 DDC Connection eee 52 7 Default Switch Setting cere ed ERR EXE XE dd 53 8 Usage Example pieta 57 1 00 TOKYO ELECTRON DEVICE LIMITED 3 inreviun List of Figures Figure 3 1 FMC Connector Pin LayoOUt ie 10 Figure 4 1 TB FMCH HDMI2 RX Block 11 Figure 4 2 External View of TB FMCH HDMI2 RX component side 12 Figure 4 3 External View of TB FMCH HDMI2 RX solder side 12 Figure 4 4 TB FMCH HDMI2 RX Board Dimensions esee eme 13 Figure 4 5 T
28. 1_12S1 LVCMOS33 RX 1 125 Audio Signal 1 RX to FPGA RX 1_12S2 LVCMOS33 RX 1 125 Audio Signal 2 RX to FPGA RX 1_12S3 LVCMOS33 RX 1 125 Audio Signal 3 RX to FPGA RX 1_LRCLK LVCMOS33 RX 1 LRCLK Signal RX to FPGA RX 1_SCL LVCMOS33 RX 1 2 Serial Clock FPGA to RX RX 1_SDA LVCMOS33 RX 1 12C Serial Data RX to from FPGA RX 1_INT1 LVCMOS33 RX 1 Interrupt Input 1 RX to FPGA RX 1_RESETN LVCMOS33 RX 1 Reset FPGA to RX RX 1_CSN LVCMOS33 RX 1 CS Output FPGA to RX RX 1_CEC LVCMOS33 RX 1 CEC Signal RX to from FPGA RX 1_DDCA_SCL_F LVCMOS33 RX 1 DDC Serial Clock RX to FPGA RX 1_DDCA_SDA_F LVCMOS33 RX 1 DDC Serial Data RX lt gt FPGA RX 1_HPD_IO LVCMOS33 RX 1 Hot Plug Control FPGA to RX RX 1_DET1 LVCMOS33 RX 1 Detect Signal RX to FPGA RSWO LVCMOS33 Rotary Switch 0 RSW1 LVCMOS33 Rotary Switch 1 RSW2 LVCMOS33 Rotary Switch 2 RSW3 LVCMOS33 Rotary Switch 3 DSWO LVCMOS33 DIP Switch 0 DSW1 Rev 1 00 LVCMOS33 DIP Switch 1 TOKYO ELECTRON DEVICE LIMITED 27 inreviun Pin Name Description DSW2 LVCMOS33 DIP Switch 2 DSW3 LVCMOS33 DIP Switch 3 DSW4 LVCMOS33 DIP Switch 4 DSW5 LVCMOS33 DIP Switch 5 DSW6 LVCMOS33 DIP Switch 6 DSW7
29. 4mA NC782125 0 02mA x2 0 04mA XCF16 VCCIO 40mA LT3503EDCB VCC_2 5V FPGA VCCIO 261m _ us MM 1170mA 2 926W LTC3026EMSE VCC 1 8V0 amp ADV G2 MO7mA XCFIGVCCINT 10mA LTC3026EMSE VCC 1 8V1 Figure 4 5 TB FMCH HDMI2 RX Power Supply Structure 1 00 TOKYO ELECTRON DEVICE LIMITED 14 inreviun 4 5 HDMI Receiver HDMI Connector uses a 5002541927 MOLEX HDMI Receiver uses an ADV7612BSWZ P Analog Devices The following device is used as ESD protection ESD protection RCLAMP0524 and RCLAMP0504 Semtech Table 4 1 shows the HDMI connector pin assignments Table 4 1 HDMI Connector receiving side Name Description TMDS receive data 2 TMDS receive data 2 shield TMDS receive data 2 TMDS receive data 1 TMDS receive data 1 shield TMDS receive data 1 TMDS receive data 0 TMDS receive data 0 shield TMDS receive data 0 TMDS receive clock TMDS receive clock shield TMDS DATA2 TMDS SHLD2 TMDS DATA2 TMDS DATA1 TMDS SHLD1 TMDS DATA1 TMDS TMDS SHLDO TMDS DATAO TMDS CLK TMDS CLK SHLD TMDS CLK TMDS receive clock CEC CEC signal RESERVED Reserved DDC SCL DDC serial clock DDC SDA DDC serial data DDC CEC GND DDC CEC ground DDC 5V 5V power supply HOTPLUG DET Hot plug detect
30. 7 P CC GND GND GBTCLK1 M2C GND 17 CC P DP1 C2M P GND LA18 P CC GND HB03 DP1 C2M N GND LA18 N CC LA23 P GND GND DP2 C9M P GND LA23 N 05 P GND DP2 C9M N GND GND 05 DP2 P GND LA27 P LA26 P GND DP2 C2M N GND 27 LA26 N 09 P GND DP2 C8M P GND GND 09 GND DP2 C8M N GND TCK GND DP3 C2M P GND SCL TDI HB13 P DP3 C2M N GND SDA TDO HB13 N GND DP2 C7M P GND 3 3VAUX GND GND DP2_C7M_N GND TMS 19 P GND GAO TRST HB19_N DP4_C2M_N GND 12V GA1 GND GND DP2 C6M P GND 3 3V HB21 P GND DP2 C6M N 12V GND HB21 N DP5 C2M P GND GND 3 3V GND DP5 C2M N GND 3 3V GND VADJ GND Rev 1 00 RESO GND 3 3V TOKYO ELECTRON DEVICE LIMITED GND 37 inreviun F row G row H row J row K row PG M2C GND VREF A M2C GND VREF B M2C GND CLK1 M2C P PRSNT M2C L CLK3 M2C P GND GND CLK1 M2C N GND CLK3 M2C N GND HAO0 P CC GND CLKO M2C P GND CLK2 M2C P 00 CC GND CLKO M2C N GND CLK2 M2C N GND 00 P CC GND P GND GND 00
31. B FMCH HDMI2 RX Power Supply Structure u 14 Figure 4 6 FPGA Output Data Timing esses 29 Figure 4 7 125 Format Audio Timing Chart enm eene 29 Figure 5 1 TB FMCH HDMI2 TX Block Diagram 1 emm emm ene 31 Figure 5 2 TB FMCH HDMI2 TX component side eme 32 Figure 5 3 TB FMCH HDMI 2 TX solder 32 Figure 5 4 TB FMCH HDMI2 TX Board Dimensions esee ems 33 Figure 5 5 TB FMCH HDMI2 TX Power Supply Structure a 34 Figure 5 6 FPGA Input Data Timing S 49 Figure 5 7 125 Format Audio Timing 49 Figure 6 1 DDC Connection Structure 51 Figure 6 2 DDC Connection Structure 52 Figure 7 1 TB FMCH HDMI2 RX Default Switch Settings component side 53 Figure 7 2 TB FMCH HDMI2 TX Default Settings component side 2 55 Figure 8 1 Usage Example uu ii ie tazen 57 Table 2 1 ROM data inei ec eter e aa ER a kausa 9 Table 4 1 HDMI Connector receiving nemen 15 Table 4 2 SCL SDA Jumper Setting 2 nna nhan nbn 15 Table 4 3 JP1 Jumper S6ttlng
32. CC LVCMOS25 input video status 0 FPGA to FMC LAO1 N CC LVCMOS25 RX 0_input video status 1 FPGA to FMC Please see Note LAO2 LVCMOS25 Unused LAO3 LVCMOS25 Unused LAO4 LVCMOS25 Unused 05 LVCMOS25 Unused LAO6 LVCMOS25 Unused LA07_N LVCMOS25 Unused LAO8 LVCMOS25 Unused LAO9 N LVCMOS25 Unused LA10 N LVCMOS25 Unused LA11 N LVCMOS25 Unused LA12 N LVCMOS25 Unused LA13 N LVCMOS25 Unused LA14 N LVCMOS25 Unused LA15 N LVCMOS25 Unused LA16 N LVCMOS25 Unused LA17 CC LVCMOS25 Unused LA18 N CC LVCMOS25 Unused LA19 N LVCMOS25 RX 0_MCLK signal FPGA to FMC LA20 N LVCMOS25 SCLK signal FPGA to FMC LA21 N LVCMOS25 RX 0_APO signal FPGA to FMC 422 LVCMOS25 AP1 signal FPGA to FMC LA23 N LVCMOS25 RX 0_AP2 signal FPGA to FMC 24 LVCMOS25 RX 0_AP3 signal FPGA to FMC LA25_N LVCMOS25 RX 0_AP4 signal FPGA to FMC LA26_N LVCMOS25 RX 0_AP5 signal FPGA to FMC LA27_N LVCMOS25 RX 0_P30 signal FPGA to FMC Cr6 R6 LA28_N LVCMOS25 RX 0_P31 signal FPGA to FMC Cr7 R7 LA29 N LVCMOS25 RX 0_P32 signal FPGA to Cr8 R8 LA30_N LVCMOS25 Cr9 R9 LA31_N LVCMOS25 R
33. D19 LVCMOS33 TX 1 Video data 19 FPGA to TX TX 1_D18 LVCMOS33 TX 1 Video data 18 FPGA to TX TX 1_D17 LVCMOS33 TX 1 Video data 17 FPGA to TX TX 1_D16 Rev 1 00 OJO O O O O O O O O O LVCMOS33 TX 1 Video data 16 FPGA to TX TOKYO ELECTRON DEVICE LIMITED 46 Description inreviun TX 1_D15 LVCMOS33 TX 1 Video data 15 FPGA to TX TX 1_D14 LVCMOS33 TX 1 Video data 14 FPGA to TX TX 1_D13 LVCMOS33 TX 1 Video data 13 FPGA to TX TX 1_D12 LVCMOS33 TX 1_D11 LVCMOS33 TX 1 Video data 11 FPGA to TX TX 1_D10 LVCMOS33 TX 1 Video data 12 FPGA to TX TX 1 Video data 10 FPGA to TX TX 1_D9 LVCMOS33 TX 1 Video data 9 FPGA to TX TX 1_D8 LVCMOS33 TX 1 Video data 8 FPGA to TX TX 1_D7 LVCMOS33 TX 1 Video data 7 FPGA to TX TX 1_D6 LVCMOS33 TX 1 Video data 6 FPGA to TX TX 1_D5 LVCMOS33 TX 1 Video data 5 FPGA to TX TX 1_D4 LVCMOS33 TX 1_D3 LVCMOS33 TX 1 Video data 3 FPGA to TX TX 1_D2 LVCMOS33 TX 1 Video data 2 FPGA to TX TX 1_D1 LVCMOS33 TX 1 Video data 1 FPGA to TX TX 1_DO LVCMOS33 TX 1 Video data 0 FPGA to TX TX 1_DCLK LVCMOS33 TX 1 Video data 4 FPGA to T
34. DMI Connector Figure 4 2 External View of TB FMCH HDMI2 RX component side ICT ai m de mme mde LA Figure 4 3 External View of TB FMCH HDMI2 RX solder side 1 00 TOKYO ELECTRON DEVICE LIMITED 12 inreviun 4 3 Board Specification The following shows TB FMCH HDMI2 RX board specifications External Dimensions W 160mm x H 69mm Number of Layers 8 layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 9 55 15 999 999 ar N arti 5 ues 6 15 2 2 gt rime iini _ para mmm e E epu Figure 4 4 TB FMCH HDMI2 RX Board Dimensions 1 00 TOKYO ELECTRON DEVICE LIMITED 13 inreviun 4 4 Supplying Power to the Board Figure 4 5 shows a TB FMCH HDMI2 RX power supply structure 12V IN LT3503EDCB VCC_5V 2ALCS22A 3mAx2 6m 52250 135mA 0 677W LT3568EDD VCC 12V FPGA VOCINT 485mA 562mA l LT3503EDCB VCC_3 3V CR Oe ee FPGA_VCAUX 50mA FPGA VOCIO 20mA e ADW7612 3125mA x2 625mA 3 750mA KC3225A 6mA 2 475W LTC1326 0 0
35. OS25 P15 signal FPGA to FMC Y3 G3 LA19 P LVCMOS25 RX 0_P16 signal FPGA to FMC Y4 G4 LA20 P LVCMOS25 Y5 G5 LA21 P LVCMOS25 RX 0_P18 signal FPGA to FMC Y6 G6 22 P LVCMOS25 RX 0_P17 signal FPGA to FMC RX 0_P19 signal FPGA to FMC Y7 G7 LA23 P LVCMOS25 RX 0_P20 signal FPGA to FMC Y8 G8 LA24 P LVCMOS25 RX 0_P21 signal FPGA to FMC Y9 G9 LA25 P LVCMOS25 RX 0_P22 signal FPGA to FMC CrO RO LA26 P LVCMOS25 RX 0_P23 signal FPGA to FMC Cr1 R1 LA27 P LVCMOS25 RX 0_P24 signal FPGA to FMC Cr2 R2 LA28_P LVCMOS25 Cr3 R3 LA29 P LVCMOS25 RX 0_P26 signal FPGA to FMC Cr4 R4 LA30_P LVCMOS25 RX 0_P25 signal FPGA to FMC RX 0_P27 signal FPGA to FMC Cr5 R5 LA31 P LVCMOS25 RX 0_P28 signal FPGA to FMC Cr6 R6 LA32 P LVCMOS25 I __ mb RX 0_P29 signal FPGA to FMC Cr7 R7 LA33_P LVCMOS25 Unused CLKO_M2C_N LVCMOS25 Unused CLK1_M2C_N Rev 1 00 LVCMOS25 unused TOKYO ELECTRON DEVICE LIMITED 22 inreviun Pin Name Description 00
36. RX 0_12S 3 0 CEC 0 RX 0_SPDIF DETO RX 0_SCLK HPD 0 RX 0_LRCLK RX 0_MCLKOUT 500254 1927 GR RX 0 INT1 CSN 8 2000 SDA 0 3 ppoosv 28 6363MHz 8 DDCO_HPD RX 0_CEC ADV 1812 8 DDCO GND RX 0_DET1 t 5 RX40 HPD 10 3 0000 0 DDCA SDA F 7 7 3 EEPROM 0 RX 0 DDCA_SCL F E gr 24LCS22A HDMI 1 RX RX 1_P 35 0 RX 1_C 0 2 RX 1_VS HS DE RX 1_DDCA SCL RX 1_LLC RX 1 DDCA SDA RX 1 I2S 3 0 CECH RX 1_SPDIF DETI RX 1_SCLK HPD 1 RX 1_LRCLK RX 1_MCLKOUT 500254 1927 TE S RX 1_INT1 CSN 8 DDGUSDA RX 1_RESETN 3 pporsv 28 6363MHz 8 DDCTHPD RX 1_CEC ADV7612 8 DDC1 GND RX 1_DET1 t s RX 1_HPD_IO o 3 RX 1_DDCA SDA F 77 I EEPROM 1 RX 1_DDCA SCL_F 241 522 Figure 4 1 TB FMCH HDMI2 RX Block Diagram Main Functions 1 HDMI receive function ADV7612 gt FPGA connector interface FPGA gt FMC HPC connector EEPROM interface JTAG interface General purpose clock interface 27 2 General purpose switch General purpose LED DDC connection Normal Through Note This design uses HDMIZO RX only Because of limited pin number of FMC LPC Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 11 TB FMCH HDMI2 Hardware User Manual 1 IN OUT Audio 4 2 External View of the Board Figures 4 2 and 4 3 show the external view of the TB FMCH HDMI2 RX board RoHS Y TII 916161412 H
37. RX 0_P22 LVCMOS33 RX 0 Video data 22 RX to FPGA RX 0_P21 LVCMOS33 RX 0 Video data 21 RX to FPGA RX 0_P20 LVCMOS33 RX 0 Video data 20 RX to FPGA RX 0_P19 LVCMOS33 RX 0 Video data 19 RX to FPGA RX 0_P18 LVCMOS33 2 2 ae RX 0 Video data 18 RX to FPGA RX 0_P17 LVCMOS33 RX 0 Video data 17 RX to FPGA RX 0_P16 LVCMOS33 RX 0_P15 LVCMOS33 gt RX 0 Video data 15 RX to FPGA RX 0_P14 LVCMOS33 RX 0 Video data 14 RX to FPGA RX 0_P13 LVCMOS33 RX 0 Video data 16 RX to FPGA RX 0 Video data 13 RX to FPGA RX 0_P12 LVCMOS33 RX 0 Video data 12 RX to FPGA RX 0_P11 LVCMOS33 RX 0 Video data 11 RX to FPGA RX 0_P10 LVCMOS33 YS RX 0 Video data 10 RX to FPGA RX 0_P9 LVCMOS33 RX 0 Video data 9 RX to FPGA RX 0_P8 LVCMOS33 RX 0 Video data 8 RX to FPGA RX 0_P7 LVCMOS33 RX 0 Video data 7 RX to FPGA RX 0_P6 LVCMOS33 RX 0 Video data 6 RX to FPGA RX 0_P5 LVCMOS33 RX 0 Video data 5 RX to FPGA RX 0_P4 LVCMOS33 RX 0 Video data 4 RX to FPGA RX 0_P3 LVCMOS33 RX 0 Video data 3 RX to FPGA RX 0_P2 LVCMOS33 RX 0 Video data 2 RX to FPGA RX 0_P1 LVCMOS33 RX 0 Video data 1 RX to FPGA PO LVCMOS33 RX 0 Video d
38. S33 0 Video data 22 FPGA to TX TX 0_D21 LVCMOS33 TX 0 Video data 21 FPGA to TX TX 0_D20 LVCMOS33 TX 0 Video data 20 FPGA to TX TX 0_D19 LVCMOS33 TX 0 Video data 19 FPGA to TX TX 0_D18 LVCMOS33 TX 0_D17 LVCMOS33 TX 0 Video data 17 FPGA to TX TX 0_D16 LVCMOS33 TX 0 Video data 16 FPGA to TX TX 0_D15 LVCMOS33 0 Video data 15 FPGA to TX TX 0_D14 LVCMOS33 0 Video data 14 FPGA to TX TX 0_D13 LVCMOS33 TX 0 Video data 18 FPGA to TX TX 0 Video data 13 FPGA to TX TX 0_D12 LVCMOS33 0 Video data 12 FPGA to TX TX 0_D11 LVCMOS33 TX 0 Video data 11 FPGA to TX TX 0_D10 LVCMOS33 0 Video data 10 FPGA to TX TX 0_D9 LVCMOS33 TX 0 Video data 9 FPGA to TX TX 0_D8 LVCMOS33 0 Video data 8 FPGA to TX TX 0_D7 LVCMOS33 TX 0 Video data 7 FPGA to TX TX 0_D6 LVCMOS33 0 Video data 6 FPGA to TX TX 0_D5 LVCMOS33 TX 0 Video data 5 FPGA to TX TX 0_D4 LVCMOS33 TX 0_D3 LVCMOS33 0 Video data 3 FPGA to TX TX 0_D2 LVCMOS33 0 Video data 2 FPGA to TX TX 0_D1 LVCMOS33 TX 0 Video data 1 FPGAto TX TX40 DO LVCMOS33 0 Video data 0 FPGA to TX TX 0_DCLK LVCMOS33 TX 0 V
39. Serial Clock FPGA to TX TX 0_LRCLK LVCMOS33 TX 0 LRCLK Signal FPGA to TX TX 0_HPD_IO LVCMOS33 TX 0 Hot Plug Control FPGA to TX TX40 PD LVCMOS33 TX 0 Power Down FPGA to TX TX 0_INT LVCMOS33 TX 0 Interrupt TX to FPGA TX 0_SCL O LVCMOS33 TX 0 Serial Clock FPGA to TX TX 0_SDA LVCMOS33 TX 0 Serial Data FPGA to TX FPGA SRSTN LVCMOS33 FPGA Reset TX 1_D35 LVCMOS33 TX 1 Video data 35 FPGA to TX TX 1_D34 LVCMOS33 TX 1 Video data 34 FPGA to TX TX 1_D33 LVCMOS33 TX 1_D32 LVCMOS33 TX 1 Video data 33 FPGA to TX TX 1 Video data 32 FPGA to TX TX 1_D31 LVCMOS33 TX 1 Video data 31 FPGA to TX TX 1_D30 LVCMOS33 TX 1 Video data 30 FPGA to TX TX 1_D29 LVCMOS33 TX 1 Video data 29 FPGA to TX TX 1_D28 LVCMOS33 TX 1 Video data 28 FPGA to TX TX 1_D27 LVCMOS33 TX 1 Video data 27 FPGA to TX TX 1_D26 LVCMOS33 TX 1 Video data 26 FPGA to TX TX 1_D25 LVCMOS33 TX 1_D24 LVCMOS33 TX 1 Video data 24 FPGA to TX TX 1_D23 LVCMOS33 TX 1 Video data 25 FPGA to TX TX 1 Video data 23 FPGA to TX TX 1_D22 LVCMOS33 TX 1 Video data 22 FPGA to TX TX 1_D21 LVCMOS33 TX 1 Video data 21 FPGA to TX TX 1_D20 LVCMOS33 TX 1 Video data 20 FPGA to TX TX 1_
40. TOKYO ELECTRON DEVICE LIMITED 4 inreviun 1 00 TOKYO ELECTRON DEVICE LIMITED 5 inreviun Introduction Thank you for purchasing the TB FMCH HDMI2 RX TB FMCH HDMI2 TX boards Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly A Danger Indicates the high possibility of serious injury or death if the product is handled incorrectly A Warning Indicates the possibility of serious injury or death if the product is handled incorrectly A Caution Indicates the possibility of injury or physical damage in connection with houses or household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch X Do not disas
41. WZ P board operation via jumpers LPC Connector LPC Connector LPC Connector LPC Connector Figure 3 1 FMC Connector Pin Layout 1 00 TOKYO ELECTRON DEVICE LIMITED inreviun 4 TB FMCH HDMI2 RX 4 1 Block Diagram Figure 4 1 shows the TB FMCH HDMI2 RX block diagram The FMC HPC connector is mounted on the solder side of the board FMC HPC LA 33 00 P N FPGA HA 23 00 P N CLK 3 0 M2C P N ASP 134488 01 CLK SYSCLK P KC5032C27 000 LED 7 0 DSW 7 0 RSW 3 0 77 JTAG FPGA TCK TMS TDI TDO PROM 87832 1420 FPGA D 7 0 FPGA DONE FPGA INITB FPGA PROGB FPGA CCLK XCF16PFSG48C XC6SLX45 3FGG484C DEC 0 HDMI 0 RX RX 0_P 35 0 RX 0 C 0 0 2 RX 0_VS HS DE RX 0_DDCA SCL RX 0 SDA
42. X TX 1 DCLK signal FPGA to TX TX 1_DE LVCMOS33 TX 1 data enable FPGA to TX TX 1_HSYNC LVCMOS33 TX 1 HSYNC FPGA to TX TX 1_VSYNC LVCMOS33 TX 1 VSYNC FPGA to TX TX 1_DSDO LVCMOS33 TX 1 DSD Audio data 0 FPGA to TX TX 1_DSD1 LVCMOS33 TX 1 DSD Audio data 1 FPGA to TX TX 1_DSD2 LVCMOS33 TX 1 DSD Audio data 2 FPGA to TX TX 1_DSD3 LVCMOS33 TX 1 DSD Audio data 3 FPGA to TX TX 1_DSD4 LVCMOS33 TX 1 DSD Audio data 4 FPGA to TX TX 1_DSD5 LVCMOS33 TX 1 DSD Audio data 5 FPGA to TX TX 1_DSD_CLK LVCMOS33 TX 1 DSD clock FPGA to TX TX 1_SPDIF LVCMOS33 TX 1 SPDIF Digital Audio FPGA to TX TX 1_MCLK LVCMOS33 TX 1 Audio Master Clock FPGA to TX TX 1_12S0 LVCMOS33 TX 1 125 Audio signal 0 FPGA to TX TX 1 1251 LVCMOS33 TX 1 12S Audio signal 1 FPGA to TX TX 1_1252 LVCMOS33 TX 1 125 Audio signal 2 FPGA to TX 1_12 3 LVCMOS33 TX 1 125 Audio signal 3 FPGA to TX TX 1_SCLK LVCMOS33 TX 1 Audio serial clock FPGA to TX TX 1_LRCLK LVCMOS33 TX 1 LRCLK signal FPGA to TX TX 1_HPD_IO LVCMOS33 TX 1 hot plug control FPGA to TX TX 1_PD LVCMOS33 TX 1 power down FPGA to TX TX 1_INT LVCMOS33 TX 1 interrupt TX to FPGA TX 1_SCL O O O O O O O O O O O O O O O O O O O
43. X 0_P34 signal FPGA to FMC Cr10 R10 LA32_N JO LVCMOS25 wa a gt 27 27 27 as I lt RX 0_P33 signal FPGA to FMC RX 0_P35 signal FPGA to FMC Cr11 R11 LA33_N LVCMOS25 Unused CLK2_M2C_P LVCMOS25 Unused CLK3_M2C_P LVCMOS25 Unused 00 LVCMOS25 Unused HA01 CC LVCMOS25 Unused HA02 LVCMOS25 Unused LVCMOS25 Unused 04 P LVCMOS25 Unused HAO05 P Rev 1 00 LVCMOS25 Unused TOKYO ELECTRON DEVICE LIMITED 23 inreviun Pin 2 Description HAO06 P LVCMOS25 unused HA07 P LVCMOS25 unused HAO08 P LVCMOS25 unused 09 P LVCMOS25 unused HA10 P LVCMOS25 unused HA11 P LVCMOS25 unused HA12 P LVCMOS25 unused HA13 P LVCMOS25 unused 14 P LVCMOS25 unused HA15 P LVCMOS25 unused HA16 P LVCMOS25 unused HA17 P CC LVCMOS25 unused HA18 P LVCMOS25 unused HA19 P LVCMOS25 unused HA20 P LVCMOS25 unused HA21 P LVCMOS25 unused HA22 P LVCMOS25 unused HA23 P LVCMOS25 unused CLK2 M2C N LVCMOS25 unused CLK3 M2C N LVCMOS25 unused 00 CC LVCMOS25 unused HA01 CC LVCMOS25 unused 02 LVCMOS25 unused LVCMOS25 unused 04 LVCMOS25 unused 05 LVCMOS25 unused 06 LVCMOS25 unused HAO07 LVCMOS25 unused HAO08
44. a 14 RX to FPGA TOKYO ELECTRON DEVICE LIMITED 26 inreviun Pin Name Spec Description RX 1_P13 LVCMOS33 RX 1 Video Data 13 RX to FPGA RX 1_P12 LVCMOS33 RX 1 Video Data 12 RX to FPGA RX 1_P11 LVCMOS33 RX 1 Video Data 11 RX to FPGA RX 1_P10 LVCMOS33 RX 1 Video Data 10 RX to FPGA RX 1_P9 LVCMOS33 RX 1 Video Data 9 RX to FPGA RX 1_P8 LVCMOS33 RX 1 Video Data 8 RX to FPGA RX 1_P7 LVCMOS33 RX 1 Video Data 7 RX to FPGA RX 1_P6 LVCMOS33 RX 1 Video Data 6 RX to FPGA RX 1_P5 LVCMOS33 RX 1 Video Data 5 RX to FPGA RX 1_P4 LVCMOS33 RX 1 Video Data 4 RX to FPGA RX 1_P3 LVCMOS33 RX 1 Video Data 3 RX to FPGA RX 1_P2 LVCMOS33 RX 1 Video Data 2 RX to FPGA RX 1_P1 LVCMOS33 RX 1 Video Data 1 RX to FPGA 1_ LVCMOS33 RX 1 Video Data 0 RX to FPGA DE LVCMOS33 RX 1 Data Enable RX to FPGA RX 1_LLC LVCMOS33 RX 1 LLC Signal RX to FPGA RX 1_SCLK LVCMOS33 RX 1 Audio Serial Clock RX to FPGA RX 1_MCLKOUT LVCMOS33 RX 1 Audio Master Clock RX to FPGA RX 1_HSYNC LVCMOS33 RX 1 HSYNC RX to FPGA RX 1_VSYNC LVCMOS33 RX 1 VSYNC RX to FPGA RX 1_SPDIF LVCMOS33 RX 1 SPDIF Digital Audio RX to FPGA RX 1_12S0 LVCMOS33 RX 1 125 Audio Signal 0 RX to FPGA RX
45. ata 0 RX to FPGA RX 0_DE LVCMOS33 RX 0 data enable RX to FPGA RX 0_LLC LVCMOS33 RX 0 LLC signal RX to FPGA RX 0_SCLK LVCMOS33 RX 0 Audio serial clock RX to FPGA RX 0_MCLKOUT LVCMOS33 RX 0 Audio master clock RX to FPGA 1 00 TOKYO ELECTRON DEVICE LIMITED 25 inreviun Pin Description SYSCLK P LVCMOS33 System Clock 27 2 RX 0_HSYNC LVCMOS33 RX 0 HSYNC RX to FPGA RX 0_VSYNC LVCMOS33 RX 0 VSYNC RX to FPGA RX 0_SPDIF LVCMOS33 RX 0 SPDIF Digital Audio RX to FPGA RX 0_12S0 LVCMOS33 RX 0 125 Audio Signal 0 RX to FPGA RX 0_12S1 LVCMOS33 RX 0 125 Audio Signal 1 RX to FPGA 0 1252 LVCMOS33 RX 0 125 Audio Signal 2 RX to FPGA 0 1253 LVCMOS33 RX 0 125 Audio Signal 3 RX to FPGA RX 0_LRCLK LVCMOS33 RX 0 LRCLK Signal RX to FPGA RX 0_SCL LVCMOS33 RX 0 2 Serial Clock FPGA to RX RX 0_SDA LVCMOS33 RX 0 I2C Serial Data RX to from FPGA RX 0_INT1 LVCMOS33 RX 0 Interrupt Input 1 RX to FPGA RX 0_RESETN LVCMOS33 RX 0 Reset FPGA to RX RX 0_CSN LVCMOS33 RX 0 CS Output FPGA to RX RX 0_CEC LVCMOS33 RX 0 CEC Signal RX to from FPGA RX 0 DDCA SCL LVCMOS33 RX 0 DDC Serial Clock RX to FPGA RX 0 DDCA SDA LVCMOS33 RX 0 Serial Data RX to from FPGA 0 HPD IO LVCMOS33 RX 0 Hot Plug Control FPGA to RX RX 0_DET1 LVCMOS33 RX 0
46. e 4 4 shows the FMC connector pin assignment Table 4 4 FMC Connector Pin Assignment B row C row D row E row GND RES1 GND PG C2M GND DP1 M2C P GND DPO C2M P GND HA01 P CC DP1 M2C GND DPO C2M N GND 1 CC GND DP9 M2C P GND GBTCLKO M2C P GND GND DP9 M2C N GND GBTCLKO M2C N GND DP2 M2C P GND DPO M2C P GND 05 P DP2 M2C N GND DPO M2C N GND 05 OO N GND DP8_M2C_P GND LA01_P_CC GND GND DP8 M2C N GND 01 CC 09 P DP3 M2C P GND 06 P GND 09 DP3 2 GND 06 05 P GND GND DP7 M2C P GND 05 HA13 P GND DP7 M2C N GND GND HA13 N M2C GND LA10 P LAO9 P GND DP4 M2C GND LA10 N 09 HA16 P GND DP6 M2C P GND GND HA16 N GND DP6 M2C N GND LA13 P GND DP5 M2C P GND LA14 P LA13 N HA20 P DP5 M2C GND LA14 GND HA20 N GND GBTCLK4 M2C P GND LA17 P CC GND GND GBTCLK1 M2C GND 17 CC P DP1 C2M P GND LA18 P CC GND HB03 DP1 C2M N GND LA18 N CC LA23 P GND GND DP2 C9M P GND LA23 N 05 P GND DP2 C9M N GND GND 05 DP2
47. f each RGB pin of FMC LSB 2 bit are always 200 in 8 bit signal format Pin Name Table 4 9 FPGA Pin Assignment Description CLKO M2C P LVCMOS25 RX 0_LLC signal FPGA to FMC CLK1 M2C P LVCMOS25 Unused 00 P CC LVCMOS25 RX 0_VSYNC signal FPGA to FMC LAO1 P CC LVCMOS25 HSYNC signal FPGA to FMC LAO2 LVCMOS25 RX 0_DE signal FPGA FMC LAO3 P LVCMOS25 RX 0_PO signal FPGA to FMC Cb0 B0 LAO4 P LVCMOS25 RX 0_P1 signal FPGA to FMC Cb1 B1 LA05_P LVCMOS25 RX 0_P2 signal FPGA to FMC Cb2 B2 LA06_P LVCMOS25 RX 0_P3 signal FPGA to FMC Cb3 B3 LA07_P LVCMOS25 RX 0_P4 signal FPGA to FMC Cb4 B4 LA08_P LVCMOS25 RX 0_P5 signal FPGA to FMC Cb5 B5 09 P LVCMOS25 RX 0_P6 signal FPGA to FMC Cb6 B6 LA10 P LVCMOS25 RX 0_P7 signal FPGA to FMC Cb7 B7 11 LVCMOS25 P8 signal FPGA to FMC Cb8 B8 LA12 P LVCMOS25 RX 0_P9 signal FPGA to FMC Cb9 B9 LA13_P LVCMOS25 RX 0_P10 signal FPGA to FMC Y10 G10 LA14 P LVCMOS25 RX 0_P11 signal FPGA to FMC Y11 G11 LA15 P LVCMOS25 RX 0_P 12 signal FPGA to FMC YO GO LA16 P LVCMOS25 RX 0_P13 signal FPGA to FMC Y1 G1 17 P CC LVCMOS25 RX 0_P14 signal FPGA to FMC Y2 G2 LA18 P CC LVCM
48. he FPGA on the TB FMCH HDMI2 TX FMC connector to FPGA data is captured by the FPGA at the rising edge of a video clock Data from the main board is transferred at the falling edge of a video clock gt HDMITX VSYNC HSYNC DE DATA Y Output data are synchronous with down edge of HDMITX Figure 5 6 FPGA Input Data Timing 5 12 Audio 12S format This design supports 125 format audio Figure 5 7 shows audio output timing chart FPGA does not synchronaise audio signals to ADV7511 64 SCLK sum sum 5 Left Right S S S 50 LM 24bit 7bit 48 2 AP1 SDATA Figure 5 7 125 Format Audio Timing Chart 1 00 TOKYO ELECTRON DEVICE LIMITED 49 inreviun 5 13 Image Size 5 13 1 2D Image Size TB FMCH HDMI2 TX supports HDMI1 4 compliant primary format and part of secondary format 1080p 60Hz Supported image size 640x480p 59 94 60Hz 1280x720p 59 94 60Hz 1920x1080i 59 94 60Hz 720x480p 59 94 60Hz 720 1440 x480i 59 94 60Hz 1280x720 50Hz 1920x1080i 50Hz 720x576p 50Hz 720 1440 x576i 50Hz 1920x1080p 59 94 60Hz 1920x1080p 50Hz 5 13 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported image size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bo
49. hort Normal JP14 DDC1_HPD 1 2 short Normal JP13 DDC1_HPD 1 2 short Normal JP15 DDC1_SDA 1 2 short Normal JP9 DDC1_SDA 1 2 short Normal JP16 DDC1_SCL 1 2 short Normal JP10 DDC1_SCL 1 2 short Normal 17 DDC1 GND 1 2 short Normal TB FMCH HDMI2 RX JP11 DDC1_GND DDC_SCL 56 DDC SDA DDC 5V DDC GND HDMI HOTPLUG DET DDC SCL DET EEPROM DDC GND DEC E Rev 1 00 1 2 short Normal TB FMCH HDMI2 TX DDC_SCL DDC_SDA DDC 5V MONITOR DDC GND HDMI HOTPLUG DET DDC SCL Figure 6 1 DDC Connection Structure Normal TOKYO ELECTRON DEVICE LIMITED 51 inreviun 6 2 Table 6 2 shows connection jumper setting Through and Figure 6 2 shows connection structure Through DDC Connection Through Table 6 2 DDC Jumper Setting Through TB FMCH HDMI2 RX TB FMCH HDMI2 TX Jumper JP6 SCLO Setting Open Jumper Set
50. ideo data 4 FPGA to TX TX 0 DCLK signal FPGA to TX SYSCLK P LVCMOS33 System clock 27MHz TX40 DE LVCMOS33 TX 0 data enable FPGA to TX TX 0_HSYNC LVCMOS33 TX 0 HSYNC FPGA to TX Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 45 Pin Name Description inreviun TX 0_VSYNC LVCMOS33 TX 0 VSYNC FPGA to TX TX40 DSDO LVCMOS33 0 DSD Audio data 0 FPGA to TX TX 0_DSD1 LVCMOS33 TX 0 DSD Audio data 1 FPGA to TX TX 0_DSD2 LVCMOS33 TX 0 DSD Audio data 2 FPGA to TX TX 0_DSD3 LVCMOS33 TX 0 DSD Audio data 3 FPGA to TX TX 0_DSD4 LVCMOS33 0 DSD Audio data 4 FPGA to TX TX 0_DSD5 LVCMOS33 TX 0 DSD Audio data 5 FPGA to TX TX40 DSD LVCMOS33 0 DSD clock FPGA to TX TX 0_SPDIF LVCMOS33 TX 0 SPDIF Digital Audio FPGA to TX TX 0_MCLK LVCMOS33 TX 0 Audio Master Clock FPGA to TX 1250 LVCMOS33 0 125 Audio Signal 0 FPGA to TX 1251 LVCMOS33 0 125 Audio Signal 1 FPGA to TX 1252 LVCMOS33 TX 0_1253 LVCMOS33 TX 0 12S Audio Signal 3 FPGA to TX TX 0_SCLK LVCMOS33 TX 0 125 Audio Signal 2 FPGA to TX TX 0 Audio
51. ing in the usage example 1 00 TOKYO ELECTRON DEVICE LIMITED 57 inreviun EE TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 1 00 TOKYO ELECTRON DEVICE LIMITED 58
52. ion The receiver has 24LCS22A SN Micro Chip This EEPROM is used to store EDID data The SCL signal can be switched by JP6 JP3 and the SDA signal using JP7 JP4 Note At factory default settings the EEPROM stores temporary data to enable output of image data from an image output device The ID used in the data is a dummy ID for evaluation purposes So do not use it for actual products Table 4 2 SCL SDA Jumper Setting Purpose Silk Setting DDC connection Normal JP6 SCLO JP7 SDAO JP3 SCL1 JP4 SDA1 JP6 1 2 short JP3 1 2 short JP7 1 2 short JP4 1 2 short Rev 1 00 connection Through DDC JP6 SCLO JP7 SDAO SCL1 JP4 SDA1 JP6 2 3 short JP3 2 3 short TOKYO ELECTRON DEVICE LIMITED JP7 2 3 short JP4 2 3 short inreviun 4 6 connector High Pin Count connecting to the main board uses an ASP 134488 01 SAMTEC Power to the TB FMCH HDMI2 RX is supplied from a 12V on the main board An external power source can also be used Table 4 3 shows JP1 jumper setting for power supply Table 4 3 JP1 Jumper Setting Purpose Silk Setting FMC connector 12VIN SEL JP1 1 2 short External power supply 12VIN SEL JP1 2 3 short To connect an external power source use the following test pin TP14 12VIN 1 00 TOKYO ELECTRON DEVICE LIMITED 16 inreviun A row Tabl
53. l power source 1 00 TOKYO ELECTRON DEVICE LIMITED 53 inreviun Table 7 2 TB FMCH HDMI2 RX Default Setting DSW RSW 2 OO N gt Silk Default Setting Function S1 1 OFF ADV7612 config ROM selection 51 2 OFF Please refer to Table 4 8 51 3 OFF 51 4 OFF 51 5 Unused Please set 51 6 Unused Please set ON 51 7 OFF Unused Please set ON 51 8 Unused Please set 52 0 Unused Please set 0 1 00 TOKYO ELECTRON DEVICE LIMITED 54 IE EM nrviun Figure 7 2 shows TB FMCH HDMI2 TX default switch settings portions enclosed by dotted lines JP8 JP5 JPG JP7 y JP3 ue FR ert m JP12 JP13 10 JP9 JP11 Figure 7 2 TB FMCH HDMI2 TX Default Settings component side Table 7 3 TB FMCH2 TX Default Settings JP Pin Silk No Initial Setting Function DDCO 5 1 2 Normal 2 3 Through DDCO HPD 1 2 Normal 2 3 Through DDCO SDA 1 2 Normal 2 3 Through DDCO SCL 1 2 Normal 2 3 Through GND 1 2 Normal 2 3 Through DDC1_5V 1 2 Normal 2 3 Through DDC1 HPD 1 2 Normal 2 3 Through DDC1 SDA 1 2 Normal 2 3 Through DDC1 SCL 1 2 Normal 2 3 Through DDC1 GND 1 2 Normal 2 3 Through 12VIN SEL 1 2 FMC connector 2 3 External power source 1 2 3 4 5 6 7 8 9 gt
54. ock Off No clock LED6 General purpose LED6 TX1 input video image clock monitor Flashing Active clock Off No clock LED7 General purpose LED7 System Reset Monitor On Reset active Off Reset release HPDO TXO hot plug display On Connected state HPD1 TX1 hot plug display On Connected state DONE Config display On Config complete Rev 1 00 12VLED TOKYO ELECTRON DEVICE LIMITED 12V display On 12V active 40 inreviun 5 9 Control Function Table 5 6 shows the onboard switch function Table 5 6 Switch Function 2 Description S1 1 ADV7511 config ROM selection 51 2 Please see Table 5 7 51 3 51 4 51 5 Unused to ON 51 6 Unused to ON 51 7 Unused to ON 51 8 Unused to ON S2 Unused to 0 S3 FPGA reconfig long push 3 seconds FPGA reset short push 1 2 3 4 5 6 7 8 9 5 9 1 ADV7511 Configuration ROM selection Table 5 7 shows the configuration ROM function and settings for ADV7511 Table 5 7 ADV7511 configuration ROM Z Color format Color Space YCbCr 444 Color Depth 8bit Color Space YCbCr 444 Color Depth 10bit Color Space YCbCr 444 Color Depth 12bit Color Space YCbCr 422 Color Depth 8bit Color Space YCbCr 422 Color Depth 10bit Color Space YCbCr 422 Color Depth 12bit
55. s Board Accessories All documents relating to this board can be downloaded from our website Club X Accessories Interboard spacers and screws Interboard jumper cable 2 Overview The TB FMCH HDMI2 comes either with AnalogDevices s HDMI Receiver ADV7612BSWZ P or HDMI Transmitter ADV7511KSTZ P Collectively there are called TB FMCH HDMI2 This document specifically describes these optional boards in the RX and TX sections respectively Each board has two independent receivers transmitters and is designed for high resolution support It uses Samtec s FMC connector and 5 HDMI connector for connection with a platform board having High Pin Count connectors This User Manual is refer to 1 channel input output and audio I2S format support ROM files TB FMCH HDMI2 boards need to download following ROM files Table 2 1 ROM data Board name FPGA ROM data TB FMCH HDMI2 RX tb fmch hdmi2 rx 1ch audio 100 mcs TB FMCH HDMI2 TX tb fmch hdmi2 tx 1ch audio 100 mcs 1 00 TOKYO ELECTRON DEVICE LIMITED 9 inreviun 3 Feature HDMI Devices Receiver AnalogDevices s ADV7612BSWZ P Transmitter AnalogDevices s ADV7511KSTZ P FMC Connector Samtec s ASP 134488 01 HDMI Connector common Molex s 5002541927 Power Supply common Jumper switch selection The RX board has an EEPROM for Display Data Channel hereafter referred to as DDC and allows setting the AnalogDevices s ADV7612BS
56. semble the product Do not attempt this Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 6 inreviun In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock ma
57. ting JP7 SDAO Open JP8 DDCO 5V 1 2 short Normal JP7 DDCO 5V 1 2 short Normal JP9 DDCO HPD 1 2 short Normal DDCO HPD 1 2 short Normal JP10 DDCO SDA 2 3 short Through JP4 DDCO SDA 2 3 short Through JP11 DDCO SCL 2 3 short Through JP5 DDCO SCL 2 3 short Through JP12 DDCO_GND 2 3 short Through JP6 DDCO_GND 2 3 short Through SCL1 Open JP4 SDAI Open JP13 DDC1_5V 1 2 short Normal JP12 DDC1_5V 1 2 short Normal JP14 DDC1_HPD 1 2 short Normal JP13 DDC1_HPD 1 2 short Normal JP15 DDC1_SDA 2 3 short Through JP9 DDC1_SDA 2 3 short Through JP16 DDC1_SCL 2 3 short Through JP10 DDC1_SCL 2 3 short Through 17 DDC1 GND 2 3 short Through TB FMCH HDMI2 RX JP11 DDC1_GND 2 3 short Through TB FMCH HDMI2 TX SCL SG DDC SDA DDC 5V HDMI DDC GND HOTPLUG DET DDC SCL EEPROM DEC DDC SCL DDC_SDA DDC Cable DDC_SCL MONITOR DDC 5V DDC GND HOTPLUG DET DDC SCL
58. ttom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing Side by Side Half 1920x1080i 50Hz Frame Packing Side by Side Half 1920x1080p 23 98 24Hz Frame Packing Side by Side Half Top and Bottom 1920x1080p 29 97 30Hz Frame Packing Top and Bottom 1920x1080p 59 94 60Hz Top and Bottom 1920x1080p 250Hz Top and Bottom 1 00 TOKYO ELECTRON DEVICE LIMITED 50 inreviun 6 DDC Connection Normal Through Two types of DDC connections are supported 6 1 DDC Connection Normal Table 6 1 shows DDC connection jumper setting Normal and Figure 6 1 shows DDC connection structure Table 6 1 DDC Jumper Setting Normal TB FMCH HDMI2 RX TB FMCH HDMI2 TX Jumper JP6 SCLO Setting 1 2 short Normal Jumper Setting JP7 SDAO 1 2 short Normal JP8 DDCO 5V 1 2 short Normal JP7 DDCO 5V 1 2 short Normal JP9 DDCO 1 2 short Normal JP8 DDCO HPD 1 2 short Normal JP10 DDCO SDA 1 2 short Normal JP4 DDCO SDA 1 2 short Normal JP11 DDCO SCL 1 2 short Normal JP5 DDCO SCL 1 2 short Normal JP12 DDCO_GND 1 2 short Normal JP6 DDCO_GND 1 2 short Normal SCL1 1 2 short Normal JP4 SDA1 1 2 short Normal JP13 DDC1_5V 1 2 short Normal JP12 DDC1_5V 1 2 s
59. ty for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice 1 00 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 1 Related Document
60. y occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock OOOQO O Do not touch connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 7 inreviun Do not use place the product in the following locations e Humid and dusty locations S Airless locations such as closet or bookshelf e Locations which receive oily smoke or steam e Locations exposed to direct sunlight e Locations close to heating equipment e Closed inside of a car where the temperature becomes high Staticky locations e Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation S Do not place heavy things on the product Otherwise the product may be damaged B Disclaimer This product is HDMI interface for Xilinx FPGA evaluation boards Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibili
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