DRV11-B general purpose DMA interface user's manual
Contents
1. 4 2 TABLES Table No Title Page 2 1 Recommended Cable Assemblies 235 3 1 CO CI CodeS y ipuku 3 4 4 CSR Bit Puncuioms muaa 4 3 CHAPTER 1 INTRODUCTION 1 1 GENERAL DESCRIPTION The 1 is a general purpose direct memory access interface for transferring 16 bit data words directly between the LSI 11 memory and a user s I O device Data Transfer Out DATO or Data Transfer In DATI takes place via the LSI 11 bus after DMA request where the DRV11 B becomes bus master Burst modes byte addressing and read modify write operation DATIO are possible with the DRV11 B The DRV11 B features switch programmable device and vector addresses and 40 pin connectors which provide for simple interfacing to the user s I O device Five registers are contained within the DRV11 B Word Count Register WCR Bus Address Register BAR Control Status Register CSR Input and Output Data Buffer Registers DBRs The CSR and DBRs are word and byte addressable whereas the WCR and BAR are only word addressable DRV11 B operation is initialized under program control by l Loading the WCR with 2 s complement of the number of transfers 2 Loading the BAR with the first address to or from which data is to be transferred 3 Loading the CSR with the desired function bits Data transfers may now proceed under the control of the 11 logic2. 45 FUNCTION AND STATUS BITS There are three function bits FNCT 1 2 3 and three status bits STAT A B C which the user can employ at his option to control and indicate the status of the DMA transfers and or the user inter face The function bits CSR bits 01 02 and 03 can be used to transfer control data to the user s interface via the OUTPUT DATA BIT lines ofthe DRV11 B The status bits CSR bits 09 10 and 11 can be used to indicate that status information is on the 1 INPUT DATA BIT lines 15 14 13 12 11 ERROR 10 09 08 07 06 05 04 03 02 O1 00 CYCLE IE XAD 16 FNCT2 GO LEGEND R Read only R W Read Write R WO Read Write to W Write only Always reads as 11 4186 Figure 4 1 CSR Format 4 2 Bit 00 01 02 03 04 05 06 07 08 09 10 11 12 Table 4 1 CSR Bit Functions Function GO Write only bit always reads as a zero Causes READY to be sent to the user s device indicating that a command has been issued 2 Allows DMA operation FNCT 1 2 3 Read write bits 1 Three output bits available for user defined functions 2 Cleared by INIT XAD16 17 Read write bits Two bits used for extended addressing Bits 04 and 05 increment with the address count when the BAR wraps around to zero IE Read write bit l Enables interrupts to occur when READY is set 2 Cleared by INIT READY Read only bit Indi
3. 3 2 1 DRVII B Registers The DRV11 B contains five 5 registers Word Count Register WCR Bus Address Register BAR Control Status Register CSR Input and Output Data Buffer Registers DBRs 3 2 1 1 Word Count Register WCR The WCR is a 16 bit read write register that controls the number of transfers This register is loaded under program control with the 2 s complement of the number of words to be transferred At the end of each transfer the word count register 15 incremented When the contents of the WCR is incremented to zero transfers are terminated READY is set and if enabled an interrupt is requested The WCR is word addressable only 3 2 1 2 Bus Address Register BAR The BAR is a 15 bit read write register This register is loaded under program control with a bus address not including address bit 0 which specifies the location to or from which data is to be transferred The BAR is incremented after each transfer and can be incremented across 32K memory boundaries via the extended address feature of the DRV11 B Sys tems with only 16 address bits will wrap around to location zero when the extended address bits are incremented The BAR is word addressable only 3 2 1 3 Control Status Register CSR The CSR is 16 bit register used to control the functions and monitor the status of the interface Bit 00 is a write only bit and always reads as a zero Bits 01 06 and bits 08 and 12 are read write bits wh
4. B general purpose DMA DRV11 s manual terface user In ff R 1 P 444444 444444 ri Lu W m sarissa ih itt AA k EK DRV 1 B OP 001 DRV11 B general purpose DMA interface user s manual digital equipment corporation marlborough massachusetts 151 Edition August 1976 Copyright O 1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice Digital Equipment Corporation assumes no respon sibility for any errors which may appear in this manual Printed in U S A This document was set on DIGITAL s DECset 8000 computerized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DEC DECtape PDP DECCOMM DECUS RSTS DECsystem 10 DIGITAL 8 DECSYSTEM 20 MASSBUS 11 UNIBUS CHAPTER 1 1 1 1 2 1 3 2 2 1 2 2 2 24 2 223 2 2 4 2 3 2 4 2 5 2 6 PATI 2 8 CHAPTER 3 3 1 E 3 2 1 3 2 1 2 3 2 1 4 3 2 2 3219 3 2 4 3 2 4 1 32225 3 3 CHAPTER 4 4 1 4 2 4 3 4 3 1 4 3 2 4 3 3 4 3 4 CONTENTS INTRODUCTION GENERA
5. Figure 1 1 shows the primary interface signals between the DRV11 B and the user s I O device DMA input DATI or output DATO data transfers take place when the processor clears READY For a DATO cycle DRV11 B to memory transfer the user s I O device presets the CONTROL BITS word count increment enable bus address increment enable CO A00 and ATTN and asserts CYCLE REQUEST to gain use of the LSI 11 bus When CYCLE REQUEST is asserted input data is latched into the input DBR the CONTROL BITS are latched into the DRV11 B DMA control and BUSY goes low DATI cycle memory to DRV11 B transfer is handled in a similar manner except that the output data is latched into the output DBR during the bus cycle 1 1 6 OUTPUT DATA BITS CYCLE REQUEST FUNCTION BITS STATUS BITS DEVICE 16 DATA ADDRESS BITS DRV11 B DMA INTERFACE BUSY CONTROL BITS 1 BUS CONTROL 1 6 INPUT DATA BITS 11 4155 Figure 1 1 DRVII B Simplified Interface Diagram When the DRV11 B becomes bus master a DATO or DATI cycle is performed directly to or from LSI 11 memory location specified by the BAR At the end of each cycle the WCR and BAR are incremented and BUSY goes high while READY remains low A second DATO or DATI cycle is performed when the user s I O device again asserts CYCLE REQUEST DMA transfers will continue asynchronously until the WCR increments to zero at which time READY goes high and the DRV11 B
6. PROCESSOR 11 4187 Figure 3 2 DATO DATOB Data Flow Diagram When the GO bit of the CSR is written to a READY goes low and the user s I O device conditions the A00 INC ENB WC INC ENB ATTN SINGLE CYCLE high for normal DMA transfers and the CO Cl refer to Table 3 1 lines and then asserts CYCLE REQUEST The INPUT DATA BITS and control bits Cl and SINGLE CYCLE are latched into the respective DRV11 B registers CYCLE REQUEST sets CYCLE and causes the DRV11 B to assert BDMR which makes anLSI Il bus request and causes BUSY to go low In response to BDMR the processor asserts BDMGO which is received as BDMGI The DRV11 B becomes bus master and asserts BSACK and negates BDMR The processor then terminates the bus grant sequence by negating BDMGO As bus master the DRV11 B performs a DATO or DATOB bus cycle by placing the memory address on BDAL lines asserting BWTBT and then asserting BSYNC The LSI 11 memory decodes the address then the DRV11 B removes the address from the BDAL lines negates BWTBT BWTBT will remain active for a DATOB and then places the user s input data on the BDAL lines and asserts BDOUT Memory receives the data and asserts BRPLY In response to BRPLY the 1 negates BDOUT and then removes the user s input data from the BDAL lines Memory now negates BRPLY the bus cycle is terminated and the bus is released when the DRV11 B negates BSACK and BSYNC At the end of
7. 3 2 1 4 Input and Output Data Buffer Registers DBRs The two DBRs are 16 bit registers The input DBR is a read only register the output DBR is a write only register Data is loaded into the input DBR by the user s device and subsequently transferred to memory under DMA control by the DRVI11 B or under program control by the LSI 11 processor Conversely data is written into output DBR from memory under DMA control by the DRV11 B or under program control by the LSI 11 processor and read by the user s device The input and output DBRs interface to the user s device by means of two separate 40 pin I O connectors These connectors may be cabled together for maintenance purposes to function as a read write register The input and output DBRs share the same bus address and are byte and word addressable 3 2 2 User Interface Lines There are 50 interface lines 25 per connector between the DRV11 B and the user s I O device Of these lines 32 are I O data lines 3 are for status and 15 are for control A brief description of these interface lines follows Mnemonic Description 00 OUT 15 OUT 16 TTL data output lines from the DRV11 B One high 00 IN 15 IN 16 TTL data input lines from the user s device One high STATUS A B C Three TTL status input lines from the user s device The func tion of these lines is defined by the user FUNCT 1 2 3 Three TTL output lines to the user s device The function of these lines is defined
8. BDAL lines by the memory and the memory asserts BRPLY The input data is accepted by the DRVII B and BDIN is negated Memory negates BRPLY and the DRV11 B negates BSACK and BSYNC to terminate the bus cycle and release the bus The OUTPUT DATA BITS for the user s I O device are stored in the DRV11 B output data buffer register These bits can be read by the user s device at the low to high transition of BUSY m USERS q gt s JS M E DATI OR DATIO DATA FLOW LSI PROCESSOR 11 4188 Figure 3 3 DMA DATIO DATI Data Flow Diagram At the end of the first transfer the DRV11 B WCR and BAR are incremented BUSY goes high while READY remains low The user s device can initiate another DATI or DATIO cycle by again setting CYCLE REQUEST transfers to the user s device can continue until the WCR increments to zero and causes an interrupt request to be generated Paragraph 3 2 4 1 3 3 TIMING Input and output timing for the DRV11 B is shown in Figures 3 4 through 3 7 The timing diagrams show user signal timing for single cycle and burst mode operations which can be either program or user initiated 3 8 6 1ST CYCLE NTH CYCLE LAST CYCLE READY OUTPUT X c O ns MIN O ns MIN WC INC ENB BA INCENB CO C1 ATTN AOO DATA IN INPUTS SINGLE CYCLE INPUT CYCLE REQUEST INPUT Ons
9. MIN BUSY OUTPUT 250ns MIN 250ns MIN 250 ns MIN N N LEGEND DATO OR DATOB BUS CYCLE Ci 1 DATI OR DATIO BUS CYCLE O Figure 3 4 1 Single Cycle User Initiated Timing Diagram i J Ons MIN 250ns MIN 11 4161 OI 1ST CYCLE NTH CYCLE LAST CYCLE LOW HERE WHEN USED TO SET UP THE CONTROL INPUTS READY OUTPUT V N NE _ WC INC ENB BA INC 7 DATA IN INPUTS ZN WEM N 1 SINGLE CYCLE INPUT Z 11 a 50ns MIN e TN pns MIN Ons MIN Wu DU BUSY OUTPUT 250ns MIN LEGEND DATO OR DATOB BUS CYCLE Ci 1 xx DATI OR DATIO BUS CYCLE O 250 5 MIN 250ns MIN 11 4277 Figure 3 5 DRVII B Single Cycle Program Initiated Timing Diagram Ilt 1ST CYCLE NTH CYCLE LAST CYCLE READY OUTPUT pe WC INC ENB BA INC ENB CO C1 ATTN DATA IN INPUTS ic u SN Figure 3 6 DR VII B Burst Mode User Initiated Timing Diagram LEGEND SEE __ 150 ne MAX I 150 oli 250 5 MIN mE m ee non K X 11 4164 B Burst Mode Program Initiated Timing Diagram CHAPTER 4 PROGRAMMING 4 41 GENERAL This chapter p
10. from the LSI 11 memory Interrupts are explained in greater detail in Chapter 4 of this manual 3 2 5 LSI 11 Memory to User s Device Transfers DATIO or DATI DMA transfers from the LSI 11 memory to the user s I O device occur in a manner similar to that described for user s I O device to memory transfers Figure 3 3 illustrates the data flow for a DMA DATIO or DATI cycle Under program control the DRV11 B WCR Figure 3 1 is loaded with a count equal to the number of transfers while the BAR is loaded with the starting address from which the first word will come the CSR is set for transfers With the CSR set READY goes low and the user s I O device conditions the CO C1 lines refer to Table 3 1 for a DATI or a DATIO and conditions the WC INC ENB BA INC ENB ATTN SINGLE CYCLE high for normal DMA transfers and asserts CYCLE REQUEST BUSY from the DRVII B goes low and the user s control bits are latched into the DRV11 B The DRV11 B then asserts BDMR which makes a bus request When the request is arbitrated as described in Paragraph 3 2 4 the DRV11 B becomes bus master When the DRV11 B becomes bus master a DATI or DATIO bus cycle is performed a DATI is described The DRV11 B places the address of the memory location from which the first word is taken on the lines and asserts BSYNC Memory decodes and latches the address The DRV11 B then removes the address from the BDAL lines and asserts BDIN Input data is now placed on the
11. generates an interrupt if interrupt enable is set to the LSI 11 processor If burst mode is selected SINGLE CYCLE low only one CYCLE REQUEST is required for the complete synchronous transfer of the specified number of data words 1 2 SPECIFICATIONS The following specifications and particulars are for informational purposes and are subject to change without notice Physical m E Quad height single width extended length module Dimensions 8 1 2 in L 10 1 2 in H 1 2 in W 21 6 cm L 26 7 cm H 1 27 cm W Weight 13 oz 370 gr User I O Connections Two 2 40 pin connectors Mounting Requirements Plugs directly into LSI 11 backplane or LSI 11 expansion backplane Electrical Logic Power Requirements 5 V 5 1 9 A nominal LSI 11 Bus Loading Presents one bus load User Loading Input Data Lines 1 TTL unit load each HIGH Logic one LOW Logic zero Input Control Lines TTL unit load each HIGH Logic one LOW Logic zero Output Data Lines 10 TTL unit loads drive each HIGH Logic one LOW Logic zero Output Control Lines 10 TTL unit loads drive each HIGH Logic one LOW Logic zero Module Type M7950 Operational Transfer Mode DMA or program controlled with interrupts Data Transfer Rate Up to 250 000 16 bit words per second in single cycle mode Up to 500 000 16 bit words per second in burst mode Environmental Temperature Storage 40 to 66 C 40 to 150 F Ope
12. the first transfer the DRV11 B WCR and BAR incremented BUSY goes high while READY remains low With BUSY high and READY low the user s I O device can initiate another DATO or DATOB cycle by again asserting CYCLE REQUEST DMA transfers can continue until the WCR increments to zero and generates an interrupt request if the interrupt enable bit is set 3 2 4 1 Interrupts When the WCR increments to zero READY goes high and the DRV11 B gener ates an interrupt request if the interrupt circuits are enabled The LSI 11 processor responds to the interrupt request BIRQ by asserting BDIN followed by BIAKI interrupt acknowledge BIAKI is received by the DRV11 B and in response places a vector address on the lines asserts BRPLY and negates BIRQ The LSI 11 processor receives the vector address and negates BDIN and BIAKI The DRVII B now negates BRPLY while the processor exits from the main program and enters a service program for the DRV11 B as indicated by the vector address Interrupt requests from the DRV11 B occur for the following conditions l When the WCR increments to zero this is a normal interrupt at the end of a designated number of transfers 2 When the user s I O device asserts ATTN this is a special condition interrupt which may be defined by the user to override the WCR 3 When a nonexistent memory location is addressed by the DRV11 B this special condition interrupt is produced when no BRPLY is received
13. when addressing a device for program controlled transfers The DRV11 B can assert BBS7 and address other devices on the LSI 11 bus without processor intervention Two bus lines one is DMA grant in the other is DMA grant out The LSI 11 processor generates BDMGO which is routed to the BDMGI pin of the first bus device If the device is requesting the bus it will inhibit passing BDMGO to the next bus device If the device is not requesting the bus it will pass BDMGO as BDMGI to the next device One bus line asserted low by the LSI 11 processor to initialize or clear devices connected to the LSI 11 bus One bus line BSACK is asserted low by a DMA device in response to the LSI 11 processor s BDMGO signal indicating that the DMA device is bus master One bus line a device asserts this signal for DMA requests and to become bus master 3 5 3 2 4 User s I O Device to LSI 11 Memory Transfer DATO or DATOB Data transfers from the user s I O device to the LSI 11 memory are DMA transfers Figure 3 2 illus trates the data flow for DMA DATO or DATOB cycle Referring to Figure 3 1 DMA transfers are initialized under program control by loading the DRV11 B WCR in 2 s complement with a count equal to the number of words to be transferred loading the BAR with the starting memory address for word storage and setting the CSR for transfers USERS DATO OR DATOB lt DATA FLOW LSI 11
14. ECTION Vector addresses 0 17744 are reserved for LSI 11 system users The DRVII B is vector address 1248 The user selects the interrupt vector address by means of switches on the DRV11 B module Figure 2 1 shows the location of the vector address selection switches Vector address selec tion switches are set to the ON closed position for bits to be encoded as ONE bits in the vector address Bits encoded as ZERO bits in the address have their switches set to the OFF open posi tion Figure 2 3 shows the address select format and presents the switch to bit relationship for the vector address selection switches DEVICE ADDRESS SELECTION SWITCHES VECTOR ADDRESS SELECTION SWITCHES 11 4156 Figure 2 1 DRVII B Connector and Switch Locations DECODED FOR E 1 4 DECODED BY 8857 SELECTED BY SWITCHES REGISTERS Sa DEVICE ADDRESS SELECTION SWITCHES OFF ZERO ONE 11 4184 Figure 2 2 DRVII B Device Address Select Format 2 6 MODULE INSTALLATION With the exception of the first four slots the LSI 11 processor always occupies the first slots the DRVII B can be installed into any four slots Paragraph 2 2 4 of the LSI 11 backplane However if REV11 refresh option is used the DRV11 B must be at a lower priority than the REV11 When inserting the module into the backplane make sure that the deep notch on the module seats against the connector block rib Do not insert or rem
15. L DESCRIPTION 5 ste y p p um NOU rure a us SPECIFICATIONS ecg W S Oh P iod eb d RELATED LITERATURE 22 93 prr INSTALLATION GENERAL PRU deci quU ee SUS Me EUR Org os EVE EU IE SYSTEM CONSIDERATIONS Lolli Bus Loading 220 2246 us Power Requirements s aop ds ooi Priority Requirements s lt es as d Space Requirements om doxes BS ewe xe E UB EOS USER TO CABLES As uibem uu xx ue RA Peg Sa Se DEVICE ADDRESS SELECTION 2 2 2 4 5 INTERRUPT VECTOR ADDRESS SELECTION MODULE INSTALLATION RR E INITIAL TURN ON T C DIAGNOSTIC PROGRAM BASIC OPERATION uuu hus spontan SD qu uk uio a dv iie Ai fa teak di ue FUNCTIONAL DESCRIPTION DRVITB mem dine S hose dex Word Count Register WCR Bus Address Register BAR Control Status Register CSR Input and Output Data Buffer Registers DBRs User nterface LINES aeu 6 6 pem UM Se ex uo oss z s p w k u NO DE Q k dog A User s I O Device to LSI 11 Memory Transfer DATO or DATOB s
16. MGO BDMR Description One bus line asserted low in response to BDIN or BDOUT and in response to BIAK transactions It is generated by the slave device for address recognition One bus line when asserted low during BSYNC time indicates an input transfer with respect to the bus master Requires a BRPLY response BDIN is asserted when the bus master is ready to accept data from the slave When asserted without BSYNC indicates that an interrupt operation is occurring One bus line asserted low by the bus master to indicate that it has placed an address on the BDAL lines The transfer is in progress until BSYNC is negated high One bus line asserted low during address time to indicate that an output sequence DATO or DATOB is to follow BWTBT is also asserted during data time for byte addressing during a DATOB One bus line device asserts low this line when its interrupt enable interrupt request and ready flip flops are set BIRQ informs the LSI 11 processor that service is requested Two bus lines one 1 is interrupt acknowledge in the other is interrupt acknowledge out BIAKI is generated by the LSI 11 processor in response to BIRQ The processor asserts low BIAKO which is routed to the BIAKI pin of the first device on the bus If the device is not requesting an interrupt BIAKO 15 passed as to the next device One bus line asserted low by the LSI 11 processor
17. XX H856to H856 Shielded flat 1 6 10 12 20 25 50 ft 0 305 1 830 3 050 3 66 6 100 7 625 15 250 m BC04Z XX H856 to open Shielded flat 6 10 15 25 50 ft end 1 830 3 050 4 575 7 625 15 250 m 2 4 DEVICE ADDRESS SELECTION The DRV11 B contains five registers the WCR the BAR the CSR the input DBR the output DBR These registers must be addressed for data and status transfers between the DRV11 B and the LSI 11 processor The two 2 DBRs use the same address The register addresses are sequential by even numbers and are as follows Register BBS7 Octal Address WCR 1 1 XXXXX2 CSR 1 XXXXX4 DBRs x l XXXXX6 The assigned DMA interface base address is 772410s The user selects a base address for assignment to the WCR and sets the device address selection switches on the DRV11 B module to decode this address The remaining BAR CSR and DBR addresses are then properly decoded by the module as they are received from the LSI 11 processor Figure 2 1 shows the location of the device address selection switches on the 1 module Switches are set to the ON closed position for bits to be decoded as ONE bits in the base address Bits decoded as ZERO bits in the address have their switches set to the OFF open position Figure 2 2 shows the address select format and presents the switch to bit relationship for the device address selection switches 2 5 INTERRUPT VECTOR ADDRESS SEL
18. by the user INIT One TTL output line used to initialize the user s device INIT V2 One TTL output line present when INIT is asserted or when FUNCT 2 is written to a one Used for interprocessor buffer applications A00 One TTL input line from the user s device This line is normally high for word transfers During byte transfers this line controls address bit 00 BUSY One TTL output line to the user s device BUSY is low when the DRV11 B DMA control logic is requesting control of the LSI 11 bus or when cycle is in progress A low to high tran sition indicates end of cycle READY One TTL output line to the user s device When the READY line goes low DMA transfers may be initiated by the user s device Cl Two 2 TTL input lines from the user s device These lines con trol the LSI 11 bus cycle for DMA transfers CO C1 codes for the four 4 possible bus cycles are listed in Table 3 1 3 3 Mnemonic SINGLE CYCLE WC INC ENB BA INC ENB CYCLE REQUEST ATTN 3 23 LSI 11 Bus Lines Description Table 3 1 C0 C1 Codes Bus Cycle One TTL input line from the user s device This line is internally pulled high for normal DMA transfers For burst mode oper ation SINGLE CYCLE is driven low by the user s device CAUTION When single cycle is driven low total system oper ation is affected because the LSI 11 bus becomes dedicated to the DMA device and other devices including the MOS memory ref
19. cates that the DRV11 B is able to accept a new command Set by INIT WCOFLO ERROR cleared by GO bit 00 CYCLE Read write bit CYCLE is used to prime a DMA bus set by CYCLE REQUEST cleared during DMA cycle INIT STAT A Read only bits Three device status input bits that indicate the state of the DSTAT A B and C user signals MAINT Read write bit Maintenance bit for use with the MAINDEC diagnostic ATTN Read only bit Indicates the state of the ATTN user signal sets READY ERROR NEX Read write to zero bit 1 Nonexistent memory indicates that as bus master the DRV11 B did not receive BRPLY or that a DATIO cycle was not completed 2 Sets ERROR 3 Cleared by INIT or by writing it to a zero 4 3 Table 4 1 CSR Bit Functions Cont Bit Function 15 ERROR Read only bit 1 Indicates one of the following special conditions NEX bit 14 b ATTN bit 13 2 Sets READY bit 7 and causes an interrupt if IE bit 6 is set 3 Cleared by removing the sp cial condition as follows is cleared by writing bit 14 to a zero b ATTN is cleared by the user device 4 4 CUT OUT ON DOTTED LINE INTERFACE USER S MANUAL EK DRV1B OP 001 DRV11 B GENERAL PURPOSE DMA Reader s Comments Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications What is your general reaction to this manual In your judgment is it comp
20. e locations The terminal will indicate the following WCR contents will be 000000 BAR contents will be 000001 CSR contents will be 127200 DBR contents will be 177777 2 TheWCR and BAR can be loaded with data from the system terminal and the correspond ing data read back on the terminal BAR bit 0 will read as a one 1 with no I O cables connected The user s I O device cables can now be connected to the DRV11 B Figure 2 1 2 8 DIAGNOSTIC PROGRAM The check procedure performed in Paragraph 2 7 does not completely verify the operation of the DRVII B Complete module operation can be verified through the use of the diagnostic software program MAINDEC MD 11 DVDRA PB The program can be loaded into the LSI 11 system by means of a paper tape reader a terminal A BCO8R maintenance cable not longer than 50 ft is required to loop the DBR output to the DBR input for checking the I O data path A complete description of the diagnostic software program and its implementation is provided in MAINDEC MD 11 DVDRA D 2 5 CHAPTER 3 BASIC OPERATION 3 1 GENERAL This chapter contains a functional description of the DRV11 B The DRV11 B registers are described as well as user device and bus operations necessary to perform DMA transfers Figure 3 1 is a block diagram of the DRV11 B descriptions are written to this diagram The chapter ends with a brief description of the timing associated with DMA transfers 3 2 FUNCTIONAL DESCRIPTION
21. ile bits 07 09 11 and 13 15 are read only bits Bit 14 can be written to a zero Bits 04 and 05 are the extended addressing bits CSR bit functions are fully described in Chapter 4 The CSR is both byte and word addressable 3 1 Ct BWTBT L OUTPUT DATA BITS OUTPUT n DIEA 0 15 OUT H BBS7 L BUFFER REGISTER DBR eron CSR 16 BUS DATA ADDRESS VECTOR BITS BDAL OO 151 BAD 17L BA INC ENB H BUS ADDRESS REGISTER BAR ADDRESS DA 00 15 3 STATE BUS DATA ADDRESS BITS DA OO 15H WORD COUNT DAOO 15 H WORD COUNT WC INC ENB H REGISTER WCR TRANS CEIVERS e imc ERROR 0415 DEVICE ADDRESS ADORESS 0 14 READY H p eser inan SWITCHES 0 13 FNCT 1 2 3H ATTN H MAINT 0 12 DEVICE VECTOR ADDRESS SE PREIS STATUS A B C DA11 10 09 GENERATOR SWITCHES CONTROL STAT ABCH CYCLE DAO8 READY DAO7 IE DAO6 XAD 16 17 DAO4 05 STATUS REGISTER CSR USER S I 0 DEVICE READY 1 H INTERRUPT LOGIC BIAKI L M BIAKO L BIRQ L 2 GO DA IE 1 H qa z gt N PROTOCOL LOGIC INPUT DATA BITS 0 15 IN H REGISTER SELECTS DMA CONTROL LOGIC 11 4160 Figure 3 1 DRVII B Block Diagram
22. lete accurate well organized well written etc Is it easy to use What features are most useful What faults do you find with the manual Does this manual satisfy the need you think it was intended to satisfy Does it satisfy your needs Why Would you please indicate any factual errors you have found Please describe your position Street Department Ca Sheu ip COTY FIRST CLASS PERMIT NO 33 MAYNARD MASS BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES A Postage will be paid by Digital Equipment Corporation Technical Documentation Department Digital Park PK3 2 Maynard Massachusetts 01754
23. ove the module with power applied After performing the initial turn on Paragraph 2 7 connect the user s I O cables to and J2 on the DRV11 B I O connectors Connector locations for the DRV11 B are shown in Figure 2 1 Pin assignments for and J2 are shown in Figure 2 4 and are specified in Paragraph 1 2 2 3 SELECTION SWITCHES SINGLE CYCLE H N OUT OUT OUT OUT OUT OUT OUT I I VECTOR ADDRESS IST OCTAL DIGIT 2 ND OCTAL DIGIT 4 TH OCTAL DIGIT O OR 4 3 RD OCTAL DIGIT PREASSIGNED AS ZEROS SSS s i OFF 2 ON ONE 11 4185 Figure 2 3 DRVII B Interrupt Vector Address Select Format INIT V2 H READY H WC INC ENB H STATUS A H INIT H STATUS B H STATUS C H 8 OUT gt 9 OUT 10 OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT T I I Do X J1 CYCLE REQUEST H 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN O IN I Ir I I T I ITI I J2 Figure 2 4 DRVII B Connector Pin Assignments BUSY H ATTNH AOO H BA INC ENB H FNCT 3 H CO H FNCT 2 H C1 H IN IN IN IN IN IN IN IN I T I Ir TK I IT 11 4159 2 7 INITIAL TURN ON After completing the module installation turn on the LSI 11 and initialize the system With no I O cables connected and using the LSI 11 terminal and operating procedures perform the following l Load the addresses of the WCR BAR CSR and DBRs through the system terminal and examine th
24. rating 5 to 50 C 41 to 122 F Relative Humidity 10 to 95 noncondensing 1 3 1 3 RELATED LITERATURE In addition to the M7950 print set the LSJ 1 PDP 11 03 User s Manual and the LSI 11 PDP 11 03 Processor Handbook contain useful information for installing and operating the DRV11 B general purpose DMA interface Handbooks may be ordered from the nearest Digital Equipment Corporation Sales Office 1 4 CHAPTER 2 INSTALLATION 2 1 GENERAL Installation of the DRV11 B general purpose DMA interface consists of selecting the device and inter rupt vector addresses and then inserting the interface into an LSI 11 processor system 2 2 SYSTEM CONSIDERATIONS Before installing the DRV11 B into an LSI 11 system consideration must be given to bus loading power priority and space requirements 2 2 1 LSI 11 Bus Loading The DRVII B presents one bus load to the LSI 11 bus Fifteen 15 bus loads can handled by the LSI 11 bus therefore the user must determine the LSI 11 bus load when installing additional LSI 11 modules 2 2 2 Power Requirements The 1 requires 5 V 590 1 9 A nominal Power for the DRV11 B is obtained from the LSI 11 system power supply 2 2 3 Priority Requirements Each device on the LSI 11 bus has an interrupt and DMA priority based on its relative position from the processor Since the user may install the DRV11 B on the bus along with other devices that use the same interrupt or DMA priori
25. resents basic programming information for the DRVII B The types of programming instructions the use of the registers program interrupts and special program considerations are presented 4 2 PROGRAMMING INSTRUCTIONS All programming instructions used for the LSI 11 processor may be used for programming the DRVI1 B 4 3 DRVII B REGISTERS Five registers are used by the DRVI11 B Word Count WCR Bus Address BAR Control Status CSR Input and Output Data Buffers DBRs The input and output data buffer share the same bus address while WCR BAR and CSR have unique addresses 4 3 1 WCR Load the 16 bit WCR with the 2 s complement negative number of DMA data transfers At the end of each cycle the WCR is incremented by one When the last transfer is made the WCR 15 incremented to zero and an interrupt is requested The WCR is not byte addressable 4 3 2 BAR Load the 15 64 BAR with the address that specifies the memory location into which the first word is written or from which the first word is read Following the transfer of each word the BAR is incremented by two to point to the next higher sequential memory word location If the BAR over flows it will increment the extended address bits and wrap around to location zero Address bit A00 used for byte transfers is driven by the user s device The BAR is not byte addressable 4 3 3 CSR The 16 bit CSR is monitored for interface status and loaded wi
26. resh function cannot One TTL input line from the user s device This line is normally high to enable incrementing the DRV11 B word counter Low inhibits incrementing One TTL input line from the user s device This line is normally high to enable incrementing the bus address counter Low inhibits incrementing One TTL input line from the user s device low to high transi tion of this line initiates request One TTL input line from the user s device This line is driven high to terminate DMA transfers to set READY and request an interrupt if the interrupt enable bit is set There are 34 LSI 11 bus signal lines used by the DRV11 B 16 of these are multiplexed and bidirection al lines which carry data and address bits Two lines are used for extended address bits while 16 lines are used for control signals A brief description of the 34 bus lines follows Mnemonic BDAL 0 BDAL 15 BAD 16 17 BDOUT Description 16 bus data address lines An address is first placed on these lines followed by the data These lines are asserted when driven low Two 2 bus lines used to address beyond 32K of memory by the 11 These lines are asserted when low One bus line when asserted low indicates that data is available on the BDAL lines and an output transfer with respect to the bus master is taking place 3 4 Mnemonic BRPLY BDIN BSYNC BWTBT BIRQ BIAKI BIAKO BBS7 BDMGi BD
27. th control bits The CSR is byte addressable Figure 4 1 shows the CSR bit assignments The function of each bit is described in Table 4 1 4 3 4 DBRs The DRBs hold the 16 bit data words for transfer to memory from the user s I O device input DBR or from the memory to the user s I O device output DBR Both share the same bus address and are word and byte addressable 4 4 4 PROGRAM INTERRUPTS DRVII B interrupts are enabled by setting bit 06 IE of the CSR when the GO 00 is issued Figure 4 1 and Table 4 1 Interrupts can occur for the following reasons 1 Word count overflow normal interrupt 2 CSR ERROR bit bit 15 set special condition 4 4 1 Word Count Overflow An interrupt request is generated when the DRVII B WCR increments to zero and produces WC OFLO word count overflow WC OFLO sets READY in the CSR at the end of the DMA cycle 4 4 2 CSR ERROR Bit Bit 15 The CSR ERROR bit can set for two possible reasons l when bit 14 of the CSR is set or 2 when CSR bit 13 ATTN is set CSR bit 14 is set when a nonexistent NEX memory location is addressed and a reply from the addressed location is not received within 15 Bit 14 will set if a DATO bus cycle does not occur 30 us after performing a DATIO bus cycle ATTN bit 13 sets the CSR ERROR bit when the user s I O device drives ATTN high ATTN is a user defined function which can be utilized to generate an interrupt request
28. ty the user must bear in mind that when more than one device is requesting service the device electrically nearest the LSI 11 microprocessor has the highest priority and will be serviced first In addition if the REV11 refresh option is used the REV11 must be at a priority level higher than that of the DRVII B Refer to the LSI 11 PDP 11 03 User s Manual Appendix G for detailed information on the REVI1 options 2 2 4 Space Requirements The DRV11 B requires four module slots Of the ous slots the and B module fingers must interface to the LSI 11 bus The C and D fingers maintain interrupt and DMA grant continuity as well as power and ground 2 3 USER I O CABLES The DRV11 B has two 40 pin connectors which provide the interface to the user s device Two cable assemblies are required It is recommended that cable assemblies from Table 2 1 be used to connect the 11 to the user s device The listed cables are terminated one or both ends with H856 40 pin connectors that mate with the connectors on the DRV11 B Cable selection is determined by the type of connections used on the user s device The desired cable length XX must be specified when order ing Lengths longer than 50 feet are not recommended for use with the DRV11 B Cables may ordered from the nearest Digital Equipment Corporation Sales Office Non standard length caoles may be ordered at additional cost 2 Table 2 1 Recommended Cable Assemblies BCOSR
29. ui CD LSI 11 Memory to User s Device Transfers DATIO or DATD TIMING eRe Wed oe ee x PROGRAMMING GENERAL SC R dd es 4 PROGRAMMING INSTRUCTIONS DRVII BREGISTERS WOR us nu ind Bus s Se ii CONTENTS Cont Page 4 4 PROGRAM INTERRUPTS 4 2 4 4 1 Word Count Overflow M 4 2 4 4 2 CSR ERROR Bit Bit 15 LT TT 4 2 45 FUNCTION AND STATUS BITS 4 2 ILLUSTRATIONS Figure No Title Page E DRV11 B Simplified Interface Diagram 22e 1 2 2 1 DRV11 B Connector and Switch Locations 2 3 2 2 DRV11 B Device Address Select Format 2 3 2 3 DRV11 B Interrupt Vector Address Select Format 2 4 2 4 DRV11 B Connector Pin Assignments 2 4 3 1 DRVII BBlock Diagram 3 2 3 2 DATO DATOB Data Flow Diagram 3 6 3 3 DMA DATIO DATI Data Flow Diagram 3 8 3 4 DRV11 B Single Cycle User Initiated Timing Diagram 3 9 3 5 DRV11 B Single Cycle Program Initiated Timing Diagram 3 10 3 6 DRV11 B Burst Mode User Initiated Timing Diagram 3 11 3 7 DRV11 B Burst Mode Program Initiated Timing Diagram 3 12 4 CSR Format a wi aie estes BE ee
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