HAL25_V2 User Manual v0.2 C. COLLEDANI, C. HU, A
Contents
1. Laboratoire d Electronique et de Physiqi stitut de Syst mes dr Subatomiques 15 BOURG User Manual HAL25 V2 User Manual v0 2 C COLLEDANI C HU A BROGNA J D BERST Laboratoire d Electronique et de Physique des Syst mes Instrumentaux Institut de Recherches Subatomiques LEPSI IN2P3 CNRS ULP Strasbourg France A M IN2P3 ul SS Sea p SCIENTIFIQUE 1 s UNIVERSIT LOUIS PASTEUR Institut NATIONAL DE PHYSIQUE NUCL AIRE SBOURI ET DE PHYSIQUE DES PARTICULES Document history HAL25 10 15 02 HAL V2 Version Date Description 0 2 19 08 2002 Bias settings updated for positive and negative pulses 0 1 12 12 2001 Based VI New pad list e VBUF DAC still exist but no more used IREF pad specified as test purpose only Transparent mode POWER_ENA register state specified HAL VI Version Date Description 0 2 24 10 2001 Physical size schematic updated 0 1 08 06 2001 Draft version before HAL25 returns from foundry HAL25 V2 User Manual v0 1 1 3 Control apt 4 JT AG 4 JTAG Register Set E H ROES 4 Bypass e Ense Cio REEL re Rees 4 Boundary2. e o lane S 25 B TRE N L I i n E P v EJ Li ii lt Butterfly3 3 g 3550 4500 E A ES V H 5450 V Units in um E pad positions are measured _ 5 d from the center of the pad Origine is given by butterfly 1 3 10 15 02 HAL25_V2 User Manual v0 1 Pad Layout 10 15 02 Front End Pads TOP Back End Pads C AIN lt 127 gt C AIN lt 64 gt C AIN lt 63 gt L AIN lt 0 gt GND GEN GND VDD GEN VDD VDD TKIN LVDS TK INP LVDS TK INN LVDS TK OUTP LVDS TK OUTN VDD TKOUT VDDD CORE GNDD CORE GNDD PERI VDDD PERI LVDS FRSTP LVDS_FRSTN LVDS_PULSEP LVDS_PULSEN LVDS HOLDP LVDS HOLDN LVDS_RCLKP LVDS_RCLKN TK_IN_C VDDD CORE GNDD CORE GNDD PERI VDDD PERI TK_OUT_C TDI TCK TDO N VDD VDD GEN v A N AN_OUTN AN_OUTP GND GEN GND VDD GEN VDD VDD PERI GND PERI TMS TRSTB PWRRSTB EnableJTAG VDDD CORE GNDD CORE ManRdRegEN ManRdRegSHB ID lt 3 gt ID lt 2 gt 1 lt 1 gt ID lt 0 gt VDDD PERI GNDD PERI GNDD CORE VDDD CORE VDD PERI GND PERI
3. Unit in micrometers __ Pin x x XCenter Y Center X Pitch Y Pitch Length High 127 345740 5168500 465740 5231500 405 74 5200 120 126 345740 5088500 465740 5151500 405 74 5120 0 80 120 125 345740 5008500 465740 5071500 405 74 5040 0 80 120 124 345740 4928500 465740 4991500 405 74 4960 0 80 120 123 345740 4848500 465740 4911500 405 74 4880 0 80 120 122 345740 4768500 465740 4831500 405 74 4800 0 80 120 121 345740 4688500 465740 4751500 405 74 4720 0 80 120 120 345740 4608500 465740 4671500 405 74 4640 0 80 120 119 345740 4528500 465740 4591500 405 74 4560 0 80 120 118 345740 4448500 465740 4511500 405 74 4480 0 80 120 117 345740 4368500 465740 4431500 405 74 4400 0 80 120 116 345740 4288500 465740 4351500 405 74 4320 0 80 120 115 345740 4208500 465740 4271500 405 74 4240 0 80 120 114 345740 4128500 465740 4191500 405 74 4160 0 80 120 113 345740 4048500 465740 4111500 405 74 4080 0 80 120 112 345740 3968500 465740 4031500 405 74 4000 0 80 120 111 345740 3888500 465740 3951500 405 74 3920 0 80 120 110 345740 3808500 465740 3871500 405 74 3840 0 80 120 109 345740 3728500 465740 3791500 405 74 3760 0 80 120 108 345740 3648500 465740 3711500 405 74 3680 0 80 120 107 345740 3568500 465740 3631500 405 74 3600 0 80 120 106 345740 3488500 465740 3551500 405 74 3520 0 80 120 105 345740 3408500 465740 347
4. VDS or out common to LVDS or CMOS outputs TK OUT C BIAS DAC register BIAS DAC is 72 bits large it sets simultaneously 9 of the 10 DACs designed in HAL25 As show bellow these 8 bit DACs set the bias voltage and current of the 128 analogue channels the analogue multiplexer and the analogue output buffer The internal reference current source can also be adjusted After reset the register bits are set to 0 this fixed the minimum power consumption of the analogue channels The reference current source is set to its nominal value Bit Name DAC register 71 64 Shaper Current 1 sx per Current Bias2 55 48 VSHA Shaper Voltage Bias 30 MAT Current Bias 39 32 VPRE PreAmp Voltage Bias xs M Analogie Muliiplexer Curren Bias _ Multiplexer Current Bias 23 16 Output Buffer Current Bias S 8 BUE Qu Buffer Voltage Blas No more used Buffer Voltage Bias No more used _7 0 IREF Internal Reference Current Source Adjust PULSE_DAC register PULSE_DAC register is 8 bits large It set the current level of the analogue pulse generated by the test pulse logic After reset the register bits are set to 0 PULSE_REG register PULSE_REG register is 128 bits large It is used during Pulse Test Mode It selects the channel where the test pulse will be injected Up to 32 channels among the 128 can be selected A bi
5. 125 125 125 125 125 125 125 125 125 125 125 250 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 Y Pitch 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 Length HAL25 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 High 23
6. 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 400 320 240 160 160 240 320 400 480 560 640 720 800 880 960 1040 1120 1200 1280 1360 1440 1520 1600 1680 1760 1840 1920 2000 2080 2160 2240 2320 2400 2480 2560 2640 2720 2800 2880 2960 3040 3120 3200 3280 3360 3440 3520 3600 3680 3760 3840 3920 4000 HAL25 V2 User Manual v0 1 80 80 80 80 80 80 80 80 80 80 80 80 80 320 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 1
7. IPLS ISHA IBUF GNDREF ITEST IREF ISHCON25 VBUF VSHA IMUX IPRE VPRE VDD VDD GEN GND Krom NEN LL OTTOM GND GEN HAL25_V2 User Manual v0 1 PS85 PS84 PS83 PS82 7581 7880 PS79 PS78 PS77 PS76 PS75 PS74 PS73 PS72 PS71 PS70 PS69 PS68 PS67 PS66 PS65 PS64 PS63 PS62 PS61 PS60 PS59 PS58 PS57 PS56 7555 7554 7553 7552 7551 7550 7549 7548 PS47 PS46 PS45 PS44 PS43 PS42 PS41 PS40 PS39 PS38 PS37 PS36 PS35 PS34 PS33 PS32 PS31 PS30 PS29 PS28 PS27 PS26 PS25 PS24 PS23 PS22 PS21 PS20 PS19 7518 PS17 PS16 7515 7514 7513 PS12 7511 7510 7509 7508 PS07 PS06 PS05 PS04 PS03 PS02 7501 HAL25 Pad Coordinates Chip 4 esign dimens 55 74 Y1 5450 X2 sign dimension from butterfly origin 3594 26 unit ym Input Pads Size H 63um L 120uum Y Pitch 80um HAL25 E chip design dimension unit in um X Ao 3650 10900 10 15 02 HAL25 V2 User Manual v0 1 Coordinates of Passivation Opening in nm
8. Scan 5 BIAS DAC ITUR CEPR SERERE 5 PULSE d EE ooo EET ETE 5 PULSE register ccssscssscccssssssscesnoosesscsenseesssecsnesssnscennessrsscssscesensesonsesss ce MIO 5 READ 221 11 NONE 5 STATUS register 6 POWBR register 0000 ERE Dee 6 TOKEN 222 10 22 11 0 1 Ate eese eene ARD 6 EE NE 6 Running 25 ee EIE 6 Biasing HAL25 eerte tete teat a e eret NR 6 Readout sees ene rien eme eere eene doe as eee eee eese recente 7 Pulse Test 2 02 ri eene nete 9 Transparent Mode ettet eene ettet reete eee 9 Boundary Scan Test EE 7 10 Physical Size and Pad Layout sese reet eee eee eene sene teneret trei 11 Front End IRE ge eene rentre eben ede nnns rhet reasons 11 Back End ente tie a TR
9. 0 465740 1471500 405 74 1440 0 80 120 79 345740 1328500 465740 1391500 405 74 1360 0 80 120 78 345740 1248500 465740 1311500 405 74 1280 0 80 120 77 345740 1168500 465740 1231500 405 74 1200 0 80 120 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10 15 02 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 345740 1008500 928500 848500 768500 688500 608500 528500 448500 368500 288500 208500 128500 191500 271500 351500 431500 511500 591500 671500 751500 831500 911500 991500 1071500 1151500 1231500 1311500 1391500 1471500 1551500 1631500 1711500 1791500 1871500 1951500 2031500 2111500 2191500 2271500 2351500 2431500 2511500 2591500 2671500 2751500 2831500 2911500 2991500 3071500 3151500 3231500 3311500 3391500 347
10. 1500 3551500 3631500 3711500 3791500 3871500 3951500 4031500 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 1151500 1071500 991500 911500 831500 751500 671500 591500 511500 431500 351500 271500 191500 128500 208500 288500 368500 448500 528500 608500 688500 768500 848500 928500 1008500 1088500 1168500 1248500 1328500 1408500 1488500 1568500 1648500 1728500 1808500 1888500 1968500 2048500 2128500 2208500 2288500 2368500 2448500 2528500 2608500 2688500 2768500 2848500 2928500 3008500 3088500 3168500 3248500 3328500 3408500 3488500 3568500 3648500 3728500 3808500 3888500 3968500 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74 405 74
11. 1500 405 74 3440 0 80 120 104 345740 3328500 465740 3391500 405 74 3360 0 80 120 103 345740 3248500 465740 3311500 405 74 3280 0 80 120 102 345740 3168500 465740 3231500 405 74 3200 0 80 120 101 345740 3088500 465740 3151500 405 74 3120 0 80 120 100 345740 3008500 465740 3071500 405 74 3040 0 80 120 99 345740 2928500 465740 2991500 405 74 2960 0 80 120 98 345740 2848500 465740 2911500 405 74 2880 0 80 120 97 345740 2768500 465740 2831500 405 74 2800 0 80 120 96 345740 2688500 465740 2751500 405 74 2720 0 80 120 95 345740 2608500 465740 2671500 405 74 2640 0 80 120 94 345740 2528500 465740 2591500 405 74 2560 0 80 120 93 345740 2448500 465740 2511500 405 74 2480 0 80 120 92 345740 2368500 465740 2431500 405 74 2400 0 80 120 91 345740 2288500 465740 2351500 405 74 2320 0 80 120 90 345740 2208500 465740 2271500 405 74 2240 0 80 120 89 345740 2128500 __465740 2191500 405 74 2160 0 80 120 88 345740 2048500 465740 2111500 405 74 2080 0 80 120 87 345740 1968500 465740 2031500 405 74 2000 0 80 120 86 345740 1888500 465740 1951500 405 74 1920 0 80 120 85 345740 1808500 465740 1871500 405 74 1840 0 80 120 84 345740 1728500 465740 1791500 405 74 1760 0 80 120 83 345740 1648500 465740 1711500 405 74 1680 0 80 120 82 345740 1568500 465740 1631500 405 74 1600 0 80 120 81 345740 1488500 465740 1551500 405 74 1520 0 80 120 80 345740 140850
12. 2 5 V Supplies for digital IO pads i e buffers and protection 2522 GNDD PERI PERI GND diodes from 35 to 32 and from 29 to 24 Noted from 35 to 32 and from 29 to 24 Note4 PS18 VDD PERI 42 5 Supplies for Analogues pads 16 to 5 i e protection PSI7 sd GND PERI PERI GND 4 4 0 Note3 87 VDD TKIN TKIN 42 5 V 5 V Supplies LVDS_TK_IN Note5 LVDS_TK_IN pad Note5 PS722 2 5 V Supplies LVDS TK OUT pad Note6 VDD TKOUT TKOUT 42 5 V 5 V Supplies LVDS_TK_OUT pad 6 LVDS OUT pad Note6 Notes 1 2 If there is an unconnected pin a performance degradation of the specified parts may be observed If there is an unconnected pin the specified parts may have unknown behaviour 3 Ifthere is an unconnected pin there will be no ESD protection but the functionality of the chip will be maintained 4 If there is an unconnected pin the chip cannot be operated i e Reset and TMS signals are not operational 5 If VDD TKIN is unconnected LVDS TK IN is disabled The chip can be operated via the pad TK IN C 6 If VDD TKOUT is unconnected LVDS TK OUT is disabled The chip can be operated via the pad TK OUT C Readout Pads 10 15 02 HAL25 V2 User Manual v0 1 12 HAL25 PS76 LVDS TK INP Dig Input LVDS ES Positive Token Input Powered by VDD TK LVDS TK
13. 20 120 120 HAL25 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 21 Output Pads Size H 95um L 95um Y Pitch modulo 125um Pin 14 13 12 11 10 r2 o s o 3 oo 4111500 345740 4191500 345740 4271500 345740 4351500 345740 4431500 345740 4511500 345740 4591500 345740 4671500 345740 4751500 345740 4831500 345740 4911500 345740 4991500 345740 5071500 345740 5151500 345740 5231500 YI 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 465740 X2 4208500 4288500 4368500 4448500 4528500 4608500 4688500 4768500 4848500 4928500 5008500 5088500 5168500 Y2 1 Center Y Center X Pitch 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 Y Pitch 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 Length HAL25 6
14. 3 63 63 63 63 63 63 63 63 63 63 63 63 63 High Coordinates of Passivation Opening in nm micrometers __ Pad Slot xi Yi x2 Y2 XCenter Y Center X Pitch YPitch Length High PS 85 3418240 5140000 3513240 5235000 3465 74 _ 5187 5 95 95 PS 84 3418240 5015000 3513240 5110000 3465 74 5062 5 0 125 95 95 PS 83 3418240 4890000 3513240 4985000 3465 74 _ 4937 5 0 125 95 95 PS 82 3418240 4765000 3513240 4860000 3465 74 4812 5 oj 125 95 95 PS 81 PS 80 No Pads PS 79 PS 78 QUNM PS 77 3418240 4140000 3513240 4235000 3465 74 4187 5 0 625 95 95 PS 76 3418240 4015000 3513240 4110000 3465 74 4062 5 0 125 95 95 PS 75 3418240 3890000 3513240 3985000 3465 74 3937 5 o 125 95 95 PS 74 3418240 3765000 3513240 3860000 3465 74 38125 0 12 95 95 PS 73 3418240 3640000 3513240 3735000 3465 74 _ 3687 5 0 125 95 95 PS 72 3418240 3515000 3513240 3610000 3465 74 3562 5 0 125 95 95 PS 71 3418240 3390000 3513240 3485000 3465 74 _ 34375 0 125 95 95 PS 70 3418240 3265000 3513240 3360000 3465 74 3312 5 0 121 95 95 PS 69 3418240 3140000 3513240 3235000 3465 74 _ 3187 5 0 125 95 95 PS 68 3418240 3015000
15. 3513240 3110000 3465 74 3062 5 0 125 95 95 PS 67 3418240 2890000 3513240 2985000 3465 74 2937 5 0 125 95 95 PS 66 3418240 2765000 3513240 2860000 3465 74 2812 5 0 125 95 95 PS 65 3418240 2640000 3513240 2735000 3465 74 2687 5 0 125 95 95 PS 64 3418240 2515000 3513240 2610000 3465 74 2562 5 0 125 95 95 PS 63 3418240 2390000 3513240 2485000 3465 74 2437 5 0 125 95 95 PS 62 3418240 2265000 3513240 2360000 3465 74 2312 5 0 125 95 95 PS 61 3418240 2140000 3513240 2235000 3465 74 2187 5 oj 125 95 95 PS 60 3418240 2015000 3513240 2110000 3465 74 2062 5 0 125 95 95 PS 59 3418240 1890000 3513240 1985000 3465 74 1937 5 o 125 95 95 PS 58 3418240 1765000 3513240 1860000 3465 74 1812 5 0 125 95 95 PS 57 3418240 1640000 3513240 1735000 3465 74 1687 5 0 125 95 95 PS 56 3418240 1515000 3513240 1610000 3465 74 1562 5 0 125 95 95 PS 55 3418240 1390000 3513240 1485000 3465 74 1437 5 0 12 95 95 PS 54 3418240 1265000 3513240 1360000 3465 74 1312 5 o 12 95 95 PS 53 3418240 1140000 3513240 1235000 3465 74 _ 1187 5 0 125 95 95 PS 52 3418240 1015000 3513240 1110000 3465 74 1062 5 0 125 95 95 PS 51 3418240 890000 3513240 985000 3465 74 _ 937 5 0 125 95 95 PS 50 3418240 765000 3513240 860000 3465 74 _ 812 5 oj 125 95 95 PS 49
16. 5235000 5360000 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 3513240 2 140000 265000 390000 515000 640000 765000 i 1265000 1390000 1515000 1640000 1765000 1890000 2015000 2140000 2265000 2390000 2515000 2640000 2765000 2890000 3390000 3515000 3640000 3765000 3890000 4015000 4140000 4265000 4390000 4515000 4640000 4765000 4890000 5015000 5140000 5265000 Y2 id 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 3465 74 X Center Y Center HAL25 V2 User Manual v0 1 X Pitch 125 125 125 125 125 125 125 125 250 125 125 125 125
17. A to 1 Set JTAG controller in Run Test Idle state 5 Generate a rising or falling PULSE signal 10 15 02 HAL25 V2 User Manual v0 1 9 HAL25 After the test READ REG register must be cleared This can done by loading it with zero or sending a fast clear FRSTB Boundary Scan Test Mode All the LVDS signals used for the readout of the circuit can be tested and set via BSR One can perform a complete readout with token injection and readout clock activation 10 15 02 HAL25 V2 User Manual v0 1 10 HAL25 Physical Size and Pad Layout Remark This prototype contains an extra test structure with its own pads They are not considered in this document HAL25 chip size 3650 x 10900 square microns It is fabricated on 0 25 um 3 layer metal process The wafers are 8 inch type The final size of the prototype submitted to the MPW4 2001 Q1 run should not exceed 4mm X 11mm after cut The chip should be aligned on its right hand side in the reticule All chip coordinates are referred to its 3 butterflies The circuit is symmetrical to the X axe Front End Pads The 128 analogue inputs are grouped in 2 sections of 64 pads They are numbered from AIN 127 down to AIN lt 0 gt They correspond respectively to the analogue channel 127 placed on the top and to the analogue channel 0 placed at the bottom of the circuit The 2 groups of pads are placed symmetrically to X axe Each pad has a passivation opening size of 120 X 63 um and has a p
18. EE eee eee CREER 11 Power Supply Pads eese eene terne ttr terrre TEE TE nsi ree 12 Readout 2 1 1 7 12 Control Pads PE 13 Test O e e aaia a 13 Logic Levels CC TTE 14 Digital Input eene nnne 14 Digital 14 Analogue Output siasa eee ee eb vie teet 14 APPENDIX T 15 APPENDIX C S E 15 Pad Definition C e theo e Ne evo ee dn rie beetles bar ster 15 Front End Pads Top to 22 0 22 2 465 12222 15 Back End Pad Slots Top to Bottom 6 15 Physical Layout d EIL eese 17 Physical Size A Am M JI 18 Pad Eayout oe EO DEO 19 Pad Coordin tesmm ___ _ 20 10 15 02 HAL25 V2 User Manual v0 1 2 HAL25 Introduction HAL25 is an ASIC dedicated to the read out of silicon strip detectors in the ALICE tracker The chip contains 128 channels The read out of the strips detectors is performed in two steps e Parallel Acquisition Each analo
19. INN Dig Input EE Negative Token Input No internal load PS74 LVDS TK OUTP Dig Output Positive Token Output Powered VDD TK LVDS TK OUTN Dig Output Negative Token Output LVDS FRSTP Dig Input Positive Fast Reset Input No internal LVDS FRSTN Dig Input Negative Fast Reset Input load LVDS PULSEP Dig input Positive Test Pulse Input No internal LVDS PULSEN Dig Input Negative Test Pulse Input load LVDS HOLDP Dig Input Positive Hold Input No internal LVDS HOLDN Dig input Negative Hold Input load LVDS_RCLKP Dig Input Positive Clock Input No internal LVDS_RCLKN Dig input Negative Clock Input load TK IN C Dig input Cmos Token Input active high TK OUT C Dig Output Cmos Token Output Control Pads Dig Input Hysteresis 0 2 5 JTAG Data Input Active high Pull Up Dig Input JTAG Clock Input Active high Dig Output JTAG Data Output Active high Dig Output 8mA JTAG Data Output Active high Dig Input JTAG Control Input Active high Dig Input Hyst PU JTAG Reset Input Active low Dig Input Power on Reset Input Active low Dig Input Hyst PU Chip ID Msb Input Active high Dig Input Chip ID Input Active high Dig Input Chip ID Input Active high Dig Input Chip ID Lsb Input Active high Test Pads PS32 EnableJTAG Dig Input Hyst PU 0 25 V _ Test Purpose Input ManRdRegEN Dig Input Test Purpose Input ManRdRegSHB Dig Input Test Purpose Input IPLS Ana IO re Test Purpose I
20. L25 Physical Size 3850 Estimated dimension The estimated final chip dimension is based 3650 Chip design dimension the measure of the die size of other IBM prototypes results could be different DE gt gt i PX z B gy e amp K E ID D P E EI E TAE E E dli B 282 rj o bg Lz Il E3 Hx e E V imp 2 Butterfly2 3 El a 9 E EY 3550 4500 A E d mm 2 EJ i z EJ H en E E Bl F 5 E A i a E S is EJ m 4 E EB N 003 E E n i E 5 160 E HI 2 EL HH 62 5 H lt 0 do AN py gt Nc Me e 2 160 E Hi 62 3 8 E H lt HI E S e as H amp 8 mel Co i C M iif Butterfly1 3 Blu E 2 F Origine 0 0 2 ME 1 B n 9 E Z E Ej E im 2 E P HI amp sf al y H 8 ES s n e zl 8 20 m a Xx gt E
21. No Pads _ PS 48 3418240 515000 3513240 610000 3465 74 562 5 0 250 95 95 PS 47 3418240 390000 3513240 485000 3465 74 _ 437 5 0 125 95 95 PS 46 3418240 265000 3513240 360000 3465 74 _ 312 5 0 125 95 95 PS 45 3418240 140000 3513240 235000 3465 74 187 5 o 125 95 95 10 15 02 HAL25 V2 User Manual v0 1 22 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Pad Slot 10 15 02 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 3418240 110000 235000 360000 485000 610000 735000 860000 1110000 1235000 1360000 1485000 1610000 1735000 1860000 1985000 2110000 2235000 2360000 2485000 2610000 2735000 2860000 2985000 3360000 3485000 3610000 3735000 3860000 3985000 4110000 4235000 4360000 4485000 4610000 4735000 4860000 4985000 5110000
22. Power Power Empty Power Power Ana IO Ana IO Ana IO Power Ana Output Ana Input Ana Ana Ana Ana Ana Ana Power Power Power Power 8mA 3ST 8mA Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU Hyst PU V 0 2 5 V 42 5 42 5 V GND GND GND GND 42 5 2 5 2 5 GND 0 2 5 V 0 2 5 V 0 2 5 V 0 2 5 V 42 5 GND 0 2 5 V 0 2 5 V 0 2 5 V 0 2 5 V 0 2 5 V 0 2 5 V 42 5 GND GND 2 5 2 5 GND GND 1 uA 2 5 V 2 5 V GND GND HAL25 Data Output JTAG Data Output Analogue Positive Supply Test Block Positive Supply Analogue Gnd Test Block Gnd Analogue Data Output Analogue Data Output Test Block Gnd Analogue Gnd Test Block Positive Supply Analogue Positive Supply Digital Positive Supply Digital Gnd JTAG Control Input JTAG Reset Input Power on Reset Input Test Purpose Input Digital Positive Supply Digital Gnd Test Purpose Input Test Purpose Input Chip ID Msb Input Chip ID Input Chip ID Input Chip ID Lsb Input Digital Positive Supply Digital Gnd Digital Gnd Digital Positive Supply Digital Positive Supply Digital Gnd Test Purpose Input Test Purpose Input Test Purpose Input Gnd for Internal Current Reference Source IREF IREF Probe Internal Current Source test purpose only Test Purpose Test Purpose Test Purpose Test Purpose Test Purpose T
23. ers Bit Bit Name Corresponding Register 7 FSM JTAG FSM register TAG Instruction tege Instruction register 5 POWER ENA TOKEN ENA _ 3 PLSCNTRL 2 EE 1 BIASDAC 0 OUTBUF CTRL UF CTRL POWER register POWER ENA is a single bit scan register It enables the power on mechanism of the analogue multiplexer when it is set to 1 This is the default value after a reset thus the multiplexer of HAL25 is ready for a normal readout Before READ REG settings it must be fixed to 0 TOKEN ENA register TOKEN ENA is a single bit scan register When set to 1 it enables the token signal TK IN used by the analogue mutiplexer to shift through the circuit After reset TOKEN ENA the token is bypassed i e it flows directly to next HAL25 ID REG register ID REG is a read only 8 bit wide register The 4 most significant bits are fixed internally The 4 remaining bits are set via the 4 input pads ID lt 3 0 gt t bit lt 0 gt ID lt 3 gt ID lt 2 gt ID lt 1 gt ID lt 0 gt Li o I 0 gt ID2 m Running HAL25 After power on reset PWRSTB or reset TRSTB e data registers are set to their default value mainly 0 e state machine in Test Logic Reset state e JTAG BYPASS register is selected e Token signal for readout is bypassed Then the bias registers and an operatin
24. est Purpose Analogue Positive Supply Test Block Supply Analogue Gnd Test Block Gnd HAL25 V2 User Manual v0 1 Active high Active high Diodes Prot Diodes Prot Active high Active low Active low Active high Active high Active high Active high Diodes Prot Diodes Prot Diodes Prot To Gnd or an ampere meter Not to be used Diodes Prot Diodes Prot Diodes Prot Diodes Prot Diodes Prot Diodes Prot 16 Physical Layout E CELLS Not Used TEK INN LVD3 OUTP LVD3 DUTN VOD TEOUT VDDD CORE GNDD CORE GNDD PERI PERI LYDS_FESTP PUL amp SEP s PULSEN LVD3 BCLKP Lvn3 TE IN VDDD CORE GNDD CORE GNOD PERI VELD PERI TK UT C TDI TDOOB T VOD GEN GND CND GEN AN GUTN AN_GUTP GND GEN GND 40 VDD GEN YDI YDD PERI GND i TESTE PBS33 PYRESTB Psaz EnablelTA amp G F531 VDDD CORE PS3 GNDD CORE ManEdRegEN PS2B5 1 P527 Peed P525 PS24 PS2Z3 YD PSZ2 GNDD PERI PB21 GNDD CORE Pee VDDD CORE FSi P818 PERI Pay PERI 15 ISHA F514 IBUF PS13 GNDREF PS12 ITEST 511 IREF Psig D3HCONEO Fae PSBB Psa PS G 5 Peed VDD 2583 VRD GEN PS58Z GND 2811 GND GEN Lert Te RERERRERERENE VERE LE EE RESERERRCREECERECEERERUETUUERENERERERCERELS 10 15 02 HAL25_V2 User Manual v0 1 HA
25. g mode have to be loaded Biasing HAL25 BIAS DAC register has to be loaded before operating HAL25 The following table gives the hexadecimal codes for nominal settings to down load in BIAS DAC 10 15 02 HAL25 V2 User Manual v0 1 6 HAL25 Name Code Hexa Hexa Value Dac Resol Dac Range Out Range Range Notes ISHCON 160nA 1nA 0 255 0 255 nA Shaping time 1 4us 2 nA Shaping time 2 215 ISHA 89 55 pA 400 nA 0 255 100 Shaping time 1 4us S uA Shaping time 2 2us VSHA 3C 0 6 V 10mV 0 200 TN 2V Positive input signal 82 13 V 0 200 0 2V Negative input signal IPRE 96 60 uA 400 nA 0 255 0 100 pA VPRE IE 300mV mV 10 mV 0 200 0 2V 4 2V Value against Pile up against Pile up IMUX A uA 400 nA 0 255 100 UA IBUF 6E 44 WA 400 nA 0 255 0 100 HA VBUF IXX Xx 10 mV 0 200 0 2 2V More Used More Used IREF 5 uA Nominal Value 04 15 05 7 5 06 7 5 07 15 96 The internal current reference source is adjustable around its nominal value from 15 up to 15 via REF sub register BIAS_DAC format i l 71 MSB _ 0 LSB ISHCON ISHA VSHA IPRE VPRE IMUX VBUF IREP PULSE DAC has to be loaded only when using the Test Pulse Generator The following table gives the
26. gue channels amplifies shapes within an adjustable time from 1 4 uS to 2 2 uS Then the signals are sampled in a storage capacitor when HOLD goes high e Serial Read out An analogue multiplexer transfers the signal from channel lt 127 gt down to channel 0 to a differential current output buffer at a 10 MHz rate A fast clear FRSTB let to abort the readout at any time Many chips can be daisy chained AIN 127 AIN 0 Analogue Sig SS ul a g LVDS Sig a P PS p 8 9 3 3 3 g 6 F 9 x 9 CMOS Sig g ON OG qm E EE o Rq Only signals for normal use are shown in the block diagram Set up and test of the circuit are performed with programmable registers accessed via an embedded slow control interface The set up consists mainly to Load the DAC which bias the analogue blocks e Authorise HAL25 to be serially read out i e to let the token used by the logic of the analogue multiplexer to flow through the chip Different tests are provided to verify the functionality of the circuit e Pulse Test Mode e Transparent Test Mode e Boundary Scan Test Mode 10 15 02 HAL25_V2 User Manual v0 1 3 Control Interface The control interface of HAL25 complies with the JTAG IEEE 1149 1 standard It allows the access of HAL25 the registers of the chip especially for the setting of the bias and the selection of the running mode On Power on Reset PWRSTB or JTAG Reset TRSTB an internal rese
27. hexadecimal code to set in PULSE_DAC to obtain a 10 MIPS equivalent test pulse Name Code Hexa Value Dac Resol Dac Range Out Range Notes PULSE_DAC 64 50004 suA 0 255 _ 0 1275uaA 10MIPS X Readout Mode This is a description is for the general case where many HAL25 are daisy chained For each chip analogue channels are read from Channel lt 127 gt down to Channel lt 0 gt HOLD RCLK FRSTB AN OUT Puy TK RES TK IN OUT N To perform a normal acquisition follow the protocol specified below l After reset e HOLD PULSE TK IN RCLK FRST must be inactive 2 Initialisation via JTAG has to be done only once Set BIAS DAC register with nominal values Set TOKEN register to 1 e Set JTAG controller in Test Logic Reset state 3 Parallel Acquisition e Upon Trigger set and maintain HOLD active after a shaping time delay of 1 4 uS to 2 2 uS 4 Serial Readout 10 15 02 HAL25 V2 User Manual v0 1 7 HAL25 This can be separated in 3 phases see on the following chronogram 1 Token Injection in the first chip e Sample TK IN pulse on first RCLK The token will shift trough the chips and active them each one after the other e Generate a second RCLK cycle AN OUT remains in High Z 2 HAL25 Chips Readout e Generate 128 RCLK cycles N is the number of the daisy chained HAL25 chips Upon RCLK cycle 1 the AN OUT output of the first chip turns active w
28. ital Gnd PS56 GNDD PERI Power GND Digital Gnd PS55 VDDD PERI Power 2 5 Digital Positive Supply PS54 TK OUT C Dig Output 8 mA 0 2 5 V Cmos Token Output PS53 TDI Dig Input Hysteresis 0 2 5 V JTAG Data Input Active high Pull Up PS52 TCK Dig Input Hyst PU 0 2 5 JTAG Clock Input Active high 10 15 02 HAL25 V2 User Manual v0 1 15 PS51 PS50 PS49 PS48 PS47 PS46 PS45 PS44 PS43 PS42 PS41 PS40 PS39 PS38 PS37 PS36 PS35 PS34 PS33 PS32 PS31 PS30 PS29 PS28 PS27 PS26 PS25 PS24 PS23 PS22 PS21 PS20 PS19 518 PS17 PS16 PS15 PS14 PS13 TDOOB VDD GND AN OUTP GND VDD VDD PERI TMS TRSTB GNDD CORE ID lt 3 gt ID lt 2 gt ID 1 ID lt 0 gt GNDD PERI VDD PERI IPLS ISHA IBUF GNDREF PS12 ITEST PS11 IREF PS10 PS09 508 507 506 505 504 503 502 501 VBUF VSHA IMUX IPRE VPRE VDD GND GND GEN 10 15 02 VDD GEN GND GEN AN OUTN GND GEN VDD GEN GND PERI PWRRSTB EnableJTAG VDDD CORE ManRdRegEN ManRdRegSHB VDDD PERI GNDD CORE VDDD CORE GND PERI ISHCON25 VDD GEN Dig Output Dig Output Empty Power Power Power Power Ana Output Ana Output Power Power Power Power Power Power Empty Dig Input Dig Input Dig Input Dig Input Power Power Dig Input Dig Input Dig Input Dig Input Dig Input Dig Input Power Power
29. itch of 80 um and contains protection diodes to VSS and VDD Pad Name ame Value Funtion 127 AIN lt 127 gt Ana Input Input Diode Protection Protection lige I Diode Protection Protection o JAIN lt 0 gt fAn Ipu AIN lt 0 gt Ana Input Input Diode Protection Protection Back End Pads The 78 pads of the back end side can be logically grouped in 4 groups Power Supplies e Readout e Control e Test Each pad has a passivation opening size of 95 X 95 um They are placed symmetrically to the X axe with a pitch of 125 um In HAL25_V2 VDD_TKOUT and VDD_TKIN pads have replaced pad VDD_TK In order to take in account empty pad positions pad slot numbers has replaced pad numbers There is 85 pad slots 10 15 02 HAL25_V2 User Manual v0 1 11 HAL25 Power Supply Pads The circuit is supplied with 2 5 V Many power pads are used in this chip The reason is the height of HAL25 and the use of separated power for e Analogue Block VDD GND pads e Digital Block VDDD CORE GNDD CORE pads e Test Pulse Generator VDD GEN GND GEN pads e Digital Pads VDDD PERI GNDD PERI pads e Analogue Pads VDD PERI GND PERI e VDD TKIN If connected to VDD the pad LVDS_TK_IN is supplied and selected If not signal TK_IN_C is selected e VDD TKOUT If connected to VDD the pad LVDS_TK_OUT is supplied TK OUT C is always selected The followi
30. ith the value of channel 127 The OUT outputs of the other chips remain in high impedance Upon RCLK cycle 126 OUT appears ready to be sampled by the next HAL25 Upon cycle 128 the value of channel 0 appears Upon RCLK cycle 129 the first chip turns in high impedance and the second turns active with channel lt 127 gt value 3 Last Chip Switch Off e Generate an extra RCLK cycle Last chip AN OUT returns in High Z e Release HOLD Remark Step 2 i e Chips Readout can be aborted at any time cycling RCLK e Send a FRSTB pulse AN_OUT returns in High Z e Release HOLD Token 175 HAL25 N HAL25 Last HAL25 Last HAL25 Injection Readout Readouts Readout Switch Off 2 Ck cycles 128 Ck cycles N x 128 Ck cycles 128 Ck cycles 1 Ck cycle RCLK TK IN AN OUT HOLD Parameter Typical Value HOLD Delay 1 4 uS to 22 uS Delay from Trigger Depends from Shaping Time HOLD Pulse Width Active High Until End of Readout Phase 10 15 02 HAL25 V2 User Manual v0 1 8 Pulse Test Mode Pulse Test mode allows the user to test the analogue channels of the chip by sending a Dirac pulse with the pulse generator via the PULSE signal This emulates the charge generated into the silicon strip detector Positive and negative Dirac pulses are generated respectively on the rising and falling edge of PULSE To perform Pulse Test Mode follows the pr
31. ity Vote Access LL SEU Detect R 1 _ gt imo Only BSR 6 No R W DOTEM values depend from BSR instructions ow EX Pecos vas Sted quens PULSE_DAC 8 Yes R W Previous value shifted out during write _ Af Re EX vale Sted au dae READ_REG 260 No R W Previous value shifted out during write a a Na EMEN E POWER_ENA 1 Yes R W Previous value shifted out during write TO ENA _3 P previous val sited cur dun ID_REG 8 No R Only Bypass Register Bypass register consists of a single bit scan register It is selected after hardware reset when the TAP is in Test Logic Reset state when its code is loaded in the Instruction Register or when the Instruction Register contains an undefined instruction 10 15 02 HAL25_V2 User Manual v0 1 HAL25 Boundary Scan Register The Boundary Scan Register according with the JTAG instructions test and set the following input and output pads Bit Corresponding Pad Signal Notes 5 LVDS RDCLKP N Input RDCLK Readout clock after LVDS conversion 4 LVDS TK INP N _ i nM ee eee in common to LVDS or CMOS inputs TK_IN_C 3 LVDS_PULSEP N Input PULSE Pulse after LVDS conversion 2 LVDS_HOLDP N eu elder ND NN after LVDS conversion 1 LVDS_FRSTP N Input FRSTB Fast Reset after LVDS conversion 0 LVDS TK OUTP N pee Token ou
32. ng table gives the list of the power pads Pads listed on the same line are interconnected by metal line inside the chip PadSlots Name _ J Value 78 Slots Name Value nection Function Sid GND Supplies for the 128 Channels Output Buffer and Bias PS82 PS48 PS39 0504 PS48 539 504 42 5 V 5 V GND bias the silicon substrate of the chip Notel bias the silicon substrate of the chip Note 1 PS71 PS58 VDDD CORE 2 5 V Supplies for the JTAG controller and the digital part of 570 557 PS57 GNDD CORE CORE GND the analogue Mux from Channel 127 64 Note2 analogue Mux from Channel lt 127 64 gt Note2 PS31 PS20 VDDD CORE 2 5 V Supplies for DAC registers and the digital part of the PS30 PS21 PS21 GNDD CORE CORE GND analogue Mux from Channel 63 0 2 Mux from Channel lt 63 0 gt Note2 585 PS45 PS42 PSO1 Supplies of the Test Pulse Generator Note PS83 PS47 PS40 PS03 VDDGEN 25 PS69 PS56 Supplies for digital IO pads i e buffers and protection PS68 555 VDDD PERI 42 5 V diodes from 67to 59 and 54 to 50 Provides also ground to LVDS x pads Note2 PS38 VDD PERI 2 5 V Supplies for analogues pads 44 43 i e protection PS37 GND PERI diodes Note3 PS23 VDDD PERI
33. nput Diodes Prot ISHA Ana IO EE uM Test Purpose Input Diodes Prot IBUF Ana IO pum Amm Test Purpose Input Diodes Prot PS13 GNDREF Power GND Gnd for Internal Current Reference Source IREF ITEST Ana Output uu 1 uA IREF Probe To Gnd or an ampere meter IREF Ana Input Ww NNNM Internal Current Source Not to be test purpose only used ISHCON25 Ana IO Test Purpose Diodes Prot VBUF Ana IO Test Purpose Diodes Prot VSHA Ana IO Test Purpose Diodes Prot IMUX Ana IO Test Purpose Diodes Prot IPRE Ana IO Test Purpose Diodes Prot VPRE Ana IO Test Purpose Diodes Prot 10 15 02 HAL25 V2 User Manual v0 1 13 Logic Levels Digital Input Digital Output Analogue Output 10 15 02 HAL25 V2 User Manual v0 1 HAL25 14 HAL25 APPENDIX Pad Definition Front End Pads Top to Bottom Pad Name Type Value Function 127 AIN lt 127 gt Ana Input Diode Protection Protection 126 AIN lt 126 gt Ana Input Diode Protection Protection Diode Protection Protection lo _ JAIN lt 0 gt Ana Input Diode Protection Protection Back End Pad Slots Top to Bottom Pad i ame Type PS85 GND GEN Power GND Test Block Gnd PS84 GND Power GND Analogue Gnd PS83 VDD GEN Power 42 5 Test Block Supply PS82 VDD Power 2 5 Analogue P
34. ositive Supply PS81 Empty PS80 Empty PS79 Empty PS78 Empty PS77 VDD TKIN Power Hysteresis 2 5 Digital Positive Supply LVDS TK IN Dig Input Pull down pad supply PS76 LVDS TK INP Dig Input LVDS Positive Token Input Powered by VDD TKIN PS75 LVDS TK INN Dig Input LVDS Negative Token Input No internal load PS74 LVDS TK OUTP Dig Output LVDS Positive Token Output Powered by VDD_TKOUT 573 LVDS_TK_OUTN Dig Output LVDS Negative Token Output PS72 VDD TKOUT Power 2 5 Digital Positive Supply LVDS_TK_OU T pad supply PS71 VDDD CORE Power 2 5 Digital Positive Supply PS70 GNDD CORE Power GND Digital Gnd PS69 GNDD PERI Power GND Digital Gnd PS68 VDDD PERI Power 42 5 V Digital Positive Supply PS67 LVDS FRSTP Dig Input LVDS Positive Fast Reset Input No internal PS66 LVDS FRSTN Dig Input LVDS Negative Fast Reset Input _ load PS65 LVDS PULSEP Dig input LVDS Positive Test Pulse Input No internal PS64 LVDS PULSEN Dig Input LVDS Negative Test Pulse Input _ load PS63 LVDS HOLDP Dig Input LVDS Positive Hold Input No internal PS62 LVDS HOLDN Dig input LVDS Negative Hold Input load PS61 LVDS RCLKP Dig Input LVDS Positive Clock Input No internal PS60 LVDS RCLKN Dig input LVDS Negative Clock Input load PS59 TK IN C Dig input Hyst PD 0 2 5 V Cmos Token Input active high PS58 VDDD CORE Power 2 5 Digital Positive Supply PS57 GNDD CORE Power GND Dig
35. otocol below 1 After reset e HOLD PULSE TK IN RCLK FRST must be inactive 2 General settings via JT AG has to be done only once e Set BIAS DAC register with nominal values Set TOKEN ENA register to 1 3 Pulse Generator setting e Set PULSE DAC register with the desired current level e Set PULSE REG with the desired channel selection pattern e Set JTAG controller in Run Test Idle state 4 Parallel Acquisition e Generate a rising or falling PULSE signal e Sample it by setting HOLD active after a shaping time delay of 1 4 US to 2 2 uS 5 Serial Readout e To perform like in Readout Mode step 4 Pulse generator is enabled until JTAG state machine goes in Test Logic Reset state Transparent Mode Transparent mode allows the user to check a single analogue channel among the 128 One can inject a signal and see on an oscilloscope the resulting output signal The signal can be an external source connected to the input or the Pulse Generator configured as specified before To set the chip in Transparent Mode follow the protocol below 1 After reset e HOLD PULSE TK IN RCLK FRST must be inactive 2 General settings via JT AG has to be done only once e Set BIAS DAC register with nominal values 3 Pulse Generator setting e Set PULSE DAC register with the desired current level e Set PULSE REG with the desired channel selection pattern 4 Setchannelin transparent mode e Set POWER to 0 e Set READ REG register e Set POWER EN
36. t is generated The Test Access Port TAP of the controller enters in the Test Logic Reset state and the BYPASS register is selected JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of desired internal data register to access 5 Bit Code Instruction Selected Register Notes 000001 Register Notes EXTEST 00 STAG INTEST 03 BSR JTAG optional instruction CLAMP 04 BYPASS JTAG optional instruction SAMPLE PRELOAD 05 BSR JTAG required instruction BYPASS IF BYPASS qiiid N BIAS DAC 09 BIAS DAC STATUS OB AME SAC T a PULSE DAC 0 PULSE DAC PULSE REG 11 ERE _ READ_REG 15 READ_REG POWER_ENA 19 AG ID REG 1B ID REG TOKEN ENA 11 TOKEN S A JTAG Register Set JTAG registers are implemented with a shift and a shadow register Only some data registers are designed such a way Remember that the JTAG standard imposes that the last significant bit of a register is downloaded first SEU tolerance and detect In order to prevent failures due to a Single Event Upset the most important registers like DAC registers have been designed with majority vote logic A detection logic allows the users to know which register has been hit by a SEU Register Name Major
37. t set to 1 enables the corresponding channel Bits PULSE_REG lt 127 gt down to PULSE_REG lt 0 gt correspond to analogue channel lt 127 gt down to analogue channel O gt READ REG register READ REG register is used to set HAL25 in transparent mode Transparent mode allows the user to check a single analogue channel among the 128 One can inject a signal in its input and see on a oscilloscope the resulting output signal READ REG is 260 bits large It gathers 4 daisy chained sub registers Bit Register Name Register Name Size IER TEMPO 2 257 130 READOUT 128 m RERO 128 1 0 OUTBUF_CTRL 2 10 15 02 HAL25 V2 User Manual v0 1 5 HAL25 To select an analogue channel lt n gt among channel 127 down to channel 0 4 bits in the READ REG have to be set to 1 READOUT n POWERON n e OUTBUF_CTRL lt 1 0 gt Example To set in transparent mode channel lt 8 gt Code is hexadecimal TEMPO READOUT POWERON OUTB 259 2200 257 130 110 3 100000000 00000000 00000000 00000100 00000000 00000000 00000000 00000100 3 STATUS register This 8 bit register stores the state of the SEU flags of the HAL25 registers A bit set to 1 indicates that the corresponding register has been hit by a SEU Registers internal value should not have change because the majority vote logic maintains the right value but it is wise to reload the regist
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