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DLV11 -E and 0 LV11-F asynchronous line interface user's manual

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2. Wh PETI E 4 10 225 ee 4 10 BREAK Generation Logic 4 10 System Reset Timing 4 10 PROGRAMMING EXAMPLES 4 10 PROGRAMMING NOTES 4 18 5 5 1 5 2 5 2 1 5 2 2 5 3 5 3 1 5 3 2 5 3 3 5 4 5 4 1 5 4 2 5 4 3 5 5 5 5 1 5 5 2 5 6 5 7 5 7 1 5 72 5 7 3 5 7 4 5 8 5 8 1 5 8 2 5 8 3 5 8 4 5 9 5 9 1 5 9 2 5 10 5 11 5 12 5 12 1 5192 5 13 APPENDIX A 2 4 4 1 DETAILED TECHNICAL DESCRIPTION GENERAL i a ae T at 5 1 BUS INTEREACE ER Se a 5 1 Address Decoding 5 1 Vector os He 5 1 DUOCONIROLETOGIC 5 2 aput 5 3 Output tege SU Meng 5 6 Vector Operio s Rd 5 7 CONTROL STATUS REGISTERS 5 7 Data x40 A 5 8 Input Operation 3 55 5 11 5 11
3. 2 1 MODULE FUNCTIONS 2 1 CIRCUIT EUNCTIONS KE 2 3 ee E 2 3 2 3 LO Control Logit 2535 5242 2 4 Control Status Registers 2 4 Data ar de Zt UR cae du Ve 2 7 Receiver Active Circuit 2 7 lterr pt Logie X 2 7 Baud Rate Control RIS 2 8 Prak Lone wu 2 8 Maintenance Mode Logic 2 8 DLV11 E Peripheral Interface 2 8 DLV11 F Peripheral Interface 2 9 DC to DC Power Inverter 2 9 INSTALLATION GENERAL 493 xc Rex he 3 1 CONFIGURATION 5 Noe We 3 1 MODULE INSTALLATION 3 1 MODULE CHECKOUT 3 11 DEV 11 E Checkout Yo o 3 15 Checkout A BS BOS 3 15 PROGRAMMING INTRODUCTION ele Ge 4 1 DEVICE REGISTERS soi 4 1 INTERRUPTS e cb EOS Cg SO S 4 9 TIMING CONSIDERATIONS 4 10 Receiver
4. SECONDARY TRANSMITTED DATA lt 14 e SUR RS 4 v REQUEST TO SEND gt d cep FORCE BUSY Be TERMINAL READY 20 4 RECEIVED DATA lt 3 BB EIA TTL M EIA INTERLOCK 11 4931 Figure 5 21 DLV11 E Peripheral Interface Signal Flow 5 27 Other exchanges involving CLEAR SEND and SECONDARY RECEIVED DATA may grammed as required by the equipment SECONDARY RECEIVED DATA and SECONDARY TRANSMITTED DATA are provided for the exchange of secondary or supervisory data with data sets having this capability SECONDARY RECEIVED DATA allows the remote data set to set one bit in the RCSR and to cause a receiver interrupt SECONDARY TRANSMITTED DATA allows the LSI 11 to transmit the state of one bit in the RCSR to the remote data set These exchanges involve only two RCSR bits and are independent of normal data exchanges between the peripheral device and the DLV11 E s data buffer registers EIA level data from the data set arrives at the DLV11 E on the RECEIVED DATA line The periph eral interface converts it to TTL levels and routes it to the RBUF Data to be transmitted from the computer to the data set is serialized in the XBUF and then routed to the peripheral interface The interface circuitry converts it to the EIA levels and transmits it out the TRANSMITTED DATA line to the data set 5 12 DLV11 F PERIPHERAL INTERFACE The DLV11 F supports either
5. Le 125 ns INTERRUPT LATENCY T DAL VECTOR 195ns MIN 320ns MAX R SYNC UNASSERTED 15ns MIN 65ns MAX R BS7 UNASSERTED NOTES 1 Timing shown at Requesting Device Bus Driver Inputs and Bus Receiver Outputs 2 Signal Name Prefixes are defined below T Bus Driver Input R Bus Receiver Output 3 Bus Driver Output and Bus Receiver Input signal names include a B prefix 11 4926 Figure 5 16 Interrupt Timing 5 19 2 LSI 11 responds to L asserting BDIN L and then BIAKI L 3 BIAKI Lis passed down the priority chain until it reaches the section of the interrupt Cae that initiated the request When the circuit receives both BDIN L and BIAKI 1 it asserts VECTOR H and also VECRQSTB H if a transmitter interrupt and negates BIRQ L 4 VECTOR H causes the I O control logic to issue BRPLY L to the computer VECTOR H and VECRQSTB H if applicable also causes the bus interface to place the vector on the LSI 11 bus lines The computer reads in the interrupt vector and then as a result of receiving BRPLY L negates BDIN L Shortly after this it also negates BIAKI L 6 The interrupt logic negates VECTOR and VECRQSTB H if 7 negation of VECTOR causes the I O control logic to negate BRPLY L and the bus interface to remove the vector from the LSI 11 bus lines An interrupt transaction does not require MATCH H BSYNC L BBS7 L or INWD L
6. PERIPHERAL PERIPHERAL ADDRESS AND DATA AND DATA INTERFACE BUFFERS MODE INTERFACE CONTROL FUNCTIONS 11 4959 Figure 2 2 DLVII E DLV11 F Data Flow Simplified Block Diagram 2 3 CIRCUIT FUNCTIONS 2 3 1 General This section discusses the circuits on a functional level and is keyed to Figure 2 3 For a more detailed coverage of circuit operation refer to Chapter 5 2 3 2 Bus Interface The bus interface circuit performs three basic functions 1 It converts signal levels of data moving between the LSI 11 bus and the interface module s internal three state bus 2 It decodes the device address and produces an address match MATCH signal 3 It generates interrupt vectors and places them on the LSI 11 bus The LSI 11 signals are standard TTL levels The module s internal three state bus however has three signal conditions It has TTL high and low states and also a disabled state When a bus interface transceiver output is disabled it goes to a high impedance condition that does not affect other devices connected to the same line This permits the lines to be used in both directions by high speed low power devices The bus interface is normally enabled to receive from the LSI 11 bus It can be switched to transmit onto the LSI 11 bus by either the I O control logic or the interrupt logic The signals received from the LSI 11 bus are ignored unless the address decoding function is enabled 2
7. 40 PIN lt CONN DB 25 BCOSC DATASET BELL 103 BELL 202 11 42961 Figure 3 3 DLV11 E Cabling Example 3 9 CURRENT LOOP MODE 40 PIN 05 DLVII F 40 PIN 40 PIN DLVII F CONN LOK LOK CONN DLVII F RECEIVER 5 5 5 _ RECEIVER PASSIVE PASSIVE TRANSMITTER TRANSMITTER ACTIVE ACTIVE 40 PIN MATE N MATE N 40 PIN CONN LOK LOK CONN DLVII F RECEIVER 5 5 PASSIVE JF DLII C TRANSMITTER PASSIVE EIA DATA LEADS ONLY MODE DB 25 DB 25 mE 5 DLV11 F 2n TERMINAL NULL MODEM CABLE VTO6 MODEL 103 DATASET AUTO MODE 11 4962 Figure 3 4 DLV11 F Cabling Examples 3 10 VIEW FROM MODULE 10 OF BACKPLANE A B C D 5 11 DLVII E 2 5 11 RXV11 3 1 11 4 BLOCK 11 4963 Figure 3 5 Typical Backplane Configuration After the module has been configured properly and the desired location determined install it in the computer as follows CAUTION DC power must be removed from the backplane dur ing module insertion and removal The module and backplane connector block may be damaged if the module is plugged in backwards 1 Position t
8. DLV11 E DLV11 F asynchronous line interface user s manual EK DLV11 OP 001 DLV11 E and DLV11 F asynchronous line interface user s manual digital equipment corporation maynard massachusetts Ist Edition June 1977 Copyright 1977 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice Digital Equipment Corporation assumes no respon sibility for any errors which may appear in this manual Printed in U S A This document was set on DIGITAL s DECset 8000 computerized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DEC DECtape PDP DECCOMM DECUS RSTS DECsystem 10 DIGITAL TYPESET 8 DECSYSTEM 20 MASSBUS 11 UNIBUS 1 1 1 1 2 1 3 1 4 2 24 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 9 2 3 8 2 3 9 2 3 10 2 3 11 2 3 12 2 3 13 3 3 1 3 2 3 3 3 4 3 4 1 3 4 2 4 4 1 4 2 4 3 4 4 4 4 1 4 4 2 4 4 3 4 4 4 4 5 4 6 INTRODUCTION PURPOSE AND SCOPE a urr a bau UE wu xe ee 1 1 OPERATING FEATURES 1 1 MODULE SPECIFICATIONS 1 3 MAINTENANCE uan EP BOR eue Ele 5 1 3 GENERAL DESCRIPTION GENERAD 233 ausit hs ee oe we NCC
9. Figure 2 DC003 Interrupt Section Timing Diagram A 5 INITO L ENB DATA H ENB CLK H ENB ST H BIRQ L RQSTB DATA ENA CLK H ENA ST RQSTA B DIN BIAKI VECTOR VECRQSTB NOTE Times are in nanoseconds 11 4151 Figure 3 DC003 and Interrupt Section Timing Diagram Table 1 DC003 Pin Signal Descriptions 1 VECTOR 2 VEC RQSTB 3 BDINL 4 INITOL 5 BINIT L 6 BIAKOL 7 BIAKIL 8 10 17 REQSTA Description INTERRUPT VECTOR GATING signal This signal should be used to gate the appropriate vector address onto the bus and to form the bus signal called BRPLY L VECTOR REQUEST signal When asserted indicates RQST service vector address is required When unasserted indicates RQST service vector address is required VEC TOR H is the gating signal for the entire vector address VEC RQST B H is normally bit 2 of the vector address BUS DATA IN This signal generated by the processor BDIN always precedes a BIAK signal INITIALIZE OUT signal This is the buffered BINIT L signal used in the device interface for general initialization BUS INITIALIZE signal When asserted this signal brings all driven lines to their unasserted state except INITO L BUS INTERRUPT ACKNOWLEDGE signal OUT This signal is the daisy chained signal that is passed by all devices not requesting interru
10. HOLDING REGISTER DEVICE ADDRESS DECODER ADDRESS JUMPERS 12 DC TO DC POWER INVERTER DATOO 02 H 12 15 VECROSTB JUMPERS BAUD RATE CONTROL TRANSMITTER JUMPERS TO T3 RECEIVER JUMPERS RO R3 TRANSMITTER CHANNEL RECEIVER CHANNEL CONTROL CIRCUITRY INTERRUPT LOGIC BHALT L EIA DATA SET CONTROL DLV11 E ONLY EIA DATA LEADS BOTH DLV11 E AND DLV11 F 20 mA CURRENT LOOP AND READER RUN DLV11 F ONLY Figure 2 3 DLVII E and DLV11 F Functional Block Diagram 11 4960 TO PERIPHERAL EQUIPMENT Not all control and status bits are both read and write some are read only bits and some write only bits A detailed description of each bit is given with the programming information in Chapter 4 2 3 5 Data Buffers The DLV11 E and the DLV11 F each have two data buffers one for receive data RBUF and one for transmit data XBUF Both data buffers handle data by bytes The RBUF also holds error flag bits pertaining to the status of the received data The data received from the peripheral device is transferred serially from the peripheral interface circuit into a receive shift register in the data buffer From there it is transferred in parallel to a holding register At the appropriate time the buffer control circuitry plac
11. 110 BAUD H 11 4927 110 BAUD DECODE Figure 5 17 Baud Rate Control Signal Flow 5 8 2 Jumper Control When the Programmable Baud Rate Enable bit is not set section A of the 5016 chip is controlled by jumpers RO through R3 This section is used to control the receiver baud rate during split speed operation During common speed operation section A and jumpers RO through R3 controls both transmitter and receiver baud rates Jumpers through always determine the output frequency of section B of the chip During split speed operation this establishes the baud rate of the transmitter During common speed operation jumpers TO through T3 and section B of the chip are not used When the module is operating in its maintenance mode and in split speed TO through T3 and section B produce the clock for both the RBUF and the XBUF 5 8 3 External Control External clock inputs can be introduced through either the backplane connector or the header con nector Pins and BL 1 are connected together by a jumper MSPAREB at each module location on the LSI 11 backplane The output of section A is routed through this jumper The jumper can be cut and an external clock applied to backplane pin BL1 This clock will then drive the receiver in split speed operation or both the receiver and the transmitter in common speed operation An external clock can be used for the transmitter in split speed operation by removing jumper 51 and applyi
12. DATA AVAILABLE PARITY ERROR FRAMING ERROR 11 4970 Figure 10 Diagram receiver samples the first STOP bit that occurs either after the PARITY bit or after the data bits if no parity is selected If a valid high STOP bit exists no further action is taken If however the STOP bit is FALSE low indicating an invalid STOP code then the UART control logic provides a framing error indication a high on FR ERR pin 14 Because the serial input from the external device is shifted into the UART a bit at a time SI pin 20 occurrence of a STOP code indicates that the entire data character has been received and shifted into the receiver shift register After the STOP bit has been sampled the receiver control logic parallel transfers the contents of the shift register into the receiver gata holding register and then sets the data available R flag The data available signal also functions as the clock input to the FRAME ERR PARITY and OVERRUN flip flops in the UART status register At this point the DA flip flop is set the OVER RUN flip flop is clear but has a high on the data input because of the output from the DA flip flop and the PARITY and FRAME ERR flip flops are set or cleared signal TRUP or FALSE strobed in from the control logic An OVERRUN condition indicates that another data is being sent to she UART before the previous
13. SET INTERRUPT bit in the RCSR if RING changes state from a 0 to a 1 or if any of the three other signals changes state from either a 0 to a 1 ora 1 to a 0 Thus when the computer program has set DSET INT ENB a signal on any of the incoming EIA control lines can initiate a receiver interrupt When the interrupt is acknowledged the program can check the RCSR to determine which signal initiated it The program can then respond by asserting the appropriate control bits in the RCSR The peripheral interface responds to a True condition on RCSR bits 1 2 or 3 DATA TERMINAL READY REQUEST TO SEND and SECONDARY TRANSMITTED DATA respectively by transmitting a TRUE condition on the corresponding EIA control line If the data set has a FORCE BUSY function jumper FB should be inserted to drive this control line with the REQUEST TO SEND bit The exchange of control signals allows a remote data set to establish a channel of commu nication with the LSI 11 through the use of a handshake A typical handshake sequence proceeds as follows A remote data set calls the local data set The local data set sends a RING signal to the DLV11 E asynchronous line interface The RING signal initiates a receiver interrupt assuming DSET INT ENB is set The program reads the RCSR and determines that the interrupt was caused by the RING signal Then through a service routine it issues the DATA TERMINAL READY and REQUEST TO SEND signals These signals direct the local data s
14. The interrupt logic overrides the module s normal I O protocol When the computer is initialized the interrupt logic is cieared by BINIT L 5 8 BAUD RATE CONTROL The baud rate control circuit establishes the speeds at which the RBUF and XBUF operate The circuit consists of two sets of wire wrap jumpers gating circuitry an oscillator and a 5016 dual baud rate generator The 5016 chip divides the oscillator frequency down to the frequency selected by the jumpers or the program In the split speed mode of operation it produces two separate clock frequen cies one for transmit and one for receive The circuit routes either these clocks or an external clock to the UART to control the baud rate s at which the module operates Also included in the baud rate control are gates that decode a selection of 110 baud When this condition is detected the circuit asserts 110 BAUD H This signal enables the UART to handle a data format having two STOP bits Figure 5 17 5 8 1 Program Control The 5016 chip has two sections each of is driven by 5 0688 MHz clock from the oscillator The two sections of the chip each divide the 5 0688 MHz clock by a selectable amount The selection for section B of the chip is accomplished by jumpers TO through T3 The frequency in section A however be controlled by either jumpers RO through R3 or three state bus lines DAT12 through 15 H The source of control for section A of the chip is selected
15. 3 The bus interface circuit monitors LSI 11 bus lines BDALOO L through BDALIS L It inverts these signals and places them on three state bus lines through DAT15 If the information the BDAL lines is the address of a location in the upper 4K of addressing space i e in the I O page the LSI 11 asserts BBS7 L This signal enables the device address decoding function in the bus interface To decode the address the circuit compares BDALO3 L through BDALI2 L with address jumpers A3 through A12 If the states of the BDAL lines match the corresponding jumpers the user has installed the circuit sends MATCH H the I O control logic MATCH H is a prerequisite for data transactions The bus interface logic generates vector addresses under the control of the interrupt logic and the vector address jumpers The circuit creates two vectors one for receiver interrupts and one for trans mitter interrupts The combination of VECTOR H and VECRQSTB H from the interrupt logic and the states of vector address jumpers V3 through V8 determines what vector will be placed on the LSI 11 bus lines 2 3 3 I O Control Logic The I O control logic directs data transactions between the LSI 11 and the interface module A data transaction can be a word or a byte a high byte or a low byte an input or an output or status information or character information The I O control logic monitors the LSI 11 bus lines to recog nize what type of transaction
16. 5 DLV11 E DLV11 F RBUF Bit Assignments 4 6 DLV11 E and DLV11 F XCSR Bit Assigments 4 7 DLV11 E and DLV11 F XBUF Bit Assignments 4 8 DLV11 F Programming Example 4 15 Serial Data Format EME we wR 4 18 DLV11 E DLV11 F Addresses 5 2 DLV11 E and DLV11 F Interrupt Vectors 5 2 Control Logic Block Diagram 5 4 Data Input 234532329 4k E ee Be 5 5 Data Output LIMINE eS eee GONE 5 6 DLVII E RCSR Data Flow 5 8 DLV11 F RCSR Data Flow 5 9 DLVII Eand DLV11 F Data Flow 5 10 Control Status Registers During DATI 5 11 Control Status Registers During DATO or ITE le 5 13 DLV11 E and DLV11 F RBUF Data Flow 5 14 DLV11 E and DLV11 F XBUF Data 1 5 16 Figure 5 14 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 5 23 5 24 2 25 5 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 Table No FIGURES CONT Title Page Receiver Active US 5 17 Inter
17. 5 7 1 DLVI11 E Receiver Interrupts In the DLV11 E a receiver interrupt sequence is started by either the UART the peripheral inter face circuitry Both cases require that the appropriate enabling bit be set in the RCSR When the computer program sets RECEIVER INTERRUPT ENABLE bit 06 in the RCSR an interrupt can be caused by RDONE H from the UART The UART asserts RDONE H when the RBUF has received and assembled a character of data When the program sets DATA SET INTERRUPT ENABLE bit 05 in the RCSR an interrupt can be initiated by DATA SET INTERRUPT from the peripheral interface circuit The peripheral interface sets DATA SET INTERRUPT when it receives control signals from a data set When either pair of conditions is satisfied the receiver channel will be enabled to request to interrupt the program When the interrupt is acknowledged discussed in Para graph 5 7 4 the interrupt chip asserts VECTOR This signal causes the assertion of the vector address bits that correspond to the vector jumpers which the user has inserted The bus interface circuit places the bits set by jumpers V3 through V8 onto LSI 11 bus lines BDALO3 L through BADLOS L All other BDAL s are negated at this time When the computer locates the service routine it may check the status bits in the RCSR to determine what condition initiated the interrupt Refer to Para graphs 4 3 and 4 6 for notes regarding simultaneous receiver and data set interrupt conditions 5
18. 7 0 This will prevent the processor from recognizing an XCSR or RCSR interrupt request that occurs during instruction execution and then erroneously acknowledging that request after the instruction has cleared it If the computer were to acknowledge the interrupt request after the interrupt enable bit has been cleared it could result in a bus timeout error when the processor attempts to input a vector from the device Programmable Baud Rate The baud rate is programmed by loading the desired bits into the high byte of the XCSR and setting bit 11 An example of a program step that does this is MOVB 130 XCSR 1 300 BAUD BIT11 ENABLE PROGRAMMABLE IDLE STATE OF 1082 RETURN IDLE LINE 8 DATA BITS STATE OF LINE m OR sToP sTOP 4 START BIT O1 02 1 03 1041051061 W CHARACT START lt ONE BIT RATE 11 4968 Figure 4 7 Serial Data Format 4 18 5 DETAILED TECHNICAL DESCRIPTION 5 1 GENERAL This chapter describes on a detailed functional level each of the 12 circuits discussed in Chapter 2 For a description of the major LSI chips refer to Appendix A For circuit schematics refer to DLV11 E Asynchronous Line Interface Circuit Schematics DIGITAL part number D CS M8017 0 1 or to DLVII F Asynchronous Line Interface Circuit Schematics DIGITAL part number D CS M8028 0 1 The functional areas described in this chapter are illust
19. CHARACTER LOOP3 BRANCH IF NO CHARACTER RECEIVED RBUF BUFFER READ RECEIVED CHARACTER INTO BUFFER XRDY XCSR CHECK FOR TRANSMITTER READY LOOP4 BRANCH IF NOT READY BUFFER XBUF CHARACTER REMOTE TERMINAL XRDY CXCSR FOR CONSOLE TRANSMITTER READY 5 BRANCH IF NOT READY BUFFER GCXBUF TRANSMIT CHARACTER CONSOLE LOOP3 BRANCH AND WAIT FOR NEXT CHARACTER 20220260 0002062 0000964 200266 20209 200204 001028 0010920 001002 0212024 001010 001014 2210282 0021022 001032 201032 361032 001036 91042 001046 021052 2010460 082050 201150 000348 001236 000344 009200 000167 090000 002001 090022 0709100 177560 177560 177562 177564 177566 001020 010706 024646 045067 012701 252737 052767 401774 295067 212701 005067 012722 952757 052737 040574 177174 001264 000109 000202 177146 001347 000166 001555 000100 002100 177564 177154 v 177560 177564 PROGRAMMING EXAMPLE THE DLV119F SHOWING THE FLEXIBILITY OF PRUGRAMMING WITH INTERRUPTS FLAGS1 969 WORD eWORD eWORD 45240 0 INVONE 2 INTENBs 100 ULADOSs RCSRs RBUF XCSRs xBuFs 177560 DLADD 64 00 4 DLADD 6 251000 INPUT 540 OUTPUT 340 START 1 INITIALIZE STACK STARTS PRINT INS
20. CLR TO SEND or SEC REC changes state 1 on a 0 1 or 1 10 0 transition of any one of these bits It is also set when RING changes from 0 to 1 Cleared by INIT or by reading the RCSR Because reading the register clears the bit it is in effect a bit When set indicates that a RINGING signal is being received from the dataset Note that the RINGING signal is not a level but an EIA control with the cycle time as shown below 4 sec 4 sec 2 sec 2 sec 2 sec Read only bit The state of this bit is dependent on the state of the CLEAR TO SEND signal from the data set When set this bit indicates an ON condition when clear it indicates an OFF condition Read only bit This bit 15 set when the data carrier is received When clear it indicates either the end of the cur rent transmission activity or an error condition Read only bit When set this bit indicates that the DLV11 E s re ceiver is active The bit is set at the center of the START bit which is the beginning of the input se rial data from the device and is cleared by the lead ing edge of R DONE H Read only bit cleared by INIT or by DONE H bit 07 4 2 Bit 10 06 05 04 3 02 Table 4 2 DLV11 E RCSR Bit Assignments Cont SEC REC Secondary Received or Supervisory Received Data Not Used RCVR DONE Receiver Done RCVR INT ENB Receiver Interrupt Enable DSET INT ENB Data Set Inter
21. EIA data leads Data Leads Only operation or 20 mA current loops It does not perform handshakes or exchange control signals with data sets 5 12 1 Data Leads Only Operation The DLV11 F does not monitor EIA control lines but it does however hold three outgoing EIA control lines in a continuous TRUE condition REQUEST TO SEND FORCE BUSY and DATA TERMINAL READY are held continuously TRUE by separate EIA drivers Figure 5 22 The peripheral interface converts data from TTL levels to EIA levels for transmission on the TRANS MITTED DATA line Data received over the RECEIVED DATA line is converted from EIA levels to TTL levels and routed through an interlock jumper to the RBUF DLV 11 F BCO5C MODEM CABLE Jis y REQUEST TO SEND FORCE BUSY DATA TERMINAL READY 06 gt p TRANSMITTED DATA 23 EIA TTL 11 4932 Figure 5 22 Data Lead Only Interface 5 28 5 12 2 Current Loop Operation The peripheral interface directly interfaces terminal devices that use 20 mA current loops It provides current for receiver and transmitter circuits and also controls the paper tape reader on teleprinters equipped with a Reader Run relay Both the transmitter and receiver circuits use neutral current loops in that current flows in only one direction as opposed to polar current loops in which it flows either way The transmitter can be jumpered for active operation by
22. ENB H is asserted at that time and once asserted are not unasserted until BSYNC L becomes unasserted EXTERNAL RESISTOR CAPACITOR NODE This node is provided to vary the delay between the BDIN L BDOUT L and VECTOR H inputs and BRPLY L output The external resistor should be tied to VCC and the capacitor to ground As an output it is the logical inversion of BRPLY L ENABLE This signal is latched at the asserted edge of L and is used to enable the select outputs and the address term of BRPLY L BUSO 8051 JA1 BUS JA2 BUS3 L JAI L 2 L L DATO H REC H DAT XMIT H JV3 H DAT 3 H JV2 H 2 H 8053 L L BUS2 L BUSO L GND BUSI L 3 1 Y v y Yol DATO JV1 H DAT1 H JV2 H DA2 H JV3 H DAT3 H MATCH H IC DCOOS TRANSMIT DATA BUS XMIT an _ REC H GROUND 5 5 BUS L OUTPUT 5 25ns e 510 2515 DAT H INPUT RECEIVE DATA FROM BUS BUS INITIALLY HIGH XMIT H GROUND REC H 30ns TO 30ns 8 BUS L INPUT RECEIVE DATA FROM BUS BUS INITIALLY LOW DAT H OUTPUT XMIT H GROUND REC H 40 son e 0 TO 30ns sro 30ns BUS L INPUT VECTOR TRANSFER BUS DAT OUTPUT JV
23. H 2015 MAX he 201 BUS L OUTPUT ADDRESS DECODING BUS L INPUT X 10 TO 40ns 5 4015 10 TO 40ns MATCH H MENB L RECEIVE MODE LOGIC DELAY XMIT H REC H gt 40 TO 90ns DAT 3 0 H OUTPUT 11 4892 Figure 8 DC005 Timing Diagram A 17 Pin 12 13 BUS 3 0 L BUSO BUSI BUS2 BUS3 DAT 3 0 H DATO DATI DAT2 DAT3 JV 3 1 H JV JV2 JV3 MATCH H 3 1 L JAIL JA2 L JA3 L XMIT H REC H Table 4 DC005 Pin Signal Descriptions Name Function BUS DATA This set of four lines constitutes the bus side of the transceiver Open collector outputs high impedance inputs LOW 1 PERIPHERAL DEVICE DATA These four tri state lines ry the inverted received data from BUS 3 0 when the trans ceiver is in the receive mode When in transmit data mode the data carried on these lines is passed inverted to BUS 3 0 When in the disabled mode these lines go open hi z HIGH 1 VECTOR JUMPERS These inputs with internal pull down resistors directly drive BUS 3 1 A low or open on the jumper pin will cause an open condition on the corresponding BUS pin if XMIT H is low A high will cause a one low to be trans mitted on the BUS pin Note that BUSO L is not controlled by any jumper input MATCH ENABLE A low on this line will enable the MATCH output A high will force MATCH low overriding the match cir
24. INTERRUPT ENABLE LOGIC MAINTENANCE MODE MAINTENANCE MODE LOGIC BREAK BREAK LOGIC 11 4918 Figure 5 8 DLVII E DLV11 F XCSR Data Flow 5 4 2 Input Operation The contents of the RCSR and XCSR are read into the LSI 11 by an input data transfer DATI The computer places the address of the register on the LSI 11 bus and then the bus interface and I O control logic decode the address The I O control logic generates register select signals that switch data selectors to the desired source Figure 5 9 The select signals also enable the output of the data selectors and if the RCSR is addressed enable bus drivers The status information leaves the CSRs on the three state bus The bus interface circuit then transfers the data to the LSI 11 bus DATA SELECTORS 7415257 TRANSMITTER STATUS BITS THREE STATE BUS RECEIVER STATUS 8097 DRIVERS REGISTER SELECT ENABLE 11 4919 Figure 5 9 Control Status Registers During DATI 5 4 3 Output Operation The LSI 11 writes control bits out to the CSRs by an output data transfer DATO or DATOB Normally the RCSR is loaded by a DATOB cycle because only the low byte contains control bits The bits used in the high byte are all read only status bits The XCSR can be loaded by a DATOB cycle if it is desired to load only the high byte e g to change the baud rate or only a low byte The computer uses a DATO cycle to transfer a full word to the XCSR When the compu
25. LOW BYTE 1 HIGH BYTE 11 4911 DLV11 E and DLV11 F Addresses SELECTED BY USER 4 ASSERTED BY INTERRUPT 9 gt gt gt gt LOGIC CIRCUIT RECEIVER m 1 TRANSMITTER VECTOR JUMPERS INSTALLED O REMOVED 1 LOGIC CIRCUIT RANGE 7748 11 4912 Figure 5 2 DLVII E and DLVII F Interrupt Vectors To place a vector on the bus lines the interrupt logic asserts VECTOR H VECTOR enables those bits whose corresponding vector jumpers have been installed This action does not require BBS7 L or INWD L 5 3 I O CONTROL LOGIC The I O control logic monitors LSI 11 bus control signals decodes the device address from the last three bits of the address word and controls the flow of data in the module The major element in the I O control logic is DC004 protocol chip This chip decodes DATOO H through DATO2 H monitors VECTOR H from the interrupt logic and MATCH H from the bus interface and responds to the following LSI 11 bus control lines BSYNCL BWTBTL BDINL BDOUTL Bussed Synchronize Bussed Write Byte Bussed Data In Bussed Data Out 5 2 CONTROLLED BY INTERRUPT The chip controls four register select lines for enabling the device registers Table 5 1 It also generates OUTHB L and OUTLB L signals to control which byte of a register is loaded The chip produces the word signal INWD to control the direction of data flow through the bus interface trans ceivers It also generates
26. START bit is received SI MARK H changes state and releases the CLEAR line to the counter The counter begins to count receiver clock pulses from the baud rate control circuit Each RCLK H pulse is 1 16th of a bit time The counter counts to eight which places it in the center of the START bit then asserts RBUSY H RBUSY is routed to the RCSR where it can be read in by the program as RECEIVER ACTIVE It is also used to stop the counter and to inhibit SI MARK H from clearing the counter When the RBUF has finished receiving the character the UART asserts RDONE H RDONE H clears the counter thereby negating RBUSY H and returning the circuit to its initial condition Thus RECEIVER ACTIVE is set during the time from the center of the START bit to the leading edge of DONE 5 7 INTERRUPT LOGIC Both transmitter and receiver interrupt functions of the interrupt logic are handled bya single DC003 interrupt chip This chip is described in Appendix The interrupt logic has a receiver interrupt channel a transmitter interrupt channel and control circuitry Figure 5 15 shows the signal flow associated with the interrupt chip R BUSY COUNTER PERIPHERAL SI MARK GATE INTERFACE MAINT SELECTOR RCSR BIT 7 R DONE H DONE _ STATE BUS RON 11 4924 Figure 5 14 Receiver Active Circuit
27. This enables the selected register to place its contents on the three state bus BDIN L is also routed to the protocol chip which asserts INWD L INWD L causes the bus interface transceivers to transfer the data from the module s three state bus to the LSI 11 bus The chip waits about 150 ns for the data to stabilize on the three state bus lines and then asserts INWD L and BRPLY L BRPLY L signals the computer that the data is on the bus The computer reads in the data and then negates BDIN L The I O control logic responds to the negation of BDIN L by negating BRPLY L The computer terminates the bus cycle by negating BSYNC L In the absence of a TRUE condition on BSYNC L the protocol chip releases the register select and INWD L signals The bus interface reverts to its normal condition of receiving from the LSI 11 bus and transmitting onto the three state bus 5 3 BUS INTERFACE DCOOS THREE STATE BUS BDALOO 15 L 15 H 805 5 CEIVERS ADDRESS DECODER 2 BSYNC L PROTOCOL CHIP 06004 1 L 1 0 CONTROL LOSIC 11 4913 Figure 5 3 I O Control Logic Block Diagram DAL 4 R ADDR 4 T DATA 4 AN 125ns MAX umm ns MAX R SYNC 751 150ns MIN 150 13 MIN R DIN po ns MIN 4415 bans zs 75ns MIN 80nsMA 4
28. When the DLV11 F interfaces a 20 mA current loop peripheral device it can be jumpered to operate in either active or passive configuration In the active configuration the peripheral interface supplies the current for the loop in the passive configuration the current is supplied by the peripheral device In either case the receive data line from the peripheral is optically isolated from the DLV11 F s internal data path The 20 mA current loop transmitter operates in either the active or passive configuration The transmit data lines are optically isolated from the DLV11 F s internal data path only in the passive configuration A Reader Run signal is produced for a peripheral device that has a reader run relay When enabled by the program the peripheral interface circuit supplies current to the relay causing the reader to advance the paper tape 2 3 13 DC to DC Power Inverter Both the DLV11 E and DLV11 F need 12 V for the data buffers and the peripheral interface This voltage is produced on the module by a small power inverter The inverter uses the 12 V power available on the LSI 11 backplane to produce a regulated 12 V for the data buffers and peripheral interface circuits 3 INSTALLATION 3 1 GENERAL This chapter describes the jumper configuration the installation requirements and the checkout of the DLV11 E DLV11 F asynchronous line interface modules The wire wrap jumper functions defined and app
29. back to their input Figure 5 20 To accomplish this the computer program sets the MAINTENANCE bit in the XCSR The latch holding this bit has two outputs One goes to the break logic to prevent the gener ation of framing error signals during operation in the maintenance mode The other output is applied to the maintenance mode data selector The data selector normally routes the incoming data from the peripheral interface to the RBUF In the maintenance mode however it switches its input to the output of the XBUF This action loops the serial data out of the XBUF back into the RBUF and disconnects the peripheral interface s received data While in the maintenance mode the serial output of the XBUF continues to go to the peripheral interface and out to the peripheral device 5 25 MAINTENANCE MODE DATA SELECTOR PERIPHERAL SI MARK INTERFACE y SERIAL IN H pouf PERIPHERAL INTERFACE DATO2 H MAINT H XCSR BIT 2 REGISTER SELECT MAINT L BREAK LOGIC Figure 5 20 Maintenance Mode Logic 11 4930 5 11 DLVII E PERIPHERAL INTERFACE The DLV11 E provides data set control by producing and responding to EIA compatible control signals EIA level receivers in the peripheral interface circuit monitor the following control lines RING CLEAR TO SEND CARRIER and SECONDARY RECEIVED DATA Figure 5 21 Each of these control lines is represented by a bit in the RCSR The peripheral interface will set the DATA
30. bit can be set by any of four other bits CAR DET CLR TO SEND SEC REC or RING NOTE When servicing a receiver interrupt from the DLV11 E if a second receiver interrupt condition develops a second interrupt request may not occur To avoid missing this second interrupt condition either all possible receiver interrupt conditions should be checked after servicing the first condition or else both interrupt enable bits bits 05 and 06 should be cleared upon entry to the service routine and then set at the end of service 44 TIMING CONSIDERATIONS 2 When programming the DLV11 E DLVII Asynchronous Line Interface it is important to con sider timing of certain functions in order to use the system in the most efficient manner Timing considerations for the receiver transmitter and break generation logic are discussed in the following paragraphs 4 4 1 Receiver bit 07 in the RCSR sets when the receiver has assembled a full character This occurs at the middle of the first STOP bit Because the receiver is double buffered data remains valid until the next character is received and assembled This permits one full character time for servicing the receiver interrupt 4 42 Transmitter The transmitter is also double buffered The XMIT RDY flag bit 07 in the XCSR i is set in itialization When the XBUF is loaded with the first character from the bus the flag clears but then sets again
31. by a data selector chip This data selector is functionally part of the high byte of the XCSR It is addressed by a combination of the Program mable Baud Rate Enable bit on DAT11 and register select lines from the I O control logic If is asserted during DATO output transaction data selector chip will route the logic states of DAT12 through DAT15 to the dual baud rate Generator chip to program the frequency When is not asserted data selector pem will select j Jumpers trough R3 to control the dual baud rate generator When computer power is first switched on the assertion of BDCOK L causes the data selector to select jumpers RO through R3 as the source of the section A frequency control From that time on the circuit can choose either the jumpers or the XCSR bits as determined by the state of the Programmable Baud Rate Enable bit A table of jumper combinations and their corresponding baud rates is presented in Chapter 3 5 20 Ics J1 9016 BAUD DAT12 THROUGH GENERATOR INPUT H FOUR BIT gt DATA SELECTOR BK1 BL1 SECTION MSPARE B CLOCK A CONTROL RCLK H S1 C1 MULTI PLEXER RECEIVE JUMPERS T UART SECTION TRANSMIT B 5 JUMPERS EXT TCLK H O O TCLK H 1 H EN L MAINT H PB GATING 5 0688 MHz OSC REGISTER SELECT DATA XCSR FORMAT JUMPERS
32. control lines from EIA levels to TTL levels for the interface module The circuit can receive four modem control signals RING CARRIER CLEAR TO SEND and SECONDARY RECEIVED DATA and can transmit four modem control signals DATA TERMI NAL READY REQUEST TO SEND FORCE BUSY and SECONDARY TRANSMITTED DATA The control signals are routed through the control status registers The interrupt logic uses the received control signals to initiate data set interrupts The program uses the transmitted control signals to perform handshakes with the data set Refer to Paragraph 5 11 for an example of a hand shake sequence 2 8 2 3 12 Peripheral Interface DLV11 F peripheral interface operates one of two possible modes 1 EIA Data Leads Only This type of operation supports terminals that use EIA levels but do not require control signal interaction 2 20 Current Loop This operation supports terminals that use either active or passive current loops It also controls the paper tape reader on DIGITAL modified TTY units that have a reader run relay When interfacing EIA level equipment the module performs the TTL to EIA and EIA to TTL level conversion on the transmit and receive data leads only During data leads only operation the module does not monitor incoming control signals Outgoing control signals REQUEST TO SEND FORCE BUSY and DATA TERMINAL READY are held by driver circuits in a continuous TRUE condition
33. have two interrupt channels one for receiver interrupts and one for transmitter interrupts These two channels operate independently If however simultaneous inter rupt requests occur the receiver channel has priority over the transmitter channel In both the DLV11 E and the DLV11 F a transmitter interrupt can occur only if the interrupt enable bit INT ENB in the XCSR 15 set With XMIT INT ENB set setting the transmitter ready XMIT RDY bit initiates an interrupt request When XMIT RDY is set it indicates that the XBUF is empty and ready to accept another character from the bus for transfer to the external device A receiver data interrupt can occur only if the interrupt enable RCVR INT ENB bit in the receiver RCSR is set With RCVR INT ENB set setting the receiver done RCVR DONE bit initiates an interrupt request When RCVR DONE is set it indicates that an entire character has been received and is ready for transfer to bus The receiver data interrupt occurs both the DLV11 E and the DLV11 F DLV11 E also has a data set interrupt The receiver portion of the DLV11 E handles multisource interrupts One of the receiver interrupt circuits is activated by RCVR INT ENB and RCVR DONE The other interrupt circuit can cause an interrupt only if the data set interrupt enable bit DATA SET INT ENB in the RCSR is set With DATA SET INT ENB set setting the DATA SET INT bit initiates an interrupt request The DATA SET INT
34. inserting jumpers 4 and 5A Figure 5 23 or for passive operation by inserting jumpers 3P and 4P In active operation the transmitter provides 20 mA nominal current to loop through the peripheral device The current is switched on and off by data bits from the XBUF In passive operation data bits from the XBUF are optically isolated from the transmission lines Through the isolator the data controls a switching circuit that switches the 20 mA current on and off In passive operation the peripheral device provides the power for the current flow The reader run circuit supplies a negative voltage approximately 12 V and a positive voltage approximately 5 V to energize the peripheral device s reader run relay If the READER ENABLE bit is set in the RCSR the reader run circuit causes the peripheral terminal s paper tape reader to advance When the START bit of the next character is received the Receiver Active circuit asserts RCVR BUSY H RCVR BUSY H clears the reader enable bit thereby switching off the current to the peripheral terminal s reader run relay The reader run bit must be set again by the program before the reader run circuit can drive the relay again The receiver circuit can be jumpered to be either active or passive When configured for active oper ation Figure 5 24 the circuit supplies a ground and a positive voltage to the peripheral device When jumpered for passive operation Figure 5 25 the receiver uses power supp
35. is to be accomplished It uses this information to control four device registers The registers are named after their functions as follows Receiver Control Status Register RCSR Transmitter Control Status Register XCSR Receiver Buffer RBUF Transmitter Buffer XBUF These four registers are described in subsequent paragraphs of this chapter An I O operation begins with the LSI 11 addressing the interface module The bus interface decodes the address asserts MATCH H to the I O control logic and places the address on the three state bus lines The I O control logic decodes the three least significant bits of the three state bus lines DATOO through DATO2 and the LSI 11 bus control signals The circuit develops register selection and byte selection signals to enable the correct data paths between the computer and the appropriate device register It also controls INWD L which determines whether the bus interface transceivers are trans mitting or receiving When data becomes available the I O control logic gates it to its destination from the LSI 11 bus to the three state bus for an output transfer or from the three state bus to the LSI 11 bus for an input transfer 2 3 4 Control Status Registers The DLV11 E and 11 each have two control status registers RCSR and the XCSR The computer writes control bits out of these registers and reads status bits in from them The registers consist of a series of latches d
36. line in conjunction with the ENA CLK H signal determines the state of the internal interrupt enable flip flop The out put of this flip flop is monitored by the ENA ST signal 13 ENB CLK H INTERRUPT ENABLE A CLOCK When asserted on the 14 ENA CLK H positive edge interrupt enable A flip flop assumes the state of the ENA DATA signal line BSYNC BDAL2 BDAL1 BDALO BWTBT BDOUT BDIN BDAL2 L ENB H BDALI L RXCX H BDALO L SELG L BWTBT L SEL4 L BSYNC L SEL2 L BOIN L SELO L BRPLY L OUTHB L BDOUT L OUTLBL GND INWDL VCC D 1 ENB x ew SYNC DAL 2 DECODER _ DAL 1 Aa y LATCH 56 p em MM NIS gt gt 5 2 E 9 9 5 5 6 SEL 4 SEL 21 SELOL OUTHB OUTLB RXCX H BRPLY VECTOR INWD L 01 Figure 4 DC004 Simplified Logic Diagrar A 9 18 Connection RX 1K 5 35022 5 15 pf 5 Pin 18 Connection RX 4 64K 1 220 pf 1 Table 2 DC004 Signal Timing vs Output Loading With Output Output Respect Being Being Signal Signal Asserted Asserted Min Max Min Max ns ns Sel 0 2 4 6 L BSYNCL 30 OUTLBL BDOUTL OUTHB L DBOUT L INWD L BDIN L An an NaN BRPLY L Load A OUTLB L Load B BRP
37. read by the program Refer to Chapter 4 for a listing of how the bits are set and cleared SOURCE RCSR DESTINATION DATA SET INTERRUPT CLEAR i DAT13 H PERIPHERAL TO SEND INTERFACE CIRCUIT CARRIER DETECT RECEIVER y ACTIVE H SECONDARY RECEIVE 1 H ACTIVE RECEIVER RBUF PONE DATO7 H RECEIVER DATO6 H INTERRUPT ENABLE INTERRUPT __ SET LOGIC DATOS H INTERRUPT ENABLE SECONDARY DATOS H TRANSMIT PERIPHERAL DATO2 H O SEND INTERFACE CIRCUIT DATA DATO TERMINAL READY 11 4916 Figure 5 6 DLV11 E RCSR Data Flow SOURCE RCSR DESTINATION RECEIVER ACTIVE RECEIVER CIRCUIT ACTIVE DAT11 H RECEIVER RBUF DONE DATO7 H RECEIVER 6 H INTERRUPT ENABLE INTERRUPT LOGIC READER RUN PERIPHERAL DATOO H INTERFACE CIRCUIT 11 4917 Figure 5 7 DLV11 F RCSR Data Flow XCSR operation is the same for both the DLV11 E and the DLV11 F Figure 5 8 The bits for the baud rate control circuit are write only bits TRANSMITTER READY is a read only bit The other XCSR bits are both read and write bits SOURCE DAT15 DAT14 PROGRAMMABLE BAUD RATE SELECT DAT13 DAT12 H DAT11 6 DATO2 DATOO XCSR DESTINATION PBR SELECT 3 PBR SELECT 2 BAUD RATE SELECT 1 CONTROL PBR SELECT O PROGRAMMABLE BAUD RATE ENABLE TRANSMITTER TRANSMITTER INTERRUPT
38. set permits connection to the chan nel When clear disconnects the interface from the channel Read write bit must be cleared by the program is not cleared by INIT See Note 2 NOTES 1 When clearing an interrupt enable bit first set the processor to its highest prior ity Processor Status Word PSW bit 7 1 After the interrupt enable bit is cleared the processor may be returned to its normal priority PSW bit 7 0 For example MTPS 200 BIC 100 CSR MTPS 0 EXIT For further information refer to Para graph 4 6 2 state of this bit is not defined after power up 4 4 14 13 12 07 06 05 04 03 01 00 RCVR RCVR RDR RESERVED RESERVED DONE RESERVED 10 08 07 06 05 01 00 11 4965 Figure 4 2 DLV11 F RCSR Bit Assignments Not Used RCVR ACT Receiver Active Not Used RCVR DONE Receiver Done RCVR INT ENB Receiver Interrupt Enable Not Used RDR ENB Reader Enable Table 4 5 DLV11 F RCSR Bit Assignments Reserved for future use When set this bit indicates that the DLV11 F in terface receiver is active The bit is set at the center of the START bit which is the beginning of the input serial data from the device and is cleared by the leading edge of RDONE Read only bit cleared by INIT or by RCVR DONE bit 07 Reserved for future use This bit is set when an entire character has been received and is ready for transfer
39. to the LSI 11 bus When set initiates an interrupt sequence provided RCVR INT ENB bit 06 is also set Read only bit cleared whenever the receiver buffer RBUF is addressed or whenever RDR ENB bit 00 is set Also cleared by INIT When set allows an interrupt sequence to start when RCVR DONE bit 07 sets Read write bit cleared by INIT Reserved for future use When set this bit advances the paper tape reader in DIGITAL modified TTY units LT33 C LT35 A C and clears the RCVR DONE bit bit 07 This bit is cleared at the middle of the START bit which is the beginning of the serial input from an external device Also cleared by INIT Write only bit 4 5 14 13 12 11 08 07 00 15 14 13 12 11 10 09 08 00 07 06 05 04 03 02 RECEIVED DATA BITS 11 4966 Figure 4 3 DLV11 E and DLV11 F RBUF Bit Assignments Table 4 4 DLV11 E and DLV11 F Bit Assignments Name ERROR Error Meaning and Operation Used to indicate that an error condition is present This bit 1 the logical OR of OR ERR FR ERR and P ERR bits 14 13 and 12 respectively Whenever one of these bits is set it causes ERROR to set This bit is not connected to the interrupt logic Read only bit cleared by removing the error pro ducing condition NOTE Error indications remain present until the next char acter is received at which time the error bits are updated INIT clear
40. to the idle state and is ready to detect another mark to space transition If however the first sample is a space low then the receiver enters the data entry state If the receiver control logic has not been conditioned to the no parity state a low on pin 35 then the receiver checks the parity of the data bits plus the parity bit following the data bits and compares it with the parity sense on the parity select line pin 39 If the parity sense of the received character differs from the parity of the UART control logic then the receive parity error line P ERR pin 13 goes high and causes the P ERR bit in the RBUF register to set If the receiver control logic has been conditioned to the no parity state a high on pin 35 then the receiver takes no action with respect to parity and maintains the parity error line P ERR pin 13 in the FALSE low state When the control logic senses a parity error it generates a P ERR signal The DATA AVAILABLE signal updates the parity error indicator A 19 STATUS WORD ENB DATA BITS a AND GATES B 55 oe BUF ROB Rot DATA STATUS ENABLE AND GATES RESET REGISTER RDE M mM DATA HOLDING REGISTER SERIAL DATA RECEIVER SHIFT REGISTER INPUT RCV CLOCK CONTROL LOG 1 PARITY PARITY NUMBER OF SELECT BITS CHARACTER SHOWN AS SINGLE BUFFERING
41. 00 CSR MTPS 0 EXIT For further information refer to Paragraph 4 6 15 08 07 00 _ RESERVED TRANSMITTER DATA BUFFER 11 5155 Figure 4 5 DLVII E and DLV11 F XBUF Bit Assignments Table 4 6 DLV11 E and DLV11 F XBUF Bit Assignments 15 08 Not Used Not defined Not necessarily read as Os 07 00 TRANSMITTER Holds the character to be transferred to the exter DATA BUFFER nal device If less than eight bits are used the char _ acter must be loaded so that it is right justified into the least significant bits Write only bits Not necessarily read as Os The unused load only bits always read as 0 s except for the XBUF which unused bits are undefined Loading unused or read only bits has no effect on the bit position The mnemonic INIT refers to the initialization signal issued by the processor Initialization is caused by one of the follow ing issuing a programmed RESET instruction pressing while in ODT the occurrence of a power up or power down condition of the processor power supply In the following descriptions transmitter refers to those registers and bits involved in accepting a parallel character from the LSI 11 for serial transmission to the external device refers to those registers and bits involved with receiving serial information from the external device for parallel transfer to the LSI 11 4 3 INTERRUPTS Both the DLV11 E and the DLV11 F
42. 0240 247105 042 127 402121 082511 052105 005015 215 220131 220121 042514 906522 40 2461206 053440 044510 020123 006454 191 042526 942510 242510 054522 006524 040 080514 051501 020125 027117 722 090001 177566 000100 00400 0425120 047531 047111 044504 052111 040503 042587 51125 046412 040510 944514 046040 212 052111 042585 0515021 046524 047123 012 0842116 054522 042522 420124 055440 012 044104 041115 051440 047524 009215 177564 176722 444440 051125 220105 043516 020114 051122 051040 407116 451101 020104 052124 046501 020123 042503 053440 940440 053517 042440 055440 052444 040515 247105 020105 053440 051125 443440 022 OUTPUTS 15 THIS IS THE ROUTINE IT ALSO IS INTERRUPT DRIVEN THIS ROUTINE IS CALLED WHEN THE TRANSMITTER IS READY R1 IS UUR GLUBAL PUINTER TO THE LINE OF OUTPUT OUTPUT RUNS AT A PRIORITY OF 7 p UUTPUT ANOTHER CHARACTER A NULL JS THE TERMINATION SIGNAL MOVB 7578 BIC BIS RTI 15 OUTVUNE FLAGS TRANSMIT THE CHARACTER NEXT BYTE NULL EXIT AND WAIT R1 098XBUF R1 MORE INTERRUPTS TELL THE MAIN ROUTINE EXIT 551555184555 Hye e ER ER ETE ERE REE SEER d eh ASCII STORAGE AREAS INST LINE e END eASCII eASCIZ eASCII eASCII eA
43. 1176 001202 001204 001212 0011220 001220 0012122 201222 00121226 201232 001234 022767 001374 005267 212701 052767 022767 001374 000000 900741 000015 290012 115704 0827024 020427 001414 026727 193404 005067 004767 110422 005267 000411 004767 105012 042767 052767 002002 112722 1112722 209297 200020 200003 177122 001535 000180 009002 171562 177600 0040015 000952 000034 000040 020102 000001 000015 094012 177110 176450 177062 000110 176546 176764 ALL WE NOW IS WAIT AND KEEP CHECKING BOTH TRANSMITTER AND RECEIVER ARE WORKING FULL SPEED es E CMP SINDUNELOUTDUNE FLAGS ARE THEY BOTH DONE BNE e IF NOT WAIT NOW WE HAVE A LINE IN THE POEM OUT CLR FLAGS CLEAN UP AGAIN MOV NOW WE WILL PRINT LINE BIS INTEND XCSR LET IT INTERRUPT 55 KOUTDONE FLAUS LINE TYPED YET BNE 5 WE MUST PATIENT HALT ALL DONE BR RESTRT TO 00 IT AGAIN END THE MAIN MODULE INPUT THIS IS THE INPUT ROUTINE IT IS INTERRUPT DRIVEN AS EACH IS RECEIVED BY THE DLV119F AN INTERRUPT IS GENERATED R2 IS THE GLUBAL POINTER TO THE NEXT LOCATION FOR STORAGE UF THE INPUT STREAM WHILE IN THIS RUUTINE THE PRIORITY IS 7 WHEN A CARRIAGE RETURN IS SEEN IS STORED AND LI
44. 17 PART OF d RCSR INTERRUPT LOGIC 1 PERIPHERAL DSET DATA SET BIT 15 INTERFACE GENI R DONE RCVR BIT 7 H RCVR INT BIT 6 25 DATOS BIT 5 ENB BDAL 15 L BDAL 14 BDAL 13 L FROM BDAL 12 L COMPUTER 1 5 BUS DATOG BDALIOL VECTOR ADDRESS JUMPERS BDALO9 L BDALO8 L v8 lt a RDY v7 _ 07 6 2 06 L 5 BDALOSL XCSR 4 ALO4 BIAKIL _ o BDALOSL V3 BDALO3 L BIAKO __ __ XMTR _RCVR c CHANNEL CHANNEL BDALO2 L BDALO L BINIT L _______ VECTOR BDALOOL CIRCUITS ___ DATA SET INT DSET INT ENB APPLY TO 1 11 ONLY E 11 4925 Figure 5 15 Interrupt Vector Signal Flow 5 7 DLVII F Receiver Interrupts The DLV11 F interrupt vector flow is the same as that of the DLVI 1 with the exception that it has no DATA SET INTERRUPT or DATA SET INTERRUPT ENABLE bits The module does not support data set control and therefore produces a receiver interrupt only for servicing the RBUF 5 7 3 Transmitter Interrupts The DLV11 E and DLV11 F function alike for transmitter interrupts The interr
45. 4 T RPLY NOTES Timing shown ot Master and Slave Device Bus Driver inputs and Bus Receiver Outputs 2 Signal name prefixes are defined below T Bus Driver Input Bus Receiver Output 3 Bus Driver Output and Bus Receiver Input signal names include a prefix 4 Don t care condition 11 4914 Figure 5 4 Data Input Timing 5 5 5 3 2 Output Operation DLV11 E DLV11 F can accept data from the computer in either bytes or words To write a word out to the interface module the computer performs a DATO bus cycle for a byte a DATOB bus cycle An output data transfer proceeds as follows l R DAL R SYNC R DOUT T RPLY R 857 R WTBT The program places the device address LSI 11 bus lines BDALOO L through BDALI5 L and asserts BBS7 L Figure 5 5 BWTBT L is asserted at this time During address time BWTBT L is negated for an input operation and asserted for an output operation BBS7 L enables the bus interface to decode the address and send MATCH H to the I O control logic The bus interface also applies through DATO2 to the I O control logic The computer asserts BSYNC The leading edge of BSYNC L latches the states of MATCH H and DATOO H through DATO2 H into the protocol chip The chip decodes the register address and asserts the appropriate select line 4 R ADDR R DATA 4 25 ns MIN 150 ns MIN 75ns MIN 140ns MIN 200ns
46. 7777 Table 4 1 lists the addresses of the registers when the module is used to interface a console device The RCSR is at the base address Each subsequent register is two locations up from the one preceding it Table 4 1 Register Addresses for Console Interfacing Register Address Receiver Control Status Register 177560 Receiver Buffer Register 177562 Transmitter Control Status Register 177564 Transmitter Buffer Register 177566 The DLV11 E differs from DLV11 F RCSR therefore the bits for these two RCSRs defined separately The DLV11 E and DLVI1 F operate identically with respect to the three other device registers The bit definition for these registers applies to both modules Figures 4 1 and 4 2 show RCSR bit assignments Figures 4 3 4 4 and 4 5 show the RBUF XCSR and XBUF respectively Tables 4 2 through 4 6 define the bit assignments 4 1 Bit 15 14 11 10 RCVR SEC pes SE ND RCVR RCVR E NOT SEC RESERVED DONE USED DTR y 02 01 00 NOT SED 11 4964 Figure 4 1 DLV11 E RCSR Bit Assignments Table 4 2 DLV11 E RCSR Bit Assignments Name DATA SET INT Data Set Interrupt RING CLR TO SEND Clear to Send CAR DET Carrier Detect RCVR ACT Receiver Active Meaning and Operation This bit initiates an interrupt sequence provided the DATA SET INT ENB bit 05 is also set This bit is set whenever CAR DET
47. DC005 TRANSCEIVER LOGIC A 1 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER A 19 Receiver Operation s eaa a e uw ED 19 4 2 5 APPENDIX 1 2 B 3 B 4 Figure No 2 1 2 2 2 3 3 1 3 2 3 3 3 4 3 5 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 CONTENTS CONT Page Transmitter Operation 21 5016 DUAL BAUD RATE GENERATOR 29 WIRE WRAP INSTRUCTIONS PURPOSE ie Se the Ho toe B de wh wg Be B 1 DEFINITIONS kd OS SER B 1 CONNECTIONS 4 538 SR RUE 2 PROCEDURE Xue uL edo Ro 3 FIGURES Title Page Interfacing Examples e 2 244 44444 Xo 2 2 DLV11 E DLV11 F Data Flow Simplified Block Diagram 2 3 DLV11 E and DLV11 F Functional Block Diagram 2 5 DEV Jumper Locations vox e 3 2 DLV I1 F Jumper Locations 2264464438426 4 46 du 3 3 DLV11 E Cabling Example 3 9 DLV 1 1 F Cabling Examples 3 10 Typical Backplane Configuration 3 11 DLV11 E RCSR Bit Assignments 4 2 DLV11 F Bit Assignments 4
48. E RUN CONTROL ACTIVE LOGIC CIRCUIT 12V 11 4933 Figure 5 23 20 mA Transmitter and Reader Run Circuit 5 30 5 12V 1 2 FOR TTY 2 0 ONLY m SERIAL DATA i 2 RECEIVED DATA H 2 INTERLOCK TTL SERIAL DATA IN 11 4934 Figure 5 24 Active Receive 20 mA Current Loop 5V 1 Ji gt 29 0 005 pF SERIAL DATA IN 2P FOR TTY ONLY ne Se e 20mA TTL RECEIVED DATA T 2 INTERLOCK TTL SERIAL DATA 11 4935 Figure 5 25 Passive Receive 20 mA Current Loop 5 31 DLVIT F PERIPHERAL INTERFACE INTERFACE CABLE pem c PART OF DATA LEADS ONLY CIRCUITRY EIA RECEIVED DATA EIA TTL LEVEL CONVERTER PART OF BCOSC CABLE TTL SERIAL IN pee oe s 9H a 20 LOOP CIRCUITRY 5 CABLE 20 SERIAL DATA PASSIVE RECEIVER 20 MA SERIAL DATA IN Ll 11 4936 Figure 5 26 Interlock Jumper Data Flow 5 32 APPENDIX A IC DESCRIPTIONS DC003 INTERRUPT LOGIC The interrupt chip is an 18 pin DIP device that provides the circuits to perform an interrupt transac tion in
49. Ged O86 4 5 12 Receiver Operation a E 5 13 Ilransmit Operation Ge es 5 15 RECEIVER ACTIVE CIRCUIT 5 16 INTERRUPT LOGIC I ce 5 16 DLV11 E Receiver Interrupts 5 17 DLV11 F Receiver Interrupts 5 18 Transmitter Interrupts Ath et Gi We Be a tn 5 19 Interrupt Transactions 5 19 BAUD RATE CONTROL TITLE 5 20 Control s supa aaa ey SPI es 5 20 Jumper Control s sssaaa sad eiaa E 5 23 ExtemavControl 5 23 LIT 5 23 BREAK LOGIC UR heh 5 23 Receive Operation ES s 5 24 Transmit 575 5 24 MAINTENANCE MODE LOGIC 5 25 DLV11 E PERIPHERAL INTERFACE 5 26 DLV11 F PERIPHERAL INTERFACE 5 28 EIA Data Leads Only Operation 5 28 Current Loop Operation 5 29 DC TO DC POWER INVERTER 5 29 IC DESCRIPTIONS DC003 INTERRUPT LOGIC ta de N Gh ap de Baio 1 DC004 PROTOCOL 1
50. LY L Load A OUTHB L Load B BRPLY L Load A Load B BRPLY L Load A VECTOR H BRPLY L Load A OUTLB L Load B BRPLY L OUTHBL 300 400 10 45 Load A Load B BRPLY L 300 400 10 45 Load A Load B BRPLY L VECTOR H 330 430 0 45 11 Figure 5 Ref ts tg 19 tig tg 10 tip 2 413 4 13 14 t13 4 3 14 13 t14 t13 4 413 13 14 BSYNC L SEL 0 2 4 6 L ais lt 276 BDOUT L 15 ke MIN m Times nanoseconds 11 4348 Figure 5 DC004 Timing Diagram FROM OUTPUT 200 pF LOAD A Figure A 6 Vcc Vcc 2800 2 15 150 pF DIODE 20777 LOAD LOAD 11 4349 DC004 Loading Configuration for Table A 2 Table 3 DC004 Pin Signal Descriptions VECTOR H BDAL2 L L BDALOL BWTBTL BSYNCL Description VECTOR This input causes BRPLY L to be generated through the delay circuit Independent of L and ENB BUS DATA ADDRESS LINES These signals are latched at the assert edge of BSYNC L Lines 2 and 1 are decoded for the select outputs line 0 15 used for byte selection BUS WRITE BYTE While the BDOUT L input is asserted this signal indicates a byte word operation Asserted byte unasserted word Decod
51. NE FEED INSERTED AFTER IT SINCE THIS 15 QUR SIGNAL STOP WE WILL CLEAR INTERRUPT ENABLE ON THE RCSR AND SET INOONE IN FLAGS 15 PCARRIAGE RETURN 12 LINE FEED MOVB BROUF PRY SAVE CHARACTER IN REGISTER 4 BIC 177000 R4 STRIP OFF PARITY JUNK CMP R4 UR IT A CARRIAGE RETURN BEO 105 i IF SO DONE CMP INCUUNT 72 00 WE HAVE 72 CHARACTERS ON THIS LINE BLO 15 NO9 SKIP AROUND CRLF INSERTION CLR INCOUNT RESET COUNTER JSR PC CRLF INSERT CRLF 15 E MOVB CHARACTER INTO LINE INC INCOUNT J COUNT IT BR 115 EXIT THIS CODE WRAPS UP RECEIVING CARRIAGE RETURN 1051 JSR PC CRLF FINISH LINE CLRB 2 APPEND NULL BYTE BIC NO MORE INTERRUPTS 818 INDUNE FLAGS SIGNAL DONE 1151 RTI EXIT CRLF MOVB Re 1 CARRIAGE RETURN MOVB LINE FEED RTS PC RETURN CHARACTERS PER LINE COUNT 11 5175 Figure 4 6 DLV11 F Programming Example Sheet 2 of 3 4 16 021236 201236 201242 2911244 201246 001254 021262 001262 901264 701272 201500 921306 291314 001315 221522 001530 001536 001544 021347 001354 201562 201370 9021376 001401 001406 001414 021422 201450 001436 001441 201446 001454 601462 221470 021476 021501 001506 001514 221522 621550 001535 112137 105711 001006 042737 52767 20020022 054524 020116 246
52. ONTROL SERIAL PARALLEL TO SERIAL OUTPUT PERIPHERAL INTERFACE TRANSMITTER SHIFT REGISTER CLK CONTROL TRANSMITTER ET 0 SERIAL PERIPHERAL INPUT INTERFACE 7 ERR LOGIC STATUS BITS 5 HOLDING REGISTER DATA THREE STATE SELECTOR BUS DRIVERS BUS Figure 5 11 UART Signal Flow 11 4921 5 13 PERIPHERAL DATA FORMAT INTERFACE JUMPERS E teu UT Saa RECEIVED DATA THREE STATE STATUS BITS 2 BUS LINES DATIS OR ERR OVERRUN H FR ERR FRAMING DATI3 H PARITY gt DAT12 H Hid Rex RDONE RECEIVED Tm DATA BITS RECEIVER SECTION H NONE 11 4922 Figure 5 12 DLVII E and DLV11 F RBUF Data Flow 5 14 checks the STOP bit to see if it is marking If the line is spacing when the UART checks for a STOP bit the UART sets the framing error flag FR ERR When the UART receives the center of the first STOP bit it transfers the data in parallel from the receiver shift register to the holding register At this time the data and error bits become available for gating on to the three state bus and the UART asserts the receiver done RDONE H signal This sets the RECEIVER DONE status bit in the RCSR If the receiver interr
53. S DB1 DB8 CONTROL STROBE A 27 Function This line accepts the serial bit input stream A high must be present when data is not being received High is a mark Low is a space A high level pulse on this pin will reset TSO TRMT and EOC to a high level and RDA PER FER and ROR to a low level The transmitter buffer empty flag goes to a high when the data bits holding register may be loaded with another character A low to high transition on this line will enter the data bits into the data bits holding register Data loading is controlled by the rising edge of DS This line goes to a high each time a full character including stop bits is transmitted It remains at this level until the start of transmission of the next character Start of transmission is defined as the mark to space transmission of the start bit It remains at a high when data is not being transmitted This line serially by bit provides the entire transmitted character It remains at a high when no data is being transmitted High is a mark low is a space These are the eight parallel data input lines If 5 6 or 7 bits are transmitted the least most significant bits are used is the least most significant bit pin 26 DB8 is the most significant bit pin 33 A high input will cause a mark high to be transmitted A high on this lead will enter the control bits POE 1 NB2 SB ND into the control bits holding register This line can b
54. SCII eASCIZ INSTRUCTIONS POEM AND INPUT LINE IN YUUR LINE ENDING WITM A CARRIAGE RETURN CR LF CR LF MARY HAD LITTLE LAMB CR LF 113 FLEECE WAS WHITE AS SNOW CR LF ANU EVERY WHERE THAT MARY gt lt gt TRE LAMB WAS SURE GO CR LF 9 STURAGE FOR INPUT LINE STARTS HERE 11 5176 Figure 4 6 DLV11 F Programming Example Sheet 3 of 3 4 17 46 PROGRAMMING NOTES Several programming considerations are presented below Additional information is available from program listings and current software manuals 1 Character Format Figure 4 7 shows the serial character format Note that when less than eight data bits are used the character must be right justified to the least significant bit The character format pertains to both the receiver and the transmitter Maintenance Mode The maintenance mode is selected by setting the MAINT bit bit 02 in the XCSR In this mode the interface disables the normal input to the receiver and replaces it with the output of the transmitter The programmer can then load various bits into the transmitter and read them back from the receiver to verify proper operation of the DLV11 E and DLV11 F logic circuits Clearing Interrupt Enable Bits Before executing an instruction that will clear the XCSR RCSR interrupt enable bits the processor should be set to its highest priority PS bit
55. SMITTER BUFFER 0 sHOLDS CHARACTER RECEIVED DELAY 0 HOLDS DELAY COUNT ORDER 0 sHOLDS DELAY COUNT ORDER sBEGINNING OF ECHO PROGRAM BEGIN CLR RCSR BY INITIALIZING BITS TO ZERO LOOP BIT RING RCSR FOR INCOMING CALL LOOPI IF PHONE IS NOT RINGING BIS DTR RCSR PHONE IS RINGING SO ANSWER WITH DTR MOV 5 DELAY UP COUNT FOR DELAY 4 11 002052 002060 002062 002070 002074 002076 002100 002106 002110 002116 002120 002126 002134 002136 002144 002152 002154 002162 032777 001007 162767 005667 001752 000765 032777 001745 032777 001770 017767 032777 001774 016777 032777 001774 016777 000746 020000 000001 177722 020000 000200 177656 000200 177652 000200 177634 Table 4 7 DLV11 E Programming Example Cont 177720 177730 177672 177662 177666 177650 177642 177636 177630 LOOP2 LOOP3 LOOP4 LOOPS BIT BNE SUB SBC BEQ BR BIT BEQ BIT BEQ MOV BIT BEQ MOV BIT BEQ MOV BR 4 13 ZCTS 2RCSR CHECK FOR CLEAR SEND LOOP3 IF ON 1 DELAY 2 DELAY DELAY DECREMENT TWO WORD INTEGER BEGIN BRANCH IF WE HAVE WAITED TOO LONG LOOP2 AND CONTINUE WAIT FOR CTS CTS RCSR 15 CHANNEL STILL ESTABLISHED BEGIN IF CTS NOT PRESENT RDONE RCSR CHECK FOR RECEIVED
56. TOP and parity bits and the number of data bits is defined in Chapter 3 The UART is driven by a clock signal or two clock signals for split speed operation from the baud rate control circuit The clock speed is 16 times the baud rate of the UART The UART transmitter internally synchronizes the START bit with the clock input to ensure a full 16 element clock periods START bit independent of the time of data loading The receiver rejects any received START bit that lasts less than one half of a bit time 5 12 5 5 1 Receiver Operation Serial data coming in from the peripheral device is converted to TTL levels by the peripheral interface and is applied to the UART s receiver section Figure 5 11 UART samples the serial input data line at 16 times the data bit rate The line is in a continuous marking state when idle When a START bit arrives the UART detects the mark to space transition and begins loading the received character into the receiver shift register The character is shifted to have its least significant bit in the lowest bit position of the register If jumpered for checking parity the UART checks the total of the received data bits plus the parity bit It checks for an even total if even parity has been selected and an odd total if odd parity has been selected A parity error will result in a flag bit P ERR being set Figure 5 12 DATA FORMAT BUS JUMPERS INTERFACE DATA BITS XCSR C
57. TR 15 SP SP INSTRUCTIONS CLR FLAGS MOV SINST R1 BIS INTEND XCSR BIT OUTUUONE PLAGS BEQ 15 INSTEAD WAITING CLR MOV CLR MOV BIS BIS FLAGS 1 INCUUNT 1 R2 INTEND RCSR BINTENB XCSR we te 9 RECEIVER VECTOR PRIORITY 7 TRANSMITTER VECTOR PRIORITY 7 USED AS THE COMMUNICATION LINK BETWEEN THE MAIN MOOULE AND THE INTERRUPT ROUTINES TO IN FLAGS TO BIT 1 TELL MAIN WHICH ROUTINE IS DONE BIT POSITION OF THE INTERRUPT ENABLE BIT IN BOTH THE RCSR AND XCSR GIVE STACK SOME ROOM THIS IS THE MAIN MODULE WHICH CONTROLS THE FLOW OF DATA a SET UP THE STACK POINTER MAKE SURE IT STARTS BELOW US START CLEAN Ri IS OUR OUTPUT BYTE POINTER SET INTERRUPT ENABLE IN XCSK WAIT FOR OUTPUT TO FINISH OUTPUT ROUTINE WILL SET BIT 1 IN FLAGS WHEN DONE ULO BE DOING OTHER PROCESSING HERE RESTART CLEAN FUR THE OUTPUT BYTE POINTER INITIALIZE INPUT COUNTER FUR THE INPUT BYTE POINTER SET INTERRUPT ENABLE IN RCSR AND XCSR 11 5174 Figure 4 6 DLV11 F Programming Example Sheet 1 of 3 4 15 201066 001066 021074 021076 021102 001106 001114 001114 001122 001124 001126 001130 001152 001154 001140 001184 901146 691154 001156 001162 091166 001166 001172 291174 001176 00
58. UT LOGIC 33 088 7 DB7 END OF ENCODER CHARACTER E EOC DATA D89 55 DATA BITS gt BUFFER REGISTER 083 082 26 DB1 LOAD SHIFT mE 22 TRANSMITTER 25 TRANSMITTER BUFFER EMPTY READY TBMT XRDY F F TIMING GENERATOR Figure 11 UART Transmitter Block Diagram DATA STROBE CLOCK INPUT 11 4971 A 21 When the data has been loaded into the UART data buffer it is next transferred to the transmitter shift register under control of signals from an encoder that selects the format determined by the control logic This permits selection of parity or no parity pin 35 the type of parity pin 39 the number of STOP bits pin 36 and the number of data bits per character pins 37 and 38 The end of character pin 24 signal goes high each time a full character including STOP bits is transmitted If this line goes low it prevents the timing generator from loading another character into the shift register The line is normally high when data i is not being and goes low at the start of transmission of the next If the transmitter TEM buffer n loaded while the previous character is being shifted through to the output line the START bit of the new character immediately follows the last STOP bit of the previous character Figure A 12 shows the pin locations and Table A 5 defines the pin functions Figure 12 UART Pin Locations A 22 Ta
59. a computer system that uses a pass the pulse type arbitration scheme The device is used in peripheral interfaces and provides two interrupt channels labeled and with the A section at a higher priority than the B section Bus signals use high impedance input circuits or high drive open collector outputs which allows the device to directly attach to the computer systems bus Maximum current required from the supply is 140 mA Figure 1 is a simplified logic diagram of the DC003 IC Timing for the A interrupt section is shown in Figure A 2 while Figure A 3 shows the timing for both A and B interrupt sections Table A 1 describes the signals and pins of the DC003 by and signal 2 DC004 PROTOCOL LOGIC The protocol chip is a 20 pin DIP device that functions as a register selector providing the signals necessary to control data flow into and out of up to four word registers 8 bytes Bus signals can directly attach to the device because receivers and drivers are provided on the chip An RC delay circuit is provided to slow the response of the peripheral interface to data transfer requests The circuit is designed such that if tight tolerance is not required then only an external 1K 20 percent resistor is necessary External RCs can be added to vary the delay Maximum current required from the supply 15 120 mA Figure A 4 is a simplified logic diagram of the DC004 IC Signal timing with resp
60. a reply BRPLY L to the LSI 11 bus Table 5 1 Register Selection Select Line DAT01H Asserted Register DAT02 H Selected 5 3 1 Input Operation When the LSI 11 program reads data in from the DLV11 E or DLV11 F to the computer DATI bus cycle the input data transfer proceeds as follows 1 The program places the device address LSI 11 bus lines BDALOO L through BDALIS5 L and asserts BBS7 L Figures 5 3 and 5 4 BWTBT L is negated at this time because all input transfers are full words rather than bytes BBS7 L enables the bus interface logic to decode the address The circuit decodes the address and sends MATCH H to the I O control logic It also inverts the address word and places it on three state bus lines DATOO through DATIS DATOO H through DATO2 H are applied to the I O control logic The computer asserts BSYNC L The leading edge of BSYNC L latches the states of MATCH H and DATOO through DATO2 into the protocol chip of the I O control logic The chip decodes DATOO through 2 to recognize the address of the device register and then asserts the appropriate register select line It asserts SEL2 L for example if the program is addressing the RBUF The register select signal conditions a gate that will later be enabled for the data transfer The computer next removes the address from the LSI 11 bus lines negates BBS7 L and asserts BDIN L BDIN L is gated with the register select lines
61. and receives bipolar levels over the data lines to the device This operation does not include control lines When configured for 20 mA current loop operation the DLV11 F can support either active or passive current loop devices Figure 2 1 illustrates several applications of the modules 2 MODULE FUNCTIONS The DLV11 E and DLV11 F asynchronous line interface modules take data from the LSI 11 and convert it to the speed character format and signal levels required by the user s peripheral devices Conversely they assemble inputs from the peripheral devices into the format required for transfer to the computer The computer program can address any of four registers in the interface modules to transfer data or status information It can also enable the interface modules to generate interrupts _ When a peripheral device requires service the interface module will if enabled interrupt the program and vector to the necessary service routine Data passes through three main circuits on its way to and from the peripheral device Figure 2 2 During computer output operations parallel data is taken off the LSI 11 bus by a bus interface circuit and placed on the module s internal three state bus The data on the three state bus enters a data buffer where it is serialized and formatted for the peripheral device From there it goes to a peripheral interface circuit that changes it from TTL to either EIA compatible bipolar levels DLV11 E or DLV11 F or 20
62. ansferred to the receiver holding register Table 5 UART Pin Functions Cont 35 NO PARITY 36 TWO STOP BITS 37 38 NUMBER OF BITS CHARACTER 39 EVEN PARITY SELECT 40 TRANSMITTER A 25 Function A high on this lead will eliminate the parity bit from the transmitted and received character The stop bits will immeidately follow the last data bit on transmission The receiver will not check parity or reception It will when asserted also clamp the PE to a low This lead will select the number of stop bits one or two to be appended immediately after the parity bit A low will insert one stop bit and a high will insert two stop bits These two leads will be internally coded to select either 5 6 7 or 8 data bits character NB2 37 38 _ Bits Character 0 L 0 L 5 0 L 1 6 1 0 L 1 8 The logic level on this pin selects the type of parity that will be appended immediately after the data bits It also determines the parity that will be checked by the receiver A low will insert and check odd parity and a high will insert and check even parity This line is for a clock whose frequency is 16 times 16X the desired transmitter baud rate 20 21 22 23 24 25 26 33 34 Table 5 UART Pin Functions Cont SERIAL INPUT EXTERNAL RESET TRANSMITTER BUFFER EMPTY DATA STROBE END OF CHARACTER SERIAL OUTPUT DATA BIT INPUT
63. ata selectors and gating circuitry During data transactions involving control and status information the I O control logic enables the XCSR or RCSR to either latch in control bits or gate out status bits When status information is to be read into the computer the LSI 11 addresses the device register containing the desired information The bus interface and I O control logic decode the address and enable the contents of the selected register to be placed on the bus and transferred into the computer When control information is to be written out to the interface modules the computer addresses the device register that is to be loaded The bus interface and I O control logic decode the address and enable the register to load the control information when it is placed on the bus 5 6 RECEIVER PERIPHERAL DATA ACTIVE INTERFACE BUFFERS CIRCUIT SERIAL IN MAINTENANCE MODE LOGIC BREAK GENERATION LOGIC 12V BREAK DETECTION REGISTER TRANSMITTER RECEIVER SERIAL SHIFT REGISTER RECEIVER HOLDING SHIFT REG BUS INTERFACE DATOO 15 THREE STATE BUS BDAL 00 151 TRANSCEIVERS CONTROL VECTOR STATUS ADDRESS REGISTERS GENERATOR TRANSMITTER CONTROL STATUS REGISTER JUMPERS V3 V8 DES CONTROL __ toec Lene SIME INR d a BIRA L BIAKO L BINIT L CONTROL CIRCUITRY TRANSMITTER
64. ble 5 UART Pin Functions Voc POWER SUPPLY Veg POWER SUPPLY GROUND RECEIVED DATA ENABLE RECEIVED DATA BITS RD8 RD1 RECEIVE PARITY ERROR FRAMING ERROR OVERRUN STATUS WORD ENABLE RECEIVER CLOCK LINE RESET DATA AVAILABLE RECEIVED DATA AVAILABLE A 23 Function 5 V supply 12 V supply Ground A low on the receiver enable line places the received data onto the output lines These are the eight data output lines These lines may be wire ORed When 5 6 or 7 level code is selected the most significant unused bits are low Characters will be right justified into the least significant bits RD1 pin 12 is the least significant bit RD8 pin 5 is the most significant bit A high indicates a mark This line goes to a high if the received char acter parity does not agree with the selected POE This line goes to a high if the received character has no valid stop bit 1 e the bit following the parity bit is not marking This line goes to a high if the previously received character is not read DA line not reset before the present character is trans ferred to the receiver holding register A low on this line places the status word bit PE DA TBMT FE OR onto the output lines This line is for a clock whose frequency is 16 times 16X the desired receiver baud rate A low on this line will reset the DA line This line goes to high when an entire character has been received and tr
65. can be used as an echo program for DLV11 E interfacing a Bell Model 103 data set When a remote terminal dials in this program answers the call and provides a character by character echo Characters are also copied onto the console device Figure 4 6 depicts a DLV11 F program The program demonstrates the flexibility of programming with interrupts It is performed on a console terminal interfaced by the DLV11 F The program exer cises the module s full duplex capability 4 10 Table 4 7 DLV11 E Programming Example 000200 002000 002002 002004 002006 002010 002012 002014 002016 002020 002022 002026 002034 002036 002044 000200 000167 001616 040000 020000 000200 000002 000200 002000 175610 175612 175614 175616 177564 177566 000000 000000 000000 005077 032777 001774 052777 012767 177752 040000 000002 000005 177744 177734 177744 200 START IMP BEGIN TO BEGINNING PROGRAM SYMBOL DEFINITIONS RING 040000 14 OF RCSR RING CTS 020000 13 OF RCSR CLEAR TO SEND RDONE 000200 BIT 07 OF RCSR RECEIVER DONE DTR 000002 BIT 01 OF RCSR DATA TERMINAL READY XRDY 000200 07 OF XCSR TRANSMITTER READY 2000 175610 OF RECEIVER 175612 BUF OF RECEIVER XCSR 175614 CSR OF TRANSMITTER XBUF 175616 BUF OF TRANSMITTER CXCSR 177564 OF CONSOLE CXBUF 177566 BUF OF CONSOLE TRAN
66. character has been transferred out If the DA flip flop is set indicating a character is stored in the holding register and the control logic attempts to set the DA flip flop again indicating a new character has been shifted into the shift register the DA signal from the control logic provides a clock input to the OVERRUN flip flop This flip flop then sets because the data 15 was set by the previous DA signal 20 If the serial input line goes from a mark high to a space low and remains at the low level the receiver shifts in one character which is all spaces then sets the FR ERR indicator and waits until the input line goes high marking before shifting in another character A 4 2 Transmitter Operation A block diagram of the UART transmitter is shown in Figure A 11 When the UART transmitter is in the idle state the serial output line pin 25 is a mark high When it is desired to transmit data a parallel character is strobed into the UART transmitter data buffer lines connected to pins 26 33 by means of the data strobe signal pin 23 The time between the low to high transition of data strobe and the corresponding mark to space transition of the serial output line i is within one clock cycle 1 16 of a bit time if the transmitter has been idle NO STOP BITS ze EVEN SEL gt CONTROL NO PARITY LOGIC BITS CHAR 372 PAR 25 SERIAL OUTPUT OUTP
67. cuit ADDRESS MATCH When BUS 3 1 match with the state of 3 1 and MENB Lis low this output is open otherwise it is low ADDRESS JUMPERS A strap to ground on these inputs will allow a match to occur with one low the corresponding BUS line an open will allow a match with a zero high a strap to will disconnect the corresponding address bit from the comparison CONTROL INPUTS These lines control the operational of the transceiver as follows REC XMIT 0 0 DISABLE BUS DAT open 0 1 DATA DAT Bus 1 20 RECEIVE BUS DAT 1 1 RECEIVE BUS DAT To avoid tristate overlap conditions an internal circuit delays the change of modes between XMIT DATA mode and delays tristate drivers on the DAT lines from enabling This action 1s independent of the DISABLE mode A 18 A 4 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER The Universal Asynchronous Receiver Transmitter UART is an LSI subsystem that accepts binary characters from either a terminal device or a computer and receives or transmits these characters with appended control and error detecting bits In order to make this subsystem universal the baud rate bits per word parity mode and number of STOP bits are selected by external logic circuits The UART is a full duplex receiver transmitter The receiver section accepts asynchronous serial binary characters and converts them to a parallel format The transmitter section accepts parallel binar
68. d Program Bit Cleared R Jumper Removed Program Bit Set Bit 11 of the XCSR Write Only Bit must be set in order to select a new baud rate under program control Also jumper PB must be inserted to enable baud rate selection under program control Table 3 3 Data Bit Selections Number of Data Bits 3 6 Designation DLV11 E DLV11 F A3 A4 AS A6 7 8 9 10 11 12 Table 3 4 Jumper Configuration When Shipped Jumper State er lt Function Implemented Jumpers through 12 implement device address 17561X for the DLV11 E and 17756 for the DLV11 F The least significant octal digit is hardwired on the module to address the four device registers as follows 0 RCSR X72 RBUF 4 XCSR X 6 XBUF This jumper selection implements interrupt vector address 300 for receiver interrupts and 304 for transmitter interrupts on the DLV11 E On the DLV11 F it selects 60 for receiver interrupts and 64 for transmitter interrupts The module is configured to receive at 110 baud The transmitter is configured for 9600 baud if split speed operation is used Break generation is enabled Parity bit is disabled Parity type is not applicable when P is removed Operation with 8 data bits per character Programmable baud rate function disabled Common speed operati
69. d to enable disable the MATCH output Three vector jumper inputs are used to generate a constant that be passed to the computer bus The three inputs directly drive three of the bus lines overriding the action of the control lines Two control signals are decoded to give three operational states receive data transmit data and disable Maximum current required from the supply is 100 mA Figure 7 is a simplified logic diagram of the DC005 IC Timing for the various functions is shown in Figure A 8 Signal and pin definitions for the 005 are presented in Table A 4 A 2 t V VCC ENADATA H 15 VECTOR H VECRQSTB RQSTA L ENAST NACLK 14 INITO L ENADATA H BINIT L ENACLK H BIAKO L ENBCLK H ENBDATA H BIRQ L ENBST H GND RQSTB H BIAKI L BINIT 1 05 06 BIAKO L z 09 L ENBST H gt 01 vecron 12 N ENBCLK 13 ES d gt 02 VECRaSTB R dd Lo 04 L 0173 Figure A 1 DCO003 Simplified Logic Diagram 5 5 BIRQ BDIN BIAKI VECTOR BIAKO NOTE L 300 300 MIN MIN L L 15 65 5 20 90 1 L 1 1 L 35 MIN 35 MIN Times are in nanoseconds 11 4150
70. d wire on the wire wrap pin Each turn should be adjacent to the next turn one turn should not be wrapped over another turn The end tail may extend tangentially away from the wire wrap pin but should not extend more than one wire diameter If a second level of wire wrap is placed on a wire wrap pin the bare wire of the second level wrap should not overlap the first level wrap The first turn of the insulated wire of the second level wrap however overlap the last turn of the first level wrap Figure 4 The wire used for the jumpers should be good quality wrapping wire DIGITAL uses the following specifications for the jumpers installed at the factory Conductor Gauge 30 AWG solid Material Silver coated copper Diameter 0 0257 0 0008 cm or 0 0003 cm 0 0101 0 0003 in or 0 0001 in B 2 11 4977 Figure 4 Two Levels of Wire Wrap Insulation Material Vinylindene flouride Outside Diameter 0 048 0 003 cm 0 018 0 001 in U L Style 1423 DC Resistance 304 8 m 1000 ft 113 6 ohms NOTE This wire should not be used for solder applications Figures B 1 and B 4 show recommended solderless wrapped connections Figure B 5 illustrates con nections that should be avoided B 4 PROCEDURE To install a wire wrap jumper proceed as follows 1 Cut a piece of 30 AWG wire 5 7 cm 2 1 4 in longer than the distance between the two wire wrap pins 2 Strip 2 7 1 1 16 in off each e
71. e slot closest to the processor module followed by the module interfacing the console terminal Refer to Microcomputer Handbook DIGITAL part number EB 06583 76 for system considerations 9 Teletype is a registered trademark of Teletype Corporation 3 1 FR C1 M1 NO V A GA IN 9A LA 6 01 Lv 11 5172 DLV11 E Jumper Locations Figure 3 1 3 2 11 5173 Figure 3 2 DLVII F Jumper Locations 3 3 12 V3 V8 RO R3 TO T3 BG m 1 2 5 Sl Table 3 1 Jumper Definitions NOTE This table pertains to both the DLV11 E and the DLVII F except as noted Jumpers are inserted to enable the function they control except for those jumpers that indicate negation such as B and Negated jumpers are removed to enable the functions they control Function These jumpers correspond to bits 3 12 of the address word When inserted they will cause the bus interface to check for a True condition on the corresponding address bit Used to generate the vector during an interrupt transaction Each inserted jumper will assert the corresponding vector address bit on the LSI 11 bus Receiver and transmitter baud rate select jumpers during common speed operation Receiver only baud rate s
72. e strobed or hard wired to a high level 5 5016 DUAL BAUD RATE GENERATOR The 5016 is an LSI MOS device containing two independent sections Each section divides its input clock frequency by one of 16 divisors to produce one of 16 different clock outputs The divisors are stored in ROMs on the chip The ROMs are addressed by circuits that latch in and decode the logical states of the address lines Figure A 13 The address lines may be strobed or held at a dc level Table A 6 lists the frequencies selected by the address lines Figure A 14 depicts the 5016 pin locations Table A 7 defines their functions STT Ta C CIRCUITS Tp CLOCK RA Rg Rc Rp 11 4972 Figure A 13 5016 Block Diagram A 29 CLOCK fT 7 Ta Ra RB Tc Rp STT STR GND 11 4973 Figure 14 5016 Pin Locations Table A 6 5016 Selectable Frequencies Transmit Receive Theoretical Actual Address Baud Frequency Frequency D C A Rate 16X Clock kHz 16X Clock kHz EJ LA LE 0 0 50 Q O Oe OK Oe Oe Crystal Frequency 5 0688 MHz A 30 Divisor 6336 4224 2880 2355 2112 1056 528 264 176 158 132 88 66 44 33 16 Mnemonic Name 10 11 12 13 16 17 18 fT Table A 7 5016 Pin Functions External Clock Input Power Supply Reciever Output Fr
73. ect to different loads are tabularized in Table A 2 and are shown in Figure A 5 Figure A 6 shows the loading for the test conditions in Table A 2 Signal and pin definitions for the DC004 are presented in Table 3 DC005 TRANSCEIVER LOGIC The 4 bit transceiver is a 20 pin DIP low power Schottky device for primary use in peripheral device interfaces functioning as a bidirectional buffer between a data bus and peripheral device logic In addition to the isolation function the device also provides a comparison circuit for address selection and a constant generator useful for interrupt vector addresses The bus I O port provides high imped ance inputs and high drive 70 mA open collector outputs to allow direct connection to a computer s data bus structure On the peripheral device side a bidirectional port is also provided with standard TTL inputs and 20 mA tristate drivers Data on this port is the logical inversion of the data on the bus side Three address jumper inputs are used to compare against three bus inputs and to generate the signal MATCH The MATCH output is open collector which allows the output of several transceiver s to be wired anded to form a composite address match signal The address jumpers can also be put into a third logical state that disconnects that jumper from the address match allowing for don t care address bits In addition to the three address jumper inputs a fourth high impedance input line is use
74. ed with B OUT L and latched BDALO L to form OUTLB L and OUTHB L BUS SYNCHRONIZE At the assert edge of this signal address information is trapped in four latches While unas serted disables all outputs except the vector term of BRPLY BUS DATA IN This is a strobing signal to effect a data input transaction Generates BRPLY L through the delay circuit and INWD L Table 3 DC004 Pin Signal Descriptions Cont BRPLY L BDOUT L INWDL OUTHBL OUTLBL Description BUS REPLY This signal is generated through an RC delay by VECTOR H and strobed by BDIN L or BDOUT L and BSYNC L and latched ENB H BUS DATA OUT This is a strobing signal to effect a data output transaction Decoded with BWTBT L and BDALO to form OUTLB L and OUTHB L Generates BRPLY L through the delay circuit IN WORD Used to gate read data from a selected register on to the data bus Enabled by L and strobed by BDIN OUT LOW BYTE OUT HIGH BYTE Used to load write data into the lower higher or both bytes of a selected register Enabled by BSYNC L and decode of BWTBT L and latched BDALO L and strobed by BDOUT L SELECT LINES One of these four signals is true as a function of L and L if ENB is asserted at the assert edge of BSYNC L They indicate that a word register has been selected for a data transaction These signals never become asserted except at the assertion of L then only if
75. elect jumpers during split speed operation see Table 3 2 Transmitter baud rate select jumpers during split speed operation Both receiver and transmitter baud rate if maintenance mode is entered during split speed operation see Tale 3 2 Jumper is inserted to enable Break generation Jumper is inserted for operation with parity Removed for even parity inserted for odd parity Receiver checks for appropriate parity and transmitter inserts appropriate parity These jumpers select the desired number of data bits see Table 3 3 Jumper is inserted to enable the programmable baud rate capability These jumpers are inserted for common speed operation Note that 5 51 must be removed when and are inserted Inserted for split speed operation Note that C and Cl must be re moved when 5 and 51 are inserted This jumper is inserted to assert BHALT L when a framing error is received except when the Maintenance bit is set This places the LSI 11 in the halt mode 3 4 DLV11 E DLV11 F FD DLVI11 E only FR DLV11 E only RS DLVI11 E only FB DLVI11 E only lA 2 and 3A DLV11 F only 2P DLV11 F only 5A DLV11 F only 3P 4P DLV11 F only DLV11 F only MT 11 only Table 3 1 Jumper Definitions Cont Function Jumper B is inserted to negate BDCOK H when a BREAK signal or framing err
76. equency Receiver Address Strobe Receiver Address Power Supply No Connection Ground Strobe Trans mitter Address Transmitter Address Transmitter Output Frequency Inverted External Clock Input Function This input is either one pin of a crystal oscilla tor package or one polarity of another external input 5 V supply This output runs at the frequency selected by the receiver address The logic levels on these inputs select the receiver output frequency fp A high level input strobe loads the receiver address RA Rp into the latch decode circuits This input may be strobed or hard wired to a high level 12 V supply Ground A high level input strobe loads the transmitter address into the latch and decode circuits This input may be strobed or hard wired to a high level The logic levels on these inputs select the transmitter output frequency fy This output runs at the frequency selected by the transmitter address This input is either one pin of a crystal pack age or one polarity of another external input APPENDIX WIRE WRAP INSTRUCTIONS B 1 PURPOSE This appendix is intended to assist the user who installs or removes wire wrap jumpers It describes and illustrates the preferred procedures and standards for producing high grade solderless wrapped jumper wire connections 2 DEFINITIONS The following terms are used in discu
77. er Interrupt Enable Not Used MAINT Meaning and Operation When set these bits choose a baud rate from 50 9600 baud See Table 3 2 Write only bits This bit must be set in order to select a new baud rate indicated by bits 12 to 15 Write only bits Reserved for future use This bit is set when the transmitter buffer XBUF can accept another character When set it initiates an interrupt sequence provided XMIT INT ENB 06 is also set _ Read only bit set by INIT When set allows an interrupt sequence to start when XMIT RDY bit 07 is set Read write bits cleared by INIT See Note Reserved for future use Used for maintenance function When set con nects the transmitter serial output to the receiver serial input while disconnecting the external device from the receiver serial input It also forces the re ceiver to run at transmitter baud rate speed when split speed operation is enabled Read write bit cleared by INIT Table 4 5 DLV11 E and DLV11 F XCSR Assignments Cont 01 Not Used Reserved for future use 00 BREAK When set transmits a continuous space to the ternal device Read write bit cleared by INIT NOTE When clearing an interrupt enable bit first set the processor to its highest priority PSW bit 7 1 After the interrupt enable bit is cleared the proces sor may be returned to its normal priority PSW bit 7 0 For example MTPS 200 BIC 1
78. es the parallel data along with error information onto the module s internal three state bus The bus interface then transfers the data to the computer Data to be transmitted to the peripheral device 15 taken off the three state bus in parallel by the XBUF and then shifted serially out to the peripheral interface circuit Both the RBUF and the XBUF provide double buffering of the data The buffering is double in that the circuits each have both a serial shift register and a parallel holding register This allows one charac ter to be held while another is being moved into or out of the buffer 2 3 6 Receiver Active Circuit The receiver active circuit monitors the serial received data line from the peripheral interface and a receiver done status bit from the RBUF The circuit generates a busy signal RBUSY to indicate that the receiver is active This signal sets the RCVR ACT bit in the RCSR 2 3 7 Interrupt Logic When a peripheral device interfaced by DLV11 E DLV11 F needs service the module can if enabled interrupt the computer program and vector to a service routine The interrupt logic can initiate two types of interrupts a receiver interrupt and a transmitter interrupt These interrupts are handled through separate receiver and transmitter channels For an interrupt transaction to occur first the program sets the interrupt enable bit in the con trol status register Next the interrupt logic recogn
79. et to answer the remote data set by sending it a carrier signal The remote data set acknowledges the carrier signal by returning its own carrier signal The local data set detects the remote data set s carrier signal and indicates this to the DLV11 E by asserting its CARRIER control line This causes another receiver interrupt Upon recognizing the CARRIER caused interrupt the program can either receive or transmit data The only prerequisites for this handshaking sequence are that the program use appro priate service routines and that the data set interrupt enable bit be set in the RCSR 5 26 BIT RCSR DATA SET INTERRUPT CLEAR TO SEND CARRIER DETECT m RECEIVE O 2 6 5 4 5 2 REQUEST TO SEND DATA 1 TERMINAL READY RBUF EIA TTL M MEM Pa yo d MCOSC MODEM CABLE DATA SET 0 4 CIRCUIT BERG CINCH 491 TRANSMITTED DATA 75 SISNATION TTL EIA LEVEL CONVERTER X INDICATOR CLEAR SEND 5 2 4 jj C4 SECONDARY RECEIVED DATA PROTECTIVE GROUND PROTECTIVE GROUND ie SIGNAL GROUND SIGNAL GROUND 1 lt TTL EIA gt
80. he XCSR XMIT RDY initiates a transmitter interrupt request if the transmitter interrupt enable bit is set in the XCSR If the interrupt function is not enabled the UART transmitter remains idle until the program requires it When the program has data to transmit to a peripheral device it uses a DATO or DATOB sequence to address the XBUF and place the data on the bus lines The bus interface moves the data from BDALOO L through BDALO 7 L to through 7 H The I O control logic enables XBUF to load the data into its holding register Figure 5 11 When the data enters the holding register the UART negates XMIT RDY The UART then transfers the data in parallel from the holding register to the transmitter shift register and reasserts XMIT RDY In the transmitter shift register the UART attaches the selected START STOP and Parity bits The assembled character is then shifted serially out of the XBUF to the peripheral interface circuitry Figure 5 13 The time between the leading edge of the register select signal from the I O control logic and the corresponding mark to space transition of the serial output line is within one clock cycle 1 16 of a bit time if the transmitter has been idle XMIT RDY is asserted as soon as a character is transferred from the holding register to the trans mitter shift register thereby indicating that the holding register is empty The next character may be loaded immediately even while the fi
81. he module so that the components side is facing row 1 2 Slide the module into its slot taking care that the module fingers mesh correctly with the backplane connector block 3 Press the module into the connector block making sure that the deep notch on the module seats against the connector block rib 4 Next plug the interface cable into the module s 40 pin header connector When the other end of the interface cable is installed the module can be powered up and checked out Interface cable installations are shown in Figures 3 3 and 3 4 Interface connector pinning is listed in Tables 3 6 and 3 7 Bus connector pinning is listed in Table 3 8 34 MODULE CHECKOUT A diagnostic program is shipped with the module and should be run to verify the proper operation of the module The program runs on an LSI 11 with the most basic options Perform the diagnostic checkout as explained in Paragraph 3 4 1 or 3 4 2 If a malfunction is detected contact the nearest DIGITAL Field Service office 3 11 Table 3 6 40 Pin Header Connector Pinning Header Berg M8017 Module BC05C Modem Cable Pin Signal Names Signal Names A Ground Ground B Ground Ground C Force Busy EIA Force Busy D Sec Clear to Send E Serial Input TTL Interlock In x F Serial Output EIA Transmitted Data H J Serial Input EIA Received Data K L External Clock M EIA Interlock Interlock Out N Serial Clock XMIT P Sec Request to Send R Serial Clock RCVR S C
82. hree ways 1 It can ignore it the apparent error 2 It can place the LSI 11 in the HALT mode 3 It can cause the LSI 11 to re boot Which action the module takes is controlled by wire wrap jumpers To place the computer in the HALT mode the break logic asserts BHALT L To cause the computer to reload a bootstrap the break logic negates BDCOK H Refer to Paragraph 5 9 for further information 2 3 10 Maintenance Mode Logic The DLV11 E and DLV11 F have a maintenance mode for verifying the operation of the modules data paths up to but not including the peripheral interface circuitry This mode is controlled by the computer program but is used only for checking the interface module not the computer In mainte nance mode data from the computer is transferred from the bus interface to the XBUF and serialized as in normal operation But then in addition to going to the peripheral interface circuit a sample of the XBUF s serial output is also routed back to the RBUF s serial input There it is converted to parallel placed on the three state bus to the bus interface and transferred back into the computer The program can then compare the received data with the transmitted data to check for errors 2 3 11 DLV11 E Peripheral Interface The peripheral interface circuitry converts the DLV11 E s data and modem control signals from TTL levels to EIA standard bipolar levels for the peripheral device Likewise it converts the peripheral s data and
83. izes the condition requiring service and asserts the interrupt request line BIRQ L to the computer When the interrupt is acknowledged by the com puter the interrupt logic enables the bus interface to place the vector on the bus lines There are two vectors one for a receiver interrupt and one for a transmitter interrupt The interrupt logic uses VECRQSTB H to indicate which vector is enabled The LSI 11 s interrupt acknowledge signal BIAKI L BIAKO L is daisy chained through the devices on the LSI 11 bus A device s priority is established by its position in the interrupt acknowledge daisy chain The interrupt acknowledge chain goes through both the receiver section and the transmitter section of the module s interrupt logic It goes through the receiver section first thereby giving the receiver channel priority over the transmitter channel A receiver interrupt is initiated when the RBUF has received and assembled a character of data and is ready to transfer it to the computer A transmitter interrupt is initiated when the XBUF s holding register is empty and is ready for another data input from the computer The DLV11 E differs from the DLV11 F in that it recognizes a second condition requiring a receiver interrupt The DLV11 E initiates a receiver interrupt when the data set that it is interfacing signals for handshake The computer program can read the DLV11 E s RCSR to determine whether the receiver interrupt is for a handshake or fo
84. lear to Send Clear to Send U V Request to Send EIA Request to Send W Power X Ring EIA Ring Y T Power Z Data Set Ready AA BB Carrier EIA Carrier External Clock Input TTL DD Data Terminal RDY EIA Data Terminal RDY EE FF Secondary XMIT EIA 202 Sec XMIT HH External Clock ENB TTL JJ Secondary Rec EIA 202 Sec RCVR KK LL EIA Sec XMIT MM Signal Quality NN EIA Sec RCVR PP RR SS Serial Output TTL TT 5V UU Ground Ground VV Ground Ground This jumper is built into the cable lt gt Table 3 7 40 Pin Header Connector Pinning Ground Ground Force Busy EIA Serial Input TTL Serial Output EIA 20 mA Interlock Serial Input EIA Serial Input 20 mA EIA Interlock Serial Input 20 mA Request to Send EIA Serial Output 20 mA Ext Clock Input TTL Data Terminal RDY EIA Reader Run 20 mA Ext Clock Enb TTL Serial Output Reader Run 20 mA Serial Output TTL 5V Ground Ground Ground Ground Force Busy Sec Clear to Send Interlock In Transmitted Data Received Data External Clock Interlock Out Serial Clock X MIT Sec Request to Send Serial Clock RCVR Clear to Send Request to Send Power Ring Power Data Set Ready Carrier Data Terminal RDY 202 Sec XMIT 202 Sec RCVR EIA Sec XMIT Signal Quality EIA Sec RCVR Sig
85. lication examples are presented Wire wrapping instructions are presented in Appendix B 3 0 CONFIGURATION Before installing the module ensure that it is configured for your application The jumper locations are depicted in Figures 3 1 and 3 2 Their functions are defined in Tables 3 1 3 2 and 3 3 Table 3 4 explains the configuration in which the modules are shipped from the factory Table 3 5 lists common applications of the DLV11 E and DLV11 F Figures 3 3 and 3 4 illustrate examples of typical cabling requirements The DLV11 F is shipped from the factory with capacitor C29 installed Figure 3 2 This capacitor is provided for applications using Teletype terminals For applications using DIGITAL terminals re move capacitor C29 33 MODULE INSTALLATION The DLV11 E or DLV11 F module can be installed in any slots in the LSI 11 backplane except the first four slots the LSI 11 processor always occupies the first slots Do not leave any unused option locations between the processor and the DLV11 E or DLV11 F An open slot would break the inter rupt acknowledge daisy chain The priority of the module is determined by its proximity to the proces sor on the bus refer to Figure 3 5 The the slot is to the processor module the higher the interface module s priority Determine the appropriate slot for the module For example if DLV11 E is interfacing commu nications lines from a host computer it would normally be placed in th
86. lied by the peripheral device In either case current passes through an optical isolator The isolator produces a TTL output that is electrically isolated from the current loop The TTL output is routed to the RBUF The RBUF accepts TTL inputs from either the EIA interface circuit or the 20 mA circuit The routing is determined by the cable attached to the 40 pin header connector Figure 5 26 An EIA modem cable will jumper the output of the 20 mA receiver to the input of the RBUF 5 13 DC TO DC POWER INVERTER The power inverter operates on 12 V from the LSI 11 power supply and produces 12 V for the the drivers and on the DLV11 F the reader run circuit The power inverter circuit consists of an oscillator driving a charge pump The output of the oscillator is capacitively coupled to a rectifier which develops a negative going output This output pumps up an inductive charge storage network and is Zener regulated back to 12 V 5 29 DLV11 F CABLE 5V 12 1 SERIAL L TRANSMITTER OUT d a 3P NY SWITCHING PA CIRCUIT TRANSMIT DATA PASSIVE TRANSMITTER ACTIVE UN TRANSMITTER 4 SERIAL 5A 5V RCSR REGISTER SELECT LN READER READER RUN gt RUN RELAY DRIVER RCVR BUSY H io RECEIVER E
87. lock 2 2256 29 5016 Pin Locations Ee 30 Solderless Wrapped Connection on Wire Wrap Pin B 1 Nic cay sete odode ie Gh va ee B 2 ee ee ee Ede uem B 2 Two Levels of Wire Wrap B 3 Defective Wire Wraps 2 vedo Bees 4 Loading the Wire Wrapping B 6 TABLES Title Page Feature Comparison cs 1 2 Jumper Definitions E RO 3 4 Baud elections 3 6 Table 3 3 3 4 3 5 3 6 3 7 3 8 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 5 2 5 3 1 2 3 4 5 6 7 TABLES CONT Title Page Data Bit Selections pri ce di d Re A Se 3 6 Jumper Configuration When Shipped 3 7 Module Application Examples 3 9 DLV11 E 40 Pin Header Connector Pinning 3 12 DLV11 F 40 Pin Header Connector Pinning 3 13 DLV11 E and DLV11 F Edge Connector Pinning 3 14 Register Addresses for Console Interfacing 4 1 DLV11 E Bit Assignments 4 2 DLV11 F Bit Assignments 4 5 DLV11 E DLVII F RBUF Bit Assig
88. loop equipment EIA standard data leads only no modem control operation Flexibility is achieved by the use of wire wrap jumpers Table 1 1 compares the features of the DLV11 E and DLV11 F with those of the DLV11 and the DL 11 series Refer to Paragraph 4 4 Timing Considerations for further information 1 1 Table 1 1 Feature Comparison NOTE X indicates feature available Features through D 0111 DLV11 DLV11 F DLVII E Programmable Baud Rates Write Only Bits Modem Control EIA Data Leads Only 20 mA Current Loop Jumper Selectable Active or Passive 20 mA Current Loop Error Flags BREAK Generation Bit Receiver Active Bit X o X Maintenance Bit On board Clocks for Split Speed Operation Halt on Framing Error Boot on Framing Error Cleared by INIT UART Cleared by DCOK No Trap on Write to RBUF 1 5STOP BITS Modem Status Bit 13 MODULE SPECIFICATIONS The following specifications and particulars are for informational purposes only and are subject to change without notice Physical Characteristics Dimensions Circuit Card Circuit Card Plus Handles Length 21 6 cm 8 5 in 22 8 cm 8 9 in Height 12 7 5 0 in 13 2 5 2 in Width 1 3 0 5 in 1 3 0 5 in Cable Connection One 40 pin header connector Mounting Requirements Plugs directly into any dual height slots on the LSI 11 backplane or LSI 11 expansio
89. mA current loop signals DLV11 F only The data then leaves the module an interface cable and goes to the user s peripheral device Data coming into the computer from the peripheral device goes through this process in reverse order The control functions within the interface module are carried out by circuits that handle I O transfers interrupt requests and control and status information The DLV11 E interfaces control signals as well as data between the LSI 11 and the peripheral The extent of this interaction is determined by the program and the type of peripheral being supported The DLV11 E and DLV11 F also have a self test function When the computer program places module in the maintenance mode parallel data travels through the bus interface and the data buffer is serialized and then loops back through the data buffer is converted back to parallel and travels through the bus interface to the computer to be checked for accuracy 2 1 TELEPHONE LINES DATASET INTERFACING A REMOTE 51 11 TERMINAL 20mA EIA CCITT INTERFACING A LOCAL TERMINAL Figure 2 1 TELEPHONE LINES EIA CCITT INTERFACING A REMOTE TERMINAL PRIVATE LINES TERMINAL EIA CCITT REMOTE COMMUNICATIONS via PRIVATE LINES TELEPHONE LINES DATASET INTERFACING A REMOTE 11 11 4958 Interfacing Examples ASYNCHRONOUS LINE INTERFACE TTL THREE STATE PARALLEL PARALLEL ae LINES LINES LINES
90. mper and install a new one lower on the pin A wire wrap joint that is installed too high on the pin should not be forced to a lower level it should be unwrapped and replaced with a new one at the lower level STATIONARY SLEEVE SLOT ROTATING SPINDLE BIT STRIPPED WIRE WIRE ANCHORING NOTCH TOOL TIP WIRE INSERTED WIRE ANCHORED WRAP POST INSERTION TYPICAL CONNECTION 11 5038 Figure B 6 Loading the Wire Wrapping Kit B 6 DLV11 E AND DLV11 F ASYNCHRONOUS LINE INTERFACE USER S MANUAL EK DLV11 OP 001 Reader s Comments Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications What is your general reaction to this manual In your judgment is it complete accurate well organized well written etc Is it easy to use What features are most useful What faults do you find with the manual Does this manual satisfy the need you think it was intended to satisfy Does it satisfy your needs _W Why Would you please indicate any factual errors you have found Please describe your position Oraa O Street ee cu aaa Depattitient C c D OCON FIRST CLASS PERMIT NO 33 MAYNARD MASS BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES Postage will be paid by Digital Equipment Corporation Technical Documentation Department Maynard Massachusetts 01754
91. n box backplane Electrical Characteristics Module Type DLV11 E M8017 DLV11 F M8028 Power Requirements 1 0 A nominal 5 5 5 0 W 150 mA nominal 12 5 1 8 W LSI 11 Bus Loading Presents one bus load Environmental Characteristics Temperature Operating 59 to 50 C 41 F to 122 F Nonoperating 40 C to 66 40 to 151 Humidity Operating and Nonoperating 10 to 95 maximum wet bulb 32 C 90 F and minimum dew point 2 C 35 F Altitude Operating 2 4 km 8 000 ft Nonoperating 9 1 km 30 000 ft 1 4 MAINTENANCE This manual explains the normal operation of the asynchronous line interface modules This informa tion and the diagnostic maintenance programs will aid the user when analyzing trouble symptoms to determine necessary corrective action A set of engineering drawings is available for each of the two modules Refer to DLV11 E Asynchronous Line Interface Circuit Schematics DIGITAL part num ber D CS M8017 0 1 or DLV11 F Asynchronous Line Interface Circuit Schematics DIGITAL part number D CS M8028 0 1 1 3 Signal names DLV11 E DLV11 F print sets are in the following basic form SOURCE SIGNAL NAME POLARITY SOURCE indicates the drawing number of the print set where the signal originates The drawing number of a print K 3 K 4 K 5 etc is located above the title block SIGNAL NAME is the proper name of the signal The names used in the pri
92. nal Rate Ground Ground 3 13 M8028 Module 05 Modem Cable Signal Names Signal Names 05 20 mA Cable Ground Interlock In lt Interlock Out Received Data Received Data Transmitted Data Reader Run Reader Run Ground Ground Table 3 8 DLV11 E and DLV11 F Edge Connector Pinning _ Mnemonic 5 2 2 12 AD2 BBS7 L AP2 BDALOL AU2 AV2 BDAL2L 2 BDAL3L BF2 BDAL4L BH2 BDALSL BJ2 BDAL6L 2 71 TE BL2 BDALSL gt BM2 BDAL9L BN2 BDAL 101 BP2 11 L BR2 121 TX E BS2 BDAL 13L BT2 BDAL 14L T BU2 BDAL 151 3 2 BDIN L AH2 BDOUT L L BIAK IL AM2 BIAK 0 L AN2 BINIT L AT2 BDMGIL AR2 BDMGOL AS2 BIRQL AL2 BRPLYL x Pe a AF2 BSYNCL AJ2 BDCOKH srt BAI GND AC2 GND ATI GND 2 GND 12 V AK1 Ec EXT R CLK REE BLI SSPARE4 _ SSPARE 5 SSPARE 6 SSPARE 7 SSPARE 8 EXT T CLK These signals are not bussed they daisy chained This jumper is wired on the backplane 3 14 3 4 1 DLV11 E Checkout To verify the operation of the DLV11 E turn off the dc power and remove the interface cable from the data set Leave the other end connected to the module s heade
93. nd of the wire B 3 END TAIL TOO LONG INSUFFICIENT TURNS PILE WRAP INSUFFICIENT INSULATION IMPROPER SPACING AND OVERLAP OVER TAPER END BENT WRAP POST OPEN WRAP SPIRAL WRAP 11 5037 Figure B 5 Defective Wire Wraps 23 Insert wire into the wire wrap bit far enough for the insulation to enter the feed slot Figure B 6 4 Loop the wire through the anchoring notch 5 Place the tool on the wire wrap pin and actuate the rotating spindle bit This should produce eight turns of bare wire and one half to two turns of insulated wire on the wire wrap pin 6 Load the free end of the wire into the wire wrap bit and wrap the other wire wrap pin Use an unwrapping tool to remove a wire wrap jumper A jumper may be snipped out to break the electrical connection but when it is desired to reuse the wire wrap pin the remaining wire should be removed carefully Pulling the wire off may bend the pin and dent the pin corners Therefore it 15 recommended than an unwrapping tool be used to remove jumper wire wraps Place the tool over the wire wrap pin and insert the end tail of the wrap into the unwrapping tool bit Carefully unwrap the wire and discard it Jumper wires should not be reused If it is desired to place a second level wrap on a wire wrap pin care should be taken not to overlap the first wrap If there is insufficient space left on the wire wrap pin for a second level wrap remove the first level ju
94. ng the external clock to backplane pin BH1 External clock frequencies must be 16 times the desired baud rate The baud rate can be controlled by an external peripheral device via the cable to the module s header connector When a TTL logic low enabling signal is applitd to J1 pin HH it causes the clock control multiplexer to select the external clock on pin CC When the enabling signal is negated the baud rate reverts to its former configuration 5 8 4 Clock Selection The receiver and transmitter clock inputs to the RBUF and XBUF timing circuitry in the UART are selected by two jumpers and a multiplexer Normally the multiplexer selects the input from pin as the receiver clock The CONN CLK EN L signal however causes the multiplexer to select header connector pin CC as the receiver clock Additionally during the maintenance mode only MAINT H causes the multiplexer to choose the transmitter clock as the source of the receiver clock in split speed operation and the receiver clock as the source of the transmitter clock in common speed operation when jumper MT is installed During split speed operation jumpers 5 and 51 inserted and jumpers and removed This routes the receiver clock to the RBUF section of the UART and the transmitter clock to the XBUF section For common speed operation jumpers 5 and 51 are removed and jumpers and are inserted This routes the receiver clock to both the RBUF and XBUF section
95. nments 4 6 DLV11 E and DLV11 F Bit Assignments 4 7 DLV11 E and DLV11 F XBUF Bit Assignments 4 8 DLV11 E Programming Example 4 11 Register Selecon w ea WC eire uta 5 3 Byte Selection Output Operations Only 5 7 WARE Clock SOURCES s we oe we eS 5 24 DC003 Pin Signal Descriptions A 7 0 004 Signal Timing vs Output Loading 11 0 004 Pin Signal Descriptions 14 0 005 Pin Signal Descriptions 18 UART Pi Functions osma GA AC A 23 5016 Selectable Frequencies A 30 SOG PurLbunctlOHWS axo 31 1 INTRODUCTION 1 1 PURPOSE AND SCOPE The DLV11 E and DLV11 F are asynchronous line interface modules that interface the LSI 11 bus to any of several standard types of serial communications lines The modules receive serial data from peripheral devices assemble it into parallel data and transfer it to the LSI 11 bus They accept data from the LSI 11 bus convert it into serial data and transmit it to the peripheral devices The two modules differ in that the DLV11 E offers full modem control whereas the DLV11 F supports either 20 mA current loop or EIA standard lines but does not include modem cont
96. nt set are also used in this manual POLARITY 15 either H or L to indicate the voltage level of the signal H 3 L ground As an example the signal K 3 INIT H originates on sheet K 3 of the drawings and means when INIT is true this signal is at approx imately 3 V LSI 11 bus signal lines do not carry a SOURCE indicator These names represent bidirectional wire ORed bus As a result multiple sources for a particular bus signal exist The LSI 11 bus signal names begin with for bussed The DLV11 E module is shipped with an H315 modem test connector included This is plugged into the interface cable in place of a data set when running maintenance programs The DLV11 F does not use this test connector A paper tape diagnostic maintenance program is shipped with the module for checkout and mainte nance The following programs are available DLV11 E MAINDEC 11 DVDVA DLV11 F MAINDEC 11 DVDVC 1 4 2 GENERAL DESCRIPTION 2 1 GENERAL The DLV11 E is designed to interface equipment that transmits and receives data over commu nications lines and conforms to EIA Standard RS232C and CCITT Recommendation V 24 The 11 is used by the program to control a communications data set through the use of control signals and handshake sequences The DLV11 F supports either EIA compatible data lines or 20 mA current loop data lines When configured for EIA support the DLV11 F transmits
97. on enabled 3 7 Jumper Designation FB 2 IP 2P 4A 5 1 Table 3 4 Jumper Configuration When Shipped Cont Jumper State _ Function Implemented speed operation disabled Halt on mE error disabled on DLV11 E dinka on DLV11 F Boot on framing error disabled The DATA TERMINAL READY signal i 18 not ere continuously True The REQUEST TO SEND signal i is not forced continuously True The contour the REQUEST TO SEND is is enabled The FORCE BUSY 15 disabled The 20 mA current receiver is configured as an active receiver The 20 mA current loop transmitter is configured for _ active operation Error flags are enabled on DLV11 E disabled on DLV11 F Factory test jumpers Not defined for field use Maintenance bit disabled 3 8 Table 3 5 Module Application Examples Module Equipment Supported DLVII E Bell Data Sets Models Modem Control 103 202C 202D 212A Bell Model 103 Data Set in automode DLVII F Teletype Model 37 Teletypewriter Teletype Model 33 and 35 Teletypewriters DIGITAL equipment DLVII F 20 mA Current Loop LA36 DECwriter read write LA35 DECwriter read only 5 Alphanumeric Terminal VT50 DECscope 12 line VT52 DECscope 24 line 02 Alphanumeric Terminals DFOI A Acoustic Telephone Coupler LT33 Teletypewriter LT35 Teletypewriter DATA SET CONTROL
98. or is received except when the Maintenance bit is set This causes the LSI 11 to reload the bootstrap Jumper B or B must be removed when B is inserted Jumper is removed to force DATA TERMINAL READY signal on Jumper is removed to force REQUEST TO SEND signal on This jumper is inserted to enable normal transmission of the REQUEST TO SEND signal Inserted to enable transmission of the FORCE BUSY signal for Bell model 103E data sets These three jumpers are inserted to make the 20 mA current loop receiver active Jumpers and 2P must be removed when 1A 2A and 3A are inserted These jumpers are inserted to make the 20 mA current loop receiver passive Jumpers and must be removed when and 2P are installed Inserted to make the 20 mA current loop transmitter active Jumpers 3P and must be removed when 4A and 5 are inserted Inserted to make the 20 mA current loop transmitter passive Jumpers 4A and 5A must be removed when 3P and 4P are inserted Jumper is removed to enable the error flags to be read in the high byte of the Receiver Buffer When inserted enables maintenance bit These are test jumpers used during the manufacture of the module They are not defined for field use Table 3 2 Baud Rate Selections Program Control Receive Jumpers Transmit Jumpers Baud Rate 50 75 110 134 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 Jumper Inserte
99. poem MIN 10 5 MIN 75 ns MIN dle MAX 25ns MIN 4 4 MIN 25ns MIN NOTES Timing shown at Master and Slave Device Bus Driver Inputs and Bus Receiver Outputs 2 Signal name prefixes are defined below T Bus Driver Input R Bus Receiver Output 3 Bus Driver Output and Bus Receiver Input signal names include a prefix 4 Don t care condition 11 4915 Figure 5 5 Data Output Timing 5 6 8 The computer removes the address from BDALOO L through 15 L and negates BBS7 L If a byte is to be transferred out to the device register BWTBT L remains asserted If a word is to be transferred BWTBT L is negated At this time the computer places data on the LSI 11 bus lines and asserts BDOUT L BDOUT L goes to the protocol chip and enables it to decode the states of BWTBT L and DATOO H The chip uses these signals to determine the desired byte of the addressed register Table 5 2 The device registers are configured for output transfers unless switched otherwise by BDIN L Therefore BDOUT L is not gated with the register select and byte lines Table 5 2 Byte Selection Output Operations Only Select Line Byte BWTBTL Asserted Selected High Don t Care OUTLB L and Both OUTHBL Low Low OUTLBL Low Low High OUTHB L High About 150 ns after it receives BDOUT L the protocol chip issues BRPLY L to the computer to signal that the module is loading data The compu
100. pt service see BIAKI L Once passed by a device it must remain passed until a new BIAKI L is generated BUS INTERRUPT ACKNOWLEDGE signal IN This sig nal is the processor s response to BIRQ L true This signal is daisy chained such that the first requesting device blocks the signal propagation while nonrequesting devices pass the signal on as BIAKO L to the next device in the chain The leading edge of BIAKI L causes BIRQ L to be unasserted by the requesting device ASYNCHRONOUS BUS INTERRUPT REQUEST from a device needing interrupt service The request is generated by a true RQST signal along with the associated true interrupt enable signal The request is removed after the acceptance of the BDIN L signal and on the leading edge of the BIAKI L signal or the removal of the associated interrupt enable or due to the removal of the associated request signal DEVICE INTERRUPT REQUEST SIGNAL When asserted with the enable flip flop asserted will cause the assertion of BIRQ L on the bus This signal line normally remains asserted until the request is serviced A 7 Table A 1 DC003 Pin Signal Descriptions Cont 11 ENBSTH INTERRUPT ENABLE A STATUS signal This signal 16 ENA STH indicates the state of the interrupt enable internal flip flop which is controlled by the signal line ENA DATA H and the ENA CLK H clock line 12 ENBDATAH INTERRUPT ENABLE A DATA signal The level on this 15 ENA DATAH
101. r another character of data 2 7 2 3 8 Baud Rate Control The baud rate control circuit generates clock signals that control the speeds at which the RBUF and XBUF move serial data The circuit can provide a common clock to both data buffer circuits common speed operation or separate transmit and receive clocks split speed operation In common speed operation both transmit and receive baud rates are either set by wire wrap jumpers RO through R3 or programmable by three state bus lines DAT12 H through DAT15 H In split speed operation the transmit baud rate is set by jumpers TO through T3 while the receive baud rate remains under the control of either RO through R3 or the computer program Should it be desired to use a baud rate not available from the baud rate control s crystal controlled clock generator the module has provisions for external inputs for both the transmit and receive clocks 2 3 9 Break Logic A BREAK signal is a continuous spacing condition on the serial data line The DLV11 E and DLV11 F can receive BREAK signals from a peripheral device normally the console device and can transmit BREAK signals to a peripheral device normally another processor Either operation can be enabled or inhibited by wire wrap jumpers When the interface module receives a BREAK signal from the serial data line it interprets the absence of STOP bits as a framing error It can respond to this apparent error or to an actual error in one of t
102. r connector Plug an H315 terminator into the free end of the interface cable Power up the computer Load and start MAINDEC 11 DVDVA When the program has been completed successfully turn off the dc power and reconnect the interface cable to the data set 3 42 DLV11 F Checkout DLVI1 F does not require a terminator plug for checkout Load and start MAINDEC 11 DVDVC Successful completion of the program indicates the module is acceptable 3 15 4 PROGRAMMING 4 1 INTRODUCTION Both the DLV1I1 E 11 program compatible with PDP 11 software Programs written for PDP 11 s using DL11 A through D interface modules will run an LSI 11 using DLV11 F configured for the same application Programs written for a DL11 E will run with a DLV11 E Also the DLV11 F will operate with LSI 11 programs written for the DLV11 This chapter defines the bits in each of the four device registers discusses interrupts and timing consid erations and gives programming examples 4 2 DEVICE REGISTERS All software control of the DLV11 E DLV11 F Asynchronous Line Interface is performed means of four device registers These registers have been assigned bus addresses and can be read or loaded with the exceptions noted using any LSI 11 instruction referring to their addresses Address assignments can be changed by altering jumpers on the module to correspond to any address within the range of 160000 to 17
103. rated individually It may be helpful however to refer back to Figure 2 3 for a general overview 5 2 BUS INTERFACE Four DC005 transceiver chips perform the bus interface functions The chips receive from and trans mit to both the computer s Bussed Address Data Lines BDALs and the module s three state bus data lines DATs The chips decode the module s address from the LSI 11 bus and place interrupt vectors on the LSI 11 bus 5 2 1 Address Decoding The computer addresses the module for both input and output data transfers A data transfer occurs in two stages address time and data time These are described further in Paragraph 5 3 I O Control Logic During address time the computer places the address on bus lines BDALOO L through 15 L and asserts the memory bank 7 select signal BBS7 L This signal indicates that the address is in the 28 32K range of addressing space and enables the DCO005 transceiver chips to decode the address The circuit performs a logical inversion on the entire address word and places it on the three state bus However it decodes only bits 03 through 12 Figure 5 1 Bits 00 through 02 pertain to device register selection and are routed to the I O control logic for decoding Bits 13 through 15 pertain to the selection of addressing space Their states are already indicated by BBS7 L Bits 03 through 12 contain the address of the specific DLV11 E or DLV11 F being addressed The bus inter face s addres
104. rol This manual describes these modules to the user It treats the two modules together for those functions common to both and separately for those areas in which they differ It is assumed that the reader has a general familiarity with the operation of the LSI 11 computer and with the requirements of the periph eral equipment Refer to Microcomputer Handbook EB 06583 76 for detailed information about the LSI 11 1 22 OPERATING FEATURES Each asynchronous line interface is constructed on a single 21 6 cm X 122 7 cm 8 5 in X 5 0 in dual height module The module mounts in any slot in the LSI 11 s backplane Both the DLV11 E and the DLV11 F have the following features e Jumper or program selectable crystal controlled baud rates 50 75 110 134 5 150 300 600 1200 1800 2000 3600 4800 7200 and 9600 e Provisions for user supplied external clock inputs for baud rate control e Jumper selectable parity and data bit formats e 51 11 bus interface and control logic for interrupt processing and vectored addressing of interrupt service routines Control status and data buffer registers directly accessible via processor instructions Program and peripheral connector plug compatible with the PDP 11 0111 series of asynchro nous line interface modules The DLV11 E is designed to interface data sets modems with control capability such as Bell models 103 202C and 202D The DLV11 F is designed for either 20 mA current
105. rst character is still being serially shifted out of the transmitter shift register Thus if the holding register and transmitter shift register are both empty the LSI 11 can parallel transfer a two character pair into the XBUF in less time than it takes for a single character to be serially transmitted to the peripheral device This advantage of double buffering applies only to the first two characters that is if a series of characters is being transmitted each character after the second must wait a serial character period for the XBUF to become ready again The actual time depends on the baud rate 5 15 BAUD FORMAT CONTROL TRANSMIT DATA BITS itk PERIPHERAL INTERFACE DATOS H gt DATO3 TRANSMITTER SECTION 5 DATO2H 9 gt XMIT DATO4H ROY DATO4H B DATOO H REGISTER SELECT 1 0 CONTROL LOGIC Figure 5 13 DLVII E and DLVII F XBUF Data Flow 11 4923 5 6 RECEIVER ACTIVE CIRCUIT The receiver active circuit produces a status bit to indicate that the RBUF is receiving a character of data This status bit RECEIVER ACTIVE is set by the START bit of the received data character and cleared by the receiver done RDONE H signal from the UART During the period between received data characters SI MARK H from the peripheral interface holds the receiver clock counter in the cleared state Figure 5 14 When a
106. rupt Enable Not Used SEC XMIT Secondary Transmitted or Supervisory Transmitted Data REQ TO SEND Request to Send This bit provides a receive capability for the reverse channel of a remote station A space 10 V is read as a 1 A transmit capability is provided by bit 03 Read only bit Reserved for future use This bit is set when an entire character has been received and is ready for transfer to the LSI 11 When set initiates an interrupt sequence provided RCVR INT ENB bit 06 is also set Cleared whenever the receiver buffer RBUF is addressed Also cleared by INIT Read only bit When set allows an interrupt sequence to start when RCVR DONE bit 07 sets Read write bit cleared by INIT See Note 1 When set allows an inerrupt sequence to start when DATA SET INT bit 15 sets Read write bit cleared by INIT See Note 1 Reserved for future use This bit provides a transmit capability for a reverse channel of a remote station When set transmits a space 10 V A receive capability is provided by bit 10 Read write bit cleared by INIT A control lead to the data set which is required for transmission jumper on the DLVII E ties this bit to REQ TO SEND or FORCE BUSY in the data set Read write bit cleared by INIT 4 3 01 Table 4 2 DLV11 E RCSR Bit Assignments Cont DTR Data Terminal A control lead for the data set communication Ready channel When
107. rupt Vector Signal Flow 5 18 Interrupt IME e qood EHE ee 5 19 Baud Rate Control Signal Flow 5 21 Break Logic Receive Signal Flow 5 25 Break Logic Transmit Signal Flow 5 25 Maintenance Logic 5 26 DLV11 E Peripheral Interface Signal 5 27 Data Lead Only Interface 5 28 20 mA Transmitter and Reader Run Circuit 5 30 Active Receive 20 mA Current Loop 5 31 Passive Receive 20 mA Current Loop 5 31 Interlock Jumper Data Flow 5 32 DC003 Simplified Logic Diagram A 3 DC003 A Interrupt Section Timing Diagram A 5 DC003 A and Interrupt Section Timing Diagram AOS A 6 DC004 Simplified Logic Diagram 9 DC004 Timing Diagram A 13 DC004 Loading Configuration for Table 2 A 14 DC005 Simplified Logic Diagram 16 DCOOS Timing EE CA 17 Data gd ur ape n eem oodd CER DE RES e A 19 UART Receiver Block Diagram A 20 UART Transmitter Block Diagram A 21 UART Pin 0621015 CE ederet 22 5016 B
108. s decoding circuitry compares the states of bits 03 through 12 with the conditions set by address jumpers A3 through A12 If a match 15 decoded the circuit asserts MATCH H to enable the I O control logic During data time the transceivers transfer data from the LSI 11 bus lines to the three state bus lines if the operation is an output data transfer If the operation is an input data transfer the I O control logic asserts the word signal INWD L switching the transceivers to their opposite state in which they transfer data from the three state bus to the LSI 11 bus 5 2 22 Vector Addressing The bus interface circuit can place one of two vector addresses on the BDAL lines when the interrupt function is enabled by the program Which vector is placed on the bus lines is determined by the interrupt logic Bit 02 of the vector word Figure 5 2 is controlled from the inter rupt logic This bit isin a TRUE state for a transmitter interrupt and is negated for a receiver interrupt Bits 03 08 can be selected by the user by removing or inserting vector jumpers V3 through V8 The remaining bits are all zeros 5 1 BDAL BITS 15 BBS7L 1 L lt RANGE 1600008 1777768 Figure 5 1 BDAL BITS 15 08 07 uu JUMPERS INSTALLED O REMOVED 1 RECEIVER TRANSMITTER DATA BUFFER
109. s of the UART Table 5 3 summarizes the possible connections discussed in this section 5 9 BREAK LOGIC The break logic performs two it causes a BREAK to be transmitted and it deiectis the action taken when a framing error or a BREAK is received 5 23 Table 5 3 UART Clock Sources Clock Source m Receiver Speed Transmitter Speed Dual Baud Rate Generator RO R3 Common Speed Split Speed TO T3 External Clock on Backplane Common Speed BL1 Split Speed External Clock on Header Connector Common Speed Only CC Requires Enable on pin HH 5 9 1 Receive Operation During normal operation the UART checks each received character for the proper number of STOP bits It does this by testing for a marking condition at the appropriate time If it finds a spacing condition instead it sets the framing error flag FR ERR The BREAK signal is a continuous spacing condition and is interpreted by the UART as a data character that is missing its STOP bit s The UART therefore responds to the BREAK signal by asserting FR ERR H Figure 5 18 MAINT L from the XCSR is gated with FR ERR H to inhibit the framing error signal FE H during the maintenance mode FE is applied to jumper B and is inverted and applied to jumper If jumper B is inserted and is removed FE H will negate control line BDCOK BDCOK H indicates to the LSI 11 that dc power is OK When negates this signal it ca
110. s the error bits OR ERR Overrun Error FR ERR Framing Error P ERR Parity Error Not Used RECEIVED DATA BITS When set indicates that reading of the previously received character was not completed RCVR DONE not cleared prior to receiving a new character Read only bit Cleared by INIT When set indicates that the character that was read had no valid STOP bit Read only bit Cleared by INIT When set indicates that the parity received does not agree with the expected parity This bit is always 0 if no parity is selected Read only bit Cleared by INIT Reserved for future use Holds the character just read If less than eight bits are selected then the buffer is right justified into the least significant bit positions In this case the higher unused bit or bits are read as O s Read only bits not cleared by INIT 4 6 Bit 15 12 11 10 08 07 06 05 03 02 15 14 13 12 11 10 09 08 SEL SEL SEL SEL SEL RESERVED 3 2 1 0 07 06 05 04 05 01 00 RESERVED MAINT SERVED BREAK 11 4967 Figure 4 4 DLVII E DLV11 F XCSR Bit Assignments Table 4 5 DLV11 E and DLV11 F XCSR Bit Assignments PBR SEL Programmable Baud Rate Select PBR ENB Programmable Baud Rate Enable Not Used XMIT RDY Transmitter Ready XMIT INT ENB Transmitt
111. ssing wire wrapping Solderless wrapped connection This connection consists of a helix of continuous solid uninsulated wire tightly wrapped around a wire wrap pin to produce a mechanically and electrically stable con nection In addition to the length of uninsulated wire wrapped around the wire wrap pin a half turn of insulated wire is wrapped around the pin to ensure better vibration characteristics Figure B 1 TAPERED TIP ON END TAIL THE PIN APEX CORNER OF THE PIN P OF WRA INSULATED WIRE No 30 AWG WIRE REFERENCE CORNER 11 4974 Figure B 1 Solderless Wrapped Connection on Wire Wrap Pin A turn of wire A turn of wire consists of one complete single helical ring of wire wrapped 360 degrees around a wire wrap pin intersecting four corners of the pin Thus a connection having n turns in contact with the wire wrap pin will intersect the reference corner 1 times Figure 2 A half turn of wire A half turn of wire contacts three of the four corners of a wire wrap pin Figure 3 End tail end tail is the end of the last turn of wire on the wire wrap pin WIRE CONTACTS ALL FOUR CORNERS AND CONTACTS THE REFERENCE CORNER TWICE 11 4975 Figure 2 Full Turn WIRE CONTACTS THREE CORNERS OF PIN 11 4976 Figure B 3 Half Turn 3 CONNECTIONS Turns counted along the edge of reference corner Figure 1 There should be seven to nine turns of insulate
112. ter addresses the desired register the bus interface and I O control logic circuits decode the address The I O control logic generates register and byte selection signals that enable the chips comprising the selected register Figure 5 10 Flip flops latch in control bits that are held in the register and data selectors route other bits to latches in the circuits which they control 5 11 TRANSMITTER TO CONTROL TRANSMITTER LATCHES CIRCUITS THREE STATE BUS RECEIVER TO CONTROL RECEIVER LATCHES CIRCUITS REGISTER AND BYTE SELECT I O LINES CONTROL LOGIC 11 4920 Figure 5 10 Control Status Registers During DATO or DATOB 5 5 DATA BUFFERS Both transmitter and receiver data buffering functions are performed mainly by a single LSI chip The chip is a Universal Asynchronous Receiver Transmitter UART The UART is a double buffered full duplex receiver transmitter The receiver section performs the RBUF function accepting asyn chronous serial binary characters converting them to parallel format and placing them on the three state bus The transmitter section performs the XBUF function accepting parallel data from the three state bus and converting it to a serial aysnchronous output The receiver strips START STOP and parity bits off the data coming in from the peripheral device The transmitter appends START STOP and parity bits to the data being transmitted out to the peripheral device Jumper control of the S
113. ter removes the data from its bus lines and negates BDOUT L The protocol chip responds to this by terminating BRPLY L The computer then terminates the bus cycle by negating BSYNC L and if applicable BWTBT L When BSYNC L is negated the protocol chip negates the register select and byte select lines 5 3 3 Vector Operation The I O control logic has the additional function of asserting BRPLY L in response to VECTOR H from the interrupt logic This action is independent of BSYNC L and MATCH H It is part of the interrupt sequence and is discussed further in Paragraph 5 7 5 4 CONTROL STATUS REGISTERS The RCSR and XCSR each consist of several types of flip flop latches rather than single devices Status bits from various circuits are placed in the registers and then under the control of the I O control logic gated on to the three state bus for transfer to the computer Control bits from the computer are loaded into the registers from the three state bus While in the registers they direct the operation of the modules 5 7 5 4 1 CSR Data Flow operation differs between the DLV11 E and DLV11 F only in those areas concerned with the peripheral interface requirements Figures 5 6 and 5 7 Some bits are set by the peripheral interface circuit receiver active circuit and the RBUF while others are set by the program via three state bus lines DATOO through DATO6 H RCSR bits except the DLV11 F s Reader Run Enable bit may be
114. upt enable bit is set RDONE H initiates an interrupt request The LSI 11 then has a full character period to service the interrupt before the next character moves into the holding register During this time the next character is being assembled in the receiver shift register After an LSI 11 DATI sequence has taken the data the I O control logic resets the receiver done status bit If the LSI 11 program does not take the data before the next character enters the holding register RDONE H does not get reset In this case the UART sets the data overrun flag OR ERR This bit goes with the next received data word to indicate that the old data was lost Any of the three error conditions Overrun Error Framing Error or Parity Error sets an end check error flag ERR as well as its own flag These error bits do not initiate an interrupt request but they are available in the high byte of the RBUF for the programmer s use 5 5 2 Transmit Operation The XBUF consists of two registers and their controlling logic all of which are contained in the UART chip A holding register stores the parallel data taken off the three state bus and then transfers it in parallel to the transmitter shift register Next the data is shifted out serially The format of the character being transmitted is controlled by the data format jumpers During idle time the UART transmits a continuous marking signal and holds the transmitter ready status bit XMIT RDY asserted in t
115. upt logic generates a transmitter interrupt when the program sets TRANSMITTER INTERRUPT ENABLE bit 06 in the XCSR and the UART asserts XMIT RDY H The UART asserts XMIT RDY H when the XBUF is empty and ready for more data from the computer When XMIT RDY H and TRANSMITTER INTERRUPT ENABLE are both TRUE the transmitter channel of the interrupt chip is enabled to request interrupt service Although these two signals are functionally bits 06 and 07 of the XCSR they are physically located in the interrupt chip After the computer acknowledges the interrupt logic s interrupt request the circuit asserts both VECTOR and VECRQSTB VECTOR is applied to vector address jumpers V3 through V8 the same as for a receiver interrupt vector In this case how ever VECRQSTB H causes the bus interface to assert BDALO2 L as well as the other selected bits on BDALO3 L through BDALOS L This results in the vector addressing of the transmitter interrupt service routine 5 7 4 Interrupt Transactions Either type of interrupt begins with the interrupt logic asserting BIRQ L the interrupt request line This is followed by an interchange of control signals and the vector address being placed on the LSI 11 bus lines The sequence proceeds as follows 1 The request is initiated by the interrupt logic asserting BIRQ L Figure 5 16 Q ns MIN 150ns MAX MINUS SERVICE TIME T IRQ 150 5 MIN 30 150 R DIN 40ns MAX RETAK
116. uses the computer to reload its bootstrap If jumper B is removed and jumper or is inserted the computer will not boot framing error If j jumper H is inserted FE H will negate control line BHALT L This causes the computer to halt when a framing error is received CAUTION mE If the LSI 11 is using MOS memory data lost when BDCOK H is negated because this action interrupts the memory refresh 5 9 2 Transmit Operation To transmit a BREAK signal the program sets the BREAK bit bit 00 in the XCSR Figure 5 19 The output of the XCSR latch holding the BREAK bit is used to inhibit the serial data output of the XBUF This causes the peripheral interface circuitry to transmit a continuous condition BREAK signal on the serial communications line BREAK generation be enabled by inserting jumper BG This allows the state of DATOO BREAK bit to control the BREAK inhibit gate When the BREAK bit is set 0 L is clocked to a continuous FALSE condition thus inhibiting the flow of serial data from the XBUF to the peripheral interface 5 24 MAINT L H BHALTL ERR DLV11 E 0411 11 4928 REGISTER SELECT PERIPHERAL INTERFACE 11 4929 Figure 5 19 Break Logic Transmit Signal Flow 510 MAINTENANCE MODE LOGIC In the maintenance mode the DLV11 E and DLV11 F modules route their output data
117. within a function of a bit time A second character can then be loaded which clears the flag again The flag then remains cleared for nearly one full character time 4 4 3 BREAK Generation Logic When the BREAK bit bit 00 in the XCSR 15 set it causes transmission ofa continuous space Because the XMIT RDY flag continues to function normally the duration of a BREAK can be timed by the pseudo transmission of a number of characters However because the transmitter is double buffered a null character all O s should precede transmission of the BREAK to ensure that the previous character clears the line In a similar manner the final transmitted character the BREAK should be null 4 4 4 System Reset Timing A system reset should not be performed immediately after the processor loads a character into the transmitter buffer for serial transmission If the system is reset before the last character has left the transmitter buffer the character will be lost when the buffer is cleared by INIT To avoid this the program should transmit two null characters after the last character and then wait for XMIT RDY to return to its true state Programs developed DLV 11 Serial Line Unit M7940 may not include these null characters since the DLV 11s transmitter buffer is not cleared 1 by the INIT 45 PROGRAMMING EXAMPLES mM Table 4 7 is an example of a typical program that
118. y characters from the bus and converts them to a serial asynchronous output with START and STOP bits added All UART characters contain a START bit five to eight DATA bits one or two STOP bits and a PARITY bit which may be odd even or turned off The STOP bits are opposite in polarity to the START bit Refer to Figure A 9 Both the receiver and transmitter are double buffered The UART internally synchronizes the START bit with the clock input to ensure a full 16 element clock periods START bit independent of the time of data loading Transmitter distortion assuming perfect clock input is less than 3 percent on any bit up to 10K baud The receiver strobes the input bit within 8 percent of the theoretical center of the bit The receiver also rejects any START bit that lasts less than one half of a bit time 10 RETURN TO IDLE DATA 5 4 sms o E OF LINE MS NEW CHARACTER RE e ee 1 ONE BIT ONE BAUD RATE 11 4968 Figure A 9 UART Data Format A 4 1 Receiver Operation A block diagram of the UART receiver is shown in Figure A 10 When the receiver is in the idle state it samples the serial input line SERIAL IN pin 20 at the selected clock edges R CLK pin 17 after the first mark to space transition of the serial input line If the first sample is a mark high the receiver returns

DLV11 -E and 0 LV11-F asynchronous line interface user's manual

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