Home

CM1-COMBO User's Manual

1. I000000000 Lr Ddpedwog NV PC MIP D 0000000000 Assembly Drawing SISI EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board For the positions of the connectors and jumper fields see the assembly plan above Connectors JACCBUS ACCESS bus FC Interface 4 pin Header J1 CompactPCI Connector J4 CompactPCI Connector PC MIP Module 1 0 J5 CompactPCI Connector PC MIP Module 1 0 MAJ1 MAJ2 PC MIP PCI Interface Module A MAJ3 PC MIP I O Interface Module A MBJ1 MBJ2 PC MIP PCI Interface Module B MBJ3 PC MIP I O Interface Module B MCJ1 MO2 PC MIP PCI Interface Module C MG3 PC MIP I O Interface Module C MDJ1 MDJ2 PC MIP PCI Interface Module D MDJ3 PC MIP I O Interface Module D SP1 RS 232 Serial Interface DSub 9 Jumper Field Factory Defaults DO Clock Source Selector Clock sourced from CompactPCI Bus Clock Factory Default JCLK i960 RP Configuration Selector 1 Initialization Mode 0 CPU held in reset 2 Accept CPCI Configuration Cycles 35 BIST active 4 CPCI Reset Passed Through to Local Reset e O Factory Default JCNF BEIS
2. 16 Hardware Watchdog 17 i960 RP Initialization Modes 7 Local DEVICES A O ae sds ie UUMEE sts ate ee ag et eg 20 Flash EEPROM store AA 20 Dynamic Random Access Memory DRAM 21 RS 232 Serial Interface 22 IC Interface o a sia 24 Serial EEPROM 24032 24 ACCESS busInterface 25 1 ciar 92 3592 9 429542 99999 90592 95 921 90592 susto dE eae 26 Diagnostics A A O A 27 CompactPCI 28 PCI Devices e 28 PCl To PCI Bridge Unit 28 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Address Translation Unit ATU 30 Systemi Connector M T apa qug ded ded arated ries cg esc geret od ge ec Sea o EA NN NR 33 VO Connectors JA PA and J5 P5 34 PC lt MIP Module Slots sin OD ROO ERE Ne es 35 Module TYPES e a re e ore aes E ea te HERUNTER ENSE ee aa ree mpa ka NAR AR nda 35 Module Injector Ejector 3
3. i E 9 o 2 2 B m e N P E N Ej NS N P N 2 Double size PC MIP Type Il Module 26 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board The CM1 COMBO is capable to carry four single size type I or type ll modules on the landing zones PC MIP A PC MIP B PC MIP C and PC MIP D The neighboring slots PC MIP A PC MIP B and PC MIP C PC MIP D respectively can carry double size modules of any type Module Injector Ejector To simplify the installation and removing of a module PC MIP uses an injector ejector system This consists of two mounting standoffs on the CM1 COMBO and two captive screws located at each end of the module This construction offers the advantage that the screws are used to fasten the module on the carrier board and in addition that the screws push the module out of the connectors when loosen the connection To install a module put the module loose on the PC MIP slot and fix the two screws by turning them clockwise This will pull the module connectors in the corresponding receptacle of the CM1 COMBO and fasten it Remove a module by turning the ejector screws counterclockwise This will pushing the module out of the connectors until it could be taken off PCI Interface The system interface of a PC MIP module
4. MDJ1 Pin Assignment 40 PC MIP Connectors MAJ2 MDJ2 Pin Assignment 41 PC MIP Connectors MAJ3 MDJ3 Pin Assignment 42 Pin Mapping PC MIP Module I Os To CompactPCI Connector J4 44 Pin Mapping PC MIP Module I Os To CompactPCI Connector J5 anaa 45 Ordering Information crecida tu ReSRERATERETDCDPE EE COR ee RS E 48 m EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7771 Intelligent PC MIP Mezzanine Carrier Board About this Manual This manual describes the technical aspects of the CM1 COMBO required for installation and system integration It is intended for the experienced user only Edition History EKF Document Ed Contents Changes Author Date Text 1851 2 2 Edition User Manual CM1 COMBO gn Febr 2001 cm1mle wpd English 3 Added chapter About this Manual gn 2 April 2001 set header font size to 12pt Nomenclature Signal names used herein with an attached designate active low lines Trade Marks Some terms used herein are property of their respective owners e g i960 RP Intel CompactPCI amp PICMG PC MIP amp MEN Micro SBS Technologies Windows 98 Windows NT Windows 2000 Microsoft EKF does not claim this list to be complete Legal E
5. CM1 COMBO CompacIPCI Intelligent Mezzanine Carrier Board for PC lt MIP Modules User s Manual Document No 1851 Edition 2 Released in April 2001 Valid for Rev 1 of the board MIP CM1 COMBO 7 7 7771 Intelligent PC MIP Mezzanine Carrier Board Contents Contents 2 gu 3 Dg RERO NORTE 4 Abou tthis Manual oes mette tA ch DE d tat Acta datu Mond ong 5 Edition sl ee SPSS 20 2 te ce eieiei EEE EEE EEE POE EE 5 A AA atre re Irae Or a dess a ee heia 5 Trade Marks 24606 26858 624280 2b Ra Ree E EE E AE EE E E EE ed d 5 Legal Exclaimer Liability Exclusion 5 Introduction and Overview uud rot nal T jo t ca he 6 Handling Informa tiOn ERR 8 Precautions 8 Guidelines to EMC Protection 8 Installing boards erica nr EE dee 9 Removing boards pure d anie tte t SC Re A te kaken te ae A te kje end 10 Connectors Jumper Fields Factory Defaults 11 PET RP Processor a oa aa 14 General Features wwa 14 Additional Documentation Zeie ee e E Rm e a e P edo 15 Clock and Reset Generation ss 16 Liao LE Lg ere cte ta tacta te ra tae e Ate Aa e t t pae ta E 16 Power On and Manual Reset
6. 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7771 Intelligent PC MIP Mezzanine Carrier Board ACCESS bus Interface To make it easy to connect external 1 C devices to the CM1 COMBO the board offers an ACCESS bus interface via the 4 pin connector JACCBUS The ACCESS bus is similar to the System Management Bus SMBus based on the FC bus Both standards are compatible to the I C bus with exception of a few electrically e g max load capacity and mechanical e g ACCESS bus defines a connector 1 C does not specifications The ACCESS bus interface on the CM1 COMBO supports up to 126 devices 7 bit device addresses minus the broadcast address and the on board serial EEPROM over a total cable length of 8 m with a maximum data rate of 100 Kbit s Each device may use its own data rate The cable consists of two shielded pairs a Ground 5V pair and a clock data pair Q z 3 O O lt We We 1 3 4 5 Connector JACCBUS EDGE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Interrupts The i960 RP provides an on chip programmable interrupt controller that allows a flexible priority level based reaction to internal and external events The processor uses inte
7. The main clock input is fed by one of two possible sources chosen by the 2x1 clock selection jumper JCLK near the J1 connector on the CM1 COMBO Clock Selection Jumper JCLK Setting Options Clock Source JCLK CompactPCI Bus Clock Signal J1 Pin D6 33 MHz Oscillator on the CM1 COMBO Normally the CM1 COMBO will be integrated in a CompactPCI rack with a system controller and possibly other boards In this case always the bus clock signal should be used as clock source JCLK removed To support a single stand alone operation without system controller the CM1 COMBO provides an on board 33 MHz oscillator that generates the necessary clock When setting the jumper JCLK the oscillators output is connected to the clock input of the board CAUTION Note that in this case the clock signal also occurs on the clock pin of the CompactPCI connector J1 Pin D6 This will lead to clock signal crashing on the bus if more than one board drives the clock The clock signal is distributed on the CM1 COMBO via a dedicated clock buffer to provide a low skew well conditioned signal as required by the PCI specification Power On and Manual Reset There are a lot of reasons which trigger a reset on the CM1 COMBO Power On switching on the power supply Vics drops below 4 65V power failed V 4 drops below 3 0V power failed Triggering the CompactPCI reset signal J1 Pin C5 JCNF 4 on Reaching time out of the hardware watchdog Sof
8. connectors J4 P4 and J5 P5 to pass the I O signals of the PC MIP modules to the rear of the system rack See Chapter PC MIP Module Slots for details of pin assignments EAT EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board PC s MIP Module Slots The PC MIP module concept was designed to offer flexible I O solutions at moderate costs This was reached by combining the advantages of PCI the good experiences of other module concepts like PCM or M Module and a small module dimension The PC MIP module standard is currently under development by the VITA 29 Task group of ANSI VITA Draft Standard Revision 0 93 February 1 2001 Information can be obtained by VITA Standards Organization 7825 East Gelding Drive Suite 104 Scottsdale AZ 85260 USA 1 602 951 8866 www vita com Module Types To adapt to different applications two basic types of BC e MIP modules are defined Type modules use the J3 connector of the module to pass l O signals to the CM1 COMBO for rear panel I O Type Il modules use an integral I O connector for I O via the front panel of the CM1 COMBO In addition the PC MIP specification distinguishes single size modules and double size modules The following schematic figure shows the general appearance of a single size type m
9. EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board Block Diagram CM1 COMBO PC MIP Modules Type I II U 32 SLOT A T 2 x Single size 1 x Double size 32 SLOT B a Sea 2 SLOT C E 9 2 x Single size 1 x Double size 42 SLOT D 9 A CompactPCl J4 og CompactPCl J5 Secondary PCI 32 bit Primary PCI 32 bit CompactPCI J1 DRAM FLASH PCI Bridge CPU Block Diagram CM1 COMBO REGE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board i960 RP Processor General Features The central unit on the CM1 COMBO is an i960 RP I O Processor a member of the 80960 family of high performance processors It combines a high speed CPU with powerful features to create an intelligent I O processor and integrates it into a Peripheral Components Interconnect PCI environment This multi function PCI device is fully compliant with the PC Local Bus Specification revision 2 1 The i960 RP local bus a 32 bit multiplexed burst bus is a high speed interface to system memory and I O Physi
10. a CompactPCI interface complying to the CompactPCI Specification Revision 2 1 CompactPCI is an industrial implementation of the familiar Peripheral Component Interconnect PCI bus It combines the well known electrical features of PCI with the more robust mechanical 19 inch rack mounting technology The interface supports 64 bit address and 32 bit data transfers It is designed for a clock frequency of 33 MHz with a transfer rate of up to 132 Mbyte s PCI Devices The CompactPCI interface is realized by the 960 RP processor It consists of two PCI functions thus it is a multi function PCI device The first function PCI function 0 is the PCI to PCI bridge unit which creates a data path between the primary the CompactPCI and the secondary the PC MIP interface PCI function 1 is the primary Address Translation Unit ATU This unit allows high speed accesses from the CompactPCI interface to the local bus devices like Flash EEPROM or DRAM Normally a BIOS running on a host system detects these PCI devices at boot time PCI To PCI Bridge Unit The PCI to PCI bridge unit serves as an electrical and logical buffer helping to overcome the electrical limits of the PCI bus Its main function is to provide a data path between the two independent PCI buses of the CompactPCI and the PC MIP interface The bridge unit features full compliance to the PCI to PCI Bridge Architecture Specification revision 1 0 It supports both upstreamin
11. bytes in size whereas the first 64 bytes must adhere to a predefined header format Primary and secondary ATU are programmed via type 0 configuration commands on the primary interface to PCI function number one Besides the i960 core processor can access the configuration space via memory mapped registers at local address 0x1200 Some of the read only registers can also be written by the i960 The following table shows the configuration header according the PCI Local Bus Specification revision 2 1 Address Translation Unit Configuration Header Format Reserved ATU Subsystem ID ATU Subsystem Vendor ID Expansion ROM Base Address Reserved Max Latency Interrupt Pin Interrupt Line EE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO CompactPCI Intelligent PC MIP Mezzanine Carrier Board The next table shows the i960 RP specific registers of the ATU configuration space Secondary ATU Status Register Secondary Outbound DAC Window Value Register SODWVR sg EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board System Connector J1 P1 The CompactPCI specification defines the usage of shielded 2 mm pitch 5 row connect
12. clearing the Core Processor Reset bit in the Extended Bridge Control Register EBCR bit 1 This deasserts the internal reset signal on the i960 core processor and the processor begins its initialization process Mode 2 allows configuration cycles on the PCI to PCI bridge at any time and allows the i960 Core processor to initialize after reset Mode 2 allows each unit of the i960 RP to be initialized in its own manner Be aware that race conditions may exist between i960 core operation after reset and host processor PCI configuration Mode 3 allows the i960 core processor to initialize and control the initialization process before the host processor is allowed to configure the i960 RP peripherals During this time the CompactPCI interface signals a Retry on all configuration cycles it receives until the i960 core processor clears the Configuration Cycle Disable bit in the EBCR The 3 jumper of JCNF exists to enable or disable the i960 RP s build in self test BIST If enabled the processor tries to check all its internal units If the check failed the processor asserts a signal that lights the red on board LED CPU FAIL and core execution stops Because BIST needs about 414000 CPU cycles it may be necessary to disable it when the restart time needs to be minimized Configuration Jumper Field JCNF BIST Setting Options JCNF 3 Processor BIST Jumper 4 of JCNF is used to forward the reset signal from the CompactPCI bus to the CPU and t
13. is called an outbound transfer The ATUs fulfil both address filtering and address translation For inbound transactions an ATU uses three registers e Inbound ATU Base Register Inbound ATU Limit Register Inbound ATU Translate Value Register A PCI address is detected as an inbound transaction by the ATU if PCI Address amp Limit Register Base Register The incoming 32 bit PCI Address is bitwise ANDed with the Limit Register When the result matches the Base Register the PCI Address is detected as being within the inbound translation window This opens a PCI address window from Base Register to Base Register Limit Register Once the transaction is claimed the address must be translated from a 32 bit PCI address to a 32 bit local address For that the incoming PCI Address is first bitwise ANDed with the bitwise inverse of the Limit Register This result is bitwise ORed with the ATU Translate Value Register The result is the 32 bit local address Local Address PCI Address amp Limit Register Translate Value Register In addition the ATUs provide address detection and translation for i960 core processor initiated cycles targeted to one of the PCI buses Both ATUs support two different translation modes e Address Translation Windows Direct Addressing Window The address translation windows are located from 048000 0000 to 09001 FFFF within the 32 bit local address space of i960 processor This range consists o
14. not connected on the CM1 COMBO See PC MIP Module Slot IDSEL Assignmenttable above for actual assignment wo 4 ETE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board System Connectors MAJ2 MDJ2 The following table shows the pin assignment of the PC MIP connectors MAJ2 MBJ2 MCJ2 and MDJ2 for the module slots A to D respectively PC s MIP Connectors MAJ2 MDJ2 Pin Assignment J2 P2 Pin Signal Name Signal Name J2 P2 Pin Reserved Reserved Reserved Reserved 5V 5V ACK64 3 3V ADO1 N AD03 ADO5 3 3V ADO7 ADOS N M66EN AD10 AD12 N AD14 C BE1 3 3V SERR 3 3V REQ64 3 3V ADOO AD02 O s n o el o co AD04 AD06 3 3V C BEO O mM rm wm yo l AT MIO el mn co AD09 AD11 AD13 3 3V AD15 U IP www w N CO a el E o B T SBO SDONE PERR 3 3V LOCK STOP GND DEVSEL 3 3V IRDY N C BE2 AD16 AD17 J2 P2 Pin Signal Name Signal Name J2 P2 Pin Notes 1 These pin positions are reserved by the PC MIP specification and not connected These pin positions are pulled to 3 3V via separate 4 7 KO resistors 3 This pin positions is not connected on the CM1 COMBO Qn ol ol SI E lM Ol oi o TRDY oa o ol o FRAME 3 3
15. 60 RP core processor Copy the program data and the Flash programming algorithm code to DRAM Run the programming code from DRAM Return to the calling function or restart the code loaded into the Flash devices 2 Programming via CompactPCI interface Reset the CM1 COMBO with JCNF setting to initialization mode 0 Alternatively the i960 RP core processor could be halted by executing the HALT instruction Program the Flash devices via the primary ATU Restart the processor Depending on the version of the CM1 COMBO there are different types of Flash devices in use 28F0165V Intel 28F16055 Intel These devices distinguish in access times and programming algorithms Programming tools currently running on LINUX or WinXX are offered by EKF and are available on request The following table shows the necessary initializations in the read and write wait state registers MBRWSO MBWWSO of the i960 RP memory controller dependent on the devices in use All timing parameters are based on a clock frequency of 33 33 MHz corresponding to 30 ns cycle time Flash Device Read And Write Wait State Settings Flash Device aana anana ee 28F160S5 0x00000220 0x00000220 20 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Dynamic Random Access Memory
16. 7 G NER 37 PCI IDSEL Assignment 38 PP ROUTING WEE 39 eai en eT osa Sese Rp xor ERE nb WA dE aos a a RO ea E 39 System Connectors MAN MDJI 39 System Connectors MAJ2 MDJ2 41 VO Connectors MAJS se MIDES 5000000008000 dru ord a ea Rr wa ane raden a 42 Mapping to CompactPCI WO Connectors J4 P4 and J5 P5 43 Technical Specifications Re 46 We Meter TEE 48 Figures CompactPCI PC MIP Carrier Module CM1 COMBO 6 Installing board into the system rack 9 Removing board from the system rack 10 hoc sabre 11 Factory Default JCLK SEERE EE 12 Block Diagram CM1 COMBO os ai A ete ie tn tn t Rn t 13 Clock Selection Jumper JCLK Setting Options 16 J mper Field JENE wa saree ia ogee an petere Rie We Mie qoe Bis ue e wie Right ee Rex 17 MG pr SPI sara zx General 1 C Addressing Byte Format 24 Serial EEPROM 24C32 Addressing Byte Format s 24 Connector AA e Eege 2e Diagnostics Display A 27 Single size PC e MIP Type I Module 35 Single size PCeMIP Type II Module 36 Double size PC MIP
17. DRAM The CM1 COMBO offers a working memory space of 8 Mbyte The memory is organized in two banks of non interleaved DRAM each 4 Mbyte in size The data path width is 32 bit without parity Similar to the Flash EEPROMs different types of DRAM devices are in use Possible types are e Fast Page Mode FPM DRAMs e Extended Data Out EDO DRAMs with an access time of at least 70 ns The following table shows typical values to program to the i960 RP memory controller to setup the DRAM interface All timing parameters are based on a clock frequency of 33 33 MHz corresponding to 30 ns cycle time DRAM Initialization Parameters DRAM Bank Read Wait State 0x00000000 RAS to CAS delay 1 5 cycles CAS pulse width 1 5 cycles no additional recovery wait states DRAM Bank Write Wait State 0x00000000 RAS to CAS delay 1 5 cycles CAS pulse width 1 5 cycles no additional recovery wait states DRAM Refresh Interval 0x00010204 Refresh enabled 15 625 us refresh interval DRAM Parity Enable 0x00000000 DRAM parity disabled DRAM Bank Control High current drives disabled DRAM bank enables 0x0000000D Fast Page Mode FPM 2 banks or 0x0000004D Extended Data Out EDO 2 banks EE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board RS 232 Serial Interface
18. ET EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Pin Mapping PC MIP Module I Os To CompactPCI Connector J5 AA s E J5 a ro ser nee asa 000 ase ner Ta mao nao m me en mer 057 pne see mer ns mar nn a o se are 051 ee men er ie aan mr as ane ae mer men are mr nor m A43 af aan aar aan ree aan ne ver ras fer ven je faen mes os mer are arr mer es om Fs ps s ane mer are aie ave mes fan are Jane re oos mer ane non ver Tas s o a aos 208 aoe aoe avs 600 vor aoe 009 aor a ow ow 3 3V 3 3V n ee ee om om 662 or 661 ws 660 B45 B44 B43 B42 B41 B36 B31 B21 ES papa s eno or or one o0 sor Bos aoe aor Ls pes me oo on oo om e on en ue paene pes ue pap a4 s Ls SABE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Technical Specifications W System Processor i960 RP and local Devices Y CPU Core gt Based on the i960JF high performance core gt Highest throughput at low power
19. To connect the CM1 COMBO to different peripheral devices the board offers a RS 232 serial interface The serial signals are fed to the male DSub 9 connector SP1 in the front panel labeled as RS232 of the board This allows to make a simple link to serial interfaces of terminals personal computers etc o o E Connector SP1 The above illustration shows the pin assignments to the connector SP1 front view of the connector Signal directions are seen from the view of the CM1 COMBO e g RxD SP1 pin 2 is an input to the CM1 COMBO Unnamed pins are not connected to any signal on the board The handshake input CTS SP1 pin 8 is pulled up by a resistor to bring the line to a proper state if the handshake signals are not used The pins 4 and 7 are pulled together on the board to the RTS line The interface is based on the well known Asynchronous Communication Element ACE 16C550 Clocked with a seperate 14 7456 MHz oscillator a transfer rate of up to 921 6 KBaud is possible The ACE is connected to bank 1 of the i960 RP s memory controller The following table shows the addressing of the ACE s registers relative to its base address ACE 16C550 Register Offset Definitions Base Address Read Access Offset Line Status Register LSR not allowed Scratch Register SCR Scratch Register SCR D lt EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail inf
20. Type ll Module 36 EE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Tables i960 RP Related Documentation 15 Configuration Jumper Field JCNF Initialization Mode Setting Options 18 Configuration Jumper Field JCNF BIST Setting Options 18 Configuration Jumper Field JCNF CPCI Reset Setting Options 19 Flash Device Read And Write Wait State Settings iles 20 DRAM Initialization Parameters 21 ACE 16C550 Register Offset Definitions 22 ACE 16C550 Read And Write Wait State Settings 23 Diagnostics Display Information 27 Bridge Configuration Header Format esee 29 Address Translation Unit Configuration Header Format 31 ATU Extended PCI Configuration Register Space 32 CompactPCI Connector J1 Pin Assignment 33 PC MIP Module Slot IDSEL Assignment 38 PCeMIP Interrupt Line Assignment 39 PC MIP Connectors MAJI
21. V o N O el ETE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board I O Connectors MAJ3 MDJ3 The following table shows the pin assignment of the PC MIP connectors MAJ3 MBJ3 MO3 and MDJ3 for the module slots A to D respectively PC MIP Connectors MAJ3 MDJ3 Pin Assignment J3 P3 Pin Signal Name Signal Name J3 P3 Pin UO 01 1 0 02 1 0 03 I O 04 I O 05 I O 07 N 1 0 10 1 0 11 1 0 12 1 0 13 UO 14 GND I O 15 1 0 16 I O 17 UO 19 I O 06 I O 08 I O 09 ep ojl D RAINJO n o I O 18 N ES N N I O 20 GND I O 21 b o I O 22 I O 23 I O 25 N I O 28 I O 29 I O 30 1 0 31 1 0 32 GND 1 0 33 I O 34 I O 35 I O 37 N I O 40 I O 41 I O 42 I O 43 I O 44 GND I O 45 I O 46 I O 47 1 0 48 I O 49 I O 50 J3 P3 Pin Signal Name Signal Name J3 P3 Pin GQ l m o 1 0 26 I O 27 BLO ao oO O 9 U elo a a a a AY AT SAR oO SI 1 0 36 I O 38 I O 39 A 00 ao oa AJN O o a o o aj a N colo sd s EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 77 Intelligent NIP Mezzanine Carrier Board Mapping to CompactPCI P I O Connectors J4 P4 a
22. are based on the well known PCI specification Regarding the mechanics PC MIP modules represent a smart and flexible successor to the M Module technology The PC MIP standard has been created by Motorola GreenSpring and MEN the specification is currently available as VITA draft submitted as ANSI standard to be released soon There can be no doubt that PCeMIP will determine the trend in mezzanine modules for many years For best results PC s MIP mezzanine modules should be used together with an intelligent carrier board as the CM1 COMBO Need a real time solution Take that CompactPCI PC MIP Carrier Module CM1 COMBO EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Based on the i960 RP embedded processor on board the CM1 COMBO is equipped with both a powerful CPU and a PCI bridge used as interface to the GompaciPCl system bus 8 MB DRAM and 4 MB Flash EEPROM build a generous local memory resource for program and data The on board 16C550 based serial communications interface can be connected to external peripherals e g as a diagnostic port The CM1 COMBO can be populated with up to 4 PC MIP modules of the type I I O wired across the rear CompactPCI connectors J4 J5 or type Il with front panel mounted connectors Neighb
23. cal and logical memory attributes are programmed via memory mapped control registers MMRs The core can maintain a sustained execution rate of one instruction per clock of most instructions The i960 RP features include Single clock execution of most instructions PCI to PCI Bridge Unit Independent Multiply Divide Unit Address Translation Unit e 128 bit register bus speeds local register caching DMA Controller 4 Kbyte two way integrated instruction cache Messaging Unit 2 Kbyte direct mapped integrated data cache Memory Controller 1 Kbyte integrated zero wait state data RAM e VC Bus Interface Unit The PCI to PCI bridge provides a connection path between two independent 32 bit PCI buses and provides the ability to overcome PCI electrical loading limits On the CM1 COMBO the bridge creates a data path between the CompactPCI bus and the PC MIP modules The bridge unit is fully compliant with the PCI to PCI Bridge Architecture Specification revision 1 0 published by the PCI Special Interest Group It allows certain bus transactions on one PCI bus to be forwarded to the other PCI bus Dedicated data queues support high performance bandwidth on the PCI buses The i960 RP supports PCI 64 bit Dual Address Cycle DAC addressing The bridge has dedicated PCI configuration space that is accessible through the primary PCI bus The two Address Translation Units ATUs permit direct data access from either PCI interface Compac
24. consumption 33 MHz 3 3 V gt Integrated 4 KB instruction and 2 KB data cache gt 1 KB internal data RAM 4 Memory gt 8 MB FPM or EDO DRAM gt 4 MB Flash ROM 32 Bit on board programmable gt Up to 4 KB burst transfers gt 32 Kbit serial EEPROM VO gt RS232 serial interface D SUB9 front panel connector 50 115 kBit s gt ACCESS bus interface SMBus 1 C across 4 pole pin header PCI to PCI Bridge gt Dual 64 Byte posting buffer for data transfer rate acceleration gt Forwards memory I O configuration commands from PCI bus to PCI bus gt local devices and memory accessible from CompactPCI bus including Flash ROM programming gt Conforms to PCI to PCI Bridge Architecture Specification revision 1 0 Y Diagnostics Debugging gt Red LED i960RP initializing fault Yellow LED access to PC MIP module s Green LED access to local peripherals or memory Reset push button switch optional NMI push button switch optional vy v v vy CompactPCI Bus 6 U height 20 32 mm width 32 Bit PCI interface 33 MHz max data transfer rate 132 MB s PCI 64 Bit dual address cycles Up to 64 byte PCI bursts Vp 3V Complies to CompactPCI Specification revision 2 1 eee ee gt TAGE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board
25. d system slots with dummy panels e Close unused front elements e g RS 232 interfaces with metallic caps Use shielded cables only e Use ferrites to prevent electromagnetic interference EMI Protect sensible interfaces e g Cheapernet with plastic caps ER EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board Installing boards Switch off the main power supply Touch the system rack to guarantee electrostatic discharge Move board carefully along the guide rails in the chosen slot of the rack Caution is given especially to the devices mounted on the backside of the circuit board Press the CompactPCI connectors of the board into the backplane receptacles by pushing the ejectors in the front panel together see illustration below Optionally screw board and rack together Switch on the main power supply Push down to insert move board at the ejectors carefully into the system rack BERE ABBA G CAUTION backside mounted devices 4 Push up to insert Installing board into the system rack No EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf
26. de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Removing boards Switch off the main power supply Touch the system rack to guarantee electrostatic discharge Optionally remove screws if board and rack are mounted together Press the board out of the CompactPCI backplane by pushing the ejectors in the front panel apart each other see illustration below Move board carefully along the guide rails out of the rack Caution is given especially to the devices mounted on the backside of the circuit board Put the removed board in the original EKF packaging bor Push up to eject Remove board at the ejectors carefully out of the system rack BARA annn BEBE oe CAUTION backside mounted devices Push down to eject Removing board from the system rack 10 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Connectors Jumper Fields Factory Defaults S gt z CM1 oE COMBO 8 2 PC MIP A EE oz ESSE S os or S ISPCON 3 PC MIP B S 2E ERE Es 5 as T 1 me JACCBUS 7B le
27. e also contains the information wether the following operations are read or write transfers If the address of an FC slave device on the bus matches the device address byte sent by a master the slave acknowledges the transfer General FC Addressing Byte Format On write operations R W 0 the master may send then further data bytes to the slave until the master generates a stop condition Each byte transferred is acknowledged by the recipient Read operations are working in the same way except that R W 1 and that the data flow is reversed Serial EEPROM 24C32 The CM1 COMBO offers a serial EEPROM 24C32 with a capacity of 4 Kbytes This device can be used e g to permanently store important parameters that should be non volatile even if the power disappears It is accessible as slave device via the 1 C bus Write accesses to the memory array of the serial EEPROM are possible any time because the hardware write protection feature of the 24C32 is not enabled on CM1 COMBO Serial EEPROM 24C32 Addressing Byte Format The above figure shows the FC bus device addressing byte that must be written to the serial EEPROM in order to read RAN 1 DeviceAddr 0xA1 or write R W 0 DeviceAddr 0xA0 data from or to it the 3 external address lines A offered by the 24C32 are hard wired to GND on the CM1 COMBO Read and write accesses with the I C bus maximum speed of 400 Kbit s are supported by the device s Sys EKF Elektronik GmbH Philipp Reis Str
28. erface while MxJ3 is the connector to wire the I O signals to the rear panel System Connectors MAJ1 MDJ1 The following table shows the pin assignment of the PC MIP connectors MAJI MBJ1 MO1 and MDJ1 for the module slots A to D respectively Enge EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board PC MIP Connectors MAJ1 MDJ1 Pin Assignment J1 P1 Pin Signal Name Signal Name J1 P1 Pin Reserved Reserved Reserved Reserved TRST 12V TMS TDI 5V INTA INTB INTC INTD 5V PRSNT1 Reserved PRSNT2st N MO OO ojoj RI N oO Reserved 3 3V Reserved GND Reserved RST 3 3V GNT N Co KM l pol nm E que m lal e Co eo Reserved wo e oO REQ 3 3V AD31 AD29 0 o eo A o Reserved AD30 3 3V AD28 AD26 N AD24 IDSEL 3 3V AD22 AD20 N AD18 Signal Name J1 P1 Pin Zl Kl A O El bM AD27 AD25 3 3V C BE3 AD23 O o a a a o Gl A N S oa 00 AD21 AD19 3 3V J1 P1 Pin Signal Name Q A 00 o o N Notes 1 These pin positions are reserved by the PC MIP specification and not connected See PC MIP Interrupt Line Assignment table above for actual assignment These pin positions are
29. f two 128 Mbyte memory windows and two 64 Kbyte I O windows for the primary and secondary ATU respectively Each memory window is divided into two areas 64 Mbyte for 32 bit PCI address cycles and 64 Mbyte for PCI double address cycles DAC The type of the PCI transfer is dependent from the area that is hit within the address translation window by the i960 core The translation mechanism used is very similar to the algorithm for the inbound transactions described above For memory and DAC accesses it is PCI Address Local Address amp OxO3FF FFFF Memory Window Value Register 20 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board UO transactions are translated by PCI Address Local Address amp 0x0000 FFFF VO Window Value Register In addition the i960 RP provides a direct addressing scheme This method of outbound PCI transactions is limited to memory transfers and works within the local address range from 0x0000 2000 to Ox7FFF FFFF only If enabled any access to these locations are forwarded to the PCI bus Which of the PCI buses are used will be decided by a bit in the ATU control register ATUCR This register also contains the direct addressing enable bit As every PCI device the ATUs implements their own configuration space This space is 256
30. g from CompactPCI to PC MIP and downstreaming from PC MIP to CompactPCI transfers Six 64 byte posting buffers are implemented in the bridge unit three for each direction PCI offers three separate address spaces 4 Gbyte memory address space 64 Kbyte I O address space 16 bit addressing 256 Byte configuration space The bridge unit acts as a filter between the primary and secondary interfaces When a memory or I O address is falling in the address window programmed in the bridge s configuration space this transaction is forwarded to the other PCI interface The configuration space of the bridge is accessible by the i960 core via memory mapped registers starting at local address 0x1000 Alternative a host can access it via CompactPCI type 0 configuration read or write cycles to PCI function number zero Some registers are read only by type 0 accesses but writable by the i960 core This allows to processor to initialize the bridge unit before the configuration process begins The following table shows the structure of the configuration space OF EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO CompactPCI Intelligent PC MIP Mezzanine Carrier Board Bridge Configuration Header Format Reserved Header Type Primary Latency Cacheline Size 0x0C Timer Reserved Secondary Subordinate Bus Seco
31. guration data can then be written or read via the Secondary Outbound Configuration Cycle Data Register SOCCDR sis EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board PCI Interrupt Routing Each PC MIP module slot offers the four interrupt request pins INTA INTB INTC and INTD These signals are wired between two module slots using a rotating schema similar to the logical interrupt assignment defined by the CompactPCI specification Assuming that each module drives just its INTAX pin this leads to a distributed interrupt request line load On the CM1 COMBO with four slots no module has to share an INTx signal with another one The next table shows the assignments of the INTx lines to the i960 RP PCI interrupt inputs For example INTA of slot A is connected to the 1960 s interrupt request input INTD PC MIP Interrupt Line Assignment i960 RP PC MIP Slot A PC MIP Slot B PC MIP Slot C PC MIP Slot D INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD Connectors PC MIP modules are connected to the carrier board via three identical 64 pin connectors These metric connectors have a pin spacing of 1 mm The connectors MxJ1 and MxJ2 are used to provide the signals for the PCI system int
32. he other local devices on the board DESS EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Configuration Jumper Field JCNF CPCI Reset Setting Options JCNF 4 CPCI Reset It is a good idea to remove JCNF 4 when the BIOS of the main CPU board within the CompactPCI does not recognize the CM1 COMBO after system reset EE GE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board Local Devices Flash EEPROM The CM1 COMBO is equipped with on board programmable Flash EEPROM devices The data bus width to these devices is 32 bit allowing the i960 RP to execute program code from Flash in full speed Therefore it is not necessary to copy the code into DRAM The Flash devices are connected to the memory bank O of the i960 RP Memory Controller They are readable and especially writeable any time with no need to enable the programming voltage Caution is given when the processor itself tries to program the Flash devices while executing code from the Flashs This will lead to a hanging processor core To program the Flash devices use one of the following alternates 1 Programming by i9
33. hed It can be identified by checking the NMI interrupt status register NISR bit 8 OR EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board Diagnostics Display There are three LEDs on the CM1 COMBO indicating the current state of the board Since no space was available in the front panel the LEDs are mounted near the back side of the SP1 connector They are visible through one of the PC MIP module windows in the front panel red yellow green Diagnostics Display The LEDs are having the following meaning Diagnostics Display Information build in self test failed both build in self test and local bus core state or local bus confidence test failed confidence test passed or processor held in reset state core is in executing mode core execution stopped yellow access to one of the PC MIP modules no access to any of the PC MIP PC MIP access modules green access to local DRAM Flash or ACE no access to any local device local access 5 277 a EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board CompactPCI Interface The CM1 COMBO offers
34. imum time of 1 6 sec after the last watchdog trigger pulse i960 RP Initialization Modes The behavior of the i960 RP after reset is controlled by the configuration selection jumper field JCNF The processor supports four initialization modes 0 to 3 where mode 1 makes no sense on the CM1 COMBO 1 2 3 4 Jumper Field JCNF SI EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Configuration Jumper Field JCNF Initialization Mode Setting Options Initialization JCNF 1 JCNF 2 CompactPCI Interface i960RP core Mode processor Mode 0 accepts transactions held in reset set Mode 1 retries all config transactions held in reset Mode 2 set accepts transactions Mode 3 retries all config transactions 1 Not useful on the CM1 COMBO Mode 0 allows a host processor to configure the i960 RP peripherals while the i960 core processor is held in reset The host processor configures the PCI to PCI bridge by assigning bus numbers allocating PCI address space and assigning IRQ numbers The memory controller and ATU can also be initialized by the host processor Program code for the i960 core processor may be downloaded into local DRAM or Flash EEPROM by the host processor The host processor then clears the i960 reset signal by
35. m PC MIP Slots PC MIP Bus Interface gt 32 Bit PCI interface 33 MHz Vp 3 3V Module Types 4 PC MIP landing zones A D for type I or type Il modules I O across CompactPCI J4 J5 or module front connector gt Neighboring slots A B C D can carry double size modules Connectors 3 each 64 pole free height connector according IEEE 1386 for any PC MIP slot Complies to PC MIP Draft Specification 0 93 ANSI VITA Task Group VITA 29 W Power Consumption 5 V 596 600 mA max without PC MIP module s 3 3 V 0 3V 1 1 A max without PC MIP module s 12 V 5 0 mA max without PC MIP module s 12 V 5 0 mA max without PC MIP module s m Temperature Humidity Operating temperature 0 70 C Humidity 5 90 non condensing Technical specifications are subject to change sd EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board Ordering Information Ordering Information COMBO CM1 1 COMBO 6U intelligent Carrier for 4 PC MIP Modules CPU i960RP 33MHz 8MB DRAM 4MB Flash ROM RS232 Serial Port CompactPCI Interface 32 Bit USB CMA 1 USB PCMIP Type II single size module 10H USB 1 1 12Mbps OHCI controller 1394 CMF 1 1394 PCMIP Type II single size module 10H IEEE 1394 OHCI FireWire Controller 400Mbp
36. nd J5 P5 The two next tables show the mapping of I O signals from the PC MIP modules to the CompactPCI connectors J4 P4 and J5 P5 The value in the column I O specifies the module slot and number of the I O signal feed to the corresponding pin The column MxJ3 gives the module slot and pin number of the PC MIP modules J3 connector for that I O signal Example On J4 pin A25 occurs the I O signal 50 of PC MIP module C which occurs also on MCJ3 pin 64 AG EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board Pin Mapping PC MIP Module I Os To CompactPCI Connector J4 i HTH as eso css om o tas one om eor 040 om a os on eor o oss 042 055 on om m e es em o em oa em om e 00 m cas se cae ou en oa ow on em om m em e eo em eos oa oer oss em om m cas cae cae car o co om con ce cer m sm ses ore o ore om em om o on m es ove ew err ore ew ee ors en om m eese es on co can o om o oor Low fo fa oo ox em om om em on on Ts INEA tity HEEN P ws os one 007 os ov oz os on ou s ere ore oos omr ome oo bar om ons oor Ls pee oe on om owo om cs on oo ELIE na ra rE rna L4 i Ls I I
37. ndary Bus Primary Bus 0x18 Latency Timer Number Number Number Secondary Status I O Limit UO Base 0x1C Prefetchable Memory Limit Prefetchable Memory Base 0x24 0x28 Reserved Ox2C 0x30 Subsystem ID 0x34 Reserved 0x38 Bridge Control Reserved 0x3C Secondary IDSEL Control 0x40 Primary Bridge Interrupt Status 0x44 Secondary Bridge Interrupt Status 0x48 Secondary Arbitration Control 0x4C PCI Interrupt Routing Control 0x50 Reserved Secondary UO Secondary I O 0x54 Limit Base Secondary Memory Limit Secondary Memory Base 0x58 Secondary Decode Enable 0x50 The registers with offset 0 to 0x38 are standard PCI to PCI bridge registers while the registers from 0x3C to Ox5C are i960 RP specific See i960 RP manual for details of the registers meaning Be EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board Address Translation Unit ATU The Address Translation Unit ATU provides an interface between the CompactPCI or PC MIP buses and the i960 local bus It consists of two parts the primary ATU for accesses from CompactPCI and the secondary ATU for accesses from the PC MIP modules Data transfers initiated by any PCI bus master to a local bus device are called inbound transactions If the i960 core starts a data access to any PCI bus slave this
38. o ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board In order to get a proper function of the ACE the following values should be programmed to the wait state registers of memory bank 1 Burst accesses to the ACE are not allowed ACE 16C550 Read And Write Wait State Settings 0x00000302 0x00000302 The ACE is able to request i960 RP core interrupts The request line of the ACE is fed to the interrupt input XINT5 of the processor An IRQ can be identified by checking the IIR of the ACE in the interrupt service routine The request is released by accessing the corresponding register that caused the interrupt e g reading an incoming character from the RBR See ACE data sheets and i960 RP manual for detailed description of interrupt programming NOSE EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board lC Interface The i960 RP supports a master and slave interface to the popular 1 C Inter Integrated Circuit bus This simple two wire serial bus allows an easy connection to other FC devices Transfer rates of up to 400 Kbit s are possible It could be programmed via the MC unit registers of the i960 RP An lC message consists of a device addressing byte and additional data bytes The device address byt
39. odule Single size PC MIP Type I Module Type modules are 47 mm by 90 mm in size They route their I O signals to the J3 connector of the module and then via traces on the CM1 COMBO to the CompactPCI connectors J4 P4 or 35 5 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7774 Intelligent PC MIP Mezzanine Carrier Board J5 P5 This kind of I O wiring makes it easy to remove the CM1 COMBO from the system rack with no need to remove any cable before Front I O Connector Single size PC MIP Type II Module Type Il modules provide a porch where a dedicated I O connector is located The PC MIP specification does not define a special type of connector to use This allows putting I O signals direct to the front panel of the CM1 COMBO and makes PC MIP modules usable also for high speed applications like Fast Ethernet etc that doesn t tolerate I O wiring to the back side of system rack Nevertheless a type ll module always contains the J3 connector J3 may be used by the module to get I Os also on the rear of the system rack but it doesn t have to do it Type II modules have a nominal size of 47 mm by 99 mm Double size modules are nearly twice the size of their single size counterparts Their sizes are 94 5 mm by 90 mm for type and 94 5 mm by 99 mm for type Il modules Front UO Connector
40. oring PCe MIP slots can hold double size modules When developing self written software for the CM1 COMBO 3 on board LEDs representing i960 and board status information are a valuable help Reset and NMI push button switches can be activated from the front panel The CM1 COMBO hardware supports the 1 0 interface This is a layered standardized driver concept modeled after the OSI reference suitable especially for intelligent VO sub processors For any different class of 1 0 devices the hosts operating system has to be provided with an Operating System Service Module OSM This is a hardware abstract LO driver layer just converting standardized 1 0 commands to proprietary I O system calls of the individual OS e g Windows NT from version 5 On the target device side the CM1 COMBO runs a Hardware Device Module HDM This driver interprets commands of the LO abstract OSM layer with concrete VO activities as the result The HDM layer does not depend on any specific OS EKF Elektronik GmbH Philipp Rei He An 1 0 communications layer between the OSM and HDM layers allows for flexible data exchange not only between host CPU and VO subsystem but also between the sub processors without charging the host with version 2 0 of the 1 0 specification Use of the intelligent CM1 COMBO frees the host CPU from critical low level tasks an essential criterion for real time applications Because the COMBO can be equi
41. ors on CompactPCI boards according to IEC 917 and IEC 1076 4 101 The 32 bit PCI interface is implemented via the J1 P1 connector while the 64 bit option requires the connector J2 P2 Since the CM 1 COMBO has a 32 bit CompactPCI interface the J2 P2 connector is not necessary and thus not mounted The J1 P1 connector also defines the supported signaling voltage Vyo A coding key in this connector is used to distinguish boards with Vi 3 3 V cadmium yellow key Vj 5 V brilliant blue key or both no key The CM1 COMBO is laid out for Vyo 5 V only and equipped with a blue coding key CAUTION Do not use the CM1 COMBO within a 3 3 V CompactPCI system CompactPCI Connector J1 Pin Assignment ae EET D E d AN I NN NE ES om a w wo ao morse m w m ADS AD2 m av GND ADe m EES ES omo om aw as am eo me sem em am mm oss vr am sone seo om me re ess oe mo roe oe RSC 3 3V FRAME IRDY op TRDY d Y Y PNI NN 28 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 777 Intelligent PC MIP Mezzanine Carrier Board Notes 1 These pin positions are not connected on the CM1 COMBO This signal is hardwired to GND on the CM1 COMBO WO Connectors J4 P4 and J5 P5 The CM1 COMBO uses the CompactPCI
42. pped with a wide variety of PC MIP modules it is a smart and flexible solution to many different industrial applications offering a fast time to market at moderate cost Member of PICMG Europe EKF Solutions Inside i960 Intel CompactPCI PICMG PICMG PCI Industrial Computers Manufacturers Group s Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Handling Information Precautions This CompactPCI board contains electrostatic sensitive devices The board should therefore remain in its original EKF packaging until it is used The antistatic coated film and box provide double protection against electromagnetic discharging as well as against dust corrosion and mechanical damaging Be sure to equalize the electrical potential of the board and the CompactPCI rack before taking out the board of the packaging by touching the packaging and metallic parts of the rack at the same time or better by wearing a ground strap Please I keep the original packaging for the case of return Notice that installing or removing of boards or other system components may done only by authorized persons Guidelines to EMC Protection To fulfill the CE specifications with regard to EMC take notice of the following guidelines Installation and operation only in EMC systems Close unuse
43. rrupt vector numbers to enter the interrupt service routine ISR This mechanism leads to fast reaction and low interrupt latency To optimize interrupt performance the vectors can be hold in the i960 RP internal RAM and the ISR can be frozen in the instruction cache See the i960 RP manual for details Internal interrupt events have their origin by the different units within the i960 RP like the FC unit the messaging unit etc External requests are fed to the processor via 8 maskable XINTO XINT7 and one non maskable NMI interrupt inputs The four inputs XINTO XINT3 are shared with the secondary PC MIP PCI interrupt inputs S_INTA S_INTD Four bits within the PCI interrupt routing select register PIRSR decide for each XINT S_INT pin wether the interrupt is lead to the i960 core or to the CompactPCI interface The CM1 COMBO owns the following peripheral interrupt devices 1 the four PC MIP modules via S_INTA S_INTD 2 the serial controller ACE via XINT5 3 the NMI push button via NMI non maskable For a description of the first two sources refer to the corresponding chapters The NMI push button is a nice tool when debugging software on the CM1 COMBO A debugger can enter the control of a running program when pushing the NMI push button Because this interrupt can not be masked by a program getting program control is always possible The interrupt request of the NMI button is active while the button is pus
44. s ISDN CMI 1 ISDN PCMIP Type II single size module 10H ISDN S T SO terminal adapter CMN 1 ETH PCMIP Type II single size module 10H 10 100Mbps Ethernet Controller RJ45 er EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de
45. ssing and interrupt generation The MU makes it easy to realize the Intelligent I O Interface 1 0 The Memory Controller allows direct control of the external memory respectively the memory mapped I Os on the CM1 COMBO including DRAM Flash EEPROM and the serial interface It features programmable chip selects and a wait state generator External memory can be configured as PCI addressable memory or private i960 RP memory Additional Documentation A detailed description of these and other features including the programming of the 960 RP processor could be find in the documentation listed below Electronic information can be obtained via http www intel com i960 RP Related Documentation Document Title Order Number i960 Rx I O Microprocessor Developer s Manual Intel Order 272736 i960 Rx I O Processor Specification Update Intel Order 272918 i960 RP RD VO Processor at 3 3 Volts data sheet Intel Order 273001 i960 Jx Microprocessor User s Guide Intel Order 272483 suse EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Clock and Reset Generation Clock Generation The CM1 COMBO is clocked by a single 33 MHz signal This master clock controls the entire timing of the i960 RP and is also the clock of the four PC MIP module slots
46. tPCI and PC MIP to local memory This allows for example the programming of the FLASH devices or downloading software to local memory via the primary CompactPCI interface without interaction of the i960 RP core Address translation is controlled through programmable memory mapped registers accessible from both the PCI interface and the i960 core processor The primary ATU has a dedicated PCI configuration space that is accessible through the CompactPCI bus or the i960 core The secondary PCI configuration space is accessible by the i960 core only The DMA Controller allows low latency high throughput data transfers between PCI bus agents and i960 RP local memory Three separate DMA channels accommodate data transfers two for the CompactPCI bus one for the secondary PCI bus The DMA Controller supports chaining and unaligned data transfers BEI EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPE Intelligent PC MIP Mezzanine Carrier Board The Messaging Unit MU provides data transfer between the PCI system and the i960 RP It uses interrupts to notify each system when new data arrives The MU has four messaging mechanisms Message Registers Doorbell Registers Circular Queues and Index Registers Each allows a host processor or external PCI device and the i960 RP to communicate through message pa
47. to its carrier board is based on PCI PCe MIP modules are 10096 compatible to the PCI standard defined by the PC Local Bus Specification revision 2 1 The modules are direct accessible by the i960 core processor via the secondary ATU and by a host via the PCI to PCI bridge unit within the i960 RP processor see chapter i960 RP Processor for details 5 87 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO GompactPC Intelligent PC MIP Mezzanine Carrier Board PCI IDSEL Assignment Every PCI device provides a configuration space of 256 bytes This space must be unique within the PCI system to configure each PCI device separately To do so the PCI signal IDSEL of each module slot is connected to a different address line of the secondary PCI bus The next table shows the corresponding assignment PC MIP Module Slot IDSEL Assignment Access to the configuration space of a PC MIP module is granted either by using the various types of PCI to PCI bridge configuration commands as defined by the PCI specification or by the i960 core processor via the secondary ATU In the latter case the processor has to write the PCI configuration address to the Secondary Outbound Configuration Cycle Address Register SOCCAR first see PCI Local Bus Specification revision 2 1 for details on configuration address formats The confi
48. tware reset caused by the i960 RP processor On Ln P UU KJ A A Ne N ll N N STG EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board The first 5 sources will reset all devices on the CM1 COMBO to a known state An integrated power supervisor generates a clean reset signal with a minimum length of 140 ms even if the voltages haven t stabilized at power on The signal is fed to the i960 RP the Flash EEPROMs the serial controller 16C550 and the four PC MIP module slots The processor can reset all four PC MIP modules by asserting the secondary PCI bus reset in the Bridge Control Register BCR bit 6 Further it can reset the 16C550 by triggering the local bus reset signal in the Extended Bridge Control Register EBCR bit 5 The i960 core is not able to reset the Flash EEPROMs Hardware Watchdog The CM1 COMBO is equipped with a hardware watchdog The watchdog is disabled after a hardware reset It is activated by toggling the general purpose output OUT1 of the UART This is done by changing bit 2 in the Modem Control Register MCR of the UART see section RS 232 Serial Interface for details of the UART s registers If the processor once touched MCR 2 the watchdog is armed and must be triggered at least every 1000 ms A hardware reset will occur after a max
49. xclaimer Liability Exclusion This manual has been edited as carefully as possible We apologize for any potential mistake Information provided herein is designated exclusively to the proficient user system integrator engineer EKF can accept no responsibility for any damage caused by the use of this manual 252 EKF Elektronik GmbH Philipp Reis Str 4 D 59065 HAMM Germany Tel 49 0 2381 6890 0 Fax 49 0 2381 6890 90 E Mail info ekf de Internet http www ekf de CM1 COMBO 7 7 7774 Intelligent PC MIP Mezzanine Carrier Board Introduction and Overview Modularity is the reason for their success different mezzanine modules can be combined on a single carrier board in order to achieve a functionality tailored exactly with the target application in mind Because the customer can profit from both individual configuration of the system and moderate cost mezzanine concepts as M Modules PMC Modules or Industry Packs are very popular for industrial grade computers Another advantage is the high density packaging as a result compared to solutions where functions are distributed over several full sized boards At the top of the evolution the PC MIP concept brings together the best characteristics of older mezzanine standards EKF now unveils the CM1 COMBO an 960 based intelligent CompactPCI carrier board for up to 4 PC MIP modules The PCeMIP PCI and M Modules and Industry Packs electrical characteristics

CM1-COMBO User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents