AMT-1 User's Manual
Contents
1. 21 3 1 2 21 3 1 3 CSR T oie RE 21 3 1 4 CSRI DER 21 3 1 5 EE 21 3 1 6 CSR In ries 21 ee 22 3 1 8 22 3 1 9 Of 22 3 1 10 ny UTE 22 3 1 11 M 23 3 1 12 CS IET aas E eM digi eo tee DEMO ska Co eiae I TOUR eines 23 3 1 13 24 3 1 14 M s 24 3 2 STATUS REGISTERS RETE 25 3 2 1 REN 25 352 2 26 3 2 3 CS RAO e e anu odas 26 3 2 4 26 3 2 5 acs saa 26 3 2 6 OU 26 3 3 qM 26 3 3 1 JTAG controller and instructions 27 3 3 2 Boundary SCAN reglsters cse e ett pe So e eene 26 3 3 3 TD code Yegister i Utente Oei te t b2. 10 2 6 TRIGGER MATCHING deed Nes adeo dete 10 2 7 gcc db uda Nec 12 2T Encoded deter eter ede po 12 2 2 IQUADNVOUITEC 2E 13 2 7 3 Bunch co nt Tessel eec dede CR HERE TR TU Oed Red 13 2 7 4 nm 13 24 9 LIVS ERE 13 2 7 6 see e e IE Ute e qo pe etes 14 2 8 READ OUT FIBRO sei ve lee dabei heads cime 15 2 9 READ OUT INTERFACE eel pene i d e e eR elg eller ne e EE eiTe dae 15 2 9 1 15 2 9 2 redd M 16 2 9 3 Packet form t se to ette e Coe oett inae ad aas eek rop dese RED Ue CUR RR eonun 16 2 10 ERROR MONITORING uere deli e e dl ti er lare eX I E o cpi Nis 18 3 CSRK REGISTERS amp 18 3 1 CONTROL REGISTERS 5 7 t done ee Qo eet iet dou EE den Ladd Cub eet vet idt des ictu ie 20 3 1 1
3. x2 mode x1 x2 x4 or x8 Input Clock x PLL mode 2 24 Channels 256 words 64 words 8 words 10 ns 500 kHz per channel Low Voltage Differential Signaling LVDS Internal 100 Ohm termination 3 3 0 3 lt 200 mA 0 85 Deg Cent 0 3 um CMOS Sea of Gate Toshiba TC220G die size 6 mm x 6 mm 0 5 mm lead pitch 144 pin plastic QFP Fine Time Measurement The original idea of the which use internal gate delay as a fine time element and stabilize the element with a feedback circuit was born in 1986 3 The chip was called TMC Time Memory Cell chip Initial TMC chip use a DLL Delay Locked Circuit technique and then PLL Phase Locked Loop technique has been used in recent chips In the PLL version we have been using a new kind of voltage controlled ring oscillator asymmetric ring oscillator Fig 2 To obtain 1 ns timing resolution 16 taps are extracted from the oscillator Fig 2 shows a simplified schematics and its timing diagram of the asymmetric ring oscillator Fig 2 only shows 8 stages but the actual chip implements 16 stages The asymmetric ring oscillator was creates equally spaced even number 16 of timing signals PLL circuit comprises a phase frequency detector PFD a charge pump a loop filter LPF and a voltage controlled oscillator VCO asymmetric ring oscillator in this case An external capacitor Cvg is required in the loop filter The PLL has divide by 2 4 and 8
4. RESETP csrO 5 RESETM 2 7 2 Event count reset An event count reset loads the programmed event count offset into the event ID counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable sepa evrst is set 2 7 3 Bunch count reset The bunch count reset loads the programmed offsets into the coarse time counter the trigger time tag bunch id counter and the reject counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable sepa bcrst is set From a bunch count reset is given to the TDC until this is seen in the hit measurements themselves a latency of the order of 2 clock cycles is introduced by internal pipelining of the coarse time counter The definition of time 0 in relation to the bunch count reset is described in more detail in section 4 2 7 4 Global reset The global reset generate master reset signal if enable mreset code is set see Fig 6 The master reset clears all buffers in the TDC and initializes all internal state machines to their initial state Before data taking an event count reset and a bunch count reset must also have been issued As shown in Fig 6 decoder circuit CSR JTAG contrioller and PLL circuit are not reset by the master_reset 2 7 5 Trigger The basis for the trigger matching is a trigger time tag locating in time where hits belong to an event of interest The first level trigger decision must be given as a c
5. see Fig 12 LVDS output LVDS output dioen gt di 0 J 911 lt I do 11 di 11 lt scan out Boundary Scan Register scan_in enable output buffer bsr_in BSR bsr out scan out 2n scan in bsr_in BSR bsr out scan out scan in do 12 bsr_in BSR bsr out S 210 12 2n scan_in scan_out bsr_out BSR bsr in scan out scan_in p de 12 bsr_in BSR bsr out pio 12 scan_out bsr_in BSR bsr out 2101 scan out scan in bsr_out BSR bsr in scan out scan in bsr_in BSR bsr out DIO 11 scan out scann 51 bsr_in BGR bsr out gt 210 51 scan out scan in bsr out BGR bsr in scan_out scan in Fig 12 JTAG boundary scan circuit for the DIO port 3 3 3 ID code register A 32 bit chip identification code can be shifted out when selecting the ID shift chain 0 11 1 27 12 31 28 Start bit 1 manufacturer code 20001 0011 000 Toshiba TDC part code decimal 1000 1011 1000 0011 assignd by Toshiba Version code 0001 Thus the total ID code in hex format is 18B83131 3 3 4 Control registers The JTAG control scan path is used to set CSRO 14 registers that should not be changed while the TDC is actively running See section 3 1 for register details 3 3 5 Status registers The JTAG status scan path is used to get access to the
6. 16 15 14 9 716 5 4 32 10 0 0 1 I TDCID Channel TDC channel number Coarse Time Coarse time measurement in bins of 25ns Fine Time Fine time measurement from PLL in bins of 25ns 32 T Edge type 1 leading edge 0 trailing edge E Hit error error has been detected in the hit measurement a coarse error a channel select error or all buffer error Combined measurement Combined measurement of leading and trailing edge 3113029 28 2726 2524 23 22 21 20 19 1817 re 5 4113 12 11 30 9 8 7 6 5 4 312 o 1 0 0 Fine Time Width Width of pulse in programmed time resolution CSR9 width select If the pulse width excees the width range the width will be FF Coarse Time Coarse time measurement of leading edge relative to trigger bins of 25ns Fine Time Fine time measurement of leading edge in bins of 25ns 32 Errors Error flags sent if an error condition have been detected 31 30 29 28 27 2625524 23 2 21 20 19 18 17 16 15 r4 8 7 6 5 4 32 110 o 1 1 of ror flags Error flags see Table 2 and CSR16 Debugging data Additional information for system debugging Separator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1411311211110 9 8 7 6 5 403121100 1 1 1 mcm 0 0 0 _____ Bunch ID Trigger time tag counter when separator was generated Buffer Occupancy 31 30 29 28 27 26 25 24 23 2
7. Muon TDC version 1 AMT 1 is a Time to Digital Converter TDC designed for the Monitored Drift Tubes MDT of the ATLAS muon detector It is processed in Toshiba 0 3 um CMOS Sea of Gate Technology TC220G Basic requirements on the AMT chip were summarized in ATLAS note MUON NO 179 1997 by J Christiansen and Arai Then AMT 0 1 was designed in a 0 7 um full custom CMOS process based on the 32 channel TDC for the quick test of front end electronics and MDT chambers On the other hand it was decided to use a Toshiba s 0 3 um CMOS process for a final production To develop and test many critical elements in the 0 3 um process a Test Element Group chip AMT TEG 2 was designed fabricated and tested successfully at KEK The AMT TEG was processed in a new 0 3 um process which will be used in final mass production The present AMT 1 design is based on the 0 but many modifications are done since the technology is different and many experience was obtained A time bin size 0 78 ns is obtained using the basic gate delay as base for the time measurement This scheme prevents the use of very high speed clocks in the circuit and results in a low power device 20 mW channel The gate delay of CMOS devices normally have very large variations as function of process voltage and temperature In this TDC a phase locked loop PLL circuit is implemented to stabilize the gate delay Oscillation frequency of the internal
8. basically be divided into three different areas as shown in the figure below A Time relationship between the hits clock and the bunch count reset generating the basic timing measurements of the TDC B Time relationship between the performed time measurements and the trigger time tag C Time relationship between the time measurements and the automatic reject 3l read out FIFO trigger maching Trigger FIFO 1 L1 buffer reset 4 Hit channel buffers y gt gt coarse count load LL reset vay Ni ue ee oe Fig 12 Time alignment between hits trigger and automatic reject A Basic time measurement As previously stated the basic time reference of the TDC measurements is the rising edges of the clock The bunch count reset defines the TO reference time where the coarse time count is loaded with its offset value The TDC also contains internal delay paths of the clock and its channel inputs which influences the actual time measurement obtained These effects can be considered as a time shift in relation to the ideal measurement The time shifts of individual channels may be slightly different but care has been taken to insure that the channel differences are below the bin size 1 ns of the TDC The time shift of the measurements also have some variation from chip to chip and variations with supply voltage and temperature These variations have also
9. bits to generate an ERROR signal When the ERROR signal becomes active the TDC can respond following ways Ignore No special action will be performed Mark events All events being generated after the error has been detected will be marked with a special error flag 3 CSR Registers amp JTAG access There are two kinds of 12 bits registers CONTROL and STATUS registers The CONTROL registers are readable and writable registers which control the chip functionality The STATUS registers are read only registers which shows chip statuses There are 15 Control registers CSRO 14 and 6 Status registers CSR16 21 These registers are accessible from 12 bit bus DIO 11 0 or through JTAG interface 18 DIO 11 0 RA 4 0 WR CS TDO Xcz TDI eee Instruction register TAP Controller Fig 10 Structure of JTAG CSR registers 19 3 1 Control registers Table 3 Bit assignment of the control registers CSRO global ri error jdisable_ enable CSRI test test ienable idisable reset 0 10 eset 0 11 erst _ i berevr 0 8 encode 0 9 mode 0 7 invert direct ringosc 0 0 0 6 5 4 mask_window 0 23 12 clkout_mode 0 3 2 0 1 0 CSR2 search window 0 35 24 CSR4 reject count offset 0 59 48 CSR3 match_window 0 47 36 CSR6 bunch count offset 0 83 72 CSR5 event count offs
10. counter thus the frequency of the VCO can be either the same or the multiplied by 2 4 or 8 of the input frequency The propagation delay of the delay elements that determine the oscillation frequency of the VCO is controlled through a control voltage V GN When hit occurs the state of the 16 taps and coarse counter latched into a hit register a S 004 041 911 051 021 244 M2 q A B C D m3 V J 7 NU van m O I Fig 2 a Asymmetric ring oscillator b extracted timing signal 2 2 Coarse Counter The dynamic range of the fine time measurement extracted from the state of the VCO is expanded by storing the state of a clock synchronous counter The hit signal may though arrive asynchronously to the clocking and the coarse counter may be in the middle of changing its value when the hit arrives To circumvent this problem two count values 1 2 a clock cycle out of phase are stored when the hit arrives Fig 3 Based on the fine time measurement from the PLL one of the two count values will be selected such that a correct coarse count value is always obtained The coarse counter has 13 bits and is loaded with a programmable coarse time offset the LSB is always 0 at reset The coarse counter of the TDC will in ATLAS be clocked by the two times higher frequency than the bunch crossing signal thereby the upper 12 bit of the coarse counter becoming a bunch count ID o
11. cycle you can assume larger value for CC such as CC 4096 window indicates window size so all these parameter is positive value 0x001 means 1 clock tick window and OxFFF means 4095 clock tick window 33 offset indicates relative time between each counters These offset is loaded into respective counters when bunch count reset is asserted All counters are roll over at value count roll Thus larger value than count roll has no meaning for the window size and the offsets 34 Appendix A Internal Data Format Channel Buffer first data 424140 3231 30 29 282726 181716 151413 3210 coarsel parity rejected edge coarse2 coarse2 coarsel vernier parity second data 888786 747576 74 73 72 606162 616059 444546 1 parity Reese rejected edge coarse2 coarse2 coarsel vernier parity if enable pair 0 edge 0 trailing edge edge 1 leading edge if enable pair edge 0 trailing edge found edge 1 trailing edge not found Level 1 Buffer parity make buffer overflow separator overflow stored enable pair 0 29 28 27 26 25 242322212019 18 17 1615 14 13 1211 109876543210 Dee see 29 28 27 26 25 24 23 22 21 20 19 18 17 1615 14 131211 109876543210 enable pair 1 over flow 29 28 27 26 25 24 23 22 21 20 19 18 17 161514 131211 109876543210 enable pair 21 under flow
12. mask window will set its mask flag The mask flags for all channels are in the end of the trigger matching process written into the read out FIFO if one or more mask flags have been set In case an error condition L1 buffer overflow Trigger FIFO overflow memory parity error etc has been detected during the trigger matching a special word with error flags is generated if enable errmark and corresponding enable error bits are set All data belonging to an event is written into the read out FIFO with a header and a trailer if enable header and enable trailer bits are set respectively The header contains an event id and a bunch id The event trailer contains the same event id plus a word count The trigger matching function may also be completely disabled enable matching 0 whereby all data from the L1 buffer is passed directly to the read out FIFO In this mode the TDC have an 11 effective FIFO buffering capability of 256 64 2 320 measurements An example of setting is shown in 4 1 2 7 Trigger Interface The trigger interface takes care of receiving the trigger signal and generate the required trigger time tag to load into the trigger FIFO In addition it takes care of generating and distributing all signals required to keep the TDC running correctly during data taking The TDC needs to receive a global reset signal that initializes and clears all buffers in the chip before data taking A bunch count reset and event count reset
13. occurs event data will be rejected to prevent the L1 buffer and the trigger FIFO to overflow The event header and event trailer data will never be rejected as this would mean the loss of event synchronization in the DAQ system Any event which have lost data in this way will be marked with an error flag Reject enable rofull reject 1 As soon as the read out FIFO full event data not event headers and trailers will be rejected Any loss of data will be signaled with an error flag 2 9 Read out Interface All accepted data from the TDC can be read out via a parallel or serial read out interface in words of 32 bits The event data from a chip typically consists of a event header if enabled accepted time measurements mask flags if enabled error flags if any error detected for event being read out and finally a event trailer if enabled 2 9 1 Parallel read out Read out of parallel data from TDC is enabled by setting enable 0 and performed a clock synchronous bus Several TDC s may share one read out bus and each TDC will be selected with CS chip select and DSPACE data space signals 15 The read out of individual hits are controlled by a DREADY data ready GETDATA get data handshake If the GETDATA signal is constantly held active independent of DREADY it is interpreted as the read out can be performed at the full speed of the TDC The effective read out speed can be slowed down by using the
14. ring oscillator is multiplied by two with the PLL thus generate 80 MHz clock This oscillator has 16 taps and time difference of two taps are exactly 1 16 of the clock period When a hit enters state of these 16 taps are latched and generate a fine time The fine time measurement is extended by a 13 bit coarse counter Although the PLL clock is 80 MHz most of logic runs at 40MHz which is same as that of the LHC clock Each channel can buffer 4 measurements until they can be written into a common 256 words deep level 1 buffer The individual channel buffers works as small derandomizer buffers before the merging of hit measurements into the common L1 buffer A trigger matching function can select events related to a trigger The trigger information consisting of a trigger time tag and an event ID can be stored temporarily in an eight words deep trigger FIFO Measurements matched to the trigger are passed to a 64 words deep read out FIFO or A time window of programmable size is available for the trigger matching to accommodate the time spread of hits related to the same event Optionally channels with hits in a time window before the trigger can be flagged The trigger time tag can optionally be subtracted from the measurements so only time measurements relative to the trigger needs to be read out Accepted data can be read out in a direct parallel format or be serialized at a programmable frequency Control amp Data JTAG signals JTA
15. 2 2120119 18 1716 15 1a 13 12 8 7 6 5 4 3 2 1 0 ojojoj L1 occupancy L1 buffer occupancy 17 R Read out FIFO full 2 10 Error monitoring All functional blocks in the TDC are continuously monitored for error conditions Memories are continuously checked with parity on all data internal state machines have been implemented with a hot encoding scheme and is checked continuously for any illegal state The JT AG instruction register have a parity check to detect if any of the bits have been corrupted during down load The CSR control registers also have a parity check to detect if any of the bits have been corrupted by a Single Event Upset SEU The error status of the individual parts can be accessed via the CSR status registers Table 2 Description of Errors Flags Comseemr ____ 0 A parity error in the coarse count has been detected in a channel buffer channel being written into the L1 buffer Readout 6 sate Parity enori Any detected error condition in the TDC sets its corresponding error status bit The error bits are reset by a global reset or error reset CSRO 10 The error bits are also reset by bunch count reset or event count reset if enable bcrevr is set the available error flags are OR ed together with individual programmable mask
16. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 Readout FIFO Event Header 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 1010 trigger_data 23 0 Lost Event Header 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 parity 1010 lost_trigger 1 1 0 trigger_data 11 0 Event Trailer 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 1100 trigger data 23 0 3 Lost Event Trailer 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 parity 1100 lost trigger 11 0 Error 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6543210 Mask Flags 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109876 543210 parity 0 0 1 0 mask flags 23 0 Single Measurement enable relative 0 28 27262524 23222120 19 16 15 14 13 1211 109876543210 Hit Error data 31 l1 data 30 T Edge Type data 17 Single Measurement enable relative 1 28 27262524 23222120 19 1615141312111098765 43210 0 0 1 1 data 2925 coarse relative 11 0 11 data 4 0 Combined Measurement enable 0 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 parity 0 100 11 data 29 17 data 10 0 Combined Measurement enable relative 1 28 27262524 23222120191817161514131211 1098765 43210 parity data 29 17 corase_ 11_data 4 0 relati
17. AMT 1 ATLAS Muon TDC version 1 User s Manual Yasuo KEK National High Energy Accelerator Research Organization 1 1 Oho Tsukuba Ibaraki 305 Japan yasuo arai kek jp http atlas kek p araiy Tel 81 298 64 5366 Fax 81 298 64 2580 ES Chip produced on Mar 2000 Rev 0 71 Jan 11 2001 zt III FUP Ur d Ir A Pa MI uum k 4 m _ s i e E 2 m Contents 0 AND FUTURE CHANGES eene o eei eua ne S nano no au ea us no cesses popa oa aa ieS Ra a 4 0 1 BUGS ica ee EU Wee Ee RP RN Udemm edet 4 0 2 FUTURE CHANGES bre erecto e Pete e deo poise stes 4 1 INTRODUCTION Po 5 2 CIRCUIT DESCRIPTION nensis o eere se Sane ra oae rana Fo E Ra 6 2 1 FINE TIME MEASUREMENT se eese sessi re esse e eset e sese reser reser eese 7 2 2 COARSE COUNTER velle eet diee tte be AR ede FR AEM eR 8 2 3 CHANNEL BUFEER nonne eerie eel i ciet dec la qu e pue a lar e E dO be 9 2 4 5 55 52 f res ns ae as Bote d Cosa ERO E PR C RE ED RE er Pn pere e ER ER EE Parse epe 9 2 5 ID EUIS e
18. DREADY GETDATA handshake protocol to introduce wait cycles The number of clock periods that the GETDATA signal is asserted is used to determine the word count for the event available in the global trailer 2 9 2 Serial read out The accepted TDC data can be transmitted serially over twisted pairs using LVDS signals by setting enable serial 1 Data is transmitted in words of 32 bits with a start bit set to one and followed by a parity bit and a stop bit When no data is transmitted the serial data and clock lines are kept at zero The serialization speed is programmable from 80 to 10 Mbits s Serial clock pos SE CES TATARAN Serial data start bit31 bit 30 stop Fig 9 Serial frame format with start bit and parity bit In addition to the serialized data an LVDS pair can carry strobe information in a programmable format as shown in Fig 9 Leading Strobe Direct serializing clock to strobe data on rising edge DS Strobe DS strobe format as specified for transputer serial links DS strobe only changes value when no change of serial data is observed For each format there are two modes one is continuous strobe regardless of data existance another mode generate strobe signal only when data is available t Serial data start parity stop DS Strobe 1 strobe_select 0 DS Strobe 1 strobe_select 1 Leading Strobe strobe select 2 Leading Strobe st
19. G TAP Serial Control Data Status Status Registers Serial Strobe zu Built In Self Test Trigger 2 44 Reject Time Counter Trigger Mask Window Matching Matching Window Search Window Start Pointer Status Channel Pulse Width Edge Time EE EE b Level 1 Buffer fe ie Pinter Channel Encoder amp Formatter Controller Fine Time Leading Edge Inputs 24ch 12 16 Fig 1 Block diagram of the AMT 1 2 Circuit Description Fig 1 shows a block diagram of the AMT 1 chip There are 24 channels of inputs Table 1 summarizes the main features of the AMT 1 chip 2 1 Table 1 1 MAIN FEATURES System Clock Frequency is 40 MHz otherwise noted Least Time Count Time Resolution Dynamic range Integral Non Linearity Differential Non Linearity Difference between channels Stability Input Clock Frequency PLL mode nternal System Clock No of Channels e Level 1Buffer Read out Buffer Trigger Buffer Double Hit Resolution Max recommended Hit rate Hit Input Level Supply Voltage Temperature range Process Package 0 78 ns bit rising edge 0 78 100ns bit falling edge RMS 300 ps rising edge RMS 300 29ns falling edges 13 4 17 bit 102 4 usec 80 ps 7 80 ps 7 Maximum one time bin lt 0 1 LSB 3 0 3 6 0 70 10 70 MHz
20. ailing edge measurement enable pair leading and trailing edge measurement If this bit is set enable_leading and enable_trailing bits are masked enable force generation of rejected hit see section 2 3 enable trailer in read out data enable header in read out data enable serial read out otherwise parallel read out enable read out of relative time to trigger time tag enable search and read out of mask flags enable trigger matching enable read out of 11 occupancy for each event use for debugging enable of automatic rejection see section 2 6 enable all time counters to be reset on bunch count reset enable master reset on event reset enable channel buffer reset when a separator is inserted enable master reset from global reset of the encoded_control 23 enable detect enable errmark ovr enable errmark rejected enable mark rejected enable errmark enable trfull reject enable reject enable rofull reject 3 1 13 CSR12 enable error 8 0 enable sepa evrst enable sepa bcrst enable sepa readout 3 1 14 CSR13 14 enable channel 23 0 enable 11 buffer overflow detection enable error marking events with overflow enable error mark event if rejected seen during matching enable special marker word for rejected hits mark all events with error word if internal error exists enable event data rejection if trigger FIFO nearly full see section 2 8 enable event data rejection if L1 buffer n
21. been kept below the bin size of the TDC by balancing the delay paths of the clock and the channels In Fig 13 a hit signal is defined such that the time measurement equals zero coarse_time_offset 0 The delay from the rising edge of the clock where the bunch reset signal was asserted to the rising edge of the hit signal is for a typical chip 55ns two clock periods plus 5ns external clock L Fig 13 Definition of reference time measurement B Alignment between coarse time count and trigger time tag To perform an exact trigger matching the basic time measurement must be aligned with the positive trigger signal taking into account the actual latency of the trigger decision The effective trigger latency in number of clock cycles equals the difference between the coarse time offset and the 32 bunch count offset The exact relation ship is latency coarse time offset bunch count offset modulus 2 A simple example is given to illustrate this A coarse time offset of 100 Hex decimal 256 and a bunch count offset of 000 Hex gives an effective trigger latency of 100 Hex decimal 256 Normally it is preferable to have a coarse time offset of zero and in this case the trigger count offset must be chosen to 000 100 Hex modulus 2 FOO Hex C Alignment between trigger time tag and reject count offset The workings of the reject counter is very similar to the trigger time tag counter The d
22. dow is also specified in steps of clock cycles The maximum trigger latency which be accommodated by this scheme equals half the maximum coarse time count 2 2 2048 clock cycles 51 us The trigger matching function is capable of working across roll over in all its internal time counters For a paired measurement the trigger matching is performed on the leading edge of the input pulse The search for hits matching a trigger is performed within an extended search window to guarantee that all matching hits are found even when the hits have not been written into the L1 buffer in strict temporal order For normal applications it is sufficient to make the search window 8 larger than the match window The search window should be extended for applications with very high hit rates or in case paired measurements of wide pulses are performed a paired measurement is not written into the L1 buffer before both leading and trailing edge have been measured To prevent buffer overflow and to speed up the search time an automatic reject function can reject hits older than a specified limit when no triggers are waiting in the trigger FIFO and enable auto reject bit is set A separate reject counter runs with a programmable offset to detect hits to reject The trigger matching can optionally search a time window before the trigger for hits which may have masked hits in the match window if enable mask bit is set A channel having a hit within the specified
23. e data path of the chip to be capable of performing effective testing of registers and embedded memory structures Furthermore it is also possible to access the CSR registers from the JTAG port JTAG TAP Test Access Port state diagram is shown in Fig 11 26 Test Logic Reset 0 Run Test 1 Select 1 Select 11 lde DR Scan IR Scan 0 e 7 0 1 Capture DR 11 Capture IR 6 0 0 Shift DR A Shift IR P Exit1 IR 9 Pause IR b Exit2 IR 8 Update IR d y 0 1 Y Fig 11 JTAG TAP controller state diagram Numbers in each states shown are state variable of the TAP controller T B Exiti DR 1 1 Pause DR 3 Update DR 5 3 3 1 JTAG controller and instructions The JT AG instruction register is 4 bits long plus a parity bit 3 0 ins 3 0 JTAG instruction 4 parity 0 parity of JTAG instruction 27 Table 6 JTAG Instructions 3 3 2 Boundary scan registers All signal pins of the TDC are passed through JTAG boundary scan registers All JTAG test modes related to the boundary scan registers are supported EXTEST INTEST SAMPLE 28 Table 7 Boundary Scan Registers BSR ENCCONTP 0 23 HITM 0 23 BUNCHRSTP EVENTRSTP 74 SERIOUTP SERIOUTM STROBEP mpu oupi DIOEN CLKOUT EE REN 29 LVDS LVDS input LVDS input see Fig 12 see Fig 12 see Fig 12 see Fig 12
24. e sepa bcrst or enable sepa evrst These will make sure that hits and triggers from different event count or bunch count periods machine cycles never are mixed In this mode it is not possible to match hits across bunch count periods This separator can be readout if enable sepa readout bit is set This mechanism is conceptually shown in Fig 8 14 Data Out Trigger separator 4 24 read out FIFO maching Trigger FIFO AM LR E separator Bunch Count Reset or Event Count Reset L1 buffer Hit Time Fig 8 Conceptual view of the separator insertion and matching 2 8 Read out FIFO The read out FIFO is 64 words deep and its main function is to enable one event to be read out while another is being processed in the trigger matching If the read out FIFO runs full there are several options of how this will be handled Back propagate enable rofull 20 enable llfull reject 0 enable trfull reject 0 The trigger matching process will be blocked until new space is available in the read out FIFO When this occurs the L1 buffer and the trigger FIFO will be forced to buffer more data If this situation is maintained for extended periods the 1 buffer or the trigger FIFO will finally become full and the measurement is stopped Nearly full reject In this mode the trigger matching will be blocked if either the L1 buffer enable llfull reject 1 or the trigger FIFO is nearly full enable trfull reject 1 If this
25. early full see section 2 8 enable event data rejection when read out FIFO full see section 2 8 ERROR signal is asserted if corresponding enable error bit is set enable generate separator on event reset enable generate separator on bunch count reset enable read out of internal separators debugging enable individual channel inputs 24 3 2 Status registers Table 5 Bit assignment of the status registers all these registers are read only scere in sep s CSR16 rfifo rfifo control empty full parity ad 0 i D 0 9 Hec duce v N ll empty nearly over_ over write_address full recover flow 0i 0D i 0 0 23 122 21 20 19 12 CSRI8 tfifo_ i tfifo tfifo running empty i nearly i full read address full i 0 35 434 133 32 31 24 CSR19 coarse tfifo_ ine counter occupancy start address 0 0 0 0 47 46 44 43 36 CSR20 coarse_counter 12 1 0 59 48 CSR21 0 0 0 0 0 0 i rfifo occupancy 5 0 0 0 0 0 0 0 0 71 70 69 68 67 66 65 60 initial value at reset JTAG bit No 3 2 1 CSR16 error_flags 8 0 status of error monitoring see section 2 10 bit coarse error parity error in the coarse counter channel select error more than channel are selected 11 buffer parity err
26. et 0 71 60 95 84 107 96 CSR9 CSRIO CSRII CSRI2 CSR13 CSR14 strobe_select 1 0 119 118 117 116 enable ienable ienable_ enable auto_ lloccup i match mask reject readout a i 131 i 130 enable enable enable readout_speed 0 129 0 128 enable width select 0 0 115 113 i 112 tde_id 0 111 108 enable enable enable enable relativei serial i header i trailer 0 0i 127 i 126 i 125 i 124 enable enable enable enable enable enable enable _ rejected i pair i trailing leading 0 0 123 122 enable enable Em o 121 120 enable enable rofull trfull reject reject reject 0 0 0 143 i 142 i 141 enable ienable ienable sepa sepa sepa readout berst evrst 0 9o i 0 j 155 i 154 153 errmark 0 140 mark iermark i errmark rejected rejected detect o 0 0i 139 138 137 136 enable _ error 152 144 enable channel 11 0 FFF 167 156 enable channel 23 12 FFF 179 168 mreset iresetcb code sepa 0 0 135 i 134 i mreset_i setcount i evrst _berst 0i O 133 i 132 initial value at reset JTAG bit No 20 3 1 1 CSRO pll_multi 1 0 The frequency ration be
27. f the measurement The bunch structure of LHC is not compatible with the natural binary roll over of the 12 bit coarse time counter The bunch counter can therefore be reset separately by the bunch count reset signal and the counter can be programmed to roll over to Zero at a programmed value The programmed value of this roll over is also used in the trigger matching to match triggers and hits across LHC machine cycles coarse count offset 0 bunch count reset Load count roll 0 Coarse counter 80MHz Clock Clock cabe NH A p Hit PLL select Coarse Count Fig 3 Phase shifted coarse counters loaded at hit 2 3 Channel Buffer Each channel can store 4 measurements before being written into the common L1 buffer The channel buffer is implemented as a FIFO controlled by an asynchronous channel controller The channel controller can be programmed to digitize individual leading and or trailing edges of the hit signal Alternatively the channel controller can produce paired measurements consisting of one leading edge and the corresponding trailing edge If the channel buffer is full when a new hit arrives it will be ignored rejected but the information of the rejected hit is transferred with next valid hit If the enable rejected bit in CSR10 is set the information of the rejected hit is transferred as soon as the channel buffer is available For the hits s
28. fine time In case a paired measurement of leading and trailing edge has been performed the complete time measurement of the leading edge plus a 8 bit pulse width is written into the L1 buffer The 8 bit pulse width is extracted from the leading and trailing edge measurement taking into account the programmed roll over value The resolution of the width measurement is programmable In case the pulse width is larger than what can be represented with a 8 bit number the width will be forced to a value of Hex When several hits are waiting in the channel buffers an arbitration between pending requests is performed New hits are only allowed to enter into the active request queue when all pending requests in the queue have been serviced Arbitration between channels in the active request queue is done with a simple hardwired priority channel 0 highest priority channel 23 lowest priority The fact that new requests only are accepted in the active request queue when the queue is empty enables all channels to get fair access to the 1 buffer 2 5 L1 Buffer The L1 buffer is 256 hits deep and is written into like a circular buffer Reading from the buffer is random access such that the trigger matching can search for data belonging to the received triggers If the L1 buffer runs full the latest written hit will be marked with a special full flag When the buffer recovers from being full the first arriving hit will be marked with a full recover fla
29. g These flags are used by the following trigger matching to identify events which may have lost hits because of the buffer being full 2 6 Trigger Matching Trigger matching is performed as a time match between a trigger time tag and the time measurements them selves The trigger time tag is taken from the trigger FIFO and the time measurements are taken from the L1 buffer Hits matching the trigger are passed to the read out FIFO Optionally the trigger time tag can be subtracted from the measurements enable relative 1 such that all measurements read out are referenced to the time bunch crossing when the event of interest occurred 10 reject count offset reject lt lt bunch count offset matching window time search window mask window trigger time Fig 5 Trigger latency and trigger window related to hits on channels There are 3 time counters coarse time trigger time and reject time counters A match between the trigger and a hit is detected within a programmable time window Fig 5 if enable match is set The trigger is defined as the coarse time count bunch count ID when the event of interest occurred hits from this trigger time until the trigger time plus the matching window will be considered as matching the trigger The trigger matching being based on the coarse time means that the resolution of the trigger matching is one clock cycle 40MHz and that the trigger matching win
30. ifference between the course time counter offset and the reject counter offset is used to detect when an event has become older than a specified reject limit The rejection limit expression is coarse time offset reject count offset modulus 2 The rejection limit should be set equal to the trigger latency plus a small safety margin In case the extraction of masking hit flags are required the reject limit should be set larger than the trigger latency masking window safety margin For a trigger latency of 100 Hex same as in example in the section above a reject limit of 108 Hex can be considered a good choice no mask detection This transforms into a reject count offset of EF8 Hex when a coarse time offset of zero is used 4 1 Example of Offset Setting In the LHC experiments there are 3564 clock cycles 88 924 usec 24 9501 ns in a beam revolution Thus the count roll over csr8 should be set 3563 deb in hex For the trigger latency of 3 usec 120 clock bunch count offset should be set to 3564 120 3444 This is summarized in Table 9 Table 9 An example of register value setting Assumptions number of clock cycles per beam revolution CC 3564 cycles trigger latency TL 120 cycles 3 usec maximum drift time DT 32 cycles 800 ns emma T o wr pe SSCS At present design count roll over must be greater than 800 search window If the bunch count reset signal is applied in each
31. is required to correctly identify the event ID and the bunch ID of accepted events These signals can either be generated separately or be coded on a single serial line at 40 MHz 2 7 1 Encoded trigger and resets Four basic signals are encoded using three clock periods Table 1 The simple coding scheme is restricted to only distribute one command in each period of three clock periods A command is signaled with a start bit followed by two bits determining the command When using encoded trigger and resets an additional latency of three clock periods is introduced by the decoding compared to the use of the direct individual trigger and resets Selection between the encoded signals and the direct signals are schematically shown in Fig Table 1 Encoded signal bit pattern Meaning bit 210 Global reset 12 PLL CLKP clock gt SOMHz Clock CLKM gt reset 1 40 i gt 40 Clock JTAG controller reset CSR reset global_reset encoded signal ENCCONTP decoder enable_mreset_code enccont trigger esr11 3 bunch_count_reset globalLreset clock reset TRIGM BUNCHRSTP F BUNCHRSTM V ENCCONTM C gt trigger master_reset C gt bunch count reset gt event count reset Fig 6 Simplified diagram of the clock reset and trigger signals V enable_mreset_evrst esr11 1 EVENTRSTP EVENTRSTM enable direct
32. ite tet 30 3 3 4 Control YOgistet Sa 3 2 pee et treo deed eene dee Send Ee qoe toe ep tee 30 249 2 STATUS TERISTICS EMEN 30 3 3 6 css o o Dp aut london e oe oA ead 31 4 4 1 TIME ALIGNMENT BETWEEN HITS CLOCK AND TRIGGER MATCHING EXAMPLE OF OFFSET SETTING sese nen 0 Bugs and Future Changes 0 1 Bugs Following bugs are found in AMT 1 and will be fixed in AMT 2 Control Parity Error Control Parity Error error flags 7 bit is prepared to indicate whether SEU Single Event Upset is occured or not in the control registers When you set a value to the control register control parity error may occur in 50 probability This occurs only if the JTAG tck cycle is longer than two clock cycle 50ns In the case when you write the CSR register through CIO lines this error will occur if the CS chip Select signlal width is longer than two clock cycle Serial transmitter In some serial mode strobe signal is not stable See Table 4 0 2 Future Changes Following changes are planned in AMT 2 Reset Inputs This inputs are changed from LVDS signal to CMOS signal inputs pin 1 RESETM gt RESETB negative logic pin 2 RESETP gt not defined yet LVDS receiver Design of LVDS recever is changed to low power version 1 Introduction The ATLAS
33. onstant latency yes no trigger 13 signal The trigger time tag is generated from a counter with a programmable offset When a trigger is signaled the value of the bunch counter trigger time tag is loaded into the trigger FIFO The effective trigger latency using this scheme equals the difference between the coarse time offset and the bunch count offset bunch count offset event count offset count roll over bunch count event count reset reset 40MHz clock Event Count trigger Trigger FIFO o Fig 7 Generation of trigger data If the trigger FIFO runs full the trigger time tags of following events will be lost The trigger interface keeps track of how many triggers have been lost so the event synchronization in the trigger matching and the DAQ system is never lost enable trfull reject 2 1 For each event with a lost trigger time tag the trigger matching will generate an event with correct event id and a special error flag signaling that the whole event has been lost 2 7 6 Separators The TDC is capable of running continuously even when bunch count resets and event count resets are issued Matching of triggers and hits across bunch count resets different machine cycles are handled automatically if the correct roll over value have been programmed Alternatively it is possible to insert special separators in the trigger FIFO and the L1 buffer when a bunch count reset or an event count reset have been issued enabl
34. or trigger FIFO parity error trigger matching error state error readout FIFO parity error readout state error YANN gt WN gt control parity error JTAG instruction parity error control parity parity of control data see section 2 10 full 0 read out FIFO full rfifo empty 0 read out FIFO empty 25 3 2 2 write address 7 0 11 buffer write address 11 overflow L1 buffer overflow bit over recover L1 buffer overflow recover bit nearly L1 buffer nearly full bit empty L1 buffer empty bit 3 2 3 18 read address 7 0 L1 buffer read address running status of START signal tfifo full trigger FIFO full bit tfifo nearly full trigger FIFO nearly full bit trigger fifo empty trigger FIFO empty bit 3 2 4 5 19 start address L1 buffer start address tfiffo occupancy trigger FIFO occupancy number of word in trigger FIFO coarse counter Coarse counter bit 0 3 2 5 CSR20 coarse counter 12 1 Coarse counter bit 12 1 3 2 6 CSR21 rfifo_occupancy 5 0 Read out FIFO occupancy number of word in read out FIFO 3 3 JTAG Port JTAG Joint Test Action Group IEEE 1149 1 standard boundary scan is supported to be capable of performing extensive testing of TDC modules while located in the system Testing the functionality of the chip itself is also supported by the JTAG INTEST and BIST capability In addition special JT AG registers have been included in th
35. r offset 21 3 1 7 CSR6 bunch count offset 11 0 trigger time tag counter offset 3 1 8 CSR7 coarse time offset 11 0 coarse time counter offset 3 1 9 5 8 count roll over 11 0 gt counter roll over value 3 1 10 CSR9 1d 3 0 TDC identifier This ID is attached to the output data width select 2 0 Set pulse width resolution in pair measurement width output resolution max width full width 7 0 full width 8 1 full width 9 2 full width 11 4 full width 12 5 full width 13 6 full width 14 7 at 40 clock readout speed 1 0 0 40 Mbps 1 20 Mbps 2 10 Mbps 3 80 Mbps strobe select 1 0 0 gated DS strobe 1 continuous DS strobe 2 gated leading edge 3 continuous leading edge caution some of the transfer mode are unstable in present chip as show below 22 3 1 11 3 1 12 Table 4 Unstable serial modes CSRIO enable leading enable trailing enable pair enable rejected enable trailer enable header enable serial enable relative enable mask enable match enable readout enable auto reject CSRI1 enable setcount bcrst enable mreset evrst enable resetcb sepa enable mreset code __ 2 a bits unstable strobe 1 cycle ahead strobe 1 2 cycle ahead strobe 1 4 cycle ahead strobe none strobe unstable strobe unstable strobe unstable enable leading edge measurement enable tr
36. robe select 3 Fig 9 Different strobe types 2 9 3 Packet format Data read out of the TDC is contained in 32 bits data packets For the parallel read out mode one complete packet word can be read out in each clock cycle In the serial read out mode a packet is sent out bit by bit The first four bits of a packet are used to define the type of data packet 16 The following 4 bits are used to identify the ID of the TDC chip programmable generating the data Only 7 out of the possible 16 packet types are defined for TDC data The remaining 9 packet types are available for data packets added by higher levels of the DAQ system TDC header Event header from TDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15114 13 12 1110 9 8 7 6 5 4 3 2 1 0 TDC Programmed ID of TDC Event ID Event ID from event counter Bunch ID Bunch ID of trigger trigger time tag TDC trailer Event trailer from TDC 31 30 29 28 27 2625524 23 22 21 20 19 18 17 16 15 14 13 12 11 10 87 65 43 2 1 Jo 1100 TDC ID Word Count Word count Number of words from TDC incl headers and trailers Mask flags Channel flags for channels having hits with in mask window 27 26 18 11e 14 Mask Ths Channels flagged as having hits with in mask window Single measurement Single edge time measurement 31 30 29 2812726254 23 22 21 20 19 18 v7
37. status of the TDC while it is running or after a run See section 3 2 for register details 30 3 3 6 Core registers The JT AG core register scan path is used to perform extended testing of the TDC chip This scan path gives direct access to the interface between the channel buffers and first level buffer logic It is used in connection with the test mode bits and is only intended for verification and production tests of the TDC chip Table 8 Bit assignment of the core registers main R meswnporeggermaeimgsae monitoring of ative ager ta reso R monitoring of it wigermadun Exe see Appendix A for internal format matching state 10 0 state waiting 00000000001 state write event header 00000000010 state write occupancy 00000000100 state active 00000001000 state write mask flags 00000010000 state write error 00000100000 state write event trailer 00001000000 state generating lost event header 00010000000 state generating lost event trailer 00100000000 state waiting for separator 01000000000 state write separator 10000000000 4 Time alignment between hits clock and trigger matching The TDC contains many programmable setups which have effects on the performed time measurements and their trigger matching The main time reference of the TDC is the clock and the bunch reset which defines the TO time The time alignment can
38. tored in the channel buffers to be written into the clock synchronous L1 buffer a synchronization of the status signals from the channel buffers is performed Double synchronizers are used to prevent any metastable state to propagate to the rest of the chip running synchronously at 40 MHz When paired measurements of a leading and a trailing edge is performed the two measurements are taken off the channel buffer as one combined measurement 2 4 Encoder When a hit has been detected on a channel the corresponding channel buffer is selected the time measurement done with the ring oscillator is encoded into binary form vernier time the correct coarse count value is selected and the complete time measurement is written into the L1 buffer together with a channel identifier Although the ring oscillator and the coarse counter runs at 80 MHz base LHC clock is 40 and bunch number is counted at 40 MHz Most of logics in are designed to run at 40 MHz To shift from 80 MHz to 40MHz regime we would like to define different name to measured time We call the upper 12 bit of the coarse counter as a coarse time and the LSB of the coarse counter plus the vernier time as a fine time Thus the coarse time will be equivalent to the bunch count Coarse Counter 13 bit Ring Oscillator 16 bit Vernier Time 4 bit Coarse Time Fine Time 12 bit 5 bit Fig 4 Definition of coarse time and
39. tween the external clock and the internal ring oscillator frequency is determined by these bits as shown below clkout_mode 1 0 CLKOUT pin mode 0 Start Sync Synchronized output of the START signal 1 40MHz PLL clock 2 output This is the system clock used in most of logics 2 80 MHz clk PLL clock outpuut 3 Coarse Counter Carry Carry outout of the Coarse Counter This can be used to extend the time range disable ringosc Stop the oscillation of the ring oscillator and disable charge pump circuit of the PLL enable direct enable direct input pins 0 trigger reset signals are came from encoded input encontp enccontm trigger reset signals are came from direct input pins trigp trigm bunchrstp bunchrstm eventrstp eventrstm test invert automatic inversion of test pattern in test mode test mode enable test mode enable errrst bcrevr enable error reset when bunch count reset or event count reset is came disable encode disable fine time encoder and output 111 error reset clear error bits in CSR16 8 0 global reset Global reset of the TDC 3 1 2 CSRI mask window 11 0 mask window in number of clock cycles 3 1 3 CSR2 search window 11 0 search window in number of clock cycles 3 1 4 CSR3 match window 11 0 matching window in number of clock cycles 3 1 5 CSR4 reject count offset 11 0 rejection counter offset 3 1 6 CSR5 event count offset 11 0 event numbe
40. ve 5 0 Separator 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 Buffer Occupancy 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 Ea 76543210 R Readout FIFO full gt 36 Trigger FIFO 232221201918171615141312 11109876543210 References 1 AMT 0 manual http pcvlsi5 cern ch 80 MicDig amt htm 2 AMT TEG http atlas kek jp araiy amtteg 3 Y Arai and T Ohsugi An Idea of Deadtimeless Readout System by Using Time Memory Cell Proceedings of the Summer Study on the Physics of the Superconductiong Supercollider Snowmass 1986 p 455 457 37
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