USER MANUAL
Contents
1. Slot1_ModuleBusy 4p F 3 S a gt OO Timeot A Bes sus Timed Out f Gi Wait For Stop Button and send the Stop Command Ess This Loop reads the Modules Busy Status This ModuleBusy FIFO Read Node has to be placed in your Block Diagram and it has to be read at least one time in Order to prevent Compiler Errors because of unused FIFOs If you use multiple Modules the ModuleBusy FIFO Nodes for every used Driver YI have to be placed on your Block Diagram and each one has to be read at least one time 4 3 EXAMPLE 3 CONTINUOUS POSITION MEASUREMENT This example configures the RDK9314 driver for continuous measurement A software loop cyclically reads the position data from the module When the Stop button is clicked the CMD_ STOP instruction is sent to the module which terminates the program Furthermore another parallel software loop reads the modules busy state as already explained in the examples before wait For Stop Button and send the Stop Command to Stop the Driver VI p m amna i Slot1_Commandin dir 4 E ecMD_STOP Timed Out The Driver YI for module slot 1 runs parallel to the calling application Data between driver and application is tranfered via FIFO Buffers Theres a CommandIn FIFO that transferes commands to the RDK Module and a CommandIn FIFO that provides data from the Module PARALLEL STARTING OF THE SET RDK 9314 FPGA DRIVER FOR SLOT 1 FPGA DEN In2. a Jib Sloti_CommandOut de Sloti_ SET_RDK_9314 Trigger D101 i i Jib Slot_ModuleBusy ie Slotl_SET_RDK_9314 5P1 RdyBsy DIO2 Lu al Slott_SET_RDK_9314_FPG amp _DRIVER vi bg Slot1_SET_RDK_9314 SPI Conv DIO3 Sotz amp Slot1_SET_RDK_9314 SPI Func DIO4 BB Slots beg Slotl_SET_RDK_9314 SPI C5 DIOS Ge Slota gh Sllotl_SET_RDK_9314 5PT MISO DIO6 i a 40 MHz Onboard Clack ii Slotl_SET_RDK_9314 SPI MOSI DIO 2 Durnmy Chassis Connector 1 kB 40 MHz Onboard Clock b fef Slot1_seT_RDk_9314 Slot 1 SET 9314 RDK G Em Chassis1 Connector 1 m E Slot2_SET_RDK_9314 Slot 2 SET 9314 RDK iM Slot_SET_RDK_9314 Slot 1 SET 9314 RDK i Slot3_SET_RDk_9314 Slot 3 SET 9314 RDK Ey Dependencies Wr Slot4_SET_RDK_9314 Slot 4 SET 9314 RDK 2 Ta Build Specifications mil FPGA APPLICATION EXAMPLE Slot 1 i BF Dependencies E ur Dependencies F 4 Build Specifications All relevant driver files are now added to the new project File Edit wiew Project Operate Tools Window Help lesa xX agt g il Project Untitled Project 1 E My Computer 8 FPGA Target RICO PCI 7833R 6 Sloti_SET_RDK_9314 i ge Slotl_SET_RDK_9314 ID Select Slot1 SET ROK 9314 SPI Clk Slot1 SET ROK 9314 Ovrsmpclk DICO Slot SET ROK 9314 Trigger DIO1 Slati_ SET ROK 9314 SPIRdvBsy DIG Sloti SET ROK 9314 5P1 Cony DIOS Slot SET ROK 9314 SPI Func D104 Slot1 SET ROK 9314 S5PI C5 DIOS Slot1 SET ROK 9314 5P1I
3. Ge u Dummy cRIO Chassis cRIO 9104 i Dummy FPGA Target RIOO cRIO 9104 Ienesuy RDK 9314 Slot 1 p Slot 2 eg Slot 3 Slot 4 eg Slots 9 Slots 8 Slot Slots E D Slot1_SET_RDK_9314 Slot 1 SET 9314 RDK pe T Slot2_SET_RDK_9314 Slot 2 SET 9314 RDK i i Slot3_SET_RDK_9314 Slot 3 SET 9314 RDK be oy Slot _SET_RDK_9314 Slot 4 SET 9314 RDK I i SlotS_SET_RDK_9314 Slot 5 SET 9314 RDK s i Slot6_SET_RDK_9314 Slot 6 SET 9314 RDK i i Slot _SET_RDK_9314 Slot 7 SET 9314 RDK be I Slot8_SET_RDK_9314 Slot 8 SET 9314 RDK i 9 40 MHz Onboard Clock s mi FPGA APPLICATION EXAMPLE Slot 1 wi a Dependencies Build Specifications j BE Dependencies ki es Build Specifications To add a new FPGA Target use the mouse and click right button onto the computer symbol and select New gt Targets and Devices Page 11 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 Project Explorer Untitled Project 1 File Edit View Project Operate Tools Window Help Sa XO X ee Fall Items Files I virtual Folder Control Library Variable Class Control Arrange by gt Expand All Collapse All NI DAGme Task NI D40m Channel NI DAOmr Scale Help Properties Targets and Devices Select an existing FPGA Target or define a new device Add Targets and Devices on My Computer Add Ta
4. FPGA R Series Expansion Chassis e FPGA APPLICATION EXAMPLE MULTIPLE RT cRIO 8 Slots vi This is an application example which demonstrates the parallel operation of up to eight RDK9314 modules in a cRIO Realtime Chassis The following chapters explain the implementation of the driver files into a new LabVIEW project Example VI FPGA APPLICATION EXAMPLE Slot 1 vi is applicable for both a PCI FPGA Target with R Series Expansion Chassis and the cRIO Realtime Platform Page 7 of 35 SETI9010MANO0001 USER MANUAL E SC Issue 01 RDK9314 3 2 1 CREATE NEW PROJECTS By USE OF THE EXAMPLE PROJECT The example project helps to create a new project To create a new project simply transfer the required driver modules via drag and drop into the new project Project Explorer RDK 9314 lvproj File Edit View Project Operate Tools Window Help gt Sa amp 0 X mr ee me Items Files fea Project ROK 9314 lvproj My Computer H TypeDefs 2 Dummy RIOO PCI 7833R i GE ROK 9314 ep Soti Relates to an internal NI PCI u S oe FPGA Card in combination i i ge Slot gt i be Fa 40 MHz Onboard Clock with a 4 Slot R Series 2 amp Dummy Chassis Connector 1 Expansion Chassis b Ed DM Slott_SeT_RDK_9314 Slot 1 SET 9314 RDK jo PP Slot2_SET_RDK_9314 Slot 2 SET 9314 RDK i Slok3_ SET RDK_ 9314 Slot 3 SET 9314 RDK ban T Slot4_SET_ROK_9314 Slot 4 SET 9314 RDK il FPGA APPLICATION EXAMPLE
5. MISO D108 DE Slot1_SET_ROK_9314SPI MOSI DIOF wo i Jik Slotti Commandin a Jik Sloti_ Command Out L Jik Sloti_ModuleBusy PL ml Slot1_SET_RDK_9314_FPGA_DRIVER vi Fa 40 MHz Onboard Clack Be Chassis Connector 1 ii Slot1_sET_RDK_9314 Slot 1 SET 9314 RDK gt Ea Dependencies a Build Specifications L u Dependencies Build Specifications ope EPP EEE Page 15 of 35 SET9010MANO0001 USER MANUAL L GE j Issue 01 RDK9314 3 2 2 6 ADDING THE FPGA APPLICATION EXAMPLE A small example application on the CD ROM demonstrates the driver usage This example explains how the driver is used for an RDK9314 module installation on slot 1 Use the drag and drop function to copy the example into the new project structure Please note that the STRG key must be pressed to copy the elements rather than moving them Project Explorer RDK 9314 lvproj BAA Project Explorer Untitled Project 1 Sele File Edit View Project Operate Tools Window Help File Edit wiew Project Operate Tools Window Help BS58 x nx Ra eal wef Sgal x ax RI ar Kall we Items Files Items Files E b Project ROK 9314 lvproj E My Computer 9 TypeDefs amp 13 Dummy RIOO PCI 7833R FPGA APPLICATION EXAMPLE ii 9 RDK9314 iii Sot G Slot2 lg FPGA APPLICATION EXAMPL 5 Slot3 g fe Project TEST PROJECT Ivproj W My Computer FPGA Target RIOD Feel FPGA APPLICATION EXAMPLE Slot 1 vi SEIRSRIE
6. Onboard Clock z mi FPGA APPLICATION EXAMPLE Slot 1 Wi E Chassis Connector 1 d Dependencies D Slot1_SET_RDK_9314 Slot 1 SET 9314 RDK E Build Specifications a Dependencies a Dependencies fa e Build Specifications i Build Specifications oS Dependencies iB Dummy CompactRIO 192 168 2 63 Real Time features not available be 4 Build Specifications Page 14 of 35 SET9010MAN0001 USER MANUAL Issue 01 RDK9314 3 2 2 5 ADDING THE DRIVER SOFTWARE COMPONENTS Every module of the example projects uses a separate folder which includes the driver VI and three different FIFO buffers These sub folders must also be copied into the new project for every new module import To do this drag the applicable sub folder into the new project structure while the STRG key is pressed Project Explorer RDK 9314 lvproj ES F Project Explorer Untitled Project 1 Siz fx Fie Edit View Project Operate Tools Window Help File Edit View Project Operate Tools Window Help Ba Bx Pi bea SEEX BR BA T i Items Files Items Files i Tl Project RDK 9314 lvproj E ea Project Untitled Project 1 9 My Computer W My Computer H J Typebefs g p FPGA Target RIOD PCI 7833R4 Je Dummy RICO PCI 7833R g Em 2 G Slotl_ SET RDK_ 9314 Poi GE RDK 9314 k amp Slotl_SET_RDK_9314 ID Select i bp er oe Sloti_SET_RDK_9314 5PLCk i ib Slot1_Commandin ie a Slotl_SET_RDK_9314 Ovrsmpclk DIO vem FE
7. defined in TypeDef RDKCMD ctl COMMAND VALUE U8 TARGET CMD_NOP 0 RDK9314 Controller This instruction sends a NOP command to the RDK9314 controller and is used internally for the driver communication to cope with the SPI communication principles COMMAND VALUE U8 TARGET CMD_RD_POS 1 RDK9314 Controller This instruction DATA O reads the actual position of the Resolver The read value 16 bit is raw data and maps the Resolver angle from 0 to 360 to the integer data range of O to 65535 Note that this data range is used for both the 14 bit and the 16 bit mode To calculate the Resolver angle in DEG use the following equation 360 Pppg DATA __ 65536 COMMAND VALUE U8 TARGET CMD_RD_AMP 3 RDK9314 Controller This instruction DATA 0 reads back the commanded excitation voltage level The voltage level data format is 16 bit integer with 1 Isb equal to 1 MVans COMMAND VALUE U8 TARGET CMD_RD_FRQ 4 RDK9314 Controller This instruction DATA 0 reads back the commanded excitation voltage frequency The frequency data format is 16 bit integer with 1 Isb equal to 1 Hz COMMAND VALUE U8 TARGET CMD_RD_RAT 5 RDK9314 Controller This instruction reads back the adjusted transfer ratio The data format is 16 bit integer and mapped as follows O for Ratio 0 0 1000 for Ratio 1 0 Page 25 of 35 SET9010MANO0001 USER MANUAL L SEC Issue 01 RDK9314 COMMAND VALUE U8 TARGET CMD_R
8. in parallel outside the rest of the program code Refer to the example on the CD ROM Calling LabVIEW Application Driver Call Module 1 gt Sloti_Commandin 4ib gt Sloti_CommandOut lF gt Sloti_ModuleBusy Ib Timed Out Timed Out Timed Out Send commands and data Receive data and command Busy Status of the module RSET FPGA OFW RDK 9314 LabVIEW Driver VI Slot 1 Service Call of a Single Driver Vis Example Module 1 Slot 1 Page 23 of 35 1 l SET9010MAN0001 USER MANUAL S Issue 01 RDK9314 EMBEDDING THE DRIVER FOR MORE THAN ONE MODULE To operate multiple modules the specific driver Vl s are all operated strictly parallel to the other program code All communication between the application program and the driver Vl s takes place via the module specific FIFO buffers Calling LabVIEW Application Driver Call Module 1 Teed OF Receive data and command Busy Status of the nr Driver Call Module 2 ROK 9314 LabVIEW Oriver Vi Slot 1 Module 1 Slot 1 Teed Out Receive data and command Busy Sta module awe ROK 9314 a Driver Vi Slot 2 Module 2 heed Camere Slot 2 gt Re Receive data command Busy Satus of the module Tun ROK 9314 MM VI Stor N Module N Slot N Service Call for Multiple Driver VI s Page 24 of 35 SET9010MANO0001 USER MANUAL ic SC Issue 01 RDK9314 3 5 2 COMMANDS All module commands are
9. into the new project Note that the STRG key must be pressed during drag and drop to copy the element Otherwise the element will be removed from the example project This operation automatically installs the I O channels of the module within a new folder as shown below gt Project Explorer RDK 9314 lvproj al Project Explorer Untitled Project 1 File Edit View Project Operate Tools Window Help File Edit View Project Operate Tools Window Help Jpoea xUOxX eR R False peal xbox era Falls we g lise Project Untitled Project 1 E My Computer BE FPGA Target RIOD PCI 7833R Slotl_SET_RDk_9314 b Project RDK 9314 lyproj I 3 My Computer 8 9 Typebefs 4 Dummy RIOO PCI 7833R a a ROK 9314 Slotl_SET_RDK_9314 ID Select E LJ Slott rg Slotl_SET_RDK_9314 SPI Clk E H J Slotz amp Slotl_SET_RDK_9314 OvrSmpClk DIOO E CJ Slots ie Slot _SET_RDK_9314 Trigger D101 i Slate i ge Slotl_SET_RDK_9314SPI RdyBsy DIO2 40 MHz Onboard Clock i h Slotl_SET_RDK_9314 5PI Conv DIO3 g Dummy Chassis Connector 1 a EN SIot1_SET_RDEK_9314 5PI Func DIO4 E foot ET ROK 9314 Slot 1 SET 9314 RDK f pe gh Slotl_SET_RDK_9314 SPI CS DIOS Slot _SET_RDK_9314 Slot 2 SET 9314 ROK ii ke gh Slotl_SET_RDK_9314 SPI MISO DIO6 i Slob3_SET_RDK_9314 Slot 3 SET 9314 RDK en Sloti SET RDK_9314 5PI MOSI DIO ee QU Sist4_SET_RDK_3314 Slot 4 SET 9314 RDK _ 40 MHz
10. is useful to copy ratio data from other modules Page 26 of 35 SET9010MANO0001 USER MANUAL L SC Issue 01 RDK9314 The data format is 16 bit integer and mapped as follows O for Ratio 0 0 1000 for Ratio 1 0 COMMAND VALUE U8 TARGET CMD_CAL_EXC 12 RDK9314 Controller This instruction calibrates the excitation voltage level To calibrate the output voltage level refer to paragraph 5 1 COMMAND VALUE U8 TARGET CMD_AUTO_CAL 13 RDK9314 Controller This instruction DATA 0 initializes an automatic calibration procedure for the modules input channels Refer to paragraph 5 more details COMMAND VALUE U8 TARGET CMD_AUTO_RAT 14 RDK9314 Controller This instruction DATA O initializes a procedure which adjusts the RDK3914 to the transfer ratio of the connected Resolver Note that this instruction must be processed when the Resolver type is changed or a Resolver is connected to the module the first time COMMAND VALUE U8 TARGET CMD_IDLE_OPERATION 15 FPGA Driver VI The driver VI s offer a specific operational mode which sends instructions to the RDK3914 in a cyclical manner This for instance is helpful to monitor a Resolver position permanently In this case the position data is permanently buffered in the CommandOut FIFO Thus the sampling speed increases as no polling mechanism is required any more In this automatic mode the module cyclically processes the idle function which is actually not idl
11. r h Nee 2 a FIFO DATA ee D a U32 FPGA DEN Slot N Slot N Slot N Data U16 gt U16 Commandin FIFO Driver VI RDK Module e COMMAND U8 This is the command to the RDK9314 See paragraph 3 5 2 for the command list e DaTA U16 Data format is U16 See paragraph 3 5 2 for more details treten UERR LHF ga At T Page 21 of 35 SET9010MANO0001 USER MANUAL E GE Issue 01 RDK9314 RECEIVING DATA FROM THE RDK9314 MODULE Receiving data from the module driver are buffered in the applicable CommandOut FIFO The data format is U32 Integer 4 Byte co 0 DATA 3 DeD En IE i N error code U32 U8 Slot N Slot N Slot N RDK Module _Driver VI CommandOut FIFO U16 gt Data U16 e COMMAND U8 Echoes the last received command with one exception the NOP command will not be echoed See also paragraph 3 5 2 for more details e ERROR U8 Includes the error code which is generated from the module See also paragraph 3 5 2 for more details e DAatA U16 The format ofthe received data is U16 See also paragraph 3 5 2 for more details Stott CommandQut Alb Page 22 of 35 SETI9010MANO0001 USER MANUAL E SC Issue 01 RDK9314 3 5 1 3 EMBEDDING AND CALLING THE RDK9314 FPGA DRIVER EMBEDDING THE DRIVER FOR ONE SINGLE MODULE The following drawing illustrates the RDK9314 driver call one single module out of the FPGA application environment Note that the FPGA driver runs
12. to be placed on your Block Diagram and each one has to be read at least one time 4 2 EXAMPLE 2 IMANUALLY TRIGGERED POSITION MEASUREMENT INDIRECT MODE This example applies a Read Position button which triggers the CMD_RD_POS instruction The Stop button sends the instruction CMD_STOP to the driver and terminates the program A parallel program loop extracts the position data from the FIFO and copies the data to the visualization element Additionally a second parallel program loop checks the modules busy state This is compulsory because every FIFO which is imported from the driver VI must be read at least one time Page 30 of 35 SET9010MANO0001 USER MANUAL L oc Issue 01 RDK9314 The Driver VI for module slot 1 runs parallel to the calling application Data between driver and application is tranfered via FIFO Buffers This Loop reads the Position of the Resolver if theres one in the FIFO Buffer Theres a CommandIn FIFO that transferes commands to the RDK Module and a CommandIn FIFO that provides data from the Module PARALLEL STARTING OF THE SET RDK 9314 FPGA DRIVER FOR SLOT 1 Slot1_Commandout 4ib f a ee ion Command F eo TY Element 14 ERRE gt Timeout E i DATA Pe men ou HF Wait for Read Button and send the ReadPosit Read Position f Crea Timed Out 3 Reset the Stop Button This Loop will be stopped if the Stop Button is pressed Read the ModuleBusy Status rar
13. 18 3 3 Connecting The RESOIVET en nannten eier 20 3 4 Running The Application sessesesesecssssesecececscsesecececeesesesececscsesecececscsesecececsesesecececsesesesececseseseseceesese 20 3 5 Operating DECAS e nee E 21 351 DriverCall AnG Data Transter aii Ea 21 35 L1 FIFO Data Transter i E E E a a E E E 21 39 2 Data Frame Setup ie a E Ea EEn ENE been EES EnA 21 3 5 1 3 Embedding And Calling The RDK9314 FPGA Driver sccsccsccsccsccsccsccsccsccscescescecceccecceccecceccnscnces 23 352 COMINGS sara O E E OAE 25 3 6 Module Identification Under LabVIEW u 29 3 7 Savine TAE SC CUD o a E E EE A A EE N E E N NG 29 3 8 PUTO AUIO err A E T 29 4 Sortware Development u a N N 30 4 1 Example 1 Manually Triggered Position Measurement Direct Mode ssesesessessssesecssscsecsescseesee 30 Page 2 of 35 SET9010MANO0001 USER MANUAL Issue 01 4 2 4 3 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 1 6 2 RDK9314 Example 2 Manually Triggered Position Measurement Indirect Mode e 2ers22200220022000200 30 Example 3 Continuous Position Measurement csccsccsccsccsccsccnccnccsccsccscescescesceccecceccecceccsccnccnees 31 technical SDECITICACION VORRRARSNPRARRERNEREEERENEREUEENER ER EENUREEREEEUEEEEEEEEEEEENEEUEEEEREPEEERSEREEEEEEUEUEEEENEREHEREEURTEUERSERCER 32 ne 1 CL ARRRERRREPRDREREOPENEEEEEEEUREPETFEUEEFIUEEUREFIUEETUERLUEBTEEFUEEETEEEOTEEEEREUTEEUEELUEREIERUERFEIEEESEEEBEFTUEEEETFTEERURUFETEEUR
14. 314 3 3 CONNECTING THE RESOLVER To make the RDK9314 ready for use plug the module into the correct slot of the cRIO Chassis Make sure to select the correct slot according to the LabVIEW project definition Then connect the modules external power supply 18Vpc 36Vpc as shown below Do not turn on power before the Resolver connection is accomplished Connect the Resolver interface as shown below see also paragraph Fehler Verweisquelle konnte nicht gefunden werden When all connection is complete the external power supply can be switched on Note that the RDK9314 module will not be detected from the chassis before the modules external power supply is switched on Resolver RDK9314 18V 36V Power Supply 3 4 RUNNING THE APPLICATION Make sure that v Application compiling process is complete The module is plugged into the correct slot according to the application The Resolver and the external supply is connected The external power supply is switched on NN SEN The cRIO Chassis supply is switched on The LabVIEW VI can now be started by clicking the Run button Use parameters Amplitude mV and Frequency Hz to adjust the excitation signal to the correct level For a precise demodulation process the RDK9314 must be adapted to the signal transfer ratio of the Resolver This is accomplished by executing the function Auto Ratio which automatically adjusts the RDK9314 module to the Resolver transfer ratio Note tha
15. 34 of 35 SETI9010MANO0001 USER MANUAL Issue 01 RDK9314 1 MODULE MAINTENANCE No maintenance is required for the RDK9314 module 8 SERVICE ADDRESS For technical support contact the SET service address SET GmbH August Braun Str 1 88239 Wangen Allg u Germany Tel 49 0 7522 91687 600 Fax 49 0 7522 91687 899 e Mail support crio smart e tech de Page 35 of 35
16. A7_FPGAAPPL 31_pc98wy7P 0 25 06 2009 10 05 55 Client Name Status Last Update Time localhost Compiling YHDL 25 06 2009 10 15 45 Details Sg Le I Slee re ee Optimizing unit lt arb_rw_1EEA4D888_0965 gt Optimizing unit lt arb_rw_1EEAESFO_0966 gt Optimizing unit lt arb_rw_1EEAB338_0967 gt Optimizing unit lt arb_rw_1EEA4F40_0968 gt Optimizing unit lt arb_rw_1EE42880_0969 gt Optimizing unit lt arb_rw_1EEAC6S0_0963 gt Server Status Compiling Compile List Stop Compile Stop Server The following window is shown when the compiling process is complete Successful Compile Report Summary Advanced Status Compilation successful Compilation Summary Logic Utilization Humber of Slice Flip Flops 3 667 out of 258 672 Number of 4 input LUTs 4 706 out of 25 672 Device Utilization Summary Humber of BUFGMUXs 2 out of 16 12 Humber of LOCed BUFGMUHs 1 out of 2 SOs Humber of External IOBs 116 out of 454 2 des Humber of LOCed IOHs 116 out of 116 100 Humber of MULT18 18s 1 out of 96 1 Humber of RAHB16s 3 out of 36 I Humber of SLICEs 3316 out of 14336 234 Clock Rates Requested rates are adjusted for jitter and accuracy Do not show this message in the Future Note The same principle applies for the NI RealTime CompactRIO platform An example on the CD ROM illustrates this application Page 19 of 35 SET9010MANO0001 USER MANUAL E m SC Issue 01 RDK9
17. ATION EXAMPLE for Slot 1 FPGA APPLICATION EXAMPLE Slo Front Panel on TEST PROJECT lyproj FPGA Target File Edit View Project Operate Tools Window Help SET SET RDK 9314 Resolver FPGA Sample Application RDK 9314 Resolver Position Cycle Speed d 150000 Hz 360 300 250 5 200 150 T 100 I I I I I I I I I 150 200 250 300 350 400 450 500 550 600 Time Step 1 l l 1 l 1 650 700 750 800 850 300 950 Calibration Settings Commands DEBUG ExcitationCalData Amplitude CyclicOperation ErrorCount Inits Done 3390 2000 H Position jo 0 ReadCounter AUTO CALIBRATION Frequency reaso acvae Last Error Code occured Jo Raw Position Value 0 Last command sent o CMD_RD_POS SinVoltage rm TE Ratio Resolver Position Last Error Command Last command received READ 0 mY J 500 joe jo CMD_RD_POS ProgramControl CosVoltage en jr ModuleBusy j rror Lode boo mw AUTO RATIO a ee Stop Program TEST PROJECT lvproj FPGA4 Target lt The compilation process starts now and may take up to 25 minutes processing time Note that the compilation time increases with the number of modules in the application because every module requires a separate driver VI and a separate FIFO buffers Page 18 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 LabVIEW FPGA Compile Server 8 6 0 Compile Status Server Service ID Client Service ID Start Time 8 MYPROJECT 10_FPGATarg
18. D_SIN_VOL 6 RDK9314 Controller This instruction DATA 0 reads the voltage of the sine input channel The voltage data format is 16 bit integer with 1 Isb equal to 1 MVays Note that for calculating the U n Vrms voltage requires a processing time of 25us this operation allows a maximum sampling rate of 40kHz COMMAND VALUE U8 TARGET CMD_RD_COS_ VOL 7 RDK9314 Controller This instruction DATA 0 reads the voltage of the cosine input channel The voltage data format is 16 bit integer with 1 Isb equal to 1 MVams Note that for calculating the U os Vrms voltage requires a processing time of 25us this operation allows a maximum sampling rate of 40kHz COMMAND VALUE U8 TARGET CMD_WR_RES_ MODE 8 RDK9314 Controller This instruction adjusts the angular resolution of the RDK9314 module to 12 14 or 16 Bit DATA 0 gt High Resolution 16 Bit DATA 1 gt Normal Resolution 14 Bit DATA 2 gt Low Resolution 12 Bit COMMAND VALUE U8 TARGET CMD_WR_AMP 9 RDK9314 Controller This instruction adjusts the modules excitation voltage The voltage data format is 16 bit integer with 1 Isb equal to 1 mVrns COMMAND VALUE U8 TARGET CMD_WR_FRQ 10 RDK9314 Controller This instruction adjusts the modules excitation frequency The frequency data format is 16 bit integer with 1 Isb equal to 1 Hz COMMAND VALUE U8 TARGET CMD_WR_RAT 11 RDK9314 Controller This instruction manually adjusts the Resolver transfer ratio which
19. ERTUEROR 32 External Power SUBDIV nenne een erh 32 EN Ci AUN OUDUN une 32 SINUS And Cosinus Signal INpuUtS sesesessssesececscsssesecsececscsesesececsssesesececscsesesececeesesesececscsesesececscseseseceee 32 POSON PEO CSS SUNG ee E EE 33 Environmental Con ltionsa u isinen unina saine inan anin aiaa i ERa n inaona ieira 33 Connector PnoUt sessie Ea a 33 Module CIND ATION aer E E E 34 Calibration Of The Excitation Voltage AMplitude ccsscssccsccssccscceccesccscceccesccscceccesccscceccsccnccesees 34 Calibration Of The Input Channels en ee 34 Mod le Maintenance nee A 35 Service Addresse 35 Page 3 of 35 SET9010MANO0001 USER MANUAL E SC Issue 01 RDK9314 1 IMPORTANT INSTRUCTIONS Please read all instructions carefully before the RDK9314 is installed into a cRIO chassis or connected to other equipment 1 1 INITIAL INSPECTION Check that the shipment is complete and note whether any damage has occurred during transport If the contents are incomplete or there is damage file a claim with the carrier immediately and notify the SET GmbH service contact to facilitate the repair or replacement of the module The address is listed in the back of the manual The following parts should be included in the shipment v RDK9314 module v CD ROM with driver software and application examples v User manual 1 2 SAFETY INSTRUCTIONS 1 2 1 MODULE FAILURE Do not install the RDK9314 module into a cRIO chassis when the module
20. ET_RDK_9314 Slot1_SET_RDK_9314 ID Select Slot1_SET_RDK_9314 SPI Clk amp Slot1_SET_RDK_9314 OvrSmpCik DIO0 Sloti_SET_RDK_9314 Trigger DIO1 fF Slot1_SET_RDK_9314 SPI RdyBsy DIO2 3 Slot1_SET_RDK_9314 SPI Conv DIO3 qh Slot1_SET_RDK_9314 5PI Func DIO4 ii Le te Slot1_SET_RDK_9314 SPI CS DIOS E a un Bi 40 MHz Onboard Clock k FPGA APPLICATION EXAMPLE SI aA APPLICATION ESAMPLE gt 10 E Dummy Chassis Connector 1 bon jh Slot1_SET_RDK_9314 Slot 1 SET 9314 RDK W Slot2_SET_RDK_9314 Slot 2 SET 9314 RDK i I Sloti_SET_RDK_9314 SPI MISO DIO6 gt Siot3_SET_RDK_9314 Slot 3 RETTEN gh Slotl_SET_RDK_9314 SPI MOSI D107 fa Slot4_SET_RDK_9314 Slot 4 SET 9314 RDK iS Slott R FPGA APPLICATION EXAMPLE Slot 1 vi be qi Slotl_Commandin 23 Dependencies i edl Slot1_Commandout ri Build Specifications fe Alk Slot1_ModuleBusy P Dependencies fag Slot1_SET_RDK_9314_FPGA_DRIVER vi ie Gee Build Specifications j 9 40 MHz Onboard Clock Page 16 of 35 SET9010MANO0001 Issue 01 USER MANUAL RDK9314 SET The copied example application can now be found in the new project structure as shown below Project Explorer Untitled Project 1 File Edit aSal xBox el R Falle we View Project Operate Tools Window Help Items Files I lise Project TEST PROJECT vpraj 9 My Co
21. N MEASUREMENT DIRECT MODE Read Pasition a Slotl_CommandOut IF a nu C 5 Slotl_Commandin IF amp E 2 o gt ERRORI i Data fy OPOPO att ated POPOTO TOTO TOTOTET Timed Out Timed Out 4 Slot1_CommandIn die Stop f Timed Out much Iannann nun nun ann san nnn nennen nn nenn nennen enn nn snn nn nn nenne nenne sense snn sense nennen sen nnn sense nennen nns en en sense sense nes ens nennen u attneeeeeeeneeseeceeeeeseeeeeeeaneecneataceeseneranseanasaceenaseeseseseasceseeseessenesceenesneasessennessesceaneasesneeneaseeceeneasescneneaseecnnsnaseennestansecnnsasennasenscennesestereesensececsesersessess MME ees Reset the Eee ee ee EEE Sto D Button fil Wait for Stop Button and send the Stop Command ra Sa The Loops will be stopped if the Stop Button is pressed The Driver YI for module slot 1 runs parallel to the calling application amp Data between driver and application is tranfered via FIFO Buffers I Element W En Theres a CommandIn FIFO that transferes commands to the RDK amp 3 Module and a CommandIn FIFO that provides data from the Module x 3 This Loop reads the Modules Busy Status This ModuleBusy FIFO Read Node has to be placed in your Block Diagram and it has to be read at least one time in Order to prevent Compiler Errors because of unused FIFOs If you use multiple Modules the ModuleBusy FIFO Nodes for every used Driver YI have
22. SET9010MANO001 USER MANUAL Issue 01 RDK9314 USER MANUAL COMPACTRIO RESOLVER TO DIGITAL CONVERSION MODULE RDK9314 Art Nr 85019 u Pe O SET RDK 9314 RDK 9314 14 Bit Resolver Demodulator it Resolver Demodulator OC lt Ta lt 70 C sIos70 C mer Var I BE NEE Var COM com 15 0 SIN HI GND ug I demoauator 2S LO SNH p ro no DE 6 668 1o ap 5 3 COSH ek lig Betlaton BECH J O M meo ada u gt DECH BECIO GND waw smar o tech de SET GmbH August Braun Str 1 88239 Wangen Allg u Germany Tel 49 0 7522 91687 600 Fax 49 0 7522 91687 899 Copyrights SET GmbH All rights reserved Information contained herein is the property of SET GmbH and shall not be duplicated copied used or disclosed in whole or in part of any purpose The right of duplication use or disclosure is permitted only by written agreement of SET GmbH August Braun Str 1 88239 Wangen Germany LabVIEW CompactRIO TestStand are Trademarks of National Instruments Page 1 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 TABLE OF CONTENTS 1 IMPOFtaNEINSTtrUCHONS anne 4 1 1 IAEA e S a EA N E A E E E E E A E A N A A 4 1 2 Safety InSstructioNns a 4 1 21 Module F llure se 4 1 22 IMPEFMISSIDIC Applications u nu0unn nina 4 1 23 Module Installation And REMOV AN n nnsne 4 124 Electrical Connections cscs A 4 2 Mod le Overview een 5 3 Getme Starte iecseeshccnsconisatsta
23. Slot 1 wi E Dependencies Build Specifications Go Dependencies 2 Build Specifications i Dummy CompactRio 192 168 2 63 Real Time Features not available Dummy cRIO Chassis cRIO 9104 ff Dummy FPGA Target RICO cRIO 9104 2 G RDK 9314 Wg Slot 1 GB slot z Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Relates to an RealTime us i Sloki SET ROK 9314 Slot 1 SET 9314 RDK CompactRIO FPGA 2 m MM Slot2_SET_PDK_9314 Slot 2 SET 9314 RDK Target 2 QU slot3_SET_RDK_9314 Slot 3 SET 9314 RDK i ie i Slot _ SET RDK_ 9314 Slot 4 SET 9314 ROK T Slot5_5ET_ROK_9314 Slot 5 SET 9314 RDK m E Slot _SET_RDK_9314 Slot 6 SET 9314 RDK ja PP Slot7_SET_ROK_9314 Slot 7 SET 9314 RDK T Slots_SET_ROK_9314 Slot 6 SET 9314 RDE 40 MHz Onboard Clock z mi FFSA APPLICATION EXAMPLE Slot 13 vi amp Dependencies l EE a CETTE E ee Build Specifications ES Dependencies ike Build Specifications Additionally a small FPGA application which uses slot 1 is on the CD ROM to demonstrate the call and use of the RDK9314 driver FPG APPLICATION EXAMPLE Slot 1 vi Page 8 of 35 SET9010MANO0001 USER MANUAL L Sc Issue 01 RDK9314 To use the RDK9314 driver within an existing LabVIEW project copy all files from the example project folder into the existing project folder Existing Project Folder Ansicht Favoriten Extras Bearbeiten Datei O Zur ck E P Suchen O
24. es COMMAND VALUE U8 TARGET CMD_RESET 17 RDK9314 Controller This instruction DATA 0 resets the RDK9314 internal controller chip COMMAND VALUE U8 TARGET CMD_STOP 18 FPGA Driver VI This instruction stops and terminates the applicable driver VI Page 28 of 35 SET9010MANO0001 USER MANUAL ic SC Issue 01 RDK9314 3 6 MODULE IDENTIFICATION UNDER LABVIEW LabVIEW automatically detects the cRIO module type Discover C Series Modules Note that the external module supply must be connected for the automatic RDK9314 identification 3 7 SAVING THE SETUP The RDK9314 automatically saves the setup in a non volatile memory 3 8 AUTO RATIO The Auto Ratio function CMD AUTO RAT automatically adjusts the RDK9314 to the transfer ratio of the connected Resolver The Auto Ratio must be triggered when the type of Resolver is changed or a Resolver is connected to the module for the first time Note that position readings may be incorrect or out of tolerance when the module is not adjusted to the Resolver transfer ratio Page 29 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 4 SOFTWARE DEVELOPMENT The example driver software addresses all module features and thus requires a reasonable amount of the FPGA resources However not all features must be used in order to save FPGA resources and to speed up the compilation process This is demonstrated in the following applications 4 1 EXAMPLE 1 MANUALLY TRIGGERED POSITIO
25. from the supplier or by the user To do this the following procedure must be followed 6 1 6 2 CALIBRATION OF THE EXCITATION VOLTAGE AMPLITUDE Plug the RDK9314 into slot 1 of a cRIO chassis and connect the external supply voltage to the module Open example VI FPGA APPLICATION EXAMPLE Slot1 vi out of the project structure and click on the button Run Program the excitation amplitude to 7000 mVrnms and the frequency to 10kHz Connect a true RMS volt meter to the excitation output signal The voltage meter must ensure a 0 05 accuracy for the 7 000 Vrus measurement range 10kHz sinusoidal waveform Adjust an ExcitationCalData value of 3290 with the CMD_CAL_EXC instruction and check the excitation output voltage Iteratively reprogram the ExcitationCalData stepwise until the excitation output voltage reading is 7 000 Vrms To increase the output voltage increase the ExcitationCalData To decrease the output voltage decrease the ExcitationCalData The ExcitationCalData can be programmed within the range of 3260 3420 CALIBRATION OF THE INPUT CHANNELS Connect the module interface as shown below Note that procedure 6 1 must be accomplished before the input channels can be calibrated Execute instruction CMD_AUTO_CAL On completion of this instruction the module calibration is complete and the calibration data is saved in the non volatile module memory RDK9314 18V 36V Power Supply Page
26. ing when no other instruction is received When the module operates the automatic mode and receives an instruction then the automatic sampling is interrupted for the processing time which is required to operate this instruction The automatic mode can be programmed as follows e NOP Deactivate the Idle Command e CMD_RD POS Read Resolver Position e CMD_RD_AMP Read Excitation Amplitude e CMD _RD_FRQ Read Excitation Frequency e CMD_RD_RAT Read Resolver Ratio e CMD_RD_SIN VOL Read Resolver Sine Voltage Vrms e CMD_RD_COS VOL Read Resolver Cosine Voltage Vrms NOU BWeE O Page 27 of 35 SET9010MANO0001 USER MANUAL SC Issue 01 RDK9314 Refer to the TypeDef USRCMD ctl for these instructions COMMAND VALUE U8 TARGET CMD_CYCLE_ SPEED 16 FPGA Driver VI This instruction adjusts the idle frequency for the automatic mode CMD_IDLE_OPERATION The standard value is 50kHz Note Changing the cycle speed has an influence on the latency time of the manual mode operation Furthermore if Usin cos Vrms values are sampled by use of the automatic mode the sampling speed must not exceed 40kHz to get correct voltage readings To ensure correct operation for automatic rms readings first the cycle time with CMD_CYCLE_ SPEED must be programmed to a value lt 40kHz This restriction applies only to Usin cos Vams voltage readings but not to the Resolver position readings which allow 50kHz sampling rate for both operational mod
27. is A obviously damaged e physical damage e lose parts inside the module e it does not function any more 1 2 2 IMPERMISSIBLE APPLICATIONS module in explosive or hazardous environments is not permissible and may i The module is designed for laboratory use Installing or operating the result in serious injury or death 1 2 3 MODULE INSTALLATION AND REMOVAL Hot Surface AN The module may be hot Touching the module may result in body injury 1 2 4 ELECTRICAL CONNECTIONS Do not exceed the voltage levels according to the technical specifications Not following this instruction may result in module damage and serious injury or death The module is not designed to isolate voltage levels of more than 50Vpc Page 4 of 35 SET9010MANO0001 USER MANUAL L oc Issue 01 RDK9314 2 MODULE OVERVIEW RDK 9314 is a compact reliable and highly versatile Resolver to digital conversion module All commonly used Resolvers can be easily connected to the module without any additional signal adaption The module has a built in excitation oscillator inclusive power stage which can drive most Resolvers directly without the necessity of an external power booster All module parameter are interactively adjustable via software A sensor detection functionality automatically adjusts the module to the specific sensor ratio Controll Sensor RDK 9314 The RDK 9314 accepts a wide voltage supply range from 18V to 36V and provides ga
28. itialize the driver by passing standard values for the Idle peration and the CycleSpeed Set the Idle Operation to Position Set the Cycle Speed for the Idle Operation Reset the Sloti_CommandOut dlk B Stop Button Error in E23 a gt Slot_CommandIn Ab a a gt Slot _Commandin db a EE Stop eE r SDT En Position Keep 3 Element 7 P Element p Timet J OrdespesdLuek IT Tmed Out f Timed Out Timed Out 3 This Loop will be stopped if the Stop Button is pressed Read the ModuleBusy Status F MlFalse vb Read B ModuleBusy amp Element J i Timed Out HE This Loop reads the Modules Busy Status This ModuleBusy FIFO Read Node has to be placed in your Block Diagram and it has to be read at least one time in Order to prevent Compiler Errors because of unused FIFOs If you use multiple Modules the ModuleBusy FIFO Nodes for every used Driver YI have to be placed on your Block Diagram and each one has to be read at least one time Page 31 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 5 TECHNICAL SPECIFICATION 5 1 HOUSING e NI CompactRIO 9952 Standard Housing e Dimensions appr Imm x 72mm x 23mm 5 2 EXTERNAL POWER SUPPLY e Supply Voltage 18Vpc 36Vpc e Current Consumption max 50mA at 28Vpc without Resolver Caution The external power supply input is isolated from the cRIO chassis signals with a maximum isolation voltage of 50Vdc Note that the excitation output and the Si
29. lvanic isolation between the cRIO rack and the demodulator interface The module is operable within the NI cRIO real time environment and can also be plugged into a NI R series expansion chassis with PCI PXI FPGA card Included in delivery are all drivers required for the cRIO systems and LabVIEW TestStand integration examples VsuP a COM SIN HI SIN LO COS HI COS LO EXEC HI EXEC LO RDK9314 applications include industrial and military position control systems such as motor control robotics and many kind of servo loops which use Resolvers Page 5 of 35 SETI9010MANO0001 USER MANUAL E S E Issue 01 RDK9314 3 GETTING STARTED 3 1 SOFTWARE INSTALLATION Before the RDK9314 module may be used in a LabVIEW project the driver software must be installed To do this use the RDK9314 CD ROM and follow the following instructions To start the installation process execute the setup exe program on the CD ROM i Setup exe Click the start button to confirm the software installation SET cRIO Modules Install SET cRIO Drivers for Current Yersion of Lab IEW When the installation is completed successfully the following message appears Successfully installed The host system is now ready for use the RDK314 module in a LabVIEW project Page 6 of 35 SET9010MANO0001 USER MANUAL i SC Issue 01 RDK9314 3 2 RDK9314 ComPpAcTRIO LABVIEW DRIVERS To use of the CompactRIO RDK9314 driver software LabVIEW 8 6 m
30. mputer 88 FPGA Target RIOD PCI 7833R slott_SET_RDK_9314 Siot1_SET_ROK_9314 10 Select Sloti SET ROK 9314 5PI clk Slot SET ROK 9314 Ovrsmpclk DIOD Sloti_ SET ROK 9314 Trigger DIO1 Sloti SET ROK S314 5PI RdyBsy DIC2 Slot SET _RDK 9314 5P1 Cony DIO3 Sloti SET ROK 9314 SPT Func DIO4 Sloti SET ROK S314 5PI C5 DIOS Slot SET RDK 9314 5PI MISO DIO6 m Slot1_SET_RDK_93145PI MOSI DIOF ey Slot PL je Slot1_Commandin gt Jik Slot1_Commandouk 2 Jie Sloti_ ModuleBusy L sl Slot1_SET_RDK_9314_FPGA_DRIVER vi pac 40 MHz Onboard Clock Se Chassisl Connector 1 2 I Sloti_S5ET_ROK_9314 Slot 1 SET 9314 RDK mB FPGA APPLICATION EXAMPLE Slot 13 Wi Gi E3 Dependencies Dens en age Build Specifications Dependencies Build Specifications Page 17 of 35 SETSO1OMANOO01 USER MANUAL A oc Issue 01 RDK9314 3 2 2 7 SAVING THE NEW PROJECT Prior to the compilation process the project must be saved To do this click on File gt Save All Enter a file name for new projects Name the Project Untitled Project 1 Speichem in TEST PROJECT 4 4 Zuletzt verwendete D Desktop Eigene Dateien er Arbeitsplatz Dateiname TEST PROJECT I Netzwerkumgeb Dateityp Projects lvproj Abbrechen 3 2 2 8 COMPILATION AND EXAMPLE EXECUTION Open VI FPGA APPLICATION EXAMPLE Slot 1 vi out of the project structure and click the Run button FPGA APPLIC
31. ne Cosine input signals are galvanically connected to the external power supply 5 3 EXCITATION OUPUT e Frequency 1kHz 10kHz adjustable via software e Amplitude 2Vrms 7 Vrms adjustable via software e Current max 150mArms short cct protected Caution The excitation output can be damaged when a power source is connected to its terminals 5 4 SINUS AND COSINUS SIGNAL INPUTS e Voltage Range 2Vems 7 Vrms e Zin differential 54kOhm Page 32 of 35 SET9010MAN0001 USER MANUAL E SC Issue 01 RDK9314 e Zin single ended 27kOhm Caution The signal inputs can be damaged when the input voltage exceeds a limit of 40V peak 5 5 POSITION PROCESSING e Resolution 12 14 16Bit adjustable via software e Accuracy 2 3 3 3 Arc min at 1 4kHz 4 10kHz e Acceleration 500kdeg s 12Bit 30kdeg s 14Bit 2kdeg s 16Bit e Settling Time 179 step 8msec 12Bit 20msec 14Bit 50msec 16Bit e Tracking Rate min 432rps 12Bit 108rps 14Bit 27rps 16Bit 5 6 ENVIRONMENTAL CONDITIONS e Temperature Range 0 C 70 C e Humidity 10 90 relative non condensing 5 7 CONNECTOR PINOUT User Interface Connector 25 pin dSUB male Page 33 of 35 6 I SET9010MANO001 USER MANUAL _ Issue 01 RDK9314 MODULE CALIBRATION The RDK9314 is calibrated when shipped If a periodical calibration is compulsory due to the field of application the module can be re calibrated
32. ntianataudaetetestcexatacieesntenbsouacanisatotastausianevteterstanatesieatotentaanstennsabatauieaneteriess 6 3 1 SofWwarenstallatiOM csini E r EEE AEE 6 3 2 RDK9314 CompactRIO LabVIEW Drivers sccsccsccsccsccscescescescsscescsscsscsccsccsccscescescescescescescescescescsceuss 7 3 2 1 Create New Projects By Use Of The Example Project cssccsccsccssccscceeccsccsccesccscceccescescceccescsccecceses 8 3 2 2 Driver Application For A NI PCI FPGA Card csccsccsccsccsccsccsccnccnccnccnccsccscescescescescescnccescsccnccncoees 10 3 2 2 1 Creating A NEW Project a ea ee ee ee nen een 10 3 2 2 2 Creating A New FPGA Target NI FPGA PCI PXI Card ssssccccccsssssssscecccccccssssseeeeccenaesssseeseesones 11 3 2 2 3 Adding An R Series Expansion Chassis scsscsscsscsscsscsccsccsccsccsccnccnccnccsccsccscescescesceccesceccnccsccnscnsonses 13 3 2 2 4 Adding The RDK9314 Hardware Components To A Project 2es2e02e0nennunnnnnnnnnnnnnnnnnnnunnunnunnennenn 14 3 2 2 5 Adding The Driver Software Components s erssennennnnnnnnnunnnnnnunnunnnnnnunnunnnnnnunnsnnnunnunnsnnsnnnunnsnnnnnn 15 3 2 2 6 Adding The FPGA Application Example ccscsscsscsccsccsccsccsccsccnccsccsccsccscescescescescesceccescuccucceccnsonees 16 3 2 2 7 Savine The NOW Project een een ee Eee 18 3 2 2 8 Compilation And Example Execution esesesessesesecsececscsesecececsesesesecececsesesecececsesesecececsesesesececseseseseceee
33. oject Close Project 1 SET 9314 ROK 2 SET 9314 RDK 3 SET 9314 RDK 4 SET 9314 ROK Slot Lyi Fage Setup Frink Print Window Ctrl F Ctrl I VI Properties Recent Projects Recent Files Real Time Features not available Ctrl g Page 10 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 3 2 2 2 CREATING A NEW FPGA TARGET NI FPGA PCI PXI CARD Both project windows can be aligned as shown below Project Explorer RDK 9314 lvproj Sel Project Explorer Untitled Project 1 Sele File Edit View Project Operate Tools Window Help File Edit wiew Project Operate Tools Window Help KNIE RER LE DE SEN BREI Ei DET TE MEN EEE Items Files Items Files ifs Project RDK 9314 lvproj B t Project Untitled Project 1 gt N My Computer 5 N My Computer 8 9 TypeDefs H 5 Dependencies er Dummy RIOO PCI 7833R i Build Specifications ii 9 ROK 9314 ii Soti i fe Sotz Slots i u Slot4 M 40 MHz Onboard Clock a Dummy Chassis Connector 1 ii T Slot1_SET_RDK_9314 Slot 1 SET 9314 RDK a Slot2_SET_RDK_9314 Slot 2 SET 9314 RDK p i Slot3_SET_RDK_9314 Slot 3 SET 9314 RDK iM Slot4_SET_RDK_9314 Slot 4 SET 9314 RDK i be FPGA APPLICATION EXAMPLE Slot 1 vi Ge Dependencies E Build Specifications j BP Dependencies be Build Specifications I si Dummy CompactRIO 192 168 2 63 Real Time features not available
34. onto the newly added FPGA Target and select New gt R Series Expansion Chassis File Edit wiew Project Operate Tools Window Help lbGm x hax E b Project Untitled Project 1 E My Computer a New VI i j it virtual Folder i ae a Execute YI on F a Control i an RIG Device Setup a u Start FPGA Wizard A E FR Series Expansion Chassis Add p FPGATIO FPGA Base Clock Confirm the dialog with OK New R Series Expansion Chassis Mame Location Discover C Series modules execution and writes to digital lines on the FPGA target Make sure vou have an R Series Expansion chassis connected to the connector selected in the Location control i Discovering Series Modules halts current FPGA Page 13 of 35 SET9010MANO0001 USER MANUAL Issue 01 RDK9314 SEI The newly added R Series Expansion Chassis is now included in the project structure Project Explorer Untitled Project 1 File Edit View Project Operate Tools Window Help Joa x Oo x ler ee I Bea Project Untitled Project 1 5 My Computer 4 FPGA Target RIOD PCI 7833R n B 40 MHz Onboard Clock k Be Chassisi Connector 1 z Dependencies x eS Build Specifications Eo Dependencies L Build Specifications 3 2 2 4 ADDING THE RDK9314 HARDWARE COMPONENTS TO A PROJECT To add a specific cRIO module to the FPGA chassis use the drag and drop function to copy the file from the example project
35. rdner Gii Adresse L C Dokumente und Einstellungen Tester02 Desktop Existing Project Folder a Wechseln zu Name Gr e Typ Existing Folder 1 Dateiordner Existing Folder 2 Dateiordner Existing Project aliases 1 K6 ALIASES Datei Existing Project vips 1 KB LYLPS Datei il Existing Project lvproj 286 KB LabVIEW Project Datei und Ordneraufgaben Andere Orte E Desktop 9 Eigene Dateien iQ Arbeitsplatz tras Key Ordner Ey ster02 Desktop CompactRIOLabvIE w Name FPGA Bitfiles TypeDefs FPGA APPLICATION EXAMPLE Slot 1 vi Dateiordner 23 06 2009 LabVIEW Instrument 29 05 2009 1KB ALIASES Datei 23 06 2009 1 K6 LYLPS Datei 29 05 2009 286 KB LabYIEW Project 29 05 2009 2KB Textdokument 19 05 2009 1 K6 ALIASES Datei 19 05 2009 Page 9 of 35 SET9010MANO0001 USER MANUAL E a SC Issue 01 RDK9314 3 2 2 DRIVER APPLICATION FOR A NI PCI FPGA CARD 3 2 2 1 CREATING A NEW PROJECT In order to use the RDK9314 driver for a new project first open the example project and then select File gt New Project E Project Explorer RDK 9314 lvproj A ele Edit view Project Mew WI New Open Chrl 0 Close krl Close All Operate Tools Window Help Chr m e alll e Save Chrl 5 Save ds Save All Chrl Shift 5 Save All this Project Save For Previous Version New Project Oper Project Save Pr
36. rgets and Devices on My Computer Targets and Devices Targets and Devices Existing target or device Existing target or device Discover an existing target s or devicefs Discover an existing target s or devices C Existing device on remote subnet Existing device on remote subnet No items can be added to My Computer No items can be added to My Computer O New target or device New target or device Create a new target or device by type Create a new target or device by type Targets and Devices Targets and Devices a D FPGA Target D TompactRIO Detecting devices f cRIO 9101 es cRIO 9102 fe cRIO 9103 ie cRIO 9104 SO R Series PCI 7611R fej PCI 7813R ei PCI 7830R PCI 7831R PCI 7833R fj PxI 7811R v i amp Le E E Project Explorer Untitled Project 1 File Edit View Project Operate Tools Window Help Jo Saw xO Xe ee a FA Items Files i jig Project Untitled Project 1 5 My Computer F FPGA Target RIOD PCI 7833R be Fo 40 MHz Onboard Clack ES Dependencies ie Build Specifications I u Dependencies x Build Specifications Page 12 of 35 SET9010MAN0001 USER MANUAL E l SC Issue 01 RDK9314 3 2 2 3 ADDING AN R SERIES EXPANSION CHASSIS To use an RDK9314 module together with a FPGA chassis an R Series Expansion Chassis must be appended to the actual project structure Use the mouse and click with the right button
37. t the Resolver must be connected to the module for this process When the Resolver type is changed make sure to execute Auto Ratio again Page 20 of 35 SET9010MANO0001 USER MANUAL L SC Issue 01 RDK9314 3 5 OPERATING DETAILS 3 5 1 DRIVER CALL AND DATA TRANSFER 3 5 1 1 FIFO DATA TRANSFER FPGA FIFO buffers are used to transfer data between the calling application and the driver Vs In total three FPGA FIFO buffers exist for each module slot Siloti Commandin JR w Sloti Com mandGut IF Slotl ModuleBusy IF Timed uk Timed uk Timed ut Send commands and data Receive data and command Busy Status of the module e COMMANDIN FIFO This buffer transfers instructions and data to the RDK3914 module driver The buffer size is 20 elements U32 and can be expanded as necessary e COMMANDOUT FIFO This buffer receives data and the echoed instruction from the RDK3914 module driver The buffer size is 20 elements U32 and can be expanded as necessary e MobduLeBusy FIFO This buffer continuously indicates the RDK9314 busy state The ModuleBusy Flag Boolean is active when the RDK9314 controller is processing data The buffer size is 20 elements U32 and can be expanded as necessary 3 5 1 2 DATA FRAME SETUP TRANSMITTING DATA TO THE RDK9314 MODULE To send data to the module driver a U32 Integer 4 byte data format applies The data simply must be written into the CommandliIn FIFO buffer Command U8 e
38. ust be installed The driver software includes a FPGA diver VI which installs the required FIFO registers to communicate with the application software Note that the FPGA applies SPI interfaces to exchange data with the RDK9314 module mi SIot1_SET_REK_9314_FPGA_DRIWER vi RDK9314 FPGA driver VI for Slot 1 Depending on the type of chassis R Series Expansion or Real Time CompactRIO chassis up to eight RDK9314 modules can be operated in parallel within one chassis Every module within a chassis applies separate data lines and hence every module requires a separate driver VI we Slot1_SET RDK_9314 FPGA DRIVER vi Slot2_SET_RDK_9314 FPGA DRIVER vi we Slok3_SET_RDK_9314_ FPGA DRIVER vi we Slot4_ SET _RDK_ 9314 FPGA DRIVER vi we SlotS_SET_RDK_9314 FPGA DRIVER vi we Slot SET RDK_9314 FPGA DRIVER vi Slot7_SET_RDK_9314 FPGA DRIVER vi Slots SET RDK_ 9314 FPGA DRIVER vi Each slot applies a separate driver VI Three example applications can be found on the CD ROM to demonstrate the structure and operation of the driver Vl s e FPGA APPLICATION EXAMPLE Slot 1 vi This is an application example which demonstrates the use of one single RDK9314 module which is installed in slot 1 of a PCI FPGA R Series Expansion Chassis or a cRIO Realtime chassis e FPGA APPLICATION EXAMPLE MULTIPLE PCI 4 Slots vi This is an application example which demonstrates the parallel operation of up to four RDK9314 modules in a PCI
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