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SIS3300/SIS3301 65/80/100 MHz VME FADCs User Manual

1. ansa 39001 Last sor KE WM Aere A anda 39001 uoo dot awor a001 An Ant 44001 VUO Tero te 32T oH mE ASY dvd DNITOOD ANDA ES SEET on vk T T aspa Agee anda ace AE SH anoa anaa SE anaa geen DEET anda AND 22A K acra E 8 bini ana AS ASH 88A f Oe anpa Ast anaa Aer anda AW r a e a anoa Aen Sein anoa ASHE l ASY T d a Z TS O80 asey IM 4 H ama AS ZS E zin C 3o 18 j Yo TH Te 90 LEE CBT Pri eo a D d AU THO Lx oa e acral Eid x qN9v eid THO g zid THO os etd 15 E 4 le 3013 TIT THO E anov any omg WE NII34A welt Eu sisay qul 3001 any aora bound T e Si WID 4012 ES EE ks A n 3dooN3 b ao angy o qul od 32 Doral os us w00 mu NIY t 1no Ni L ET Die D HOTA MOTA Am AT De os v y idc Ae auov Oe Nov Q vim EK Eroa THO Tn NI STaNNWHO 0T 9SOV96Z 117 NAAT ONTI WOINOO qu aoar og soral nora oee Ary Vina 001 Aan velo de mat Sr ONE ONE 4 INOA NIA Op FE anov Oms an O1 8SO WET 117 ech 138440 THO clum aub ail ol co aNDY omi ooral 001 awor Ke us t 19 mai SCH us INCA NA O te zem qu 919 t 13S44O THO C Ee Gori wre Page 69 of 72 SIS Documentation SIS3300 SIS3301 SIS tk 65 80 100 MHz FADC VME 11 Index JEN ME ups dea e edens 7 12 16 ATE oh hain Bilas eo dR 53 OU 4i u hamu tapete Bee ct tte 53 Egeter eC
2. 9 module jd asse keet eene 19 No OF Sampl s u aet 38 61 start delay state ote 23 25 Status zeit dr poe pe ns Deeg bas 54 stop del y 4 tete 23 25 threshold neret 34 36 time stamp predivider esses 26 trigger Setup tenen ege 39 TORG cue AT HO 57 ROARK nesrin ecelesie ge 20 RORA bended edits 20 Totary SWitCh EEN 13 el 20 single ended recede 55 single Shot 4 i e eterno 62 Ea ra e eere Eee td 62 A RE 13 KA 13 TCK pee nee edt 60 UP 60 Deet eege SE dod 60 Technical Properties Features 7 termination P215 tatto stet de 66 threshold z iie eR 11 34 RE 60 ID onam en TERR SUO Es 34 41 42 DOS Su ssh 11 Page 71 of 72 SIS Documentation SIS3300 SIS3301 ui PES 11 trigger Control 11 trigger event directory 4l trigger generation 11 Tundra c imeem ete eret 20 Universe If n teen teret 20 user nic CE 18 54 EED atit orina 18 OUER 18 54 USED EE 46 USED INPUT E 54 enable tgo ep teet 18 user output clear per depre 17 SIS GmbH A 65 80 100 MHz FADC VME NGC isis EE 60 KA EE 12 65 Backplane aaaea eR rre es 10 esiste ror ue Eeer 66 ULC EE 11 readout T DT 12 KEE EE 57 VME addressing 52e sette eie 13 VMB64X inia 7 13 65 67 VMEGAXP 3 iia been texta 67 VSB EE 7 66 width external start stop ses
3. Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 LEMO PCB Coax control connector LEMO EPB 00 250 NTN 90 PCB LEMO Analog input connector LEMO EPL 00 250 NTN 90 PCB LEMO Analog input connector LEMO EPG 00 302 NLN 3301 differential input version 10 5 P2 row A C pin assignments The P2 connector of the SIS3300 has several connections on rows A and C for the F1002 compatible use at the DESY H1 FNC subdetector This implies that the module can not be operated in a VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3300 is shown below P2A Function P2C Function 1 5 2 V 1 5 2 V 2 5 2 V 2 5 2 V 3 5 2 V 3 5 2 V 4 not connected 4 not connected 5 not connected 5 not connected 6 DGND 6 DGND 7 P2_CLOCK_H 7 P2 CLOCK L 8 DGND 8 DGND 9 P2_START_H 9 P2_START_L 10 P2_STOP_H 10 P2_STOP_L 11 P2_TEST_H 11 P2_TEST_L 12 DGND 12 DGND 13 DGND 13 DGND 14 DGND 14 DGND 15 DGND 15 DGND 16 not connected 16 not connected T s 17 is 31 not connected 18 not connected Note The P2 ECL signals are bussed and terminated on the backplane of F1002 crates The user has to insure proper termination if a cable backplane or add on backplane is used Page 66 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 10 6 Row d and z Pin Assig
4. M 47 5 1 1 Front panel SU SIG oet eR te Rn et RENE UR eei Rede ente 47 5 2 Daleiden ee 47 5 3 Start lose UNENEE Dee EES AE ENEE 48 54 Stop lOgIC SUImiary ee eoo a DESEN hd SEN 49 6 C Operati ni uu un 50 6 1 VC RE u uu aaa aa aa Gaan w q puasa a had a qa Aaah Qua uhu 50 6 2 16 17 T STE eessen Bede o uaa teo nad eite e div d Oa AS 50 6 3 Start S miplimp n eot Gh adeo dp p i RO te as e OR A ete ates rete peer het 50 D Stop Sampling Event ioa us ae ha hte Ee Bate di auod i 51 6 5 End of Sampling clear arm disable Sample Clock AA 51 de NS Ganley Ou s s s tome od ute utis tas te eds E dun dii iu o dus tnde 52 e EE 53 8 1 Control In OUutputs 2 See erepti o fe ee det i enin tene eo een 54 8 1 1 USE InpUt EE 54 8 1 2 Control input termiatiobi ore e Ades quii bd teer ee ee eite 54 82 Anal g E 55 8 2 1 Input range and impedance configuration for single ended SIS3300 1 sss 55 8 2 2 Input range and impedance for differential SIS3301 essere 55 8 3 E OC 56 GE RER ei 8 RE 56 9 Jumpers ConfiguratiQn 2 221 5 er Eee tete pna NEP Y YAN Y PASO aspas RS PASEOS ANNE EA NER Ee MER UNE 57 OU C Esos oce eoe mette scie ia eh san ead ed e e 57 9 1 1 EL E 57 9 1 2 SIS3300 2 V2 arid Ing EE 57 9 2 RRE 57 9 3 Offsetadj stMment erret e d a i t tete etr os Ee EE ute 58 9 3 1 SIS33001 eeneg a aqu uqu Tuan eege eege Ee H 58
5. 4 12 Key address start Auto Bank Switch mode 0x40 write define SIS3300 KEY START AUTO BANK SWITCH 0x40 write only D32 A write with arbitrary data to this register key address will start the auto bank switch mode 4 13 Key address stop Auto Bank Switch mode 0x44 write define SIS3300 KEY STOP AUTO BANK SWITCH 0x44 write only D32 A write with arbitrary data to this register key address will stop the auto bank switch mode 4 14 Key address clear BANK1 FULL Flag 0x48 write define SIS3300 KEY BANK1 FULL FLAG 0x48 write only D32 A write with arbitrary data to this register key address will clear the BANK1 FULL Flag 4 15 Key address clear BANK2 FULL Flag 0x4C write define SIS3300 KEY BANK2 FULL FLAG Ox4C write only D32 A write with arbitrary data to this register key address will clear the BANK2 FULL Flag Page 28 of 72 SIS3300 3301 SIS Documentation SIS GmbH 65 80 100 MHz FADCs VME 4 16 One wire Id register 1 0x60 read write SIS3301 V3 05 only define SIS3300 ONE WIRE 0x60 read write D32 A DS2430 256 Bit 1 wire EEPROM can be installed on the SIS3301 to store the serial number of the module This information is stored in the 64 bit application register of the DS2430 in the factory Offset Contents Example SIS3301 80 SN 10 Module Id m 2 Clock 0x00 3 Speed 0x80 4 0x00 5
6. DIL A INDY ASN anov aNDV aee 3001 Kal 9TIS012 s oc sc puo 2084 awor aga dunv 3 9 2 a E F 1 D a Z T X15 O04 12 zin aol us acral 3012 x x dav b AST dora dora ru angy aNDY sisay sz 30001 any aor one ouer aNDY m VOID 4012 7 A CEPS V anda A KI T ACC anda A G isd anda AE EA anda AEEA 31 GNDV anov OHDN OHDN Nov ag Fa b ASW GNDV ag n3 QONDV AST TE GONDV AST Tp GONDV AST 1E OHDN AST E nM Av EH GNDV ASN 9 GNDV AST Z anov AS G 20 IHI 0 I1nOJ34A ES M001 na NIJ3HA I Hwy SID old 6d 8d ia 3qoSN4 G 9a sa A000Na PO a za Ny 1a od NV IL Old IHD Tn 0L 8S2G120 IT ND OEE MIN VETA a001 4001 WLIO Ee WL ONE ON INOA NIA Nov aNov aNnov Lin 3219509 aNnov Zd Zd i all wu bid basi oLTaL 26 rai n us 7135440 IH2 C gni us 13S44O IHO Q O AHY gor oral NI TTSNNVHO IOWT CH 195440 1H2 138440 THO Page 68 of 72 SIS GmbH VME SIS3300 3301 65 80 100 MHz FADCs SIS Documentation 10 7 2 SIS3301 differential any ai 7135440 THO CF 13S33O IH2 O
7. 65 80 100 MHz FADCs VME 4 Register Description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font like define SIS3300 CONTROL STATUS 0x0 read write D32 refers to the sis3300 h header file 4 1 Control Status Register 0x write read define SIS3300 CONTROL STATUS 0x0 read write D32 The control register is in charge of the control of basic properties of the SIS3300 1 board like output signal assignment in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register Bit write Function read Function 31 Clear reserved 15 30 Clear reserved 14 29 Clear reserved 13 28 Clear reserved 12 27 Clear reserved 11 26 clear bank full pulse to output 3 25 clear bank full pulse to output 2 24 clear bank full pulse to output 1 23 Clear reserved 7 22 Disable internal trigger routing 21 Activate trigge
8. Enable front panel gate mode not Start Stop Status front panel gate mode 9 Enable P2 Start Stop logic Status P2 start stop logic 8 Enable front panel Lemo Start Stop logic Status front panel start stop logic 7 Enable stop delay value defined by stop delay register Status stop delay 6 Enable start delay value defined by start delay register Status start delay 5 Enable multi event mode Status multi event mode 0 Enable Sample Clock will be cleared with end of event 1 Enable Sample Clock will be cleared at end of bank only i e with last page of memory 4 Enable Autostart in multi event mode only Status Autostart 3 Use delay locked loop for external clock Status delay locked loop for external SIS3301 03 06 only clock 2 Enable auto bank switch mode Status auto bank switch mode 1 Enable Sample Clock for Memory Bank 2 arm for sampling Status sample clock bank 2 0 Enable Sample Clock for Memory Bank 1 arm for sampling Status sample clock bank 1 The power up default value reads Ox Clock source bit setting table Clock Source Clock Source Clock Source Clock Source Bit2 Bitl BitO 0 0 0 internal 80 100 MHz Page 23 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME internal 40 50 MHz internal 20 25 MHz internal 12 5 MHz internal 6 25 MHz internal 3 125 MHz external clock front panel P2 Clock re l l Kea Lac
9. unused read back as 0 address counter The address counter is not in a defined state after power up or Key Reset Unused bits are not updated and may contain arbitrary data i e only the number of bits that corresponds to the selected page size will hold significant data example the lowest 7 bits are valid for a page size of 128 4 31 Bank 2 address counter 0x20000C 0x28000C 0x30000C 0x38000C define SIS3300 BANK2 ADDR CNT ADC12 0x20000C read only D32 define SIS3300 BANK2 ADDR CNT ADC34 0x28000C read only D32 define SIS3300 BANK2 ADDR CNT ADC56 0x30000C read only D32 define SIS3300 BANK2 ADDR CNT ADC78 0x38000C read only D32 Same as bank 1 address counters but for bank 2 of ADC groups 1 2 3 4 Page 43 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 32 Bank 1 event counter 0x200010 0x280010 0x300010 0x380010 define SIS3300 BANK1 EVENT CNT ADC12 0x200010 read only D32 define SIS3300 BANK1 EVENT CNT _ADC34 0x280010 read only D32 define SIS3300 BANK1 EVENT CNT ADC56 0x300010 read only D32 define SIS3300 BANK1 EVENT CNT ADC78 0x380010 read only D32 This read only registers hold the current bank 1 event counter for ADC groups 1 2 3 4 The counter is 12 bit wide The counter will change while the ADC is sampling as events are coming in The returned value is the current event number The regis
10. 9 3 2 el EE 59 DAs PAG EE 60 DU AADD8ONdIX EEE EA EEE SE u au TS uuu uc d d e dr ous Used ed 61 10 1 Data acquisition Todes eer RR tenet PERI ENEE 61 10 l c Multiplexer modes eie eene eere cm erre EENE de in e De ex evo He Fee PES Red 61 10 1 2 Random external clock mode oe tee ee alas spa sd 62 10 1 3 wrap versus single shot no wrap mode 62 10 0 4 Auto bank Switch mod stees aie hel dhe ere ee 64 10 2 Power ee EE 65 10 3 Operating conditiOns oo ber Dn ee e RE EUN UR EUER eee aie 65 10 3 L EE 65 10 3 2 Hot Sw p live imserti n i 8 50 8 erm eee dete E DA E Sn 65 104 Connector types i ee e didit te eii ii eden 66 Page 4 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 10 5 P2row A C pin assignments Sia eden aa eig eene tur eed o cedes ulasan 66 10 6 Row d and z Pin Assignments nennen eene trennt nr enne nnen een ntn ene tn nete entre nne nenne 67 10 7 Input Schematies wi ie e np ei e e RD i Ier e te 68 10 7 1 SIS330x singl ended a 5 ree e hiec e AI a e I ORA eds 68 10 7 2 SIS330T differential erheben Ee Aes 69 INE In sc PR 70 Page 5 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 1 Introduction The SIS3300 3301 are eight channel ADC digitizer boards with a sampling rate of up to 105 MHz for the individual channel and a resolution of 12 14 bit The boards ar
11. 2 placed on D2 during VME IRQ ACK cycle 0 1 IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle 0 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle 0 The power up default value reads Ox 00000000 Page 20 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 4 Interrupt control register 0xC define SIS3300 IRQ CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are foreseen for the time being three of them are associated with an interrupt condition the fourth condition is reserved for future use Bit Function w r Default 31 unused Status IRQ source 3 user input 0 30 unused Status IRQ source 2 reserved 0 29 unused Status IRQ source 1 end of last event bank full 0 28 unused Status IRQ source 0 end of event 0 27 unused Status VME IRQ 0 26 unused Status internal IRQ 0 25 unused 0 0 24 unused 0 0 23 Clear IRQ source 3 Status flag source 3 0 22 Clear IRQ source 2 Status flag source 2 0 21 Clear IRQ source 1 Status flag source 1 0 20 Clear IRQ source 0 Status flag source 0 0 19 Disable IRQ source 3 0 0 18 Disable IRQ source 2 0 0 17 Disable IRQ source 1 0 0 16 Disable IRQ source 0 0 0 15 unused 0 0 14 unused 0 0 13 unused 0 0 12 unused 0 0 11 unused 0 0 4 unused 0 0 3 Enable IRQ so
12. 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 2 6 Averaging Averaging over N N 2 4 8 128 consecutive samples can be used to cover the domain of lower speed digitizers with the SIS3300 1 cards without compromising on the resolution signal to noise ratio side 2 7 Trigger control pre post start stop and gate mode The SIS3300 1 features pre post trigger capability as well as start stop mode acquisition and a gate mode in which start and stop are derived from the leading and trailing edge of a single control input signal The trigger behaviour is defined by the acquisition control register 2 8 Internal Trigger generation The trigger output of the SIS3300 1 can be either used to interact with external trigger logic or to base start stop on a threshold i e one individual threshold per ADC channel of the digitized data Trigger generation can be activated with two conditions e module armed i e sample clock active trigger can be used to start acquisition e module armed and started trigger can be used to stop acquisition The user can select between triggering on the conditions above and below threshold 2 9 Time Stamp Memory A 1024 x 24 bit Time Stamp Memory is implemented for each memory bank An internal counter starts with the first Stop trigger condition in multievent mode and it will be incremented with the sample clock or with the predivided sample clock factor 1 to 256 Each s
13. DS to DTACK 30 40ns 64bit every 125ns gt 64 MByte sec i B 2 2 00 V amp Ch2 2 00V M 100ns Chi x 1 84 v H I Tek Run 100 e Hi Res uar T SIS330x DS to DTACK 50 60ns 128bit every 200ns gt 80 MByte sec 2eVME Page 12 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 3 VME Addressing As the SIS3300 VME FADC features memory options with up to 2 banks of 4 times 128 K samples each A32 addressing was implemented as the only option Hence the module occupies an address space of OXFFFFFF Bytes i e 16 MBytes are used by the module The SIS3300 1 firmware addressing concept is a pragmatic approach to combine standard rotary switch style settings with the use of VME64x backplane geographical addressing functionality The base address is defined by the selected addressing mode which is defined by jumper array J1 and possibly SW and SW2 in non geographical mode Function EN A32 EN GEO EN VIPA reserved Lf The table below summarises the possible base address settings J1 Setting Bits A32 GEO VIPA 31 30 29 28 27 26 25 24 X SW SW2 thon el al x x S e e lt lt lt lt lt GIGI OI O G x Not implemented in this design Shorthand Explanation
14. El C C l a l a L I Ke l C9 ol l C9 l Refer to the table in section 2 5 2for allowed clock speeds Lower sampling rates into memory can be accomplished with a sampling clock within the specified range in combination with the clock predivider register in multiplexer mode or random external clock mode 4 5 1 Delay locked loop for external clock 8183301 03 06 The external clock signal in the range 60 105 MHz from a SIS3820 clock distributor e g is used to drive a delay locked loop The delay locked loop output is used as ADC clock Page 24 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 6 Start Delay register 0x14 read write define SIS3300 START DELAY 0x14 read write D32 Pretrigger operation can be implemented via the start delay register in conjunction with front panel start stop or gate mode operation The external and autostart start signal or leading edge of the gate will be delayed by the value of the register 2 clocks if the external start delay is enabled in the acquisition control register Bit 32 unused read as 0 16 unused read as 0 15 START DELAY BITI5 0 START DELAY BITO The power up default value is 0 4 7 Stop Delay register 0x18 read write define SIS3300 STOP DELAY 0x18 read write D32 Posttrigger operation can be implemented via the stop delay register in conjunction with front
15. IK eegen 23 J113 57 NET 57 J210 JTAG uu be ERE 6 57 60 inn E 57 ET E 58 TOSCO D 57 KA Page 70 of 72 SIS Documentation SIS3300 3301 clear bank full Tag 28 clear bank full Tag 28 general reset a ciet pupas sa 27 start auto bank switch mode 28 stop auto bank switch mode 28 VME start sampling 27 VME stop sampling 27 Key address i iui geed ege aves EE NEES 14 LED A 56 D p 56 P 56 R 56 SAM nebat iuh eeu aep Bap 56 SR DE 56 STEP ayau bereitet ees 56 ERG oraren a tele tte EE ise 56 U 56 TE REN 17 18 56 LEDs front T o eni Hte ett 56 BEEMO 2t pui bel 47 58 LINUX uoto tet bte etes 20 TS ue eee eee ee 65 67 M39 MBETOA EE 7 12 16 MEMOLY EE 7 9 management onam a i REIR 9 UU ELE 9 memory divisions a 31 mode auto bank switch eene 64 auto Start a ether rts 62 AVETAGING tege eer e t Ur dete 32 dual bank toe eere 9 external random clock 33 Bale Lasten er EPOR s 47 gate change 32 46 multi event teri evi 9 51 62 multiplexer 18 24 32 37 38 61 UU 39 random external clock 24 54 62 single event eo hp sette 51 Single shot tote deserto 62 SST SEODu ss saa ees 11
16. K Samples 128 1 0 1 512 Samples 256 1 1 0 256 Samples 512 1 1 1 128 Samples 1024 Page 33 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 20 Threshold registers 0x100004 0x200004 0x280004 0x300004 0x380004 define SIS3300 TRIGGER THRESHOLD ALL ADC 0x100004 write only D32 This register is implemented on the base of the individual channel group The address SIS3300 TRIGGER THRESHOLD ALL ADC can be used to write the same value simultaneously to the registers of all channel groups define 8183300 TRIGGER THRESHOLD ADC12 0x200004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC34 0x280004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC56 0x300004 read write D32 define SIS3300 TRIGGER THRESHOLD ADC78 0x380004 read write D32 These read write registers hold the threshold values for the ADC channels 1 3 5 7 and 2 4 6 8 Via the bits 31 and 15 of the channel group the user can select between greater GT or less than equal as trigger criterion GT means trigger condition is valid if sample data greater then threshold data For SIS3300 Bit 3l 30 28 127 16 15 14 12 11 0 Function 0 GT unused threshold value 0 GT unused threshold value 1 LE ADC 1 3 5 7 1 LE ADC 2 4 6 7 default after Reset OxOfffOfff disable Trigger For SIS3301 Bit 31 30 29 16 15 14 13 0 Function 0 GT unused threshold v
17. SWI SW2 Setting of rotary switch SW1 or SW2 respective GAO GA4 Geographical address bit as defined by the VME64x P backplane Notes e This concept allows the use of the SIS3300 1 in standard VME as well as in VME64x environments i e the user does not need to use a VME64x backplane e The factory default setting is EN_A32 closed SW1 3 SW2 0 i e the module will react to A32 addressing under address 0x30000000 e Early SIS3300 boards PCB SIS3300 V1 have a different base address scheme Page 13 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 3 1 Address Map The 8183300 resources and their locations are listed in the table below Note Write access to a key address KA with arbitrary data invokes the respective action Offset Size in BLT Access Function Bytes 0x00000000 4 W R Control Status Register J K register 0x00000004 4 R Module Id and Firmware Revision register 0x00000008 4 R W Interrupt configuration register 0x0000000C 4 R W Interrupt control register 0x00000010 4 R W Acquisition control status register J K register 0x00000014 4 R W Extern Start Delay register 0x00000018 4 R W Extern Stop Delay register 0x0000001C 4 R W Time stamp predivider register 0x00000020 4 KAW General Reset 0x00000030 4 KA W_ VME Start sampling 0x00000034 4 KA W_ VME Stop sampling 0x
18. Status User LED 1 LED on 0 LED off denotes power up default setting 4 1 1 Trigger activation Trigger generation can be activated for two states of the SIS3300 1 By default trigger generation is active as soon as the module is armed i e a sample clock is active In this mode the trigger can be used to start the digitizer with stop condition end of event e g Trigger generation upon armed and started i e bit 6 of the control register set the trigger is used to stop the module what is a efficient mode of operation in conjunction with autostart e g 4 1 2 Trigger routing The trigger status is present on LEMO output 1 with user output and multiplexer mode disabled It can be used to form a general trigger decision with external trigger electronics which is fed back to the corresponding input start stop on the digitizer s The trigger is routed on board to the stop input with the internal trigger routing bit set Page 18 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 2 Module Id and Firmware Revision Register 0x4 read define SIS3300 MODID 0x4 read only D32 This register reflects the module identification of the SIS3300 1 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adapt
19. aad 7 ABD sic P Hn 7 13 57 address DSO ick iste ite t E n ne rei eatin 57 Address Map eth tette aereis 14 address SPACE ee fib wives eie saa dala 13 addressing E EE H Amanda ee qu haut enter etre he de de 19 analog T ENEE 55 armed EE 17 AUTOSTART iem whens Seeche 64 aVerag ig sis Sege eret peste 11 32 Bl FULL ueni rtg hri peg 64 B2 EE 64 backpl iie 5 ceret eite tenet 7 13 65 bank 1 address counter sanini a 43 disable sample clocK 23 enable sample clock esse 23 EVEN COUNTER eege oeste ies 44 event directory T 42 event time stamp directory 30 IDETOEy z neger 46 trigger event directory 41 bank 2 address COUNTER s arie ey 43 disable sample clock sss 23 enable sample clock esses 23 event counter aiat eee Os 44 event time stamp directory 30 IDETOEy 4 aie siete to tup te rp aeo Saha itakusha 46 trigger event directory 41 block RAM eerte hero eie 9 BEI32 coe tnam RH RA ER 7 12 board layo t eese 52 J B103 0Y EE E 20 ee H external ii aae ER NUT 10 24 internal cct ertet terere 10 Ee ER 10 CIOCK eT 10 23 CONT00 need eerie tes 60 Configur tioh eoe ENNEN 57 GOHDEChO i 7 Connector TY PES eege u HE EE 66 control dp ratte 1
20. default Each input is terminated with a resistor network 5 pins 4 resistors common pin to socket pin 6 to ground the names of the input sockets are listed in the table below Designation Inputs Resistor Network 4 Clock In RN140A 3 Start RN140B 2 Stop RN140C 1 User in RN140D Page 54 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 8 2 Analog inputs 8 2 1 Input range and impedance configuration for single ended SIS3300 1 Input impedance and range are configured with a set of SMD resistors The input range configuration is a combination of selecting the requried input voltage span and a possible input shift by means of a potentiometer A unit with an input range of 2 5 V 2 5 V anda module with 0 V 5 V both have a span of 5 V which is shifted by 2 5 V to the negative side in the later case e g The table below lists the configuration for ADC channel 1 The other channels are configured with their corresponding resistors R20A R20I for channel 7 e g Voltage span Impedanc R10A R10B R10D R10E R10F R10G R10H R101 e 50 Ohm 50 0 560 1 2k 25 0 560 1 2k 50 Ohm 50 0 560 560 25 0 560 560 1 Kohm 1 2K 0 L 2k T 21 25 0 1 2k 1 2k 50 Ohm 50 680 23 BL 25 680 33 511 50 Ohm 50 1k 15 560 25 1k l5 560 50 Ohm 50 1 2k 15 560 25 1 2k l5 560 o u Ia NIN I lt lt lt lt lt a us 75 Ohm 75
21. document 3 00 27 05 02 Official release 3 01 19 06 02 Removal of side cover for better conduction cooling 3 02 04 07 02 Explanation for single shot wrap mode 3 10 08 09 02 Further extension of wrap mode description SIS3300 SIS3301 differential input schematic configuration 3 20 28 10 02 SIS3301 80 MHz 3 30 12 12 02 SIS3301 100 MHz 3 40 12 08 04 Bug fix in clock speed table for SIS3301 80 03 06 firmware for 8183301 external clock with delay locked loop Page 2 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME Table of contents E e 3 NS ione T us ai qa 6 1 1 Related y een R ea hte e teeth te eig 6 2 De chnical E EE 7 2 1 Key functionality ed iei n oeil e ete E Ic PA d tu ete e e eate db et Ge 7 e UE E 8 2 2 1 Dual channel group 5 20 n pen Er e te ee t ipei EE 9 2 3 Modes ot Operation insu na aro deett p a ER P EU Pr ne e anaes ones 9 2 4 Memory management Deet 6 ran he terr Eee t de E E p EO eie EE teed 9 2 4 1 Single Event Mode inpar cba no aec pbi band odds 9 2 4 2 Mult Event Mode ns nu et eo e a a PO E be abere 9 2 4 3 Dual Bank Mode 2 une tei em go p P bar E pee ete dee rre ier 9 2 5 Clock sources t eie tec De e o b e RERO ER 10 2 5 1 Internal clock 5 8 2 eme e me cr RR BUR P RR e elders 10 2 5 2 External clock eoe ose te cime ERE P rr ree t ee o be rere 10 2 5 3 Random External Clock 2 tno eee et a e OR cra c tee dee es 10 2 6 Aver
22. register holds the values for N M and P as shown in the table below Bit 31 reserved read 0 30 reserved read 0 29 reserved read 0 28 enable pulse mode 27 reserved read 0 26 reserved read 0 25 reserved read 0 24 enable N M mode 23 reserved read 0 20 reserved read 0 19 bit 3 of P 18 bit 2 of P 17 bit 1 of P 16 bit 0 of P 15 reserved read 0 12 reserved read 0 11 bit 3 of N 10 bit 2 of N 9 bit 1 of N 8 bit O of N 7 reserved read 0 4 reserved read 0 3 bit 3 of M 2 bit 2 of M 1 bit 1 of M 0 bit O of M The power up default value reads Ox 00000000 Page 39 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 25 MAX No of Events registers 0x10002C 0x20002C 0x28002C 0x30002C 0x38002C define SIS3300 MAX NO OF EVENTS ALL ADC 0x10002C write only D32 define 8183300 MAX NO OF EVENTS ADC12 0x20002C read write D32 define SIS3300 MAX NO OF EVENTS ADC34 0x28002C read write D32 define SIS3300 MAX NO OF EVENTS ADC56 0x30002C read write D32 define SIS3300 MAX NO OF EVENTS ADC78 0x38002C read write D32 This register is implemented for each channel group and it has to be configured to the same value in all groups what is done most straightforward by writing to the address SIS3300 MAX NO OF EVENTS ALL ADC
23. to memory until an external clock pulse is detected The internal clock will strobe a datum to memory upon recognition of a leading edge on the clock input Random external clock mode is activated by writing 0x800 to the acquisition control register 10 1 3 wrap versus single shot no wrap mode The SIS330x can be operated in single shot no wrap or wrap mode in both single and multi event mode 10 1 3 1 single shot The digitizer will acquire data until the end of event once it is started The first datum is at the beginning of the event the last datum is stored at the end of the event 10 1 3 2 wrap mode The digitizer will acquire data until it is stopped by one of the stop conditions At the end of event the memory write pointer will wrap to the beginning of the event and old data are overwritten by the latest digitized values The memory stop pointer can be at any position within the event after the stop and the data set has to be rearranged after readout to have it in one consecutive block You will have to check the wrap bit in the event directory upon readout to know whether the data from stop pointer to the end of event are valid also what is the case as soon as the memory pointer has wrapped once The first part of the event sits between stop pointer and end of event if the wrap bit had been set and the second portion sits from the start of event until the stop pointer If the stop delay is active the stop delay will run down befor
24. writing the corresponding value to the register Bit 31 unused read as 0 16 unused read as 0 15 Time stamp predivider BIT15 0 Time stamp predivider BITO The power up default value is 0 Note A predivider value of 0 can not be used with firmware V201 Page 26 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 9 Key address general reset 0x20 write define SIS3300_KEY RESET 0x20 write only D32 A write with arbitrary data to this register key address resets the SIS3300 to it s power up state 4 10 Key address VME start sampling 0x30 write define SIS3300 KEY START 0x30 write only D32 A write with arbitrary data to this register key address will initiate sampling on the active memory bank if a bank is armed for sampling 4 11 Key address VME stop sampling 0x34 write define SIS3300 KEY STOP 0x34 write only D32 A write with arbitrary data to this register key address will halt sampling on the active page In Single Event Mode or during the last page the sampling this command will halt the the sampling To Abort a sampling in Multi Event Multibank mode the following cycles have to be executed issue disable autostart issue KEY STOP AUTO BANK SWITCH issue SIS3300 KEY STOP issue clear BX ENABLE Page 27 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME
25. 00 MHz or divided down to lower clock frequencies The table below lists the valid clock settings for the different SIS3300 3301 boards Clock SIS3300 SIS3301 65 100 MHz X 80 MHz 50 MHz 40 MHz 25 MHz 20 MHz 12 5 MHz 6 25 MHz 3 125 MHz SIS3301 80 SIS3301 105 X lt I x X X gt x gt lt gt lt gt Xx 2 5 2 External clock A symmetric external clock NIM level ratio between 45 55 and 55 45 can be fed to the module through a LEMOOO connector An ECL clock over rows A C of the J2 VME backplane can be used as an alternative For optimum performance the clock frequency should be within the specified range for the given ADC chip Module Min sym clock Max sym clock SIS3300 1 MHz 105 MHz SIS3301 65 15 MHz 65 MHz SIS3301 80 15 MHz 80 MHz SIS3301 105 15 MHz 105 MHz 2 5 3 Random External Clock Random external clock mode allows to operate the SIS3300 1 with basically arbitrary external clock pulse trains or slow external clocks The module is clocked with the internal clock typically at 100 MHz and a data word will be stored to memory upon the next leading edge of the internal clock after a leading edge on the external clock input is detected Internal pipelining has to be taken into account the datum will precede the clock by 10 clock ticks i e about 100 ns on a SIS3300 clocking at 100 MHz Page 10 of
26. 00000040 4 KA W Start auto bank switch 0x00000044 4 KA W _ Stop auto bank switch 0x00000048 4 KA W Clear bank memory full 0x0000004C 4 KA W Clear bank 2 memory full 0x00000060 4 R W One wire Id Register SIS3301 V3 05 only 0x00001000 0x1000 BLT32 R Event Time Stamp directory bank 1 0x00002000 0x1000 BLT32 R Event Time Stamp directory bank 2 Event information all ADC groups 0x00100000 4 W only Event configuration register all ADCs 0x00100004 4 W only Trigger Threshold register all ADCs 0x0010001C 4 W only Trigger Flag Clear Counter register all ADCs 0x00100020 4 W only Clock Predivider register all ADCs 0x00100024 4 W only No Of Sample register all ADCs 0x00100028 4 W only Trigger setup register all ADCs 0x0010002C 4 W only Max No of Events register all ADCs 0x00101000 0x1000 BLT32 R Event directory bank 1 all ADCs 0x00102000 0x1000 BLT32 R Eevent directory bank 2 all ADCs Event information ADC group 1 0x00200000 4 R W Event configuration register ADC1 ADC2 0x00200004 4 R W Trigger Threshold register ADC1 ADC2 0x00200008 4 R Bank address counter ADC1 ADC2 0x0020000C 4 R Bank2 address counter ADC1 ADC2 0x00200010 4 R Bank Event counter ADC1 ADC2 0x00200014 4 R Bank Event counter ADC1 ADC2 0x00200018 4 R Actual Sample Value ADCI ADC2 0x00200
27. 01C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00200020 4 R W Clock Predivider register ADC1 ADC2 0x00200024 4 R W No Of Sample register ADC1 ADC2 0x00200028 4 R W Trigger setup register ADC1 ADC2 0x0020002C 4 R W Max No of Events register ADC1 ADC2 0x00201000 0x1000 BLT32 R Event directory bank 1 ADC1 ADC2 0x00202000 0x1000 BLT32 R Event directory bank 2 ADCI1 ADC2 Event information ADC group 2 Page 14 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 0x00280000 4 R W Event configuration register ADC3 ADC4 0x00280004 4 R W Trigger Threshold register ADC3 ADC4 0x00280008 4 R Bank address counter ADC3 ADC4 0x0028000C 4 R Bank2 address counter ADC3 ADC4 0x00280010 4 R Bank1 Event counter ADC3 ADC4 0x00280014 4 R Bank2 Event counter ADC3 ADC4 0x00280018 4 R Actual Sample Value ADC1 ADC2 0x0028001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00280020 4 R W Clock Predivider register ADC3 ADC4 0x00280024 4 R W No_Of_Sample register ADC3 ADC4 0x00280028 4 R W Trigger setup register ADC3 ADC4 0x0028002C 4 R W Max No of Events register ADC3 ADC4 0x00281000 0x1000 BLT32 R Event d
28. 1 Cl EE 54 control ET oet recipe 54 termi nati n u u ites 54 e m a e teens 65 SI E A E E 7 D32 cott ete e eee tio E 7 data formats zec eee terere tee eer 46 delay locked loop 24 DESY ree ipe tt bee rtr 66 differential sd at eme 55 DOS natu Gb adeo dem ut rer 20 DS2430 nce wns eee eae a e 29 edge leading amo eet oc ether 11 trailing a acid Eerad Nia Mees 11 BEPROML paq heces 29 E 9 event counte nadn e het ere Green 44 event directory 31 42 43 63 event 5126 q nan paya E etie ER ec 31 extemal ClOCK TT 24 SEN RE 9 EW STEE Eege AEN 6 60 enr 66 TOST ert oir REPERI ORA need 46 EPGA deua euenit 9 uei EE 56 front p nel x niue ng etes 7 53 GAS Lor eL E eg 13 gate chalay e ieren Ee eege ree 32 PALE MOTE EE 11 geographical addressing 67 GND onera ha a S e a e a EE E 60 BEE 66 hot SWap e rettet crescit 65 67 input ANALOG opone epp es 55 COMMON T 54 USE itte n ERR EE EORR OREMUS 54 input schematics essere 68 Intel ttr eee 20 interrupt bank full ete eek 51 end Of event ee rete eee eine 51 interrupter mode sss eee ee eee 20 interrupter type sone ann Sau ayasa 20 introduction nette eret e retinet 6 IRQ bank full eter eet 21 end of event ee 21 User Input carte ettet Ray 21 TRO Imod acces erc 20 ROAK eee ten ee i 20 RORA teatri 20
29. 2k 0 560 33 2k 0 560 Note defects that are due to in field input range configuration change are not covered by the modules warranty 8 2 2 Input range and impedance for differential SIS3301 The differential version of the SIS3301 has an input impedance of 100 Ohms and an input range of 1 V 1V Page 55 of 72 SIS3300 SIS3301 SIS Documentation SIS GmbH I 65 80 100 MHz FADC VME 8 3 LED s The 8183300 has 8 front panel LEDs to visualise part of the modules status The user and access LED are a good way to check first time communication addressing with the module Color Designator Function Red A Access to SIS3300 VME slave port Yellow P Power Green R Ready on board logic configured Green U User to be set cleared under program control Red SAM Sampling Yellow SRT Start lit with start input or leading edge in gate mode Green STP Stop lit with stop input or trailing edge in gate mode Green TRG Trigger lit if one or more channels are above threshold The on duration of the access sampling start stop and trigger LEDs is stretched to guarantee visibility even under low rate conditions 8 4 PCB LEDs The 8 surface mounted red LEDs D200A to D200H on the top left corner of the component side of the SIS3300 are routed to the control FPGA their use may depend on the firmware design Page 56 of 72 SIS3300 3301 65 80 100 MHz FADCs
30. 34 wntel esee 27 4 12 Key address start Auto Bank Switch mode 0x40 write 28 4 13 Key address stop Auto Bank Switch mode 0x44 write nas 28 4 4 Key address clear BANK1 FULL Flag 0x48 write essent 28 4 15 Key address clear BANK2 FULL Flag 0x4C write sese 28 4 16 One wire Id register 1 0x60 read write SIS3301 V3 05 only 29 4 17 Event Time Stamp directory bank 1 0x1000 0x1ffc read only 30 4 18 Event Time Stamp directory bank 2 0x2000 0x2ffc read only 30 4 19 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 31 4 19 1 Gatechamimng mode uu eebe EE 32 4 19 27 Averaegme mode ipn e b o D ce baignade tes 32 4 19 3 MULETIPEEXER MOBB 5 7 3 nene opm re A pe aides 32 4 19 4 EXTERNAL RANDOM CLOCK MODE A 33 GE WEEN 33 4 20 Threshold registers 0x100004 0x200004 0x280004 0x300004 0x380004 34 421 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C 36 Page 3 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 4 22 Clock Predivider register 0x 100020 0x200020 0x280020 0x300020 0x380020 37 4 23 No Of Sample register 0x100024 0x200024 0x280024 0x300024 0x380024 38 4 24 Trigger setup register regi
31. 47 KE E 36 62 module design ient neret 8 multi event MEMOTY EE 9 multiplexer mode seen 18 61 N 39 HO WIAD C ENEE ENEE ENNEN 62 offset gana sauna upaku usss 58 59 operating conditions a 65 Operatlon a entente au u au 47 50 operation modes sese 9 output bank full e Sle teh 54 Ts ae mee 54 ST Sree Sheesh ha Causa EE e ae 11 18 54 SIS GmbH 65 80 100 MHz FADCs VME USC Lie eege Sg ee e ee 54 P 39 LEE 67 P 7 67 pin assignments T 66 UE LEE 66 P2 clock ame rege 24 PASE c c aaah a t eim E a e au pea 9 PaSe SIZE cues pU eee e bau as 33 PCB nae pep amem 57 67 PIPCME Sickie aries una ne ove dene 26 61 pipelmning ion nin eet tete 10 26 poll b ehe hers 51 POSHISSE assqa ee oem ete tme 62 potentiometer Offset ere 58 power CONSUMPTION esse e ee ee eee eee 65 PECTS SSL cce etc es erede ite tene 62 PROM Go oso e rt tege t ex 60 VAD BE E 46 register acquisition control9 11 23 25 47 48 51 61 62 64 actual sample erit teet 45 clock predivider 37 40 61 COMMON at ERR REIS 19 47 48 description KE 17 event configuration 9 31 firmware revision sese eee eee 19 Id T 29 interrupt configuration 20 21 memory configuration
32. C 8 Oe O a O O O Uo gt G 3 zL struck de x z 00090 Page 53 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 8 1 Control In Outputs The control I O section features 8 LEMOOO connectors with NIM levels Designation Inputs Outputs Designation 4 Clock In _ Clock Out 4 3 Start Ready for Start bank full output 3 2 Stop Ready for Stop bank full output 2 1 User in User out trigger Multiplexer Strobe bank full output 1 The ready for start and ready for stop outputs can be used to interfere with external deadtime logic Ready for start will become active as soon as the sample clock for one of the banks is active Ready for stop will go active as soon as the start signal was seen by the module The external clock must be a symmetric signal unless the module is operated in external random clock mode The width of an external start stop pulse must be greater or equal two sampling clock periods 8 1 1 User input User input functionality was implemented to allow for synchronous recording of one external status bit like chopper on off e g with the ADC data stream The user bin information is recorded with the ADC data see section 4 35 The current status of the logic level is represented by Bit 16 of the status register 8 1 2 Control input termination The control inputs are configured for 50 Q termination i e with 47 Q by
33. SIS Documentation SIS GmbH VME 9 Jumpers Configuration 9 1 Jl The function of J1 depends on the PCB printed circuit board revision level The board revision level is printed in white on the lower edge of the card on the component side as a text of the form SIS3300_V1 e g 9 1 1 SIS3300 V1 Selection of bits 31 28 of the 32 bit A32 address see base address section 9 1 2 SIS3300 V2 and higher The SIS3300 supports several addressing modes the actual mode is selected by jumper array Jl The given mode is selected if its corresponding jumper is in place The four jumper positions are described in the table below The A32 jumper is closest to the modules front panel Jumper Function Factory default GER A32 enable A32 addressing closed c GEO enable geographical addressing open VIPA not implemented yet open a reserved reserved open 9 2 J190 Reset Jumper 5 of jumper array J190 defines the reset behaviour of the SIS3300 upon VME Sysreset If the jumper is closed the module will be reset with VME Sysreset The other fields of the array are unused in the current firmware design HE Jumper Function Factory default Exp H 1 unused open EB 2 enable watchdog closed DD 3 unused open HU 4 unused open 0 0 5 unused open Hu 6 Connect module reset to VME S
34. SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME SIS3300 SIS3301 65 80 100 MHz VME FADCs User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 4 49 0 40 60 87 305 0 Fax 4 49 0 40 60 87 305 20 email info struck de http www struck de Version 3 40 as of 12 08 04 Page 1 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME Revision Table Revision Date Modification 0 01 27 09 00 Generation 1 00 15 01 01 First official release 1 01 17 01 01 Trigger functionality added 1 02 21 01 01 MBLT64 readout 1 03 01 06 01 Bug fix in acquisition register 1 10 01 08 01 Documentation J190 description Design Version 2 added Multiplexer Mode Firmware Revision Register 0x33000102 new bit in Acquisition control register bit 15 MULTIPLEXER Mode new Clock Predivider registers new No_of_Sample registers new Output 1 function in MULTIPLEXER Mode 2 00 29 10 01 V2 hardware revision extended functionality 2 10 05 11 01 extended trigger functionality description 2 11 15 11 01 Bug fixes ADC chip frequency range 3 0x 24 05 02 Prerelease for major functionality firmware upgrade V3 implementation of gate chaining mode introduction of averaging 2e VME readout implementation change in trigger bit behaviour Combination of SIS3300 and SIS3301 manual to one
35. SIS3300 CLOCK PREDIVIDER ADC34 0x280020 read write D32 define SIS3300 CLOCK PREDIVIDER ADC56 0x300020 read write D32 define SIS3300 CLOCK PREDIVIDER ADC78 0x380020 read write D32 This register is implemented for each channel group and it has to be written with the same value Use the address 8183300 CLOCK PREDIVIDER ALL ADC to write to the registers of all channel groups simultaneously The Clock Predivider factor max 255 Oxff is defined by this register It is used in multiplexer mode only Bit Function Default 3 Unused read 0 0 8 Unused read 0 0 H Clock Predivider bit 7 MSB 0 0 Clock Predivider bit 0 LSB 0 The power up default value reads Ox 00000000 Page 37 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 23 No_Of_Sample register 0x100024 0x200024 0x280024 0x300024 0x380024 define SIS3300 NO OF SAMPLE ALL ADC 0x100024 write only D32 define SIS3300 NO OF SAMPLE ADC12 0x200024 read write D32 define 8183300 NO OF SAMPLE ADC34 0x280024 read write D32 define 8183300 NO OF SAMPLE ADC56 0x300024 read write D32 define 8183300 NO OF SAMPLE ADC78 0x380024 read write D32 This register is implemented for each channel group and it has to be written with the same value Use the address 8193300 NO OF SAMPLE ALL ADC to write to the registers of all channel groups simultaneously The No of
36. Sample factor max 255 Oxff is defined by this register It is used in MULTIPEXER mode only Bit Function Default 3 Unused read 0 0 8 Unused read 0 0 7 No_Of_Sample bit 7 MSB 0 0 No_Of_Sample bit 0 LSB 0 The power up default value reads Ox 00000000 Note The value of these registers Clock Predivider No_of_Sample is copied autonomously to the 4 ADC groups As the register is write only the user will have to read back the value from one of the ADC groups in case read back functionality is desired Page 38 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 24 Trigger setup register registers 0x100028 0x200028 0x280028 0x300028 0x380028 define SIS3300 TRIGGER SETUP ALL ADC 0x100028 write only D32 define SIS3300 TRIGGER SETUP ADC12 0x200028 read write D32 define SIS3300 TRIGGER SETUP ADC34 0x280028 read write D32 define SIS3300 TRIGGER SETUP ADC56 0x300028 read write D32 define SIS3300 TRIGGER SETUP ADC78 0x380028 read write D32 This bit register is implemented on the channel group the register S193300 TRIGGER SETUP ALL ADC is used to write to the registers of all channel groups simultaneously The behaviour of the trigger output of the SIS3300 can be controlled by this register The user can select between a N over M under threshold or a pulsed trigger output with pulse width P At the same time the
37. Serial 0x00 6 Number 0x00 7 0x0A Note Module Id and Clock speed are stored in hexadecimal form for better readability the serial number is stored as straight 32 bit decimal value Refer to the PDF data sheet of the DS2430 and the LINUX example program rom_read c on the SIS3301 documentation CDROM for details on the operation of the EEPROM Bit Read function Write function 31 0 not used 16 0 not used 15 BUSY cmd RESET 14 Present cmd WRITE 13 0 cmd READ 12 0 reserved 11 0 reserved 10 0 reserved 9 reserved reserved 8 reserved reserved H read datum bit7 write datum bit7 6 read datum bit6 write datum bit6 5 read datum bit5 write datum bit5 4 read datum bit4 write datum bit4 3 read datum bit3 write datum bit3 2 read datum bit2 write datum bit2 1 read datum bitl write datum bitl 0 read datum bit0 write datum bitO Page 29 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 4 17 Event Time Stamp directory bank 1 0x1000 0x1ffc read only define SIS3300 EVENT TIMESTAMP DIR_BANK1 0x1000 read only D32 BLT32 size 0x1000 The event time stamp directory can be used to measure time between triggers stops in multi event mode A scaler counting the ADC clock is enabled with the first stop hence the time stamp for the first event will read 0 always The counter value of the 24 bit wide scaler is writ
38. TS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 10 2 Power consumption The SIS3300 1 is a single supply design to facilitate operation in any VME environment i e the module does not require special backplanes or non standard VME voltages The power consumption of a two memory bank module digitizing at 100 MHz was measured to be Voltage Current 5V lt 6A 12 V lt 40mA 12V lt DU mA P 32W 10 3 Operating conditions 10 3 1 Cooling Although the SIS3300 1 is mainly a 2 5 and 3 3 V low power design substantial power is consumed by the Analog to Digital converter chips and linear regulators Hence forced air flow is required for the operation of the board The board may be operated in a non condensing environment at an ambient temperature between 10 and 40 Celsius A power up warm up time of some 10 minutes is recommended to ensure equilibrium on board temperature conditions 10 3 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3300 is configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal Page 65 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH l 65 80 100 MHz FADC VME 10 4 Connector types The VME connectors and the two different types of front panel connectors used on the SIS3300 are
39. This register is used in GATE Chaining Multi Event Mode only It limits the number of Events in the GATE Chaining Multi Event Mode ate chaining mode sampling will stop when a the maximum number of events is reached or b the end of bank is reached In this case the last event gate may be incomplete Bit 31 16 15 0 Function unused read back as 0 Max No Of Events The power up default value is 0 Page 40 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 26 Trigger event directory bank 1 0x101000 0x101ffc define SIS3300 EVENT DIRECTORY BANK1 ALL ADC 0x101000 read only D32 BLT32 size 0x1000 This Trigger event directory holds the stop pointer s i e end address 1 of memory bank 1 The directory is 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once i e if the memory pointer has reached the end Event Data End Address D16 DO offset address el E w es nN oo ND Ke lt w nN oo elelea alioi codd ec SISI BISIG 99191919 0x0 T1 T2 T3 TA4 T5 T6 T7 T8 O W O End Address 1 of Event 0 Oxffc T1 T2 T3 TA T5 TG6 T7 T8 O W O End Address 1 of Event 1023 W wrap around bit T1 T8 trigger information ADC 1 ADC 8 1 ADC channel has met trigger criterion for this event 0 ADC channel has not triggered for this event 4 27
40. Trigger event directory bank 2 0x102000 0x102ffc define SIS3300 EVENT DIRECTORY BANK2 ALL ADC 0x102000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 41 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 28 Event directories bank 1 0x201000 0x201ffc 0x281000 0x281ffc 0x301000 0x301 ffc 0x381000 0x381ffc define SIS3300 EVENT DIRECTORY BANK1 ADC12 0x201000 define 8183300 EVENT DIRECTORY BANK1 ADC34 0x281000 define SIS3300 EVENT DIRECTORY BANK1 ADC56 0x301000 define SIS3300 EVENT DIRECTORY BANK1 ADC78 0x381000 read only D32 BLT32 size 0x1000 These arrays are redundant and not used in standard operation use the trigger event directory instead The event directories hold the stop pointer s i e end address 1 of each channel group of memory bank 1 The directories are 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once i e if the memory pointer has reached the end offset address Event Data End Address D16 DO D21 20 D18 D17 D19 D31 24 D23 22 End Address 1 of Event 0 0x0 T2 T1 T2 T1 O End Address 1 of Event 1023 o oO Oxffc W wrap around bit T1 T2 trigger information ADC 1 3 5 7 ADC 2 4 6 8 of channel group 4 29 Event directories bank 2 0x202000 0x202ffc 0
41. age EE 11 2 7 Trigger control pre post start stop and gate mode 11 2 8 Internal Trigger gener ti n oed rh P ee etre ete ete e ie Rete EE E E Ve re Ae 11 29 Time Stamp Memory eto SI eerie rene or Oe ote lee ee tege i e e ete atte 11 210 VME EE 11 211 VMEReado t Speed a l e leis A O eR arte es te BS 12 3 20 ME 13 3 1 Address TTT 14 4 Register Description sising erit e e VU SISTER Ur T SEANCE ed Ed 17 4 1 Control Status Register Ox write read sse 17 4 1 1 PIS AE e EE 18 4 1 2 PIS Ser Fong Walesa hapas esha Sisal A ith AI ei bee e and keene acts 18 4 2 Module Id and Firmware Revision Register 0x4 read 19 4 2 1 Major revisi n numbers S huara o D ee eie e edt e e etre t is 19 4 3 Interrupt configuration register 0x8 eee eee 20 4 3 1 Meu C n 20 44 Interrupt control register 0x C yu La et eerste Eege le tee subs 21 4 5 Acquisition control register 0x10 read write eese eene ener ener nennen 23 4 5 1 Delay locked loop for external clock SIS3301 03 06 seen 24 4 6 Start Delay register 0x14 read write sneri ea eene nennen enne trennen enne nne nennen nnne 25 4 7 Stop Delay register 0x18 t ad Write TTT 25 4 8 Time stamp predivider register KIC 26 4 9 Key address general reset 0x20 Write aaa aaa iisas nennen nennen rennen enne nre nenne nne nne nenne 27 4 10 Key address VME start sampling 0x30 wt 27 4 11 Key address VME stop sampling 0x
42. alue 0 GT unused threshold value 1 LE ADC 1 3 5 7 1 LE ADC 2 4 6 7 default after Reset Ox3fff3fff Page 34 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME The function of the trigger setup register is illustrated with the drawing below Pri gt M lt N gt N OV OxFFF Is eO j Threshold 5V 0x0 COMPARATOR GT valid maa rii COMPARATOR LE me aia SSE _ LLL GT N M TRIGGER valid C77 nad puo mi LE N M TRIGGER mvaid valid valid GT N M TRIGGER PUL S LE N M TRIGGER PULS 7 aia i i P Example LEMO Out Page 35 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 4 21 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C define SIS3300 TRIGGER FLAG CLR CNT ALL ADC 0x10001C write only D32 define SIS3300 TRIGGER FLAG CLR CNT ADC12 0x20001C read write D32 define SIS3300 TRIGGER FLAG CLR CNT ADC34 0x28001C read write D32 define SIS3300 TRIGGER FLAG CLR CNT ADC56 0x30001C read write D32 define SIS3300 TRIGGER FLAG CLR CNT ADC78 0x38001C read write D32 This register is implemented on the base of the channel group Use the address 8193300 TRIGGER FLAG CLR CNT ALL ADC to write to the registers of all channel groups simultaneously The Trigger Flag bit is set as soon as an ADC channel meets the trigg
43. at for SIS3300 offset address ADC1 3 5 7 ADC2 4 6 8 D31 D30 29 D28 D27 16 D15 D14 13 D12 D11 0 0x0 U 00 OR bit 12 bit data G 00 OR bit 12 bit data Ox7fffc U 00 OR bit 12 bit data G 00 OR bit 12 bit data Data format for SIS3301 offset address ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0x0 U OR bit 14 bit data G OR bit 14 bit data Ox7fffc U OR bit 14 bit data G OR bit 14 bit data Shorthand Explanation U status of user bit if enabled 0 otherwise OR out of range set with over or underflow 0 otherwise G set on the first sample in Gate Chaining Mode 0 otherwise 4 36 Bank 2 memory 0x600000 Ox7ffffc define 8183300 MEMBASE BANK2 ADC12 0x600000 define 8183300 MEMBASE BANK2 ADC34 0x680000 define 8183300 MEMBASE BANK2 ADC56 0x700000 define SIS3300 MEMBASE BANK2 ADC78 0x780000 Bank 2 memory is installed to allow for parallel readout from one memory bank while the other memory bank is acquiring data The second memory bank has the same structure as bank 1 Page 46 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 5 Description of Start Stop and Gate operation modi 5 1 Start stop mode Different start and stop conditions can be used in combination with start stop mode as illustrated in the start and stop logic summaries Note LEMO o
44. ations Bit Function Reading 31 Module Id Bit 15 30 Module Id Bit 14 29 Module Id Bit 13 3 28 Module Id Bit 12 27 Module Id Bit 11 26 Module Id Bit 10 25 Module Id Bit 9 3 24 Module Id Bit 8 23 Module Id Bit 7 22 Module Id Bit 6 21 Module Id Bit 5 U 20 Module Id Bit 4 19 Module Id Bit 3 18 Module Id Bit 2 17 Module Id Bit 1 Q l 16 Module Id Bit 0 15 Major Revision Bit 7 14 Major Revision Bit 6 13 Major Revision Bit 5 12 Major Revision Bit 4 11 Major Revision Bit 3 10 Major Revision Bit 2 9 Major Revision Bit 1 8 Major Revision Bit 0 7 Minor Revision Bit 7 6 Minor Revision Bit 6 5 Minor Revision Bit 5 4 Minor Revision Bit 4 3 Minor Revision Bit 3 2 Minor Revision Bit 2 1 Minor Revision Bit 1 0 Minor Revision Bit 0 4 2 1 Major revision numbers Find below a table with major revision numbers used to date Major revision number Application user 0x01 to OxOF Generic designs 0x10 Amanda Page 19 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 4 3 Interrupt configuration register 0x8 define SIS3300 IRQ CONFIG 0x8 read write D32 This read write register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are foreseen for the time being three of
45. e 54 Ka 36 62 KEE EE 41 42 Page 72 of 72
46. e single width 6U VME card which has no special i e non standard VME voltage requirements Dual memory bank functionality in conjunction with multi event memory structure and a range of trigger options give the unit the flexibility to cover a variety of applications Applications comprise but are not limited to e digitization of slow detectors like calorimeters e spectroscopy with Ge detecors e beam profile monitor readout e serialized readout of u Strip detector data As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals htm 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis3300firm htm The JTAG firmware installation procedure is described in http www struck de sis3300_jtagprog pdf Page 6 of 72 SIS Documentation SIS3300 3301 65 80 100 MHz FADCs VME SIS GmbH 2 Technical Properties Features 2 1 Key functionality Find below a list of key features of the SIS3300 and SIS3301 digitizers SIS3300 SIS3301 65 SIS3301 80 SIS3301 105 Sampling rate per channel 105 MHz 65 MHz 80 MHz 105 MHz Minimum symmetric clock 1 MHz 15 MHz 15 MHz 15 MHz Res
47. e the digitizer will actually stop to acquire data and this functionality can be used to have both data from before and after the stop in memory Example e multi event mode e event size 1024 i e 128 events per bank e stop delay 512 The digitizer will have 512 samples pre and 512 samples post trigger recorded After rearrangement of the data see above the location of the stop will be in the middle of the array Wrap mode will be used in conjunction with multi event and auto start mode in most cases to start the digitizer with minimum delay after an event has been acquired Page 62 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME no wrap event N stops at end of page Start Stop Event N 1 Event N Event N 1 wrap event N started write pointer cycling within event DE GE E Event N 1 Event N Event N 1 wrap event N stopped stop pointer at arbitrary position within event Stop Event N 1 Event N Event N 1 The memory write pointer will increment with the ADCs clock and the digitized values are stored to the addressed memory location The wrap bit will be set W 1 in the event and trigger event directory for the given event if the pointer has wrapped around at least once In that case the event is split as illustrated in the lowest trace below If the wrap bit is not set W 0 the entries from the be
48. enabled sampling stops automatically at the end address of each page e in Multi Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop for each Event 6 5 End of Sampling clear arm disable Sample Clock e in single event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling one event e in multi event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling last event The user software can poll on the status of the sample clock enable bit in the acquisition control register or use the end of event or bank full interrupt conditions Page 51 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 7 Board layout A printout of the silk screen of the component side of the PCB is shown below PAS3 Wa 21 7 wanna 7 L D200A EES i si t et aai ua GAC BEE HIE EE Lis H HRE TT C170H LS srel Sie Gap 33 JCI M I Oss GmbH 02 2000 www struck de Page 52 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 8 Front panel The SIS3300 is a single width 4TE 6U VME module A sketch of the SIS3300 left hand side and SIS3301 front panels without handles is shown below A SIS3301 ADC O Offset 100MHZ AD
49. er criterion This flag remains latched until the next event start i e it will not be cleared as new ADC data which do not meet the trigger criterion come in with Wrap mode active The Trigger Flag Clear Counter register allows you to define a number of samples after which the Trigger Flag bit will be cleared unless a new trigger occurred A counter for the given ADC channel is preloaded with the value of the Trigger Flag Clear counter register when the trigger criterion for this channel is met Consecutive sampling clocks will decrement the counter and the Trigger Flag bit will be cleared as soon as the counter reaches 0 If a new trigger occurs before the counter has reached 0 it will be reloaded with the value from the register retrigger Note typically the user may want to set the value of the Trigger Flag Clear counter register to the memory page size but this is not mandatory The Trigger Flag Clear Logic is disabled if the counter is loaded with O power up default Bit 31 16 15 0 Function unused read back as 0 Trigger Flag Clear counter register The power up default value is 0 Page 36 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 22 Clock Predivider register 0x100020 0x200020 0x280020 0x300020 0x380020 define SIS3300 CLOCK PREDIVIDER ALL ADC 0x100020 write only D32 define SIS3300 CLOCK PREDIVIDER ADC12 0x200020 read write D32 define
50. f the unarmed armed sampling state as long as a sampling clock is distributed on the ADC board internal clock or active clocking external clock For SIS3300 ADC 1 3 5 7 ADC2 4 6 8 D31 29 D28 D27 16 D15 13 D12 D11 0 000 OR bit 12 bit data 000 OR bit 12 bit data For SIS3301 ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0 OR bit 14 bit data 0 OR bit 14 bit data OR Out of range set with over or underflow Page 45 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 4 35 Bank 1 memory 0x400000 Ox5ffffc define 8183300 MEMBASE BANK1 ADC12 0x400000 define SIS3300 MEMBASE BANK1 ADC34 0x480000 define SIS3300 MEMBASE BANK1 ADC56 0x500000 define SIS3300 MEMBASE BANK1 ADC78 0x580000 write D32 read D32 BLT32 MBL64 2eVME size 0x80000 Bank memory is divided into 4 channel groups of 128 KSamples each i e 512 KByte deep for every channel group 2MByte in total The 32 bit wide memory locations hold the data of 2 ADCs each Readout can be done with D32 BLT32 MBLT64 or 2eVME for memory tests D32 write cycles only are supported Notes e FIFO block transfer cycles i e readout from a constant VME address in block transfer are supported from every channel group internal 17 bit address counter A18 to A2 e 2eVME cycles have to start on a 0x100 boundary 0x0 0x100 0x200 Data form
51. ginning of the event page up the the stop pointer are valid only The rest of the page event may hold arbitrary data from earlier acquisition cycles in that case sampled data invalid data 1023 i write pointer W 0 1023 write pointer Wz1 1023 2nd part of signal 1st part of signal write pointer stop address event directory Page 63 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 10 1 4 Auto bank switch mode Auto bank switch mode was introduced for efficient use of the two memory banks on acquisition The mode is activated by issuing a KEY_START_AUTO_BANK_SWITCH after the feature was activated by setting bit 2 in the acquisition control register The bank full flags B1_FULL and B2_FULL are cleared with the KEY at the same time a first start is generated if AUTOSTART is enabled also Data will be acquired into memory bank 1 until the bank is full At this point the flag B1_FULL will be set and acquisition changes over to bank 2 if the flag B2_FULL is not set The user can read out data from bank 1 in parallel to ongoing acquisition into bank 2 and clear the B1_FULL flag after the readout was completed As soon as memory bank 2 is filled acquisition will be handed over to bank 1 again if B1_FULL has been cleared already The active memory bank will acquire data until the bank is filled if a KEY STOP_AUTO_BANK_SWITCH is issued Page 64 of 72 SIS Documentation S
52. identify the four channel groups 4 19 1 Gate chaining mode Gate chaining mode was implemented to allow for effective acquisition of small events of arbitrary length Sampling in gate chaining mode will stop when e Maximum number of events see 4 25 is reached e End of bank is reached the last event gate may be incomplete in this case The first data word of a gate is marked with a 1 in the G ate bit in memory refer to the data format table in section 4 35 For up to 1024 events the information in the event directory is valid also For gate chaining mode you have to a enable multi event mode b enable gate chaining mode The deadtime between two gates is 8 clock ticks Note the page size bits 2 0 of the event configuration are ignored in gate chaining mode as the event size is defined by the gate length of the individual gate pulses which does not have to be constant 4 19 2 Averaging mode Averaging mode is implemented to improve the signal to noise ratio in lower speed digitization applications N consecutive samples are summed up in the FPGAs of the dual channel groups Averaging mode is activated by specifying a non zero value for bits 18 16 of the event configuration register s Average Bit 2 Average Bit 1 Average Bit averaged samples 0 0 0 no average U 0 1 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 4 19 3 MULTIPLEXER MODE Multi
53. irectory bank 1 ADC3 ADC4 0x00282000 0x1000 BLT32 R Event directory bank 2 ADC3 ADC4 Event information ADC group 3 0x00300000 4 R W Event configuration register ADC5 ADC6 0x00300004 4 R W Trigger Threshold register ADC5 ADC6 0x00300008 4 R Bank address counter ADC5 ADC6 0x0030000C 4 R Bank2 address counter ADC5 ADC6 0x00300010 4 R Bank Event counter ADC5 ADC6 0x00300014 4 R Bank Event counter ADC5 ADC6 0x00300018 4 R Actual Sample Value ADC1 ADC2 0x0030001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00300020 4 R W Clock Predivider register ADC5 ADC6 0x00300024 4 R W No_Of_Sample register ADC5 ADC6 0x00300028 4 R W Trigger setup register ADCS ADC6 0x0030002C 4 R W Max No of Events register ADCS ADC6 0x00301000 0x1000 BLT32 R Event directory bank 1 ADC5 ADC6 0x00302000 0x1000 BLT32 R Event directory bank 2 ADCS ADC6 Event information ADC group 4 0x00380000 4 R W Event configuration Register ADC7 ADC8 0x00380004 4 R W Trigger Threshold register ADC7 ADC8 0x00380008 4 R Bank address counter ADC7 ADC8 0x0038000C 4 R Bank2 address counter ADC7 ADC8 0x00380010 4 R Bank Event counter ADC7 ADC8 0x00380014 4 R Bank Event counter ADC7 ADC8 0x00380018 4 R Actual Sample Value ADC7 ADC8 0x0038001C 4 lt R W Trigger Flag Clear Counter register ADCI ADC2 0x00380020 4 R W Clock Predivider register ADC7 ADC8 0x00380024 4 E R W No Of Sa
54. limited in single event operation to match the requirements of the given application The memory configuration is defined through the memory configuration register while bank handling on dual memory bank modules is under control of the acquisition control register 2 4 1 Single Event Mode The full memory of 128 K Samples of the SIS3300 1 is used as one big circular buffer or as single shot memory in single event mode unless memory size is limited by the event configuration register 2 4 2 Multi Event Mode The memory can be divided in up to 1024 pages or events to make the acquisition of shorter signals more efficient The stop pointers for the individual page can be retrieved from the event directory In auto start mode the ADC advances to the next page and starts sampling automatically 2 4 3 Dual Bank Mode Dual bank mode Bank Switch mode is available on cards except SIS3300 V1 PCBs The single multi event selection will influence both memory banks in the same fashion Data from the inactive bank can be readout while the other bank is acquiring new data Page 9 of 72 SIS3300 SIS3301 65 80 100 MHz FADC SIS Documentation SIS GmbH I VME 2 5 Clock sources The SIS3300 3301 features 3 basic clock modes e Internal clock e External symmetric clock e External random clock 2 5 1 Internal clock The internal clock is generated from an on board 40 or 50 MHz quartz It is either doubled by a delay locked loop to 80 1
55. mple register ADC7 ADC8 0x00380028 4 R W Trigger setup register ADC7 ADC8 0x0038002C 4 R W Max No of Events register ADC7 ADC8 0x00381000 0x1000 BLT32 R Event directory bank 1 ADC7 ADC8 0x00382000 0x1000 BLT32 R Event directory bank 2 ADC7 ADC8 Bank memory 0x00400000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADCI ADC2 0x00480000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC3 ADC4 0x00500000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC5 ADC6 0x00580000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC7 ADC8 Page 15 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME Bank 2 memory 0x00600000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADCI ADC2 0x00680000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC3 ADC4 0x00700000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC5 ADC6 0x00780000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC7 ADC8 W in D32 only for memory test e g Note 1 The event information is identical for the four ADC groups unless the module has a hardware problem hence it will be sufficient for normal operation to retrieve the needed information from one group only Note 2 MBLT64 and 2eVME read access is supported from the memory banks only Page 16 of 72 SIS Documentation SIS3300 3301 SIS GmbH
56. n the design n ees LI Bj 588531 ENSE al cur caooF BERE 5 Eoo conus ss GmbH D www Page 59 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 9 4 JTAG The SIS3300 on board logic can load its firmware either from two serial PROMs or via the JTAG port on connector CONIOO A list of firmware designs can be found under http www struck de sis3300firm htm Hardware like the XILINX HW JTAG PC in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG connector is a 9 pin single row 1 10 inch header the pin assignment on the connector can be found in the table below Pin Short hand Description 1 VCC Supply voltage 2 GND Ground 3 nc not connected cut to avoid polarity mismatch 4 TCK test clock 5 nc not connected 6 TDO test data out 7 TDI test data in 8 nc not connected 9 TMS test modus Page 60 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 10 Appendix 10 1 Data acquisition modes 10 1 1 Multiplexer mode Multiplexer mode was implemented to facilitate data acquisition with external multiplexing hardware One of the outputs of the SIS3300 can be used to control the external multiplexing circuitry Multiplexer mode is activated by setting Bit 15 of the acquisition control register Upon a start external or via VME key add
57. nments The SIS3300 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing PCB revisions V2 and higher and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GAO GND 11 RESP GA1 12 GND GND 13 GA2 14 GND GND 15 GA3 16 GND GND 17 GA4 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND GND 31 GND 1 GND 1 32 GND VPC 1 GND VPC 1 Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 67 of 72 SIS GmbH VME SIS3300 SIS3301 65 80 100 MHz FADC SIS Documentation 10 7 Input Schematics 10 7 1 SIS330x single ended 3001 001 S001 ATIS TIO n rmana Ant Amt soo ru Aer At toot 3o
58. olution 12 bit 14 bit 14 bit 14 bit Analog bandwidth gt 80 MHz 35 MHz 40 MHz 70 MHz Typical pedestal variance 0 7 bit 1 1 bit 1 1 bit 1 1 bit Differential input version X X X 2 x 128 KSample default X X X X 2 x 512 KSample option X X X limited for better resolution with symmetric input range Common properties of all boards are Geographical addressing mode in conjunction with VME64x backplane e 8 channels e special clock modes clock prescaling external arbitrary clock L e external internal clock e multi event mode e N sample averaging N 2 4 8 128 e Read on the fly actual sample value e pre post trigger option e Two independent memory banks e trigger generation e 4NIM control inputs 4 NIM control outputs e A32 D32 BLT32 MBLT64 2eVME e e Hot swap in conjunction with VME64x backplane e VME64x Connectors e VME64x Front panel e VME64x extractor handles on request e F1002 compatible P2 row A C assignment e 5 V 12V and 12 V VME standard voltages channel to channel crosstalk below noise i e invisible in Fourier spectrum Note The SIS3300 1 shall not be operated on P2 row A C extensions like VSB e g due to the compatibility to the F1001 FADC modules clock and start stop distribution scheme Page 7 of 72 SIS Documentation SIS3300 SIS3301 65 80 100 MHz FADC SIS GmbH VME 2 2 Module design The 8183300 consists of four identical gr
59. oups of 2 ADC channels and a control section as shown in the simplified block diagram below System Clock Front Panel Control O VME Interface and Control FPGA Clock Distribution VMEBus Dual Channel Group 4 Channels 7 and 8 Dual Channel Group 3 Channels 5 and 6 Dual Channel Group 2 Channels 3 and 4 Dual Channel Group 1 Channels 1 and 2 Page 8 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 2 2 1 Dual channel group Two ADC channels form a group which memory is handled by one Field Programmable Gate Array FPGA 12 14 32 FPGA Event Directory 2 3 Modes of Operation The SIS3300 was developed with maximum flexibility in mind The FPGA based design of the card allows to meet the requirements of many readout applications with dedicated firmware designs in the future The initial firmware is supposed to furnish you with an easy to use yet powerful high speed high resolution Flash Analog to Digital Converter FADC implementation that covers many everyday analog to digital applications ADC 1 Gd 2 4 Memory management The individual memory bank s can be used either as one contiguous memory or as a subdivided multi event memory In addition memory depth can be
60. panel start stop or gate mode operation The external stop signal or trailing edge of the gate will be delayed by the value of the register 2 clocks if the stop delay is enabled in the acquisition control register Bit 32 unused read as 0 16 unused read as 0 I5 STOP DELAY BITI5 0 STOP DELAY BITO The power up default value is 0 Page 25 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME Note The user can generate a gate of defined length in clock ticks by fanning a short pulse to the start and stop input with start stop mode active stop delay enabled and the stop delay register programmed to the desired gate width Pipelining will have to be taken into account i e the digitised signal is about 40 ns with the module sampling at 100 MHz ahead of the respective control signal a fact that can be used in external trigger decisions For longer external trigger decisions one can consider to pipeline the ADC data in the FPGA in future firmware revisions before storing them to memory 4 8 Time stamp predivider register 0x1C define SIS3300 TIMESTAMP PREDIVIDER Ox1C read write D32 The read write time stamp predivider register is used to define a prescale factor for the frequency of the time stamp counter The time stamp counter counts at the clock rate with the time stamp predivider value of 0 and 1 a prescale factor of 2 65535 is selected by
61. plexer mode was implemented to synchronize data acquisition of the SIS3300 1 with slow external multiplexing hardware Refer to section 10 1 1 for a description of this acquisition scheme Both bit 15 of the acquisition control register and bit 15 of the event configuration register have to be set to acquire data in multiplexer mode Page 32 of 72 SIS3300 3301 SIS Documentation SIS GmbH 65 80 100 MHz FADCs VME 4 19 4 EXTERNAL RANDOM CLOCK MODE This mode allows for sampling at arbitrary low and non symmetric external clock The digitizer is set up for internal clock and will strobe one datum to memory with the leading edge of the internal clock cycle that follows the leading edge of an external clock pulse as illustrated below Pipelining between the actual analog input signal and the value stored to memory has to be taken into account Both bit 11 of the acquisition control register and bit 11 of the event configuration register have to be set to acquire data in external random clock mode External Clock e E H E ee Internal Clock K IERE e ESSE E D EC ER EE RER e b has Clock to Memory epe AA 4 19 5 Page size The page event size is defined by the 3 page size bits as follows Page size Page size Page size Page size Number of divisions Bit 2 Bit 1 Bit 0 Events Bank 0 0 0 128 K Samples 1 0 0 1 16K Samples 8 0 1 0 4 K Samples 32 0 1 1 2 K Samples 64 1 0 0 1
62. r upon armed 20 Non inverted trigger output 19 Disable reserved 3 Status P2 SAMPLE IN 18 Enable user output disable trigger output Status P2 RESET IN 17 Clear user output Status P2 TEST IN 16 Switch off user LED Status User Input 15 Set reserved 15 Status Control 15 14 Set reserved 14 Status Control 14 13 Set reserved 13 Status Control 13 12 Set reserved 12 Status Control 12 11 Set reserved 11 Status Control 11 10 set bank full pulse to output 3 Status Bank full pulse on LEMO output 3 9 set bank full pulse to output 2 Status Bank full pulse on LEMO output 2 8 set bank full pulse to output 1 Status Bank full pulse on LEMO output 1 highest priority 7 Set reserved 7 Status Control 7 6 Enable internal trigger routing Status trigger routing l to input 0 don t route 5 Activate trigger upon armed and started Status trigger generation 1 armed and started 0 armed 4 Invert trigger output Status trigger output inversion 1 inverted O straight Page 17 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 3 Enable reserved 3 Status reserved 2 Enable trigger output disable user output multiplexer mode 0 Status of user trigger output 1 trigger output O user output multiplexer mode 1 output set by multiplexer out pulse 1 Set user output if bit 2 is not set Status User Output 1 output on O output off 0 Switch on user LED
63. ration of the digitization process Like the control register it is implemented in a J K fashion read write D32 Bit Write Function Read 31 Clear multiplexer mode 0 30 Clear Clock Source Bit2 0 29 Clear Clock Source Bitl 0 28 Clear Clock Source But 0 27 Disable external clock random mode 0 26 Disable front panel gate mode not start stop 0 25 Disable P2 Start Stop logic 0 24 Disable front panel LEMO start stop logic 0 23 Disable external stop delay Bank 2 full 22 Disable external start delay Bank 2 busy 2 Disable multi event mode Bank 1 full 0 Enable sample clock will be cleared with end of event Enable sample clock will be cleared at end of bank only i e with last page of memory 20 Disable Autostart in multi event mode only Bank 1 busy 19 Switch off delay locked loop for external clock 0 SIS3301 03 06 only 18 Disable auto bank switch mode Bank switch busy 17 Disable sample clock for memory bank 2 disarm sampling 0 16 Disable sample clock for memory bank 1 disarm sampling ADC BUSY 15 Set multiplexer mode Status multiplexer mode 14 Set clock source Bit 2 Status clock source Bit 2 13 Setclock source Bit 1 Status clock source Bit 1 12 Setclock source Bit 0 Status clock source Bit 0 11 Enable external clock random mode Status external clock random mode 10
64. ress the analog input will be latched to memory after ON 10 clock cycles At the same time a pulse of width one clock cycle will be generated on ouput 1 Acquisition will terminate after M samples The ADC has an internal pipeline of 12 Clock cycles Note The minimum value for the Predivider register value is 4 Example Assume one multiplexing cycle consists of 20 words The analog signal will become valid after 11 us and will be written to memory after 12 us Set internal Sampling clock to 12 5 MHz Clock cycle 80 ns Preset Predivider register to 0x96 150 150x 80 ns 12 us Preset No Of Sample register to 0x14 20 Write 0x8000 set Bit 15 to acquisition control register SIS3300 Start Input 3 Start Output 1 Next clock Puls Clear Next MUX D Analog Input Analog Inputs Start NIM L Output 1 NIM write to RAM f JL ek IL address 0i 2i Illustration of multiplexer mode Page 61 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME 10 1 2 Random external clock mode The minimum clock frequency of the analog to digital converter chips of the SIS3300 and 3301 is limited Random external clock mode was implemented to allow to acquire data at arbitrary low clock frequencies and irregular clock The digitizer will sample at the selected internal clock speed 50 MHz e g but no data are stored
65. rupt configuration register VME IRQ Level and Vector type of IRQ requester e define in Interrupt control register enable IRQ source e define in Acquistion register Set Clock source Set Start Stop or Gate mode Enable Disable P2 External Start Stop Enable Disable LEMO External Start Stop Enable Disable External Stop Delay Enable Disable External Start Delay Set Single or Multi Event Mode if Multi Event then enable disable Autostart e define in Event configuration register Enable Disable Autostop at end address of Page Set Page size 6 2 Arm for sampling e define in Acquistion register Enable Sample Clock for Memory Bank or Bank 6 3 Start Sampling e in Single Event mode Issue key Start or External Start e in Multi Event mode with Autostart disabled Issue key Start or External Start for each Event e in Multi Event mode with Autostart enabled Issue key Start or External Start for the first Event only Note activation of auto bank switch mode with multi event mode enabled will start sampling automatically Page 50 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 6 4 Stop Sampling Event e in Single Event mode with Autostop enabled sampling stops automatically at the end address of the page e in Single Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop e in Multi Event mode with Autostop is
66. ster The maximum number of events is defined by the size of the event directory which has 1024 entries The maximum number of events is limited to 65535 in gate chaining mode to allow for shorter gates also Bit function 3 unused read 0 20 unused read 0 19 Event_CONF Bit 19 reserved function 18 Average Bit 2 17 Average Bit 1 16 Average Bit 0 15 MULTIPLEXER MODE 14 Event CONF Bit 14 reserved function 13 Event CONF Bit 13 reserved function 12 1 former enable trigger event directory 11 EXTERNAL CLOCK RANDOM MODE 10 Event CONF Bit 10 reserved function 9 Channel Group ID Bit 1 Channel Group ID Bit 0 Event_CONF Bit 7 reserved function Event_CONF Bit 5 reserved function ENABLE GATE CHAINING MODE 8 7 6 Event CONF Bit 6 reserved function 5 4 3 Enable Wrap around mode no address auto stop 0 Autostop at end of page 1 Wrap around page until STOP External or KEY 2 Page size Bit 2 1 Page size Bit 1 0 Page size Bit 0 Page 31 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME The power up default values of the registers are SIS3300 EVENT CONFIG ADC12 0x00001000 SIS3300 EVENT CONFIG ADC34 0x00001100 SIS3300 EVENT CONFIG ADC56 0x00001200 SIS3300 EVENT CONFIG ADC78 0x00001300 i e the two channel group ID bits
67. sters 0x100028 0x200028 0x280028 0x300028 0x380028 39 4 25 MAX No of Events registers 0x 10002C 0x20002C 0x28002C 0x30002C 0x38002C 40 4 26 Trigger event directory bank 1 0x101000 0x101ffc eene enne 41 4 27 Trigger event directory bank 2 0x102000 0x IO 41 4 28 Event directories bank 1 0x201000 Ox201ffc 0x281000 Ox281ffc 0x301000 0x301ffc 0x38 1000 E 42 4 29 Event directories bank 2 0x202000 0x202ffc 0x282000 0x282ffc 0x302000 0x302ffc 0x332000 0x382ffC NEE 42 4 30 Bank 1 address counter 0x200008 0x280008 0x300008 0x380008 43 4 31 Bank address counter 0x20000C 0x28000C 0x30000C 0x38000C 43 4 32 Bank 1 event counter 0x200010 0x280010 0x300010 0x380010 44 4 33 Bank 2 event counter 0x200014 0x280014 0x300014 0x380014 44 4 34 Actual Sample registers 0x200018 0x280018 0x300018 0x380018 45 4 35 Bank 1 memory 0x400000 Ox5ffffc s sese eee 46 4 36 Bank 2 memory 0x600000 Ox 7ffffc s sese eee 46 5 Description of Start Stop and Gate operation modi 47 5 1 Start Stop Modea a r EE n a E E EE aE A E
68. ten to the corresponding location for subsequent events offset address Time Stamp D23 D0 0x0 Time Stamp 0 Oxffc Time Stamp 1023 4 18 Event Time Stamp directory bank 2 0x2000 0x2ffc read only define SIS3300 EVENT TIMESTAMP DIR BANK2 0x2000 read only D32 BLT32 size 0x1000 As for bank 1 offset address Time Stamp D23 D0 0x0 Time Stamp 0 Oxffc Time Stamp 1023 Page 30 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 19 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 define SIS3300 EVENT CONFIG ALL ADC 0x100000 write only D32 define SIS3300 EVENT CONFIG ADC12 0x200000 read write D32 define SIS3300 EVENT CONFIG ADC34 0x280000 read write D32 define 8183300 EVENT CONFIG ADC56 0x300000 read write D32 define SIS3300 EVENT CONFIG ADC78 0x380000 read write D32 This register is implemented for each channel group and it has to be written with the same value the best way is to make use of the address 8193300 EVENT CONFIG ALL ADC to write to the registers of all channel groups simultaneously The number of memory divisions events is defined by this register in multi event mode The lowest three bits define the number of memory divisions as listed in the table below On dual bank units both memory banks will be affected by the configuration of the event configuration regi
69. ter is implemented on the channel group base but the information is redundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 16 15 0 Function unused read back as 0 event counter The event counter is not in a defined state after power up or Key Reset 4 33 Bank 2 event counter 0x200014 0x280014 0x300014 0x380014 define SIS3300 BANK2 EVENT CNT ADC12 0x200014 read only D32 define SIS3300 BANK2 EVENT CNT ADC34 0x280014 read only D32 define SIS3300 BANK2 EVENT CNT ADC56 0x300014 read only D32 define SIS3300 BANK2 EVENT CNT ADC78 0x380014 read only D32 Same as bank 1 event counter but for bank 2 of ADC groups 1 4 Page 44 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 34 Actual Sample registers 0x200018 0x280018 0x300018 0x380018 define SIS3300_ACTUAL SAMPLE VALUE ADC12 0x200018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC34 0x280018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC56 0x300018 read only D32 define SIS3300 ACTUAL SAMPLE VALUE ADC78 0x380018 read only D32 Read on the fly of the actual converted ADC values The registers are updated with every ADC clock unless a concurrent VME read access is pending The register contents is refreshed and can be read any time i e they are updated independent o
70. the bank full pulse by setting bit 9 of the control register 5 3 Start logic summary The diagram below illustrates the implemented start conditions of the SIS3300 1 Autostart LEMO Start In P2 Sample In VME Key Start Note Condition Register Comment G Bit 8 1 Acquisition Control Enable front panel start stop logic ne Bit 9 1 Acquisition Control Enable P2 start stop logic s Bit 6 1 Acquisition Control Start delay enable A Bit 6 0 Acquisition Control No start delay Page 48 of 72 SIS Documentation SIS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 5 4 Stop logic summary The diagram below illustrates the implemented stop conditions of the SIS3300 1 5 LEMO Start In trailing edge a MUX Internal Trigger LEMO Stop In STOP P2 Reset In DELAY STOP VME Key Stop Autostop Note Condition Register Comment g Bit 8 1 Acquisition Control Enable front panel start stop logic 72 Bit 9 1 Acquisition Control Enable P2 start stop logic e Bit 7 1 Acquisition Control Stop delay enable 4 Bit 7 0 Acquisition Control No stop delay E Bit 10 0 Acquisition Control use start stop mode Bit 10 1 use gate mode 6 Bit 6 1 Control Route trigger Page 49 of 72 SIS Documentation SIS3300 SIS3301 65 80 100 MHz FADC SIS GmbH L VME 6 Operation 6 1 Configuration e Issue key reset e define in Inter
71. them are associated with an interrupt condition the fourth condition is reserved for future use The interrupter type is DO8 4 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again ROAK IRQ mode can be used in conjunction with the University of Bonn LINUX Tundra Universe II driver by Dr J rgen Hannappel on Intel based VME SBCs Bit Function Default 31 0 Se 0 16 0 15 0 14 0 13 0 12 RORA ROAK Mode 0 RORA 1 ROAK 0 11 VME IRQ Enable 0 IRQ disabled 1 IRQ enabled 0 10 VME IRQ Level Bit 2 0 9 VME IRQ Level Bit 1 0 8 VME IRQ Level Bit 0 0 7 IRQ Vector Bit 7 placed on D7 during VME IRQ ACK cycle 0 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 0 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 0 4 IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 0 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle 0 2 IRQ Vector Bit
72. top trigger condition end of event writes the counter value into Time Stamp Memory 2 10 VME Interrupts Two registers the Interrupt configuration and the Interrupt control register are implemented for interrupt setup and control Four Interrupt sources are implemented External User Input LEMO input 1 End of event End of last event in multievent mode Memory bank full in bank switch mode Dual bank Page 11 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH l 65 80 100 MHz FADC VME 2 11 VME Readout Speed The VME interface is optimized for readout speed An internal FIFO pipeline structure allows for high speed readout in block transfer mode BLT32 MBLT64 2e VME The timings below were measured with the SIS3100 VME master and the SIS3300 SIS3301 VME Slave The upper scope trace shows the VME signal DS1 data strobe low active The VME Master asserts the DS1 to request read data The lower signal shows the VME signal DTACK Data Acknowledge low active The VME Slave asserts the DTACK to acknowledge that the data is valid on VME Tek Run TRI Hi Res uar A 1181s 3 7840s Edge Slope I t I SIS330x DS to DTACK 30 40ns TW 32bit every 120ns_ gt 33MByte sec d ANE M EB z 2 00V w Ch2 2 00 V M 100ns Chil 1 84 V Source Coupling ID level Mode Edge eni c X 1 84 V Holdoff Tek Run 100MS s Hi Res m i EE i d SIS330x
73. urce 3 Status enable source 3 read as 1 if enabled 0 if disabled 0 2 Enable IRQ source 2 Status enable source 2 read as 1 if enabled 0 if disabled 0 1 Enable IRQ source 1 Status enable source 1 read as 1 if enabled 0 if disabled 0 0 Enable IRQ source 0 Status enable source 0 read as 1 if enabled 0 if disabled 0 The power up default value reads Ox 00000000 Page 21 of 72 SIS Documentation SIS3300 SIS3301 65 80 100 MHz FADC SIS GmbH VME The generation of the status flags the IRQ flags and the actual IRQ is illustrated with the schematic below Ae Source 0 Status FLAG Source 0 Clear ee Source 1 Enable 0 Status IRQ Source 0 Clear Ba Source 2 Status FLAG Source 1 Status IRQ internal Enable 1 Source 1 VME IRQ _ Clear Ss E Source 3 Status FLAG Source 2 Status IRQ Enable 2 Source 2 Status IRQ Clear Status FLAG Source 3 Enable 3 VME IRQ ENABLE Clear ROAK RD IRQ ACK g VME_IRQ Page 22 of 72 SIS Documentation SIS3300 3301 65 80 100 MHz FADCs SIS GmbH VME 4 5 Acquisition control register 0x10 read write define SIS3300 ACQUISTION CONTROL The acquisition control register is in charge of most of the settings related to the actual 0x10 configu
74. utput 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect the bank full pulse by setting bit 9 of the control register Sampling LEMO Output 2 0 7 V 5 1 1 Front panel start stop One option to use start stop mode is with NIM front panel start and stop signals The width of the start and stop pulse has to exceed 2 sampling clocks Following steps are part of the setup in this case e enable front panel start stop logic by setting bit 8 of acquisition control register e connect start to LEMO input 3 e connect stop to LEMO input 2 5 2 Gate mode A single external signal is used to define sampling start and stop The start signal i e LEMO input 3 is used as gate input in this mode The leading edge of the signal defines the start the stop condition is given by the trailing edge as illustrated below The width of the gate has to exceed 2 sample clocks Following steps are required to activate gate mode e enable front panel start stop logic set bit 8 of acquisition control register e enable front panel gate mode set bit 10 of acquisition control register 0v Start LEMO Input 3 Sampling LEMO Output 2 0 7 V Page 47 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 80 100 MHz FADC VME Note LEMO output 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect
75. x282000 0x282ffc 0x302000 0x302ffc 0x382000 0x382ffc define SIS3300 EVENT DIRECTORY BANK2 ADC12 0x202000 define SIS3300 EVENT DIRECTORY BANK2 ADC34 0x282000 define SIS3300 EVENT DIRECTORY BANK2 ADC56 0x302000 define SIS3300 EVENT DIRECTORY BANK2 ADC78 0x382000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 42 of 72 SIS Documentation STS3300 3301 SIS GmbH 65 80 100 MHz FADCs VME 4 30 Bank 1 address counter 0x200008 0x280008 0x300008 0x380008 define SIS3300 BANK1 ADDR CNT ADC12 0x200008 read only D32 define SIS3300 BANK1 ADDR CNT ADC34 0x280008 read only D32 define SIS3300 BANK1 ADDR CNT ADC56 0x300008 read only D32 define SIS3300 BANK1 ADDR CNT ADC78 0x380008 read only D32 These read only registers hold the current bank 1 address counter for ADC group 1 2 3 4 and bank The counter is 17 bit wide The counter will change while the ADC is sampling after the ADC was stopped the stop position can be retrieved in multi event mode it will have to be read from the event directory The address counter points to the next memory location that will be written to see Trigger event directory also The register is implemented on the channel group base but the information is redundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 17 16 0 Function
76. ysreset closed 0 0 7 unused open oo 8 unused open The enable watchdog jumper has to be removed during the initial JTAG firmware load Page 57 of 72 SIS Documentation SIS3300 SIS3301 SIS GmbH I 65 80 100 MHz FADC VME 9 3 Offset adjustment 9 3 1 SIS3300 The pedestal or offset of single ended non symmetric ADC channels can be adjusted with the potentiometers RP10A through RP80A see table below The sensitivity for the positive or negative offset can be reduced by two limit jumpers 2 mm the full range is available with both jumpers open Do not install both jumpers for a channel in parallel channel limit pos offset limit neg offset Offset Potentiometer 1 JP78 JP79 RP80A 2 JP76 JP77 RP70A 3 JP58 JP59 RP60A 4 JP56 JP57 RP50A 5 JP38 JP39 RP40A 6 JP36 JP37 RP30A 7 JP18 JP19 RP20A 8 JP16 JP17 RP10A The position of the two jumpers JP78 and JP79 close to potentiometer RP80A for ADC channel 1 is illustrated in the portion of the board shown below The displayed area is the vicinity of the channel 1 LEMO input connector CON80 Page 58 of 72 SIS3300 3301 SIS uL SIS Documentation 65 80 100 MHz FADCs VME 9 3 2 SIS3301 Due to the higher sensitivity of the 14 bit ADC it is expected that this design will be mainly used with differential and or symmetric inputs Potentiometers can be installed but the limit jumpers are not present i

SIS3300/SIS3301 65/80/100 MHz VME FADCs User Manual

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