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M30245 Group User's Manual

1. Note 1 Can be used when an external clock is selected Note 2 Can be used when the external signal is being counted in event counter mode Note 3 Can be used in one shot mode and one shot sweep mode Note 4 Can be used when count source is fC32 Note 5 Only when USB suspend mode Note 6 When the MCU running in low speed or low power dissipation mode do not enter wait mode with CM02 is set to 1 Note 7 When I C mode is selected NACK ACK start stop condition detection interrupt are selected and when SS pin is selected trouble error interrupt is selected Rev 2 00 Oct 16 2006 page 277 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 Power Control 5 Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start up time and interrupt sequence When interrupt is generated in stop mode CM10 becomes 0 and clearing stop mode Starting oscillation and supplying BCLK execute the interrupt sequence as follow In the interrupt sequence the processor carries out the following in sequence given a CPU gets the interrupt information the interrupt number and interrupt request level by read ing address 0000016 The interrupt request bit of the interrupt written in address 0000016 will then be set to 0 b Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in
2. 0 0 Note 1 If the AD control regsiter 0 is rewritten during A D conversion the conversion result is indeterminate Note 2 When changing A D operation mode reset the analog input pin Note 3 This bit is disabled in single sweep mode repeat sweep mode 0 and repeat sweep mode 1 Note 4 Set to 1 when ADTRG is selected Note 5 When f XIN exceeds 10 MHz the AD frequency must be less than 10 MHz by dividing Symbol ADCON1 Address When reset 03D716 0016 Bit Symbol Bit Name Function SCANO A D sweep pin select bit SCAN1 ANO AN1 ANO ANO to AN3 ANO AN1 ANO to AN5 ANO to AN2 ANO to AN7 ANO to AN3 Note 2 MD2 A D operation mode select bit 1 0 Any mode other than repeat sweep mode 1 Repeat sweep mode 1 BITS 8 10 bit mode select bit 8 bit mode 10 bit mode CKS1 Frequency select bit 1 Note 3 fAD 2 or fAD 4 is selected fAD 1 or fAD 3 is selected VCUT Vref connect bit Vref not connected Vref connected Reserved Must always be set to 0 Note 1 If the AD control regsiter 1 is rewritten during A D conversion the conversion result is indeterminate Note 2 This bit is invalid in one shot mode and repeat mode Channels shown in parentheses are valid when repeat sweep mode 1 bit 2 1 is selected Note 3 When f XIN exceeds 10 MHz the AD frequency must be l
3. AD register 0 Result AD register 1 AD register 2 DA Result Note When AD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 oAD cycles for 10 bit resolution Figure 2 9 15 Operation timing of repeat sweep 1 mode Rev 2 00 Oct 16 2006 page 228 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter Selecting Sample and hold b7 b0 AD control register 2 Address 03D416 X Le Ke XT apcone L A D conversion method select bit 1 With sample and hold KO Must always be set to 0 Setting AD control register 0 and AD control register 1 b bo 4 AD control register 1 Address 03D716 AD control register 0 0 0 1 Address 03D616 ADCONO ADCONI Invalid in repeat sweep mode 0 Invalid in Repeat mode L A D operation mode select bit 1 Note 1 Repeat sweep mode 0 is selected 1 Must always be 1 Note 1 in repeat sweep mode 1 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode Trigger select bit 0 Software trigger A D conversion start flag i 0 A D conversion disabled L Frequency select bit 1 Note 2 0 fAD 2 or fAD 4 is selected Frequency select bit 0 Note 2 1 fAD or faD 3 is selected 0 fAD 3 or fAD 4 is selected 1 fAD or faD 2 is selected LV connect bit 1 Vref connec
4. in Clear EP1 IN interrupt status flag Clear EP1 OUT interrupt status flag Clear EP2 IN interrupt status flag Clear EP2 OUT interrupt status flag Clear EP3 IN interrupt status flag 0 No action 1 Clear interrupt status flag Clear EP3 OUT interrupt status flag Clear EP4 IN interrupt status flag Clear EP4 OUT interrupt status flag Clear error interrupt status flag Figure 2 8 25 USB function interrupt related registers Rev 2 00 Oct 16 2006 page 159 of 354 7tENESAS REJ09B0340 0200 M30245 Group USB function interrupt request detected USBIS Read one word and store it to RAM RAM Write one word to USBIC RAM bit8 1 USB error interrupt routine RAM bit1 1 or RAM bit3 1 or RAM bit5 1 or RAM bit7 1 USB endpoint x OUT interrupt routine RAM bitO 1 or RAM bit2 1 or RAM bit4 1 or RAM bit6 1 USB endpoint x IN interrupt routine Completion of USB funxtion interrupt process 2 USB function Enables each interrupt by the USBIE address 028816 028916 at initial routine Clears USB interrupt status register 1 2 by writing 1 to the bit corresponding to the USBIC Executes error handling of endpoint 0 to 4 Figure 2 8 26 USB function interrupt processing routine Rev 2 00 Oct 16 2006 page 160 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 USB function 2 8 4 USB Operation Suspend Resume Function The USB device has received
5. Symbol SSIxMRO x 0 1 Address 031016 037016 2 Serial sound interface When reset 0016 Bit symbol Bit name Function SSIEN Serial Sound Interface enable bit Disable Enable XMTEN Transmitter enable bit Disable Enable RXEN Receiver enable bit Disable Enable RFBEN Rate feedback counter enable bit 0 Disable 1 Enable CWIDO Channel width select bit 0 CWID1 Channel width select bit 1 b5 b4 0 0 32 bit 0 1 24 bit 1 0 Disable 11 16 bit RFMTO Receiver format select bit 0 0 LSB first 1 MSB first RFMT1 Receiver format select bit 1 0 LSB justified 1 MSB justified Serial Sound Interface x mode register 1 b7 b6 b5 b4 b3 b2 bi bo Symbol SSIxMR1 x 0 1 Address 031116 037116 When reset 0016 0 0 Figure 2 6 3 Serial Sound Interface function related registers 2 0 Bit symbol Bit name Function XMTFMT Transmitter format 0 LSB first 1 MSB first Reserved bit Always set to 0 RFBSRC Rate feedback counter source 0 SCK 1 WS SCKP SCK polarity select bit 0 Falling edge 1 Rising edge WSP WS polarity select bit Falling edge Rising edge WSDLY WS delay select bit Delayed WS Normal WS Reserved bit Always set to 0
6. Rev 2 00 Oct 16 2006 page 114 of 354 REJ09B0340 0200 7tENESAS M30245 Group In the case of the USB audio class the following stream is output 2 Serial sound interface Audio stream PCM from the PC to the M30245 USB FIFO For 16 bit data Fourth byte Fifth byte Third byte LSB Left Low LL Right High RH Right Low RL RHIRLILHILLIRHIRL LHi LL RHiRL LH LL USB FIFO data setup FIFO data M30245 FIFO address Second byte LH 0 First byte LL Fourth byte RH Third byte RL Sixth byte LH Fifth byte LL 14 3 2 1 0 Eighth byte RH Seventh byte RL 15 14131211 10 9 8 7 6 5 4 3 2 1 0 Tenth byte LH Ninth byte LL Twelfth byte RH Eleventh byte RL O For 16 bit data LSB MSB LSB bo b7 b0 Left Buffer OPERATION Byte 1 ae First Word Write First byte Second byte Right Buffer Byte 0 Byte 1 Left High LH eo First byte Left Low LL LSB first transmit receive Second Word Write Third byte Fourth byte Third Word Write Fourth Word Write Fifth byte Sixth byte LL b0 tob7 RL bO to b7 LH b8 to b15 RH b8 to b15 Seventh byte Eighth byte Just as 16 bits the data width is expanded to output data for 24 bits and 32 bits OFor 24 bit data MSBLSB b7 b0 Left Buffer Right Buffer First Word Write First byte LL Byte 1 Second byte LM Byte 1 Second Word Write Third byte L
7. Reserved Must always be set to 0 Note Always read a 0 Figure 2 8 46 USB endpoint x x 1 to 4 IN control and status register Rev 2 00 Oct 16 2006 page 198 of 354 7tENESAS REJ09B0340 0200 M30245 Group USB endpoint x x 1 to 4 IN MAXP register 2 USB function This register indicates endpoint x x 1 to 4 IN maximum packet size The default value is 0 byte When the endpoint is initialized due to any reason such as that the request for setting the endpoint SET_DESCRIPTOR SET_CONFIGURATION SET_INTERFACE etc is received from the host CPU change the endpoint x IN maximum packet size value by writing in this register Set a packet size value specified for every transfer type to be used The configuration of USB endpoint x x 1 to 4 IN MAXP register is shown in Figure 2 8 47 USB Endpoint x IN MAXP register b15 b8 b7 bO _ b7 Symbol 0 0 0 EPxIMP x 1 4 Address When reset 02A016 02A616 000016 02AC16 02B216 Bit Symbol Bit Name Function IMAXP9 0 Endpoint x IN maximum packet f Set the endpoint x IN size maximum packet size Reserved Must always be set to 0 Figure 2 8 47 USB endpoint x x 1 to 4 IN MAXP register Rev 2 00 Oct 16 2006 page 199 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB endpoint x x 1 to 4 IN FIFO configuration register
8. Interrupt enable flag lt 1 Stop all clocks E A System clock control register 1 Address 000716 lololololi gi All clock stop control bit 1 All clocks off stop mode Insert at least four NOPs following JMP B instruction after the instruction that sets the all clock stop control bit to 1 Shift to stop mode Wait for the interrupt for return from suspend state Execute the interrupt process lt the interrupt for return from suspend state occurs for return from suspend state USB resume remote wakeup Restore the settings changed for stop mode as required Olnterrupt enable flag lt 0 OProtect disabled etc USB suspend interrupt request process is complete Figure 2 8 29 USB suspend interrupt request processing routine 2 5 USB Resume Interrupt Request Processing Routine When the resume signal is received from the host CPU during the USB suspend mode when de tected any bus activity on D D line in suspend detect state the USB resume interrupt request occurs The USB suspend status flag is automatically set to 0 at this time The USB resume interrupt request processing routine is shown in Figure 2 8 30 Rev 2 00 Oct16 2006 page 167 of 354 RENESAS REJ09B0340 0200 M30245 Group Detection of USB resume interrupt request 2 USB function Clearing the protect bo Protect register Address 000A16 1 PRCR Enable bit for writing to
9. RD signal WR signal Destination H Besiation Data bus CPU use E N CPU use E CPU use cycle Write signal to software DMAi request bit DMAi i i i request bit i DMA transfer counter Indeterminate DMAi f interrupt j request bit Pd DMAi Cleared to 0 when interrupt request is enable bit accepted or cleared by software In the case in which the number of transfer times is set to 2 Figure 2 10 5 Example of operation of one shot transfer mode Rev 2 00 Oct 16 2006 page 245 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 DMAC a A Setting DMAi request cause select register b0 DMAi request cause select register Address 03B816 03BA16 03B016 03B216 DMiSL i 0 to 3 DMA request cause select bit Software trigger is always enabled Software DMA request bit Set to 0 Setting DMAi control register b7 bO DMAi control register Address 002C16 003C16 018C16 019C16 DMiCON i 0 to 3 Transfer unit bit select bit 1 8 bits Repeat transfer mode select bit 0 Single transfer DMA request bit 0 DMA not requested DMA enable bit 0 Disabled Source address direction select bit 1 Forward Bit 4 and bit 5 cannot be set to 1 simultaneously Destination address direction select bit 0 Fixed Bit 4 and bit 5 cannot be set to 1
10. 036916 UART1 bit rate generator U1BRG 036A16 036B16 UART1 transmit buffer register U1TB 036C16 UART1 transmit receive control register 0 U1C0 036D16 UART1 transmit receive control register 1 U1C1 036E16 036F16 UART1 receive buffer register U1RB x 03A816 UARTO transmit receive mode register UOMR 03A916 UARTO bit rate generator UOBRG O3AA16 03AB16 UARTO transmit buffer register UOTB 03AC14 UARTO transmit receive control register 0 UOCO O3AD16 UARTO transmit receive control register 1 U0C1 O03AE16 O3AF16 UARTO receive buffer register UORB Figure 2 4 2 Memory map of UARTi related registers Rev 2 00 Oct 16 2006 page 59 of 354 7tENESAS REJ09B0340 0200 M30245 Group UARTi transmit buffer register i 0 to 3 Note K N b8 b0 b7 O Symbol UOTB U1TB U2TB U3TB Address 03AB16 O3AA16 036B16 036A16 033B16 033A16 032B16 032A16 When reset Indeterminate Indeterminate Indeterminate Indeterminate 2 UART Bit Symbol Function Function R it Symbo clock synchronous serial I O mode UART mode 1 Ooo a E i 1 Nothing is assigned Write 0 when writing to these bits l Transmit data Transmit data xi l The values are indeterminate when read Note Use MOV instruction to write to this register UARTi receive buffer register i 0 to 3 b15
11. Figure 2 2 2 Timer A related registers 1 Rev 2 00 Oct 16 2006 page 8 of 354 REJ09B0340 0200 RENESAS M30245 Group Timer Ai register i 0 to 4 Note 1 Address 038716 038616 038916 038816 Symbol TAO TA1 TA2 038B16 038A16 038D16 038C16 TA3 TA4 038F 16 038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 2 TimerA Mode Function Values that can be set Timer mode 16 bit counter set to divide ratio 000016 to FFFF16 Event counter mode 16 bit counter set to divide ratio Note 2 000016 to FFFF16 One shot timer mode 16 bit counter set to one shot width Note 6 000016 to FFFF16 Note 3 16 bit PWM 16 bit PWM set to PWM pulse H width 000016 to FFFF16 Note 4 7 Note 3 8 bit PWM Low order bits 8 bit prescaler set to PWM period Notes 5 7 High order bits 8 bit PWM set to PWM pulse H width Notes 5 7 0016 to FE16 Both high order and low order addresses Note 3 Count start flag b7 b6 b5 b4 b3 b2 bi Read and write data in 16 bit units Counts pulses from an external source of timer overflow Use MOV instruction to write to this register When setting value is n PWM period and H width of PWM pulses are PWM period 216 1 fi PWM pulse H width n fi When setting value of high order address is n and setting value of low
12. Rev 2 00 Oct 16 2006 page 72 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface 2 4 5 Operation of Serial I O transmission used for SIM interface In transmitting data in UARTi i 0 to 3 mode used for SIM interface choose functions from those listed in Table 2 4 6 Operations of the circled items are described below Figure 2 4 13 shows the operation timing and Figures 2 4 14 and 2 4 15 show the set up procedures Table 2 4 6 Choosed functions Transfer data O Direct format Transfer clock O Internal clock f1 fs f32 format source 2 Inverse format External clock CLKi pin Operation 1 Setting the transmit enable bit and receive enable bit to 1 and writing transmission data to the UARTI i 0 to 3 transmit buffer register readies the data transmissible status Set UARTi i 0 to 3 transfer interrupt for being enabled 2 Transmission data held in the UARTi i 0 to 3 transmit buffer register is transmitted to the UARTiI i 0 to 3 transmit register At this time the first bit the start bit of the transmission data is transmitted from the TxDi i 0 to 3 pin Then data is transmitted bit by bit in se quence LSB MSB parity bit and stop bit s 3 When the stop bit s is are transmitted the transmit register empty flag goes to 1 which indicates that transmission is completed At this time the UARTi i 0 to 3 transmit interrupt request bit goes to 1 The transfe
13. SET_IN_BUF_RDY bit This bit controls IN FIFO When there is a space in IN FIFO when IN_BUF_STS1 IN_BUF_STS0 002 in single buffer or IN_BUF_STS1 IN BUF_STS0 002 or 012 in double buffer enable data can be written in the IN FIFO One transmit data is prepared by setting this bit to 1 after writing the transmit data to the IN FIFO To transmit an empty packet set this bit to 1 without writing any data When this bit is set to 1 the completion of one transmit data ready is notified to the USB function control unit and simultaneously the IN FIFO status IN_BUF_STS1 IN _BUF_STS0O flags is up dated In the AUTO_SET enable when a short packet data whose size is smaller than the EPxIMP value in continuous transfer disable or the BUF_SIZ value in continuous transfer enable has been written the IN_ BUF_STS1 and IN_BUF_STS0 flags are not automatically updated In this case set this bit to 1 Rev 2 00 Oct 16 2006 page 196 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function CLR_UNDER_RUN bit The UNDER_RUN flag is cleared to 0 by setting 1 to this bit TOGGLE_INIT bit This bit initializes data toggle bit required in bulk and interrupt transfer When initialization of the data toggle sequence is requested from the host CPU at the time of configu ration etc set this bit to 1 before starting the IN endpoint communication and initialize PID to DATAO At this time the
14. Figure 2 8 23 USB function interrupt enable register Rev 2 00 Oct 16 2006 page 152 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB frame number register This register is used to contain 11 bit frame number of SOF token received from the host CPU This is the read only register The configuration of USB frame number register is shown in Figure 2 8 24 USB Frame Number register Note b15 b8 b7 bO b7 olo Symbol Address When reset USBFN 028A16 000016 Bit Symbol Bit Name Function FN10 0 SOF frame number bit 11 bit frame number issued with an SOF packet Reserved 0 when read Note Read only Figure 2 8 24 USB frame number register Rev 2 00 Oct 16 2006 page 153 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 USB Endpoint 0 Interrupt In the endpoint 0 interrupt the interrupt request occurs when the data transmit receive of endpoint 0 are completed Set the interrupt priority level by using USB endpoint 0 interrupt control register EPOIC address 004616 The interrupt request bit of the EPOIC is set to 1 and the USB endpoint 0 interrupt occurs when one of the following events occur A data is successfully received A data is successfully transmitted e The DATA_END bit of the EPOCS register is cleared to 0 e The SETUP_END flag of the EPOCS register is set to 1
15. Rev 2 00 Oct16 2006 page 251 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 CRC Calculation Circuit 2 11 3 SFR Access Snoop Function The CRC calculation circuit includes the ability to snoop write read to from the SFR addresses and to execute CRC automatic calculation SFR access snoop function In order to execute CRC calculation for data which have been written read to from the SFR setting data to CRC input register again is not re quired The target SFRs include USB related registers UART related registers and Serial Sound Inter face related registers Operation 1 The bit 1 of CRC mode register selects either CRC CCITT or CRC 16 and the bit 7 selects either LSB first or MSB first 2 The target SFR addresses are set to CRC snoop address register bit 0 to 9 of CRCSAR Snooping of writing to the target SFR is enabled with CRC snoop on write enable bit bit 15 of CRCSAR and snooping of reading from the target SFR is enabled with CRC snoop on read enable bit bit 14 of CRCSAR 3 The initial value 000016 is set to CRC data register 4 If writing into the target SFR is executed by either the CPU or DMA while 1 is set to CRC snoop on write enable bit the CRC calculation circuit will store the data written to the target SFR in CRC input register and executes CRC calculation Similarly if reading from the target SFR by the CPU or DMA while 1 is set to CRC snoop on read enable bit calculation circuit will store
16. Bit Symbol Bit Name Function All clock stop control bit 0 Clock on CM10 Note 4 1 All clocks off stop mode wit _1 Reserved bit Always set to 0 Xin Xout drive capacity 0 LOW CMIS select bit Note 2 1 HIGH Main clock division select 57 e CM16 bit 1 Note 3 0 0 No division mode 0 1 Divide by 2 mode 1 0 Divide by 4 mode oi 1 1 Divide by 16 mode CM17 Note 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register Note 2 This bit changes to 1 when changing from high speed medium mode to stop mode and at reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 3 Can be selected when bit 6 of the system clock control register 0 address 000616 is O If 1 division mode is fixed at 8 Note 4 If this bit is set to 1 XouT turns H and the built in feedback resistor is cut off XCIN and XCOUT turn high impedance state Figure 2 16 4 Power control related registers Rev 2 00 Oct 16 2006 page 279 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Power Control 2 16 2 Stop Mode Set Up Settings and operation for entering stop mode are described here Operation 1 Enables the interrupt used for returning from stop mode 2 Sets the interrupt enable flag I flag to 1 3 Clearing the protection and setting all clock
17. Figure 2 6 6 Example of Serial Sound Interface receive timing Rev 2 00 Oct 16 2006 page 119 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial sound interface 2 6 3 Precautions for Serial Sound Interface Description For flash memory version SSI transmission data must be latched as the following timing by a receiver e SCKP 0 falling edge within 3 BCLK cycles from the rising edge of SCK e SCKP 1 rising edge within 3 BCLK cycles from the falling edge of SCK Rev 2 00 Oct 16 2006 page 120 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 Frequency synthesizer PLL 2 7 Frequency synthesizer PLL This paragraph explains the registers setting method and the notes related to the frequency synthesizer PLL circuit 2 7 1 Overview The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the fSYN clock These clocks are a multiple of the external input standard clock f XIN Figure 2 7 1 shows the frequency synthesizer circuit block diagram gt fusB USBC5 Frequency Prescaler Frequency Multiplier FSCCRO FSD FSCCR 03DE16 03DD16 03DC16 03DF 16 03DB16 Data Bus Figure 2 7 1 Frequency synthesizer circuit block diagram 1 Related Registers Figure 2 7 2 shows a memory location diagram for the frequency synthesizer related registers Fig ures 2 7 3 and 2 7 4 show the composition of the frequency synthes
18. M a Host issues Idle state Idle state error Device issues 1 The data toggle bit is toggled at the next phase DATAO DATA1 or DATA1 DATAO Figure 2 8 5 Bulk transfer Rev 2 00 Oct 16 2006 page 133 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 4 Isochronous Transfer isochronous IN Transfer In isochronous IN transfer which data are transferred from the device to the host CPU isochronous IN transactions are repeated Isochronous transaction does not have the handshake phase The data packet consists only of DATAO Toggling with DATA1 is not performed When transmit data is available in IN FIFO the M30245 group issues a data packet to the IN token The M30245 group executes the following responses when the data are not transmitted normally When the received IN token is destroyed the data are not issued When the transmit data are not available in IN FIFO an empty packet of data length 0 is issued isochronous OUT Transfer In isochronous OUT transfer which data are transferred from the host CPU to the device isochro nous OUT transactions are repeated Isochronous transaction does not have the handshake phase The data packet consists only of DATAO Toggling with DATA1 is not performed The M30245 group has received a data packet indicates whether or not the data content is normal by using a status flag The M30245 group e
19. P102 Kl2 P103 Kis Figure 2 14 4 Example of circuit using the key input interrupt 1 Enter to stop mode 2 Cancel stop mode 3 Key scan oi Key matrix scan 4 Enter to stop mode ra P104 output P105 output P106 output P107 output P100 to P103 input Key input Key OFF Key ON Key OFF Key ON Key input interrupt processing r Figure 2 14 5 Example of operation of key input interrupt REJ09B0340 0200 M30245 Group 2 Key Input Interrupt 2 Setting key input mode register bO XIX of of 1 1 ofo te pee mode register Address 03F916 P10 Key input edge select bit 0 P10 Key input edge select bit 1 b1 bo 00 Falling edge P100 and P101 Key input enable bit 1 Enabled P102 and P103 Key input enable bit 1 Enabled P104 and P105 Key input enable bit 1 Disabled P106 and P107 Key input enable bit 1 Disabled Setting port P10 direction register b7 b 1 1 1 i Port P10 directi ister Add 03F616 ne ee ae irection register ress 0 Input mode Functions as an input port 1 Output mode Functions as an output port Setting pull up control register 2 SLR I Sune control register 2 Address 03FE16 P100 to P103 1 Pulled high Setting key input interrupt control register b7 bO OPP LH Me ea interrupt control register Address 0041 16 Interrupt priority level select bit b2 b1 b0 Level 0
20. Pull up control register 1 PUR1 Pull up control register 2 PUR2 Port control register PCR RENESAS M30245 Group 2 Programmable I O Ports Port 7 drive capacity register b7 b6 b5 b4 b3 b2 bi bo Symbol Address When reset P7DR 03FA16 0016 The N channel high drive capacity is activated for the corresponding P eNotnaldiive 1 N channel high drive Port control register b7 b6 b5 b4 b3 b2 bi Symbol Address When reset PCR 03FF16 0016 Bit Symbol Bit Name Function When input port read port input level When output port Port P1control register read the contents of Port P1 register Read the contents of Port P1 register through input output port F Data read mode enabled OECTRL AND Flash OE control bit Output disabled Input disabled WECTRL AND Flash WE control bit Command Address mode enabled PO amp P1 0 2 GPI O function AFPE AND Flash port enable bit PO amp P1 0 2 AND Flash control function Nothing is assigned Write 0 when writing to this bit The value is 0 when read Figure 2 17 2 Programmable I O ports related registers 1 Rev 2 00 Oct 16 2006 page 288 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Programmable I O Ports Port Pi direction register Note 1 b7 b6 b5 b4 b3 b2 bi bd Symbol Address When reset PDi i 0 to 7 10 03E216 03E316 03E616 03E716 03EA16 0016 03EB16
21. The value is indeterminate when read 0 Output disabled 1 Output enabled Note 1 Note 1 When disabling the error signal output set the UIERE bit to 0 after setting the UiMR register Figure 2 5 4 Serial interface special function related registers 3 Rev 2 00 Oct 16 2006 page 90 of 354 REJ09B0340 0200 RENESAS M30245 Group b7 b6 b5 b4 b3 b2 bi UARTi special mode register 1 i 0 to 3 Symbol UiSMR i 0 to 3 Bit Name clock synchronous 2 Serial Interface Special Function Address When reset 03A716 036716 033716 032716 0016 Function Function serial O mode UART mode 12C mode select bit Normal mode C mode Set to 0 Arbitration lost detecting flag control bit Update per bit Update per byte Set to 0 Bus busy flag STOP detected START detected Set to 0 SCLL sync output enable bit Disabled 1 Enabled Set to 0 Bus collision detect sampling Set to 0 clock select bit Rising edge o transfer clock Timer Ai underflow signal Note 2 Auto clear function select bit of transmit enable bit Set to 0 Auto clear when bus No auto clear function collision occurs Transmit start condition select Set to 0 bit Ordinary Falling edge o b7 b6 b5 b4 b3 b2 bi Nothing is assigned Write 0 when writing to this bit The v
22. seting ooo ef i 09806 098 b7 bo 2 1 CRC input register CRCIN 2 cycles After CRC calculation is complete b15 bO 118916 CRC data register CRCD 03BD16 03BC16 3 y 6 Stores CRC code The code resulting from sending 0116 in LSB first mode is 1000 0000 Thus the CRC code in the generating polynomial X16 X12 X5 1 becomes the remainder resulting from dividing 1000 0000 X18 by 1 0001 0000 0010 0001 in conformity with the modulo 2 operation LSB N MSB Modulo 2 operation is 1000 1000 yf operation that complies 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 with the law given below 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 LsB x 9 8 1 1 A s Thus the CRC code becomes 1001 0001 1000 1000 Since the operation is in LSB first mode the 1001 0001 1000 1000 corresponds to 118916 in hexadecimal notation If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C switch between the LSB side and the MSB side of the input holding bits and carry out the CRC operation Also switch between the MSB and LSB of the result as stored in CRC data MSB b7 bo CRC input register CRCIN After CRC calculation is complete b15 bO CRC data register CRCD l CAME 03BD16 03BC16 Y ooo Stores CRC code Figure 2 11 3 Calculation example using the CRC calculation circuit when using CRC CCITT
23. 0 fAD 2 or fAD 4 is selected 1 fAD or fAD 3 is selected Vref connect bit 1 Vref connected Reserved bit Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 When f XIN is over 10 MHz the fap frequency must be under 10 MHz by dividing and set AD frequency to 10 MHz or lower A Setting A D conversion start flag PUERENEN PEES register 0 Address 03D616 A D conversion start flag 1 A D conversion started Start A D conversion Stop A D conversion Fa Reading conversion result AD registerO Address 03C116 03C016 ADO AD register 1 Address 03C316 03C216 AD1 oe AD register2 Address 03C516 03C416 AD2 AD register3 Address 03C716 03C616 AD3 AD register 4 Address 03C916 03C816 AD4 AD register5 Address 03CB16 03CA16 AD5 AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 O3CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 9 11 Set up procedure of single sweep mode Rev 2 00 Oct 16 2006 page 225 of 354 lt ENESAS REJ09B0340 0200 an M30245 Group 2 A D Converter 2 9 6 Operation of A D Converter in repeat sweep mode 0 In repeat sweep 0 mode choose functions from those listed in Table 2 9 6 Operations of the circled items are described below
24. Figure 2 8 39 Device configuration notification processing routine 2 when receiving GET_CONFIGURATION request Rev 2 00 Oct 16 2006 page 181 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 8 6 USB Operation Endpoints 1 to 4 Receive Endpoints 1 to 4 can apply to the isochronous transfer bulk transfer and interrupt transfer The endpoints 1 to 4 respectively have their IN transmit FIFOs and OUT receive FIFOs For using the endpoints 1 to 4 OUT enable each endpoint OUT FIFO by USB endpoint enable register address 028E16 The size and the starting location every 64 bytes of each endpoint x x 1 to 4 OUT FIFO can be set according to the user s system The buffer size of OUT FIFO can be set to a maximum of 1024 bytes per 64 bytes for one endpoint When the double buffer mode is enabled the buffer which has twice as much as the set size is available for the OUT FIFO The size and starting location of FIFO the double buffer mode enable can be set by USB endpoint x OUT FIFO configuration register EPXOFC When one buffer data is received from the host CPU the data are written to the endpoint x OUT FIFO and the number of bytes of receive packet data are stored in USB endpoint x OUT write count register When a data receive request from the host CPU occurs while data are already written and OUT FIFO cannot be received NAK is automatically transmitted in bulk transfer interrupt transfer and an overrun occurs in isochronous tran
25. Mask Function of Endpoint 0 Interrupt Factor By setting the DATA_END_MASK bit of USB endpoint 0 control and status register the M30245 group can control whether or not to clear the DATA_END flag as the endpoint 0 interrupt factor Clearing of the DATA_END flag is masked at the time of resetting The DATA_END flag is not cleared as an endpoint 0 interrupt factor Rev 2 00 Oct 16 2006 page 154 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 USB Function Interrupt The USB function interrupts include the endpoint x x 1 4 IN interrupt endpoint x x 1 4 OUT inter rupt and error interrupt An interrupt request occurs on completion of data transmit receive or on occurrence of an error such as overrun underrun setting the status flag which is the factor of the interrupt request inside USB function interrupt status register to 1 When using the USB function interrupt set the interrupt priority level at USB function interrupt control register address 005D16 and the corresponding bit of USB function interrupt enable register to 1 The USB function interrupt involves multiple interrupt request factors Therefore during processing of the USB function interrupt an interrupt request may occur newly and the interrupt status flag can be changed by it When performing USB function interrupt processing be sure to first save contents of interrupt status register and to clear the status flag Then process the interrupt reque
26. Maximum frequency MHz Model No 3 57 M5M29GB T160BVP 80 b 3V with wait Maximum frequency MHz Model No 8 33 M5M29GB T 160BVP 80 2 SRAM a 3V without wait Maximum frequency MHz Model No M5M54R08AJ 12 M5M54R16AJ ATP 12 5 12 b 3V without wait Maximum frequency MHz Model No M5M54R08AJ 12 M5M54R16AJ ATP 12 10 0 Rev 2 00 Oct 16 2006 page 346 of 354 7RENESAS REJ09B0340 0200 4 External Buses M30245 Group 4 External Buses 4 5 Releasing an External Bus HOLD input and HLDA output The Hold feature is to relinquish the address bus the data bus and the control bus on M30245 side in line with the Hold request from the bus master other than M30245 when the two or more bus masters share the address bus the data bus and the control bus The Hold feature is effective only in memory expansion mode and microprocessor mode The sequence of using the Hold feature may be 1 The external bus master turns the input level of the HOLD terminal to L 2 When M30245 becomes ready to relinquish buses each bus becomes high impedance state at the falling edge of BCLK 3 The HLDA terminal becomes L at the rising edge of the next BCLK 4 The external bus master uses a bus 5 When the external bus master finishes using a bus the external bus master returns the input level of the HOLD terminal to H 6 The output from HLDA terminal becomes H at the risi
27. O Timer A4 event trigger select bit 6 6 Input on TA4IN is selected Note 2 Setting PWM s pulse s H level width b15 b8 Timer AO register Address 038716 038616 b7 b0 b7 bo Timer A1 register Address 038916 038816 Timer A2 register Address 038B16 038A16 Timer A3 register Address 038D16 038C16 Timer A4 register Address 038F 16 038E16 Can be set to 000116 to FFFF16 Continued to the next page Figure 2 2 26 Set up procedure of pulse width modulation mode 8 bit PWM mode selected 1 Rev 2 00 Oct 16 2006 page 32 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 TimerA Continued from the previous page Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCcIN by 32 r Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect C 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bO KX Count start flag Address 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2 2 27 Set up procedure of pulse width modulation mode 8 bit PWM mode selected 2 Rev 2 00 Oct 16 2006 page 33 of 354 7tENESAS REJ09B0340 0200 M30245
28. Up down flag Address 038416 UDF ________________ Timer A3 two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled Timer A4 two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled Setting trigger select register b7 b0 Trigger select register Address 038316 TRGSR Timer A3 event trigger select bit b5 b4 0 0 Input on TAIN is selected Note 2 Timer A4 event trigger select bit b7 b6 0 0 Input on TA4 is selected Note 2 Note 2 Set the corresponding port direction register to 0 Setting divide ratio b15 b7 bo Timer A3 register Address 038D16 038C16 TA3 Timer A4 register Address 038F 16 038E16 TA4 X L Can be set to 000016 to FFFF16 Setting count start flag b7 b0 X Count start flag Address 038016 TABSR Timer A3 count start flag L Timer A4 count start flag Start count Set up procedure of two phase pulse signal process in event counter mode multiply by 4 mode selected RENESAS 2 Timer A M30245 Group 2 TimerA 2 2 9 Operation of Timer A one shot timer mode In one shot timer mode choose functions from those listed in Table 2 2 9 Operations of the circled items are described below Figure 2 2 20 shows the operation timing and Figures 2 2 21 shows the set up procedure Table 2 2 9
29. for bulk transfer and interrupt transfer SEND_STALL bit This bit controls the STALL response to the host CPU Set this bit to 1 when the IN endpoint is in STALL state While this bit is set to 1 the USB function control unit transmits the STALL handshake concerning all the IN transactions to the host CPU When the IN endpoint has returned from STALL state write 0 to clear this bit The IN endpoint communication is resumed Rev 2 00 Oct 16 2006 page 197 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function AUTO_SET bit This bit controls setting of SET_IN_BUF_RDY bit With this bit being set to 1 when one data packet whose is equal to the maximum packet size EPxIMP set value has been written to IN FIFO in continuous transmit disable or when data equal to the buffer size byte count set in the BUF_SIZ of the EPxIFC have been written to IN FIFO in continuous transmit enable the IN_BUF_STS1 and IN_BUF_STSO flags are updated without SET_IN_BUF_RDY bit being set to 1 However when a short packet data whose size is smaller than the EPxIMP value in continuous transfer disable or the BUF_SIZ value in continuous transfer enable has been written IN BUF_STS1 and IN_BUF_STS0 flags are not automatically updated In such cases set SET_IN_BUF_RDY bit to 1 by software With this bit being set to 0 set SET_IN_BUF_RDY bit to 1 by software after the transmit data are written to IN FIFO
30. 03A916 005316 UARTO transmit NACK SSIO interrupt control register SOTIC O3AA16 ARTO bit rate generator UOBRG 03AB16 ARTO transmit buffer register UOTB 005516 UARTS receive ACK interrupt control register S3RIC 03AC16 ARTO transmit receive control register 0 UOCO 03AD16 ARTO transmit receive control register 1 U0C1 O3AE16 032816 UARTS transmit receive mode register U3MR O3AF16 032916 UARTS bit rate generator USBRG ARTO receive buffer register UORB 032A16 UARTS transmit buffer register U3TB 032B16 032C16 UARTS transmit receive control register 0 U3C0 032D16 UARTS transmit receive control register 1 U3C1 032E16 UARTS receive buffer register U3RB 032F16 X 033816 UART2 transmit receive mode register U2MR 033916 UART2 bit rate generator U2BRG 033A16 UART2 transmit buffer register U2TB 033B16 033C16 UART2 transmit receive control register 0 U2C0 033D16 UART2 transmit receive control register 1 U2C1 033E16 033Fi6 UART2 receive buffer register U2RB Figure 2 3 1 Memory map of serial I O related registers Rev 2 00 Oct 16 2006 page 41 of 354 REJ09B0340 0200 7tENESAS M30245 Group UARTI transmit buffer register i 0 to 3 Note bi k 0 b7 bO Symbol AO UTE U3TB Address 03AB16 03AA16 036B16 036A16 033B16 033A16 032B16
31. 2 14 Key Input Interrupt Usage 2 14 1 Overview of the key input interrupt usage Key input interrupt can be generated by a falling edge rising edge or both edges input to any Port 10 pin It can also be used as a Key on wake up function for canceling the wait mode or stop mode It is possible to select the edge of the Key input interrupt for P10 with bits O and 1 of key input mode register This register is also used to enable or disable Port 10 pins that are to be used for Key input interrupts Port 10 can be configured with pull up resistors using the pull up control resistor The following is an overview of the key input interrupt usage 1 Enabling disabling the key input interrupt The key input interrupt can be enabled and disabled using the key input mode register 0O3F916 and the key input interrupt register 004116 The key input interrupt is affected by the interrupt priority level IPL and the interrupt enable flag I flag A falling edge rising edge or both edges input to any Port 10 pin can be selected by P10 Key input edge select bits bitO and bit1 of O3F 916 2 Occurrence timing of the key input interrupt With key input interrupt acceptance enabled pins P100 through P107 which are set to input become key input interrupt pins Klo through KI7 A Key input interrupt occurs when the selected edge is input to a Key input interrupt pin At this moment the level of other key input interrupt pins must be H No interrupt occ
32. Frequency synthesizer PLL 2 7 2 Operation of frequency synthesizer The following explains how to setup after hardware reset Table 2 7 1 to 2 7 3 show frequency synthe sizer related registers setting examples Operation 1 Cancel the protect register 2 Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary for the fUSB 3 Enable the frequency synthesizer by setting frequency synthesizer control register 4 The protect register should be set to write disabled A 3ms wait is necessary 5 The frequency synthesizer locked status bit should be checked It is necessary to recheck after a wait of 0 1ms if it is 0 unlocked 6 Enable USB clock 7 After waiting four cycles of the o or greater the USB enable bit should be set to 1 A minimum delay of 250ns is needed before performing any other USB related registers read write operations Prescaler Clock f XIN is prescaled down by the frequency synthesizer prescaler register FSP to generate fPIN When the frequency synthesizer prescaler register is set at 255 the prescaler is disabled and fPIN f XIN Table 2 7 1 shows some examples of how the frequency synthesizer prescaler register is set fPIN f XIN 2 n 1 n FSP value Note The value of fPIN should not be set below 1 MHz Table 2 7 1 Example of setting the frequency synthesizer prescaler register FSP FSP Value fX 12 MHz 12 00 MHz 1 MH
33. M30245 Group 2 USB function USB Function Interrupt Clear register b15 b8 b7 b0 b7 010 Symbo Address When reset rr cr ar a a a aa a a a a a a USBIC 028616 000016 Bit Symbol Bit Name Function ear EP1 IN interrupt status flag ear EP1 OUT interrupt status flag ear EP2 IN interrupt status flag 0 No action 1 Clear interrupt status flag ear EP2 OUT interrupt status flag Cl Clear EP3 IN interrupt status flag Clear EP3 OUT interrupt status flag Cl Cl Cl lear EP4 IN interrupt status flag lear EP4 OUT interrupt status flag ear error interrupt status flag Reserved Must always be 0 Note Write only Figure 2 8 22 USB function interrupt clear register USB Function Interrupt Enable register b15 b8 b7 bO b7 0 10 Symbol Address When reset 7 E E aa a aaa a aa a USBIE 028816 01FF16 Bit Symbol Bit Name Function NTENO EP1 IN interrupt enable bit 0 Disabled NTEN1 EP1 OUT interrupt enable bit 1 Enabled NTEN2 EP2 IN interrupt enable bit NTEN3 EP2 OUT interrupt enable bit NTEN4 EP3 IN interrupt enable bit NTEN5 EP3 OUT interrupt enable bit NTEN6 EP4 IN interrupt enable bit NTEN7 EP4 OUT interrupt enable bit NTEN8 Error interrupt enable bit Reserved Must always be 0
34. Note b15 b8 b7 bO b7 olo Symbol Address When reset 4 T Poi T USBIS 028416 000016 Bit Symbol Bit Name Function NTSTO EP1 IN interrupt status flag O No interrupt request NTST EP1 OUT interrupt status flag 1 Interrupt request issued NTST EP2 IN interrupt status flag NTST EP2 OUT interrupt status flag NTST EP3 IN interrupt status flag INTST EP3 OUT interrupt status flag NTST EP4 IN interrupt status flag NTST EP4 OUT interrupt status flag NTST8 Error interrupt status flag Reserved Must always be 0 Note Read only Figure 2 8 21 USB function interrupt status register USB function interrupt clear register This register is used to clear the USB function interrupt request factor The interrupt status flag corresponding to USB function interrupt status register is cleared to 0 by setting 1 to the interrupt status clear flag The configuration of USB function interrupt status register is shown in Figure 2 8 22 USB function interrupt enable register This register is used to set the USB function interrupt request factor The USB function interrupt request occurs when the request of interrupt which set the enable bit to 1 occurs The configuration of USB function interrupt enable register is shown in Figure 2 8 23 Rev 2 00 Oct 16 2006 page 151 of 354 7tENESAS REJ09B0340 0200
35. PU03 P14 to P17 pull u OO PU04 P20 to P23 pull u Oio PU05 P24 to P27 pull u O O PUO6 P30 to P33 pull up OO PU07 P34 to P37 pull up OO Note In memory expansion and microprocessor mode the content of this register can be changed but the pull up resistance is not connected Pull up control register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset ITITIT Pur 03FDi6 0016 Note 2 Bitsymbol Btname J Fuon Rw J PU10 P4o to P43 pull up Note 3 The corresponding port is pulled oio 1 PU11 P44 to P47 pull up high with a pull up resistor oio 0 Not pulled high PU12 P50 to P53 pul a Note 3 1 Pulled high oio PU13 P54 to P57 pull u oO PU14 P60 to P63 pull u OO PU15 P64 to P67 pull u oo PU16 P72 to P73 pull up Nore 1 OO PU17 P74 to P77 pull up Oi O Note 1 Since P70 and P71 are N channel open drain ports pull up is not available for them Note 2 This register becomes 0216 when reset under the following conditions a Hardware reset when Vcc is applied to the CNVss pin b Software reset if bit 1 and bit O of processor mode register 0 address 000416 102 or 112 before reset Note 3 In memory expansion and microprocessor mode the content of these bits can be changed but the pull up resistance is not connected Pull up control register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PUR2 03FE16 0016 Bitsymbol Biname Fm fR 4 PU20 P80 to P83 pull up The correspon
36. Setting UARTi transmit receive control register 1 i 0 to 3 50 UARTI transmit receive control register 1 ofol vict Address o3AD16 36D16 033D16 32D16 UARTI continuous receive mode enable bit 0 Continuous receive mode disabled Data logic select bit 0 No reverse Set to 0 in clock synchronous I O mode N oo Reception enabled UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Reception enable bit 1 Reception enabled Writing dummy data Note UARTO transmit buffer register Address 03AB16 03AA16 UOTB p 7 Ho UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB ae ee Setting dummy data Figure 2 5 19 Set up procedure of reception in serial interface special function slave mode with clock delay 2 Note Use MOV instruction to write to this register Start reception Checking completion of data reception b7 UARTI transmit receive control register 1 LOLI UiC1 Address 03AD16 36D16 033D16 32D16 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register Checking error b15 b8 UARTO receive buffer register Address 03AF16 O3AE16 UORB b7 bO b7 UART1 receive buffer reg
37. TA3 Timer A4 register Address 038F16 038E16 TA4 Can be set to 000016 to FFFF16 2 TimerA b7 Setting count start flag Count start flag Address 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2 2 13 Set up procedure of event counter mode reload type selected Rev 2 00 Oct 16 2006 page 19 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 TimerA 2 2 6 Operation of Timer A event counter mode free run type selected In event counter mode choose functions from those listed in Table 2 2 5 Operations of the circled items are described below Figure 2 2 14 shows the operation timing and Figure 2 2 15 shows the set up procedure Table 2 2 5 Choosed functions Count source Input signal to TAIN Pulse output function No pulses output counting falling edges Pulses output Input signal to TAIN Count operation type Reload type counting rising edges Free run type TAj overflow Factor for switching Content of up down flag between up and down Input signal to TAiouT Note j i 1 butj 4 wheni 0 Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count
38. The corresponding port register and port direction register are invalid UARTI transmit receive control register 1 i 0 to 3 b7 b6 b5 b4 b3 b2 bi bo Symbol UIC1 i 0 t03 03AD16 Bit Symbol Bit Name seri Transmit enable clock synchronous Address 036D16 033D16 032D16 Function ial O mode fe Transmit disabled bit Transmit enabled When reset 0216 Function RW UART mode Riw Transmit buffer empty flag Data present in transmit buffer register No data present in transmit buffer register Receive enable Rec bit 1 Rec eive disabled eive enabled Receive complete flag Data packet in receive buffer register No data packet in receive buffer register UARTI transmit interrupt cause select bit Transmit buffer empty TI 1 Transmit buffer completed TXEPT 1 UARTI continuous receive mode enable bit Continuous receive mode disabled Continuous receive mode enabled Set to 0 Data logic 0 No reverse Reverse select bit 1 Error signal output enable bit Set to 0 The value is indeterminate when read 0 Output disabled 1 Output enabled Note 1 Note 1 When disabling the error signal output set the UIERE bit to 0 after setting the UiMR register Figure 2 3 4 Serial l O related registers 3 Rev 2 00 Oct 16 2006 page 44 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Clock
39. This register sets endpoint x x 1 to 4 IN FIFO BUF_NUM This bit sets the starting location of the endpoint x x 1 to 4 IN FIFO per 64 bytes For example when IN FIFO is allocated starting at the 320th byte the set value is 0001012 BUF_SIZ This bit sets one buffer size of the endpoint x x 1 to 4 IN FIFO per 64 bytes For example when 256 bytes is set the set value is 01002 DBL_BUF With this bit being set to 1 IN FIFO of the corresponding endpoint is changed into double buffer mode The byte count for a valid IN FIFO becomes twice as much as the value specified by the BUF_SIZ at the time of double buffer Set carefully not to overlap with the FIFO start position of other endpoints CONTINUE Set this bit to 1 when continuous transmit is enabled The bit is valid only in bulk transfer The USB function control unit by dividing one buffer data equal to the byte count set in the BUF_SIZ in the IN FIFO into one packet size the maximum packet size set in the EPxIMP units transmits them one by one to the host PC When the last one packet is smaller than the size set in the EPxIMP it is transmitted as a short packet When continuous transmit mode is enabled the value set in the BUF_SIZ has to be equal to an integral multiple of the maximum packet size Pay attention to the following when setting this register Not exceed 3072 bytes in IN FIFO starting location IN FIFO size Not overlap endpoint FIFOs ea
40. USB EP2 IN max packet size register EP2IMP 02EA 6 02EBie6 USB EP2 IN FIFO configuration register EP2IFC 02EC16 02ED16 USB EP3 IN control status register EP3ICS 02EEi6 02EFt6 USB EP3 IN max packet size register EP3IMP 02F016 02F116 USB EP3 IN FIFO configuration register EP3IFC 02F216 02F316 USB EP4 IN control status register EP4ICS USB EP4 IN max packet size register EP4IMP USB EP4 IN FIFO configuration register EP4IFC Figure 2 8 8 USB registers memory mapping Rev 2 00 Oct 16 2006 page 137 of 354 REJ09B0340 0200 RENESAS 2 USB function USB EP1 OUT control status register EP1OCS USB EP1 OUT max packet size register EP1OMP USB EP1 OUT write count register EP1WC USB EP1 OUT FIFO configuration register EP 1OFC USB EP2 OUT control status register EP2OCS USB EP2 OUT max packet size register EP2OMP USB EP2 OUT write count register EP2WC USB EP2 OUT FIFO configuration register EP2OFC USB EP3 OUT control status register EP3O0CS USB EP3 OUT max packet size register EP3OMP USB EP3 OUT write count register EP3WC USB EP3 OUT FIFO configuration register EP3OFC USB EP4 OUT control status register EP40CS USB EP4 OUT max packet size register EP4OMP USB EP4 OUT write count register EP4WC USB EP4 OUT FIFO configuration register EP4OFC USB reserved USB reser
41. USB resume interrupt control register RSMIC 02BFi 02C016 USB reset interrupt control register RSTIC 02C1 16 USB SOF interrupt control register SOFIC 02C216 USB Vbus detect interrupt control register VBDIC 02C316 02C416 USB function interrupt control register USBFIC 02C516 USB address register USBA 02C616 02C716 USB power management register USBPM 02C816 02C916 USB interrupt status register USBIS 02CA16 02CBi6 USB interrupt clear register USBIC 02CC16 02CD16 USB interrupt enable register USBIE 02CE16 02CF16 02D016 USB frame number register USBFN 02D116 USB ISO control register USBISOC 02D216 02D316 USB endpoint enable register USBEPEN 02D416 02D516 USB DMAO request register USBDMA0 USB DMA1 request register USBDMA1 02D816 USB DMA2 request register USBDMA2 02D916 02DA16 USB DMA3 request register USBDMA3 02DBi6 02DC16 USB EPO control status register EPOCS 02DD16 02DE16 USB EPO max packet size register EPOMP 02DF 16 USB EPO OUT write count register EPOWC 02E016 02E116 USB EP1 IN control status register EP1ICS 02E216 02E3i6 USB EP1 IN max packet size register EP 1IMP 02E416 02E5i6 USB EP1 IN FIFO configuration register EP1IFC 02E6i6 02E7i6 USB EP2 IN control status register EP2ICS 02E8i6 02E916
42. b7 b0 T UARTi bit rate generator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 _____ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTI bit rate generator when transmission reception is halted Transmission enabled b7 b0 UARTI transmit receive control register 1 LI Jt ViCi Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Writing transmit data Note b15 b8 UARTO transmit buffer register Address 03AB16 03AA16 UOTB b7 b0 b7 b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Setting transmission data Setting transmission data 9th bit Note Use MOV instruction to write to this register When CTSi input level L Start transmission Checking the status of UARTi transmit receive control register i 0 to 3 br b0 UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled When transmitting continuously Writing next transmit data Note b15 b8 UARTO transm
43. gs Serial Sound Interface 1 RF register SSI1 RF d d d Serial Sound Interface 1 receive buffer register SS11RXB Figure 2 6 1 Memory map of Serial Sound Interface function related registers Rev 2 00 Oct16 2006 page 112 of 354 AS REJ09B0340 0200 RENES M30245 Group Serial Sound Interface x transmit buffer register b15 b8 b7 i b7 Symbol SSIxTXB x 0 1 Address 031516 031416 037516 037416 2 Serial sound interface When reset 000016 Function Transmit data Note 1 Note 1 For byte access write data to addresses 031416 and 037416 only Do not access to addresses 031516 and 037516 Serial Sound Interface x receive buffer register bo Symbol SSIxRXB x 0 1 Address 031716 031616 037716 037616 When reset 000016 Function Receive data Note 1 Note 1 For byte access write data to addresses 031616 and 037616 Do not access to addresses 031716 and 037716 Serial Sound Interface x RF register bO Symbol SSIxRF x 0 1 Address 031916 031816 037916 037816 When reset 000016 Function Rate feedback counter value Figure 2 6 2 Serial Sound Interface function related registers 1 Rev 2 00 Oct 16 2006 page 113 of 354 REJ09B0340 0200 7tENESAS M30245 Group Serial Sound Interface x mode register 0 b7 b6 b5 b4 b3 b2 bi bo
44. request bit o ae n Cleared to 0 when interrupt request is accepted or cleared by software Pp Timer A1 interrupt 1 a g request bit Figure 3 1 1 Operation timing of long period timers Rev 2 00 Oct 16 2006 page 295 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications Used for timer mode Timer AO interrupt request bit Timer A1 interrupt request bit Used for event counter mode Figure 3 1 2 Connection diagram of long period timers Rev 2 00 Oct 16 2006 page 296 of 354 7RENESAS REJ09B0340 0200 M30245 Group Setting timer AO 3 Timer A Applications Selecting timer mode and functions rofopoo ope ojo Re mode register Address 039616 Selection of timer mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Gate function select bit b4 b3 0 0 Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 00 fi 62 5ns source f XIN 16MHz f Xcin 32 768kHz 500ns 2us 976 56us Setting counter value b8 b0 b7 b0 ge E ER Setting timer A1 Selecting event counter mode and each function p7 22 Timer A1 mode register Address 039716 fofofofofofolol tam Selection of event counter mode Pulse output function select bit 0 Pu
45. 0 UARTO Bus col T UART2 Bus col T lision Start stop condition detection ouble error detection lision Start stop condition detection ouble error detection Bus collision interrupt IFSR7 request cause select bit 1 U UART1 Bus col U IART3 Bus col lision Start stop condition detection T rouble error detection lision Start stop condition detection Trouble error detection Figure 2 5 7 Serial interface special function related registers 6 Rev 2 00 Oct 16 2006 page 93 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Serial Interface Special Function 2 5 2 Operation of Serial Interface Special Function transmission in master mode without delay In transmitting data in serial interface special function master mode choose functions from those listed in Table 2 5 1 Operations of the circled items are described below Figure 2 5 8 shows the operation timing and Figures 2 5 9 and 2 5 10 show the set up procedures Table 2 5 1 Choosed functions Transfer clock Internal clock f1 fs f32 SSi port function SSi function disabled source External clock CLKi pin enable O SSi function enabled CLK polarity Output transmission data at Clock phase set O Without clock delay the falling edge of the transfer clock With clock delay Output transmission data at Serial input port set the rising edge of the transfer clock Tx
46. 0 invalid Transfer data 8 bits long 0 10 Serial I O mode Transfer data 9 bits long 011 12C mode Inhibited except in cases Inhibited except in cases listed above listed above CKDIR Internal external clock 0 Internal clock Internal clock select bit 1 External clock Note 1 External clock Note 1 STPS i petaen bit length select bit Ba 0 One stop bit 1 Two stop bits ili d parity select bit a Valid when bit 6 1 o A Odd parity O O Even parity PRYE Parity enable bit Invalid o Parity disabled aie Parity enabled att SLEP TxD RxD input output 0 Normal polarity switch bit Note 2 1 Reversed Note 1 When IC bus interface mode is selected set the port direction register for the corresponding oor SCLi to 0 or the port direction register to 1 and the port data register to 1 When a mode other than serial I O mode is selected set the port direction register for the corresponding port CLKi to 0 Note 2 Normally set to 0 Note 3 Set the RxDi pin s port direction register to O when receiving Figure 2 5 3 Serial interface special function related registers 2 Rev 2 00 Oct 16 2006 page 89 of 354 7tENESAS REJ09B0340 0200 M30245 Group UARTI transmit receive control register 0 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiCO i 0 to 3 Address 03AC16 036C16 033C16 032C16 2 Serial Interface Special Function When reset 0816 Bit name BRG count
47. 00 Oct 16 2006 page 304 of 354 REJ09B0340 0200 7tENESAS M30245 Group 3 Timer A Applications 3 4 Solution for External Interrupt Pins Shortage Overview The following are solution for external interrupt pins shortage Figure 3 4 1 shows the set up procedure Use the following peripheral function e Event counter mode of timer A Specifications 1 Inputting a falling edge to the TAOIN pin generates a timer AO interrupt Operation 1 Set timer AO to event counter mode set timer to 0 and set interrupt priority levels in timer AO 2 Inputting a falling edge to the TAOIN pin generates a timer AO interrupt Rev 2 00 Oct 16 2006 page 305 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications p Initialization of timer AO b7 b0 r fo oy Of of Of 07 oT 4 Timer AO mode register TAOMR Address 039616 Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAOout pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type When not using two phase pulse signal processing set this bit to 0 ue ee ie gt Timer AO register 0016 0016 TAO Address 038716 038616 b7 b0 0 Up down flag Address 038416 UDF Timer
48. 002616 002516 002416 Address 002916 002816 Initialization of DMA1 b7 b4 b3 b2 b1 b16b15 bo bo DMAO t lect regist oo oji 070 DmistiAdoressoeag 0S iI DMA request cause select bit 00100 Timer AO Software DMA request bit 0 Software is not generated 0016 b7 b0 b7 b23 b16 b15 0816 b7 b0 b7 b15 b0 b8 b7 a cc b0 b8 b7 0016 0016 DMA1 source pointer SAR1 DMA1 destination DAR1 pointer b0 b7 b0 0016 7F16 DMA1 transfer counter TCR1 b7 bo DX 1 0 1 oft f Address 003216 003116 003016 Address 003616 003516 003416 Address 003916 003816 N DMA1 control register DM1CON Address 003C16 Transfer unit bit select bit 1 8 bits Repeat transfer mode select bit 1 Repeat transfer DMA request bit 0 DMA not requested DMA enable bit 1 Enabled Source address direction select bit 0 Fixed Destination address direction select bit 1 Forward Continued to the next page Figure 3 5 3 Set up procedure of memory to memory DMA transfer 1 Rev 2 00 Oct16 2006 page 309 of 354 REJ09B0340 0200 RENESAS M30245 Group 3 DMAC Applications Continued from the previous page Initialization of timer AO b7 bo Ti A d i Leelee Taom tAddress 039616 Selection of timer mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Gate function select bi
49. 02B016 INTPT bit Note 0 Select non rate feedback interrupt transfer 1 Select rate feedback interrupt transfer ISO bit 0 Select non isochronous endpoint 1 Select isochronous endpoint Note When using the normal interrupt tranfer set O USB Endpoint x OUT control and status register EPxOCS x 1 4 Address 02B616 02BE16 02C616 02CE16 ISO bit 0 Select non isochronous endpoint 1 Select isochronous endpoint at Only when using isochronous tranfer Setting the USB ISO control register b15 b8 b7 bO b7 USB ISO control register Address 028C16 0 0 0 USBISOC 4 AUTO FLUSH bit 0 Hardware auto flush disabled 1 Hardware auto flush enabled ISO update bit 0 ISO update disabled 1 ISO update enabled Artificial SOF enable bit 0 Artificial SOF disabled 1 Artificial SOF enabled USB transmit receive process Figure 2 8 20 Initialization procedure of endpoint 1 Rev 2 00 Oct 16 2006 page 148 of 354 REJ09B0340 0200 7tENESAS 2 USB function M30245 Group 2 USB function 3 Disable of USB Function Control Unit After the USB function control unit being enabled if the system design requires to disable the USB function follow the procedure below 1 Disable the USB clock by clearing USB enable bit USBC7 to 0 2 Disable the U
50. 032A16 2 Clock Synchronous Serial I O When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Function Bit Symbol clock synchronous serial I O mode UART mode Transmit data Transmit data Transmit data 9th bit Nothing is assigned Write O when writing to these bits The values are indeterminate when read Note Use MOV instruction to write to this register UARTI receive buffer register i 0 to 3 fe Symbol bo UORB A U2RB U3RB Address 03AF16 03AE16 036F16 036E16 033F16 033E16 032F16 032E16 Function clock synchronous serial I O mode Receive data When reset Indeterminate Indeterminate Indeterminate Indeterminate Function UART mode Receive data Receive data 9th bit Nothing is assigned Write O when writing to these bits The values are indeterminate when read Arbitration lost detecting flag Note 1 0 Not detected Detected Invalid Overrun error flag Note 2 Framing error flag Note 2 No overrun error Overrun error Invalid No overrun error Overrun error No framing error Framing error Parity error flag Note 2 Invalid No parity error Parity error Error sum flag Note 2 Note 1 Always write 0 Note 2 Bits 15 to 12 are set to 00002 when the serial I O mode select bit bits 0 to 2 at addresses 03A816 036816 033816 032816 are set to
51. 0ojo jojoji1 CM1 All clock stop control bit 1 All clocks off stop mode Reserved bit Must always be set to 0 NOP instruction X 4 Insert at least four NOPs following JMP B instruction after Key input interrupt request generation the instruction that sets the all clock stop control bit to 1 S g Key input interrupt a A Store the registers Key matrix scan b7 bo Port PO register Address 03E016 PO Key scan data 1110 1101 1011 0111 Decision of key input data b0 0101010 a PO register Address 03E016 Key scan data Restore the registers REIT instruction N Figure 3 8 4 Set up procedure of controlling power using stop mode 2 Rev 2 00 Oct 16 2006 page 324 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 Controlling Power Applications 3 9 Controlling Power Using Wait Mode Overview The following are steps for controling power using wait mode Figure 3 9 1 shows the operation timing and Figures 3 9 2 to 3 9 4 show the set up procedure Use the following peripheral functions e Timer mode of timer A e Wait mode A flag named F WIT is used in the set up procedure The purpose of this flag is to decide whether or not to clear wait mode If F_WIT 1 in the main program the wait mode is entered if F_WIT 0 the wait mode is cleared Specifications 1 Connect a 32 768 kHz osci
52. 3 029016 029216 Address 029416 029616 When reset 000016 Bit Symbol Bit Name Function Reserved Must always be set to 0 DMAxR1 EP1 IN FIFO write request select bit DMAxR2 EP2 IN FIFO write request select bit DMAxR3 EP3 IN FIFO write request select bit DMAxR4 EP4 IN FIFO write request select bit 1 Selected 0 Not selected Reserved Must always be set to 0 DMAxR6 EP1 OUT FIFO read request select bit DMAxR7 EP2 OUT FIFO read request select bit DMAxR8 EP3 OUT FIFO read request select bit DMAxR9 EP4 OUT FIFO read request select bit 1 Selected 0 Not selected Reserved Must always be set to 0 Figure 2 8 50 USB DMAx x 0 to 3 request register Rev 2 00 Oct16 2006 page 207 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 DMA Request by Endpoint x OUT DMA Request Factors When endpoint 1 to 4 OUT FIFO write request select bit is set to the DMA request factor origin of USBO0 USB1 USB2 USB3 the DMA request factor includes the following three kinds On occurrence of an event when all the specified conditions have been satisfied for each factor the DMA request of DMA0 DMA1 DMA2 DMA3 occurs Factor 1 Conditions DMA enable bit of DMAi control register is set to 1 enable Any one of endpoint x x 1 to 4 OUT FIFO read request select bit in USB DMAx x 0 to 3
53. 3 Operation of Serial I O reception in clock synchronous serial I O mode csssseereeeeeeeees 49 2 3 4 Precautions for Serial I O in clock synchronous Serial I O mode cseeceseseeeeseeeeeeeeeeesneeeeeeeees 53 2 4 Clock Asynchronous Serial I O UART ccccseeeeeeeeeeeseeeseeeeeeeeeeeeeseeeeeeeeeeeseeeeeees 55 QA A OVONVIOW or a ra A pugesoodeseuuacusctycdde va0 Sagvas0ss EA aA aA ANN 55 2 4 2 Operation of Serial I O transmission in UART mode cccceceseeeeeeeeeseeeeeesesseeeeesneseeenenseeseenees 64 2 4 3 Operation of Serial I O reception in UART MOde s ecceeseessseeeeeeeeesenaeeeseeeeeeseeseseeeeeeseeseeneeneneees 68 2 4 4 Serial I O Precautions UART Mode cccccessceeeeeeesecceeesensceeseeseneeeesesnsecenseeseseeaesesneseeonenseseeones 72 2 4 5 Operation of Serial I O transmission used for SIM interface cccssseeneeesseeeeeesessceeeeeesseeneees 73 2 4 6 Operation of Serial I O reception used for SIM interface ccscccsseeeeseeeeeeeeeseseeeeeeeeeeesneenensees 77 2 4 7 Clock Signals in used for the SIM Interface ccccescceseseeeeeseeeeneeeeeeeeeesseaeseneeeesseaesenseeeessaeseaseeeeeeeees 81 2 5 Serial Interface Special FUNCTION ccceeeeeeeeeeeeeeeeeesneeeeeeeeeenseeeeeeeeeeeseeeeeeeeeeeeeeess 85 225 1 OVENWIOW onena a A AA peauootooss vue weds Saaeunod AAN 85 2 5 2 Operation of Serial Interface Special Function tra
54. 4 1 Software waits and bus cycles A CSxW CSExW Bus Cycles iii Note 2 Note 2 2 BCLK cycles 2 BCLK cycles m a 1 BCLK cycle 1 BCLK cycle ie 2 BCLK cycles 2 BCLK cycles External memory oo w 3 BCLK cycles 3 BCLK cycles areas o 10 4 BCLK cycles 4 BCLK cycles o n Donost _ _ _ i 1 BCLK cycle 2 BCLK cycles Note 1 When using the RDY signal set to 0 Note 2 Set CSEiW bits i 0 to 3 after setting the corresponding CSiW bit i 0 to 3 of the CSR register to 0 When CSiW bits are set to 1 CSEiW bits must be returned to 002 Rev 2 00 Oct 16 2006 page 343 of 354 AS REJ09B0340 0200 RENES M30245 Group 4 External Buses Single chip mode 0000016 0040016 Internal RAM area XXXXX16 BCLK x 1 Type No Address XXXXX16 Address YYYYY16 M30245FCGP 02BFF16 E000016 M30245MC XXXGP 02BFF16 E000016 M30245M8 XXXGP 017FF16 F000016 Internal ROM area e Memory expansion mode and microprocessor examples apply with the following settings CS0 1 CS0 output enabled CS3 1 CS3 output enabled CSOW 0 with CSO wait CS3W 1 without CS3 wait CSEOW 012 CSO 2 wait expansion Memory expansion mode Microprocessor mode 0000016 0000016 0040016 0040016 Internal RAM area BCLK x 1 Internal RAM area BCLK x 1 XXXXX16 XXXXX16 Internal area reserved Internal area reserved 0400016 Read BCLK x 1 0400016 Read BCLK x 1 CS3 external ar
55. 8 25 and the USB function interrupt routine is shown in Figure 2 8 26 Rev 2 00 Oct 16 2006 page 158 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB function interrupt control register Address 005D16 b7 b0 PEMA USBFIC L Interrupt priority level select bit Interrupt request bit 0 Interrupt not requested USB function interrupt enable register Address 028816 b15 b8 b7 bO b7 b0 0 USBIE EP1 IN interrupt enable bit EP1 OUT interrupt enable bit EP2 IN interrupt enable bit EP2 OUT interrupt enable bit EP3 IN interrupt enable bit 0 Disabled 1 Enabled EP3 OUT interrupt enable bit EP4 IN interrupt enable bit EP4 OUT interrupt enable bit Error interrupt enable bit USB function interrupt status register Address 028416 b15 b8 b7 bO b7 0 USBIS b0 a EP1 IN interrupt status flag EP1 OUT interrupt status flag EP2 IN interrupt status flag EP2 OUT interrupt status flag EP3 IN interrupt status flag EP3 OUT interrupt status flag EP4 IN interrupt status flag EP4 OUT interrupt status flag Error interrupt status flag 0 No interrupt request 1 Interrupt request issued USB function interrupt clear register Address 028616 b15 b8 b7 0 USBIC bO b7 bO
56. 9 3 Operation of A D Converter in one shot mode an external trigger selected In one shot mode choose functions from those listed in Table 2 9 3 Operations of the circled items are described below Figure 2 9 6 shows timing chart and Figure 2 9 7 shows the set up procedure Table 2 9 3 Choosed functions Operation clock AD Divided by 4 fap divided by 3 fap divided by 2 fap fab Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Trigger for starting Software trigger A D conversion Trigger by ADTRG Sample amp Hold Not activated Activated Operation 1 If the level of the ADTRG changes from H to L with the A D conversion start flag set to 1 the A D converter begins operating 2 After A D conversion is completed the content of the successive comparison register con version result is transmitted to AD register i At this time the A D conversion interrupt re quest bit goes to 1 Also the A D converter stops operating 3 If the level of the ADTRG pin changes from H to L the A D converter carries out conversion from step 1 again If the level of the ADTRG pin changes from H to L while conversion is in progress the A D converter stops the A D conversion in process and carries out conver sion from step 1 again 1 Start A D conversion 2 A D conversion is 3 Start A D complete conversion 8 bit resolution
57. A D converter stopped RE REI ns 1 VREF VREF VREF VREF VREF 10th i n8in7 n6 n5in4 n3in2 n1 _ _ JV 2 4 1024 2048 M Conversion complete n8 n7 n6 n5 n4 n3 n2 n1 n0 This data transfers to the bit 0 to bit 9 of AD register i Result of A D conversion Theoretical A D conversion characteristic Ideal A D conversion characteristic M oH 0 VREF y 4 VREF y 9 x3 WBEEy 4021 VREE y 1022 VREF x 4923 VREF lt gt 1024 1024 1024 1024 1024 VREF a x 0 5 Analog input voltage 1024 ome q Figure 2 9 18 Theoretical A D conversion characteristics 10 bit mode Rev 2 00 Oct 16 2006 page 232 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter 2 9 10 Method of A D Conversion 8 bit mode 1 In 8 bit mode 8 higher order bits of the 10 bit successive comparison register becomes A D conversion result Hence if compared to a result obtained by using an 8 bit A D converter the voltage compared is different by 3 VREF 2048 see what are underscored in Table 2 9 10 and differences in stepping points of output codes occur as shown in Figure 2 9 19 Table 2 9 10 The comparison voltage in 8 bit mode compared to 8 bit A D converter 8 bit mode 8 bit A D converter Comparison voltage Vref Optimal conversion characteristics of 8 bit A D converter VREF 5 12 V Output c
58. AO up down flag 0 Down count XXX a flag Address 038016 Timer AO count start flag 1 Starts counting One shot start flag Address 038216 Reserved bit Must always be 0 Timer AO event trigger select flag b7 b6 0 0 Input on TAON is selected Note 1 C Note Set the corresponding port direction register to 0 Setting interrupt priority levels in timer AO b7 bo Timer AO interrupt control register Address 005416 ebb TT TAOIC Interrupt control level set a value 1 to 7 Initialization of port P7 direction register PTTL oa P7 direction register Address 03EF 16 Port P71 direction register 0 Input mode Setting interrupt enable flag I flag i Figure 3 4 1 Set up procedure of solution for a shortage of external interrupt pins Rev 2 00 Oct 16 2006 page 306 of 354 ENESAS REJ09B0340 0200 i M30245 Group 3 DMAC Applications 3 5 Memory to Memory DMA Transfer Overview The following are steps for changing both source address and destination address to transfer data from memory to another The DMA transfer utilizes the workings that assign a higher priority to the DMAO transfer if transfer requests simultaneously occur in two DMA channels Figure 3 5 1 shows the operation timing Figure 3 5 2 shows the block diagram and Figures 3 5 3 and 3 5 4 show the set up procedure Use the following peripheral functions e Timer mode of timer A e Two DMAC channels
59. Address 038316 TRGSR Timer A2 event trigger select bit b3 b2 0 0 Input on TA2IN is selected Note 2 Timer A3 event trigger select bit b5 b4 0 0 Input on TA3IN is selected Note 2 Note 2 Set the corresponding port direction register to 0 Setting divide ratio b15 b8 b7 bO b7 bo ee Timer A2 register Address 038B16 038A16 TA2 Timer A3 register Address 038D16 038C16 TA3 o Can be set to 000016 to FFFF16 E J Setting count start flag b7 bi Count start flag Address 038016 TABSR Timer A2 count start flag Timer A3 count start flag Start count 2 Timer A Figure 2 2 17 Set up procedure of two phase pulse signal process in event counter mode normal mode selected Rev 2 00 Oct 16 2006 page 23 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 8 Operation of timer A two phase pulse signal process in event counter mode multiply by 4 mode selected In processing two phase pulse signals in event counter mode choose functions from those listed in Table 2 2 7 Operations of the circled items are described below Figure 2 2 18 shows the operation timing and Figure 2 2 19 shows the set up procedure Table 2 2 7 Choosed functions Count operation type Reload type Processing two phase Normal processing pulses Note o 4 multiplication processing O Free run type Note Timer A3 alone can be selected Timer A2 is so
60. Address 039616 TAiMR i 0 to 4 Selection of PWM mode 1 Must always be 1 in PWM mode External trigger select bit 0 Falling edge of TAiIN pin s input signal Note Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 1 Functions as a 8 bit pulse width modulator Count source select bit b7 b6 to 039A16 Count Count source period 00 fi source f XIN 16MHz f XCIN 32 768kHz 01 fs 10 f32 62 5ns 1 1 fc32 500ns 2us Note 1 Set the corresponding port direction register to 0 976 56us yy Clearing timer Ai interrupt request bit Please refer to the notes on the pulse width modulation mode of Timer A Timer Ai interrupt control register b7 bO XXXXo Addresses 005416 004516 004716 005716 005916 TAIIC i 0 to 4 Interrupt request bit Setting event trigger select bit b7 Timer AO event trigger select bit 00 Input on TAON is selected Note Trigger select register ae bO One shot start flag fol taddress 038216 TLE LE LLI taddress 038316 ONSF TRGSR Timer A1 event trigger select bit 9 6 Input on TAIN is selected Note 2 Timer A2 event trigger select bit 6 6 Input on TA2IN is selected Note 2 Timer A3 event trigger select bit 6 6 Input on TASIN is selected Note 2 Note 2 Set the corresponding port direction register to
61. BCLK f Xin 8 CM07 0 CMO06 1 CM07 0 Note 1 CMO06 1 Main clock is oscillating Sub clock is oscillating Low speed mode CM07 0 Note 1 3 lt _ BCLK f Xcin y CM07 1 CM07 1 Note 2 CMO5 0 CMO5 1 Main clock is oscillating CM04 1 Sub clock is stopped C CMO6 0 Notes 1 3 High speed mode Medium speed mode divided by 2 mode BCLK f Xin CM07 0 CMO06 CM17 0 CM16 0 0 BCLK f Xin 2 CM07 0 CMO6 0 CM17 0 CM16 1 Medium speed mode divided by 4 mode Medium speed mode divided by 16 mode BCLK f Xin 4 CM07 0 CMO6 O CM17 1 CM16 0 BCLK f Xin 16 CM07 0 CMO6 0 CM17 1 CM16 1 Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 1 Note 2 CMO5 1 BCLK f Xcin CM07 1 CM07 CM06 0 Note 1 0 Note 3 Note 1 Switch clock after oscillation of main clock is sufficiently stable Note 2 Switch clock after oscillation of sub clock is sufficiently stable Note 3 Change CM06 after changing CM17 and CM16 Note 4 Transit in accordance with arrow Figure 2 16 1 State transition diagram of power control mode Rev 2 00 Oct 16 2006 page 275 of 354
62. Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TAIN pin External trigger input rising edge of input signal to the TAIN pin Timer overflow TAj TAk overflow Writing 1 to the one shot start flag Note j i 1 but j 4 wheni 0 k i 1 but k 0 wheni 4 Operation 1 Setting the one shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source At this time the TAiOUT pin outputs an H level 2 The instant the value of the counter becomes 000016 the TAiOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer Ai interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value in the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TAiOUT pin outputs an L level At this time the timer Ai interrupt request bit goes to 1 n reload register content 9 2 Stop count 1 Start count 3 Start count
63. Count source period 01 fs source f X N 16MHz f XciN 32 768kHz 10 f32 62 5ns 1 1 fc32 500ns ae 2 Note Set the corresponding port direction register to 0 E 976 56us aa a Setting divide ratio Timer AO register Address 038716 038616 TAO er 8 bo Timer A1 register Address 038916 038816 TA1 Timer A2 register Address 038B16 038A16 TA2 Po Timer 3 register Address 038016 038C16 TAB Timer A4 register Address 038F16 038E16 TA4 Ooo Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 LPT CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2 2 9 Set up procedure of timer mode gate function selected 7tENESAS S M30245 Group 2 TimerA 2 2 4 Operation of Timer A timer mode pulse output function selected In timer mode choose functions from those listed in Table 2 2 3 Operations of the circled items are described be
64. DMA interrupt request bit changes to 1 simultaneously 4 After DMAi transfer counter is underflowed when the next DMA request is generated DMA transfer is repeated from 1 1 Request signal for a DMA transfer occurs 3 Underflow i 2 Data transfer begins i LIL E r Dummy cyo Destination Dummy cycle i Destination Dummy cycle E A y cyc jj er Ne x ly cy icPU use soureey y CPU use Source l X y CPU use Address bus CPU use RD signal WR signal Dummy cycle Destination yy Dummy cycle Destination i Dumny cycle x ination x y cy i i aai th Data bus l CPU use y 1 i cpu use Source x Y CPU use oure y Y cpu use Write signal to software DMAi request bit DMAi request bit b116 iy DMA transfer Indeterminate Xy X counter l DMAi T interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Dmi T enable bit In the case in which the number of transfer times is set to 2 Figure 2 10 7 Example of operation of repeated transfer mode Rev 2 00 Oct 16 2006 page 247 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 DMAC Setting DMAi reques
65. FORCE_STALL flag is cleared to 0 by setting 1 to this bit CLR_DATA_ERR bit The DATA_ERR flag is cleared to 0 by setting 1 to this bit Rev 2 00 Oct 16 2006 page 183 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function TOGGLE_INIT bit This bit initializes data toggle sequence bit in bulk interrupt transfer With this bit being set to 1 the PID of the next packet to be received from the host CPU becomes DATAO When initialization of the data toggle sequence is requested from the host CPU at the time of configuration etc set TOGGLE_INIT bit and initialize PID to DATAO before starting the OUT end point communication At this time the internal read write counter of OUT FIFO is also initialized On completing PID initialization this bit is automatically cleared to O FLUSH bit This bit controls the OUT FIFO packet With this bit being set to 1 one buffer data received in OUT FIFO is flushed out from the OUT FIFO When there is one buffer data in OUT FIFO the OUT FIFO becomes empty At this time the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from 112 102 to 002 When there are two buffer data in OUT FIFO the older data is flushed out from the OUT FIFO At this time the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from 112 to 102 This indicates that one more buffer data is left inside the OUT FIFO The receive data may be destroyed if this bit i
66. Group 2 TimerA 2 2 12 Precautions for Timer A timer mode 1 To clear reset the count start flag is set to O Set a value in the timer Ai register then set the flag to 1 2 Reading the timer Ai register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Ai register with the reload timing shown in Figure 2 2 28 gets FFFF16 Reading the timer Ai register after setting a value in the timer Ai regis ter with a count halted but before the counter starts counting gets a proper value Reload Read value Hex ee aie FFFF ee Time n reload register content Figure 2 2 28 Reading timer Ai register Rev 2 00 Oct 16 2006 page 34 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 13 Precautions for Timer A event counter mode 1 To clear reset the count start flag is set to O Set a value in the timer Ai register then set the flag to 1 2 Reading the timer Ai register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Ai register with the reload timing shown in Figure 2 2 29 gets FFFF16 by underflow or 000016 by overflow Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts count ing gets a proper value 3 Please note the standards for the differences between the 2 pul
67. Interface Special Function 2 5 3 Operation of Serial Interface Special Function reception in master mode with clock delay In receiving data in serial interface special function master mode choose functions from those listed in Table 2 5 2 Operations of the circled items are described below Figure 2 5 11 shows the operation timing and Figures 2 5 12 and 2 5 13 show the set up procedures Table 2 5 2 Choosed functions Transfer clock Internal clock f1 fa f32 SSi port function SSi function disabled source er ae u External clock CLKi pin enable SSi function enabled CLK polarity Output reception data at Clock phase set Without clock delay the rising edge of the transfer clock With clock delay Output reception data at Serial input port set TxDi RxDi selected the falling edge of the master mode transfer clock Contniols receive Disabled STxDi SRxDi selected Enabled slave mode Operation 1 Set an SS port of the transmitter side IC to output L level 2 Writing dummy data to the UARTi transmit buffer register setting the receive enable bit to 1 and the transmit enable bit to 1 makes the data receivable status ready 3 In synchronization with the first rising edge of the transfer clock the input signal to the RxDi pin is stored in the highest bit of the UARTi receive register Then data is taken in by shifting right the content of the UARTi reception da
68. Microcomputer Receiver side IC Example of operation 1 Output L at the receiver side IC 4 Transmission is complete 2 Transmission enabled 5 Transmit next data 3 Start transmission Tc Transfer clock Port Transmit enable bit TE Data is set to UARTI transmit buffer register Transmit buffer empty flag TI Transferred from UARTi transmit buffer register to UARTi transmit register w 200000 002200 0000D Transmit register 4 1 empty flag o o Loo E TXEPT f Transmit interrupt request bit IR i E X A Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Te TCLK 2 n 1 fi The above timing applies to the following settings fi frequency of BRGi count source f1 f8 32 Internal clock is selected n value set to BRGi e CLK polarity select bit 0 e Transmit interrupt cause select bit 0 Figure 2 5 8 Operation timing of transmission in serial interface special function master mode without clock delay Rev 2 00 Oct 16 2006 page 95 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Setting UARTi transmit receive mode register i 0 to 3 UARTI transmit receive mode register UiMR Address 03A816 36816 033816 32816 Must be fixed to 001 Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mod
69. Not selected Selected Data logic select function No reverse Operation 1 Reverse Setting the receive enable bit to 1 readies data receivable status At this time output from the RTSi pin goes to L level to inform the transmission side that the receivable status is ready 2 When the first bit the start bit of reception data is received from the RxDi pin output from the RTS goes to H level Then data is received bit by bit in sequence LSB MSB and stop bit s 3 When the stop bit s is are received the content of the UARTi receive register is transmitted to the UARTi receive buffer register At this time the receive complete flag goes to 1 to indicate that the reception is completed the UARTi receive interrupt request bit goes to 1 and output from the RTS pin goes to L level 4 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read Note Rev 2 00 Oct 16 2006 page 68 of 354 REJ09B0340 0200 e Set RxDi pin s port direction register to 0 7tENESAS M30245 Group Example of wiring Microcomputer Example of operation BRGi s count source Receive enable bit RxDi Transfer clock Receive complete flag RTSi Receive interrupt request bit 1 Reception enabled 2 Start reception Reception started when transfer clock is generated by falling
70. PWM mode 1 Must always be 1 in PWM mode 1 Selected by event trigger select register Count source b0 TEEF Timer Ai mode register i 0 to 4 Address 039616 to 039A16 1 Rising edge of TAiIN pin s input signal Note 1 0 Functions as a 16 bit pulse width modulator Count source period f XIN 16MHz f XCIN 32 768kHz 62 5ns 11 fc32 500ns 2us Note 1 Set the corresponding port direction register to O i 976 56us A Clearing timer Ai interrupt request bit Please refer to the notes on the pulse width modulation mode of Timer A bO Timer Ai interrupt control register b7 XXXXJo Addresses 005416 004516 004716 005716 005916 TAIIC i 0 to 4 Interrupt request bit fo Setting event trigger select bit bO One shot start flag b7 Jo Address 038216 ONSF Timer AO event trigger select bit b7 b6 00 Input on TAOIN is selected Note Trigger select register Address 038316 TRGSR Timer A1 event trigger select bit b1 bO 0 0 Input on TATIN is selected Timer A2 event trigger select bit 66 Input on TA2IN is selected Timer A3 event trigger select bit b5 b4 i 0 0 Input on TA3IN is selected Note 2 Set the corresponding port direction register to 0 Timer A4 event trigger select bit 6 Input on TA4IN is selected Note 2 Note 2 Note 2 Note 2 Setting PWM
71. REJ09B0340 0200 2 Timer A M30245 Group 2 TimerA 2 2 10 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 10 Operations of the circled items are described below Figure 2 2 22 shows the operation timing and Figures 2 2 23 and 2 2 24 show the set up procedure Table 2 2 10 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition External trigger input falling edge of input signal to the TAIN pin External trigger input rising edge of input signal to the TAiIN pin Timer overflow TAj TAk overflow Note j i 1 butj 4wheni 0 k i 1 butk 0 wheni 4 Operation 1 If the TAiIN pin input level changes from L to H with the count start flag set to 1 the counter performs a down count on the count source Also the TAiOUT pin outputs an H level 2 The TAiOUT pin output level changes from H to L when a set time period elapses At this time the timer Ai interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAiOUT outputs an L level Note e The period of PWM
72. REJ09B0340 0200 7tENESAS M30245 Group 2 Power Control 3 Returning from stop mode The stop mode can be canceled by hardware reset or by generating an interrupt request If an inter rupt is to be used to cancel stop mode that interrupt must first have been enabled and the priority level of the interrupt not to be used for clearing must be set to level 0 before changing to stop mode If an interrupt is used to cancel stop mode that interrupt routine is processed If only a hardware reset and NMI interrupt are used to cancel stop mode the priority level of all interrupts must be set to level 0 before changing to stop mode When changing from high speed medium mode to stop mode and at reset the main clock division select bit 0 bit 6 at address 000616 is set to 1 When changing from low speed low power dissipa tion mode the value before stop mode is retained 4 Returning form wait mode The wait mode can be canceled by hardware reset or by generating an interrupt request If an inter rupt is to be used to cancel wait mode that interrupt must first have been enabled and the priority level of the interrupt not to be used for clearing must be set to level 0 before changing to wait mode If an interrupt is used to cancel wait mode the microcomputer selects the clock used when the WAIT instruction is executed for BCLK and restarts operating in that interrupt routine If only a hardware reset or NMI interrupt will be used to cancel w
73. REJ09B0340 0200 i M30245 Group 2 Watchdog Timer 6 Registers related to the watchdog timer Figure 2 12 1 shows the memory map of watchdog timer related registers and Figure 2 12 2 shows watchdog timer related registers 000E16 Watchdog timer start register WDTS 000F16 Watchdog timer control register WDC 001016 Figure 2 12 1 Memory map of watchdog timer related registers Watchdog timer control register b7 b6 b5 b4 b3 b2 bi Symbol Address When reset Tele LLL woe O00Fis 000X000 Btgmba High order bit of Watchdog timer Reserved bit Must always be set to 0 T Divided by 16 WDC7 Prescaler select bit Divided by 128 Watchdog timer start register b7 bo Symbol Address When reset Loo O WDTS 000E16 Indeterminate ction The Watchdog timer is initialized and starts counting after the first write instruction to this register after reset Writing any value to this register resets the counter to 7FFF16 Figure 2 12 2 Watchdog timer related registers Rev 2 00 Oct 16 2006 page 255 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Watchdog Timer 2 12 2 Operation of Watchdog Timer Watchdog timer interrupt The following is an operation of the watchdog timer using watchdog timer interrupt Figure 2 12 3 shows the operation timing and Figure 2 12 4 shows the set up procedure Operation 1 Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it t
74. RTS function is selected Note 4 Data present in transmit register during transmission No data present in transmit register transmission completed CTS RTS function enabled CTS RTS function disabled 2 Clock Synchronous Serial I O When reset 0816 Function During UART mode b1 b0 00 f1is selected 0 1 f8 is selected 10 f32is selected 1 Inhibited Valid when bit 4 0 CTS function is selected Note 1 RTS function is selected Note 4 Data present in transmit register during transmission No data present in transmit register transmission completed CTS RTS function enabled CTS RTS function disabled Data output select bit Note 2 CLK polarity select bit UFORM Transfer format select bit Note 3 TxDi SDAi and SCLi pin is CMOS output TxDi SDAi and SCLi pin is N channel open drain output Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Note 1 Set the corresponding port direction register to 0 Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output ee and SCLi pin is CMOS output TxDi SDAi and SCLi pin is N channel open drain output Note 3 Only clock synchronous serial I O mode and 8 bit UART mode are valid Note 4
75. SIM card F Hz Timer Ak counter set value 1 Rev 2 00 Oct 16 2006 page 83 of 354 REJ09B0340 0200 7tENESAS clock 1116 1 16 17856 1 32 35712 1 64 71424 Combination in which the F D itself does not become an integer 2 SIM interface UARTI bit rate oie M30245 Group Table 2 4 9 TimerAi register adjustment factor SIM card internal clock F Hz Bit rate D 2 O il 1 4 1 8 1 16 11904 2975 1 32 72 93 44 1 64 23808 5951 1 558 279 2 4 44 12 93 1 2 174 2232 5 1 16 8928 2231 1 32 17856 4463 1 64 35712 8927 1 2 1488 371 1 8 1 16 1 32 1164 _ A 0 gt O A Combination in which the F D itself does not become an integer Setting example under the following conditions f XIN 16 MHz Timer Aj counter set value 3 UARTi bit rate generator set value 0 Rev 2 00 Oct 16 2006 page 84 of 354 RENESAS REJ09B0340 0200 7 4 n 1488 al el 93l 1116 278 ta 2976 1 8 4464 1115 11904 2975 7 4 a zaa ass aseol al 1860 2 4 ie a el tage 374 aa 185 ava tes ee 743 at s952 1487 1 32 47616 11903 1 64 95232 23807 a 1se a 7 eT raal 15 1 2 6 1 7440 2 SIM interface Timer Ai SiM ear Bitrate Timer Aj value interna Glog D F D value F Hz 27 55 1115 92 3 1487 8 7 7 4 4 46 2 7440 Combination impossible to deal with due to the current spe
76. Synchronous Serial I O 2 3 2 Operation of Serial I O transmission in clock synchronous serial I O mode In transmitting data in clock synchronous serial I O mode choose functions from those listed in Table 2 3 1 Operations of the circled items are described below Figure 2 3 5 shows the operation timing and Figures 2 3 6 and 2 3 7 show the set up procedures Table 2 3 1 Choosed functions Transfer clock Internal clock f1 fs f32 Transfer clock LSB first source External clock CLKi pin MSB first CTS function CTS function enabled Transmission Transmission buffer empty interrupt factor CTS function disabled p Transmission complete CLK polarity Output transmission data at the falling edge of the transfer clock Data logic select No reverse function Reverse Output transmission data at E the rising edge of the kes RxD I O t transfer clock polarity reverse bit Reverse Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTi transmit buffer register makes data transmissible status ready 2 When input to the CTSi pin goes to L level transmission starts the CTSi pin must be controlled on the reception side 3 In synchronization with the first falling edge of the transfer clock transmission data held in the UARTIi transmit buffer register is transmitted to the UARTIi transmit register At this time the UARTIi transmit in
77. TA4n is selected Note 2 S b15 b7 a Setting divide ratio Timer AO register Address 038716 038616 TAO ba Timer A1 register Address 038916 038816 TA1 bO b7 bo Timer A2 register Address 038B16 038A16 TA2 OoOo TS OO y S E Timer A3 register Address 038D16 038C16 TA3 Timer A4 register Address 038F16 038E16 TA4 A Can be set to 000016 to FFFF16 T Setting count start flag b7 bo XXX Count start flag Address 038016 TABSR L Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2 2 15 Set up procedure of event counter mode free run type selected Rev 2 00 Oct 16 2006 page 21 of 354 REJ09B0340 0200 7tENESAS 2 TimerA M30245 Group 2 TimerA 2 2 7 Operation of timer A two phase pulse signal process in event counter mode normal mode selected In processing two phase pulse signals in event counter mode choose functions from those listed in Table 2 2 6 Operations of the circled items are described below Figure 2 2 16 shows the operation timing and Figure 2 2 17 shows the set up procedure Table 2 2 6 Choosed functions Count operation type Reload type Free run type Two phase pulses Normal processing process Note 4 multiplication processing Note Timer A3 alone can be selected Time
78. The INTST8 is set to 1 in one of the following cases e The FORCE_STALL flag of endpoint 0 control and status register EPOCS is set to 1 e The SETUP_END flag of EPOCS is set to 1 e The UNDER_RUN flag of USB endpoint x IN control and status register EPxICS addresses 029E 16 02A416 O2AA16 02B016 is set to 1 Due to delay in writing of data to FIFO underrun has occurred at any one of the IN endpoints that are used for isochronous transfer e The OVER_RUN flag of USB endpoint x OUT control and status register EPxOCS addresses 02B616 02BE16 02C616 0O2CE16 is set to 1 Due to delay in reading of data from FIFO overrun has occurred at any one of the OUT endpoints that are used for isochronous transfer e The FORCE_STALL flag of EPxOCS is set to 1 e The DATA_ERR flag of EPxOCS is set to 1 Rev 2 00 Oct 16 2006 page 155 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 4 USB Reset Interrupt This interrupt is used for detection of the USB reset This occurs when the USB function control unit has received reset signal from the host CPU or detected SEO on the D D line for at least 2 5us At this time all the USB internal registers are made into reset state To resume communication each endpoint needs to be initialized When using the USB reset interrupt set the interrupt priority level at USB reset interrupt control register RSTIC address 005A 16 5 USB Suspend I
79. The configuration of USB endpoint x x 1 to 4 IN control and status register is shown in Figure 2 8 46 USB Endpoint x IN Control and Status register b15 b8 b7 b0 b7 Symbol Address When reset ojo l AE EPxICS x 1 4 029Et6 02A416 000316 E a a a ae 02AA16 02B016 Bit Symbol Bit Name Function INxcSRO IN_BUF_STS0 flag a m indicate the EPx IN buffer status 0 0 No data set in the IN buffer INxCSR1 IN_BUF_STS1 flag 0 1 Single buffer mode N A Double buffer mode one data set in the IN buffer 1 0 Single buffer mode N A Double buffer mode N A 1 1 Single buffer mode one data set in the IN buffer Double buffer mode two data sets in the IN buffer INxCSR2 UNDER RUN flag No underrun detected Underrun detected INxCSR3_ SET_IN_BUF_RDY No action Data set loaded to the IN buffer updates IN buffer status flags INxCSR4 CLR_UNDER_RUN O No action Clears UNDER_RUN flag No action INxCSR5 TOGGLE_INT Initialize the next data PID as a DATAO for transmission No action INxCSR6 FLUSH Flush out one data set INxCSR7 INTPT Select non rate feedback interrupt transfer Select rate feedback interrupt transfer Select non isochronous endpoint INxeSre ISO Select isochronous endpoint No STALL by CPU INxCSR9 SEND_STALL STALL by CPU AUTO_SET disabled INxCSR10 AUTO_SET AUTO_SET enabled
80. UART mode Transfer format select bit Must be 0 LSB first in direct format Setting UART transmit receive control register 1 i 0 to 3 ue PO UARTI transmit receive control register 1 ool vict Address o3ADi6 36D16 033D16 32D16 UARTI transmit interrupt cause select bit 1 Transmission completed TXEPT 1 Must be fixed to 0 in UART mode Data logic select bit Must be 0 no reverse in direct format Error signal output enable bit in UART mode 1 Output enabled Continued to the next page Figure 2 4 14 Set up procedure of transmission in UART mode used for SIM interface 1 Rev 2 00 Oct 16 2006 page 75 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface Continued from the previous page Setting UARTIi bit rate generator i 0 to 3 b7 bO TTTLUIT TT UARTI bit rate generator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 ____ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTI bit rate generator when transmission reception is halted a _ Transmission enabled b7 b0 UARTi transmit receive control register 1 ay i vict Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note Note Set RXD pin s port direction register to 0 a Writing transmit data Note b8 U
81. UARTIi special mode register 3 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UISMR3 i 0 to 3 03A516 036516 033516 032516 0016 Bit Name Function SS port function unction disabled enable bit Note 1 unction enabled No clock delay Clock phase set bit Clock delay Serial input port Select TxDi and RxDi master mode set bit posp Select STxDi and SRxDi slave mode Clock output CLKi is CMOS output select bit CLKi is N channel open drain output No fault error Fault error flag Fault error Note 2 SDA TxDi digital 7 b6 b5 delay time set bit 0 0 0 No delay Notes 3 4 00 1 1 to 2 cycle of UIBRG count source 0 1 0 2 to 3 cycle of UIBRG count source 0 3 to 4 cycle of UIBRG count source 1 4 to 5 cycle of UIBRG count source 1 5 to 6 cycle of UIBRG count source 1 6 to 7 cycle of UIBRG count source 1 o 8 cycle of UIBRG count source Set SS function after setting CTS RTS disable bit bit 4 of UARTI transfer receive control register 0 to 1 Only 0 may be written These bits are used for SDAi TxDi output digital delay when using UARTI for I C interface Otherwis set to 000 The amount of delay varies with the load on SCLi and SDAi pins When external clock is selected delay is increased by approximately 100ns Figure 2 5 6 Serial interface special function related registers 5 Rev 2 00 Oct 16 2006 page 92 of 35
82. a request valid B To processing of request invalid Valid Setting of USB endpoint 0 control and status register Continued on a status stage on CD b7 USB endpoint 0 control and status register 0 1 EPOCS Address 029816 CLR_OUT_BUF_RDY bit 1 Clear OUT_BUF_RDY flag CLR_SETUP flag 1 Clear SETUP flag Writing of transmit data on data stage b15 b8 b7 bO b7 USB endpoint 0 IN FIFO data register ae EPO Address 02E016 Write the configuration value one byte Continued on next page Figure 2 8 38 Device configuration notification processing routine 1 when receiving GET_CONFIGURATION request Rev 2 00 Oct 16 2006 page 180 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function Continued from previous page Setting of USB endpoint 0 control and status reister Note 1 or D b7 USB endpoint 0 control and status register 0 1 EPOCS Address 029816 SET_IN_BUF_RDY bit 1 Set IN_BUF_RDY flag to 1 SET_DATA_END bit 1 Set DATA_END flag to 1 S Note 1 Set the SET_IN_BUF_RDY bit and the SET_DATA_END bit simultaneously The USB function control unit is shifted to status stage after the data are transmitted on data stage Waiting for completion of status phase Completion of GET CONFIGURATION request
83. an interrupt assigned the highest priority watchdog timer interrupt etc are regulated by hardware Figure 2 15 4 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine Reset gt NMI gt DBC gt Watchdog timer gt Peripheral I O gt Single step gt Address match Figure 2 15 4 Hardware interrupts priorities Rev 2 00 Oct 16 2006 page 270 of 354 7RENESAS REJ09B0340 0200 M30245 Group 6 Interrupt resolution circuit 2 Multiple Interrupts When two or more interrupts are generated simultaneously this circuit selects the interrupt with the highest priority level Figure 2 15 5 shows the circuit that judges the interrupt priority level Priority level of each interrupt Level 0 initial value Vbus detection USB reset USB resume USB suspend USB EPO INT1 INTO USB function USB SOF Timer A4 Timer A3 Timer A2 Timer A1 Timer AO DMA3 DMA2 DMA1 DMAO UARTO reception ACK SSIO reception UART1 reception ACK SSI1 reception UART2 reception ACK UARTS reception ACK UARTO transmission NACK SSI0 transmission UART1 transmission NACK SSI1 transmission UART2 transmission NACK UARTS tra
84. b7 b8 b0 b7 W bo Address O3AF 16 O3AE16 036F 16 O36E16 033F 16 033E16 032F16 032E16 Function clock synchronous serial I O mode Symbol UORB U1RB U2RB U3RB Receive data When reset Indeterminate Indeterminate Indeterminate Indeterminate Function UART mode Riw I I l Receive data O X Receive data 9th bit Nothing is assigned Write 0 when writing to these bits The values are indeterminate when read Not detected Detected Arbitration lost detecting flag Note 1 Invalid Overrun error flag Note 2 No overrun error Overrun error 0 No overrun error Overrun error Framing error flag Note 2 Invalid 0 No framing error Framing error Parity error flag Note 2 Error sum flag Note 1 Always write 0 Invalid 0 No parity error Parity error 0 No error 1 Error Note 2 Bits 15 to 12 are set to 00002 when the serial I O mode select bit bits 0 to 2 at addresses 03A816 036816 033816 032816 are set to 0002 or the receive enable bit is set to 0 Bit 15 is set to 0 when all of bits 14 to 12 are set to 0 Bits 14 and 13 are also set to 0 when the lower byte of the UARTIi receive buffer register addresses 03AE16 036E16 033E16 032E16 is read Figure 2 4 3 UARTi related registers 1 Rev 2 00 Oct 16 2006 page 60 of 354 REJ09B0340 0200 7tENESAS M30245 G
85. b7 bo Serial Sound Interface 1 mode register 0 1 SSHMRO_ Address 037016 Serial Sound Interface enable bit 1 Enabled Enable DMAO or DMAO control register xx 1 0 DMOCON Address 002C16 DMA request bit 0 DMA not requested DMA enable bit 1 Enabled Continued to the next page Figure 3 7 3 Setting routine 2 of DMA transfer from USB OUT FIFO to serial sound interface Rev 2 00 Oct 16 2006 page 319 of 354 lt ENESAS REJ09B0340 0200 an M30245 Group 3 USB Applications Continued from the previous page The DMA request of the serial sound interface 1 transmit is occurred when DMA enable bit 1 and the OUT_BUF_STS1 flag of endpoint 1 1 DMAO transfer of the 1st word DMA request from the 2nd byte on is occurred when DMA enable bit 1 and the OUT_BUF_STS1 flag of endpoint 1 1 DMAO transfer from the 2nd word on MEP RE EEE RPE DMA enable bit is set to 0 by underflow of the DMAO transfer counter Completion of the DMAO transfer and occurrence of the DMAO interrupt request Setting CLR_OUT_BUF_RDY bit of endpoint 1 to 1 and completion of one receive packet data fetch after confirming of the DMAO interrupt request b8 b0 b7 7 20 USB Endpoint 1 OUT Control and Status register EP10CS Address 02B616 CLR_OUT_BUF_RDY bit 1 Data set
86. bit Two edges Nothing is assigned Write 0 when writing to this bit The value is indeterminate when read IFSR6 Bus collision interrupt 0 UARTO Bus collision request cause select bit 0 Start stop condition detection Trouble error detection UART2 Bus collision Start stop condition detection Trouble error detection Bus collision interrupt UART1 Bus collision request cause select bit 1 Start stop condition detection Trouble error detection UART3 Bus collision Start stop condition detection Trouble error detection Figure 2 4 6 UARTi related registers 4 Rev 2 00 Oct 16 2006 page 63 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 4 2 Operation of Serial I O transmission in UART mode 2 UART In transmitting data in UART mode choose functions from those listed in Table 2 4 4 Operations of the circled items are described below Figure 2 4 7 shows the operation timing and Figures 2 4 8 and 2 4 9 show the set up procedures Table 2 4 4 Choosed functions Transfer clock Internal clock f1 fs f32 source External clock CLKi pin Data logic select function No reverse Reverse CTS function CTS function enabled CTS function disabled TxD RxD I O polarity reverse bit No reverse Reverse Transmission Transmission buffer empty interrupt factor Transmission complete Bus collision detection function Not se
87. bit 0 0 CM16 and CM17 valid 1 Division by 8 mode System clock select bit Note 1 Note 2 0 XIN XOUT 1 XCIN XCOUT Note 1 When switching the system clock it is necessary to wait for the oscillation to stabilize Note 2 Set the WAIT peripheral function clock stop bit to 0 when the system clock select bit is 1 i a 4 WAIT instruction C Insert JMP B instruction before the WAIT instruction and at least four NOPs after the WAIT instruction Wait mode Figure 2 16 6 Example of wait mode set up Rev 2 00 Oct 16 2006 page 281 of 354 AS REJ09B0340 0200 RENES 2 Power Control M30245 Group 2 Power Control 2 16 4 Precautions in Power Control 1 The processor does not switch to stop mode when the NMI pin is at L level 2 When returning from stop mode by hardware reset RESET pin must be set to L level until main clock oscillation is stabilized 3 When entering wait mode insert a JMP B instruction before a WAIT instruction Do not ex ecute any instructions which can generate a write to RAM between the JMP B and WAIT instructions Disable the DMA transfers if a DMA transfer may occur between the JMP B and WAIT instructions After the WAIT instruction insert at least 4 NOP instructions When enter ing wait mode the instruction queue roadstead the instructions following WAIT and depend ing on timing some of these may execute before the microcomputer enters wait
88. buffer register 1 Data present in receive buffer register Checking error b15 b8 UARTO receive buffer register Address 03AF16 03AE16 UORB b7 b0 b7 bo UART1 receive buffer register Address 036F 16 036E16 U1RB UART2 receive buffer register Address 033F 16 033E16 U2RB UARTS receive buffer register Address 032F 16 032E16 U3RB Received data Invalid in UART mode Overrun error flag 0 No overrun error 1 Overrun error found Framing error flag 0 No framing error 1 Framing error found Parity error flag 0 No parity error 1 Parity error found Error sum flag 0 No error 1 Error found Processing after reading out received data Figure 2 4 18 Set up procedure of reception in UART mode used for SIM interface 2 Rev 2 00 Oct 16 2006 page 80 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 SIM interface 2 4 7 Clock Signals in used for the SIM Interface In conforming to the SIM interface the UART clock signal within the SIM card needs to conform to the UARTI i 0 to 3 clock signal within the microprocessor Two examples are given here as means of generating a UARTIi clock signal within the microprocessor In the case of setting a value equal to or less than 1 256 X 1 16 in the division rate of UARTi clock Choose f1 for the UART s source clock signal and set an optional value in the bit rate generator In the case of setting a value equal to or gre
89. cases given below and begins a down count a When the watchdog timer writes to the watchdog timer start register while a count is in progress b When the watchdog timer underflows 4 Runaway detection When the watchdog timer underflows either a watchdog timer interrupt occurs or reset is selected depending on the setting of the watchdog timer function select bit In writing a program write to the watchdog timer start register before the watchdog timer underflows The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag I flag In processing a watchdog timer interrupt set the software reset bit to 1 to reset software Rev 2 00 Oct 16 2006 page 253 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Watchdog Timer 5 Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected Table 2 12 1 shows the watchdog timer cycle Table 2 12 1 The watchdog timer cycle f XIN 16MHz Period Approx 32 8ms Note Approx 262 1ms Note Approx 65 5ms Note Approx 524 3ms Note Approx 131 1ms Note Approx 1 049s Note Approx 524 3ms Note 1 Approx 4 194s Note 0 Approx 262 1ms Note valid vane 1 Approx 2 097s Note Invalid Invalid Invalid Invalid Approx 2s Note Note An error due to the prescaler occurs Rev 2 00 Oct 16 2006 page 254 of 354 ENESAS
90. cause malfunction of the internal read pointer Table 2 8 3 Status on Endpoint 1 to 4 OUT FIFOs Single buffer Double buffer OUT FIFO size The number of bytes specified by the BUF_SIZ by the BUF_SIZ xX 2 No data No data Space equal to one buffer Space equal to two buffer Invalid Invalid Invalid One data set in the OUT FIFO Space equal to one buffer One data set in the OUT FIFO Two data set in the OUT FIFO No space in the OUT FIFO No space in the OUT FIFO 1 Bits 6 to 9 of EPXOFC PID Initialization When TOGGLE _INIT bit is set to 1 the read write counter inside the FIFO is initialized To initialize the PID set TOGGLE_INIT bit to 1 when the OUT FIFO is empty the OUT_BUF_STSO and OUT_BUF_STS1 flags are 002 Rev 2 00 Oct 16 2006 page 191 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function 6 USB Receive Endpoints 1 to 4 OUT Example The endpoints 1 to 4 OUT packet fetching routine in continuous transfer disable is shown in Figure 2 8 44 In addition to packet fetch process error flag OVER_RUN FORCE_STALL DATA_ERR process is required for every transfer type Process of USB endpoint x OUT packet fetch A rai Confirming of whether one packet is received in the OUT FIFO check the OUT_BUF_STS0 and the OUT_BUF_STS1 b15 b8 br bo b7 bo USB endpoint x OUT control and status register ojo EPxOCS x 1 4 Address 02B616 02BE16 02C616 02CE16 O
91. continues At this time the timer Ai interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the switch takes effect from the next effective edge of the count source 4 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer Ai interrupt request bit goes to 1 n reload register content 2 Undertlow 3 Switch count Counter content hex Set to 1 by software Count start flag J Set to 1 by software Up down flag Cleared to 0 when interrupt request is accepted or cleared by software Timer Ai interrupt 4 er A Ao request bit ni Note First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Figure 2 2 14 Operation timing of event counter mode free run type selected Rev 2 00 Oct 16 2006 page 20 of 354 7tENESAS REJ09B0340 0200 M30245 Group f Selecting event counter mode and functions b7 bo Timer Ai mode register i 0 to 4 Address 039616 to 039A16 OPPO of ol tai 0 to 4 Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAi OUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause sel
92. e One byte temporary RAM address 080016 Specifications 1 Transfer the content of memory extending over 128 bytes from address F600016 to a 128 byte area starting from address 0040016 Transfer the content every time a timer AO interrupt request occurs 2 Use DMAO for a transfer from the source to built in memory and DMA1 for a transfer from built in memory to the destination Operation 1 A timer A interrupt request occurs Though both a DMAO transfer request and a DMA1 trans fer request occur simultaneously the former is executed first 2 DMAO receives a transfer request and transfers data from the source to the built in memory At this time the source address is incremented 3 Next DMA1 receives a transfer request and transfers data involved from built in memory to the destination At this time the destination address is incremented 1 Transfer request generation 3 Start DMA1 transferring 2 Start DMAO transferring Timer AO a transfer request 0 Source address Source address Address bus F600016 080016 X 080016 0040016 Destination address Destination address RD signal WR signal Instruction cycle DMAO operation The DMAO operation and DMA1 operation are not necessarily executed in succession due to the a cycle steal operation The instruction cycle varies from instruction to instruction Since the parts of the RD and WR signals shown in short dash lines vary in step with writing
93. edge 1 i of start bit a gt e Becomes L by reading the receive buffer 0 aja A me Transmitter side IC 2 UART 4 Data is read 3 Receiving is completed D7 Stop bit cA Receive data taken in Transferred from UARTi receive register to UARTIi receive buffer register val Cleared to 0 when interrupt request is accepted or cleared by software Timing of transfer data 8 bits long applies to the following settings Transfer data length is 8 bits Parity is disabled One stop bit RTS function is selected Figure 2 4 10 Operation timing of reception in UART mode Rev 2 00 Oct 16 2006 page 69 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 UART Setting UARTIi transmit receive mode register i 0 to 3 b7 b0 UARTI transmit receive mode register o o Jofoj1jo 1 UiMR Address 03A816 36816 033816 32816 Serial I O mode select bit Note b2 b1 b0 1 0 1 Transfer data 8 bits long Internal external clock select bit 0 Internal clock Stop bit length select bit 0 One stop bit Valid when bit 6 1 Parity enable bit 0 Parity disabled TxD RxD I O polarity reverse bit Usually set to 0 Note Set the RxDi pin s port direction register to O when receiving Setting UARTi transmit receive control register 0 i 0 to 3 b b ofo 0 0 c UARTI transmit receive control register 0 UiCO Address 03A
94. full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products How to Use This Manual This user s manual is written for the M30245 group The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers This manual explains a function of the following kind e M30245M8 XXXGP e M30245MC XXXGP e M30245FCGP These products have similar features except for the memories which differ from one product to another Be careful when writing a program as the memories have different capacities RAM Size Byte 10K i Flash memory version M30245FCGP Ne da fy EEEn Taa sets aTe ohn cans Loh oh Mask ROM version M30245MC XXXGP PENTIRSI 5K Mask ROM version M30245M8 XXXGP i ROM Size i Byte The figure of each register configuration describes its functions and a
95. functions e Timer mode of timer A e Event counter mode of timer A Specifications 1 Set timer AO to timer mode and set timer A1 to event counter mode 2 Perform a count on count source f1 using timer AO to count for 1 ms and perform a count on timer AO using timer A1 to count for 1 second 3 Connect a 16 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter to begin counting The counter of timer AO performs a down count on count source f1 2 If the counter of timer AO underflows the counter reloads the content of the reload register and continues counting At this time the timer AO interrupt request bit goes to 1 The counter of timer A1 performs a down count on underflows in timer AO 3 If the counter of timer A1 underflows the counter reloads the content of the reload register and continues counting At this time the timer A1 interrupt request bit goes to 1 reload register content 1 Start count 2 Timer AO underflow 3 Timer A1 underflow e 3 Timer AO counter content hex n reload register content Start count ic oO E 3 Q 0 lt x a oO E H 000016 Set to 1 by software Cleard 0 by software i Time i i Timer AO count 1 start flag o Set to 1 by software Timer At count 1 a start flag o Timer AO interrupt 1
96. i eee aren Trigger select bit 0 Software trigger Vref connect bit A D conversion start flag Pe Wsheounested 0 A D conversion disabled Reserved bit Frequency select bit 0 Note 2 0 faD 3 or faD 4 is selected 1 faD or faD 2 is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 When f XIN is over 10 MHz the fap frequency must be under 10 MHz by dividing and set AD frequency to 10 MHz or lower Setting A D conversion start flag b0 AD control register 0 Address 03D616 E ADCONO A D conversion start flag 1 A D conversion started Start A D conversion Stop A D conversion Ponana O conenen Q suena Reading conversion result AD registerO Address 03C116 03C016 ADO bs AD register 1 Address 030316 03C216 AD1 bO b7 AD register2 Address 03C516 03C416 AD2 AD register 3 Address 030716 03C616 AD3 AD register 4 Address 030916 03C816 AD4 AD register5 Address 03CB16 0O3CA16 AD5 AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 O3CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 9 5 Set up procedure of one shot mode Rev 2 00 Oct 16 2006 page 219 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2
97. input at rising edge Transfer format select bit 0 LSB first Note UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output C It cannot be set to CMOS output J fe Setting UART transmit receive control register 1 i 0 to 3 ef b0 UARTI transmit receive control register 1 lojojo vici address 03AD16 36D16 033D16 32D16 Loo UARTi continuous receive mode enable bit 0 Continuous receive mode disabled Data logic select bit 0 No reverse Set to 0 in clock synchronous serial I O mode Continued to the next page Figure 2 3 9 Set up procedure of reception in clock synchronous serial I O mode 1 Rev 2 00 Oct 16 2006 page 51 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O Continued from the previous page i r Reception enabled b7 b0 UARTIi transmit receive control register 1 D 1 vict Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note Ss n e Writing dummy data b7 b0 b7 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB Note UARTO transmit buffer register Address 03AB16 03AA16 UOTB bO UARTS transmit buffer register Address 032B16 032A16 U3TB Setting dummy data Note Use MOV instruction to write to this re
98. internal read write pointer of IN FIFO is also initialized FLUSH bit This bit controls the IN FIFO packet Read the IN_BUF_STS1 and IN_BUF_STS0 flags and confirm that there are data in the IN FIFO and then set this bit to 1 When the IN FIFO is flushed the IN BUF_STS1 and IN_BUF_STS0 flags are updated as follows When there is one buffer data in IN FIFO the IN FIFO becomes empty At this time the IN BUF_STS1 and IN_BUF_STSO flags are updated to 002 When two buffer data exist in IN FIFO the older data is flushed At this time the IN BUF_STS1 and IN_BUF_STS0 flags are updated to 012 This indicates that one more buffer data is left inside the IN FIFO The transmit data may be destroyed if this bit is set to 1 during USB transfer On completing one buffer data flush this bit is automatically cleared to 0 eINTPT bit This bit controls transfer mode in interrupt transfer Only when using the IN endpoint for the rate feedback interrupt transfer set this bit to 1 With this bit being set to 1 when an IN token is received from the host CPU IN FIFO data are transmitted regardless of the IN_BUF_STS1 and IN_BUF_STS0 flag states or the data toggle Fix this bit at O for isochronous transfer bulk transfer and normal interrupt transfer ISO bit This bit controls isochronous transfer With this bit being set to 1 the IN endpoint is used for isoch ronous transfer Fix this bit at O
99. interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Figure 2 14 6 Set up procedure of key input interrupt Rev 2 00 Oct 16 2006 page 266 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 15 Multiple interrupts Usage 2 15 1 Overview of the Multiple interrupts usage The following is an overview of the multiple interrupts usage 1 Interrupt control 2 Multiple Interrupts Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted What is described here does not apply to non maskable interrupts Enable or disable a non maskable interrupt using the interrupt enable flag I flag interrupt priority level selection bit or processor interrupt priority level IPL Whether an interrupt request is present or absent is indicated by the interrupt request bit The interrupt request bit and the interrupt priority level select bit are located in the interrupt control register of each interrupt Also the interrupt enable flag flag and the IPL are located in the flag register FLG Figure 2 15 1 shows the memory map of the interrupt control registers and Figure 2 15 2 shows the interrupt control registers 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F 16 005016 0051 0052 0053 0054 0055 0
100. is completed 6 When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock 7 In using a key input interrupt none of the 8 pins ANo through AN7 can be used as an A D conversion port if the A D input voltage goes to L level a key input interrupt occurs 8 Use AD under 10 MHz When XIN is over 10 MHz divide it Rev 2 00 Oct 16 2006 page 230 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2 9 9 Method of A D Conversion 10 bit mode 1 The A D converter compares the reference voltage Vref generated internally based on the contents of the successive comparison register with the analog input voltage VIN input from the analog input pin The comparison result is stored in the successive comparison register and then VIN is converted to digital value successive comparison method If a trigger oc curs the A D converter carries out the following 1 Fixes bit 9 of the successive comparison register Compares Vref with VIN In this instance the contents of the successive comparison register are 10000000002 default Bit 9 of the successive comparison register varies depending on the comparison re sult as follows If Vref lt VIN then 1 is assigned to bit 9 If Vref gt VIN then 0 is assigned to bit 9 2 Fixes bit 8 of the successive comparison register Sets bit 8 of the successive comparison register to 1 then compare
101. is determined then the interrupt request being held is accepted Interrupt priority level of the interrupt request being held gt Returned the IPL Figure 2 15 6 shows the example of the multiple interrupts operation Rev 2 00 Oct 16 2006 page 272 of 354 7tENESAS REJ09B0340 0200 M30245 Group nterrupt request generated 2 Multiple Interrupts Nesting Rasa Wan out Interrupt 1 Interrupt priority level 3 Interrupt 2 Interrupt priority level 5 Interrupt 3 Interrupt priority level 2 Multiple interrupts 5 Interrupt 2 Not acknowledged because of low interrupt priority Main routine instructions are not executed Interrupt enable flag Processor interrupt priority level Automatically executed Be sure to set in software Figure 2 15 6 Example of the multiple interrupts operation Rev 2 00 Oct 16 2006 page 273 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Power Control 2 16 Power Control Usage 2 16 1 Overview of the power control usage Power Control refers to the reduction of CPU power consumption by stopping the CPU and oscillators or decreasing the operation clock The following is a description of the three available power control modes 1 Modes Power control is available in three modes a Normal operation mode e High speed mode Divide by 1 frequency of the main clock becomes the BCLK The CPU operates with the BC
102. is valid only in isochro nous transfer When OUT FIFO is not empty and disables receiving at start of the OUT token from the host CPU occurrence of an overrun is recognized setting this bit to 1 Clear this flag by writing 1 to CLR_OVER_RUN bit FORCE_STALL flag This flag indicates occurrence of a packet size error When the data packet which size exceeds USB endpoint x OUT MAXP register value is transmitted from the host CPU this flag becomes 1 While this bit is set to 1 the USB function control unit does not receive packet data If it is in bulk transfer also STALL handshake is transmitted to the host CPU Clear this flag by writing 1 to CLR_FORCE_STALL bit DATA_ERR flag This flag indicates occurrence of data error in isochronous transfer The bit is valid only in isochro nous transfer If any bit stuffing error or CRC error is detected in the received packet this flag be comes 1 Clear this flag by writing 1 to CLR_DATA_ERR bit CLR_OUT_BUF_RDY bit This bit controls OUT FIFO Set this bit to 1 after one receive buffer data is read from OUT FIFO Completion of one buffer data fetch is notified to the USB function control unit and simultaneously the OUT_BUF_STSO and OUT_BUF_STS1 flags are updated When the AUTO_CLR function is enabled this bit does not need to be set up CLR_OVER_RUN bit The OVER_RUN flag is cleared to 0 by setting 1 to this bit CLR_FORCE_STALL bit The
103. level O cannot be written for the fault error flag In the slave mode the 0 can be written for the fault error flag regardless of the input to the SSi input pins 5 Function selection For serial interface special function the following functions can be selected a Function for choosing CLK polarity This function switches the CLK polarity of the transfer clock The following operations are available e Data is input at the falling edge of the transfer clock and is output at the rising edge e Data is input at the rising edge of the transfer clock and is output at the falling edge b Function for setting clock phase This function switches the phase of the transfer clock Choose either of the following Without clock delay With clock delay c Function for setting serial input pin This function switches the serial bus control privilege between the master mode and slave mode Choose either of the following e Master mode e Slave mode Rev 2 00 Oct 16 2006 page 85 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Following are some examples in which various functions a through c are selected e Transmission Operation WITH outputting transmission data at falling edge of transfer clock no clock delay master mode e Reception Operation WITH inputting reception data at rising edge of transfer clock clock delay master mode e Transmission Operation WITH outputting transmission da
104. mode Program example when entering wait mode Program Example JMP B L1 Insert JMP B instruction before WAIT instruction L1 FSET WAIT Enter wait mode NOP More than 4 NOP instructions NOP NOP NOP 4 When entering stop mode insert a JMP B instruction immediately after executing an instruc Rev 2 00 Oct 16 2006 page 282 of 354 REJ09B0340 0200 tion which sets the CM10 bit in the CM1 register to 1 and then insert at least 4 NOP instruc tions When entering stop mode the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to 1 all clock stops and some of these may execute before the microcomputer enters stop mode or before the interrupt routine for return ing from stop mode Program example when entering stop mode Program Example FSET BSET CM10 Enter stop mode JMP B L2 Insert JMP B instruction L2 NOP More than 4 NOP instructions NOP NOP NOP 7tENESAS M30245 Group 2 Power Control 5 Before the count source for BCLK can be changed from XIN to XCIN or vice versa the clock to which the count source is going to be switched must be oscillating stably Allow a wait time in software for the oscilla tion to stabilize before switching over the clock 6 Suggestions to reduce power consumption a Ports The processor retains the state of each programmable I O port even when it goes to wait mode or to stop mode A current flows in active I O p
105. much as the set size is available for the IN FIFO The size and starting location of FIFO the double buffer mode enable can be set by USB endpoint x IN FIFO configuration register EPxIFC When packet data are transmitted to the host CPU the data are written to the endpoint x IN FIFO When a data transmit request from the host CPU occurs before the data are written to IN FIFO NAK is automati cally transmitted in bulk transfer and interrupt transfer or an empty packet with O data length is auto matically transmitted in isochronous transfer The data transmitted to the host CPU is controlled based on the communication status of endpoints 1 to 4 IN The default of endpoints 1 to 4 is bulk transfer Each endpoint should be initialized in order to use other transfer modes The transmit of endpoints 1 to 4 can select the following functions Continuous Transmit Mode This function is used for transmitting data at a higher speed This mode can be set only for endpoints 1 to 4 IN bulk transfer With continuous tranfer mode bit of the EPxIFC being set to 1 the continuous transmit mode is enabled In continuous transmit mode the USB function control unit by dividing the data in IN FIFO into one packet size the maximum packet size set in the EPxIMP units transmits them one by one to the host PC When the last one packet is smaller than the size set in the EPxIMP it is transmitted as a short packet When continuous transmit mode is enabled th
106. no function in A mode Set the specified value e Valid when bit A 0 When bit A is 1 the bit concerned has no function When bit A is 0 the bit concerned has function Table of Contents Chapter 1 Hardware ssisscccciiecre aie eineiiaie I Chapter 2 Peripheral Functions Usage ssccee 3 DV ed B oI OA risa Aechiscaetssteduasece Lauanabyanash A E domasuse E 4 PAPES E a a EE E E EE E AEE EE E E E E E AS 4 21 2 Protect Operati sac cresicececsceceds odsccecesticcrsdecutecdecedeascedeectendyeseeecuecedesates edatuessuedvesaccedhouseedssiedetuecessecteeatectes 5 2 2 Mer A soci oh rcsinastedeccen cote wecenubaanndaavsadtenscacawsasasundeeesnesous decedsihsvanssexvadynibacanoaebeuieusenaces meds 6 25221 OVCTVIOW E NE EEE ANE E E N E E A E E EEEE 6 2 2 2 Operation of Timer A timer MOE ccceeeeeeceeeeseeeeeeeeeeeeeeeensneeeseeeeseneseeenennaeseeeesnaaeseeeesaeseeeeeaees 12 2 2 3 Operation of Timer A timer mode gate function selected ecceeeceeeseeeeeeeeeeeseeeseseeeeeneeesesneeeeeeeees 14 2 2 4 Operation of Timer A timer mode pulse output function Selected ccsccceseeseeeeeseeeeeeeeeeees 16 2 2 5 Operation of Timer A event counter mode reload type selected cssecseseeeseeeeeeteeesseeeeesees 18 2 2 6 Operation of Timer A event counter mode free run type selected ccsecceseceseeeeeeseeeseeeneeesees 20 2 2 7 Operation of timer A two phase pulse signal proces
107. ns tact RD DB With the Wait option selected ta OE lt m 0 5 x 109 f BCLK 60 ns tac2 RD DB m 1 when 1 wait selected m 2 when 2 waits selected and m 3 when 3 waits selected 5 Data setup time tsu D Data setup time tsu D must satisfy the following conditional expressions a Vcc 3 0 to 3 6 V PM16 0 WR width normal tsu D lt n 0 5 x 109 f BCLK 40 ns td DB WR e PM16 1 WR width expanded tsu D lt n x 109 f BCLK 40 ns td DB WR 40 ns td BCLK DB th BCLK WR data output delay time WR signal output hold time n 1 no wait n 2 1 wait n 3 2 waits n 4 3 waits Access time Without wait E 1 wait Figure 4 4 1 Relation between the frequency of BCLK and memory 1 Rev 2 00 Oct 16 2006 page 341 of 354 AS REJ09B0340 0200 RENES M30245 Group 4 External Buses OE access time Without wait 1 wait amp 2 waits lt 3 waits Data set up time Without wait E 1 wait amp 2 waits gt lt 3 waits Figure 4 4 1 Relation between the frequency of BCLK and memory 2 Rev 2 00 Oct 16 2006 page 342 of 354 RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 4 2 Connecting Low Speed Memory To connect memory with long access time ta A either decrease the freque
108. order address is m PWM period and H width of PWM pulse are PWM period 28 1 X m 1 fi PWM pulse H width m 1 n fi When the Timer Ai register is set to 000016 the counter does not operate and the Timer Ai interrupt request is not generated When the pulse is se to output the pulse does not output from the TAIOUT pin When the Timer Ai register is set to 000016 the pulse width modulator does not operate and the output level of the TAiOUT pin remains L level therefore the Timer Ai interrupt request is not generated This also occurs in the 8 bit pulse width modulator mode when the significant 8 high order bits in the Timer Ai register are set to 0016 bo Address 038016 Symbol TABSR When reset XXX000002 Bit Symbol Bit Name Function TAOS Timer AO count start flag 0 Stops counting TA1S 1 Starts counting Timer A1 count start flag TA2S Timer A2 count start flag TA3S TA4S Timer A3 count start flag Timer A4 count start flag Nothing is assigned Write O when writing to these bits The contents are indeterminate if read Figure 2 2 3 Timer A related registers 2 Rev 2 00 Oct 16 2006 page 9 of 354 REJ09B0340 0200 7tENESAS M30245 Group Up down flag Note b7 b6 b5 b4 b3 b2 bi bo Trigger select register b7 b6 b5 b4 b3 b2 bi bo S
109. page 190 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function 4 Interrupt Transfer Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for interrupt transfer ISO bit of USB endpoint x x 1 to 4 OUT control and status register is set to O for interrupt transfer setting Also for initialization of toggle sequence bit in interrupt transfer set TOGGLE_INIT bit to 1 and initialize PID to DATAO Receive Operation The endpoint x OUT receive operation in the interrupt transfer is same as the bulk transfer Refer to Receive Operation of 2 Bulk Transfer Endpoints 1 to 4 Receive Fetch of Receive Data The fetch procedure of endpoint x OUT receive data in the interrupt transfer is same as the bulk transfer Refer to Fetch of Receive Data of 2 Bulk Transfer Endpoints 1 to 4 Receive Although continuous transfer is valid for the bulk transfer only 5 Precautions for Receive Read from OUT FIFO Be sure to confirm the OUT_BUF_STS1 and OUT_BUF_STS0 flags states when reading data from the OUT FIFO Based on these flags states judge whether there are receive data in the OUT FIFO Be sure to read the byte count of data specified by USB endpoint x OUT write count register value before setting CLR_OUT_BUF_RDYbitto 1 when reading data from the OUT FIFO If the CLR_OUT_BUF_RDY bit is set to 1 during fetching of data from the OUT FIFO the setting can
110. products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Tec
111. pulses becomes 216 1 fi and the H level pulse width becomes n fi If the timer Ai register is set to 000016 the pulse width modulator does not work and the the TAiOUT pin output level remains at L fi frequency of the count source f1 f8 32 f 32 n value of the timer e Set TAIIN pin s port direction register to 0 Conditions Reload register 000316 external trigger rising edge of TAiIN pin input signal is selected 1 8 X 2 1 Count source TAiIN pin ES i k input signal Trigger is not generated by this signal Set to 1 by software i i Cleared to 0 i by software Count start flag Start count 2 Output level H to L 3 One period is complete 1 fi Xn 4 Stop count PWM pulse output from TAiOUT pin Cleared to 0 when interrupt request is Timer Ai interrupt 1 accepted or cleared by software request bit 0 ee ee Note n 000016 to FFFE16 Figure 2 2 22 Operation timing of pulse width modulation mode 16 bit PWM mode selected Rev 2 00 Oct 16 2006 page 28 of 354 RENESAS REJ09B0340 0200 Rev 2 00 Oct 16 2006 page 29 of 354 REJ09B0340 0200 M30245 Group 2 TimerA la Selecting PWM mode and functions b7 TAIMR i 0 to 4 External trigger select bit Trigger select bit 16 8 bit PWM mode select bit Count source select bit b7 b6 00 f1 01 fs 10 f32 Selection of
112. register XXXL TTI Addresses 005416 004516 004716 005716 005916 TAIIC i 0 to 4 Interrupt request bit Va ting one shot timer s time Sel 9 08 Timer AO register Address 038716 038616 b7 b0 b7 b0 Timer A1 register Address 038916 038816 Timer A2 register Address 038B16 038A16 Timer A3 register Address 038D16 038C16 Timer A4 register Address 038F16 038E16 C Can be set to 000116 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 b0 Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 r Setting count start flag b7 b0 XXX Count start flag Address 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag C i Timer A4 count start flag Setting one shot start flag b7 0 One shot start flag Address 038216 ONSF Timer AO one shot start flag Timer A1 one shot start flag Timer A2 one shot start flag Timer A3 one shot start flag Timer A4 one shot start flag Start count Figure 2 2 21 Set up procedure of one shot mode Rev 2 00 Oct 16 2006 page 27 of 354 RENESAS
113. register3 Address 03C716 03C616 AD3 AD register 4 Address 03C916 03C816 AD4 AD register 5 Address 03CB16 03CA16 ADS AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 0O3CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Printer Setting A D conversion start flag bO 0 AD control register 0 Address 03D616 A D conversion start flag 0 A D conversion disabled Stop A D conversion Figure 2 9 9 Set up procedure of repeat mode Rev 2 00 Oct 16 2006 page 223 of 354 ENESAS REJ09B0340 0200 x M30245 Group 2 9 5 Operation of A D Converter in single sweep mode 2 A D Converter In single sweep mode choose functions from those listed in Table 2 9 5 Operations of the circled items are described below Figure 2 9 10 shows timing chart and Figure 2 9 11 shows the set up procedure Table 2 9 5 Choosed functions Operation clock AD Divided by 4 fap divided by 3 fap divided by 2 fap AD Trigger for starting A D conversion Software trigger Trigger by ADTRG Resolution 8 bit 10 bit Analog input pin ANo and AN1 2 pins ANo Sample amp Hold Not activated Activated to ANs 4 pins ANo to AN5 6 pins ANo to AN7 8 pins Operation 1 Setting the A D conversion star
114. request occurs the interrupt priority level is compared with the IPL The interrupt is enabled only when the priority level of the interrupt is higher than the IPL Therefore setting the interrupt priority level to 0 disables the interrupt Table 2 15 1 shows the settings of interrupt priority levels and Table 2 15 2 shows the interrupt levels enabled according to the contents of the IPL The following are conditions under which an interrupt is accepted interrupt enable flag I flag 1 interrupt request bit 1 interrupt priority level gt IPL Rev 2 00 Oct 16 2006 page 269 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Multiple Interrupts The interrupt enable flag I flag the interrupt request bit the interrupt priority select bit and the IPL are independent and they are not affected by one another Table 2 15 1 Settings of interrupt priority levels Table 2 15 2 Interrupt levels enabled according to the contents of the IPL pale rity Interrupt priority pee IPL Enabled interrupt priority levels b2 bi b0 IPL2 IPL1 IPLo 0 0 0 Level 0 interrupt disabled 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Level 1 Low 0 0 1 Interrupt levels 2 and above are enabled 0 1 0 Level 2 0 1 0 Interrupt levels 3 and above are enabled O 1 1 Level 3 0O 1 1 Interrupt levels 4 and above are enabled 1 0 0 Level 4 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Level 5 1 0 1 Interrupt levels 6 and
115. reset interrupt control register RSTIC USB SOF interrupt control register SOFIC USB Vbus detect interrupt control register VBDIC USB function interrupt control register USBFIC INT2 interrupt control register INT2IC INTO interrupt control register INTOIC Figure 2 15 1 Memory map of the interrupt control registers Rev 2 00 Oct 16 2006 page 267 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Multiple Interrupts Interrupt control register Note 1 Symbol Address When reset Address When reset KUPIC 004116 XXXXX0002 005116 XXXXX0002 S2RIC 004216 XXXXX0002 0052 XXXXxX0002 S13BCNIC 004316 XXXXX0002 0053 XXXXX0002 TA1IC 004516 XXXXX0002 0054 XXXXX0002 EPOIC 004616 XXXXX0002 0055 XXXXX0002 TA2IC 004716 XXXXX0002 0056 XXXXX0002 SORIC 004A16 XXXXX0002 0057 XXXXX0002 ADIC 004B16 XXXXX0002 0058 XXXXX0002 DMOIC 004Ci6 XXXXX0002 005916 XXXXX0002 S3TIC 004Di6 XXXXX0002 005A16 XXXXX0002 b7 b6 b5 b4 b3 b2 bi b0 DM1IC 004E16 XXXXxX0002 005B16 XXXXX0002 S2TIC 004F16 XXXXX0002 005C16 XXXXX0002 DM2IC 005016 XXXXX0002 005D16 XXXXxX0002 r ILVLO Interrupt priority level select bit Level 0 interrupt disabled Level 1 ILVL1 Level 2 Level 3 Level 4 Level 5 ILVL2 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested 1 Interrupt requested Nothing is assigned Write O when writing to these bits The contents are indeterminate if read Symbol Address When re
116. restored from stop mode with the main clock s divide ratio unchanged Figure 2 16 2 Sequence of returning from stop mode 6 Registers related to power control Figure 2 16 3 shows the memory map of power control related registers and Figure 2 16 4 shows power control related registers 000616 System clock control register 0 CMO 000716 System clock control register 1 CM1 Figure 2 16 3 Memory map of power control related registers Rev 2 00 Oct 16 2006 page 278 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Power Control System clock control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 olo Symbol Address When reset CMO 000616 4816 Bit Symbol Bit Name Function R Ww uai 0 0 Reserved bit Always set to 0 WAIT peripheral function CM02 clock stop bit Do not stop in wait mode ine Stop in wait mode Note 8 Xcin Xcout drive capacity LOW CM03 select bit Note 2 ane io HIGH i I O port CM04 Port Xc select bit Xcin Xcout generation iO Main clock Xin Xout CMO05 stop bit Note 3 4 5 on Off 9 Main clock division select CM16 and CM17 valid CM06 bit 0 Note 7 o Divide by 8 mode System clock select bit 0 Xin Xout i CM07 Note 6 4 Xcin Xcout 2 i i e 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register e 2 Changes to 1 when changing to stop mode and at a res
117. s pulse s H level width b8 Timer AO register Address 038716 038616 Timer A1 register Address 038916 038816 Timer A2 register Address 038B16 038A16 Timer A3 register Address 038D16 038C16 Timer A4 register Address 038F 16 038E16 b0 b7 bO Can be set to 000116 to FFFF16 Continued to the next page Figure 2 2 23 Set up procedure of pulse width modulation mode 16 bit PWM mode selected 1 7tENESAS M30245 Group 2 TimerA Continued from the previous page Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 oc Clock prescaler reset flag Address 038116 Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bO KYI Count start flag Address 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2 2 24 Set up procedure of pulse width modulation mode 16 bit PWM mode selected 2 Rev 2 00 Oct 16 2006 page 30 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 11 Operation of Timer A pulse width modulation mode 8 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 1
118. simultaneously Setting DMAi source pointer DMAO source pointer Address 002216 to 002016 SARO DMA1 source pointer Address 003216 to 003016 SAR1 DMA2 source pointer Address 018216 to 018016 SAR2 DMAS3 source pointer Address 019216 to 019016 SAR3 b23 b19 b16 b15 b8 b7 b3 b0 b7 b0 b7 b0 DDD o ef E Source pointer Stores the source address Setting DMAi destination pointer DMAO destination pointer Address 002616 to 002416 DARO DMA1 destination pointer Address 003616 to 003416 DAR1 DMA2 destination pointer Address 018616 to 018416 DAR2 DMA destination pointer Address 019616 to 019416 DAR3 b19 b16 b15 b8 b3 b0 b7 b0 b7 bo XXX Es Destination pointer Stores the destination address Setting DMAi transfer counter DMAO transfer counter Address 002916 002816 TCRO DMA1 transfer counter Address 003916 003816 TCR1 DMA2 transfer counter Address 018916 018816 TCR2 DMAS transfer counter Address 019916 019816 TCR3 b0 Transfer counter Set a value one less than the transfer count Setting DMAi control register b7 bO DMAi control register Address 002C16 003C16 018C16 019C16 DDI 1 I pmiconi oto 3 DMA enable bit Me 1 Enabled Note Clear DMA request bit simultaneously again When software DMA request bit 1 Start DMA transmission Figure 2 10 6 Set up procedure of one shot transfer mode Rev 2
119. source select bit CTS RTS function select bit Function During clock synchronous serial I O mode bi b0 b1 b0 00 f1is selected 00 0 1 f8is selected 01 10 f32is selected 10 1 1 Inhibited 11 Valid when bit 4 0 TS function is selected Note 4 Function During UART mode f1 is selected fais selected f32 is selected Inhibited Valid when bit 4 0 0 CTS function is selected Note 1 0 CTS function is selected Note 1 1 RTS function is selected Note 4 TXEPT Transmit register empty 0 Data present in transmit register during transmission No data present in transmit register transmission completed Data present in transmit register during transmission No data present in transmit register transmission completed CRD CTS RTS disable bit NCH Data output select bit Note 2 CTS RTS function enabled CTS RTS function disabled TxDi SDAi and SCLi pin is CMOS output TxDi SDAi and SCLi pin is CTS RTS function enabled CTS RTS function disabled TxDi SDAi and SCLi pin is CMOS output TxDi SDAi and SCLi pin is CKPOL CLK polarity select bit UFORM Transfer format select bit 0 LSB first N channel open drain output Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 1 M
120. space of one or more packets in the IN FIFO Any one of endpoint x x 1 to 4 IN FIFO write request select bit in USB DMAx x 0 to 3 request register is set to 1 The other bits are set to 0 valid setting Event 1 byte 1 word data is written in the endpoint x IN FIFO which is set in USB DMAx x 0 to 3 request register DMA Transfer to Endpoint x IN FIFO The DMA request factor of USBO USB1 USB2 USB3 corresponds to write in the endpoints 1 4 IN FIFO Factor 3 Therefore with endpoint x IN FIFO being specified to the DMA destination pointer and the transfer destination address direction being fixed when DMA transfer is executed by Factor 1 Factor 2 or Factor 3 Factor 3 occurs Therefore when one buffer data is written in IN FIFO by DMA transfer it is possible that the 1st byte 1st word data is DMA transferred by Factor 1 Factor 2 or Factor 3 and the other data starting from the 2nd byte 2nd word up to the last byte last word are DMA transferred by Factor 3 For details of DMA transfer refer to Chapter 2 10 DMAC Rev 2 00 Oct 16 2006 page 209 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 8 9 Precautions for USB 1 USB Communication In applications requiring high reliability we recommend providing the system with protective mea sures such as USB function initialization by software or USB reset by the host to prevent USB com munication from being terminated unexpectedly for examp
121. synthesizer enable bit of frequency synthesizer control register to 1 2 Wait for 3ms 3 Check that frequency synthesizer lock status bit of frequency synthesizer control register is set to 1 When this bit has been set to 0 wait for 0 1ms and then check again Repeat the re check until the bit becomes 1 4 Set USB clock enable bit of USB control register to 1 Do not write to USB related registers other than the USBC USBAD and frequency synthesizer re lated registers when the USB clock has been disabled in the suspend state Rev 2 00 Oct 16 2006 page 165 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 4 USB Suspend Interrupt Request Processing Routine When using the USB suspend interrupt set USB suspend interrupt control register address 005616 In the USB suspend interrupt when the USB suspend status flag SUSPEND of USB power manage ment register is set to 1 the interrupt request occurs The USB suspend interrupt request processing routine is shown in Figure 2 8 28 and Figure 2 8 29 Detection of USB suspend interrupt request Setting USB control register b7 bo 0 0 0 0 0 0 USB control register Address 000C16 USBC USB clock enable bit 0 Disable 48MHZ clock supply disabled Clearing the protect bo i Protect register Address 000A16 PRCR L Enable bit for writing to system clock control registers 0 a
122. the OUT_BUF_RDY flag is set to 1 by receiving the SETUP token the USB function control unit responds with NAK to the data request from the host CPU Until decoding of request data from the host CPU is completed do not set this bit to 1 nor the OUT_BUF_RDY flag is set to O e SET_IN_BUF_RDY bit This bit controls setting of the IN _BUF_RDY flag to 1 Completion of one buffer data write is notified to the USB function control unit Set this bit to 1 after writing the data packet to IN FIFO When this bit is written to 1 the IN_BUF_RDY flag is set to 1 e CLR_SETUP bit This bit controls clearing of the SETUP flag Set this bit to 1 after decoding the SETUP packet When this bit is written to 1 the SETUP flag is cleared to 0 Rev 2 00 Oct 16 2006 page 171 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function e SET_DATA_END bit This bit controls setting of the DATA_END flag to 1 When the last data has been written in IN FIFO in the IN data phase or when the last data has been read from OUT FIFO in the OUT data phase set this bit to 1 When this bit is set to 1 the DATA_END flag is set to 1 At this time simultaneously set the CLR_OUT_BUF_RDY bit or SET_IN_BUF_RDY bit to 1 Completion of processing of the data which had amount of data set by setup phase is notified to the USB function control unit and the process shifts into status phase processi
123. the TAiOUT pin output level remains at L fi frequency of the count source f1 f8 f32 fc32 n value of the timer e When a trigger is generated the TAiout pin outputs L level of same amplitude as H level of the set PWM pulse after which it starts PWM pulse output e Set TAIIN pin s port direction register to 0 Conditions Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 External trigger falling edge of TAIN pin input signal is selected 1 fi X m 1 X 28 1 e gt comaenees MANUTAN ANN 1 Start count 2 Output level H to L 3 One period is i l complete 4 Stop count a Count start flag i i TAIIN pin input p et 1 fiX m Underflow signal of 8 bit jf prescaler Note 2 1 Ti 1 gt e Pes Cleared to 0 when interrupt request 4 is accepted or cleared by software Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FE16 n 0016 to FE16 Figure 2 2 25 Operation timing of pulse width modulation mode with 8 bit PWM mode selected PWM pulse output from TAiOUT pin Timer Ai interrupt request bit o oe a gt ie sige ne a ie Rev 2 00 Oct 16 2006 page 31 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA Nc Selecting PWM mode and functions Timer Ai mode register i 0 to 4
124. the content of the reload register is reloaded and the count continues At this time the timer Ai interrupt request bit goes to 1 4 Setting the count start flag to O causes the counter to hold its value and to stop Note e Make the pulse width of the signal input to the TAIIN pin not less than two cycles of the count source n reload register content 1 Start count 3 Underflow gt 2 Stop count E 4 Stop count Start count again Counter content hex o 3S g D Time Set to 1 by software Set to 1 by software Cleared to 0 by software Count start flag TAIIN pin wi a S E input signal Cleared to 0 when interrupt request is accepted or cleared by software Timer Ai interrupt 1 request bit Q Figure 2 2 8 Operation timing of timer mode gate function selected Rev 2 00 Oct 16 2006 page 14 of 354 7tENESAS REJ09B0340 0200 Rev 2 00 Oct 16 2006 page 15 of 354 REJ09B0340 0200 M30245 Group 2 TimerA a Selecting timer mode and functions Timer Ai mode register i 0 to 4 Address 039616 to 039A16 TAiMR i 0 to 4 Selection of timer mode Pulse output function select bit 0 Pulse is not output TAi OUT pin is a normal port pin Gate function select bit b4 b3 1 1 Timer counts only when TAiIN pin is held H Note 0 Must always be 0 in timer mode Count source select bit H a a Count
125. the following the instant the transmission buffer is emptied or the instant the transmission register is emptied When transmis sion buffer empty timing is selected an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register Therefore data can be transmitted in succession When transmission register empty timing is selected an interrupt occurs when data transmission is complete g TxD RxD I O polarity reverse function This function is to reverse a polarity of TxD port output level and a polarity of RxD port input level Following are some examples in which various functions a through g are selected e Transmission Operation WITH CTS function transmission at falling edge of transfer clock LSB First interrupt at instant transmission buffer is emptied e Transmission Operation WITH CTS RTS function disabled transmission at falling edge of transfer clock LSB First interrupt at instant transmission is completed e Reception Operation WITH RTS function reception at falling edge of transfer clock LSB First suc Rev 2 00 Oct 16 2006 page 40 of 354 RENESAS REJ09B0340 0200 M30245 Group cessive reception mode disabled 6 Input to the serial I O and the direction register To input an external signal to the serial I O slect the function select register A to I O port and set the direction register to input 7 Pins related to the serial I O e CTSo CTS1 CTS2 CTS3 pins e RT
126. the instruction in the address indicated by the ad dress match interrupt register Set the first address of the instruction in the address match interrupt register Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt The first instruction of an interrupt routine does not generate an address match interrupt either 3 Returning from an address match interrupt The address put in the stack when an address match interrupt occurs depends on the instruction not yet executed the instruction the address match interrupt register indicates The return address is not put in the stack For this reason to return from an address match interrupt either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction lt Instructions whose address is added to by 2 when an address match interrupt occurs gt e 16 bit operation code instructions 8 bit operation code instructions given below ADD B S IMM8 dest SUB B S IMM8 dest AND B S IMM8 dest OR B S IMMB8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S_ IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMM8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S _ IMM dest However dest A0 A1 lt Instructions whose address is added to by 1 when an address match interrupt oc
127. the interrupt which is used interrupt which is used to cancel the wait mode is to cancel the wait mode is higher higher than the processor interrupt priority IPL of than the processor interrupt priority the routine where the WAIT instruction is executed IPL of the routine where the WAIT instruction is executed Reserved bit Must always be set to 0 C Disable the interrupt not to be used for cancelling wait mode 2 Interrupt enable flag I flag 1 13 Canceling protect b7 b0 0 7 Protect register Address 000A16 D D 4 PD pq PRCR L Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 and frequency synthesizer registers addresses 03DB16 to 0O3DF 16 1 Write enabled Reserved bit Must always be set to 0 7 3 Control of CPU clock System clock control register 1 b7 b0 System clock control register 0 Address 000716 CM1 070 Address 000616 CMO Reserved bit LL Reserved bit Must always be set to 0 Must always be set to 0 Main clock division select bit WAIT peripheral function clock stop bit Note 2 b7 b6 0 Do not stop f1 fs f32 in wait mode 0 0 No division mode 1 Stop f1 fs f32 in wait mode 0 1 Division by 2 mode Port Xc select bit 1 0 Division by 4 mode 0 I O port 1 1 Division by 16 mode 1 XCIN XCOUT generation Main clock X n XourT stop bit 0 On 1 Off Main clock division select
128. the suspend signal from the host CPU following the power input state and then controls power supply and shifts the state into the suspend state And by receiving the resume signal from the host CPU or transmitting the resume signal to the host CPU in the case of remote wakeup it returns to the state before shifting into the suspend state and resumes the USB communication This section explains how the M30245 group controls a shift into suspend state recovery at the time of resume in the state which the USB function control unit is enabled 1 Related Registers USB power management register This register is used to control the suspend resume by the USB function control unit e USB Suspend Status Flag When the USB function control unit does not detected any bus activity on D D line for at least 3ms the USB suspend status flag is set Simultaneously the USB suspend interrupt request occurs This flag is automatically cleared in the following cases The active signal from the host CPU has been detected on the USB s D D line When the resume signal has been received and simultaneously the USB resume interrupt request has oc curred Transmission of the resume signal to the host CPU has been completed After USB remote wakeup bit being set to 1 when clearing it to O to stop resume signal transmission If the USB clock has been disabled during the suspend mode this flag is not cleared until after the USB clock is
129. the temporary register Note within the CPU c Sets the interrupt enable flag I flag the debug flag D flag and the stack pointer assignment flag U flag to O the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed d Saves the content of the temporary register Note within the CPU in the stack area e Saves the content of the program counter PC in the stack area f Sets the interrupt priority level of the accepted instruction in the IPL Note This register cannot be utilized by the user After the interrupt sequence is completed the processor resumes executing instruc tions from the first address of the interrupt routine Figure 2 16 2 shows the sequence of returning from stop mode Writing 1 to CM10 ash all clock stop control bit Operated by divided by 8 mode BCLK T neterminate sP 2 J SP4 vec Yvese Address bus l 00000 Indeterminate SP 2 SP 4 vec vec 2 Data bus h naaien Indeterminate contents contents contents contents RD a i Y_ indeterminate Indeterminate J WR i S a cqx75rt__ _ Stop mode Oscillation start up Interrupt sequence approximately 20 cycle 13u sec Single chip mode f Xin 16MHz Note Shown above is the case where the main clock is selected for BCLK If the sub clock is selected for BCLK the sub clock functions as BCLK when
130. transmit data again due to an error such as staggered serial clock caused by noise set the UARTi transmit buffer register again then transmit the data again To set the UARTIi transmit buffer register again 1 Set the serial I O mode select bits to 0002 invalidate serial I O 2 Set the serial I O mode select bits again 3 Set the transmit enable bit to 1 enable transmission then set transmission data in the UARTi transmit buffer register 5 Function selection For clock synchronous serial I O the following functions can be selected a CTS RTS function In the CTS function an external IC can start transmission reception by inputting an L level to the CTS pin The CTS pin input level is detected when transmission reception starts Therefore if the level is set to H during transmission reception it will stop from the next data The RTS function informs an external IC that RTS is reception ready and has changed to L RTS goes back to H at the first falling edge of the transfer clock Rev 2 00 Oct 16 2006 page 39 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O The clock synchronous serial I O has three types of CTS RTS functions to choose from e CTS RTS functions disabled CTS RTS pin is a programmable I O port e CTS function only enabled CTS RTS pin performs the CTS function e RTS function only enabled CTS RTS pin performs the RTS function b Function for choosing
131. transmit request state Figure 3 9 3 revised Chapter 4 added Chapter 5 added C 2 RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER USER S MANUAL M30245 Group Publication Data Rev A Jan 24 2003 Rev 2 00 Oct 16 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan M30245 Group User s Manual rCENESAS Renesas Technology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
132. types an overflow of the timer or a software trigger The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical d Pulse width modulation PWM mode In this mode the arbitrary pulses are successively output Either a 16 bit fixed period PWM mode or 8 bit variable period mode can be selected The trigger for initiating output can also be selected Please refer to the one shot timer mode explanation for details as the operation is identical 2 Count source The internal count source can be selected from f1 f8 32 and fc32 Clocks f1 f8 and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc32 is derived by dividing the CPU s secondary clock by 32 Rev 2 00 Oct 16 2006 page 6 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 3 Frequency division ratio In timer mode or pulse width modulation mode the value set in the timer register 1 becomes the frequency division ratio In event counter mode the set value 1 becomes the frequency division ratio when a down count is performed or FFFF16 the set value 1 becomes the frequency division ratio when an up count is performed In one shot timer mode the value set in the timer register be comes the frequency division ratio The counter overflows or underflows when a count source equal to a frequency division ratio is input and an interrupt occurs For the pu
133. unloaded from the OUT FIFO updates OUT_BUF_STS1 and OUT_BUF_STSO To subsequently start DMAO transfer Disable DMAO once and set the DMAO related registers again Figure 3 7 4 Setting routine 3 of DMA transfer from USB OUT FIFO to serial sound interface Rev 2 00 Oct 16 2006 page 320 of 354 7RENESAS REJ09B0340 0200 M30245 Group 3 Controlling Power Applications 3 8 Controlling Power Using Stop Mode Overview The following are steps for controlling power using stop mode Figure 3 8 1 shows the operation timing Figure 3 8 2 shows an example of circuit and Figures 3 8 3 and 3 8 4 show the set up procedure Use the following peripheral functions e Key input interrupts Stop mode e Pull up function This example is not performed USB power control Please refer section 2 8 4 for the power control of USB related Specifications 1 Use POo through P03 for the scan output pins of a key matrix Use the input pins Klo through KI3 of the key input interrupt function for the key input reading pins The pull up function is also used 2 If a key input interrupt request occurs clear the stop mode and read a key Operation 1 Enable a key input interrupt and set the pull up function to pins Klo through KI3 Change the output of POo through POs to L and enter stop mode 2 If a key is pressed L is input to one of pins Klo through KI3 to clear
134. updated enabling a receive of the next one packet data Note 2 eIn Single Buffer Mode The OUT_BUF_STS1 and OUT_BUT_STS0 flags are updated from 112 the OUT FIFO full to 002 the OUT FIFO empty eIn Double Buffer Mode When there are one more packet data Note 2 in the OUT FIFO the OUT_BUF_STS1 and OUT_BUF_STS1 flags are updated from 112 the OUT FIFO full to 102 one data set in the OUT FIFO In this case the second packet data Note 2 can be continuously fetched When there are no data packet does in the OUT FIFO the OUT_BUF_STS1 and OUT_BUF_STS1 flags are updated from 102 one data set in the OUT FIFO to 002 the OUT FIFO empty When one packet data Note 2 is read from the OUT FIFO while the AUTO_CLR function is en abled AUTO_CLR bit is 1 the OUT_BUF_STS1 and OUT_BUF_STS0 flags are automatically updated without CLR_OUT_BUF_RDY bit being set to 1 Note 2 In continuous transfer enable read the description by substituting the underlined part with buffer data On receiving one buffer full data equal to byte count set in the BUF_SIZ ora short packet one buffer data receive is completed Also the BUF_SIZ has to be equal to an integral multiple of the EPxOMP Rev 2 00 Oct 16 2006 page 189 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 lsochronous Transfer Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for isoch
135. x X X Timer Ak counter 1 2 0 1 16 341 2 1860 1 Timer Ak counter 464 Table 2 4 9 shows an example of setting in the timer Ak counter Rev 2 00 Oct 16 2006 page 81 of 354 7tENESAS REJ09B0340 0200 M30245 Group Clock generator Figure 2 4 19 XIN M30245 Timer Aj counter flip flop Timer Ak counter flip flop f1 No External clock Bit rate generator 1 16 y UARTi clock T SIM CARD 2 SIM interface CLK L SIM card internal clock frequency division ratio UART clock L UART UART Example of connection Rev 2 00 Oct16 2006 page 82 of 354 7tENESAS REJ09B0340 0200 Note i 0 to 3 M30245 Group Table 2 4 8 UARTi bit rate adjustment factor i 0 to 3 SIM card internal clock F Hz Bit a 1 2 1 4 1 8 1 16 1 32 1 64 1 2 1 4 1 8 1 16 1 32 1 64 1 2 1 4 1 8 1 16 1 32 1 64 UARTI bit rate generator value internal 186 1488 1116 72 92l 93 sa 185 Oo Ld LE a zo Ld 223 sea eves i7ese 35712 1 zaa t85 2 __a72 _a2 es _ oo M rE 2076 sos2 sig04 Le 185 Combination impossible to deal with due to the current specifications of M30245 Setting example under the following conditions f XIN 16 MHz
136. z bo UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Start transmission Checking the status of UARTi transmit buffer register i 0 to 3 b7 b0 7 l l UARTi transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled wT When transmitting continuously Writing next transmit data Note b15 b8 UARTO transmit buffer register Address 03AB16 03AA16 UOTB b7 b0 b7 b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Setting transmission data Note Use MOV instruction to write to this register m Se ep Transmission is complete Figure 2 5 16 Set up procedure of transmission in serial interface special function slave mode without clock delay 2 Rev 2 00 Oct 16 2006 page 105 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 Serial Interface Special Function 2 5 5 Operation of Serial Interface Special Function reception in slave mode with clock delay In receiving data in serial interface special function slave mode
137. 00 Oct 16 2006 page 246 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 DMAC 2 10 3 Operation of DMAC repeated transfer mode In repeat transfer mode choose functions from the items shown in Table 2 10 2 Operations of the circled items are described below Figure 2 10 7 shows an example of operation and Figure 2 10 8 shows the set up procedure Table 2 10 2 Choosed functions Transfer space Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address Unit of transfer 8 bits 16 bits Operation 1 When software trigger is selected setting software DMA request bit to 1 generates a DMA transfer request signal 2 If DMAC is active data transfer starts and the contents of the address indicated by the DMAi forward direction address pointer are transferred to the address indicated by the DMAi desti nation pointer When data transfer starts directly after DMAC becomes active the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter and the value of the DMAi source pointer is reloaded by the DMAi forward direction address pointer Each time a DMA transfer request signal is generated 2 byte of data is transferred The DMAi transfer counter is down counted and the DMAi forward direction address pointer is up counted 3 Though DMAi transfer counter is underflowed DMA enable bit is still 1 The
138. 0002 or the receive enable bit is set to 0 Bit 15 is set to 0 when all of bits 14 to 12 are set to 0 Bits 14 and 13 are also set to 0 when the lower byte of the UARTIi receive buffer register addresses 03AE16 036E16 033E16 032E16 is read Figure 2 3 2 Serial l O related registers 1 Rev 2 00 Oct 16 2006 page 42 of 354 REJ09B0340 0200 Invalid RENESAS No error Error M30245 Group 2 Clock Synchronous Serial I O UARTI bit rate generator o 0 to 3 Note 1 2 b7 Address When reset 03A916 Indeterminate 036916 Indeterminate 033916 Indeterminate 032916 Indeterminate Function Values that can be set Assuming that set value n BRGi divides the count source by 0016 to FFis o n 1 Note 1 Use MOV instruction to write to this register Note 2 Write a value to this register while transmit receive halts UARTIi transmit receive mode register i 0 to 3 b7 b6 b5 b4 b3 b2 bi Symbol Address When reset UOMR 03A816 0016 U1MR 036816 0016 U2MR 033816 0016 U3MR 032816 0016 Function Bit name During clock synchronous serial I O mode Function During UART mode SMDO lt erial I O mode select bit Must be fixed to 001 oan b2 b1 bo 100 Transfer data 7 bits long Note 3 9 99 Serial I O invalid 101 Transfer data 8 bits long SMD1 0 1 0 Serial 1 O mode 110 Transfer data 9 bits long 0 11 12C mode Inhibited except in cases Inhibited except in cases SNA
139. 008B s to a 16 bit data bus Rev 2 00 Oct 16 2006 page 336 of 354 7RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 3 3 8 bit Memory to 8 bit Width Data Bus Connection Example Figure 4 3 4 shows an example of connecting two M5M5278 s SRAM to an 8 bit data bus In this dia gram when reset the microcomputer starts operating in single chip mode Change this mode to memory expansion mode in a program Microcomputer M5M5278D M5M5278D Ao to A14 Figure 4 3 4 Example of connecting two M5M5278 s to an 8 bit data bus Rev 2 00 Oct 16 2006 page 337 of 354 RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 3 4 Two 8 bit and 16 Bit Memory to 16 Bit Width Data Bus Connection Example Figure 4 3 5 shows an example of connecting M5M28F 102 16 bit flash memory and two M5M5278 s 8 bit SRAM to a 16 bit data bus ee Microcomputer CNVss WRH BYTE WRL A1 to A16 M5M5278D M5M28F102 Figure 4 3 5 Example of connection of two 8 bit memories and one 16 bit memory to 16 bit width data bus Rev 2 00 Oct 16 2006 page 338 of 354 7RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 3 5 Chip Selects and Address Bus When there are insufficient chip select signals it is necessary to generate chip selects externally Figure 4 3 6 shows an example of a connection in which the CS2 128K bytes area is divided into four 32K byte areas M
140. 0200 M30245 Group 2 USB function 2 Bulk Transfer Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for bulk transfer ISO bit of USB endpoint x x 1 to 4 OUT control and status register is set to O for bulk transfer setting Also for initialization of toggle sequence bit in bulk transfer set TOGGLE_INIT bit to 1 and initialize PID to DATAO Set by using USB endpoint x OUT FIFO configuration register in order to enable double buffer mode and continuous receive mode Set AUTO_CLR bit of USB endpoint x OUT control and status register to 1 in order to use the AUTO_CLR function Receive Operation When one packet data Note 1 is received in OUT FIFO the OUT_BUF_STS1 and the OUT_BUF_STSO flags of the corresponding EPxOCS are automatically updated In single buffer mode when double buffer mode bit is O these flags are updated from 002 to 112 In double buffer mode they are updated as follows When the first one packet data Note 1 of the double buffer has been written to the OUT FIFO and the second packet data Note 1 is ready to be written the OUT_BUF_STS1 and OUT_BUF_STSO flags are updated from 002 to 102 When two packet data Note 1 have been written in OUT FIFO the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from 102 to 112 Note 1 In continuous transfer enable read the description by substituting the underlined
141. 0200 RENES M30245 Group Selecting timer mode and functions Timer Ai mode register i 0 to 4 Address 039616 to 039A16 TAiMR i 0 to 4 Selection of timer mode Pulse output function select bit 1 Pulse is output TAi OUT pin is a pulse output pin Note Gate function select bit b4 b3 3 i Gate function not available TAiIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 source f XIN 16MHz f XciN 32 768kKHz 00 f1 01 f8 62 5ns 500ns 10 f32 1 1 fc32 2us Note The setting of the corresponding port register and 976 56us C the direction register are invalid Setting divide ratio Timer AO register Address 038716 038616 TAO b8 Timer A1 register Address 038916 038816 TA1 Timer A2 register Address 038B16 038A16 TA2 Timer A3 register Address 038D16 038C16 TA3 Timer A4 register Address 038F 16 038E16 TA4 Can be set to 000016 to FFFF16 T Setting clock prescaler reset flag D This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 LPL CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O a Setting count start flag x o Count start flag Addres
142. 03CF16 Axs 03D416 AD control register 2 ADCON2 03D516 03D616 AD control register 0 ADCONO 03D716 AD control register 1 ADCON1 03D816 AD register 0 ADO AD register 1 AD1 AD register 2 AD2 AD register 3 AD3 AD register 4 AD4 AD register 5 AD5 AD register 6 AD6 AD register 7 AD7 Figure 2 9 1 Memory map of A D converter related registers Rev 2 00 Oct 16 2006 page 215 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter AD control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi bo AD control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi bo Symbol ADCONO Address 03D616 0016 When reset Bit Symbol Bit Name Function R CHO H1 2 Analog input pin select bit CH2 6 O S10 Org ANO AN1 AN2 AN3 AN4 AN5 AN6 AN7 Note 2 3 0 Oo 0 MDO A D operation mode select bit 0 MD1 sl 2A OCOO 40 Oc zo One shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 200gZ 200008 Oo 0 0 TRG Trigger select bit Software trigger ADTRG trigger O ADST A D conversion start flag A D conversion disabled A D conversion enabled CKSO Frequency select bit 0 Note 5 0 fAD 3 or fAD 4 is selected AD or fAD 2 is selected 0 0
143. 03EE16 03EF16 03F616 Bit symbol ____Bitname Function RW PDi_O_ Port Pio direction register _ 0 0 Por H direction register 1 Ea as an input port ee 1 Output mode oo Functions as an output port 10 0 eae ay o o o o Pbi 6 Por Pie direction register ool oo Note 1 In memory expansion and microprocessor mode the contents of corresponding port Pi direction register of pins Ao to A19 Do to D15 CSo to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified Port P8 direction register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PD8 03F216 00X000002 Bit symbol PD8_0 Port P80 direction register 10 0 PD8_1 Port P81 direction register 0 Input mode 10 0 Functions as an input port PD8_2 Port P82 direction register 4 Output mode 10 0 PD8 3 Port P83 direction register Functions as an output port O O PD8_4 Port P84 direction register o o Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate PD8 6 Port P86 direction register 9 Input mode Functions as an input port eo i 1 Output mode PD8_7 Port P87 direction register Functions as an output port Port P9 direction register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PD9 03F316 XXXX00X02 Ee 0 Input mode Port P90 direction register Functions as an input port 1 Output mode Functions as an outpu
144. 056 0057 0058 0059 005A 005B 005C 005D 005E 005F 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Key input interrupt control register KUPIC UART2 receive ACK interrupt control register S2RIC UART1 3 Bus collision interrupt control register S13BCNIC INT1 interrupt control register INT1IC Timer A1 interrupt control register TA1IC USB Endpoint 0 interrupt control register EPOIC Timer A2 interrupt control register TA2IC UART1 receive ACK SSI1 interrupt control register S1 RIC UARTO 2 Bus collision interrupt control register SO2BCNIC UARTO receive ACK SSIO interrupt control register SORIC AD conversion interrupt control register ADIC DMAO interrupt conrol register DMOIC UARTS transmit NACK interrupt control register S3TIC DMA interrupt control register DM1IC UART2 transmit NACK interrupt control register S2TIC DMA2 interrupt control register DM2IC UART1 transmit NACK SSI1 interrupt control register S1TIC DMAS3 interrupt control register DM3IC UARTO transmit NACK SSIO interrupt control register SOTIC Timer AO interrupt control register TAOIC UARTS receive ACK interrupt control register S3RIC USB suspend interrupt control register SUSPIC Timer A3 interrupt control register TA3IC USB resume interrupt control register RSMIC Timer A4 interrupt control register TA4IC USB
145. 1 by software A D conversion 1 a start flag g AD register i y Result A D conversion i interrupt request g Cleared to 0 when interrupt request is accepted or cleared by software Note When oabD frequency is less than 1MHZ sample and hold function cannot be selected Conversion rate per analog input pin is 49 oAD cycles for 8 bit resolution and 59 oAD cycles for 10 bit resolution Figure 2 9 4 Operation timing of one shot mode Rev 2 00 Oct 16 2006 page 218 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 A D Converter Selecting Sample and hold b7 b0 AD control register 2 Address 03D416 1 e XXe A lt ancon L A D conversion method select bit 1 With sample and hold Must always be set to 0 Setting AD control register 0 and AD control register 1 b7 bo i AD control register 1 Address 03D716 Jofofojo y Re cau register 0 Address 03D616 yoy fel Lid eee regis Analog input pin select bit Note 1 Invalid in one shot mode b2 b1 b0 0 0 0 ANd is selected AN1 is selected AN2 is selected ANs is selected A D operation mode select bit 1 Note 1 01 10 ag 00 AN4 is selected 01 10 tii 0 Must always be 0 in one shot mode 8 10 bit mode select bit 0 8 bit mode AN5 is selected 1 10 bit mode AN6 is selected AN7 is selected L Frequency select bit 1 Note 2 One shot mode is selected Note 1
146. 1 Operations of the circled items are described below Figure 2 2 25 shows the operation timing and Figures 2 2 26 and 2 2 27 show the set up procedure Table 2 2 11 Choosed functions Count source Internal count source f1 fs fs2 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition External trigger input falling edge of input signal to the TAIN pin External trigger input rising edge of input signal to the TAIN pin Timer overflow TAj TAk overflow Note j i 1 butj 4 wheni 0 k i 1 but k 0 wheni 4 Operation 1 If the TAiIN pin input level changes from H to L with the count start flag set to 1 the counter performs a down count on the count source Also the TAiOUT pin outputs an H level 2 The TAiOUT pin output level changes from H to L when a set time period elapses At this time the timer Ai interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAiOUT pin outputs an L level Note e The period of PWM pulses becomes m 1 X 28 1 fi and the H level pulse width becomes n X m 1 fi If 0016 is set in the eight higher order bits of the timer Ai register the pulse width modulator does not work and the
147. 1 to 4 OUT write count register Rev 2 00 Oct 16 2006 page 186 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB endpoint x x 1 to 4 OUT FIFO configuration register This register sets endpoint x x 1 4 OUT FIFO BUF_NUM This bit sets the starting location of the endpoint x x 1 4 OUT FIFO per 64 bytes For example when OUT FIFO is allocated starting at the 320th byte the set value is 0001012 BUF_SIZ This bit sets one buffer size of the endpoint x x 1 4 OUT FIFO per 64 bytes For example when 256 bytes is set the set value is 01002 DBL_BUF With this bit being set to 1 OUT FIFO of the corresponding endpoint is changed into double buffer mode The byte count for a valid OUT FIFO becomes twice as much as the value specified by the BUF_SIZ at the time of double buffer Set carefully not to overlap with the FIFO start position of other endpoints CONTINUE This bit enables continuous transfer mode Set this bit to 1 when continuous transfer is enabled The bit is valid only in bulk transfer The USB function control unit writes the receive data from the host PC in OUT FIFO sequentially by one packet size the maximum packet size set in the EPxOMP and receives continuously until one buffer full or a short packet is received When continuous receive mode is enabled the BUF_SIZ has to be equal to an integral multiple of the EPxOMP Further the user s system has to be comprehended beforehand th
148. 10 1 iy Interrupt Stop mode p Stop mode H Interrupt Transition of normal mode Main clock is oscillating a Lat Inorg CM10 1 CM10 1 fe Reset Ng J WAIT CPU operation stopped Medium speed mode Hinstruction_ __ divided by 8 mode _ C Wait mode 4 t Y Interrupt WAIT C i d High speed medium N speed mode Bx instruction gt Wait d P alt moqe A Interrupt N i Y WAIT CP ration Low speed low power dissipation mode _ instruction gt Interrupt Wait mode Normal mode 7 Refer to the following for the transition of normal mode Main clock is oscillating Sub clock is oscillating CM04 of Sub clock is stopped Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 CMO6 1 CM04 1 Notes 1 3 fe High speed mode Medium speed mode divided by 2 mode BCLK f Xin CM07 0 CMO6 0 CM17 0 CM16 0 BCLK f Xin 2 CMO7 0 CMO06 0 CM17 0 CM16 1 Medium speed mode divided by 4 mode Medium speed mode divided by 16 mode BCLK f Xin 4 CM07 0 CMO6 O CM17 1 CM16 0 BCLK f Xin 16 CM07 0 CMO6 0 CM17 1 CM16 1 Medium speed mode divided by 8 mode
149. 28 AD cycles 1 10 bit resolution 33 AD cycles ae p fat EEUU LJ L L LJ Lu l i Set to 1 by software A D aq a conversion start flag ADTRG A D conversion 1 OP o interrupt request o Cleared to 0 when interrupt request is accepted or cleared by software Note When oaD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 oAD cycles for 8 bit resolution and 59 aD cycles for 10 bit resolution Figure 2 9 6 Operation timing of one shot mode with an external trigger selected Rev 2 00 Oct 16 2006 page 220 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter Selecting Sample and hold b0 AD control register 2 Address 03D416 ADCON2 L A D conversion method select bit 1 With sample and hold a Must always be set to 0 N Setting AD control register 0 and AD control register 1 b7 bo b7 b0 F 0111010 AD control register 0 Address 03D616 QO OT 1 AD control register 1 Address 03D716 ADCONO ADCON1 Analog input pin select bit Note 1 Invalid in one shot mode b2 b1 b0 0 0 ANo is selected L A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in one shot mode AN2 is selected AN8 is selected __ 8 10 bit mode select bit AN4 is selected 0 8 bit mode AN5 is selected 1 10 bit mode AN6 is selected AN7 is selec
150. 3FF 16 Output code result of A D conversion Theoretical A D conversion characteristic 10 15 20 25 30 35 40 45 50 55 Analog input voltage mV Figure 2 9 21 Absolute accuracy 10 bit resolution Rev 2 00 Oct 16 2006 page 235 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 A D Converter Differential non linearity error Differential non linearity error refers to the difference between 1 LSB width based on the theoretical A D conversion characteristics an analog input width that can meet the expectation of outputting an equal code and an actually measured 1 LSB width analog input voltage width that outputs an equal code If 10 bit resolution is used and if VREF reference voltage 5 12 V differential non linearity error 1LSB refers to the fact that 1 LSB width actually measured falls on a range from 0 mV to 10 mV though 1 LSB width based on the theoretical A D conversion characteristics is 5 mV Output code result of A D conversion 1 LSB width for theoretical A D conversion characteristic Differential non linear error 15 20 25 30 35 40 45 Analog input voltage mV Figure 2 9 22 Differential non linearity error 10 bit resolution Rev 2 00 Oct 16 2006 page 236 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2 9 12 Internal Equivalent Circuit of Analog Input Figure 2 9 23 shows the internal equivalent circuit of analog input Vcc O Vcc Vs Z J AVcc Par
151. 4 REJ09B0340 0200 RENESAS M30245 Group UARTI special mode register 4 i 0 to 3 b7 b6 b5 b4 b3 b2 bi bo Symbol Address UiSMR4 i 0 to 3 03A416 036416 033416 032416 2 Serial Interface Special Function When reset 0016 Start condition 0 generate bit Note 1 Clear Start Function 1 Restart condition generate bit Note 1 Clear Start Stop condition generate bit Note 1 Clear Start SCL SDA output select bit Ordinal block Start stop condition generate block ACK data bit ACK NACK ACK data output enable bit SI O data output ACKD output SCL output stop enable bit Disabled Enabled SCL wait output bit 3 SCL L hold disabled SCL L hold enabled Note 2 Note 1 These bits automatically become 0 when a start condition is generated Note 2 This bit is unavailable when SCLi is external clock Interrupt request cause select register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address 035F16 INTO interrupt polarity swiching bit 0 1 When reset 0016 One edge Two edges INT1 interrupt polarity swiching bit 0 1 One edge Two edges INT2 interrupt polarity swiching bit 0 1 One edge Two edges Nothing is assigned Write 0 when writing to this bit The val ue is indeterminate when read Bus collision interrupt IFSR6 request cause select bit 0
152. 45 Group 2 Protect 2 1 2 Protect Operation The following explains the protect operation Figure 2 1 2 shows the set up procedure Operation 1 Setting 1 in the write enable bit of system clock control registers 0 and 1 and frequency synthesizer related registers causes system clock control register 0 and 1 and frequency synthesizer related registers to be in write enabled state 2 The contents of system clock control register 0 and 1 and these of frequency synthesizer related registers are changed 3 Setting 0 in PRCO causes system clock control register 0 and 1 and frequency synthesizer related registers to be in write inhibited state 4 To change the contents of processor mode register 0 and that of processor mode register 1 follow the same steps as in dealing with system clock control registers and frequency synthe sizer related registers 1 Clearing the protect set to write enabled state b7 b0 Protect register Address 000A16 POTEN l pe i Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 and frequency synthesizer related registers address 03DB16 to O3DF 16 1 Write enabled 3 Setting the protect set to write inhibited state b7 bO Protect register Address 000A16 PODDD lol prer Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 and frequency synthesizer related registers address 03DB16 to 03DF16 0 Wr
153. 45 group can select a USB USB0 USB1 USB2 USB3 as the DMA request factor The USBO corresponds to DMAO USB1 to DMA1 USB2 to DMA2 and USB3 to DMA3 The DMA request factor origin of USBO USB1 USB2 USB3 is also set by setting any one of endpoints 1 to 4 IN OUT factors to USB DMAx x 0 to 3 request register 2 USB function The DMA request factor of USBO USB1 USB2 USB3 occurs under particular conditions not only on occurrence of an interrupt request of each endpoint but also on write read to from IN OUT FIFO 1 Related Registers USB DMAx x 0 to 3 request register This register sets the DMA request factor origin of USBO USB1 USB2 USB3 When under particular conditions write read to from the FIFO of the endpoint selected by this register or an event such as the endpoint s interrupt request occurs a DMA request occurs This register can be set 1 only to 1 bit When multiple bits are simultaneously set to 1 the setting becomes invalid Other DMA related registers also need to be set before a valid value is set for example 000112 USBO USB1 USB2 USB3 is set to DMA request cause select bits b4 b3 b2 b1 b0 of DMAx x 0 to 3 request cause select register addresses 03B816 03BA16 03B016 03B216 The configuration of USB DMAx x 0 to 3 request register is shown in Figure 2 8 50 USB DMAx Request registers b15 b8 b7 bo b7 Symbol 0 0 USBDMAx x 0 to
154. 5 Group 2 Serial Interface Special Function Example of wiring Microcomputer Receiver side IC Example of operation 1 Set SSi port to L with the output from the receiver side IC port i 2 Transmission enabled 4 Transmission is complet 3 Start transmission 5 Transmit next data 4 Transfer clock f TE 0 Transfer data is set to UARTi transmit buffer register Transmit buffer 1 empty flag TI Transferred from UARTI transmit butter register to transmit register Sti Tazss XOX YE HES KOHN OHNO O 2020000 C Transmit register 1 ee a ee empty flag TXEPT g l Transmit interrupt 1 a es a request bit IR g has ka Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Make sure that the following conditions are met when External clock is selected the CLKi pin input H before data reception e CLK polarity select bit 0 Transmit enable bit 1 Transmit data written to UARTIi transmit buffer register fEXT frequency of external clock Figure 2 5 14 Operation timing of transmission in serial interface special function slave mode without clock delay Rev 2 00 Oct 16 2006 page 103 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Setting UARTIi transmit receive mode regi
155. 5 Group 2 USB function USB endpoint 0 MAXP register This register indicates the IN OUT maximum packet size of endpoint 0 When a GET_DESCRIPTION request is received from the host CPU write to this register to change the IN OUT maximum packet size value of endpoint 0 Set the packet size value 8 16 or 32 bytes specified by control transfer The default value is 8 bytes The configuration of USB endpoint 0 MAXP register is shown in Figure 2 8 33 USB Endpoint 0 MAXP register b8 Symbol Address When reset EPOMP 029A16 000816 Bit Symbol Bit Name Function Set maximum packet size EPOMP6 0 Maximum packet size of EPO IN OUT Reserved Must always be 0 Figure 2 8 33 USB endpoint 0 MAXP register USB endpoint 0 OUT write count register This register contains the number of bytes of the current data set in the OUT FIFO When the USB function control unit completes the data packet receive from the host CPU set the value of this regis ter When one buffer data receive completes read this register and determine the number of bytes to be read from OUT FIFO This register value is not decremented even if the data is read from OUT FIFO When CLR_OUT_BUF_RDY bit of the EPOCSR is set to 1 this register value is cleared to 0 The configuration of USB endpoint 0 OUT write count register is shown in Figure 2 8 34 USB Endpoint 0 Write Cou
156. 6 Transmit enable bit 1 Transmit enable Disable DMAO b7 DMAO control register DMOCON Address 002C16 DMA enable bit 0 Disabled Setting DMAO cause select register 0 DMAO cause select register 0 1114 1 most address 038816 a a DMA request cause select bits 01110 UART1 transmit Nothing is assigned Write 0 when writing to these bits Software DMA request bit 0 Not occurred Setting DMAO control register b7 b0 DMAO control register 0 1 0 0 9 1 DMocon Address 002C16 Transfer unit select bit 1 8 bits Repeat transfer mode select bit 0 Single transfer DMA request bit 0 DMA not requested DMA enable bit 0 Disabled Source address direction select bit 1 Forward Destination address direction select bit 0 Fixed Setting source pointer internal RAM address and destination pointer UART1 transmit buffer b23 b19 b16b15 b8 b7 bo DMAO source pointer ofololo 0416 0016 SARO Address 002216 to 002016 Stores the internal RAM address 040016 Nothing is assigned Write O when writing to these bits t b19 b16b15 bo DMAO destination pointer ojojoj 0316 6A16 DARO Address 002616 to 002416 _______ Stores the address of UART1 transmit buffer register 036A16
157. 6 033D16 32D16 aa Must be fixed to 0 in UART mode Data logic select bit 0 No reverse Error signal output enable bit in UART mode 0 Output disabled Continued to the next page Figure 2 4 8 Set up procedure of transmission in UART mode 1 Rev 2 00 Oct 16 2006 page 66 of 354 7tENESAS REJ09B0340 0200 2 UART M30245 Group Continued from the previous page Setting UARTi bit rate generator i 0 to 3 b7 bO UARTi bit rate generator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 _____ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTI bit rate generator when transmission reception is halted aun enabled b0 UARTi transmit receive control register 1 POT UiC1 Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled b7 b0 b7 Setting transmission data Setting transmission data 9th bit Note Use MOV instruction to write to this register ee as A Writing transmit data Note b15 b8 UARTO transmit buffer register Address 03AB16 03AA16 UOTB b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB When CTSi input level L Start transmission Checking the status of UARTi transmit buffer register
158. 6 to 001016 RMADO Address match interrupt register 1 Address 001616 to 001416 RMAD1 b23 b20 b19 b16 b15 b8 b7 b4 b3 b0 b7 b0 b7 o Can be set to 0000016 to FFFFF16 Setting address match interrupt enable register b7 0 Address match interrupt enable register Address 000916 AIER Address match interrupt 0 enable bit 1 Interrupt enabled Address match interrupt 1 enable bit 1 Interrupt enabled Figure 2 13 4 Set up procedure of address match interrupt Rev 2 00 Oct 16 2006 page 260 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 Address Match Interrupt C Address match interrupt routine J 1 Storing registers 2 Determining the interrupt address No Address match 0 Yes Address match 0 program Address match Yes Address match 1 program lt 3 Rewriting the stack Restoring registers y Handling an error REIT Explanation 1 Storing the contents of the registers holding the main program status to be kept 2 Determining the interrupt address Determining which factor generated the interrupt 3 Rewriting the stack Rewriting the return address Figure 2 13 5 Overview of the address match interrupt handling routine Rev 2 00 Oct 16 2006 page 261 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Key Input Interrupt
159. 7 b0 b7 b0 0 USB endpoint x OUT control and status register EPxOCS x 1 4 Address 02B616 02BE16 02C616 O2CE16 CLR_OUT_BUF_RDY bit 1 Updates OUT_BUF_STS0 OUT_BUF_STS1 flags Note 3 The packet data is one buffer data in continuous transfer mode Note 4 When the AUTO_CLR bit is set to 1 the OUT_BU_STSO and the OUT_BUF_STS1 flags are automatically updated without setting 1 to the CLR_OUT_BUF_RDY bit when the data count equal to one packet is read from the OUT FIFO Execution of the above 2 3 and 4 when one more are set in the OUT FIFO Completion of packet fetch Figure 2 8 44 Endpoint 1 to 4 OUT packet fetching routine Rev 2 00 Oct 16 2006 page 192 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function 2 8 7 USB Operation Endpoints 1 to 4 Transmit Endpoints 1 to 4 can apply to the isochronous transfer bulk transfer and interrupt transfer The endpoints 1 to 4 respectively have their IN transmit FIFOs and OUT receive FIFOs For using the endpoints 1 to 4 IN enable each endpoint IN FIFO by USB endpoint enable register ad dress 028E16 The size and the starting location every 64 bytes of each endpoint x x 1 4 IN FIFO can be set according to the user s system The buffer size of IN FIFO can be set to a maximum of 1024 bytes per 64 bytes for one endpoint When the double buffer mode is enabled the buffer which has twice as
160. 7 bO Lo Destination pointer Stores the destination address ra Setting DMAi transfer counter DMAO transfer counter Address 002916 002816 TCRO DMA1 transfer counter Address 003916 003816 TCR1 DMA2 transfer counter Address 018916 018816 TCR2 b15 b8 DMAS transfer counter Address 019916 019816 TCR3 bO bo b7 bo Transfer counter C Set a value one less than the transfer count Setting DMAi control register b7 b0 DMAi control register Address 002C16 003C16 018C16 019C16 DOI t pmicons o to 3 DMA enable bit er C 1 Enabled Note Clear DMA request bit simultaneously again When software DMA request bit 1 Start DMA transmission Figure 2 10 8 Set up procedure of repeated transfer mode Rev 2 00 Oct 16 2006 page 248 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 11 CRC Calculation Circuit 2 11 1 Overview 2 CRC Calculation Circuit Cyclic Redundancy Check CRC is a method that compares CRC code formed from transmission data by use of a polynomial generation with CRC check data so as to detect errors in transmission data Using the CRC calculation circuit allows generation of CRC code The microcomputer uses a generator polyno mial of CRC_CCITT X18 X12 X5 1 or CRC 16 X18 X15 4 X24 1 to generte CRC code And the CRC circuit includes the ability to snoop reads and writes to SFR addresses This can be used to accumulate the
161. ART1 receive ACK SSI1 interrupt control register S1RIC 004916 UARTO 2 Bus collision interrupt control register S02BCNIC 004A16 UARTO receive ACK SSIO interrupt control register SORIC wz 004D14 UARTS transmit NACK interrupt control register S3TIC 004F 16 UART2 transmit NACK interrupt control register S2TIC 005116 UART1 transmit NACK SSI1 interrupt control register S1TIC 7 005316 UARTO transmit NACK SSIO interrupt control register SOTIC X 005516 UARTS receive ACK interrupt control register S3RIC 032816 UARTS transmit receive mode register U3MR 032916 UARTS bit rate generator U3BRG 032A16 032Bi6 UARTS transmit buffer register U3TB 032C16 UARTS transmit receive control register 0 U3CO 032D16 UARTS transmit receive control register 1 U3C1 032E16 032F16 UARTS receive buffer register U3RB X 033816 UART2 transmit receive mode register U2MR 033916 UART2 bit rate generator U2BRG 033A16 033B16 UART2 transmit buffer register U2TB 033C16 UART2 transmit receive control register 0 U2C0 033D16 UART2 transmit receive control register 1 U2C1 033E16 033F16 UART2 receive buffer register U2RB 2 UART 035F16 Interrupt cause select register IFSR N 036816 UART1 transmit receive mode register U1MR
162. ARTO transmit buffer register Address 03AB16 03AA16 UOTB b0 b7 b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032Ai6 U3TB Setting transmission data Note Use MOV instruction to write to this register Se C UARTI transmit interrupt Confirm RxDi pin level b bi b7 o Port P6 register Address 03EC16 y go P7 register Address 03ED16 P6 L Porn P71 register RxD2 pin Port P62 register RxDo pin 0 L level 0 L level 1 H level 1 H level Port P66 register RxD1 pin Port P75 register RxD3 pin eag Bg 0 L level 0 L level ore 1 H level 1 H level REIT instruction Figure 2 4 15 Set up procedure of transmission in UART mode used for SIM interface 2 Rev 2 00 Oct 16 2006 page 76 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 SIM interface 2 4 6 Operation of Serial I O reception used for SIM interface In receiving data in UARTi i 0 to 3 mode used for SIM interface choose functions from those listed in Table 2 4 7 Operations of the circled items are described below Figure 2 4 16 shows the operation timing and Figures 2 4 17 to 2 4 18 show the set up procedures Table 2 4 7 Choosed functions Transfer data Direct format Transfer clock Internal clock f1 fs f32 format sou
163. AS REJ09B0340 0200 M30245 Group 3 USB Applications Continued from the previous page Setting DMAO control register b7 bo DMAO control register DX lt PxLo 0f0 0 0 0 DMOCON Address 002C16 Transfer unit select bit 0 16 bits Repeat transfer mode select bit 0 Single transfer DMA request bit 0 DMA not requested DMA enable bit 0 Disabled Source address direction select bit 0 Fixed Destination address direction select bit 0 Fixed Setting source pointer endpoint 1 OUT FIFO data register and destination pointer SS interface 1 transmit buffer register b23 b19 b16b15 b8 b7 b0 DMAO source pointer ojojo 0216 E616 SARO Address 002216 to 002016 Stores the endpoint 1 OUT FIFO Address 02E616 Nothing is assigned Write 0 when writing to these bits b16b15 bo 0 0 DMAO destination pointer DARO Address 002616 to 002416 Stores the SS interface 1 transmit register Address 037416 Nothing is assigned Write 0 when writing to these bits Checking that OUT_BUF_STS1 flag is 1 and setting the number of the transfer bytes Note ra b15 b8 b7 b0 b7 DMAO transfer counter 0016 8F 16 TCRO Address 002916 002816 Note Set 1 2 X the value of Endpoint 1 OUT write count register 1 Enable serial sound interface 1
164. AXP register USB endpoint x x 1 to 4 OUT write count register This 11 bit register contains the number of bytes of one buffer data written in the endpoint x x 1 4 OUT FIFO This register is for read only When the USB function control unit completes the data packet receive from the host CPU set the value of this register When one buffer data receive com pletes read this register and determine the byte count of the data to be read from OUT FIFO This register value is not decremented even if the data are read from USB endpoint x OUT FIFO register When this register is read while there are two buffer data in OUT FIFO in the double buffer mode the number of bytes of the packet data received at first is already stored When CLR_OUT_BUF_RDY bit is set to 1 after one buffer data is read from OUT FIFO this register value is updated to the number of bytes of buffer data subsequently received The configuration of USB endpoint x x 1 to 4 OUT write count register is shown in Figure 2 8 42 USB Endpoint x OUT Write Count register b15 b8 b7 BO 167 Symbol Address When reset 0 0 EPxWC x 1 4 02BA16 02C216 000016 Po oe fo GE SR a a 02CA16 02D216 Bit Symbol Bit Name Function The byte count of receive one buffer data in the EPx OUT FIFO is set WCNT10 0 Receive byte count Reserved Must always be 0 Figure 2 8 42 USB endpoint x x
165. C16 36C16 033C16 32C 16 BRG count source select bit b1 b0 00 f1 is selected 01 fs is selected 1 0 f32 is selected 11 Inhibited CTS RTS function select bit Valid when bit 4 0 1 RTS function is selected Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS disable bit 0 CTS RTS function enabled Data output select bit Note 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output Must be fixed to 0 in UART mode L Transfer format select bit 0 LSB first Note UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output XN Setting UART transmit receive control register 1 i 0 to 3 zi b0 UARTI transmit receive control register 1 lofofo TT UiC1 Address 03AD16 36D16 033D16 32D16 Must be fixed to 0 in UART mode Data logic select bit 0 No reverse Error signal output enable bit in UART mode 0 Output disabled Continued to the next page Figure 2 4 11 Set up procedure of reception in UART mode 1 Rev 2 00 Oct 16 2006 page 70 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 UART Continued from the previous page Setting UARTI bit rate generator i 0 to 3 b7 bO UARTi bit rate g
166. CLK polarity This function switches the polarity of the transfer clock The following operations are available e Data is input at the falling edge of the transfer clock and is output at the rising edge e Data is input at the rising edge of the transfer clock and is output at the falling edge c Function for choosing which bit to transmit receive first This function is to choose whether to transmit receive data from bit 0 or from bit 7 Choose either of the following e LSB first Data is transmitted receivec from bit 0 e MSB first Data is transmitted received from bit 7 d Function for choosing continuous receive mode Continuous receive mode is a mode in which reading the receive buffer register makes the reception enabled status ready In this mode there is no need to write dummy data to the transmit buffer register so as to make the reception enabled status ready But at the time of starting reception read the receive buffer register into a dummy manner e Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready e Continuous receive mode Reading the reception buffer register makes the reception enabled status ready e Data logic select function This function is to reverse data when writing to transmit buffer register or reading from receive buffer register f Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from
167. CRC value on a stream of data without using extra bandwidth to explicitly write data into the CRCIN register 1 Registers related to CRC calculation circuit Figure 2 11 1 shows the memory map of CRC related registers and Figure 2 11 2 shows CRC re lated registers 03B416 03B516 CRC snoop address register CRCSAR 03B616 CRC mode register CRCMR X 03BC16 03BD16 CRC data register CRCD 03BE16 CRC input register CRCIN Figure 2 11 1 Memory map of CRC related registers Rev 2 00 Oct 16 2006 page 249 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 CRC Calculation Circuit CRC data register b15 b8 oy ae Address When reset 03BC16 to O3BD16 Indeterminate Function Values that canbe set R iW CRC calculation result output 000016 to FFFFis O O CRC input register b7 Symbol Address When reset CRCIN 03BE16 Indeterminate Function Values that can be set R w Data input 0016 to FF16 0KO CRC mode register p7 Symbol Address When reset CRCMR 03B616 0016 Function Bit symbol Bit name CRCPS CRC mode polynomial 0 X164X12 X3 1 CRC CCITT selection bit 1 X16 X15 X2 1 CRC 16 Nothing is assigned Write 0 when writing to this bit The value is 0 if read CRC mode mode 0 LSB first mode selection bit 1 MSB first mode CRCMS CRC snoop address
168. D conversion start flag is set to O by software The conversion result is transmitted to AD register i every time a conversion is completed 1 Start A D conversion 2 Conversion result is transferred to the AD register 3 A D conversion 8 bit resolution 28 oAD cycles i 8 bit resolution 28 pAD cycles 3 is complete 10 bit resolution 33 AD cycles 10 bit resolution 33 AD cycles UU UUW UUW Set to 1 by software Cleared to 0 by software A D conversion 1 f i start flag g i l AD register i Result x Result A D conversion Stop Convert Convert Conver Stop Note When eap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 oD cycles for 10 bit resolution Figure 2 9 8 Operation timing of repeat mode Rev 2 00 Oct 16 2006 page 222 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter Selecting Sample and hold b7 b0 AD control register 2 Address 03D416 DTD DXDT ansonz 9e A D conversion method select bit 1 With sample and hold Ne Must always be set to 0 a Setting AD control register 0 and AD control register 1 b7 b0 b7 0 l olol AD control register 0 Address 03D616 fg AD control register 1 Address 03D716 ADCONO ADCON1 Anal
169. Di RxDi selected master mode Transmission Transmission buffer empty STxDi SRxDi selected interrupt factor i Transmission complete slave mode Operation 1 Set an SS port of the receiver side IC to output L level 2 Setting the transmit enable bit to 1 and writing transmission data to the UARTi transmit buffer register makes data transmissible status ready 3 In synchronization with the first falling edge of the transfer clock transmission data held in the UARTI transmit buffer register is transmitted to the UARTIi transmit register At this time the UARTIi transmit interrupt request bit goes to 1 Also the first bit of the transmission data is transmitted from the TxDi pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges 4 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that transmission is completed The transfer clock stops at L level 5 If the next transmission data is set in the UARTi transmit buffer register while transmission is in progress before the eighth bit has been transmitted the data is transmitted in succession Note e Set SSi pin to H level If L level is input to the pin a fault error will be generated Rev 2 00 Oct 16 2006 page 94 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Example of wiring
170. External clock Note 1 External clock Note 1 0 Normal Reversed Note 1 When 12C bus interface mode is selected set the port direction register for the corresponding port SCLi to 0 or the port direction register to 1 and the port data register to 1 When a mode other than serial I O mode is selected set the port direction register for the corresponding port CLKi to 0 Note 2 Normally set to 0 Note 3 Set the RxDi pin s port direction register to O when receiving Figure 2 4 4 UARTi related registers 2 Rev 2 00 Oct 16 2006 page 61 of 354 REJ09B0340 0200 7tENESAS M30245 Group UARTI transmit receive control register 0 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 U Symbol iCO i 0 to 3 Bit name BRG count source select bit CTS RTS function select bit Address 03AC16 036C16 033016 032C16 Function During clock synchronous serial I O mode b1 b0 00 f1is selected 0 1 f8is selected 10 f32is selected 1 1 Inhibited Valid when bit 4 0 0 CTS function is selected Note 1 RTS function is selected Note 4 When reset 0816 Function During UART mode b1 b0 00 f1is selected 01 fsis selected 10 f32is selected 11 Inhibited Valid when bit 4 0 0 CTS function is selected Note 1 1 RTS function is selected Note 4 Transmit register empty flag Data present in transmit register during transmission No data present in transmit reg
171. Figure 2 9 12 shows timing chart and Figure 2 9 13 shows the set up procedure Table 2 9 6 Choosed functions Operation clock AD Divided by 4 fap divided Trigger for starting Software trigger by 3 fap divided by 2 fap A D conversion AD Trigger by ADTRG Resolution 8 bit 10 bit Sample amp Hold Not activated Analog input pin Activated ANo and AN1 2 pins ANo to ANs 4 pins ANo to AN5 6 pins ANo to AN7 8 pins Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo pin 2 After the A D conversion of voltage input to the ANo pin is completed the content of the successive comparison register conversion result is transmitted to AD register 0 3 The A D converter converts all pins selected by the user The conversion result is transmitted to AD register i corresponding to each pin every time A D conversion on the pin is completed The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until the A D conversion start flag is set to O by software 1 Start A D conversion 2 AN1 conversion begins after ANO sabia 4 A D conversion _ conversion is complete 3 Consecutive conversion is complete 8 bi resolution 28 oAD cycles 8 bit resolution 28 oAD cycles 10 bit resolution 33 gap cycles 10 bit resolution 33 AD cycles i a
172. H Fourth byte RL Third Word Write Fifth byte LM Sixth byte LH Fourth Word Write Seventh byte OFor 32 bit data Eighth byte Left Buffer LL bO to b7 LM b8 to b15 LH b16 to b23 MSB LSB b7 b0 RL b0 to b7 RM b8 to b15 RH b16 to b23 Right Buffer OPERATION Byte 3 First Word Write First byte LL Byte 2 Second byte LML Byte 1 Byte 2 Byte 1 Second Word Write Third byte LMH Fourth byte LH Third Word Write Fifth byte RL Sixth byte RML Fourth Word Write Seventh byte RMH LL bO to b7 LML b8 to b15 LMH b16 to b23 LH b24 to b31 Eighth byte RH RL b0 to b7 RML b8 to b15 RHH b16 to b23 RH b24 to b31 Figure 2 6 4 Example of Audio stream PCM from the PC to the M30245 USB FIFO Rev 2 00 Oct16 2006 page 115 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Serial sound interface 2 6 2 Example of Serial Sound Interface operation When using Serial Sound Interface SSI the DMA is recommended for reading and writing data quickly from the receive buffer to the transmit buffer A programming example using DMA is shown below Figure 2 6 5 shows an example of Serial Sound Interface transmit timing and Figure 2 6 6 shows an example of Serial Sound Interface receive timing kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Serial Sound Interface initialization routine Serial Sound Interface
173. HE WR Note 3 P53 to P57 BCLK HLDA HOLD ALE RDY Bus width 16 bit BYTE L Microcomputer External device POo to P07 Data bus Do to D7 P10 to P17 Data bus Ds to D15 P20 to P27 P30 to P37 Address bus Ao to A15 P40 to P43 Address bus A16 to A19 Note 1 P44 to P47 Chip select CS0 to CS3 Note 2 P50 to P52 RD WRL WRH RD BHE WR Note 3 BCLK HLDA HOLD ALE RDY Note 1 Can be switched to I O port using the port P40 to P43 function select bits of processor mode register 0 address 000416 Note 2 When reset only CSo outputs a chip select signal CS1 through CS3 become input ports I O ports can be switched using the CSi output enable bit of the chip select control register address 000816 Note 3 The feature can be switched using the R W mode select bit of processor mode register 0 address 000416 Figure 4 2 1 Level of BYTE pin and external data bus width Rev 2 00 Oct 16 2006 page 331 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 2 2 Chip Selects and Address Bus Chip selects P44 CS0 through P47 CS3 are output in areas resulting from dividing a 1 M byte memory space into four To use the chip select the chip select output must be enabled by setting the chip select control register Figure 4 2 2 shows addresses in which chip selects become active L Since the extent of the internal area and the external area in memory expansion mode is different from those in microproces
174. In this diagram when reset the microcomputer starts operating in single chip mode Change this mode to memory expansion mode in a program Microcomputer M5M51016BTP Do to D15 Figure 4 3 1 Example of connecting M5M51016BTP Rev 2 00 Oct 16 2006 page 334 of 354 AS REJ09B0340 0200 RENES M30245 Group 4 External Buses 4 3 2 8 bit Memory to 16 bit Width Data Bus Connection Example Figure 4 3 2 shows an example of connecting two M5M5278 s SRAM to a 16 bit data bus In this dia gram when reset the microcomputer starts operating in single chip mode Change this mode to memory expansion mode in a program Microcomputer CNVss WRL BYTE Do to D15 M5M5278D M5M5278D A1 to A15 Figure 4 3 2 Example of connecting two M5M5278 s to a 16 bit data bus Rev 2 00 Oct 16 2006 page 335 of 354 RENESAS REJ09B0340 0200 M30245 Group 4 External Buses Figure 4 3 3 shows how to connect two Am29LVO008B flash memory In 16 bit bus mode the BHE WRH pin functions as BHE When connecting 8 bit flash memory chips to the 16 bit bus make sure the microcomputer s WRL pin is connected to the WR pins on both flash memory chips and that data is written to the flash memory in units of 16 bits beginning with an even address Microcomputer Am29LV008B Ai to A19 Am29LV008B Figure 4 3 3 Example of connecting two Am29LV
175. LK selected Each peripheral function operates according to its assigned clock Medium speed mode Divide by 2 divide by 4 divide by 8 or divide by 16 frequency of the main clock becomes the BCLK The CPU operates according to the BCLK selected Each peripheral function operates according to its assigned clock Low speed mode fc becomes the BCLK The CPU operates according to the fc clock The fc clock is supplied by the secondary clock Each peripheral function operates according to its assigned clock e Low power consumption mode The main clock operating in low speed mode is stopped The CPU operates according to the fc clock The fc clock is supplied by the secondary clock The only peripheral functions that operate are those with the sub clock selected as the count source b Wait mode The CPU operation is stopped The oscillators do not stop c Stop mode All oscillators stop The CPU and all built in peripheral functions stop This mode among the three modes listed here is the most effective in decreasing power consumption Figure 2 16 1 is the state transition diagram of the above modes 2 Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity Rev 2 00 Oct 16 2006 page 274 of 354 RENESAS REJ09B0340 0200 M30245 Group Transition of stop mode wait mode 2 Power Control All oscillators stopped Stop mode M
176. N FIFO set SET_IN_BUF_RDY bit to 1 and simultaneously set SET_DATA_END bit to 1 Both the IN_BUF_RDY flag and DATA_END flag are set to 1 When the DATA_END flag becomes 1 after completion of transmission of the last data packet the USB function control unit proceeds to the status phase processing When the status phase is completed the DATA_END flag is cleared to O Manage the stage of control transfer by software Example of one packet data transmit procedure 1 Check that the packet data does not exist in IN FIFO the IN_ BUF_RDY flag is O before writing the data of the 2nd packet and after of data stage 2 The data is written in IN FIFO based on the amount specified on the SETUP stage When an empty packet with 0 data length is transmitted the data is not written in IN FIFO The subsequent stage and operation are determined 3 With SET_IN_BUF_RDY bit being set to 1 one packet transmission is prepared and the next stage control is managed e For shifting into the status stage even if the next data to be transmitted does not exist simulta neously set SET_IN_BUF_RDY bit and SET_DATA_END bit e When the next empty packet is transmitted set SET_IN_BUF_RDY bit to 1 and continue transmitting processing Rev 2 00 Oct 16 2006 page 176 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 4 Control Transfer Example of Standard Device Request Receive The control transfer includ
177. NTilC i 1 2 Address 004416 005E16 0 Ololo S1RIC Address 004816 S02BCNIC Address 004916 Interrupt priority level select bit 000 Interrupt disabled Reserved bit Must always be set to 0 KUPIC Address 004116 DMilC i 0 to 3 Address 004C16 004E16 005016 005216 SiRIC i 0 2 3 Address 004A16 004216 005516 SiTIC i 0 to 3 Address 005316 005116 004F 16 004D16 3 Controlling Power Applications S Continued to the next page Figure 3 9 2 Set up procedure of controlling power using wait mode 1 Rev 2 00 Oct 16 2006 page 326 of 354 AS REJ09B0340 0200 RENES M30245 Group Continued from the previous page 3 Controlling Power Applications Canceling protect BXKEELL IT Protect register Address 000A16 PRCR 1 write enabled Enables writing to system clock control registers 0 and 1 address 000616 and 000716 Switching system clock b7 1 System clock control register 0 Address 000616 CMO Reserved bit Must always be set to 0 System clock select bit 1 XCIN XCOUT b0 o Stopping main clock System clock control register 0 Address 000616 Reserved bit Must always be set to 0 Main clock X N XouT stop bit 1 Off F_WIT 1 C Interrupt enable flag I flag lt 1 JMP B instruction WAIT instruction NOP instruct
178. Nothing is assigned Write 0 when writing to these bits J J Continued to the next page Figure 3 6 2 Setting routine 1 of DMA transfer from RAM to UART using SFR snooping function Rev 2 00 Oct16 2006 page 313 of 354 ENESAS REJ09B0340 0200 X M30245 Group 3 CRC Snoop Function Applications Continued from the previous page Enable DMAO b7 DMADO control register DMOCON Address 002C16 DMA request bit 0 DMA not requested DMA enable bit 1 Enabled e Clear CRC data register b15 b8 b7 0016 CRC data register CRCD Address 03BD16 03BC16 Setting CRC mode register 0 CRC mode register 0 CRCMR Address 03B616 CRC mode polynomial selection bit 0 CRC CCITT CRC mode selection bit 0 1 MSB first mode Setting CRC snoop address register b15 b8 b7 CRC snoop address register ue een CRCSRA Address 03B516 03B416 _____ SFR snoop address bit Set address 036A16 UART1 transmit buffer register CRCSAR Read 0 Disabled CRCSAR Write Me 1 Enabled Set Software DMA request bit to 1 in the status that DMA enable bit is 1 b0 b7 DMAO cause select register 1 XX DMOSL Address 03B816 Software DMA request bit 1 Occurred yp Transfer to CRC input register
179. O consists of total 256 bytes including IN transmit FIFO and OUT receive FIFO each respectively of 128 bytes The starting position is allocated from the 3072nd byte to the 3327th byte of the endpoint FIFO Both the endpoint 0 FIFO size and the starting position are fixed The FIFO size to be used is determined by the USB endpoint 0 maximum packet size The packet data received from the host CPU are written in endpoint O OUT FIFO When a data receive request is issued by the host CPU while data already exists in the OUT FIFO responds with NAK auto matically When packet data are transmitted to the host CPU the transmit data are written in the endpoint 0 IN FIFO When a data transmit request is issued by the host CPU before the data are written in IN FIFO responds with NAK automatically A packet data can realize higher transmit receive by enabling continu ous transfer When an error is detected in control transfer responds with STALL automatically and the error detection is reported Based on the status of the endpoint 0 communication data transmit receive is controlled in accordance with the device request which is received from the host CPU 1 Related Registers USB address register USB address register maintains 7 bits addresses of the USB function control unit that are allocated by the host CPU The USB function control unit of the M30245 group responds to the token packet for the address retained in this register When the USB function
180. OQOOSOCIOHOOSSOE_OOSSOSOE r A g S a E a 7 Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Te TcLK 2 n 1 fi The above timing applies to the following settings fi frequency of BRGi count source f1 f8 f32 e Internal clock is selected n value set to BRGi e CTS function is selected e CLK polarity select bit 0 e Transmit interrupt cause select bit 0 Figure 2 3 5 Operation timing of transmission in clock synchronous serial I O mode Rev 2 00 Oct 16 2006 page 46 of 354 REJ09B0340 0200 7tENESAS M30245 Group Figure 2 3 6 Set up procedure of transmission in clock synchronous serial I O mode 1 2 Clock Synchronous Serial I O Setting UARTIi transmit receive mode register i 0 to 3 b0 UARTIi transmit receive mode register b7 fo Jofofof UiMR Address 03A816 36816 033816 32816 Must be fixed to 001 Serial I O mode Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to 0 A a Setting UARTi transmit receive control register 0 i 0 to 3 b7 b0 olol Jol To UARTi transmit receive control register 0 UiCO Address 03AC16 36C16 033C16 32C 16 BRG count source select bit b1 b0 00 f1 is selected 01 fs is s
181. OUT_BUF_RDY flag POCSR1__ IN_BUF_RDY flag No setup packet ready for unload Data set ready for transmit DATA_END not set by CPU or DATA END is set by CPU POCSR3 DATA_END flag then status phase starts DATA END set by CPU No protocol violation detected Protocol violation detected No premature completion of control transfer Premature completion of control transfer No action Data set unloaded from the OUT buffer No action Data set loaded in IN buffer sets IN_BUF_RDY flag No action Clears SETUP flag No action Last data pcket transferred to from buffer No action Clears FORCE_STALL flag No action Clears SETUP END flag No EPO STALL by CPU EPO STALL by CPU Clearing DATA_END event causing EPO interrupt is POCSR13 DATA_LEND_MASK unmasked Clearing DATA_END event causing EPO interrupt is masked POCSR2_ SETUP flag oj o 9g 0 POCSR4 FORCE_STALL flag POCSR5 SETUP_END flag POCSR6 CLR_OUT_BUF_RDY POCSR7 SET_IN BUF_RDY POCSR8 CLR_SETUP POCSR9 SET_DATA_END POCSR10 CLR_FORCE_STALL POCSR11_ CLR_SETUP_END 0 4 0 20 42 o 0 42 0 4 o o o POCSR12 SEND_STALL o Reserved Must always be 0 Note Always read a 0 Figure 2 8 32 USB endpoint 0 control and status register Rev 2 00 Oct16 2006 page 173 of 354 AS REJ09B0340 0200 RENES M3024
182. PLT TTT UiC1 Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Writing transmit data Note UARTO transmit buffer register Address 03AB16 03AA16 UOTB bis 08 bo UARTI transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB L M Setting transmission data Note Use MOV instruction to write to this register Start transmission Checking the status of UARTi transmit buffer register i 0 to 3 b7 UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled When transmitting continuously Writing next transmit data Note b8 615 UARTO transmit buffer register Address 03AB16 03AA16 UOTB b7 b0 b7 bo UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Setting transmission data Note Use MOV instruction to write to this register ep Transmission is complete Output an H to the SS port on the receiver side IC Rev 2 00 Oct 16 2006 page 97 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial
183. REJ09B0340 0200 CENESAS M30245 Group User s Manual RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY M16C 20 SERIES All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Technology Corp without notice Please review the latest information published by Renesas Technology Corp through various means including the Renesas Technology Corp website http www renesas com Rev 2 00 Renesas Technology Revision date Oct 16 2006 www renesas com 10 11 12 13 Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in thi
184. SB Function Address register b15 b8 b7 bO b7 Symbol Address When reset USBA 028016 000016 Bit Symbol Bit Name Function 7 bit programmable FUNAD6 0 Function address function address Reserved Must always be 0 Figure 2 8 31 USB address register USB endpoint 0 control and status register USB endpoint 0 control and status register consists of the bits concerning control information and status information of endpoint 0 e OUT_BUF_RDY Flag This flag shows the status of OUT FIFO The OUT_BUF_RDY flag is set to 1 in the following cases The setup packet is received One data packet is received from the host CPU in the data phase Set the OUT_BUF_RDY flag to 0 by setting 1 to CLR_OUT_BUF_RDY bit after reading the OUT FIFO e IN_BUF_RDY Flag This flag shows the status of IN FIFO When this flag is set to 1 shows that data to be transmitted to the host CPU exists in FIFO When transmission of the IN FIFO data is completed or when the SETUP_END flag is set to 1 this flag is cleared to O e SETUP Flag When the setup packet is received from the host CPU this flag is set to 1 The OUT_BUF_RDY flag is also set to 1 at this time This flag is cleared by setting 1 to CLR_SETUP bit DATA_END Flag This flag shows the status phase control of control transfer After the status phase is star
185. SB clock by clearing USB clock enable bit USBC5 to 0 3 Disable the frequency synthesizer by clearing frequency synthesizer enable bit FSE to O Normally for system design which continues enabling the USB function disabling the USB function control unit is not required 4 Vbus Detection During USB self powered operation the Vbus detect function is used to switch into bus power only when the device is connected to the host PC and power supply is available from the Vbus for minimiz ing battery consumption To use the Vbus detect function it is necessary that the VobusDTCT pin is processed by hardware and the Vbus detect interrupt is set by software The VobusDTCT pin is used for the Vbus detect function When operating the USB in self powered mode connect the Vbus line from the USB connector to the VbusDTCT pin For enable disable of the Vbus detect function set Vbus detect enable bit bit 7 at address 001F 16 of USB attach detach register to 1 Set the interrupt priority level by using USB Vbus detect interrupt control register VBDIC address 005C16 Each time the USB host powers ON OFF a Vbus detect interrupt will be occurred When a Vbus detect interrupt is occurred the Vbus detect state bit located in the port 9 data register bit 1 at address 03F 116 should be read to determine if the Vbus is powered ON OFF To avoid receiving a false Vbus detect interrupt at start up the Vbus detect should be enabled before e
186. SB first N channel open drain output Set to 0 0 LSB first 1 MSB first Note 1 Set the corresponding port direction register to O Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output Note 3 Only clock synchronous serial I O mode and 8 bit UART mode are valid Note 4 The corresponding port register and port direction register are invalid UARTI transmit receive control register 1 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiC1 i 0 to 3 Bit Symbol Bit Name Transmit enable bit Address When reset 03AD16 036D16 033D16 032D16 0216 Function clock synchronous serial I O mode Transmit disabled 1 Transmit enabled Function i UART mode Riw Transmit buffer empty flag Data present in transmit buffer register No data present in transmit buffer register Receive enable bit Receive disabled 1 Receive enabled Receive complete flag Data packet in receive buffer register No data packet in receive buffer register UARTI transmit interrupt cause select bit Transmit buffer empty TI 1 Transmit buffer completed TXEPT 1 UARTI continuous receive mode enable bit Continuous receive mode disabled Continuous receive mode enabled Set to 0 Data logic select bit 0 No reverse 1 Reverse Error signal output enable bit Set to 0
187. SBC5 S USBC7 Enable USB function control unit Figure 2 8 16 Setup timing of frequency synthesizer after hardware reset Rev 2 00 Oct 16 2006 page 144 of 354 RENESAS REJ09B0340 0200 M30245 Group Figure 2 2 USB function Initialization of USB FCU Clearing the protect b7 b0 Protect register Add 000A16 OA e ee Enable bit for writing to system clock control registers 0 and 1 and frequency synthesizer related registers 1 Write enabled Enable bit for writing to processor mode registers 0 and 1 0 Write inhibited Reserved bit Se Setting frequency synthesizer related registers z Frequency synthesizer prescaler FSP Address 03DE16 a 0016 to FF16 can be set b7 bo Frequency synthesizer B7 22 Frequency synthesizer bnaltibliey divider Ld g holt Address OSB Bip FSD Address 03DF16 C 5 0016 to FF16 can be set E 0016 to FF16 can be set Setting frequency synthesizer control register BODO Frequency synthesizer control register Address 03DC16 FSC Frequency Synthesizer enable bit 1 Enabled VCO gain control bit b2 b1 0 0 Lowest gain 0 1 Low gain 1 0 High gain Recommended 11 Highest gain Reserved bit LPF current control bit Note Note If the time for locking frequency synthesizer b6 b5 is needed first set to 112 High current 00 Disabled and set to 102 Medium current 0 1 Low current after it locked 1 0 Medium current Recom
188. So RTS1 RTS2 RTS3 pins e CLKo CLK1 CLK2 CLK3 pins e RxDo RxD1 RxD2 RxD3 pins e TxDo TxD1 TxD2 TxD3 pins 2 Clock Synchronous Serial I O Input pins for the CTS function Output pins for the RTS function Input output pins for the transfer clock Input pins for data Output pins for data Note Note Since TxD2 pin is N channel open drain this pin needs pull up resistor 8 Registers related to the serial I O Figure 2 3 1 shows the memory map of serial I O related registers and Figures 2 3 2 to 2 3 4 show serial O related registers 004216 UART2 receive ACK interrupt control register S2RIC NSN ow 036816 ART1 transmit receive mode register U1MR 004816 UART1 receive ACK SSI1 interrupt control register S1RIC 036916 ART1 bit rate generator U1BRG IN 036A16 N 004A16 UARTO receive ACK SSIO interrupt control register SORIC 036B16 ART1 transmit buffer register U1TB 036C16 aw ART1 transmit receive control register 0 U1CO 036D16 004D16 UARTS transmit NACK interrupt control register S3TIC ART1 transmit receive control register 1 U1C1 036E16 N 036F16 004F16 UART2 transmit NACK interrupt control register S2TIC ART1 receive buffer register U1RB PX X 005116 UART1 transmit NACK SSI1 interrupt control register S1TIC 03A816 ARTO transmit receive mode register UOMR
189. Start count 4 Stop count gt 1 gt Reload is Reload Counter content hex Set to 1 by software Cleared to 0 by software Seal Count start flag Write signal to r one shot start flag 1 fi X n i i le 1 fi_X n 1 gt One shot pulse output H i from TAIOUT pin LI L H Ti Ai int t eal I reg est bit me 0 A Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 20 Operation timing of one shot mode Rev 2 00 Oct 16 2006 page 26 of 354 7RENESAS REJ09B0340 0200 M30245 Group A Selecting one shot timer mode and functions b7 b0 o 0 E qo Timer Ai mode register i 0 to 4 Address 039616 to 039A16 TAiMR i 0 to 4 Selection of one shot timer mode Pulse output function select bit 1 Pulse is output External trigger select bit When internal trigger is selected this bit can be 1 or 0 Trigger select bit 0 When the one shot start flag is set 1 0 Must always be 0 in one shot timer mode Count source select bit j Count Count source period DEBS source f XIN 16MHz f XCIN 32 768kKHz on SEs 10 f32 i 500ns 1 1 fc32 1 2us 976 56 J Clearing timer Ai interrupt request bit Please refer to the notes on the one shot timer mode of Timer A b7 bo Timer Ai interrupt control
190. T2 transmit NACK UART3 transmit NACK A D Disabled Note 3 DMA1 DMA2 DMA3 Disabled Note 3 Disabled Note 3 x x Disabled Note 3 Nothing is assigned Write O when writing to these bits The value is O when read DSR Software DMA Software trigger is always enabled request bit Write 1 to trigger DSR bit Note 1 Software is always enabled Note 2 SSl Serial sound interface Note 3 This value should not be set DMA1 request cause select register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address DM1SL 03BA16 When reset 0016 Bit Symbol Bit Name Function Note 2 bi 8 S200 00 00 00 00 00g BAOtAOA0OAOHA OHA OA OH OA OA OA OA Og DSELO DMA request cause select bits 000000002 000000008 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 xX DMA Disabled INT1 falling edge INT1 two edges USB1 Timer AO Timer A1 Timer A2 Timer A3 Timer A4 UARTO receive ACK SSIO0 receive UART1 receive ACK SSI1 receive UART2 receive ACK UART3 receive ACK UARTO transmit NACK SSIO transmit UART1 transmit NACK SSI1 transmit UART2 transmit NACK UART3 transmit NACK A D DMAO Disabled Note 3 DMA2 DMA3 Disabled Note 3 Disabled Note 3 x x Disabled Note 3 4 Nothing is assigned Writ
191. TA4TGH Timer A4 event trigger select bit Input on TA4IN is selected Note Invalid TA3 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to 0 Figure 2 2 4 Timer A related registers 3 Rev 2 00 Oct 16 2006 page 10 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 TimerA Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset CPSRF 038116 0XXXXXXX2 Bit Symbol Bit Name Function Nothing is assigned Write 0 when writing to these bits The contents are indeterminate if read 0 No effect CPSR Clock prescaler reset flag 1 Reset The value is 0 when read One shot start flag b7 b6 b5 b4 b3 b2 bi bO 0 Symbo Address When reset ONSF 038216 0016 Bit Symbol Bit Name Function TAOOS Timer AO one shot start flag 0 Invalid 1 Timer start Note 1 TA10S Timer A1 one shot start flag TA2OS Timer A2 one shot start flag TA3OS Timer A3 one shot start flag TA40S Timer A4 one shot start flag Reserved Always set to 0 bi b0 TAOTGL 0 0 Input on TAOIN is selected Notes 2 3 Timer AO event trigger 0 1 Invalid select bit 1 0 TA4 overflow is selected TAOTGH 1 1 TA1 overflow is selected Note 1 The value is O when read Note 2 Set the corresponding pi
192. UT_BUF_STS0 flag OUT_BUF_STS1 flag b1 b0 0 0 No data set in the OUT buffer 0 1 Invalid 1 0 Single buffer mode Invalid Double buffer mode one data set in the OUT buffer Single buffer mode one data set in the OUT buffer Double buffer mode two data set in the OUT buffer No data set in the OUT FIFO Data set in the OUT FIFO 2 Reading of the number of receive one packet data Note 1 and storing it in the RAM_CNT user definition RAM b15 b8 ee bo b7 20 USB endpoint x OUT write count register 9 0 0 9 9 EPxWC x 1 4 Address 02BA16 02C216 02CA16 02D216 ______________Read the number of bytes of reception data and store it in the RAM_CNT Note 1 The packet data is one buffer data in continuous transfer mode 3 Reading of receive data equal to receive data count RAM_CNT from the OUT FIFO and storing it in the RAM_DATA user definition RAM b15 b8 a bo b7 20 USB endpoint x OUT FIFO data register EPxO x 0 4 Address 02E216 02E616 02EA16 02EE16 02F216 Read the reception data and store it in the RAM_DATA Note 2 Define the RAM_DATA equal to byte count required for receive 4 Setting of the CLR_OUT_BUF_RDY bit to 1 and completion Note 4 of one packet data Note 3 fetch b15 b8 b
193. UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Note 2 revised Note 4 added UiCi Note 1 added Figure 2 5 5 UiSMR bit 7 revised UISMR2 bit 7 revised Note 1 added Figure 2 5 6 UiSMR3 bit 5 7 revised Note 4 The amount of delay varies with the load on SCLi and SDAi pins added Figure 2 5 7 Note 2 added Figure 2 5 9 UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Figure 2 5 12 UiMR Note 1 added UiCO bit5 TxDi gt TxDi SDAi and SCLi revised Figure 2 5 15 UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Figure 2 5 18 UiMR Note 1 added UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised 110 120 2 6 added C 1 REVISION HISTORY M30245 Group User s Manual Rev Date Summary 2 00 Oct 16 2006 Figure 2 7 3 FSC bit 2 1 revised Table 2 7 1 revised Table 2 7 3 revised 2 8 2 USB control register the minimum 250ns of delay gt a minimum 187 5 ns of delay three cycles of BCLK 2 Enable of USB Function Control Unit 3 7 8 revised Figure 2 8 16 Wait for 4 or more cycles of 6 deleted Figure 2 8 17 FSC bit 2 1 revised Figure 2 8 18 revised 2 USB Endpoint 0 Interrupt The SETUP_END flag added 3 USB Function Interrupt e The last ACK for control rea added e Artificial SOF Function revised e USB Suspend Mode Control 1 revised and 5 6 Note added Returning Routine of USB Function Control Unit 5 dele
194. When selecting ATTACH function Set 0316 When ATTACH function disabled Set 0016 b7 bo USB Attach Detach register Address 001F16 ol ol fll Fae USBAD Port 90 Second 0 Normal mode for Port 90 1 Forces Port 90 to operate as pull up for D Attach Detach 0 Detach 1 Attach Reserved bit USB block enabled Note b7 bo USB control register Address 000C16 1 1 0 0 0 0 0 USBC USB enable bit 1 USB blobk enabled Note After the USB block is enabled USBC7 set to 1 a minimum delay of 187 5ns is needed before performing any other USB register read write operations Figure 2 8 18 Initialization procedure of frequency synthesizer and USB function control unit 2 Rev 2 00 Oct 16 2006 page 146 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function Initialization of Endpoint Initialization of endpoint 0 Control transfer b15 b8 a bo b7 bo USB endpoint 0 MAXP register Address 029A16 09 EPOMP Maximum packet size of endpoint 0 IN OUT a Setting the size and start location of IN OUT FIFO b15 b8 b7 b0 b7 USB Endpoint x IN FIFO configuration register EPxIFC x 1 to 4 Address 02A216 02A816 02AE16 02B416 0 IN FIFO buffer start number Select the starting number for the EPx IN FIFO in unit
195. able bit should be set to 1 A minimum delay of 250ns is needed before performing any other USB related registers read write operations Rev 2 00 Oct 16 2006 page 126 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 8 USB function 2 8 1 Overview The USB function control unit of the M30245 group is compliant with USB2 0 specification and supports Full Speed transfer USB2 0 specification defines the following four kinds of transfer types Control Transfer isochronous Transfer Interrupt Transfer Bulk Transfer The USB function control unit is provided with 9 endpoints including endpoint 0 endpoints 1 to 4 OUT receive and endpoints 1 to 4 IN transmit each of which having an FIFO The endpoint 0 can apply only to the control transfer same in transfer form as the bulk transfer while endpoints 1 to 4 IN OUT can apply to the bulk transfer isochronous transfer and interrupt transfer The size and the starting position of endpoints 1 to 4 IN OUT FIFO can be set according to the user s system The size and the starting position of endpoint 0 IN OUT FIFO are fixed Further when the double buffer mode is enabled the buffer which has twice as much as the set size is available for the IN OUT FIFO When the continuous receive transmit mode is enabled data can be transferred at a high speed in bulk transfer The USB related interrupts include USB suspend interrupt USB resume interrupt USB reset interrupt USB endpoin
196. above are enabled 1 1 0 Level 6 1 1 0 Interrupt levels 7 and above are enabled 1 1 1 Level 7 High 1 14i 1 All maskable interrupts are disabled When either the IPL or the interrupt priority level is changed the new level is reflected to the interrupt in the following timing e When changing the IPL using the REIT instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction e When changing the IPL using either the POPC LDC or LDIPL instruction the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used e When changing the interrupt priority level using the MOV or similar instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used 5 Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling check ing whether interrupt requests are made the interrupt assigned a higher priority is accepted Assign an arbitrary priority to maskable interrupts peripheral I O interrupts using the interrupt priority level select bit If the same interrupt priority level is assigned however the interrupt assigned a higher hardware priority is accepted Priorities of the special interrupts such as Reset dealt with as
197. ait mode the priority level of all interrupts must be set to level 0 before changing to stop mode Table 2 16 1 shows the interrupts that can be used for canceling stop mode and wait mode 5 BCLK in returning from wait mode or stop mode a Returning from wait mode The processor immediately returns to the BCLK which was in use before entering wait mode b Returning from stop mode CMO6 is set to 1 when the device enters stop mode after selecting the main clock for BCLK CM17 and CM16 do not change state In this case when restored from stop mode the device starts oper ating in divided by 8 mode When the device enters stop mode after selecting the subclock for BCLK CM06 CM17 CM16 and CMO07 all do not change state In this case when restored from stop mode the device starts operat ing in low speed mode Rev 2 00 Oct 16 2006 page 276 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Power Control Table 2 16 1 Interrupts available for clearing stop mode and wait mode Wait mode Interrupt for clearing CM02 1 Note 6 Stop mode CM02 0 CM07 0 CM05 0 UARTO UART 2 Bus collision detection Possible Note 1 Note 1 Start stop condition detection interrupt UART1 UART3 Bus collision detection Possible Note 1 Note 1 Start stop condition detection interrupt DMAO interrupt Impossible Impossible Impossible DMA 1 interrupt Impossible Impossible Impossible DMA2 interrupt Impossible Impossible Impossible DMA3 interru
198. aiting for completion of status phase DATA_END flag 1 0 Setting of address to USB address register Note 1 b15 b8 2i bo b7 bo USB address register 2 09 USBA Address 028016 L Set the third byte the lower of wValue of reception data __ Note 1 Only the lower 1 byte of the receive device address should be set J Completion of SET_ADDRESS request Figure 2 8 37 Processing routine 2 for getting device address when receiving SET_ADDRESS request Rev 2 00 Oct 16 2006 page 179 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function Receiving of endpoint 0 setup packet Confirming of receive data p18 eae bo USB endpoint 0 control and status register 0 EPOCS Address 029816 OUT_BUF_RDY flag Note 1 0 Reading data packet is complete 1 Data packet reception is compete SETUP flag 0 Data packet reception 1 SETUP packet reception Note 1 There is no receive data in FIFO 0 when this bit is set to 0 Reading of receive data b15 b8 b7 b0 b7 USB endpoint 0 OUT FIFO data register EPOO Address 02E216 ________ The data equal to receive byte count are read setup packet is 8 byte Store the receive data in user definition RAM To processing routine of other standard requests Is
199. akeup has been enabled enable interrupt control register of the peripheral functions used in remote wakeup 5 Set I flag to 1 6 Stop the system clock by setting all clock stop control bit bit O of CM1 to 1 7 During the bus power supply operation after setting the low power consumption mode by dis abling interrupts that are not used in return from the USB suspend state etc execute the low power consumption mode Note When the device is in self powered operation the above control is not required Rev 2 00 Oct 16 2006 page 163 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 USB function 3 USB Resume Function Returning Routine from USB Suspend State To return from the USB suspend state the M30245 group uses the USB resume interrupt occurred by receiving the resume signal from the host or the interrupt for remote wakeup for transmitting the resume signal to the host Returning by Resume Interrupt When the resume signal is received from the host CPU during the USB suspend state when de tected any bus activity on D D line in suspend detect state the USB resume interrupt request occurs setting 1 to interrupt request bit of USB resume interrupt control register address 005816 When the USB clock is operated the USB suspend status flag is automatically set to 0 at this time For returning from the suspend state by the USB resume interrupt follow the procedure below 1 Return the USB function
200. alues are indeterminate when read Note 1 Only O may be written Note 2 UARTO Timer A3 underflow signal UART1 Timer A4 underlfow signal UART2 Timer AO underflow signal UARTi special mode register 2 i 0 to 3 Symbol UiSMR2 i 0 to 3 Bit Name 12C mode select bit 2 Address When reset 03A616 036616 033616 032616 0016 NACK ACK interrupt DMA source ACK Transfer to receive buffer at the rising edge of last bit of receive clock Receive interrupt occurs at the rising edge of last bit of receive clock UART transfer receive interrupt DMA source UART receive Transfer to receive buffer at the falling edge of last bit of receive clock Receive interrupt occurs at the falling edge of last bit of receive clock Clock synchronous bit Disable Enable SCL wait output bit Disab Enable SDA output stop bit Disab Enable UARTI initialize bit Disable Enable SCL Wait output bit 2 UARTIi clock 0 output SDA output inhibit bit Disabled Enabled high impedance Nothing is assigned Write 0 when writing to this bit The values are indeterminate when read Note 1 These bits are unavailable when SCLi is external clock Figure 2 5 5 Serial interface special function related registers 4 Rev 2 00 Oct 16 2006 page 91 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Serial Interface Special Function
201. amples are described in section 2 4 2 and 2 4 3 e Transmission WITH CTS function WITHOUT other functions e Reception WITH RTS function WITHOUT other functions Also the SIM interface is used by adding some extra settings in clock asynchronous serial I O mode Direct or inverse format is selected by connecting SIM card The following examples are described in section 2 4 4 and 2 4 5 e Transmission WITH direct format e Reception WITH direct format 6 Input to the serial I O and the direction register To input an external signal to the serial I O set the direction register of the relevant port to input 7 Pins related to the serial I O e CTSo CTS1 CTS2 CTS3 pins Input pins for the CTS function RTSo RTS1 RTS2 RTS3 pins Output pins for the RTS function e CLKo CLK1 CLK2 CLK3 pins Input pins for the transfer clock e RxDo RxD1 RxD2 RxD3 pins Input pins for data e TxDo TxD1 TxD2 TxD3 pins Output pins for data Note Note Since TxD2 pin is N channel open drain this pin needs pull up resistor Rev 2 00 Oct 16 2006 page 58 of 354 7RENESAS REJ09B0340 0200 M30245 Group 8 Registers related to the serial I O Figure 2 4 2 shows the memory map of serial I O related registers and Figures 2 4 3 to 2 4 6 show UA RTi related registers 004216 UART2 receive ACK interrupt control register S2RIC 004316 UART1 3 Bus collision interrupt control register S13BCNIC N 004816 U
202. and IN_BUF_STSO flags are updated from 002 the IN FIFO empty to 112 the IN FIFO full eIn Double Buffer Mode When the first packet data Note 1 of double buffer is written while there is a space in IN FIFO the IN_BUF_STSO and IN_BUF_STS1 flags are updated from 002 to 012 indicating that the second packet data Note 1 is ready to be written to the IN FIFO In this case second packet data can be continuously prepared When there is only the first packet data Note 1 in the IN FIFO and second packet data Note 1 is written the IN BUF_STSO and IN_BUF_STS1 flags are updated from 012 to 112 indicating that no more data can be written to the IN FIFO The USB function control unit transmits one packet data Note 1 in the next IN token Note 1 In continuous transfer enable read the description by substituting the underlined part with buffer data As for one buffer data when SET_IN_ BUF_RDY bit is set to 1 after data less than the value set in the BUF_SIZ are written to IN FIFO one buffer data transmit is pre pared Also the BUF_SIZ has to be equal to an integral multiple of the EPxIMP Rev 2 00 Oct 16 2006 page 201 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 USB function While the AUTO_SET is enabled AUTO_SET bit is 1 when one data packet whose is equal to the maximum packet size EPxIMP set value has been written to IN FIFO in continuous transmit dis able or when data e
203. ansmission i 4 Start transmission parity error Tc Transfer clock Transmit enable bit TE Data is set in UARTI transmit buffer register Transmit buffer empty flag TI Transferred from UARTI transmit buffer register to UARTi transmit register Parity Stop i TxDi Note 2 RxDi Note 2 Since a parity error occurred the L level returns from SIM card i ine level i Nea i j Detects the level H N Detects the level ae interrupt Transmit buffer using an interrupt empty flag es routine TEXPT Transmit interrupt request bit IR o xX Pa Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Tc 16 n 1 fi or 16 n 1 fEXT fi frequency of BRGi count source f1 f8 32 fexT frequency of BRGi count source external clock n value set to BRGi The above timing applies to the following settings e Parity is enabled One stop bit e Transmit interrupt cause select bit 1 Note 1 The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing Note 2 TxDi and RxDi are connected in the manner of wired OR as shown in the connection diagram Therefore the signal levels of TxDi and RxDi should be the same but the output signals are shown separately for ease of understanding Also the signal level resulting from connecting TxDi and RxDi is sh
204. ared The USB function control unit transmits this data to the IN token until next transmit data are updated Transmit Operation Normal Interrupt Transfer The endpoint x IN transmit operation in the normal interrupt transfer is same as the bulk transfer Refer to Transmit Operation of 2 Bulk Transfer Endpoints 1 to 4 Transmit Rev 2 00 Oct 16 2006 page 204 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function Rate Feedback Interrupt Transfer In real application rate feedback interrupt transfer always has data to be transmitted to the host Therefore the device does not repond with NAK to the IN token from the host in this transfer On receiving IN token from the host CPU the IN FIFO data are always transmitted in the current data sequence bit regardless of the IN BUF_STSO and IN_BUF_STS1 values Except this point the transmit operation is the same as the normal interrupt transfer When IN token is received from the host CPU while SEND_STALL bit being set to 1 STALL response is automatically returned On receiving IN token from the host CPU the IN FIFO data are transmitted in the current data sequence bit On completing one data transmit on receiving ACK from the host CPU the IN FIFO status is updated data toggle sequence bit is toggled DATAO DATA1 or DATA1 gt DATA0O and the endpoint x IN interrupt request occurs At this time unlike the normal interrupt transfer the IN FIFO data are not delet
205. arted transfer clock again to start transmitting immediately after confirming CTS L a Transfer clock IL 1 Transmission enabled 4 Confirme stop bit i 2 Confirme CTS 5 Start transmission 3 Start transmission H H Transmit enable bit TE Data is set in UARTi transmit buffer register Transmit buffer 1 empty flag TI Transferred from UARTI transmit buffer register to UARTi transmit register CTSi Parity Stop Stopped pulsing because transfer enable bit 0 bit i TxDi Transmit register empty flag TXEPT Transmit interrupt request o a eS S bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc 16 n 1 fi or 16 n 1 fEXT e Parity is enabled fi frequency of BRGi count source f1 fa f32 One stop bit fEXT frequency of BRGi count source external clock e CTS function is selected n value set to BRGi e Transmit interrupt cause select bit 1 Figure 2 4 7 Operation timing of transmission in UART mode Rev 2 00 Oct 16 2006 page 65 of 354 lt ENESAS REJ09B0340 0200 an M30245 Group ia UARTi transmit receive mode register i 0 to 3 b0 UARTI transmit receive mode register dococaci UIMR Address 03A816 36816 033816 32816 Serial I O mode select bit b2 b1 bO 1 0 1 Transfer data 8 bits long Internal exte
206. asitic Sa ON resistor diode ON resistor approx 0 6kQ approx 2kQ Wiring resistor 7 I C Approx 3 0pF ANO Lo approx 0 2k0 Analog input voltage Pp AMP l swt Eta l gt l i l ON resistor l Pae approx 5k Q l l l l l l i l l l l l l 1 Sampling I control signal l l ladder type prige i ladder tvpe z P wiring resistors Chopper type ao 2kQ i 10 l amplifier V ON resistor approx 0 2kQ AD successive conversion register Vref Resistor Comparison voltage ladder ON resistor approx 0 6kQ ADT A D conversion interrupt request Comparison reference voltage Vref generator Sampling Comparison Connect to O SW1 conducts only on the ports selected for analog input Control signal SW2 and SW3 are open when A D conversion is not in for Sw2 progress their status varies as shown by the waveforms in Connect to the diagrams on the left Connect to i SW4 conducts only when A D conversion is not in progress Control signal for SW3 Connect to Warning Use only as a standard for designing this data Mass production may cause some changes in device characteristics Figure 2 9 23 Internal equivalent circuit to analog input Rev 2 00 Oct 16 2006 page 237 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2 9 13 Sensor s Output Impedance under A D Conversion reference value To carry out A D conversion properly charging the internal capacit
207. at dose not generate the interrupt request for that register For details see the precautions for interrupts Note 2 This bit can only be reset 0 but cannot be set 1 Port P10 direction register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PD10 03F616 0016 RW ere Port P101 direction register 0 Imput mode l O0 Gurions asan mpat por FOO Functions as an output port O O CKA CKG oo oo Figure 2 14 2 key input interrupt related registers 1 Rev 2 00 Oct16 2006 page 263 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Key Input Interrupt Key input mode register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset KUPM 03F916 0016 Bit Symbol Bit Name Function bi b0 KISO P10 Key input edge select 0 0 0 Falling edge 0 1 Rising edges 1 0 Two edge KIS1 P10 Key input edge select 1 1 1 Reserved 0 Disabled KIEO P100 and P101 Key input enable bit 1 Enabled Disabled P102 and P103 Key input enable bit KIE1 Ymp Enabled Disabled KIE2 P104 and P105 Key input enable bit Enabled Disabled KIE3 P106 and P107 Key input enable bit Enabled Nothing is assigned Write O when writing to these bits The value is 0 if read Pull up control register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PUR2 03FE16 0016 Bitsymbol Btname Function RW 4 PU20 P80 to P83 pull up The correspond
208. at the receive data from the host PC are equal to the buffer size or includes a short packet Pay attention to the following when setting the BUF_NUM BUF_SIZ Not exceed 3072 bytes in OUT FIFO starting location OUT FIFO size Not overlap Endpoint FIFOs each other USB Endpoint x OUT FIFO register b15 b8 b7 bo 67 Symbol Address When reset 0 0 00 EPxOFC x 1 4 02BC 16 02C416 000016 Too a a 7 7 TEE a E 02CC16 02D416 Bit Symbol Bit Name Function Select the starting number for the EPx OUT FIFO BUF_NUM FIFO buffer in units of 64 bytes start number 000000 buffer stating location 0 000001 buffer stating location 64 000010 buffer stating location 128 101111 buffer stating location 3008 last starting number Select the buffer size for the EPx OUT FIFO BUF_SIZ FIFO buffer size in units of 64 bytes 0000 buffer stating location 64 0001 buffer stating location 128 0010 buffer stating location 192 1111 buffer stating location 1024 largest buffer size 0 Disabled DBL_BUF Double buffer mode 1 Enabled Continuous transfer 0 Disabled Note CONTINUE mode 1 Enabled Reserved Must always be 0 Note Valid for bulk transfer type only Figure 2 8 43 USB endpoint x x 1 to 4 OUT FIFO configuration register Rev 2 00 Oct 16 2006 page 187 of 354 7tENESAS REJ09B0340
209. at the same time by SFR snoop function 1st byte DMA transfer J Continued to the next page Figure 3 6 3 Setting routine 2 of DMA transfer from RAM to UART using SFR snooping function Rev 2 00 Oct 16 2006 page 314 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 CRC Snoop Function Applications Continued from the previous page The DMA transfer request from the 2nd byte on is occurred when DMA enable bit 1 and the UART1 is transmit request state gt Transfer of the data to CRC input register by the SFR snoop function DMAO transfer from the 2nd byte on DMA enable bit is set to 0 by underflow of the DMAO transfer counter 4 r Completion of the DMAO transfer and occurrence of the DMAO interrupt request Transfer of the 16 bit calculation result which is stored in CRC data register to UART1 transmit buffer register every 1 byte To subsequently start the DMAO transfer Disable the DMAO once and set the DMAO related registers once again Figure 3 6 4 Setting routine 3 of DMA transfer from RAM to UART using SFR snooping function Rev 2 00 Oct 16 2006 page 315 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 USB Applications 3 7 Transfer from USB FIFO to Serial Sound Interface Overview The M30245 group by use of DMAC transfers data from
210. ater than 1 256 X 1 16 in the division rate of UARTi clock Set the bit rate generator to O turn the source clock signal to timer output and set an optional value in the timer Let F be the clock signal within the SIM card and D be the bit rate adjustment factor then the formula for the UART clock signal becomes as follows Figure 2 4 19 shows an example of connection e In the case of setting a value equal to or less than 1 256 X 1 16 in the division rate of UARTi clock UARTI clock signal within microprocessor UART clock within SIM card 1 1 1 fi x x fi x Bit rate generator 1 16 Timer Aj counter 1 1 x flip flop x FD Let XIN 16 MHz timer Aj counter 1 F 372 and D 1 then the value to be set in the bit rate generator becomes 1 1 1 4 4 6 x x 16 Xp ak 5 X aan Bit rate generator 1 16 Tei 2 372 1 Bit rate generator 92 Table 2 4 8 shows an example of setting in the UARTi bit rate generator In the case of setting a value equal to or greater than 1 256 X 1 16 in the division rate of UARTi clock UARTIi clock signal within microprocessor UART clock within SIM card 1 1 1 fix x flip flop X 3 Timer Ak counter 1 Bit rate generator 1 16 1 1 f1x x flip flop x Timer Ajcounterr 1 P7 OP X FD Let XIN 16 MHz timer Aj counter 3 bit rate generator 0 F 1860 and D 1 then the value to be set in the timer Ak counter becomes 1 1 1 1 1 1 6 x X X X 16
211. ath is designed to work with the data format of the USB audio class device specifications The transmitter receiver must change channels on every WS transition The number of SCKs within a WS high low period is set as the channel width The channel width can be selected from among 16 bits 24 bits and 32 bits using channel width select bits 0 and 1 bits 4 and 5 of the SSIIMRO register If the number of SCKs exceeds the channel width the receiver will stop receiving data until the next WS edge and the transmitter continues to transmit 0 However if the number of the SCKs falls short of the channel data width both the transmitter and the receiver will immediately switch to transmit and receive respectively of the next channel data item Select function In the Serial Sound Interface function the following features can be selected 1 Rate feedback function When used with the USB interface the Serial Sound Interface can count the number of WSs or SCKs per USB frame The count value is loaded into the serial sound interface xRF register x 0 or 1 on the falling edge of each SOF pulse generated by the USB core The SOF pulse is a frame delimiter used in USB communication The value read from the register is the count from the immediately preceding USB frame 2 Channel width selection function Channel widths of 32 24 and 16 bits can be used to transmit and receive data The width can be selected by the channel width select bits 0 an
212. be acicarascavensneastecasieceuecGuesaasode saes tun sndhSveusaavaseseansnanenitedeasaatae 240 2 10 1 Overview of the DMAC usage cccsseceeeeeeseeeeeeseeeeeecaesesaeeeeesaeseseaeeeneeeeesaeesaeeeeeseaeseseeeeeeseeseseeeeeees 240 2 10 2 Operation of DMAC one shot transfer mode ccccseecceeeeseeeeeeeeseeeeeeeeeseeseeeeseaeseeeesaaeeeenenees 245 2 10 3 Operation of DMAC repeated transfer mode ccceeeeeeeseeseeeeeeseeeesneeeeneeeeeesnaesnseeeeeseeeseneeeeeneas 247 2 11 CRC Calculation Circuit sisssiissiccssiccsssssnsccnscnsteccteccetavdssvsasssvedecedssneanndastesccsseceeccuweceue 249 2E OVV OW aaen a SR Aa ETA A E A AAAA E E AA E EA 249 2 11 2 Operation of CRC Calculation Circuit cccccseeeeseeeeeeeneeeeeeeeeeseeeeeeeeeesaeeeeeeeeseseaesenseeeessesenseeeeeeas 251 2 11 3 SFR Access Snoop Function sssssssssnseunnsuunennnnnnnnnnnnnnnnnnnnnnenunnnannnnunnnnunnnnunnnnnnnnnnn annen nnne nnnnn ennenen nnna 252 2 12 Watchdog TIME ssccscavacacewcctewes catuaravavdnseaaseadudeaudnaduncndecuuddeevansudepredesnevanauaaaanauaeeceautncss 253 221251 OVEGRVIOW E E E Seta ccadecansiae E E A seucdauasueusdacatedseaavaddeacabs taddueesd dadteeaveedae 253 2 12 2 Operation of Watchdog Timer Watchdog timer interrupt ccsccssseeeeeeeeeeteeeeseeeeeseeeseeeeeeenees 256 2 13 Address Match Interrupt Usage eccceeeeeeeeeeeeeeeeeeneneneneeeeeseeeseneeeeeeseeeeeeeeeneees 258 2 13 1 Overview of the address match in
213. ble bit of DMAi control register is set to 1 enable Any oneendpoint x x 1 to 4 IN FIFO write request select bit in USB DMAx x 0 to 3 request register is set to 1 The other bits are set to 0 valid setting Event The IN FIFO state of the endpoint x IN which is set in USB DMAx x 0 to 3 request register has been updated and the IN_BUF_STS1 and IN_BUF_STS0 flags are set to 002 at the time of single buffer and 012 at the time of double buffer When there are the space of one or more packets in the IN FIFO At this time when one packet transfer is completed the endpoint x IN interrupt request simultaneously occurs Factor 2 Conditions DMA enable bit of DMAi control register is set to 1 enable The IN _BUF_STS1 and IN_BUF_STSO0 flags of endpoint x IN which is set in USB DMAx x 0 to 3 request register are set to O02 or 012 When there are the space of one or more packets in the IN FIFO There is no selection of USB DMAx x 0 to 3 request register 0016 Event Any one endpoint x x 1 to 4 IN FIFO write request select bit in USB DMAx x 0 to 3 request register is set to 1 The other bits are set to O valid setting Factor 3 Conditions DMA enable bit of DMAi control register is set to 1 enable The IN_BUF_STS1 and IN_BUF_STS0 flags of endpoint x IN which is set in USB DMAx x 0 to 3 request register are set to 002 or 012 When there are the
214. cally is returned without receiving the data At this time the FORCE_STALL flag is set to 1 and when error interrupt has been enabled by USB function inter rupt enable register an error interrupt request occurs INTST8 is set to 1 Rev 2 00 Oct 16 2006 page 188 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function When an error is detected in bulk OUT transfer a response is not returned without ACK and NAK responses Error checks such as CRC check and bit justification conforming to USB2 0 specifica tion are automatically performed So the error does not have to be controlled by software Fetch of Receive Data On receiving one packet data Note 2 the received packet data Note 2 from OUT FIFO is read Fetch one packet data Note 2 in the following procedure 1 Confirm that there are receive data in the OUT FIFO by the statuses of the OUT_BUF_STS1 and OUT_BUF_STS0 flags 2 Determine the data byte count to be read from the OUT FIFO by reading USB endpoint x x 1 to 4 OUT write count register 3 Read the data byte count determined in the above 2 from the OUT FIFO Every time that 1 2 byte data are read from the OUT FIFO the internal write pointer is automati cally decremented by one two Content of the internal write pointer cannot be read 4 Set CLR_OUT_BUF_RDY bit to 1 to complete one receive packet data fetch Note 2 At this time the OUT FIFO status OUT_BUF_STS1 and OUT_BUF_STS0 flags are
215. ce address is incremented and the content of the transfer counter is down counted The transferred data are automatically writ ten in CRC input register by the SFR access snoop function 7 As a result of repetition of the above 6 when the DMAO transfer counter underflow DMA enable bit is set to 0 to complete the DMAO transfer Simultaneously the DMAO interrupt request occurs When the DMAO interrupt request is detected CRC data register 2 bytes is read it is transferred to the UART1 transmit buffer sequentially Rev 2 00 Oct 16 2006 page 311 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 CRC Snoop Function Applications M30245 0040016 OO5FF16 Source area Contents of 1st byte i transmission data CRC input register Contents of 2nd byte transmission data Contents of 3rd byte transmission data Snoop the address of UART1 transmit buffer register UART1 transmit ok Contents of 512th byte Transmission transmission data buffer register da DMAOQ transfer Figure 3 6 1 Block diagram of DMA transfer from RAM to UART and SFR snooping function Rev 2 00 Oct16 2006 page 312 of 354 7RENESAS REJ09B0340 0200 M30245 Group 3 CRC Snoop Function Applications Initialization of UART1 See 2 3 2 Operation of Serial I O transmission in clock synchronous serial I O mode for detail Enable UART1 transmit ld bo UART1 transmit receive control register 1 1 U1C1 Address 036D1
216. cess these registers in word cycle or byte cycle to the lower byte The configuration of USB x x 0 4 IN FIFO data register is shown in Figure 2 8 12 USB Endpoint x IN FIFO Data register b15 b8 b7 bO b7 Symbol Address When reset EPxI x 0 4 02E016 02E416 02E816 N A 02EC16 02F016 Bit Symbol Bit Name Function DATA_15 0 EPO IN FIFO Data Write transmit data to this register Note 1 Data is undefined if this register is read Note 2 Write only to this register with a Word command or a Byte command to the lower 8 bits Do not write a byte of data to the upper 8 bits b8 b15 Figure 2 8 12 USB x x 0 4 IN FIFO data register Rev 2 00 Oct 16 2006 page 141 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function USB endpoint x x 0 to 4 OUT FIFO data register Endpoints 0 to 4 respectively have their OUT FIFOs When data are received from the host PC read the receive data from these registers Access these registers in word cycle or byte cycle to the lower byte The configuration of USB x x 0 4 OUT FIFO data register is shown in Figure 2 8 13 USB Endpoint x OUT FIFO Data register b15 b8 b7 bo b7 Symbol Address When reset EPxO x 0 4 02E216 02E616 02EA16 N A 02EE16 02F216 Bit Symbol Bit Name Function Read receive data DATA_15 0 EPO OUT FIFO Da
217. ch other The configuration of USB endpoint x x 1 to 4 IN FIFO configuration register is shown in Figure 2 8 48 USB Endpoint x IN FIFO register b15 b8 b7 bo b7 Symbol Address When reset olo EPxIFC x 1 4 02A216 02A816 000016 rT fo ae fy a ita oo ao Pook ot 02AE16 02B416 Bit Symbol Bit Name Function Select the starting number for the EPx IN FIFO BUF_NUM FIFO buffer in units of 64 bytes start number 000000 buffer stating location 0 000001 buffer stating location 64 000010 buffer stating location 128 101111 buffer stating location 3008 last starting number Select the buffer size for the EPx IN FIFO BUF_SIZ FIFO buffer size in units of 64 bytes 0000 buffer stating location 64 0001 buffer stating location 128 0010 buffer stating location 192 1111 buffer stating location 1024 largest buffer size Disabled DBL_BUF Double buffer mode 1 Enabled Continuous transfer 0 Disabled CONTINUE mode 1 Enabled Note Reserved Must always be set to 0 Note Valid for bulk transfer type only Figure 2 8 48 USB endpoint x x 1 to 4 IN FIFO configuration register Rev 2 00 Oct 16 2006 page 200 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function 2 Bulk Transfer Endpoints 1 to 4 Transmit Setting of Transfer Type When endpoints 1 to 4 IN are used for b
218. choose functions from those listed in Table 2 5 4 Operations of the circled items are described below Figure 2 5 17 shows the operation timing and Figures 2 5 18 and 2 5 19 show the set up procedures Table 2 5 4 Choosed functions Transfer clock Internal clock f1 fa f32 SSi port function SSi function disabled source er ae u External clock CLKi pin enable SSi function enabled CLK polarity Output reception data at Clock phase set Without clock delay the rising edge of the transfer clock With clock delay Output reception data at Serial input port set TxDi RxDi selected the falling edge of the master mode transfer clock Contniols receive Disabled STxDi SRxDi selected Enabled slave mode Operation 1 An SSi port is input L level which outputs from the transmitter side IC port 2 Writing dummy data to the UARTi transmit buffer register setting the receive enable bit to 1 and the transmit enable bit to 1 makes the data receivable status ready 3 In synchronization with the first rising edge of the transfer clock the input signal to the SRxDi pin is stored in the highest bit of the UARTi receive register Then data is taken in by shifting right the content of the UARTi reception data in synchronization with the rising edges of the transfer clock 4 When 1 byte data lines up in the UARTIi receive register the content of the UARTi receive register is transm
219. cifications of M30245 M30245 Group 2 Serial Interface Special Function 2 5 Serial Interface Special Function 2 5 1 Overview Serial interface special function can control communications on the serial bus using SSi input pins The following is an overview of the serial interface special function 1 Transmission reception format 8 bit data 2 Transfer rate If the internal clock is selected as the transfer clock the divide by 2 frequency resulting from the bit rate generator division becomes the transfer rate The bit rate generator count source can be se lected from the following f1 f8 and f32 Clocks f1 fg and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Furthermore if an external clock is selected as the transfer clock the clock frequency input to the CLK pin becomes the transfer rate 3 Error detection Fault error can be detected in the master mode When an L signal is input to an SSi pin in the multiple master system it is judged there is another master existed and the TxDi RxDi and CLKi pins all become high impedance Moreover the fault error interrupt request bit becomes 1 and a fault error interrupt is generated 4 How to deal with an error When the fault error flag is set to 0 output is restored to the clock output and data output pins In the master mode if an SSi input pin is H level 0 can be written for the fault error flag When an SSi input pin is L
220. configuration notification processing routine of GET CONFIGURATION request is shown in Figure 2 8 38 and Figure 2 8 39 Describe these processing to endpoint 0 interrupt processing 1st byte pe 8th byte bmRequestType bRequest wValue windex wlength 00000000B SET_ADDRESS Device address code 0516 000016 000016 Lower Higher Figure 2 8 35 SET_ADDRESS Request Rev 2 00 Oct 16 2006 page 177 of 354 RENESAS REJ09B0340 0200 M30245 Group Receiving of endpoint 0 setup packet a Confirming of receive data b15 b8 bz bo b7 USB endpoint 0 control and status register 0 EPOCS Address 029816 OUT_BUF_RDY flag Note 1 0 Reading data packet is complete 1 Data packet reception is compete SETUP flag 0 Data packet reception 1 SETUP packet reception Note 1 There is no receive data in FIFO 0 when this bit is set to O Reading of receive data b15 b8 bz bo br USB endpoint 0 OUT FIFO data register EPOO Address 02E216 ______ The data equal to receive byte count are read setup packet is 8 byte Store the receive data in user definition RAM 3 bRequest 0516 p To processing routine of other standard requests 2 USB function p gt TO processing of request invalid x espe Getting of new address continued on next page z Getting of address de
221. control unit Refer to the next page 2 Enable other functions as circumstances demand Returning by Remote Wakeup When clock operation is started by the remote wakeup interrupt other than the USB resume inter rupt during the USB suspend state transmit the resume signal to the host CPU as follows 1 Return the USB function control unit Refer to the next page 2 Set USB remote wakeup bit to 1 and transmit the resume signal to the host CPU Retain 1 for min 1ms to max 15ms 3 Set USB remote wakeup bit to O and complete the resume signal transmission The USB sus pend status flag is automatically cleared at this time Also when returning from the stop mode the main clock dividing ratio has been set to 8 dividing mode for which resetting is required Wait for enough oscillation stabilization time before resetting main clock division select bit of system clock control register 0 address 000616 For details refer to Clock Generating Circuit of Chapter 1 Hardware Rev 2 00 Oct 16 2006 page 164 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function Returning Routine of USB Function Control Unit To return from the USB suspend state to the previous state perform return control of the USB function control unit as follows Further clearing the bit of protect register address 000A16 is required for changes in frequency synthesizer control register address 03DC16 1 Set frequency
222. control unit is in the initial state or has received a reset signal from the host CPU this register value is the default address 000016 When the USB block has been disabled bit 7 of USB control register is set to 0 this register value is the address 000016 After receiving the SET_ADDRESS request from the host CPU rewrite USB address register and update the address For rewriting USB address register follow the procedure below e When the device is in the default state USB address register value is O00016 1 When USB address register has received the SET_ADDRESS request from the host CPU store the new address data in the USB address register 2 When the status phase of the SET_ADDRESS request is completed USB address register is automatically rewritten into the address written in above mentioned 1 When the status phase is not normally completed USB address register is not rewritten e When the device is in the address state USB address register value is other than 000016 1 When USB address register has received the SET_ADDRESS request from the host CPU con firm that the status phase of SET ADDRESS request completes 2 Store the new address data in USB address register USB address register is rewritten into the new address data The configuration of USB address register is shown in Figure 2 8 31 Rev 2 00 Oct 16 2006 page 169 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function U
223. ction USB Endpoint x OUT Control and Status register b8 Oy ea b7 symbol Address 02B616 02BE16 o o Jade ls EPxOCS x 1 4 gacet6 02CEt6 When reset 000016 Bit Symbol Bit Name Function OUTxCSRO OUT _BUF_STSO flag anope ols indicate the EPx OUT buffer status 0 0 No data set in the OUT buffer OUTxCSR1 OUT_BUF_STS1 flag 9 1 Single buffer mode N A Double buffer mode N A 1 0 Single buffer mode N A Double buffer mode one data set in the OUT buffer 1 Single buffer mode one data set in the OUT buffer Double buffer mode two data sets in the OUT buffer VER RUN fl OUTXESRZ 0 UN fag No over run detected Over run detected OUTxCSR3 FORCE_STALL flag No packet size larger than MAXP violation detected Packet size larger than MAXP violation detected OUTxCSR4 DATA_ERR flag No data error detected Data error detected LR T BUF RD No action OUTxCSR5_ CLR_OUT_BUF_ Data set unloaded from the OUT buffer updates status flags No action OUTxCSR6 CLR_OVER_RUN Clears OVER_RUN flag No action OUTxCSR7 CLR_FORCE_STALL 1 Clears FORCE_STALL flag OUTxCSR8 CLR_DATA_ERR No action Clears DATA_ERR flag No action OUTxCSR9 TOGGLE_INIT Initialize the next data PID as a DATAO for reception No action OUTxCSR10 FLUSH Flush out one data set Select non isochronous endpoin
224. curs gt e Instructions other than those listed above Figure 2 13 1 Unexecuted instructions and corresponding stacked addresses Figure 2 13 1 shows unexecuted instructions and corresponding the stacked addresses 4 How to determine an address match interrupt Address match interrupts can be set at two different locations However both location will have the same vector address Therefore it is necessary to determine which interrupt has occurred address match interrupt 0 or address match interrupt 1 Using the content of the stack etc determine which interrupt has occurred according to the first part of the address match interrupt routine Rev 2 00 Oct 16 2006 page 258 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Address Match Interrupt 5 Registers related to the address match interrupt Figure 2 13 2 shows the memory map of address match interrupt related registers and Figure 2 13 3 shows address match interrupt related registers 000916 Address match interrupt enable register AIER X 001016 001116 Address match interrupt register 0 RMADO 001216 001316 001416 001516 Address match interrupt register 1 RMAD1 001616 Figure 2 13 2 Memory map of address match interrupt related registers Address match interrupt enable register e a a a a ay Symbol Address When reset AIER 000916 XXXXXX002 Address match interrupt 0 0 Interrupt disaled enable bit 1 enabled Address match i
225. d 1 in serial sound interface mode register 0 REJ09B0340 0200 M30245 Group 2 Serial sound interface 3 LSB MSB first select function This function is to choose whether to transmit receive data from bit 1 or bit 7 This is valid when the transfer data length is 8 bits long Choose either of the following e LSB first Data is transmitted received from bit 0 e MSB first Data is transmitted received from bit 7 4 Multiple receive format select function If the number of SCKs in a WS high low period is less than the channel width the data can be placed either MSB or LSB justified 5 SCK polarity select function This function selects whether transmit and receive data are synchronized to the rising or falling edge of WS This is selected by the SCK polarity bit in the serial sound interface x mode register 1 6 WS polarity select function This function is to transmit receive data synchronized to the rising edge or the falling edge of WS This is selected by the WS polarity select bit in the Serial Sound Interface x mode register 1 7 WS delay select function Either of the following modes may be selected for the channel change timing e Normal WS mode WS transitions one SCK period before a channel change The channel changes one SCK period after WS transitions e Delayed WS mode WS transitions concurrently with a channel change Input to the Serial Sound Interface function and the corresponding direction register When inputtin
226. d not be set Figure 2 10 3 DMAC related registers 2 Rev 2 00 Oct 16 2006 page 243 of 354 7tENESAS REJ09B0340 0200 2 DMAC M30245 Group DMAi control register b7 b6 b5 b4 b3 b2 bi b0 Symbol DMiCON i 0 3 Address 002C16 003C16 018C16 019C16 2 DMAC When reset 00000X002 Bit Symbol Bit Name Function DMBIT Transfer unit select bit 16 bits 8 bits DMASL Repeat transfer mode select bit Single transfer Repeat transfer DMAS DMA request bit Note 1 DMA not requested DMA requested DMAE DMA enable bit Disabled Enabled DSD Source address direction select bit Note 3 Fixed Forward DAD Destination address direction select bit Note 3 Fixed Forward _ Nothing is assigned Write O when writing to these bits The value is 0 when read Note 1 DMA request can be cleared by resetting the bit Note 2 This bit can only be set to 0 Note 3 Source address direction select bit and destination address direction select bit cannot be set to 1 simultaneously DMAi source pointer i 0 3 b23 b19 b16 b15 3 l l bob Symbol SARO SAR1 SAR2 DMAi destination pointer i 0 3 b23 b19 3 b16 b15 b7 b b0b7 SAR3 Address 002216 to 002016 003216 to 003016 018216 to 018016 019216 to 019016 When reset Indeterminat
227. dent such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input
228. derflow Timer AO counter n reload register content 3 Timer A1 starl count 4 Timer At stop count oO i 3 Q is lt E oO E H Set to 1 by software Timer AO count Pais Set to 1 by software Timer A1 count q A i start flag un PWM pulse output o a from TAlouT pin Timer AO interrupt 1 request bit Q LI L a Cleared to 0 wD interrupt aissi is accepted or cleared by software Timer A1 interrupt 1 4 r request bit To i Cleared to 0 when interrupt request is accepted or cleared by software ims A Figure 3 2 1 Operation timing of variable period variable duty PWM output Used for timer mode Set to period Timer AO interrupt request bit Timer A1 interrupt request bit Used for one shot timer mode Set to H width Figure 3 2 2 Connection diagram of variable period variable duty PWM output Rev 2 00 Oct 16 2006 page 300 of 354 7RENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications Setting timer AO a Selecting timer mode and functions of of ao on 0 Te meee anes esas one Selection of timer mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Gate function select bit b4 b3 00 Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit b7 b
229. ding port is pulled high with a pull up resistor PU21 P84 to P87 pull up 0 Not pulled high Except P85 1 Pulled high P90 to P93 pull up PU24 P100 to P103 pull up The corresponding port is pulled high with a pull up resistor PU25 P104 to P107 pull up 0 Not pulled high 1 Pulled high Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out tobe 0 Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be 0 Figure 2 17 5 Programmable I O ports related registers 4 Rev 2 00 Oct16 2006 page 291 of 354 RENESAS REJ09B0340 0200 THIS PAGE IS BLANK FOR REASONS OF LAYOUT Chapter 3 Examples of Peripheral Functions Applications M30245 Group 3 Applications This chapter presents applications in which peripheral functions built in the M30245 are used They are shown here as examples In practical use make suitable changes and perform sufficient evaluation For basic use see Chapter 2 Peripheral Functions Usage Rev 2 00 Oct 16 2006 page 294 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 Timer A Applications 3 1 Long Period Timers Overview In this process Timer AO and Timer A1 are connected to make a 16 bit timer with a 16 bit prescaler Figure 3 1 1 shows the operation timing Figure 3 1 2 shows the connection dia gram and Figures 3 1 3 and 3 1 4 show the set up procedure Use the following peripheral
230. e 0 when writing to these bits The value is 0 when read DSR Software DMA Software trigger is always enabled request bit Write 1 to trigger DSR bit Note 1 Software is always enabled Note 2 SSI Serial sound interface Note 3 This value should not be set Figure 2 10 2 DMAC related registers 1 Rev 2 00 Oct 16 2006 page 242 of 354 RENESAS REJ09B0340 0200 2 DMAC M30245 Group DMA2 request cause select register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address DM2SL 03B016 When reset 0016 Bit Symbol Bit Name Function Note 2 DSELO DMA request cause select bits cecDCC OCC OOCC OOOO Og 0000000000000000 x 0000 0000 0000 x 00 00 00 00 00 00 4 0 0 0 0 0 0 0 0 2 0 20 0 08 DMA Disabled INT2 falling edge INT2 two edges USB2 Timer AO Timer A1 Timer A2 Timer A3 Timer A4 UARTO receive ACK SSIO receive UART1 receive ACK SSI1 receive UART2 receive ACK UARTS receive ACK UARTO transmit NACK SSIO transmit UART1 transmit NACK SSI1 transmit UART2 transmit NACK UARTS transmit NACK A D DMAO DMA1 Disabled Note 3 DMA3 Disabled Note 3 Disabled Note 3 x Disabled Note 3 Nothing is assigned Write O when writing to these bits The value is O when read DSR Software DMA Software
231. e Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to 0 XN Va Setting UARTi transmit receive control register 0 i 0 to 3 er 1 E UARTi transmit receive control register 0 lolo l o UiCO Address 03AC16 36C16 033C16 32C 16 BRG count source select bit b1 b0 00 f1 is selected 01 fs is selected 1 0 f32 is selected 1 1 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed _ CTS RTS disable bit 1 CTS RTS function disabled Data output select bit Note 2 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to 0 Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output Setting UARTi special mode register 3 i 0 to 3 b7 bo UARTI special mode register 3 o o UISMR3 Address 03A516 36516 033516 32516 L SS po
232. e Count Count source period b7 b6 i source f XIN 16MHz f XcIN 32 768kHz Cost 62 5ns 500ns 2us 976 56us Setting counter value b15 b8 br po B b0 Timer AO register Address 038716 038616 TAO Setting timer A1 Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit 1 Pulse is output External trigger select bit Invalid when choosing timer s overflow as trigger Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit Count Count source period b7 b6 Source f XIN 16MHz_ f XcIN 32 768kHz 00 _ _ gt 62 5ns 500ns 2us 976 56us Continued to the next page Figure 3 2 3 Set up procedure of variable period variable duty PWM output 1 Rev 2 00 Oct 16 2006 page 301 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications Continued from the previous page Setting trigger select register b7 b0 TT TLL Trigger select register Address 038316 LITT TED TRGSR Timer A1 event trigger select bit b1 b0 1 0 TAO overflow is selected Setting one shot timer s time b15 b8 br Dobi b0 Timer A1 register Address 038916 038816 Setting count start flag bo fl A Xx een Timer AO count start flag 1 Starts counting Timer A1 count star
233. e Indeterminate Indeterminate Indeterminate Function Transfer address specification RW Source pointer stores the source address 0000016 to FFFFF16 Nothing is assigned Write 0 when writing to these bits The value is 0 when read Symbol DARO DAR1 DAR2 DMAi transfer counter i 0 3 b15 b8 b7 b0b7 DAR3 Address 002616 to 002416 003616 to 003416 018616 to 018416 019616 to 019416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Transfer address specification Ri W Destination pointer stores the destination address 0000016 to FFFFF16 Nothing is assigned Write 0 when writing to these bits The value is 0 when read oio Address 002916 to 002816 003916 to 003816 018916 to 018816 019816 to 019816 Symbol TCRO TCR1 TCR2 TCR3 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Transfer count specification Transfer counter Set a value one less than the transfer count 0000016 to FFFFF16 Figure 2 10 4 DMAC related registers 3 Rev 2 00 Oct 16 2006 page 244 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 DMAC 2 10 2 Operation of DMAC one shot transfer mode In one shot transfer mode choose functions from the items shown in Table 2 10 1 Operations of the circled items are d
234. e Valid when bulk tranfer y Continued to the next page Figure 2 8 19 Initialization procedure of endpoint 1 Rev 2 00 Oct16 2006 page 147 of 354 ENESAS REJ09B0340 0200 X M30245 Group Continued from the previous page Initialization of endpoint x x 1 to 4 Bulk tranfer Interrupt transfer Isochronous transfer b15 b8 bo b7 b7 0 USB endpoint x IN MAXP register b15 b7 gt EPxIMP x 1 to 4 Address 02A016 02A616 02AC16 02B216 Set the maximum packet size 0 USB endpoint x OUT MAXP register 7 EPxOMP x 1 to 4 Address 02B816 02C016 02C816 02D016 Set the maximum packet size USB endpoint enable register Address 028E16 USBEPEN Endpoint 1 OUT FIFO enable bit 0 Disabled 1 Enabled Endpoint 1 IN FIFO enable bit 0 Disabled 1 Enabled Endpoint 2 OUT FIFO enable bit 0 Disabled 1 Enabled Endpoint 2 IN FIFO enable bit 0 Disabled 1 Enabled Endpoint 3 OUT FIFO enable bit 0 Disabled 1 Enabled Endpoint 3 IN FIFO enable bit 0 Disabled 1 Enabled Endpoint 4 OUT FIFO enable bit 0 Disabled 1 Enabled Endpoint 4 IN FIFO enable bit 0 Disabled 1 Enabled USB Endpoint x IN control and status register EPxICS x 1 4 Address 029E16 02A416 02AA16
235. e 1 First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Figure 2 2 16 Operation timing of two phase pulse signal process in event counter mode normal mode selected Rev 2 00 Oct 16 2006 page 22 of 354 REJ09B0340 0200 RENESAS M30245 Group Selecting event counter mode and functions Timer Ai mode register i 2 3 Address 039816 039916 TAIMR i 2 3 Selection of event counter mode 0 Must always be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing Count operation type select bit Note 1 1 Free run type Two phase pulse signal processing operation select bit 0 Normal processing operation Note 1 First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Two phase pulse signal processing select bit b7 Up down flag Address 038416 UDF Timer A2 two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled Timer A3 two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled a Setting trigger select register b7 bo Trigger select register
236. e IN FIFO size has to be equal to an integral multiple of the maximum packet size AUTO_SET Function With AUTO_SET bit of EPxICS being set to 1 the AUTO_SET function is enabled When transmit data of the buffer size specified in the BUF_SIZ is written to the IN FIFO in AUTO_SET enable state the IN BUF_STSO and IN_BUF_STS1 flags are updated without SET_IN_BUF_RDY bit being set to 1 However when a short packet data whose size is smaller than the EPxIMP value in continuous transfer disable or than the BUF_SIZ value in continuous transfer enable has been written the IN_BUF_STS1 IN_BUF_STS0 flags are not automatically updated In these cases the completion of data transmit ready is indicated by setting SET_IN_BUF_RDY bit to 1 The AUTO_SET function is useable both in continuous transmit mode and in continuous transmit mode disable of endpoints 1 to 4 IN Not available with endpoint 0 Rev 2 00 Oct 16 2006 page 193 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 1 Related Registers USB ISO control register This register controls isochronous transfer of endpoints 1 to 4 This register setting is valid for all the isochronous transfer IN endpoints that are used simultaneously AUTO_FLUSH bit This bit controls transmit packet data destruction in isochronous transfer This bit can be used only when setting 1 to both ISO_UPDATE bit and ISO bit The bit is valid only for the IN endpoints 1 to 4 in isochr
237. e a e a a a a aan Aea aa aa a ea ea aae Saa aana 281 2 16 4 Precautions in Power Control ccssecceceeeeeeeeeeseeeeeeceeseseeeeeesaeeeaneeeenseeeesseaesnseeeesseaeseseeeeeseeeseaaeeeenes 282 2 17 Programmable I O Ports Usage i nsccisiiiccesetsssnincencsdecudatesntansadecuieceassusuawoudeecvanducnseses 284 2 17 1 Overview of the programmable I O ports USAGE ssssssssunsennnennnnnnnnnunnenunnnnnnnnnnnnnnnnnnnnnnnnn nunne ennen 284 Chapter 3 Examples of Peripheral Functions ADDINCATIONS saci eetecirectecesinctin tities 298 3 1 Long Period Timers viv insinesticitintarclmsbsntilahienbswinntinusbtenlgihietiabiutedatiotubateluinietdiuabanbbats 295 3 2 Variable Period Variable Duty PWM Output cccccsssseeeeeeeeeeseseeeeeeeeeeeeeeeeeeeeees 299 3 3 B zz QU PU isai ninian enman iei atanena in aaeeeo eoe aa eaaa eera aana haehaa aiheen ada lanei eni 303 3 4 Solution for External Interrupt Pins Shortage ccccssssseeeeeeeeeeseseeeeeeeeeeeeeeeeeeeeeees 305 3 5 Memory to Memory DMA Transfer 0ccceseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeees 307 3 7 Buzzer OULD UN wiesncndsetiicestacucadratevasanadadacsiadeanauauanducaxasenadeuiedvavansenesscacsvadousuduneeauanuuaaseiies 311 3 6 CRC Calculation SFR Access Snoop Function in Clock Synchronous Serial Data Transmit viii cvccciiessesivasncanienewecveivnansiseedsiveewueasdwunrssusonseuwaveadsbawasieeeeneeeenss 311 3 7 Transfer from USB FIFO to Serial Sound In
238. e are no packet data in the IN FIFO until the next SOF packet is detected Also for flushing the IN FIFO in isochronous IN transfer by using software the AUTO FLUSH func tion is used While ISO_UPDATE bit 1 AUTO_FLUSH bit 1 and ISO bit INxCSR8 1 the USB function control unit at the time of detecting a SOF packet from the host PC or on the artificial SOF auto matically flushes old data packet inside the IN FIFO if both the IN BUF_STS1 and the IN_BUF_STSO flags are 1 IN FIFO full state In isochronous transfer for double buffer use the AUTO FLUSH function Rev 2 00 Oct 16 2006 page 203 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 4 Interrupt Transfer Endpoints 1 to 4 Transmit Setting of Transfer Type Interrupt transfer setting has two kinds including the normal interrupt transfer and the rate feedback interrupt transfer When endpoints 1 to 4 IN are used for the normal interrupt transfer ISO bit and INTPT bit of USB endpoint x IN control and status register are respectively to 0 When the isochronous device has the rate feedback function and endpoints 1 to 4 IN are used for rate feedback interrupt transfer not only ISO bit and INTPT bit of USB endpoint x IN control and status register are respectively set to 0 and to 1 but also double buffer mode enable bit of USB endpoint x IN FIFO configuration register is set to O so that single buffer is enabled Also fo
239. e bit to g Read the lower order byte of the UARTIi receive buffer register e When all error overrun framing and parity are removed the flag is cleared M30245 Group 2 UART 4 How to deal with an error When receiving data read an error flag and reception data simultaneously to determine which error has occurred If the data read is erroneous initialize the error flag and the UARTIi receive buffer register then receive the data again To initialize the UARTi receive buffer register 1 Set the receive enable bit to 0 disable reception 2 Set the receive enable bit to 1 again enable reception To transmit data again due to an error on the reception side set the UARTi transmit buffer register again then transmit the data again To set the UARTIi transmit buffer register again 1 Set the serial I O mode select bits to 0002 invalidate serial I O 2 Set the serial I O mode select bits again 3 Set the transmit enable bit to 1 enable transmission then set transmission data in the UARTi transmit buffer register 5 Functions selection In operating UART the following functions can be used a CTS RTS function CTS function is a function in which an external IC can start transmission reception by means of inputting an L level to the CTS pin The CTS pin input level is detected when transmission reception starts so if the level is gone to H while transmission recepti
240. e count source Reset the prescaler for generating fc32 by Clock prescaler reset flag Address 0381 16 1 Prescaler is reset When read the value is O P Setting count start flag b7 b0 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Count start flag Address 038016 Start count Figure 2 2 7 Set up procedure of timer mode Rev 2 00 Oct 16 2006 page 13 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 TimerA 2 2 3 Operation of Timer A timer mode gate function selected In timer mode choose functions from those listed in Table 2 2 2 Operations of the circled items are described below Figure 2 2 8 shows the operation timing and Figure 2 2 9 shows the set up procedure Table 2 2 2 Choosed functions Count source Internal count source fi fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAiiN pin is at L level Performs count only for the period in which the TAIN pin is at H level Operation 1 When the count start flag is set to 1 and the TAiIN pin inputs at H level the counter per forms a down count on the count source 2 When the TAiIN pin inputs at L level the counter holds its value and stops 3 If an underflow occurs
241. e pointer SAR2 DMA2 destination pointer DAR2 DMA2 transfer counter TCR2 DMA2 control register DM2CON 9016 DMAS3 source pointer SAR3 9316 9416 9516 DMA3 destination pointer DAR3 9816 9916 DMAS transfer counter TCR3 DMAS3 control register DM3CON DMA2 cause select register DM2SL DMAS cause select register DM3SL DMAO cause select register DMOSL DMA1 cause select register DM1SL Figure 2 10 1 Memory map of DMAC related registers Rev 2 00 Oct 16 2006 page 241 of 354 REJ09B0340 0200 7tENESAS M30245 Group DMAO request cause select register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address DMOSL 03B816 When reset 0016 Bit Symbol Bit Name Function Note 2 bi 8 t 0O0 0O00 00 0 0002008 4 0 0 0 0 0 0 0 0 2 0 20 0 08 DSELO DMA request cause select bits aot a a steer a a O OO OO OO OO OGOOGO CcCCcCCcC CC OF O OOOD OO O A ei ei nei ei ai a OOOO OOOO 28 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x DMA Disabled INTO falling edge INTO two edges USBO Timer AO Timer A1 Timer A2 Timer A3 Timer A4 UARTO receive ACK SSI0 receive UART1 receive ACK SSI1 receive UART2 receive ACK UART3 receive ACK UARTO transmit NACK SSIO transmit UART1 transmit NACK SSI1 transmit UAR
242. ea E Write BCLK x 2 CS3 external area Write BCLK x 2 4 n m Le m CSO external area BCLK x3 0000016 Internal area reserved CSO external area BCLK x 3 YYYYY16 BCLK x 2 Internal ROM area BCLK x 1 Figure 4 4 3 Relation of processor mode and the wait bit CSiW CSIEW Rev 2 00 Oct 16 2006 page 344 of 354 RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 2 RDY function usage To use the RDY function set a software wait The RDY function operates when the BCLK signal falls with the RDY pin at L the bus does not vary for 1 BCLK and the state at that moment is held The RDY function holds the state of bus for the period in which the RDY pin is at L and releases it when the BCLK signal falls with the RDY pin at H Figure 4 4 4 shows an example of RDY circuit f XIN 10MHz that holds the state of bus for 1 BCLK te ed Ne Ne Ne ee Na ee ee Oe oN 1 RDY accepted 2 RDY cleared The state of data bus and that of address bus are held for the period between 1 and 2 Figure 4 4 4 Example of RDY circuit holding state of bus for 1 BCLK f XIN 10MHz Rev 2 00 Oct 16 2006 page 345 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 4 3 Connectable Memories Connectable memories and their maximum frequencies are given here M30245 group maximum frequency is 16MHz without the wait for Vec 3V 1 Flash memories Read only mode a 3V without wait
243. ect ing that there are transmit packet data at the time of status updating of the IN FIFO operates artifi cially as having no transmit packet data until the next SOF packet is detected On detecting SOF packet one packet of data which has been set to the IN FIFO is transmitted to the IN token from the host CPU Rev 2 00 Oct 16 2006 page 194 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function Artificial SOF enable bit This bit enables the artificial SOF function With this bit being set to 1 when a SOF packet from the host PC has been destroyed due to any cause and no valid SOF packet has been received even after 1ms from the preceding start of the frame the artificial SOF receive is operated And the USB SOF interrupt request also occurs Therefore even if the SOF packet is destroyed due to any cause a new frame can be formed by this function without waiting for the next SOF packet The artificial SOF receive function is operated once after the valid SOF packet is received twice Artificial SOF status flag This flag is the artificial SOF function status flag This flag is valid when the artificial SOF function has been enabled Artificial SOF enable bit is 1 With this flag being set to 1 an artificial SOF receive has occurred by the artificial SOF function This flag is cleared by setting 1 to CLR_ART_SOF bit Artificial SOF status clear bit Artificial SOF status flag is cleared to 0 by se
244. ect bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit Note 1 1 Free run type L Invalid in event counter mode i 0 1 Invalid when not using two phase pulse signal processing i 2 to 4 C Note 1 First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type b7 Setting up down flag 0 0 0 Up down flag Address 038416 UDF Timer AO up down flag 0 Down count Timer A1 up down flag 0 Down count Timer A2 up down flag 0 Down count Timer A3 up down flag 0 Down count Timer A4 up down flag 0 Down count Se When not using the two phase pulse signal processing function set the select bit to 0 NS a Setting one shot start flag and trigger select register b7 One shot start flag Address 038216 Trigger select register Address 038316 ONSF TRGSR Timer AO event trigger select bit Timer A1 event trigger select bit b7 b6 b1 b0 0 0 Input on TAOn is selected Note 2 0 0 Input on TA11 is selected Note 2 bo b7 b0 Timer A2 event trigger select bit b3 b2 0 0 Input on TA2IN is selected Note 2 Timer A3 event trigger select bit b5 b4 0 0 Input on TA3IN is selected Note 2 Timer A4 event trigger select bit Note 2 Set the corresponding port direction register to 0 b7 b6 0 0 Input on
245. ed which is retained until the next packet data are updated When one data transmit has not been unsuccessfully completed an ACK not received from the host CPU the data are re transmitted in the next IN token the same data are transmitted in the same toggle 5 Precautions for Transmit Writing to IN FIFO Be sure to confirm that there is a space in the IN FIFO before writing data to the IN FIFO in prepara tion for packet data to the IN FIFO The IN FIFO state is indicated by the IN BUF_STS1 and the IN_BUF_STS0O flags Based on these flags states determine the count of data packets set in the IN FIFO The IN FIFO status IN_BUF_STS1 and IN_BUF_STS0 flags is updated when transmit data are prepared in the IN FIFO SET_IN_BUF_RDY bit is set to 1 when transmitting of one data to the host CPU is completed or when data inside the IN FIFO have been flushed AUTO_FLUSH bit or FLUSH bit has functioned Table 2 8 4 Status on Endpoint 1 to 4 IN FIFOs Single buffer Double buffer IN FIFO size IN BUF_STS1 IN_BUF_STSO Specify IN FIFO size by the The number of bytes specified BUF_SIZ by the BUF_SIZ x 2 No data No data Space equal to one buffer Space equal to two buffer Invalid Invalid Invalid One data set in the IN FIFO Space equal to one buffer One data set in the IN FIFO Two data set in the IN FIFO No space in the IN FIFO No space in the IN FIFO 1 Bits 6 to 9 of EPxIFC PID Initialization W
246. eee 338 4 3 5 Chip Selects and Address BUS neraman araara aaaea Ea ae aeea a amo aea aa aee a aea anaa Saanaa Phase naene enaena at 339 4 4 Connectable Memories cccwices siveinseicecesecessnsnsssnnssenscesteeddededeseteessiveseedecssecsvenseanseenseteees 340 4 4 1 Operation Frequency and ACCESS TIME c ccscccceeeeeeeeeeeeeeeenenesesnneeeeeeeeesneeeeeeeeeesseaeseneeeesseeseesneeeeeas 340 4 4 2 Connecting LOW Speed Memory sssccccecceesseeneneeeeeesesensneeeeeeeeasneeeeseessasaaeseneeeeeseaeseaseeeeseeeseeaeenenss 343 4 4 3 Connectable Memories cs secceeeeeesseeeeeeeeesecaeeeeeeeeeesaesenaeeeeesaeseseaeeeeseeeeseaeeeaseeeeseaesaseeeeseseesesseeeenes 346 4 5 Releasing an External Bus HOLD input and HLDA outpul c cceccesssseeeeeees 347 4 6 Precautions for External BUS ccccccssssseseesseeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeseeeeeseneeeeoneeseeees 349 Chapter 5 Standard Characteristics essssee 351 5 1 DC Standard Characteristics ccccccsseccsesccesecceeeeeseeeceeeeeeeeeeeeeeseeeeeseaeeeeussenesseneees 352 5 1 1 Port Standard Characteristics oi isiicis cescesiess stvccdeeecdaccd desea vwcvecebccuaeccsnccbadvadveasoateacetdeuedbuanes sacceddenseadedess 352 5 1 2 VCC ICC Characteristics scciicicccccccnc sa wt ec sas ea vane cen scdadcnccnct wnevdemon Suc eunsnucntensdecdensdudecddeecdsos ataeccwnadhstendeus 354 Chapter 1 Hardware See M30245 group datasheet Chapter 2 Peripheral Fu
247. el high drive for the N channel transistor drive capacity of port P7 can be selected Port P7 can be configured to drive an LED by increasing the drive strength of the corre sponding N channel transistor bits Rev 2 00 Oct16 2006 page 284 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Programmable I O Ports 6 I O functions of built in peripheral devices Table 2 17 1 shows relation between ports and I O functions of built in peripheral devices Table 2 17 1 Relation between ports and I O functions of built in peripheral devices P6 I O pins Serial sound interface 1 C and SPI communication pins for UARTO and UART1 P7 Timer AO to A3 I O pins I O pins or 1 C SPI communication pins for UART2 and UARTS LED drive output pins P80 P81 Timer A4 I O pins P82 P83 P84 Input pins for external interrupt P86 P87 Sub clock oscillation circuit I O pins P90 Attach Detach control pin for USB P92 SOF output pin for USB P93 A D trigger input pin P10 A D converter input pins key input interrupt function input pins 7 Examples of working on non used pins Table 2 17 2 contains examples of working on non used pins There are shown here for mere ex amples In practical use make suitable changes and perform sufficient evaluation in compliance with you application a Single chip mode Table 2 17 2 Examples of working on unused pins in single chip mode Pin name Connection Ports PO to P10 excluding P85 Af
248. elected 10 f32 is selected 1 1 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS disable bit 0 CTS RTS function enabled Data output select bit Note 2 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to O Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output J ai Setting UART transmit receive control register 1 i 0 to 3 b7 bo UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 UARTI transmit interrupt cause select bit 0 Transmit buffer empty TI 1 Data logic select bit 0 No reverse Set to 0 in clock synchronous serial I O mode Continued to the next page Rev 2 00 Oct 16 2006 page 47 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O Continued from the previous page Setting UARTi bit rate generator i 0 to 3
249. eload type S Invalid in event counter mode i 0 1 Invalid when not using two phase pulse signal processing i 2 to 4 b7 Setting up down flag ol olo po Up down flag Address 038416 UDF L Timer AO up down fi 0 Down count Timer A1 up down fi 0 Down count Timer A4 up down f Timer A2 up down f 0 Down count Timer A3 up down f 0 Down count 0 Down count N When not using the 2 phase pulse signal processing function set the select bit to 0 b7 Setting one shot start flag and trigger select register bo bo Se b15 b7 Note Set the corresponding port direction register to 0 b7 b6 b1 b0 0 One shot start flag Address 038216 Trigger select register Address 038316 a ONSF TRGSR Timer AO event trigger select bit Timer A1 event trigger select bit 0 0 Input on TAOn is selected Note 0 0 Input on TAIN is selected Note b3 b2 b5 b4 b7 b6 Timer A2 event trigger select bit 0 0 Input on TA2In is selected Note Timer A3 event trigger select bit 0 0 Input on TA3IN is selected Note Timer A4 event trigger select bit 0 0 Input on TA4iN is selected Note Setting divide ratio Timer AO register Address 038716 038616 TAO b8 Timer A1 register Address 038916 038816 TA1 b0 b7 Timer A2 register Address 038B16 038A16 TA2 Timer A3 register Address 038D16 038C16
250. en op frequency is less than 1MHz sample and hold function cannot be selected t Cleared to 0 when interrupt request is accepted or cleared by software Conversion rate per analog input pin is 49 aD cycles for 8 bit resolution and 59 aD cycles for 10 bit resolution Figure 2 9 10 Operation timing of single sweep mode Rev 2 00 Oct 16 2006 page 224 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 A D Converter Selecting Sample and hold b7 b0 oTo 5 1 AD control register 2 Address 03D416 ADCON2 A D conversion method select bit 1 With sample and hold Must always be set to 0 C Setting AD control register 0 and AD control register 1 b0 b7 b0 AD control register 0 AD control register 1 Address 03D716 001 0 ADCON1 Address 03D616 ADCONO Invalid in single sweep mode A D sweep pin select bit Note 1 b1 b0 A 0 0 ANo AN1 2 pins Single sweep mode is selected 0 1 ANo to AN3 4 pins Note 1 10 ANo to ANs 6 pins Trigger select bit 1 1 ANo to AN7 8 pins 0 Software trigger A D operation mode select bit 1 Note 1 A D conversion start flag 0 Must always be 0 in Single sweep mode 0 A D conversion disabled 8 10 bit mode select bit Frequency select bit 0 Note 2 0 8 bit mode 0 faD 3 or fAD 4 is selected 1 10 bit mode 1 fAD or fAD 2 is selected _______________ Frequency select bit 1 Note 2
251. enerator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 ____ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTIi bit rate generator when transmission reception is halted Reception enabled b7 b0 UARTI transmit receive control register 1 D ViCi Address 03AD16 36D16 033D16 32D16 Receive enable bit 1 Reception enabled Note Note Set RXD pin s port direction register to 0 I Start reception Checking completion of data reception bi 50 UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register a Checking error UARTO receive buffer register Address 03AF16 O3AE16 UORB b8 bO b7 bo UART1 receive buffer register Address 036F 16 036E16 U1RB UART2 receive buffer register Address 033F 16 033E16 U2RB UARTS receive buffer register Address 032F 16 032E16 U3RB Received data Invalid in UART mode Overrun error flag 0 No overrun error 1 Overrun error found Framing error flag 0 No framing error 1 Framing error found Parity error flag 0 No parity error 1 Parity error found Error sum flag 0 No error 1 Error found Processing after reading out received data Figure 2 4 12 Set up procedure o
252. er data Parity bit Stop bit Figure 2 4 1 Transmission reception format Table 2 4 1 Transmission data names and functions ST start bit A 1 bit L signal to be added immediately before character bits This bit signals the start of data transmission DATA character bits Transmission data set in the UARTIi transmit buffer register PAR parity bit A signal to be added immediately after character bits so as to increase data reliability The level of this signal so varies that the total number of 1 s in character bits and this bit always becomes even or odd depending on which parity is chosen even or odd SP stop bit Either 1 bit or 2 bit H signal to be added immediately after character bits after the parity bit if parity is checked This they signals the end of data transmission Rev 2 00 Oct 16 2006 page 55 of 354 7tENESAS REJ09B0340 0200 Rev 2 00 Oct 16 2006 page 56 of 354 REJ09B0340 0200 M30245 Group 2 Transfer rate 2 UART The divide by 16 frequency resulting from division in the bit rate generator BRG becomes the trans fer rate The count source for the transfer rate register can be selected from f1 fg 32 and the input from the CLK pin Clocks f1 f8 32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Table 2 4 2 Example of baud rate setting Baud rate BRG s System clock 16MHz System clock 7 3728MHz bps count sou
253. error occurred P 2 Start reception 4 Data is read Tc Transfer clock Receive enable bit RE Parity Stop bit RxDi Note TxDi Note Since a parity error occurred the Ps L level returns from TxDi Signal line level Note Receive complete flag RI q Read to receive buffer Receive interrupt Read to receive buffer request bit IR g eee N a R O EES Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Te 16 n 1 fior 16 n 1 fext fi frequency of BRGi count source f1 f8 32 fExT frequency of BRGi count source external clock n value set to BRGi The above timing applies to the following settings Parity is enabled One stop bit e Transmit interrupt cause select bit 1 Note TxDi and RxDi are connected in the manner of wired OR as shown in the connection diagram So TxDi and RxDi ought to become the same signal from the logical standpoint but the output signals turn complex so they are shown separately Also the signal level resulting from connecting TxDi and RxDi is shown as a signal line level Figure 2 4 16 Operation timing of reception in UART mode used for SIM interface Rev 2 00 Oct 16 2006 page 78 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface T Setting UARTIi transmit receive mode register i 0 to 3 b7 b0 UARTIi transmit receive mode reg
254. es the setup stage data stage and status stage Which one of write transfer read transfer and no data transfer is executed in the data stage is deter mined by the content of the setup data acquired in the setup stage Examples of the receive processing routine of the SET_ADDRESS request and the GET_CONFIGURATION request are described For rewriting USB address register when the SET_ADDRESS request is received follow the proce dure below When the device is in the default state USB address register value is 0 1 When USB address register is received the SET_ADDRESS request from the host CPU store the new address data in the USB address register 2 When the status phase of the SET_ADDRESS request is completed USB address register is rewritten into the address written in above mentioned 1 When the status phase is not normally completed USB address register is not rewritten When the device is in the address state USB address register value is other than 0 1 When USB address registeris received the SET_ADDRESS request from the host CPU confirm that the status phase of SET_ADDRESS request completes 2 Store the new address data in USB address register The USB function control unit applies this address to all the subsequent device accesses The SET_ADDRESS request is shown in Figure 2 8 35 the device address acquisition processing routine of USB SET_ADDRESS request is shown in Figure 2 8 36 and Figure 2 8 37 the device
255. escribed below Figure 2 10 5 shows an example of operation and Figure 2 10 6 shows the set up procedure Table 2 10 1 Choosed functions Transfer space Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address Unit of transfer 8 bits 16 bits Operation 1 When software trigger is selected setting software DMA request bit to 1 generates a DMA transfer request signal 2 If DMAC is active data transfer starts and the contents of the address indicated by the DMAi forward direction address pointer are transferred to the address indicated by the DMAi desti nation pointer When data transfer starts directly after DMAC becomes active the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter and the value of the DMAi source pointer is reloaded by the DMAi forward direction address pointer Each time a DMA transfer request signal is generated 1 byte of data is transferred The DMAi transfer counter is down counted and the DMAi forward direction address pointer is up counted 3 If the DMA transfer counter underflows the DMA enable bit changes to 0 and DMA transfer is completed The DMA interrupt request bit changes to 1 simultaneously o Request signal for a DMA transfer occurs o Underflow 2 Data transfer begins Ue PLL Address bus i CPU use coe eek CPU use
256. ess than 10 MHz by dividing Figure 2 9 2 AD converter related registers 1 Rev 2 00 Oct 16 2006 page 216 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 A D Converter AD control register 2 Note b7 b6 b5 b4 b3 b2 bi _ bo Symbol Address When reset AIX ADCON2 03D416 X00X0XX02 Bit Symbol Bit Name Function SMP AID conversion method 0 Without sample and hold select bit 1 With sample and hold Nothing is assigned Write 0 when writing to these bits The values are indeterminate when read Reserved Must always be set to 0 Nothing is assigned Write 0 when writing to this bit The value is indeterminate when read Reserved Must always be set to 0 o Nothing is assigned Write 0 when writing to this bit The values are indeterminate when read Note If the AD control regsiter 2 is rewritten during A D conversion the conversion result is indeterminate AD register i i 0 to 7 Symbol Address When reset b15 OS ig ADi i 0to 2 03C016 to 3C116 03C216 to 3C316 03C416 to 3C516 Indeterminate ADi i 3to5 03C616 to 3C716 03C816 to 3C916 03CA16 to 3CB16 Indeterminate ADi i 6to 7 03CC16 to 3CD16 03CE16 to 3CF16 Indeterminate Function Eight low order bits of A D conversion results During 10 bit mode Two high order bits of A D conversion results During 8 bit mode The values are ind
257. ession an overrun error occurs if the serial interface starts re ceiving the next data item while the receive complete flag is 1 before reading the contents of the UARTIi receive buffer register and receives the 7th bit of the next data item and then the overrun error flag is set to 1 In this instance the next data is written to the UARTI receive buffer register so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again If an overrun error occurs the UARTi receive interrupt request bit does not go to 1 4 To receive data in succession set dummy data in the lower order byte of the UARTi transmit buffer register every time reception is made In continuous receive mode when the receive buffer is read out the unit simultaneously goes to a receive enable state without having to set dummy data back to the transmit buffer register again 5 With an external clock selected perform the following set up procedure with the CLKi pin input level H if the CLK polarity select bit 0 or with the CLKi pin input level L if the CLK polarity select bit 1 1 Set receive enable bit to 1 2 Set transmit enable bit to 1 3 Write dummy data to the UARTIi transmit buffer register 6 Output from the RTS pin goes to L level as soon as the receive enable bit is set to 1 This is not related to the content of the tran
258. essor mode some of the pins function as the address bus the data bus and as control signals and this makes the external buses be able to operate When accessing an external area 8 bit data bus width or 16 bit data bus width can be selected based on the BYTE pin level 16 bit width is used to access an internal area regardless of the level of the BYTE pin Fix the BYTE pin either to H or L level 8 bit and 16 bit data bus widths cannot be used together in an external area Make sure the BYTE pin is fixed to H level when an 8 bit bus width is selected and L level when a 16 bit bus width is selected Rev 2 00 Oct 16 2006 page 330 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 2 Data Access 4 2 1 Data Bus Width If the voltage level input to the BYTE pin is H the external data bus width becomes 8 bits and P10 Ds through P17 D15 can be used as I O ports Figure 4 2 1 If the voltage level input to the BYTE pin is L the external data bus width becomes 16 bits and POo Do through P07 D7 and P10 D8 through P17 D15 operate as a data bus Do through D15 Figure 4 2 1 Bus width 8 bit BYTE H Microcomputer External device P00 to P07 Data bus Do to D7 momen n 1 O port P20 to P27 Al P30 to P37 Address bus A0 to A15 P40 to P43 nd Address bus A16 to A19 Note 1 P44 to P47 Chip select CS0 to CS3 Note 2 P50 to P52 K RD WRL WRH RD B
259. et e 3 When entering power saving mode main clock stops using this bit When returning from stop mode and operating in XIN set this bit to 0 When main clock oscillation is operating by itself set system clock select bit CM07 to 1 before setting this bit to 1 e 4 When inputting external clock only clock oscillation buffer is stopped and clock input is acceptable e 5 If this bit is set to 1 XoUT becomes H The built in feedback resistor remains connected so XIN becomes pulled up to Xout H using the feedback resistor e 6 Set port Xc select bit CM04 to 1 and stabilize the sub clock oscillating before setting to this bit from O to 1 Do not write to both bits at the same time Also set the main clock stop bit CM05 to 0 and stabilize the main clock oscillating before setting this bit from 1 to 0 Note 7 This bit changes to 1 when changing from high speed medium mode to stop mode and at reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 8 fc3z is not included Do not set to 1 when using low speed or low power dissipation mode Note 9 When the XcIN XCOUT is used set ports P86 and P87 as the input ports without pull up System clock control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 0 0 Symbol Address When reset CM1 000716 2016
260. eterminate when read Nothing is assigned Write 0 when writing to these bits The values are indeterminate when read Figure 2 9 3 A D converter related registers 2 Rev 2 00 Oct 16 2006 page 217 of 354 ENESAS REJ09B0340 0200 X M30245 Group 2 A D Converter 2 9 2 Operation of A D converter one shot mode In one shot mode choose functions from those listed in Table 2 9 2 Operations of the circled items are described below Figure 2 9 4 shows the operation timing and Figure 2 9 5 shows the set up procedure Table 2 9 2 Choosed functions Operation clock HAD Divided by 4 fan divided by 3 fap divided by 2 fap fab Resolution 8 bit 10 bit Analog input pin O One of ANo pin to AN7 pin Trigger for starting O Software trigger A D conversion Trigger by ADTRG Sample amp Hold Not activated Activated Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to begin operating 2 After A D conversion is completed the content of the successive comparison register con version result is transmitted to AD register i At this time the A D conversion interrupt re quest bit goes to 1 Also the A D conversion start flag goes to 0 and the A D converter stops operating 1 Start A D conversion 2 A D conversion is complete 8 bit resolution 28 AD cycles 10 bit resolution 33 AD cycles Set to
261. f 354 lt ENESAS REJ09B0340 0200 an M30245 Group 2 A D Converter 2 9 8 Precautions for A D Converter 1 Write to each bit except bit 6 of AD control register 0 to each bit of AD control register 1 and to bit O of AD control register 2 when A D conversion is stopped before a trigger occurs In particular when the Vref connection bit is changed from 0 to 1 start A D conversion after an elapse of 1 us or longer 2 To reduce conversion error due to noise connect a voltage to the AVcc pin and to the Vref pin from an independent source It is recommended to connect a capacitor between the AVss pin and the AVcc pin between the AVss pin and the Vref pin and between the AVss pin and the analog input pin ANi Figure 2 9 17 shows the an example of connecting the capacitors to these pins Microcomputer C120 47 uF C220 47 uF C3100 pF for reference Use thick and shortest possible wiring to connect capacitors Figure 2 9 17 Use of capacitors to reduce noice 3 Set the direction register of the following ports to input the port corresponding to a pin to be used as an analog input pin and external trigger input pin P93 4 Rewrite to analog input pin after changing A D operation mode 5 When using the one shot or single sweep mode Confirm that A D conversion is complete before reading the AD register Note When A D conversion interrupt request bit is set it shows that A D conversion
262. f reception in UART mode 2 Rev 2 00 Oct 16 2006 page 71 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 UART 2 4 4 Serial I O Precautions UART Mode Description When the level of the CLKi and CTSi pins goes to H Note 1 if the UIMR register is set to any of the following the UiERE bit in the UiC1 register is set to 1 parity error signal output enabled When the PRYE bit in the UiMR register is set to 1 while the UIERE bit is 1 parity error signal output enabled the TXDi pin outputs L level if a parity error occurs while receiving data To prevent this set the UIERE bit after setting the UiMR register e Change the setting of bits SMD2 to SMDO from 0002 serial I O disabled to 1012 UART mode transfer data length 8 bits e Change the setting of bits SMD2 to SMDO from 0012 clock synchronous serial I O mode to 1002 UART mode transfer data length 7 bits e Change the setting of bits SMD2 to SMDO from 0012 clock synchronous serial I O mode to 1012 UART mode transfer data length 8 bits e Change the setting of bits SMD2 to SMDO from 0012 clock synchronous serial I O mode to 1102 UART mode transfer data length 9 bits e Change the setting of bits SMD2 to SMDO from 0102 I2C mode to 1012 UART mode transfer data length 8 bits Note 1 If the pins are not used as CLKi or CTSi these conditions apply when the pin level goes to H
263. f the transfer clock TxD RxD I O polarity reverse bit No reverse Reverse Operation 1 Writing dummy data to the UARTIi transmit buffer register setting the receive enable bit to 1 and the transmit enable bit to 1 makes the data receivable status ready At this time the output from the RTSi pin goes to L level which informs the transmission side that the data receivable status is ready output the transfer clock from the IC on the transmission side after checking that the RTS output has gone to L level 2 In synchronization with the first rising edge of the transfer clock the input signal to the RxDi pin is stored in the highest bit of the UARTi receive register Then data is taken in by shifting right the content of the UARTi reception data in synchronization with the rising edges of the transfer clock 3 When 1 byte data lines up in the UARTIi receive register the content of the UARTIi receive register is transmitted to the UARTi receive buffer register The transfer clock stops at H level At this time the receive complete flag and the UARTI receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read Note e Set CLKi and RxDi pins port direction register to 0 Rev 2 00 Oct 16 2006 page 49 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Clock Synchronous Seria
264. fault state Setting of receive device address to USB address register Note 2 b15 b8 b7 bO b7 bo USB address register 0 ojo USBA Address 028016 __ G L Set the third byte the lower of wValue of reception data Note 2 Only the lower 1 byte of the receive device address should be set Setting of USB endpoint 0 control and status reister Continued on a status stage we bo by bo USB endpoint 0 control and status register EPOCS Address 029816 0 1 CLR_OUT_BUF_RDY bit 1 Clear OUT_BUF_RDY flag CLR_SETUP flag 1 Clear SETUP flag SET_DATA_END bit 1 Set DATA_END flag to 1 Waiting for completion of status phase Completion of SET_ADDRESS request Figure 2 8 36 Processing routine 1 for getting device address when receiving SET_ADDRESS request Rev 2 00 Oct 16 2006 page 178 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function continued from previous page Getting of new address address state Setting of USB endpoint 0 control and status register r Go e7 bo USB endpoint 0 control and status register 0 1 EPOCS Address 029816 CLR_OUT_BUF_RDY bit 1 Clear OUT_BUF_RDY flag CLR_SETUP flag 1 Clear SETUP flag SET_DATA_END bit 1 Set DATA_END flag to 1 W
265. from the host at the time of transaction start 8 bits 7bits 4 bits 5 bits PID ADDR ENDP orcs PID OUT OxE1 IN 0x69 SETUP 0x2D Data Packet Packet to use at the time of data transfer 8 bits Oto 1034 bytes 16 bits PID DATA _ crc16 PID DATAO 0xC3 DATA1 0x4B Hand Shake Packet Packet to use at the transaction which controls flow 8 bits PID ACK 0xD2 NAK 0xA5 STALL 0x1E Note In each packet there are SOP as start of packet and EOP as end of packet Figure 2 8 2 Kinds of packet Table 2 8 1 List of USB packet recognitions PID name Process overview SETUP Reports the operation request to device by the host CPU IN Requests the data transmit to device by the host CPU OUT Requests the data receive to device by the host CPU SOF Indicates the start of frame to device by the host CPU DATA DATAO Indicates that the sequence bit of transmit receive data is even number DATA1 Indicates that the sequence bit of transmit receive data is odd number Handshake ACK Reports that the transmit data was correctly completed NAK Reports that the device is in the communication wait state STALL Reports that the communication was incorrectly completed Rev 2 00 Oct 16 2006 page 129 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function Transaction A transaction is the unit in which the host CPU schedules one frame Each transaction is config ured with packe
266. g With the internal clock the RTS function has no effect Figure 2 3 11 shows an example of wiring Transmitter side IC Receiver side IC Figure 2 3 11 Example of wiring Rev 2 00 Oct 16 2006 page 53 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O Transmission 1 With an external clock selected perform the following set up procedure with the CLKi pin input level H if the CLK polarity select bit 0 or with the CLKi pin input level L if the CLK polarity select bit 1 1 Set the transmit enable bit to 1 2 Write transmission data to the UARTIi transmit buffer register 3 L level input to the CTSi pin when the CTS function is selected Reception 1 In operating the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside from the TxDi pin transmission pin when receiving data 2 With the internal clock selected setting the transmit enable bit to 1 transmission enabled status and setting dummy data in the UARTi transmission buffer register generates a shift clock With the external clock selected a shift clock is generated when the transmit enable bit is set to 1 dummy data is set in the UARTi transmit buffer register and the external clock is input to the CLKi pin 3 When receiving data in succ
267. g an external clock input for the CPU clock set the main clock stop bit to 1 Setting the main clock stop bit to 1 causes the XOUT pin not to operate and the power consumption goes down when using an external clock input the clock signal is input regardless of the content of the main clock stop bit Rev 2 00 Oct 16 2006 page 283 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Programmable I O Ports 2 17 Programmable I O Ports Usage 2 17 1 Overview of the programmable I O ports usage Eighty one programmable I O ports and one input only port are available I O pins also serve as I O pins for built in peripheral functions Each port has a direction register that defines the I O direction and also has a port register for I O data In addition each port has a pull up control register that defines pull up in terms of 4 bits The input only port has neither direction register nor pull up control bit The following is an overview of the programmable I O ports usage 1 Writing to a port register With the direction register set to output the level of the written values from each relevant pin is output by writing to a port register The output level conforms to CMOS output Port P70 and P71 are N channel open drain Writing to the port register with the direction register set to input inputs a value to the port register but nothing is output to the relevant pins The output level remains floating In memory expansion and microproces
268. g an external signal to the Serial Sound Interface set the corresponding port s direction register as input Serial Sound Interface function related pins 1 SCLKo and SCLKipins Transfer clock input 2 WSo and WSipins Channel clock input 3 RXo and RXipins Data input 4 XMITo and XMITipins Data output Serial Sound Interface function related register Figure 2 6 1 shows a memory map of the frequency synthesizer related registers Figures 2 6 2 and 2 6 3 show the configuration of Serial Sound Interface function related registers respectively Set the port s direction register appropriately and disable the clock synchronous serial and the UART which share the port Rev 2 00 Oct 16 2006 page 111 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial sound interface l d d 031016 Serial Sound Interface 0 mode register 0 SSOMRO 031116 Serial Sound Interface 0 mode register 1 SSOMR1 031216 Reserved ss ss Csr 031316 Reserved 0314 a Serial Sound Interface 0 transmit buffer register SSOTXB Ai Serial Sound Interface 0 receive buffer register SSORXB 16 031816 031916 Serial Sound Interface 0 RF register SSORF 031A16 Reserved 037016 Serial Sound Interface 1 mode register 0 SSI1MRO 037116 Serial Sound Interface 1 mode register 1 SSI1MR1 037216 Reserved 037316 Reserved st Serial Sound Interface 1 transmit buffer register SSI1 TXB 037616 037716
269. ger than one cycle of the timer s count source after the previous trigger occurred Rev 2 00 Oct 16 2006 page 37 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 15 Precautions for Timer A pulse width modulation mode 1 To clear reset the count start flag is set to O Set a value in the timer Ai register then set the flag to 1 2 The timer Ai interrupt request bit becomes 1 if setting operation mode of the timer in compli ance with any of the following procedures e Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer Ai interrupt interrupt request bit set timer Ai interrupt request bit to 0 after the above listed changes have been made 3 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TAiOUT pin is outputting an H level in this instance the output level goes to L and the timer Ai interrupt request bit goes to 1 If the TAiOUT pin is outputting an L level in this instance the level does not change and the timer Ai interrupt request is not generated Rev 2 00 Oct 16 2006 page 38 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O 2 3 Clock Synchronous Serial I O 2 3 1 Overview Clock synchronous serial I O carries out 8 bit data communications in
270. gister Start reception a Checking completion of data reception b7 b0 UARTi transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register S 7 a Checking error g bs UARTO receive buffer register Address 03AF16 03AE16 UORB bob7 UART1 receive buffer register Address 036F 16 036E16 U1RB UART2 receive buffer register Address 033F 16 033E16 U2RB UARTS receive buffer register Address 032F 16 032E16 U3RB Overrun error flag 0 No overrun error 1 Overrun error found Processing after reading out received data Figure 2 3 10 Set up procedure of reception in clock synchronous serial I O mode 2 Rev 2 00 Oct 16 2006 page 52 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 Clock Synchronous Serial I O 2 3 4 Precautions for Serial I O in clock synchronous serial I O mode Transmission reception 1 With an external clock selected and choosing the RTS function the output level of the RTSi pin goes to L when the data receivable status becomes ready which informs the transmis sion side that the reception has become ready The output level of the RTSi pin goes to H when reception starts So if the RTSi pin is connected to the CTSi pin on the transmission side the circuit can transmission and reception data with consistent timin
271. gister b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset P8 03F016 Indeterminate Bit symbol R Data is input and output to and from rt P A ee ret each pin by reading and writing to P82 Port P82 regis and from each corresponding bit P8_3 Port P83 regis except for P85 P8_5 Port P85 regis P8 6 Port P86 regis P8_7 Port P87 regis P83 0 L level data Port P84 regis 1 H level data Port P9 register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset P9 03F 116 Indeterminate Bit symbol Port P90 register L level data H level data VbusDTCT Vbus detect state bit a Not powered Powered Note 1 Port P92 register L level data H level data Port P93 register L level data H level data Nothing is assigned Write 0 when writing to these bits The value is indeterminate if read Note 1 This pin cannot be used for GPI O This bit reads O when Vbus detect is disabled Figure 2 17 4 Programmable I O ports related registers 3 Rev 2 00 Oct 16 2006 page 290 of 354 lt ENESAS REJ09B0340 0200 nk M30245 Group 2 Programmable I O Ports Pull up control register 0 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PURO 03FC16 0016 Bit symbol ened Poo to Poa puly The corresponding port is pulled oO 4 PUO1 P04 to P07 pull u high with a pull up resistor OO PU02 P10 to P13 pull u 0 Not pulled high Ke 1 Pulled high
272. gt oAD ae WI Set to 1 by software i Cleared to 0 by software A D conversion start flag 0 J AD register 0 AD register 1 x Result AD register i X Result Note When o0aD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 ap cycles for 8 bit resolution and 59 pap cycles for 10 bit resolution Figure 2 9 12 Operation timing of repeat sweep 0 mode Rev 2 00 Oct 16 2006 page 226 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 A D Converter Selecting Sample and hold b7 bO AD control register 2 Address 03D416 DTD XT aoconz 99 A D conversion method select bit 1 With sample and hold a Must always be set to 0 x Setting AD control register 0 and AD control register 1 b7 0 b7 b0 i 0 7 7 AD control register 0 0 RBC ONT register 1 Address 03D716 Address 03D616 ADCONO aie Invalid in repeat sweep mode 0 Invalid in Repeat mode A D operation mode select bit 1 Note 1 Repeat sweep mode 0 is selected 0 Must always be 0 in repeat mode Note 1 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode _____ Trigger select b
273. h Detach Register b7 b6 b5 b4 b3 b2 bi b0 aii ee i Bit symbol 0 Normal mode for Port 90 P9o second Port 90 Second 1 Forces Port 90 to operate as pull up for D Attach Attach Detach 0 ATTACH e oa ae 5 0 Disabled VBDT Vbus detect enable 1 Enabled o0 Figure 2 8 10 USB Attach Detach register Rev 2 00 Oct 16 2006 page 140 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB endpoint enable register Endpoints 1 to 4 are used to enable endpoint IN OUT FIFOs for use The endpoint 0 is always enabled and cannot be disabled by software All Endpoints 1 to 4 are disabled after reset The configuration of USB endpoint enable register is shown in Figure 2 8 11 USB Endpoint Enable register b15 b8 b7 bO b7 0 0 0 Symbol Address When reset fm ies ee es emi e a a ib pound USBEPEN 028E16 000016 Bit Symbol Bit Name Function EP1_OUT EP1 OUT enable 0 Disabled EP1_IN EP1 IN enable 1 Enabled EP2_OUT EP2 OUT enable EP2_IN EP2 IN enable EP3_OUT EP3 OUT enable EP3_IN EP3 IN enable EP4_OUT EP4 OUT enable EP4_IN EP4 IN enable Reserved Must always be 0 Figure 2 8 11 USB endpoint enable register USB endpoint x x 0 to 4 IN FIFO data register Endpoints 0 to 4 respectively have their IN FIFOs At the time of transmission to the host PC write the transmit data in these registers Ac
274. hake Handshake Handshake Control Write SETUP stage DATA stage Status stage DATAO DATA1 0 Handshake Handshake Handshake No data Control SETUP stage Status stage DATAO Handshake Handshake 5 Host issues Device issues Figure 2 8 4 Control transfer communication sequence Rev 2 00 Oct 16 2006 page 131 of 354 REJ09B0340 0200 REN Ea M30245 Group 2 USB function Control Read Transfer In setup stage host notifies the device that it is control read transfer Then in data stage data are transmitted from the device to host through repetition of IN transaction Finally in status stage OUT transaction is executed that the host transmits an empty packet of data length 0 to the device to complete the control read transfer Control Write Transfer In setup stage host notifies the device that it is control write transfer Then in data stage data are transmitted from the host to device through repetition of OUT transaction Finally in status stage IN transaction is executed that the device transmits an empty packet of data length 0 to the host to complete the control write transfer No Control Data Transfer In setup stage host notifies the device that it is no control data transfer Then in status stage IN transaction is executed that the device transmits an empty packet of data length 0 to the host to complete the no control data transfer The execution result of setup stage and data stage are notif
275. he following timing e When changing the flag using the REIT instruction the acceptance of the interrupt takes effect as the REIT instruction is executed e When changing the flag using one of the FCLR FSET POPC and LDC instructions the acceptance of the interrupt is effective as the next instruction is executed When changed by REIT instruction Determination whether or not to Interrupt request generated accept interrupt request Previous Interrupt sequence instruction If flag is changed from 0 to 1 by REIT instruction When changed by FCLR FSET POPC or LDC instruction Determination whether or not to Interrupt request generated accept nt request Previous instructiori FSET Next instruction Interrupt sequence If flag is changed from 0 to 1 by FSET instruction Figure 2 15 3 The timing of reflecting the change in the flag to the interrupt 3 Interrupt Request Bit The interrupt request bit is set to 1 by hardware when an interrupt is requested After the interrupt is accepted and jumps to the corresponding interrupt vector the request bit is set to 0 by hardware The interrupt request bit can also be set to 0 by software Do not set this bit to 1 4 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL Set the interrupt priority level using the interrupt priority level select bit which is one of the component bits of the interrupt control register When an interrupt
276. he reload is carried out for the transfer counter and on the address pointer subjected to forwar d direction The following examples are described in section 2 10 2 and 2 10 3 A fixed address from an arbitrary 1M byte space one shot transfer e An arbitrary 1M byte space from a fixed address repeated transfer 8 Regis ters related to DMAC 2 DMAC Figure 2 10 1 shows the memory map of DMAC related registers and Figures 2 10 2 and 2 10 4 show DMAC related registers 002016 002116 002216 DMAO source pointer SARO 002316 002416 002516 002616 DMAO destination pointer DARO 002716 002816 002916 DMAO transfer counter TCRO 002015 DMAO control register DMOCON 003016 003116 003216 DMA1 source pointer SAR1 0 003316 003416 003516 003616 DMA1 destination pointer DAR1 0 0 0 003716 003816 003916 DMA transfer counter TCR1 0 0 003C16 DMA1 control register DM1CON 004C16 DMAO interrupt control register DMOIC 004E16 DMA interrupt control register DM1IC 005016 DMA2 interrupt control register DM2IC 005216 DMAS interrupt control register DM3IC 018016 018116 018216 018316 018416 018516 018616 018716 019816 018916 018Ci5 019116 019216 019616 019716 019Ci6 03B016 03B116 03B216 03B816 03B916 O3BA16 DMA2 sourc
277. hen External clock is selected the CLKi pin input H before data reception CLK polarity select bit 0 Transmit enable bit gt 1 Receive enable bit 1 Dummy data write to UARTIi transmit buffer register fEXT frequency of external clock Figure 2 5 17 Operation timing of reception in serial interface special function slave mode with clock delay Rev 2 00 Oct 16 2006 page 107 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function b7 bO 0 1 0 01 Setting UARTIi transmit receive mode register i 0 to 3 UARTI transmit receive mode register UiMR Address 03A816 36816 033816 32816 Note 2 Set the c Must be fixed to 001 Note 1 t Internal external clock select bit 1 External clock Note 2 Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to 0 Note 1 Set the RxDi pin s port direction register to 0 when receiving orresponding port direction register to 0 ff Setting UARTi b7 bO 0 0 1 0 It canno S 1 Data output select bit Note 2 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge transmit receive control register
278. hen TOGGLE _INIT bit is set to 1 the read write counter inside the FIFO is initialized To initialize the PID set TOGGLE_INIT bit to 1 in the IN FIFO is empty state the IN BUF_STSO and IN_BUF_STS1 flags are 002 Rev 2 00 Oct 16 2006 page 205 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 USB function 6 USB Transmit Endpoints 1 to 4 IN Example The endpoints 1 to 4 IN transmit packet prepare routine continuous transfer disable is shown in Figure 2 8 49 In addition to packet prepare process error process by the UNDER_RUN flag is re quired in isochronous transfer Process of USB endpoint x IN packet prepare C4 Confirming of whether there is a space which is equal to one packet in the IN FIFO check the IN_ BUF_STSO and the IN_BUF_STS1 b15 b8 z ale bO_b7 bo USB endpoint x IN control and status register sa EPxICS x 1 4 Address 029E16 02A416 02AA16 02B016 __IN_BUF_STSO flag IN_BUF_STS1 ilag b1 b0 0 0 No data set in the IN buffer 0 1 Single buffer mode N A Double buffer mode one data set in the IN buffer 0 N A 1 Single buffer mode one data set in the IN buffer C Double buffer mode two data set in the IN buffer IN FIFO full There is a space in the IN FIFO 2 Writing of the transmit data equal to one packet data Note 1 to the IN FIFO b15 b8 b7 bob USB endpoint x IN FIFO data register EP
279. hen this bit is set to 1 the P90 has the USB attach detach function serving as the power supply pin for pull up to the D line When using the USB attach detach function be sure to connect be tween the USB D pin and the P90 ATTACH pin via a 1 5kQ pull up resistance Also in either case be sure to connect the UVcc pin to the power source eAttach detach bit This bit is valid when port 90 Second bit is set to 1 When this bit is set to O supply of UVcc pin voltage to P90 is stopped and the USB cable becomes a detach state artificially When this bit is set to 1 the USB cable becomes a attach state artificially since the Uvcc pin voltage is supplied to the P90 and D line is pulled up After frequency synthesizer is stabilized set 1 attach state to this bit Vbus detect enable bit This bit is used to enable Vbus detection by setting to 1 When enabling the Vbus detection con nect the Vbus pin of USB connector to a VbusDTCT pin When attach detach bit is changed from 0 to 1 or from 1 to 0 time required till the host recog nizes attach detach varies according to board resistance factor capacity factor USB cable capacity of the device host s board characteristics and processing speed Perform sufficient evaluation through controlling attach detach bit in accordance with the actual user s system The configuration of USB attach detach register is shown in Figure 2 8 10 USB Attac
280. hnology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of acci
281. i 0 to 3 by b0 UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit buffer empty flag 0 Data present in transmit buffer register No data present in transmit buffer register Writing next transmit data enabled When transmitting continuously 2 UART b7 b0 b7 Setting transmission data Note Use MOV instruction to write to this register Writing next transmit data Note b15 b8 UARTO transmit buffer register Address 03AB16 O3AA16 UOTB b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Figure 2 4 9 Set up procedure of transmission in UART mode 2 Rev 2 00 Oct 16 2006 page 67 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 4 3 Operation of Serial I O reception in UART mode 2 UART In receiving data in UART mode choose functions from those listed in Table 2 4 5 Operations of the circled items are described below Figure 2 4 10 shows the operation timing and Figures 2 4 11 and 2 4 12 show the set up procedures Table 2 4 5 Choosed functions Transfer clock Internal clock f1 fs f32 source External clock CLKi pin TxD RxD I O polarity reverse bit No reverse Reverse RTS function RTS function enabled RTS function disabled Bus collision detection function
282. i 0 0 0 0 0 0 ymbo ress en rese FSCCR 03DB16 000000002 Bit Symbol Bit Name Function 0 Xin FSCCRO Clock source selection 1 fSYN Reserved Must always be set to 0 FCCR4 Divide by 3 option 0 Normal 1 Divide by 3 Reserved Must always be set to 0 Figure 2 7 3 Frequency synthesizer registers 1 Rev 2 00 Oct 16 2006 page 122 of 354 ENESAS REJ09B0340 0200 M30245 Group Frequency Synthesizer Prescaler Register b7 b6 b5 b4 b3 b2 bi b0 Symbol FSP Bit Symbol FSP Frequency Synthesizer Multiply Register b7 b6 b5 b4 b3 b2 bi b0 Symbol FSM Bit Symbol FSM Frequency Synthesizer Divide Register b7 b6 b5 b4 b3 b2 bi b0 Symbol FSD Bit Symbol FSD Address 03DE16 Bit Name Frequency synthesizer prescaler value Address 03DD16 Bit Name Frequency synthesizer multiplier value Address 03DF16 Bit Name Frequency synthesizer divider value Figure 2 7 4 Frequency synthesizer registers 2 Rev 2 00 Oct 16 2006 page 123 of 354 REJ09B0340 0200 7tENESAS 2 Frequency synthesizer PLL When reset 111111112 Function Generates fPIN fPIN f XIN 2 n 1 n FSP value When reset 111111112 Function Generates fvco by multiplying fPIN fvco fPIN X 2 n 1 n FSM value When reset 111111112 Function Generates fsYN by dividing fvco fsYN fvco 2 m 1 m FSD value M30245 Group 2
283. i 0 to 3 UARTI transmit receive control register 0 UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 b0 0 0 f1 is selected 0 1 f8 is selected 1 0 f32 is selected 1 1 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS TS RTS disable bit CTS RTS function disabled of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to 0 Note 2 UART2 transfer pin TxD2 P70 is N channel open drain output t be set to CMOS output b7 b0 ELEY Ph 7 Setting UARTi special mode register 3 i 0 to 3 UARTIi special mode register 3 UiSMR3 Address 03A516 36516 033516 32516 SS port function enable bit 1 SS function enable Clock phase set bit 1 With clock delay Serial input port set bit 1 Select STxDi and SRxDi Slave mode Continued to the next page Figure 2 5 18 Set up procedure of reception in serial interface special function slave mode with clock delay 1 Rev 2 00 Oct 16 2006 page 108 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Serial Interface Special Function Continued from the previous page fo
284. icrocomputer ON Oak WDM 74HC138 Do to D7 M5M5278 M5M5278 Do to D7 Memory map 0000016 4 0800016 OFFFF16 1000016 17FFF16 1800016 1FFFF 2000016 2FFFF 3000016 FFFFF Figure 4 3 6 Chip selects and address bus Rev 2 00 Oct 16 2006 page 339 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 4 Connectable Memories 4 4 1 Operation Frequency and Access Time Connectable memories depend upon the BCLK frequency f BCLK The frequency of f BCLK is equal to that of the BCLK and is contingent on the oscillator s frequency and on the settings in the system clock select bits bit 6 of address 000616 and bits 6 and 7 of address 000716 The following are the conditional equations for the connections Meet these conditions minimally Fig ures 4 4 1 and 4 4 2 show the relation between the frequency of BCLK and memory 1 Read cycle time tCR write cycle time tCW Read cycle time tCR and write cycle time tCW must satisfy the following conditional expressions With the Wait option cleared tCR lt 109 f BCLK and tCW lt 2 x 109 f BCLK When CSxW 1 read one cycle of BCLK write two cycles of BCLK With the Wait option selected tCR lt m 1 x 109 f BCLK and tCW lt m 1 x 109 f BCLK When CSxW 0 and the number of the expansion waits is selected by the CSExW bit m denotes the number of Wait states m 1 when 1 wait selec
285. ied to host CPU in status stage For details of response format of control transfers refer to USB2 0 specification Device Request Concerning setup transaction in the setup stage of control transfer format of its data phase has been defined which is called device request For standard 0 type it is called standard device request which is the basic device request to be supported by all the USB devices For class 1 type it is called class request The USB implementers forum USB IF defines a device class and determines the configuration required in the class and the class request For each data format of the device request refer to USB2 0 specification or the specification for each class Rev 2 00 Oct 16 2006 page 132 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 Bulk Transfer Bulk IN Transfer In bulk IN transfer which data are transmitted from the device to the host CPU IN transactions are repeated When transmit data are available in IN FIFO the M30245 group issues a data packet to the IN token When during the handshake phase of each transaction the M30245 group has nor mally received ACK packet issued by the host PC it toggles DATAO and DATA1 of data packet on next data phase This serves to ensure handshake The M30245 group executes the following re sponses when the data are not transmitted normally When the received IN token is destroyed response is not executed eWhen ACK handshake was not i
286. il the processor mode is switched by use of software after reset Thus the voltage levels of the pins destabilize and there can be an increase in the power source current while these pins are input ports Note 6 VbusDTCT pin is pulled down internaly Rev 2 00 Oct 16 2006 page 286 of 354 REJ09B0340 0200 RENESAS M30245 Group 8 Registers related to the programmable I O ports Figure 2 17 1 shows the memory map of programmable I O ports related registers and Figures 2 17 2 to 2 17 5 show programmable I O ports related registers Figure 2 17 1 Memory map of programmable I O ports related registers Rev 2 00 Oct 16 2006 page 287 of 354 REJ09B0340 0200 03FA16 03FB16 03FC16 O3FDi6 O3FE16 03FF16 2 Programmable I O Ports Port PO PO Port P1 P1 Port PO direction register PDO Port P1 direction register PD1 Port P2 P2 Port P3 P3 Port P2 direction register PD2 Port P3 direction register PD3 Port P4 P4 Port P5 P5 Port P4 direction register PD4 Port P5 direction register PD5 Port P6 P6 Port P7 P7 Port P6 direction register PD6 Port P7 direction register PD7 Port P8 P8 Port P9 P9 Port P8 direction register PD8 Port P9 direction register PD9 Port P10 P10 Port P10 direction register PD10 P7 drive capacity register P7DR Pull up control register 0 PURO
287. in this case 16 bit transfer 2 When the OUT_BUF_STS1 flag of endpoint 1 is set to 1 and packet data receive has been detected set the DMAO transfer counter to the 1 2 X the data count of receive one packet 1 in this application example 143 value is set 3 Set DMA enable bit of DMAOCON to 1 DMAO is enabled Then the DMAO transfer request from the serial sound interface occurs 4 When the transfer request is received the DMAO transfers the 1st word 16 bit data from the endpoint 1 OUT FIFO to the serial sound interface 1 Simultaneously the content of the transfer counter is down counted Then the DMAO transfer request from the serial sound interface occurs 5 As a result of repetition of the above 4 when the DMAO transfer counter underflow DMA enable bit is set to 0 to complete the DMAO transfer Simultaneously the DMAO interrupt request occurs When the DMAO interrupt request is detected set CLR_OUT_BUF_RDY bit of endpoint 1 OUT to 1 Rev 2 00 Oct 16 2006 page 316 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 USB Applications M30245 DMAOQ transfer Host CPU USB transfer y USB endpoint 1 Serial Sound Interface 1 gt OUT FIFO gt gt transmit buffer register Figure 3 7 1 Block diagram of DMA transfer from USB FIFO to serial sound interface Rev 2 00 Oct 16 2006 page 317 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 USB Applications Initialization USB f
288. ing port is pulled PU21 P84 to P87 pull up high with a pull up resistor Except P85 0 Not pulled high PU P90 to P93 pull u 1 Pulled high gt Eemo Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be 0 PU24 P100 to P103 pull up The corresponding port is pulled high with a pull up resistor PU25 P104 to P107 pull up 0 Not pulled high 1 Pulled high Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out tobe 0 Figure 2 14 3 key input interrupt related registers 2 Rev 2 00 Oct 16 2006 page 264 of 354 ENESAS REJ09B0340 0200 M30245 Group 2 Key Input Interrupt 2 14 2 Operation of Key Input Interrupt The following is an operation of key input interrupt Figure 2 14 4 shows an example of a circuit that uses the key input interrupt Figure 2 14 5 shows an example of operation of key input interrupt and Figure 2 14 6 shows the setting procedure of key input interrupt Operation 1 Set the direction register of the ports to be changed to key input interrupt pins to input and set the pull up function 2 Setting the key input interrupt control register and setting the interrupt enable flag makes the interrupt enabled state ready 3 If a falling edge is input to either Klo through KI7 the key input interrupt request bit goes to 1 P104 P105 P106 P107 P100 Klo P101 Kit
289. inuous receive mode enable bit Continuous receive mode disabled Data logic select bit 0 No reverse Set to 0 in clock synchronous serial I O mode b7 Setting UARTI bit rate generator i 0 to 3 bo a aS UARTI bit rate generator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 Gan be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTi bit rate generator when transmission reception is halted Output an L to SS port on the transmitter side IC b7 p 1 Reception enabled bo UARTIi transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled ____ Reception enable bit 1 Reception enabled Writing dummy data Note b15 b8 p A b0 b7 UARTO transmit buffer register Address 03AB16 03AA16 UOTB UART1 transmit buffer register Address 036B16 036A16 U1TB 6 UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Le Setting dummy data Note Use MOV instruction to write to this register Start reception Checking com b7 pletion of data reception UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 Receive complete flag 0 No data present in receive buffer register 1 Data present i
290. ion X 4 s i INTO interrupt request generated TA2 interrupt request generated Starting main clock oscillator b7 b0 0 System clock control register 0 Address 000616 CMO Reserved bit Must always be set to 0 Main clock XIN XouT stop bit 0 On 0 0 Wait until the main clock has stabilized Switching system clock b7 b0 o oJ TITT System clock control register 0 Address 000616 CMO Reserved bit Must always be set to 0 System clock select bit 0 XIN XOUT Figure 3 9 3 Set up procedure of controlling power using wait mode 2 Rev 2 00 Oct 16 2006 page 327 of 354 REJ09B0340 0200 REN E M30245 Group 3 Controlling Power Applications INTO interrupt J Store the registers Restore the registers C REIT instruction Timer A2 interrupt Store the registers Counting clock Restore the registers C REIT instruction Figure 3 9 4 Set up procedure of controlling power using wait mode 3 Rev 2 00 Oct16 2006 page 328 of 354 RENESAS REJ09B0340 0200 Chapter 4 External Buses M30245 Group 4 External Buses 4 1 Overview of External Buses Memory and I O external expansion can be connected to microcomputer easily by using external buses When memory expansion mode or microprocessor mode is selected for proc
291. is initialized by disabling The DMA to use is also initialized In this example one DMA is used for each Serial Sound Interface input and output PESSELAEA TRACES SES RERERA CESS EESEP ERS CEEONS AE SRAREE SS SE REATAE ROASTS PERE AEEESS SERRA ESAS EP RENE ESOL EERE EAS A ssitmr1 0x00 SSI STOP ssilmr0 0x00 SSI STOP dm0s 0x00 DMAO STOP dmOcon 0x00 DMAO STOP dm1sl 0x00 DMA1 STOP dmicon 0x00 DMA1 STOP kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk hee Setting example Audio transmission can be set before or after audio reception The DMA to use is set DMAO audio data transmission and DMA1 audio data reception PEESEAAER EEE ER SEN CEREAL AES SERA EEAES EERE HSER AEASERE a ESSERE RESEEAE ELS ELAS EATS EERE ESAS SS ESE EASE SENS 1 dm0Oic 0x06 DMA completion interrupt enabled dm0sl 0x0e DMAO factor SSI 1 transmit sar0 unsigned long amp txb_buffer source address buffer RAM etc dar0 unsigned long amp ssi1txb destination address SSI 1 transmit buffer tcrO txb_counter DMAO transfer cycle setting dmtic 0x06 DMA completion interrupt enabled dm1sl 0x0a DMA1 factor SSI 1 receive sar1 unsigned long amp ssi1rxb source address SSI 1 receive dar1 unsigned long amp rxb_buffer destination address buffer RAM etc ter1 rxb_counter DMA1 transfer cycle set
292. ister 1 USB ISO control register USB endpoint x x 1 4 IN control and status register USB endpoint x x 1 4 IN FIFO configuration register 2 8 8 USB Operation Interface of USB and DMAC transfer Rev 2 00 Oct 16 2006 page 138 of 354 REJ09B0340 0200 1 4 USB endpoint x x 1 4 IN MAXP register 1 4 r USB DMAx x 0 3 request register RENESAS M30245 Group 2 USB function 2 8 2 USB function control The USB function control unit needs to be enabled for using the USB function The initialization procedure of the USB function control unit is explained below 1 Related Registers USB control register This register is used to control each operation of the USB function control unit When using the USB function be sure to set USB clock enable bit to 1 before USB enable bit is set to 1 This register is not affected by the USB reset signal After the USB is enabled USBC7 1 a minimum 187 5 ns of delay three cycles of BCLK is required before performing any other USB register read write opera tions USB clock enable bit This bit is used to enable disable the USB clock fusb This clock is supplied from frequency synthe sizer and is required for the USB operation Set this bit to 1 when enabling the USB clock USB SOF port select bit This bit is used to enable disable a SOF signal output on the P92 pin Set this bit to 1 when using the USB SOF signal In this case set the port P92 to o
293. ister Address 036F16 036E16 U1RB KX UART2 receive buffer register Address 033F 16 033E16 U2RB UARTS receive buffer register Address 032F 16 032E16 U3RB Overrun error flag 0 No overrun error 1 Overrun error found Processing after reading out received data Rev 2 00 Oct 16 2006 page 109 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial sound interface 2 6 Serial sound interface 2 6 1 Overview The Serial Sound Interface SSI is a synchronous serial data interface used primary for transferring digital audio data The bus of the 30245 Serial Sound Interface has four lines Continuous serial clock SCK e Word channel select WS e Serial data out XMIT e Serial data in RX A basic Serial Sound Interface based communication system has two Serial Sound Interfaces and a master controller which generates both SCK and WS The Serial Sound Interface that generates the control signals SCK and WS operates as a master and the Serial Sound Interface that receives the external control signals operates as slave The 30245 Sound Serial Interface can operate only as a slave The transmitter receiver must change channels on every WS transition Through separate transmit and receive pins simultaneous transmit and receive can be performed in synchronization with the same SCK and WS signals The following is an overview of the Serial Sound Interface Transmission reception format The data p
294. ister loft ojoti ji fofi UiMR Address 03A816 36816 033816 32816 Serial I O mode select bit Note 1 b2 b1 bO 1 0 1 Transfer data 8 bits long Internal external clock select bit 1 External clock Note 2 Stop bit length select bit 0 One stop bit Odd even parity select bit Valid when bit 6 1 Must be 0 odd parity in inverse format _ Parity enable bit 1 Parity enabled TxD RxD I O polarity reverse bit Usually set to 0 Note 1 Set the RxDi pin s port direction register to 0 when receiving 2 Set the corresponding port direction register to 0 fo Setting UARTIi transmit receive control register 0 i 0 to 3 b7 b0 UARTIi transmit receive control register 0 Mohli UiCO Address 03AC16 36C16 033C16 32C 16 L BRG count source select bit 00 f1 is selected 01 f8 is selected 1 0 f32 is selected 1 1 Inhibited Valid when bit 4 0 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed i CTS RTS disable bit 1 CTS RTS function disabled L Data output select bit 1 TxDi SDAi and SCLi pin is N channel open drain output Must be fixed to 0 in UART mode sr Transfer format select bit Must be 1 MSB first in inverse format Setting UART transmit receive control register 1 i 0 to 3 b7 b0 UART i tran
295. ister transmission completed 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed NCH Note 2 CTS RTS disable bit Data output select bit CTS RTS function enabled CTS RTS function disabled TxDi SDAi and SCLi pin is CMOS output TxDi SDAi and SCLi pin is N channel open drain output CTS RTS function enabled CTS RTS function disabled TxDi SDAi and SCLi pin is CMOS output TxDi SDAi and SCLi pin is N channel open drain output CKPOL CLK polarity select bit Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Set to 0 Transfer format select bit 0 LSB first 1 MSB first Note 1 Set the corresponding port direction register to 0 Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output It cannot be set to CMOS output 0 LSB first 1 MSB first Note 3 Only clock synchronous serial I O mode and 8 bit UART mode are valid Note 4 The corresponding port register and port direction register are invalid UARTI transmit receive control register 1 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiC1 i 0 to 3 Figure 2 4 5 UARTi related Rev 2 00 Oct 16 2006 page 62 of REJ09B0340 0200 Bit Name Add
296. it 0 Software trigger CSD cconneerrsion start flag 0 A D conversion disabled ____________ Frequency select bit 1 Note 2 0 fAD 2 or fAD 4 is selected Frequency select bit 0 Note 2 1 fap or faD 3 is selected 0 fAD 3 or fAD 4 is selected 1 fAD or faD 2 is selected Vref connect bit 1 Vref connected Reserved bit Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 When f XIN is over 10 MHz the fan frequency must be under 10 MHz by dividing and set aD frequency to 10 MHz or lower Ha Setting A D conversion start flag b7 b0 7 AD control register 0 Address 03D616 A D conversion start flag 1 A D conversion started Repeatedly carries out A D conversion on pins Start A D conversion selected through the A D sweep pin select bit OOP Transmitting conversion result to AD register i AD registerO Address 03C116 03C0i6 ADO AD register1 Address 03C316 03C2i6 AD1 b8 AD register 2 Address 03C516 030416 AD2 b0 b7 AD register3 Address 03C716 03C616 AD3 AD register4 Address 03C916 03C816 AD4 AD register5 Address 03CB16 03CA16 AD5 AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Setti
297. it A D converte Theoretical A D conversion characteristic in the 8 bit mode gt VREF x 4 VREF VREE x 254 VREE x 255 256 256 56 Analog input voltage Figure 2 9 20 Theoretical A D conversion characteristics 8 bit mode Rev 2 00 Oct 16 2006 page 234 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 9 11 Absolute Accuracy and Differential Non Linearity Error Absolute accuracy 2 A D Converter Absolute accuracy is the difference between output code based on the theoretical A D conversion characteristics and actual A D conversion result When measuring absolute accuracy the voltage at the middle point of the width of analog input voltage 1 LSB width that can meet the expectation of outputting an equal code based on the theoretical A D conversion characteristics is used as an ana log input voltage For example if 10 bit resolution is used and if VREF reference voltage 5 12 V then 1 LSB width becomes 5 mV and 0 mV 5 mV 10 mV 15 mV 20 mV are used as analog input voltages If analog input voltage is 25 mV absolute accuracy 3LSB refers to the fact that actual A D conversion falls on a range from 00216 to 00816 though an output code 00516 can be ex pected from the theoretical A D conversion characteristics Zero error and full scale error are included in absolute accuracy Also all the output codes for analog input voltage between VREF and AVcc becomes
298. it buffer register Address 03AB16 03AA16 UOTB b7 b0 b7 b0 UART1 transmit buffer register Address 036B16 036A16 U1TB UART2 transmit buffer register Address 033B16 033A16 U2TB UARTS transmit buffer register Address 032B16 032A16 U3TB Setting transmission data Setting transmission data 9th bit Note Use MOV instruction to write to this register Nome ep FANSMiIsSsion is complete Figure 2 3 7 Set up procedure of transmission in clock synchronous serial I O mode 2 Rev 2 00 Oct 16 2006 page 48 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 Clock Synchronous Serial I O 2 3 3 Operation of Serial I O reception in clock synchronous serial I O mode In receiving data in clock synchronous serial I O mode choose functions from those listed in Table 2 3 2 Operations of the circled items are described below Figure 2 3 8 shows the operation timing and Figures 2 3 9 and 2 3 10 show the set up procedures Table 2 3 2 Choosed functions Transfer clock source Internal clock f1 fs f32 External clock CLKi pin Transfer clock LSB first MSB first RTS function RTS function enabled RTS function disabled Continuous receive mode Disabled Enabled CLK polarity Output transmission data at the falling edge of the transfer clock Data logic select function No reverse Reverse Output transmission data at the rising edge o
299. it buffer register i 0 to 3 Note b15 b8 CO Symbol Address When reset UOTB 03AB16 03AA16 Indeterminate U1TB 036B16 O36A16 Indeterminate U2TB 033B16 033A16 Indeterminate U3TB 032Bi16 032A16 Indeterminate Function Function i Bit Symbol clock synchronous serial I O mode UART mode R iW l Transma data Transmtdeta resm data xO l I Transmit data 9th bit xO l Nothing is assigned Write 0 when writing to these bits The values are indeterminate when read Note Use MOV instruction to write to this register UARTi receive buffer register i 0 to 3 on bo oe Femme Symbol Address When reset UORB O3AF16 O3AE16 Indeterminate U1RB 036F 16 O36E16 Indeterminate U2RB 033F 16 033E16 Indeterminate U3RB 032F 16 032E16 Indeterminate Function Function Bit Symbol Bit Name clock synchronous UART mode Ri W serial I O mode Receive data Receive data Receive data 9th bit Nothing is assigned Write O when writing to these bits The values are indeterminate when read Arbitration lost Not detected Invalid detecting flag Note 1 Detected Overrun error flag No overrun error 0 No overrun error Note 2 Overrun error 1 Overrun error Framing error flag No framing error Note 2 Invalid Framing error Parity error flag i No parity error Note 2 Invalig Parity error Error sum flag Invalid No error Note 2 nyval Error No
300. itch takes effect from the next effective edge of the count source 4 Setting the count start flag to O causes the counter to hold its value and to stop 5 If an overflow occurs the content of the reload register is reloaded and the count continues At this time the timer Ai interrupt request bit goes to 1 n reload register content 5 Overflow 1 Start count 2 Underflow 4 Stop count tn lt Start count again Counter content hex Set to 1 by software Set to 1 by software Cleared to 0 software Count start flag Set to 1 by software Up down flag Cleared to 0 when interrupt request is accepted or cleared by sdftware Timer Ai interrupt 1 request bit Figure 2 2 12 Operation timing of event counter mode reload type selected Rev 2 00 Oct 16 2006 page 18 of 354 RENESAS REJ09B0340 0200 M30245 Group b7 Selecting event counter mode and functions bo Timer Ai mode register i 0 to 4 Address 039616 to 039A16 0 0 0 0 0j0 1 TAIMR i 0 to 4 Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAi OUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content ____________ Q Must always be O in event counter mode _ Count operation type select bit 0 R
301. ite inhibited C 2 Setting system clock control register i i 0 1 Figure 2 1 2 Set up procedure for protect function Rev 2 00 Oct 16 2006 page 5 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 Timer A 2 2 1 Overview The following is an overview for timer A a 16 bit timer 1 Mode Timer A operates in one of the four modes a Timer mode In this mode the internal count source is counted Two functions can be selected the pulse output function that reverses output from a port every time an overflow occurs or the gate function which controls the count start stop according to the input signal from a port b Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers The free run type in which nothing is reloaded from the reload register can be selected when an underflow occurs The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical Furthermore Timer A has a two phase pulse signal processing function which generates an up count or down count in the event counter mode depending on the phase of the two input signals The normal mode or 4 multiplication mode can be selected depending on the phase detective method c One shot timer mode In this mode the timer is started by the trigger and stops when the timer goes to 0 The trigger can be selected from the following 2
302. ith clock delay Output transmission data at Serial input port set TxDi RxDi selected the rising edge of the transfer clock master mode Transmission Transmission buffer empty STxDi SRxDi selected interrupt factor Transmission complete slave mode Operation 1 Input L level to an SSi port by the output from the receiver side IC s port 2 Setting the transmit enable bit to 1 and writing transmission data to the UARTi transmit buffer register makes data transmissible status ready 3 In synchronization with the first falling edge of the transfer clock transmission data held in the UARTIi transmit buffer register is transmitted to the UARTIi transmit register At this time the UARTIi transmit interrupt request bit goes to 1 Also the first bit of the transmission data is transmitted from the STxDi pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges 4 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that transmission is completed 5 If the next transmission data is set in the UARTi transmit buffer register while transmission is in progress before the eighth bit has been transmitted the data is transmitted in succession Note e Set CLKi pin s port direction register to 0 Rev 2 00 Oct 16 2006 page 102 of 354 RENESAS REJ09B0340 0200 M3024
303. itted to the UARTi receive buffer register At this time the receive complete flag and the UARTIi receive interrupt request bit goes to 1 5 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read Note e Set CLKi and SRxDi pins port direction register to 0 Rev 2 00 Oct 16 2006 page 106 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Example of wiring Microcomputer Transmistter side IC Example of operation 1 Set SSi port to L by the output from the transmitter side IC port 4 Reception is complete 2 Reception enabled j f 5 Read of reception data 3 Start reception i j pul Receive enable bit RE Transmit enable bit TE i Dummy data is set in UARTI transmit buffer register Transmit buffer empty flag TI Transferred from UARTi transmit buffer register to UARTI transmit register SSi i i 1 fext Reception data isitaken in P COVEN EEE CD OOO OEE Transferred from UARTI receive register i Read out from UARTI receive buffer register Receive complete q to UARTi receive buffer register i flag Rl g Receive interrupt 1 a a CO _ request bit IR g Padi Padi Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Make sure that the following conditions are met w
304. izer related registers 000A16 Protect register PRCR X 03DB16 Frequency synthesizer clock control register FSCCR 03DC16 Frequency synthesizer control register FSC 03DD16 Frequency synthesizer multiply register FSM 03DE16 Frequency synthesizer prescaler register FSP 03DF16 Frequency synthesizer divide register FSD Figure 2 7 2 Memory map of frequency synthesizer related registers Rev 2 00 Oct 16 2006 page 121 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Frequency synthesizer PLL Frequency Synthesizer Control register b7 b6 b5 b4 b3 b2 bi bO olo Symbol Address When reset se e FSC 03DC16 011000002 Bit Symbol Bit Name Function FSE Frequency synthesizer enable bit 0 Disabled 1 Enabled b2 b1 vcoo 0 0 Lowest gain VCO gain control bit 0 1 Low gain 1 0 High gain Note 1 Vvco1 1 1 Highest gain Reserved bit Must always be set to O b6 b5 CHGO 0 0 Disabled LPF current control bit Note 2 H 1 1 Low current 0 Medium current Note 1 1 High current CHG1 0 Unlocked Frequency synthesizer lock status bit LS q vey 1 Locked Note 1 Recommended Note 2 Bits 6 and 5 are set to bit 6 bit 5 1 1 at reset When using the frequency synthesizer we recommend to set to bit 6 bit 5 1 0 Frequency Synthesizer Clock Control register b7 b6 b5 b4 b3 b2 bi bO Symbol Add Wh
305. l I O Example of wiring Microcomputer Transmitter side IC CLK TxD Example of operation Receive enable 1 bit RE o Transmit enable 1 bit TE 0 Dummy data is set in UARTIi transmit buffer register Transmit buffer empty flag TI Transferred from UARTI transmit register to UARTi transmit buffer register RTSi r Even if the reception is completed RTS does not change A lt 1 fext RTS becomes L when the RI bit changes from 1 to 0 Q Reception data is taken in RxDi Transferred from UARTi receive register Read out from UARTIi receive buffer register Receive complete 1 to UARTi receive buffer register flag RI Receive interrupt 1 request bit IR o 4 Cleared to 0 when interrupt request is accepted or cleared by software Overrun error flag OER Shown in are bit symbols The above timing applies to the following settings Make sure that the following conditions are met when External clock is selected the CLKi pin input H before data reception e RTS function is selected Transmit enable bit gt 1 CLK polarity select bit 0 Receive enable bit gt 1 Dummy data write to UARTI transmit buffer register fEXT frequency of external clock Figure 2 3 8 Operation timing of reception in clock synchronous serial I O mode Rev 2 00 Oct 16 2006 page 50 of 354 7RENESAS REJ09B0340 0200 M30245 Grou
306. lated registers 16 bit registers except USB endpoint x x 0 to 4 IN FIFO data register EPxl USB endpoint x x 0 to 4 OUT FIFO data register EPxO USB control register USBC and USB attach detach register USBAD are available for word access and byte access The EPxl and the EpxO are only available for word access or byte access to the lower bytes The USBC and the USBAD of 8 bit registers are only available for byte access After software reset contents of all the USB related registers are retained While the USB clock is held disabled in suspend mode writing in the USB internal registers other than USBC USBAD and frequency synthesizer related registers is disabled 4 Packet Data Destruction eWhen FLUSH bit of endpoint x OUT control and status register EPxOCS is set to 1 during USB transfer the receive data may be destroyed Be sure to set FLUSH bit of the EPxOCS to 1 only when there are data in OUT FIFO OUT_BUF_STS1 and OUT_BUF_STS0 are set to 102 or 112 When FLUSH bit of USB endpoint x IN control and status register EPxICS is set to 1 during USB transfer the transmit data may be destroyed Be sure to read the IN_BUF_STS1 and the IN_BUF_STS0O flags and to confirm that there are data in IN FIFO before setting FLUSH bit of the EPxICS to 1 In isochronous transfer use AUTO_FLUSH bit bit 0 of address 028C16 Rev 2 00 Oct 16 2006 page 212 of 354 RENESAS REJ09B0340 0200 M30245 Grou
307. le due to external causes such as noise 2 Peripheral Circuit The peripheral circuit block diagram is shown in Figure 2 8 51 the passive part of LPF pin is shown in Figure 2 8 52 and the connection diagram of decoupling capacitor is shown in Figure 2 8 53 USB2 0 specification specifies the driver impedance 28 44Q See 7 1 1 1 Full speed 12Mb s Driver Characteristics Connect a serial resistor recommended value 27 33Q to the USB D pin and the USB D pin to satisfy this specification Also connect if required the capacitors between the USB D pin USB D pin and the Vss pin These capacitors control ringing or adjust the times of rising falling and the crossover point of D D As the numerical values and the configuration of the peripheral components need to be adjusted according to differences in characteristic impedance and layout of the mount printed circuit board Therefore fully evaluate on the system in use and observe waveforms before adjusting the connection or disconnection and the values of the resistance and the capacitor When the USB Attach Detach function is not used connect the UVcc pin and the USB D pin via a 1 5kQ resistance D line pull up timing depends on the UVCC pin When the USB Attach Detach function is used connect the P90 ATTACH pin and the USB D pin via a 1 5kQ resistance Irrespective of use of the USB Attach Detach function connect the UVCc pin to the power supply In addition the time required for
308. leared and the DATA_END flag is set to 1 The USB function unit proceeds to the status phase process when the DATA_END flag is set to 1 When the status phase completes the DATA_END flag is cleared to O Manage the stage of control transfer by software When the SETUP packet is received the USB endpoint 0 interrupt occurs regardless of setting of continuous transfer mode enable bit The OUT_BUF_RDY flag and the SETUP flag are set to 1 Example of one packet data receive procedure 1 Check that one packet data is received in OUT FIFO 2 Read the number of bytes of receive packet data from USB endpoint 0 OUT write count register Determine the amount of data to read from OUT FIFO 3 Read the data of only amount equal to determined in the above mentioned 2 from OUT FIFO To analyze the received data the subsequent stage and operation are determined based on the read data 4 With CLR_OUT_BUF_RDY bit being set to 1 the OUT_BUF_RDY flag is cleared to complete fetch of the receive one packet and manage the next stage control At this time when the SETUP packet is received the SETUP flag is also cleared by setting 1 to CLR_SETUP bit e For shifting into the status stage even if the next data to be received or transmitted does not exist simultaneously set CLR_OUT_BUF_RDYbit and also CLR_SETUP bit for the SETUP packet and SET_DATA_END bit to 1 e For responding with STALL response to the next token
309. lected Selected Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTIi transmit buffer register readies the data transmissible status 2 When input to the CTSi pin goes to L transmission starts the CTSi pin needs to be con trolled on the reception side 3 Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register At this time the first bit the start bit of the transmission data is transmitted from the TxDi pin Then data is transmitted bit by bit in sequence LSB MSB parity bit and stop bit s 4 When the stop bit s is are transmitted the transmit register empty flag goes to 1 which indicates that transmission is completed At this time the UARTi transmit interrupt request bit goes to 1 The transfer clock stops at H level 5 If the transmission condition of the next data is ready when transmission is completed a start bit is generated following to stop bit s and the next data is transmitted Note e Set CTSi pin s port direction register to 0 Rev 2 00 Oct 16 2006 page 64 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 UART Example of wiring Microcomputer Receiver side IC Note Since TxD2 pin is N channel open drain this pin needs pull up resistance Example of operation When confirming stop bit stopped transfer clock once because CTS H Tc St
310. lely used for normal processes and timer A4 is solely used for 4 multiplication processes Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the interrupt request bit goes to 1 Note The up count or down count conditions are as follows Table 2 2 8 The up count or down count conditions Input signal to the Input signal to the Input signal to the Input signal to the TAiouT pin TAIIN pin TAiouT pin TAIIN pin Up count H level Rising H level Falling L level Falling L level Rising Rising L level Rising H level Falling H level Falling L level e Set TAIIN pin and TAiOUT pin s port direction register to 0 1 Start count Sister a eee ees PP A FFFF16 Note Counter content hex 000016 Set to 1 by software Eas m Time 2 Unde
311. listed above listed above CKDIR Internal external clock T Internal clock T Internal clock select bit External clock Note 1 External clock Note 1 Ts prema wwe eea bo PRY Odd even parity select bit Invalid Valid when bit 6 0 Odd parity 1 Even parity PRYE Parity enable bit Invalid 0 Parity disabled 1 Parity enabled SLeEp TxD RxD input output O Normal polarity switch bit Note 2 1 Reversed 0 0 Note 1 When 12C bus interface mode is selected set the port direction register for the corresponding port SCLi to 0 or the port direction register to 1 and the port data register to 1 When a mode other than serial I O mode is selected set the port direction register for the corresponding port CLKi to 0 Note 2 Normally set to 0 Note 3 Set the RxDi pin s port direction register to O when receiving Figure 2 3 3 Serial l O related registers 2 Rev 2 00 Oct 16 2006 page 43 of 354 REJ09B0340 0200 7tENESAS M30245 Group UARTIi transmit receive control register 0 i 0 to 3 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiCO i 0 to 3 BRG count source select bit CTS RTS function select bit Transmit register empty flag TS RTS disable bit Address 03AC16 036C16 033C16 032C16 Function During clock synchronous serial I O mode b1 b0 00 ftis selected 01 fsis selected 10 f32is selected 1 Inhibited y when bit 4 0 0 CTS function is selected Note 1
312. ll clocks off stop mode Reserved bit Must always be set to 0 Insert at least four NOPs following JMP B instruction after the instruction that sets the all clock stop control bit to 1 a All clocks off stop mode Figure 2 16 5 Example of stop mode set up Rev 2 00 Oct16 2006 page 280 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 16 3 Wait Mode Set Up Settings and operation for entering wait mode are described here Operation 1 Enables the interrupt used for returning from wait mode 2 Sets the interrupt enable flag I flag to 1 3 Clears the protection and changes the content of the system clock control register 4 Executes the WAIT instruction 1 Setting interrupt to cancel wait mode Interrupt control register KUPIC Address 004116 SiRIC i 0 2 3 Address 004A16 004216 005516 S13BCNIC Address 004316 TAiIC i 0 to 4 Address 005416 004516 004716 005716 005916 EPOIC Address 004616 ADIC Address 004Bi6 SiTIC i 0 to 3 Address 005316 005116 004F16 004D16 SUSPIC Address 005616 RSMIC Address 005816 SOFIC Address 005Bi6 VBDIC Address 005Ci6 USBFIC Address 005D16 INTiIC i 0 to 2 Address 005F 16 004416 005E16 b7 b0 b0 S1RIC Address 004816 ZONZO Ao so2gcnic Address 004916 Interrupt priority level select bit L Interrupt priority level select bit Make sure that the interrupt priority Make sure that the interrupt priority level of the level of
313. llator to XCIN to serve as the timer count source As interrupts occur every one second which is a count the timer reaches the controller returns from wait mode and count the clock using a program 2 Clear wait mode if a INTO interrupt request occurs Operation 1 Switch the system clock from XIN to XCIN to get low speed mode 2 Stop XIN and enter wait mode In this instance enable the timer A2 interrupt and the INTO interrupt 3 When a timer A2 interrupt request occurs at 1 second intervals start supplying the BCLK from XCIN At this time count the clock within the routine that handles the timer A2 interrupts and enter wait mode again 4 If a INTO interrupt occurs start supplying the BCLK from XCIN Start the XIN oscillation within the INTO interrupt and switch the system clock to XIN 1 Shift to low speed mode 2 Stop XIN 3 Timer A2 interrupt 4 INTo interrupt XOUT XGIN Timer A2 overflow Timer A2 interrupt processing High speed High speed e o o er Low speed Low speed i Low speed Low speed Figure 3 9 1 Operation timing of controling power using wait mode Rev 2 00 Oct 16 2006 page 325 of 354 RENESAS REJ09B0340 0200 M30245 Group Initial condition bo olo Jo System clock control register 0 Address 000616 CMO Reserved bit Must always be set to 0 WAIT peripheral function clock stop bit 0 Do not stop peripheral function clock in wait mode XCIN XCOUT drive capaci
314. low Figure 2 2 10 shows the operation timing and Figures 2 2 11 shows the set up proce dure Table 2 2 3 Choosed functions Count source Internal count source fi fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAiiN pin is at L level Performs count only for the period in which the TAIN pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Ai interrupt request bit goes to 1 Also the output polarity of the TAIOUT pin reverses 3 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAiOUT pin outputs an L level n reload register content 2 Underflow 1 Start count 3 Stop count Start count again Counter content hex Cleared to g by Set to 1 by software _ software Setto 1 by software a Count start flag Pulse output from TAiOUuT pin Cleared to 0 when interrupt request is accepted or cleared by software Timer Ai interrupt request bit Figure 2 2 10 Operation timing of timer mode pulse output function selected Rev 2 00 Oct 16 2006 page 16 of 354 AS REJ09B0340
315. lse is not output TA10UT pin is a normal port pin Count polarity select bit Up down switching cause select bit 0 Up down flag content 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type When not using two phase pulse signal processing set this bit to O Continued to the next page Figure 3 1 3 Set up procedure of long period timers 1 Rev 2 00 Oct 16 2006 page 297 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 Timer A Applications Continued from the previous page Setting trigger select register b7 bo III To Trigger select register Address 038316 oe ae TRGSR E Timer A1 event trigger select bit b1 b0 1 0 TAO overflow is selected Setting counter value b15 b8 b7 pO be b0 Timer A1 register Address 038916 038816 Setting count start flag bi 0 XXXI TT OI ae Start flag Address 038016 Timer AO count start flag 1 Starts counting Timer A1 count start flag 1 Starts counting Start countin Figure 3 1 4 Set up procedure of long period timers 2 Rev 2 00 Oct 16 2006 page 298 of 354 7RENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications 3 2 Variable Period Variable Duty PWM Output Overview In this process Timer AO and A1 are used to generate variable period variable duty PWM out put Figure 3 2 1 shows the operation timing Figure 3 2 2 shows the connection diag
316. lse output function the output from the port varies the value in the port register does not vary 4 Reading the timer Either in timer mode or in event counter mode reading the timer register takes out the count at that moment Read it in 16 bit units The data either in one shot timer mode or in pulse width modulation mode is indeterminate 5 Writing to the timer To write to the timer register when a count is in progress the value is written only to the reload register When writing to the timer register when a count is stopped the value is written both to the reload register and to the counter Write a value in 16 bit units 6 Relation between the input output to from the timer and the direction register With the output function of the timer pulses are output regardless of the contents of the port direction register To input an external signal to the timer set the port direction register to input 7 Pins related to timer A a TAOIN TA1IN TA2IN TASIN TA4IN Input pins to timer A b TAQoUT TA10UT TA20uUT TA30UT TA40UT Output pins from timer A They become input pins to timer A when event counter mode is active 8 Registers related to timer A Figure 2 2 1 shows the memory map of timer A related registers Figures 2 2 2 through 2 2 5 show timer A related registers Rev 2 00 Oct 16 2006 page 7 of 354 7tENESAS REJ09B0340 0200 M30245 Group 004516 Timer A1 interrupt control register TA1IC 004716 Ti
317. mended N 1 1 High current D Setting the protect Protect register Address 000A16 b7 bo PDDDDI lolo pace Enable bit for writing to system clock control registers 0 and 1 and frequency synthesizer related registers 0 Write inhibited Enable bit for writing to processor mode registers 0 and 1 0 Write inhibited Reserved bit Me Wait for 3ms Checking the frequency synthesizer locked status bit It is necessary to recheck after a wait of 0 1ms if it is O H ve Frequency synthesizer control register Address 03DC 16 FSC Frequency synthesizer lock status bit 0 Unlocked 1 Locked Frequency synthesizer stabilized Continued to the next page 8 17 Initialization procedure of frequency synthesizer and USB function control unit 1 Rev 2 00 Oct 16 2006 page 145 of 354 7tENESAS REJ09B0340 0200 M30245 Group an Continued from the previous page 2 USB function When using fSYN as a main clock b7 bo Frequency synthesizer clock control register Address 03DB16 Lel brr Freque Clock source selection bit 1 fSYN Divide by 3 option 0 Normal 1 Divide by 3 Note Note When this bit is 1 set FSD to 0216 USB clock enabled be 0 USB control register Address 000C 16 Jo of of of o usec USB clock enable bit 1 Enable Supply 48MHZ clock Me Selecting ATTACH DETACH
318. mer A2 interrupt control register TA2IC 005416 Timer AO interrupt control register TAOIC 005716 Timer A3 interrupt control register TA3IC 005916 Timer A4 interrupt control register TA4IC 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 038416 Trigger select register TRGSR Up down flag UDF 038616 038716 038816 038916 Timer AO TAO Timer A1 TA1 038A16 038B16 Timer A2 TA2 038C16 Timer A3 TA3 038D16 038E16 038F16 nw Timer A4 TA4 039616 __ Timer AO mode register TAOMR Timer A1 mode register TA1MR 039716 039816 039916 Timer A2 mode register TA2MR Timer A3 mode register TASMR 039A16 Timer A4 mode register TA4MR Figure 2 2 1 Memory map of timer A related registers Timer Ai mode register i 0 to 4 b7 b6 b5 b4 b3 b2 bi bO Symbol TAIMR i 0 to 4 Address When reset 039616 to 039A16 0016 2 Timer A Bit Symbol Bit Name Function TMODO TMOD1 Operation mode select bit bi b0 0 0 Timer mode 0 1 Event counter mode 1 0 One shot timer mode 1 1 PWM mode MRO MR1 MR2 MR3 Function varies with each mode operation TCKO TCK1 Count source select bit Function varies with each mode operation
319. n L level is input to the HOLD pin 2 HOLD is detected 3 The CPU releases the bus 4 An L is output to the HLDA pin 5 An H is input to the HOLD pin 6 An H is output to the HLDA pin 7 The CPU not releases the bus 8 The CPU resumes using the bus Figure 4 5 1 Example of releasing the external bus Rev 2 00 Oct 16 2006 page 348 of 354 7RENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 6 Precautions for External Bus Description When the MCU enters wait mode while operating in memory expansion mode or micropro cessor mode a pin functioning as part of the address or data bus retains it s state on the bus before wait mode is entered Shift to single chip mode and output an arbitrary value in order to reduce current consumption By shifting to single chip mode a pin which was functioning as part of the bus becomes a general purpose port and can output an arbitrary value Set the port registers and direction registers after shifting to single chip mode this implies that any control pins CS WR RD etc being used for access of an external device be changed as well If the port registers and direction registers are set while in memory expansion mode or microprocessor mode the operation will be ignored This is similar when entering stop mode Figure 4 6 1 shows the setting procedure to enter wait mode or stop mode Operate in memory expansion mode or microprocess
320. n be incremented However both registers cannot be incremented The links between the source and destination are as follows a A fixed address from an arbitrary 1M bytes space b An arbitrary 1M bytes space from a fixed address c A fixed address from another fixed address 002016 to 003F16 and 018016 to 019F 16 cannot be accessed 2 The number of bits of data transferred The number of bit of data indicated by the transfer counter is transferred If a 16 bit transfer is se lected up to 128K bytes can be transferred If an 8 bit transfer is selected up to 64K bytes can be transferred The transfer counter is decremented each time one bit of data is transferred and a DMA interrupt request occurs when the transfer counter underflows 3 DMA transfer factor The DMA transfer factor can be selected from the following 31 factors falling edge two edges of INT0 INT1 INT2 pin timer AO interrupt request through timer A4 interrupt request UARTO transmission NACK SS interface 0 transmission interrupt request UARTO reception ACK SS interface 0 reception interrupt request UART1 transmission NACK SS interface 1 transmission interrupt request UART1 reception ACK SS interface 1 reception interrupt request UART2 transmission NACK interrupt re quest UART2 reception ACK interrupt request UARTS transmission NACK interrupt request UART3 reception ACK interrupt request USBO USB1 USB2 USB3 function interrupt request A D conversion interrupt reques
321. n receive buffer register a Checking error b8 b15 b7 b0 UARTO receive buffer register Address 03AF16 03AE16 UORB UART1 receive buffer register Address 036F 16 036E16 U1RB b0 UART2 receive buffer register Address 033F16 033E16 U2RB b7 UAI UARTS receive buffer register Address 032F16 032E16 U3RB Overrun error flag 0 No overrun error 1 Overrun error found Processing after reading out received data Output H to the SS port on the transmitter side IC Figure 2 5 13 Set up procedure of reception in serial interface special function master mode with clock delay 2 Rev 2 00 Oct 16 2006 page 101 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Serial Interface Special Function 2 5 4 Operation of Serial Interface Special Function transmission in slave mode without delay In transmitting data in serial interface special function slave mode choose functions from those listed in Table 2 5 3 Operations of the circled items are described below Figure 2 5 14 shows the operation timing and Figures 2 5 15 and 2 5 16 show the set up procedures Table 2 5 3 Choosed functions Transfer clock Internal clock f1 fs f32 SSi port function SSi function disabled source External clock CLKi pin enable O SSi function enabled CLK polarity Output transmission data at Clock phase set O Without clock delay the falling edge of the transfer clock W
322. n result During 8 bit mode When read the content is indeterminate POPPE ORDO REC RPR RE ORR PREC RRO P Setting A D conversion start flag b7 bo 0 AD control register 0 Address 03D616 ADCONO __________________A D conversion start flag 0 A D conversion disabled hc Stop A D conversion Figure 2 9 7 Set up procedure of one shot mode with an external trigger selected Rev 2 00 Oct 16 2006 page 221 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2 9 4 Operation of A D Converter in repeat mode In repeat mode choose functions from those listed in Table 2 9 4 Operations of the circled items are described below Figure 2 9 8 shows timing chart and Figure 2 9 9 shows the set up procedure Table 2 9 4 Choosed functions Operation clock Divided by 4 fap divided AD by 3 fap divided by 2 fap fap Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Trigger for starting Software trigger A D conversion Trigger by ADTRG Sample amp Hold Not activated Activated Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start operating 2 After the first conversion is completed the content of the successive comparison register conversion result is transmitted to AD register i The A D conversion interrupt request bit does not go to 1 3 The A D converter continues operating until the A
323. n s port direction register to 0 Note 3 To start count in one shot timer mode do not use an extrenal trigger input Figure 2 2 5 Timer A related registers 4 Rev 2 00 Oct 16 2006 page 11 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 2 Operation of Timer A timer mode In timer mode choose functions from those listed in Table 2 2 1 Operations of the circled items are described below Figure 2 2 6 shows the operation timing and Figure 2 2 7 shows the set up procedure Table 2 2 1 Choosed functions Count source Internal count source f1 fs fs2 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAiiN pin is at L level Performs count only for the period in which the TAiiN pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Ai interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow Start count again a a Counter content hex Time Cleared to 0 by l software Set to 1 by software Cleared to 0 when inte
324. n selected 33 AD cycles for 10 bit resolution or 28 oAD cycles for 8 bit resolution No Sample amp Hold function 59 oAD cycles for 10 bit resolution or 49 dAD cycles for 8 bit resolution Table 2 9 1 Conversion time every operation clock Frequency select bit 1 0 0 Frequency select bit 0 0 1 A D converter s OAD fAD 3 OAD fAD 4 OAD fAD 2 operation clock Min conversion 8 bit mode 28 X AD cycles Note 1 10 bit mode 33 X AD Min conversion 8 bit mode 11 2us 5 6us time Note 2 10 bit mode 13 2us 6 6us Note 1 The number of conversion cycles per one analog input pin Note 2 The conversion time per one analog input pin when fAD f XIN 10 MHz Rev 2 00 Oct 16 2006 page 213 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter 4 Functions selection a Sample amp Hold function Sample amp Hold function samples input voltage when A D conversion starts and carries out A D con version on the voltage sampled When A D conversion starts input voltage is sampled for 3 cycles of the operation clock When the Sample amp Hold function is selected set the operation clock for A D conversion to 1 MHz or higher b 8 bit A D to 10 bit A D switching function Either 8 bit resolution or 10 bit resolution can be selected When 8 bit resolution is selected the 8 higher order bits of the 10 bit A D are subjected to A D conversion The equations for 10 bit resolu tion a
325. n supplied power to the bus Default State This is the state where the reset signal has been received from the host CPU It is responded as default address 0 This is the unconfigured state configuration 0 Address State This is the state which the SET_ADDRESS standard device request has been received and a device address other than 0 has been assigned This is the unconfigured state Configuration 0 Configured State This is the state which endpoint 0 has been received the SET_CONFIGURATION standard device request and the device has been configured Suspend State This is the state which inactive state followed 3ms or more If a bus active has been detected the state shifts to the former one In the M30245 group when a bus reset is detected in suspend state detects bus active and shifts to the former state then detects the bus reset 7 USB Related Registers Memory Mapping The USB related registers memory mapping is shown in Figure 2 8 8 The list of USB related registers items is shown in Table 2 8 2 Rev 2 00 Oct 16 2006 page 135 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function Attached state Hub Hub Deconfigured Configured Suspend detected USB suspend interrupt Powered a Suspend state Resume detected USB resume interrupt USB bus reset detected USB reset interrupt USB bus reset detected USB reset interrupt Suspend detected USB suspend interrupt Default a Suspend
326. nabling the Vbus detect interrupt Use the following procedure when enabling the Vbus detect func tion 1 Enable a Vbus detect by setting 1 to Vbus detect enable bit bit 7 at address 001F 16 2 Clear the Vbus detect interrupt request by setting 0 to Vbus detect interrupt request bit bit 3 at address 005C 16 3 Enable the Vbus detect interrupt by setting the Vbus detect interrupt priority level greater than 0002 bit 0 to 2 at address 005C 16 Rev 2 00 Oct 16 2006 page 149 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 8 3 USB Interrupt The USB related interrupts include USB suspend interrupt USB resume interrupt USB reset interrupt USB endpoint 0 interrupt USB function interrupt and USB SOF interrupt 1 Related Registers USB function interrupt status register This register is used to judge the USB function interrupt factor This is the read only register which indicates each interrupt request state of endpoint x x 1 4 IN interrupt endpoint x x 1 4 OUT inter rupt and error interrupt On occurrence of an interrupt request this is set to 1 Each interrupt status flag can be cleared to 0 by setting 1 to the corresponding bit of USB function interrupt clear register Endpoint 1 IN Interrupt Status Flag Endpoint 2 IN Interrupt Status Flag Endpoint 3 IN Interrupt Status Flag Endpoint 4 IN Interrupt Status Flag These flags indicate endpoint x x 1 4 IN inte
327. ncluded in the transmit data it is retransmitted on next IN token When the M30245 group was stalling STALL handshake is returned When the transmit data are not available in IN FIFO NAK handshake is returned Bulk OUT Transfer In bulk OUT transfer which data are transmitted from the host CPU to the device OUT transactions are repeated The M30245 group has normally received a data packet and then returns ACK handshake Normal receiving is the status which is free of any bit stuffing error or CRC error and which data PID have been correctly received When during the handshake phase of each transaction the host PC has normally received ACK packet issued by the M30245 group it toggles DATAO and DATA1 of data packet on next data phase This serves to ensure handshake The M30245 group executes the following responses when the data are not received normally When the received OUT token is destroyed response is not executed When the M30245 group was stalling STALL handshake is returned Also when the packet which is exceeding receivable data size is transmitted STALL handshake is returned When inconsistency of the sequence bits is detected in the received data ACK handshake is returned When OUT FIFO of the M30245 group could not receive full data NAK handshake is returned For details refer to USB2 0 specification Bulk IN Bulk OUT Idle state Idle state NAK STALL
328. nctions Usage M30245 Group 2 Protect 2 1 Protect 2 1 1 Overview Protect is a function that causes a value held in a register to be unchanged even when a program runs away The following is an overview of the protect function 1 Registers affected by the protect function The registers affected by the protect function are a System clock control registers 0 1 addresses 000616 and 000716 b Processor mode registers 0 1 addresses 000416 and 000516 c Frequency synthesizer related registers address 03DB16 to O3DF 16 The values in registers a through c cannot be changed in write protect state To change values in the registers put the individual registers in write enabled state 2 Protect register Figure 2 1 1 shows protect register Protect register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset XX XXxIlol PRCR 000A16 XXXXX0002 Bit symbol Enables writing to system clock 0 Write inhibited control registers 0 and 1 addresses 1 Write enabled 000616 and 000716 and frequency synthesizer registers addresses 03DB16 to O3DF 16 Enables writing to processor mode 0 Write inhibited registers 0 and 1 addresses 000416 1 Write enabled and 000516 Reserved Must always be set to 0 lo o Nothing is assigned When write set 0 When read their contents are indeterminate Figure 2 1 1 Protect register Rev 2 00 Oct 16 2006 page 4 of 354 7tENESAS REJ09B0340 0200 M302
329. ncy of BCLK or set a soft ware wait Using the RDY feature allows you to connect memory having the timing that precludes con nection though you set software wait 1 Using software wait Set software wait for the external memory areas by using either of bits CSOW through CS3W of the chip select control register address 000816 or the chip select expansion register address 001B16 When using the RDY signal the corresponding CSOW through CS3W bit must be set to 0 Bits CSOW through CS3W of the chip select control register correspond to chip select CSO through CS3 respectively If these bits are set to 1 the read bus cycle results in one cycle of BCLK and the write bus cycle results in two cycles of BCLK if these bits are set to 0 the read write cycle results in two three or four cycles of BCLK according to the chip select expansion register setting When the corresponding bit of the chip select control register is set to O the chip select expansion register setting becomes valid When this bit is set to 1 set the corresponding bit of the chip select expansion register to O02 When reset the value of the chip select control register and the chip select expansion register is set to 0016 These control bits do not affect the SFR area and the internal ROM RAM area Figure 4 4 1 shows software wait and bus cycle and Figure 4 4 3 shows relation of processor mode and the wait bit CSIW CSIEW Table 4
330. nd 1 and frequency synthesizer related registers 1 Write enabled Setting frequency synthesizer control register b7 bO 0 Frequency synthesizer control register Address 03DC16 FSC Frequency Synthesizer enable bit 0 Disabled Setting the interruppt for return from suspend mode Note1 2 bo USB resume interrupt control register Address 005816 RSMIC ani Interrupt priority level select bit b2 b1 bO 0 0 0 Level 0 interrupt disabled 00 1 Level 1 0 10 Level 2 011 Level3 100 Level 4 101 Level5 110 Level 6 111 Level 7 Interrupt request bit 0 Interrupt not requested Note 1 Confirms that the interrupt enable flag l of flag register is set to 0 before setting the interrupt to higher priority level than the USB suspend interrupt The interrupt should be higher priority level than the USB suspend interrupt when those event are returned from the suspend mode by process key input interrupt etc other than the USB resume interrupt Note 2 When the interrupt is not used to clear the stop mode the interrupt should be disabled by setting W the interrupt priority level to 0 Continued to the next page Figure 2 8 28 USB suspend interrupt request processing routine 1 Rev 2 00 Oct16 2006 page 166 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function Continued from the previous page
331. nd 8 bit resolution are given below 10 bit resolution Vref X n 210 Vref X0 5 210 n 1 to 1023 0 n 0 8 bit resolution Vref X n 28 Vref X 0 5 210 n 1 to 255 0 n 0 c A D conversion by external trigger The user can select software or an external pin input to start A D conversion d Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A D converter To decrease the microcomputer s power consumption cut Vref To carry out A D conversion start A D conversion 1 us or longer after connecting Vref 5 Input to A D converter and the relation of direction register To use the A D converter set the direction register of the relevant port to input 6 Pins related to A D converter a ANo pin through AN7 pin Input pins of the A D converter b AVcc pin Power source pin of the analog section c VREF pin Input pin of reference voltage d AVss pin GND pin of the analog section e ADTRG pin Trigger input pin of the A D converter 7 A D converter related registers Figure 2 9 1 shows the memory map of A D converter related registers and Figures 2 9 2 and 2 9 3 show A D converter related registers Rev 2 00 Oct 16 2006 page 214 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 A D Converter 004B16 AD conversion interrupt control register ADIC Ax 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03C D16 03CE16
332. ng e CLR_FORCE_STALL bit This bit controls clearing of the FORCE_STALL flag When this bit is written to 1 the FORCE_STALL flag is cleared to 0 e SEND_STALL bit This bit controls the STALL response to the host CPU To responds with STALL when an invalid request has received from the host CPU set this bit to 1 simultaneously as CLR_OUT_BUF_RDY bit is set to 1 When this bit is set to 1 the USB function control unit transmits to the host CPU the STALL handshake concerning all the IN OUT transactions When a new valid SETUP packet is received clear a data by writing 0 in this bit e DATA_END_MASK bit This bit controls whether the DATA_END flag clear becomes an endpoint 0 interrupt factor When this bit is set to 1 clearing the DATA_END flag does not become an endpoint 0 interrupt factor This bit is set to 1 at the time of reset The configuration of USB endpoint 0 control and status register is shown in Figure 2 8 32 Rev 2 00 Oct 16 2006 page 172 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB Endpoint 0 Control and Status register b15 b8 b7 bO b7 Symbol When reset 00 on oo EEEE e EPOCS 200016 Bit Symbol Bit Name Function No setup packet or data set ready for unload Setup packet or data set ready for unload No data set ready for transmit Data set ready for transmit POCSRO
333. ng A D conversion start flag b7 bO 0 AD control register 0 Address 03D616 A D conversion start flag 0 A D conversion disabled Stop A D conversion Figure 2 9 13 Set up procedure of repeat sweep 0 mode Rev 2 00 Oct 16 2006 page 227 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter 2 9 7 Operation of A D Converter in repeat sweep mode 1 In repeat sweep 1 mode choose functions from those listed in Table 2 9 7 Operations of the circled items are described below Figure 2 9 14 shows ANi pin s sweep sequence Figure 2 9 15 shows timing chart and Figure 2 9 16 shows the set up procedure Table 2 9 7 Choosed functions Operation clock AD Divided by 4 fap divided Trigger for starting Software trigger by 3 faD divided by 2 fAD A D conversion AD Trigger by ADTRG Resolution 8 bit 10 bit Sample amp Hold Not activated Analog input pin Activated Ano 1 pin ANo and AN1 2 pins ANo to AN2 3 pins ANo to AN8 4 pins Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo pin 2 After the A D conversion on voltage input to the ANo pin is completed the content of the successive comparison register conversion result is transmitted to AD register 0 3 Every time the A D converter carries out A D conversion on a selected analog input pin the A D converter carries out A D co
334. ng edge of the next BCLK 7 Each bus returns from the high impedance state to the former state at the falling edge of the next BCLK As given above each bus invariably gets in the high impedance state while the HLDA output is L Also M30245 does not relinquish buses during a bus cycle That is if a Hold request comes in during a bus cycle the HLDA output become L after that bus cycle finishes In the Hold state the state of each terminal becomes as follows Address bus Ao to A19 High impedance state The case in which A16 to A19 are used as ports P40 to P43 64K byte address space in microprocessor mode and in memory expansion mode too falls under this category e Data bus Do to D15 High impedance state The case in which Ds to D15 are used as ports P10 to P17 8 bit external bus width in microprocessor mode and in memory expansion mode too falls under this category RD WR WRL WRH BHE High impedance state ALE An internal clock signal having the same phase as BCLK is output CSO to CS3 High impedance state The case in which ports are selected by the chip selection control register too falls under this category Figure 4 5 1 shows an example of relinquishing external buses Rev 2 00 Oct 16 2006 page 347 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 External Buses Timing chart BCLK HOLD HLDA Indeterminate ALE CSn Bus released 1 2 3 4 5 6 7 8 1 A
335. nnn nnna 218 2 9 3 Operation of A D Converter in one shot mode an external trigger Selected s cesseeeeee 220 2 9 4 Operation of A D Converter in repeat MOE cceseeeseeeeeeeeeeseeeeeeeeeeeseaeesnseeeesesaeseseeeeeeseesenneeenes 222 2 9 5 Operation of A D Converter in single SWEEP mode ecceeseeseeeeeeeeeeeeseeeeneeneesseaesnseeeeeseneseneeeeeees 224 2 9 6 Operation of A D Converter in repeat SWEEP mode O cceseccesseeeeeeeeeesneeeeneneeeeeaesenseeeeseaesenseeeeneas 226 2 9 7 Operation of A D Converter in repeat SWEEP mode 1 cceseccsseeeeeeeeeeeseeeeeeeeeeeneaeseneeeeessesenseeeneas 228 2 9 8 Precautions for A D Converter cccccssecceeeseeeeeeeenneeeeeeeenseaeeeeensnaaeseeensaaeseensnaaeseeensesaeeeensnnneeeeenenes 230 2 9 9 Method of A D Conversion 10 bit mode ccccesseeceeeeseeeeeeensnneeeeeenseaaeceensneaeeeeensecaeeesenseeeeeeennes 231 2 9 10 Method of A D Conversion 8 bit mode cccssseceeeeseeeeeeeneneeeseeenseaeeeensneaeseeenseneseeenneeeeeeeneees 233 2 9 11 Absolute Accuracy and Differential Non Linearity Error ccssccccesseeeeeeeeseeeeeeeeeseeeeeeenseeneeeeennees 235 2 9 12 Internal Equivalent Circuit of Analog Input ccccccceceeeeeeeseeeeeeeeeeeeeeeeseeeeneeeeesseaeseseeeeeseneseseeeeeeeas 237 2 9 13 Sensor s Output Impedance under A D Conversion reference ValUe sccceesseeeeeeseees 238 2 10 DMAC US ag ei ics sates ootecsces t
336. nous transfer setting Transmit Data Preparation The endpoint x IN packet data preparation procedure in the isochronous transfer is same as the bulk transfer Refer to Transmit Data Preparation of 2 Bulk Transfer Endpoints 1 to 4 Transmit Continuous transfer is valid for the bulk transfer only Transmit Operation A packet whose PID is DATAO is transmitted to the IN token from the host CPU When IN token is received from the host CPU while there are no data in IN FIFO an empty packet with O data length is automatically transmitted an underrun error occurs and the UNDER_RUN flag is set to 1 When the UNDER_RUN flag is set to 1 while the error interrupt is enabled by USB function interrupt enable register an error interrupt request occurs INTST8 is set to 1 When IN token is received from the host CPU while there are packet data in IN FIFO data are transmitted At this time the IN FIFO status is updated and the endpoint x IN interrupt request oc curs In isochronous transfer timing in which data are transmitted to the IN token from the host CPU differs by setting of ISO_UPDATE bit When ISO_UPDATE bit is set to 1 setting 1 to SET_IN_BUF_RDY bit which is the packet control signal is delayed until the next SOF packet is received so that transmission of the IN FIFO data packet is delayed At this time whether there are actual packet data or not it is replied to the IN token that ther
337. nsmission NACK A D conversion UARTO UART2 Bus collision detection H Start stop condition detection UART1 UARTS Bus collision detection Start stop condition detection Key input interrupt Processor interrupt priority level IPL Interrupt enable flag I flag High Priority of peripheral I O interrupts if priority levels are same Address match Watchdog timer DBC NMI Reset Figure 2 15 5 Interrupts resolution circuit Rev 2 00 Oct 16 2006 page 271 of 354 REJ09B0340 0200 RENESAS Interrupt request accepted M30245 Group 2 Multiple Interrupts 2 15 2 Multiple Interrupts Operation The state when control branched to an interrupt routine is described below The interrupt enable flag I flag is set to 0 the interrupt is disabled The interrupt request bit of the accepted interrupt is set to O The processor interrupt priority level IPL is assigned to the same interrupt priority level as as signed to the accepted interrupt Setting the interrupt enable flag I flag to 1 within an interrupt routine allows an interrupt request as signed a priority higher than the IPL to be accepted An interrupt request that is not accepted because of low priority will be held If the condition following is met when the REIT instruction returns the IPL and the interrupt priority
338. nsmission completed CTS RTS disable bit 1 CTS RTS function disabled Data output select bit Note 2 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to 0 Note 2 UART2 transfer pin TxD2 P70 is N channel open drain output C It cannot be set to CMOS output Setting UARTi special mode register 3 i 0 to 3 b7 b0 UARTIi ial mod ister 3 TITI hE UISMR3 Address 03A 36516 033516 32516 SS port function enable bit 1 SS function enable Clock phase set bit 1 With clock delay Serial input port set bit 0 Select TxDi and RxDi Master mode Continued to the next page Figure 2 5 12 Set up procedure of reception in serial interface special function master mode with clock delay 1 Rev 2 00 Oct 16 2006 page 100 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Continued from the previous page Setting UARTI transmit receive control register 1 i 0 to 3 UARTI transmit receive control register 1 UiC1 Address 03AD16 36D16 033D16 32D16 UARTI transmit interrupt cause select bit 0 UA 0 Transmit buffer empty TI 1 RTi cont
339. nsmission in master mode WITHOUT Celay sidni a cadet eeeecencetee testi ctinenssecdateeeseceetuecesstbdiwecvcacuatecesenccceecceeeceteccesecdaeesennse 94 A 1 2 5 3 Operation of Serial Interface Special Function reception in master mode with Clock delay r r wees castew cece aa eaa a a a aa Ea aS Tae ines cau adaa a a aa Paar a aaraa aad 98 2 5 4 Operation of Serial Interface Special Function transmission in slave MOdEC cceseeseseeeeeee 102 WITHOUT delay E anea aaen A E AEE A AE A T TS 102 2 5 5 Operation of Serial Interface Special Function reception in slave mode With cssseeeee 106 Clock delay EEE E A A E A teatuaauensbaveees 106 2 6 Serial sound interface ssssssssnnnnnnererernnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn 110 2 6 51 EE T E EE E E E E E EE E E A E I E sacs adoLeensesaooouneets 110 2 6 2 Example of Serial Sound Interface operation ccseeeeeseeseseeeeeeseeeeseeeeeeseeeeseaeeeneeeeesenaeeneeeeeeeas 116 2 6 3 Precautions for Serial Sound Interface cceeseeceeeeeeeeeeeeeeseeeeeeeeneeeseeeesnaeeseenennaeseeensaaeseeeeenes 120 2 7 Frequency synthesizer PLL cciissccnccscescisnciasersersuanecciavensnanscsewsiesaeinsnneauesrerasaucntuerers 121 TW OT D E ETE EE EE E E Do E EE O E AN T A EEN P AN E E E I E 121 2 7 2 Operation of frequency synthesizer cccceeecceceeeeeeceeeeseeeeseeeneeeeseeeeseceeseeeesnaeseeseeseaeseeenenaeseeneeenes 124 2 7 3 Precautions f
340. nsmit receive mode register UOMR 03A916 032916 UARTS bit rate generator U3BRG UARTO bit rate generator UOBRG O3AA16 032A16 032B16 UARTS transmit buffer register U3TB 03AB16 UARTO transmit buffer register UOTB 03AC16 032C16 UARTS transmit receive control register 0 U3C0 UARTO transmit receive control register 0 U0CO 03AD16 032D16 UARTS transmit receive control register 1 U3C1 UARTO transmit receive control register 1 U0C1 03AE16 032E16 032F16 UARTS receive buffer register U3RB O3AF 16 UARTO receive buffer register UORB R 033416 UART2 special mode register 4 U2SMR4 033516 033616 UART2 special mode register 3 U2SMR3 UART2 special mode register 2 U2SMR2 033716 UART2 special mode register 1 U2SMR 033816 UART2 transmit receive mode register U2MR 033916 UART2 bit rate generator U2BRG 033A16 033B16 UART2 transmit buffer register U2TB 033C16 UART2 transmit receive control register 0 U2CO 033D16 UART2 transmit receive control register 1 U2C1 033E16 033F16 UART2 receive buffer register U2RB Figure 2 5 1 Memory map of serial interface special function related registers Rev 2 00 Oct 16 2006 page 87 of 354 REJ09B0340 0200 7tENESAS M30245 Group 2 Serial Interface Special Function UARTIi transm
341. nt register b15 b8 b7 bO b7 olo 0 Symbol Address When reset EPOWC 029C16 000016 Bit Symbol Bit Name Function i i The number of bytes of the current EPOWC7 0 Receive byte count data set in EPO OUT FIFO Reserved Must always be 0 Figure 2 8 34 USB endpoint 0 OUT write count register Rev 2 00 Oct 16 2006 page 174 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 Control Transfer Endpoint 0 Receive The endpoint 0 receives the packet data from the host CPU in the setup stage or the data stage by the control write transfer When the receive of a valid SETUP packet or a data packet completes the SETUP flag and the OUT_BUF_RDY flag are automatically set to 1 and the number of bytes of receive data are set in USB endpoint 0 OUT write count register address 029C16 Read the data of only amount equal to received byte count from the endpoint 0 OUT FIFO Every time that one byte data is read from OUT FIFO the internal write pointer is automatically decremented by 2 in word access and by 1 in byte access The contents of internal write pointer cannot be read When the data read from OUT FIFO is completed simultaneously set 1 to CLR_OUT_BUF_RDY bit and SET_DATA_END bit When the SETUP packet is received clearing the SETUP flag by setting 1 to CLR_SETUP bit is required Therefore the OUT_BUF_RDY flag is c
342. nterface activation routine for 32 bits et AAA Ak iA A AAA AE EERE AREA Ek ifdef OUT_Q_BIT_NO_32 ssitmr0 0x01 SSIEN 1 ssi1mr0 Oxc1 32bit MSB justified ssitmr1 0x21 SCK neg WS neg MSB first normal ssitmr0 0xc7 32bit Tx enable Rx enable MSB justified endif Rev 2 00 Oct 16 2006 page 117 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Serial sound interface Serial Sound Interface timing 1 Fs 48 kHz or 44 1kHz WSDLY 1 SCK Min 64 x Fs 2 8MHz Max192 x Fs 9 2MHz SCKP 1 WSP 0 SCKP 0 WSP 0 SCKP 1 WSP 1 SCKP 0 WSP 1 XMTFMT 0 MSB first XMTFMT 1 LSB first Serial Sound Interface timing 2 Fs 48 kHz or 44 1kHz SCKP 1 WSP 0 SCKP 0 WSP 0 v SCKP 1 WSP 1 mooo ar v SCKP 0 WSP 1 XMTFMT 0 MSB first XMTFMT 1 LSB first Figure 2 6 5 Example of Serial Sound Interface transmit timing Rev 2 00 Oct 16 2006 page 118 of 354 REJ09B0340 0200 REN Pa M30245 Group 2 Serial sound interface Serial Sound Interface timing 3 SCKP 1 WSP 0 SCKP 0 WSP 0 SCKP 1 WSP 1 SCKP 0 WSP 1 RFMT1 0 MSB first RFMT1 1 LSB first Serial Sound Interface timing 4 Fs 48 kHz or 44 1kHz SCKP 1 WSP 0 SCKP 0 WSP 0 SCKP 1 WSP 1 mog gS v SCKP 0 WSP 1 RFMTO 0 MSB first RFMTO 1 LSB first
343. nterrupt This interrupt is used for detection of inactivity on the USB bus line The suspend status flag of USB power management register USBPM address 028216 is set when the USB function control unit has detected suspend signal on the USB bus line or not detected any bus activity on the D D line for at least 3ms Simultaneously the USB suspend interrupt occurs When using the USB suspend interrupt set the interrupt priority level at USB suspend interrupt control register SUSPIC address 005616 6 USB Resume Interrupt This interrupt is used for detection of activity on the USB bus line while the device is in suspend state When the USB function control unit has received resume signal on the USB bus line or detected activity on the D D line the interrupt request occurs and the USB resume interrupt occurs by setting 1 to resume interrupt request bit of USB resume interrupt control register RSMIC address 005816 When using the USB suspend interrupt set the interrupt priority level at the RSMIC Rev 2 00 Oct 16 2006 page 156 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 7 USB SOF Start of Frame Interrupt This interrupt is valid to control the isochronous transfer When a valid SOF PID is detected receive of an SOF packet is recognized and an interrupt request occurs The frame number 11 bits of the SOF packet received from the host is automatically stored in USB frame number register In isochronou
344. nterrupt 1 0 Interrupt disaled enable bit 1 enabled Nothing is assigned Write O when writing to these bits If read the value is indeterminate Address match interrupt register i i 0 1 b19 b16 b15 b8 Symbol Address When reset b3 b0 bz bo b7 RMADO 001216 to 001016 X0000016 RMAD1 001616 to 001416 X0000016 1 Address setting register for address match interrupt 0000016 to FFFFF16 Nothing is assigned Write O when writing to these bits If read the value is indeterminate Figure 2 13 3 Address match interrupt related registers Rev 2 00 Oct16 2006 page 259 of 354 LKENESAS REJ09B0340 0200 an M30245 Group 2 Address Match Interrupt 2 13 2 Operation of Address Match Interrupt The following is an operation of address match interrupt Figure 2 13 4 shows the set up procedure of address match interrupt and Figure 2 13 5 shows the overview of the address match interrupt handling routine Operation 1 The address match interrupt handling routine sets an address to be used to cause the ad dress match interrupt register to generate an interrupt 2 Setting the address match enable flag to 1 enables an interrupt to occur 3 An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed C Setting address match interrupt register Address match interrupt register 0 Address 00121
345. nterrupt control register SORIC 036616 UART1 special mode register 3 U1SMR3 UART1 special mode register 2 U1SMR2 036716 004D16 UARTS transmit NACK interrupt control register S3TIC UART1 special mode register 1 U1SMR 036816 UART1 transmit receive mode register U1MR 036916 004F16 UART2 transmit NACK interrupt control register S2TIC UART1 bit rate generator U1BRG 036A16 036B16 UART1 transmit buffer register U1TB 005116 UART1 transmit NACK SSI1 interrupt control register S1TIC 036C16 UART1 transmit receive control register 0 U1C0 036D16 005316 UARTO transmit NACK SSIO interrupt control register SOTIC UART1 transmit receive control register 1 U1C1 036E16 036F16 005516 UARTS receive ACK interrupt control register S3RIC UART1 receive buffer register U1 RB 032416 IN IN SS UARTS special mode register 4 USSMR4 7 03A416 UARTO special mode register 4 UOSMR4 03A516 032516 03A616 UARTO special mode register 2 UOSMR2 032616 UARTS special mode register 3 U3SMR3 UARTS special mode register 2 U3SMR2 03A716 032716 UARTS special mode register 1 U3SMR UARTO special mode register 3 UOSMR3 UARTO special mode register 1 UOSMR 03A816 032816 UARTS transmit receive mode register USMR UARTO tra
346. ntrol transfer in operation by being transmitted to one transaction The packet after STALL handshake is regarded as the start of new control transfer Set this flag to 0 by writing 1 to CLR_FORCE_STALL bit e SETUP_END flag This flag shows the interrupt in control transfer This flag is set to 1 when at least one of the following conditions occurs Transmission of the data which had amount of data set by setup phase during data phase process ing is completed The status phase is started before the DATA_END flag is set Anew SETUP packet is received before status phase is completed When this flag is set to 1 and transmit data to the host CPU exists IN_BUF_RDY bit is cleared to 0 and the IN FIFO data is destroyed Discontinue access to FIFO and process the preceding setup Also when a new SETUP packet is received right after the SETUP_END flag is set to 1 when the next new SETUP packet is received before the data phase or the status phase is completed the SETUP flag and the OUT_BUT_RDY flag in addition to the SETUP_END flag are set to 1 indicat ing that anew SETUP packet data exists in OUT FIFO Set the SETUP_END flag to 0 by writing 1 to CLR_SETUP_END bit e CLR_OUT_BUF_RDY bit This bit controls clearing of the OUT_BUF_RDY flag This bit is set to 1 after reading the data packet from OUT FIFO When this flag is written to 1 the OUT_BUF_RDY flag is cleared to O When
347. nversion on only one unselected pin and then the A D converter carries out A D conver sion from the ANo pin again The conversion result is transmitted to the corresponding AD register i every time conversion on a pin is completed The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until software goes the A D conversion start flag to 0 When AN0 is selected When ANo AN1 are selected When ANo to AN2 are selected When ANo to AN3 are selected Time Time Converted analog input pin Converted analog input pin Converted analog input pin Converted analog input pin Figure 2 9 14 ANi pin s sweep sequence in repeat sweep mode 2 Conversion result is transfered to AD i i 1 Start ANo pin conversion register 0 3 Consecutive conversion A D conversion 4 A D i 8 bit resolution 8 bit resolution 8 bit resolution 8 bit resolution conversion 28 oan cycles 28 gap cycles i 28 gan cycles 28 gap cycles is complete 10 bit resolution 10 bit resolution 10 bit resolution 10 bit resolution i 33 ap cycles i 33 aD cycles 33 gad cycles 33 aD cycles a gt lt gt on UU i Set to 1 by software Cleared to 0 by software A D 4 M i conversion start flag o
348. o start a down count 2 With a count in progress writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting 3 Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting The watchdog timer resumes count ing after returning from the execution of the WAIT instruction or from the stopped state 4 If the watchdog timer underflows it is initialized to 7FFF16 and continues counting At this time a watchdog timer interrupt occurs 1 Start count 3 In stopped state or WAIT 4 Generate i 1 instruction is executing etc watchdog timer 2 Write operation i interrupt lt 7FFF16 E E EE EE i 000016 Write signal to the H watchdog timer start register SE Figure 2 12 3 Operation timing of watchdog timer watchdog timer interrupt Rev 2 00 Oct 16 2006 page 256 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 Watchdog Timer Setting watchdog timer control register Watchdog timer control register Address 000F 16 Reserved bit Must always be 0 Prescaler select bit 0 Divided by 16 1 Divided by 128 a Setting watchdog timer start register b0 Ooo E Watchdog timer start register Address 000E16 WDTS nN J a The watchdog timer is initialized and starts counting with a write instruction to this register The
349. ode Result of A D conversion 02 01 00 10 30 Analog input voltage mV Optimal conversion characteristics in 8 bit mode VREF 5 12 V Output code Result of A D conversion 10 bit 1 0bit mode 8bit mode 17 5 37 5 Analog input voltage mV Note Differences in stepping points of output code for analog input voltage Figure 2 9 19 The level conversion characteristics of 8 bit mode and 8 bit A D converter Rev 2 00 Oct 16 2006 page 233 of 354 AS REJ09B0340 0200 RENES M30245 Group Table 2 9 11 Variation of the successive comparison register and Vref while A D conversion is in progress 8 bit mode Successive approximation register 2 A D Converter A D converter stopped MTE fvi 2 1st comparison VREF VREF naa V v 2 2048 2nd comparison 0 0 VREF VREF _ VREF 4 st comparison result VREF n9 1 4 2048 M ae vs gt 3rd comparison ns 1 0 0 0 0 0 ns 1 V VREF VREF VREF _ VREF 4_ 2nd comparison result 2 4 8 2048 ns 0 8th comparison ng ng n7 n e n5 n4 VREF 2048 V 4 VREF VREF VREF t 4 256 n9 n8 n7 n6 n5 n4 Conversion n2 0 complete This data transfers to bit 0 to bit 7 of AD register i Result of A D conversion Theoretical A D conversion characteristic of general 8 b
350. og input pin select bit Note 1 Invalid in Repeat mode b2 b1 b0 0 0 AN0 is selected A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in repeat mode AN2 is selected 1 0 1 AN3 is selected _________ 8 10 bit mode select bit 0 AN4 is selected 0 8 bit mode 1 0 1 ANs is selected 1 10 bit mode AN6 is selected AN7 is selected Frequency select bit 1 Note 2 Repeat mode is selected Note 1 n be ee Pi eE Trigger select bit 0 Software trigger ________________ Vref connect bit 1 Vref connected A D conversion start flag 0 A D conversion disabled Reserved bit Frequency select bit 0 Note 2 0 fap 3 or fAD 4 is selected 1 fAD or faD 2 is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode y Note 2 When f XIN is over 10 MHz the fab frequency must be under 10 MHz by dividing and set AD frequency to 10 MHz or lower Setting A D conversion start flag b7 b0 7 AD control register 0 Address 03D616 A D conversion start flag 1 A D conversion started Repeatedly carries out A D conversion on pins version selected through the A D input pin select bit Start A D conversio Transmitting conversion result to AD register i AD registerO Address 03C116 03C016 ADO AD register1 Address 030316 03C2i6 AD1 b8 AD register2 Address 03C516 03C416 AD2 b0 b7 AD
351. on is in progress transmission recep tion stops at the next data RTS function is a function to inform an external IC that RTS pin output level has changed to L when reception is ready RTS regoes to H at the first falling edge of the transfer clock When using clock asynchronous serial I O choose one of three types of CTS RTS functions e CTS RTS functions disabled CTS RTS pin is a programmable I O port e CTS function only enabled CTS RTS pin performs the CTS function e RTS function only enabled CTS RTS pin performs the RTS function b Data logic select function This function is to reverse data when writing to transmit buffer register or reading from receive buffer register c LSB MSB first select function This function is to choose whether to transmit receive data from bit 0 or bit 7 This is valid when the transfer data length is 8 bits long Choose either of the following e LSB first Data is transmitted received from bit 0 e MSB first Data is transmitted received from bit 7 d TxD RxD I O polarity reverse function This function is to reverse a polarity of TxD port output level and a polarity of RxD port input level Rev 2 00 Oct 16 2006 page 57 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 UART e Bus collision detection function This function is to sample the output level of the TxD pin and the input level of the RxD pin if their values are different then an interrupt request occurs The following ex
352. onous transfer While ISO_UPDATE bit 1 AUTO_FLUSH bit 1 and ISO bit INxCSR8 1 the USB function control unit at the time of detecting SOF packet on receiving from the host PC or on the artificial SOF operation automatically flushes old data packet inside the IN FIFO if both the IN _BUF_STS1 and the IN_BUF_STSO0 flags are 1 IN FIFO full state In isochronous transfer for double buffer use the AUTO FLUSH function ISO_UPDATE bit This bit controls the transmit timing of packet data in isochronous transfer The bit is valid only for the IN endpoints 1 to 4 in isochronous transfer While ISO_UPDATE bit 0 and ISO bit 1 the USB function control unit at the time of receiving of an IN token from the host CPU transmits one packet of the IN FIFO data if SET_IN_BUF_RDY bit of the corresponding endpoint has been set beforehand to 1 While ISO_UPDATE bit 1 and ISO bit 1 a packet control internal signal is not output to the transmit control circuit inside the USB function control unit even if SET_IN_BUF_RDY bit of the corresponding endpoint is set to 1 even if a data packet whose size is equal to the maximum packet size is written to the IN FIFO when AUTO_SET function is enabled Setting 1 to SET_IN_BUF_RDY bit which is the packet control signal is delayed until the next SOF is received so that transmission of the IN FIFO data packet is delayed The USB function control unit on det
353. ontinuous receive mode and in the continuous receive mode disable of endpoints 1 to 4 OUT Not available with endpoint 0 Rev 2 00 Oct 16 2006 page 182 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function 1 Related Registers USB endpoint x x 1 to 4 OUT control and status register OUT_BUF_STS1 OUT_BUF_STS0 flags These flags indicate OUT FIFO state At the time of reading the receive data from the host PC read these flags to confirm the OUT FIFO state When the OUT_BUF_STS1 and the OUT_BUF_STS0 flags are respectively set to O02 there are no data in OUT FIFO When they are respectively set to 102 there are only one buffer data in double buffer Invalid for single buffer When they are respectively set to 112 there are one buffer data in single buffer while there are two buffer data in double buffer When they are respectively set to 012 it is invalid These flags are updated when one of the following events occurs One valid buffer data is successfully received from the host One buffer data is successfully fetched from OUT FIFO CLR_OUT_BUF_RDY bit is set to 1 after read of one receive data from OUT FIFO completes When the AUTO_CLR function is enabled these flags are updated without CLR_OUT_BUF_RDY bit being set to 1 The OUT FIFO buffer data are flushed When FLUSH bit is set to 1 OVER_RUN flag This flag indicates occurrence of an overrun in isochronous transfer The bit
354. or C shown in Figure 2 9 23 has to be completed within a specified period of time With T as the specified time time T is the time that switches SW2 and SW3 are connected to O in Figure 2 9 23 Let output impedance of sensor equivalent circuit be RO microcomputer s internal resistance be R precision error of the A D converter be X and the A D converter s resolution be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode t Vc is generally Vc VIN 1 e C RO R And when t T Vc VIN x VIN VIN 1 X Y Y e c RO R _ X Y T in X C R0 R Y T Hence RO R Celn X Y With the model shown in Figure 2 9 24 as an example when the difference between VIN and Vc becomes 0 1LSB we find impedance RO when voltage between pins Vc changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 3 us in the A D conversion mode with sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 3 us R 7 8 KQ C 3 pF X 0 1 and Y 1024 Hence 0 3 X 10 RO 7 8 X10 3 0 X 108 3 0 X 10 e In ae 1024 Thus the allowable output impedance of the sensor circuit capable of thoroughly driving the A D con verter tu
355. or Frequency synthesizer ccescseeeeeeeeeee eee ee eee ee anne neaeeeeeeseeeeeneeaseneaeaeeeeeeseeeeeneennees 126 228 USB TN GUO WN svicscsccntcesdsonisesecccceadadasssassetensnemntendeanas uve aKa KA aai aaeei raaa shop aanas nadaa 127 2 8 1 OVErViIEW sorserien aa a eaa ai aed ee a ea ie olen aad 127 2 9 2 USB function Contolera are a Ea a e E eke ee A as 139 2 8 3 USB Interrupt A aa E E E E O E E 150 2 8 4 USB Operation Suspend Resume Function ss sssussseunenennenunneunnnnunnnnnnnununnunnnnnnnnnnnnnnnnnnnnnnnnnnn nanana 161 2 8 5 USB Operation Endpoint 0 ccsececeseeceeeeeeeeneeeeneeeeensaeeenseeeeeeaeseanneeeeseesasaaeseneeeeesnaeseaseaeeseesenseeeenes 169 2 8 6 USB Operation Endpoints 1 to 4 Receive ceccceecceseeeeeeeeeeeeneeeeeeeeeeanaeeeeeeeesseaeseneeeeeseaeeeeseeeeeeas 182 2 8 7 USB Operation Endpoints 1 to 4 Transmit cccceeceeseeeee sete eeeneeeeeeeeeesneeeeeeeeeesseaesenseeeeseeseeseeeeeeas 193 2 8 8 USB Operation Interface with DMAC Transfer ccs eccecesseeeeeeeeseceeeeeeeneeeeeeeeseaeseeeesaaeeeeneenes 207 2 8 9 Precautions for USB ieisisc os dececsesveceecleceteteccceeivvecseces a EKA REA seulees tefaandees deundeesSuyenlbeasaevauederevesbecestbeaeees 210 2 9 A D GONVGMIG E E A a E E 213 2 91 OVerviB W eea aeaa E a a AT eect ON ee a ee E aa aE EES 213 2 9 2 Operation of A D converter one shot mode ssssssssssssnnennnunnennnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn nnm
356. or cleared by software Shown in are bit symbols Te TCLK 2 n 1 fi The above timing applies to the following settings fi frequency of BRGi count source f1 f8 f32 Internal clock is selected n value set to BRGi e CLK polarity select bit 0 Figure 2 5 11 Operation timing of reception in serial interface special function master mode with clock delay REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Setting UARTi transmit receive mode register i 0 to 3 pz a UARTI transmit receive mode register UiMR Address 03A816 36816 033816 32816 Must be fixed to 001 Note Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to 0 Note Set the RxDi pin s port direction register to 0 when receiving Setting UARTIi transmit receive control register i 0 to 3 UARTI transmit receive control register 0 UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 bO 0 0 fi is selected 0 1 fs is selected 1 0 f32 is selected 11 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register tra
357. or mode Shift to single chip mode Set the port register Set the direction register Enter the wait mode or stop mode Note 1 This program does not work in external area Transfer a program to internal RAM and work on internal RAM Figure 4 6 1 Setting procedure to enter wait mode or stop mode Rev 2 00 Oct 16 2006 page 349 of 354 7tENESAS REJ09B0340 0200 THIS PAGE IS BLANK FOR REASONS OF LAYOUT Chapter 5 Standard Characteristics M30245 Group 5 Standard Characteristics 5 1 DC Standard Characteristics Standard characteristics described in this chapter are just examples and not guaranteed For rated values refer to Electrical Characteristics of Datasheet 5 1 1 Port Standard Characteristics Figures 5 1 1 to 5 1 4 show port standard characteristics Vec 3 3V Note 1 These characteristics are just examples and not guaranteed For rated values refer to Electrical Characteristics of Datasheet Figure 5 1 1 VOH IOH standard characteristics of ports PO to P10 except P63 P67 and P85 Vcc 3 3V Note 1 These characteristics are just examples and not guaranteed For rated values refer to Electrical Characteristics of Datasheet Figure 5 1 2 VoL loL standard characteristics of ports PO to P10 except P63 P67 and P85 Rev 2 00 Oct 16 2006 page 352 of 354 AS REJ09B0340 0200 RENES M30245 Group 5 Standard Characteristics VoH V Note 1 These characteristics are just examples and not g
358. orts A pass current flows in input ports that float When entering wait mode or stop mode set non used ports to input and stabilize the potential b Memory expansion mode and microprocessor mode When the MCU enters wait mode while operating in memory expansion mode or microprocessor mode a pin functioning as part of the address or data bus retains it s state on the bus before wait mode is entered Shift to single chip mode and output an arbitrary value in order to reduce current consumption By shifting to single chip mode a pin which was functioning as part of the bus be comes a general purpose port and can output an arbitrary value Set the port registers and direction registers after shifting to single chip mode this implies that any control pins CS WR RD etc being used for access of an external device be changed as well The same applies to stop mode c A D converter A current always flows in the VREF pin When entering wait mode or stop mode set the Vref connec tion bit to 0 so that no current flows into the VREF pin d Stopping peripheral functions In wait mode stop non used peripheral functions using the WAIT peripheral function clock stop bit However peripheral function clock fc32 does not stop so that the peripherals using fc32 do not con tribute to the power saving When the MCU running in low speed or low power dissipation mode do not enter WAIT mode with this bit set to 1 e External clock When usin
359. otect 5 Wait for 3ms to stabilize the frequency synthesizer 6 Check frequency synthesizer lock status bit If the frequency synthesizer is in unlock state waiting for 0 1ms and rechecking are repeated Setting of the USB function control unit 7 Set the USBC5 to 1 to enable the USB clock 8 Set the USB attach detach register to 0316 Port P90 is set as the power supply pin for pull up to the D line and set the USBC7 to 1 to enable the USB block For operation of the USB related registers a minimum 187 5ns of wait three cycles of BCLK is required Initialize the endpoint to be used after the USB function control unit being enabled The setting example of frequency synthesizer division is shown in Figure 2 8 15 The setup timing of frequency synthesizer after hardware reset is shown in Figure 2 8 16 The initialization procedure of frequency synthesizer and USB function control unit are shown in Figure 2 8 17 and Figure 2 8 18 The initialization procedure of endpoint is shown in Figure 2 8 19 and Figure 2 8 20 Rev 2 00 Oct 16 2006 page 143 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function FSD FF 16 0116 25516 FSP Frequency synthesizer prescaler FSM Frequency synthesizer multiplier FSD Frequency synthesizer divider Figure 2 8 15 Setting example of frequency synthesizer division RESET a Enable frequency synthesizer FSE Wait for 3ms c LS Enable USB clock L U
360. own as a signal line level Note 3 i 0to 3 Figure 2 4 13 Operation timing of transmission in UART mode used for SIM interface Rev 2 00 Oct 16 2006 page 74 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface L a Setting UARTi transmit receive mode register i 0 to 3 b7 bO of fojo o 4 UARTIi transmit receive mode register UiMR Address 03A816 36816 033816 32816 Serial I O mode select bit b2 b1 bO 1 0 1 Transfer data 8 bits long Internal external clock select bit 0 Internal clock Stop bit length select bit 0 One stop bit Odd even parity select bit Valid when bit 6 1 Must be 1 even parity in direct format Parity enable bit 1 Parity enabled TxD RxD I O polarity reverse bit Usually set to 0 Setting UARTI transmit receive control register 0 i 0 to 3 p7 UARTI transmit receive control register 0 Hoan aaa UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 b0 0 0 f1 is selected 0 1 fs is selected 1 0 f32 is selected 1 1 Inhibited Valid when bit 4 0 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS disable bit 1 CTS RTS function disabled Data output select bit 1 TxDi SDAi and SCLi pin is N channel open drain output Must be fixed to 0 in
361. p 2 A D Converter 2 9 A D Converter 2 9 1 Overview The A D converter used in the M30245 group operates on a successive conversion basis The following is an overview of the A D converter 1 Mode The A D converter operates in one of five modes a One shot mode Carries out A D conversion on input level of one specified pin only once b Repetition mode Repeatedly carries out A D conversion on input level of one specified pin c One shot sweep mode Carries out A D conversion on input level of two or more specified pins only once d Repeated sweep mode 0 Repeatedly carries out A D conversion on input level of two or more specified pins e Repeated sweep mode 1 Repeatedly carries out A D conversion on input level of two or more specified pins This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times 2 Operation clock The operation clock can be selected from the following fab divide by 2 fAD divide by 3 fAD and divide by 4 fAD The fAD frequency is equal to that of the CPU s main clock fAD f XIN Set the opera tion clock to 10 MHz or lower When f XIN is over 10 MHz the fAD frequency must be under 10 MHz by dividing 3 Conversion time Number of conversion for A D convertor varies depending on resolution as given Table 2 9 1 shows relation between the A D converter operation clock and conversion time Sample amp Hold functio
362. p 2 Clock Synchronous Serial I O petting UARTI transmit receive mode register i 0 to 3 b0 UARTIi transmit receive mode register o Taal UiMR Address 03A816 36816 033816 32816 Must be fixed to 001 Serial I O mode Set the RxDi pin s port direction register to 0 when receiving Internal external clock select bit 1 External clock Note Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to O C Note Set the corresponding port direction register to 0 Setting wi transmit receive control register i 0 to 3 b 20 UARTI transmit receive control register 0 ojoj 0 UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 b0 00 f1 is selected 01 fs is selected 1 0 f32 is selected 1 Inhibited CTS RTS function select bit Valid when bit 4 0 1 RTS function is selected Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS disable bit 0 CTS RTS function enabled Data output select bit Note 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is
363. part with puffer data The USB function control unit writes the receive data from the host PC in OUT FIFO sequentially by one packet size the maximum packet size set in the EPxOMP re ceives continuously until one buffer full or a short packet is received When the OUT token is received from the host CPU while SEND_ STALL bit is set to 1 STALL response is automatically returned When there is a packet space in OUT FIFO on receiving the OUT token from the host CPU in the current data toggle sequence bit the data are received and ACK response is returned At this time the OUT FIFO status is updated updates the OUT_BUF_STS1 and OUT_BUF_STS0 flags and data toggle sequence bit is toggled DATAO DATA1 or DATA1 DATAO Further the endpoint x OUT interrupt request occurs When there is a packet space in OUT FIFO on receiving the OUT token from the host CPU in the toggle which is different from the current data toggle sequence bit it is regarded that the ACK having responded for the packet previously received has dropped and therefore the host CPU has trans mitted the same data Only ACK response therefore is returned without receiving the data When the OUT token is received from the host CPU while there are already data in OUT FIFO and packet data cannot be received NAK response is automatically returned When a packet which size exceeds the maximum packet size is transmitted from the host CPU STALL response automati
364. pedance Figure 3 3 1 Operation timing of buzzer output Rev 2 00 Oct 16 2006 page 303 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications P Initialization of timer AO b4 b3 b7 b6 00 fi b15 b8 b7 bi ore ore _ b7 b0 TABSR lt KX Timer AO mode register TAOMR Address 039616 Selection of timer mode Pulse output function select bit 0 Pulse is not output TAQout pin is a normal port pin Gate function select bit 0 0 Gate function not available TAQin pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Timer AO register Count start flag Address 038016 Timer AO count start flag 1 Starts counting Count source period f XIN 16MHz_ f XcIN 32 768kKHz 62 5ns 500ns 2us 976 56us Count source TAO Address 038716 038616 Initialization of port P7 direction register PD7 b7 b0 Port P7 direction register Address 03EF16 Port P70 direction register 0 Input mode Buzzer ON b7 bo PT Ett yy YT Timer AO mode register Address 039616 TAOMR Pulse output function select bit 1 Pulse is output Port P70 is TAOOUT output pin Buzzer OFF b7 bo Timer AO mode register Address 039616 TAOMR Pulse output function select bit 0 Pulse is not output Figure 3 3 2 Set up procedure of buzzer output Rev 2
365. port XI LP arias 16 Port PO regi rees ED EE Interrupt priority level select bit Address 03E016 J PO Set higher value than the present IPL Key scan data Processor interrupt priority level IPL 0 Interrupt enable flag I 0 Setting interrupt except stop mode cancel Interrupt control register SiRIC i 0 2 3 Address 004A16 004216 005516 S13BCNIC Address 004316 TAiIC i 0 to 4 Address 005416 004516 004716 005716 005916 EPOIC Address 004616 ADIC Address 004B16 DMiIC i 0 to 3 Address 004C16 004E16 005016 005216 SITIC i 0 to 3 Address 005316 005116 004F 16 004D16 SUSPIC Address 005616 RSMIC Address 005816 RSTIC Address 005A 16 SOFIC Address 005B16 VBDIC Address 005C16 USBFIC Address 005D16 INTiIC i 0 to 2 Address 005F16 004416 005E16 b7 b0 b0 S1RIC Address 004816 bepp A 0 00 S02BcNIiC Address 004916 Interrupt priority level select bit Interrupt priority level select bit 000 Interrupt disabled 000 Interrupt disabled Reserved bit Ao Must always be set to 0 Canceling protect b0 Protect register Address 000A16 POPPP PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 and frequency synthesizer registers addresses 03DB16 to 03DF16 1 Write enabled Setting operation clock after returning from stop mode When operating with XIN after re
366. pt Impossible Impossible Impossible Key input interrupt Possible Possible Possible A D interrupt Note 3 Impossible Impossible UARTO transmit NACK Possible Note 1 Note 1 SSIO transmit interrupt Note7 UARTO receive ACK Possible Note 1 Note 1 SSIO receive interrupt Note 7 UART1 transmit NACK Possible Note 1 Note 1 SSI1 transmit interrupt Note7 UART1 receive ACK Possible Note 1 Note 1 SSI1 receive interrupt Note 7 UART2 transmit NACK interrupt Note 7 Possible Note 1 Note 1 UART2 receive ACK interrupt Note 7 Possible Note 1 Note 1 UARTS transmit NACK interrupt Note 7 Possible Note 1 Note 1 UARTS receive ACK interrupt Note 7 Possible Note 1 Note 1 Timer AO interrupt Possible Note 2 Note 4 Note 2 Timer A1 interrupt Possible Note 2 Note 4 Note 2 Timer A2 interrupt Possible Note 2 Note 4 Note 2 Timer A3 interrupt Possible Note 2 Note 4 Note 2 Timer A4 interrupt Possible Note 2 Note 4 Note 2 USB suspend interrupt Possible Possible Impossible USB resume interrupt Possible Possible Note 5 USB reset interrupt Possible Possible Impossible USB SOF interrupt Possible Possible Impossible USB Vbus detection interrupt Possible Possible Possible USB function interrupt Possible Possible Impossible USB EPO interrupt Possible Possible Impossible INTO interrupt Possible Possible Possible INT1 interrupt Possible Possible Possible INT2 interrupt Possible Possible Possible NMI interrupt Possible Possible Possible
367. qual to the buffer size byte count set in the BUF_SIZ of the EPxIFC has been written to IN FIFO in continuous transmit enable the IN BUF_STS1 and IN_BUF_STS0 flags are updated without SET_IN_BUF_RDY bit being set to 1 However when a short packet data whose size is smaller than the EPxIMP value in continuous transfer disable or the BUF_SIZ value in con tinuous transfer enable has been written the IN BUF_STS1 and IN_BUF_STS0 flags are not auto matically updated In such cases set the SET_IN_BUF_RDY bit to 1 by software Transmit Operation On completing transmitting of one packet data Note 2 to the host the IN_BUF_STSO and IN_BUF_STS1 flags are automatically updated In single buffer mode when double buffer mode bit is O these flags are updated from 112 to 002 In double buffer mode they are updated as follows While there are two packet data Note 2 in IN FIFO the IN BUF_STSO and IN_BUF_STS1 flags are updated from 112 to 012 when one of the data is transmitted indicating that one more transmit data is left inside the IN FIFO When there is one packet data Note 2 in IN FIFO the IN_ BUF_STSO and IN_BUF_STS0O flags are updated from 012 to 002 when the data are transmitted indicating that the IN FIFO becomes empty Note 2 In continuous transfer enable read the description by substituting the underlined part with buffer data The USB function control unit transmits
368. quest register is set to 1 The other bits are set to 0 valid setting Event 1 byte 1 word data is read from the endpoint x OUT FIFO which is set in USB DMAx x 0 to 3 request register Reading of Endpoint x OUT FIFO in DMA Transfer The DMA request factor of USB0 USB1 USB2 USB3 corresponds to read from the endpoints 1 to 4 OUT FIFO Factor 3 Therefore with endpoint x OUT FIFO being specified to the DMA source pointer and the transfer source address direction being fixed when DMA transfer is executed by Factor 1 Factor 2 or Factor 3 Factor 3 occurs Therefore when one buffer data one packet data is read from OUT FIFO by DMA transfer it is possible that the 1st byte 1st word data is DMA transferred by Factor 1 Factor 2 or Factor 3 and the other data starting from the 2nd byte 2nd word up to the last byte last word are DMA transferred by Factor 3 For details of DMA transfer refer to Chapter 2 DMAC Rev 2 00 Oct 16 2006 page 208 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 DMA Request by Endpoint x IN DMA Request Factor When endpoint x x 1 to 4 IN FIFO write request select bit is set to the DMA request factor origin of USB0 USB1 USB2 USB3 the DMA request factor includes the following three kinds On occurrence of an event when all the specified conditions have been satisfied for each factor the DMA request of DMA0 DMA1 DMA2 DMA3 occurs Factor 1 Conditions DMA ena
369. r A2 is solely used for normal processes and timer A4 is solely used for 4 multiplication processes Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer Ai interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer Ai interrupt request bit goes to 1 Note e The up count or down count conditions are as follows If a rising edge is present at the TAiIN pin when the input signal level to the TAIOUT pin is H an up count is performed If a falling edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is H a down count is performed e Set TAIIN pin and TAiOUT pin s port direction register to 0 1 Start count Input pulse 2 Underflow Counter content hex Set to 1 by software Count start flag Timer Ai interrupt 1 i request bit o Cleared to 0 when interrupt request is accepted or cleared by software Not
370. r clock stops at H level 4 If the transmission condition of the next data is ready when transmission is completed a start bit is generated following to stop bit s and the next data is transmitted 5 If a parity error occurs an L is output from the SIM card and the RxDi i 0 to 3 terminal turns to L level Check the RxDi i 0 to 3 terminal s level within the UARTi i 0 to 3 transmission interrupt routine and if it is found to be at the L level then handle the error Note e The parity error level is determined within a UARTi i 0 to 3 transmission interrupt When a transmission interrupt request occurs set the priority level of the transmission interrupt higher than those of other interrupts so that the interrupt routine can be immediately carried out Either in the main routine or in an interrupt routine the interrupt inhibition time has to be made as short as possible e Set the RxDi i 0 to 3 pin s port direction register to input e Select N channel open drain output for TxDi pin with data output select bit of UARTi i 0 to 3 transmit receive control register 0 Rev 2 00 Oct 16 2006 page 73 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface Example of wiring Microcomputer Note1 SIM card Note1 TxDi pin is N channel open drain and needs a pull up resistance Note2 i 0 to 3 Example of operation when direct format 1 Transmission enabled 3 Confirm stop bit 5 Dispose 2 Start tr
371. r initialization of toggle sequence bit in interrupt transfer set TOGGLE_INIT bit to 1 and initialize PID to DATAO Transmit Data Preparation Normal Interrupt Transfer The endpoint x IN packet data preparation procedure in the normal interrupt transfer is same as the bulk transfer Refer to Transmit Data Preparation of 2 Bulk Transfer Endpoints 1 to 4 Transmit Continu ous transfer is valid for the bulk transfer only Rate Feedback Interrupt Transfer In real application transmit data to the host CPU has to be always prepared Prepare one transmit data to the IN FIFO in the following procedure For details of the following 1 and 2 refer to the single buffer mode parts in Transmit Data Preparation 2 3 of 2 Bulk Transfer Endpoints 1 to 4 Transmit Continuous transfer is valid for the bulk transfer only 1 Write one packet data to be transmitted to the IN FIFO At the time of writing the data pay attention to the timing so that an IN token is not received from the host Every time 1 byte data are written to the IN FIFO the internal write pointer is automatically incremented by one Con tents of the internal write pointer cannot be read For transmitting an empty packet with 0 data length do not write data to the IN FIFO 2 Set SET_IN_BUF_RDY bit to 1 after writing of the data to the IN FIFO are completed At this time the IN FIFO state is updated and one packet transmit is prep
372. r pin TxD2 P70 and SCL2 P71 is N channel open drain output s It cannot be set to CMOS output g A Setting UARTi special mode register 3 i 0 to 3 b7 UARTI special mode register 3 Ihh UISMR3 Address 03A516 36516 033516 32516 SS port function enable bit 1 SS function enable Clock phase set bit 0 No clock delay Serial input port set bit 1 Select STxDi and SRxDi Slave mode N Continued to the next page Figure 2 5 15 Set up procedure of transmission in serial interface special function slave mode without clock delay 1 Rev 2 00 Oct 16 2006 page 104 of 354 RENESAS REJ09B0340 0200 M30245 Group Continued from the previous page 2 Serial Interface Special Function NL Setting UARTI transmit receive control register 1 i 0 to 3 b0 UARTIi transmit receive control register 1 ol TT UiC1 Address 03AD16 36D16 033D16 32D16 UARTi transmit interrupt cause select bit 0 Transmit buffer empty TI 1 Data logic select bit 0 No reverse Set to 0 in clock synchronous I O mode Transmission enabled UARTIi transmit receive control register 1 b7 bO I i uict Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Writing transmit data Note L l setting transmission data Note Use MOV instruction to write to this register UARTO transmit buffer register Address 03AB16 03AA16 UOTB pis oo
373. r registers addresses 03DB16 to 03DF16 1 Write enabled Reserved bit Must always be set to 0 NX a 3 Setting operation clock after returning from stop mode When operating with XIN after returning When operating with XcIN after returning b7 b0 System clock control register O b7 b0 System clock control register 0 of 0 0 Address 000616 CMO TLE 0 0 jAddress 000616 CMO L_T_ Reserved bit L_I Reserved bit Must always be set to 0 Must always be set to 0 Main clock XIN XOuT stop bit i Port XC select bit On XCIN XCOUT generation System clock select bit System clock select bit XIN XOUT XCIN XCOUT As this register becomes setting mentioned above when As this register becomes setting mentioned above when operating with XcIN operating with Xin count source of BCLK is XIN count source of BCLK is XciN the user does not need to set it again the user does not need to set it again A When operating with XIN set port Xc select bit to 1 before setting system clock When operating with Xcin set main clock Xn XouT stop bit select bit to 1 The both bits cannot be set at the same time to 0 before setting system clock select bit to 0 The both k bits cannot be set at the same time 3 All clocks off stop mode System clock control register Address 000716 All clock stop control bit 1 A
374. ram and Figures 3 2 3 and 3 2 4 show the set up procedure Use the following peripheral functions e Timer mode of timer A e One shot timer mode of timer A Specifications 1 Set timer AO in timer mode and set timer A1 in one shot timer mode with pulse output function 2 Set 1 ms the PWM period to timer AO Set 500 us the width of PWM H pulse to timer A1 Both timer AO and timer A1 use f1 for the count source 3 Connect a 16 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter of timer AO to begin counting The counter of timer AO performs a down count on count source f1 2 If the counter of timer AO underflows the counter reloads the content of the reload register and continues counting At this time the timer AO interrupt request bit goes to 1 3 An underflow in timer AO triggers the counter of timer A1 and causes it to begin counting When the counter of timer A1 begins counting the output level of the TA1O0UT pin goes to H 4 As soon as the count of the counter of timer A1 becomes 000016 the output level of TA1 OUT pin goes to L and the counter reloads the content of the reload register and stops counting At the same time the timer A1 interrupt request bit goes to 1 Rev 2 00 Oct 16 2006 page 299 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 Timer A Applications reload register content 1 Timer AO start count 2 Timer AO un
375. rce O Inverse format oO External clock CLKi pin Operation 1 Setting the transmit enable bit and receive enable bit to 1 readies data receivable status 2 When the first bit the start bit of reception data is received from the RxDi i 0 to 3 pin data is received bit by bit in sequence LSB MSB and stop bit s 3 When the stop bit s is are received the content of the UARTi i 0 to 3 receive register is transmitted to the UARTi i 0 to 3 receive buffer register At this time the receive complete flag goes to 1 to indicate that the reception is completed and the UARTi i 0 to 3 receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTi i 0 to 3 buffer register is read 5 When the parity error is occurred TXDi i 0 to 3 pin goes to L level Note e Set the RxDi and CLKi pins port direction register to 0 e Select N channel open drain output for TxDi i 0 to 3 pin with data output select bit of UARTi i 0 to 3 transmit receive control register 0 Rev 2 00 Oct 16 2006 page 77 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 SIM interface Example of wiring Microcomputer SIM card External clock Note1 TxDi pin is N channel open drain and needs a pull up resistance Note2 i 0 to 3 Example of operation when inversed format 1 Reception enabled 3 Receiving is completed 5 Parity
376. rce BRG s set value n 207 CF16 Actual time bps BRG s set value n Actual time bps 103 6716 51 3316 207 CF16 3 An error detection In UART mode detected errors are shown in Table 2 4 3 Table 2 4 3 Error detection Type of error Description When the flag turns on How to clear the flag e This error occurs when the serial interface starts receiving the next data item before reading the contents of the UARTI receive buffer register and receives the bit preceding the final stop bit of the next data item e The contents of the UARTi receive buffer register are undefined e The UARTI receive interrupt request bit does not go to 1 Overrun error e This error occurs when the stop bit falls short of the set number of stop bits Framing error e With parity enabled this error occurs when the total number of 1 s in character bits and the parity bit is different from the specified number Parity error Error sum flag e This flag turns on when any error overrun framing or parity is detected The error is detected when data is transferred from the UARTI receive register to the UARTi receive buffer register 7tENESAS e Set the serial I O mode select bits to 0002 e Set the receive enable bit to 9 e Set the serial I O mode select bits to 0002 e Set the receive enabl
377. re enabled e USB remote wakeup bit When the USB suspend signal status flag is set to 1 the USB function control unit transmits the resume signal to the host CPU while setting 1 to USB remote wakeup bit Set USB remote wakeup bit to 1 in order to transmit the resume signal to the host CPU and to return to the previous state remote wakeup in the USB suspend state Retain this bit at 1 for min 1ms to max 15ms before completing the resume signal transmission by clearing to O The configuration of USB power management register is shown in Figure 2 8 27 Rev 2 00 Oct 16 2006 page 161 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function USB Power Management register b15 b8 b7 b0 b7 b0 olol olololojoljojolojojolojo Symbol Address When reset USBPM 028216 000016 Bit Symbol Bit Name Function 0 Not in suspend state SUSPEND Suspend state flag 1 In suspend state Note 1 WAKEUP _ Remote wakeup 0 End remote wakeup signal 1 Remote wakeup signaling Note 3 Reserved Must always be 0 Note 1 This flag is cleared when WAKEUP 1 or a resume signal is detected Note 2 Set 0 when writing Note 3 If SUSPEND 1 set this bit to 1 keep this bit set for a minimum of 1ms and a maximum of 15ms Figure 2 8 27 USB power management register Rev 2 00 Oct 16 2006 page 162 of 354 ENESAS REJ09B0340 0200 M30245 Gro
378. register b15 b8 b7 bO b7 Symbol Address When reset CRCSAR 03B516 03B416 Bit name Function CRCSAR 9 0 CRC Snoop address bits SFR address to snoop Note Nothing is assigned Write 0 when writing to this bit The value is indeterminate if read CRC Snoop on 0 Disabled OROSH read enable bit 1 Enabled CRC Snoop on 0 Disabled CRCSW write enable bit 1 Enabled Note Only USB UART and SSI related registers can be snooped Figure 2 11 2 CRC related registers Rev 2 00 Oct 16 2006 page 250 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 CRC Calculation Circuit 2 11 2 Operation of CRC Calculation Circuit The following describes the operation of the CRC calculation Figure 2 11 3 shows an example of calcu lation using the CRC CCITT Operation 1 Select CRC CCITT or CRC 16 and LSB first or MSB first by bit 0 and bit 5 of CRC mode register 2 The CRC calculation circuit sets an initial value in the CRC data register 3 Writing 1 byte data to the CRC input register generates CRC code based on the data register CRC code generation for 1 byte data finishes in two machine cycles 4 When several bytes of CRC calculation is performed in succession write the following data in the CRC input register continuously 5 The content of CRC data register after all data is written becomes CRC code b15 bO CRC data register CRCD
379. request register is set to 1 The other bits are set to 0 valid setting Event The OUT FIFO state of the endpoint x OUT which is set in USB DMAx x 0 to 3 request register has been updated and the OUT_BUF_STS1 and OUT_BUF_STS0 flags are set to 112 at the time of single buffer and 102 at the time of double buffer When data of one or more buffers are received in OUT FIFO At this time when one packet receive is completed the endpoint x OUT interrupt request simultaneously occurs Factor 2 Conditions DMA enable bit of DMAi control register is set to 1 enable The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB DMAx x 0 to 3 request register are set to 102 or 112 When data of one or more packets are received in OUT FIFO There is no selection of USB DMAx x 0 to 3 request register 0016 Event Any one of endpoint x x 1 to 4 OUT FIFO read request select bit in USB DMAx x 0 to 3 request register is set to 1 The other bits are set to 0 valid setting Factor 3 Conditions DMAenable bit of DMAi control register is set to 1 enable The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB DMAx x 0 to 3 request register are set to 102 or 112 When data of one or more packets are received in OUT FIFO Any one of endpoint x x 1 to 4 OUT FIFO read request select bit in USB DMAx x 0 to 3 re
380. ress 03AD16 036D16 033D16 032D16 Function clock synchronous serial I O mode UART mode When reset 0216 Function Transmit enable bit Transmit disabled Transmit enabled Transmit buffer empty flag Data present in transmit buffer register No data present in transmit buffer register Receive enable bit Receive disabled Receive enabled Receive complete flag Data packet in receive buffer No data packet in receive buffer register register UARTI transmit interrupt cause select bit Transmit buffer empty TI 1 Transmit buffer completed TXEPT 1 UARTI continuous receive mode enable bit Continuous receive mode disabled Continuous receive mode enabled Set to 0 Data logic select bit 0 No reverse 1 Reverse Error signal output enable bit Set to 0 The value is indeterminate when read 0 Output disabled 1 Output enabled Note 1 Note 1 When disabling the error signal output set the UiERE bit to 0 after setting the UiMR register registers 3 354 7tENESAS 2 UART M30245 Group 2 UART Interrupt request cause select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset IFSR 035F16 0016 INTO interrupt polarity One edge swiching bit Two edges INT1 interrupt polarity One edge swiching bit Two edges INT2 interrupt polarity One edge swiching
381. rflow 3 Overflow Count start flag 1 g Cleared to 0 when interrupt request is accepted or cleared by software Timer Ai interrupt 4 Pa Pa request bit o Note First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Figure 2 2 18 Operation timing of two phase pulse signal process in event counter mode multiply by 4 mode selected Rev 2 00 Oct 16 2006 page 24 of 354 RENESAS REJ09B0340 0200 M30245 Group Figure 2 2 19 Rev 2 00 Oct 16 2006 page 25 of 354 REJ09B0340 0200 Selecting event counter mode and functions Timer Ai mode register i 3 4 Address 039916 039A16 TAiMR i 3 4 Selection of event counter mode 0 Must always be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing Count operation type select bit Note 1 1 Free run type Two phase pulse signal processing operation select bit 1 Multiply by 4 processing operation Note 1 First set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Two phase pulse signal processing select bit b7 bO
382. rnal clock select bit 0 Internal clock Stop bit length select bit 0 One stop bit Odd even parity select bit Valid when bit 6 1 0 Odd parity Parity enable bit 1 Parity enabled TxD RxD I O polarity reverse bit C Usually set to 0 g Setting UARTi transmit receive control register 0 i 0 to 3 bo UARTI transmit receive control register 0 COsGEOmS UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 b0 0 0 f1 is selected 0 1 f8 is selected 1 0 f32 is selected 1 1 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTSI RTS diss disable bit 0 CTS RTS function enabled Data output select bit Note 2 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output Must be fixed to 0 in UART mode Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to 0 It cannot be set to CMOS output n Note 2 UART2 transfer pin TxD2 P70 and SCL2 P71 is N channel open drain output Setting UART transmit receive control register 1 i 0 to 3 20 UARTI transmit receive control register 1 0 of o l l UiC1 Address 03AD16 36D1
383. rns out to be approximately 3 0 kQ Tables 2 9 12 and 2 9 13 show output impedance values based on the LSB values Microprocessor s inside Sensor equivalent circuit R 7 8kQ VVV C 3 0pF Figure 2 9 24 A circuit equivalent to the A D conversion terminal Rev 2 00 Oct 16 2006 page 238 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 A D Converter Table 2 9 12 Relation between output impedance and precision error of A D converter 10 bit mode Reference value f Xin Cycle Sampling time Resolution i ie us us oF 3 x ae Sample amp hold bit is enabled N OI O mY NI 0 Go CO NI 0J Go 2x cycle Sample amp hold bit is disabled os 3 x Die Sample amp hold bit is enabled 2 x cycle Sample amp hold bit is disabled Rev 2 00 Oct 16 2006 page 239 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 DMAC 2 10 DMAC Usage 2 10 1 Overview of the DMAC usage DMAC transfers one data item held in the source address to the destination address every time a transfer request is generated The following is an overview of the DMAC usage 1 Source address and destination address Both the register which indicates a source and the register which indicates a destination comprise of 24 bits so that each can cover a 1M bytes space After transfer of one bit of data is completed the address in either the source register or the destination register ca
384. ronous transfer ISO bit of USB endpoint x x 1 to 4 OUT control and status register is set to 1 for isochronous transfer setting Receive Operation When there is a packet space in OUT FIFO on receiving the OUT token from the host CPU the data are received At this time the OUT FIFO status is updated the endpoint x OUT interrupt request occurs When an error is detected in the received packet simultaneously the DATA_ERR flag is set to 1 Error checks such as CRC check conforming to USB2 0 specification are automatically performed When the OUT token is received from the host CPU while there are already data in OUT FIFO and packet data cannot be received an overrun error occurs At this time the OVER_RUN flag is set to aa ae Further when a packet which size exceeds the maximum packet size is transmitted from the host CPU the FORCE_STALL flag is set to 1 without receiving the data While error interrupt has been enabled by USB function interrupt enable register an error interrupt request occurs when any one of the OVER_RUN flag FORCE_STALL flag or DATA_ERR flag is set to 1 INTST8 is set to 1 Fetch of Receive Data The fetch procedure of endpoint x OUT receive data in the isochronous transfer is same as the bulk transfer Refer to Fetch of Receive Data of 2 Bulk Transfer Endpoints 1 to 4 Receive Although continuous transfer is valid for the bulk transfer only Rev 2 00 Oct 16 2006
385. roup UARTI bit rate generator o 0 to 3 Note 1 2 b7 bo Symbol UOBRG U1BRG U2BRG U3BRG Address 03A916 036916 033916 032916 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Values that can be set Assuming that set value n BRGi divides the count source by 0016 to FF1e 0 n 1 Note 1 Use MOV instruction to write to this register Note 2 Write a value to this register while transmit receive halts UARTi transmit receive mode register i 0 to 3 Address When reset 03A816 0016 Symbol UOMR b7 b6 b5 b4 b3 b2 bi b0 U1MR U2MR U3MR 036816 0016 033816 0016 032816 0016 Function During clock synchronous serial I O mode Must be fixed to 001 b2 b1 b0 0 0 0 Serial I O invalid 0 1 0 Serial I O mode 0 11 12C mode Inhibited except in cases Bit name Serial I O mode select bit Note 3 Function During UART mode Transfer data 7 bits long Transfer data 8 bits long Transfer data 9 bits long Inhibited except in cases CKDIR Internal external clock T Internal clock fe Internal clock select bit STPS stop bit length select bit Invalid 0 One stop bit iji a Odd even parity select bit Invalid Valid when bit 6 1 0 Odd parity 1 Even parity PRYE Parity enable bit Invalid 0 Parity disabled 1 Parity enabled TxD RxD input output polarity switch bit Note 2 1 SLEP listed above listed above
386. rrupt request is accepted or cleared by software Timer Ai interrupt 4 i i request bit Q Set to 1 by software Count start flag Figure 2 2 6 Operation timing of timer mode Rev 2 00 Oct 16 2006 page 12 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 TimerA Selecting timer mode and functions TAiMR i 0 to 4 Selection of timer mode Pulse output function select bit Gate function select bit b4 b3 00 01 Count source select bit b7 b6 00 fi 01 f8 Timer Ai mode register i 0 to 4 Address 039616 to 039A16 0 Pulse is not output TAi OUT pin is a normal port pin Gate function not available TAIIN pin is a normal port pin 0 Must always be 0 in timer mode Count source Count source period f XIN 16MHz__ f XcIN 32 768kHz 62 5ns 10 f32 1 1 fc32 500ns 2us 976 56us a Setting divide ratio b15 b7 bO Loo T E b8 a Ooo Can be set to 000016 to FFFF16 Timer AO register Address 038716 038616 TAO Timer A1 register Address 038916 038816 TA1 Timer A2 register Address 038B16 038A16 TA2 Timer A3 register Address 038D16 038C16 TA3 Timer A4 register Address 038F16 038E16 TA4 Setting clock prescaler reset flag dividing the XCIN by 32 b7 b0 LAA CPSRF Clock prescaler reset flag 0 No effect e This function is effective when fc32 is selected as th
387. rrupt request state respectively These flags are set to 1 at the corresponding endpoint that has been enabled by USB function interrupt enable register in the following cases The endpoint is enabled from a disabled state One buffer data is successfully transmitted Buffer flush has been executed by either AUTO_FLUSH or FLUSH bit bit 6 at address EPxICS being set to 1 while buffer data exists in the IN FIFO e Endpoint 1 OUT Interrupt Status Flag Endpoint 2 OUT Interrupt Status Flag Endpoint 3 OUT Interrupt Status Flag Endpoint 4 OUT Interrupt Status Flag These each indicate endpoint x x 1 4 OUT interrupt request state When a data is successfully received these flags are set to 1 at the corresponding endpoint e Error Interrupt Status Flag This flag indicates that an error has been occurred at the endpoint x x 0 4 This flag is set to 1 in the following cases The EPOCSR4 FORCE_STALL flag of endpoint 0 is set to 1 The EPOCSR5 SETUP_END flag of endpoint 0 is set to 1 The INXCSR2 UNDER_RUN flag of endpoint 1 to 4 IN is set to 1 The OUTxCSR2 OVER_RUN flag of endpoint 1 to 4 OUT is set to 1 The OUTxCSR3 FORCE_STALL flag of endpoint 1 to 4 OUT is set to 1 The OUTxCSR4 DATA_ERR flag of endpoint 1 to 4 OUT is set to 1 Rev 2 00 Oct 16 2006 page 150 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function USB Interrupt Status register
388. rst set to Reload type operation Once the first counting pulse has occurred the timer may be changed to Free Run type Rev 2 00 Oct 16 2006 page 36 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 TimerA 2 2 14 Precautions for Timer A one shot timer mode 1 At reset the count start flag is set to 0 Set a value in the timer Ai register then set the flag to 1 2 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TAiOUT pin outputs L level e The interrupt request generated and the timer Ai interrupt request bit goes to 1 3 The timer Ai interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer Ai interrupt interrupt request bit set timer Ai interrupt request bit to 0 after the above listed changes have been made 4 If a trigger occurs while a count is in progress after the counter performs one down count following the reoccurrence of a trigger the reload register contents are reloaded and the count continues To generate a trigger while a count is in progress generate the second trigger after an elapse lon
389. rt function enable bit 1 SS function enable Clock phase set bit 0 Without clock delay Serial input port set bit 0 Select TxDi and RxDi Master mode Continued to the next page Figure 2 5 9 Set up procedure of transmission in serial interface special function master mode without clock delay 1 Rev 2 00 Oct 16 2006 page 96 of 354 7tENESAS REJ09B0340 0200 M30245 Group PU Figure 2 5 10 Set up procedure of transmission in serial interface special function master mode without clock delay 2 2 Serial Interface Special Function Continued from the previous page Setting UARTi transmit receive control register 1 i 0 to 3 b7 60 UARTI transmit receive control register 1 ofof Jol ViCi Address 03AD16 36D16 033D16 32D16 UARTI transmit interrupt cause select bit 0 Transmit buffer empty TI 1 Data logic select bit 0 No reverse Set to 0 in clock synchronous serial I O mode Setting UARTi bit rate generator i 0 to 3 b7 0 bi UARTi bit rate generator Address 03A916 036916 033916 032916 UIBRG i 0 to 3 ______ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTI bit rate generator when transmission reception is halted Output an L to SS port on the receiver side IC Transmission enabled UARTI transmit receive control register 1 b7 bO
390. s 038016 TABSR Timer AO count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count 2 Timer A Figure 2 2 11 Set up procedure of timer mode pulse output function selected Rev 2 00 Oct 16 2006 page 17 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 2 2 5 Operation of Timer A event counter mode reload type selected In event counter mode choose functions from those listed in Table 2 2 4 Operations of the circled items are described below Figure 2 2 12 shows the operation timing and Figure 2 2 13 shows the set up procedure Table 2 2 4 Choosed functions Count source Input signal to TAIN Pulse output function No pulses output counting falling edges Pulses output Input signal to TAIN Count operation type Reload type counting rising edges Free run type Factor for switching Content of up down flag between up and down Input signal to TAiouT TAj overflow Note j i 1 butj 4 wheni 0 Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Ai interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the sw
391. s Vref with VIN Bit 8 of the successive comparison register varies depending on the comparison result as follows If Vref lt VIN then 1 is assigned to bit 8 If Vref gt VIN then 0 is assigned to bit 8 3 Fixes bit 7 through bit 0 of the successive comparison register Carries out step 2 above on bit 7 through bit 0 After bit 0 is fixed the contents of the successive comparison register conversion result are transmitted to AD register i Vref is generated based on the latest content of the successive comparison register Table 2 9 8 shows the relationship of the successive comparison register contents and Vref Table 2 9 9 shows how the successive comparison register and Vref vary while A D conversion is in progress Figure 2 9 18 shows theoretical A D conversion characteristics Table 2 9 8 Relationship of the successive comparison register contents and Vref Successive approximation register n 0 1 t01023 Rev 2 00 Oct 16 2006 page 231 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 A D Converter Table 2 9 9 Variation of the successive comparison register and Vref while A D conversion is in progress 10 bit mode VREF V gt M VREF VREF 1st comparison gt 2048 V 4 f VREF VREF VREF i V 2nd comparison 0 0 2 4 2048 V n9 0 y st comparison result 3rd comparison nsl1 0o olo olo VREF VREF VREF _ VREF jy 2 4 204 ne 0 t 2nd comparison result 3 OM
392. s document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its
393. s in event counter mode NOKrmMal MOde SElECIEM EE E T E A E 22 2 2 8 Operation of timer A two phase pulse signal process in event counter mode multiply by 4 mode selected eccccceseeeeeeeeeeeeeeeeeeseeeeseeeeeeeeseeneseeeeseseeeeeeesaseseeeeseeseseeneseeeeenenseeeeeneneets 24 2 2 9 Operation of Timer A one shot timer mode sssssssssununnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn nnmnnn 26 2 2 10 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected 2 2220122 28 2 2 11 Operation of Timer A pulse width modulation mode 8 bit PWM mode selected 2 0s0 31 2 2 12 Precautions for Timer A timer mode ccccee cee eeeeeee eee e ee cence ee eee ne ene eeee eee see eeee sagen neeeee eee nnmnnn 34 2 2 13 Precautions for Timer A event counter mode 2 cete eee eeeeeeeeeeeeeeeeeeeeeeeeeneeaneneaseeeeeeeeseeeeeneennees 35 2 2 14 Precautions for Timer A one shot timer MOE 22 ccceeeeeeeeeeeeeeeeee cence sense eneenseneaeeeeeeeeeseeeeeneennees 37 2 2 15 Precautions for Timer A pulse width modulation mode seeeceeeeeee eee eeeeneeneeeeeeeeseeeeeeeeneeneees 38 2 3 Clock Synchronous Serial O ssissiscvssncsencscnsssussaaeascceccct cctsvenersadeconcveneestsentesecsauccescucuswens 39 2 3 WOVCIVIEW eeaeee ie Whiten ee i EE E OE tes ee 39 2 3 2 Operation of Serial I O transmission in clock synchronous serial I O mode 2 essseeee 45 2 3
394. s of 64 bytes 000000 buffer starting location 0 000001 buffer starting location 64 000010 buffer starting location 128 101111 buffer starting location 3008 last starting number IN FIFO buffer size Select the buffer size for the EPx IN FIFO in units of 64 bytes 0000 buffer size 64 0001 buffer size 128 0010 buffer size 192 1111 buffer size 1024 largest buffer size Double buffer mode 0 Double buffer mode disabled 1 Double buffer mode enabled Continuous transfer mode Note 0 Continuous transfer disabled 1 Continuous transfer enabled USB Endpoint x OUT FIFO configuration register EPxOFC x 1 to 4 Address 02BC16 02C416 02CC16 02D416 OUT FIFO buffer start number Select the starting number for the EPx OUT FIFO in units of 64 bytes 000000 buffer starting location 0 000001 buffer starting location 64 000010 buffer starting location 128 101111 buffer starting location 3008 last starting number OUT FIFO buffer size Select the buffer size for the EPx OUT FIFO in units of 64 bytes 0000 buffer size 64 0001 buffer size 128 0010 buffer size 192 1111 buffer size 1024 largest buffer size Double buffer mode 0 Double buffer mode disabled 1 Double buffer mode enabled Continuous transfer mode Note 0 Continuous transfer disabled 1 Continuous transfer enabled Not
395. s set to 1 during USB transfer Read the OUT_BUF_STS1 and OUT_BUF_STS0 flags and confirm that there are data in the OUT FIFO and then set this bit to 1 On completing one buffer data destruction this bit is automatically cleared to 0 ISO bit Set this bit to 1 in order to use an endpoint in isochronous transfer Set this bit to O in order to use an endpoint in bulk interrupt transfer SEND_STALL bit This bit controls the STALL response to the host CPU in bulk transfer interrupt transfer Set this bit to 1 when the OUT endpoint is in STALL state While this bit is set to 1 the USB function control unit transmits the STALL handshake concerning all the OUT transactions to the host CPU When the OUT endpoint has returned from STALL state clear this bit by writing 0 The OUT endpoint communication is resumed AUTO_CLR bit This bit controls setting of CLR_OUT_BUF_RDY bit With this bit being set to 1 when one receive buffer data is read from OUT FIFO the OUT_BUF_STS1 and OUT_BUF_STS0 flags are automatically updated without CLR_OUT_BUF_RDY bitbeing set to 1 With this bit being set to 0 on completing one receive buffer data fetch from OUT FIFO CLR_OUT_BUF_RDY bit has to be set to 1 by software The configuration of USB endpoint x OUT control and status register is shown in Figure 2 8 40 Rev 2 00 Oct 16 2006 page 184 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB fun
396. s transfer P92 can be used as the SOF output pin by setting 1 to USB SOF port select bit of USB control register Set P92 to output port Every time that the SOF signal is received from the host the P92 outputs Low for about 166ns two cycles of the 12MHz USB clock When using the USB SOF interrupt set the interrupt priority level at USB SOF interrupt control register SOFIC address 005B16 Artificial SOF Function If the SOF packet from the host PC is destroyed due to any cause and thus the SOF packet is not correctly received within 1 ms of the start of the frame a virtual SOF receive operation is performed and an USB SOF interrupt is generated Even if the SOF packet is destroyed due to any cause a new frame can be formed by this function without waiting for the next SOF packet This function operates once to virtually receive an SOF packet after two SOF packets have been received cor rectly Rev 2 00 Oct 16 2006 page 157 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 8 USB Function Interrupt Routine This interrupt is used to control data flow This occurs on completion of data transmit receive or on occurrence of an error such as overrun underrun When using the USB function interrupt set the interrupt priority level at USB function interrupt control register address 005D16 and the correspond ing bit of USB function interrupt enable register to 1 The related registers are shown in Figure 2
397. sed Figure 2 3 2 UiRB Note 1 deleted ABT W x gt Figure 2 3 3 UiMR When reset revised Note 3 added Figure 2 3 4 UiCO bit 5 TxDi TxDi SDAi and SCLi revised Note 2 revised Note 4 added UiCi Note 1 added Figure 2 3 6 UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Figure 2 3 8 Example of operation revised Figure 2 3 9 UiMR bit 0 2 Set the corresponding to 0 when receiving gt Set the RxDi to 0 when receiving revised UiCO bit5 TxDi gt TxDi SDAi and SCLi revised Reception 3 revised Table 2 4 3 Overrun error Description revised c LSB MSB first select function added Figure 2 4 3 UiRB Note 1 deleted ABT W x gt Figure 2 4 4 UiMR When reset revised Note 3 added Figure 2 4 5 UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Note 2 revised Note 4 added UiCi Note 1 added Figure 2 4 8 UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Figure 2 4 11 UiMR Note 1 added UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised 2 4 4 added Figure 2 4 13 Example of operation when direct format revised Note 2 added Figure 2 4 14 UiCO bit 5 TxDi TxDi SDAi and SCLi revised Figure 2 4 17 UiMR Note 1 added UiCO bit 5 TxDi gt TxDi SDAi and SCLi revised Figure 2 5 2 UiRB Note 1 deleted ABT W x gt Figure 2 5 3 UiMR When reset revised Note 3 added Figure 2 5 4
398. sed for streaming data such as animation and audio data which requires real time 2 Communication Protocol Host CPU has the initiative for the entire USB communication Even when data are transmitted to the host from the device the host gives the right of use to the device before data are transmitted The host in order to process multiple transfers simultaneously schedules each transfer in packet unit within a frame of 1ms interval The frames image is shown below ims ims ims SOF Audioimouse printer scanner SOF Audio printer scanner scanner Isochronous trasnfer Interrupt trasnfer Bulk trasnfer Figure 2 8 1 Frame image Packet A packet is the unit in which the host CPU or the device secures a bus In the USB data are transmit ted received in the packet unit A packet is a group of bit data strings fields which starts with the SOP Start of Packet as a part of the SYNC synchronous data field This is followed by the PID field which identifies a packet type and then each data field of a frame number address data field etc finally ending with EOP End of Packet which indicates the end of a packet The packet types and formats are shown below Rev 2 00 Oct 16 2006 page 128 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function SOF Packet Packet to start the frame to be issued from the host for every 1ms 8 bits 8 bits 5 bits PID SOF 0xA5 Token Packet Packet to be issued
399. ses used in the two phase pulse signals input signals to the TAIN pin and TAiOUT pin i 2 3 4 as shown in Figure 2 2 30 4 When free run type is selected if count is stopped set a value in the timer Ai register again 1 Down count 2 Up count Reload Counter value Counter value Hex aae papa ie FFFO FFFE FFFF n n 1 Read value a Read value fie ala oje ee FFFO FFFE FFFF 0000 n 1 Time Time n reload register content n reload register content Figure 2 2 29 Reading timer Ai register Vcc 5V f XIN 20MHz TAQIN Min Min TA4IN Vcc 3V f XIN 10MHz TA2OUT TA30UT TA40UT Figure 2 2 30 Standard of 2 phase pulses Rev 2 00 Oct 16 2006 page 35 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 TimerA 5 In the case of using as Free Run type the timer register contents may be unknown when counting begins If the timer register is set before counting has started then the starting value will be unknown e In the case where the up down count will not be changed Enable the Reload function and write to the timer register before counting begins Rewrite the value to the timer register immediately after counting has started If counting up rewrite 000016 to the timer register If counting down rewrite FFFF16 to the timer register This will cause the same operation as Free Run type mode e In the case where the up down count has changed Fi
400. set INT11IC 004416 XX00X0002 S1RIC 004816 XX00X0002 b7 b6 b5 b4 b3 b2 bi b0 S02BCNIC 004916 XX00X0002 VINY XX00X000 TI hls 008Fi6 Xx00X0002 Erma Funetion Interrupt priority level b2b1 b0 select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 Interrupt not requested 1 Interrupt requested POL Polarity select bit 0 Selects falling edge 1 Selects rising edge Reserved bit Always set to 0 Nothing is assigned Write O when writing to these bits The contents are indeterminate if read Note 1 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts Note 2 This bit can only be reset 0 but cannot be set 1 Note 3 For S1RIC 004816 and SO2BCNIC 004916 0 should always be written Figure 2 15 2 Interrupt control registers Rev 2 00 Oct 16 2006 page 268 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Multiple Interrupts 2 Interrupt Enable Flag I flag The interrupt enable flag I flag controls the enabling and disabling of maskable interrupts Setting this flag to 1 enables all maskable interrupts setting it to O disables all maskable interrupts This flag is set to O after reset The content is changed when the flag is changed causes the acceptance of the interrupt request in t
401. sfer not receiving the packet data The data receive from the host CPU is controlled based on the communication status of endpoints 1 to 4 OUT The default of endpoints 1 to 4 is bulk transfer Each endpoint should be initialized in order to use other transfer modes The receive of endpoints 1 to 4 can select the following functions Continuous Receive Mode This function is used for receiving data from the host PC at a higher speed This mode can be set only for endpoints 1 to 4 OUT bulk transfer With continuous transfer mode bit of the EPxOFC being set to 1 the continuous receive mode is enabled The USB function control unit writes the receive data from the host PC in OUT FIFO sequentially by the maximum packet size that is set in USB endpoint x OUT MAXP register EPXOMP When the last one packet is smaller than the size set in the EPxOMP it is received as a short packet When continuous receive mode is enabled the buffer size has to be equal to an integral multiple of the EPxOMP Further the user s system has to be comprehended beforehand that the receive data from the host PC are equal to the buffer size or includes a short packet AUTO_CLR Function When receive data from OUT FIFO are read both the OUT _BUF_STSO and the OUT_BUF_STS1 flags are updated without CLR_OUT_BUF_RDY bit being set to 1 The AUTO_CLR function is en abled by setting AUTO_CLR bit of the EPxOCS to 1 The AUTO_CLR function is available both in the c
402. signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after
403. simultaneously set CLR_OUT_BUF_RDY bit and also CLR_SETUP bit for the SETUP packet and SEND_STALL bit to 1 e When the valid new SETUP packet is received after setting SEND_STALL bit clear SEND_STALL bit and set CLR_OUT_BUF_RDY bit to 1 and also CLR_SETUP bit for the SETUP packet Rev 2 00 Oct 16 2006 page 175 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 Control Transfer Endpoint 0 Transmit The endpoint 0 transmits the packet data to the host CPU in the data stage by the control read after completion of receive request analysis process in the setup stage Write one packet data to be transmitted in IN FIFO Every time that one byte data is written in IN FIFO the internal write pointer is automatically incremented by 2 in word access and by 1 in byte access The contents of internal write pointer cannot be read When the data write in IN FIFO is completed set IN_BUF_RDY flag to 1 by setting 1 to SET_IN_BUF_RDY bit When an empty packet with 0 data length is transmitted data is not written in IN FIFO and SET_IN_BUF_RDY bit is set to 1 At this time one packet transmission is prepared and is transmitted by the USB function control unit in the next IN token The IN_BUF_RDY flag is automatically set to O when one packet data transmission is completed to the host CPU or on receiving ACK or when the SETUP_END flag is set to 1 After writing the last data packet in I
404. smit buffer empty flag or the content of the transmit enable bit Output from the RTS pin goes to H level when reception starts and goes to L level when reception is completed This is not related to the content of the transmit buffer empty flag or the content of the receive complete flag Rev 2 00 Oct 16 2006 page 54 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 UART 2 4 Clock Asynchronous Serial I O UART 2 4 1 Overview UART handles communications by means of character by character synchronization The transmission side and the reception side are independent of each other so full duplex communication is possible The following is an overview of the clock asynchronous serial I O 1 Transmission reception format Figure 2 4 1 shows the transmission reception format and Table 2 4 1 shows the names and func tions of transmission data Transfer data length 7 bits _ _ 1ST 7DATA __ 1SP m 1ST 7DATA _ 2SP m 1ST 7DATA 1PAR 1SP 1ST 7DATA 1PAR 2SP Transfer data length 8 bits 1ST 8DATA _ 1SP m 1ST 8DATA _ 2SP m 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP Transfer data length 9 bits 1ST 9DATA _ 1SP m 1ST 9IDATA _ 2SP m 1ST 9DATA 1PAR 1SP 1ST 9DATA 1PAR 2SP ST Start bit Character bit Transf
405. smit receive control register 1 HEILT vict fAdaress 03AD16 36D16 033D16 32D16 UARTi transmit interrupt cause select bit 1 Transmission completed TXEPT 1 Must be fixed to 0 in UART mode Data logic select bit Must be 1 reverse in inverse format Error signal output enable bit in UART mode 1 Output enabled Continued to the next page Figure 2 4 17 Set up procedure of reception in UART mode used for SIM interface 1 Rev 2 00 Oct 16 2006 page 79 of 354 lt ENESAS REJ09B0340 0200 an M30245 Group 2 SIM interface Continued from the previous page I Setting UART i bit rate generator i 0 to 3 b7 bO BRENT EEE UARTi bit rate generator Address 03A916 036916 033916 032916 UiBRG i 0 to 3 ____ Can be set to 0016 to FF16 Note Note Use MOV instruction to write to this register Write to UARTI bit rate generator when transmission reception is halted Reception enabled b7 b0 UARTi transmit receive control register 1 D i uict Address 03AD16 36D16 033D16 32D16 Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note Note Set RxD pin s port direction register to 0 i E Start reception Checking completion of data reception b 50 UARTI transmit receive control register 1 TLL TEL vict address 03AD16 3616 033D16 32D16 Receive complete flag 0 No data present in receive
406. sor mode the contents of corresponding port and direction registers of pins AO to A19 DO to D15 CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified 2 Reading a port register With the direction register set to output reading a port register takes out the content of the port regis ter not the content of the pin With the direction register set to input reading the port register takes out the content of the pin 3 Input only port P85 is used as the input only port it also serves as NMI P85 has no direction register Pull up cannot be set to this port As NMI cannot be disabled an NMI interrupt occurs if a falling edge is input to P85 Use P85 for reading the level input at this time only 4 Setting pull up The pull up control bit allows setting of the pull up in terms of 4 bits either in use or not in use For the four bits chosen pull up is effective only in the ports whose direction register is set to input Pull up is not effective in ports whose direction register is set to output Do not set pull up of corresponding pin when XCIN XCOUT is set or a port is used as A D input Pull up can be set for PO to P3 P40 to P43 P50 to P53 in only single chip mode Pull up cannot be set for PO to P3 P40 to P43 P50 to P53 in memory expansion and microprocessor modes The contents of register can be changed but the pull up resistance is not connected 5 Setting drive capacity A normal drive and N chann
407. sor mode there is a difference between areas for which CS0 is output When an internal ROM RAM area is being accessed no chip select is output and the address bus does not change the address of the external area that was accessed previously is held 0000016 SFR area 003FF16 0040016 Internal RAM area Internal reserved area O3FFF16 0400016 O7FFF16 2800016 2FFFF16 3000016 CFFFFi6 D000016 Internal reserved area YYYYY16 Internal ROM area FFFFFi6 0800016 27FFF16 Part number Address XXXXX16 4 External Buses Address YYYYY16 M30245FCGP 02BFF16 E000016 M30245MC XXXGP 02BFF16 E000016 M30245M8 XXXGP CS2 0800016 to 27FFF16 128K 017FF16 CS2 0800016 to 27FFF16 128K F000016 2800016 to 2FFFF16 32K 3000016 to FFFFF16 832K A EE EENE E E PE E E Memory expansion mode Memory expansion mode Figure 4 2 2 Addresses in which chip selects turn active L Rev 2 00 Oct 16 2006 page 332 of 354 REJ09B0340 0200 7tENESAS M30245 Group 4 External Buses Chip select control register 7 4 2 1 cr e Ara eco Symbol Address When reset CSR 000816 0116 7 a CSO output enable bit 0 Chip select output disabled cesio CS1 output enable bit Normal port pin 2 1 Chip select output enabled CS2 output enable bit CS3 output enable bit con CS0 wait bit 0 Wait state inserted CS1W CS1 wait bit 1 No wait state CS2W CS2 wai
408. st that has occurred when the interrupt process has been received based on the saved data value Endpoint x x 1 4 IN Interrupt In the endpoint x x 1 4 IN interrupt when each USB endpoint x IN interrupt status flag INTST0 2 4 6 of the corresponding endpoints of USB function interrupt status register is set to 1 an interrupt request occurs Each flag INTSTO 2 4 6 is set to 1 in one of the following cases e The corresponding bit of USB endpoint enable register USBEPEN address 028E16 is set to 1 The endpoint is enabled from a disabled state e A data is successfully transmitted e AUTO FLUSH of hardware has been executed or FLUSH bit of corresponding USB endpoint x IN control and status register EPxICS addresses 029E16 02A416 O2AA16 02B016 being set to 1 while one or two packet data exist in the IN FIFO e The last ACK for control read transfer is destroyed Endpoint x x 1 4 OUT Interrupt In the endpoint x x 1 4 OUT interrupt when each USB endpoint x OUT interrupt status flag INTST1 3 5 7 of the corresponding endpoints of USB function interrupt status register is set to 1 an interrupt request occurs When a data is successfully received at the corresponding endpoint each flag INTST1 3 5 7 is set to 1 Error Interrupt In the error interrupt when the error interrupt status flag INTST8 of USB function interrupt status register is set to 1 an interrupt request occurs
409. state state Resume detected USB resume interrupt Execute SetAddress USB function interrupt DeviceAddress 01h to 7Fh Suspend detected USB suspend interrupt Address a Suspend state state Resume detected USB resume interrupt Execute SetConfiguration Execute SetConfiguration USB function interrupt USB function interrupt Configuration Value 0 Configuration Valuex0 Suspend detected USB suspend interrupt Configured oe Suspend state state Resume detected USB resume interrupt Figure 2 8 7 Device state transition Rev 2 00 Oct 16 2006 page 136 of 354 AS REJ09B0340 0200 RENES M30245 Group 000C16 001F 16 004616 005616 005816 005A16 005B16 005C16 005D16 028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C16 028D16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C16 029D16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A6i6 02A716 02A816 02A 6 02AAi6 02ABi6 02AC16 02AD16 02AE16 02AFi6 02B016 02B116 02B216 02B3i6 02B4i6 02B516 02B616 USB control register USBC 02B716 02B816 USB Attach Detach register USBAD 02B 6 02BAi6 02BBi6 USB Endpoint 0 interrupt control register EPOIC 02BC16 USB suspend interrupt control register SUSPIC 02BD16 02BE16
410. ster i 0 to 3 b7 bO TFT UARTi transmit receive mode register o UiMR Address 03A816 36816 033816 32816 Must be fixed to 001 Internal external clock select bit 1 External clock Note Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode TxD RxD I O polarity reverse bit Usually set to 0 C Note Set the corresponding port direction register to 0 Setting UARTi transmit receive control register i 0 to 3 UARTIi transmit receive control register 0 UiCO Address 03AC16 36C16 033C16 32C16 BRG count source select bit b1 bO 0 0 fi is selected 01 fs is selected 1 0 f32 is selected 1 1 Inhibited CTS RTS function select bit Valid when bit 4 0 0 CTS function is selected Note 1 Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS disable bit 1 CTS RTS function disabled Data output select bit Note 2 0 TxDi SDAi and SCLi pin is CMOS output 1 TxDi SDAi and SCLi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note 1 Set the corresponding port direction register to O Note 2 UART2 transfe
411. stop control bit to 1 stops oscillation and causes the processor to go into stop mode 1 Setting interrupt to cancel stop mode Interrupt control register KUPIC Address 004116 SIRIC i 0 2 3 Address 004A16 004216 005516 S13BCNIC Address 004316 TAIIC i 0 to 4 Address 005416 004516 004716 005716 005916 SiTIC i 0 to 3 Address 005316 005116 004F16 004D16 RSMIC Address 005816 VBDIC Address 005Cie INTiIC i 0 to 2 Address 005F16 004416 005E16 be bo Be bo S1RIC Address 004816 BPPP LLL Doe sozecnic Address 004916 Interrupt priority level select bit Interrupt priority level select bit Make sure that the interrupt priority Make sure that the interrupt priority level of the level of the interrupt which is used to interrupt which is used to cancel the wait mode is cancel the wait mode is higher than higher than the processor interrupt priority IPL of the processor interrupt priority IPL of the routine where the WAIT instruction is executed the routine where the WAIT instruction is executed Reserved bit Must always be set to 0 Disable the interrupt not to be used for cancelling stop mode K 2 Interrupt enable flag I flag 1 y 3 Canceling protect b7 bo 1 DDDD lt Dx Protect register Address 000A16 PRCR L Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 and frequency synthesize
412. stop mode A key input interrupt occurs to execute the key input interrupt handling routine 3 Sequentially set POo through P03 to L to determine which key was pressed 4 When the process to determine the key pressed is completed change the output from POo through P03 to L again and enter stop mode Rev 2 00 Oct16 2006 page 321 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 Controlling Power Applications 1 Shift to stop mode 2 Cancel a stop mode 3 Key scan Key matrix scan 4 Shift to stop mode POo output P01 output P02 output P03 output ee O a cee o P100 to P103 input or S Key input on KeyON 1 ea ear Key input interrupt processing CPU clock lt j fae Stop mode Stop mode Figure 3 8 1 Operation timing of controlling power using stop mode POo P01 P02 P0O3 I O port P100 Klo P101 Kh P102 Kl2 P103 KI3 Figure 3 8 2 Example of circuit of controling power using stop mode Rev 2 00 Oct16 2006 page 322 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 Controlling Power Applications Initial condition b7 bo Pull up control register 2 b7 bo Port PO direction register Address 03FE16 T1117111 Address 03E216 PUR2 PDO P100 to P103 pulled high Key scan output port Port P10 direction register Address 03F616 PDO bo Key input interrupt control register b7 i Add 0041 Key scan input
413. synchronization with the clock The following is an overview of the clock synchronous serial I O 1 Transmission reception format 8 bit data 2 Transfer rate If the internal clock is selected as the transfer clock the divide by 2 frequency resulting from the bit rate generator division becomes the transfer rate The bit rate generator count source can be se lected from the following f1 f8 and f32 Clocks f1 fg and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Furthermore if an external clock is selected as the transfer clock the clock frequency input to the CLK pin becomes the transfer rate 3 Error detection Only overrun errors can be detected Overrun error is an error that occurs if the serial interface starts receiving the next data item before reading the contents of the UARTi receive buffer register and receives the 7th bit of the next data 4 How to deal with an error e When receiving data read an error flag and reception data simultaneously to determine which error has occurred If the data read is erroneous initialize the error flag and the UARTi receive buffer register then receive the data again To initialize the UARTIi receive buffer register 1 Set the receive enable bit to 0 disable reception 2 Set the serial I O mode select bit to 0002 invalid serial I O 3 Set the serial I O mode select bit 4 Set the receive enable bit to 1 again enable reception e To
414. system clock control registers 0 and 1 and frequency synthesizer related registers 1 Write enabled Setting frequency synthesizer control register b7 Frequency synthesizer control register Address 03DC16 FSC Frequency Synthesizer enable bit 1 Enabled Clearing the protect Protect register Address 000A16 PRCR Enable bit for writing to system clock control registers 0 and 1 and frequency synthesizer related registers 0 Write disabled Wait for 2ms y Wait till the frequency synthesizer stabilized Frequency synthesizer control register Address 03DC16 FSC Frequency synthesizer lock status bit 0 Unlocked 1 Locked Frequency synthesizer stabilized Note Check the frequency synthesizer lock status bit It is necessary to recheck C after a wait of 0 1ms if it is 0 Setting USB control register b7 USB control register Address 000C16 1 0 0 0110 0 USBC USB clock enable bit 1 Enable Supply 48MHZ clock USB resume interrupt request process is complete Figure 2 8 30 USB resume interrupt request processing routine Rev 2 00 Oct 16 2006 page 168 of 354 ENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 8 5 USB Operation Endpoint 0 Endpoint 0 is used only for control transfer Endpoint 0 FIF
415. t OUTxCSR11 ISO Select isochronous endpoint No STALL by CPU OUTxCSR12 SEND_STALL STALL by CPU 0 AUTO_CLR disabled OUTxCSR13 AUTO_CLR 1 AUTO_CLR enabled Reserved Must always be set to 0 Note Always read a 0 when writing to this bit Figure 2 8 40 USB endpoint x x 1 to 4 OUT control and status register Rev 2 00 Oct 16 2006 page 185 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 USB function USB endpoint x x 1 to 4 OUT MAXP register This register indicates endpoint x x 1 4 OUT maximum packet size The default value is 0 byte When the endpoint is initialized due to any reason such as that the request for setting the endpoint SET_DESCRIPTOR SET_CONFIGURATION SET_INTERFACE etc is received from the host CPU change the endpoint x OUT maximum packet size value by writing in this register Set a packet size value specified for every transfer type to be used The configuration of USB endpoint x x 1 to 4 OUT MAXP register is shown in Figure 2 8 41 USB Endpoint x OUT MAXP register b15 b8 b7 b0 b7 Symbol Address When reset 0 0 EPxOMP x 1 4 02B816 02C016 000016 a a OS cr a a a 02C816 02D016 Bit Symbol Bit Name Function F Set maximum packet size of OMAXP9 0 Maximum packet size EPx OUT Reserved Must always be 0 Figure 2 8 41 USB endpoint x x 1 to 4 OUT M
416. t and the transaction types are determined according to the configuration pat tern The transaction types and formats are shown below OIN transaction OUT transaction SETUP transaction idle state idle state idle state OUT SETUP DATAO 1 DATAO v idle state idle state idle state lsochronous transaction IN lsochronous transaction OUT idle state idle state LIN OUT DATAO DATAO l idle state idle state Token packet issued by the host Handshake packet issued by the host Data packet issued by the host Data packet issued by the device Handshake packet issued by the device Figure 2 8 3 Formats of transactions Rev 2 00 Oct16 2006 page 130 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function Communication Sequence The control transfer is used common to all devices at the time of setup which consists of three kinds of stages being combined for one processing The control transfer starts with setup stage According to the content data stage control read transfer or control write transfer is executed followed by status stage being executed to finally complete one processing In control transfer use of endpoint 0 has been specified The communication sequence of control transfer is shown in Figure 2 8 4 Control trasnfer Control Read SETUP stage DATA stage Status stage DATAO DATA1 0 Hands
417. t b4 b3 00 Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 source f X n 16MHz f Xc n 32 768kHz 00 fi 62 5ns 500ns 2us 976 56us b15 b8 b7 bo 3Ere Timer AO register TAO Address 0387 038616 b7 b0 b7 bo XXXIII SE flag Address 038016 Timer AO count start flag 1 Starts counting Figure 3 5 4 Set up procedure of memory to memory DMA transfer 2 Rev 2 00 Oct 16 2006 page 310 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 CRC Snoop Function Applications 3 6 CRC Calculation SFR Access Snoop Function in Clock Synchronous Serial Data Transmit Overview The M30245 group by use of DMAC transfers data from the internal RAM to the UART1 and the result is transferred to the UART1 by use of SFR access snoop function The block diagram is shown in Figure 3 6 1 and the setting routine is shown in Figure 3 6 2 to Figure 3 6 4 The peripheral functions to be used are as follows e DMAC 1 Channel e Internal RAM address 0040016 512 bytes e UART1 Clock synchronous serial I O mode e CRC calculation circuit e SFR access snoop function Specifications 1 Data transfer is performed starting at address 0040016 from the area with 512 bytes to the UART1 Data are transferred from area between the address 0040016 and the 512nd byte to the UART1 Transfer is exec
418. t control transfer is supported without any exception for the devices compliant with USB Bulk Transfer This transfer is used to transfer the data which delay does not cause any problem in aperiodic com munication which occurs suddenly This is used to transfer large quantities of data Hardware detects errors in order to guarantee transfer data A request for retransmission is issued by detecting of any error For example they include the output data from printer and image data of scanner Rev 2 00 Oct 16 2006 page 127 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function Interrupt Transfer This transfer is used to notify the host of aperiodic and low frequency data from the device For example they include the notification of out of paper in printer and data concerning devices such as the mouse and the keyboard isochronous Transfer This transfer is used for continuous and periodic communication Once the communication path is established a transfer rate is guaranteed with a limited delay The maximum size of transfer data is specified by the endpoint which is read by the host as the configuration data of the device Based on this data transfer within the frame is scheduled and the bus time required for transfer of the maxi mum size of data is secured with preference Although the band width and the transfer rate of data transfer are guaranteed retransmission is not executed even if an error exists in the transfer This is u
419. t software trigger and DMA trigger Software trigger is always enabled When software trigger is selected DMA transfer is generated by writing 1 to software DMA interrupt request bit When other factor is selected DMA transfer is generated by generating corresponding interrupt request 4 Channel priority High to low priority DMA0O DMA1 DMA2 DMA3 5 Writing to a register When writing to the source register or the destination register with DMA enabled the content of the register with a fixed address will change at the time of writing Therefore the user should not write to a register with a fixed address when the DMA enable bit is set to 1 The contents of the register with forward direction selected and the transfer counter are changed when reloaded A reload occurs either when the transfer counter underflows or when the DMA enable bit is re enabled after having been disabled The reload register can be written to as in normal conditions Rev 2 00 Oct 16 2006 page 240 of 354 7RENESAS REJ09B0340 0200 M30245 Group 6 Readi ng to a register The reload register can be read to as in normal conditions 7 Switching function a Switching between one shot transfer and repeated transfer One shot transfer refers to a mode in which DMA is disabled after the transfer counter underflows Repeated transfer refers to a mode in which a reload is carried out after the transfer counter under flows T
420. t 0 interrupt USB function interrupt and USB SOF interrupt The USB function control unit can control the state transition of the USB device based on these interrupt requests 1 Transfer Type The USB specifications largely concern 2 types including the one for the host side PC Hub to control the connected peripheral devices and the other for the peripheral device side Device which is con nected to the real machine Further depending on the number of data dealt with in the device the peripheral devices which require more data concerning image audio etc at one time have the communication specification with high transfer speed 12Mbps called Full Speed function while the peripheral devices keyboard mouse which require less data have the communication specification with low transfer speed 1 5Mbps called Low Speed function Further a communication specification with even higher speed is available which is called Hi Speed function 480Mbps These communication specifications are each determined by device class of the peripheral devices and the transfer type to be used is determined for each peripheral device The M30245 group supports the following four kinds of transfer types Control Transfer This transfer is used for communication of request response form bi directional in aperiodic com munication which occurs suddenly This is mainly used at the time of setup As all the devices have to be supported in the standard device reques
421. t bit CS3Ww CS3 wait bit Chip select expansion register RL cece Symbol Address When reset CSE 001Bi6 0016 7 CSEOW CS0 wait expansion bit 1 Wait state CSE1W CS1 wait expansion bit 2 Wait states 3 Wait states CSE2W CS2 wait expansion bit Inhibited CSE3W CS3 wait expansion bit Note 1 Set CSEiW bits i 0 to 3 after setting the corresponding CSiW bit i 0 to 3 of the CSR register to 0 When CSiW bits are set to 1 CSEiW bits must be returned to 002 Figure 4 2 3 Level of BYTE pin and external data bus width 4 2 3 R W Modes The read write signal that is output when accessing an external area can be selected between the RD BHE WR and the RD WRH WRL modes by setting the R W mode select bit bit 2 of the processor mode register 0 address 000416 Use the RD BHE WR mode to access an 8 bit and a 16 bit wide RAM and the RD WRH WRL to access a 16 bit wide RAM When the M30245 is reset the RD BHE WR mode is selected by default To switch over the R W mode change the RD BHE WR to the RD WRH WRL mode before accessing an external RAM Refer to the connection examples of RD BHE WR and RD WRH WRL shown in Section 4 3 Connection Examples Rev 2 00 Oct 16 2006 page 333 of 354 7tENESAS REJ09B0340 0200 M30245 Group 4 External Buses 4 3 Connection Examples 4 3 1 16 bit Memory to 16 bit Width Data Bus Connection Example Figure 4 3 1 shows an example of connecting M5M51016BTP SRAM
422. t cause select register b7 bo DMAi request cause select register Address 03B816 03BA16 03B016 03B216 DOI pmisui oto 3 Li tT DMA request cause select bit Software trigger is always enabled Software DMA request bit Set to 0 C Setting DMAi control register b7 b0 1 lolololilo DMAi control register Address 002C16 003C16 018C16 019C16 DMiCON i 0 to 3 Transfer unit bit select bit 0 16 bits Repeat transfer mode select bit 1 Repeat transfer DMA request bit 0 DMA not requested DMA enable bit 0 Disabled Source address direction select bit 0 Fixed Bit 4 and bit 5 cannot be set to 1 simultaneously Destination address direction select bit C 1 Forward Bit 4 and bit 5 cannot be set to 1 simultaneously Setting DMAi source pointer DMAO source pointer Address 002216 to 002016 SARO DMA1 source pointer Address 003216 to 003016 SAR1 DMA2 source pointer Address 018216 to 018016 SAR2 DMAS source pointer Address 019216 to 019016 SAR3 b23 b16 b15 b8 b7 bO b7 b0 b7 b0 PIX YN Le Source pointer Stores the source address a Setting DMAi destination pointer DMAO destination pointer Address 002616 to 002416 DARO DMA1 destination pointer Address 003616 to 003416 DAR1 DMA2 destination pointer Address 018616 to 018416 DAR2 DMAS destination pointer Address 019616 to 019416 DAR3 b19 b16 b15 b8 b3 b0 b7 b0 b
423. t flag 1 Starts counting Start countin Figure 3 2 4 Set up procedure of variable period variable duty PWM output 2 Rev 2 00 Oct 16 2006 page 302 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 Timer A Applications 3 3 Buzzer Output Overview The timer mode is used to make the buzzer ring Figure 3 3 1 shows the operation timing and Figure 3 3 2 shows the set up procedure Use the following peripheral function e The pulse outputting function in timer mode of timer A Specifications 1 Sound a 2 kHz buzz beep by use of timer AO 2 Effect pull up in the relevant port by use of a pull up resistor When the buzzer is off set the port high impedance and stabilize the potential resulting from pulling up 3 Connect a 16 MHz oscillator to XIN Operation 1 The microcomputer begins performing a count on timer AO Timer AO has disabled interrupts 2 The microcomputer begins pulse output by setting the pulse output function select bit to Pulse output effected P70 changes into TAQOUT pin and outputs 2 kHz pulses 3 The microcomputer stops outputting pulses by setting the pulse output function select bit to Pulse output not effected P70 goes to an input pin and the output from the pin becomes high impedance 1 Start count 2 Buzzer output ON 3 Buzzer output OFF Timer AO l overflow timing i q Count start flag Pulse output function select bit P70 output High impedance i High im
424. t flag to 1 causes the A D converter to start the conversion on voltage input to the ANo pin 2 After the A D conversion of voltage input to the ANo pin is completed the content of the successive comparison register conversion result is transmitted to AD register 0 The A D converter converts all analog input pins selected by the user The conversion result is trans mitted to AD register i corresponding to each pin every time conversion on one pin is com pleted 3 When the A D conversion on all the analog input pins selected is completed the A D conver sion interrupt request bit goes to 1 At this time the A D conversion start flag goes to 0 The A D converter stops operating 1 Start A D conversion 2 After A D conversion on ANo pin is complete A D converter begins converting all pins selected 8 bit resolution 28 oAD cycles i 8 bit resolution 28 paD cycles 10 bit resolution 33 aD cycles 10 bit resol ution 33 aD cycles 3 A D conversion is complete a ili a vu Set to 1 by software A D conversion 4 start flag AD register 0 y Result AD register 1 AD register i A D conversion 1 interrupt request o y Result bit Note Wh
425. t port Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate PD9_2 Port P92 direction register 9 Input mode i Functions as an input port ae 1 Output mode PD9_3 Port P93 direction register Functions as an output port Nothing is assigned In an attempt to write to this bit write O The value if read turns out to be indeterminate Figure 2 17 3 Programmable I O ports related registers 2 Rev 2 00 Oct16 2006 page 289 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Programmable I O Ports Port Pi register Note 2 b7 b6 b5 b4 b3 b2 bi b Symbol Address When reset Pi i 0 to 7 10 03E016 03E116 03E416 03E516 03E816 Indeterminate 03E916 03EC16 03ED16 03F416 Indeterminate Bisyo Fon Po register Data is input and output to and from 9 0 Port Pit register each pin by reading and writing to O 0 Port Pi2 register and from each corresponding bit 00 Port Pis register err i oo 1 H level data Note 1 Port Pia register 00 Port Pis register 00 10 OO Pie Port Pis register 10 0 Port Piz register oO Note 1 Since P70 and P71 are N channel open drain ports the data is high impedance Note 2 In memory expansion and microprocessor mode the contents of corresponding port Pi register of pins Ao to A19 Do to D15 CSo to CS8 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified Port P8 re
426. ta at falling edge of transfer clock no clock delay slave mode e Reception Operation WITH inputting reception data at rising edge of transfer clock clock delay slave mode 6 Input to the serial interface special function and the direction register To input an external signal to the serial interface special function set the direction register of the relevant port to input 7 Pins related to the serial interface special function e CLKo CLK1 CLK2 CLK3 pins Input output pins for the transfer clock e RxDo SRxDo RxD1 SRxD1 RxD2 SRxD2 RxD3 SRxD3 pins Input pins for data e TxDo STxDo TxD1 STxD1 TxD2 STxD2 TxD3 STxD3 pins Output pins for data 8 Registers related to the serial I O Figure 2 5 1 shows the memory map of serial interface special function related registers and Figures 2 5 2 to 2 5 7 show Serial interface special function related registers Rev 2 00 Oct 16 2006 page 86 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function 004216 UART2 receive ACK interrupt control register S2RIC N 004316 UART1 3 Bus collision interrupt control register S13BCNIC 035F16 iN Interrupt cause select register IFSR 004816 UART1 receive ACK SSI1 interrupt control register S1RIC N 036416 004916 UARTO 2 Bus collision interrupt control register SO2BCNIC UART1 special mode register 4 U1SMR4 036516 004A16 UARTO receive ACK SSIO i
427. ta from this register Note 1 Writing to this register might cause a system error Note 2 Read only from this register with a Word command or a Byte command to the lower 8 bits Do not read a byte of data from the upper 8 bits b8 b15 Figure 2 8 13 USB x x 0 4 OUT FIFO data register The endpoint x IN OUT FIFO mapping is shown in Figure 2 8 14 Endpoint FIFO 64 bytes gt 64 bytes 7 This area is allocated for IN OUT FIFOs of the endpoint 1 to 4 The FIFO size and start position can be specified for every 64 byte by USB EPx IN FIFO configuration register and USB EPx OUT FIFO configuration register 3328 bytes Endpoint 0 IN FIFO 128 bytes 256 bytes OUT FIFO 128 bytes Figure 2 8 14 Endpoint x IN OUT FIFO mapping Rev 2 00 Oct 16 2006 page 142 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 USB function 2 Enable of USB Function Control Unit The initialization procedure of the USB function control unit of the M30245 group after hardware reset is explained below Further for power supply being supplied from the USB the total driving current has to be controlled to keep equal to or below 100mA Setting of the frequency synthesizer 1 Clear protect 2 Set the frequency synthesizer related registers to generate 48MHz required for the fUSB 3 Enable the frequency synthesizer by setting bit 0 in the frequency synthesizer control register to T 4 Disable pr
428. ta in synchronization with the rising edges of the transfer clock 4 When 1 byte data lines up in the UARTIi receive register the content of the UARTi receive register is transmitted to the UARTi receive buffer register At this time the receive complete flag and the UARTIi receive interrupt request bit goes to 1 5 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read Note e Set RxDi pins port direction register to 0 e Set SSi pin to H level If L level is input to the pin a fault error will be generated Rev 2 00 Oct 16 2006 page 98 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 Serial Interface Special Function Example of wiring Microcomputer Transmitter side IC Example of operation 1 Output L on the transmitter side IC 2 Reception enabled 4 Reception is complete 3 Start reception 5 Read of reception data B a aee E U Port Receive enable bit RE Transmit j enableibit TE Dumny data is set in UARTi transmit buffer register Transmit buffer empty flag TI CLKi Reception data is taken in YEEKEXEENEXEX EEE EXENENE ENE XOOEXEXEXEONE Transferred from UARTI receive register Read out from UARTIi receive buffer register to UARTIi receive buffer register 1 Receive complete 1 flag RI 9 Receive interrupt request bit IR Cleared to 0 when interrupt request is accepted
429. te 1 Always write 0 Note 2 Bits 15 to 12 are set to 00002 when the serial I O mode select bit bits 0 to 2 at addresses 03A816 036816 033816 032816 are set to 0002 or the receive enable bit is set to 0 Bit 15 is set to 0 when all of bits 14 to 12 are set to 0 Bits 14 and 13 are also set to 0 when the lower byte of the UARTi receive buffer register addresses 03AE16 036E16 033E16 032E16 is read Figure 2 5 2 Serial interface special function related registers 1 Rev 2 00 Oct 16 2006 page 88 of 354 REJ09B0340 0200 RENESAS M30245 Group 2 Serial Interface Special Function UARTI bit rate generator o 0 to 3 Note 1 2 Address When reset ru bo 03A916 Indeterminate 036916 Indeterminate 033916 Indeterminate 032916 Indeterminate Function Values that can be set Assuming that set value n BRGi divides the count source by 0016 to FFie Fo n 1 Note 1 Use MOV instruction to write to this register Note 2 Write a value to this register while transmit receive halts UARTI transmit receive mode register i 0 to 3 Symbol Address When reset b7 b6 b5 b4 b3 b2 bi bO UOMR 03A816 0016 U1MR 036816 0016 U2MR 033816 0016 U3MR 032816 0016 Function A i F Function Bit name During clock synchronous R iw serial I O mode During UART mode F Must be fixed to 001 Serial I O mode select bit v Transfer data 7 bits long O O Note 3 4 9 0 Serial 1
430. ted Frequency select bit 1 Note 2 0 fap 2 or fAD 4 is selected 1 fAD or fAD 3 is selected One shot mode is selected Note 1 ___ Trigger select bit 1 ADTRG trigger L Vref connect bit 1 Vref connected __________________ A D conversion start flag 0 A D conversion disabled Reserved bit Frequency select bit 0 Note 2 0 faD 3 or faD 4 is selected 1 faD or faD 2 is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Ne Note 2 When f XIN is over 10 MHz the fan frequency must be under 10 MHz by dividing and set aD frequency to 10 MHz or lower Setting A D conversion start flag b7 b0 CECILL TT AD control register 0 Address 03D616 ADCONO __________________A D conversion start flag 1 A D conversion started When ADTRG pin level becomes from H to L Start A D conversion i i AD registerO Address 03C116 03C016 ADO Reading conversion result AD register1 Address 03C316 03C216 AD1 b8 AD register2 Address 03C516 03C416 AD2 BO bO AD register3 Address 03C716 03C616 AD3 x x x x x x AD register4 Address 03C916 03C816 AD4 AD register5 Address 03CB16 03CA16 AD5 AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 O3CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversio
431. ted Reserved bit Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 When f XIN is over 10 MHz the fab frequency must be under 10 MHz by dividing and set oD frequency to 10 MHz or lower Setting A D conversion start flag b7 b0 AD control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Converts non selected pin after converting pins Start A D conversion selected through the A D sweep pin select bit Uri Transmitting conversion result to AD register i AD registerO Address 03C116 03C016 ADO AD register1 Address 03C316 03C216 AD1 b8 AD register 2 Address 03C516 030416 AD2 b7 b0 b7 bo AD register 3 Address 03C716 03C616 AD3 ACIN E AD register 4 Address 03C916 03C816 AD4 AD register5 Address 03CB16 03CA16 AD5 AD register6 Address 03CD16 03CC16 AD6 AD register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Setting A D conversion start flag b7 bo 0 AD control register 0 Address 03D616 ADCONO A D conversion start flag 0 A D conversion disabled Stop A D conversion Figure 2 9 16 Set up procedure of repeat sweep 1 mode Rev 2 00 Oct 16 2006 page 229 o
432. ted other than the FSC other than the USBC USBAD and frequency synthe sizer related registers Figure 2 8 29 added e USB endpoint 0 MAXP register SET_DESCRIPTOR gt GET_DESCRIPTOR 2 8 9 1 USB Communication added 2 Peripheral Circuit between the USB D pin and the USB D pin or deleted Figure 2 8 51 revised 3 Register Bit addresses 030016 to 033C16 excepting FSC gt other than the USBC USBAD and frequency synthesizer related registers Figure 2 11 2 CRCMR CRCSAR When reset revised CRCSAR Note added 2 11 3 The target SFRs include the the UART related registers gt The target SFRs include Serial Sound Interface related registers 2 13 1 When the external bus to the external areas added 2 16 1 2 Reducing the driving capacity in power consumption deleted 3 revised 4 added Figure 2 16 5 3 following JMP B instruction added Figure 2 16 6 Insert at least four NOPs after the WAIT instruction is executed gt Insert JMP B instruction before NOPs after the WAIT instruction 2 16 4 3 revised 4 added d deleted Table 2 17 1 revised Table 2 17 3 AVss VREF USB D USB D LPF VobusDTCT Note 6 added Figure 2 17 2 PCR revised Figure 2 17 3 PD9 When reset revised 3 3 deleted Figure 3 7 4 The DMA transfer request from is transmit request state gt The DMA tansfer request from in
433. ted m 2 when 2 waits selected and m 3 when 3 waits selected 2 Address access time ta A Address access time ta A must satisfy the following conditional expressions a Vcc 3 0 to 3 6 V With the Wait option cleared ta A lt 109 f BCLK 80 ns With the Wait option selected ta A lt m 1 x 109 f BCLK 80 ns m 1 when 1 wait selected m 2 when 2 waits selected and m 3 when 3 waits selected 80 ns td BCLK AD tsu DB RD th BCLK RD address output delay time data input setup time RD signal output hold time 3 Chip select access time ta S Chip select access time ta S must satisfy the following conditional expressions a Vcc 3 0 to 3 6 V With the Wait option cleared ta S lt 109 f BCLK 80 ns With the Wait option selected ta S lt m 1 x 109 f BCLK 80 ns m 1 when 1 wait selected m 2 when 2 waits selected and m 3 when 3 waits selected 80 ns td BCLK CS tsu DB RD th BCLK RD chip select output delay time data input setup time RD signal output hold time Rev 2 00 Oct 16 2006 page 340 of 354 AS REJ09B0340 0200 RENES M30245 Group 4 External Buses 4 Output enable time ta OE Output enable time ta OE must satisfy the following conditional expressions a Vcc 3 0 to 3 6 V With the Wait option cleared ta OE lt 109 f BCLK x 2 60
434. ted or when a new SETUP packet is received this flag is automatically set to 0 When DATA_END_MASK bit is set to 1 at the time of resetting the DATA_END flag is always set to 0 and endpoint 0 interrupt factor does not occur by clearing the DATA_END flag to 0 e FORCE_STALL Flag This flag shows the error occurrence in control transfer This flag is set to 1 for reporting an error when at least one of the following conditions occurs IN token without SETUP stage is received An incorrect data toggle is received in the STATUS stage DATAO is used An incorrect data toggle is received in the SETUP stage DATA 1 is used Data exceeding the one specified in the SETUP stage are required IN token is received after the DATA_END flag is set Rev 2 00 Oct 16 2006 page 170 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 USB function Data exceeding the one specified in the SETUP stage are required An OUT token is received after the DATA_END flag is set Data exceeding the one specified are received in USB endpoint 0 MAXP register Except for when an incorrect data toggle is received in the SETUP stage on occurrence of the above condition STALL is transmitted to the IN OUT token with a problem When an incorrect data toggle is received in the SETUP stage ACK is returned to the SETUP stage and STALL is returned to next IN OUT token The STALL handshake occurring by the above condition completes the co
435. ter setting for input mode connect every pin to Vss or Vcc via a resistor or after setting for output mode leave these pins open Note 1 Note 2 Note 3 XouT Note 1 Open NMI Connect to Vcc via a resistor pull up UVcc AVcc Connect to Vcc AVss VREF BYTE Connect to Vss USB D USB D Open LPF Open VbusDTCT Open Note 1 When an external clock is input to the XIN pin Note 2 If setting these pins in output mode and opening them ports are in input mode until switched into output mode by use of software after reset Thus the voltage levels of the pins become unstable and there can be instances in which the power source current increases while the ports are in input mode In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes setting the contents of the direction registers periodically by use of software increases program reliability Note 3 Output L if port P70 and P71 are set to output mode Port P70 and P71 are N channel open drain output Rev 2 00 Oct 16 2006 page 285 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Programmable I O Ports b Memory expansion mode microprocessor mode Table 2 17 3 Examples of working on unused pins in memory expansion mode or microprocessor mode Pin name Connection Ports P6 to P10 excluding P85 After setting for input mode connect every pin to Vss or Vcc
436. terface ccccssssseeeeeeeeeeeeeeeeeeeees 316 3 8 Controlling Power Using Stop Mode ccccceeeeseeeeeeeeeeeeeeeeeeeeenseeeeeneeeseeeeeeeeeeeeeees 321 3 9 Controlling Power Using Wait Mode cccccssssseeeceeeeseeeeeeeeeeeeeesneeeeeeeeeeneeeeeeeeeeees 325 Chapter 4 External BUSS cccceceeseescessssseseeeeeesees O29 4 1 Overview of External Buses scisisicecesecssecnscsssnnsscesecsscwndetenesavenssiesncesnsasesessncecssennsesesecede 330 A Ala CCOSS cited E E E EE utente 331 4 2 1 Data Bus Width iiic2ccccsccdcdctecescacaee aed cae a a aaae a a aa a aa aaaea A aa a a di raaa Edea apiki ia Kandia niaii 331 4 2 2 Chip Selects and Address BUS cccssecceseeeseseeeeseeeeeesaeseseeeeeesaeseseeeeenseeeeseaeeseseeeeseaesaaneaeeeseeseseeaeeees 332 423 RIN MOJE S ii a aAa S aada tet cde daana eaaa e aaa a ade a da a aa a a E Eaa 333 4 3 Connection Examples wiscsasciicidsiindeeadeacinzeasusdedwineannnaicteuianiinadeaweseweussbaaideiensneauadeniliny 334 4 3 1 16 bit Memory to 16 bit Width Data Bus Connection Example csscceeecesseeeeseeeeeeeeeseeeeeeenea 334 4 3 2 8 bit Memory to 16 bit Width Data Bus Connection Example ccsssssessseeeseeseeesseeeeesneeennensnes 335 A 3 4 3 3 8 bit Memory to 8 bit Width Data Bus Connection Example ccsssecesseeeeseseeeeseeeeeeseeseseeeeeeeas 337 4 3 4 Two 8 bit and 16 Bit Memory to 16 Bit Width Data Bus Connection Example scsse
437. terrupt USAGE cseecceeeeeseeeeeeeeeeeseeeeneneeesesaeseseeeeseseeseneeneeeeas 258 2 13 2 Operation of Address Match Interrupt cccceeceseseeeeseeeeseneeeeseeeeeseeeseseeeeeeeeeeesnaeeenseeeesenaeensneeeeeas 260 2 14 Key Input Interrupt Usage c eeeeeeeeeeeeeeeeeee ee eeeeeeeeeseeeeessnnnnnnnnnnneeeeneeeeeeeeeeees 262 2 14 1 Overview of the key input interrupt USAGE cccesceeeeeee esses ee eneeeeeeeeeeeneeeeeeeeeeeseaesenseeeeseesenseeeeneas 262 2 14 2 Operation of Key Input Interrupt ceceeeeeeteeeeeeeee ences ee eeeeeeeeaeeeaneeeeneeeeesneeesnseeeessnaesaaeeeeesseeseneeeeenes 265 2 15 Multiple interrupts Usage iiiaiciisecesieciaedeededestnndasantandiuiainandeaseadweniaudastasaedaeaenmasauniuiind 267 2 15 1 Overview of the Multiple interrupts usage sssssssusssunneuunnnennenennenunnnunnnnunnnnnnnunnnnnnnnnnnnnnnnn nenne nnmnnn 267 2 15 2 Multiple Interrupts Operation ccssecceceeeeeeceeeeeeeeeeeeeeseseeeeeeeesesneeeeneneeesneaeenseeeessnaesaseeeeseseeseaeeeeeeeas 272 2 16 Power Control Usage isiscsacisiicisssdesteasacandeaaieawivinnandanacrainaitoadadwoanasdoubasieumieencaassudianais 274 2 16 1 Overview of the power control USAGE cceseceseeeeeeseeeeseeeeeeseeseseeeeenseeeeseaaesneeeeeseaesasneeeeeseeseneeeeenes 274 2 16 2 Stop Mode Set Up sucess ccccsecececesscetiee cake cacatetecectas cans aaa adaa Ea araa Ee aa aaa aaa aa daada aaa 280 2160 3 Wait M de S t UP e a aa a ea a e e ae
438. terrupt request bit goes to 1 Also the first bit of the transmission data is transmitted from the TxDi pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges 4 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that transmission is completed The transfer clock stops at H level 5 If the next transmission data is set in the UARTi transmit buffer register while transmission is in progress before the eighth bit has been transmitted the data is transmitted in succession Rev 2 00 Oct 16 2006 page 45 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 Clock Synchronous Serial I O Example of wiring Microcomputer Receiver side IC CLKki CLK TxDi RxD CTSi Since TXD2 pin is N channel open drain this pin needs pull up resistance Example of operation Transfer clock Transmit enable bit TE Transmit buffer empty flag TI CTSi TxDi Transmit register empty flag TXEPT Transmit interrupt request bit IR 1 Transmission enabled 4 Transmission is complete 2 Confirming CTS 5 Transmit next data 3 Start transmission Tc Data is set to UARTI transmit buffer register Transferred from UARTI transmit buffer register to UARTIi transmit register Stopped pulsing because 1 Stopped pulsing because CTSi H Y transfer enable bit 0 H i P
439. the USB endpoint 1 OUT FIFO to SS interface 1 transmit buffer register and fetches one packet data The block diagram is shown in Figure 3 7 1 and the setting routine is shown in Figure 3 7 2 to Figure 3 7 4 The peripheral functions to be used are as follows e DMAC 1 channel e USB endpoint 1 OUT Receive e Serial sound interface 1 Specifications 1 Receive packet data of the endpoint 1 OUT FIFO are transferred to SS interface 1 transmit buffer register Transfer is executed every time the DMA transfer factor of the serial sound interface 1 occurs 2 Use the DMAO to transfer data from the endpoint 1 OUT FIFO to SS interface 1 transmit buffer register Select the serial sound interface 1 transmit to the DMAO request factor Select the single transfer mode and set the DMAO transfer counter to 1 2 X the data count of one packet received with endpoint 1 OUT 1 3 Set the endpoint 1 OUT maximum packet size to 288 bytes when sampling 48KHz 24 bit stereo and disable the AUTO_CLR function The data count of receive packet of endpoint 1 endpoint 1 OUT write count register is set to 288 bytes Endpoint 1 OUT is used in isochro nous transfer 4 On completing the DMAO transfer fetch of one packet data from the endpoint 1 OUT FIFO is completed by setting CLR_OUT_BUF_RDY bit of endpoint 1 to 1 Operation 1 Initialize the DMAO related registers in the state which DMA is disabled and USB DMAO request register is not selected
440. the data read from the target SFR in CRC input register and executes CRC calcu lation The CRC calculation circuit can only calculate CRC codes on data 1 byte at a time Therefore if a target SFR is accessed in a word 16 bit bus cycle only 1 byte data are stored into CRC input register 5 When 1 byte data is stored in CRC input register CRC codes are generated in CRC data register based on the stored data and the content of CRC data register Generation of CRC codes for 1 byte of data is completed in two machine cycles Rev 2 00 Oct 16 2006 page 252 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Watchdog Timer 2 12 Watchdog Timer 2 12 1 Overview The watchdog timer can detect a runaway program using its 15 bit timer prescaler The following is an overview of the watchdog timer 1 Watchdog timer start procedure When reset the watchdog timer is in stopped state Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count The watchdog timer once started operating cannot be stopped by any means other than stopping conditions 2 Watchdog timer stop conditions The watchdog timer stops in any one of the following states a Period in which the CPU is in stopped state b Period in which the CPU is in waiting state c Period in which the microcomputer is in hold state 3 Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the
441. the host PC to recognize the USB Attach Detach varies depending on the whole system state such as substrate resistance components capacitance components USB cable capacitance and substrate characteristics and processing speed of the host Fully evaluate on the system subject to actual use Connect all the passive parts of the LPF pin as close to the LPF pin as possible Connect an insulating connector ferrite beads between the AVss pin and the digital Vss between the AVcc pin and the digital Vcc Also at this time when an A D converter is used connect the Vref pin to the AVcc pin Rev 2 00 Oct 16 2006 page 210 of 354 7RENESAS REJ09B0340 0200 M30245 Group Frequency synthesizer lenable lock Figure 2 8 51 680pF 10 0 1uF 10 Figure 2 8 52 Passive part of LPF pin Rev 2 00 Oct 16 2006 page 211 of 354 REJ09B0340 0200 2 USB function P90 control enable Ca PORT90_ ATTACH SECOND DETACH USB Transceiver The value of resistance and capacitor and the configuration will depened on the layout of printed circuit board Peripheral circuit block diagram Ferrite Beads AVcc 80pin Decoupling Capacitors Figure 2 8 53 Decoupling capacitor 7tENESAS M30245 Group 2 USB function 3 Register Bit When the USB reset interrupt request occurs all the USB internal registers become reset state To resume communication each endpoint needs to be initialized All the USB re
442. the transmit data in sequence by one packet size the maximum packet size set in the EPxIMP When the last one packet is smaller than the size set in the EPxIMP it is received as a short packet When IN token is received from the host CPU while SEND_STALL bit is set to 1 STALL response is automatically returned When IN token is received from the host CPU while there are no packet data in the IN FIFO NAK response automatically is returned When IN token is received from the host CPU while there are packet data in the IN FIFO data are transmitted by using the current data toggle sequence bit On completing one packet data transmit on receiving ACK from the host CPU the IN FIFO status is updated the IN BUF_STS1 and IN_BUF_STSO flags are updated and data toggle sequence bit is toggled DATAO DATA1 or DATA1 DATAO At this time the endpoint x IN interrupt request occurs When one packet data has been unsuccessfully transmitted ACK not received from the host CPU the data are re trans mitted in the next IN token the same data are transmitted in the same toggle Rev 2 00 Oct 16 2006 page 202 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 3 Isochronous Transfer Endpoints 1 to 4 Transmit Type of Transmit Transfer When endpoints 1 to 4 IN are used for isochronous transfer ISO bit and INTPT bit of USB endpoint x IN control and status register are respectively set to 1 and to O for isochro
443. ting kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Activation processing routine DMA activation DMAO can be activated before or after DMA1 PECSELAEARIR TELLS RERARA ERS L EE EESE RA CELEN ARE ARAREE SS SEREREAT AORTA SARE ATOR ESE RAANAS ROLES ES ERN CERES EE RARER E dmOcon 0x18 DMAO start 16bit SRC inc single dmicon 0x28 DMA1 start 16bit DES inc single Serial Sound Interface is stopped at this point SH RERAEESES Serial Sound Interface is enabled and audio data transmission reception starts Continued to the next page Rev 2 00 Oct 16 2006 page 116 of 354 AS REJ09B0340 0200 RENES M30245 Group 2 Serial sound interface Continued from the previous page Serial Sound Interface activation routine for 16 bits AAA eee iA A eR RRR ERR RRR R ER Ek ifdef OUT_Q_BIT_NO_16 ssitmr0 0x01 SSIEN 1 ssi1mr0 Oxf1 16bit MSB justified ssitmr1 0x21 SCK neg WS neg MSB first normal ssitmr0 Oxf7 16bit Tx enable Rx enable MSB justified endif Serial Sound Interface activation routine for 24 bits 88 eR AERA RRR AA RRR ER RE ARE AEH ifdef OUT_Q_BIT_NO 24 ssitmr0 0x01 SSIEN 1 ssi1mr0 0xd1 24bit MSB justified ssitmr1 0x21 SCK neg WS neg MSB first normal ssi1mr0 Oxd7 24bit Tx enable Rx enable MSB justified endif Serial Sound I
444. to the internal RAM waveforms are not output to the RD and WR pins Figure 3 5 1 Operation timing of memory to memory DMA transfer Rev 2 00 Oct 16 2006 page 307 of 354 7tENESAS REJ09B0340 0200 M30245 Group 3 DMAC Applications Source area Destination area F600016 F600016 content 0040016 F600116 content F600216 content F607F16 Temporary RAM F607F16 content 0047F16 80016 Data transfer by DMAO Data transfer by DMA1 Figure 3 5 2 Block diagram of memory to memory DMA transfer Rev 2 00 Oct16 2006 page 308 of 354 RENESAS REJ09B0340 0200 M30245 Group 3 DMAC Applications Initialization of DMAO b4 b3 b2 b1 b23 b16b15 b23 b16b15 b7 b0 b7 b15 b7 b7 b0 b7 b0 bo b8 b7 b8 b7 oe Ome b0 b8 b7 b0 DMAO request cause select register DMOSL Address 03B816 DMA request cause select bit 00100 Timer AO Software DMA request bit 0 Software is not generated DMAO source pointer SARO b0 DMAO destination DARO pointer b0 DMAO transfer counter TCRO bo Xole DMAO control register DMOCON Address 002C16 Transfer unit bit select bit 1 8 bits Repeat transfer mode select bit 1 Repeat transfer DMA request bit 0 DMA not requested DMA enable bit 1 Enabled Source address direction select bit 1 Forward Destination address direction select bit 0 Fixed Address 002216 002116 002016 Address
445. trigger is always enabled request bit Write 1 to trigger DSR bit Note 1 Software is always enabled Note 2 SSI Serial sound interface Note 3 This value should not be set DMAS3 request cause select register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address DM3SL 03B216 When reset 0016 Bit Symbol Bit Name Function Note 2 bi D 00 00 00 00 00 008 Agaga G G OA OHA a a DSELO DMA request cause select bits peepee 4342 4230000 TDVDVVCGGOCOCCCOCOF 00000000 00000 0008 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x DMA Disabled INTO falling edge INTO two edges USB3 Timer AO Timer A1 Timer A2 Timer A3 Timer A4 UARTO receive ACK SSIO receive UART1 receive ACK SSI1 receive UART2 receive ACK UART3 receive ACK UARTO transmit NACK SSIO transmit UART1 transmit NACK SSI1 transmit UART2 transmit NACK UARTS transmit NACK A D DMAO DMA1 DMA2 Disabled Note 3 Disabled Note 3 Disabled Note 3 x x Disabled Note 3 Nothing is assigned Write 0 when writing to these bits The value is 0 when read DSR Software DMA Software trigger is always enabled request bit Write 1 to trigger DSR bit Note 1 Software is always enabled Note 2 SSI Serial sound interface Note 3 This value shoul
446. tting 1 to this bit The configuration of USB ISO control register is shown in Figure 2 8 45 USB ISO Control register b15 b8 b7 bo b7 0 0 0 Symbol Address When reset mote eT E a E E 7 USBISOC 028C16 000016 Bit Symbol Bit Name Function Hardware auto flush disabled AUTO FL AO MUSDE Hardware auto flush enabled ISO update disabled IS0_UPD SON paate bi ISO update enabled 0 Artificial SOF disabled ART_SOF_ENA Artificial SOF enable bit Artificial SOF enabled Not generated by device Note 1 ART_SOF_SET Artificial SOF set flag Generated by the device 0 No action CLR_ART_SOF Clear artificial SOF set flag 1 Clear ART_SOF_SET flag Reserved Must always be 0 Note 1 Read only Note 2 Always read 0 Figure 2 8 45 USB ISO control register Rev 2 00 Oct 16 2006 page 195 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function USB endpoint x x 1 to 4 IN control and status register IN_BUF_STS1 IN_BUF_STSO flags These flags indicate IN FIFO state At the time of writing the data to be transmitted to the host PC in IN FIFO read these flags to confirm the IN FIFO state They are respectively set to 112 at the time of resetting When the corresponding endpoint be comes enable state from disable state the IN BUF_STS1 and the IN_BUF_STS0 flags are respec tivel
447. ttributes as follows 1 XXX register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset 0 XXX XXX 0016 a a ae A se 2 Bit symbol Bit name Function XXX select bit 00 XXX 01 XXX 1 0 Must not be set Vss 11 XXX a Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminats Reserved bit Must always be set to 0 EIEEE DEEA Function varies with each operation mode caieigieiare aime aie aire 3 be neeceneeceneeceneenonsend XXX7 XXX flag 1 Blank Set to 0 or 1 according to intended use 0 Set to 0 1 Set to 1 x Nothing is assigned 2 R Read O Possible to read X lmpossible to read Nothing is assigned W Write O Possible to write X Written value is invalid When write value can be 0 or 1 Nothing is assigned 3 Terms to use here are explained as follows e Nothing is assigned Nothing is assigned to the bit concerned When write set O for new function in future plan e Must not be set Not select The operation at having selected is not guaranteed e Reserved bit Reserved bit Set the specified value e Function varies with each operation mode Bit function changes according to the mode of peripheral functions e Always set to 0 in A mode Set the corresponding bit to O in A mode e Invalid in A mode The bit concerned has
448. turning When operating with XCIN after returning b7 b0 System clock control register 0 bo System clock control register 0 0 0 0 0 CMo Address 000616 0 0 CMO Address 000616 L_L Reserved bit L_L Reserved bit Must always be set to 0 Must always be set to 0 Main clock XIN XOUT stop bit On el clock select bit bcs ee IN XOUT ystem clock select bi XCIN XCOUT Port Xc select bit XCIN XCOUT generation As this register becomes setting mentioned above when operating with XIN count source of BCLK is XIN As this register becomes setting mentioned above when operating with XcIN the user does not need to set it again count source of BCLK is XcIN the user does not need to set it again When operating with XcIN set main clock XIN XOUT stop bit When operating with XIN set port Xc select bit to 1 before setting system to 0 before setting system clock select bit to 0 The both clock select bit to 1 The both bits cannot be set at the same time bits cannot be set at the same time Continued to the next page Figure 3 8 3 Set up procedure of controlling power using stop mode 1 Rev 2 00 Oct 16 2006 page 323 of 354 AS REJ09B0340 0200 RENES M30245 Group 3 Controlling Power Applications Continued from the previous page a Interrupt enable flag I flag 1 All clocks off stop mode b7 b0 System clock control register 1 Address 000716
449. ty select bit Port Xc select bit 1 Functions as XcIN XCOUT oscillator Main clock XIN XOUT stop bit 0 Oscillating Main clock divide ratio select bit 0 System clock select bit 0 XIN XOUT bo olo Timer A2 mode register Address 039816 TA2MR Operation mode select bit b1 b0 0 0 Timer mode Count source select bit b7 b6 1 1 fc32 f Xcin divided by 32 b15 b8 b7 bo A i 0316 FFi6 ana A2 register Address 038A16 038B16 b7 b0 7 XKKKKKE Clock prescaler reset flag Address 0381 16 CPSRF Rrescaler is reset b7 b0 D D gt 4 1 Count start flag Address 038016 TABSR TA2 start counting b7 bo KKK PEE Timer A2 interrupt control register Address 004716 TA2IC TA2 interrupt priority level INTO interrupt control register Address 005F 16 INTOIC INTO interrupt priority level Processor interrupt priority level IPL 0 Interrupt enable flag I 0 Setting interrupt except clearing wait mode Interrupt control register ADIC Address 004B16 S13BCNIC Address 004316 SUSPIC Address 005616 TAiIC i 0 1 3 4 Address 005416 004516 005716 005916 RSMIC Address 005816 EPOIC Address 004616 RSTIC Address 005A 16 b7 bo SOFIC Address 005B16 EEK PET VBDIC Address 005C16 USBFIC Address 005D16 Interrupt priority level select bit b2 b1 b0 0 0 0 Interrupt disabled b7 bo I
450. uaranteed For rated values refer to Electrical Characteristics of Datasheet Figure 5 1 3 VOH IOH standard characteristics of ports P63 to P67 Vec 3 3V Topr 20 C Topr 85 C VoL V Note 1 These characteristics are just examples and not guaranteed For rated values refer to Electrical Characteristics of Datasheet Figure 5 1 4 VoL loL standard characteristics of ports P63 P67 and P7 when high drive selected Rev 2 00 Oct 16 2006 page 353 of 354 AS REJ09B0340 0200 RENES M30245 Group 5 Standard Characteristics 5 1 2 Vcc Icc Characteristics Figure 5 1 5 and Figure 5 1 6 show Vcc lIcc characteristics Measuring condition Topr 25 C f XIN Square wave 16MHz Single chip mode Without wait No division mode Figure 5 1 5 Vcc Icc characteristics Mask version Measuring condition Topr 25 C XIN Square wave 16MHz Single chip mode Without wait No division mode Figure 5 1 6 Vcc Icc characteristics Flash version Rev 2 00 Oct 16 2006 page 354 of 354 AS REJ09B0340 0200 RENES REVISION HISTORY M30245 Group User s Manual Rev Date Summary A Jan 24 2003 First edition issued Oct 16 2006 2 2 1 c 3 types gt 2 types an external input signal deleted Figure 2 2 4 UDF bit 5 7 R O Figure 2 2 5 ONSF Note 3 added 2 2 10 deleted Figure 2 2 34 deleted 2 3 1 3 Error detection revi
451. ulk transfer both ISO bit and INTPT bit of USB endpoint x IN control and status register are set to 0 for bulk transfer setting Also for initialization of toggle sequence bit in bulk transfer set TOGGLE_INIT bit to 1 and initialize PID to DATAO In order to enable double buffer mode and continuous transmit mode use USB endpoint x IN FIFO configuration register for setting In order to use the AUTO_SET function set AUTO_SET bit of USB endpoint x IN control and status register to 1 Transmit Data Preparation The transmit data has to be beforehand prepared in IN FIFO in order to transmit data Prepare one packet data Note 1 to the IN FIFO in the following procedure 1 Confirm that there is a packet space in the IN FIFO Read the IN_BUF_STS1 and IN_BUF_STS0 flags and confirm that they are either 002 the IN FIFO empty or 012 writable of second data in double buffer 2 Write one packet data Note 1 to be transmitted to the IN FIFO Every time 1 byte data are written to the IN FIFO the internal write pointer is automatically incremented by one Contents of the internal write pointer cannot be read For transmitting an empty packet with 0 data length do not write data to the IN FIFO 3 Set SET_IN_BUF_RDY bit to 1 At this time the IN FIFO status is updated as follows the IN BUF_STS1 and IN_BUF_STS0 flags are updated and the transmit preparation is completed eIn Single Buffer Mode The IN_BUF_STS1
452. unction unit See 2 8 USB function for detail Setting USB related registers Enable USB endpoint 1 OUT b15 b8 b7 b0 b7 0 USB endpoint enable register USBEPEN Address 028E16 EP1 OUT enable bit 1 Enabled USB Endpoint 1 OUT control and status register EP10CS_ Address 02B616 AUTO_CLR bit 0 AUTO_CLR disabled olololo USB Endpoint 1 OUT MAXP register EP1OMP_ Address 02B816 _______________ Set to 12016 288 bytes Initialization serial sound interface See 2 6 Serial sound interface for detail Disable DMAO b7 DMADO control register 0 DMOCON Address 002C16 DMA enable bit 0 Disabled Setting DMAO cause select register ee gt DMAO cause select register 0 OZA Oj1 1 10 pMosL Address 03B816 DMA request cause select bits 01110 SSI transmit Nothing is assigned Write O when writing to these bits Software DMA request bit 0 Not occurred Set USB DMAO request register address 029016 to 000016 not selected Continued to the next page Figure 3 7 2 Setting routine 1 of DMA transfer from USB OUT FIFO to serial sound interface Rev 2 00 Oct 16 2006 page 318 of 354 7RENES
453. up 2 USB function 2 USB Suspend Function In the M30245 group the USB suspend status flag SUSPEND of USB power management register address 028216 is set to 1 when the suspend signal has been received from the host CPU or not detected any bus activity on the D D line for at least 3ms Simultaneously the USB suspend inter rupt request occurs To shift into the USB suspend state control the USB function control unit in the following procedure Further for changes in frequency synthesizer control register address 03DC16 or system clock con trol register1 address 000716 clearing the corresponding bit of protect register address 000A 16 is required USB Suspend Mode Control 1 Set USB clock enable bit of USB control register to 0 Do not write to USB internal registers other than the USBC USBAD and frequency synthesizer related registers when the USB clock has been disabled in the suspend state 2 During the bus power supply operation as a low power device control it to reduce the total driving current to 500uA or below or 2 5mA or below when remote wakeup has been enabled as a high power device by the host CPU For details of the power control in suspend refer to USB2 0 specification 3 Set frequency synthesizer enable bit of frequency synthesizer control register to 0 4 Set the return interrupt from the USB suspend state Set USB resume interrupt control register address 005816 When remote w
454. urs when the level of other key input interrupt pins is L 3 How to determine a key input interrupt A key input interrupt occurs when the selected edge is input to one of eight pins but each pin has the same vector address Therefore read the input level of Port P10 in the key input interrupt routine to determine the interrupted pin 4 Registers related to the key input interrupt Figure 2 14 1 shows the memory map of key input interrupt related registers and Figure 2 14 2 and 2 14 3 show key input interrupt related registers 004116 Key input interrupt control register KUPIC 03F616 Port P10 direction register PD10 03F916 Key input mode register KUPM O3FE16 Pull up control register 2 PUR2 Figure 2 14 1 Memory map of key input interrupt related registers Rev 2 00 Oct 16 2006 page 262 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Key Input Interrupt Key input interrupt control register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset KUPIC 004116 XXXXX0002 Bit symbol RW ILVLO Interrupt priority level SEIECEDN Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit Interrupt not requested O O Interrupt requested Note 2 Nothing is assigned Write O when writing to these bits The contents are indeterminate if read Note 1 To rewrite the interrupt control register do so at a point th
455. uted every time 1 byte of serial transmit is completed 2 Use the DMAO to transfer data from the internal RAM to the UART1 Select the UART1 transmit to the DMAO request factor Select the single transfer mode and set the DMAO transfer counter to 511 bytes 512 1 3 Set the CRC calculation circuit to the CRC CCITT and set CRC snoop address register to the address of UART1 transmit buffer register write snoop 4 On completing the DMA 2 byte data of CRC data register calculation result are transferred to the UART1 and operation is completed Operation 1 Initialize the UART1 related registers 2 Initialize the DMAO related registers in DMA disable state 3 Set the DMAO transfer counter to the transfer data consisting of 511 bytes in this case 8 bit transfer 4 Initialize the CRC calculation circuit and the SFR access snoop function 5 Set the software DMA request bit of DMAO to 1 At this time 1st byte data are transferred from RAM to the transmit buffer of the UART1 Simultaneously the transfer source address is incremented and the content of the transfer counter is down counted The transferred data are automatically written in CRC input register by the SFR access snoop function 6 When the transmit buffer of the UART1 becomes writable state the DMA transfer request is occurred by the UART1 At this time the next data are transferred from RAM to the transmit buffer of the UART1 Simultaneously the transfer sour
456. utput mode When this bit is set to 1 low pulse is always output for about 166ns 2 cycles of the 12MHz USB clock at start of the frame packet USB enable bit This bit is used to enable disable the USB block When this bit is set to 1 USB function is enabled After setting 1 to this bit wait for at least 250ns and then read or write the other USB related register The configuration of USB control register is shown in Figure 2 8 9 USB Control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset USBC 000C16 0016 Bit Symbol Bit Name Function Reserved Must always be set to 0 USBC5 USB clock enable bit Disable Enable USBC6 USB SOF port select bit Disable Note 1 Enable USBC7 USB enable bit Disable Note 2 Enable Note 1 P92 is used as GPI O pin Note 2 All USB internal registers are held at their default values Figure 2 8 9 USB control register Rev 2 00 Oct 16 2006 page 139 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function USB attach detach register This register is used to control attach detach from the USB host without physically attaching detaching the USB cable Port 90 Second bit The port P90 operates as standard port when this bit is set to 0 Connect a 1 5kQ resistance between the USB D pin and the Uvcc pin The timing of D line pull up is depending on the Uvcc pin W
457. v 2 00 Oct 16 2006 page 125 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Frequency synthesizer PLL 2 7 3 Precautions for Frequency synthesizer 1 Bits 6 and 5 of frequency synthesizer control register are set to bit6 bits 1 1 at reset When using the frequency synthesizer we recommended to set to bit6 bit5 1 0 2 Set fSYN to 12 MHz or lower 3 The value of fPIN should not be set below 1 MHz 4 When the frequency synthesizer is enabled do not use the output of the frequency synthesizer until after a 2 5ms delay That will stabilize the output Also after the frequency synthesizer has been enabled because the output is temporarily 2 5ms unstable the contents of none of the registers should be changed 5 When using the frequency synthesizer connect a low pass filter to the LPF terminal 6 The following setup for the frequency synthesizer should be done after hardware resest 1 Cancel the protect register 2 Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary for the fUSB 3 Enable the frequency synthesizer by setting frequency synthesizer control register 4 The protect register should be set to write disabled A 3ms wait is necessary 5 The frequency synthesizer locked status bit should be checked It is necessary to recheck after a wait of 0 1ms if it is 0 unlocked 6 Enable USB clock 7 After waiting four cycles of the f or greater the USB en
458. ved USB reserved USB reserved USB reserved USB reserved USB reserved USB reserved USB EPO IN FIFO EPOI USB EPO OUT FIFO EP0O USB EP1 IN FIFO EP11 USB EP1 OUT FIFO EP10 USB EP2 IN FIFO EP2l USB EP2 OUT FIFO EP20 USB EP3 IN FIFO EP3I USB EP3 OUT FIFO EP30 USB E4 IN FIFO EP41 USB EP4 OUT FIFO EP40 M30245 Group 2 USB function Table 2 8 2 List of USB Related Registers Items Section name Register name 2 8 2 USB function control USB control register USB Attach Detach register USB endpoint enable register USB endpoint x x 0 4 IN FIFO data register USB endpoint x x 0 4 OUT FIFO data register 2 8 3 USB Interrupt USB function interrupt status register USB function interrupt clear register USB function interrupt enable register USB frame number register 2 8 4 USB Operation Suspend Resume Function USB power management register 2 8 5 USB Operation Endpoint 0 USB address register USB endpoint 0 control and status register USB endpoint 0 MAXP register USB endpoint 0 OUT write count register 2 8 6 USB Operation Endpoint 1 4 reception USB endpoint x x 1 4 OUT control and status register USB endpoint x x 1 4 OUT MAXP register USB endpoint x x 1 4 OUT FIFO configuration register 2 8 7 USB Operation Endpoint 1 4 transmission 1 USB endpoint x x 1 4 OUT write count reg
459. via a resistor or after setting for output mode leave these pins open Note 2 Note 3 Note 4 P45 CS1 to P47 CS3 After setting for port input mode and setting CS1 to CS3 output enable bit to 0 connect to Vcc via a resistor pull up BHE Note 5 ALE Note 5 HLDA Note 5 Xout Note 1 BCLK Open HOLD RDY NMI Connect via resistor to Vcc pull up UVcc AVcc Connect to Vss AVss VREF Open USB D USB D Open LPF Open VbusDTCT Note 6 Open Note 1 When an external clock is input to the XIN pin Note 2 If setting these pins in output mode and opening them ports are in input mode until switched into output mode by use of software after reset Thus the voltage levels of the pins become unstable and there can be instances in which the power source current increases while the ports are in input mode In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes setting the contents of the direction registers periodically by use of software increases program reliability Note 3 Make wiring as short as possible not more than 2 cm from the microcomputer s pins in working on non used pins Note 4 Output L if port P70 and P71 are set to output mode Port P70 and P71 are N channel open drain output Note 5 When a Vss level is connected to the CNVSs pin these pins are input ports unt
460. watchdog timer value is always initialized to 7FFF16 regardless of the value written Generating watchdog timer interrupt a Cancel protect register Protect register Address 000A 16 PRCR Enables writing to processor mode register 0 and 1 addresses 000416 and 000516 1 Write enabled Reserved bit Va Software reset a Processor mode register 0 Address 000416 PMO Software reset bit The device is reset when this bit is set to 1 The value of this bit is O when read XN Figure 2 12 4 Set up procedure of watchdog timer interrupt watchdog timer interrupt Rev 2 00 Oct 16 2006 page 257 of 354 RENESAS REJ09B0340 0200 M30245 Group 2 Address Match Interrupt 2 13 Address Match Interrupt Usage 2 13 1 Overview of the address match interrupt usage The address match interrupt is used for correcting a ROM or for a simplified debugging purpose monitor When the external bus is used for 8 bits the address match interrupt is not used to the external areas The following is an overview of the address match interrupt usage 1 Enabling disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt It is affected neither by the processor interrupt priority level IPL nor the interrupt enable flag I flag 2 Timing of the address match interrupt An interrupt occurs immediately before executing
461. xecutes the following responses when the data are not received normally When the received OUT token is destroyed the data are not received When the received data are destroyed bit stuffing error or CRC error occur the data are received When the packet which is exceeding receivable data size is transmitted the data are not received When OUT FIFO of the M30245 group could not receive the full data the data are not received lsochronous IN lsochronous OUT Idle state Idle state IN 4 Host issues Idle state Device issues Idle state Figure 2 8 6 Isochronous transfer 5 Interrupt Transfer This transfer form is same as the bulk transfer Refer to 3 Bulk Transfer of this manual Rev 2 00 Oct 16 2006 page 134 of 354 7tENESAS REJ09B0340 0200 M30245 Group 2 USB function 6 Device State The device has states and transits between the states The M30245 group does not execute state transition on the hardware Control it by the software based on requests of the related USB interrupt request The device state transition is shown in Figure 2 8 7 A series of processes from bus connection to configuration is called emulation Each state is ex plained as follows Connection State This is the state which the device has been connected to the bus Powered State This is the state where the hub has been completed the configuration and has bee
462. xl x 0 4 Address 02E016 02E416 02E816 02EC16 02F016 Setting of the transmit data Note 1 The packet data is one buffer data in continuous transfer mode 3 Setting of the SET_IN_BUF_RDY bit to 1 and completion of one packet data Note 2 prepare b15 b8 b7 bO b7 b0 0 P a USB endpoint x IN control and status register EPxICS x 1 4 Address 029E16 02A416 02AA16 02B016 ann SET_IN_BUF_RDY bit 1 Transmission data set loaded to the IN buffer updates IN_BUF_STSO IN_BUF_STS1 flags Note 2 The packet data is one buffer data in continuous transfer mode Note 3 When the AUTO_SET bit is set to 1 this bit is automatically set to 1 when the data count set by maximum packet size register is written to the IN FIFO When the AUTO_SET bit is set to 0 or the AUTO_SET bit is set to 1 and it is a short packet data packet which is smaller than maximum packet size this bit is set to 1 by software Execution of the above 2 and 3 again when the second packet data is set on the double buffer mode a Completion of packet data prepare Figure 2 8 49 Endpoint 1 to 4 IN packet prepare routine Rev 2 00 Oct 16 2006 page 206 of 354 7RENESAS REJ09B0340 0200 M30245 Group 2 8 8 USB Operation Interface with DMAC Transfer The M302
463. y cleared to 002 automatically When they are 002 there are no data in IN FIFO When they are respectively set to 012 there are only one buffer data in double buffer Invalid for single buffer When they are respectively set to 112 there are no space in IN FIFO There are one buffer data in single buffer while there are two buffer data in double buffer When they are respectively set to 102 it is invalid These flags are updated when one of the following events occurs One buffer data of IN FIFO is successfully transmitted to the host PC One buffer data is successfully prepared in IN FIFO SET_IN_BUF_RDY bit is set to 1 when writing of one transmit data to the IN FIFO completes Or at the time of AUTO_SET enable when the data count equal to the EPxIMP or the BUF_SIZ in continuous transfer enable has been written in the FIFO However when a short packet has been written at the time of AUTO_SET enable these flags are not automatically updated In such cases set SET_IN_BUF_RDY bit to 1 by software One buffer data is flushed UNDER_RUN flag This flag indicates occurrence of an underrun in isochronous transfer The bit is valid only in isochro nous IN transfer When there are no data packet in IN FIFO at start of the IN token from the host CPU occurrence of an underrun is recognized and this flag is set to 1 This flag is cleared to O by setting 1 to CLR_UNDER_RUN bit
464. ymbol UDF Address 038416 When reset 0016 2 TimerA Bit Symbol Bit Name Function TAOUD Timer AO up down flag TA1UD Timer A1 up down flag TA2UD Timer A2 up down flag TA3UD Timer A3 up down flag TA4UD Timer A4 up down flag 0 Down count 1 Up count This specification becomes valid when the up down flag content is selected for up down switching cause TA2P Timer A2 two phase pulse signal processing select bit TA3P Timer A3 two phase pulse signal processing select bit TA4P Timer A4 two phase pulse signal processing select bit 0 Disabled 1 Enabled When not using the two phase pulse signal processing function set the select bit to 0 Note Use MOV instruction to write to this register Symbol TRGSR Address 038316 When reset 0016 Bit Symbol Bit Name Function TAITGL TA1TGH Timer A1 event trigger select bit Input on TAIN is selected Note Invalid TAO overflow is selected TA2 overflow is selected TA2TGL TA2TGH Timer A2 event trigger select bit Input on TA2IN is selected Note Invalid TA1 overflow is selected TA3 overflow is selected TA3TGL TA3TGH Timer A3 event trigger select bit Input on TASIN is selected Note Invalid TA2 overflow is selected TA4 overflow is selected TA4TGL
465. z 16 00 MHz 1 MHz 12 00 MHz 2 MHz 16 00 MHz 2 MHz 12 00 MHz 3 MHz 12 00 MHz 6 MHz 12 00 MHz REJ09B0340 0200 M30245 Group 2 Frequency synthesizer PLL Frequency Multiplier fvco is generated via the Frequency Synthesizer Mul tiply register FSM address 03DD16 When the Frequency Multiply register is set to 255 multiplication is disabled and fvco fPIN The value of n should be set so that fvco becomes 48MHz Table 2 7 2 shows some examples of how the frequency synthesizer multiply register is set fvco fPIN X 2 n 1 n FSM value Table 2 7 2 Example of Setting the Frequency Multiply Register FSM f FSM Value ie on Dec Hex 1 MHz 23 1716 48 MHz 2 MHz 11 0B16 48 MHz 4 MHz 5 0516 48 MHz 6 MHz 3 0316 48 MHz 8 MHz 2 0216 48 MHz 12 MHz 1 0116 48 MHz Frequency Divider Clock fSYN is a divided down version of fvco fSYN is generated via the frequency synthesizer divide register FSD When the frequency synthesizer divider register is set to 255 division is disabled and fSYN fvco Table 2 7 3 shows some examples of how the frequency synthesizer division register is set fSYN fvco 2 m 1 m FSD value Note 1 Set fSYN to 12MHz or lower Table 2 7 3 Example of Setting the frequency synthesizer divide register FSD f FSD Value fevn tile Dec Hex 12 00 MHz 8 00 MHz 48 MHz 16 00 MHz Note 1 6 00 MHz 127 7Fi6 187 50 kHz Note 1 fsyN fvco m 1 when FSCCR4 1 and m 2 Re

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