User's Manual - TQ
Contents
1. Name Alias Type Power Supply Output Driver Input Type PU PD Ethernet VO VDD IO 3 3 V 4 4 LVTTL ETH 1 5 TXD 0 VO VDD IO 3 3 V 4 4 LVTTL 2 5 TXP TX TXD 1 VDD IO 3 3 V 4 4 LVTTL 3 USB PRTPWR TXD 2 O VDD IO 3 3 V 4 4 LVTTL 4 58 SPEED TXD 3 IO 3 3 V 4 4 LVTTL ETH 5 USB SUPEND TX ER O VDD IO 3 3 V 4 4 LVTTL ETH 6 058 OE RTS MDC VO VDD IO 3 3 V 4 4 LVTTL 7 TXN VDD IO 3 3 V 4 4 LVTTL _8 DV VO 10 3 3 4 4 LVTTL ETH 9 CD RX VDD IO 3 3 V 4 4 8 8V Schmitt Trigger ETH 10 CTS COL I O VO VDD IO 3 3 V 4 4 LVTTL ETH 11 TX CLK l O O VDD IO 3 3 V 4 4 33 VSchmitt Trigger ETH 12 VDD IO 3 3 V 4 4 LVTTL ETH 13 USB RXD CTS RXD 1 O VDD IO 3 3 V 4 4 LVTTL E ETH 14 058 RXP UART RX RXD 2 VDD IO 3 3 V 4 4 LVTTL 15 USB RXN RX RXD 3 VDD IO 3 3 V 4 4 LVTTL 16 USB OVRCNT CTS _ VDD IO 3 3 V 4 4 LVTTL 17 CD CRS IO 3 3 V 4 4 LVTTL IrDA PSC6 0 IRDA RX TxD VO VDD IO 3 3 V 4 4 LVTTL PSC6_1 VO VDD IO 3 3 V 4 4 LVTTL PSC6 2 52. 45 SOFTWARE 45 7 SAFETY REQUIREMENTS AND PROTECTIVE 46 7 1 Requirements 46 7 2 ESD 46 7 3 Reliability arid Service 46 7 4 Climate Conditions and Operational Conditions 47 75 Environmental 47 APPENDIX 48 8 1 Acronyms and 48 8 2 50 3 la components User s Manual TQM5200 UM 300 Illustration directory Illustration 1 Illustration 2 Illustration 3 Illustration 4 Illustration 5 Illustration 6 Illustration 7 Illustration 8 Illustration 9 Illustration 10 Illustration 11 Illustration 12 TOMSZ0 Block Dia ara mm 10 Processor Block Diagram 12 MPC5200 Clock 2 0000000000000000000000000 17 Chip Select 0 Boot
3. Pin Function Description 1 3V3 PWR Module supply 3 3 V 5 2 GND PWR Module supply 3 ETH_17 4 4 mA CD CRS 4 ETH_16 4 4 mA USB_OVRCNT CTS RX_ER 5 ETH_15 4 4 mA USB RXN RX RXD 3 6 ETH_14 4 4 mA USB_RXP UART_RX RXD 2 7 13 4 4 USB RXD CTS RXD 1 8 ETH 12 4 4 mA RXDJ 0 9 ETH 11 4 4 mA TX 3 3 V Schmitt Trigger 10 GND PWR Module supply 11 ETH 9 4 4 mA CD RX CLK 3 3 V Schmitt Trigger 12 ETH 10 4 4 mA CTS COL 13 3V3 PWR Module supply 3 3 V 5 14 ETH_8 4 4 mA RX DV 15 ETH 7 4 4 mA 16 _6 4 4 mA USB OE RTS Reset configuration bit 17 ETH 5 4 4 mA USB SUPEND TX ER Reset configuration bit 18 GND PWR Module supply 19 ETH 3 4 4 mA USB PRTPWR TXD 2 Reset configuration bit 20 ETH 4 4 4 mA USB TXD 3 Reset configuration bit 21 ETH 1 4 4 mA RTS TXD 0 Reset configuration bit 22 ETH 2 4 4 mA USB TXP TX TXD 1 Reset configuration bit 23 IRQ3 3V3 4 4 mA 100k PD 24 ETH 0 3V3 4 4 mA 100k PU TX TX EN Reset configuration bit 25 3V3 PWR Module supply 3 3 V 5 26 GND PWR Module supply 27 IRQ1 3V3 4 4 mA 100k PU 28 IRQ2 3V3 4 4 mA 100k PD 29 PCI STOPZ
4. Pin Function Description 65 EXT AD 21 3V3 10 10 mA 66 GND PWR Module supply 67 EXT AD 19 3V3 10 10 mA 68 EXT AD 18 3V3 10 10 mA 69 EXT AD 17 3V3 10 10 mA 70 EXT AD 16 3V3 10 10 mA 71 EXT AD 15 3V3 10 10 mA 72 EXT AD 14 3V3 10 10 mA 73 3 3V PWR Module supply 3 3 V 5 96 74 GND PWR Module supply 75 EXT AD 13 3V3 10 10 mA 76 EXT AD 12 3V3 10 10 mA 77 EXT AD 11 3V3 10 10 mA 78 EXT AD 10 3V3 10 10 mA 79 EXT AD 9 3V3 10 10 mA 80 EXT AD 8 3V3 10 10 mA 81 EXT AD 7 3V3 10 10 mA 82 GND PWR Module supply 83 EXT AD 5 3V3 10 10 mA 84 EXT AD 6 3V3 10 10 mA 85 3 3V PWR Module supply 3 3 V 5 96 86 EXT AD 4 3V3 10 10 mA 87 EXT AD 3 3V3 10 10 mA 88 EXT AD 2 3V3 10 10 mA 89 EXT AD 1 3V3 10 10 mA 90 GND PWR Module supply 91 LP RW 0 3V3 4 4 mA Reset configuration bit 92 EXT AD 0 3V3 10 10 mA 93 LP 0 3V3 6 6 mA Reset configuration bit 94 LP_TS 0 3V3 8 8 mA Reset configuration bit 95 LP_ACK 3V3 4k7 PU 96 LP_OE 0 3V3 6 6 mA 97 3 3 PWR Module supply 3 3 V 5 98 GND PWR Module supply 99 ATA_ISOLATION 3V3 8 8 mA 100 ATA IOR Z 3V3 8 8 mA Reset configuration bit 101 3V3 8 8 mA Reset configuration bit 102 ATA INTRQ 3V3 8 8 mA 10k PD 103 ATA IOCHRDY 3V3 8 8 mA 10k PU 104 ATA 3V3 8 8 mA Reset
5. 1 2 120 2 40 1 9 H 541 57 9 78 1 80 Illustration 9 view through the printed circuit board Page 43 5 4 View 5200 Illustration 10 Top View 5 5 Bottom View TQM5200 User s Manual TQM5200 UM 300 Illustration 11 Bottom View 44 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH fm Manual TQM5200 UM 300 components 5 6 Side View TQM5200 Illustration 12 Stack heights not to scale 5 0 0 2 Combination of module connector and standard mating connector 6 7 or 8 mm are possible with different connectors on the target hardware 1 8 0 16 Printed circuit board Coils maximum height on top Table 33 Stack Heights To avoid damages caused by mechanical stress it is recommended to extract the TQM5200 from the target hardware only by using the special extraction tool MOZI52xx te 2 5 mm should be kept free on the target hardware along the longitudinal edges on both sides of the module for the extraction tool MOZI52xx B Two holes are provided for mounting the module on the target hardware and or for mounting a CPU heat sink 6 Software On the module an adapted version of U Boot is preinstalled as boot loader It is the basic software delivered with the TQM5200 For more information see separate
6. in Quality User s Manual TQM5200 TQM5200 UM 300 12 10 2010 User s Manual 5200 UM 300 la components Table of contents 1 ABOUT THIS MANUAL 7 11 Safety MD Me EM I M De 7 12 Terms and Conventions 7 1 8 Handling and ESD c M 8 1 4 Registered Trademarks 9 UENIRE 9 RR mmm 9 cec 9 2 PRODUCT IDEA 10 3 FUNCTIONALITY AND SYSTEM 1 10 3 1 System Architecture Block 2 2 1 2 1 2 1 nnn 10 3 2 System Components 11 4 ELECTRONICS SPECIFICATION ee 12 4 1 System T 12 12 4 1 2 CPU Power On Reset 14 4 1 3 mm TM 16 Sg 18 4 1 5 Temperature inerte tutae SERE PR Hn
7. 80 Pin Grafik Board to Board Connector 0 8 mm Pitch 240 Pin Basis Board to Board Connector 0 8 mm Pitch Illustration 1 TQM5200 Block Diagram Page 10 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 3 2 System Components The board contains the following system components e Freescale PowerPC processor MPC5200B up to 400 MHz with MPC603e processor core e 33 MHz oscillator for the CPU clock e Silicon Motion graphics controller SM501 with 8 Mbyte internal graphics memory 24 MHz oscillator for the graphics controller SDRAM 16 Mbyte up to 128 Mbyte 256 Mbyte 2 32 bit data bus width e Flash 4 Mbyte up to 32 Mbyte Flash 32 bit data bus width e SRAM no SRAM 512 Kbyte or 1 Mbyte 16 bit data bus width Possibility for battery back up via battery supply from the target hardware Serial EEPROM 0 kbit or 64 kbit IPC bus e CPLD for Reset Configuration and control of SRAM and graphics controller e Driver for two serial interfaces RxD TxD e 32 bit bus driver and 24 bit address register for module components at the Local Plus Bus e COP JTAG interface e Single power supply 3 3 V e Switch mode DC DC converter on board 3 3 V to 1 5 V e Linear DC DC converter on board 3 3 V to 1 8 V 1 5 supervisor power fail logic 1 8 supervisor power fail logic e 3 3 V supervisor power fail logic with SRAM battery backup e 240 pin
8. PSC1 PSC2 C Two Two Illustration 2 Processor Block Diagram 12 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components The module offers the following features CPU Core MPC603e series G2 LE core Superscalar architecture 760 MIPS at 400 MHz 40 C to 85 C 450 MIPS at 264 MHz 40 C to 105 C 16 k Instruction cache 16 k Data cache Double precision FPU Instruction and Data MMU Standard amp Critical interrupt capability SDRAM Memory Interface Up to 133 MHz operation 256 Mbyte addressing range 32 bit data bus e Built in initialization and refresh External Bus Interface Supports interfacing to ROM Flash SRAM memories or other memory mapped devices 8 programmable Chip Selects Non multiplexed data access using 8 16 32 bit data bus with up to 26 bit address Short or Long Burst capable Multiplexed data access using 8 16 32 bit data bus with up to 25 bit address Peripheral Component Interconnect PCI Controller Version 2 2 PCI compatibility PCI initiator and target operation 32bit PCI address data bus 33 and 66 MHz operation PCI arbitration function ATA Controller e Version 4 ATA compatible external interface e ATA Software Reset via PSC1 4 If this feature is used do not use PSC1 4 for other functions Six Programmable Serial Controllers PSCs
9. 18 Address Q 19 19 Chip Select 0 Boot Configuration Register 21 Flash Memory component EU 21 Chip Select 2 Configuration Register esee 22 SRAM Memory 0 00 22 Serial SPEM 23 Parameter for SDRAM Controller Configuration 24 SDRAM components selection of all released components 24 Graphics 26 Chip Select 1 Configuration 22222 26 Oscillators for the Graphics Controller 27 RS232 UART Signals CC 27 27 Board to Board Connectors 28 Plug Connector n 30 Pin configuration plug connector X1 base module connector 1 31 Plug eco 33 Pin configuration plug connector base module connector 2 34 Pin Assignment Connector X2 Graphics Connector 1 35 Pin Assignment Connector X4 Graphics Connector 2 35 Signal Characteristics E 39 Available Chip Selects and 40 COP JTAG Int
10. 18 4 1 6 Address 19 per TT 19 Flash detto ended e NDA NU 19 SRAM 22 uer t 23 41 11 E 23 1111 Parameter for SDRAM Controller Configuration 24 4 1 11 2 SDRAM component 24 4 1 12 Graphics 25 4 1 13 Clock generation for Graphics 27 27 4 1 15 Serial Interfaces 27 4 1 16 Module Interfaces EP 28 4 1 16 1 Board to Board oda crant ere ades ttis ads sent E rad dd Edd 28 4 1 16 2 Plug Connector Sms 29 4 1 16 3 Pin Config raton X 31 41154 Plug Connector X3 32 41 16 55 Configuration X3 34 4 1 16 6 Configuration X2 35 4 1 16 7 Pin Configuration X4 eec 35 4 1 16 8 Electrical Characteristics of the Module Inter
11. osv Poer Yi 100 99 vie ATAISOLAHON ATA Control ATA Control Powr _____ ___ _ 06 0 LP 54 Yib 10 100 33 Power LP_CS2 LP_CS3 14 LP CSOR __ w14 ____ 116 115 Heservef9 Reserve LM75 Alarm Non CPU Start L H Boot Ctrl Power 06020 120 1119 33V ______ Power Table 24 Pin configuration plug connector X1 base module connector 1 Page 31 la components User s Manual TQM5200 UM 300 4 1 16 4 Plug Connector X3 Pin Function Description 1 3 3 PWR Module supply 3 3 V 5 96 2 GND PWR Module supply 3 HRESET 3V3 6 mA 10k PU 5200 HW Reset Open drain output 3 3 V Schmitt Trigger 4 RESIN 3V3 5k6 PU TQM5200 RESET IN 5 PO_RESET 3V3 6 6 mA TQM5200 RESET OUT 6 SRESET 3V3 6 mA 10k PU 5200 SW Reset open drain output 3 3 V Schmitt Trigger 7 CPU_JTAG_TMS 3V3 10k PU Processor debug port 8 CPU 3V3 8 8 mA Processor debug port 9 CPU JTAG TDI 3V3 10k PU Processor debug port 10 GND PWR Module supply 11 CPU JTAG TRST 1 3V3 Processor debug port 12 TEST SEL 1 3V3 8 8 mA 10k PD ENID Input in Test Mode for processor production test 13 3 3V PWR Module supply 3 3 V 5 96 14 CPU JTAG TCK 3V3 10k PU Processo
12. Table 27 Pin Assignment Connector X2 Graphics Connector 1 4 1 16 7 Pin Configuration X4 Pp 2 1 33v Poer Poer ewo 6 5 rp w LCD Interface LCD Interface FP aw 9 2195 Power 9Nb 33V LCD Interface Power 0 2 21 LCD Interface FP6 26 25 33 Power Power 0 30 9 8 LCD Interface LCD Interface Bower ___ 3v Table 28 Pin Assignment Connector X4 Graphics Connector 2 Page 35 User s Manual 5200 UM 300 x la components 4 1 16 8 Electrical Characteristics of the Module Interfaces In the following table the signal characteristics of the module pins are described Name Alias Type Supply Output Driver Input PU PD IOL mA PCI LP AD Bus EXT AD 31 0 O VDD IO 3 3 V 12 12 PCI LVTTL 0 IO 3 3 V 16 16 PCI 1 O IO 3 3 V 16 16 PCI 2 IO 3 3 V 16 16 PCI 3 IO 3 3 V 16 16 PCI PCI CLOCK IO 3 3 V 12 12 PCI PCI_DEVSEL V
13. 3V3 16 16 mA 5k6 30 IRQO 3V3 4 4 mA 100k PU 31 PCI 3V3 16 16 mA 5k6 32 PCI 3V3 16 16 mA 5k6 PU 33 PCI 3V3 16 16 mA 5k6 34 GND PWR Module supply 35 PCI 3V3 16 16 mA 5k6 36 PCI SERRZ 3V3 16 16 mA 5k6 37 3V3 PWR Module supply 3 3 V 5 38 PCI 3V3 8 8 mA 5k6 39 PCI 3V3 8 8 mA 40 PCI PAR 3V3 16 16 mA 41 PCI DEVSEL 3V3 16 16 mA 5k6 PU 42 GND PWR Module supply 43 PCI CBE 3 3V3 16 16 mA 44 PCI ID SEL 3V3 8 8 mA 45 PCI CBE 2 3V3 16 16 mA 46 PCI 3V3 16 16 mA 5k6 PU 47 PCI CBE 1 3V3 16 16 mA 48 PCI CLOCK O 3V3 12 12 mA 49 3V3 PWR Module supply 3 3 V 5 50 GND PWR Module supply 51 PCI CBE 3V3 16 16 mA 52 EXT AD 30 3V3 10 10 mA 53 EXT AD 31 3V3 10 10 mA 54 EXT AD 28 3V3 10 10 mA 55 EXT AD 29 3V3 10 10 mA 56 EXT AD 26 3V3 10 10 mA 57 EXT AD 27 3V3 10 10 mA 58 GND PWR Module supply 59 EXT AD 25 3V3 10 10 mA 60 EXT AD 24 3V3 10 10 mA 61 3 3 PWR Module supply 3 3 V 5 96 62 EXT AD 22 3V3 10 10 mA 63 EXT AD 23 3V3 10 10 mA 64 EXT AD 20 3V3 10 10 mA 29 la components User s Manual TQM5200 UM 300
14. Er EDT TIMER 7 PSC3 9 T PSC2 4 dinis PSC2 2 PSC2 PSC2 0 PSC1 47 PSC1 2 GND M PSC6 2 5 6 0 85232 85232 TxD 1 Power cno 05 co5 806 PSC3 2 07 A08 Aao ___ Coo 60 76 68 ioi 103 Reserve os Resevei2 mo 107 Reseve13 po _ Power E pm ____ m unm JTAG TCK JTAG TMS Power 1120 119 3 9 Power Table 26 Pin configuration plug connector X3 base module connector 2 Page 34 User s Manual TQM5200 UM 300 x sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 4 1 16 6 Pin Configuration X2 Power GND 2 1 3 3 CLK OF SM501_CLKOF 4 3 44 5 501 USE Power 60 J __ 5 15 5 501 USB 25 0 7 M9 ___ GPIO24 GPIO 27 8 1 590 9 M2 J GPIO20 X GPIO GPIO Power f Interac LCD Interface FPEN 7 26 25 33V Power Power GND 15350 29 5 32 31 CRT Interface CRT Interface Power 39
15. 0010 3 3 4 4 LVTTL PSC6 3 USB RTS VDD IO 3 3 V 4 4 LVTTL USB USB 0 USB VDD IO 3 3 V 4 4 LVTTL USB 1 USB VO VDD IO 3 3 V 4 4 LVTTL 0582 058 IO 3 3 V 4 4 LVTTL USB 058 RXD O VDD IO 3 3 V 4 4 LVTTL USB 4 USB RXP O VDD IO 3 3 V 4 4 LVTTL E USB 5 USB RXN VDD IO 3 3 V 4 4 LVTTL USB 6 58 PRTPWR O IO 3 3 V 4 4 LVTTL E USB 7 USB SPEED VO VDD IO 3 3 V 4 4 LVTTL USB_8 5 SUPEND VDD IO 3 3 V 4 4 LVTTL 05 9 USB OVRCNT VO VDD IO 3 3 V 4 4 LVTTL 2 0 SCL VO VDD IO 3 3 V 4 4 3 3 V Schmitt Trigger I2C 1 SDA VDD IO 3 3 V 4 4 3 3 V Schmitt Trigger 120 2 SCL VO VDD IO 3 3 V 3 3 3 3 V Schmitt Trigger I2C 3 SDA VO VDD IO 3 3 V 3 3 3 3 V Schmitt Trigger 37 la components User s Manual TQM5200 UM 300 Alias Power Supply Output Driver Input PU PD IOL mA PSC PSC1 0 TxD Sdata_out MOSI TX VO VDD IO 3 3 V 3 3 LVTTL PSC1 1 RxD Sdata_in MISO TX VO VDD_IO 3 3 V 3 3 LVTTL 5 1 2 Sync IO 3 3 V 4 4 LVTTL 5 1 3 SCK CTS IO 3 3 4 4 LVTTL PSC1
16. 10 3 3 4 4 LVCMOS Pull Down USB 1 0 3 3 V USB 3 3 V Serial Interfaces RS232 TxD 1 Output IO 3 3 V 60 60 LVTTL RS232 RxD 1 Input IO 3 3 V LVTTL RS232 TxD 2 Output 3 3 V 60 60 LVTTL RS232 RxD 2 Input IO 3 3 V LVTTL Table 29 Signal Characteristics GPIO13 has a 5 6 Pull up 5 GPIOs may not be driven during the Reset Phase as these GPIOs are analyzed for the Reset Configuration a M Page 39 User s Manual TQM5200 UM 300 x la components 4 1 17 Chip Selects und Interrupts This table shows the chip selects and interrupts which are available at the plug connectors Pin Signal Name Description Status X1 116 LP 50 Chip Select 0 Used X1 113 LP 518 Chip Select 1 Used X1 112 LP 52 Chip Select 2 Used X1 111 LP CS3 Z Chip Select 3 Available X1 110 LP CS4 Z Chip Select 4 Available X1 108 LP 55 Chip Select 5 Available X1 30 IRQO Interrupt 0 Available X1 27 IRQ1 Interrupt 1 Used X1 28 IRQ2 Interrupt 2 Available X1 23 IRQ3 Interrupt 3 Available Table 30 Available Chip Selects and Interrupts 4 1 18 Service Interfaces 4 1 18 1 Download Interface The serial interface at PSC1 is the default download interface only RxD and TxD For this purpose the serial interface at PSC1 is defined in the software Universal Boot
17. 4 1 11 SDRAM e Up to four memory devices with a bus width of 16 bit each Chip Select through Mem 50 and Mem CS1 132 MHz clock One or two memory banks each 32 bit wide e Available for normal temperature range 16 Mbyte to 256 Mbyte e Available for extended temperature range 16 Mbyte to 128 Mbyte e CAS Latency 3 When the mode control and configuration register of the Micron 48LC16M16A2 75 SDRAM are programmed the following parameters must be taken into consideration Page 23 User s Manual 5200 UM 300 x la components 4 1 11 1 Parameter for SDRAM Controller Configuration Description Setting Unit yo 64 ms iow o oS Register Type Generate a Mode Register Set command Yes ExendRowandCoum o Precharge DiveRueforMDQandMDQS Drveexeptiomad J 4 22 2 Soft Precharge Table 15 Parameter for SDRAM Controller Configuration The following register settings result from the above described parameters e Mode Register MBAR 0x0100 gt 0x008D0000 e Control Register MBAR 0x0104 gt 0xD14F0000 e Configuration Register 1 MBAR 0x0108 gt 0xD2322800 e Configuration Register 2 MBAR 0x010C gt 0x8AD70000 The description of the individual register bits can be found in section
18. 5 no __ ____ ErH32 8 7 mn Ethernet Powr _____ ____ 9 o Ethernet ems 14 33V Powr Powr geret Ethernet ____ 6 osv wer _____ _____ 30 29 vos Pc Sto 33 PCLPERR PCI Control Reay 3 ssy Pow Pow 4t wor PCLDEVSE PCI Control PCI Powr GND 4 33V ______ PCI ATAILP AD Bus Power _____ 58 57 EXTAD27 POVATALP AD Bus EXT AD 24 60 59 ExXTAD25 PCVATAILP AD Bus 22 vog 61 33V Poer Powr _____ ____ 66 6 Yo EXrAD21 Ext AD 18 68 67 Yo4 19 PCI ATA LP AD Bus PCVATAILP AD Bus EXT AD 16 Wo4 70 69 vos 17 33V Power ExrAp8 Wi 79 PCI ATA LP AD Bus Power _____ 8 7 PCVATAILP IAD Bus EXT AD 4 ____ 86 85 33V Powe _____ ___ 90 89 wis ALPADBus LP Control LP_OE 96 95 _ 9
19. www tq components com 1 6 Copyright Copyright protected 2010 by TQ Components GmbH This manual may not be copied reproduced translated changed or distributed completely or partially in electronic machine readable or in any other form without the written consent of TQ Components GmbH 1 7 Disclaimer TQ Components GmbH does not guarantee that the information in this manual is up to date correct complete or of good quality Nor does TQ Components assume guarantee for further usage of the information Liability claims against TQ Components GmbH referring to material or idea related damages caused due to usage or non usage of the information given in the manual or caused due to usage of erroneous or incomplete information are exempted as long as there is no proven intentional or negligent fault of TQ Components GmbH TQ Components GmbH explicitly reserves the rights to change or add to the contents of this manual or parts of it without special notification Page 9 User s Manual TQM5200 UM 300 la components 2 Product Idea While designing the TQM5200 particular importance has been given to the compact dimensions With just 80 x 60 the 5200 has a very compact form factor Apart from requiring less space on the target hardware it also has advantages with mechanical stress e g shock or vibration Robustness and industrial suitability were also important criteria according to which the connector sys
20. Byte 2 for 32 bit access 90 GND PWR Module supply 91 Reserve 1 Reserve Not connected 92 SEL 3V3 4 4 mA Byte select Byte 3 for 32 bit access 93 Reserve 3 Reserve Not connected 94 Reserve 2 Reserve Not connected 95 Reserve 5 Reserve Not connected 96 Reserve 4 Reserve Not connected 97 3 3V PWR Module supply 3 3 V 5 96 98 GND PWR Module supply 99 Reserve 7 Reserve Not connected 100 Reserve 6 Reserve Not connected 101 Reserve 9 Reserve Not connected 102 Reserve 8 Reserve Not connected 103 Reserve 11 Reserve Not connected 104 Reserve 10 Reserve Not connected 105 Reserve 12 Reserve Not connected 106 GND PWR Module supply 107 Reserve 13 Reserve Not connected 108 Reserve 14 Reserve Not connected 109 3 3V PWR Module supply 3 3 V 5 96 110 Reserve 16 Reserve Not connected 111 Reserve 15 Reserve Not connected 112 Reserve 18 Reserve Not connected 113 Reserve 17 Reserve Not connected 114 GND PWR Module supply 115 JTAG TDI 3V3 10k PU PLD JTAG 116 JTAG TDO O 3V3 8 8 mA PLD JTAG 117 JTAG TMS 3V3 10k PU PLD JTAG 118 JTAG TCK 3V3 10k PU PLD JTAG 119 3 3V PWR Module supply 3 3 V 5 96 120 GND PWR Module supply T This value refers to Data Sheet MPC5200BDS Rev 01 state 01 2006 Under certain circumstances changes in the Data Sheet can lead to the fact that the data in this table is no longer correct 2 Further descriptions about the pins can
21. 4 55 VO IO 3 3 V 4 4 LVTTL PSC2 0 Sdata out MOSI TX VO VDD IO 3 3 V 4 4 LVTTL PSC2 1 5 MISO TX O VDD IO 3 3 V 4 4 LVTTL PSC2 2 Sync IO 3 3 V 4 4 LVTTL 5 2 3 CTS _ VDD_IO 3 3 V 4 4 LVTTL PSC2 4 55 VO IO 3 3 V 4 4 LVTTL PSC3 0 USB OE TxD TX VO VDD IO 3 3 V 3 3 LVTTL PSC3 1 USB TXN RxD RX VDD IO 3 3 V 3 3 LVTTL PSC3 2 58 RTS IO 3 3 4 4 LVTTL 2 PSC3 3 USB RXD CTS O VDD IO 3 3 V 4 4 LVTTL PSC3 4 USB RXP CD O VDD IO 3 3 V 4 4 LVTTL PSC3 5 USB RXN VDD IO 3 3 V 4 4 LVTTL PSC3 6 USB PRTPWR MOSI VDD IO 3 3 V 4 4 LVTTL PSC3 7 USB MISO O VDD IO 3 3 V 4 4 LVTTL PSC3 8 USB SUPEND SS O IO 3 3 V 4 4 LVTTL PSC3 9 USB_OVRCNT SCK VO VDD IO 3 3 V 4 4 LVTTL GPIO TIMER GPIO WKUP 7 O IO 3 3 V 8 8 LVTTL TIMER 0 VO IO 3 3 V 4 4 LVTTL TIMER 1 IO 3 3 V 4 4 LVTTL TIMER 2 MOSI VDD IO 3 3 V 4 4 LVTTL m TIMER_3 MISO O 0 10 3 3 V 4 4 LVTTL E TIMER 4 55 VO IO 3 3 V 4 4 LVTTL TIMER_5 SCK VO VDD IO 3 3 V 4 4 LVTTL TIMER 6 VO VDD IO 3 3 V 4 4 LVTTL TIMER 7 VO IO 3 3 V 4 4 LVTTL Misc PORRESET Input VDD IO 3 3 V 3 3 Schmit
22. 8 SDRAM Memory Controller of the MP5200 User Manual 2 The SDRAM components are listed in the following table 4 1 11 2 SDRAM components MT48LC32M16A2TG 75 45511632 75 SDRAM 32 x16 C to 70 C MT48LC 16M16A2TG 75 45561632 1175 SDRAM 16 M x16 40 C to 85 C MT48LC8M16A2TG 75 K45281632E TI75 SDRAM 8 x16 40 C to 85 C MT48LC4M16A2TG 75 K45641632E TI75 SDRAM 4 M x16 40 to 85 Table 16 SDRAM components selection of all released components Page 24 sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 0 components 4 1 12 Graphics Controller The Silicon Motion graphics controller SM501 is used Illustration 6 5 501 Block Circuit Diagram The SM501 offers the following features Host Interface e Direct 32 bit CPU and PCI interface Xscale PXA 25x SH3 4 and MIPS direct CPU bus interface e PCI v2 1 compliant Display Support e LCD digital and CRT analog with Dual Display e LCD 320x240 up to 1024x768 16 32 bit 1280x1024 16 bit only e CRT VGA to SXGA 16 32 bit Widescreen support up to 1280 768 16 e Hardware rotation e Portrait and landscape display e Can display different orientation on each output 2D Video Acceleration Engine e Optimized 128 bit 2D drawing engine e Intelligent DMA command interpreter for enhanced performance e Both front end and back end video engin
23. 80 pin 320 pin Board to Board plug system All pins of the PowerPC processors are routed to the two 120 pin Board to Board connectors except the SDRAM interface and the XTAL pins Further all pins of the graphics controller related to the LCD and CRT interface are routed to two 40 pin module connectors Transceivers for Ethernet USB CAN etc except RS232 transceivers are not assembled on the module If necessary drivers can be implemented on the target hardware 1 With one memory bank for the MPC5200 Rev 1 2 Chip masks Revision A With two memory banks starting with MPC5200 Chip masks Revision B from Q3 2005 3 64 and128 Mbyte addressed by the bank select bits 11 User s Manual 5200 UM 300 la components 4 Electronics Specification The module is supplied with 3 3 V DC The processor core voltage 1 5 V and the core voltage for the graphics controller 1 8 V are generated from the input voltage 3 3 V on the module with voltage regulators The TQM5200 is specified for a temperature range of 0 C to 70 C Optionally it is also available for a temperature range of 40 C to 85 C 41 System components 4 1 1 CPU Systems Integration 16K 32 Entry ICache MMU 16K 32 Entry DCache MMU Memory USB Controller Two Embedded PowerPC 603e Core With double precision FPU XL Bus ECCE Intelligent DMA Controller Unit JTAG J1850 CAN 2 0 0400 12
24. RXN 46 PSC3 6 3V3 4 4 mA USB PRTPWR MCLK MOSI 47 PSC3 3 3V3 4 4 mA USB RXD Frame CTS 48 PSC3 4 3V3 4 4 mA USB CD 49 3 3V PWR Module supply 3 3 V 5 96 50 GND PWR Module supply 51 PSC3 1 3V3 3 3 mA USB TXN RxD RX RS232 Driver2 52 PSC3 2 3V3 4 4 mA USB RTS 3 3 V Schmitt Trigger 53 PSC3 0 3V3 3 3 mA USB OE TxD TX RS232 Driver2 54 PSC2 4 3V3 4 4 mA Frame 55 CD 55 PSC2 3 3V3 4 4 mA BitClk CTS 3 3 V Schmitt Trigger 56 PSC2 2 3V3 4 4 mA Sync RTS 57 PSC2 1 3V3 4 4 mA RxD Sdata in RX 58 GND PWR Module supply 59 PSC1 3 3V3 4 4 mA BitClk CTS 3 3 V Schmitt Trigger 60 PSC2 0 3V3 4 4 mA TxD Sdata out TX 61 3 3V PWR Module supply 3 3 V 5 96 62 PSC1 4 3V3 4 4 mA Frame SS CD ATA Reset 63 PSC1 1 3V3 3 3 mA RxD Sdata in RX RS232 Driver1 i Page 32 sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components Pin Function Description 64 PSC1 2 3V3 4 4 mA Sync RTS 65 PSC1 0 3V3 3 3 mA TxD Sdata out TX RS232 Driver 66 GND PWR Module supply 67 PSC6 3 3V3 4 4 mA IR USB
25. RxD und TxD signals of the RS232 interfaces are available at the module connectors The signals are allocated on the connector in such a manner that all processor signals non CPU and PLD signals as well as the reserve pins are routed to two 120 pin connectors The signals of the graphics controller are routed to two 40 pin module connectors 4 1 16 1 Board to Board Connectors Board to Board connection with two 120 pin and two 40 pin plug connectors 0 8 mm pitch The 0 8 mm pitch plug connectors are available in different heights 5 mm high module plug connectors are used on the 5200 Board to Module Connector Target Hardware Connector Boar edd No of Pins Qty Supplier Order No of Pins Supplier Order No 5 mm 40 2 tyco 177983 1 40 tyco 177984 1 6 mm 40 tyco 179029 1 7 mm 40 tyco 179030 1 8 40 tyco 179031 1 5 mm 120 2 tyco 177983 5 120 tyco 177984 5 6 mm 120 tyco 179029 5 7 mm 120 tyco 179030 5 8 mm 120 tyco 179031 5 Table 22 Board to Board Connectors The following lists describe the functionality and signal characteristics of the module pins Page 28 sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 4 1 16 2 Plug Connector X1
26. UART RS232 interface e CODEC interface for Soft Modem Master Slave CODEC Mode 125 and AC97 e Full duplex SPI mode IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller FEC Supports 100 Mbps IEEE 802 3 10 Mbps IEEE 802 3 10 Mbps 7 wire interface Universal Serial Bus Controller USB Version 1 1 Host only e Support for two independent USB slave ports Two Inter Integrated Circuit Interfaces 2 Serial Peripheral Interface SPI Dual CAN 2 0 A B Controller MSCAN Motorola Scalable Controller Area Network MSCAN architecture e Implementation of version 2 0A B CAN protocol Standard and extended data frames J1850 Byte Data Link Controller BDLC e J1850 Class B data communication network interface compatible and ISO compatible for low speed 125 kbps serial data communications in automotive applications Supports 4x mode 41 6 kbps n frame response types 0 1 2 and 3 supported Bg M Page 13 la components MPC5200CVR400B 400 MHz PPC 40 C to 85 C User s Manual TQM5200 UM 300 1 The functions described here are not available simultaneously The ote 7 PSCs functions are multiplexed More information about it can be n found in section 2 of the MPC5200 User Manual 4 1 2 CPU Power On Reset Configuration In the table shown below the described adjustments are made as per the rising edges of HRESET and a Hold Time of two clock cycl
27. UM 300 la components Acronym Meaning MOZI Module Extractor Modulzieher MSCAN Motorola Scalable Controller Area Network MSOP Micro Small Outline Package NA Not Assembled NC Not Connected PCB Printed Circuit Board PCI Peripheral Component Interconnect PD Pull Down Resistor PLD Programmable Logic Device PLL Phase Locked Loop PPC PowerPC PSC Programmable Serial Controller PU Pull Up Resistor PWR Power RAM Random Access Memory RF Radio Frequency RO Read Only ROM Read Only Memory RTC Real Time Clock SDRAM Synchronous Dynamic Random Access Memory SRAM Static Random Access Memory TQFP Thin Quad Flat Package TSSOP Thin Shrink Small Outline Package TTL Transistor Transistor Logic U Boot Universal Bootloader UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VCO Voltage Controlled Oscillator WO Write Only WP Write Protection Table 34 Acronyms and Definitions Page 49 la components User s Manual TQM5200 UM 300 8 2 References 1 2 3 4 5 6 MPC5200 Hardware Specifications Rev 2 5 2004 Freescale MPC5200 Users Guide Rev 2 8 2004 Freescale Application Note AN2458 D Rev 2 08 2004 MPC5200 Local Plus Bus Interface Freescale 5 501 Databook Rev 1 01 Silicon Motion Am29LV256ML 256 Megabit 16 M x 16 bit 32 M x 8 bit MirrorBit 3 0 Volt only Uniform Sector
28. as the default download interface As an alternative to PSC1 UART the PSC6 UART by can be configured as the default interface by setting O resistors For this a modified Universal Boot is required which supports this interface as by default 4 1 18 2 gt COP JTAG Interface signals of the Freescale COP JTAG interface debugging interface are available externally The COP JTAG interface is directly routed to the plug connectors It offers the following signals Pim SignaiNam Type 1 T0 o io 121 Gem s SSS 7 __ SS s m Sorese HadRee 15 OUT Check Stop OUt Proiecivo creut on tne arget harar 4 Tem esv Pw O Table 31 COP JTAG Interface 6 Pin Assignment on the Starterkit STK52xx The module pins are listed in Link einf gen table 20 connector X3 Page 40 sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 4 1 19 Supply The supply voltage of the module is specified as follows e Module supply 3 3 V 5 96 Battery supply 3 0 V to 2 7 V for example Lithium cell CR2032 Rae Vom 5200 3V Supervisor 33V Vopn 233V
29. components 8 Appendix User s Manual TQM5200 UM 300 8 1 Acronyms and Definitions The following terminology and abbreviations are used Acronym Meaning AD Address Data ATA Advanced Technology Attachment BDLC Byte Data Link Controller CAN Controller Area Network CODEC Code Decode COP Common On chip Processor CPLD Complex Programmable Logic Device CPU Central Processing Unit CS Chip Select DC Direct Current DS Data Size EEPROM Electrically Erasable Programmable Read Only Memory Byte wise re writable EMC Electromagnetic Compatibility ESD Electrostatic Discharge ETH Ethernet FEC Fast Ethernet Controller Flash Electrically Erasable Programmable Read Only Memory Block Erase FPU Floating Point Unit FR 4 Flame Retardant 4 GND Ground GPIO General Purpose Input Output IEEE Institute of Electrical and Electronics Engineers IFR In Frame Response IP Internet Protocol IrDA Infrared Data Association IRQ Interrupt Request Inter Integrated Circuit JTAG Joint Test Action Group Kbps Kilobit Per Second LED Light Emitting Diode Mbps Megabit Per Second MII Media Independent Interface MIPS Million Instructions Per Second MMU Memory Management Unit 48 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200
30. configuration bit 105 ATA DRQ 3V3 8 8 mA 10k PD 106 GND PWR Module supply 107 ATA Reset 3V3 8 8 mA 10k PU Driven from PSC1 4 Software reset 108 LP 55 O 3V3 8 8 mA 100k PU 109 3 3 PWR Module supply 3 3 V 5 96 110 LP 54 O 3V3 8 8 mA 100k PU 111 LP CS3 O 3V3 8 8 mA 100k PU 112 LP CS24 O 3V3 4 4 mA 100k PU Chip select for SRAM 113 LP 51 O 3V3 8 8 mA 100k PU 114 GND PWR Module supply 115 Reserve 19 Reserve connected 116 LP 50 3V3 4 4 mA 100k PU Chip select for Flash Changeover of Boot address 117 Start L H 3V3 3K3 PD 0 Low boot 1 High boot 118 LM75 O 6 mA 10K PU Alarm output of Temperature sensor Open drain output 119 3 3 PWR Module supply 3 3 V 5 96 120 GND PWR Module supply This value refers to Data Sheet MPC5200BDS Rev 01 state 01 2006 sjueuoduio2 D1 Aq 0L0ZO Under certain circumstances changes in the Data Sheet can lead to the fact that the data in this table is no longer correct Further descriptions about the pins can be gathered from the Data Sheet MPC5200BDS Rev 01 state 01 2006 Table 23 Plug Connector X1 i Page 30 2010 by TQ Components GmbH User s Manual 5200 UM 300 la components 4 1 16 3 Pin Configuration X1 Group wesaesa Function Group co 2 Ethernet
31. multiplexed 17 AL 1 ALE Length 18 AA 0 ACK Active 19 CE 1 Chip Enable bit 20 21 AS 11 Address Size field 22 23 DS 01 Data Size field 24 25 Bank 00 Bank bits 26 27 Wtyp 11 Wait state Type bits 28 WS 0 Write Swap bit 29 RS 0 Read Swap bit 30 WO 0 Write Only bit 31 RO 0 Read Only bit Table 12 Chip Select 2 Configuration Register K6X4016T3F TF70 SRAM 4 Mbit 40 C to 85 C K6X8016T3B TF70 SRAM 8 Mbit 40 C to 85 IS62WV25616BLL 55TLI 155 SRAM 4 Mbit 40 C to 85 IS62WV51216BLL 55TLI ISSI SRAM 8 Mbit 40 0 85 Table 13 _ 22 sjueuoduio2 D1 Aq 01020 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 4 1 10 EEPROM The serial EEPROM can e g store the characteristics of the module and customer specific parameter data non volatile As against flash individual memory cells can be deleted and overwritten in the EEPROM At delivery the EEPROM is erased e 0 to 64 Kbit Control bus 2 of the CPU I2C 25 I2C_2SDA 10 Pull up resistors at 12C_2SCL and 2 250 e Address lines of EEPROM at 0b000 M24C01WDW6 ST Microelectronics 1 K EEPROM TSSOP8 40 C to 85 C M24CO2WDW6 ST Microelectronics 2 K EEPROM TSSOP8 40 C to 85 C M24C04WDW6 ST Microelectronics 4 K EEPROM TSSOP8 40 C to 85 C Table 14 Serial EEPROM
32. supply is switched off Violation of this guideline may result in damage destruction of the module and be dangerous to your health Improper handling of your TQ product renders the guarantee invalid Proper ESD handling The electronic components of your TQ product are sensitive to electrostatic discharge ESD Always wear antistatic clothing and use ESD safe tools packing materials etc and operate your TQ product in an ESD safe environment Especially when you switch modules on change jumper settings or connect other devices Page 8 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 1 4 Registered Trademarks TQ Components GmbH aims to adhere to the copyrights of all the used graphics and texts in all publications and strives to use original or license free graphics and texts All the brand names and trademarks mentioned in the publication including those protected by a third party unless specified otherwise in writing are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation One should conclude that brands and trademarks are protected through the rights of a third party 1 5 Imprint TQ Components GmbH Gut Delling 2 0 82229 Seefeld Tel 49 0 8153 9308 0 Fax 49 0 8153 9308 134 Email info tgc de Web http
33. 26 27 28 29 30 31 150 9 0 0 0 0 0 0 0 0 0 9 0 0 0 9 0 Illustration 7 Chip Select 1 Configuration Register MBAR 0x0304 Bits Name Setting Description 0 7 WaitP Oxff Number of Wait States 8 15 Oxff The base number of wait states 16 MX 1 MX bit specifies whether transaction operates as multiplexed or non multiplexed 17 AL 1 ALE Length 18 AA 1 ACK Active 19 CE 1 Chip Enable bit 20 21 AS 11 Address Size field 22 23 08 11 Data Size field 24 25 Bank 11 Bank bits 26 27 11 Wait state Type bits 28 WS 0 Write Swap bit 29 RS 0 Read Swap bit 30 WO 0 Write Only bit 31 RO 0 Read Only bit Description of the setting as in Chip Select 0 Table 10 Table 18 Chip Select 1 Configuration Register 5 26 01 Aq 01029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 4 1 13 Clock generation for Graphics Controller For clock generation a 24 MHz oscillator is mounted For applications with a TFT Display on the Flat panel interface a Low EMI Spread Spectrum Oscillator is optionally installed This is an interface where heavy demands are made on the electromagnetic interfering radiation SX03 0507 E 50 W 24 000MHz Oscillator 24 MHz 40 C to 85 C 3HM57 F 24 000R C 1 5 EuroQuartz Low EMI Spread Spectrum 40 to 85 Oscillator 24 MHz Table 1
34. 9 Oscillators for the Graphics Controller 4 1 14 Diagnosis LED A red LED is provided to indicate CPU Reset 4 1 15 Serial Interfaces The internal UART PSC1 or optional the UART PSC6 of the MPC5200B is connected via RS232 compatible transceiver RxD TxD channel to the Board to Board connector It is configurable by placing 0 resistors irrespective of which of the two UARTS is used The internal UART PSC3 is connected the RS232 transceiver to the Board to Board connector RxD TxD channel Optionally the PSC3 UART can be detached by removing two 0 resistors The RS 232 interfaces offer a maximum speed of 115200 Baud UART Signal Name Signal Name CPU Port RS232 TxD 1 X3 72 UART1_TXD PSC1_0 X3 65 RS232_RxD_1 X3 71 UART1_RXD PSC1_1 X3 63 RS232_TxD_2 X3 76 UART3_TXD PSC3_0 X3 53 RS232_RxD_2 X3 75 UART3_RXD PSC3 1 X3 51 Table 20 RS232 UART Signals Component Mamufactuer Temperature Range SP3222EEA Dual RS232 transceiver 40 C to 85 Table 21 RS232 27 User s Manual 5200 UM 300 la components 4 1 16 Module Interfaces Except SDRAM interface the PLL supply and the XTAL pins all other microprocessor pins are routed to the plug connectors The CRT interface the LCD interface as well as the GPIOs of the graphics controller are routed to the plug connectors Moreover a Master Reset input an SRAM backup power input as well as driven
35. CLK BitCIk RTS 3 3 V Schmitt Trigger 68 PSC6 2 3V3 4 4 mA IrDA TX TxD 69 PSC6 1 3V3 4 4 mA CTS FRAME 70 5 6 0 3V3 4 4 mA IrDA 71 85232 RxD 1 115 85232 Port 1 Input PSC1 RxD 72 85232 TxD 1 O 15V 5VA 35 35 mA RS232 Port 1 Output PSC1 TxD 73 3 3V PWR Module supply 3 3 V 5 96 74 GND PWR Module supply 75 RS232 RxD 2 15V RS232 Port 2 Input PSC3 RxD 76 85232 TxD 2 15V 5V4 35 35 mA RS232 Port 2 Output PSC3 TxD I2C 3 3 3 V Schmitt Trigger EEPROM and temperature sensor 77 SDA 2 3V3 2 2 mA 10k PU HW address 000 I2C 2 3 3V Schmitt Trigger EEPROM and temperature sensor 78 SCL 2 3V3 2 2 mA 10k PU HW address 000 79 1 3V3 4 4 mA PU 2 1 3 3 V Schmitt Trigger 80 SCL 1 3V3 4 4 mA PU I2C 0 CAN1 3 3 V Schmitt Trigger Input accelerates Flash programming time when high voltage is applied 81 3V3 5k6 PU for higher throughput during system production Protects first or last sector regardless of sector protection settings 82 GND PWR Module supply 83 HRESETF 13V3 External Flash reset over 10k coupled with HRESET 84 GPIO_WKUP_7 3V3 8 8 mA 85 3 3 PWR Module supply 3 3 V 5 86 Vbatt 3V3 Battery supply for SRAM 87 SEL 3V3 4 4 mA Byte select Byte 0 for 32 bit access 88 SEL 0 3V3 4 4 mA Byte select Byte 1 for 32 bit access 89 SEL 2 3V3 4 4 mA Byte select
36. Can be applied as a prescale to WaitX or used by itself as specified by WTyp bits below Wait states control how many clocks the corresponding CS pin remains active Base number of wait states to insert or combined with WaitP as specified by WTyp bits below cfg operation rstcfg 11 on pad_eth_03 is zero then 4 wait states are in effect else 48 wait states are in effect Wait States equals the number of PCI clocks from CS assertion to when data must be valid from boot device MX bit specifies whether a transaction operates as multiplexed or non multiplexed A multiplexed transaction presents address and data in different tenures During the address tenure ALE is asserted At the end of ALE AD bus is switched to data tenure and CSx pin is asserted 16 MX 1 0 Non multiplexed 1 Multiplexed cfg operation rstcfg 14 on pad_eth_06 is low boot operation is non multiplexed single tenure else boot operation is multiplexed dual tenure ALE length multiplexed transactions only O ALE width is 1 internal IP bus clock 17 AL 1 1 ALE width is 2 internal IP bus clocks At boot time internal IP bus clock is twice the frequency of the PCI clock Therefore AL defaults to 1 2 IP bus clocks for boot device ACK Active multiplexed transactions only This bit defines whether ALE inputis active or not If AA is 1 programmed wait states can be overridden when if the external device drives the ACK input low If AA is 0 the ACK inputis ign
37. Configuration Register MBAR 0x0300 19 Chip Select 2 Configuration Register MBAR 0x0308 22 SM501 Block Circuit Diagram er pra EIAS 25 Chip Select 1 Configuration Register MBAR 0 0304 26 Supply voltage 41 Top view through the printed 43 VIGW sei 44 Bottom Vio RR 44 Stack heights not to gt 45 4 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual 5200 UM 300 la components Table directory Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Terms 7 cO RU ME LL 14 Reset Configuration hese siete S 15 Oscillators and crystal oscillator for MPC5200 _ 16 18 TQM5200 18 Temperature
38. DD IO 3 3 V 16 16 PCI PCI_FRAME O VDD_IO 3 3 V 16 16 PCI z PCI_GNT O IO 3 3 V 8 8 LVTTL PCI IDSEL VDD IO 3 3 V 8 8 LVTTL PCI IRDY O IO 3 3 V 16 16 PCI PAR O VDD IO 3 3 V 16 16 PCI PERR O VDD IO 3 3 V 16 16 PCI PCI REQ O IO 3 3 V 8 8 LVTTL VDD IO 3 3 V 16 16 PCI PCI_SERR O 0 10 3 3 V 16 16 PCI PCI_STOP VDD_IO 3 3 V 16 16 PCI PCI_TRDY IO 3 3 V 16 16 PCI Local Plus LP_ACK O 0 IO 3 3 V 6 6 LVTTL Pullup LP ALE O VDD IO 3 3 V 7 7 LVTTL LP OE IO 3 3 V 6 6 LVTTL RW VDD IO 3 3 V 6 6 LVTTL LP_TS IO 3 3 V 6 6 LVTTL LP CSO O VDD IO 3 3 V 6 6 LVTTL LP CS1 O VDD IO 3 3 V 6 6 LVTTL LP CS2 O VDD IO 3 3 V 6 6 LVTTL LP CS3 O VDD IO 3 3 V 8 8 LVTTL LP CS4 O VDD IO 3 3 V 8 8 LVTTL LP CS5 O VDD IO 3 3 V 8 8 LVTTL ATA DACK O VDD IO 3 3 V 8 8 LVTTL O IO 3 3 V 8 8 LVTTL INTRQ IO 3 3 V 8 8 LVTTL IOCHRDY IO 3 3 V 8 8 LVTTL O IO 3 3 V 8 8 LVTTL ATA IOW O IO 3 3 V 8 8 LVTTL ATA_ISOLATION O VDD IO 3 3 V 8 8 LVTTL Page 36 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components
39. Environmental Protection By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the product it is produced in such a way a modular construction that it can be easily repaired and disassembled The energy consumption of this subassembly is minimised by suitable measures Printed pc boards are delivered in reusable packaging Modules and devices are delivered in an outer packaging of paper cardboard or other recyclable material Due to the fact that at the moment there is still no technical equivalent alternative for printed circuit boards with bromine containing flame protection FR 4 material such printed circuit boards are still used No use of PCB containing capacitors and transformers polychlorinated biphenyls These points are an essential part of the following laws The law to encourage the circular flow economy and assurance of the environmentally acceptable removal of waste as at 27 9 94 source of information BGBI I 1994 2705 Regulation with respect to the utilization and proof of removal as at 1 9 96 source of information 1996 1382 1997 2860 Regulation with respect to the avoidance and utilization of packaging waste as at 21 8 98 source of information BGBI 1998 2379 Regulation with respect to the European Waste Directory as at 1 12 01 source of information BGBI I 2001 3379 e M Page 47 la
40. Flash Memory with Versatile I O Control Publication 25263 Rev C Amendment 2 Issue Date June 11 2003 MPC5200 L25R Errata Rev 4 9 2004 Freescale Page 50 sjueuoduio2 D1 Aq 0L0ZO
41. be gathered from the Data Sheet MPC5200BDS Rev 01 state 01 2006 Table 25 Plug Connector X3 _______ 33 la components 4 1 16 5 Pin Configuration X3 2 1 SRESET 4 6 5 402 8 7 IMS Power J 9 fao CPU CPU JTAG 13 33 Power GND USB1 Power GND 0581 1 USB1 3 1 5 mm 0581 5 0581 7 wm USB1 8 USB1 9 TIMER 0 TIMER 1 TIMER 3 Timer TIMER 2 Timer TIMER 4 TIMER 6 PSC3 8 PSC3 PSC3 6 PSC3 4 A05 C05 B06 07 08 09 C09 C10 37 35 ______ Power 39 PSC3 5 PSC3 3 33v PSC3 1 PSC3 0 ind PSC2 3 PSC2 1 PSC1 3 PSCi E fen esce Powr sc fve we Sa WP ACC rusn Reset Battery vbat3va ___ 9 85 osv Por Poner en 1 19 91 non CPU serpa 638 ____ noncPU s2 91 eee f ense 96 5 s fer Poer 97 Reseve6 110 99 7 Reserve 102 101 Reserve
42. ble 32 Maximum current consumption 4 1 19 4 Power Consumption Typical Values Following values are to be considered for the typical power consumption of the TQM5200 without external protective circuit e 5200 with graphics controller and one SDRAM Bank 128 Mbyte present approx 1100 mA TQM5200 without graphics controller with 16 Mbyte SDRAM approx 900 mA 4 1 19 5 Reset Logic Supervisor The Reset Logic comprises of the following functions e Monitoring of all supply voltages used on the module 3 3 V 1 8 V 1 5 V e External reset input Battery back up function for SRAM battery not on the module e Chip Select gating for SRAM Reset Status displayed by a red LED 7 Without external protective circuit 8 One SDRAM Bank equipped Two SDRAM Banks equipped i Page 42 01 Aq 0L0ZO 2010 by TQ Components GmbH 9 5 1 5 2 5 3 User s Manual TQM5200 UM 300 0 components Mechanics General Information e High pin count SMD plug connectors with 0 8 mm pitch e The combination with different counterparts allows customisation of the stack height to the height of the parts mounted on the target hardware e Double sided SMD assembly Dimensions e Dimensions of the PCB 80 mm x 60 mm e Overall height approx 10 mm e Free overall height under the module approx 2 9 mm Mounting oj 48 g X2
43. cell ppc cfg 0 4 XLB CLOCK i MEM CLOCK T stem 8 xlb sel IPB CLOCK ipb clk sel 2 PCI CLOCK PCI Clock Divider xlb sel ipb clk sel pci clk sel 1 0 1 fsystem USB CLOCK Fractional Divider 48 MHz CLOCK 6 6 25 6 5 11 SYS XTAL IN PSCI MCLK DIVIDER 5 1 MCLK sys feystem MclkDiv 8 0 1 divide Lid PSC2 MCLK DIVIDER PSC2 MCLK f MclkDiv 8 0 1 divide PSC3 DIVIDER PSC3 MCLK MclkDiv 8 0 1 Sys cfg 0 2 2 PSC6 MCLK DIVIDER PSC6 MCLK Illustration 3 feystem MclkDiv 8 0 1 MPC5200 Clock Relations Page 17 components User s Manual TQM5200 UM 300 4 1 4 CPLD A Lattice ispMach4064V 5 481 is used as CPLD in a 48 pin TQFP housing In addition to the CPU Power On Reset Configuration described above the CPLD generates two Byte Select signals for the SRAM component Tye ispMach4064V 57481 CPLD 64 macro cells 40 C to 85 Table 5 CPLD The JTAG pins of the CPLD are connected to the module pins of the TQM5200 described in the following table TCK PLD X348 CPLD JTAG Interface xem dT terface Sly ow 6m Table 6 TQM5200 CPLD JTAG Interface 4 1 5 Temperature M
44. elect Control Register IE bit In any case no transaction is presented to the peripheral NOTE This bit is high from Reset indicating Boot Device is Read Only Chip Select 0 Boot Configuration Register K8P2815UQB EI4B Flash MirrorBit 16 M 16 40 C to 85 C Table 11 Flash Memory component These devices have a 64 ball Fortified BGA housing with dimensions of 13 x 11 mm Page 21 User s Manual 5200 UM 300 la components 4 1 9 SRAM e One memory bank with 16 bit bus width e Memory capacity 512 Kbyte or optional 1 Mbyte e Access time 70 ns Battery buffering via module connector Standby Power consumption max 20 pA The SRAM is connected an address register and a bus driver to the multiplexed Local Plus Bus of the processor e The ALE Signal is configured as long e Four wait states are used for accessing the SRAM e Signal CS2 is used for SRAM selection 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mem Waitx RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 2 27 6 2 28 29 30 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Illustration 5 Chip Select 2 Configuration Register MBAR 0x0308 31 Isb 0 Bits Name Setting Description 0 7 WaitP 0x00 Number of Wait States 8 15 WaitX 0x04 The base number of wait states 16 MX 1 MX bit specifies whether transaction operates as multiplexed or non
45. ents without any further measures Following measures are recommended e Generally applicable Shielding of the inputs shielding connected well to ground housing on both ends e Supply voltages Protection by suppressor diode s Slow signal lines RC filtering perhaps Zener diode e Fast signal lines Integrated protective devices Suppressor diode arrays 73 Reliability and Service Life The module is designed for a service life of 10 years It was also designed to be insensitive to vibration and impact Page 46 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH fm Manual TQM5200 UM 300 components 7 4 Climate Conditions and Operational Conditions e Protection class 00 Relative air humidity operation storing 10 90 not condensing The possible temperature range strongly depends on the installation situation heat dissipation by conduction and convection Hence no fixed value can be given for the whole assembly Reliable operation is generally achieved when the following conditions are met e Standard temperature range Chip temperature of the CPU 0 to 70 Package temperature of the remaining ICs C to 70 Storage temperature 5 C to 85 C e Extended temperature range Chip temperature of the CPU 40 C to 85 C Package temperature of the remaining ICs 40 C to 85 C Storage temperature 55 C to 100 C 7 5
46. erface MTM 40 Maximum current 42 wired cse HT 45 Acronyms and Definitions t a Rena Abou 49 Page 5 la components Revision history User s Manual TQM5200 UM 300 Rev Date Name Pos Modification 049 08 08 2004 VJU Creation Provisional Specification 050 09 08 2004 ANW Adaptation 201 17 01 2005 VJU Finalization 202 16 02 2005 VJU Revision after internal checks 203 25 02 2005 VJU 5 3 Drawing added 14 04 2005 ANW Revision 204 10 05 2005 DEN Translation 300 12 10 2010 Petz Completely revised Page 6 01 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 1 About this manual This manual contains technical information concerning the TQ Minimodule TQM5200 11 Tips on Safety Improper or incorrect handling of the product can substantially reduce its life span 1 2 Terms and Conventions Symbol Tag Meaning This symbol represents the handling of electrostatic sensitive modules and or components These components are often damaged destroyed with the transmission of a voltage higher than about 50 V A human body usually only experiences electrostatic discharges above approximately 3 000 V This symbol indicates the possible use
47. es e 7 hardware display layers to support split screen overlay and alpha blending Per pixel or planar alpha blend capability between layers e Colour space conversion from YUV422 YUY2 and UYVY YUV420 Planar4 1 1 YV12 IYUV 1420 IMC1 IMC2 IMC3 4 NV12 NV21 RGB565 RGBA888 to RGB565 or RGBF888 Memory Configurations Dedicated graphics memory with 8 Mbyte Package 19 mm x 19 mm 297 pin BGA 0 8 mm ball grid Process 0 18 um e Internal memory option 0 or 8 Mbyte Page 25 User s Manual 5200 UM 300 la components SM501GE08 Silicon Motion Graphics Controller 40 C to 85 C Table 17 Graphics Controller The graphics controller operates at 66 MHz in the SH4 mode For this it is connected to the Local Plus Bus of the MPC5200 The Local Plus Bus is selected in the memory by the CS1 signals through the graphics controller and is configured as a 32 bit multiplexed bus The ALE and the TS Signal are configured as long Access to the SM501 is controlled by acknowledge Maximum number of wait states are programmed for this type of access and for the addresses of CS1 signals An access cycle ends one pulse after the falling edge of the acknowledge signal The values for the CS1 Configuration Register are listed in the following table msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 0 0 0 0 0 0 0 0 0 9 0 0 0 9 0 16 17 18 19 20 21 22 23 24 25
48. es SYS XTAL of CPU pins and are stored in the CDM Reset Configuration register The adjusted configuration cannot be changed when the CPU is running The Reset configuration is set by a CPLD During the Reset phase the configuration is set at the configuration pins of the CPU until the rising edge of the HRESET Afterwards the CPLD outputs are changed to high impedance Wrong adjustment can render the system to be no longer bootable With the settings established the PLL configuration is among the things that are of concern This configuration determines the XL bus Frequency and the CPU core frequency Settings for PCI and Local Plus Bus are derived from the XL bus frequency and can be changed at runtime Further boot settings are made here which apply only to data accesses over Boot CS The access over 0 to 55 be changed at runtime Warning The default values specified in Table 3 are qualified for the module TQM5200 The settings of the deviating values takes place at one s own risk and without guarantee on the part of TQ Components GmbH Malfunctions as well as destruction of the module cannot be excluded with deviating configurations Page 14 sjueuoduio2 D1 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 CDM Reset Config Register Bit T T 3 5200 Start up Signal Name Config Signal from CDM la components Desc
49. faces 36 2 sjueuoduio2 D1 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components Table of contents 4 1 17 Chip Selects und 40 4 1 18 Service 40 4 1 18 1 Download 40 4 1 18 2 Interface 40 e 41 4 1 19 1 Tolerance of the external supply 41 4 1 19 2 Internal voltage KHEN 41 4 1 19 3 Power Consumption Maximum Values 42 4 1 19 4 Power Consumption Typical 42 1195 Reset Logic Supervisor 42 5 gt MECHANICS 43 5 1 General 43 52 DIMENSIONS 43 Io re 43 5 4 View 5200 44 5 5 Bottom View 5200 44 5 6 Side View 1 5200
50. mall or big data size config bit Data Size field represents the peripheral data bus size in bytes 00 1 Byte 01 2 Bytes 10 3 Bytes Not Supported 2223 DS 1 11 4 Bytes cfg operalion rstcfg 13 on 05 is low then the data size for non multiplexed boot device is set to 8 bits 05 00 else the boot device is treated as 16 bit DS 201 device For multiplexed mode boot device the selection is 16 bit data or 32 bit data respectively 2425 00 Bank bits are reflected on external AD lines AD 26 25 during Address tenure of a multiplexed transaction Register bit 24 is the msb and appears AD 26 Wait state type bits define the application of wait states contained WaitP and WaitX fields as follows 00 is applied to read and write cycles is ignored 26 27 WTyp 1 01 is applied to Read cycles is applied to Write cycles 10 lt is applied to Reads WaitX 16 bit value is applied to Writes 11 WaitP Waitx as a full 16 bit value is applied to Reads and Writes e Page 20 0 7 0 00 8 15 0 08 18 0 01 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components Bits Name Setting Description 28 WS Write Swap bit If high Endian byte swapping occurs during writes to a
51. nge of direction is controlled by the LP_RW signal TAALVC16245A Philips 16 bit bus driver 40 to 85 9 4 1 8 Flash Memory e 3 3 V flash of the MirrorBit Series Samsung 16 bit e 1 bank with two devices and a bus width of 32 bit e Connected at the multiplexed Local Plus Bus The address signals are connected via 25 bit address register and the data is connected via a 32 bit bus driver The ALE signal is configured as e Eight wait states are used for accessing the flash memory e Memory sizes of 4 to 32 Mbyte using the Bank Select bits 64 128 Mbyte e Access time 120 ns The signal Boot CS physical 50 is used as chip select to boot from Flash The configuration for CSO is described in Table 10 The status signal RY BY of the Flash is not used i e the write and delete cycles must be checked by polling the Flash status bits DQ7 Toggle bits etc msbO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EL WaitX RESET 0 0 0 0 0 0 0 0 cg cg cg cg 16 17 18 19 20 21 22 23 4 25 26 27 28 29 30 31 WTyp ws Rs wo cfg 1 1 1 cg cg cg 0 0 0 0 0 0 0 1 Illustration 4 Chip Select 0 Boot Configuration Register MBAR 0x0300 Page 19 User s Manual 5200 UM 300 la components Chip Select 0 Boot Configuration Register Bits Name Setting Description Number of wait states to insert
52. of voltages greater than 24 V Please note the relevant statutory regulations in this regard Non compliance with these regulations can lead to serious damage to your health and also cause damage destruction of the component This symbol indicates a possible source of danger Acting against the procedure described can lead to possible damage to your health and or cause damage destruction of the material used This symbol represents important details or aspects for working with TQ products Filename ext This specification is used to state the complete file name with its corresponding extension Instructions Examples of an application e g Specifying memory partitions E 1 5 Processing a script 4 4255 Reference Cross reference to another section figure or table Table 1 Terms and conventions 7 User s Manual 5200 UM 300 la components 1 3 Handling and ESD tips General handling of your TQ products The TQ product may only be used and serviced by certified personnel who have taken note of the information the safety regulations in this document and all related rules and regulations A general rule is not to touch the TQ product during operation This is especially important when switching on changing jumper settings or connecting other devices without ensuring beforehand that the system s power
53. onitoring e Monitors the CPU temperature indirectly using a temperature sensor on the soldering side of the PCB near the CPU Sensor 75 The switching output of LM75 is routed to the Board to Board connectors Control bus I2C_2SCL 2 25 address lines 06000 2 bus is shared with 5 as the address parts are fixed and there is no address collision with EEPROMs National Semiconductor 400 kHz 3 Addr 40 to 85 C MSOP8 0 65 mm LM75CIMM 3 Table 7 Temperature Sensor 18 01 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components 4 1 6 Address Register All bus subscribers which are connected to the Local Plus Bus in multiplexed mode SRAM flash graphics controller require an address register with up to 25 bit width The addresses are locked with the address register with the rising edge of the inverted LP_ALE signal As a latch the positive edge triggered register 74LVC16374 is used SN74LVC16374 DGG 16 bit D Latch 40 C to 85 C Table 8 Address Register 4 1 7 Bus Driver Bus drivers are installed to prevent a bus overload This bus is divided into Local Plus ATA and PCI bus Two 16 bit bus drivers type 74ALVC16245A are used The bus drivers are activated with the signals Boot CS 50 flash CS1 graphics controller and CS2 SRAM The cha
54. ored Wait states are still in effect If no ACK is received cycle terminates at end of wait state period cfg rstcfg 14 on pad 06 is high indicating multiplexed mode boot device then AA is assumed high as well This lets the boot device shorten the Wait State period by asserting the ACK input An individual Enable allows CS operation for the corresponding CS pin CE must be high to allow 19 CE 1 Register 6 master enable bit must also be high except when CS 0 is used for boot ROM Enable 0 Disabled register writes can occur but no external access is generated Address Size field defines size of peripheral Address bus in bytes and must be consistent with physical connections 00 8 bits 01 16 bits 10 224 bits 11 gt 25 bits 20 21 AS 1 See documentation for Physical Connection requirements The combination of address size data size and transaction type MX must be consistent with the peripheral physical connection In case of a multiplexed transaction the entire address is driven regardless of address size field cfg operation rstcfg 13 on pad 05 is low then the address size for non multiplexed boot device is 24 bits AS 210 else the boot device is treated as 16 bit address AS 201 device For multiplexed mode boot devices the maximum 25 bits of address is always driven This rstcfg bit more particularly affects the DS field below and can be thought of as the s
55. peripheral 8 bit peripherals this bit has no effect For 16 bit peripherals byte swapping can occur For 32 bit peripherals possible in MUXed mode only byte swap can occur 1 swap 0 NO swap 2 byte swap is AB to BA 4 byte swap is ABCD to DCBA NOTE Transactions at less than the defined port size i e data size apply swap rules as above according to the current transaction size 29 RS Read Swap bit Same as WS but swapping is done when reading data from a peripheral 1 5 0 swap cfg operalion rstcfg 12 on pad_eth_04 is low data from the boot device is Endian swapped when read This only has effect for boot devices configured as 16 or 32 bit data size 30 wo Write Only bit If bit is high the peripheral is treated as a write only device An attempted read access results in a bus error as dictated by Chip Select Control Register EBEE bit and or an interrupt as dictated by Chip Select Control Register IE bit In any case no transaction is presented to the peripheral A bus error means the internal cycle is terminated with a transfer error acknowledge ips_xfr_err assertion to IP bus TEA assertion to XL bus 31 RO Table 10 Read Only bit If bit is high the peripheral is treated as a read only device An attempted write access results in a bus error as specified by Chip Select Control Register EBEE bit and or an interrupt as specified by Chip S
56. r debug port 3 3 V Schmitt Trigger 15 Test Mode1 3V3 10k PD Test Mode Select 1 for processor production test Scan Enable for processor production test PLL BYPASS input 16 TEST SEL 0 3V3 4 4 mA CK STOP output 17 Test ModeO 3V3 10k PD Test Mode Select 0 for processor production test 18 GND PWR Module supply 19 USB1 1 3V3 4 4 mA USB TXN Reset configuration bit 20 USB1 0 3V3 4 4 mA USB OE 21 USB1 3 3V3 4 4 mA USB RXD 22 USB1 2 3V3 4 4 mA USB TXP Reset configuration bit 23 USB1 5 3V3 4 4 mA USB RXN 24 USB1 4 3V3 4 4 mA USB RXP 25 3 3V PWR Module supply 3 3 V 5 96 26 GND PWR Module supply 27 USB1 7 3V3 4 4 mA USB SPEED 28 USB1 6 3V3 4 4 mA USB PORTPWR 29 USB1 9 3V3 4 4 mA USB OVERCNT 30 USB1 8 3V3 4 4 mA USB SUSPEND 31 TIMER 1 3V3 4 4 mA 32 TIMER 0 3V3 4 4 mA 33 TIMER 3 3V3 4 4 mA MISO 34 GND PWR Module supply 35 TIMER 5 3V3 4 4 mA SCK 36 TIMER 2 3V3 4 4 mA MOSI 37 3 3V PWR Module supply 3 3 V 5 96 38 TIMER 4 3V3 4 4 mA 55 39 7 3V3 4 4 mA 40 TIMER 6 3V3 4 4 mA 41 PSC3 9 3V3 4 4 mA USB SCK 42 GND PWR Module supply 43 PSC3 7 3V3 4 4 mA USB SPEED MISO 44 PSC3 8 3V3 4 4 mA USB SUSPEND 55 45 PSC3 5 3V3 4 4 mA USB
57. ription MPC5200 G2_LE PPC ATA_lOW ppc 2 Core PLL Configuration LP _ TUE FE o D e pa pe s me EE sel XLB CLK SYS 4 XLB CLK SYS Fvco 8 SYS Fvcozl6 5 5 FREF SYS Fvco 12 5 5 FREF VCO SYS VCO VCO 2 x SYS_PLL_FVCO No Boot in Most Graphics Mode Boot in Most Graphics Mode Microprocessor Boot Address Exception table location ETH2 ppc_msrip Bit 0 0000 0100 hex Bit 1 FFFO 0100 hex 0 4 IP bus clocks of wait state Bit 0 No byte lane swap same endian ROM image ETH4 boot_rom_swap Byte lanie ewer different endian ROM image For non muxed boot ROMs Bit 0 8 bit boot ROM data bus 24 bit max boot ROM address bus Bit 1 16 bit boot ROM data bus 16 bit boot ROM address bus 13 1 18 ETH5 boot rom size For muxed boot ROMs boot ROM address is max 25 significant bits during address tenure 16 bit ROM data bus Bit 1 32 bit ROM data bus non muxed boot ROM bus single tenure transfer 14 1 17 ETH6 boot rom type Bit 1 muxed boot ROM bus with address and data tenures ALE and TS active No Boot in Large Flash Mode ETH1 large flash sel Bit 1 Boot in Large Flash Mode Table 3 Reset Configuration Page 15 User s Manual 5200 UM 300 la components 4 1 3 CPU Clock generation On the module two oscillators and one crys
58. specification Page 45 User s Manual 5200 UM 300 la components 7 Safety Requirements and Protective Requlations 71 EMC Requirements The module was developed according to the requirements of electromagnetic compatibility EMC Depending on the target hardware anti interference measures may still be necessary to guarantee the adherence to the limits for the overall system Following measures are recommended e Robust ground planes adequate ground planes on the target hardware e With metal casings a good at least according to RF connection to the target hardware or to the potential of the housing sufficient number of blocking capacitors in all supply voltages e Fast or permanent clocked lines e g clock should be kept short avoid interference of other signals by distance and or shielding e Filtering of all signals which can be connected externally also slow signals and DC can radiate RF indirectly 7 2 ESD Requirements In order to avoid interspersion on the signal path from the input to the protection circuit in the system the protection against electrostatic discharge should be arranged directly at the inputs of a system As these measures always have to be implemented on the target hardware no special preventive measures were planned on the module According to the data sheets the used devices already have some protection however this is generally not sufficient to fulfil the legal requirem
59. srambattery gt Processor 0 SDRAM Backup controller Flash Graphics 3 3V SRAM Supply Power Low VDD 1 5 V Prozessor PLL Power Fail Logic DC DC Converter 1 8 1 8 V Power Fal agio o SM501 Core Illustration 8 Supply voltage 4 1 19 1 Tolerance of the external supply voltage Tolerance of 3 3 V supply VCC3V3 3 3 V 5 3 135 V to 3 465 V Reset is triggered when voltage drops below 3 06 V 4 1 19 2 Internal voltage MPC5200 Core voltage 1 5 V 5 90 SM501 Core voltage 1 8 V 5 Page 41 la components a M ee sl User s Manual 5200 UM 300 la components 4 1 19 3 Power Consumption Maximum Values Device 3 3 1 5 1 8 Processor Core 800 Processor I O 10 1 5 mA 660 mA 1320 mA 40 Serial EEPROM 1 mA Graphics controller 160 mA 80 mA Flash 120 mA Supervisor 3 3 V 40 pA Power Fail Logic 1 5 V 10 pA Power Fail Logic 1 8 V 10 pA 65232 transceiver 1 mA 20 Address register 20 mA PLD 12 Total approx 1050 mA 1700 mA approx 800 mA approx 80 mA Total to be supplied max 1550 2100 3 3 V Ta
60. t Trigger VO IO 3 3 V 8 3 3 Schmitt Trigger SRESET VO IO 3 3 V 8 3 3 Schmitt Trigger IRQO VO IO 3 3 V 4 4 LVTTL IRQ1 IO 3 3 V 4 4 LVTTL IRQ2 0010 3 3 V 4 4 LVTTL IRQ3 IO 3 3 V 4 4 LVTTL 38 01 Aq 0029 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 la components Name Alias Type Power Supply Output Driver Input Type PU PD IOL mA Test Configuration SYS PLL TPA O VDD IO 3 3 V 4 4 LVTTL TEST MODE 0 Input IO 3 3 V 4 4 LVTTL TEST MODE 1 Input IO 3 3 V 4 4 LVTTL TEST SEL 0 O VDD IO 3 3 V 4 4 LVTTL Pullup TEST SEL 1 O VDD IO 3 3 V 8 8 LVTTL JTAG TCK Input IO 3 3 V LVTTL Pullup JTAG TDI Input IO 3 3 V LVTTL Pullup JTAG TDO TDO VO VDD IO 3 3 V 8 8 LVTTL JTAG TMS TMS Input IO 3 3 V LVTTL Pullup JTAG TRST TRST Input IO 3 3 V LVTTL Pullup Graphics Interface FP 23 0 Output IO 3 3 V 4 4 CRT HSYNC Output IO 3 3 V 4 4 CRT VSYNC Output IO 3 3 V 4 4 CRT Red Output analog 6 6 Output analog 6 6 Output analog 6 6 GPIO all
61. tal oscillator are present 33 MHz oscillator for the CPU 24 MHz oscillator for the SM501 Graphics controller 32 768 kHz crystal oscillator for the MPC5200 s RTC To use this RTC the 3 3 V supply voltage of the module must be available In order to reduce the quiescent current input for a system it is recommended to implement an external RTC on the target hardware An external RTC can be connected e g via the bus clock frequencies required by the CPU are generated CPU internal derived from the 33 MHz oscillator SX03 0507 E 50 W TJE Oscillator 33 MHz 40 to 85 33 000MHz SX03 0507 E 50 W TJE Oscillator 24 MHz 40 C to 85 24 000MHz MC306 Epson Seico Crystal oscillator 40 to 85 32 768 2 Table 4 Oscillators and crystal oscillator for the MPC5200 The clock frequencies for the 5200 module are derived from the 33 MHz input clock and set by the Reset configuration register to generate the following frequencies XLB CIk 132 MHz PB CIk 132 MHz PCI Bus CIk 66 MHz 396 MHz Page 16 01 Aq 0L0ZO 2010 by TQ Components GmbH User s Manual TQM5200 UM 300 0 components vCOcore divide by 2or4 XLB Clock Divider 603e G2 LE CORE CLOCK 603e 62 LE Core APLL divide by 2 2 5 3 0 7 5 8 Core APLL Control Logic e
62. tem of the module was selected Based on experience a 0 8 mm mezzanine connector system is used 3 Functionality and System Architecture The TQM5200 is a Minimodule based on the MPC5200 PowerPC CPU Freescale and an SM501 graphics controller by Silicon Motion 3 1 System Architecture Block Diagram 01 Aq 0L0ZO External Power Supply SDRAM EEPROM SRAM 32 Bit seriell I2C ___ 16 Bit multiplexed 16 128MByte 512kByte 1MByte 33V 256MByte BARBI Supervisor Flash 3 3V Power Fail Logic Adress 32 Bit multiplexed SRAM Battery Backup Register 4MByte 32MByte 64MByte Programmable SDRAM Local Plus Bus 24 Bit Serial Controller 66MHz 33MHz Controllers Core Supply Reset Configuration including Motorola PowerPC MPC5200 Fait Logic 15V PLD 400MHz Ethernet10 100 USB Host UART I2C SPI IRDA Em 97 Supervisor Gates 1 5 Treiber 24MHz 4 8V Power Fail Logic 32 Bit COP JTAG RS232 d Grafik Controller 32 Bit multiplexed Test Degugging Drivers for 2 RS232 SM501 8MB Byte internal Memory
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