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Infineon 80C517/80C537 User's Manual

1. Bit Function MXO Select 12 input channels of the A D converter MX1 MX2 MX3 ADM A D conversion mode When set a continuous conversion is selected If ADM the converter stops after one conversion BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is completed ADEX Internal external start of conversion When set the external start of conversion by P6 0 ADST is enabled Figure 7 27 Special Function RegisterADCON1 Address 0DC 4 2 1 1 A D converter control register 1 It contains channel selection bits to Bits to 2 can be written or read either in ADCONO or in ADCON1 Semiconductor Group 85 SIEMENS On Chip Peripheral Components Table 7 6 Selection of the Analog Input Channels MX3 MX2 1 Selected Channel Pin 0 0 0 0 Analog input 0 P7 0 0 0 0 1 Analog input 1 P7 1 0 0 1 0 Analog input 2 P7 2 0 0 1 1 Analog input 3 7 0 1 0 0 Analog input 4 P7 4 0 1 0 1 Analog input 5 P75 0 1 1 0 Analog input 6 P7 6 0 1 1 1 Analog input 7 P7 7 1 x 0 0 Analog input 8 P8 0 1 X 0 1 Analog input 9 P8 1 1 X 1 0 Analog input 10 P8 2 1 X 1 1 Analog input 11 P8 3 X means that the value may be 1 or 0
2. JB bit rel Function Jump if bit is set Description If the indicated bit is a one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected Example The data present at input port 1 is 11001010p The accumulator holds 56 010101108 The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 Operation JB lt 3 if bit 1 then PC lt PC rel Encoding 00100000 bit address rel address Bytes Cycles Semiconductor Group 205 SIEMENS Instruction Set JBC bit rel Function Jump if bit is set and clear bit Description If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction n either case clear the designated bit The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the in
3. 106 7 5 5 Timer Compare Register Configurations in the CCU 107 7 5 5 1 Compare Function of Timer 2 with Registers CRC CC1 to 4 108 7 5 5 2 Compare Function of Registers to CM7 116 7 5 6 Capture Function in the 123 7 6 Anthmetie aw CARY RA GE 126 7 6 1 Programming the MDU 126 7 6 2 Multiplication DIVISION uum ees rd NALE a 128 7 6 3 Normalize and Shift 5 e oe SU EROS ARR NUR 129 7 04 OVertOW Flag za nam TERREA A TEE 132 FOO TOSEMO Flag iua 132 7 7 Power Saving Modes SURE ex A RR AU NOS AUR ERREUR 134 7 7 1 136 7 7 2 Power Down Mode 2 Lug kde PES yh hee a ear eee ae aa LS 139 7 7 3 Slow Down 140 7 8 Fail Save Mechanisms sull ull ke eee ee mS ee mn RC 141 Semiconductor Group 6 SIEMENS 80C517 80C537 Table of Contents Page 7 8 4 Programmable Watchdog Timer 141 7 8 2 Oscillator Watchdog ac wr abite ce aceti dd ar a eee Cs 146 7 9 Oscillator and Clock Circuit EE NU e xS 148 T10 System Glock sont cna ES 150 8 Interrupl Syslem xcci e ELE E Res 152 8 1 Interrupt St L
4. E AS 5 x ot 5 2 5 ac EE x gt lt gt lt 05 S c Qc tnc ac GU z gt lt gt lt C m8 o a Receive Figure 7 17 b Timing Diagram Serial Interfaces 0 and 1 Mode 1 Mode B Semiconductor Group 73 SIEMENS On Chip Peripheral Components S Internal Bus 0 8 Write to SxBUF Shift Data TX Control Tlx Send Baud Serial gt 1 Rate gt Port Clock Interrupt RX Clock Load Tm SxBUF Transition RX Control Detector 1FFy Shift Register RXD l X Shift Load Shift SxBUF Note x means that O or 1 can SZ be inserted for interface SxBUF 0 or interface 1 resp Read SxBUF 7 Internal Bus MCS01834 Figure 7 18 a Functional Diagram Serial Interfaces 0 and 1 Modes 2 and 3 Mode A Semiconductor Group 74 On Chip Peripheral Components SIEMENS 9 81012 M VU VU MIU VU VEU MIU 1000990 18 13534 91 1g Transmit 1415 1495 7 Receive 9015 Il axl HIUS ANEXS 94 291 XL Timing Diagram Serial Interfaces 0 and 1 Modes 2 and 3 Mode Figure 7 18 b 75 Semiconductor Group SIEMENS On Chip Peripheral Components 7 3 Timer 0 and Timer 1 SAB 80C517
5. 0 5 V Output low voltage VoL 0 45 V 1 6 mA ports 1 2 3 4 5 6 Notes see page 311 Semiconductor Group 308 SIEMENS SAB 80C517 80C537 DC Characteristics cont d Parameter Symbol Limit Values Unit Test Condition min max Output low voltage Vout 0 45 V 3 2mA ports ALE PSEN RO Output high voltage Vou 2 4 V 80 ports 1 2 3 4 5 6 0 9 10 Output high voltage Vout 2 4 V 800 pA port 0 in external bus mode 0 9 V 80 pA ALE PSEN RO Logic 0 input current Ti 10 70 Vin 0 45 V ports 1 2 3 4 5 6 Input low current to RESET 10 100 Vin 0 45 V for reset Input low current XTAL2 15 uA 0 45 V Input low current 20 Vin 0 45 V OWE PE SWD Logical 1 to 0 transition current 65 650 2 ports 1 2 3 4 5 6 Input leakage current 1 1 uA 10 45 lt Vin lt port 0 EA ports 7 8 Pin capacitance 10 pF 1 MHz 25 Power supply current Active mode 12 MHz 9 Icc _ 40 mA 5 9 Idle mode 12 2 15 mA 5 Slow down mode 12 MHz 9 15 mA Voc 25 Active mode 16 MHz 9 Icc 52 3 mA 5 Idle mode 16 MHz 19 mA 5 v Slow down mo
6. 263 11 Device lt 265 Semiconductor Group 7 SIEMENS Introduction 1 Introduction The SAB 80C517 80C537 is a high end microcontroller in the Siemens SAB 8051 8 bit microcontroller family It is based on the well known industry standard 8051 architecture a great number of enhancements and new peripheral features extend its capabilities to meet the extensive requirements of new applications Nevertheless the SAB 80C517 maintains compatibility within the Siemens SAB 8051 family in fact the SAB 80C517 is a superset of the Siemens SAB 80C515 80C535 microcontroller thus offering an easy upgrade path for SAB 80 C 515 80 C 535 users In addition to all features of the SAB 80C515 there are several enhancements for higher performance The SAB 80C517 has been expanded e g in its arithmetic characteristics fail save mechanisms analog signal processing facilities and timer capabilities Listed below is a summary of the main features of the SAB 80C517 80C537 8 Kbyte on chip program memory SAB 80C517 only ROMless version also available SAB 806537 Full compatibility with SAB 80C515 80C535 256 byte on chip RAM 256 directly addressable bits 1 microsecond instruction cycle at 12 MHz oscillator frequency 64 of 111 instructions are executed in one instruction cycle External program and data memory expandable up to 64 Kbyte each 8 bit A D converter 1
7. Encoding 1110 0101 direct address Bytes 2 Cycles 1 MOV A is not a valid instruction The content of the accumulator after the execution of this instruction is undefined Semiconductor Group 215 SIEMENS Instruction Set MOV A QRi Operation MOV lt Ri Encoding 1110 011i Bytes 1 Cycles 1 MOV A data Operation MOV lt data Encoding 01110100 immediate data Bytes 2 Cycles 1 MOV Rn A Operation MOV Rn lt A Encoding 11111 i1rrr Bytes 1 Cycles 1 MOV Rn direct Operation MOV Rn direct Encoding 1010 irrr direct address Bytes Cycles 2 Semiconductor Group 216 SIEMENS Instruction Set MOV Rn data Operation MOV Rn lt data Encoding 0111 irrr immediate data Bytes 2 Cycles 1 MOV direct A Operation MOV direct lt A Encoding 1111 0101 direct address Bytes 2 Cycles 1 MOV direct Rn Operation MOV direct Rn Encoding 10001 irrr direct address Bytes Cycles MOV direct direct Operation MOV direct lt direct Encoding 1000 0101 dir addr src dir addr dest Bytes Cycles 2 Semiconductor Group 217 SIEMENS Instruction Set MOV Operation Encoding Bytes Cycl
8. Bit Symbol 211 210 Timer 2 input selection 0 0 No input selected timer 2 stops 0 1 Timer function input frequency 12 T2PS 0 or fosc 24 T2PS 1 1 0 Counter function external input controlled by T2 P1 7 1 1 Gated timer function input controlled by pin T2 P1 7 T2R1 T2RO Timer 2 reload mode selection 0 X Reload disabled 1 0 Mode 0 auto reload upon timer 2 overflow TF2 1 1 Mode 1 reload upon falling edge at pin T2EX P1 5 T2CM Compare mode bit for registers CRC CC1 through CC3 When set compare mode 1 is selected T2CM 0 selects compare mode 0 T2PS Prescaler select bit When set timer 2 is clocked in the timer or gated timer function with 1 24 of the oscillator frequency T2PS 0 gates foso 12 to timer 2 T2PS must be 0 for the counter operation of timer 2 Semiconductor Group 100 SIEMENS On Chip Peripheral Components 7 5 2 Compare Timer This timer the fourth timer in the SAB 80C517 is implemented to function as a fast 16 bit time base for the compare registers to CM7 The compare timer combine with the CMx registers can be employed as high speed output unit or as a fast 16 bit pulse width modulator unit For this case every CMx register assigned to the compare timer automatically operates in compare mode 0 a compare timer overflow sets the corresponding output line at port 4 to low level a compare match pulls the pin high again see also section
9. Figure 7 32 Timing Diagram of an A D Converter Semiconductor Group 92 SIEMENS On Chip Peripheral Components 7 5 The Compare Capture Unit CCU The compare capture unit is one of the SAB 80C517 s most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation pulse width modulation pulse width measuring etc The CCU consists of two 16 bit timer counters with automatic reload feature and an array of 13 compare or compare capture registers A set of six control registers is used for flexible adapting of the CCU to a wide variety of user s applications The CCU is the ideal peripheral for various automotive control applications ignition injection control anti lock brakes etc as well as for industrial applications DC three phase AC and stepper motor control frequency generation digital to analog conversion process control etc The detailed description in the following sections refers to the CCU s functional blocks as listed below Timer 2 with 12 input clock 2 bit prescaler 4 bit prescaler SAB 80C517 identification mark BB or later 16 bit reload counter gated timer mode and overflow interrupt request Compare timer with fosc 2 input clock 8 bit prescaler 16 bit reload and overflow interrupt request Compare reload capture register array consisting of four different kinds of registers one 16 bit compare reload capture
10. Semiconductor Group 37 SIEMENS System Reset 6 1 2 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active low level at pin 10 the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all soecial function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is not performed if there is no clock available at the device This can be avoided using the oscillator watchdog which provides an auxiliary clock for performing a correct reset without clock at the XTAL1 and XTAL2 pins See section 7 8 for further details The RESET signal must be active for at least two machine cycles after this time the SAB 80C517 remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 6 2 shows this timing for a configuration with EA 0 external program memory Thus between the release of
11. Using timer 1 to generate baud rates In mode 1 and 3 of serial channel 0 timer 1 can be used for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows SMOD Mode 1 3 baud rate 32 x timer 1 overflow rate The timer 1 interrupt is usually disabled in this application The timer itself can be configured for either timer or counter operation and in any of its operating modes In the most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010p In the case the baud rate is given by the formula 25 0 x oscillator frequency 32 x 12 x 256 TH1 Mode 1 3 baud rate One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001 p and using the timer 1 interrupt for a 16 bit software reload Table 7 4 lists various commonly used baud rates and shows how they can be obtained from timer 1 Semiconductor Group 56 SIEMENS On Chip Peripheral Components Table 7 4 Timer 1 Generated Commonly Used Baud Rates Baud Rate fosc MHz SMOD Timer 1 C T Mode Reload Value Mode 1 3 62 5 Kbaud 12 0 1 0 2 19 2 Kbaud 11 059 1 0 2 FDH 9 6 Kbaud 11 059 0 0 2 FDH 4 8 Kbaud 11 059 0 0 2 2 4 Kbaud 11 059 0 0 2 1 2 Kbaud 11 059 0 0 2 E8H 110 Baud 6 0 0 0 2 72H 110 Ba
12. Idle mode The CPU is gated off from the oscillator All peripherals are still provided with the clock and are able to work Power down mode Operation of the SAB 80C517 is completely stopped the oscillator is turned off This mode is used to save the contents of the internal RAM with a very low standby current Slow down mode The controller keeps up the full operating functionality but its normal clock frequency is internally divided by eight This slows down all parts of the controller the CPU and all peripherals to 1 8th of their normal operating frequency Slowing down the frequency greatly reduces power consumption All of these modes a detailed description of each is given in the following sections are entered by software Special function register PCON power control register see figure 7 57 is used to select one of these modes These power saving modes especially the power down mode replace the hardware power down supply for the internal RAM via a dedicated pin as itis common with NMOS microcontrollers During the power saving modes the power supply for the SAB 80C517 is again via all pins There is no further dedicated pin for power down supply For the SAB 80C517 several provisions have been made to quality it for both electrically noisy environments and applications requiring high system security In such applications unintentional entering of the power saving modes must be absolutely avoided A power sav
13. CR RUN 8 2 Fundamental Structure uulelleele esses 10 3 Central Processing Unit 13 3 1 General Description eua ot door Gag eer cen os deb GN ae ba AR ud 13 3 2 A MMI anch 14 4 Memory Organization 16 4 1 Program MeMO ida e irte cy TERES RA EE REPERI ERR SR eS 16 4 2 Data soi praece Cea Se d a DEN soto gen PE SUERTE MAE 16 4 3 General Purpose Registers 20 4 4 Special Function Registers i oq or pre scr e E uo 20 5 External Bus Interface corto er 27 5 1 Accessing External 27 5 2 Eight Datapointers for Faster External Bus Access 29 5 3 PSEN Program Store Enable 33 5 4 ALE Address Latch Enable 33 5 5 Overlapping External Data and Program Memory Spaces 33 6 System RESO oneni une 35 6 1 Hardware Reset and Power Up 35 6 1 1 eset Function and 35 6 1 2 Hardware Reset Timing 38 6 2 Reset Output 39 7 On Chip Peripheral Components 40 7 1 Parallell Ou orate a whee a we hae PE E UE Eu E a
14. Intel Corporation 1980 Semiconductor Group 177 SIEMENS Instruction Set ACALL addr11 Function Description Example Operation Encoding Bytes Cycles Absolute call ACALL unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the stack pointer twice The destination address is obtained by successively concatenating the five high order bits of the incremented PC op code bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL No flags are affected Initially SP equals 074 The label SUBRTN is at program memory location 0345 After executing the instruction ACALL SUBRTN at location 01234 SP will contain 094 internal RAM location 084 and 09 will contain 25 and 014 respectively and the PC will contain 0345 ACALL lt PC 2 SP lt SP 1 lt 7 0 SP lt SP 1 SP lt PC15 8 PC10 0 lt page address 10 a9 a8 1 000 1 a5 a4 a3 a2 al ad Semiconductor Group 178 SIEMENS Instruction Set ADD A lt src byte gt Function Add Description ADD adds the byte variable
15. Note that for an alternate input function the port bit latch has to be programmed with a 1 For bit latches of port pins that are used as compare outputs the value to be written to the bit latches depends on the compare mode established A list of all special function registers concerned with the CCU is given in table 7 9 CTREL Internal Bus 16 bit Reload Compare Timer 8x 16 bit Compare Max Clockz fgsc 2 Max Clock fog 12 copt Comp 3 663 69 16 bit Rel Capt CRC gt Comp P r e 5 r MCB01577 Figure 7 33 Block Diagram of the CCU Semiconductor Group 94 SIEMENS On Chip Peripheral Components Table 7 8 Alternate Port Functions of the CCU Pin Symbol Pin Alternate Function No P5 0 CCMO 68 Concurrent compare 0 P5 1 CCM1 67 Concurrent compare 1 P5 2 CCM2 66 Concurrent compare 2 P5 3 CCM3 65 Concurrent compare 3 P5 4 CCM4 64 Concurrent compare 4 P5 5 CCM5 63 Concurrent compare 5 P5 6 CCM6 62 Concurrent compare 6 P5 7 CCM7 61 Concurrent compare 7 P4 7 CM7 9 Comp output for the CM7 reg P4 6 CM6 8 Comp output for the CM6 reg P4 5 CM5 7 Comp output for the CM5 reg P4 4 CM4 6 Comp output for the CM4 reg P4 3 CM3 5 Comp output for the CM3 reg P4 2 CM2 3 Comp output for the CM2 reg P4 1 CM1 2 Comp output for the CM1 reg P4 0 CMO 1 Comp out
16. MOV A Rn Move register to accumulator 1 1 MOV A direct 1 Move direct byte to accumulator 2 1 MOV A Ri Move indirect RAM to accumulator 1 1 MOV A data Move immediate data to accumulator 2 1 MOV Rn A Move accumulator to register 1 1 MOV Rngirect Move direct byte to register 2 2 MOV Rn data Move immediate data to register 2 1 MOV direct A Move accumulator to direct byte 2 1 MOV direct Rn Move register to direct byte 2 2 MOV direct direct Move direct byte to direct byte 3 2 MOV direct Ri Move indirect RAM to direct byte 2 2 MOV direct data Move immediate data to direct byte 3 2 MOV Ri A Move accumulator to indirect RAM 1 1 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate data to indirect RAM 2 1 MOV DPTR data16 Load data pointer with a 16 bit constant 3 2 MOVC A A DPTR Move code byte relative to DPTR to accumulator 1 2 MOVC A A Move code byte relative to PC to accumulator 1 2 MOVX A Ri Move external RAM 8 bit addr to A 1 2 MOVX A DPTR Move external RAM 16 bit addr to A 1 2 MOVX Ri A Move A to external RAM 8 bit addr 1 2 MOVX Move A to external RAM 16 bit addr 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 A Rn Exchange register with accumulator 1 1 A direct Exchange direct byte with accumulator 2 1 XCH A Ri Exchange indirect RAM with accumulator 1 1 XCHD A Ri Exchange low order nibble indir RAM with A 1
17. Port 6 XTAL1 8 bit XTAL2 MCL00776 Logic Symbol Semiconductor Group 267 SIEMENS SAB 80C517 80C537 VacND P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 P3 0 SAB P3 1 P39 80C517 80C537 P3 3 P3 4 P3 5 P3 6 P3 7 P1 7 P1 6 P1 5 P1 4 P6 4 P6 3 P6 2 P6 1 P6 0 OWE P5 0 P5 1 P5 2 5 3 5 4 5 5 P5 6 5 7 Vss P0 7 6 P0 5 P0 4 P0 3 P0 2 MCP00775 Pin Configuration P LCC 84 Semiconductor Group 268 SIEMENS SAB 80C517 80C537 o gt lt eS M Qa ac E amp RR BR BR KKK Z ZaZaaaaaqdkaa ESSE ee eR ie el SEHE IT CC4 INT2 P1 4 7 7 VAGND N C VAREF N C N C N C N C CC3 INT6 P1 3 N C CC2 INT5 P1 2 N C CC1 INT4 P1 1 RESET CCO INT3 P1 0 P4 7 CM7 Vss P4 6 CM6 Vec P4 5 CM5 XTAL2 P4 4 CM4 XTAL1 P4 3 CM3 P2 0 PE SWD P2 1 P4 2 CM2 p2 2 SAB 80C517 80C537 P4 1 CMf P2 3 P4 0 CMO P2 4 Voc P2 5 Ves P2 6 RO 2 7 P8 3 PSEN 8 2 ALE P8 1 EA P8 0 N C P6 7 P0 0 P6 6 P0 1 P6 5 N C N C N C N C P0 2 N C LJ LJ LJ LJ EJ EJ EJ EJ EJ LJ LJ LJ LJ LJ LJ LH HI ELI LJ no ley IO LO iO iO 10 6 d dq do do a amp a aa cnmaaaanaanmraoaaonran Ae SOR OSS NNI DR aO lt 88858828 DES
18. lt A Ri Encoding 001110111 Bytes 1 Cycles 1 ADDC A data Operation ADDC lt A C data Encoding 00110100 Bytes 2 Cycles 1 Semiconductor Group immediate data 182 SIEMENS Instruction Set AJMP addr11 Function Description Example Operation Encoding Bytes Cycles Absolute jump AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice op code bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP The label JMPADR is at program memory location 01234 The instruction AJMP JMPADR is at location 03454 and will load the PC with 0123y AJM P PC PC 2 PC10 0 lt page address 10 a9 a8 0 0001 a5 a4 a3 a2 al ad Semiconductor Group 183 SIEMENS Instruction Set ANL lt dest byte gt lt src byte gt Function Logical AND for byte variables Description performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode combinations When the destination
19. or 000011016 and the value 17 114 or 00010001 p in B since 251 13 18 17 Carry and OV will both be cleared DIV A15 8 B7 0 lt A B 1000 0100 Semiconductor Group 199 SIEMENS Instruction Set DJNZ lt byte gt lt rel addr gt Function Description Example Decrement and jump if not zero DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of 00 will underflow to OFFy No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Internal RAM locations 404 504 and contain the values 1 70 and 15 respectively The instruction sequence DJNZ 40H LABEL 1 DJNZ 50H LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at label LABEL 2 with the values 004 and 154 in the three RAM locations The first jump was nottaken because the result was zero This instruction provides a simple way of executing a program loop a given number of times
20. ter MCP02150 Pin Configuration P MQFP 100 2 Semiconductor Group 269 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions Symbol Pin Number P LCC 84 100 2 Function P4 0 P4 7 1 3 5 9 64 66 68 72 Port 4 is a bidirectional I O port with internal pull up resistors Port 4 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 4 pins being externally pulled low will source current in the DC characteristics because of the internal pull up resistors This port also serves alternate compare functions The secondary functions are assigned to the pins of port 4 as follows CMO 4 0 CM1 P4 1 CM2 P4 2 Compare Channel 2 Compare Channel 0 P4 2 CM3 P4 3 Compare Channel 3 P4 4 P4 5 P4 6 Compare Channel 1 CM4 P4 4 Compare Channel 4 CM5 P4 5 Compare Channel 5 CM6 P4 6 Compare Channel 6 CM7 P4 7 Compare Channel 7 PE SWD 4 67 Power saving modes enable Start Watchdog Timer A low level on this pin allows the software to enter the power down idle and slow down mode In case the low level is also seen during reset the watchdog timer function is off on default Use of the software controlled power saving modes is blocked when this pin is held on high level A
21. 0 ns after PSEN Input instruction float 43 toLcL 20 ns after PSEN Address valid after PXAV 55 8 ns PSEN Address to valid instr tayiy 198 0 115 ins Address float to PSEN tazp 0 0 ns Interfacing the SAB 80C517 to devices with float times up to 55 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 315 SIEMENS SAB 80C517 80C537 AC Characteristics cont d Parameter Symbol Limit Values Unit 16 MHz Clock Variable Clock 1 t 3 5 MHzto 16 MHz min max min max External Data Memory Characteristics RD pulse width RLRH 275 100 ns WR pulse width 275 100 ns Address hold after ALE 1 Axo 90 214 35 ns RD to valid data in 148 165 ns Data hold after RD fRHDX 0 0 ns Data float after RD tRHDZ 55 214 70 Ins ALE to valid data fLLDV 350 815 0 150 ins Address to valid data tAypy 398 165 ins ALE to WR or RD fU WI 138 238 50 50 WR RD high to ALE 23 103 40 40 ns high Address valid to WR tAVWL 120 4 130 ns Data valid to WR tavwx 13 50 ns transi
22. 127 7F y A S A cratch Pad Area 30H 2FH 77 75 2EH 6F 6D 20H 67 65 2CH 5F 50 2By 57 55 2AH AF 40 29H 47 46 45 28H 3c 3B 3A 39 38 274 26H 25H 26 25 24H 23H 22H 21H 20H 1FH 18 17H FH MCA01818 Figure 4 3 Mapping of the Lower Portion of the Internal Data Memory Semiconductor Group 19 SIEMENS Memory Organization 4 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word PSW 3 and PSW 4 select the active register bank see description of the PSW This allows fast context switching which is useful when entering subroutines or interrupt service routines ASM51 and the device SAB 80C517 default to register bank 0 The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction of code indicates which register is to be used For indirect addressing RO and Ri are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the stack pointer to location 074 and increments it once to start from location 08H which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank th
23. 2 1 0 pointer DPTR 0 DPTRO 0 0 1 DPTR 1 1 DPTR 2 DPH 83 DPL 82 1 1 DPTR 3 1 DPTR 4 0 1 DPTR 5 External Data Memory 1 1 0 DPTR 6 MCODO779 1 1 1 Figure 3 Addressing of External Data Memory Semiconductor Group 282 SIEMENS SAB 80C517 80C537 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The 81 special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area The special function registers are listed in table 1 In this table they are organized in groups which refer to the functional blocks of the SAB 80C517 Block names and symbols are listed in alphabetical order Table 1 Special Function Register Address Register Name Register Contents after Reset CPU ACC Accumulator OEO 00 B B Register OFO 00 DPH Data Pointer High Byte 8 004 DPL Data Pointer Low Byte 824 00H DPSEL Data Pointer Select Register 924 XXXX X000g 3 PSW Program Status Word Register ODO 00 SP Stack Pointer 814 074 A D ADCONO A D Converter Control Register O 00857 00 Converter ADCON1 A D Converter Control Register 1 XXXX 0000g 3 ADDAT A D Converter Data Register 9 004 DAPR D AConver
24. Circuitry To Interrupt CTF OP i Circuitry Overflow MCB00783 Figure 7 Block Diagram of the Compare Timer Semiconductor Group 293 SIEMENS SAB 80C517 80C537 BEEN Overflow gt Compare Timer 7 Output Comparator Circuit 4 Compare Latch CTF MCA00784 Compare Register CMx Figure 8 Compare Mode 0 with Registers CMO to CM7 Semiconductor Group 294 SIEMENS SAB 80C517 80C537 Interrupt Structure The SAB 80C517 has 14 interrupt vectors with the following vector addresses and request flags Table 4 Interrupt Sources and Vectors Source Request Flags Vector Address Vector 0003 External interrupt 0 TFO 000 Timer 0 overflow IE1 0013 External interrupt 1 TF1 001By Timer 1 overflow RIO TIO 00234 Serial channel 0 TF2 EXF2 002By Timer 2 overflow ext reload IADC 00434 A D converter IEX2 004By External interrupt 2 IEX3 00534 External interrupt 3 IEX4 005 External interrupt 4 IEX5 0063 External interrupt 5 IEX6 006 External interrupt 6 0083 Serial channel 1 CTF 009Bj Compare timer overflow Each interrupt vector can be individually enabled disabled The response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles External interrupts O and 1 can be activated by a low level or a negative transition selectable at their corresponding input pin external inter
25. Encoding 1010 0010 bit address Bytes 2 Cycles 1 MOV bit C Operation MOV bit lt C Encoding 1001 0010 bit address Bytes Cycles 2 Semiconductor Group 220 SIEMENS Instruction Set MOV DPTR data16 Function Load data pointer with a 16 bit constant Description data pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once Example The instruction MOV DPTR 1234H will load the value 1234 into the data pointer will hold 124 and DPL will hold 34H Operation MOV DPTR lt data15 0 DPH O DPL lt data15 8 O data7 0 Encoding 1001 0000 immed data 15 8 immed data 7 0 Bytes Cycles Semiconductor Group 221 SIEMENS Instruction Set MOVC A A lt base reg gt Function Description Example Move code byte The MOVC instructions load the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit accumulator contents and the contents of a sixteen bit base register which may be either the data pointer or the PC In the latter case the PC is incremented to the address of the following instr
26. Example The label is assigned to the instruction at program memory location 12344 The instruction LUMP at location 01234 will load the program counter with 12344 Operation LUMP lt addr15 0 Encoding 00000010 addr15 addr8 addr7 Bytes Cycles Semiconductor Group 214 SIEMENS Instruction Set MOV lt dest byte gt lt src byte gt Function Move byte variable Description The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Example Internal RAM location 304 holds 404 The value of RAM location 404 is 104 The data present at input port 1 is 11001010B 0 MOV RO 30H lt MOV RO A lt 40H MOV R1 A R1 lt 40H MOV B 1 B lt 10H MOV R1 P1 RAM 40H lt MOV 2 1 2 lt 0 leaves the value 30 in register 0 40H in both the accumulator and register 1 10H in register B and 11001010p both in RAM location 404 and output on port 2 MOV A Rn Operation MOV A lt Rn Encoding 1110 1 Bytes 1 Cycles 1 MOV A direct Operation MOV A lt direct
27. If ET2 0 the timer 2 interrupt is disabled EAL Enables or disables all interrupts If EAL 0 no interrupt will be acknowledged If EAL 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit Semiconductor Group 155 SIEMENS Interrupt System Figure 8 3 Special Function Register IEN1 Address 0 8 OBDYy OBC OBBy 0B9j OB8y OB8y EXEN2 EX6 EX5 EX4 EX3 EX IEN1 This bit is not used for interrupt control Bit Function EADC Enables or disables the A D converter interrupt If EADC 0 the A D converter interrupt is disabled EX2 Enables or disables external interrupt 2 capture compare interrupt 4 If EX2 0 external interrupt 2 is disabled Enables or disables external interrupt 3 capture compare interrupt 0 If EX3 0 external interrupt 3 is disabled EX4 Enables or disables external interrupt 4 capture compare interrupt 1 If EX4 0 external interrupt 4 is disabled EX5 Enables or disables external interrupt 5 capture compare interrupt 2 If EX5 0 external interrupt 5 is disabled EX6 Enables or disables external interrupt 6 capture compare interrupt 3 If EX6 0 external interrupt 6 is disabled EXEN2 Exables or disables the timer 2 external reload interrupt EXEN2 0 disables the timer 2 external reload interrupt The external reload function is
28. XTAL1 Output of the inverting oscillator amplifier To drive the device from an external clock source XTAL2 should be driven while XTAL1 is left unconnected There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is devided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 41 48 14 21 I O Port 2 is a bidirectional I O port with internal pull up resistors Port 2 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as in puts As inputs port 2 pins being externally pulled low will source current Z in the DC characteristics because of the internal pull up resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull up resistors when issuing 1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register Input Output Semiconductor Group 274 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 Functi
29. 6 0 ADST ViNTAREF VINTAGND VAREF VAGND D A Converter 5 4 3 2 Write to DAPR DAPR DAj Internal V A Shaded areas are not used in ADC functions MCB00780 Figure 4 Block Diagram A D Converter Semiconductor Group 288 80 517 80 537 SIEMENS Compare Capture Unit CCU The compare capture unit is a complex timer register array for applications that require high speed I O pulse width modulation and more timer counter capabilities The CCU contains one 16 bit timer counter timer 2 with 2 bit prescaler reload capability and a max clock frequency of 12 1 MHz with a 12 MHz crystal one 16 bit timer compare timer with 8 bit prescaler reload capability and a max clock frequency of fosc 2 6 MHz with a 12 MHz crystal thirteen 16 bit compare registers five of which can be used as 16 bit capture registers up to 21 output lines controlled by the CCU seven interrupts which can be generated by CCU events Figure 5 shows a block diagram of the CCU Eight compare registers CMO to CM7 can individually be assigned to either timer 2 or the compare timer Diagrams of the two timers are shown in figures 6 and 7 The four compare capture registers and the compare reload capture register are always connected to timer 2 Dependent on the register type and the assigned timer two compare modes can be selected Table 3 illustrates possible combinations and t
30. CJNE lt dest byte gt lt src byte gt rel Function Description Example Compare and jump if not equal CJNE compares the magnitudes of the tirst two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The accumulator contains 344 Register 7 contains 564 The first instruction in the sequence CJNE R7 60H NOT EQ POCHE fates R7 60H NOT_EQ JC REQ_LOW If R7 lt 60H T m R7 gt 60H sets the carry flag and branches to the instruction at label NOT EQ By testing the carry flag this instruction determines whether R7 is greater or less than If the data being presented to port 1 is also 344 then the instruction WAIT CJNE A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the accumulator does equal the data read from P1 If some other value was inp
31. Figure 7 38 Port Latch in Compare Mode 0 Semiconductor Group 104 SIEMENS On Chip Peripheral Components Modulation Range of a PWM Signal and Differences between the Two Timer Compare Register Configurations in the CCU There are two timer compare register configurations in the CCU which can operate in compare mode 0 either timer 2 with a CCx CRC and CC1 to CC4 register or the compare timer with a CMx register They basically operate in the same way but show some differences concerning their modulation range when used for PWM Generally it can be said that for every PWM generation with n bit wide compare registers there are 2 different settings for the duty cycle Starting with a constant low level 0 duty cycle as the first setting the maximum possible duty cycle then would be 1 1 2 x 100 96 This means that a variation of the duty cycle from 0 to real 10096 can never be reached if the compare register and timer register have the same length There is always a spike which is as long as the timer clock period In the SAB 80C517 there are two different modulation ranges for the above mentioned two timer compare register combinations The difference is the location of the above spike within the timer period at the end of a timer period or at the beginning plus the end of a timer period Please refer to the description of the relevant timer register combination in section 7 5 5 1 or 7 5 5 2 for details Timer Count FFF
32. Otherwise a static input current might result at the corresponding analog input which will also affect the accuracy of the other input channels 7 4 3 A D Converter Timing A conversion is internally started by writing into special function register DAPR ADEX 0 A write to DAPR will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the busy flag BSY will be set When external start is selected ADEX 1 the conversion starts in the machine cycle following the one where the low level was detected at P6 0 ADST The conversion procedure is divided into three parts Load time f During this time the analog input capacitance see data sheet must be loaded to the analog input voltage level The external analog source needs to be strong enough to source the current to load the analog input capacitance during the load time This causes some restrictions for the impedance of the analog source Sample time fs During this time the internal capacitor array is connected to the selected analog input channel The sample time includes the load time which is described above After the load time has passed the selected analog input must be held constant for the rest of the sample time Otherwise the internal calibration of the comparator circuitry could be affected which might result in a reduced accuracy of the converter However in typical applications a voltage chan
33. Pin EA controls whether program fetches below address 2000 are done from internal or external memory Data Memory The data memory space consists of an internal and an external memory space External Data Memory Up to 64 KByte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing MOVX instructions utilizing registers RO and R1 can be used A 16 bit external memory addressing is supported by eight 16 bit datapointers Multiple Datapointers As a functional enhancement to standard 8051 controllers the SAB 80C517 contains eight 16 bit datapointers The instruction set uses just one of these datapointers at a time The selection of the actual datapointers is done in special function register DPSEL data pointer select addr 924 Figure 3 illustrates the addressing mechanism Internal Data Memory The internal data memory is divided into three physically distinct blocks the lower 128 bytes of RAM including four banks of eight registers each the upper 128 byte of RAM the 128 byte special function register area A mapping of the internal data memory is also shown in figure 2 The overlapping address spaces are accessed by different addressing modes The stack can be located anywhere in the internal data memory Semiconductor Group 281 SIEMENS SAB 80C517 80C537 DPSEL 92 DPTR7 DPSEL Selected Data
34. Semiconductor Group 321 SIEMENS SAB 80C517 80C537 CLKOUT PSEN Programm Memory Access Data Memory Access RD WR MCTO0794 System Clock Timing Semiconductor Group 322 SIEMENS SAB 80C517 80C537 ROM Verification Characteristics 25 5 5 10 Vss OV Parameter Symbol Limit values Unit min max ROM Verification Address to valid data fAVQV 48 tci cL ns ENABLE to valid data t ELQV 48 CLCL ns Data float after ENABLE 1 7 0 48 tci cL ns Oscillator frequency 1 4 6 MHz P1 0 P1 7 hyay Port 0 Data OUT 2 7 ENABLE MCD02453 Address 1 0 1 7 A0 A7 Inputs 2 5 2 6 PSEN Vss P2 0 P2 4 AB A12 ALE EA Data 0 0 7 00 07 RESET Vss ROM Verification For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vo Vo level occurs gt 20 mA Semiconductor Group 323 SIEMENS SAB 80C517 80C537 Recommended Oscillator Circuits 40 40 xui NC 3 5 16 MHz CH 39 External Oscillator 59 MAG Signal 30pF 10pF MCS00796 incl stray capacitance AC Testing 0 2 Voc 0 9V Test Points 0 2V 0 1V 0 45V MCA00697 AC Inputs during testing are driven
35. is a accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 110000116 and register 0 holds 101010105 then the instruction ANL will leave 814 10000001 in the accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run time The instruction ANL P1 01110011p will clear bits 7 3 and 2 of output port 1 ANL A Rn Operation ANL lt A Rn Encoding 01011 Bytes 1 Cycles 1 ANL A direct Operation ANL lt A direct Encoding 010110101 direct address Bytes 2 Cycles 1 Semiconductor Group 184 SIEMENS Instruction Set ANL A Ri Operation ANL lt A Ri Encoding 01010111 Bytes 1 Cycles 1 ANL A data Operation ANL A A data Encoding 01010100 Bytes 2 Cycles 1 ANL direct A Operation ANL direct
36. 1 1 MOV A ACC is not a valid instruction Semiconductor Group 253 SIEMENS Instruction Set Instruction Set Summary cont d Mnemonic Description Byte Cycle Boolean Variable Manipulation CLR C Clear carry flag 1 1 CLR bit Clear direct bit 2 1 SETB C Set carry flag 1 1 SETB bit Set direct bit 2 1 CPL C Complement carry flag 1 1 CPL bit Complement direct bit 2 1 ANL AND direct bit to carry flag 2 2 ANL C bit AND complement of direct bit to carry 2 2 ORL C bit OR direct bit to carry flag 2 2 ORL C bit OR complement of direct bit to carry 2 2 MOV C bit Move direct bit to carry flag 2 1 bit C Move carry flag to direct bit 2 2 Program and Machine Control ACALL addr11 Absolute subroutine call 2 2 LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 Return from interrupt 1 2 AJMP addri1 Absolute jump 2 2 LJMP 16 Long iump 3 2 SJMP Short jump relative addr 2 2 JMP oA DPTR Jump indirect relative to the DPTR 1 2 JZ rel Jump if accumulator is zero 2 2 JNZ rel Jump if accumulator is not zero 2 2 JC rel Jump if carry flag is set 2 2 JNC rel Jump if carry flag is not set 2 2 JB bit rel Jump if direct bit is set 3 2 JNB bit rel Jump if direct bit is not set 3 2 JBC bit rel Jump if direct bit is set and clear bit 3 2 CJNE Agirect rel Compare direct byte t
37. 1 a Interrupt Structure of the SAB 80C517 Semiconductor Group 153 SIEMENS Interrupt System Timer 1 Overflow Compare Timer Overflow EI P1 1 INT4 CC1 IEX 4 ail Receiver Ser Channel 0 Transmitter P1 2 INT5 CC2 Timer 2 Overflow IET 2 P1 5 T2EX P1 3 INT6 CC3 Highest Priority Level Lowest Priority Level 2 5 00107 Q5 07U MCS00786 Figure 8 1 b Interrupt Structure of the 80C517 cont d Semiconductor Group 154 SIEMENS Interrupt System Figure 8 2 Special Function Register IENO Address 0 8 0A8H OAFLy OAC OABY OAM 8 EAL wor 2 eso ET EX1 ETO Exo IENO This bit is not used for interrupt control Bit Function Enables or disables external interrupt 0 If EXO 0 external interrupt 0 is disabled ETO Enables or disables the timer 0 overflow interrupt If ETO 0 the timer 0 interrupt is disabled 1 Enables or disables external interrupt 1 If EX1 0 external interrupt 1 is disabled ET1 Enables or disables the timer 1 overflow interrupt If ET1 0 the timer 1 interrupt is disabled ESO Enables or disables the serial channel 0 interrupt If ESO 0 the serial channel 0 interrupt is disabled ET2 Enables or disables the timer 2 overflow or external reload interrupt
38. 5 CM5 P2 0 P4 6 CM6 P4 7 CM7 P3 0 RxD P3 1 TxD P3 2 INTO P3 3 INTT P3 4 TO P5 0 P5 1 OCM1 P5 2 0CM2 P5 3 OCM3 P5 4 0CM4 P3 5 T1 P5 5 0 5 P5 6 0CM6 PSEN P3 7 RD P3 6 WR P6 0 ADST P6 1 RxD1 P0 7 P6 2 TxD1 P0 6 P6 3 P0 5 P6 4 P0 4 P6 5 PO 3 P6 6 P0 2 P6 7 P0 1 P0 0 P5 7 0 7 EA RESET pr OWE SWD RD vec vss Analog Digital Inputs 1 0 5D 6D 7D 8D MCB01864 Figure 10 4 Connecting the SAB 80C517 with External Program and Data Memory Semiconductor Group 264 SIEMENS High Performance 8 Bit CMOS Single Chip Microcontroller Advanced Information SAB 800517 SAB 806537 Versions for 12 MHz and 16 MHz operating frequency e 8Kx8 ROM SAB 80C517 only 256 x8 on chip RAM Superset of SAB 80C51 architecture 1 us instruction cycle time at 12 MHz 750 ns instruction cycle time at 16 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Four 16 bit timer counters Powerful 16 bit compare capture unit CCU with up to 21 high speed or PWM output channels and 5 capture inputs Versatile fail safe provisions SAB 80C517 80C537 Microcontroller with factory mask programmable ROM Microcontroller for external ROM Fast 32 bit division 16 bit 2 multiplication
39. ADDR OUT valid PCL OUT valid without MOVX with MOVX Figure 5 2 a and b External Program Memory Execution Semiconductor Group SIEMENS System Reset 6 System Reset 6 1 Hardware Reset and Power Up Reset 6 1 1 Reset Function and Circuitries The hardware reset function incorporated in the SAB 80C517 allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode see section 7 7 is to be terminated Additionally to the hardware reset which is applied externally to the SAB 80C517 there are two internal reset sources the watchdog timer and the oscillator watchdog They are described in detail in section 7 8 Fail Save Mechanisms The chapter at hand only deals with the external hardware reset The reset input is an active low input at pin 10 RESET An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held low for at least two machine cycles 24 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle in which RESET is low and is repeated every cycle until RESET goes high again During reset pins ALE and PSEN are configu
40. BD ADCONO 7 This also starts the baud rate timer When Timer1 shall be used for baud rate generation bit BD must be cleared In any case bit SMOD PCON 7 selects an additional divider by two The default values after reset in registers SORELL and SORELH provide a baud rate of 4 8 kBaud with SMOD 0 or 9 6 kBaud with SMOD 1 at 12 MHz oscillator frequency This guarantees full compatibility to older steppings of the SAB 80C517 Timer 1 Overflow Baud Rate Phase 2 CLK Generator j e MSC02223 Figure 7 11b Block Diagram of Baud Rate Generation for Serial Interface 0 If the new baud rate generator is used the baud rate of Serial Channel 0 in Mode 1 and 3 can be determined as follows 25 00 x oscillator frequency 64 x 210 SOREL Mode 1 3 baud rate with SOREL SORELH 1 0 SORELL 7 0 Semiconductor Group 60 SIEMENS On Chip Peripheral Components 7 2 2 Serial Interface 1 7 2 2 1 Operating Modes of Serial Interface 1 The serial interface 1 is an asynchronous channel only and is able to operate in two modes as an 8 bit or 9 bit UART These modes however correspond to the above mentioned modes 1 2 and 3 of serial interface 0 The multiprocessor communication feature is identical with this feature in serial interface 0 The serial interface 1 has its own interrupt request flags and which have dedicated interrupt vector location See section 8 for more details about the inte
41. RAM Ports 1 and 2 are used for normal I O Registers 0 and 1 contain 124 and 344 Location 344 of the external RAM holds the value 564 The instruction sequence MOVX 1 MOVX RO A copies the value 564 into both the accumulator and external RAM location 12 Semiconductor Group 224 Instruction Set MOVX A Ri Operation MOVX lt Ri Encoding 11100011 Bytes 1 Cycles 2 MOVX A DPTR Operation MOVX lt DPTR Encoding 1110 0000 Bytes 1 Cycles 2 MOVX Ri A Operation MOVX Ri lt A Encoding 1111 0011 Bytes 1 Cycles 2 MOVX DPTR A Operation MOVX DPTR Encoding 1111 0000 Bytes 1 Cycles 2 Semiconductor Group 225 SIEMENS Instruction Set MUL AB Function Description Example Operation Encoding Bytes Cycles Multiply MUL AB multiplies the unsigned eight bit integers in the accumulator and register B The low order byte of the sixteen bit product is left in the accumulator and the high order byte in B If the product is greater than 255 OF Fi the overflow flag is set otherwise it is cleared The carry flag is always cleared Originally the accumulator holds the value 80 50 4 Register B holds the value 160 The instruction MUL AB will give the product 12 800 3200p so B is changed to 324 00110010p and the accumulator is cleared The overflow flag is set carry
42. SIEMENS On Chip Peripheral Components se 1 52 53 54 5 56 st 152 3 54 ss se st 52 fee RD WR L CLKOUT MCT01858 Figure 7 69 Timing Diagram System Clock Output Semiconductor Group 151 SIEMENS Interrupt System 8 Interrupt System The SAB 80C517 provides 14 interrupt sources with four priority levels Seven interrupts can be generated by the on chip peripherals i e timer 0 timer 1 timer 2 compare timer serial interfaces 0 and 1 and A D converter and seven interrupts may be triggered externally Short Description of the Interrupt Structure for Advanced SAB 80 C 515 Users The interrupt structure of the SAB 80C517 has been mainly adapted from the SAB 80 C 515 Thus each interrupt source has its dedicated interrupt vector and can be enabled disabled individually there are also four priority levels available In the SAB 80C517 two interrupt sources have been added Compare timer overflow interrupt Receive and transmit interrupt of serial interface 1 In the SAB 80 C 515 the 12 interrupt sources are combined to six pairs each pair can be programmed to one of the four interrupt priority levels In the SAB 80C517 the new interrupt sources were added to two of these pairs thus forming triplets therefore the 14 interrupt sources are combined to six pairs or triplets each pair or triplet can be programmed to one of the four interrupt priori
43. SRC 2 MOV DPL LOW DES PTR 2 MOV DPH HIGH DES PTR 2 Increment destination pointer ex time INC relevant Transfer byte to destination address MOVX QDPTR A 2 Save destination pointer MOV LOW DES PTR DPL 2 MOV HIGH DES PTR DPH 2 Restore old datapointer POP DPH 2 POP DPL 2 Total execution time machine cycles 28 Semiconductor Group 31 SIEMENS External Bus Interface 2 Using Two Datapointers Code for an SAB 80C517 Initialization Routine Action Code Initialize DPTR6 with source pointer MOV DPSEL 06H MOV DPTR 1FFFH Initialize DPTR7 with destination pointer MOV DPSEL 07H MOV DPTR 2FA0H Table Look up Routine under Real Time Conditions Action Code Machine Cycles Save old source pointer PUSH DPSEL 2 Load source pointer MOV DPSEL 06H 2 Increment and check for end of table INC DPTR execution time not relevant for this CJNE consideration sed Fetch source data byte from ROM table MOVC A DPTR Save source_pointer and load MOV DPSEL 07H destination pointer Transfer byte to destination address MOVX QDPTR A Save destination pointer and restore old POP DPSEL datapointer Total execution time machine cycles 12 The above example shows that utilization of the SAB 80C517 s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here fou
44. The external interrupts 4 INTA 5 INT5 6 INT6 are positive transition activated The flags that actually generate these interrupts are bits IEX4 IEX5 and IEX6 in register IRCON see figure 8 7 In addition these flags will be set if a compare event occurs at the corresponding output pin P1 1 INT4 CC1 P1 2 INT5 CC2 and P1 3 INT6 CC3 regardless of the compare mode established and the transition at the respective pin When an interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored too The compare timer interrupt is generated by bit CTF in register CTCON see figure 8 8 which is set by arollover in the compare timer If a compare timer interrupt is generated flag CTF will have to be cleared by software Semiconductor Group 159 SIEMENS Interrupt System Figure 8 7 Special Function Register IRCON Address 0C0 0 7 0 6 OCS O0C4 0 3 0C24 1 OCOY 0 EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCON Bit Function IADC A D converter interrupt request flag Set by hardware at the end of a conversion Must be cleared by software IEX2 External interrupt 2 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 4 INT2 CC4 Cleared when interrupt is initiated IEX3 External interrupt 3 edge flag Set by hardware when external interrup
45. an access to external data memory when RD WR signals are active The first ALE of the second cycle of a MOVX instruction is missing see figure 5 2 b Consequently in any system that does not use data memory ALE is activated at a constant rate of 1 6 of the oscillator frequency and can be used for external clocking or timing purposes 5 5 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the SAB 80C517 the external program and data memory spaces can be combined by AND ing PSEN and RD A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 33 SIEMENS External Bus Interface b ALE PSEN RD P2 ALE PSEN RD P2 lt One Machine Cycle One Machine Cycle 1 s2 s3 s4 s5 s6 s1 S2 3 S4 5 s6 Bldg TL E PCH OUT OUT OUT OUT OUT PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid 4 One Machine Cycle One Machine Cycle 1 s2 s3 s4 s5 56 s1 s2 s3 s4 s5 56 PCH OUT OUT 2 OUT OUT OUT IN A A A PCL OUT valid MCS02094
46. are given mA and measured at 5 V see also notes 4 and 5 7 The output impedance of the analog source must be low enough to assure full loading of the sample capacitance during load time After charging of the internal capacitance in the load time 7 the analog input must be held constant for the rest of the sample time Ts 8 The differential impedance Rp of the analog reference voltage source must be less than 1 at reference supply voltage co Exceeding the limit values at one or more input channels will cause additional current which is sinked sourced at these channels This may also affect the accuracy of other channels which are operated within the specification 10 Only valid for not selected analog inputs 11 No missing code Semiconductor Group 311 SIEMENS SAB 80C517 80C537 0 2 Vog 0 1V MCT00793 Clock of Waveform for Tests in Active Idle Mode and Slow Down Mode Semiconductor Group 312 SIEMENS SAB 80C517 80C537 AC Characteristics Voc 5 10 0 VTA Oto 70 C for the SAB 80C517 83C537 T a 40 to 85 C for the SAB 80C517 83C537 T40 85 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit Values Unit 12 MHz Clock Variable Clock 1 t 3 5 MHz to 12 MHz min max min max Program Memory C
47. are multifunctional as they additionally provide a capture see section 7 5 6 ora reload capability the CRC register only see section 7 5 1 A general selection of the function is done in register CCEN see figure 7 41 For compare function they can be used in compare mode 0 or 1 respectively The compare mode is selected by setting or clearing bit T2CM in special function register T2CON Semiconductor Group 108 SIEMENS On Chip Peripheral Components Figure 7 41 Special Function Register CCEN COCAHS COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAHO COCALO CCEN Compare capture enable register selects compare or capture function for register CRC CC1 to Bit Function COCAHO COCALO Compare capture mode for CRC register 0 0 Compare capture disabled 0 1 Capture on falling rising edge at pin P1 0 INT3 CCO 1 0 Compare enabled 1 1 Capture on write operation into register CRCL COCAH1 COCAL1 Compare capture mode for CC register 1 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 1 INT4 CC1 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 COCAH2 COCAL2 Compare capture mode for CC register 2 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 2 INT5 CC2 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 COCAH3 COCAL3 Compare capture mode for CC register 3 0 0 Compare capture disabled
48. be cleared after having been set and the value shown when reading one of these bits is always zero 0 Figure 7 57 shows the special function register PCON This double instruction sequence is implemented to minimize the chance of unintentional entering the power down mode which could possibly freeze the chip s activity in an undesired status Note that PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is composed of byte handling instructions The following instruction sequence may serve as an example ORL PCON 00000010B Set bit PDE bit PDS must not be set ORL PCON 01000000B Set bit PDS PDE must not be set The instruction that sets bit PDS is the last instruction executed before going into power down mode If idle mode and power down mode are invoked simultaneously the power down mode takes precedence The only exit from power down mode is a hardware reset Reset will redefine all SFR S but will not change the contents of the internal RAM In the power down mode can be reduced to minimize power consumption Care must be taken however to ensure that is not reduced before the power down mode is invoked and that is restored to its normal operating level before the power down mode is terminated The reset signal that terminates the power down mode also frees the oscillator The reset should not be activated before is restored to its norma
49. capture register by bits in SFR CCEN compare capture enable register and CC4EN compare capture 4 enable register That means in contrast to the compare modes it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register The bit positions and functions of CCEN are listed in figure 7 41 the one for CC4EN in figure 7 47 Semiconductor Group 124 SIEMENS On Chip Peripheral Components Input _ 2 Clodi m L2 TH2 TF2 Interrupt Request Write to Iv Iv gt 1 Capture P1 0 INT3 CRCL CRCH CC o e 7 126046 EM LL External Pd gt IEX3 Interrupt 3 Request 01855 Figure 7 53 Capture with Registers CRC CC4 Timer 2 Interrupt Request Write to P1 1 INT4 External CC1 Interrupt 4 Request MCS01856 Figure 7 54 Capture with Registers CC1 to CC3 Semiconductor Group 125 SIEMENS On Chip Peripheral Components 7 6 Arithmetic Unit This on chip arithmetic unit of the SAB 80C517 provides fast 32 bit division 16 bit multiplication as well as shift and normalize features All operations are unsigned integer operations The arithmetic unit further on also called MDU for Multiplication Division Unit has been integrated to support the 8051 core of the SAB 80C517 in real time control applications It can increase the execution speed of math intensive softwar
50. cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higher priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IENO IEN1 IEN2 or IPO IP1 the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 168 SIEMENS Instruction Set 9 Instruction Set The SAB 80C517 instruction set includes 111 instructions 49 of which are single byte 45 two byte an
51. data memory 256 bytes of internal data memory 128 byte special function register area 4 1 Program Memory The program memory of the SAB 80C517 consists of an internal and an external memory portion see figure 4 1 8 Kbytes of program memory may reside on chip SAB 80C517 only while the SAB 80C537 has no internal ROM The program memory can be externally expanded up to 64 Kbyte If the EA pin is held high the 80C517 executes out of the internal program memory unless the address exceeds 1 FFF Locations 20004 through OFFFFy are then fetched from the external program memory If the EA pin is held low the SAB 80C517 fetches all instructions from the external program memory Since the SAB 80C537 has no internal program memory pin EA must be tied low when using this device In either case the 16 bit program counter is the addressing mechanism Locations 034 through in the program memory are used by interrupt service routines 4 2 Data Memory The data memory address space consists of an internal and an external memory portion Internal Data Memory The internal data memory address space is divided into three physically separate and distinct blocks the lower 128 byte of RAM the upper RAM area and the 128 byte special function register SFR area see figure 4 2 While the latter SFR area and the upper RAM area share the same address locations they must be accessed through different addressing modes The map in f
52. division 16 bit multiplication as well as shift and normalize features All operations are integer operations Operation Result Remainder Execution Time 32 bit 16 bit 32 bit 16 bit 6 toy 16 bit 16 bit 16 bit 16 bit 41 cy 16 bit 16 bit 32 bit 4 toy 32 bit normalize 6 toy 32 bit shift left right 6 t y U 4 1 us 12 MHz oscillator frequency 2 maximal shift speed is 6 shifts cycle The MDU consists of six registers used for operands and results and one control register Operation of the MDU can be divided in three phases 1st Write MDO Last Write MD5 or ARCON First Read Last Read MD0 MD3 or MD5 v v Phase 1 X Phase 2 3 Load Registers Calculate Read Registers limes ag 00787 10 Operation of the MDU To start an operation register MDO to MD5 or ARCON must be written to in a certain sequence according to table 5 or 6 The order the registers are accessed determines the type of the operation A shift operation is started by a final write operation to register ARCON see also the register description Semiconductor Group 298 SIEMENS SAB 80C517 80C537 Table 5 Programming the MDU for Multiplication and Division Operation 32 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit First Write D endL MDO D endL MDO M andL MD1 D end MD1 D end MD4 M orL MD2 D e
53. functions implemented in the SAB 80 C 515 can also be used in the SAB 80C517 Furthermore the SAB 80C517 has nine further compare registers and an additional 16 bit timer thus providing a high flexibility in assigning compare registers to timers and output lines Table 7 10 shows possible configurations of the CCU and the corresponding compare modes which can be selected The following sections describe the function of these configurations Semiconductor Group 107 SIEMENS On Chip Peripheral Components Table 7 10 CCU Configurations Assigned Compare Compare Output at Possible Modes Timer Register Timer 2 CRCH CRCL P1 0 INT3 CCO Comp mode 0 1 Reload CCH1 CCL1 P1 1 INT4 CC1 Comp mode 0 1 CCH2 CCL2 P1 2 INT5 CC2 Comp mode 0 1 CCHS CCLS3 P1 3 INT6 CC3 Comp mode 0 1 CCH4 CCL4_ P1 4 INT2 CC4 Comp mode 0 1 CCH4 CCL4 P5 0 CCMO Comp mode 1 CCH4 CCL4 P5 7 CCM7 Comp mode 1 CMHO CMLO P4 0 CMO Comp mode 1 CMH7 CML7 P4 7 CM7 Comp mode 1 Compare CMHO CMLO 4 0 Comp mode 0 with shadow latches timer CMH7 CML7 4 7 7 Comp mode 0 with shadow latches 7 5 5 1 Compare Function of Timer 2 with Registers CRC CC1 to CC4 Compare Function of Registers CRC CC1 to CC3 The compare function of registers CRC CC1 to CC3 is completely compatible with the corresponding function of the SAB 80 C 515 Registers CRC CC1 to CC3 are permanently connected to timer 2 All four registers
54. high level during reset performs an automatic start of the watchdog timer immediately after reset When left unconnected this pin is pulled high by a weak internal pull up resistor Input Output Semiconductor Group 270 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number 10 P LCC 84 P MQFP 100 2 Function RESET 10 73 RESET A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517 A small internal pull up resistor permits power on reset using only a capacitor connected to VAREF 11 78 Reference voltage for the A D con verter VAGND 12 79 Reference ground for the A D converter P7 7 P7 0 13 20 80 87 Port 7 is an 8 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the lower 8 bit of the multiplexed analog inputs of the A D converter simultaneously Input Output Semiconductor Group 271 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number VO Function P LCC 84 P MQFP 100 2 P3 0 P3 7 21 28 90 97 VO 3 is a bidirectional I O port with internal pull up resistors Port 3 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that s
55. idle mode Note that PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is to be done by byte handling instructions Semiconductor Group 137 SIEMENS On Chip Peripheral Components The following instruction sequence may serve as an exemple ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode Terminating the Idle Mode The idle mode can be terminated by activation of any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the instruction will be the one following the instruction that set the bit IDLS The other possibility of terminating the idle mode is a hardware reset Since the oscillator is still running the hardware reset is held active for only two machine cycles for a complete reset Figure 7 57 Special Function Register PCON Address 87 87H PDS IDLS SD GF1 GFO PDE IDLE PCON These bits not used in controlling the power saving modes Bit Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS IDLE start bit The instruction that sets the IDSL flag
56. if the first byte still has not been read by the time reception of the second byte is complete the last received byte will be lost The serial channel 0 is completely compatible with the serial channel of the SAB 80 C 51 Serial channel 1 has the same functionality in its asynchronous modes but the synchronous mode is lacking 7 2 1 Serial Interface 0 7 2 1 1 Operating Modes of Serial Interface 0 The serial interface 0 can operate in four modes one synchronous mode three asynchronous modes The baud rate clock for this interface is derived from the oscillator frequency mode 0 2 or generated either by timer 1 or by a dedicated baud rate generator mode 1 3 A more detailed description of how to set the baud rate will follow in section 7 2 1 3 Mode 0 Shift register synchronous mode Serial data enters and exits through RXDO TxDO outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator frequency Mode 1 8 bit UART variable baud rate 10 bits are transmitted through TxDO or received through RxD0O a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB80 in special function register SOCON The baud rate is variable Mode 2 9 bit UART fixed baud rate 11 bits are transmitted through TxDO or received through RxD0O a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On tr
57. ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency Mode 3 9 bit UART variable baud rate 11 bit are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable Variable Baud Rates for Serial Interface 0 Variable baud rates for modes 1 and 3 of serial interface 0 can be derived from either timer 1 or from the oscillator via a special prescaler BD Timer 1 may be operated in mode 1 to generate slow baud rates or mode 2 The dedicated baud rate generator BD provides the two standard baud rates 4800 or 9600 baud with 0 16 deviation Table 8 shows possible configurations and the according baud rates SAB 80C517 devices with stepping code CA or later provide a dedicated baud rate generator for the serial interface 0 This baud rate genertaor is a free running 10 bit timer with programmable reload registers 5 SMOD Mode 1 3 baud rate Jose 64x 219 SOREL The default value after reset in the reload registers SORELL and SORELH prvide a baud rate of 4 8 kBaud SMOD 0 or 9 6 kBaud SMOD 1 at 12 MHz oscillator frequency This guarantees full compatibility to the SAB 80C517 older steppings Semiconductor Group 304 SIEMENS SAB 80C517 80C537 Serial Interface 1 Serial interface 1 can oper
58. indicated to the accumulator leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 1100001 1p and register 0 holds 10101010p The instruction ADD A RO will leave 6 011011016 in the accumulator with the AC flag cleared and both the carry flag and OV set to 1 ADD A Rn Operation ADD A lt A Rn 0010 irrr Bytes 1 Cycles 1 ADD A direct Operation Encoding Bytes Cycles ADD lt A direct 00010101 direct address 2 1 Semiconductor Group 179 SIEMENS Instruction Set ADD A Ri Operation ADD lt A Ri Encoding 001010111 Bytes 1 Cycles 1 ADD A data Operation ADD lt A data Encoding 00100100 immediate data Bytes 2 Cycles 1 Semicondu
59. inputs when used for digital input 7 1 4 3 Read Modify Write Feature of Ports 0 through 6 Some port reading instructions read the latch and others read the pin see figure 7 1 The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in table 7 2 If the destination is a port or a port bit these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO to P6 for example MOV reads the value from port 3 pins while ANL P4 0 reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in this list are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Semiconductor Group 49 SIEMENS On Chip Peripheral Components Table 7 2 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC
60. instruction ending at location 01224 Internal RAM locations OAy and contain the values 234 and 014 respectively The instruction will leave the stack pointer equal to 094 and return program execution to location 0123 15 8 lt SP SP lt SP 1 PC7 0 lt SP SP lt SP 1 0011 0010 Semiconductor Group 235 SIEMENS Instruction Set RL A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator left The eight bits in the accumulator are rotated one bit to the left Bit 7 is rotated into the bit 0 position No flags are affected The accumulator holds the value OC5y 11000101 The instruction RL A leaves the accumulator holding the value 8By 100010116 with the carry unaffected RL An 1 lt An 0 6 lt A7 00100011 Semiconductor Group 236 SIEMENS Instruction Set RLC A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator left through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected The accumulator holds the value 0 5 11000101p and the carry is zero The instruction RLC A leaves the accumulator holding the v
61. interrupt requests when a transmission or a reception of a frame has completed The corresponding interrupt request flags for serial interface 1 are or resp See section 8 for more details about the interrupt structure The interrupt request flags and can also be used for polling the serial interface 1 if the serial interrupt shall not be used i e serial interrupt 1 not enabled The control and status bits of the serial channel 1 in special function register S1CON are illustrated in figure 7 12 Figure 7 13 shows the special function register S1BUF which is the data register for receive and transmit Note that these special function registers are not bit addressable Due to this fact bit instructions cannot be used for manipulating these registers This is important especially for S1CON where a polling and resetting of the RI1 or request flag cannot be performed by JNB and CLR instructions but must be done by a sequence of byte instructions LOOP MOV A S1CON JNB ACC 0 LOOP Testing of ANL S1CON 0FEH Resetting of Semiconductor Group 61 SIEMENS On Chip Peripheral Components Figure 7 12 Special Function Register S1CON Address SM 5 SM21 REN1 TB81 RB81 TI S1CON Bit Function SM SM 0 serial mode A 9 bit UART SM 1 serial mode B 8 bit UART 21 Enables the multiprocessor communication
62. interrupt routine has to calculate the next compare value for the current channel e g CC2 Tocnext Tccauty where is the next compare value in 2 Tectt is the constant total number of counts for one PWM cycle 200 for PWM channel 2 Tcca is the actual compare register contents which just caused the interrupt 1 the variable count determining the duty cycle of the PWM signal The interrupt routine may be left when Tccnext IS loaded to register CC2 the port latch is complemented and prepared for the next transition and auser defined flag is set to mark that this PWM cycle is now completed Semiconductor Group 257 SIEMENS Application Examples The same calculation must be performed when register CC1 has had its match and has caused an interrupt for PWM channel 1 But this is done independently from channel 2 since both channels have their own interrupt request flags When either of the two count values of Tecnex has been reached by timer 2 in our example channel 1 is first then the corresponding interrupt routine polls the user flag and is informed that a new PWM cycle is to be generated It therefore calculates the next compare value to Tocauy where Tocauty may be a new value for the duty cycle calculated in another task of the program 10 1 2 Sine Wave Generation with a CMx Registers Compare Timer Configuration The follo
63. is cleared MUL Semiconductor Group 226 SIEMENS Instruction Set NOP Function Description Example Operation Encoding Bytes Cycles No operation Execution continues at the following instruction Other than the PC no registers or flags are affected It is desired to produce a low going output pulse on bit 7 of port 2 lasting exactly 5 cycles A simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR P2 7 NOP NOP NOP NOP SETB P2 7 NOP 00000000 Semiconductor Group 227 SIEMENS Instruction Set ORL lt dest byte gt lt src byte gt Function Logical OR for byte variables Description ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 11000011
64. lt direct A Encoding 01010101 Bytes 2 Cycles 1 Semiconductor Group immediate data direct address 185 SIEMENS Instruction Set ANL direct data Operation ANL direct lt direct data Encoding 01010011 direct address immediate data Bytes Cycles 2 Semiconductor Group 186 SIEMENS Instruction Set ANL C lt src bit gt Function Logical AND for bit variables Description If the Boolean value of the source bit is a logic then clear the carry flag otherwise leave the carry flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct bit addressing is allowed for the source operand Example Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV C P1 0 Load carry with input pin state ANL C ACC 7 AND carry with accumulator bit 7 ANL C OV AND with inverse of overflow flag ANL C bit Operation ANL C lt C bit Encoding 1000 0010 bit address Bytes Cycles 2 ANL C bit Operation ANL C lt bit Encoding 1011 0000 bit address Bytes 2 Cycles 2 Semiconductor Group 187 SIEMENS Instruction Set
65. or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL 1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output port 1 Each pulse will last three machine cycles two for DJNZ and one to alter the pin Semiconductor Group 200 SIEMENS Instruction Set DJNZ Operation Encoding Bytes Cycles DJNZ Operation Encoding Bytes Cycles Rn rel DJNZ lt PC 2 Rn Rn 1 if Rn gt or Rn lt 0 then PC PC rel direct rel rel address 11011 rel address 2 DJNZ PC lt PC 2 direct lt direct 1 if direct gt or direct lt 0 then PC lt PC rel 1101 0101 direct address 2 Semiconductor Group 201 SIEMENS Instruction Set INC lt byte gt Function Increment Description increments the indicated variable by 1 An original value of OFF 4 will overflow Example INC A Operation Encoding Bytes Cycles INC Rn Operation Encoding Bytes Cycles to 00 No flags are affected Three addressing modes are allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data l
66. output signal changes from low to high It goes back to a low level on timer overflow As long as compare mode 0 is enabled the appropriate output pin is controlled by the timer circuit only and not by the user Writing to the port will have no effect Figure 7 38 shows a functional diagram of a port latch in compare mode 0 The port latch is directly controlled by the two signals timer overflow and compare The input line from the internal bus and the write to latch line are disconnected when compare mode 0 is enabled Compare mode 0 is ideal for generating pulse width modulated output signals which in turn can be used for digital to analog conversion via a filter network or by the controlled device itself e g the inductance of a DC or AC motor Mode 0 may also be used for providing output clocks with initially defined period and duty cycle This is the mode which needs the least CPU time Once set up the output goes on oscillating without any CPU intervention Figure 7 39 illustrates the function of compare mode 0 For some information on how to operate a timer compare register configuration to generate PWM signals e g by using a compare interrupt please refer to chapter 7 5 5 where more details about the configurations can be found or to chapter 10 where two application examples are provided Compare ee V Read Latch Internal Bus Write to Latch Access Disabled Read Pin Timer 2 Overflow MCS01845
67. pulled low by an external source When externally pulled low the port pins source current 1 or For this reason these ports are sometimes called quasi bidirectional Yoo Internal Pull Up Arrangement Int Bus o Pin ps MCS01823 Figure 7 2 Basic Output Driver Circuit of Ports 1 through 6 In fact the pullups mentioned before and included in figure 7 2 are pullup arrangements as shown in figure 7 3 One n channel pulldown FET and three pullup FETs are used The pulldown FET n1 is of n channel type It is a very strong driver transistor which is capable of sinking high currents o it is only activated if a 0 is programmed to the port pin A short circuit to must be avoided if the transistor is turned on since the high current might destroy the FET The pullup FET p1 is of p channel type It is activated for two oscillator periods S1P1 and S1P2 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a 0 The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin Semiconductor Group 42 SIEMENS On Chip Peripheral Components The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than 1 therefore the pin may also be
68. register three 16 bit compare capture registers one 16 bit compare capture register with additional concurrent compare feature eight 16 bit compare registers with timer overflow controlled loading Altogether the register array may control up to 21 output lines and can request up to 7 independent interrupts For brevity in the following text all double byte compare compare capture or compare reload capture registers are called CMx x 0 7 x 0 4 or CRC register respectively The block diagram in figure 7 33 shows the general configuration of the CCU All CCx registers and the CRC register are exclusively assigned to timer 2 Each of the eight compare registers CMO through CM7 can either be assigned to timer 2 or to the faster compare timer e g to provide up to 8 PWM channels The assignment of the CMx registers which can be done individually for every single register is combined with an automatic selection of one of the two possible compare modes Semiconductor Group 93 SIEMENS On Chip Peripheral Components Port 5 port 4 and seven lines of port 1 have alternate functions dedicated to the CCU These functions are listed in table 7 8 Normally each register controls one dedicated output line at the ports Register CC4 is an exception as it can manipulate up to nine output lines one at port 1 4 and the other eight at port 5 concurrently This feature the concurrent compare is described in section 7 5 5 1
69. sets the corresponding interrupt request flag Thus the current task of the CPU is interrupted of course provided the priority of the compare interrupt is higher than the present task priority and the corresponding interrupt service routine is called This service routine then sets up all the necessary parameters for the next compare event Some advantages in using compare interrupts Firstly there is no danger of unintentional overwriting a compare register before a match has been reached This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count Secondly and this is the most interesting advantage of the compare feature the output pin is exclusively controlled by hardware therefore completely independent from any service delay which in real time applications could be disastrous The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event This in turn is supposed to happen after a sufficient space of time Please note two special cases where a program using compare interrupts could show a surprising behavior The first configuration has already been mentioned in the description of compare mode 1 The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock In this case it should be carefully considered that the compare signal is active as long as the timer 2 count is e
70. single chip systems which have to manage PWM periods below 50 microseconds require a very efficient on chip timer hardware to leave enough CPU time to perform other control tasks in real time The SAB 80C517 takes advantage of the fast compare timer and the TOC loading mechanism to meet the above requirements 10 2 Using an SAB 80C537 with External Program Memory and Additional External Data Memory Figure 10 4 shows an example of how to connect an external program and data memory to the SAB 80C517 80C537 For the program memory a standard EPROM 2764A is used An 8 Kbyte static RAM 5565 serves as external data memory The 74HCT573 works as address latch The address space ranges from 0 to 1FFFy 8 Kbyte Pin EA is tied low so all program memory accesses are done from external memory Port 0 is the multiplexed address data bus while port 2 always emits the high order byte of the address Therefore in this configuration port 0 and port 2 must not be used as general purpose ports Semiconductor Group 263 SIEMENS Application Examples 1 0 1 0 1 0 XTAL2 XTAL Varer P8 3 AN11 P8 2 AN10 P8 1 AN9 P8 0 AN8 P1 0 INT3 CCO P7 5 AN5 P1 1 INT4 CC1 P7 4 AN4 P1 2 INT5 CC2 P7 3 AN3 P1 3 INT6 CC3 P7 2 AN2 P1 4 INT2 CC4 P7 1 AN1 P1 5 T2EX P7 0 ANO P1 6 CLKOUT 1 7 12 P2 7 P2 6 P4 0 CM0 P2 5 P4 1 CM1 P2 4 P4 2 CM2 P2 3 P4 3 CM3 P2 2 P4 4 CM4 P2 1 P4
71. subtraction otherwise AC is cleared OV is set if the operation results in a carry to the high order bit of the result but not a carry from the bit or vice versa otherwise OV is cleared OV is used in two s complement arithmetic because it is set when the signal result cannot be represented in 8 bits Pis set if the modulo 2 sum of the eight bits in the accumulator is 1 odd parity otherwise P is cleared even parity When a value is written to the PSW register the P bit remains unchanged as it always reflects the parity of A Semiconductor Group 173 SIEMENS Instruction Set 9 2 3 Logic The SAB 80C517 performs basic logic operations on both bit and byte operands Single Operand Operations CLR sets A or any directly addressable bit to zero 0 SETB sets any directly bit addressable bit to one 1 CPL is used to complement the contents of the A register without affecting any flag or any directly addressable bit location RL RR RRC SWAP are the five operations that can be performed on A RL rotate left RR rotate right RLC rotate left through carry RRC rotate right through carry and SWAP rotate left four For RLC and RRC the CY flag becomes equal to the last bit rotated out SWAP rotates A left four places to exchange bits 3 through 0 with bits 7 through 4 Two Operand Operations ANL performs bitwise logical AND of two operands for both bit and byte operands and returns t
72. the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles lt One Machine Cycle gt 54 S5 96 1 S2 S3 S4 S5 6 1 52 S3 S4 S5 S6 1 S2 bl eT p dr pb o dee ede Tn Ed E Wt lt COIN MCT01821 Figure 6 2 CPU Timing after Reset Semiconductor Group 38 SIEMENS System Reset 6 2 Reset Output Pin RO As mentioned before the SAB 80C517 internally synchronizes an external reset signal at pin RESET in order to perform a reset procedure Additionally the SAB 80C517 provides several fail save mechanisms e g watchdog timer and oscillator watchdog which can internally generate a reset too Thus it is often important to inform also the peripherals external to the chip that a reset is being performed and that the controller will soon start its program again For that purpose the SAB 80C517 has a pin dedicated to output the internal reset request This reset output RO at pin 82 shows the internal and already synchronized reset signal requested by any of the three possible sources in the SAB 80C517 external hardware reset watchdog timer reset oscillator watchdog reset The duration of the active low signal of the reset output depends on the source which requests it In the case of the external hardware reset it is the synchronized external reset s
73. tied to ground e g when used as input with logic low input level The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current in addition the pullup FET p3 is activated a higher current can be sourced M Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving cabability is stronger if a logic high level is output Delay 2 Osc Periodes Mec 21 3 Port e e o Pin Q Vss Input Data 1 zl read pin 3 MCS01824 Figure 7 3 Output Driver Circiut of Ports 1 through 6 The described activating and deactivating of the four different transistors translates into four states the pins can be input low state IL p2 active only input high state IH steady output high state p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active Semicond
74. time is not 0 the receive circuits are reset and the unit goes back looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid itis shifted into the input shift register and reception of the rest of the frame will proceed As data bits come from the right 1 s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 B is a 9 bit register it flags the RX control block to do one last shift The signal to load SOBUF S1BUF and RB80 RB81 and to set RIO RI1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RIO RI1 0 and 2 either SM20 SM21 0 or the received stop bit 1 Semiconductor Group 67 SIEMENS On Chip Peripheral Components If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB80 RB81 the 8 data bits go into SOBUF S1BUF and RIO RI1 is activated At this time no matter whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RXDO RxD1 7 2 3 3 Mode 2 9 Bit UART Serial Interface 0 Mode 2 is functionally identical to mode 3 see below The only exception is that in mode 2 the baud rate can be programmed to two fixed quantities either 1 32 or 1 64 of the oscillator frequency Note that serial interface O cannot
75. timer there is an automatic reload from the registers SORELL address AAH and SORELH address The lower 8 bits of the timer are reloaded from SORELL while the upper two bits are reloaded from bit 0 and 1 of register SORELH The baud rate timer is reloaded by writing to SORELL Semiconductor Group 58 SIEMENS On Chip Peripheral Components SORELH 0 1 SORELL Baud Rate Clock gt 10 Bit Timer Overiiog fosc 2 MCS02222 Figure 7 11a Baud Rate Generator for Serial Interface 0 The default value after reset of SORELL is OD9 4 SORELH contains 11 Special Function Register SORELH SORELL Bit No MSB LSB Addr SORELH Bit No MSB LSB 7 6 5 4 3 2 1 0 Addr 136 SORELL 2 shaded areas are not used for programming the baudrate timer Bit Function SORELH 0 1 Reload value Upper two bits of the timer reload value SORELL 0 7 Reload value Lower 8 bit of timer reload value Reset value of SORELL is 0D94 SORELH contains XXXX XX11p Semiconductor Group 59 SIEMENS On Chip Peripheral Components Figure 7 11b shows a block diagram of the options available for baud rate generation of Serial Channel 0 It is a fully compatible superset of the functionality of older SAB 80C517 steppings The new baud rate generator can be used in modes 1 and 3 of the Serial Channel 0 It is activated by setting bit
76. total conversion time including sample time is 13 machine cycles 13 us at 12 MHz oscillator frequency Conversion can be programmed to be single or continuous at the end of a conversion an interrupt can be generated A unique feature is the capability of internal reference voltage programming The internal reference voltages Vintarer and Vintaanp for the A D converter are both programmable to one of 16 steps with respect to the external reference voltages This feature permits a conversion with a smaller internal reference voltage range to gain a higher resolution In addition the internal reference voltages can easily be adapted by software to the desired analog input voltage range see table 2 Table 2 Adjustable Internal Reference Voltages Step DAPR 3 0 VintAGND VintAREF DAPR 7 4 0 0000 0 0 5 0 1 0001 0 3125 2 0010 0 625 3 0011 0 9375 4 0100 1 25 1 25 5 0101 1 5625 1 5625 6 0110 1 875 1 875 7 0111 2 1875 2 1875 8 1000 2 5 2 5 9 1001 2 8125 2 8125 10 1010 3 125 3 125 11 1011 3 4375 3 4375 12 1100 3 75 3 75 13 1101 4 0625 14 1110 4 375 15 1111 4 68754 Semiconductor Group 287 SIEMENS SAB 80C517 80C537 8 00 Internal 7 DB ADCON1 DC _ a ADCONO 083 2 MX 1 q A D Converter
77. turned on and off by switching it out of and into its own mode 8 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself OSC 12 fosc 12 C T 0 In i nterru TLO B Bits TO Pin C T 1 Control Gate Pin fosc 12 8 Bits TR1 Control MCSO1840 Figure 7 24 Timer Counter 0 Mode 3 Two 8 Bit Timer Counter Semiconductor Group 82 SIEMENS On Chip Peripheral Components 7 4 A D Converter The SAB 80C517 provides an A D converter with the following features 12 multiplexed input channels which can also be used as digital inputs port 7 port 8 Programmable internal reference voltages 16 steps each via resistor array 8 bit resolution within the selected reference voltage range 13 microseconds conversion time including sample time at 12 MHz oscillator frequency Selectable external or internal start of conversion trigger Interrupt request generation after each conversion For the conversion the method of successive approximation via capacitor array is used The externally applied reference voltage range has to be held on a fixed value within the specifications see section A D Converter Characteristics in the data sheet The internal reference voltages can be varied to reduce the reference voltage range of the A D converter and thus to achieve a higher resolution Fig
78. value 5 01011100p Operation SWAP 0 5 7 4 A7 4 lt A3 0 1100 0100 Bytes 1 Cycles 1 Semiconductor Group 244 SIEMENS Instruction Set XCH A lt byte gt Function Exchange accumulator with byte variable Description loads the accumulator with the contents of the indicated variable at the same time writing the original accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing Example RO contains the address 204 The accumulator holds the value 3F 001111116 Internal RAM location 204 holds the value 754 01110101p The instruction XCH A RO will leave RAM location 204 holding the value 001111116 and 75H 011101016 in the accumulator XCH A Rn Operation XCH A 5 Rn Encoding 1100 irrr Bytes 1 Cycles 1 XCH A direct Operation XCH S direct Encoding 110010101 direct address Bytes 2 Cycles 1 Semiconductor Group 245 SIEMENS Instruction Set XCH A Ri Operation XCH 5 Ri 11000111 Bytes 1 Cycles 1 Semiconductor Group 246 SIEMENS Instruction Set XCHD A Ri Function Description Example Operation Encoding Bytes Cycles Exchange digit XCHD exchanges the low order nibble of the accumulator bits 3 0 generally
79. values for the next cycle may be programmed from now on The activation of the TOC loading depends on a few conditions described in the following A TOC loading is performed only if the CMLx register has been changed by the CPU A write instruction to the low byte of the CMx register is used to enable the loading The 8 bit architecture of the SAB 80C517 requires such a defined enable mechanism because 16 bit values are to be transferred in two portions two instructions Imagine the following situation one instruction e g loading the low byte of the compare register is executed just before timer overflow and the other instruction loading the high byte after the overflow If there were no rule the TOC loading would just load the new low byte into the compare latch The high byte written after timer overflow would have to wait till the next timer overflow Semiconductor Group 120 SIEMENS On Chip Peripheral Components The mentioned condition for TOC loading prevents such undesired behavior If the user writes the high byte first then no TOC loading will happen before the low byte has been written even if there is a timer overflow in between If the user just intends to change the low byte of the compare latch then the high byte may be left unaffected Summary of the above description of the TOC loading The CMx registers are when switched to the compare timer protected from direct loading by the CPU A register l
80. voltages Vintaner For this purpose the internal reference voltages can be programmed in steps of 1 16 of the external reference voltages Varer Vaawp by four bits each in register DAPR Bits 0 to specify Vintacnp While bits 4 to 7 specify Vintarer A minimum of 1 V difference is required between the internal reference voltages Vntarer Vintacny for proper operation of the A D converter This means for example the case where Varer is 5 V and is 0 V there must be at least four steps difference between the internal reference voltages Vinracnp The values of and Vinarer are given by the formulas DAPR 3 0 ViNrAGND VAGND AREF Vann 16 with DAPR 3 0 lt Cy DAPR 7 4 VAGND Vangr m Vacub 16 with DAPR 7 4 gt DAPR 3 0 is the contents of the low order nibble and DAPR 7 4 the contents of the high order nibble of DAPR Figure 7 29 Special Function Register DAPR Address ODA Programming of Vintarer Programming of Vintacnp DAPR H D A converter program register Each 4 bit nibble is used to program the internal reference voltages Write access to DAPR starts conversion DAPR 3 0 VAGND AREF 16 with DAPR 3 0 lt 13 DAPR 7 4 ViNTAREF VAGND AREF Vaanp 16 with DAPR 7 4 gt 3 Semiconductor Group 88
81. with its default time out period The value in the reload register WDTREL however can be overwritten at any time to set any time out period desired The Second Possibility of Starting the Watchdog Timer The watchdog timer can also be started by software This method is compatible to the start procedure in the SAB 80 C 515 Only setting of bit SWDT in special function register IEN1 figure 7 61 starts the watchdog timer Starting the watchdog timer does not automatically reload the WDTREL register into the watchdog timer registers WDTL WDTH reload of WDTREL occurs only when using the double instruction refresh sequence SETB WDT SETB SWDT Using the software start the time out period can be programmed before the watchdog timer starts running Note that once the watchdog timer has been started it cannot be stopped by anything but an external hardware reset through pin 10 with a low level applied to pin PE SWD Refreshing the Watchdog Timer At the same time the watchdog timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT IENO 6 and by the next instruction setting SWDT IEN1 6 Bit WDT will automatically be cleared during the second machine cycle after having been set For this reason setting SWDT bit has to be a one cycle instruction e g SETB SWDT This double instru
82. 0 1 Capture on rising edge at pin P1 3 INT6 CC3 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 Figure 7 42 and 7 43 show the general timer compare register port latch configuration for registers CRC and CC1 to CC4 in compare mode 0 and compare mode 1 Please note that the compare interrupts of registers CRC and CC4 can be programmed to be negative or positive transition activated Compare interrupts for the CC1 to CC3 registers are always positive transition activated Semiconductor Group 109 SIEMENS On Chip Peripheral Components Interrupt Compare Register CCx J Comparator Compare Signal Overflow P1 4 P1 0 Interrupt CC4 INT 2 INT 3 MCS01849 Figure 7 42 Timer 2 with Registers CCx CRC and CC1 to CC4 in Compare Mode 0 Interrupt Compare Register CCx Compare Signal Latch Circuit TH2 TL2 Timer 2 P1 7 P1 0 INT 3 501850 Figure 7 43 Timer 2 with Registers CCx and CC1 to CC4 Compare Mode 1 Semiconductor Group 110 SIEMENS On Chip Peripheral Components Modulation Range in Compare Mode 0 As already mentioned in the general description of compare mode 0 section 7 5 4 a 100 variation of the duty cycle of a PWM signal cannot be reached A time portion of 1 2 of an n bit timer period is always left over This spike may either appear when the compare register is set to the reload va
83. 0 5 ms for signal 1 500 timer 2 counts at fosc 12 MHz and 0 2 ms for signal 2 200 counts Thus compare mode 1 must be used because in this mode both transitions can be preset by software Timer 2 may run with its full period from 0000 overflowing at a count rate of 65 535 OFFFF p External interrupts INT4 and INT5 are enabled as compare interrupts and the compare registers CC1 and CC2 are initialized to 50 96 duty cycle thus containing a value of 250 and 100 respectively The contents of the port latches must be preprogrammed to a complementary level which will appear after the corresponding compare event Now timer 2 is started The first compare interrupt occurs after 100 timer increments caused by the contents of register CC2 Figure 10 1 illustrates the task schedule of the program Every compare event causes an interrupt request which is served after a certain response time depending on the current task being in progress There are a few jobs to be done which are described in the following Semiconductor Group 256 SIEMENS Application Examples Timer 2 Count 0 50 100 150 200 250 300 350 400 450 500 550 Timer start Compare interrupt INT 5 Compare interrupt INT 6 MCT01861 H servicing interrupt task Interrupt is pending and will be serviced when current CPU task is completed Figure 10 1 Task Schedule for Additive Compare Program The
84. 2 multiplexed inputs Programmable reference voltages External internal start of conversion Two 16 bit timers counters 8051 compatible Powerful compare capture unit CCU based on a 16 bit timer counter and a high speed 16 bit timer for fast compare functions One 16 bit reload compare capture register Four 16 bit compare capture registers one of which serves up to nine compare channels concurrent compare Eight fast 16 bit compare registers Arithmetic unit for division multiplication shift and normalize operations Eight datapointers instead of one for indirect addressing of program and external data memory Extended watchdog facilities 16 bit programmable watchdog timer Oscillator watchdog Semiconductor Group 8 SIEMENS Introduction Nine ports Seven bidirectional 8 bit ports One 8 bit and one 4 bit input port for analog and digital input signals Two full duplex serial interfaces with own baud rate generators Four priority level interrupt systems 14 interrupt vectors Three power saving modes Slow down mode Idle mode Power down mode Siemens high performance ACMOS technology P LCC 84 package The ROMless version SAB 80C537 is identical with the SAB 80C517 except for the fact that it lacks the on chip program memory the SAB 80C537 is designed for applications with external program memory In this manual any reference made to the SAB 80C517 applies to both ver
85. 23 01024 21 In other words an SUMP with a displacement of would be a one instruction infinite loop SJMP PC 2 lt PC rel 10000000 rel address Semiconductor Group 241 SIEMENS Instruction Set SUBB A lt src byte gt Function Description Example Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the accumulator leaving the result in the accumulator SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears C otherwise If C was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or immediate The accumulator holds 11001001 p register 2 holds 544 01010100p and the carry flag is set The instruction SUBB A R2 will leave the value 744 01110100p in th
86. 32 bit normalize and shift by peripheral MUL DIV unit MDU Eight data pointers for external memory addressing Fourteen interrupt vectors four priority levels selectable 8 bit A D converter with 12 multiplexed inputs and programmable ref voltages Two full duplex serial interfaces Fully upward compatible with SAB 806515 Extended power saving modes Nine ports 56 I O lines 12 input lines Two temperature ranges available 0 to 70 C 40 to 85 Plastic packages P LCC 84 P MQFP 100 2 SAB 80C517 80C537 Oscillat 8 Datapointer Watchdog Timer 8 bit USART 2 x Analog Digital Input RAM Watchdog 256 x 8 Port 0 1 0 i i 2 MCA01 473 1 SAB 800517 1 0 SAB 800515 Analog Digital Input Semiconductor Group 04 95 80 517 80 537 SIEMENS SAB 80C517 80C537 is a high end member of the Siemens SAB 8051 family of microcontrollers It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture ACMOS is a technology which combines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C515 features and operating characteristics the SAB 80C517 is expanded in its arithmetic capabilities fail safe characteristics analog signal processing and timer capabilities The SAB 80C537 is identical with the SAB 80C517 except that it lacks the on chip program memory The SAB 80C517 SAB 80C537 i
87. 5 OF8y P6 Port 6 P7 Port 7 Analog Digital Input 0DBH XXH P8 Port 8 Analog Digital Input 4Bit XXH Pow Sav M PCON Power Control Register 87H 00H Serial ADCONO A D Converter Control Register 008 00 Channels PCON Power Control Register 87H 00H SOBUF Serial Channel 0 Buffer Register 99H XXH SOCON Serial Channel 0 Control Register 98H SORELL Serial Channel 0 Reload Reg low byte 0 9 SORELH Serial Channel 0 Reload Reg high byte OBAH XXXX XX11p S1BUF Serial Channel 1 Buffer Register 9CH XXH S1CON Serial Channel 1 Control Register 9By 0X00 0000p S1REL Serial Channel 1 Reload Register 9DH 00H S1RELH Serial Channel 1 Reload Reg high byte OBBH XXXX XX11B TCON Timer Control Register 88H 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH TL1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 89 00H Watchdog Interrupt Enable Register 0 0A84 00 IEN1 2 Interrupt Enable Register 1 0B8H4 00 IPO Interrupt Priority Register 0 9 00H IP12 Interrupt Priority Register 1 OB9y4 XX00 0000p WDTREL Watchdog Timer Reload Register 86H 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminat
88. 6 7 2 3 1 Mode 0 Synchronous Mode Serial Interface 0 66 7 2 3 2 Mode 1 Mode B 8 Bit UART Serial Interfaces 0 and 1 67 7 2 3 3 Mode 2 9 Bit UART Serial Interface 0 68 7 2 3 4 Mode 3 Mode A 9 Bit UART Serial Interfaces 0 and 1 68 7 3 3er oand mMer D cuca ie eo EEE E we mec rele ncs 76 Tale Mode Pos S enr dta pL 79 Sur Modei ook o eR DE Fco bud 80 KSS 81 KIA ModE 82 7 4 AD GCOnVellgE uate Sc aca M e ce Mod 83 7 4 1 Function and Control 83 7 4 1 1 Initialization and Input Channel Selection 83 7 4 1 2 Start of Conversion 5 se dto aaa 87 7 4 2 Reference Voltages 87 74 3 A D Converter Timing 91 7 5 The Compare Capture Unit 93 TST HMEC daem aA iese se Gaara aa ha 97 7 5 2 The Compare 101 7 5 3 Compare Function in the 103 7 5 4 Compare Modes of the CCU 103 7 5 4 1 Compare Mode 0 104 7 5 4 2 Compare Mode 1
89. 6 and RO holds 554 010101016 then the instruction ORL A RO will leave the accumulator holding the value 007 11010111p When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the accumulator at run time The instruction ORL P1 00110010p will set bits 5 4 and 1 of output port 1 ORL A Rn Operation ORL lt A v Rn Encoding 0100 Bytes 1 Cycles 1 Semiconductor Group 228 SIEMENS Instruction Set ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles A direct ORL lt A v direct direct address immediate data 0100 0101 2 1 A Ri ORL lt A v Ri 01000111 1 1 A data ORL lt A v data 01000100 2 1 direct A ORL direct lt direct v A 01000010 2 1 Semiconductor Group direct address SIEMENS Instruction Set ORL direct data Operation ORL direct lt direct data Encoding 01000011 direct address immediate data B
90. 67 External Clock Source Semiconductor Group 149 SIEMENS On Chip Peripheral Components 7 10 System Clock Output For peripheral devices requiring a system clock the SAB 80C517 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1 6 CLKOUT If bit CLK is set bit 6 of special function register ADCONO see figure 7 68 a clock signal with 1 12 of the oscillator frequency is gated to pin P1 6 CLKOUT To use this function the port pin must be programmed to a one 1 which is also the default after reset Figure 7 68 Special Function Register ADCONO Address 0D8 4 ODE ODDy ODCy ODBH uar ODS 0 0D8j ADEX BSY ADM MX2 qe ADCONO __ These bits are not used in controlling the clock out functions Bit Function CLK Clockout enable bit When set pin P1 6 CLKOUT outputs the system clock which is 1 12 of the oscillator frequency The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states Thus the duty cycle of the clock signal is 1 6 Associated with a MOVX instruction the system clock coincides with the last state S3 in which a RD or WR signal is active A timing diagram of the system clock output is shown in figure 7 69 Note During slow down operation see section 7 7 the frequency of the clockout signal is divided by eight Semiconductor Group 150
91. 7 31 illustrate these applications Semiconductor Group 89 SIEMENS On Chip Peripheral Components 5 00 V ANO AN1 AN 4 375 V 3 125 V 1 25 V 0 625 V OV VAGND MCS01841 Figure 7 30 Adjusting the Internal Reference Voltages to the Range of the External Analog Input Voltages First Conversion Second Conversion E E diet 35 125 V VINTAREF 1 875 V ViNTAGND 0v VACND MCS01842 Sample Sample Time Time Figure 7 31 Increasing the Resolution by a Second Conversion Semiconductor Group 90 SIEMENS On Chip Peripheral Components The external reference voltage supply need only be applied when the A D converter is used otherwise the pins Varer May be left unconnected The reference voltage supply has to meet some requirements concerning the level of Vagnp and Varer and the output impedance of the supply voltage see also A D Converter Characteristics in the data sheet The voltage Varer must meet the following specification Varer Voc 5 96 The voltage Vagnp must meet a similar specification Vacno Vss 0 2 V The differential output impedance of the analog reference supply voltage should be less than 1 If the above mentioned operating conditions are not met the accuracy of the converter may be decreased Furthermore the analog input voltage Vanpur must not exceed the range from Vagnp 0 2 V to Varer 0 2 V
92. 7 5 4 1 The minimum resolution attainable at the port 4 outputs is 6 appr 166 6 ns at fosc 12 MHz The compare timer is provided with a 16 bit auto reload and an 8 bit prescaler for a very high flexibility concerning timer period length and input clock frequency A block diagram of the compare timer is shown in figure 7 36 Input Clock Selection The compare timer receives its input clock from a programmable prescaler which provides eight different input frequencies fosc 2 fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 256 The selection can be done in a three bit field binary coded in special function register CTCON see figure 7 37 Register CTCON can be written to at any time its default value after reset is that iS fosc 2 input frequency Control CTCON Ld gt To Compare Circuitry To Interrupt 16 Bit Compare Timer CTF Circuitry Overflow 16 Reload CTREL MCB00783 Figure 7 36 Compare Timer Block Diagram Semiconductor Group 101 SIEMENS On Chip Peripheral Components Programming the Compare Timer in Auto Reload Operation The compare timer is once started a free running 16 bit timer which upon overflow is automatically reloaded by the contents of the special function register CTRELL compare timer reload register low byte and CTRELH compare timer reload register high byte An initial writing to the reload regist
93. 7 identification mark BB or later Semiconductor Group 161 SIEMENS Interrupt System 8 2 Priority Level Structure As already mentioned above all interrupt sources are combined as pairs or triplets table 8 1 lists the structure of the interrupt sources Table 8 1 Pairs and Triplets of Interrupt Sources External interrupt 0 Serial channel 1 interrupt A D converter interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt Compare timer interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 Timer 2 interrupt External interrupt 6 Each pair or triplet of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IPO and one in IP1 figure 8 9 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure determined by the poll
94. B 80C517 has an internal ROM of 8 Kbyte The program memory can externally be expanded up to 64 Kbyte see Bus Expansion Control The internal RAM consists of 256 bytes Within this address space there are 128 bit addressable locations and four register banks each with 8 general purpose registers In addition to the internal RAM there is a further 128 byte address space for the special function registers which are described in sections to follow Because of its Harvard architecture the SAB 80C517 distinguishes between an external program memory portion as mentioned above and up to 64 Kbyte external data memory accessed by a set of special instructions As an important improvement of the 8051 architecture the SAB 80C517 contains eight datapointers instead of one in the 8051 which speed up external data access Bus Expansion Control The external bus interface of the SAB 80C517 consists of an 8 bit data bus port 0 a 16 bit address bus port 0 and port 2 and five control lines The address latch enable signal ALE is used to demultiplex address and data of port 0 The program memory is accessed by the program store enable signal PSEN twice a machine cycle A separate external access line EA is used to inform the controller while executing out of the lower 8 Kbyte of the program memory whether to operate out of the internal or external program memory The read or write strobe RD WR is used for accessing the external data memory Perip
95. BUF S1BUF signal The transmission begins with activation of SEND which puts the start bit to TXDO TxD1 One bit time later DATA is activated which enables the output bit of the transmit shift register to TxDO TxD1 The first shift pulse occurs one bit time after that As data bits shift out to the right zeros are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just left of the MSB and all positions to the left of that contain zero This condition flags the TX control to do one last shift and then deactivate SEND and set TIO TI1 This occurs at the 10th divide by 16 rollover after write to SOBUF S1BUF Reception is initiated by a detected 1 to 0 transition at RxDO RxD1 For this purpose RxDO RxD1 is sampled at a rate of 16 times whatever baud rate has been established When a reception is detected the divide by 16 counter is immediately reset and 1 FFy is written into the input shift register Resetting the divide by 16 counter aligns its rollover with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16 counter states At the 7th 8th and 9th counter state of each bit time the bit detector samples the value of RXDO RxD1 The value accepted is the value that was seen at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit
96. CML2 Compare reg 2 low byte 0D6H CML3 Compare reg 3 low byte OE2y CML4 Compare reg 4 low byte OE4y CML5 Compare reg 5 low byte OE6L CML6 Compare reg 6 low byte 2 CML7 Compare reg 7 low byte OF4y CMSEL Compare input select OF7y CRCH Com rel capt reg high byte OCByY CRCL Com rel capt reg low byte OCA CTCON Com timer control reg OE1y CTRELH Com timer rel reg high byte ODFy CTRELL Com timer rel reg low byte IRCON Interrupt control register 0 2 Timer 2 high byte TL2 Timer 2 low byte 0CCH T2CON Timer 2 control register 0C8H Semiconductor Group 96 SIEMENS On Chip Peripheral Components 7 5 1 Timer 2 Timer 2 is one of the two 16 bit time bases of the compare capture unit It can operate as timer event counter or gated timer The block diagram in figure 7 34 a shows the general configuration of the timer 2 wt CTCON T TOR T T T2CON me No input selected timer 2 stops fosc 12 o Timer function e P17 T2 Counter function external qu input es at pin P1 7 12 Prescaler Timer 2 input selection gt 1 5 2 E SYNC EXF2 Interrupt Request Reload 1 available only in SAB 800517 80C537 5 MCBO1474 identification mark BB or later shaded areas are not used for this function Figure 7 34 a Block Diagram of
97. D pin The possible steps to go into power down mode could then be as follows Apower fail signal forces the controller to go into a high priority interrupt routine This interrupt routine saves the actual program status At the same time pin PE SWD is pulled low by the power fail signal Finally the controller enters power down mode by executing the relevant double instruction sequence 7 7 1 Idle Mode In idle mode the oscillator of the SAB 80C517 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial channels the A D converter the oscillator watchdog the division multiplication unit and all timers except for the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the division multiplication unit are not running maximum power reduction can be achieved This state is also the test condition for the idle J g see the DC characteristics in the data sheet Thus the user has to take into account that the right peripheral continues to run or is stopped respectively during idle Also the state of all port pins either the pins controlle
98. FY Contents Timer Count of a Timer Compare Value Register Timer Count Reload Value Interrupt can be generated on overflow Compare Output P1 x CCx MCTO1846 Interrupt can be generated on compare match Figure 7 39 Function of Compare Mode 0 Semiconductor Group 105 SIEMENS On Chip Peripheral Components 7 5 4 2 Compare Mode 1 In compare mode 1 the software adaptively determines the transition of the output signal This mode can only be selected for compare registers assigned to timer 2 It is commonly used when output signals are not related to a constant signal period as in a standard PWM generation but must be controlled very precisely with high resolution and without jitter In compare mode 1 both transitions of a signal can be controlled Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity If mode 1 is enabled and the software writes to the appropriate output latch at the port the new value will not appear at the output pin until the next compare match occurs Thus one can choose whether the output signal is to make a new transition 1 to 0 or 0 to 1 depending on the actual pin level or should keep its old value at the time the timer 2 count matches the stored compare value Figure 7 40 shows a functional diagram of a timer compare register port latch configuration in compare mode 1 In this function the port latch consis
99. IB EDT Oso uc PE Pd Ee RE OR op aha 152 8 2 Priority Level Structure 162 8 3 How Interrupts are Handled 164 8 4 Exterhal INterrUptS auo S Ea E ER E e SEXE 3 167 8 5 Response ITO on ded ac ay hak Sacha S NCC x e CE ta we EN 168 9 Instruction Set irre dno vec pene x ERES IPIE ERE ETE 169 9 1 Addressi g MOdeS xu crga aw Ra CR t SS xa Dc ul dr eC Owes RACER CR 169 9 2 Introduction to the Instruction Set 171 9 2 1 OUR a 171 9 2 2 ACUNMCUC sss wa wedrv ie va ed ex pde a e ux Aa ERE Oa eee 172 9 23s e NEM SN on She d OR E 174 924 Transter qase Dau vastas CU De e 174 9 3 Instruction 5 176 10 Application Examples 256 10 1 Application Examples for the Compare Functions 256 10 1 1 Generation of Two Different PWM Signals with Additive Compare using 2 das dade lave ina da eee a hea keke den 256 10 1 2 Sine Wave Generation with a CMx Registers Compare Timer COnngurauOn lt a A i244 taeda etn ede de tae buie d HAN Ruta tae bees 258 10 2 Using an SAB 80C537 with External Program Memory and Additional External Data Memory
100. LCX 20 ns Rise time CLCH 20 ns Fall time t CHCL 20 ns AC Characteristics cont d Parameter Symbol Limit Values Unit Variable Clock Frequ 1 MHz to 16 MHz min max External Clock Drive Oscillator period 1 62 5 285 ns Oscillator frequency 1 tereL 13 5 16 MHz High time CHCX 25 ns Low time 1 25 ns Rise time x 20 ns Fall time t CHCL 20 ns Semiconductor Group 319 SIEMENS SAB 80C517 80C537 0 2 e c 0 1V MCT00793 External Clock Cycle Semiconductor Group 320 SIEMENS SAB 80C517 80C537 AC Characteristics cont d Parameter Symbol Limit Values Unit 12 MHz Clock Variable Clock 1 t 3 5 MHz to12 MHz min max min max System Clock Timing ALE to CLKOUT fLLSH 543 Tte ci 40 ns CLKOUT high time tSHSL 127 21 40 ns CLKOUT low time tSLSH 793 1016 40 ns CLKOUT low to ALE tSLLH 43 123 tcLcL 40 40 ns high AC Characteristics cont d Parameter Symbol Limit Values Unit 16 MHz Clock Variable Clock 1 t 3 5 MHz to 16 MHz min max min max System Clock Timing ALE to CLKOUT fLLSH 398 Tte ci 40 ns CLKOUT high time tSHSL 85 211 40 ns CLKOUT low time tSLSH 585 10 40 ns CLKOUT low to ALE tsLLH 23 103 40 40 ns high
101. Mode B 8 Bit Baud rate 1 62 5K 4800 9600 1 5 375 UART Baud rate X Timer 1 BD 8 bit baud rate generator derived from Mode Mode 2 Mode 3 Mode A 9 Bit Baud rate 187 5 K 1 62 5K 1 5 375K UART 375 Baud rate 2 Timer 1 8 bit baud rate generator derived from Baud rate values are given for 12 MHz oscillator frequency Semiconductor Group 303 SIEMENS SAB 80C517 80C537 Serial Interface 0 Serial Interface 0 can operate in 4 modes Mode 0 Shift register mode Serial data enters and exits through RXDO TXDO outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator frequency Mode 1 8 bit UART variable baud rate 10 bit are transmitted through RXDO or received through RXDO a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB80 in special function register SOCON The baud rate is variable Mode2 9 bit UART fixed baud rate 11 bit are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is
102. N 6 CMEN 5 CMEN 4 CMEN 3 CMEN 2 CMEN 1 CMEN O CMEN Contains enable bits for compare registers CMO to CM7 When set compare function is enabled and led to the output lines Bit Function CMEN 7 Compare enable bit for CM7 CMEN 6 Compare enable bit for CM6 CMEN 5 Compare enable bit for CM5 CMEN 4 Compare enable bit for CM4 CMEN 3 Compare enable bit for CM3 CMEN 2 Compare enable bit for CM2 CMEN 1 Compare enable bit for CM1 CMEN O Compare enable bit for CMO Semiconductor Group 1 17 SIEMENS On Chip Peripheral Components First Configuration Registers Assigned to the Compare Timer Every CMx register switched to the compare timer as a time base operates in compare mode 0 and uses a port 4 pin as an alternate output function see table 7 8 Alternate Port Functions of the CCU Modulation Range in Compare Mode 0 In the general description of compare mode 0 section 7 5 4 and in the description of the timer 2 CCx register configuration section 7 5 5 1 it was mentioned that a compare output is restricted in its maximum or minimum duty cycle There is always a time portion of 1 2 at n bit timer length which is left over This spike may either appear when the compare register is set to the reload value limiting the lower end of the modulation range or it may occur at the end of a timer period as realized in this configuration In a compare timer CMx register c
103. NL A Rn AND register to accumulator 1 1 ANL A direct AND direct byte to accumulator 2 1 ANL A Ri AND indirect RAM to accumulator 1 1 ANL A data AND immediate data to accumulator 2 1 ANL direct A AND accumulator to direct byte 2 1 ANL direct Zdata AND immediate data to direct byte 3 2 ORL A Rn OR register to accumulator 1 1 ORL A direct OR direct byte to accumulator 2 1 ORL A Ri OR indirect RAM to accumulator 1 1 ORL A data OR immediate data to accumulator 2 1 ORL direct A OR accumulator to direct byte 2 1 ORL direct data OR immediate data to direct byte 3 2 Exclusive OR register to accumulator 1 1 XRL Adirect Exclusive OR direct byte to accumulator 2 1 XRL A Ri Exclusive OR indirect RAM to accumulator 1 1 XRL A data Exclusive OR immediate data to accumulator 2 1 XRL direct A Exclusive OR accumulator to direct byte 2 1 XRL direct Zdata Exclusive OR immediate data to direct byte 3 2 CLR Clear accumulator 1 1 Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right through carry 1 1 SWAP A Swap nibbles within the accumulator 1 1 Semiconductor Group 252 SIEMENS Instruction Set Instruction Set Summary cont d Mnemonic Description Byte Cycle Data Transfer
104. Output This pin outputs the internally synchronized reset request signal This signal may be generated by an external hardware reset a watchdog timer reset or an oscillator watch dog reset The reset output is active low Vas 37 60 83 10 62 Circuit ground potential Voc 38 84 11 63 Supply Terminal for all operating modes N C 2 5 25 Not connected 28 29 36 51 53 74 77 88 89 Input Output Semiconductor Group 278 SIEMENS SAB 80C517 80C537 OWE Oscillator Watchdog ROM 8K x 8 L 256 x 8 SAB 806517 OSC amp Timing only XTAL2 fk RESET Programmable RO Watchdog Timer Port 0 8 bit digit 1 0 PSEN Div Mul Unit lt Port 1 Port 1 bit _ mo _ 8 bit digit 1 0 EA PE Port 2 Y digi 1 0 Timer 2 T or Capture 8 digit 1 0 Compare Unit Compare Timer Port 4 8 bit digit 1 0 Port 5 Serial Channel 0 8 bit digit 1 0 Progr Baud Rate Generator Port 6 8 bit digit 1 0 Serial Channel 1 Port 7 Progr Baud Rate WS Generator 8 bit digit analog Input fl Port 8 AGND 4 bit digit analog Input MCB00777 Figure 1 Block Diagram Semiconductor Group 279 SIEMENS SAB 80C517 80C537 Functional Description The SAB 80C517 is based on 8051 arc
105. P MQFP 100 2 Function P6 0 P6 7 70 77 46 50 54 56 I O Port 6 is a bidirectional I O port with internal pull up resistors Port 6 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 6 pins being externally pulled low will source current in the DC characteristics because of the internal pull up resistors Port 6 also contains the external A D converter control pin and the transmit and receive pins for serial channel 1 The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 6 as follows ADST P6 0 external A D converter start pin RxD1 P6 1 receiver data input of serial interface 1 1 P6 2 transmitter data output of serial interface 1 P8 0 P8 3 78 81 57 60 Port 8 is a 4 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the higher 4 bit of the multiplexed analog inputs of the A D converter simultaneously Input O Output Semiconductor Group 277 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number l O Function P LCC 84 P MQFP 100 2 RO 82 61 Reset
106. P3 0 Alt Input Shift Register Shift Function SOBUF SOBUF L Read Internal Bus MCS01831 Figure 7 16 a Functional Diagram Serial Interface 0 Mode 0 Semiconductor Group 70 SIEMENS On Chip Peripheral Components Transmit Receive a h AN MCTO1832 Write to SOCON Clear RI S5P2 5 6 Write to SOBUF S6P2 Data Out Shift Clock Shift Clock o ca RXDO Receive gt lt nac ALE Send Shift TXDO TIO RIO Shift TXDO Figure 7 16 b Timing Diagram Serial Interface 0 Mode 0 Semiconductor Group 71 SIEMENS On Chip Peripheral Components Internal Bus 1 Write to SxBUF Shift TX Control Data Send Tix gt 1 Baud Serial gt Rate Port Clock Interrupt 1 0 RX Clock Load Transition Start SxBUF Detector RX Control 1FFy Shift gt NU SE Input Shift Register 9Bits RXDx Shift Load shift SxBUF Note x means that 0 or 1 can be inserted for interface 0 or interface 1 resp Read SxBUF Internal Bus MCS01833 Figure 7 17 a Functional Diagram Serial Interfaces 0 and 1 Mode 1 Mode B Semiconductor Group 72 SIEMENS On Chip Peripheral Components wo n Transmit 5 5 m Lu ac co 1
107. P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch However reading the latch rather than the pin will return the correct value of 1 Semiconductor Group 50 SIEMENS On Chip Peripheral Components 7 2 Serial Interfaces The SAB 80C517 has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation The two channels are full duplex meaning they can transmit and receive simultaneously They are also receive buffered meaning they can commence reception of a second byte before a previously received byte has been read from the receive register however
108. SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 Function P5 7 P5 0 61 68 37 44 I O Port 5 is a bidirectional I O port with internal pull up resistors Port 5 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 5 pins being externally pulled low will source current J in the DC characteristics because of the internal pull up resistors This port also serves the alternate function Concurrent Compare The secondary functions are assigned to the port 5 pins as follows CCMO P5 0 concurrent compare 0 COMI P5 1 concurrent compare 1 2 P5 2 concurrent compare 2 P5 3 concurrent compare 4 5 4 concurrent compare 4 CCM5 P5 5 concurrent compare 5 CCM6 P5 6 concurrent compare 6 7 5 7 concurrent compare 7 2 o OWE 69 45 Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog When left unconnected this pin is pulled high by a weak internal pull up resistor When held low level the oscillator watchdog function is off Input Output Semiconductor Group 276 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number P LCC 84
109. SIEMENS Microcomputer Components SAB 80C517 80C537 8 Bit CM OS Single Chip M icrocontroller User s M anual 05 94 Edition 05 95 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Munchen Siemens AG 1995 All Rights Reserved Attention please As far as patents or other rights of third par ties are concerned liability is only assumed for components not for applications pro cesses and circuits implemented within com ponents or assemblies The information describes the type of compo nent and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For in formation on the types in question please contact your nearest Siemens Office Semi conductor Group Siemens AG is an approved CECC manufac turer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us un sorted
110. SIEMENS On Chip Peripheral Components If DAPR 3 0 or DAPR 7 4 0 the internal reference voltages correspond to the external reference voltages Vagnp Varer respectively If Vainput gt Vintarer the conversion result is OFFy if lt Vintacno the conversion result is 00H Vainpur is the analog input voltage If the external reference voltages Vagnp 0 V and Varer 5 V with respect to Vss and are applied then the following internal reference voltages and VyrAgee shown in table 7 7 can be adjusted via the special function register DAPR Table 7 7 Adjustable Internal Reference Voltages Step DAPR 3 0 V intacno VintaREF DAPR 7 4 0 0000 0 0 5 0 1 0001 0 3125 2 0010 0 625 3 0011 0 9375 4 0100 1 25 1 25 5 0101 1 5625 1 5625 6 0110 1 875 1 875 7 0111 2 1875 2 1875 8 1000 2 5 2 5 9 1001 2 8125 2 8125 10 1010 3 125 3 125 11 1011 3 4375 3 4375 12 1100 3 75 3 75 13 1101 4 0625 14 1110 4 375 15 1111 4 6875 The programmability of the internal reference voltages allows adjusting the internal voltage range to the range of the external analog input voltage or it may be used to increase the resolution of the converted analog input voltage by starting a second conversion with a compressed internal reference voltage range close to the previously measured analog value Figures 7 30 and
111. The bits to MX2 in special function register ADCONO and the bits to in ADCON 1 are used for selection of the analog input channel Table 7 6 lists the selected input channels The bits MXO to MX2 are represented in both the registers ADCONO and ADCON1 however these bits are present only once it has the same effect irrespective of whether they are accessed via ADCONO or ADCON1 This is done in order to maintain software compatibility to the 80 C 515 In this device there are only eight input channels which are selected by to MX2 in ADCONO Thus program written for the SAB 80 C 515 selects one of the lower eight input channels port 7 if the bit MX3 is reset which is the default value after reset For clarity In the SAB 80 C 515 the analog input channel is called port 6 or ANO to AN7 resp However it is found on the same address 0DB jj as the SAB 80C517 s port 7 If all 12 multiplexed input channels are required register ADCON 1 is to be used It contains a four bit field to select one of all 12 input channels the eight inputs at port 7 and the four inputs at port 8 Thus there are two methods of selecting a channel of port 7 and it does not matter which is used if a new channel is selected in ADCON 1 the change is automatically done in the corresponding bits to MX2 in ADCONO and vice versa If bit is set the additional analog inputs at port 8 are used and MX1 then determine which chan
112. Timer 2 Semiconductor Group 97 SIEMENS On Chip Peripheral Components Timer Mode In timer function the count rate is derived from the oscillator frequency A 2 1 prescaler offers the possibility of selecting a count rate of 1 12 or 1 24 of the oscillator frequency Thus the 16 bit timer register consisting of TH2 and TL2 is either incremented in every machine cycle or in every second machine cycle The prescaler is selected by bit T2PS in special function register 2 see figure 7 35 T2PS is cleared the input frequency is 1 12 of the oscillator frequency if T2PS is set the 2 1 prescaler gates 1 24 of the oscillator frequency to the timer Gated Timer Mode In gated timer function the external input pin T2 P1 7 functions as a gate to the input of timer 2 If T2 is high the internal clock input is gated to the timer T2 0 stops the counting procedure This will facilitate pulse width measurements The external gate signal is sampled once every machine cycle for the exact port timing please refer to section 7 1 Parallel 1 0 Event Counter Mode In the counter function the timer 2 is incremented in response to a 1 to 0 transition at its corresponding external input pin T2 P1 7 In this function the external input is sampled every machine cycle When the sampled inputs show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the timer register in the cycle fol
113. achieve this baud rate in mode 3 Its baud rate clock is generated by timer 1 which is incremented by a rate of fosc 12 The dedicated baud rate generator of serial interface 1 however is clocked by a fosc 2 signal and so its maximum baud rate is fogc 32 7 2 3 4 Mode 3 Mode A 9 Bit UART Serial Interfaces 0 and 1 Eleven bits are transmitted through TxDO TxD1 or received through RxDO RxD1 a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB80 TB81 can be assigned the value of 0 or 1 On reception the 9th data bit goes into RB80 RB81 in SOCON S1CON Figures 7 18 a and b show a functional diagram of the serial interfaces in mode 2 and 3 or mode A resp and associated timing The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register The write to SOBUF S1BUF signal also loads TB80 TB81 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter thus the bit times are synchronized to the divide by 16 counter and not to the write to SOBUF S1BUF signal The transmission begins with the activation of SEND which put
114. ad is caused by a timer overflow auto reload Mode 1 Reload is caused in response to a negative transition at pin T2EX P1 5 which also can request an interrupt Timer Counters 0 and 1 These timer counters are fully compatible with timer counter or 1 of the SAB 8051 and can operate in four modes Mode 0 8 bit timer counter with 32 1 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer timer counter 1 in this mode holds its count External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Semiconductor Group 291 SIEMENS SAB 80C517 80C537 CTCON T T2CON TT PIER No input selected timer 2 stops fosc 12 lt Timer function P17 T2 Counter function external qo input ue at pin P1 7 12 Prescaler Timer 2 input selection ARIS gt P1 5 T2EX SYNC EXF2 Interrupt Request Reload 1 available only in SAB 80C517 80C537 MCBO1474 identification mark BB or later shaded areas are not used for this function Figure 6 Block Diagram of Timer 2 Semiconductor Group 292 SIEMENS SAB 80C517 80C537 fosc 2 3 Bit Prescaler 16 32 64 128 Compare Timer Control CTCON ae gt To Compare
115. al mode 0 Shift register mode fixed baud rate 0 1 Serial mode 1 8 bit UART variable baud rate 1 0 Serial mode 2 9 bit UART fixed baud rate 1 1 Serial mode 3 9 bit UART variable baud rate SM20 Enables the multiprocessor communication feature in modes 2 and 3 In mode 2 or 3 and SM20 being set to 1 RIO will not be activated if the received 9th data bit RB80 is 0 In mode 1 and SM20 1 RIO will not be activated if a valid stop bit has not been received In mode 0 SM20 should be 0 RENO Receiver enable Enables serial reception Set by software to enable reception Cleared by software to disable reception TB80 Transmitter bit 8 Is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB80 Receiver bit 8 In modes 2 and 3 it is the 9th bit that was received In mode 1 if SM20 0 RB80 is the stop bit that was received In mode 0 RB80 is not used TIO Transmitter interrupt Is the transmit interrupt flag Set by hardware at the end of the 8th bit time in mode or at the beginning of the stop bit in the other modes in any serial transmission Must by cleared by software RIO Receiver interrupt Is the receive interrupt flag Set by hardware at the end of the 8th bit time in mode 0 or during the stop bit time in the other modes in any serial reception Must be cleared by software Semiconductor Group 53 SIEMENS On Chip Peripheral Components 7 2 1 2 Multiprocessor Commu
116. alue 8 100010108 with the carry set RLC 1 lt An 0 6 A0 lt C lt A7 00110011 Semiconductor Group 237 SIEMENS Instruction Set RR A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator right The eight bits in the accumulator are rotated one bit to the right Bit 0 is rotated into the bit 7 position No flags are affected The accumulator holds the value OC5y 11000101 The instruction RR A leaves the accumulator holding the value OE2y 11100010p with the carry unaffected RR lt An 1 n 0 6 7 lt A0 00000011 Semiconductor Group 238 SIEMENS Instruction Set RRC A Function Rotate accumulator right through carry flag Description eight bits in the accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example The accumulator holds the value 5 11000101 p the carry is zero The instruction RRC A leaves the accumulator holding the value 624 01100010 with the carry set Operation RRC An An 1 n 0 6 A7 lt lt A0 00010011 Bytes 1 Cycles 1 Semiconductor Group 239 SIEMENS Instruction Set SETB lt bit gt Function Set bit Des
117. ampled the cycle before Therefore there must be met certain requirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once S4 55 56 51 P1 2 P1 2 1 2 P1 2 SLE LI UU UU UU UU Lu Input sampled e g MOV A P1 e g P1 A Old Data X New Data MCTO1828 Figure 7 6 Port Timing Semiconductor Group 48 SIEMENS On Chip Peripheral Components 7 1 4 2 Port Loading and Interfacing The output buffers of ports 1 through 6 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the 80C517 The corresponding parameters are Vo and Vo The same applies to port 0 output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that the ports 1 through 6 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters and the DC characteristics specify these currents Port 0 as well as the input only ports 7 and 8 however have floating
118. and therefore tries to start a new calculation in phases 1 through 3 of the same process sets the error flag The same applies for any shift operation normalize shift left right The error flag is set if the user s program reads one of the relevant registers MDO to or if it writes to MDO again before the shift operation has been completed Please note that the error flag mechanism is just an option to monitor the MDU operation If the user s program is designed such that an MDU operation cannot be interrupted by other calculations then there is no need to pay attention to the error flag In this case it is also possible to change the order in which the MDx registers are read or even to skip some register read instructions Concerning the shift or normalize instructions it is possible to read the result before the complete execution time of six machine cycles has passed e g when a small number of shifts has been programmed All of the above illegal actions would set the error flag but on the other hand do not affect a correct MDU operation The user has just to make sure that everything goes right The error flag MDEF is located in ARCON and can be read only It is automatically cleared after being read Semiconductor Group 133 SIEMENS On Chip Peripheral Components 7 7 Power Saving Modes The SAB 80C517 provides due to Siemens ACMOS technology three modes in which power consumption can be significantly reduced
119. ansmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency Semiconductor Group 51 SIEMENS On Chip Peripheral Components Mode 3 9 bit UART variable baud rate 11 bits are transmitted through TxDO or received through RxDO a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is ignored In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable In all four modes transmission is initiated by any instruction that uses SOBUF as a destination register Reception is initiated in mode 0 by the condition RIO 0 and RENO 1 Reception is initiated in the other modes by the incoming start bit if RENO 1 The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed The correspondi
120. are 7 of compare unit 7 P5 0 CCMO Concurrent compare 0 P5 1 CCM1 Concurrent compare 1 5 2 CCM2 Concurrent compare 2 P5 3 CCM3 Concurrent compare 3 P5 4 CCM4 Concurrent compare 4 P5 5 CCM5 Concurrent compare 5 P5 6 CCM6 Concurrent compare 6 P5 7 CCM7 Concurrent compare 7 P6 0 ADST Ext A D converter start P6 1 RXD1 Serial input channel 1 P6 2 TXD1 Serial output channel 1 Semiconductor Group 47 SIEMENS On Chip Peripheral Components 7 1 4 Port Handling 7 1 41 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 7 6 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was s
121. at V 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measure ments are made at V jymin for a logic 1 and V max for a logic 0 Input Output Waveforms Timing Reference Vos Points Vo 0 1V MCA00606 Float Waveforms Semiconductor Group 324
122. at first the external interrupt input is controlled by the pin s level When the compare option is enabled the interrupt logic input is switched to the internal compare signal which carries a low level when no true comparison is detected So the interrupt logic sees a 1 to 0 edge and sets the interrupt request flag An unintentional generation of an interrupt during compare initialization can be prevented if the request flag is cleared by software after the compare is activated and before the external interrupt is enabled 7 5 5 2 Compare Function of Registers CMO to CM7 The CCU of the SAB 80C517 contains another set of eight compare registers an additional timer the compare timer and some control SFR in the CCU which have not been described yet These compare registers and the compare timer are mainly dedicated to PWM applications The additional compare registers CMO to CM7 however are not permanently assigned to the compare timer each register may individually be configured to work either with timer 2 or the compare timer as shown in table 7 10 on page 133 The flexible assignment of the CMx registers allows an independent use of two time bases where by different application requirements can be met Any CMx register connected to the compare timer automatically works in compare mode e g to provide fast PWM with low CPU intervention Together with timer 2 CMx registers operate in compare mode 1 the latter configuration which is descr
123. atch notthe input pins Register 0 contains 7 01111110p Internal RAM locations 7 and 7 contain and 404 respectively The instruction sequence INC RO INC RO INC RO will leave register 0 set to 7 and internal RAM locations 7 and 7Fy holding respectively 00H and 41 INC lt A 1 00000100 INC Rn lt Rn 1 00001 Semiconductor Group 202 SIEMENS Instruction Set INC direct Operation INC direct lt direct 1 Encoding 0000 0101 direct address Bytes 2 Cycles 1 INC Ri Operation INC Ri lt Ri 1 Encoding 000010111 Bytes 1 Cycles 1 Semiconductor Group 203 SIEMENS Instruction Set INC DPTR Function Increment data pointer Description Increment the 16 bit data pointer by 1 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFFy to will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Example Registers and DPL contain 124 and OFEy respectively The instruction sequence INC DPTR INC DPTR INC DPTR will change and DPL to 134 and 01 Operation INC DPTR lt DPTR 1 Encoding 10100011 Bytes 1 Cycles 2 Semiconductor Group 204 SIEMENS Instruction Set
124. atch couple provides a defined load time at timer overflow Thus the CPU has a full timer period to load a new compare value there is no danger of overwriting compare values which are still needed in the current timer period When writing a 16 bit compare value the high byte should be written first since the write to low byte instruction enables a 16 bit wide TOC loading at next timer overflow fthere was no write access to a CMx low byte then no TOC loading will take place Because of the TOC loading all compare values written to CMx registers are only activated in the next timer period Initializing the Compare Register Compare Latch Circuit Normally when the compare function is desired the initialization program would just write to the compare register called register latch The compare latch itself cannot be accessed directly by a move instruction it is exclusively loaded by the timer overflow signal In some very special cases however an initial loading of the compare latch could be desirable If the following sequence is observed during initialization then latches the register and the compare latch can be loaded before the compare mode is enabled Semiconductor Group 121 SIEMENS On Chip Peripheral Components Action Select compare mode 1 CMSEL x 0 Move the compare value for the first timer period to the compare register CMx high byte first Switch on compare mode 0 CMSEL x 1 Mo
125. ate generator itself is identical with the one used for Serial Channel 0 It consists of a free running 10 bit timer with Fosc 2 input frequency On overflow of this timer there is an automatic reload from the registers S1REL address 9 and S1RELH address The lower 8 bits of the timer are reloaded from SOREL while the upper two bits are reloaded from bit 0 and 1 of register S1RELH The baud rate timer is reloaded by writing to S1REL The baud rate in Mode A and B can be determined by the following formula oscillator frequency 32 x 216 Reload Value Mode A B baud rate with Reload Value STRELH 1 0 S1RELL 7 0 Semiconductor Group 64 SIEMENS On Chip Peripheral Components Figure 7 15A shows a block diagram of the baud rate generator for Serial Interface 1 STRELH 0 1 Baud Rate Clock fosc 2 502224 Figure 7 15A Baud Rate Generator for Serial Interface 1 Special Function Register S1RELH STRELL Bit No MSB LSB 7 6 5 4 3 2 1 0 Addr OBBy msb S1RELH Bit No MSB LSB 7 6 5 4 3 2 1 0 Addr 09 Isb S1REL shaded areas are not used for programming the baudrate timer Bit Function S1RELH 0 1 Reload value Upper two bits of the timer reload value S1REL 0 7 Reload value Lower 8 bit of timer reload value Reset value of S1REL is STRELH contains XXXX XX11B Se
126. ate in two asynchronous modes Mode 9 bit UART variable baud rate 11 bits are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9 data bit TB81 in S1CON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB81 or a second stop bit by setting TB81 to 1 On reception the 9 data bit goes into RB81 in special function register S1CON while the stop bit is ignored Mode B 8 bit UART variable baud rate 10 bits are transmitted through TXD1 or received through RXD1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB81 in special function register S1CON Variable Baud Rates for Serial Interface 1 Variable baud rates for modes A and B of serial interface 1 can be derived from a dedicated baud rate generator baud rate clock 16 running timer with programmable reload register SAB 80C517 devices with stepping code or later provide a 10 bit free running timer for baud rate generation The baud rate clock baud rate is generated by a 8 bit free Mode A B baud rate 32x 2 Reload Value Watchdog Units The SAB 80C517 offers two enhanced fail safe mechanisms which allow an automatic recov ery from hardware failure or software upset programmable watchdog timer WDT variable from 512 ms up to ab
127. ates of Serial Channel 0 As already mentioned there are several possibilities to generate the baud rate clock for the serial interface 0 depending on the mode in which it is operated To clarify the terminology something should be said about the difference between baud rate clock and baud rate The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization as mentioned in the detailed description of the various operating modes in section 7 2 3 Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results in the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Semiconductor Group 54 SIEMENS On Chip Peripheral Components Mode 0 The baud rate in mode 0 is fixed oscillator frequency 12 Mode 0 baud rate Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON see figure 7 9 If SMOD 0 which is the value after reset the baud rate is 1 64 of the oscillator frequency If SMOD 1 the baud rate is 1 32 of the oscillator frequency 253MOD Mode 2 baud rate oscillator frequency Figure 7 9 Special Function Register PCON Address 874 874 SMOD IDLE PCON These bits are not used in controlling serial interface O Bit Functi
128. bed in more detail in section 5 2 Ports 0 to 8 PO to P8 are the SFR latches to port 0 to 8 respectively The port SFRs 0 to 5 are bit addressable Ports 0 to 6 are 8 bit I O ports that is in total 56 I O lines which may be used as general purpose ports and which provide alternate output functions dedicated to the on chip peripherals of the SAB 80C517 Port 7 8 bit and port 8 4 bit are general purpose input ports and have no internal latch That means these port lines are used for the 12 multiplexed input lines of the A D converter but can also be used as digital inputs P7 P8 are the associated SFRs when the digital value is to be read by the CPU Both ports can be read only You can find more about the ports in section 7 1 parallel 1 0 Semiconductor Group 25 SIEMENS Memory Organization Peripheral Control Data and Status Registers Most of the special function registers are used as control status and data registers to handle the on chip peripherals In the special function register table the register names are organized in groups and each of these groups refer to one peripheral unit More details on how to program these registers are given in the descriptions of the following peripheral units Unit Symbol Section Ports 7 1 Serial channels 7 2 Timer 0 1 7 3 A D converter ADC 7 4 Compare capture unit CCU 7 5 Arithmetic unit MUL DIV unit MDU 7 6 Power saving cont
129. bit is the last instruction before entering the idle mode SD When set the slow down mode is enabled GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting the power down mode is enabled IDLE Idle mode enable bit When set starting the idle mode is enabled Semiconductor Group 138 SIEMENS On Chip Peripheral Components 7 7 2 Power Down Mode In the power down mode the on chip oscillator is stopped Therefore all functions are stopped only the contents of the on chip RAM and the SFR s are held The port pins controlled by their port latches output the values that are held by their SFR S The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode when enabled the clockout signal P1 6 CLKOUT will stop at low level ALE and PSEN are held at logic low level see table 7 13 If the power down mode is to be used the pin PE SWD must be held low Entering the power down mode is done by two consecutive instructions immediately following each other The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 The following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS will not initiate the power down mode Bit PDE and PDS will automatically
130. ce a special write sequence selects an operation The MDU monitors the whole write and read out sequence to ensure that the CPU has fetched the result correctly and was not interrupted by another calculation task See section 7 6 4 The Error Flag Thus a complete operation lasts from writing the first byte of the operand in phase 1 until reading the last byte of the result in phase 3 7 6 2 Multiplication Division The general mechanism to start an MDU activity has been described above The following description of the write and read sequences adds to the information given in the table below where the write and read operations necessary for a multiplication or division are listed Table 7 11 Programming the MDU for Multiplication and Division Operation 32Bit 16Bit 16Bit 16Bit 16Bit x 16Bit First Write D endL MDO D endL MDO M andL MD1 D end MD1 D enaH MD4 MD2 D end D endH MD4 D orL MD1 M andH MD4 D orL Last Write MD5 D orH MD5 D orH MD5 M orH First Read MDO QuoL MDO QuoL MDO PrL MD1 Quo MD1 QuoH MD1 MD2 Quo MD4 RemL MD2 MD4 RemL Last Read MD5 RemH MD5 RemH PrH Semiconductor Group 128 SIEMENS On Chip Peripheral Components Write Sequence The first and the last write operation in phase one are fixed for every calculation of the MDU All write operations inbetween determine the type of MDU calculation A write to MDO is the first tra
131. ciated Memory Spaces Addressing Modes Associated Memory Spaces Register addressing RO through R7 of selected register bank ACC B CY Bit DPTR Direct addressing Lower 128 bytes of internal RAM special function registers Immediate addressing Program memory Register indirect addressing Internal RAM R1 RO SP external data memory R1 RO DPTR Base register plus index register addressing Program memory DPTR A PC A Register Indirect Addressing Register indirect addressing uses the contents of either RO or R1 in the selected register bank as a pointer to locations in a 256 byte block the 256 bytes of internal RAM or the lower 256 bytes of external data memory Note that the special function registers are not accessible by this method The upper half of the internal RAM can be accessed by indirect addressing only Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16 bit data pointer Execution of PUSH and POP instructions also uses register indirect addressing The stack may reside anywhere in the internal RAM Base Register plus Index Register Addressing Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register DPTR or PC and index register ACC This mode facilitates look up table accesses Boolean Processor The Boolean processor is a bit
132. cription SETB sets the indicated bit to one SETB can operate on the carry flag or any directiy addressable bit No other flags are affected Example The carry flag is cleared Output port 1 has been written with the value 34 001101005 The instructions SETB C SETB 1 0 will leave the carry flag set to 1 and change the data output on port 1 to 5 001101015 SETB C Operation SETB C 1 Encoding 11010011 Bytes 1 Cycles 1 SETB bit Operation SETB bit 1 Encoding 1101 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 240 SIEMENS Instruction Set SJMP rel Function Description Example Operation Encoding Bytes Cycles Short jump Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it The label RELADR is assigned to an instruction at program memory location 01234 The instruction SJMP RELADR will assemble into location 01004 After the instruction is executed the PC will contain the value 01234 Note Under the above conditions the instruction following SUMP will be at 1024 Therefore the displacement byte of the instruction will be the relative offset 01
133. ction 4 4 the stack can be located anywhere in the whole internal data memory address space The stack depth is limited only by the internal RAM available 256 byte maximum However pay attention to the fact that the stack is not overwritten by other data and vice versa External Data Memory Figure 4 2 and 4 3 contain memory maps which illustrate the internal external data memory To address data memory external to the chip the MOVX instructions in combination with a 16 bit datapointer or an 8 bit general purpose register are used Refer to chapter 9 Instruction Set or 5 External Bus Interface for detailed descriptions of these operations A maximum of 64 Kbytes of external data memory can be accessed by instructions using a 16 bit address The datapointer structure in the SAB 80C517 deserves special attention since it consists of eight 16 bit registers which can be alternatively selected as datapointers See section 4 4 and chapter 5 for further details Shared Address Location FFFF Upper Special 28 Bytes Function Internal Registers Externa RAM External Data Memory Lower 128 Bytes Internal RAM Internal External 1 0 Program Memory Data Medion Direct Byte d 2 Addressing Addressing MCB00078 Figure 4 2 Data Memory SFR Address Spaces Semiconductor Group 18 SIEMENS Memory Organization
134. ction Set Summary Mnemonic Description Byte Cycle Arithmetic Operations ADD A Rn Add register to accumulator 1 1 ADD A direct Add direct byte to accumulator 2 1 ADD A Ri Add indirect RAM to accumulator 1 1 ADD A data Add immediate data to accumulator 2 1 ADDC A Rn Add register to accumulator with carry flag 1 1 ADDC A direct Add direct byte to A with carry flag 2 1 ADDC A Ri Add indirect RAM to A with carry flag 1 1 ADDC A data Add immediate data to A with carry flag 2 1 A Rn Subtract register from A with borrow 1 1 SUBB Adirect Subtract direct byte from A with borrow 2 1 SUBB A Ri Subtract indirect RAM from A with borrow 1 1 SUBB A data Subtract immediate data from A with borrow 2 1 INC A Increment accumulator 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 1 INC Ri Increment indirect RAM 1 1 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 1 DEC QRi Decrement indirect RAM 1 1 INC DPTR Increment data pointer 1 2 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 4 DA A Decimal adjust accumulator 1 1 Semiconductor Group 251 SIEMENS Instruction Set Instruction Set Summary cont d Mnemonic Description Byte Cycle Logic Operations A
135. ction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog Semiconductor Group 142 SIEMENS On Chip Peripheral Components The reload register WDTREL can be written to at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software Sede WDT Reset Request WDTH i IPO 0A9 qos External HW Reset PE SWD WDTREL 00788 Figure 7 58 Block Diagram of the Programmable Watchdog Timer Figure 7 59 Special Function Register WDTREL 086 Watchdog timer reload register WDTREL Bit Function WDTREL 7 Prescaler select bit When set the watchdog is clocked through an additional divide by 16 prescaler see figure 7 58 WDTREL 6 Seven bit reload value for the high byte of the watchdog timer This to value is loaded to the WDT when a refresh is triggered by a consecutive WDTREL O setting of bits WDT and SWDT Semiconductor Group 143 SIEMENS On Chip Peripheral Components Watchdog Reset and Watchdog Status Flag If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7 The duration
136. ctively The instruction sequence POP DPH POP DPL will leave the stack pointer equal to the value 304 and the data pointer set to 01234 At this point the instruction POP SP will leave the stack pointer set to 204 Note that in this special case the stack pointer was decremented to 2 before being loaded with the value popped 205 Operation POP direct lt SP SP SP 1 Encoding 110110000 direct address Bytes 2 Cycles 2 Semiconductor Group 232 SIEMENS Instruction Set PUSH direct Function Description Example Operation Encoding Bytes Cycles Push onto stack The stack pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer Otherwise no flags are affected On entering an interrupt routine the stack pointer contains 094 The data pointer holds the value 0123 The instruction sequence PUSH DPL PUSH will leave the stack pointer set to and store 234 and 014 in internal RAM locations and OBy respectively PUSH SP SP 1 SP direct 1100 0000 direct address 2 2 Semiconductor Group 233 SIEMENS Instruction Set RET Function Return from subroutine Description pops the high and low order bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at
137. ctor Group 180 SIEMENS Instruction Set ADDC A lt src byte gt Function Add with carry Description ADDC simultaneously adds the byte variable indicated the carry flag and the accumulator contents leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 1100001 1g and register 0 holds 10101010p with the carry flag set The instruction ADDC A RO will leave 01101110p in the accumulator with AC cleared and both the carry flag and OV set to 1 ADDC A Rn Operation ADDC lt A Rn Encoding 0011 14rrr Bytes 1 Cycles 1 ADDC A direct Operation Encoding Bytes Cycles ADDC lt A direct 00110101 direct address 2 1 Semiconductor Group 181 SIEMENS Instruction Set ADDC A Ri Operation ADDC
138. d 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input I9 Capacitive loading on ports 0 and 2 may cause the Voy on ALE and to momentarily fall below the 0 9 Vcc specification when the address lines are stabilizing 3 Power down pp is measured with all output pins disconnected EA RESET Port 0 Port 7 Port 8 XTAL1 N C XTAL2 Vas VAGND N C VAREF PE SWD OWE Icc active mode is measured with all output pins disconnected XTAL2 driven with clock signal according to the figure below XTAL1 N C EA OWE PE SWD Port 0 Port 7 Port 8 RESET Vas would be slightly higher if a crystal oscillator is used gi kc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with clock signal according to the figure below XTAL1 N C RESET OWE Port 0 Port 7 Port 8 Voc EA PE SWD Icc slow down mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with clock signal according to the figure below XTAL N C Port 7 Port 8 EA PE SWD 6 Icc max at other frequencies is given by active mode 3 1 fosc 3 0 idle mode 1 0 fosc 3 0 Where fosc is the oscillator frequency in MHz Icc values
139. d it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come from the right 1 s shift out to the left When the start bit arrives at the leftmost position in the shift register which is a 9 bit register it flags the RX control block to do one last shift load SOBUF S1BUF and RB80 RB81 and set RIO RI1 The signal to load SOBUF S1BUF and RB80 RB81 and to set RIO RI1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RIO RI1 0 and 2 either SM20 SM21 0 or the received 9th data bit 1 If either one of these two conditions is not met the received frame is irretrievably lost and RIO RI1 is not set If both conditions are met the received 9th data bit goes into RB80 RB81 the first 8 data bits go into SOBUF S1BUF One bit time later no matter whether the above conditions are met or not the unit goes back to look for a 1 to 0 transition at the RxDO RxD1 input Note that the value of the received stop bit is irrelevant to SOBUF S1BUF RB80 RB81 or RIO RI1 Semiconductor Group 69 SIEMENS On Chip Peripheral Components Internal Bus RXDO 5 P3 0 Output Function Start Shift uin fi T m TX Control 36 TX Clock was E F x P3 1 Serial gt opi d unction Interrupt Clock RENO RIO RIO RIO g Start Receive RX Control RX Clock 4 4 4 4 4 4 1 0 Shift z RXDO i i
140. d 17 three byte instructions The instruction opcode format consists of a function mnemonic followed by a destination source operand field This field specifies the data type and addressing method s to be used Like all other members of the 8051 family the SAB 80C517 can be programmed with the same instruction set common to the basic member the SAB 8051 Thus the SAB 80C517 is 100 software compatible to the SAB 8051 and may be programmed with 8051 assembler or high level languages 9 1 Addressing Modes The SAB 80C517 uses five addressing modes register direct immediate register indirect base register plus index register indirect Table 9 1 summarizes the memory spaces which may be accessed by each of the addressing modes Register Addressing Register addressing accesses the eight working registers RO R7 of the selected register bank The least significant bit of the instruction opcode indicates which register is to be used ACC B DPTR and CY the Boolean processor accumulator can also be addressed as registers Direct Addressing Direct addressing is the only method of accessing the special function registers The lower 128 bytes of internal RAM are also directly addressable Immediate Addressing Immediate addressing allows constants to be part of the instruction in program memory Semiconductor Group 169 SIEMENS Instruction Set Table 9 1 Addressing Modes and Asso
141. d baud rate generator for baud rate generation in both operating modes see figure 7 14 This baud rate generator consists of a free running 8 bit timer with fosc 2 input frequency The timer is automatically reloaded at overflow by the contents of register S1REL see figure 7 15 The timer must be started by writing the desired reload value to register S1REL The baud rate in operating modes A and B can be determined by following formula oscillator frequency Mode A B baud rate 32 x 256 STREL At 12 MHz oscillator frequency a baud rate range from about 1 5 kbaud up to 375 kbaud is covered Using the fast baud rates offers the same functionality as the operating mode 2 in serial interface 0 with its fixed baud rates Semiconductor Group 63 SIEMENS On Chip Peripheral Components Phase 2 CLK fosc 2 Baud Rate Clock 8 Bit Timer Overflow MCS01830 Figure 7 14 Baud Rate Generator for Serial Interface 1 Figure 7 15 Special Function Register S1REL Address 90 Serial interface 1 reload register S1REL 8 bit reload register for baud rate generator of serial interface 1 7 2 2 4 New Baud Rate Generator for Serial Channel 1 A new baud rate generator for Serial Channel 1 which is implemented in SAB 80C517 devices with stepping code CA or later now offers a wider range of selectable baud rates Especially a baud rate of 1200 baud can be achieved now The baud r
142. d by their latches or controlled by their secondary functions depends on the status of the controller when entering idle Normally the port pins hold the logical state they had at the time idle was activated If some pins are programmed to serve their alternate functions they still continue to output during idle if the assigned function is on This applies for the compare outputs as well as for the system clock output signal and the serial interface in case the latter could not finish reception or transmission during normal operation The control signals ALE and PSEN are held at logic high levels see table 7 13 During idle as in normal operating mode the ports can be used as inputs Thus a capture or reload operation as well as an A D conversion can be triggered the timers can be used to count external events and external interrupts can be detected Semiconductor Group 136 SIEMENS On Chip Peripheral Components Table 7 13 Status of External Pins During Idle and Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power down Idle Power down ALE High Low High Low PSEN High Low High Low Port 0 Data Data Float Float Port 1 Data alternate Data Data alternate Data outputs last output outputs last output Port 2 Data Data Address Data Port 3 Data alternate Data Data alternate Data outputs last output outputs la
143. d output reacts in a predefined way either with a positive or negative transition Variation of this time stamp somehow changes the wave of a rectangular output signal at a port pin This may as a variation of the duty cycle of a periodic signal be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms In the case of the SAB 80C517 two compare modes are implemented to cover a wide range of possible applications see section 7 5 4 below In the SAB 80C517 thanks to the high number of 13 compare registers and two associated timers several timer compare register combinations are selectable In some of these configurations one of the two compare modes may be freely selected others however automatically establish a compare mode In the following the two possible modes are generally discussed This description will be referred to in later sections where the compare registers are described 7 5 4 Compare Modes of the CCU As already mentioned there are only a few compare registers with their corresponding port circuitry which are able to serve both compare modes In most cases the mode is automatically set depending on the timer which is used as time base or depending on the port which outputs the compare signal Semiconductor Group 103 SIEMENS On Chip Peripheral Components 7 5 4 1 Compare Mode 0 In mode 0 upon matching the timer and compare register contents the
144. de 16 2 19 mA 5 Power down PD 50 pA 2 5 5 V9 Notes see page 311 Semiconductor Group 309 SIEMENS SAB 80C517 80C537 A D Converter Characteristics 5 10 0 V 5 Vss 0 2 V VintaREF VintaGnp gt 1V T a 0 to 70 C for the SAB 80C517 83C537 T a 40 to 85 C for the SAB 80C517 83C537 T40 875 Parameter Symbol Limit values Unit Test Condition min typ Analog input voltage V ANPUT VAGND VAREF V 9 0 2 0 2 Analog input C 25 60 pF 7 capacitance Load time tL 2 toy us 7 Sample time ts 7 us 7 incl load time Conversion time tc 13 lus 7 incl sample time Total unadjusted error TUE 2 LSB Varner Vss 11 Internal reference error VintREFERR 30 mV 8 Supply current 5 mA 8 Notes see page 311 Semiconductor Group 310 SIEMENS SAB 80C517 80C537 Notes for pages 308 309 and 310 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and ports 1 3 4 5 and 6 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may excee
145. default values of the special function registers SFR to which they are forced during reset are listed in table 6 1 After reset is internally accomplished the port latches of ports O to 6 default in This leaves port 0 floating since it is an open drain port when not used as data address bus All other port lines ports 1 through 6 output a one 1 Ports 7 and 8 which are input only ports have no internal latch and therefore the contents of the special function registers P7 and P8 depend on the levels applied to ports 7 and 8 The contents of the internal RAM of the SAB 80C517 is not affected by a reset After power up the contents is undefined while it remains unchanged during a reset it the power supply is not turned off Semiconductor Group 36 SIEMENS System Reset Table 6 1 Register Contents Register Contents PC 0000H IENO IEN1 00H ACC 00H IEN2 XXXX 00X0p ADCONO 00H IPO 00H IP1 XX00 0000p ADCON 1 XXXX 0000p IRCON 00H ADDAT 00H MDO 5 XXH ARCON 0XXX 6 OFFy B 00H PCON 00H CCL1 4 00H PSW 00H CCH1 4 00H SOBUF S1BUF 0 00H SOCON 00H CC4EN 00H S1CON 0X00 0000p CMEN 00H S1REL 00H CMLO 7 00H SP 07H 7 00H TCON 00H CMSEL TLO THO 00H CRCL CRCH 00H TL1 TH1 00H CTCON 00008 TL2 TH2 00H CTRELL CTRELH 00H TMOD 00H DAPR 00H T2CON DPSEL XXXX X000p WDTREL 00H 7 0000H
146. dos 40 YsL 1 Port SUUCINGS y suvle dos RR SU s Sa E ACE Rs S eoe 40 7 1 2 Port 0 and Port 2 used as Address Data Bus 45 7 1 3 Alternate Functions 46 TP 48 PE 48 7 1 4 2 Port Loading and Interfacing 49 7 1 4 8 Read Modify Write Feature of Ports 0 through 6 49 7 2 Serial Interfaces Doo ue Coles acie a db dac E o RERUMS 51 7 2 1 Serial Interface O 51 7 2 1 1 Operating Modes of Serial Interface 0 51 7 2 1 2 Multiprocessor Communication Feature 54 7 2 1 3 Baud Rates of Serial 0 54 7 2 1 4 New Baud Rate Generator for Serial Channel 0 58 fire Oel IO THO T tae dab echec aC c HA Re dice Sos aur to qi rod 61 7 2 2 1 Operating Modes of Serial Interface 1 61 Semiconductor Group 5 SIEMENS 80C517 80C537 Table of Contents Page 7 2 2 2 Multiprocessor Communication Feature 63 7 2 2 3 Baud Rates of Serial 1 63 7 2 2 4 New Baud Rate Generator for Serial Channel 1 64 7 2 3 Detailed Description of the Operating Modes 6
147. e 4 These registers are available in the CA step and later steps Semiconductor Group 23 SIEMENS Memory Organization The following paragraphs give a general overview of the special function registers and refer to sections where a more detailed description can be found Accumulator SFR Address 0E0H ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word Register PSW SFR Address 0D0H OD74 006 005 004 0D34 002 001 000 0DO CY AC FO RS1 RSO OV Fi Psw The PSW register contains program status information Bit Function CY Carry Flag AC Auxiliary carry flag for BCD operations FO General purpose user flag 0 RS1 RSO Register bank select control bits 0 0 Bank 0 selected data address 004 074 0 1 Bank 1 selected data address 08 4 0F 1 0 Bank 2 selected data address 10 17 1 1 Bank 3 selected data address 184 1FH OV Overflow flag F1 General purpose user flag 1 P Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of one bits in the accumulator i e even parity Register SFR Address The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad registe
148. e shift count which must not be 0 otherwise a normalize operation would be executed During shift zeroes come into the left or right end of the registers MDO or respectively The first machine cycle of a shift left right operation executes four shifts while all following cycles perform 6 shifts Hence a 31 bit shift takes 6 microseconds at 12 MHz Completion of both operations normalize and shift can also be controlled by the error flag mechanism described in 7 6 4 The error flag is set if one of the relevant registers MDO through MD3 is accessed before the previously commenced operation has been completed For proper operation of the error flag mechanism it is necessary to take care that the right write or read sequence to or from registers MDO to MD3 see table 7 12 is maintained Semiconductor Group 131 SIEMENS On Chip Peripheral Components Table 7 12 Programming a Shift or Normalize Operation Operation Normalize Shift Left Shift Right First write MDO least significant byte MD1 MD2 MD3 most significant byte Last write ARCON start of conversion First read MDO least significant byte MD1 MD2 Last read MD3 most significant byte 7 6 4 The Overflow Flag An overflow flag is provided for some exceptions during MDU calculations There are three cases where flag MDOV ARCON 6 is set by hardware Division by zero Multiplication with a result greater then 0000 auxiliary carry o
149. e SP should be initialized to a different location of the RAM which is not used for data storage 4 4 Special Function Registers The special function register SFR area has two important functions Firstly all CPU registers except the program counter and the four register banks reside here The CPU registers are the arithmetic registers like A B PSW and pointers like SP DPHx and DPLx Secondly a number of registers constitute the interface between the CPU and all on chip peripherals That means all control and data transfers from and to the peripherals use this register interface exclusively The special function register area is located in the address space above the internal RAM from addresses 80 to FFy All 81 special function registers of the SAB 80C517 reside here Sixteen SFRs that are located on addresses dividable by eight are bit addressable thus allowing 128 bit addressable locations within the SFR area Since the SFR area is memory mapped access to the special function registers is as easy as with the internal RAM and they may be processed with most instructions In addition if the special functions are not used some of them may be used as general scratch pad registers Note however all SFRs can be accessed by direct addressing only The special function registers are listed in the following tables where they are organized in functional groups which refer to the functional blocks of the SAB 80C517 Block names and sy
150. e accumulator with the carry flag and AC cleared but OV set Notice that 0OC9 minus 544 is 75 4 The difference between this and the above result is due to the borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB A Rn Operation Encoding Bytes Cycles SUBB lt A Rn 1001 1rrr Semiconductor Group 242 SIEMENS Instruction Set SUBB Operation Encoding Bytes Cycles SUBB Operation Encoding Bytes Cycles SUBB Operation Encoding Bytes Cycles A direct SUBB A A C direct direct address A Ri A data immediate data 1001 0101 2 1 SUBB A lt A Ri 1001 0111 SUBB lt A C data 1001 0100 2 1 Semiconductor Group 243 SIEMENS Instruction Set SWAP A Function Swap nibbles within the accumulator Description SWAP A interchanges the low and high order nibbles four bit fields of the accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected Example The accumulator holds the value 0 5 11000101p The instruction SWAP A leaves the accumulator holding the
151. e activated by a positive transition The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1 5 T2EX but only if bit EXEN is set Since the external interrupt pins INT2 to INT6 are sampled once in each machine cycle an input high or low should be held for at least 12 oscillator periods to ensure sampling If the external inter rupt is transition activated the external source has to hold the request pin low high for INT2 and INT3 if it is programmed to be negative transition active for at least one cycle and then hold it high low for at least one cycle to ensure that the transition is recognized so that the corresponding in terrupt request flag will be set see figure 8 12 The external interrupt request flags will automati cally be cleared by the CPU when the service routine is called Semiconductor Group 167 SIEMENS Interrupt System a Level Activated Interrupt Low Level Threshold P3 x INTx 1 Machine Cycle b Transition Activated Interrupt High Level Threshold Y e g P3 x INTx Low Level Threshold gt 1 Machine Cycle 1 Machine Cycle MCTO1860 Transition to be detected Figure 8 12 External Interrupt Detection 8 5 Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine
152. e duty cycle of the PWM signal is done by a variation of the contents of the compare register CMO CMO is loaded with new compare values in an high prioritized interrupt routine This makes the loading independent from other tasks running on the CPU The new compare values are loaded by a cyclic look up table routine The table is located in the ROM and contains the compare values for every sample point In our case the sine wave is synthesized by six sample points The program flow is best described by a program flow chart see figure 10 3 The following paragraphs give some additional details Main Program CCU and interrupt initialization is done according to the previous description of the CCU configuration There is no other task in this application to be done in the main program The controller is free for any other job e g I O control algorithms adapting the sine wave table etc nterrupt Service Routine The interrupt program contains the table look up routine only This routine is illustrated in figure 10 3 and performs the following two little jobs managing the table pointer loading the CMO register Semiconductor Group 261 SIEMENS Application Examples Main Program Interrupt Program Do General Initialization Fetch Byte from Table Initialize Compare Load Byte into Compare reg CMLx Initialize Interrupts Increment Table Pointer End of Table reached Wait or Do any other Task Set Tab
153. e error flag mechanism see below To start a shift or normalize operation the last write must access register ARCON Semiconductor Group 129 SIEMENS On Chip Peripheral Components Read Sequence The order in which the first three registers MDO to MD2 are read is not critical The last read from MD3 determines the end of a whole shift or normalize procedure and releases the error flag mechanism Note Any write access to ARCON triggers a shift or normalize operation and therefore changes the contents of registers to Figure 7 56 Register ARCON OEFY MDEF SLR SC 4 3 SC2 SC1 5 0 ARCON Arithmetic control register Contains control flags and the shift counter of the MDU Triggers a shift or a normalize operation in register MDO to MD3 when being written to Bit Function MDEF Error flag Indicates an improperly performed operation MDEF is set by hardware when an operation is retriggered by a write access to MDx before the first operation has been completed MDEF is automatically cleared after being read MDOV Overflow flag Exclusively controlled by hardware MDOV is set by following events division by zero multiplication with a result greater than OFFFFy SLR Shift direction bit When set shift right is performed SLR 0 selects shift left operation SC 4 Shift counter 3 When preset with 00000p nor
154. e for the present timer period Thus the CPU only changes the compare event for the next timer period since the loading of the latch is performed by the timer overflow signal of the compare timer This means for an application which uses several PWM outputs that the CPU does not have to serve every single compare line by an individual interrupt It only has to watch the timer overflow of the compare timer and may then set up the compare events of all compares for the next timer period This job may take the whole current timer period since the TOC loading prevents unintentional overwriting of the actual and prepared value in the compare latch Semiconductor Group 119 SIEMENS On Chip Peripheral Components Overflow CTF Interrupt Logic Output 4 16 Bi 168i Compare Latch 168i TOC Loadin Write to CMLx 16 Bi Compare Register CMx Figure 7 51 Compare Function of a CMx Register Assigned to the Compare Timer 1865 Figure 7 51 shows more detailed block diagram of a register connected to the compare timer It illustrates that the CPU can only access the special function register CMx the actual compare latch is however loaded at timer overflow The timer overflow signal also sets an interrupt request flag CTF in register CTCON which may be used to inform the CPU by an interrupt that a new timer cycle has started and that the compare
155. e routines by factor 5 to 10 The MDU is handled by seven registers which are memory mapped as special function registers like any other registers for peripheral control Therefore the arithmetic unit allows operations concurrently to and independent of the CPU s activity The following table describes the four general operations the MDU is able to perform Operation Result Remainder Execution Time 32bit 16bit 32bit 16bit 1 6bit 1 6bit 16bit 16bit 4 toy 16bit x 16bit 32bit 4 toy 32 bit normalize 6 toy 32 bit shift L R 6 toy 1 1 1 microsecond at 12 MHz oscillator frequency 2 The maximal shift speed is 6 shifts per machine cycle 7 6 1 Programming the MDU Operating Registers of the MDU The seven SFR of the MDU consist of registers MDO to which contain the operands and the result or the remainder resp and one control register called ARCON Thus MDO to MD5 are used twofold for the operands before a calculation has been started and for storage of the result or remainder after a calculation This means that any calculation of the MDU overwrites its operands If a program needs the original operands for further use they should be stored in general purpose registers in the internal RAM Semiconductor Group 126 SIEMENS On Chip Peripheral Components Operation of the MDU The MDU can be regarded as a special coprocessor for multiplication divi
156. ement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected The accumulator originally holds 0 The instruction sequence JNZ LABEL1 INC A JNZ LABEL2 will set the accumulator to 014 and continue at label LABEL2 JNZ lt PO 2 if A 0 then PC PC rel 0111 0000 rel address Semiconductor Group 211 SIEMENS Instruction Set JZ rel Function Description Example Operation Encoding Bytes Cycles Jump if accumulator is zero If all bits of the accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected The accumulator originally contains 01 The instruction sequence JZ LABEL1 DEC A JZ LABEL2 will change the accumulator to 004 and cause program execution to continue at the instruction identified by the label LABEL2 JZ lt PC 2 if A 0 then PC PC rel 01100000 rel address Semiconductor Group 212 SIEMENS Instruction Set addr 6 Function Description Example Operation Encoding Bytes Cycles Long call LCALL calls a subroutine l
157. er CTRELL the low byte starts the timer If the compare timer is already running a write to CTRELL again triggers an instant reload of the timer in other words restarts the timer in the cycle following the write instruction with the count being loaded to the reload registers CTRELH CTRELL Figure 7 37 Compare Timer Control Register CTCON OE1y T2PS1 CTF CLK2 CLK1 CLKO CTCON Compare timer control register Contains clock selection bits for the compare timer the compare timer overflow flag and the control bit for the timer 2 prescaler Bit Function CLK2 CLK1 Compare timer input clock selection See table below CLKO CTF Compare timer overflow flag Bit is cleared by hardware If the compare timer interrupt is enabled CTF 2 1 will cause an interrupt T2PS1 Prescaler select bit for timer 2 T2PS1 must be 0 for the counter operation of timer 2 CLK2 CLK1 CLKO Function Compare timer input clock is fog 2 Compare timer input clock is fosc 4 Compare timer input clock is fosc 8 Compare timer input clock is fosc 16 Compare timer input clock is 64 Compare timer input clock is fosc 128 0 1 0 1 0 Compare timer input clock is fosc 32 1 0 1 CO 1O OoO o O oO gt gt olo Compare timer input clock is 256 Semiconductor Group 102 SIEMENS On Chip Peripheral Comp
158. ernal memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents see also chapter 7 1 2 and chapter 5 for more details about the external bus interface Digital Analog Input Ports Ports 7 and 8 are available as input ports only and provide for two functions When used as digital inputs the corresponding SFR s P7 and 8 contain the digital value applied to port 7 and port 8 lines When used for analog inputs the desired analog channel is selected by a three bit field in SFR ADCONO or a four bit field in SFR ADCON1 as described in section 7 4 Of course it makes no sense to output a value to these input only ports by writing to the SFR s P7 or P8 this will have no effect If a digital value is to be read the voltage levels are to be held within the input voltage specifications V V Since P7 and P8 are not bit addressable registers all input lines of P7 or P8 are read at the same time by byte instructions Semiconductor Group 40 SIEMENS On Chip Peripheral Components Nevertheless it is possible to use ports 7 and 8 simultaneously for analog and digital input However care must be taken that all bits of P7 or P8 that have an undetermined value caused by their analog function are masked In order to guarantee a high quality A D conversion digital input lines of p
159. es MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Ooeration Encoding Bytes Cycles direct Ri MOV direct lt Ri 1000 0111 direct address direct data direct address immediate data direct address Semiconductor Group MOV direct lt data 01110101 Ri A MOV Ri lt 1111 0111 1 1 Ri direct MOV Ri lt direct 10100111 2 218 SIEMENS Instruction Set MOV Ri data Operation MOV Ri lt data Encoding 0111 0111 immediate data Bytes 2 Cycles 1 Semiconductor Group 219 SIEMENS Instruction Set MOV lt dest bit gt lt src bit gt Function Move bit data Description The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected Example The carry flag is originally set The data present at input port 3 is 11000101p The data previously written to output port 1 is 354 001101016 MOV P1 3 C MOV C P3 3 MOV P1 2 C will leave the carry cleared and change port 1 to 394 00111001p MOV C bit Operation MOV C bit
160. es can be activated as described in the following sections The watchdog timer has to be started by software if system protection is desired When left unconnected the pin PE SWD is pulled to high level by a weak internal pullup This is done to provide system protection by default The logic level applied to pin PE SWD can be changed during program execution in order to allow or block the use of the power saving modes without any effect on the on chip watchdog circuitry the watchdog timer is started only if PE SWD is on high level at the moment when reset is released a change at PE SWD during program execution has no effect on the watchdog timer this only enables or disables the use of the power saving modes A change of the pin s level is detected in state 3 phase 1 A Schmitt trigger is used at the input to reduce susceptibility to noise In addition to the hardware enable disable of the power saving modes a double instruction sequence which is described in the corresponding sections is necessary to enter power down and idle mode The combination of all these safety precautions provide a maximum of system protection Semiconductor Group 135 SIEMENS On Chip Peripheral Components Application Example for Switching Pin PE SWD For most applications in noisy environments components external to the chip are used to give warning of a power failure or a turn off of the power supply These circuits could be used to control the PE SW
161. ess data bus port 0 uses a pullup FET as shown in figure 7 4 a When a 16 bit address is used port 2 uses the additional strong pullups p1 to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Read Latch Control Voc Internal Pull Up Arrangement Pin MCS01826 Read Pin Figure 7 4 b Port 2 Circuitry Semiconductor Group 45 SIEMENS On Chip Peripheral Components 7 1 3 Alternate Functions Several pins of ports 1 3 4 5 and 6 are multifunctional They are port pins and also serve to implement special features as listed in table 7 1 Figure 7 5 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pull down FET is on and the port pin is stuck at 0 This does not apply to ports 1 0 to 1 4 and ports 5 0 to 5 7 when operated in compare output mode refer to section 7 5 3 for details After reset all port latches contain ones 1 Alternate V Output a bas Internal Latch Pull Up Arrangement Pin Int Bus P Write v to Latch MCS01827 Read Alternate Pin Input Function Figure 7 5 Circ
162. f the lower 16bit Start of normalizing if the most significant bit of is set MD3 7 1 Any operation of the MDU which does not match the above conditions clears the overflow flag Note that the overflow flag is exclusively controlled by hardware It cannot be written to 7 6 5 The Error Flag An error flag bit MDEF in register ARCON figure 7 56 is provided to indicate whether one of the arithmetic operations of the MDU multiplication division normalize shift left right has been restarted or interrupted by a new operation This can possibly happen e g when an interrupt service routine interrupts the writing or reading sequence of the arithmetic operation in the main program and starts a new operation Then the contents of the corresponding registers are indeterminate they would normally show the result of the last operation executed Semiconductor Group 132 SIEMENS On Chip Peripheral Components In this case the error flag can be used to indicate whether the values in the registers MDO to MD5 are the expected ones or whether the operation must be repeated For a multiplication division the error flag mechanism is automatically enabled with the first write instruction to MDO phase 1 According to the above described programming sequences this is the first action for every type of calculation The mechanism is disabled with the final read instruction from MD3 or MD5 phase 3 Every instruction which rewrites MDO
163. feature in mode A If SM21 is set to 1 will not be activated if the received 9th data bit RB81 is 0 In mode B if SM21 1 will not be activated if a valid stop bit was not received REN1 Receiver enable of interface 1 Enables serial reception Set by software to enable reception Cleared by software to disable reception TB81 Transmitter bit 8 of interface 1 Is the 9th data bit that will be transmitted in mode A Set or cleared by software as desired RB81 Receiver bit 8 of interface 1 Is the 9th data bit that was received in mode In mode B if SM21 0 RB81 is the stop bit that was received Transmitter interrupt of interface 1 Is the transmit interrupt Set by hardware at the beginning of the stop bit in any serial transmission Must be cleared by software Receiver interrupt of interface 1 Is the receive interrupt flag Set by hardware at the halfway through the stop bit time in any serial reception Must be cleared by software Figure 7 13 Special Function Register S1BUF Address 9CH Serial interface 1 buffer register S1BUF Receive and transmit buffer of serial interface 1 Writing to S1BUF loads the transmit register and initiates transmission Reading out S1BUF accesses a physically separate receive register Semiconductor Group 62 SIEMENS On Chip Peripheral Components 7 2 2 2 Multiprocessor Communication Feature Mode A of the serial interface 1
164. ge of approx 200 300 mV at the inputs during this time has no effect Semiconductor Group 91 SIEMENS On Chip Peripheral Components Conversion time fc The conversion time includes the sample and load time Thus fc is the total time required for one conversion After the load time and sample time have elapsed the conversion itself is performed during the rest of tc In the last machine cycle the converted result is moved to ADDAT the busy flag BSY is cleared before The A D converter interrupt is generated by bit IADC in register IRCON IADC is already set some cycles before the result is written to ADDAT The flag IADC is set before the result is available in ADDAT because the shortest possible interrupt latency time is taken into account in order to ensure optimal performance Thus the converted result appears at the same time in ADDAT when the first instruction of the interrupt service routine is executed Similar considerations apply to the timing of the flag BSY where usually a JB BSY instruction is used for polling If a continuous conversion is established the next conversion is automatically started in the machine cycle following the last cycle of the previous conversion One Machine Cycle BSY te E Interrupt Request Result is written I Flag IADC is Set into ADDAT MCTO1843 MOV DAPR xxH Internal Start or P6 0 ADST 0 External Start
165. grammable watchdog timer WDT with variable time out period from 512 microseconds up to approx 1 1 seconds at 12 MHz The SAB 80C517 s WDT is a superset of the SAB 80515 watchdog An oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into the reset state if the on chip oscillator fails 7 8 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this periodical refresh of the watchdog timer an internal hardware reset will be initiated The software can be designed so that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the SAB 80C517 is a 15 bit timer which is incremented by a count rate of either foycre 2 OF foycre 32 fosc 12 That is the machine clock is divided by a series arrangement of two prescalers a divide by two and a divide by 16 prescaler see figure 7 58 The latter is enabled by setting bit WDTREL 7 Immediately after start see next section for the start procedure the watchdog timer is initialized to the reload value programmed to WDTREL O WDTREL 6 After an external HW or HWPD reset an oscillator power on reset a watchdog timer reset register WDTREL is cleared to 00 The lower seven bits of WDTREL can be
166. haracteristics ALE pulse width fLHLL 127 2 tci cL 40 ns Address setup to ALE tAVLL 53 30 ns Address hold after ALE fLLAx 48 teLcL 35 ns ALE to valid fLLIV 233 4tctc_ 100 ns instruction in ALE to PSEN 58 cLCL 25 ns PSEN pulse width p pH 215 3 cLCL Z 35 ns PSEN to valid 150 SICLCL 100 ns instruction in Input instruction hold tPXIX 0 0 ns after PSEN Input instruction float tpxpx 63 20 ns after Address valid after tpxay 75 8 ns PSEN Address to valid 302 0 115 jns instruction in Address float to PSEN tazpL ns Interfacing the 80C517 to devices with float times up to 75 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 313 SIEMENS SAB 80C517 80C537 AC Characteristics cont d Parameter Symbol Limit Values Unit 12 MHz Clock Variable Clock 1 t 3 5 MHzto 12 MHz min max min max External Data Memory Characteristics RD pulse width 400 100 ns WR pulse width tWLWH 400 100 ns Address hold after ALE fLLAX2 132 2tctc_ 30 ns RD to valid instr in RLDV 252 165 ns Data hold after RD tRHDX 0 0 ns Data floa
167. has a number of general purpose 16 bit timer counters timer 0 timer 1 timer 2 and the compare timer timer 2 and the compare timer are discussed separately in section 7 5 Compare Capture Unit Timer counter 0 and 1 are fully compatible with timer counters 0 and 1 of the SAB 8051 and can be used in the same operating modes Timer counter 0 and 1 which are discussed in this section can be configured to operate either as timers or event counters n timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscillator frequency n counter function the register is incremented in response to a 1 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 and P3 5 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least
168. has a special provision for multiprocessor communication In this mode 9 data bits are received The 9th bit goes into RB81 Then follows a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt i e the request flag is set will be activated only if RB81 1 This feature is enabled by setting bit SM21 in S1CON A way to use this feature in multiprocessor communications is as follows If the master processor wants to transmit a block of data to one of the several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM21 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM21 bit and prepare to receive the data bytes that will be coming After having received a complete message the slave is setting SM21 again The slaves that were not addressed leave their SM21 set and go on about their business ignoring the incoming data bytes In mode B SM21 can be used to check the validity of the stop bit If SM21 1 in mode B the receive interrupt will not be activated unless a valid stop bit is received 7 2 2 3 Baud Rates of Serial Channel 1 As already mentioned serial interface 1 uses its own dedicate
169. he corresponding output lines Table 3 CCU Configuration Assigned Timer Compare Register Compare Output at Possible Modes Timer 2 CRCH CRCL P1 0 INT3 CCO Comp mode 0 1 Reload CC1H CC1L P1 0 INT4 CC1 Comp mode 0 1 CC2H CC2L P1 0 INT5 CC2 Comp mode 0 1 CC3H CC3L P1 0 INT6 CC3 Comp mode 0 1 CC4H CC4L P1 0 INT2 CC4 Comp mode 0 1 CC4H CC4L P5 0 CCMO Comp mode 1 CC4H CC4L P5 7 CCM7 Comp mode 1 CMOH CMOL P4 0 CMO Comp mode 1 CM7H CM7L 4 7 7 1 Compare timer CMOH CMOL P4 0 CMO Comp mode 0 with add latches CM7H CM7L P4 7 CM7 Comp mode 0 with shadow latches Semiconductor Group 289 SIEMENS SAB 80C517 80C537 16 Bit Reload CTREL Compare Bit a Timer 0 00007 TU Max Clock fosc 2 CMSEL Timer 11 P e C r Capt Com 4 CC4 Capt Com 3 CC3 Capt Com 2 CC2 Capt C 37 apt Com 1 CC1 16 Rel Capt MCB00781 Figure 5 Block Diagram of the Compare Capture Unit Semiconductor Group 290 SIEMENS SAB 80C517 80C537 Compare In the compare mode the 16 bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register If the count value in the timer registers matches one of the stored val
170. he frequency greatly reduces power consumption The Idle Mode The CPU is gated off from the oscillator but all peripherals are still supplied by the clock and able to work The Power Down Mode Operation of the SAB 80C517 is stopped the oscillator is turned off This mode is used to save the contents of the internal RAM with a very low standby current All of these modes are entered by software Special function register PCON power control register address is 87 is used to select one of these modes Hardware Enable for Power Saving Modes A dedicated Pin PE SWD of the SAB 80C517 allows to block the power saving modes Since this pin is mostly used in noise critical application it is combined with an automatic start of the Watchdog Timer see there for further description PE SWD logic high level Using of the power saving modes is not possible The instruction sequences used for entering of these modes will not affect the normal operation of the device PE SWD logic low level All power saving modes can be activated by software When left unconnected Pin PE SWD is pulled to high level by a weak internal pullup This is done to provide system protection on default The logic level applied to pin PE SWD can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on chip watchdog circuitry Power Down Mode The power down mode is entered by two c
171. he input pins Register 0 contains 7 011111116 Internal RAM locations 7 and 7 contain 00 and 40 respectively The instruction sequence DEC RO DEC RO DEC RO will leave register 0 set to 7 and internal RAM locations 7 and 7F1 set to OFFy and 3Fy DEC lt A 1 0001 0100 DEC Rn lt Rn 1 0 0 O 1 1rrr Semiconductor Group 197 SIEMENS Instruction Set DEC direct Operation DEC direct lt direct 1 Encoding 000110101 direct address Bytes 2 Cycles 1 DEC Ri Operation DEC Ri lt Ri 1 Encoding 000110111 Bytes 1 Cycles 1 Semiconductor Group 198 SIEMENS Instruction Set DIV AB Function Description Example Operation Encoding Bytes Cycles Divide DIV AB divides the unsigned eight bit integer in the accumulator by the unsigned eight bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception If had originally contained 00 the values returned in the accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The accumulator contains 251 OFBy or 111110115 and B contains 18 124 or 00010010p The instruction DIV AB will leave 13 in the accumulator
172. he result to the location of the first operand ORL performs bitwise logical OR of two source operands for both bit and byte operands and returns the result to the location of the first operand XRL performs logical Exclusive OR of two source operands byte operands and returns the result to the location of the first operand 9 2 4 Control Transfer There are three classes of control transfer operations unconditional calls returns jumps conditional jumps and interrupts All control transfer operations some upon a specific condition cause the program execution to continue a non sequential location in program memory Semiconductor Group 174 SIEMENS Instruction Set Unconditional Calls Returns and Jumps Unconditional calls returns and jumps transfer control from the current value of the program counter to the target address Both direct and indirect transfers are supported ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address ACALL is a 2 byte instruction used when the target address is in the current 2K page LCALL is a 3 byte instruction that addresses the full 64K program space In ACALL immediate data i e an 11 bit address field is concatenated to the five most significant bits of the PC which is pointing to the next instruction If ACALL is in the last 2 bytes of a 2K page then the call will be made to the next page since the PC will have been i
173. hen configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 7 4 a is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to th port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port 0 is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data V Control Read Latch Pin 501825 Figure 7 4 a Port 0 Circuitry Semiconductor Group 44 SIEMENS On Chip Peripheral Components 7 1 2 Port 0 and Port 2 used as Address Data Bus As shown in figures 7 4 a and 7 4 b the output drivers of ports 0 and 2 can be switched to an internal address or address data bus for use in external memory accesses In this application they cannot be used as general purpose 1 0 even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the P2 SFR remains unchanged while the PO SFR has 1 s written to it Being an addr
174. heral Control All on chip peripheral components I O ports serial interfaces timers compare capture registers the interrupt controller and the A D converter are handled and controlled by the so called special function registers These registers constitute the easy to handle interface with the peripherals This peripheral control concept as implemented in the SAB 8051 provides the high flexibility for further expansion as done in the SAB 80C517 Moreover some of the special function registers like accumulator Bregister program status word PSW stack pointer SP and the data pointers DPTR are used by the CPU and maintain the machine status Semiconductor Group 12 SIEMENS Central Processing Unit 3 Central Processing Unit 3 1 General Description The CPU Central Processing Unit of the SAB 80C517 consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the cont
175. hes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored too as shown in the following table 8 2 Semiconductor Group 165 SIEMENS Interrupt System Table 8 2 Interrupt Source and Vectors Interrupt Request Flags Interrupt Vector Address Interrupt Source IEO 00034 External interrupt O TFO 000BH Timer 0 overflow IE1 0013H External interrupt 1 TF1 001 Timer 1 overflow RIO TIO 0023H Serial channel 0 TF2 EXF2 002 Timer 2 overflow ext reload IADC 0043H A D converter IEX2 004By External interrupt 2 IEX3 0053H External interrupt 3 IEX4 005 External interrupt 4 IEXS 0063H External interrupt 5 IEX6 006BH External interrupt 6 RH TH 0083 Serial channel 1 CTF 009 Compare timer overflow Execution proceeds from that location until the instruction is encountered The instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted
176. hitecture It is a fully compatible member of the Siemens SAB 8051 80C51 microcontroller family being a significantly enhanced SAB 806515 The SAB 80C517 is therefore 100 96 compatible with code written for the SAB 80C515 CPU Having an 8 bit CPU with extensive facilities for bit handling and binary BCD arithmetics the SAB 80C517 is optimized for control applications With a 12 MHz crystal 5896 of the instructions execute in 1 us Being designed to close the performance gap to the 16 bit microcontroller world the SAB 80C517 s CPU is supported by a powerful 32 16 bit arithmetic unit and a more flexible addressing of external memory by eight 16 bit datapointers Memory Organisation According to the SAB 8051 architecture the SAB 80C517 has separate address spaces for program and data memory Figure 2 illustrates the mapping of address spaces Shared Address Location Upper Special 28 Bytes Function Internal Registers External External Data Memory Lower 128 Bytes Internal RAM Internal External 1 0 Program Memory pala Miro Direct Byte ine Addressing Addressing MCB00078 Figure 2 Memory Mapping Semiconductor Group 280 SIEMENS SAB 80C517 80C537 Program Memory The SAB 80C517 has 8 KByte of on chip ROM while the SAB 80C537 has no internal ROM The program memory can externally be expanded up to 64 Kbyte
177. hown in figure 7 22 0 opt TLO THO TFO Interrupt A 8 Bits 8 Bits TO Pin Control INTO Pin MCS01838 Figure 7 22 Timer Counter 0 1 Mode 1 16 Bit Timer Counter Semiconductor Group 80 SIEMENS On Chip Peripheral Components 7 3 3 Mode2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 7 23 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged m on 0 Interrupt TO Pin Jone Control Gate INTO Pin MCS01839 Figure 7 23 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 81 SIEMENS On Chip Peripheral Components 7 3 4 Mode 3 has different effects on timer 0 and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two separate counters The logic for mode 3 on timer 0 is shown in figure 7 24 TLO uses the timer 0 control bits C T GATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be
178. ibed in the next section allows the CPU to control the compare output transitions directly The assignment of the eight registers CMO to CM7 to either timer 2 or to the compare timer is done by an 8 channel 2 1 multiplexer shown in the general block diagram in figure 7 33 The multiplexer can be programmed by the corresponding bits in special function register CMSEL see figure 7 48 The compare function itself can individually be enabled in the SFR CMEN see figure 7 49 Note however that these register are not bit addressable which means that the value of single bits can only be changed by AND ing or OR ing the register with a certain mask Semiconductor Group 116 SIEMENS On Chip Peripheral Components Figure 7 48 Special Function Register CMSEL OF7y CMSEL 7 CMSEL 6 CMSEL 5 CMSEL 4 CMSEL 3 CMSEL 2 CMSEL 1 CMSEL 0 CMSEL Contains select bits for registers CMO to CM7 When set CMLx CMHx are assigned to the compare timer and compare mode is enabled The compare registers are assigned to timer 2 if CMSELx 0 In this case compare mode 1 is selected Bit Function CMSEL 7 Select bit for CM7 CMSEL 6 Select bit for CM6 CMSEL 5 Select bit for CM5 CMSEL 4 Select bit for CM4 CMSEL 3 Select bit for CM3 CMSEL 2 Select bit for CM2 CMSEL 1 Select bit for CM1 CMSEL O Select bit for CMO Figure 7 49 Special Function Register CMEN OF6y CMEN 7 CME
179. ication the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in figure 7 66 It is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 30 pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications It a ceramic resonator is used C and C are normally selected to be of somewhat higher values typically 47 pF We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors Semiconductor Group 148 SIEMENS On Chip Peripheral Components To drive the SAB 80 C517 with an external clock source the external clock signal is to be applied to XTAL2 as shown in figure 7 67 XTAL1 has to be left unconnected A pullup resistor is suggested to increase the noise margin but is optional if Voy of the driving gate corresponds to the specification of XTAL2 S To Internal a Timing Circuitry vs SAR popa 1 J XTAL2 1 L MCS01868 Quartz Crystal or Ceramic Resonator Figure 7 66 On Chip Oscillator Circuitry External Oscillator XTAL2 Signal XTAL1 501869 Figure 7
180. icient to load only the low byte See figure 7 52 block diagram of a CMx register connected to timer 2 Semiconductor Group 122 SIEMENS On Chip Peripheral Components Compare Timer 2 Interrupt Logic Output Bit re Compa Write to Register Latch CMx MCAO1 866 Figure 7 52 CMx Register Assigned to Timer 2 7 5 6 Capture Function in the CCU Each of the four compare capture registers CC1 to CC4 and the CRC register can be used to latch the current 16 bit value of the timer 2 registers TL2 and TH2 Two different modes are provided for this function In mode 0 an external event latches the timer 2 contents to a dedicated capture register In mode 1 a capture will occur upon writing to the low order byte of the dedicated 16 bit capture register This mode is provided to allow the software to read the timer 2 contents on the In mode 0 the external event causing a capture is for CC registers 1 to 3 a positive transition at pins CC1 to CC3 of port 1 for the CRC and CC4 register a positive or negative transition at the corresponding pins depending on the status of the bits ISFR and I2FR in SFR T2CON If the edge flags are cleared a capture occurs in response to a negative transition if the edge flags are seta capture occurs in response to a positive transition at pins P1 0 INT3 and P1 4 INT2 CC4 Semiconductor Group 123 SIEMENS On Chip Peripheral Comp
181. ignal at pin RESET In the case of a watchdog timer reset or oscillator watchdog reset the RESET OUT signal takes at least two machine cycles which is the minimal duration for a reset request allowed For details how the reset requests are OR ed together and how long they last see also chapter 7 8 Fail Save Mechanisms Semiconductor Group 39 SIEMENS On Chip Peripheral Components 7 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the SAB 80C517 except for the integrated interrupt controller which is described separately in chapter 8 Sections 7 1 and 7 2 are associated with the general parallel and serial I O facilities while the remaining sections describe the miscellaneous functions such as the timers A D converter compare capture unit multiplication division unit power saving modes fail save mechanisms oscillator and clock circuitries and system clock output 7 1 Parallel I O 7 1 1 Port Structures Digital The SAB 80C517 allows for digital I O on 56 lines grouped into 7 bidirectional 8 bit ports Each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO through P6 are performed via their corresponding special function registers PO to P6 The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory In this application port 0 outputs the low byte of the ext
182. igure 4 2 and the following table show the addressing modes used for the different RAM SFR spaces Semiconductor Group 16 SIEMENS Memory Organization Address Space Locations Addressing Mode Lower 128 bytes of RAM 00 to 7FH direct indirect Upper 128 bytes of RAM to indirect Special function registers to OFFyY direct For details about the addressing modes see chapter 9 1 FFFF External 2000 1 FFF 1 FFF Internal External EA 1 EA 0 0 0 MCB01817 Figure 4 1 Program Memory Address Space The lower 128 bytes of the internal RAM are again grouped in three address spaces see figure 4 3 1 A general purpose register area occupies locations 0 trough 1 see also section 4 3 2 The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bits Programming information These bits can be referred to in two ways both of which are acceptable for the ASM51 One way is to refer to their addresses i e 0 to 7 The other way is with reference to bytes 20 to 2 Thus bits 0 to 7 can also be referred to as bits 20 0 20 7 and bits 8 are the same as 21 0 21 7 and so on Each of the 16 bytes in this segment may also be addressed as a byte 3 Locations 0 to 7Fy can be used as a scratch pad area Semiconductor Group 17 SIEMENS Memory Organization Using the stack pointer SP a special function register described in se
183. imal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the decimal adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 Semiconductor Group 195 SIEMENS Instruction Set Operation Encoding Bytes Cycles BCD variables can be incremented or decremented by adding 014 or 994 If the accumulator initially holds 304 representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 294 in the accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 DA contents of accumulator are BCD if A3 0 gt 9 1 then A3 0 lt 0 6 if 7 4 gt 9 v C 1 then A7 4 lt A7 4 6 1101 0100 Semiconductor Group 196 SIEMENS Instruction Set DEC byte Function Decrement Description variable indicated is decremented by 1 An original value of 00 4 will underflow Example DEC A Operation Encoding Bytes Cycles DEC Rn Operation Encoding Bytes Cycles to OFF No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not t
184. imultaneous requests of the same priority level 8 3 How Interrupts are Handled The interrupt flags are sampled at 5 2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IENO IEN1 IEN2 or IPO and IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 IEN2 or IPO and IP1 then least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the CPU Semiconductor Group 164 SIEMENS Interrupt System The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine c
185. in figure 7 34 b Two reload modes are selectable In mode 0 when timer 2 rolls over from all 1 s to all 0 s it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16 bit value in the CRC register which is preset by software The reload will happen in the same machine cycle in which TF2 is set thus overwriting the count value 0000 In mode 1 a 16 bit reload from the CRC register is caused by a negative transition at the corresponding input pin T2EX P1 5 In addition this transition will set flag EXF2 if bit EXEN2 in SFR IEN1 is set the timer 2 interrupt is enabled setting EXF2 will generate an interrupt The external input pin T2EX is sampled in every machine cycle When the sampling shows a high in one cycle and a low in the next cycle a transition will be recognized The reload of timer 2 registers will then take place in the cycle following the one in which the transition was detected Timer 2 Interrupt Request Figure 7 34 b Timer 2 in Reload Mode Semiconductor Group 99 SIEMENS On Chip Peripheral Components Figure 7 35 Special Function Register 2 0C8H Mi OCC OCBY 0 9 0 T2RO T2CM T2l1 210 T2CON These bits are not used in controlling the CCU Timer 2 control register Bit addressable register which controls timer 2 function and compare mode of registers CRC CC1 to CC3
186. ing edge low level triggered external interrupts IEO Interrupt 0 edge flag Set by hardware when external interrupt edge is detected Cleared when interrupt is initiated IT1 Interrupt 1 type control bit Set cleared by software to specify falling edge low level triggered external interrupts IE1 Interrupt 1 edge flag Set by hardware when external interrupt edge is detected Cleared when interrupt is initiated TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when interrupt is initiated TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when interrupt is initiated The A D converter interrupt is generated by IADC in register IRCON see figure 8 7 It is set some cycles before the result is available That is if an interrupt is generated in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine with respect to the minimal interrupt response time If continuous conversions are established IADC is set once during each conversion If an A D converter interrupt is generated flag IADC will have to be cleared by software The external interrupt 2 INT2 CC4 can be either positive or negative transition activated depending on bit I2FR in register T2CON see figure 8 6 The flag that actually generates this interrupt is bit IEX2 in register IRCON In addition this flag will be set if a co
187. ing mode would reduce the controller s performance in the case of slow down mode or even stop any operation in the case of power down mode This situation might be fatal for the system which is controlled by the microcontroller Such critical applications often use the watchdog timer to prevent the system from program upsets Then an accidental entering of the power saving modes would even stop the watchdog timer and would circumvent the watchdog timer s task of system protection Semiconductor Group 134 SIEMENS On Chip Peripheral Components Hardware Enable for the Use of the Power Saving Modes To provide power saving modes together with effective protection against unintentional entering of these modes the SAB 80C517 has an extra pin disabling the use of the power saving modes As this pin will most likely be used only in critical applications it is combined with an automatic start of the watchdog timer see the description in section 7 8 Fail Save Mechanisms This pin is called PE SWD powers saving enable start watchdog timer and its function is as follows E SWD 1 logic high level Use of the power saving modes is not possible The instruction sequences used for entering these modes will not affect the normal operation of the device only if PE SWD is held at high level during reset the watchdog timer is started immediately after reset is released PE SWD 0 logic low level All power saving mod
188. ing sequence as follows see figure 8 10 Within one pair or triplet the leftmost interrupt is serviced first then the second and third when available The pairs or triplets are serviced from top to bottom of the table Semiconductor Group 162 SIEMENS Interrupt System Figure 8 9 Special Function Registers and IP1 Address and 0 9 0 9 OB9y4 5 4 IPO 3 IPO 2 IPO 1 1 0 0 IPO IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 1 1 These bits are not used for interrupt control Corresponding bit locations in both registers are used to set the interrupt priority level of an interrupt pair or triplet Bit Function IP1 x IPO x 0 0 Set priority level 0 lowest 0 1 Set priority level 1 1 0 Set priority level 2 1 1 Set priority level 3 highest Bit Function IP1 0 IP0 0 IEO RI1 TH ADC IP1 1 IPO 1 TFO IEX2 IP1 2 IP0 2 IE1 IEX3 IP1 3 IP0 3 TF1 CTF IEX4 IP1 4 IPO 4 RIO TIO IEX5 IP1 5 IPO 5 TF2 EXF2 IEX6 Semiconductor Group 163 SIEMENS Interrupt System Figure 8 10 Priority Within Level Structure High gt Low Priority Interrupt Source IEO RI TI IADC High TFO IEX2 IE1 l TF1 CTF IEX4 RIO TIO IEX5 TF2 EXF2 IEX6 Low Note This priority within level structure is only used to resolve s
189. ions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of RO or R1 in the current register bank provide an eight bit address multiplexed with data on PO Eight bits are sufficient for external expansion decoding or a relatively small RAM array For somewhat larger arrays any output port pins can be used to output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instructions the data pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while PO multiplexes the low order eight bits DPL with data The P2 special function register retains its previous contents while the P2 output buffers are emining the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64 Kbyte since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types A large RAM array with its high order address lines driven by P2 can be addressed via the data pointer or with code to output high order address bits to P2 followed by a MOVX instruction using RO or R1 An external 256 byte RAM using multiplexed address data lines e g an SAB 8155 RAM I O timer is connected to the SAB 80 c 5XX port 0 Port provides control lines for the external
190. is cleared all bits set to zero No flags are affected Example The accumulator contains 5 01011100p The instruction CLR A will leave the accumulator set to 00 00000000p Operation CLR 0 Encoding 1110 0100 Bytes 1 Cycles 1 Semiconductor Group 191 SIEMENS Instruction Set CLR bit Function Clear bit Description indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Example Port 1 has previously been written with 5D 01011101p The instruction CLR P1 2 will leave the port set to 594 01011001 p CLR C Operation CLR C 0 Encoding 11000011 Bytes 1 Cycles 1 CLR bit Operation CLR bit lt 0 Encoding 1100 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 192 SIEMENS Instruction Set CPL A Function Complement accumulator Description Each bit of the accumulator is logically complemented one s complement Bits which previously contained a one are changed to zero and vice versa No flags are affected Example The accumulator contains 5 01011100p The instruction CPL A will leave the accumulator set to OA3 10100011p Operation CPL lt Encoding 1111 0100 Bytes 1 Cycles 1 Semiconductor Group 193 SIEMENS Instruction Set CPL bit Function Complement bit Descripti
191. is cleared by the on chip hardware when the service routine is vectored too The two interrupts of the serial interfaces are generated by the request flags RIO and TIO in register SOCON and TI1 in register S1CON respectively Figures 7 7 and 7 12 show SFR s SOCON and S1CON That is the two request flags of each serial interface are logically OR ed together Neither of these flags is cleared by hardware when the service routine is vectored too In fact the service routine of each interface will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the bit will have to be cleared by software The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON Figures 8 6 and 8 7 show SFR s T2CON and IRCON Neither of these flags is cleared by hardware when the service routine is vectored too In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared by software Semiconductor Group 157 SIEMENS Interrupt System Figure 8 5 Special Function Register TCON Address 884 8Fy 8Dy 8CH 8By 89 88 88H TF1 TFO IE1 IT1 IEO ITO TCON 2 These bits are not used for interrupt control Bit Function ITO Interrupt 0 type control bit Set cleared by software to specify fall
192. is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figures 3 1 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction Semiconductor Group 14 SIEMENS Central Processing Unit EE eee P1 P2 P1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 P2 P1 21 2 1 P2 05 XTAL2 LLU ULL ALE Read Read next Opcode Opcode Discard Read next Opcode Again 1 Byte 1 Instruction e g INC Read Read 2nd Opcod Byt s T next Opcode 3 55 8 b 2 Byte 1 Instruction e g ADD A Data Read next Opcode Again Read Opcode Read next Opcode Discard Y Y Y STSTISTTSISTSTSISIRSTSTS c 1 Byte 2 Cycle Instruction e g INC DPTR Read next Opcode Again 4 Read Read next Opcode Opcode No Fetch No Fetch i MOVX Discard No ALE ests 5 8 Ts 35 8 d MOVX 1 2 Cycle MCB01816 Access External Memory Figure 3 1 Fetch Execute Sequence Semiconductor Group 15 SIEMENS Memory Organization 4 Memory Organization The SAB 80C517 CPU manipulates operands in the following four address spaces upto 64 Kbyte of program memory upto 64 Kbyte of external
193. it Port 1 1 2 8 bi digi 1 0 PE SWD UL IN Port 2 mi k 8 bit digit 1 0 Timer 2 Port 3 or Capture 8 bit digit 1 0 Compare Unit Compare Timer LIN Port 4 4 8 51 digit 1 0 5 Serial Channel 0 Port 5 8 bit digit 1 0 Progr Baud Rate Generator Port 6 digi 1 0 Serial Channel Port 7 analog Input 0 Progr Baud Rate Generator AGND Port 8 4 bit digit analog Input 00777 Figure 2 1 Functional Block Diagram Semiconductor Group 11 SIEMENS Fundamental Structure Central Processing Unit The CPU is designed to operate on bits and bytes The instructions which consist of up to 3 bytes are performed in one two or four machine cycles One machine cycle requires twelve oscillator cycles The instruction set has extensive facilities for data transfer logic and arithmetic instructions The Boolean processor has its own full featured and bit based instructions within the instruction set The SAB 80C517 uses five addressing modes direct access immediate register register indirect access and for accessing the external data or program memory portions a base register plus index register indirect addressing Memory Organization The SA
194. ith register A accumulator XCHD exchanges the low order nibble of the source operand byte with the low order nibble of A MOVX performs a byte move between the external data memory and the accumulator The external address can be specified by the DPTR register 16 bit or the R1 or RO register 8 bit MOVC moves a byte from program memory to the accumulator The operand in A is used as an index into a 256 byte table pointed to by the base register DPTR or PC The byte operand accessed is transferred to the accumulator Address Object Transfer MOV DPTR data loads 16 bits of immediate data into a pair of destination registers and DPL 9 2 2 Arithmetic The SAB 80C517 has four basic mathematical operations Only 8 bit operations using unsigned arithmetic are supported directly The overflow flag however permits the addition and subtraction operation to serve for both unsigned and signed binary integers Arithmetic can also be performed directly on packed BCD representations Addition NC increment adds one to the source operand and puts the result in the operand ADD adds A to the source operand and returns the result to A ADDC add with carry adds A and the source operand then adds one 1 if CY is set and puts the result in A DA decimal add adjust for BCD addition corrects the sum which results from the binary addition of two digit decimal operands The packed decimal sum formed b
195. itional outputs of CC4 at P5 0 to P5 2 Additional outputs of CC4 at P5 0 to P5 3 Additional outputs of CC4 at P5 0 to P5 4 Additional outputs of CC4 at P5 0 to P5 5 Additional outputs of CC4 at P5 0 to P5 6 a ss Oo Oo olo 0 1 0 1 0 1 0 1 Additional outputs of CC4 at P5 0 to P5 7 Semiconductor Group 114 SIEMENS On Chip Peripheral Components Using Interrupts in Combination with the Compare Function The compare service of registers CRC CC1 CC2 CC3 and CC4 is assigned to alternate output functions at port pins P1 0 to P1 4 Another option of these pins is that they can be used as external interrupt inputs However when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected but the pin s level can still be read under software control Thus a change of the pin s level will not cause a setting of the corresponding interrupt flag In this case the interrupt input is directly connected to the internal compare signal thus providing a compare interrupt The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next compare match The principle is that the internal compare signal generated at a match between timer count and register contents not only manipulates the compare output but also
196. keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the SAB 800517 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 5 1 illustrates the addressing mechanism a 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx Semiconductor Group 29 SIEMENS External Bus Interface DPSEL Selected Data 2 1 0 pointer DPTR DPTR DPTR DPTR DPTR DPTR DPTR DPTR DPTRO DPH 884 DPL 82y MN RET External Data Memory MCD00779 Cc O oco Ooo wc c FP C C Figure 5 1 Accessing of External Data Memory via Multiple Datapointers Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the contents of the datapointer must be altered between two or more 16 bit addres
197. l operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Semiconductor Group 139 SIEMENS On Chip Peripheral Components 7 7 3 Slow Down Mode In some applications where power consumption and dissipation is critical the controller might run for a certain time at reduced speed e g if the controller is waiting for an input signal Since in CMOS devices there is an almost linear interdependence of the operating frequency and the power supply current a reduction of the operating frequency results in reduced power consumption In the slow down mode all signal frequencies that are derived from the oscillator clock are divided by eight This also includes the clockout signal at pin P1 6 CLKOUT If the slow down mode is to be used the pin PE SWD must be held low The slow down mode is entered by setting bit SD PCON 4 see figure 7 57 The controller actually enters the slow down mode after a short synchronization period max two machine cycles The slow down mode can be used together with idle and power down mode The slow down mode is disabled by clearing bit SD Semiconductor Group 140 SIEMENS On Chip Peripheral Components 7 8 Fail Save Mechanisms The SAB 80C517 offers two on chip peripherals which monitor the program flow and ensure an automatic fail safe reaction for cases where the controller s hardware fails or the software hangs up Apro
198. l output signal is periodically varied in the length of its high or low time duty cycle One high and one low time together make up a sample point of the sine wave to be synthesized The generation of the sine wave out of the modulated digital signal is done by a low pass filter PWM frequency In this example the switching frequency of the PWM signal is fixed The frequency is determined by the reload value resolution and the input clock of the timer 8 bit resolution This means that only eight bits of the 16 bit wide timer and compare circuitry are used to generate the PWM signal faster PWM frequency Thus the duty cycle of the signal is programmable in 256 steps Each step represents a quantum of one machine state or 166 6 ns at fos 12 MHz 256 x 166 6 ns 42 649 us 1 42 649 us 23 4 kHz Configuration of the CCU To generate a sine wave the duty cycle of a PWM signal must be varied periodically as mentioned above One PWM period or one sample point is represented by a full compare timer period The high to low transition of the PWM signal takes place upon every compare timer overflow the low to high transition is programmable and takes place when the timer count matches the contents of the compare register gt compare mode 0 In the worst case maximum sine wave frequency the contents of the compare register must be reloaded in every compare timer period Compare timer setup Input clock The i
199. le Pointer to first Address MCA01863 Figure 10 3 Program Flow Charts The interrupt routine takes full advantage of the TOC loading The interrupt routine is always vectored to some time after a compare timer overflow This means that the new compare value is moved to at an undefined moment in the current timer period The moment depends on the interrupt response time uncertainty of 3 to 9 machine cycles and on the length of the interrupt routine itself perhaps there are more channels to serve etc Without any further provisions like the TOC loading there would be no chance for loading an early compare value e g CMO 0000 because the timer would have passed these early counts before the loading was completed The TOC loading now solves the above problem The interrupt service routine is always thinking one cycle in advance It actually loads the compare value or sample point for the next timer period Thus the CPU has one full timer period to serve all compares The compare value loaded to the CMO register by the interrupt routine will be immediately transferred to the actual compare latch at the next compare timer overflow This overflow then again requests a new interrupt service routine Semiconductor Group 262 SIEMENS Application Examples Conclusion This application example is meant to show that the CCU of the SAB 80C517 is able to generate very fast PWM signals with low CPU effort Small
200. lear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxxx 1111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 604 or 664 to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction The accumulator holds the value 561 01010110p representing the packed BCD digits of the decimal number 56 Register 3 contains the value 674 01100111p representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard two s complement binary addition resulting in the value OBEy 101111105 in the accumulator The carry and auxiliary carry flags will be cleared The decimal adjust instruction will then alter the accumulator to the value 24 001001005 indicating the packed BCD digits of the dec
201. led by a high level at pin OWE pin 69 An oscillator watchdog reset sets status flag OWDS which can be examined and modified by software Figure 12 shows a block diagram of the oscillator watchdog pos J IPO OA9y OWD Reset Request gt On Chip Oscillator Frequency Delay Comparator 5 Cycles Internal Clock Watchdog Oscillator MCB00789 Figure 12 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 306 SIEMENS SAB 80C517 80C537 Instruction Set Summary The SAB 80C517 80C537 has the same instruction set as the industry standard 8051 micro controller A pocket guide is available which contains the complete instruction set in functional and hexa decimal order Furtheron it provides helpful information about Special Function Registers In terrupt Vectors and Assembler Directives Literature Information Title Ordering No Microcontroller Family SAB 8051 Pocket Guide B158 H6497 X X 7600 Semiconductor Group 307 SIEMENS SAB 80C517 80C537 Absolute Maximum Ratings Ambient temperature under bias BAB COGS 1 PBSC a 1 sites rore oo Eo geb RE 0 to 70 C SAB 806517 83659 7 140 85 iion ui ule 40 to 85 C Storage temperature a ipia Y RR 65 to 150 Voltage on pins with respect to ground Vag 0 5 Vto6 5 V Voltage on any
202. loaded by software at any time Examples given for a 12 MHz oscillator frequency WDTREL Time Out Period Comments 00H 65 535 ms This is the default value and coincides with the watchdog period of the SAB 80515 1 18 Maximum time period 512 us Minimum time period Semiconductor Group 141 SIEMENS On Chip Peripheral Components Starting the Watchdog Timer There are two ways to start the watchdog timer depending on the level applied to pin PE SWD pin 4 This pin serves two functions because it is also used for blocking the power saving modes For details see chapter 7 7 The First Possibility of Starting the Watchdog Timer The automatic start of the watchdog timer directly after an external HW reset is a hardware start initialized by strapping pin 4 PE SWD to In this case the power saving modes power down mode idle mode and slow down mode are also disabled and cannot be started by software The self start of the watchdog timer by a pin option has been implemented to provide high system security in electrically very noisy environments Note The automatic start of the watchdog timer is only performed if PE SWD power save enable start watchdog timer is held at high level while reset is active A positive transition at this pin during normal program execution will not start the watchdog timer Furthermore when using the hardware start the watchdog timer starts running
203. lock to do one last shift and load SOBUF At S1P1 in the 10th machine cycle after the write to SOCON that cleared RIO RECEIVE is cleared and RIO is set Semiconductor Group 66 SIEMENS On Chip Peripheral Components 7 2 3 2 Mode 1 Mode B 8 Bit UART Serial Interfaces 0 and 1 Ten bits are transmitted through TxDO or TxD1 or received through RxDO or RxD1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception through RxDO the stop bit goes into RB80 SOCON on reception through RxD1 RB81 S1CON stores the stop bit The baud rate for serial interface 0 is determined by the timer 1 overflow rate or by the internal baud rate generator of serial interface Serial interface 1 receives the baud rate clock from its own baud rate generator Figures 7 17 a and b show a simplified functional diagram of both serial channels in mode 1 or mode B resp The generation of the baud rate clock by the various timers is described in sections 7 2 1 3 and 7 2 2 3 Transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register The write to SOBUF S1BUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control block that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next roll over in the divide by 16 counter thus the bit times are synchronized to the divide by 16 counter not to the write to SO
204. locks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 284 SIEMENS SAB 80C517 80C537 Table 1 Special Function Register cont d Address Register Name Register Contents after Reset Compare CCEN Comp Capture Enable Reg 0C1y 004 Capture CC4EN Comp Capture Enable 4 Reg 0C9 X000 0000 Unit CCU 1 Comp Capture Reg 1 High Byte 0 004 CCH2 Comp Capture Reg 2 High Byte 0C5 004 CCH3 Comp Capture Reg High Byte 0 7 004 CCH4 Comp Capture Reg 4 High Byte OCF 004 CCL1 Comp Capture Reg 1 Low Byte 0C2 004 CCL2 Comp Capture Reg 2 Low Byte 0C4 004 CCL3 Comp Capture Reg 3 Low Byte 0C6 004 CCL4 Comp Capture Reg 4 Low Byte OCE 004 CMEN Compare Enable Register 004 CMHO Compare Register 0 High Byte 003 004 CMH1 Compare Register 1 High Byte 005 00 CMH2 Compare Register 2 High Byte 007 CMH3 Compare Register 3 High Byte 0 004 CMH4 Compare Register 4 High Byte OE5y 00 CMH5 Compare Register 5 High Byte 0 7 004 CMH6 Compare Register 6 High Byte 004 CMH7 Compare Register 7 High Byte OF5 004 CMLO Compare Register 0 Low Byte 0D2 00 CML1 Compare Register 1 Low Byte 004 004 CML2 Compare Register 2 Low Byte 006 004 CML3 Compare Register 3 Low Byte OE2 00 CML4 Compare Register 4 Low Byte 0 4 004 CML5 Compare Register 5 Low Byte OE6 004 CML6 Compare Register 6 L
205. lowing the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle see also section 7 1 Parallel I O for the exact sample time at the port pin P1 7 Note The prescaler must be off for proper counter operation of timer 2 i e T2PS must be 0 In either case no matter whether timer 2 is configured as timer event counter or gated timer a rolling over of the count from all 1 s to all O s sets the timer overflow flag TF2 bit 6 in SFR IRCON interrupt request control which can generate an interrupt If TF2 is used to generate a timer overflow interrupt the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt for EXF2 see below Both request flags cause the program to branch to the same vector address The input clock to timer 2 is selected by bits 210 211 and T2PS as listed in figure 7 35 Semiconductor Group 98 SIEMENS On Chip Peripheral Components Reload of Timer 2 The reload mode for timer 2 is selected by bits T2RO and T2R1 in SFR T2CON as listed
206. lting sum to the program counter This will be the address for subsequent instruction fetches Sixteen bit addition is performed modulo 215 a carry out from the low order eight bits propagates through the higher order bits Neither the accumulator nor the data pointer is altered No flags are affected An even number from 0 to 6 is in the accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR JMP_TBL AJMP LABELO AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator equals 044 when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address JMP lt A DPTR 01110011 Semiconductor Group 208 SIEMENS Instruction Set JNB Function Description Example Operation Encoding Bytes Cycles bit rel Jump if bit is not set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010p The accumulator holds 56 4 01010110p The instructi
207. lue limiting the lower end of the modulation range or it may occur at the end of a timer period In a timer 2 CCx register configuration in compare mode 0 this spike is divided into two halves one at the beginning when the contents of the compare register is equal to the reload value of the timer the other half when the compare register is equal to the maximum value of the timer register here OFFFF Please refer to figure 7 44 where the maximum and minimum duty cycle of a compare output signal is illustrated Timer 2 is incremented with the machine clock 12 thus at 12 MHz operational frequency these spikes are both approx 500 ns long CCHx CCLx 0000y or CRCH CRCL maximum duty cycle NC L Appr 1 2 of a Machine Cycle CCHx CCLx FFFFY minimum duty cycle Appr 1 2 of a Machine Cycle H P1 x 1851 Figure 7 44 Modulation Range of a PMW Signal Generated with a Timer 2 CCx Register Combination Compare Mode 0 The following example shows how to calculate the modulation range for a PWM signal To calculate with reasonable numbers a reduction of the resolution to 8 bit is used Otherwise for the maximum resolution of 16 bit the modulation range would be so severely limited that it would be negligible Semiconductor Group 111 SIEMENS On Chip Peripheral Components Example Timer 2 in auto reload mode contents of reload register CRC 16 1 Rest
208. ly an external program memory Semiconductor Group 28 SIEMENS External Bus Interface 5 2 Eight Datapointers for Faster External Bus Access The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment instruction any other pointer handling is to be done byte by byte For complex applications with numerous external peripherals or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages How the Eight Datapointers of the SAB 80C517 are Realized Simply adding more datapointers is not suitable because of the need to keep up 100 compatibility to the 8051 instruction set This instruction set however allows the handling of only one single 16 bit datapointer DPTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 100 compatibility to 8051 architecture the SAB 80C517 contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program may
209. mable baud rate generator An 8 bit resolution A D converter with software adjustable reference voltages has been integrated to allow analog signal processing As a counterpart to the A D converter the SAB 80C517 includes a powerful compare capture unit with two 16 bit timers for all kinds of digital signal processing The controller has been completed with well considered provisions for fail safe reaction in critical applications and offers all CMOS features like low power consumption as well as an idle power down and slow down mode Figure 2 1 shows a block diagram of the SAB 80C517 Readers who are familiar with the SAB 8051 or SAB 80515 may concentrate on chapters 6 and 7 where the reset conditions and the new peripheral components are described Chapter 8 Interrupt System has a special section for 80515 professionals where enhancements of the interrupt structure compared to the SAB 80515 are summarized For readers however who are newcomers to the 8051 family of microcontrollers the following section may give a general view of the basic characteristics of the SAB 80C517 The details of operation are described later in chapters 3 and 4 Semiconductor Group 10 SIEMENS Fundamental Structure OWE Oscillator Watchdog ROM RAM 8K x 8 256 x 8 SAB 806517 OSC amp Timing only XTAL2 RESET Programmoble dum RO Watchdog Timer Port 0 ALE Port 0 8 bit digit PSEN Div Mul Un
210. malizing is selected After operation SC 0 2 to SC 4 contain the number of normalizing shifts performed When set 1 with a value 0 shift operation is started The number of shifts 0 performed is determined by the count written to SC 0 to SC 4 Semiconductor Group 130 SIEMENS On Chip Peripheral Components Normalizing Normalizing is done on an integer variable stored in MDO least significant byte to MD3 most significant byte This feature is mainly meant to support applications where floating point arithmetic is used To normalize means that all reading zeroes of an integer variable in registers MDO to are removed by shift left operations The whole operation is completed when the MSB most significant bit contains a 1 To select a normalize operation the five bit field ARCON O to ARCON 4 must be cleared That means a write to ARCON instruction with the value XXXO 0000g starts the operation After normalizing bits ARCON 0 to ARCON 4 contain the number of shift left operations which were done This number may further on be used as an exponent The maximum number of shifts in a normalize operation is 31 25 1 The operation takes six machine cycles at most that means 6 microseconds at 12 MHz Shifting In the same way by a write to ARCON instruction a shift left right operation can be started In this case register bit SLR ARCON 5 has to contain the shift direction and ARCON 0 to ARCON 4 th
211. mbols are listed in alphabetical order Bit addressable special function registers are marked with a dot in the fifth column Special function registers with bits belonging to more then one functional block are marked with an asterisk at the symbol name Semiconductor Group 20 SIEMENS Memory Organization Special Function Registers of the SAB 80C517 Block Symbol Name Address Contents after Reset CPU ACC Accumulator 0E0H B Register OFO 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H DPSEL Data Pointer Select Register 92H XXXX X000p PSW Program Status Word Register 00H SP Stack Pointer 81H 07H A D ADCONO A D Converter Control Register 0 008 00H Converter ADCON1 A D Converter Control Register 1 XXXX 0000p ADDAT A D Converter Data Register OD9y 00H DAPR D A Converter Program Register ODAH 00H Interrupt IENO Interrupt Enable Register 0 0A8H 00H System CTCON Com Timer Control Register OE1y OXXX 0000p IEN1 Interrupt Enable Register 1 00H IEN2 Interrupt Enable Register 2 9AH XXXX 00X0p IPO Interrupt Priority Register 0 0A9H 00H IP1 Interrupt Priority Register 1 9 XX00 0000p IRCON Interrupt Request Control Register OCO 00H TCON Timer Control Register 88 00H T2CON Timer 2 Control Register 00H MUL DIV ARCON Arithmetic Control Register OXXX XXXXp Unit MDO Multiplication Division Registe
212. miconductor Group 65 SIEMENS On Chip Peripheral Components 7 2 3 Detailed Description of the Operating Modes The following sections give a more detailed description of the several operating modes of the two serial interfaces The sections 7 2 3 2 and 7 4 3 4 apply to both of the serial interfaces The description of the synchronous mode 0 and the asynchronous mode 2 refers only to serial interface 0 7 2 3 1 Mode 0 Synchronous Mode Serial Interface 0 Serial data enters and exits through RxDO TxDO outputs the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at 1 12 of the oscillator frequency Figures 7 16 a and b show a simplified functional diagram of the serial port in mode 0 and associated timing Transmission is initiated by any instruction that uses SOBUF as a destination register The write to SOBUF signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between write to SOBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line P3 0 and also enables SHIFT CLOCK to the alternate output function line P3 1 SHIFT CLOCK is low during S3 S4 and S5 of every machine cycle and high during S6 S1 and S2 while the interface is transmitting Before and after transmis
213. mpare event occurs at the corresponding output pin P1 4 INT2 CC4 regardless of the compare mode established and the transition at the respective pin If an interrupt 2 is generated flag IEX2 is cleared by hardware when the service routine is vectored too Semiconductor Group 158 SIEMENS Interrupt System Figure 8 6 Special Function Register 2 Address 0C8j OCDY _ aid 0C8H 1 These bits are not used for interrupt control Bit Function I2FR External interrupt 2 falling rising edge flag When set the interrupt 2 request flag IEX2 will be set on a positive transition at pin P1 4 INT2 I2FR 0 specifies external interrupt 2 to be negative transition activated ISFR External interrupt 3 falling rising edge flag When set the interrupt 3 request flag IEXS will be set on a positive transition at pin P1 0 INT3 I8FR 0 specifies external interrupt 3 to be negative transition active Like the external interrupt 2 the external interrupt 3 can be either positive or negative transition activated depending on bit I3FR in register T2CON The flag that actually generates this interrupt is bit IEX3 in register IRCON In addition this flag will be set if a compare event occurs at pin P1 0 INT3 CCO regardless of the compare mode established and the transition at the respective pin The flag IEX3 is cleared by hardware when the service routine is vectored too
214. n an oscillator failure is detected and it is cleared by an external HW reset or by software see figure 7 62 The block diagram in figure 7 64 illustrates the function of the oscillator watchdog Note that the OWD reset request is held for at least three additional cycles after the on chip oscillator returns to normal operation This is done to ensure a proper oscillator startup Semiconductor Group 146 SIEMENS On Chip Peripheral Components oos On Chip PO OA9 XTALZ Oscillator Frequency Delay OWD Resei Request Comparator 3 Cycles Internal Clock gt Watchdog Oscillator MCB00789 Figure 7 64 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 147 SIEMENS On Chip Peripheral Components 7 9 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip at half the oscillator frequency These signals define the internal phases states and machine cycles as described in chapter 3 Figure 7 65 shows the recommended oscillator circuit XTAL2 806517 XTAL1 30 pF 10 pF for Quartz Crystal MCS01867 Figure 7 65 Recommended Oscillator Circuit In this appl
215. ncremented to the next instruction prior to execution RET transfers control to the return address saved on the stack by a previous call operation and decrements the SP register by two 2 to adjust the SP for the popped address AJMP LUMP and SJMP transfer control to the target operand The operation of AJMP and LJMP are analogous to ACALL and LCALL The SJMP short jump instruction provides for transfers within a 256 byte range centered about the starting address of the next instruction 128 to 127 JMP 2A DPTR performs a jump relative to the DPTR register The operand in A is used as the offset 0 255 to the address in the DPTR register Thus the effective destination for a jump can be anywhere in the program memory space Conditional Jumps Conditional jumps perform a jump contingent upon a specific condition The destination will be within a 256 byte range centered about the starting address of the next instruction 128 to 127 JZ performs a jump if the accumulator is zero JNZ performs a jump if the accumulator is not zero JC performs a jump if the carry flag is set JNC performs a jump if the carry flag is not set JB performs a jump if the directly addressed bit is set JNB performs a jump if the directly addressed bit is not set JBC performs a jump if the directly addressed bit is set and then clears the directly addressed bit CJNE compares the first operand to the second operand and performs a jump if the
216. nd D end MD3 D endH MD4 D endH MD1 M andH MD4 D orL D orL Last Write MD5 D orH MD5 D orH MD5 M orH First Read MDO QuoL MDO QuoL MDO PrL MD1 Quo MD1 QuoH MD1 MD2 Quo MD3 QuoH MD4 RemL MD2 MD4 RemL Last Read MD5 RemH MD5 RemH MD3 PrH Table 6 Shift Operation with the CCU Operation Normalize Shift Left Shift Right First Write MDO least significant byte MD1 MD2 MD3 most significant byte Last Write ARCON start of conversion First Read MDO least significant byte MD1 MD2 Last Read MD3 most significant byte Abbreviations Dividend 1st operand of division Dior Divisor 2nd operand of division Multiplicand 1st operand of multiplication Multiplicator 2nd operand of multiplication Pr Product result of multiplication Rem Remainder Quo Quotient result of division pale means that this byte is the least significant of the 16 bit or 32 bit operand H means that this byte is the most significant of the 16 bit or 32 bit operand Semiconductor Group 299 SIEMENS SAB 80C517 80C537 Ports The SAB 80C517 has seven 8 bit I O ports and two input ports 8 bit and 4 bit wide Port 0 is an open drain bidirectional I O port while ports 1 to 6 are quasi bidirectional I O ports with internal pull up resistors That means when configured as inputs ports 1 to 6 will be pulled high and will source current when externally pulled low Port 0 will float when configured a
217. nel of port 8 is being selected see table 7 6 Semiconductor Group 86 SIEMENS On Chip Peripheral Components Ports P7 and P8 are dual purpose input ports If the input voltage meets the specified logic levels they can be used as digital inputs as well regardless of whether the pin levels are sampled by the A D converter at the same time The special function register ADDAT figure 7 28 holds the converted digital 8 bit data result The data remains in ADDAT until it is overwritten by the next converted data ADDAT can be read or written under software control If the A D converter of the SAB 80C517 is not used register ADDAT can be used as an additional general purpose register Figure 7 28 Special Function Register ADDAT Address 009 0 9 Conversion result ADDAT This register contains the 8 bit conversion result 7 4 1 2 Start of Conversion An internal start of conversion ADEX 0 is triggered by a write to DAPR instruction The start procedure itself is independent of the value which is written to DAPR However the value in DAPR determines which internal reference voltages are used for the conversion see section 7 4 2 When single conversion mode is selected ADM 0 only one conversion is performed In continuous mode after completion of a conversion a new conversion is triggered automatically until bit ADM is reset When external start of conversion is selected a write to DAPR will not start the conve
218. ng interrupt request flags for serial interface O are TIO or RIO resp See section 8 for more details about the interrupt structure The interrupt request flags TIO and RIO can also be used for polling the serial interface 0 if the serial interrupt is not to be used i e serial interrupt 0 not enabled The control and status bits of the serial channel 0 in special function register SOCON are illustrated in figure 7 8 Figure 7 7 shows the special function register SOBUF which is the data register for receive and transmit The following table summarizes the operating modes of serial interface O Serial Interface 0 Mode Selection SMO SM1 Mode Descriptions Baud Rate 0 0 0 Shift register fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART fosc 64 32 1 1 3 9 bit UART Variable Figure 7 7 Special Function Register SOBUF Address 994 99H Serial interface 0 buffer register SOBUF Receive and transmit buffer of serial interface 0 Writing to SOBUF loads the transmit register and initiates transmission Reading out SOBUF accesses a physically separate receive register Semiconductor Group 52 SIEMENS On Chip Peripheral Components Figure 7 8 Special Function Register SOCON Address 9814 9Fy 9CH 9BH 9AH 99H 98H 984 SMO SM1 SM20 RENO TB80 RB80 TIO RIO SOCON Bit Symbol SMO SM1 0 0 Seri
219. nication Feature Modes 2 and 3 of the serial interface 0 have a special provision for multi processor communication In these modes 9 data bits are received The 9th bit goes into RB80 Then a stop bit follows The port can be programmed such that when the stop bit is received the serial port 0 interrupt will be activated i e the request flag RIO is set only if RB80 1 This feature is enabled by setting bit SM20 in SOCON A way to use this feature in multiprocessor communications is as follows If the master processor wants to transmit a block of data to one of the several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM20 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be coming After having received a complete message the slave sets SM20 again The slaves that were not addressed leave their SM20 set and go on about their business ignoring the incoming data bytes SM20 has no effect in mode 0 In mode 1 SM20 can be used to check the validity of the stop bit If SM20 1 in mode 1 the receive interrupt will not be activated unless a valid stop bit is received 7 2 1 3 Baud R
220. not affected by EXEN2 Semiconductor Group 156 SIEMENS Interrupt System Figure 8 4 Special Function Register IEN2 Address 09 09 ECT ES1 IEN2 Bit Function ES1 Enable serial interrupt of interface 1 Enables or disables the interrupt of serial interface 1 If ES1 0 the interrupt is disabled ECT Enable compare timer interrupt Enables or disables the interrupt at compare timer overflow If ECT 0 the interrupt is disabled In the following the interrupt sources are discussed individually The external interrupts 0 and 1 INTO and INT1 can each be either level activated or negative transition activated depending on bits ITO and IT1 in register TCON see figure 8 5 The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers exception see section 7 3 4 for timer 0 in mode 3 When a timer interrupt is generated the flag that generated it
221. nput clock is set to 2 This can be done in special function register CTCON In this case the timer is incremented every machine cycle 166 6 ns at 12 MHz Reload The reload register high byte is set to CTRELL low byte must contain Thus the timer counts from to OFFFF 8 bit reload 256 steps Semiconductor Group 259 SIEMENS Application Examples Sine Wave Table angle 30 90 150 210 270 330 CMLx 40H 00H 40H COH COH MCT01862 Figure 10 2 PWM Generation for Sine Wave Synthesis Semiconductor Group 260 SIEMENS Application Examples Compare Setup Compare mode Compare register CMO consisting of CMHO and CMLO is used in compare mode 0 This means bit CMSEL O must be set in register CMSEL to assign CMO to the compare timer and switch on compare mode 0 Enable port output The compare is enabled with SFR bit CMEN O in register The corresponding compare output pin is port 4 0 Interrupts Since the compare value may be varied in every compare timer period it is most effective to use the compare timer overflow interrupt for reloading the compare register CMO with a new value Enable Interrupt The compare timer overflow interrupt is enabled by SFR bit ECT in register IEN2 The general enable flag EAL in register IENO must be set too The Program Variation of th
222. nsfer to be done in any case This write resets the MDU and triggers the error flag mechanism see below The next two or three write operations select the calculation type 32bit 16bit 16bit 1 6bit 16bit x 16bit The last write to MD5 finally starts the selected MUL DIV operation Read Sequence Any read out of the MDx registers should begin with MDO The last read from MD5 division or multiplication determines the end of a whole calculation and releases the error flag mechanism There is no restriction on the time within which a calculation must be completed The CPU is allowed to continue the program simultaneously to phase 2 and to fetch the result bytes at any time If the user s program takes care that interrupting a calculation is not possible monitoring of the calculation process is probably not needed In this case only the write sequence must be observed Any new write access to MDO starts a new calculation no matter whether the read out of the former result has been completed or not 7 6 3 Normalize and Shift Register ARCON controls an up to 32 bit wide normalize and shift operation in registers MDO to It also contains the overflow flag and the error flag which are described in the next two sections Figure 7 56 illustrates special function register ARCON Write Sequence A write to MDO is also the first transfer to be done for normalize and shift This write resets the MDU and triggers th
223. nternal pull up resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current Z in the DC characteristics because of the internal pull up resistors It is used for the low order address byte during program verifi cation It also contains the interrupt timer clock capture and compare pins that are used by various options The output latch must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows INT3 CCO P1 0 interrupt 3 input compare 0 output capture 0 input INT4 CC1 P1 1 interrupt 4 input compare 1 output capture 1 input INT5 CC2 P1 2 interrupt 5 input compare 2 output capture 2 input INT6 CC3 P1 3 interrupt 6 input compare 3 output capture 3 input INT2 CC4 P1 4 interrupt 2 input compare 4 output capture 4 input 2 P1 5 timer 2 external reload trigger input CLKOUT P1 6 system clock output T2 P1 7 counter 2 input Input Output Semiconductor Group 273 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number 10 P LCC 84 P MQFP 100 2 Function XTAL2 39 12 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits XTAL1 13
224. nverter 6 0 ADST VinTAREF VNTAGND ViREF VAGND D A Converter 5 4 5 2 DAPR Internal MCB00780 Figure 7 25 Block Diagram of the A D Converter Semiconductor Group 84 SIEMENS On Chip Peripheral Components An externally controlled conversion can be achieved by setting the bit ADEX In this mode on single conversion is triggered by a 1 to 0 transition at pin P6 0 ADST if ADM is 0 P6 0 ADST is sampled suring S5P2 of every machine cycle When the samples show a logic high in one cycle and a logic low in the next cycle the transition is detected and the conversion is started When ADM and ADEX is set a continuous conversion is started when pin P6 0 ADST sees a low level the conversion is stopped when the pin P6 0 ADST goes back to high The last commenced conversion during low level will be completed The busy flag BSY ADCONO 4 is automatically set when a conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect There is also an interrupt request flag IADC IRCON 0 that is set when a conversion is completed See section 8 for more details about the interrupt structure Figure 7 26 Special Function Register ADCONO Address 0D8 ODFy ODE O0DDj ODCj ODBy ODAY 008 0D8j BD CLK ADEX BSY ADM MX ADCONO These bits are not used in controlling A D converter functions
225. o A and jump if not equal 3 2 Semiconductor Group 254 SIEMENS Instruction Set Instruction Set Summary cont d Mnemonic Description Byte Cycle Program and Machine Control cont d CJNE A data rel Compare immediate to A and jump if not equal 3 2 CJNE Rn data rel Compare immed to reg and jump if not equal 3 2 CJNE Ri data rel Compare immed to ind and jump if not equal 3 2 DJNZ Rn rel Decrement register and jump if not zero 2 2 DJNZ direct rel Decrement direct byte and jump if not zero 3 2 NOP No operation 1 1 Semiconductor Group 255 SIEMENS Application Examples 10 Application Examples 10 1 Application Examples for the Compare Functions 10 1 1 Generation of Two Different PWM Signals with Additive Compare using the Registers The following example gives an idea of how to use compare mode 1 and compare interrupts for an additive pulse width modulation Assume that an application requires two PWM signals at two port pins providing different switching frequencies e g a switching frequency of 2 kHz at port 1 1 further on called PWM channel 1 and 5 kHz at port 1 2 further on called PWM channel 2 In this case compare mode 0 cannot be used since it uses the timer overflow signal to switch all compare outputs to low level and thereby provides the same switching frequency In our case however the period of each PWM signal is different being
226. ocated at the indicated address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the stack pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space No flags are affected Initially the stack pointer equals 074 The label SUBRTN is assigned to program memory location 12344 After executing the instruction SUBRTN at location 01234 the stack pointer will contain 094 internal RAM locations 08 and 094 will contain 264 and 014 and the PC will contain 12344 LCALL lt SP lt SP 1 SP lt 7 0 SP lt SP 1 SP lt PC15 8 lt addr15 0 00010010 addr15 addr8 addr7 addrO Semiconductor Group 213 SIEMENS Instruction Set LJMP addr16 Function Long jump Description LUMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected
227. of the reset signal then depends on the prescaler selection either 8 cycles or 128 cycles This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS watchdog timer status bit 6 in special function register IPO is set Figure 7 62 shows a block diagram of all reset requests in the SAB 80C517 and the function of the watchdog status flags The WDTS flag is a flip flop which is set by a watchdog timer reset and cleared by an external HW reset Bit WDTS allows the software to examine from which source the reset was activated The watchdog timer status flag can also be cleared by software Figure 7 60 Special Function Register IENO OACY OABY OAS 8 EAL WDT Eso IENO These bits are not used in controlling the fail safe mechanisms Bit Function WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer Figure 7 61 Special Function Register IEN1 OBCy 0B94 OB8y SWDT EX5 EADC OB8y IEN1 These bits are not used in controlling the fail safe mechanisms Bit Function SWDT Watchdog timer start flag Set to activate the watchdog timer When directly set after setting WDT a
228. ogram flow then it could easily be that a compare register is overwritten before the timer had the chance to reach the previously loaded compare value Hence there must be something to synchronize the loading of the compare registers to the running timer circuitry This could either be an interrupt caused by the timer circuitry as described before or a special hardware circuitry Semiconductor Group 118 SIEMENS On Chip Peripheral Components a CMHx CMLx CTREL maximum duty cycle P4 x H b CMHx CMLx FFFFy minimum duty cycle One H y eye One machine state or two oscillator cycle MCT01854 Figure 7 50 Modulation Range of a PWM Signal Generated with a Compare Timer CMx Register Combination Thus TOC loading means that there is dedicated hardware in the CCU which synchronizes the loading of the compare registers CMx in such a way that there is no loss of compare events It also relieves the CPU of interrupt load What does this hardware look like A CMx compare register in compare mode consists of two latches When the CPU tries to access register it only addresses a register latch and not the actual compare latch which is connected to the comparator circuit The contents of the register latch may be changed by the CPU at any time because this change would never affect the compare event for the current timer period The compare latch the actual latch holds the compare valu
229. on bit variable specified is complemented bit which had been a one is changed to zero and vice versa No other flags are affected CPL can operate on the carry or any directly addressable bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Example Port 1 has previously been written with 5 010111015 The instruction sequence CPL P1 1 CPL 1 2 will leave the port set to 5 01011011 CPL C Operation CPL bit lt C Encoding 10110011 Bytes 1 Cycles 1 CPL bit Operation CPL bit Encoding 1011 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 194 SIEMENS Instruction Set DA A Function Description Example Decimal adjust accumulator for addition DA A adjusts the eight bit value in the accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC flag is one six is added to the accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagated through all high order bits but it would not c
230. on PSEN 49 22 The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periodes except during external data memory accesses Remains high during internal pro gram execution ALE 50 23 The Address Latch Enable output is used for latching the address into external memory during normal operation It is activated every six oscillator periodes except during an external data memory access 51 24 External Access Enable When held at high level instructions are fetched from the internal ROM when the PC is less than 8192 When held at low level the SAB 80C517 fetches all instructions from external program memory For the SAB 80C537 this pin must be tied low 0 7 52 59 26 27 30 35 I O Port 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull up resistors when issuing 1 s Port 0 also outputs the code bytes during program verification in the SAB 83C517 External pull up resistors are required during program verification Input O Output Semiconductor Group 275 SIEMENS
231. on SMOD When set the baud rate of serial interface 0 in modes 1 2 3 is doubled Modes 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a dedicated baud rate generator or by timer 1 Using the baud rate generator In modes 1 and 3 the SAB 80C517 can use the internal baud rate generator for serial interface O To enable this feature bit BD bit 7 of special function register ADCONO must be set see figure 7 10 This baud rate generator divides the oscillator frequency by 2496 Bit SMOD PCON 7 also can be used to enable a multiply by two prescaler see figure 7 9 At 12 MHz oscillator frequency the commonly used baud rates 4800 baud SMOD 0 and 9600 baud SMOD 1 are available with 0 16 96 deviation The baud rate is determined by SMOD and the oscillator frequency as follows Semiconductor Group 55 SIEMENS On Chip Peripheral Components 253MOD Mode 1 3 baud rate 5496 x oscillator frequency Figure 7 10 Special Function Register ADCONO Address 008 ODE ODD ODCy ODBYy 009 008 BD BSY ADM 2 These bits are not used in controlling serial interface 0 Bit Function BD Baud rate enable When set the baud rate in modes 1 and 3 of serial interface 0 is taken from a dedicated prescaler Standard baud rates 4800 and 9600 baud at 12 MHz oscillator frequency can be achieved
232. on sequence JNB P1 S LABEL 1 JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 JNB PC lt PC if bit O then lt PC rel 0011 0000 bit address rel address Semiconductor Group 209 SIEMENS Instruction Set JNC rel Function Description Example Operation Encoding Bytes Cycles Jump if carry is not set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL1 CPL LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2 JNC lt PC 2 if C 0 then PC lt PC rel 0101 0000 rel address Semiconductor Group 210 SIEMENS Instruction Set JNZ rel Function Description Example Operation Encoding Bytes Cycles Jump if accumulator is not zero If any bit of the accumulator is a one branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displac
233. once before it changes it must be held for at least one full machine cycle In addition to the timer and counter selection timer counters 0 and 1 have four operating modes from which to select Semiconductor Group 76 SIEMENS On Chip Peripheral Components Figure 7 19 Special Function Register TCON Address 88 8Fy 8DH 8CH 88H 8BH 8AH 89H 88 TF1 1 TRO 1 1 IEO TCON Ld These bits are not used in controlling timer counter 0 and 1 Bit Function TRO Timer 0 run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD shown in figures 7 19 and 7 20 In the following descriptions the symbols THO and TLO are used specify the high byte and low byte of timer 0 TH1 and TL1 for timer 1 re
234. onents In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to contain a one 1 The external input is sampled in every machine cycle When the sampled input shows a low high level in one cycle and a high low in the next cycle a transition is recognized The timer 2 contents is latched to the appropriate capture register in the cycle following the one in which the transition was identified In mode 0 a transition at the external capture inputs of registers CCO to CC4 will also set the corresponding external interrupt request flags IEX2 to IEX6 If the interrupts are enabled an external capture signal will cause the CPU to vector to the appropriate interrupt service routine In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register The write to register signal e g write to CRCL is used to initiate a capture The value written to the dedicated capture register is irrelevant for this function The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction In this mode no interrupt request will be generated Figures 7 53 and 7 54 show functional diagrams of the capture function of timer 2 Figure 7 53 illustrates the operation of the CRC or CC4 register while figure 7 54 shows the operation of the compare capture registers 1 to 3 The two capture modes can be established individually for each
235. onents When the reload register is to be loaded with a 16 bit value the high byte of CTREL must be written first to ensure a determined start or restart position Writing to the low byte then triggers the actual reload procedure mentioned above The 16 bit reload value can be overwritten at any time Overflow Interrupt of the Compare Timer The compare timer has as any other timer in the SAB 80C517 its own interrupt request flag which is in this case called CTF This flag is located in register CTCON CTF and is set when the timer count rolls over from all ones to the reload value The overflow interrupt eases e g software control of pulse width modulated output signals A periodic interrupt service routine caused by an overflow of the compare timer can be used to load new values in the assigned compare registers and thus change the corresponding PWM output accordingly Please refer to section 8 for details about the overflow interrupt enabling vector address priority etc 7 5 3 Compare Function in the CCU The compare function of a timer register combination can be described as follows The 16 bit value stored in a compare or compare capture register is compared with the contents of the timer register the count value in the timer register matches the stored value an appropriate output signal is generated at a corresponding port pin The contents of a compare register can be regarded as time stamp at which a dedicate
236. onfiguration the compare output is set to a constant high level if the contents of the compare registers are equal to the reload register CTREL The compare output shows a high level for one timer clock period when a CMx register is set to OFFFF Thus the duty cycle can be varied from 0 xx to 100 depending on the resolution selected see calculation example in section 7 5 5 1 Please refer to figure 7 50 where the maximum and minimum duty cycle of a compare output signal is illustrated One clock period of the compare timer is equal to one machine state 2 oscillator periods if the prescaler is off Thus at 12 MHz operational frequency the spike is approx 166 6 ns long The Timer Overflow Controlled Loading There is one great difference between a CMx register and the other previously described compare registers compare outputs controlled by CMx registers have no dedicated interrupt function They use a timer overflow controlled loading further on called TOC loading to reach the same performance as an interrupt controlled compare To show what this TOC loading is for it will be explained more detailed in the following The main advantage of the compare function in general is that the controller s outputs are precisely timed by hardware no matter which task is running on the CPU This in turn means that the CPU normally does not know about the timer count So if the CPU writes to a compare register only in relation to the pr
237. onsecutive instructions directly following each other The first instruction has to set the flag PDE power down enable and must not set PDS power down set The following instruction has to set the start bit PDS Bits PDE and PDS will automatically be cleared after having been set The instruction that sets bit PDS is the last instruction executed before going into power down mode The only exit from power down mode is a hardware reset The status of all output lines of the controller can be looked up in table 7 Semiconductor Group 301 SIEMENS SAB 80C517 80C537 Table 7 Status of External Pins During Idle and Power Down Outputs Last instruction executed from Last instruction executed from internal code memory external code memory Idle Power down Idle Power Down ALE High Low High Low PSEN High Low High Low Port 0 Data Data Float Float Port 1 Data alternate Data last output Data alternate Data last output outputs outputs Port 2 Data Data Address Data Port 3 Data alternate Data last output Data alternate Data last output outputs outputs Port 4 Data alternate Data last output Data alternate Data last output outputs outputs Port 5 Data alternate Data last output Data alternate Data last output outputs outputs Port 6 Data alternate Data last output Data alternate Data last output outputs outputs Idle Mode During idle mode all peripherals of the SAB 80C517 are s
238. or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or with the ex press written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support de vice or system or to affect its safety or ef fectiveness of that device or system 2 Life support devices or systems are in tended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS Revision History SAB 80C517 80C537 User s Manual Revision History 04 95 Previous Releases 06 91 10 92 08 93 04 94 Page Subjects changes since last revision 119 Figure 7 33 writing error corrected 133 Pin assignment Table 7 10 corrected 141 Page number reference number corrected 167 Software watchdog timer start extended description 188 Description of CTF flag modified 360 ROM verification timing text added Semiconductor Group 4 SIEMENS 80C517 80C537 Table of Contents Page 1 Introduction yee SOS OE SUAE
239. ort 7 and port 8 should not toggle while a neighbouring port pin is executing an A D conversion This could produce crosstalk to the analog signal Digital I O Port Circuitry Figure 7 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the 7 l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin self is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO to P6 activate the read latch signal while others activate the read pin signal see section 7 1 4 3 Read Latch Port Port Driver Circuit pin MCS01822 Read Pin Figure 7 1 Basic Structure of a Port Circuitry Semiconductor Group 41 SIEMENS On Chip Peripheral Components Port 1 through 6 output drivers have internal pullup FET s see figure 7 2 Each line can be used independently as an input or output To be used as an input the port bit must contain a one 1 that means for figure 7 2 Q 0 which turns off the output driver FET n1 Then for ports 1 through 6 the pin is pulled high by the internal pullups but can be
240. ould among others be a complex multiple phase stepper motor control as well as the control of ignition coils of a car engine All these applications have in common that predefined bit patterns must be put to an output port at a precisely predefined moment This moment refers to a special count of timer 2 which was loaded to compare register CC4 Figure 7 46 gives an example of how to generate eight different rectangular wave forms at port 5 using a pattern table and a time schedule for these patterns The patterns are moved into port 5 before the corresponding timer count is reached The future timer count at which the pattern shall appear at the port must be loaded to register CC4 Thus the user can mask each port bit differently depending on whether he wants the output to be changed or not Concurrent compare is enabled by setting bit COCOEN in special function register CCAEN A 1 in this bit automatically sets compare mode 1 for register CC4 too A 3 bit field in special function register CC4EN determines the additional number of output pins at port 5 Port P1 4 CC4 INT2 is used as a standard output pin in any compare mode for register CC4 Semiconductor Group 112 SIEMENS On Chip Peripheral Components m gt To interrupt Logic Port Latch Circuit P1 4 dada dus Comparator COCON 1 COCON 2 COCON 3 m2 m2 NUN Timer 2 Port 5 Output Buffer 501852 Fig
241. out 1 1 s time out period 12 MHz Upward compatible to 80515 watchdog oscillator watchdog OWD monitors the on chip oscillator and forces the microcontroller to go into reset state in case the on chip oscillator fails Programmable Watchdog Timer The WDT can be activated by hardware or software Hardware initialization is done when pin PE SWD Pin 4 is held high during RESET The 80C517 then starts program execution with the WDT running Pin PE SWD doesn t allow dynamic switching of the WDT Software initialization is done by setting bit SWDT A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively A block diagram of the watchdog timer is shown in figure 11 When a watchdog timer reset occurs the watchdog timer keeps on running but a status flag WDTS is set This flag can also be manipulated by software Semiconductor Group 305 SIEMENS SAB 80C517 80C537 SIS WDT Reset Request WDTH IPO 0A9 Jes 1 j External HW Reset PE SWD Control Logic qw Tn 6 088 WDTREL MCB00788 Figure 11 Block Diagram of the Programmable Watchdog Timer Oscillator Watchdog The oscillator watchdog monitors the on chip quartz oscillator A detected oscillator failure fosc appr 300 kHz causes a hardware reset The reset state is held until the on chip oscillator is working again The oscillator watchdog feature is enab
242. ow Byte OF2 004 CML7 Compare Register 7 Low Byte OF4 00H CMSEL Compare Input Select OF7y 004 CRCH Com Rel Capt Reg High Byte OCBy 00 CRCL Com Rel Capt Reg Low Byte 0 004 CTCON Com Timer Control Reg OE1 OXXX 0000 CTRELH Com Timer Rel Reg High Byte ODF 004 CTRELL Com Timer Rel Reg Low Byte 00 004 TH2 Timer 2 High Byte OCDy TL2 Timer 2 Low Byte 004 T2CON Timer 2 Control Register 0C8 00 1 Bit addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 285 SIEMENS SAB 80C517 80C537 Table 1 Special Function Register cont d Address Register Name Register Contents after Reset Ports PO Port 0 804 1 FF P1 Port 1 90 2 Port 2 0A0 FF P3 Port 3 0BO 4 Port 4 8 1 5 Port 5 8 FF P6 Port 6 P7 Port 7 Analog Digital Input XX P8 Port 8 Analog Digital Input 4 bit ODDy Pow Sav PCON Power Control Register 87 004 Modes Serial ADCONO 2 A D Converter Control Reg 0D8 00 Channels PCON 2 Power Control Register 874 SOBUF Serial Channel 0 Buffer Reg 994 XX4 3 SOCON Serial Channel 0 Control Reg 984 00 SORELL Channel 0 Reload Reg OAAH OD9u l
243. ow byte SORELH 4 Serial Channel 0 Reload Reg XXXX XX1 18 high byte S1BUF Serial Channel 1 Buffer Reg 9C 0XX4 3 S1CON Serial Channel 1 Control Reg 9By 0X00 000g 3 S1REL Serial Channel 1 Reload Reg 9Dy 00H low byte S1RELH Serial Channel 1 Reload Reg XXXX XX1 1g high byte Timer 0 TCON Timer Control Register 88 00 Timer 1 THO Timer 0 High Byte 8 00H TH1 Timer 1 High Byte 8Dy 004 TLO Timer 0 Low Byte 8 00h TL1 Timer 1 Low Byte 8By TMOD Timer Mode Register 89 Watchdog 2 Interrupt Enable Register 0 0A8 00 IEN1 2 Interrupt Enable Register 1 0B8 1 00 IPO 2 Interrupt Priority Register 0 9 IP12 Interrupt Priority Register 1 9 XX00 0000g 9 WDTREL Watchdog Timer Reload Reg 864 1 A Semiconductor Group Bit addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks X means that the value is indeterminate and the location is reserved These registers are available in the CA step and later steps 286 SIEMENS SAB 80C517 80C537 A D Converter SAB 80C517 contains an 8 bit A D Converter with 12 multiplexed input channels which uses the successive approximation method It takes 7 machine cycles to sample an analog signal during this sample time the input signal should be held constant the
244. pare timer overflow Set by hardware at a rollover of the compare timer Bit is cleared by hardware since CA step cleared by software in BC step and earlier versions If the compare timer interrupt is enabled CTF 1 will cause an interrupt All of these bits that generate interrupts can be set or cleared by software with the same result as if they had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be cancelled by software The only exceptions are the request flags IEO and IE1 If the external interrupts 0 and 1 are programmed to be level activated IEO and IE1 are controlled by the external source via pin INTO and respectively Thus writing a one to these bits will not set the request flag IEO and or IE1 In this mode interrupts O and 1 can only be generated by software and by writing a 0 to the corresponding pins INTO P3 2 and INT1 P3 3 provided that this will not affect any peripheral circuit connected to the pins Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the special function registers IENO IEN1 and IEN2 figures 8 2 8 3 and 8 4 Note that IENO contains also a global disable bit EAL which disables all interrupts at once Also note that in the SAB 8051 the interrupt priority register IP is located at address 8 in the 80C517 this location is occupied by register IEN1 1 Only available in SAB 80C51
245. phase 1 through S6P2 state 6 phase 2 Each state lasts for two oscillator periods Typically arithmetic and logical operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 3 1 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL2 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Execution of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second is read during S4 of the same machine cycle If it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 3 1 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most SAB 80C517 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction
246. pin with respect to ground 0 5to 40 5 V Input current on any pin during overload condition 10mA to 10 Absolute sum of all input currents during overload condition 1100mAl POWSPdISSIDAllOrt Pa Ferte 2W Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Vn gt or Vin lt Vas the Voltage on pins with respect to ground Vss must not exeed the values definded by the absolute maximum ratings DC Characteristics Voc 5 10 Vas 0 T a 0to 70 C for the SAB 80C517 83C537 T a 40 to 85 for the SAB 80C517 83C537 T40 85 Symbol Limit Values Unit Test Condition min max Input low voltage except EA Vy 0 5 0 2 Vec 0 1 Input low voltage EA Vi 4 0 5 0 2 0 3 Input high voltage 0 2 0 5 V 0 9 Input high voltage to XTAL2 V iHi 0 7 0 5 V Input high voltage to RESET 2 0 6
247. processor integrated into the SAB 80C517 It has its own instruction set accumulator the carry flag bit addressable RAM and I O Semiconductor Group 170 SIEMENS Instruction Set The Bit Manipulation Instructions Allow set bit clear bit complement bit jump if bit is set jump if bit is not set jump if bit is set and clear bit move bit from to carry Addressable bits or their complements may be logically AND ed or OR ed with the contents of the carry flag The result is returned to the carry register 9 2 Introduction to the Instruction Set The instruction set is divided into four functional groups data transfer arithmetic logic control transfer 9 2 1 Data Transfer Data operations are divided into three classes general purpose accumulator specific address object None of these operations affects the PSW flag settings except a POP or MOV directly to the PSW Semiconductor Group 171 SIEMENS Instruction Set General Purpose Transfers MOV performs a bit or byte transfer from the source operand to the destination operand PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP POP transfers a byte operand from the stack location addressed by the SP to the destination operand and then decrements SP Accumulator Specific Transfers XCH exchanges the byte source operand w
248. program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged Semiconductor Group 166 SIEMENS Interrupt System 8 4 External Interrupts The external interrupts 0 and 1 can be programmed to be level activated or negative transition activated by setting or clearing bit ITO or IT1 respectively in register TCON see figure 8 5 If ITx 0 x 0 or 1 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is negative edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt If the external interrupt 0 or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external interrupts 2 and 3 can be programmed to be negative or positive transition activated by setting or clearing bit I2FR or I3FR in register T2CON see figure 8 6 If IXFR 0 x 2 or 3 external interrupt x is negative transition activated If IXFR 1 external interrupt is triggered by a positive transition The external interrupts 4 5 and 6 ar
249. put for the CMO reg P1 7 T2 29 External count or gate input to timer 2 P1 5 T2EX 31 External reload trigger input P1 4 INT2 CC4 32 Comp output capture input for CC register 4 P1 3 INT6 CC3 33 Comp output capture input for CC register 3 P1 2 INT5 CC2 34 Comp output capture input for CC register 2 P1 1 INT4 CC1 35 Comp output capture input for CC register 1 P1 0 INT3 CCO 36 Comp output capture input for CRC register 1 Pin numbering refers to the P LCC 84 package Semiconductor Group 95 SIEMENS On Chip Peripheral Components Table 7 9 Special Function Registers of the CCU Symbol Description Address CCEN Comp capture enable reg 0C1H CC4EN Comp capture 4 enable reg 0 9 CCH1 Comp capture reg 1 high byte 0C3y CCH2 Comp capture reg 2 high byte 0C5y CCH3 Comp capture reg 3 high byte 0 7 CCH4 Comp capture reg 4 high byte CCL1 Comp capture reg 1 low byte 0C2y CCL2 Comp capture reg 2 low byte 0C4y CCL3 Comp capture reg low byte 0C6H CCL4 Comp capture reg 4 low byte Compare enable register OF6y4 CMHO Compare reg 0 high byte OD3y CMH1 Compare reg 1 high byte 005 2 Compare reg 2 high byte 007 CMH3 Compare reg 3 high byte CMH4 Compare reg 4 high byte OE5y CMH5 Compare reg 5 high byte 0E7H CMH6 Compare reg 6 high byte OF3yH CMH7 Compare reg 7 high byte 5 CMLO Compare reg 0 low byte 002 CML1 Compare reg 1 low byte 0D4H
250. put pin Example The accumulator holds 564 01010110p The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the label LABEL2 with the accumulator modified to 524 01010010p Operation JBC lt 3 if bit 1 then bit 0 lt PC rel Encoding 0001 0000 bit address rel address Bytes Cycles Semiconductor Group 206 SIEMENS Instruction Set JC rel Function Description Example Operation Encoding Bytes Cycles Jump if carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice No flags are affected The carry flag is cleared The instruction sequence JC LABEL1 CPL JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 JC PC 2 if C 1 then PC PC rel 0100 0000 rel address Semiconductor Group 207 SIEMENS Instruction Set JMP A DPTR Function Description Example Operation Encoding Bytes Cycles Jump indirect Add the eight bit unsigned contents of the accumulator with the sixteen bit data pointer and load the resu
251. qual to the contents of the corresponding compare register and that the compare signal has a rising and a falling edge Furthermore the shadow latches used in compare mode 1 are transparent while the compare signal is active Thus with a slow input clock for timer 2 the comparator signal is active for a long time high number of machine cycles and therefore a fast interrupt controlled reload of the compare register could not only change the shadow latch as probably intended but also the output buffer Semiconductor Group 115 SIEMENS On Chip Peripheral Components When using the CRC or CC4 register you can select whether an interrupt should be generated when the compare signal goes active or inactive depending on the status of bits or I2FR in T2CON respectively Initializing the interrupt to be negative transition triggered is advisive in the above case Then the compare signal is already inactive and any write access to the port latch just changes the contents of the shadow latch Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal goes active The second configuration which should be noted is when compare functions are combined with negative transition activated interrupts If the port latch of port P1 0 or P 1 4 contains a 1 the interrupt request flags IEX3 or IEX2 will immediately be set after enabling the compare mode for the CRC or CCA register The reason is th
252. r Semiconductor Group 24 SIEMENS Memory Organization Stack Pointer SFR Address 081 The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin at location 084 above register bank zero The SP can be read or written under software control Datapointer SFR Address 0824 and 0834 Datapointer Select Register SFR Address 0924 As a functional enhancement to standard 8051 controllers the SAB 80C517 contains eight 16 bit registers which can be used as datapointers To be compatible with 8051 architecture the instruction set uses just one of these datapointers at a time The selection of the actual datapointer is done in special function register DPSEL datapointer select register address 92 Each 16 bit datapointer DPTRx register is a concatenation of registers DPHx data pointer s high order byte and DPLx data pointer s low order byte These pointers are used in register indirect addressing to move program memory constants and external data memory variables as well as to branch within the 64 Kbyte program memory address space Since the datapointers are mainly used to access the external world they are descri
253. r O 9 XXH MD1 Multiplication Division Register 1 XXH MD2 Multiplication Division Register 2 OEBH XXH MD3 Multiplication Division Register 3 XXH MD4 Multiplication Division Register 4 0EDH XXH 5 Multiplication Division Register 5 XXH 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate Semiconductor Group 21 SIEMENS Memory Organization Special Function Registers of the SAB 80C517 cont d Block Symbol Name Address Contents after Reset Compare CCEN Compare Capture Enable Register 0C1H 00H Capture CC4EN Compare Capture 4 Enable Register 0 9 X000 0000p Unit CCH1 Compare Capture Register 1 High Byte 0 00H CCU CCH2 Compare Capture Register 2 High Byte 0C5y 00H CCH3 Compare Capture Register High Byte 0 7 00H CCH4 Compare Capture Register 4 High Byte 0 00H CCL1 Compare Capture Register 1 Low Byte 0C2H 00H 12 Compare Capture Register 2 Low Byte 0C4y 00H CCL3 Compare Capture Register 3 Low Byte 0C6H 00H CCL4 Compare Capture Register 4 Low Byte 00H CMEN Compare Enable Register OF6y4 00H CMHO Compare Register 0 High Byte 00H CMH1 Compare Register 1 High Byte OD5y 00H CMH2 Compare Register 2 High Byte 0D7H 00H CMH3 Compare Register 3 High Byte 00H CMH4 Compare Regis
254. r data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that an SAB 80C517 program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use Semiconductor Group 32 SIEMENS External Bus Interface 5 3 PSEN Program Store Enable The read strobe for external fetches is PSEN PSEN is not activated for internal fetches When the CPU is accessing external program memory PSEN is activated twice every cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 12 osillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 6 oscillator periods The execution sequence for these two types of read cycles is shown in figure 5 2 a and b 5 4 ALE Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from PO into an external latch during fetches from external memory The address byte is valid at the negative transition of ALE For that purpose ALE is activated twice every machine cycle This activation takes place even if the cycle involves no external fetch The only time no ALE pulse comes out is during
255. r holding the value 694 01101001 p When the destination is a directly addressed byte this instruction can complement combinations of bits in any RAM location or hardware register The pattern of bits to be complemented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B will complement bits 5 4 and 0 of output port 1 XRL A Rn Operation Encoding Bytes Cycles XRL2 lt Rn 01101 1 Semiconductor Group 248 SIEMENS Instruction Set XRL A direct Operation XRL lt A v direct Encoding 01100101 direct address Bytes 2 Cycles 1 XRL A Ri Operation XRL lt A v Ri Encoding 01100111 Bytes 1 Cycles 1 XRL A data Operation XRL lt A v data Encoding 01100100 immediate data Bytes 2 Cycles 1 XRL direct A Operation XRL direct lt direct v A Encoding 01100010 direct address Bytes 2 Cycles 1 Semiconductor Group 249 SIEMENS Instruction Set XRL direct data Operation XRL direct lt direct v data Encoding 0110 00411 direct address immediate data Bytes Cycles 2 Semiconductor Group 250 SIEMENS Instruction Set Instru
256. red as inputs and should not be stimulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins A pullup resistor is internally connected to to allow a power up reset with an external capacitor only An automatic reset can be obtained when is applied by connecting the reset pin to Vas a capacitor as shown in figure 6 1 a and c After has been turned on the capacitor must hold the voltage level at the reset pin for a specified time below the upper threshold of the Schmitt trigger to effect a complete reset Semiconductor Group 35 SIEMENS System Reset The time required is the oscillator start up time plus 2 machine cycles which under normal conditions must be at least 10 20 ms for a crystal oscillator This requirement is usually met using a capacitor of 4 7 to 10 microfarad The same considerations apply if the reset signal is generated externally figure 6 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive RESET SAB 80C517 RESET SAB 80C517 Q t RESET V SAB 80C517 MCS01820 Figure 6 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 0000 The
257. representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affected RO contains the address 204 The accumulator holds the value 364 001101108 Internal RAM location 204 holds the value 75 4 011101016 The instruction XCHD will leave RAM location 204 holding the value 764 01110110p and 35H 001101016 in the accumulator XCHD A3 0 Ri 3 0 110110111 Semiconductor Group 247 SIEMENS Instruction Set XRL lt dest byte gt lt src byte gt Function Description Example Logical Exclusive OR for byte variables XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch notthe input pins If the accumulator holds 110000116 and register 0 holds 10101010B then the instruction XRL A RO will leave the accumulato
258. riction of module Range 0 195 icti 0 556 x2 100 0 195 This leads to a variation of the duty cycle from 0 195 to 99 805 for a timer 2 CCx register configuration when 8 of 16 bits are used Compare Function of Register CC4 Concurrent Compare Compare register CC4 is new in the SAB 80C517 and permanently assigned to timer 2 It has its own compare capture enable register CC4EN see figure 7 47 Register CC4 can be set to operate as any of the other CC registers see also figures 7 42 and 7 43 Its output pin is P1 4 CC4 INT2 and it has a dedicated compare mode select bit COMO located in register CC4EN In addition to the standard operation in compare mode 0 or 1 there is another feature called concurrent compare which is just an application of compare mode 1 to more than one output pin Concurrent compare means that the comparison of CC4 and timer 2 can manipulate up to nine port pins concurrently A standard compare register in compare mode 1 normally transfers a preprogrammed signal level to a single output line Register CC4 however is able to put a 9 bit pattern to nine output lines The nine output lines consist of one line at port P1 4 which is the standard output for register CC4 and an additional eight lines at port 5 see figure 7 45 Concurrent compare is an ideal and effective option where more than one synchronous output signal is to be generated Applications including this requirement c
259. rol of the instruction decoder The ALU performs the arithmetic operations add subtract multiply divide increment decrement BCD decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations of set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The A B and PSW registers are described in section 4 4 The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The PC is manipulated by the control transfer instructions listed in the chapter Instruction Set The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Semiconductor Group 13 SIEMENS Central Processing Unit 3 2 CPU Timing A machine cycle consists of 6 states 12 oscillator periods Each state is divided into a phase 1 half during which the phase 1 clock is active and a phase 2 half during which the phase 2 clock is active Thus a machine cycle consists of 12 oscillator periods numbered S1P1 state 1
260. rol unit 7 7 Watchdog unit WDT OWD 7 8 Interrupt system 8 Semiconductor Group 26 SIEMENS External Bus Interface 5 External Bus Interface The SAB 80C517 allows for external memory expansion To accomplish this the external bus interface common to most 8051 based controllers is employed To speed up external bus accesses the SAB 80C517 contains eight 16 bit registers used as datapointers This enhancement to the 8051 architecture is described in section 5 2 5 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware Accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 see section 7 1 Port 0 and port 2 with exceptions are used to provide data and address signals In this section only the port 0 and port 2 functions relevant to external memory accesses are described for further details see chapter 7 1 Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or 8 bit address MOVX Ri Role of PO and P2 as Data Address Bus When used for accessing external memory port 0 provides the data byte time multiplexed with the low b
261. rrupts The baud rate clock for this interface is generated by a dedicated baud rate generator A more detailed description how to set the baud rate follows in section 7 2 2 3 and 7 2 2 4 Mode A 9 bit UART variable baud rate 11 bits are transmitted through TxD1 or received through RxD1 a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmission the 9th data bit TB81 in 1 can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB81 or a second stop bit by setting TB81 to 1 On reception the 9th data bit goes into RB81 in special function register SOCON while the stop bit is ignored In fact mode A of serial interface 1 is identical with mode 2 or 3 of serial interface 0 in all respects except the baud rate generation see section 7 2 2 3 Mode B 8 bit UART variable baud rate 10 bits are transmitted through TxD1 or received through RxD1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB81 in special function register S1CON In fact mode B of serial interface 1 is identical with mode 1 of serial interface O in all respects except for the baud rate generation see section 7 2 2 3 In both modes transmission is initiated by any instruction that uses S1BUF as a destination register Reception is initiated by the incoming start bit if REN1 1 The serial interfaces also provide
262. rsion in this case conversion starts when a falling edge at pin P6 0 ADST is detected In single conversion mode one conversion is performed until the next falling edge at P6 0 ADST is recognized In continuous mode new conversions are started automatically as long as pin P6 0 ADST is on low level This is done until P6 0 ADST goes to logic high level in this case the last commenced conversion is completed 7 4 2 Reference Voltages The SAB 80C517 has two pins to which a reference voltage range for the on chip A D converter is applied pin Varer for the upper voltage and pin Vienn for the lower voltage In contrast to conventional A D converters it is now possible to use not only these externally applied reference voltages for the conversion but also internally generated reference voltages which are derived from the externally applied ones For this purpose a resistor ladder provides 16 equidistant voltage levels between Virer These steps can individually be assigned as upper and lower reference voltage for the converter itself These internally generated reference voltages are called Vintarer and Vintaano The internal reference voltage programming can be thought of as a programmable D A converter which provides the voltages Vintages and for the A D converter itself Semiconductor Group 87 SIEMENS On Chip Peripheral Components The SFR DAPR see figure 7 29 is provided for programming the internal reference
263. rupts 2 and 3 can be programmed for triggering on a negative or a positive transition The external interrupts 2 to 6 are combined with the corresponding alternate functions compare output and capture input on port 1 For programming of the priority levels the interrupt vectors are combined to pairs or triples Each pair or triple can be programmed individually to one of four priority levels by setting or clearing one bit in special function register IPO and one in IP1 Figure 9 shows the interrupt request sources the enabling and the priority level structure Semiconductor Group 295 SIEMENS SAB 80C517 80C537 Highest Priority Level Receiver Ser Channel 1 Transmitter A D Converter 2 C m t2 V m Timer 0 Overflow 5 Q5 O U lt 500785 Figure 9 Interrupt Structure Semiconductor Group 296 SIEMENS SAB 80C517 80C537 Highest Priority Level Timer 1 Overflow Compare Timer Overflow re P1 1 INT4 CC1 Receiver Ser Channel 0 Transmitter 5 Q5 07U P1 2 INT5 CC2 Timer 2 Overflow P1 5 T2EX P1 3 INT6 CC3 MCS00786 Figure 9 cont d Interrupt Structure Semiconductor Group 297 SIEMENS SAB 80C517 80C537 Multiplication Division Unit This on chip arithmetic unit provides fast 32 bit
264. s input Port 0 and port 2 can be used to expand the program and data memory externally During an access to external memory port 0 emits the low order address byte and reads writes the data byte while port 2 emits the high order address byte In this function port 01 not an open drain port but uses a strong internal pullup FET Port 1 3 4 5 and port 6 provide several alternate functions Please see the Pin Description for details Port pins show the information written to the port latches when used as general purpose port When an alternate function is used the port pin is controlled by the respective peripheral unit Therefore the port latch must contain a one for that function to operate The same applies when the port pins are used as inputs Ports 1 3 4 and 5 are bit addressable The SAB 80C517 has two dual purpose input ports The twelve port lines at port 7 and port 8 can be used as analog inputs for the A D converter If input voltages at P7 and P8 meet the specified digital input levels Vj and Vj the port can also be used as digital input port Semiconductor Group 300 SIEMENS SAB 80C517 80C537 Power Saving Modes SAB 80C517 provides due to Siemens ACMOS technology three modes in which power consumption can be significantly reduced The Slow Down Mode The controller keeps up the full operating functionality but is driven with the eighth part of its normal operating frequency Slowing down t
265. s maintained until the on chip oscillator is working again This ensures a maximum of system protection with a minimum of susceptibility to distortion or to operating errors In the reset state all port pins of the 80C517 show a 1 The oscillator watchdog consists of an integrated RC oscillator combined with a frequency comparator If the on chip oscillator s frequency falls below the frequency of the RC oscillator the comparator generates a signal which initiates a reset The RC oscillator runs with a frequency of typically 300 kHz and works without any external components It also determines as long as it is used the lower limit of the SAB 80C517 s operating frequency which is therefore specified at 1 MHz Since the frequency comparator of the oscillator watchdog takes its inputs directly from the on chip oscillator the minimum frequency of 1 MHz does not restrict the use of the slow down mode In this mode the CPU runs with one eighth of the normal clock rate see section 7 7 The oscillator watchdog circuitry can be enabled externally If the OWE pin oscillator watchdog enable is pulled low the oscillator watchdog function is off If the pin is left unconnected or has a logic high level the watchdog oscillator is activated Thus the watchdog is enabled even if the pin or the path to the pin is broken Like the watchdog timer circuitry the oscillator watchdog circuitry contains a status flip flop This flip flop is set whe
266. s supplied in a 84 pin plastic leaded chip carrier package P LCC 84 and in a 100 pin plastic quad metric flat package P MQFP 100 2 Ordering Information Type Ordering Code Package Description 8 bit CMOS Microcontroller SAB 80C517 M TBD P MQFP 100 2 ble ROM 12 MHz SAB 80C537 N Q67120 C452 P LCC 84 for external memory 12 MHz SAB 80C537 M TBD P MQFP 100 2 SAB 80C517 N T40 85 Q67120 C483 P LCC 84 with factory mask programma ble ROM 12 MHz SAB 80C517 M T40 85 P MQFP 100 2 ext temperature 40 to 85 C SAB 80C537 N T40 85 Q67120 C484 P LCC 84 for external ROM 12 MHz 80C537 M T40 85 P MQFP 100 2 xt temperature 40 to 85 SAB 80C517 N16 Q67120 C723 P LCC 84 with mask programmable SAB 80C517 M16 TBD PAXIGEBSUGS aoi MAZ Cextatemperagire j E 7 140 to 110 C SAB 80C537 N16 Q67120 C722 P LCC 84 for external memory 16 MHz SAB 80C537 M16 TBD 100 2 80C517 N16 T40 85 Q67120 C724 P LCC 84 with mask programmable ROM 16 MHz ext temperature 40 to 85 C SAB 80C517 16 N T40 85 Q67120 C725 P LCC 84 with factory mask programma ble ROM 12 MHz Semiconductor Group 266 SIEMENS SAB 80C517 80C537 Voc Vss Port 7 8 bit Port 0 8 8 bit 4 bit Port 1 d lt gt si AGND LN Port 2 _ ONE E E PE SWD SAB Bn Port 3 RO 80C517 RESET 80C537 Port 4 __ 8 bit EA ALE Port 5 8 bit PSEN
267. s the start bit to TxDO TxD1 One bit time later DATA is activated which enables the output bit of transmit shift register to TxDO TxD1 The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeros are clocked in Thus as data shift out to the right zeros are clocked in from the left When TB80 TB81 is at the output position of the shift register then the stop bit is just left of the TB80 TB81 and all positions to the left of that contain zeros Semiconductor Group 68 SIEMENS On Chip Peripheral Components This condition flags the TX control unit to do one last shift and then deactivate SEND and set TIO This occurs at the 11th divide by 16 rollover after write to SOBUF S1 BUF Reception is initiated by a detected 1 to 0 transition at RxDO RxD1 For this purpose RxDO RxD1 is sampled of a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1 is written to the input shift register At the 7th 8th and 9th counter state of each bit time the bit detector samples the value of RxDO RxD1 The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves vali
268. ses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table 1 Start address of table in external RAM 2FA0H Semiconductor Group 30 SIEMENS External Bus Interface 1 Using only One Datapointer Code for an 8051 Initialization Routine Action Code Initialize shadow_variables with source_pointer MOV LOW SRC_PTR 0FFH MOV HIGH SRC_PTR 1FH Initialize shadow variables with destination_pointer MOV LOW DES_PTR 0A0H MOV HIGH DES_PTR 2FH Table Look up Routine under Real Time Conditions Action Code Machine Cycles Save old datapointer PUSH DPL 2 PUSH DPH 2 Load Source Pointer MOV DPL LOW SRC_PTR 2 MOV DPH HIGH SRC_PTR 2 Increment and check for end of table INC DPTR execution time not relevant for this CJNE consideration ndi Fetch source data byte from ROM table MOVC A 2 Save source pointer and load MOV LOW SRC DPL 2 destination pointer MOV HIGH
269. sion SHIFT CLOCK remains high At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register is shifted one position to the right As data bits shift to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just left of the MSB and all positions to the left of that contain zeros This condition flags the TX control block to do one last shift and then deactivates SEND and sets TIO Both of these actions occur at S1P1 in the 10th machine cycle after write to SOBUF Reception is initiated by the condition RENO 1 and RIO 0 At S6P2 in the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at 3 1 and S6P1 in every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted one position to the left The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 in the same machine cycle As data bits come in from the right 1 s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX control b
270. sion and shift Its operations can be divided into three phases see also figure 7 55 1 Loading the MDx registers 2 Executing the calculation 3 Reading the result from the MDx registers During phase two the MDU works on its own parallelly to the CPU Execution times of the above table refer to this phase Because of the fast operation and the determined execution time for SAB 80C517 s instructions there is no need for a busy flag The CPU may execute a determined number of instructions before the result is fetched The result and the remainder of an operation may also be stored in the MDx registers for later use Phase one and phase three require CPU activity In these phases the CPU has to transfer the operands and fetch the results 1st Write 00 Last Write MD5 or ARCON First Read Last Read MDO MD3 or MD5 v v Phase 1 Phase 2 gt Phase 3 gt Load Registers Calculate Read Registers Time MCA00787 Figure 7 55 Operating Phases of the MDU Semiconductor Group 127 SIEMENS On Chip Peripheral Components How to Select an Operation The MDU has no dedicated instruction register only for shift and normalize operations register is used in such way The type of calculation the MDU has to perform is selected following the order in which the MDx registers are written to see table 7 11 This mechanism also reduces execution time spent for controlling the MDU Hen
271. sions the SAB 80C517 and the SAB 80C537 unless otherwise noted Figure 1 1 shows the logic symbol of the SAB 80C517 Voc Vss Port 0 8 bit Port 1 8 bit Port 2 8 bit Port 3 8 bit Port 4 8 bit Port 5 8 bit Port 6 8 bit TII MCL00776 Figure 1 1 Logic Symbol Semiconductor Group 9 SIEMENS Fundamental Structure 2 Fundamental Structure The SAB 80C517 is a totally 8051 compatible microcontroller while its peripheral performance has been increased significantly It includes the complete SAB 80 C 515 providing 100 upward compatibility This means that all existing 80515 programs or user s program libraries can be used further on without restriction and may be easily extended to the new SAB 80C517 The SAB 80C517 is in the Siemens line of highly integrated microcontrollers for control applications Some of the various on chip peripherals have been added to support the 8 bit core in case of stringent real time requirements The 32 bit 16 bit arithmetic unit the improved 4 level interrupt structure and the increased number of eight 16 bit datapointers are meant to give such a CPU support But strict compatibility to the 8051 architecture is a principle of the SAB 80C517 s design Furthermore the SAB 80C517 contains three additional 8 bit I O ports and twelve general input lines The additional serial channel is compatible to an 8051 UART and provided with an independent and freely program
272. spectively The operating modes are described and shown for timer O If not explicitly noted this applies also to timer 1 Semiconductor Group 77 SIEMENS On Chip Peripheral Components Figure 7 20 Special Function Register TMOD Address 89 894 GATE C T M1 MO M1 MO TMOD Timer 1 Timer 0 Timer counter 0 1 mode control register Bit Symbol Gate Gating control When set timer counter x is enabled only while INTx pin is high and control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock 8 bit timer counter operates as 8 bit timer counter TLx serves as 5 bit prescaler 16 bit timer counter and TLx are cascaded there is no prescaler 8 bit auto reload timer counter THX holds a value which is to be reloaded into TLx each time it overflows Timer 0 TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THOO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 78 SIEMENS On Chip Peripheral Components 7 3 1 Mode 0 Putting either timer counter into mode 0 configures it as an 8 bi
273. st output Port 4 Data alternate Data Data alternate Data outputs last output outputs last output Port 5 Data alternate Data Data alternate Data outputs last output outputs last output Port 6 Data alternate Data Data alternate Data outputs last output outputs last output The watchdog timer is the only peripheral which is automatically stopped during idle The idle mode makes it possible to freeze the processor s status for a certain time or until an external event causes the controller to go back into normal operating mode Since the watchdog timer is stopped during idle mode this useful feature of the SAB 80C517 is provided even if the watchdog function is used simultaneously If the idle mode is to be used the pin PE SWD must be held low Entering the idle mode is to be done by two consecutive instructions immediately following each other The first instruction has to set the flag bit IDLE PCON 0 and must not set bit IDLS PCON 5 the following instruction has to set the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS will not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after having been set If one of these register bits is read the value shown is zero 0 Figure 7 57 shows special function register PCON This double instruction sequence is implemented to minimize the chance of unintentionally entering the
274. t after RD tRHDZ 97 214 70 Ins ALE to valid data fLDV 517 81c c 150 ns Address to valid data tAypy 585 9 tereL 165 ins ALE to WR or RD fLLWL 200 300 3 50 50 ns WR or RD high to ALE 43 123 tere 40 40 ns high Address valid to WR fAVWL 203 4fcici 130 ns Data valid to WR tavwx 33 50 ns transition Data setup before WR tqvwx 433 7 150 ns Data hold after WR tWHOX 33 50 ns Address float after RD az 0 0 ns Semiconductor Group 314 SIEMENS SAB 80C517 80C537 AC Characteristics 5 10 Vsgs 0V TA 0 to 70 for the 80C517 16 83C537 16 T a 40 to 85 for the SAB 80C517 16 83C537 16 T40 85 for port 0 ALE and PSEN outputs 100pF C for all outputs 80 pF Parameter Symbol Limit Values Unit 16 MHz Clock Variable Clock 1 t ci cL 3 5 MHz to 16 MHz min max min max Program Memory Characteristics ALE pulse width fLHLL 85 2tc cL 740 ns Address setup to ALE tAVLL 33 tcLcL 30 ns Address hold after 1 Ax 28 35 ns ALE to valid instr in fLLIV 150 100 jns ALE to PSEN 38 25 ns PSEN pulse width 153 35 l ns PSEN to valid instr in 88 100 ns Input instruction hold tPXIX 0
275. t edge was detected or when a compare event occurred at pin 1 0 INT3 CCO Cleared when interrupt is initiated IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 1 INT4 CC1 Cleared when interrupt is initiated IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 2 INT5 CC2 Cleared when interrupt is initiated IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 3 INT6 CC3 Cleared when interrupt is initiated TF2 Timer 2 overflow flag Set by timer 2 overflow Must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt EXF2 Timer 2 external reload flag Set when a reload is caused by a negative transition on pin T2EX while EXEN2 1 When the timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector the timer 2 interrupt routine Can be used as an additional external interrupt when the reload function is not used EXF2 must be cleared by software Semiconductor Group 160 SIEMENS Interrupt System Figure 8 8 Special Function Register CTCON Address 0 1 OE1y CTCON T2PS1 1 These bits are not used for interrupt control Bit Function CTF Com
276. t timer counter with a divide by 32 prescaler Figure 7 21 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all O s it sets the timer overflow The overflow then can be used to request an interrupt see section 8 for details about the interrupt structure The counted input is enabled to the timer when TRO 1 and either GATE 0 or INTO 1 setting GATE 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON GATE is in TMOD The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TR1 TF1 TH1 TL1 and INT1 for the corresponding timer 1 signals in figure 7 21 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 OSC nterru TLO THO TFO P 5 Bits 8 Bits TO Pin C T 1 Control INTO Pin MCS01837 Figure 7 21 Timer Counter 0 1 Mode 0 13 Bit Timer Counter Semiconductor Group 79 SIEMENS On Chip Peripheral Components 7 3 2 Mode 1 Mode 1 is the same as mode 0 except that the timer register is run with all 16 bits Mode 1 is s
277. tate can be used as inputs As inputs port 3 pins being externally pulled low will source current in the DC characteristics because of the internal pull up resistors Port 3 also contains the interrupt timer serial port 0 and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows Rx DO P3 0 receiver data input asynchronous or data input output synchronous of serial interface Tx DO P3 1 transmitter data output asynchronous or clock output synchronous of serial interface 0 INTO P3 2 interrupt 0 input timer 0 gate control INT1 P3 3 interrupt 1 input timer 1 gate control TO P3 4 counter 0 input T1 P3 5 counter 1 input WR P3 6 the write control signal latches the data byte from port 0 into the external data memory RD P3 7 the read control signal enables the external data memory to port O Input Output Semiconductor Group 272 SIEMENS SAB 80C517 80C537 Pin Definitions and Functions cont d Symbol Pin Number l O Function P LCC 84 P MQFP 100 2 P1 7 P1 0 29 36 98 100 Port 1 1 6 9 is a bidirectional I O port with internal pull up resistors Port 1 pins that have 1 s written to them are pulled high by the i
278. te to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port 0 before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe For further information see section 5 3 External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active or whenever the program counter PC contains a number that is larger than O1FFFY This requires the ROMless version SAB 80C537 to have EA wired low to allow the lower 8 program bytes to be fetched from external memory When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose The contents of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is a MOVX DPTR or a MOVX Ri Since the SAB 80C537 has no internal program memory accesses to program memory are always external and port 2 is at all times dedicated to output the high order address byte This means that port and port 2 of the 80C537 can never be used as general purpose This also applies to the SAB 80C517 when it is operated with on
279. ter 4 High Byte 0E5H 5 Compare Register 5 High Byte OE7y 00H CMH6 Compare Register 6 High Byte OF3y 00H CMH7 Compare Register 7 High Byte 5 00H CMLO Compare Register 0 Low Byte 0D24H 00H CML1 Compare Register 1 Low Byte 0D4y 00H CML2 Compare Register 2 Low Byte 0D6H 00H CML3 Compare Register 3 Low Byte OE2y 00H CML4 Compare Register 4 Low Byte 4 00H CML5 Compare Register 5 Low Byte 0E6H CML6 Compare Register 6 Low Byte OF2y 00H CML7 Compare Register 7 Low Byte OF4y 00H CMSEL Compare Input Select 7 00H CRCH Com Rel Capt Register High Byte OCByY 00H CRCL Com Rel Capt Register Low Byte OCA 00H CTCON Com Timer Control Register OE1y OXXX 0000p CTRELH Com Timer Rel Register High Byte ODFy 00H CTRELL Com Timer Rel Register Low Byte ODEY 00H TH2 Timer 2 High Byte 00H TL2 Timer 2 Low Byte 0CCH 00H T2CON Timer 2 Control Register 0C8Q 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate Semiconductor Group 22 SIEMENS Memory Organization Special Function Registers of the SAB 80C517 cont d Block Symbol Name Address Contents after Reset Ports PO Port 0 80H FFy P1 Port 1 90 FFy P2 Port 2 FFy P3 Port 3 OBOy FFy P4 Port 4 OE8y FFy P5 Port
280. ter Program Register ODA 004 Interrupt IENO Interrupt Enable Register 0 0A84 004 System 2 Timer Control Register 1 0XXX 0000g IEN1 Interrupt Enable Register 1 0B84 00 IEN2 Interrupt Enable Register 2 9 XXXX 00X0g 3 IPO Interrupt Priority Register 0 9 004 IP1 Interrupt Priority Register 1 OBS XX00 0000p IRCON Interrupt Request Control Register 0CO 7 00 TCON 2 Timer Control Register 884 00 T2CON Jimer 2 Control Register 0 8 004 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 Xmeans that the value is indeterminate and the location is reserved Semiconductor Group 283 SIEMENS SAB 80C517 80C537 Table 1 Special Function Register cont d Address Register Name Register Contents after Reset MUL DIV ARCON Arithmetic Control Register OXXX XXXXg Unit MDO Multiplication Division Register 0 OE9 XX MD1 Multiplication Division Register 1 MD2 Multiplication Division Register 2 OEBy Multiplication Division Register MD4 Multiplication Division Register 4 OEDy MD5 Multiplication Division Register 5 OEE XX 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional b
281. the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The stack pointer originally contains the value OBy Internal RAM locations OAH and OBy contain the values 234 and 01 respectively The instruction RET will leave the stack pointer equal to the value 094 Program execution will continue at location 01234 Operation RET PC15 8 SP SP SP 1 PC7 0 lt SP SP SP 1 Encoding 0010 0010 Bytes 1 Cycles 2 Semiconductor Group 234 SIEMENS Instruction Set RETI Function Description Example Operation Encoding Bytes Cycles Return from interrupt RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The stack pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt is pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed The stack pointer originally contains the value OBy An interrupt was detected during the
282. the binary machine language encoding and a symbolic description or restatement of the function is also provided Note Only the carry auxiliary carry and overflow flags are discussed The parity bit is computed after every instruction cycle that alters the accumulator Similarily instructions which alter directly addressed registers could affect the other status flags if the instruction is applied to the PSW Status flags can also be modified by bit manipulation Semiconductor Group 176 SIEMENS Instruction Set Notes on Data Addressing Modes Rn direct Ri data 16 bit A z Working register RO R7 128 internal RAM locations any port control or status register Indirect internal or external RAM location addressed by register RO or R1 8 bit constant included in instruction 16 bit constant included as bytes 2 and 3 of instruction 128 software flags any bit addressable I O pin control or status bit Accumulator Notes on Program Addressing Modes addr16 addr1 1 rel Destination address for LCALL and LUMP may be anywhere within the 64 Kbyte program memory address space Destination address for ACALL and AJMP will be within the same 2 Kbyte page of program memory as the first byte of the following instruction SJMP and all conditional jumps include an 8 bit offset byte Range is 127 128 bytes relative to the first byte of the following instruction All mnemonics copyrighted
283. till supplied by the oscillator clock Thus the user has to take care which peripheral should continue to run and which has to be stopped during Idle The procedure to enter the Idle mode is similar to entering the power down mode The two bits IDLE and IDLS must be set by to consecutive instructions to minimize the chance of unintentional activating of the idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on The control signals ALE and PSEN hold at logic high levels see table 7 Semiconductor Group 302 SIEMENS SAB 80C517 80C537 Table 8 Baud Rate Generation Function Serial Interface 0 Serial Interface 1 Mode Mode 0 8 Bit Baud rate 1 MHz fosc 12 MHz synchronous channel Baud rate fosc E derived from Mode Mode 1
284. tion Data setup before WR tqywu 288 7 150 ns Data hold after WR tWHOX 13 50 ns Address float after RD az 0 0 ns Semiconductor Group 316 SIEMENS SAB 80C517 80C537 ALE Port 0 Port 2 8 15 8 15 MCTO0790 Program Memory Read Cycle ALE RD Faval teupz 40 7 V N 40 47 RI DPL AL AA Data In 1777 from PCL Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH 00791 Data Memory Read Cycle Semiconductor Group 317 SIEMENS SAB 80C517 80C537 ALE PSEN tum e tum WR lovwx 1 LLAX2 Port 0 Instr IN A0 A7 from PCL e Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00098 Data Memory Write Cycle Semiconductor Group 318 SIEMENS SAB 80C517 80C537 AC Characteristics cont d Parameter Symbol Limit Values Unit Variable Clock Frequ 3 5 MHz to 12 MHz min max External Clock Drive Oscillator period fcLCL 83 3 285 ns Oscillator frequency 1 35 12 MHz High time CHCX 20 ns Low time tC
285. ts of two separate latches The upper latch which acts as a shadow latch can be written under software control but its value will only be transferred to the output latch and thus to the port pin in response to a compare match Note that the double latch structure is transparent as long as the internal compare signal is active While the compare signal is active a write operation to the port will then change both latches This may become important when driving timer 2 with a slow external clock In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch For details see also section 7 5 5 1 Using Interrupts in Combination with the Compare Function A read modify write instruction see section 7 1 will read the user controlled shadow latch and write the modified value back to this shadow latch A standard read instruction will as usual read the pin of the corresponding compare output Semiconductor Group 106 SIEMENS On Chip Peripheral Components Compare Register Circuit Compare Latch Shadow Latch Port Circuit Timer Register Output Latch Timer Circuit MCS01848 O Pin Figure 7 40 Compare Function of Compare Mode 1 7 5 5 Timer Compare Register Configurations in the CCU The compare function and the reaction of the corresponding outputs depend on the timer compare register combination Basically all compare
286. ty levels see chapter 8 2 Figure 8 1 gives a general overview of the interrupt sources and illustrates the request and control flags described in the next sections The priority structure and the corresponding control bits are listed in section 8 2 8 1 Interrupt Structure A common mechanism is used to generate the various interrupts each source having its own request flag s located in a special function register e g TCON IRCON SOCON 1 Provided the peripheral or external source meets the condition for an interrupt the dedicated request flag is set whether an interrupt is enabled or not For example each timer 0 overflow sets the corresponding request flag TFO If it is already set it retains a one 1 But the interrupt is not necessarily serviced Now each interrupt requested by the corresponding flag can individually be enabled or disabled by the enable bits in SFR s IENO IEN1 IEN2 see figure 8 2 8 3 and 8 4 This determines whether the interrupt will actually be performed In addition there is a global enable bit for all interrupts which when cleared disables all interrupts independent of their individual enable bits Semiconductor Group 152 SIEMENS Interrupt System Highest Priority Level P3 2 M INTO Lowest Priority Level Receiver RI 21 Ser Channel 1 Transmitter T A D Converter Timer 0 Overflow TFO DODOLCQ0WN Q5 07U MCS00785 Figure 8
287. uction before being added to the accumulator otherwise the base register is not altered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected A value between 0 and 3 is in the accumulator The following instructions will translate the value in the accumulator to one of four values defined by the DB define byte directive REL_PC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01 it will return with 774 in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead MOVC A A DPTR Operation Encoding Bytes Cycles MOVC lt A DPTR 100110011 Semiconductor Group 222 SIEMENS Instruction Set MOVC A QA PC Operation MOVC PC PC 1 lt 1000 0011 Bytes 1 Cycles 2 Semiconductor Group 223 SIEMENS Instruction Set MOVX lt dest byte gt lt src byte gt Function Description Example Move external The MOVX instructions transfer data between the accumulator and a byte of external data memory hence the appended to MOV There are two types of instruct
288. uctor Group 43 SIEMENS On Chip Peripheral Components If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with 0 the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH 2 SOH state If it is used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 the pin might remain in the IL state and provide a weak 1 until the first 0 to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities Port 0 in contrast to ports 1 through 6 is considered as true bidirectional because the port 0 pins float w
289. ud 12 0 0 0 1 Figure 7 11 shows the mechanisms for baud rate generation of serial channel 0 while table 7 5 summarizes the baud rate formulas for all usual configurations Phase 2 CLK Timer 1 fosc 2 Overflow Baud Rate Clock MCS01829 Figure 7 11 Generation of Baud Rates for Serial Channel 0 Semiconductor Group 57 SIEMENS On Chip Peripheral Components Table 7 5 Baud Rates of Serial Interface 0 Baud Rate Derived Interface Baud Rate from Mode Timer 1 in mode 1 1 3 2SMOD see table 7 4 5 X 16 x timer 1 overflow rate Timer 1 in mode 2 1 3 2SMOD Jose see table 7 4 X X 2 16 12x 256 TH1 Oscillator 2 29M0D 1 X X 2 16 2 BD 1 3 2SMOD 1 po X X 2 16 1248 7 2 1 4 New Baud Rate Generator for Serial Channel 0 The SAB 80C517 devices with stepping code CA or later have a new baud rate generator for serial channel 0 which provides greater flexibility and better resolution It substitutes the 80C517 s baud rate generator at Serial Channel 0 which provides only 4 8 kBaud or 9 6 kBaud at 12 MHz crystal frequency Since the new generator offers greater flexibility it is often possible to use it instead of Timer1 which is then free for other tasks Figure 7 11a shows a block diagram of the new baud rate generator for Serial Channel 0 It consists of a free running 10 bit timer with fosc 2 input frequency On overflow of this
290. ues an appropriate output signal is generated and an interrupt is requested Two compare modes are provided Mode 0 Upon a match the output signal changes from low to high It goes back to low level when the timer overflows Mode 1 The transition of the output signal can be determined by software A timer overflow signal doesn t affect the compare output Compare registers CMO to CM7 use additional compare latches when operated in mode 0 Figure 8 shows the function of these latches The latches are implemented to prevent from loss of compare matches which may occur when loading of the compare values is not correlated with the timer count The compare latches are automatically loaded from the compare registers at every timer overflow Capture This feature permits saving of the actual timer counter contents into a selected register upon an external event or a software write operation Two modes are provided to latch the current 16 bit value of timer 2 registers into a dedicated capture register Mode 0 Capture is performed in response to a transition at the corresponding port pins to CC3 Mode 1 Write operation into the low order byte of the dedicated capture register causes the timer 2 contents to be latched into this register Reload of Timer 2 A 16 bit reload can be performed with the 16 bit CRC register which is a concatenation of the 8 bit registers CRCL and CRCH There are two modes from which to select Mode 0 Relo
291. uitry of Ports 1 3 4 5 and 6 0 through 6 2 Ports 6 3 through 6 7 have no alternate functions as discribed above Therefore the port circuitry can do without the switching capability between alternate function and normal I O operation This more simple circuitry is shown as basic port structure in figures 7 1 and 7 2 Semiconductor Group 46 SIEMENS On Chip Peripheral Components Table 7 1 Alternate Functions of Port Pins Port Pin Alternate Function P1 0 INT3 CCO Ext interrupt 3 capture 0 compare 0 P1 1 INT4 CC1 Ext interrupt 4 capture 1 compare 1 P1 2 INT5 CC2 Ext interrupt 5 capture 2 compare 2 P1 3 INT6 CC3 Ext interrupt 6 capture 3 compare 3 P1 4 INT2 CC4 Ext interrupt 2 capture 4 compare 4 1 5 2 Timer 2 ext reload trigger input P1 6 CLKOUT System clock output 1 7 T2 Timer 2 external count input P3 0 RXDO Serial input channel 0 P3 1 TXDO Serial output channel 0 P3 2 INTO Ext interrupt 0 P3 3 INTT Ext interrupt 1 P3 4 TO Timer 0 external count input P3 5 T1 Timer 1 external count input P3 6 WR External data memory write strobe P3 7 RD External data memory read strobe P4 0 CMO Compare 0 of compare unit 7 4 1 CM1 Compare 1 of compare unit 7 P4 2 CM2 Compare 2 of compare unit 7 P4 3 CM3 Compare 3 of compare unit 7 P4 4 CM4 Compare 4 of compare unit 7 P4 5 CM5 Compare 5 of compare unit 7 P4 6 CM6 Compare 6 of compare unit 7 P4 7 CM7 Comp
292. ure 7 25 shows a block diagram of the A D converter There are four user accessible special function registers ADCONO ADCON1 A D converter control registers ADDAT A D converter data register and DAPR D A converter program register for the programmable reference voltages The analog input channels port 7 and port 8 can also be used for digital input refer also to section 7 1 Parallel 7 4 1 Function and Control 7 4 1 1 Initialization and Input Channel Selection Special function register ADCONO which is illustrated in figure 7 26 is used to set the operating modes to check the status and to select one of eight analog input channels Special function register ADCON1 figure 7 27 controls the selection of all twelve input channels Register ADCONO contains two mode bits Bit ADM is used to choose the single or continuous conversion mode In single conversion mode only one conversion is performed after starting while in continuous conversion mode after the first start a new conversion is automatically started on completion of the previous one Semiconductor Group 83 SIEMENS On Chip Peripheral Components Write to DAPR Shaded areas are not used in ADC functions P 8 00 Internal Bus s 7 DBy ADCOM DC ADCONO 08 q Port 7 Port 8 A D Co
293. ure 7 45 Concurrent Compare Function of Register 4 Pattern Table 8 Bit Schedule Table 16 Bit Compare Register CC4H CC4L Timer Count 4000 1000 20004 30004 5 7 5 6 5 5 5 4 ALII u 5 2 Port Pattern P5 1 P5 0 MCTO1853 Figure 7 46 Example for a Concurrent Compare at Port 5 Semiconductor Group 113 SIEMENS On Chip Peripheral Components Figure 7 47 Compare Capture Enable Register CC4EN 0C9y COCON2COCON 1 COCONOCOCOENCOCAH4 COCAL4 COMO CCAEN Selects compare or capture function number of concurrent compares and compare mode of register CC4 Bit Function COCAH4 0 0 1 1 COCAL4 0 1 0 1 Compare capture mode for CC4 register Compare capture disabled Capture on falling rising edge at pin P1 0 INT2 CC4 Compare enabled Capture on write operation into register CC4L COMO Compare mode bit When set compare mode 1 is selected for CC4 COMO 0 selects compare mode 0 COCOEN Enables the compare mode 1 and the concurrent compare output for CC4 Setting of this bit automatically sets bit COMO COCON2 COCON1 COCONO Selects additional concurrent compare outputs at port 5 See table below COCON2 COCON1 COCONO Function One additional output of CC4 at P5 0 Additional outputs of CC4 at P5 0 to P5 1 Add
294. ut on P1 the program will loop at this point until the P1 data changes to 34 Semiconductor Group 188 SIEMENS CJNE Operation Encoding Bytes Cycles CJNE Operation Encoding Bytes Cycles CJNE Operation Encoding Bytes Cycles A direct rel lt 3 if lt gt direct then PC lt PC relative offset if A lt direct then 1 else C 0 Instruction Set 1011 0101 rel address direct address A data rel lt PC 3 lt gt then PC relative offset if lt data then C 1 else C 0 1011 0100 immediate data rel address RN data rel lt 3 if lt gt data then PC relative offset if Rn lt data then C lt 1 else C 0 1011 1rrr immediate data rel address Semiconductor Group 189 SIEMENS Instruction Set CJNE Ri data rel Operation lt PC 3 rel address if Ri lt gt data then PC PC relative offset if Ri lt data then C lt 1 else C 0 Encoding 10110111 immediate data Bytes Cycles 2 Semiconductor Group 190 SIEMENS Instruction Set CLR A Function Clear accumulator Description The accumulator
295. ve the compere value for the second timer period to the compare register Enable the compare function CMEN x 1 Set up the prescaler for the compare timer Set specific compare output to low level CLR P4 x Start the compare timer with a desired value write to CTREL Second Configuration Registers Assigned to Timer 2 Comment This is also the default value after reset In compare mode 1 latch is loaded directly after a write to CMLx Thus the value slips directly into the compare latch Now select the rigth compare mode The register latch is loaded This value is used after the first timer overflow The compare output is switched to low level Compare function is initialized The output will oscillate Any CMx register switched to timer 2 as a time base operates in compare mode 1 In this case CMx registers behave like any other compare register connected to timer 2 e g the CRC or CCx registers Please refer to the above description of compare mode 1 for further details Since there are no dedicated interrupts for the CMx compare outputs again a buffered compare register structure is used to determine an exact 16 bit wide loading of the compare value the compare value is transferred to the actual compare latches at a write to CMLx instruction low byte of CMx Thus the CMx register is to be written in a fixed order too high byte first low byte second If the high byte may remain unchanged it is suff
296. watchdog timer refresh is performed Semiconductor Group 144 SIEMENS On Chip Peripheral Components OWD Reset Request WDT Reset Request SET SET wsos n Internal Reset Synchronization CLEAR External HW Reset Request RESET o Internal Bus lt MCS01857 Figure 7 62 Watchdog Status Flags and Reset Requests Figure 7 63 Special Function Register IPO 0A9 OWDS WDTS 1P0 2 IPO These bits are not used in controlling the fail safe mechanisms Bit Function OWDS Oscillator watchdog timer status flag Set by hardware when an oscillator watchdog reset occured Can be cleared or set by software WDTS Watchdog timer status flag Set by hardware when a watchdog timer reset occured Can be cleared or set by software Semiconductor Group 145 SIEMENS On Chip Peripheral Components 7 8 2 Oscillator Watchdog What happens a microcontroller system it the controller s on chip oscillator stops working This failure e g caused by a broken crystal an open connection to the crystal or a long term disturbance normally leaves the system in a random undetermined state The SAB 80C517 provides a fail safe reaction upon an oscillator failure If the on chip oscillator frequency falls below a certain limit due to a hardware defect the oscillator watchdog initiates an internal reset This reset state i
297. wing example of a PWM generation demonstrates the use of some important features of the SAB 80C517 s CCU flexibly programmable compare timer with 16 bit reload and 8 selectable input clocks fosc 2 to fosc 256 TOC oading mechanism to reduce interrupt load of the CPU The above features allow PWM generation for digital to analog conversion with extremely low external hardware costs simple passive RC filter or any other integrating device output frequencies from less than 1 Hz 16 bit reload timer input clock of 256 to 3 MHz 2 bit reload timer input clock of 2 The following paragraphs do not contain a basic description of PWM generation with microcontrollers but rather should give an idea of how to use the CCU of the SAB 80C517 in this kind of applications Please refer to other literature for a general description of the pulse width modulation The example in the following uses typical parameters a PWM frequency above the audible range 23 4 kHz with 8 bit resolution The PWM may for instance be used to generate a sine wave via a low cost RC filter To simplify matters just one PWM channel is used in this example The SAB 80C517 however can drive up to eight channels with the fast compare timer Semiconductor Group 258 SIEMENS Application Examples Explanation of a Few Terms Pulse width modulation In our case the PWM is used to synthesize a sine wave This means that a digita
298. y DA is returned to A CY is set if the BCD result is greater than 99 otherwise it is cleared Semiconductor Group 172 SIEMENS Instruction Set Subtraction SUBB subtract with borrow subtracts the second source operand from the the first operand the accumulator subtracts one 1 if CY is set and returns the result to A DEC decrement subtracts one 1 from the source operand and returns the result to the operand Multiplication MUL performs an unsigned multiplication of the A register returning a double byte result A receives the low order byte B receives the high order byte OV is cleared if the top half of the result is zero and is set if it is not zero CY is cleared AC is unaffected Division DIV performs an unsigned division of the A register by the B register it returns the integer quotient to the A register and returns the fractional remainder to the B register Division by zero leaves indeterminate data in registers A and B and sets OV otherwise OV is cleared CY is cleared AC remains unaffected Flags Unless otherwise stated in the previous descriptions the flags of PSW are affected as follows CY is set if the operation causes a carry to or a borrow from the resulting high order bit otherwise CY is cleared AC is set if the operation results in a carry from the low order four bits of the result during addition or a borrow from the high order bits to the low order bits during
299. y are not equal CY is set if the first operand is less than the second operand otherwise it is cleared Comparisons can be made between A and directly addressable bytes in internal data memory or an immediate value and either A a register in the selected register bank or a register indirectly addressable byte of the internal RAM DJNZ decrements the source operand and returns the result to the operand A jump is performed if the result is not zero The source operand of the DJNZ instruction may be any directly addressable byte in the internal data memory Either direct or register addressing may be used to address the source operand Interrupt Returns RETI transfers control as RET does but additionally enables interrupts of the current priority level Semiconductor Group 175 SIEMENS Instruction Set 9 3 Instruction Definitions All 111 instructions of the SAB 80C517 can essentially be condensed to 54 basic operations in the following alphabetically ordered according to the operation mnemonic section Instruction Flag Instruction Flag OV AC CY OV AC ADD X X X SETBC 1 ADDC X X X CLR C 0 SUBB X X X CPL C X MUL 0 X ANL C bit X DIV 0 X ANL C bit X DA X ORL C bit X RRC X ORL C bit X RLC X MOV C pit X CJNE X A brief example of how the instruction might be used is given as well as its effect on the PSW flags The number of bytes and machine cycles required
300. ycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 8 11 C1 lt C2 gt a 4 C4 gt 5 S5P2 SSS OS eS cn Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCTO1859 Figure 8 11 Interrupt Response Timing Diagram Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 8 11 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated LCALL pus
301. yte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port 0 pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes OFF to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 27 SIEMENS External Bus Interface Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustrated in figure 5 2 a and b Data memory In a write cycle the data by
302. ytes Cycles 2 Semiconductor Group 230 SIEMENS Instruction Set ORL C lt src bit gt Function Logical OR for bit variables Description Set the carry flag if the Boolean value is a logic 1 leave the carry in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Example Set the carry flag if and only if P1 0 1 ACC 7 1 or OV MOV C P1 0 Load carry with input pin P1 0 ORL C ACC 7 OR carry with the accumulator bit 7 ORL C OV OR carry with the inverse of OV ORL C bit Operation ORL C C v bit Encoding 0111 0010 bit address Bytes 2 Cycles 2 ORL C bit Operation ORL v bit Encoding 1010 0000 bit address Bytes 2 Cycles 2 Semiconductor Group 231 SIEMENS Instruction Set POP direct Function Pop from stack Description contents of the internal RAM location addressed by the stack pointer is read and the stack pointer is decremented by one The value read is the transfer to the directly addressed byte indicated No flags are affected Example The stack pointer originally contains the value 324 and internal RAM locations 304 through 324 contain the values 204 23 and 014 respe

Infineon 80C517/80C537 User's Manual

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