USER'S MANUAL - Oho
Contents
1. scuk Z4x595 5 74x595 74x595 lt input connector 6 or 9 pin stacking connector 9 pin 4 OHO DY1 circuit description One basic display unit one digit consists of a 7 segment led display with a common anode connected to a 74x595 like shift register with output catch registers The current limiting series resistor arrays are not shown in the overview but in schematics of course An OHO DY1 module consists of three digits interconnected as shown in the block diagram The shift register parts of the 74x595s are all clocked by SCLK with input data SER on the rising edge of SCLK SCLK and SER as well as RCLK are routed from the 6 or 9 pin input connector The 74x595s are chained from right to left forming a 24 bit shift register The output of the first 74x595 on the right side is fed to the middle 74x595 which feeds its output to the left 74x595 which offers its output QH2 on the 9 pin stacking connector on pin6 Since the 7 segment displays uses a common anode a 0 on the input data is needed to light up a segment input data on SER has to be inverted The module SCLK clock and the SER input data can be seen as the module SPI clock with its data input clocked on the rising edge A microcontroller SPI peripheral can be used to drive these signals However also software bit banging is reasonable SCLK can be as high as about 10 MHz on 3 3V modules or about 15 MHz on 5V modules thus no softwa2. d 4oi2auuoc2 isa utd g pHo ee eee e ee NU gxT INOJ 4012e9UuO02 Utd 9 e queduo2 ywertbtg eoeeee amp OXO dg id ub s Diop 9 1ueubes Taxg Jj ueubes B8XB J ueubes pxo g aueubes goxo 2 1ueubes zara g iueubes BTxa u iueubes Jan ISAT GS WaT ujluS eieg iueubes 3d 40 N33H9 NG NOILdO AY IdSId avs earvr9sdl QSTTSSOL Hd HU 20 30 30 ao Jo ao doo HH xHD UNI 8g 195 HD 90 Md886819HU rz OHO DY1 USER S MANUAL V1 2 Page 17 of 22 T T n99u Ltr DC GL NEO 428qunN aiuaeunoo g Page 18 of 22 enIq TAG OHO 31lIL NGHIYO L cCop El E ER 4070UZTOPUEG oP MINOALMA 13 0HO Weis HD OND 19S HD avtasc S1 se npou G1d9 uim pesn j peiaous Sg isnw zgdp pue Tdf zen ENDI 40328UU005 buppeis Tenan d uper u opi E M id855129HU9 rZ ca 19 wN xHD UNS r3ezeco93ud nM u10s HD K Ta 40128uUC2 s utd g OHD e CNDI TINOJ 4012eUuo2 utd 9 e qneduoo iue rbrg c baxg dg iuewbes zx 9 iueubes TOXQ jaueubes g8xp 3 1ueubes x Q iueubes ggxg 29 iueubes zox 8 aueubes BTXB Uu aueubes Jan IIA 33n M id865129HUrvz gvTOS8c S11 1SAtj GSW 497 ytus Sen iueubes Abita NS NOILdO AY IdSIO 9 S UAS 419 OHO DY1 USER S MANUAL V1 2 9 9 5 p des gt c o E pem ES de o
3. output continuous 1 indicates display frame end dy frameend C output single clock 1 indicates display frame end dy pwm input iech a 1111 sets max intensity 0000 lowest only if dy_update is always set to 1 dy_counter output 16 32 main free running binary counter as state machine substitution for display control only the first 16 lower significant bits are used all 32 bits can be used externally as divided clock outputs dy_sclk output display module SCLK as described above dy_ser output display module SER as described above dy rcik output display module RCLK as described above OHO DY1 USER S MANUAL V1 2 Page 13 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 2 OHO DY1 core usage The core can be used quite easily to display hex numbers only the signals dy clock dy rst n and dy data must be provided see the core examples Since the display uses a non multiplexed approach users may want to update the display after an input data dy data change only To do so a single clock pulse trigger on dy update starts the display frame update from the actual dy data array Frame end is indicated by the core via dy frameend and frameend c Please note that the input data dy data must be stable up to the end of the display frame Even easier is to update the di
4. OHO DY1 core interface signals Signal name Direction Length Function dy_clock input 1 core clock 10 125MHz recommended dy rst n input 1 core reset negative active dy data input array 15x9 user defined array data type 15 digits x std logic vector 8 downto 0 dy data 0 is first right digit of first module dy data 1 is second middle digit of first module dy data 2 is third left digit of first module dy data 3 is first digit of second module dy data 4 is second digit of second module dy data 5 is third digit of second module dy data 6 is first digit of third module dy data 7 is second digit of third module dy data 8 is third digit of third module dy data 9 is first digit of fourth module dy data 10 dy data 11 12 13 is second digit of fourth module is third digit of fourth module dy data 12 is first digit of fifth module dy data 13 is second digit of fifth module dy data 14 is third digit of fifth module one 9bit word is defined in the next table 0 1 2 d 4 5 6 7 8 9 1 1 1 1 dy_update input display update 1 updates display continuously and allows PWM brightness control a single clock pulse 1 or longer pulses updates the display only for one or DupVal see ohopack vhd times max brightness only dy frame output pulse nearly as long as display frame indicates frame start dy frameend
5. QO SS N N LO SR QOQ o 5 A o o 2 D o 2 cc 9 p O L O 8 Schematics 5V blue Version OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 9 Module Layout 3 3V Version 9 pin p must be soldered on bottom side vis SPU aan ix z 104 100 8k2 aa 194 Top view OHO DY1 USER S MANUAL V1 2 Page 19 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 10 Module Layout 5V non blue Version 8 pin jack must be soldered on bottom side Cr i OHO DY1 USER S MANUAL V1 2 Page 20 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 11 Module Layout 5V blue Version 9 pin p must be sgldered on bottom side SP RAZ RAL da4 RAS da2 Ra LH gt lt Ii M E Ci a0n p svo o avV as 100 100 oC aa 190 G 144 Top view OHO_DY1 USER S MANUAL V1 2 Page 21 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 12 USER S MANUAL Revisions Version Date d m y Comments V1 0 20 07 2009 First Release V1 1 21 07 2009 Small corrections V1 2 16 08 2009 Small corrections new module variants OHO DY1 USER S MANUAL V1 2 Page 22 of 22
6. OHO_DY1 USER S MANUAL V 1 2 OHO Elektronik www oho elektronik de Author M Randelzhofer OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO Elektronik Michael Randelzhofer Rudolf Diesel Str 8 85221 Dachau Germany WEB www oho elektronik de EMAIL info oho elektronik de Phone 49 8131 339230 FAX 49 8131 339294 2009 OHO Elektronik Michael Randelzhofer All rights reserved Disclaimer Under no circumstances OHO Elektronik Michael Randelzhofer is liable for consequential costs losses damages lost profits Any schematics pcb or program parts are under the copyright of OHO Elektronik Michael Randelzhofer and can only be reproduced by permission of this company The contents of this USER S MANUAL are subject to change without notice However the main changes are listed in the revision table at the end of this document Products of OHO Elektronik Michael Randelzhofer are not designed for use in life support systems where malfunction of these products could result in personal injury The products of OHO Elektronik Michael Randelzhofer are intended for use in a laboratory test environment or for OEM s only They can generate radio frequency energy depending on the downloaded design and application which can disturb local radio or TV equipment and so they have not been tested to be CE compliant If you encounter any technical problems or mistakes in thi
7. and blue only on 5V modules available brightness controllable PWM gt VHDL core available gt OHO DYI modules can be also used on most microcontrollers reverse voltage protection OHO DY1 USER S MANUAL V1 2 Page 5 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO DY1 USER S MANUAL V1 2 Page 6 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 2 OHO DY1 Board Pictures AT cL Ke Fel TOL tel tele Lo The picture show the three possible connector configurations of the OHO_DY1 The module in the middle is soldered with a 6 pin connector which fits into the Xilinx Spartan3E and Spartan3A 3AN 3ADSP Starterkits On the right side a 9 pin jack is soldered on the bottom side of the display module This one can be plugged into the test connector of an OHO CPLD or FPGA module or stacked into the 9 pin connector under the led display modules of any already plugged OHO_DY1 module A maximum of 2 stacked modules is recommended for debugging purposes because of mechanical issues however 5 modules max 15 digits are supported by the VHDL display core A version without connector shown on the left side in the picture above is available for customers who want to use their own hardware On the left side an unsoldered version can be delivered where the customer can decide which connector he or she wants to use Please n
8. onik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 5 Brief OHO _DY1 core description The core sends display data to the OHO DY1 modules in display frames containing data for 16 display digits however only 15 digits can be user defined One display frame starts with 8x16 128 SCLK cycles with its associated display data on SER and finishes with a pulse containing a rising and falling edge on RCLK The main timing generator of the OHO_DY1 core is a simple free running 32 bit binary up counter clocked by the system clock e g 50MHz and is named displaycounter dy counter The counter is defined as a std logic vector as displaycounter 31 downto 0 Only the lower 16 bits are used by the core to buid a display frame the upper 16 bits can be used by the user or is optimized away by the post processing tools A display frame starts when all 16 lower displaycounter bits are zero A display frame only stops if dy update is reset to low and if the internal display update counter decremented to zero SCLK is derived from displaycounter 8 system clock divided by 256 about 195kHz 50MHz In other words one SCLK low time takes 256 system clocks which corresponds to more than 5us Setup and one SCLK high time also takes 256 system clocks which corresponds to more than bus Hold time 50MHz for the interconnected 74x595 Display data on SER is generated by the function SerialHexDecode in 8 SCLK packets one packe
9. ote There are modules for 3 3V power supply normally used in Xilinx Starter Kits and 5V modules used for the OHO FPGA and CPLD modules OHO DY1 USER S MANUAL V1 2 Page 7 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 3 One OHO DY 1 module on a Xilinx Spartan 3ADSP Starter Kit au c gt ay 2 4 Two OHO_DY1 modules on a Xilinx Spartan 3A Starter Kit I KR J OHO_DY1 USER S MANUAL V1 2 Page 8 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 5 Four OHO DY 1 modules on a Xilinx Spartan 3E Starter Kit 283558 e d SPA 38985C 2 6 Five OHO DY1 modules on an OHO GOP XC3S200 module 2 7 Five OHO DY1 modules on an OHO GODIL48 module OHO DY1 USER S MANUAL V1 2 Page 9 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO DY1 USER S MANUAL V1 2 Page 10 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 OHO DY1 Block Diagram we oe oe ou ee hk hh AAA k hh hh AAA A hh k A e SER lt SCLK
10. re delays should be necessary for the display update function loop See datasheets of 74HC595 for 3 3V and 74AHCT595 for 5V modules but consider that the clock and data signals are not terminated on the modules itself so frequencies have to be derated Please note that these frequecies must be derated again for stacked modules OHO DY1 USER S MANUAL V1 2 Page 11 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de The common catch register clock of the 74x595s RCLK is connected to the output enables of all 74x595s thus display update is coupled with display enable This allows for brightness control by pulse width modulation PWM with a reduced pin count The display is updated by a rising edge on RCLK The display is enabled by a logical 0 and disabled by a logical 1 on RCLK The signals RCLK SCLK and QH2 are connected to the 9 pin stacking connector so with adding another module the block diagram is effectively extended to the left with n x 3 digits where n is the number of stacked modules The 3 3V version of the OHO_DY1 module uses a 74HC595 device with appropriate series resistors for the LED 7 segment displays It can be used for Xilinx Starter Kits with a 6 pin Digilent compatible connector or with OHO CPLD and FPGA modules with a 9 pin connector running from 3 3V 3 5V Any microcontroller or other device with 3 3V levels can also be used the connector used is up to the u
11. s 3 3V Version 225 16 7 Schematics 5V non blue Version 17 8 Schematics 5V blue Version 18 9 Module Layout 3 3V Ye AR ana Ba 19 10 Module Layout 5V non blue Version am maa Manga 20 11 Module Layout 5V blue DEER 21 12 USER S MANUAL Revislons mna 22 OHO DY1 USER S MANUAL V1 2 Page 3 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO DY1 USER S MANUAL V1 2 Page 4 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 Introduction The OHO_DY1 module is a small 28mm x 23mm 0 9 x 0 9 7 segment display unit for displaying 3 digits of hex numbers 12 bits or arbitrary segment combinations including their associated decimal points It is primarily intended for debugging or educational use The modules can be stacked to extend the number of digits A VHDL core is available to directly display hex numbers on up to 5 stacked OHO DY1 modules Alternatively the modules can be connected to any microcontroller or DSP using only 3 GPIOs 2 1 OHO DY1 Features small 3 digit 7 segment display module upto 5 stackable modules on the same connector gt 9 pin OHO or 6 pin Digilent compatible interface connector 3 l O s needed gt 9 pin connector can be reduced to 7 pins for use with OHO CPLD modules simple SPI like interface gt 3 3V and 5V modules available red green
12. s document please contact mrandelzhofer oho elektronik de serious hints are very appreciated Trademarks All brand names or product names mentioned are trademarks or registered trademarks of their respective holders PAL and GAL are registered trademarks of Lattice Semiconductor Corp OHO DY1 USER S MANUAL V1 2 Page 2 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 1 Table of contents k Table of OOE S unn Sau akha ususln sess 3 2 lnttod ctlOl EE 5 2 1 OHO ee 5 2 2 OHO DYI1 Board Pictures oooooooooWoooooooooom W nenen 7 2 3 One OHO DYI module on a Xilinx Spartan 3ADSP Starter ku 8 2 4 Two OHO DYI modules on a Xilinx Spartan 3A Starter Kit 8 2 5 Four OHO DYI modules on a Xilinx Spartan 3E Starter Kit 9 2 6 Five OHO DYI modules on an OHO GOP XC3S200 module 9 2 7 Five OHO DYI modules on an OHO GODILAS module eee eene 9 m OHO DYIBIOSE RE 11 4 OHO DY1 cirgiit esit 11 De OHO DI VI EE 13 Dele OHO DY 1 core iilerlace E 13 5 2 OHO RER 14 5 33 OHO DY 1 core input signal dy_data format n a 14 SAs MAN ee ea aa Na RE 14 55 Brief OHO DY L core d SceriptiOB aa oa nana 15 6 Schematic
13. ser s choice The module must be powered from 3 3V The 5V version of the OHO DY1 module uses a 74AHCT595 device with appropriate series resistors for the LED 7 segment displays The 74AHCT595 yet powered from DV accepts 3 3V and 5V logic levels It can be used for OHO CPLD and FPGA modules with a 9 pin connector running from 5V Any microcontroller or other device with 3 3V or 5V levels can also be used the connector used is up to the user s choice The module must be powered from 5V Table of orderable configurations options Label code Suitable for Comment 5ggg0 OHO 5V FPGA and CPLD A 5V display module with 3 green led display digits 5ggg1 modules Schottky diode PMEG2020EJ assembled 50001 A 5V display module with 3 orange led display digits 5bbb0 A 5V display module with 3 blue led display digits rrr0 Xilinx Starterkits A 3 3V display module with 3 red led display digits arrr1 Schottky diode BAT54HTG1 assembled 3ggg1 A 3 3V display module with 3 green led display digits The label code consists of 3 parts the first digit is 3 or 5 for the supply voltage 3 3V or 5V the next 3 digits show a colour code for every digit from left to right the last digit is an internal manufacturing version code for reference OHO DY1 USER S MANUAL V1 2 Page 12 of 22 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 OHO DY1 Vhdl core 5 1
14. splay continuously by setting dy update to 1 which also allows for PWM brightness control 5 3 OHO DYI core input signal dy data format One dy data word is defined as a VHDL std logic vector 8 downto 0 so its a 9 bit vector The vector can contain an 8 bit raw segment word with all the seven segments of one display digit and an additional decimal point segment Alternatively the vector can contain 5 bits consisting of one 4 bit hex number which will be decoded by the core plus the decimal point dy data vector part polarity Function std logic vector 8 0 raw display format including decimal point std logic vector 7 downto 0 inverted data display segments defined in ohopack vhd std logic vector 8 4 hex display format std logic vector 7 1 is on 0 is off decimal point std logic vector 6 downto 4 not used std logic vector 3 downto 0 hex code X x display decoded hex number 5 4 OHO DY1 core examples There are some example zip files for the following hardware which demonstrates easily how to use the OHO_DY1 display core Xilinx Spartan SE Starter Kit Xilinx Spartan 3A 3AN Starter Kit Xilinx Spartan 3A DSP S3D1800A Starter Platform OHO GOP XC3S200 module OHO GODIL48 module Y V Vv Vv v Please note Some demos need a jumper from pin6 to pin7 at the stacking connector of the OHO_DY1 module OHO DY1 USER S MANUAL V1 2 Page 14 of 22 OHO Elektr
15. t represents one display digit 16 packets are sent for 16 digits in one whole display frame SerialHexDecode uses 2 input parameters one is the display data to serialize the signal actualdigit The other parameter is the timing source for the serialisation the 3 bit signal displaycounter 1 1 downto 9 A 16 to 1 multiplexer sources actualdigit from all 15 input values of the display core input signal digits The multiplexer select input is driven by displaycounter 15 downto 12 When the least significant 16 bits of the displaycounter rolls over to X 0000 thus incrementing the most significant 16 bits of the counter RCLK is set to 1 to generate a rising edge which transfers the shift register content to the 74x595 output latch to display the transferred display frame In a single display frame update RCLK needs to be reset on the next rising SCLK to switch on the LED displays During continuous display update in the next display frame RCLK needs to be reset again to enable a further display update That RCLK reset is also derived from displaycounter 15 downto 12 dependent on dy pwm which forms a pulse width modulated output enable also connected to RCLK for display brightness OHO DY1 USER S MANUAL V1 2 Page 15 of 22 9 9 5 lt T des E gt c o E pem o 2 de o QO Kam y N LO SC ea o Fe 15 A o o HD Q o E tc o e O L O 6 Schema
16. tics 3 3V Version T T 39e9us EG EG TC 6007 80 9T op SGUNN iueunooq do TA OHO JALIL B AIS TESS91G F1TOPNY AINOALAMT 13 0HO NGHIYO 12248 ASJOUZIOPUEH TSLUSIN Se npou OO uit p sn It pai40us eq isnu Zdf pue Tdf BXT END 40128uu03 buneis m cc Ir ugat uear L3020293Hd o 19 oer T1H9TSV8 iro K T GNU OXT INOQ 40128UU02 utd 9 lq L zp d ue Deg zxQ 9 yusub s Texg J iueubes 08XQ0 3 1ueubes 0x0 GQ Wawbes goxo 23 1ueubes zoxo g 1ueubesg Dap H 1ueubegS Jan JJA 1SAT4 GSW MSI ius eeg wewbes 3H 40 N33H9 neve NOILdO AUJdSIG 8 i aos AIDS 9MUTOSZSI OST LISOL STLTISOL 9MYT88ZSLA SMYTA8ZS11 stTgsol HOGG Ok HD OND g 19S HD AIS 2u g us Ho gon MdS6SOHFe HD OND 19S HD HOGG Ok OHO DY1 USER S MANUAL V1 2 Page 16 of 22 o 9 fe o 5 lt Q o des 9 gt c E gt o dc o Q KS N A LO e QO co 5 2 E o E Q o 2 tc E o x lt p O i O Ion 5V non blue Versi ICS 7 Schemat L L 2894S BCBG TC 6007 80 9T 91 48qunN Yu sun3oq TAG OHO 311Il g 4IS Tasetq 1opny MINOWLMAITA 0HO fiuHOUd 12258 4 jouz1 puet JOLUSIN Se npou OI ULIM pesn jr pai4ous eq isnu zdgr pue Jaf 6x1 END2 40128uU05 Hur ers E Meer ogy TO91HPS198 co 13 ITA 4 T1H9T7SU08 IgA 4 K
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