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User Manual - DENX Computer Systems

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1. ADAPTER PEEDI Blackfin 14 Blackfin TARGET Ji 1 VFEE Je 2 1 3 at TK EMJau 2 LA 4 FSTbidr 3 5 at Ta 4 ICI dol 5 7 at TNS TNSin 6 8 7 a A aod ERR HEADER 2x7 NC 11 TO TFSTIn 10 12 11 13 Tin 12 NC 4 13 15 EAK Oat 14 1 4 17 ac 8 Q4 19 at TET TE 20 bidr PST r E A i IV Y v o nd populated 7 Title PEEDI BF14 Modue ADAPTER Company RONETIX bx Rev 1 0 Amo ILKOILIEV 6 10 2007 317 ere a m ADAPTER PEEDI 4x BFIN14 http download ronetix info peedi doc schematics peedi 4xbfin14 pdf ADAPTER PEEDI 4x Blackfin 14 A 2 ABC Di Z 1 Mac lt 2 K KI EA PASC K gr EIN eg amp KI 8 C D x L gt D4 D5 D6 Ds Pu DV 5 v v7 v v OLIN LIL421N IETLZZPIN LIL421N PEEDI Packi ARET N ET Blackfin TARCET Blackfin TARCET Ji 1 Ri HEADER2x7 HEALER2x7 HEADER2x7 HEACER2x7 An Je I P 5 2 1K 1 1 1 1 3 at OK Ny 2 nN 2 NO 2 NC 2 4 NG 3 No 3 n 3 3 E MER Mdat 5 VEER2 5 T E T 5 To LVR VFEFA 7 at TNS TN6in 6 TNS 6 m6 6 E 6 8 7 Fj 7 7 9 aM TOKin 8 TOK 8 TK T s m Ts 10 9 9 a 8 11 TO TFST 10 mE 10 El rq
2. For OneNAND FLASH devices these are OneNAND PEEDI User s manual 37 www ronetix at Using PEEDI CHIP ADDR BASE BAD BLOCKS ERASE BAD BLOCKS OOB INFO FILE AUTO ERASE For MPC5500 devices these are MPC5500 CHIP BASE ADDR ALLOW SHADOW MODIFY FILE AUTO ERASE For MCF5200 devices these are MCF5200 CHIP BASE ADDR IPS BASE CPU CLOCK FILE AUTO ERASE CHIP Description FLASH chip type To find if your flash is supported and see its exact name use flash find If your FLASH chip is not supported by the current FLASH database please contact us and we will provide you with the latest database This parameter may be present multiple times in a single FLASH section each time specifying different FLASH chip This way if the CHECK ID parameter is YES PEEDI will read the onboard FLASH ID and will find the right chip among the all chips enumerated using the CHIP parameter Argument Flash chip present in FLASH DB CHECK ID Description When specified YES if single FLASH chip is described by the CHIP parameter PEEDI will check if the onboard FLASH chip reports the same as selected by the CHIP parameter If multiple FLASH chips are enumerated using more than one CHIP parameter PEEDI will automatically consider the chip which ID matches the reported by the onboard FL
3. 13 1 2 3 High productivity with the Multi Core feature ccccccccconncocconcccccnnnnccconononnnnncnonnnononononanaos 13 2 INSTALLATION uec 14 2 1 Hardware installation alias 14 231 1 Connection ISU CU ONS osien s ee tert wan E a ree estt che Lo oui 15 2 2 SofttWare Ifistalldlloh id didas 16 3 USING REED anna dan 17 3 1 PEED te acuario dd 17 a o AAA A s 18 2 2 b TIedBoor ON QUAN OM et a dt e 18 3 2 2 Firmware Update procedure mts alt dd dd 19 3 2 2 1 Update vid AS e o eae 19 3222 Update via BIUIGITIO trat io oia bob aC NOE oda Eo petia toon cin eee oue 19 3 2 3 RedBoot commands used with PEEDI eese 20 TOMA NG Me Ee EIC DC RR TOP TE RAM 20 LE CS DNE C c c 20 o MAR DC FM PAM DNE PE 20 3 3 erento c 21 3 9 T1 NetWOTK configuration eiii oa dete seen ete dae at A Medrano ia 21 3 9 2 TACNA 21 wi emenMelericcA Pee 21 Secon DEBUGGER PROTOCOL iaa NOSE 21 sre tiM xd 22 Section PLATFORM ARM 22 Secon PLA TPORM Euh a S 26 Section PLATFORM_CortexM3 Section PLATFORM CortexM3 SWD 26 Section PEATEORM J GOfTexAB cepta et tectae e pbee ois bismuth dale aestate iude deus 26 Section PLATFORM XSCALE oia 27 section PLATFORM MECO sirs E a E A 27 Section PLATFORM MPC8300 siii is 28 Section PLATFORM MPC5200 et due ia 29 Sector PLATFORM MPG8500 ad 29 Section PLATFORM APP C400 cali
4. 56 3 0 MUNIDIC core SUP DOM ut M 58 3 7 Script execution using the front panel interface scceeeeeessssssseeseeeeeeeeseeseneensneees 59 3 9 senal inteiace cional ana a a a a A AA a 60 3 9 ARM DCC MENACE E a ud derunt d a a a aaa 60 3 10 Working WHA IASIONTIAD a a a aaa 61 3 11 Working with other debuggerS sssssssnnnunnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn 63 3 11 1 ARM Developer Suite ADS v1 2 AXD debugger cccccccccccccccoooccccconncnononononacoconnnnnnnnnos 63 3 11 2 ARM RealView Developer Suite RVDS v2 2 RealView debugger 66 9 13 9 Green Hills MULTIVS 6 Tor ARM uii ient enter ia 70 3 11 4 IAR Embedded Workbench for ARM v4 30 oocccccccccnccccoccnncocononnconononncononcnnconancnncnnanens 72 3 12 Debugging Linux Kernel a a E 74 3 13 Target OS tasks awareness and debugging uClinux applications 74 3 14 Working with CLI Command Line Interface cccccnnnnncciccconccnnnccnccoccnnnnnncnnonananonnnnonanannns 76 3 14 Fe pA CONVENIO Mi TH NETS 76 3 14 20 eoe TED m T 78 jon E 78 TIAN SU CMs bates O A 78 ol A 78 IS e RICE 78 elo E O OR 79 COCK PEACE ERE EEE O 79 cj
5. ADAPTER PEEDI MIPS14 http download ronetix info peedi doc schematics peedi mips14 pdf PEEDI MPS TARGET J1 1 VFF 2 2 TRSTin 1 3 at TK 2 4 4 Tin 3 5 at TT 4 d4 4 i8 Oat 5 7 at NS 6 8 TBn v HEADER 2X7 2 54mm 9 razo 8 49 8 10 TKin 9 11 TO 10 49 10 pe 4 FSrBdr 11 13 NS 12 14 ONTin 13 15 Vref at 14 an e 17 NC e 19 out TRST A 20 bidr FST o not populated Title PEEDI MPS14 Module ADAPTER Size Company FCNETIX m FPev 1 0 Author ILKOILIEV 1217 2008 15 58 Sheet 1 of 1 PEEDI User s manual 115 www ronetix at ADAPTER PEEDI AVR32 http download ronetix info peedi doc schematics peedi avr32 pdf Specifications PEEDI un ver AVRG2 TARGET 2 3 at TK i 5 at TO Tin 1l 16 2 Iz 1 at TVS THOat 3 18 waat 4 9 Ny TNSin 5 10 Tn 6 HEADER 2x5 11 in TO NC 7 12 EST 8 13 di Tin 9 n 14 10 15 v De 4 17 v 8 1 19 at TFST 20 bid PST Title PEEDI AVR2 Modue ADAPTER Company FCNETIX Sze Rev 10 Amo ILKOILIEV 5152009 1646 hug dO J PEEDI User s manual 116 www ronetix at FAQ 5 FAQ Q What is JTAG
6. ADAPTER 1120 1114 TARGET EVULATOR TI 204n CT TI 14 pin 1 27x2 54nm pitch 2 54x2 54nm pitch Ji Je TVS m TMS out 1 2 TRST in TRST out 2 3 TH in TO out 3 4 nS TUS 4 5 VFEF out Vref in 5 6 NS RST bidr 6 7 TDO out TDOin 7 8 8 9 RTOX out RTCKin 9 10 10 11 aa in TOKout 11 12 12 13 bidr EMD 13 14 bidr EMUI 14 15 FST bidr 16 e V po 7 P x Molex 0015910140 Tyoo 5 1461306 ae Molex 0015916143 Molex OD159tx14x bendi Tyoo 5 1472793 Tyoo 966269 7 Title TI20 1114 Mode ADAPTER Santec RSVH110 02 SD Santec RSM110 02LD amay RONETIX P Pa 10 Hamin VE25152045 Auto ILKOILIEV 6122009 1700 Sed id 1 PEEDI User s manual 114 www ronetix at Specifications ADAPTER PEEDI COP16 http download ronetix info peedi doc schematics peedi cop16 paf PEEDI J1 VHE E PowerPC COP16 3 out Oo 4 L J2 5 out Tm A m out 1 e E Ta in 7 out NS TST in 4 8 NC 5 e NT a 9 out RxD TK in 7 E E l 10 m RO in 8 mo ye in 9 11 TO g m out 10 12 SET in 11 E 0 12 13 E TO H E PST in 13 14 mc 14 e NC 15 15 oc SRESET a W ic 16 e 17 c OK g NEN 18 LI 19 out ST 20 oc FST A i Title PEEDI COP 16 Module ADAPTER Size Company FRONETIX GIVBH m Rev 1 0 Author LKOILIEV 527 2008 1554 Sheet of
7. M 79 jU n rer RN M EE E ERROR CIR ONCE EA UN 79 VO METTE A TN 80 ops ne EA eee eee tee UT 80 KSC tp TEE 80 SS le HH ETC 80 Qf T TN 81 ile e 81 fles H 81 clear r 82 ip rc Em 82 ej T M IQ 82 icio 82 zio n 82 PEED User s manual 7 www ronetix at Contents o PI germ rrr CEN METRE MEN ANE E EE RT NO 82 loo HM C cT x CT 83 HATO WAS pene rn alisha a caidas 83 NO MOC SUNS sti aes Sic aie ant rm 83 MO WAG Cl e e ate 83 MO CONTIG ep HE 83 Infedre mE M 84 e A P 84 MIO SOI ret C em E 85 TRIES 6 ig Denne ETT t 85 WTOP DO nee PE 85 MEMO a EUR 85 MEMO TG dClocicutene Ut Mii uM LU tre ere MEME ULCUS Duc MEC rodent henner ein tere 85 A A a E A a 86 MEMO O gw 86 MEMO ANN aaa E a E RE ER 87 A RR 87 Memory aia aia 87 Ma A A A reat Ener ne 88 MENO VEIS E O ed aa 88 MEMO AUD oo 89 A Rede la a ati ode ee dcc uia e S cpu PEE 89 UL I eee ee ee ee 8
8. Erase from 0x019f0000 0x01a00000 Program from 0x007f0000 0x00800000 at 0x019f0000 RedBoot 3 2 3 RedBoot commands used with PEEDI These commands are used to update configure test and run PEEDI fconfig Syntax fconfig Description Enter RedBoot and PEEDI configuration parameters Arguments None Example fconfig update Syntax update FILEPATH Description Update PEEDI firmware If no argument is provided last used will be taken Default first used argument is taken when fconfig command is used Arguments FILEPATH filepath of the file Example Update update http www myserver com mydir myfile bin update tftp 192 168 1 1 mydir myfile bin update xmodem update ymodem memtest Syntax memtest c Description Test available not occupied by RedBoot RAM Arguments C perform continuous test Example memtest memtest c PEEDI User s manual 20 WWW ronetix at Using PEEDI 3 3 Configure PEEDI 3 3 1 Network configuration RedBoot and PEEDI share the same network settings To set up the network look in RedBoot Configuration Note Purchased PEEDI is set to get its network settings from a DHCP server o You can see the PEEDI IP by pressing and holding the green button on the front PEEDI panel The IP will be shown on the front panel LED indicator Or connect to PEEDI on the RS232 and the IP is shown during boot up 3 3 2 Target configuration file To operate PEEDI needs t
9. Connect to Target F 4 Show Connection Organizer Version L Disconnect All Targets Show Task Window 1 4T91E655 ARM Angel Connection 2 ATILEBSS ARM Multi Ice 3 4T91EB55 and Slingshot 4 Flash hello Setn In the Connection Chooser dialog select the new created connection and click Connect Connection Chooser Connect to a Target Custom cnc Now you should be connected to PEEDI and may start debugging 3 11 4 IAR Embedded Workbench for ARM v4 30 In the Embedded Workbench IDE click Project gt Options to open the options dialog YF LAR Embedded Workbench IDE File Edit View Project Tools Window Help Du Workspace Add Files Add Group H amp M Debug Remove Import File List Edit Configurations Create New Project Add Existing Project Options Alt F7 Source Code Control Make Fe PEEDI User s manual 72 WWW ronetix at Using PEEDI Here select Debugger on the left and Angel for Driver Options for node Basic E 3 X Category Factory Settings General Options C C Compiler Setup Download Extra Options Plugins Assembler Custom Build Driver Runto Build Actionis eas main Linker Simulator Angel IAR ROM monitor I Use macro file O SPROJ_DIRSwescurceWEB55_RAM mac a Macraigar EDI Device description File Third Party Dri OP argy Liwer Override default STUUOLRI
10. File used to describe target specifics loaded at boot up PEEDI User s manual 121 www ronetix at PEEDI package contents 7 PEEDI Package contents Make sure all the items listed below are present when opening the PEEDI package PEEDI Power adapter 5V 1A JTAG or BDM cable and adapter Patch cable CAT5 2m Serial cable 1 1 2m Software CD PEEDI User s manual 122 www ronetix at Warranty 8 Warranty RONETIX warrants PEEDI to be free of defects in materials and workmanship for a period of 24 months following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship RONETIX will replace defective PEEDI The remedy for breach of this warranty shall be limited to replacement and shall not encompass any other damages including but not limited loss of profit special incidental consequential or other similar claims RONETIX specifically disclaims all other warranties expressed or implied including but not limited to implied warranties of merchantability and fitness for particular purposes with respect to defects in PEEDI and the program license granted herein including without limitation the operation of the program with respect to any particular application use or purposes In no event shall RONETIX be liable for any loss of profit or any other commercial damage including but not limited to special incidental con
11. O Power supply NO Reset button oo Ethernet port PEED User s manual 17 WWW ronetix at Using PEEDI 3 2 Setup with RedBoot RedBoot is a bootstrap loader which during normal boot up is used to load and launch PEEDI s executable image RedBoot is also used to update PEED s firmware and to configure network settings which are later used by PEEDI RedBoot has some useful testing facilities like ping and memtest 3 2 1 RedBoot Configuration RedBoot and PEEDI share the same network settings To set the network you need to connect a simple terminal application set to 115200 8 N 1 for example HyperTerminal to the PEEDI s RS232 port using a serial straight through cable with DB9M male and DB9F female connectors on each end Next step is to restart PEEDI by pressing the RESET button while holding both front panel buttons pressed This will tell RedBoot not to load and launch the PEEDI executable if available but to wait for connection on RS232 or Ethernet While rebooting RedBoot should output some diagnostic information on the serial port which you should see When RedBoot is ready to accept commands it will show the command line prompt RedBoot gt Now you can use the fconfig command to set and save to FLASH all the parameters When asked for different parameters please enter the following WARNING If PEEDI is set to get its network settings from a DHCP server and if the Ethernet cable is unplugged or ther
12. PEEDI can be used as a FLASH programmer in two ways The first way is to connect to PEEDI via telnet and execute FLASH command and script files from the command line interface CLI This is the more sophisticated way because you can see all the status messages in an easy understandable format i e warnings and errors Host Crossover cable Sy Q Q S S Target 1 Target 2 Target N The second way is to use the front panel interface to choose start and observe the status of scripts which invokes the desired FLASH commands Here you can define an AUTORUN script to be executed every time a target is connected this way there is no need to start the script manually very useful and time saving when great volumes of targets are to be programmed PEEDI O 4S Target 1 Target2 Target N PEED User s manual 12 www ronetix at Introduction 1 2 2 PEEDI as a device tester Here the PEEDI can be used in the same manner as in the previous section making telnet connection or through the front panel interface Depending on the specifics of what is to be tested two major ways can be followed Execute commands that directly make some sort of test i e flash verify memory crc etc Download executable code into target which will perform the desired test and set a CPU register or memory on exit to a value showing the result of the test Using this method there is almost no test that could not be performed 1 2 3 H
13. this may happen if MSM keys all of 0x000000000 are programmed in to the FLASH Some TMS470 devices have internal Analog Watch Dog timer AWD The AWD must be disabled in order to use PEEDI for debugging or programming The AWD can be disabled by grounding the AWD pin Alternatively WDKICK TIME CFG parameter can be used and PEEDI will kick periodically the AWD 3 4 9 Intel XScale family Debugging XScale core is a little complicated by the fact that the exception vectors must be cached in the mini instruction cache where the debug handler resides PEEDI provides two ways of defining the vectors see Section PLATFORM XSCALE First is to set them fixed suitable when the vectors are not updated dynamically at runtime And the second is to tell PEEDI to read them from the target s memory each time a debug event occurs suitable when vectors are set by the user application at runtime There are several ways to provoke a debug event 1 Set 32 bit write access watch point at the last modified by the user code vector 2 Set hardware breakpoint to a point of the code where the vectors have been set but not yet enabled 3 In the source code add a software break asm bkpt 1 where the vectors have been set but not yet enabled PEEDI recognizes this special break and immediately starts the target again with refreshed vectors Once the target has been stopped by the desired debug event you can again start it and the exception vectors will be
14. csrO Flash at 0x1000000 2 ws memory write OxFFE00004 0x02003029 csri RAM at 0x2000000 2 ws memory write OxFFFFF124 OxFFFFFFFF disable all interrupts Then load and start the executable memory load tftp 192 168 1 1 init bin bin 0x20 load executable image skipping interrupt table set cpsr OxD3 set supervisor mode interrupts disabled set sp 0x200 set stack pointer if program uses stack breakpoint add Ox8 set break at software interrupt vector address go Start executable wait 50 wait to complete halt halt if not completed break del 1 del break at software interrupt vector address Section FLASH This section tells PEEDI what type are the onboard FLASH chips and what their configuration is These are all possible variants of connecting different FLASH chips Internal microcontroller FLASH or external One 8 bit chip forming 8 bit architecture Two 8 bit chips forming 16 bit architecture Four 8 bit chips forming 32 bit architecture One 16 bit chip forming 16 bit architecture Two 16 bit chips forming 32 bit architecture One 32 bit chip forming 32 bit architecture When describing external FLASH configuration the following parameters must be specified External FLASH CHIP CHECK ID PEEDI User s manual 33 www ronetix at Using PEEDI ACCESS METHOD CHIP WIDTH CHIP COUNT BASE ADDR FILE AUTO ERASE Considering your configuration
15. A This is a standardized high speed serial interface IEEE 1149 widely used for programming and debugging programmable logic and processors It is non intrusive runs regardless of the state of the processor and gives access to processor registers memory and other resources Q What is TAP Controller A The TAP controller provides access to many of the test support functions built into the JTAG compliant device The TAP is a state machine The state machine controls all operations for one JTAG compliant device Each JTAG compliant device has its own TAP controller You can sequence through the state machine functions via the TCK and TMS inputs Q What is EmbeddedICE A EmbeddedlCE is an extension to the core architecture and provides the ability to do in circuit emulation with deeply embedded cores The EmbeddedICE macrocell adds a JTAG TAP controller and breakpoint watchpoint logic to the ARM microcontroller which can be accessed externally through a JTAG port Hence software debug is facilitated by interfacing these JTAG pins of the micro to the host development system containing the ARM software development tools through a JTAG interface device such as PEEDI Q What is PEEDI A The PEEDI Powerful Embedded Ethernet Debug Interface is a debugging and development tool that provides the user the ability to see what is taking place in the target system and control its behavior The PEEDI probe provides the debug services that the d
16. Example info registers info registers all info registers 0 info registers 0 all info registers all info registers all all info target Syntax info target CORE Description Show general core information Arguments None Example info target info target 0 info contig Syntax info config Description Show JTAG configuration Arguments None Example info config PEED User s manual 83 www ronetix at Using PEEDI info ice Syntax info ice REGISTER CORE al1 Description Display ICE Breaker registers Arguments Example info ice info ice ice5 info ice 5 info cp15 info cp14 Syntax info cp15 Oxxxxx CORE al1 info cp14 Oxxxxx CORE a11 Description List current CP15 registers values The ARM9 control coprocessor cp15 provides additional registers that are used to configure and control the caches MMU protection system the clocking mode and other system options Via JTAG CP15 registers are accessed either direct physical access mode or via interpreted MCR MRC instructions ARM920 Physical and Interpreted access mapping to CP15 registers Register number for physical access mode bit 12 0 i5 13 en 9 8 7 saje o 090 0 000 1 00 0 x CFn The bit i selects the instruction cache scan chain bit 33 The bit x extends access to register 15 scan chain bit 38 Register number for interpreted access mode bit 12 1 The 16bit register num
17. NEWNAME new file name Example card rename image bin backup bin eeprom Syntax eeprom SUBCOMMAND Description Manage EEPROM files EEPROM file system if flat i e directories are not supported Keep in mind it has very limited storage space tenths of kilobytes Subcommand must be provided Arguments SUBCOMMAND subcommand specifying the operation Example eeprom dir eeprom dir Syntax PEEDI User s manual 98 www ronetix at Using PEEDI eeprom dir SEARCHCRITERIA Description Displays a list of files Arguments SEARCHCRITERIA string to filter printed output Example eeprom dir eeprom dir txt eeprom copy Syntax eeprom copy SOURCE DESTINATION Description Copy file Arguments SOURCE the source file to be copied DESTINATION file to be saved Example eeprom copy target cfg backup cfg eeprom type Syntax eeprom type FILE Description Show content of text file Arguments FILE text file to be shown Example eeprom type target cfg eeprom delete Syntax eeprom delete FILE Description Delete file Arguments FILE file to be deleted Example eeprom delete target cfg eeprom rename Syntax eeprom rename FILE NEWNAME Description Rename file Arguments FILE file to be renamed NEWNAME new file name Example eeprom rename image bin backup bin eeprom format Syntax eeprom format Description Format EEPROM file system erasing all files Arguments None P
18. Period in milliseconds or 0 WAKEUP_TIME Description Time to delay the JTAG operations after RESET is released This time is usually used to allow the clock oscillator to stabilize You must set it for the Sharp LH7A404 Cirrus EP7209 and the Freescale MAC7100 CPU families Argument Period in milliseconds WDKICK_TIME Description If this parameter is present PEEDI will periodically kick the TMS470 Analog Watch Dog timer with the specified time between two kicks Argument Period in milliseconds DBGREQ_OUTPUT Description Define the state of the JTAG DBGREQ line Argument HIGH LOW Core specific parameters Note Multiple core support is an option that has to be purchased from Ronetix if the multicore support is not purchased instead of COREn prefix where n is integer number only CORE can also be used COREn Description Core declaration Argument Type of CORE ARM7TDMI ARM9TDMI ARM920T ARM940T ARMS926E ARM946E FEROCEON and a TAP number separated by comma COREn_STARTUP_MODE Description PEEDI behavior when starting the target Argument RESET Force the target to debug mode immediately out of reset No code is executed after reset default mode STOP XX After power up PEEDI waits XX ms this gives time to the target to execute its own initialization code and target is placed in debug mode halted RUN After reset the target executes code until stopped by the Telnet halt command PEED User s ma
19. TFTP or HTTP server to copy the files from peedi gt transfer tftp 192 168 1 1 mydir MyFile txt card myfile txt The transfer command can also be used to copy files from the memory card to any file server on the Ethernet Before actually copy the files you may need to create some directories delete old files or something else To do this use the PEEDI CLI card subcommands 3 18 JTAG cable adapters PEEDI is packed with one 20 pin standard JTAG adapter cable one custom 10 pin JTAG adapter cable and a 14 pin adapter cable is available for free upon request All adapters are mounted on the PEEDI JTAG connector and next the target cable is connected to the given adapter Adapter JTAG cable Target The ARM20 adapter has standard ARM pinout and may be used with almost all ARM evaluation boards The ARM10 adapter has no standard pinout but it is useful when the target JTAG cable connector has to be small The ARM14 adapter is used for some old ARM evaluation boards If your target JTAG connector pinout is not standard you may need to make your own target cable considering the PEEDI JTAG connector pinout The 4xARM20 adapter is used when you want to take advantage of the multiple core support The adapter automatically shorts the unused JTAG connector pins to chain the available targets so there is no need to set jumpers manually Target 2 Target 1 deal Target 3 4x ARM20 adapter 3 19 PEEDI licenses PEED
20. a ol T NN a nl m i 13 E Tin 12 Tin 12 ain Tol a Ta E y q 13 q B 13 13 fe DEl e mo M THU TDO 14 TOt 14 1 17 18 A 19 out TFST pac BEEN A Bo JC 2 1 1 1 he mE 2 2 2 Z i HOLE3 5M HAB 5MM HAE 5MMHCOLES x Ope x x Tie FEED EF 14 Male ADAPTER Ompay RNE 9m Rev 1 0 EE Alto LKOLIEV 6262008 11 58 Sed 1 d PEEDI User s manual 112 www ronetix at ADAPTER PEEDI TI JTAG 14 http download ronetix info peedi doc schematics peedi ti14 paf Specifications PEEDI TI TARGET F HEADER 2x7 1 in VFEF Jp 2 TMSin 1 3 out TOK TRSTin 2 4 i TD in 3 5 out TO 4 6 0 Vref out 5 7 out TVS FST in 6 8 i TDOau 7 9 8 10 4 0 RTOKout 9 11 in TDO 10 12 TOKin 11 13 in HIOK 12 14 EMD LS 15 i l EMUI Le 16 17 1 E i 18 i S 19 out TRST 20 bidr FET B i R1 R2 P3 not populated o Title PEEDI T114 Mole ADAPTER Compay FONETIX En Fa 1 0 Author ILKOILIEV 6 12 2009 17 04 Shed 1 cd 1 PEEDI User s manual 113 WWW ronetix at ADAPTER TI 20 TI14 http download ronetix info peedi doc schematics ti2O ti14 pdf Specifications
21. 1 1 mydir myimage bin and use it like this peedi flash program myfile bin 0x100 Or even you may define an alias using as base another alias because alias searching is recursive PEED User s manual 100 www ronetix at Using PEEDI peedi gt eeprom alias fpe fp erase 3 14 4 Using scripts Scripts are useful when series of commands are frequently executed For example loading and executing image on the target peedi gt memory load tftp 192 168 1 1 myimage bin bin 0x20 peedi gt set cpsr 0xD3 peedi set sp 0x200 peedi gt breakpoint add Ox8 peedi go Instead of typing all the commands you could create text file and put all command to be executed MyScript txt memory load tftp 192 168 1 1 myimage bin bin 0x20 load image set cpsr OxD3 disable interrupts set sp 0x200 Set stack breakpoint add 0x8 set breakpoint go Start execution Comments could be used in script files command processor ignores everything after character to the end of the line If some command returns error code script execution is interrupted and error message is issued Aliases can also be used in scripts Once the script file is ready it can be ran with run command peedi gt run tftp 192 168 1 1 mydir MyScript txt The script file could reside anywhere PEEDI could load a file local EEPROM MMC SD card TFTP FTP HTTP servers 3 15 Working with the FLASH programmer PEEDI has built in universal FLASH pro
22. 3 4 13 Freescale MCF5200 family The Freescale MCF52xx family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files WARNING Set very carefully the CPU CLOCK parameter otherwise the FLASH may be damaged 3 4 14 Analog Devices Blackfin family Most of the Blackfin devices can access only up to 4MB of external FLASH memory Usually this limitation is workarounded by connecting the free higher address pins of FLASH to PIO PFx pins of the CPU So the software running on the CPU must ensure the PFx pins are driven properly to access the PEEDI User s manual 55 www ronetix at Using PEEDI desired part of the FLASH PEEDI also supports this kind or FLASH configuration making the work with such kind of configuration just like as the FLASH is entirely visible For more information see Section PLATFORM BLACKFIN PEEDI supports programming of NAND flash chips connected to the CPU s async bus or the NFC controller FLASH and Atmel DataFlash chips connected to the CPU s SPI For all these configurations PEEDI writes only to the specific peripheral controller registers It is the user s responsibility to set the needed GPIOs in the INIT section of the CFG file i e to set the corresponding PORTx FAR and PORTx MUX registers so the FLASH is accessible through async bus NFC or SPI For help on this check the sample CFG files from our website It is
23. 30 Section PLATFORM GOLDE IRE uenis Senate et id 30 Section PLATFORM BLACKFIN sientas serus tt mad cud es ici 30 Section PEATEORM MIPSS92 1 entra ute o bie beh Last iec ance oni S etate idees 32 section PLATFORM A VAS E 32 SECUOMINI HP S 32 SOCIO E EA SEI ue neat eio enun TC endende oat ati educa cedente etia sU M Ui op s ee 33 sies O 0 ER PC RE SE E 44 BS CLL PRA acid a dei el 46 SECO Bas LNE err osos ere et ee 46 Secon DISPLA dis la 47 DECHONMAG TON le 47 PEEDI User s manual 6 WWW ronetix at Contents 3 4 CPU specific considerallons icini ctore e p cuc o dau tede cpu iia 49 3 45 Atmel ATSTSADZ Tamil in lod 49 24 2 AlmeL AVRS2UG family secti eoa Eoo id 49 34 3 Philips EPC 2000 TMV N 49 3 4 4 Freescale MAC7100 family cccccsssseeeecceceesseceeesneeeseeeeeseneeseeeeceesaeseeeeeesauagseseeesanagess 49 9 4 5 S T 9 TA LAMA e 50 CE CIE STR TIM TEE 50 cr acu cile str 51 349 nrssrercun ce Lr 51 34 9 INTE XScale Taly M TR S 52 3410 NAND ELA ccm E 52 3 4 11 Freescale MPC5500 amilasa ER 53 3 4 12 Freescale PowerQUICC II Pro MPC83XX family sse 55 3 4 13 Freescale MCF5200 family cccccssscccccceesseeececeeeesseeeceeseeeeuseceeseaaeseeeeessaueuseeeeessnagass 55 3 4 14 Analog Devices Blackfin family occoononccccononocococonnnncccononnoononennononnnononcannnnonnnnnos 55 39 rre
24. Accepted value 1024 65535 PROTOCOL Description Describes the debugger protocol If several protocols need to be enabled they must be enumerated on the same line separated by comma Argument gdb remote GDB remote protocol will be used adp Angel debug protocol will be used GDB READ INGNORE TIME Description PEEDI User s manual 21 www ronetix at Using PEEDI This is GDB problem workaround If read target memory error occurs within this period after the GDB is connected no error will be returned to GDB This is because GDB refuses to connect to the target if it gets an error during the connection procedure GDB tries to read the stack frame during the connection sequence and this may lead to invalid memory accesses Argument Period in milliseconds Example DEBUGGER PROTOCOL PROTOCOL gdb remote adp gdb remote and adp protocols REMOTE PORT 2000 TCP IP port GDB_READ_INGNORE_TIME 3000 Read error ignore period Section TARGET This section describes the target s platform PLATFORM Description Target s platform Argument ARM ARM11 CortexM3 CortexM3 SWD CortexA8 XScale Blackfin MPC5500 MPC8300 ColdFire or MIPS32 Example TARGET PLATFORM ARM Section PLATFORM_ARM In this section there are parameters specific to the given ARM cores Every core must be defined with the COREn parameter where n is a number each parameter related to this core must be preceded with the same COREn pr
25. Appendix A Sample target configuration files The ALLOW SHADOW MODIFY FLASH section parameter is used to protect the device from unwanted permanent locking this may happen if Shadow FLASH is erased or the configuration word programmed to something different than 0x55AA55AA For more information read MPC55XX Reference Manual Insight gdb versions below 6 0 are not supported because they have different register order defined in the gdb remote debug protocol PEEDI User s manual 54 www ronetix at Using PEEDI 3 4 12 Freescale PowerQUICC II Pro MPC83XX family PEEDI supports debugging Linux kernel running on MPC8300 devices with MMU enabled If the instruction or data address translation is enabled IR and DR bits set in MSR PEEDI assumes all the addresses used by gdb or the user in the console to be effective and need to be translated to physical ones before the very memory access First PEEDI ties a BAT translation if it fails and the COREn MMU PTBASE parameter is present in the target configuration file then PEEDI tries a page translation on the given address The COREn MMU PTBASE parameter must point to a physical address which contains the virtual address of the two pointers array COREn MMU PTBASE Address of the array Address of swapper pg dir Second user pointer Before debugging the user must manually set all the pointers using mem write commands which can be put in the INIT section for example Newer Linux kernels h
26. BOD OM alldas E m 100 3 143 Using allas ca AN 100 AA USING SCFIDIS aid dro 101 3 15 Working with the FLASH programmer eeeeeeeeeeeee eere eene enne nennen nennt 101 3 16 Multiple FLASH SUDDOLE cic iri rio a ae aenea ru put ondit a e deduc adde ce asa sequ 102 3 17 Working with a MMC SD Memory card 1111 eeeeee e eeeeeee eene nennen nnn nennt 102 3 18 JTAG Cable adapIers iones 103 3 19 PEEDIMNCENSES anar 103 As SPECIFICATIONS uiiidisieecersecesk oc depo a 105 5 gio 117 6 Be iu 120 f PEEDILPACKAGE CONTENTS aaa 122 8 WARRANTS ed 123 APPENDIX A SAMPLE TARGET CONFIGURATION FILES 124 PEEDI User s manual 9 WWW ronetix at Introduction 1 Introduction PEEDI Powerful Embedded Ethernet Debug Interface is an EmbeddedICE solution that enables you to debug software running on ARM processor cores via the JTAG port JTAG is an IEEE standardized protocol that enables full control of the CPU core giving the opportunity to debug embedded software which extremely reduces Time To Market and increases the quality of the end product PEEDI is a debugging and development tool that provides the ability to see what is taking place in the target system and control its behavior PEEDI provides the services needed to perform all debugging operations It receives command packets over the communication link and translates them into JT
27. If no arguments are provided last used will be taken Default first used arguments are taken from FILE parameter of the currently selected FLASH section in target configuration file Arguments PIED cores to program COREn Or all FILE the image file to be programmed FORMAT format of image file bin binary file inex Intel HEX format srec Motorola S record format elf ELF format OFFSET Must be provided for binary files because they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset Example flash multi program 0 2 tftp 192 168 1 1 image elf elf flash multi program all ftp 192 168 1 1 imge bin bin 0x100 flash multi verify Syntax flash multi verify COREO COREn FILE FORMAT OFFSET Description Check image file onto several targets simultaneously If no arguments are provided last used will be taken Default first used arguments are taken from FILE parameter of the currently selected FLASH section in target configuration file Arguments FGOREO Cores to program COREn Or fall PEEDI User s manual 92 www ronetix at Using PEEDI FILE the image file to be programmed FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format OFFSET Must be provided for binary files because they don t have any address information lf provided with hex srec o
28. NOR chips the memory read command may be used Arguments PEED User s manual 93 WWW ronetix at Using PEEDI ADDRESS start address COUNT count in bytes Example flash read 0x1000 8 Flash read flash into Syntax Flash info Description Show target FLASH configuration information Arguments None Example Flash info flash find Syntax Flash find SEARCHCRITERIA Description List specified or all chips in FLASH data base Arguments SEARCHCRITERA used to filter listed output and wild characters are also accepted Example flash find flash find AT49BV160 flash find 29r flash this Syntax flash this SUBCOMMAND Description The flash this command is used to execute FLASH specific subcommand available only for the given FLASH See below for the available commands Arguments SUBCOMMAND FLASH specific subcommand to be executed Example flash this hidden enter flash this hidden exit flash this nvmbit 2 1 flash this hidden Syntax flash this hidden enter exit Description Enter exit hidden ROM mode on some FLASH devices Once the hidden ROM mode is entered the flash erase and flash program commands can be used on the hidden FLASH sector Arguments enter enter hidden ROM mode exit exit hidden ROM mode Example flash this hidden enter flash this hidden exit PEEDI User s manual 94 www ronetix at Using PEEDI flash this nvmbit Syntax flash this nvmbit BIT VALUE Description Set
29. Note No error is returned to GDB in case of an invalid 4 byte memory read access during a period defined by GDB READ INGNORE TIME in the target configuration file o This is because GDB refuses to connect to the target if it gets an error during this i connection sequence GDB tries to read the stack frame during the connection sequence and this may lead to invalid memory access PEEDI User s manual 62 WWW ronetix at A 3 11 Working with other debuggers Since PEEDI supports Angel Debug Protocol ADP any debugger which can connect to the ARM s Angel Debug Monitor may be used to debug with PEEDI At the moment most of the debuggers are ADP compatible so you may use practically all of them to debug with PEEDI Generally you must set the debugger to connect to PEEDI which will act as a target debug monitor via Ethernet using the Angel debug monitor protocol on the IP you have assigned to your PEEDI Since ADP is not designed to be used with multiple cores if your PEEDI is connected to more than one core you can select the core you wish to connect to using the adp CLI command Make sure you have enabled the ADP protocol in the PEEDI s configuration file DEBUGGER PROTOCOL adp ADP debug protocol Here are some examples on how to set some of the most popular debuggers to work with PEEDI Note To successfully connect to PEEDI using the ADP protocol the ADP protocol must be enabled in the target configuration file of PEEDI
30. Offset of the field that points to the next item PID 4 OxEO offset of the field containing the task PID NAME 16 Ox1FC offset of the field containing the task name CONTEXT 10 4 0x4 Ox1C offset of the field containing the task context CONTEXT REG r4 0x00 list of reg names and their offsets in the context CONTEXT REG r5 0x04 CONTEXT REG r6 0x08 CONTEXT REG r7 Ox0C CONTEXT REG r8 0x10 CONTEXT REG r9 0x14 CONTEXT REG r10 0x18 CONTEXT REG r11 0x1C CONTEXT REG sp 0x20 CONTEXT REG pc 0x24 For Linux the section should look like this OS ARM UCLINUX v26 PEEDI User s manual 74 WWW ronetix at Using PEEDI BASE 4 OxCO2FF068 address of init task structure NEXT 4 OxB4 offset of the field that points to the next item PID 4 OxEO offset of the field containing the task PID NAME 16 Ox1FC offset of the field containing the task name CODE START 4 OxBC 0x48 offset of the field containing the task code addr DATA START 4 OxBC 0x48 8 offset of the field containing the task data addr BSS START 4 OxBC 0x48 12 offset of the field containing the task data addr CONTEXT 10 4 0x4 Ox1C offset of the field containing the task context CONTEXT REG r4 0x00 list of reg names and their offsets in the context CONTEXT REG r5 0x04 CONTEXT REG r6 0x08 CONTEXT REG r7 OxOC CONTEXT REG r8 0x10 CONTEXT REG r9 0x14 CONTEXT REG r10 0x
31. TMS e 6 8 EVT 7 9 out GDBRQ g HEADER 2x7 10 FST in 9 E in TDO TVSin 10 Vref out 11 13 in g 12 14 FDY out 13 15 in GDBACK JOOP 14 16 17 NC 18 m 19 9 TEST po 20 bid PST i Title PEEDI FREESCALE JTAG Maie ADAPTER Omay FCNETIX Sze Rx 1 0 Author ILKOILIEV 6122009 16 42 Shed 1 d 1 PEEDI User s manual 110 www ronetix at Specifications ADAPTER PEEDI Freescale BDM26 http download ronetix info peedi doc schematics peedi bdm26 paf ColdFire BDIVP6 PEEDI y Je a Nc J BT in 2 1 in VE 3 2 DSAK in 4 3 at TOK e 5 4 NC 6 o 5 at Ta RST 7 ae DS in 8 7 at TVS M 9 198 y D at 10 9 NS 11 10 NO O 11 in TDO pe is 12 M 14 13 in RICK ue 15 14 NC 16 bo o E 15 17 NC ME 16 NS O 17 1 ME a y NO 9 18 20 amp 19 at TRST E 21 20 bdr RST y NO 22 23 QKCHJ at 24 EMEN 25 MM E NC TA in 26 Title PEEDI BDIVP6 Maie ADAPTER QGnpay RONETIX p Rv 1 0 Atha RONETIX 6122009 16D Sed 1 d 1 PEEDI User s manual 111 www ronetix at Specifications ADAPTER PEEDI Blackfin JTAG 14 http download ronetix info peedi doc schematics peedi_bf14 paf
32. all data that is sent from the telnet application to the TCP port is forwarded to the RS232 port Note that no flow control is supported You can use the normal command line telnet connection to PEEDI simultaneously as they work completely independent For information how to set serial port parameters see section SERIAL in Target configuration file chapter 3 9 ARM DCC Interface On ARM targets PEEDI routes the core s DCC to a TCP port This way if a telnet connection is opened to that TCP port the telnet application will receive each byte coming in through the DCC The TCP port to connect to is the value specified for the COREn DCC PORT parameter in the target configuration file You can use these GNU GCC compatible simple C functions in your target code to communicate via the DCC define DCC_TX_BUSY 2 define DCC RX READY 1 unsigned int dcc recv char void unsigned int cc status PEEDI User s manual 60 WWW ronetix at Using PEEDI do asm X volatile mrc p14 0 0 cO cO n r status while status amp DCC RX READY e3sm mrc pl4 0 0 c1 c0 n r cc return cc j void dcc send char unsigned int cc unsigned int status do __asm__ volatile mrc p14 0 0 cO cO n r status while status amp DCC TX BUSY lt asm mcr PLA 0 0 c1 cO novi cop ECOS j void dcc send string const char ss while ss dcc send char ss Keep in mind that
33. and Appendix A Sample target configuration files 3 4 3 Philips LPC2000 family The Philips LPC2000 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files To successfully connect to a LPC2000 device the pull down resistor that enables the JTAG interface must not be more than 1k because PEEDI has internal 10k pull ups Because the JTAG clock is synchronized to the internal CPU clock it is recommended to use adaptive JTAG clock or clock up to 1MHz for normal work the second argument of the JTAG_CLOCK parameter To successfully program a LPC2000 device make sure you have specified valid RAM address for the CORE_WORKSPACE parameter in the PLATFORM ARM section The internal RAM starts from 0x40000000 so this is a good value for this parameter To successfully verify the FLASH contents first you must set the MEMMAP register to map the flash vectors at address 0x00000000 like this memory write 0OxXE01FC040 0x00000001 You may issue the previous command every time you need to verify or you may put it in the init section of the core in the target configuration file this way it will be executed automatically To secure the LPC2000 device your application must set FLASH address location Ox1FC User flash sector 0 with value 0x87654321 2271560481 Decimal when programmed This will disable the JTAG port and some of the ISP command
34. and its license to be present as well For more information see the explanation of the DEBUGGER section of the target configuration file in the PEEDI user s manual 3 11 1 ARM Developer Suite ADS v1 2 AXD debugger When your project is built click the debug Icon to start the AXD debugger UNE dev P Order Targets ets Then click Options gt Configure Target to open the Choose Target dialog Views Execute Options Window Help Disassembly Mode Configure Interface Configure Target Configure Processor Source Path w Status Bar Profiling PEED User s manual 63 WWW ronetix at Using PEEDI Here click Add to open the Open file dialog Select the Remote A dll in the ADS s Bin folder and click Open Remote A dll is the RDI to ADP interface library Choose Target Target Environments ttbzdb m C vi 3 an P Use the ARM Debugger with the y 2 PluainLib dl 3 seminost dl Timer dll ttb dll execute ARM programe without pk E Profiler dll 5HW 32 DLL toolconf dll EEb_pre Instructions in software raetherdriver all Stackuse dll Tracer dll Tube c raserialdriver dll sunvrmhub dll tracesupport dl validat EA gt File name Remote 4 dll Files of type DLLs dil Cancel y Now select the new created target and click Configure to open the Remote A connection dialog Choose Target E xl Target Environments 1 5 1 Es BinsAemote A
35. be debugged Cgdb continue Start the application Or Cgdb si make single step When finished debugging you can leave gdb insight in to ways with or without resetting the target To exit resetting the target type Cgdb quit Otherwise type gdb detach gdb quit To make your life easier you may define various commands in a gdb init file and tell gdb to load that file when starting like this arm elf insight command my_gdb_init Assuming that your PEEDI has IP 192 168 1 10 my gdb init file may contain something like this this will tell gdb to connect to PEEDI using remote protocol target remote 192 168 1 10 2000 info target the following will define a user command define 11 set cpsr 0xD3 load end Download Performance By default GDB versions previous than v6 5 50 from 06 08 2006 download program code and data in small packets that are not necessarily a multiple of four bytes in length This causes program download times to be slower than necessary especially with ARM targets There are two GDB internal variables that affect this To improve GDB download performance you should set the download write size to a binary value 16KB and the memory write packet size to a larger value to allow for packet overhead 4100 bytes is plenty For example to download 16KB at a time gdb set remote memory write packet size fixed gdb set remote memory write packet size 16384 gdb set download write size 16128
36. controller peripheral A pin 2 SPI MISO Description This describes which PIO is dedicated to the SPI MISO signal Used when describing Atmel DataFlash Argument controller peripheral pin for example PIOA A O PIOA controller peripheral A pin O SPI MOSI Description This describes which PIO is dedicated to the SPI MOSI signal Used when describing Atmel DataFlash Argument controller peripheral pin for example PIOA A 1 PIOA controller peripheral A pin 1 SPI CS Description This describes which PIO is dedicated to the SPI CS signal Used when describing Atmel DataFlash Argument controller peripheral pin for example PIOA A 3 PIOA controller peripheral A pin 3 If the CPU parameter is set to BF5XX this parameter accepts values of 1 to 7 which corresponds to FLG1 FLG7 See BlackFin s SPI FLG CMD BASE Description Base address that if written to the NAND CLE signal will be asserted On MPC83XX devices with built in NAND FLASH controller this parameter tells PEEDI the offset of Internal Memory Mapped Registers i e value of IMMRBAR Argument Address DATA BASE Description Base address that if written to the NAND ALE and CLE signals will be inactive PEEDI User s manual 41 WWW ronetix at Using PEEDI On MPC83XX devices with built in NAND FLASH controller this parameter tells PEEDI the address of the data buffer used by NAND FLASH controller Argument Address ADDR BASE Description Base address that
37. dll 1 20 805 m 151 C X Bin amp RMulatedl 120805 T Bleue Save Ag Configure Connect the SAM Debugger directly to a target board or to an EmbeddedlCE unit attached to a target board Directly connected target boards require Angel debug monitor software Conforms to RDI 1 51 Cancel Help PEED User s manual 64 WWW ronetix at Using PEEDI In the dialog click Select and select ARM Ethernet driver Remote A connection Remote connection driver Name No diver selected Filename Filename Description Available connection drivers Configuration ARM ethernet driver ARM serial driver ARM serial parallel driver Cancel Help Heartbeat Enabled Disabling heartbeat will disable host timeout and packet resend Browse IN A SS Endian v Lith Big There i no need ta specify the endianness of Angel targets Remove LIF Cancel Help Click Configure and enter the IP address of your PEEDI and click OK on both dialogs to close them Remote A connection EE rx Remote connection driver M ame RM ethernet driver Filename Jraetherdriver dll Descriptions Remote 4 Ethernet driver amp 1999 2000 AAM Ltd Communications driver for use with Angel Debug Monitor Configuration address undefined Configure Cha eee ethernet connection Target IP address i dz 158 3 53 E Cancel Help He
38. if written to the NAND ALE signal will be asserted Argument Address CS ASSERT Description Describes memory write operation address data that will assert the NAND chip select connected to a PIO pin Argument Address and data to be written CS RELEASE Description Describes memory write operation address data that will release the NAND chip select connected to a PIO pin Argument Address and data to be written ALE ASSERT Description Describes memory write operation address data that will assert the NAND Address Latch Enable connected to a PIO pin Argument Address and data to be written ALE RELEASE Description Describes memory write operation address data that will release the NAND Address Latch Enable connected to a PIO pin Argument Address and data to be written CLE ASSERT Description Describes memory write operation address data that will assert the NAND Command Latch Enable connected to a PIO pin Argument Address and data to be written CLE RELEASE Description Describes memory write operation address data that will release the NAND Command Latch Enable connected to a PIO pin Argument Address and data to be written BAD BLOCK TABLE Description If this parameter is set to YES PEEDI will check for Linux style main and mirror Bad Block Tables and if not found it will create them on the last two good blocks of the NAND FLASH chip Argument YES NO BAD BLOCKS PEEDI User s manua
39. multi load COREO ZCOREn FILE FORMAT OFFSET Description Load image file into several targets simultaneously If no arguments are provided last used will be taken Default first used arguments are taken from COREn FILE of target configuration file While file is loaded PC will be set at start of the image or at entry point if provided by the image file Arguments SCOREO cores to load the file to COREn Or all FILE the image file to be loaded FORMAT format of image file bin binary file inex Intel HEX format srec Motorola S record format elf ELF format CE Must be provided for binary files because they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset Example memory multi load all tftp 192 168 1 1 image bin bin 0x1000 memory multi load 0 2 tftp 192 168 1 1 image elf elf memory verify Syntax memory verify FILE FORMAT OFFSET Description Verify target RAM with image file If no arguments are provided last used with the memory load command will be taken Arguments FILE the image file to be verified with FORMAT format of image file PEEDI User s manual 88 www ronetix at Using PEEDI bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format PPE Must be provided for binary files because they don t have any address information If provided with ihex s
40. these are blocking functions 3 10 Working with Insight gdb To be able to debug an application with gdb the application must be compiled using the g O0 options to enable debugging and disable optimizing When your application is built and ready to be debugged start gdb or insight arm elf gdb myapp Or arm elf insight myapp To connect to the target assuming that your PEEDI is set to use IP 192 168 1 10 type in the console window gdb target remote 192 168 1 10 2000 This will tell GDB to connect to PEEDI using remote protocol Now you can load your application into target s memory like this Cgdb load This will load required application sections into target memory at addresses specified during the link process User can manage these addresses using linker script files While load command is being executed gdb sets PC to the entry point of the application if you want to start execution from another point or just the real entry point is different from the one set by gdb you can manually set PC to a desired location like this Cgdb set pc 0x200040 If you want to make sure that your application starts with all interrupts disabled you can do this gdb set cpsr 0xD3 If your application utilizes stack and the startup code does not initialize the stack pointer you can do this manually like this gdb set sp 0x201000 PEED User s manual 61 WWW ronetix at Using PEEDI Now your application is ready to
41. to connect to the target Connection Control Administrat rvdebug brd E B af xj Help EHA ABM A PR APM Ltd RDI targets H APMulator ARM instruction set simulator Remote A dll Ci Program FilesMAEMEDI MTargetsMEemote 411 3 1190 AARM o o pd E localhost Connect Defining Mode Connection Properties At this point you should be able to load and debug the project executable image PEEDI User s manual 69 www ronetix at 3 11 3 Green Hills MULTI v3 6 for ARM Click Target gt Show Connection Organizer to open the Connection Organizer FA Builder for default bld File Edit Project Build Debug Target Version Config Windows Help 6 E E Connect to Target F4 D e Show Connection Organizer Disconnect Al Targets Show Task window Version Filename default bld default con k ENS eae CC hello c 1 4T91E655 ARM Angel Connection Elresource bid 2 ATILEBSS ARM Multi ICE resource reactne 0303 ATATEBSS end slingshot hpserv Standard d 4 rdiserw multiice 3 rdiserv adp stand Flash hello ocdsery standard 3 Darg setun In the Connection Organizer click Method gt New to open Create New Connection Method dialog a Connection Organizer File Method Target Oper Eonmectto Target Us Eonmect and Debug Open Executable del Connect and Debug Connect and Flash Edit ony Move Delete In Create New Connection Method dialog type some co
42. update command is invoked RedBoot update If not changed the default update path points to the last version of the firmware directly on the RONETIX web site If update 1 is entered also the last version of the firmware directly from the RONETIX web site will be downloaded The following command will attempt to download the firmware using the HTTP protocol from a directory on the server this syntax can be used with TFTP too RedBoot update http server subdir file bin After you enter the command using your specific conditions if the host is accessible and the file is present you should see this RedBoot gt update load r m tftp b 0x100000 h 192 168 1 1 fw peedi revA last bin Raw file loaded 0x00100000 0x002abi1bf assumed entry at 0x00100000 Current Firmware Hardware Ver Software Ver Rua ON PEEDI User s manual 19 WWW ronetix at Using PEEDI New Firmware Hardware Ver 1 2 Software Ver 1 1 Install PEEDI firmware version 1 1 y n y WARNING The firmware image you are trying to load exceeds your update license Continue update y n y fis delete peedi Erase from O0x01840000 0x019fTO0000 222 22222 5 9932 Erase from 0x019f0000 0x01a00000 Program from 0x007f0000 0x00800000 at 0x019f0000 fis create b 0x100000 1 Ox1AB1CO f 0x1840000 e 0x600040 r 0x600000 peedi Erase from 0x01840000 0x019f0000 nnn nr Program from 0x00100000 0x002abi1cO at 0x01840000
43. will be take effect after the next start 3 2 2 Firmware update procedure First of all you need to reset PEEDI by pressing the RESET button on the back while holding both front panel buttons pressed This will tell RedBoot not to load and launch the PEEDI executable but to wait for connection on RS232 or Ethernet Entering the RedBoot command line prompt can be done using two different ways via RS232 port using serial straight through cable and a simple terminal application set to 115200 8 N 1 or if the network is configured you can connect using telnet application Once in the RedBoots command line prompt verify by pressing ENTER RedBoot s prompt should appear RedBoot gt you can update the firmware the following ways 3 2 2 1 Update via RS232 If you want to update PEEDI via RS232 your terminal application must support XMODEM or YMODEM protocols Now execute RedBoot gt update xmodem Or RedBoot gt update ymodem to tell RedBoot to start listening on RS232 port for incoming packets Next tell your terminal application to start downloading the PEEDI firmware 3 2 2 2 Update via Ethernet Now you may use update command to update the PEEDI firmware You can update using TFTP HTTP The syntax of the update command is update FILEPATH The command shown below will attempt to download the firmware using the default filepath entered while configuring RedBoot using the fconfig command or the path used when last
44. you must specify CHPIS and WIDTH parameters WIDTH is the width of a single chip so system width will be CHIPS multiplied by WIDTH When describing internal microcontroller FLASH the FLASH section parameters depends on the specific microcontroller family For Atmel AT91SAM7 family these are Atmel AT91SAM7 CHIP CPU CLOCK AUTO LOCK SECURE FLASH FILE AUTO ERASE For Atmel AVR32UC3 family these are Atmel AVR32UC CHIP AUTO LOCK SECURE FLASH FILE AUTO ERASE For Philips LPC2000 family these are Philips LPC2000 CHIP CPU CLOCK CHECK ID FILE AUTO ERASE SET VECTORS CHECKSUM For Philips LPC2900 family these are Philips LPC2900 PEEDI User s manual 34 www ronetix at Using PEEDI CHIP CPU CLOCK FILE AUTO ERASE ACCESS METHOD For Freescale MAC7100 family these are Freescale MAC7100 CHIP MAC7100 or MAC7100 DATA CPU CLOCK FILE AUTO ERASE For ST STR7 family these are ST STR7 CHIP DATA BANK ACCESS METHOD BASE ADDR SECURE FLASH FILE AUTO ERASE AUTO LOCK For ST STM32 family these are ST STM32 CHIP BASE ADDR ACCESS METHOD FILE AUTO ERASE For Microchip PIC32 family these are PIC32 CHIP ACCESS METHOD FILE AUTO ERASE For Tl TMS470
45. you target configuration file and reboot PEEDI If the license is not meant for this PEEDI it will be simply skipped this means that multiple PEEDIs may load single shared target configuration file just fill in all PEEDIs licenses PEEDI User s manual 104 WWW ronetix at Specifications 4 Specifications 5kHz 33MHz JTAG Clock Adaptive Clocking Target Voltage hey oN Network Interface Ethernet 10 100 BaseT Serial Interface RS232 5V 1A reverse polarity protection overvoltage protection up to 100V 6 9V overvoltage shutdown Robust Aluminum case 115x105x35mm Power supply 2 54mm pitch IEC 1000 4 2 Direct Discharge 4kV Power Jack 2 1mm 2 5 kV Human Body Model 500 V CDM S 45V Electrostatic Discharge Protection Operating temperature 5 C 60 C Storage temperature 20 C 80 C Relative humidity non T PEEDI User s manual 105 www ronetix at Specifications JTAG Target connector signals 1 REPARAR Note Each signal JTAG pin has a 10k pull up 1 2V 5 0V Target reference voltage used to create the logic level Vcc Target Input reference for the input comparators It also controls the output logic levels to the target It is normally fed from Vcc I O on the target board JTAG Clock Connects to the target TCK line JTAG TDI Output Test Data In signal from PEEDI to the target JTAG port Connects to the target TDI line Output JTAG TMS p Connects to the target TMS line Out
46. 10 4 TMS in 6 HEADER 2x5 11 in TDO RST in 7 12 i TDI in 8 13 in RTCK Vref out 9 14 TDO out 10 15 NC 16 17 NC 18 19 out TRST A 20 bidir RST Title PEEDI ARM10 Module ADAPTER Company RONETIX res Rev 1 0 Author ILKO ILIEV 7 17 2005_13 19 Sheet 1 of 1 PEEDI User s manual 108 www ronetix at Specifications 4x ARM20 JTAG cable adapter schematic http download ronetix info peedi doc schematics peedi 4xARM20 paf x ADAPTER PEED 4x ARVRO EF AAA VREFO y 100 P4 RAN VREF y LV V M Dider for he NON AUTOversion 100 PS RANI I LAA MT 100 F6 RAND VERS YY Vi 100 e 220 220 en 220 a 220 D4 RAN D5 RAN Ds RAN D7 AA p gt as HA Pw Paws LTST C170KT Fo LTST Ct70CKT RIO LTST Cf70CKT RH LTST Ct70CKT Ri2 1 ry d A 2 BATS4ON 44 e Td PEED a 2 APMTARCET O ARVITARCET 1 APMTARGET 2 ARVITARCET 3 BAT54ON J1 J2 J3 J4 J5 1 h e Mero o 1 REFI 1 VHS o 1 VES e 1 2 2 2 2 2 3 out TRSTin 3 TRST 3 T
47. 18 CONTEXT REG r11 0x1C CONTEXT REG Sp 0x20 CONTEXT REG pc 0x24 For eCos the section should look like this OS ARM ECOS v2 BASE 4 0x6a74 O address of init task structure NEXT 4 OxEC Offset of the field that points to the next item PID 2 0x58 offset of the field containing the task PID NAME 32 OxE8 O offset of the field containing the task name CONTEXT 19 4 0x0c 0 offset of the field containing the task context CONTEXT REG r0 0x00 list of reg names and their offsets in the context CONTEXT REG r1 0x04 CONTEXT REG r2 0x08 CONTEXT REG r3 OxOC CONTEXT REG r4 Ox10 CONTEXT REG r5 0x14 CONTEXT REG r6 0x18 CONTEXT REG r7 Ox1C CONTEXT REG r8 0x20 CONTEXT REG r9 0x24 CONTEXT REG r10 0x28 CONTEXT REG r11 0x2C CONTEXT REG r12 0x30 CONTEXT REG sp 0x34 CONTEXT REG Ir 0x38 CONTEXT REG pc 0x48 the PC placeholder is not filled so we use svc lr instead CONTEXT REG cpsr 0x40 Debugging uClinux applications Since uClinux is a MMU less port of Linux and loads applications at different addresses every time thus itis hard to debug applications because the debugger does not know applications sections addresses To tell the gdb the addresses you need first use the info threads and then the add symbol file command like this peedi info threads 11 thread 18 spar OxF64040 s data OxF4A004 s bss OxF53104 Ox00f6918c in 10 thre
48. 192 168 1 1 image elf elf 0x1000 flash program tftp 192 168 1 1 image bin bin 0x1000 flash multi erase Syntax flash multi erase COREO COREn ADDRESS LENGTH chip Description Erase all FLASH sectors that belong or overlap to the specified region on into several targets simultaneously If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments on cores to erase COREn Or all ADDRESS beginning of FLASH region LENGTH length of FLASH region in bytes default is 1 if not supplied Example flash multi erase all 0x400000 0x1000 flash multi erase 1 2 0x400000 0x1000 PEEDI User s manual 91 www ronetix at Using PEEDI flash multi erase Zall chip flash multi blank Syntax flash multi blank COREO COREn ADDRESS LENGTH Description Check if blank all FLASH sectors that belong or overlap to the specified region on into several targets simultaneously If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments gone cores to check COREn Or all ADDRESS beginning of FLASH region LENGTH length of FLASH region in bytes default is 1 if not supplied Example flash multi blank Zall 0x400000 0x1000 flash multi blank 1 2 0x400000 0x1000 flash multi program Syntax flash multi program COREO COREn FILE FORMAT OFFSET Description Program image file into several targets simultaneously
49. 4 PowerPC set spr register by number Set RAMBAR 0x0 ColdFire set control register by name set ctrl 0xC05 0x0 ColdFire set control register by address Syntax halt CORE al1 Description Stop current or specified core s If no core is specified current will be stopped Arguments CORE core to be stop fall all cores will be stopped Example halt halt 0 halt Hall Syntax reset detect reset run stop MILISECONDS Description Hardware reset all core on the JTAG chain causing re initialization of each core If no argaments are provided last used will be taken or the reset will be performed considering the CORE STARTUP MODE config parameter Disable enable target reset detection Arguments reset reset and stop the target immediately run reset and leave the target running stop MILISECONDS reset and stop the target after specified time detect 0 disable the target reset detection detect 1 enable the target reset detection Example reset reset reset reset run reset stop 1000 reset detect O reset detect 1 Syntax PEEDI User s manual 81 www ronetix at Using PEEDI echo jtag beep jtag target quit reboot redboot watchdog Description Reboot PEEDI and reload the target configuration file and re initialize all cores Reboot and enter RedBoot command line Enable PEEDI internal watchdog Arguments None Example reboot reboot redboot reboot watchdog Syntax ech
50. 9 iae c ic 89 MASI ONAN impeMT H 90 Ul bic Dp 90 VAS TOM NO A Tct 90 MASI VOM OG ob Mc ERES 90 Ep ke Sa A nn ae ETES 91 CDO q PO OPC OOO UE O E leto dac sere centr I rli 91 itas Muero iia dl 91 io DIIS 33 erste te cece ueste dau tuteutie dien epa Sete ea ee she tence hate ars Eu aee US eq 92 TAS A AMAT Prog aM NOTE TE E 92 A hei E castes tea ate teak ieee dfe DAUERN I RE 92 MASIVO Mi apa Mte rer tere ter E emer LS Nu nu Sl UEM ae 93 utem Me ee ca 93 A A eme 93 A 94 UC Hio e Cnm 94 itis c di 94 co a A 94 MAMI IV a os 95 ASAS SS CU a ice e 95 o cm scu hdeotossdan se hoe cit a e itane etra atado 95 Break DONT MENE PERE 073 N Id M MAL eda LE OK PU aie 95 preak pontada er Em 95 preakpoint ada Mad EE 96 Drs akpolnt add Wate ase tind dl iii ta 96 Dre ar DOIN delle moisen e E tai 96 A A 96 ee A O 97 o O ae Me eo eee eee ene ee ee 97 CAMO A o weasosaeousnconctes E 97 e lfeHriofc MU 97 GANG GIN generc cH cC r 97 Cd CODY ee DL Ct 98 Card o cm rp e 98 t il 98 e o P 98 AN 98 BOO ONY A q ea chadeqocln sacceteananscen nace S S 98 BEDI OM CODY mcr mer 99 PEED User s manual 8 WWW ronetix at Contents A me CeO a ence 99 eeprom delel EE T Tt TO e 99 isset ETE 99 CODO TON Aen ere 99
51. AG operations that are needed to provide the specific service It can control the operation of the target processor and target system start and stop the processor s execution it can set breakpoints in a program examine and store values in the processor s registers and examine and store program code or data in the target system s memory PEEDI can work in cooperation with a host computer or autonomously using MMC SD card 1 1 PEEDI in the development process In the development process PEEDI can be used mainly as a debugger JTAG interface and FLASH programmer Two major configurations are possible here 1 1 1 Single developer environment Using the developer s PC as a host computer this is suitable for small projects Here all necessary tools for compiling and debugging the project must be installed on the developers PC including file server TFTP FTP or HTTP allowing PEEDI to retrieve configuration files or executable images In this configuration the developers PC must be connected to PEEDI in a common LAN using crossover patch cable or via Ethernet hub switch A simple configuration Ethernet Linux host or Windows Cygwin arm elf gcc arm elf Id arm elf insight Ethernet PEEDI User s manual 10 www ronetix at Introduction 1 1 2 Multiple developers environment Dedicated server with all the necessary development tools installed is used for a host The developer uses his PC only as a graphical terminal to logo
52. ASH chip Argument YES NO ACCESS METHOD PEEDI User s manual 38 www ronetix at Using PEEDI Description Flash programming method If AGENT is specified the FLASH programmer will return an error if the agent failed to start if AUTO is specified the programmer will try to start the agent if failed it will perform direct programming If DIRECT is specified the programmer will perform direct programming Note Programming using agent is many times faster than programming directly To enable agent usage set COREn WORKSPACE parameter in the PLATFORM section of the target configuration file Argument AUTO AGENT DIRECT CHIP WIDTH Description Chip width some FLASH chips support several widths Argument 8 16 32 CHIP COUNT Description Number of FLASH chips Argument 1 2 4 BASE ADDR Description Start address of FLASH Argument First valid FLASH address FILE Description This parameter defines the default flash multi program command s arguments This parameter may have two or three arguments The first argument is the file to be programmed The second argument is the file type BIN SREC IHEX or ELF The third argument is mandatory for binary files and optional for all other types of files it is the address where the file should be loaded Argument FILE NAME FILE FORMAT FILE ADDRESS AUTO ERASE Description Do or do not erase affected FLASH sectors before program operation for more information see f
53. ASH region LENGTH length of FLASH region default is 1 if not supplied Example flash blank 0x400000 0x1000 flash erase Syntax flash erase ADDRESS LENGTH flash erase chip Description Erase all FLASH sectors that belong or overlap to the specified region If no arguments are provided last used will be taken Default first used region is whole FLASH flash erase chip erase using the CHIP ERASE command if supported from the flash device Arguments ADDRESS beginning of FLASH region LENGTH length of FLASH region in bytes default is 1 if not supplied Example flash erase 0x400000 0x1000 flash erase chip flash lock Syntax flash lock ADDRESS LENGTH Description If supported by FLASH lock protect against write erase all FLASH sectors that belong or overlap to the specified region If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments ADDRESS beginning of FLASH region LENGTH length of FLASH region default is 1 if not supplied Example flash lock 0x400000 0x1000 flash unlock Syntax flash unlock ADDRESS LENGTH Description If supported by FLASH unlock unprotect against write erase all FLASH sectors that belong or overlap to the specified region If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments ADDRESS beginning of FLASH region LENGTH length of FLASH region de
54. AY BRIGHTNESS 20 VOLUME 51 Section ACTIONS Declares what scripts can be executed using front panel buttons each declaration must be on a new line The declaration consists of a number associated with the specified script name A section with the same name must exist somewhere in the target configuration file If AUTORUN N parameter is specified where N is number of a script the given script will be executed every time a target is connected to PEEDI For more information see Script execution using the front panel interface Example ACTIONS AUTORUN 2 1 erase program verify 2 prog http erase program verify PEEDI User s manual 47 WWW ronetix at Using PEEDI flash prog tftp 192 168 1 41 main romram bin bin 0x400000 flash verify tftp 192 168 1 41 main romram bin bin 0x400000 prog http flash prog http 192 168 1 41 main_romram bin bin 0x400000 erase PEEDI User s manual 48 WWW ronetix at Using PEEDI 3 4 CPU specific considerations WARNING A The following may be extremely important for your target so read it very carefully 3 4 1 Atmel AT91SAM7 family The Atmel AT91SAM7 family devices need a special FLASH section in the target configuration file for more info rmation see Section FLASH and Appendix A Sample target configuration files 3 4 2 Atmel AVR32UC family The Atmel AVR32UC family devices need a special FLASH section in the target configuration file for more info rmation see Section FLASH
55. B 0x400 boundary 3 Must not overlap user application code COREn_VECTOR_UNDEF COREn_VECTOR_SWI COREn_VECTOR_PABORT COREn VECTOR DABORT COREn VECTOR RES COREn_VECTOR_IRQ COREn VECTOR FIQ COREn RELOCATED UNDEF COREn RELOCATED SWI COREn RELOCATED PABORT COREn RELOCATED DABORT COREn RELOCATED RES COREn RELOCATED IRGQ COREn RELOCATED FIQ Description Because of the XScale debugging specifics PEEDI must be aware of the exception vectors Each of these parameters must have value of AUTO or an exact value which represents a hex encoded ARM instruction In case of AUTO is specified PEEDI will read the original vector value from the target memory on each debug event halt step go etc Or you can put a constant value if you exactly know the vector s instruction for example OxE59ff018 stands for Idr pc pc 18 instruction Argument AUTO or a hex encoded ARM instruction For example of this section see the example configuration files in the appendix of this document section PLATFORM MPC5500 This section describes the MPC55XX cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT PEEDI User s manual 27 WWW ronetix at Using PEEDI COREn LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE MPC5500 and a TAP number separated by comma COREn NEX
56. EED User s manual 99 www ronetix at Using PEEDI Example eeprom format eeprom alias Syntax eeprom alias ALIAS MEANING Description List or un define an alias Arguments ALIAS alias to be un defined MEANING alias meaning to be defined Example eeprom alias eeprom alias cl card dir eeprom alias cl 3 14 3 Using aliases Aliases are very helpful and time saving when frequently using long commands with many arguments For example we can define an alias named fp for peedi flash program tftp 192 168 1 1 dir image bin bin 0x100 and instead of writing the whole command with all its arguments we could only write peedi gt fp Characters tell the command processor that an alias is closed between the brackets Aliases are defined using eeprom alias command like this peedi gt eeprom alias fp flash program tftp 192 168 1 1 dir image bin bin 0x100 Next time fp is met all defined aliases will be searched for fp and the string will be interpreted as the defined meaning of the alias To un define an alias you can peedi gt eeprom alias fp You could use an alias with combination of an argument like this peedi gt fp erase Or define an argument or part of it as an alias peedi gt eeprom alias myserver 192 168 1 1 and use it like this peedi gt flash program tftp myserver mydir myimage bin bin 0x100 or peedi gt eeprom alias myfile tftp 192 168
57. EPROM Power Up a Target Assen Target RST and wait RESET TIME COREN STARTUP MODE RESET na Wait WAKELP TIME Sel initial JTAG CLOCK read CPU ID and check EmbeddediCe logic COREn STARTUP MODE RUN Reena po vases STOP piod Stop Target CPU and read all Registers Process Target INIT section if existe E Set normal JTAG CLOCK second parameter of JTAG CLOCK Process GDB CLI requests PEEDI User s manual 57 WWW ronetix at Using PEEDI 3 6 Multiple core support The multiple core extra license is required support allows you to debug program up to 4 independent targets using only single PEEDI The targets must be chained using the multiple core cable adapter available from Ronetix 4x ARM20 Adapter AAA WARNING All targets must have equal power supply 10 tolerance is permissible The A highest power supply is taken for reference for the PEEDI output schematic so the JTAG signals will have that value WARNING You must use as short as possible cables because the equivalent cable length is the sum of all cables Even then you may need to decrease the JTAG clock in the target configuration file The JTAG CHAIN parameter in the PLATFORM ARM section must be correctly set and each core must be described Example PLATFORM ARM section describing two chained cores PLATFORM ARM JTAG CHAIN 4 4 list of IR
58. FLASH using specific file type in a given format to an exact address issue peedi gt flash program tftp 192 168 1 1 mydir myimage bin bin 0x100 The address to program the image at must be aligned to the FLASH access width i e if the FLASH is 16 bits 2 bytes accessible the address must be aligned by 2 If the FLASH is an Intel Strata the alignment must be 32 bytes If the internal FLASH of an Atmel AT91SAM7 series microcontroller is programmed the alignment must be equal to the FLASH page size 128 or 256 bytes If the internal FLASH of a Philips LPC2000 series microcontroller is programmed the alignment must 256 bytes After the flash is programmed you can verify it by peedi gt flash verify or peedi gt flash verify tftp 192 168 1 1 mydir myimage bin bin 0x100 Note Most of the flash commands if executed without arguments will take the last used o arguments If executed for first time they will take their default arguments For more information on how to use the FLASH programmer please see the flash CLI commands 3 16 Multiple FLASH support The PEEDI FLASH programmer supports targets with multiple FLASH chips mapped at different addresses Every FLASH must be described in separate section in the target configuration file If multiple FLASH chips configurations are present on the target each chip configurations must be described in different section see section PLATFORM ARM If single FLASH chip configuration is used th
59. Host PEEDI Hub Switch SS Patch cable Patch cable amp 2 Connect the PEEDI interface unit to the target hardware using the supplied JTAG adapter and cable The JTAG adapter must be on the PEEDI side of the JTAG cable If your target JTAG port pinout is not standard you may need to make your own target cable considering the PEEDI JTAG connector pinout Host PEEDI Target Crossover cable JTAG cable Y Power up the target hardware Connect the external power supply to the PEEDI and to the power outlet When PEEDI boots if you have a terminal connected to the RS232 port of PEEDI you will see some status messages dd PEEDI User s manual 15 www ronetix at Using PEEDI 2 2 Software installation See Cross development with GNU toolchain and Eclipse http www ronetix at software html PEEDI User s manual 16 www ronetix at Using PEEDI 3 Using PEEDI This chapter will explain PEEDI s operating modes PEEDI s interface and the basic steps of configuring the software tools for working with PEEDI To start using PEEDI you need to configure network settings make target configuration file 3 1 PEEDI interface TARGET PWR TPW ETH STAT bh Power LED Target power LED Ethernet connect activity LED Target connect activity LED Script number status LED display Next script button Start script button Target connector MMC SD card slot RS232 port c O N O C A C N _L
60. I needs some licenses to operate Each license unlocks specific feature of PEEDI Licenses are kept in and loaded from the LICENSE section of the target configuration file So you must fill there the licenses you have acquired before you start using PEEDI The minimum required licenses are provided PEEDI User s manual 103 www ronetix at Using PEEDI when PEEDI is purchased and are printed on the bottom side of PEEDI Also new purchased PEEDI is set to load the target configuration file from the EEPROM where we have put the file and the licenses The UPDATE DDMMMYYYY license allows you to update PEEDI firmware to version signed to DDMMMYY Y Y date This is the date when your firmware warranty expires see chapter Warranty If you update your PEEDI with firmware released after that date your PEEDI will refuse to work You can recover from this situation either loading older firmware or acquire a new update license so please contact Ronetix if the UPDATE license has expired and you need to update PEEDI firmware To give you a license we need to know your PEEDI serial number which is sent over the RS232 port when PEEDI boots or printed when you connect to PEEDI telnet CLI The PEEDI serial number should look like this SN PD 1234 5678 90AB After we receive it we will send you the license which should look like this KEY DESCRIPTION 1234 5678 90AB C You have to insert that string in a new line in the LICENSE section of
61. In the panel right click on the ARM A RR item and next click Add Remove Edit devices to open the HDI target list Connection Control Administratsrvdebug brd E E B x Help Mame Description EHA ABM PR APM Ltd RDI targets pi M ARM instruction sel Collapse al ai ed Connection Broker Expand All localhost Simulator Broker Connection Properties Add Remove Edit Devices Select Board File 34 ki Connect f Synch f RDI Target List Use the check boses ta add or remove ADI targets from the connection manager Hame Version Description JR ARMulator ARM instruction set simulator Create New RDI Target xum a E X Enter a name and a description For the new entry in the connection list Short Mame example Dual TBMI Fiemote A dl Description example ulti EE with two SAM rE T C Program Files WAM ADIT argetstA emote 41 3 1595 E Lancel PEEDI User s manual 67 www ronetix at Using PEEDI Now select the new created item in the RDI Target List and click Configure RDI Target List DOO _ ox Use the check boses to add or remove ADI targets from the connection manager Hame Version Description G4 Remote 4 dll CA Program Filez amp RHM SRDISTargerssRHemote 551 3 1 385 MH ARMulator v1 4 ARM instruction set simulator Add DLL Reset list i Remove Duplicate Close In the dialog click Select and se
62. ORE CORE ADDRESS Zal 1 Description Step one instruction current or specified core s If no address is provided the core s will steps from its current PC value If no core is specified current core will be stepped If argument all is provided all cores will be stepped from their current PC values Arguments ADDRESS address to step from CORE core to be stepped all all cores will be stepped Example step step 0x100040 step 0 step 0 100040 step 0 100040 2 step Zall execute Syntax execute OPCODE Description Force CPU to execute specified instruction Supported in MPC5500 targets only Arguments OPCODE opcode of instruction to be executed Example execute 0x7C0007A4 set Syntax set coprocessor spr ctrl REGISTER VALUE PEEDI User s manual 80 www ronetix at Using PEEDI halt reset reboot Description Set target CPU register For more information about cp15 see info cp15 command Arguments REGISTER name of register to set VALUE value to set Example set r0 0x12345678 set general purpose register set ice8 0x12345678 set ICE register 8 r n set dfsr 0x12345678 ARM9 set CP15 instr Data FSR register using interpreted access set cp15 Ox51AF 0x123 ARM9 set CP15 instr TTB register using interpreted access bit12 1 set cp15 Ox000D 0x678 ARM9 set CP15 Process ID register using physical access bit12 0 set MASO 0x1234 PowerPC set spr register by name set spr 624 0x123
63. PEEDI Powerful Embedded Ethernet Debug Interface User Manual Version 1 37 SELECT TARGET pwr TPW AA i E E gTART w i ETH SU RONETOY embedded development tools Acknowledgements April 2010 Ronetix has made every attempt to ensure that the information in this document is accurate and complete However Ronetix assumes no responsibility for any errors omissions or for any consequences resulting from the use of the information included herein or the equipment it accompanies Ronetix reserves the right to make changes in its products and specifications at any time without notice Any software described in this document is furnished under a license or non disclosure agreement It is against the law to copy this software on magnetic tape disk or other medium for any purpose other than the licensee s personal use Ronetix Development Tools GmbH Waidhausenstrasse 13 5 1140 Vienna Austria Tel 43 720 500315 43 1 956 3138 Fax 43 1 8174 955 3464 Internet www ronetix at E Mail info ronetix at Acknowledgments ARM ARM7 ARMS ARM11 Cortex M3 Cortex A8 and Thumb are trademarks of ARM Ltd PowerPC and ColdFire are trademarks of Freescale Ltd Blackfin is trademark of Analog Devices Ltd Windows Win32 Windows CE are trademarks of Microsoft Corporation Ethernet is a trademark of XEROX MIPS32 is a trademark of MIPS Technologies AVR32 is a trademark of Atmel All other trademarks ar
64. R CATCH MASK COREn BREAK PATTERN COREn DCC PORT and CORHEn LOCKOUT RECOVERY About the CORE parameter COREn Description PEEDI User s manual 26 www ronetix at Using PEEDI Core declaration Argument Type of CORE OMAP3530 and a TAP number separated by comma For example of this section see the example configuration files in the appendix of this document oection PLATFORM XSCALE This section describes the XScale cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN and COREn LOCKOUT RECOVERY including some additional parameters COREn Description Core declaration Argument Type of CORE XScale and a TAP number separated by comma COREn USE FAST DOWNLOAD Description If YES is specified PEEDI will send data to the target without checking if the target is ready with the previous data assuming that the target writes the received data faster than PEEDI is sending it This type of transfer is faster bun less reliable Use it only if you are sure that the target is fast enough i e the CPU is running on high frequency Argument YES NO COREn DEBUG HANDLER ADDR Description The address where the XScale debug handler should be mapped at Argument Choosing address has three limitations 1 Due to the limitation of the ARM branch instruction the address must be within these ranges 0x00000000 0x01FFFC00 or 0xFE000000 OxFFFFFCOO 2 Must be aligned to a 1K
65. RST 3 TRST 3 4 4 4 4 4 1 P 5 ot TD m TDiin 5 TDlin 5 TDiin 5 TDiin 5 6 6 6 6 6 Iz 7 7 7 7 ot TM Ten IMS TVS aS 8 8 8 8 8 1 e e e e e 9 NO TOKin 9 a TK 9 y TOK 9 a TK 9 10 1 10 10 10 2 E E 4x HEADER 2x10 11 in TO J6 11 J7 11 J8 11 Jo 11 1 1 1 1 12 e 12 12 12 12 13 NC 2 TDOout 13 2 TDOout 13 2 TDOout 13 2 TDOout 13 e 14 14 14 14 14 15 NO RSTin 15 RET 15 AST 15 AST 15 16 16 16 16 16 17 NC 17 17 17 17 18 18 18 18 18 19 ot RST 19 19 19 19 20 bdr RST e e 20 qe f Ct e PMR 10 0 6V Ut r DA 1 n IND ad FAN epu 2 IN m DAA E c zo LDA e q IN 10K o BN as DRVO 6 Ri DRVI eR Re INIS 9 PR2 a amp MED FTANAD GD a MER 3 6 8 a VEZ 2 17 e X VES T AAAS a 1K PWR PWR SP721ABalso possible Q Q 425 anande ce ca 7 1 8 100NF 100NF Title PEEDHAX ARVEO Module ADAPTER e WYNT Si OK zo Company FONETIX Aa Fev 1 0 ecd i EE Autor AONETIX 10 7 2006_1957 Sheet 1 of 1 PEEDI User s manual 109 www ronetix at ADAP Specifications TER PEEDI Freescale JTAG 14 http download ronetix info peedi doc schematics peedi nexus14 paf ADAPTER PEEDI FREESCALE JTAG 14 NEXUS PEEDI FREESCALE TARGET J1 1 in VFEF B 2 TO in 1 3 at TOK 2 4 TDOou 3 5 s TO 4 6 i Tak l 5 7 at
66. T DIRBSSCONFIB SIDat3TsamsB4 dd Than click Angel on the left to show the Angel connection options select TCP IP for communication and enter the IP address of your PEEDI Now click OK and you should be able to debug with PEEDI Options for node Basic Categor Factor Settings General Options C C Compiler Angel Assembler Communication Custom Build v Send heartbeat v TCPAP Build Actions E Linker C Se al A5232 Debugger Simulator ad 92 168 3 59 IAA ROM monitor J Lirik Serial pork settings Macraigar is Part com T Third Party Driver Baud rate 5600 Lag communication fTOOLEIT BIBST cspycamm lag PEEDI User s manual 73 WWW ronetix at Using PEEDI 3 12 Debugging Linux kernel To debug the kernel you bootloader must be set to load and start the kernel successfully In the target configuration file set the COREn STARTUP MODE to RESET and in the INIT section add this for all targets except Xscale break add hard 0x90000398 addr from nm vmlinux grep start kernel go Start CPU wait 30000 stop wait 30 seconds to enter debug break del all remove previously added watchpoint beep 500 20 beep to signalize ready for debug For Xscale targets use this break add watch Oxffff001C w 32 watch point on setting vectors go Start CPU wait 30000 stop wait 30 seconds to enter debug break del all remove previously added watchpoint beep 500 20 beep to signalize ready for
67. The serial interface gets its configuration parameters from this section These parameters are BAUD Description Baud rate Argument 1200 2400 4800 9600 19200 38400 57600 or 115200 STOP BITS Description Stop bits Argument 1 1 50r2 PARITY Description Parity Argument NONE EVEN ODD TCP PORT Description Port serial traffic to be routed to If set to 0 the PEEDI serial port is used for command line interface Argument 1024 65535 0 use PEEDI serial for command line interface Example SERIAL BAUD 115200 STOP_BITS 1 PARITY NONE TCP_PORT 2023 section TELNET PEED User s manual 46 WWW ronetix at Using PEEDI This section has only two parameters The first sets the new command prompt string after the configuration file is loaded The second parameter can be omitted it tells what ASCII code to be used for backspace action PROMPT Description This will change the default PEEDI telnet prompt Argument The prompt closed in quotation marks BACKSPACE Description Telnet backspace character ASCII code Argument The code Example TELNET PROMPT peedi BACKSPACE 127 Section DISPLAY These sections parameters specify the brightness of the seven segment LED indicator and the volume of the speaker both accept values in the range O 100 BRIGHTNESS Description Seven segment LED indicator brightness Argument 0 100 VOLUME Description Speaker volume Argument 0 100 Example DISPL
68. USS3 ACCESS Description This parameter accepts NO or memory region start address and length in bytes If a memory region is supplied usually this is the RAM of the target PEEDI will access target memory region using the nexus3 module This method is about three times faster but it uses physical addresses i e bypasses the MMU You can properly use this method if the MMU is set to be transparent i e virtual addresses are equal to physical ones Argument NO START ADDRESS LENGTH COREn SMALL REGS FRAME Description From GDB version 6 8 the MPC5500 registers frame has changed Now latest GDB versions use smaller register frame For PEEDI to be compatible to the new format set this parameter to YES If you want it to be compatible to the old GB versions set it to NO Argument YES NO For example of this section see the example configuration files in the appendix of this document section PLATFORM MPC8300 This section describes the MPC83XX cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT COREn LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE MPC8313 MPC8321 MPC8323 MPC8343 MPC8349 and a TAP number separated by comma COREn BOOT ADDR Description Normally the boot address for PowerPC is OxFFF00100 or 0x00000100 depending on the Reset Configuratio
69. acceptable values for the BASE ADDR parameter in the FLASH section 0x00000000 STR71x and STR73x 0x40000000 STR71x 0x80000000 STR73x If the SECURE FLASH target configuration parameter is set to YES The first time the device is secured by programming the DBGP bit of the NVAPRO register Each time after the device is secured programming the next un programmed bit PEN bit of the NVAPR1 register Keep in mind that once secured the device may be temporary or permanently unsecured only by the code that is programmed in the FLASH so avoid securing the device if the code inside it can not unlock it because the devise may become unusable The device can be permanently secured unsecured only sixteen times because after that all NVAPR1 bits are programmed 3 4 6 ST STRO family The ST STR9 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files You can program the FLASH configuration and security using this PEEDI raw JTAG commands manually or put in a script ISC ENABLE jtag pui 17 lsb Ox1FFOC idle IR ISC ENABLE jtag rd 10 lsb Ox3FF ilde DR 2 bypass 8 dont care bits prog config jtag ri 17 lsb Ox1FF11 idle IR jtag rd 10 lsb 0x50 ilde jtag ri 17 lsb Ox1FF20 idle jtag rd 32 lsb 0x00000000 stop jtag 0 32 lsb 0x00000000 stop jtag 0 2 lsb 0x3 idle wait 1000 ISC ADDRESS SHIFT Configuration re
70. ad 17 sh OxF89040 s data OxFA1004 s bss OxFA40B4 0x00f6918c in O thread 16 telnetd OxFACO40 s data OxFA8004 s bss OxFA9984 Ox00f6918c in thread 15 inetd OxFB8040 s data OxFD9004 s bss OxFDA544 Ox00f6918c in O thread 7 mtdblockd Ox00f6918c in O thread 6 kupdated 0x00f6918c in O thread 5 bdflush 0x00f6918c in O thread 4 kswapd Ox00f6918c in O thread 3 ksoftirqd cPUO 0x00f6918c in O thread 2 keventd 0x00f6918c in O thread 1 init OxFF0040 s data OxFC4004 s bss OxFC4F44 0Ox00f6918c in O peedi add symbol file spar gdb OxF64040 s data OxF4A004 s bss 0xF53104 add symbol table from file spar gdb at text addr Oxf64040 data addr Oxf4a004 bss_addr 0xf53104 e N U A UIO NOO O y or n y Reading symbols from home user spar spar gdb done PEEDI User s manual 75 WWW ronetix at Using PEEDI 3 14 Working with CLI Command Line Interface PEEDI CLI allows you to e Perform simple debugging You can load executable image into target RAM get or set target memory or registers put break and watch points start step or stop the target For more information see the description of core go breakpoint step halt reset info memory commands e Program target flash Full functional FLASH programmer is available capable of programming different image file formats For more information see the description of flash command e Manage files from vari
71. ample of this section see the example configuration files in the appendix of this document section PLATFORM MIPS32 This section describes the MIPS32 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT and COREn LOCKOUT RECOVERY About the CORE parameter COREn Description Core declaration Argument Type of CORE MIPS32 or PIC32 and a TAP number separated by comma For example of this section see the example configuration files in the appendix of this document Section PLATFORM AVR32 This section describes the AVR32 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the CORHEn BREAK PATTERN COREn DCC PORT and COREn VECTOR CATCH MASK About the CORE parameter COREn Description Core declaration Argument Type of CORE AVR32AP7 or AVR32UC3 and a TAP number separated by comma COREn BLOCK ACCESS Description This parameter accepts NO or memory region start address and length in bytes If a memory region is supplied usually this is the RAM of the target PEEDI will access target memory region using the MEMORY WORD ACCESS TAP command Argument NO START ADDRESS LENGTH For example of this section see the example configuration files in the appendix of this document Section INIT This is the section specified by COREn INIT parameter It includes commands which are executed once after every targ
72. artbeat W Enabled Disabling heartbeat will disable hast timeout and packet resend T Endian Lite Big There is no need to specify the endianness of Angel targets LIF Cancel Help PEED User s manual 65 www ronetix at Using PEEDI After that click OK on the Choose target dialog and the debugger should connect to PEEDI Choose Target E Al x Target Environments ADP 0000 R1 STET te Adi j ARMUL 151 CA ABin BMmulate dl pem Save As Configure Connect the SAM Debugger directly to a target board or to an EmbeddedlCE unit attached to a target board Directly connected target boards require Angel debug monitor software Conforms to RDI 1 51 Cancel Help At this point you should be able to debug your project 3 11 2 ARM RealView Developer Suite RVDS v2 2 RealView debugger Click Target gt Connect to target to open the Connection Control panel Fe RYDEBUG Unattached File Edit View Target Project Build Debug Tools Help 4 Li E MH Connect to Target Alt n gi 4 File sn O SOURCE Disconnect Defining Mode hae E ED Disconnect CrH AlE4 ot connecte Click to Caonne Connection Properties Alt ShiFE 0 Attach Window Ea a Connection Connections b le Load Image CEras Shift o ik Reload Image to Target Cbrl F5 Refresh Symbols Recent Images k PEEDI User s manual 66 www ronetix at Using PEEDI
73. ave built in support for automatic update of the pointers so no user setup is required only the COREn MMU PTBASE must be set to OxFO where the kernel puts the pointer to the array But this feature must be enabled in order to be used make menuconfig kernel hacking Include BDI 2000 user context switcher here you can also set the Compile the kernel with debug info option Sometimes gdb and insight do not want to load the debug info because of an internal bug in this case adding gstabs option in the makefile fixes this WARNING On some cores MPC8349 in order the software breakpoints to work the A interrupt vectors must reside in valid memory So you must either initialize the memory properly or either set the MSR IP to a value so the vectors fall on a valid memory When the COREn RCW CFG parameter is present PEEDI overrides the Reset Configuration Words with the values provided This is useful when the RCW that is fetched during board reset does not suit the user s needs when debugging or programming the board using PEEDI The COREn BOOT ADDR CFG must be set considering the RCW that is fetched set because RCW sets the reset vector address the boot address If PEEDI reports info target does not enter debug mode forcing halt this might mean that the CPU boots from an address different than the one set by the COREn BOOT ADDR parameter So you should check again both COREn_ RCW and COREn BOOT ADDR parameters
74. ber is used to build the appropriate MCR MRC instruction CRm Specified Coprocessor Action Determines specific coprocessor action Its value is dependent on the CP15 register used For details refer to CP15 specific register behavior CRn Determines the destination coprocessor register opc_1 Defines the coprocessor specific code Value is c15 for CP15 opc_2 Determines specific coprocessor operation code By default set to 0 ARM926 Physical access mapping to CP15 registers 13 11 10 8 7 4 3 0 Opc 2 ARM94x Physical access mapping to CP15 registers HOM x Cn i PEEDI User s manual 84 WWW ronetix at Using PEEDI The bit i selects the instruction cache scan chain bit 32 The bit x extends access to register 6 scan chain bit 37 Example info cp15 Show all CP15 registers info cp15 Ox51AF ATM920 show inst TTB register using interpreted access bit12 1 info cp15 0x0109 ARM920 show inst cache lockdown register using physical access b1t12 0 info cp15 ittb info spr Syntax info spr NAME NUMBER ZCORE Zal1l Description List current SPR registers values PowerPC targets only Example info spr info spr PID info spr 48 info ctrl Syntax info ctrl NAME ADDRESS Description List current control registers values ColdFire targets only Example info ctrl info ctrl RAMBAR info ctrl 0xc05 info breakpoint Syntax info breakpoint CORE Description List all s
75. chapter CPU specific considerations Added Appendix A Sample Target Configuration Files Updated chapter FAQ November 2005 Added Angel Debug Protocol usage explanation The chapter Software Installation moved to the Software Installation Guide September 2005 Updated Boot sequence Added multiple core explanation Added multiple flash explanation Added flash set command Added flash lock command Added flash unlock command Added flash query command Removed flash write command Added Atmel AT91SAM7 series microcontroller support August 2005 Added parameter STARTUP_MODE in section PLATFORM_ARM Added Boot sequence Complemented firmware update procedure July 2005 PEEDI User s manual 5 www ronetix at Contents 1 INTRODUCTION P M 10 1 1 PEEDI in the development process necesse eee eeeee een nenne nnn nnne nnn nnns 10 1 1 1 Single developer CNViIrONMEN ccecccccccsesseeceececeesseceeceeeaeseeeeesseaseeeeeesauasseeeeesaaagaes 10 1 1 2 Multiple developers environment cccccsseeeceeceeeceeeeeeeeeeeeaeeueeeeecsaeaseeeeeesanasseeeeesanaaees 11 1 2 PEEDI in the manufacturing process eese eeeeee e eeee enne een nennen nnn 12 1 2 1 PEEDI as a standalone FLASH programme c cccceccecesseeeeeeeceeseeeeeeesaaeeseeeeesaaenees 12 122 IPEEDI AS a device tester accs
76. clear Atmel AT91SAM7 general purpose NVM bit Arguments BIT bit number VALUE O to clear or 1 to set the specified bit Example flash this nvmbit 2 O flash this nvmbit 2 1 flash this secure Syntax flash this secure Description Secure AT91SAM7 CPU Arguments None Example flash this secure flash this option Syntax flash this option erase flash this option BYTE VALUE Description Manage ST STM32 CPU option bytes Arguments BYTE byte number 0 7 VALUE value to be written to the option byte Example flash this option erase flash this option O OxA5 breakpoint Syntax breakpoint SUBCOMMAND Description Manage target break and watch points Subcommand must be provided Arguments SUBCOMMAND subcommand specifying the operation Example breakpoint list breakpoint add Syntax breakpoint add ADDRESS Description Set software break point Unlimited number of software break points can be set If address 1 or OXFFFFFFFF is specified only the ARM ICE registers will be set for software breakpoints but not actual breakpoint will be set In this case the CPU will break enter debug if the breakpoint pattern is met anywhere during the code execution Suitable to embed breaks in the source of the debugged application Arguments PEEDI User s manual 95 WWW ronetix at Using PEEDI ADDRESS address of the break Example breakpoint add 0x400040 breakpoint add 1 breakpoint add hard Syntax breakpoin
77. debug This will set a break watch in the beginning of the Linux kernel code and will start the kernel This way after target is powered the kernel will be started and a little later it will enter debug At this point you can start gdb insight pointing the kernel ELF image file Next you can use the target command to connect to PEEDI Make a si just for the gdb insight to refresh its source window Now you can set remove breakpoints in you source code step by step examine the execution or issue continue to start the kernel after you have set all the breakpoints you desire If a break point is hit gdb insight will highlight the source line where the execution has stopped 3 13 Target OS tasks awareness and debugging uClinux applications PEEDI provides target OS tasks awareness i e when debugging the info threads gdb command or Insights View gt Thread List will list you all the OS tasks processes threads But before using info threads you must first set in the target configuration file a section that tells PEEDI how to find the tasks This section includes addresses and offsets you need to fill in order for PEEDI to be able to scan the OS task list First add a COREn OS CFG parameter and set is to point to the OS section like this CORE OS OS ARM LINUX v26 section which contains the OS parameters For Linux the section should look like this OS ARM LINUX v26 BASE 4 OxCO2FF068 address of init task structure NEXT 4 OxB4 P
78. dir card cd Syntax card cd DIRECTORY Description Change current directory Arguments DIRECTORY directory to make current Example card cd mydir card md Syntax card md DIRECTORY Description Make new directory Arguments DIRECTORY name of the directory to be made Example card md mynewdir card rd Syntax card rd DIRECTORY Description Remove directory The directory must be empty Arguments DIRECTORY directory to be removed Example card rd mydir card dir Syntax card dir SEARCHCRITERIA DIRECTORY Description Displays a list of files and subdirectories in a directory Arguments SEARCHCRITERIA string to filter printed output DIRECTORY directory which content to be listed Example card dir card dir bin card dir mydir PEED User s manual 97 www ronetix at Using PEEDI card copy Syntax card copy SOURCE DESTINATION Description Copy file Arguments SOURCE the source file to be copied DESTINATION file to be saved Example card copy image bin mydir backup bin card type Syntax card type FILE Description Show content of text file Arguments FILE text file to be shown Example card type target cfg card delete Syntax card delete FILE Description Delete file Arguments FILE file to be deleted Example card delete target cfg card rename Syntax card rename FILE NEWNAME Description Rename file Arguments FILE file to be renamed
79. dow Cgdb target remote 192 168 1 10 2000 This will tell GDB to connect to PEEDI using remote protocol Now you can load your application into targets memory like this Cgdb load And your application is ready for debugging Cgdb continue start the application Or Cgdb si make single step PEEDI User s manual 117 www ronetix at FAQ Q What is Eclipse A The Eclipse IDE is a complete integrated development platform similar to Microsoft s Visual Studio Originally developed by IBM it has been donated to the Open Source community and is now a massive world wide Open Source development project Q What is Cygwin A Cygwin is a free Linux like environment for Windows It works on all Windows 32 bit OS versions since Windows 95 except Windows CE Cygwin is not a way to run native Linux apps on Windows Applications must be rebuilt from source code to get it running on Windows Q What is Cygwin X A Cygwin X is a port of the X Window System to the Microsoft Windows family of operating systems Cygwin X runs on all recent consumer and business versions of Windows as of 2003 12 27 those versions are specifically Windows 95 Windows 98 Windows Me Windows NT 4 0 Windows 2000 Windows XP and Windows Server 2003 For more information see http x cygwin com Q What are GNU cross development tools A Atoolchain is a collection of software tools used for the development and building of software for a particular target archit
80. dy with the choice press the red button to start the script While the script is being executed the LED indicator will rotate its segments to show that the execution is in progress When the script is successfully completed the led indicator will show the chosen script and the speaker will produce a single beep notifying the end of operation If an error occurs during execution some of the commands exited with error code the execution is terminated the LED indicator will start to blink with the error code and the speaker will beep a number of times equal to the error code Then you can start the script again by pressing the red button If you press the green button the display will show the current script pressing it again will show the next available script so you can chose another script to execute Here are the available error codes 1 TIMEOUT 2 NOT FOUND 3 INVALID ARGUMENT 4 GENERIC ERROR More information about the error can be obtained by connecting to PEEDI using telnet and then restarting the script Status messages are output to every opened telnet connection when a script is executed The scripts are defined in the following manner in the ACTIONS section list all scripts that you want to define in this format N script_name where N a hex number 1 9 and A F and is associated with the script_name then define section named script name and put any number of commands each command must be on a new line These scripts are us
81. e flash this option BYTE VALUE An option byte can be written only once after it is erased If you want to change the value of previously written byte you must erase it this will erase all other option values so you may need to set them again You can see current option bytes using memory read16 Ox1FFFF800 8 Use the following commands in the target INIT script to enable SWO stimulus output init SWO mem write OxE0042004 0x20 enable async trace mem write OxE0040010 1 SWO prescaler 1 mem write OxEO0400F0 1 enable Manchester encoding mem write 0xE0040304 O0 bypass formatter mem write OxEOOO00FBO OXC5ACCE55 unlock access to ITM registers mem write OxE0000E80 0x10009 trace ID 1 ITM enabled mem write OxE0000E40 OxF enable all tracing ports mem write OxE0000E00 OXFFFFFFFF enable all stimulus ports PEEDI supports only Manchester SWO encoding up to 66MHz PEEDI checks for new incoming telnet connection only when the target CPU is halted If the SWO functionality seems unstable lower the CPU clock or increase the SWO prescaler both of these will result in lower SWO clock 3 4 8 TI TMS470 family The TI TMS470 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files TMS470 devices use four WORD long keys to protect FLASH from unwanted erase write operations so be careful not to write them accide
82. e m integer number may be skipped When working with the programmer the first FLASH is selected as current by default To work on another FLASH use the flash set command to select it The multiple FLASH support could also be used to describe different profiles for the same FLASH for example with different program method type or different image file specified This way you can easy switch to the desired profile using the flash set command 3 17 Working with a MMC SD memory card As mentioned before PEEDI can operate autonomously i e without an Ethernet and a host computer This is achieved by storing all necessary files target configuration image script and other files into a MMC or SD memory card WARNING If PEEDI is set to get its network settings from a DHCP server and if the Ethernet A cable is unplugged or there is no DHCP server on the Ethernet it may take some minutes for PEEDI to boot To avoid this make sure PEEDI can reach a DHCP server or set it to use a static IP address PEED User s manual 102 WWW ronetix at Using PEEDI PEEDI can not format a MMC SD card The card must be FAT file system formatted in order to use it with PEEDI There are two ways to copy the necessary files to the memory card First is to use a MMC SD card reader and a PC to copy the files The second way when no card reader is available is to copy the needed files using the PEEDI CLI transfer command for this purpose you will also need a FTP
83. e among TFTP FTP HTTP MMC SD and EEPROM Arguments SOURCE the source file to be copied DESTINATION where the file to be saved Example transfer card dump bin tftp 192 168 1 1 dump bin copy file from the mmc sd card to a TFTP server transfer dump bin ftp user pass 192 168 1 1 dump bin copy file from the EEPROM card to a FTP server transfer http 192 168 1 1 dump bin tftp 192 168 1 1 dump copy file from a HTTP server to a TFTP server type Syntax type FILE Description Show content of text file Arguments FILE text file to be shown Example type ftp myuser mypass0192 168 1 1 target cfg wait Syntax wait MILISECONDS stop PEED User s manual 78 WWW ronetix at Using PEEDI core clock adp run Description Wait specified time period or wait target to stop with a given timeout Useful when target needs some delay while executing commands in INIT section of the target configuration or script file Arguments MILISECONDS period to be waited in milliseconds Actual resolution is 10 ms Example wait 1000 wait 5000 stop Syntax core CORE Description Show set current core Arguments CORE core number of desired core to be current Example core core 1 Syntax clock init normal kHz Description Switch JTAG BDM target clock init normal or any desired frequency This is useful when the INIT section is too long and takes too much time Using this command you can init
84. e is no DHCP server on the Ethernet it may take some time for PEEDI to boot To avoid this make sure PEEDI can reach a DHCP server Use DHCP for network configuration yes no ENTER Gateway IP address X X X X Local IP address X X X X Local IP address mask X X X X Default server IP address used by RedBoot and PEEDI X X X X Note o Instead of Xs enter IP address digits Next you will be asked for the path of the configuration file Target config file path Accepted paths for the different protocols are tftp server sub directory filename cfg ftp user passwordQ server sub directory filename cfg http server sub directory filename cfg card sub_directory fi lename cfg Note A server is indicated by its IP address Now you may enter DNS server used by RedBoot to resolve hostnames DNS server IP address If left blank and PEEDI is set to get the network configuration from DHCP server the DNS server IP will also be taken from the DHCP Next you will be prompted for the RedBoot telnet port RedBoot telnet port 23 Finally you may enter the update command default file path Update filepath lt l gt http ww ronetix at download firmware fw_peedi_revA_last bin PEEDI User s manual 18 WWW ronetix at Using PEEDI 2 tftp 192 168 3 1 fw peedi rev A last bin custom path Path 1 If you have changed some of the parameters you will be ask to save them at the end If you confirm to save them they
85. e pointer to the two page pointers array For example of this section see the example configuration files in the appendix of this document Section PLATFORM PPC400 This section describes the PPC400 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT COREn LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE PPC405 and a TAP number separated by comma For example of this section see the example configuration files in the appendix of this document Section PLATFORM COLDFIRE This section describes the ColdFire cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the JTAG CHAIN JTAG CLOCK TRST TYPE CORE ENDIAN CORE BREAK PATTERN CORE DCC PORT CORE LOCKOUT RECOVERY and CORE VECTOR CATCH MASK including some additional parameters BDM CLOCK Description BDM clock before and after initialization Argument Both clock values in kHz separated by comma MAX BDM clock is 33MHz See your ColdFire CPU user s manual for correct BDM clock Use ADAPTIVE n to set the BDM clock to PSTCLK n CORE Description Core declaration Argument Type of CORE MCF5200 MCF5206 MCF5272 MCF5300 MCF5400 CORE MEMMAP Description Defines a valid memory region Up to 32 regions can be defined in the target configuration file When eve
86. e trademarks of their respective companies 2005 2010 RONETIX GmbH All rights reserved PEED User s manual 2 WWW ronetix at Change log Change log April 2010 Added MPC8500 support Added PPC405 support Added PXA320 NAND FLASH support December 2009 Added target command Added STM32 agent FLASH programming Added Freescale iMX51 NAND FLASH support Added BAD BLOCK TABLE NAND FLASH CFG parameter Added SWAP BI NAND FLASH CFG parameter Added option to use file path in the BASE parameter of OS section Added Cortex M3 SWO Stimulus Trace Ports support Added target OS tasks awareness Corrected Debugging Linux Kernel chapter June 2009 Added MPC5200 debug and FLASH support Added AVR32 debug and FLASH support Added 32 bit DCC transfer for ARM targets Added STR9 FLASH secure unsecure support April 2009 Added reset detect command iudi Added LPC29XX FLASH support Added BASE ADDR parameter in ST STM32 FLASH section March 2009 Added MIPS32 support Added Cortex M3 SWD support Added PIC32 FLASH support December 2008 Added Cortex A8 support October 2008 Added Freescale iMX27 NAND FLASH support Added OneNAND FLASH support Added Luminary Micro FLASH support Added Freescale MPC8300 RCW explanation September 2008 Added COREn DATASPACE parameter Replaced COREn_WORKSPACE_ADDR and COREn WORKSPACE LEN parameters with single COREn_WORKSPACE parameter August 2008 Added unique serial numbe
87. ebugger uses to perform debug operations It receives command packets over the communication link and translates them into the JTAG operations that are needed to provide the specific service First it can control the operation of the target processor and target system What does it mean to control the target In most cases it means to start and stop the processor s execution of instructions at arbitrary points in a program examine and store values in the processor s registers and examine and store program code or data in the target system s memory Q What is debugging A Debugging is the process of removing bugs from computer programs On one end of the spectrum debugging means staring at your source code until you see the bug An infinitely more effective method is to use a special program called a debugger Q What is a debugger A A debugger is a program that runs other programs A debugger lets the user programmer stop running the program at any time and poke around internally You can examine and change memory contents call functions and look at system registers Besides all these fun things a debugger can be used to fix your programs Q How to set gdb to work with PEEDI A First compiled your application with the g OO option to enable debugging Next start gdb pointing your application arm elf insight myapp To connect to the target assuming that your PEEDI is set to use IP 192 168 1 10 type in the console win
88. ected to the first chip select of the CPU so physically accessible at 0x20000000 via 1MB window and its A19 A20 and A21 pins are connected to PF4 PF5 and PF8 CPU pins the configuration should look like this The 8MB FLASH is virtually mapped at 0x30000000 COREO VMEM 0x30000000 0x800000 It 1s physically visible through a 1MB window at 0x20000000 COREO VMEM WINDOW 0x20000000 0x100000 PF4 PF5 and PF8 are used to drive A19 A20 and A21 of the FLASH COREO VMEM ADDRESS PINS PF4 PF5 PF8 Now we can erase program and verify the whole 8MB of FLASH at address 0x30000000 using any PEEDI flash command Keep in mind that when defining FLASH section in the target configuration file you need to specify the virtual address of the FLASH for the BASE ADDR parameter PEEDI User s manual 31 www ronetix at Using PEEDI CORE MEMMAP Description Defines a valid memory region Up to 32 regions can be defined in the target configuration file When even one region is defined PEEDI begins to check every memory access operation if it falls into a defined memory region If the memory operation is out of the defined regions PEEDI interrupts the operation and issues an error This is made so because when an access is made to an invalid memory address via the JTAG the Blackfin CPU may stop to respond to any further memory operations until reset Argument Start and end addresses of the desired memory region separated by comma For ex
89. ecture The GNU toolkit consists of the following software utilities e GCC an ANSI C compiler G an ANSI tracking C compiler GDB source and assembly language command line debugger GAS GNU assembler LD GNU linker Insight a graphical user interface for GDB For more information see http www gnu org Q How to enter RedBoot command line A First restart PEEDI holding front panel buttons pressed this way RedBoot will not execute its boot script and the main PEEDI application will not be loaded Then you can access the command line via the RS232 port using suitable terminal application capable of opening the serial PC RS232 port or via telnet connecting to the port specified by the fconfig command Q How to update PEEDI firmware A See Firmware update procedure Q How to set target configuration file path A Enter RedBoot command line and use either fconfig or config commands Example config new target cfg file path Q How to set the network configuration of PEEDI A Enter RedBoot command line and use fconfig command Q Why PEEDI has a display and two buttons on the front panel A These are used to select start and observe the execution of user defined scripts which contain PEEDI commands Those scripts are defined in the target configuration file for more information see Using scripts Q How big image can PEEDI program A The image to program is not buffered to the PEEDI s RAM but it is downloaded f
90. efix The parameters that must be set are Global parameters for all ARM cores JTAG_CHAIN Description Length of IRs Instruction Registers of the devices on the JTAG chain All IRs must be enumerated the ones not supported by PEEDI must be skipped when defining COREn parameters see below Argument Enumerated all JTAG IR lengths separated by comma JTAG_CLOCK Description JTAG clock before and after initialization Argument Both clock values in kHz separated by comma MAX JTAG clock is 33MHz but 16 20MHz is recommended You ca use ADAPTIVE if the CPU supports adaptive clocking JTAG TDO DELAY Description Delay the sample of the TDO JTAG line For best performance different CPUs require different TDO sample delay When this parameter is not preset a 5ms value is set by default Argument 0 35 the delay in ns AUTO PEEDI tests the CPU and sets the optimum TDO delay TRST TYPE Description PEEDI User s manual 22 WWW ronetix at Using PEEDI Type of TRST output Argument OPENDRAIN or PUSHPULL RESET TIME Description If O is specified no reset will be issued this way PEEDI can be attached to already initialized and running target so INIT section could also be missing If the target executes code after reset even CORE STARTUP MODE RESET this means the TAP is not active during reset add a second argument time argument this will tell PEEDI to make a second reset pulse after which no code will be executed Argument
91. eful when using PEEDI in autonomous stand alone mode not connected to a PC In such mode PEEDI can be used as a stand alone FLASH programmer If all needed files are stored on a MMC SD card no Ethernet cable is necessary and PEEDI will need only power supply cable If AUTORUNEN parameter is specified where N is number of a script the given script will be executed PEEDI User s manual 59 www ronetix at Using PEEDI every time a target is connected to PEEDI This eliminates the need to manually start the script very useful and time saving when great volumes of targets are to be programmed Example ACTIONS AUTORUN 3 1 prog_tftp_dump 2 erase_program 3 prog_tftp 4 prog_card 6 dump_tftp 8 dump_card erase program flash erase 0x400000 0x600000 flash prog tftp 192 168 1 41 main romram bin bin 0x400000 prog tftp flash prog tftp 192 168 1 41 main romram bin bin 0x400000 erase prog tftp dump lash prog ee 192 168 1 41 dump bin bin 0x400000 erase pr T prog card flash prog card dump bin bin 0x400000 erase dump tftp memory dump 0x400000 0x100000 tftp 192 168 1 41 dump bin dump card memory dump 0x400000 0x100000 card dump bin 3 8 Serial Interface PEEDI s RS232 connector is routed to a predefined TCP port in the configuration file This way if a telnet connection is opened to that TCP port the telnet application will receive each byte coming in through the RS232 port Vice versa
92. et break and watch points of current or a specified core Arguments CORE core s break and watch points to be listed Example info breakpoint info breakpoint 1 memory Syntax memory SUBCOMMAND Description Manage target memory Subcommand must be provided Arguments SUBCOMMAND subcommand specifying the memory operation Example memory read memory read Syntax memory read TYPE ADDRESS COUNT PEEDI User s manual 85 WWW ronetix at Using PEEDI Description Read and show target memory contents If no arguments are provided last used will be taken ignoring ADDRESS and starting the listing with the next address to be listed after the previous execution of memory read Default first used arguments are 8 32 bit values at address 0x00000000 Arguments TYPE memory access 8 value is 8 bits byte long 16 value is 16 bits half word long 32 value is 32 bits word long 64 value is 64 bits double word long value is string ADDRESS where the value resides COUNT how many consecutive values to be listed if not provided count 1 is assumed Example memory read 0x1000 memory read8 0x1000 memory read16 0x1000 memory read32 0x1000 memory read64 0x1000 memory read 0x1000 memory read 0x1000 8 memory read memory write Syntax memory write TYPE ADDRESS VALUE COUNT Description Write target memory with specified value If no arguments are provided last used will be taken Arguments TYPE memor
93. et power detection and target reset The purpose of this section is to initialize the target map the memory init peripherals and so on Most of these are memory write commands Example PEEDI User s manual 32 WWW ronetix at Using PEEDI INIT EB55800 memory write OxFFFF4020 Ox004F0002 enable main clock wait 100 wait to stabilize memory write OxFFFF4020 0x004F4002 switch to main clock memory write OxFFFF4020 Ox3F006802 enable PLL wait 100 wait to lock memory write OxFFFF4020 0x3F008722 switch to PLL pres 4 mul 8 memory write OxFFEO0020 0x00000001 cancel reset remapping memory write OxFFEOO0000 0x010020A5 csrO Flash at 0x1000000 2 ws memory write OxFFE00004 0x02003029 csri RAM at 0x2000000 2 ws Sometimes it is impossible to initialize the target only by using the commands in the INIT section of the target configuration file In cases like this to perform the initialization an executable image can be loaded and executed in the target using the memory load and go commands Before loading the image the RAM where it will be loaded must be initialized Follow these steps to make a successful initialization Note e This is working INIT section for AT91M55800A CPU In this case the last instruction of the executable must be SWI informing that job has finished INIT EB55800 First init chip selects memory write OxFFEO0020 0x00000001 cancel reset remapping memory write OxFFEOO0000 0x010020A5
94. example if the port specified is 2000 and the core number is 2 starting from 0 then you should connect to PEEDI for a debug session at TCP port 2002 gdb target remote 192 168 1 10 2000 first target gdb target remote 192 168 1 10 2002 third target PEEDI User s manual 58 www ronetix at Using PEEDI Note The reset JTAG signal is common for all targets so if one developer resets his target all targets will get reset When opening a CLI telnet session the first core number 0 is selected as default core To select another core to work with use the core command Peedi core Z1 When debugging via the Angel debug protocol using the adp CLI command you can choose which core to connect to Peedi gt adp 1 Now of you connect to PEEDI using the ADP protocol you will debug core 1 Using the flash multi program and flash multi erase CLI commands you can program up to four targets at once saving huge amounts of time when many boards need to be programmed peedi gt flash multi erase 0 1 peedi flash multi program 0 1 tftp 192 168 1 1 myfile elf This will program targets 0 and 1 simultaneously 3 Script execution using the front panel interface You can define various command scripts in the configuration file and execute them using the front panel buttons Press the green button to choose the script you wish to execute the LED indicator will show the numbers associated with the available scripts when rea
95. family these are PEEDI User s manual 35 www ronetix at Using PEEDI TI TMS470 CHIP ACCESS METHOD BASE ADDR PROTECTION KEYO PROTECTION KEY1 PROTECTION KEY2 PROTECTION KEYS ALLOW ZERO KEYS FILE AUTO ERASE For Luminary LM3S family these are LM3S CHIP CPU_CLOCK ACCESS METHOD FILE AUTO ERASE For SPI FLASH or Atmel DataFlash family connected to an Atmel AT91 CPU these are SPI or AT45 CHIP CPU SPI DIV nSPl nCS SPI SPCK SPI MISO SPI MOSI SPI CS FILE AUTO ERASE For SPI FLASH or Atmel DataFlash family connected to a BlackFin CPU these are SPI or AT45 CHIP CPU SPI DIV SPI CS PEEDI User s manual 36 WWW ronetix at Using PEEDI FILE AUTO ERASE For SPI FLASH FLASH or Atmel DataFlash family connected to a NXP LPC2000 CPU these are SPI or AT45 CHIP CPU SPI DIV CS ASSERT CS RELEASE FILE AUTO ERASE For NAND FLASH devices these are NAND CHIP CPU DATA BASE CMD BASE ADDR BASE CS ASSERT CS RELEASE ALE ASSERT ALE RELEASE CLE ASSERT CLE RELEASE BAD BLOCK TABLE BAD BLOCKS ERASE BAD BLOCKS SWAP BI OOB INFO FILE AUTO ERASE DAVINCI UBL DESCIPTOR MAGIC DAVINCI UBL DESCIPTOR ENTRY POINT DAVINCI UBL DESCIPTOR LOAD ADDR DAVINCI UBL MAX IMAGE SIZE
96. fault is 1 if not supplied Example flash unlock 0x400000 0x1000 PEEDI User s manual 90 www ronetix at Using PEEDI flash query Syntax flash query ADDRESS LENGTH Description If supported by FLASH show the lock status of all FLASH sectors that belong or overlap to the specified region On NAND devices show the bad block list If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments ADDRESS beginning of FLASH region LENGTH length of FLASH region default is 1 if not supplied Example flash unlock 0x400000 0x1000 flash program Syntax flash program FILE FORMAT OFFSET erase Description Program image file into target FLASH If no arguments are provided last used will be taken Default first used arguments are taken from FILE parameter of the currently selected FLASH section in target configuration file Arguments FILE the image file to be programmed FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format OFFSET Must be provided for binary files because they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset erase if this argument is provided all affected FLASH sectors will be pre erased upon programming Example flash program tftp 192 168 1 1 image elf elf erase flash program tftp
97. gister ISC PROGRAM write 32 config bits write 32 config bits write 2 bypass bits wait ready J A He oil Ml prog secure jtag ri 17 lsb Ox1FF11 idle IR jtag rd 10 lsb 0x80 ilde jtag ri 17 lsb Ox1FF22 idle jtag rd 2 lsb 0x3 idle wait 1000 ISC ADDRESS SHIFT DR Configuration register j ISC_PROGRAM_SECURITY Skip the two bypass bits wait ready H A s ISC DISABLE jtag ri 17 lsb Ox1FFOC idle IR jtag rd 10 lsb Ox3FF ilde DR ISC DISABLE 2 bypass 8 don t care bits PEEDI User s manual 50 WWW ronetix at Using PEEDI If the Flash security is enabled the only way to unlock the device is to perform JTAG Lockout Recovery procedure PEEDI executes a JTAG Lockout Recovery during reset processing if the STR9 flash is secured and if the configuration file contains CORE LOCKOUT RECOVERY YES 3 4 7 ST STM32 family The ST STM32 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files In the STM32 microcontrollers the FLASH may be write protected The protection is set using the STM32 option bytes Option bytes are used to configure also other STM32 CPU settings for more information see the STM32F10xxx Flash programming For managing STM32 option bytes PEEDI has the flash this option command To erase all option bytes use flash this option erase To write a single option byte us
98. given blocks as bad Once marked as bad the blocks a not marked anymore PEEDI supports direct programming of JFFS2 images to the NAND flash For this the OOB_INFO parameter must be set to JFFS2 This way PEEDI will the write the data loading from the image file and will calculate the ECC and program it to the OBB spare bytes PEEDI supports only BIN images starting from address 0 When programming the image bad blocks will be just skipped and left un programmed They will not affect the block count order See at91sam9261 pm9261 cfg and pxa270 custom cfg from our example configuration Appendix A Sample target configuration files If you use a custom file system using PEEDI you can program a bootloader to the NAND chip that will gain the control of the system after it is rebooted and could handle the programming of the left empty NAND FLASH chip considering the NAND file system you use and the bad block present in the given target WARNING The PEEDI TFTP client uses 512 bytes or 2048 bytes if supported by the A TFTP server transfer block size which limits the size of the image file to 32MB or 128MB If your file is bigger use HTTP FTP file server or use MMC SD card to store the file and put it on PEEDI 3 4 11 Freescale MPC5500 family PEEDI User s manual 53 www ronetix at Using PEEDI The Freescale MPC5500 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and
99. grammer The programmer is used through the flash CLT commands The programmer can program FLASH chips in two ways 1 Directly completely non intrusive no target memory is used but very slow 2 Using small agent program which is downloaded to the target RAM 1KB and uses configurable data buffer 0 5 64KB So you can choose which is best suitable for your needs but keep in mind that the agent method is much faster The programming method is set in the FLASH section of the target configuration file where the configurations are available DIRECT AGENT and AUTO where first agent is tried if failed the direct method is used The image to program is not buffered to the PEEDI s RAM but it is downloaded from a TFTP FTP HTTP server or a MMC SD card and programmed in configurable data blocks 0 5 64KB which means that there is no theoretical maximum size limit of the image to be programmed Using the programmer you can program the FLASH chip verify the FLASH chip erase part or entire FLASH chip blank check the FLASH chip lock unlock if supported To erase the FLASH type PEED User s manual 101 WWW ronetix at Using PEEDI peedi gt flash erase this will erase the whole FLASH to erase all sectors within specified FLASH region type peedi gt flash erase 0x200000 0x1000 To program the FLASH using the default arguments from the target configuration file type peedi gt flash program To program the
100. he word Command Line Interface Linux like runtime environment for Windows The core which is set to be current i e default when no core is specified Default server address used when no server is specified Debug Communication Channel communication channel over the JTAG The GNU Debugger A computer that provides data and other services to another computer Especially a computer providing debugging services to a target being debugged A breakpoint that is implemented using non intrusive additional hardware Hardware breakpoints are the only method of halting execution when the location is in Read Only Memory ROM Using a hardware breakpoint often results in the processor halting completely This is usually undesirable for a real time system Graphical User Interface of GDB An executable file that has been loaded onto a processor for execution Type of interface which enables direct access to most CPU resources Multi Media or Secure Digital memory card used to store files Program Counter CPU register that holds the address of the next instruction to be executed The Red Hat boot loader used for update setting some configuration parameters or to load and launch the PEEDI executable image 120 WWW ronetix at Glossary S Script List of CLI commands executed one by one until the last or until an error is returned T Target configuration file
101. ialize in the beginning the system clock the PLL and then switch to normal clock This will allow much faster execution of the INIT section Arguments init normal or desired clock to be used from now on frequency in kHz Example clock init clock normal clock 3000 Syntax adp CORE Description Show select core for the next ADP debug session Arguments CORE core number of desired core to be selected Example adp adp 1 Syntax run ZSCRIPT NUMBER SCRIPT_NAME SCRIPT FILE Description Execute script from the target configuration file or a file containing CLI commands Arguments number associated with a scrip defined in the NES configuration file SCRIPT_NAME name of a scrip defined in the configuration file SCRIPT_FILE file containing CLI commands to be executed PEEDI User s manual 79 www ronetix at Using PEEDI Example run 1 run card myscript cmd go Syntax go ADDRESS ZCORE CORE ADDRESS Zal 1 Description Start current or specified core s If no address is provided the core s will start from its current program counter PC value If no core is specified current core will be started If argument all is provided all cores will be started from their current PC values Arguments ADDRESS address to start from CORE core to be started stall all cores will be started Example go go 0x100040 go 0 go 0 100040 go 0 100040 2 go Hall step Syntax step ADDRESS ZC
102. igh productivity with the Multi Core feature If you acquire the Multi Core feature you can quadruple you productivity because you can work on four targets simultaneously using only a singe PEEDI The targets must be chained using the multiple core cable adapters available from Ronetix Target 1 Target 2 Target3 Target 4 PEEDI User s manual 13 www ronetix at Using PEEDI 2 Installation This chapter will explain how to connect PEEDI to the target and how to configure all the tools necessary for development Two major steps must be followed in order to set up a working PEEDI Connect all required cables this including power cord target cable and if necessary the Ethernet cable which will provide connection to a host computer or file servers This is explained in the hardware installation chapter Install and configure insight gdb debugger This is explained in the software installation chapter 2 1 Hardware installation Front panel and side connectors P JTAG Target MMC SD connector card slot SELECT TARGET Rear panel connectors Power Ethernet RS232 port connector port ETHERNET PEEDI User s manual 14 www ronetix at Using PEEDI 2 1 1 Connection instructions To connect the PEEDI interface unit to your host and to the target hardware 1 Connect the host computer to an Ethernet network or directly to the PEEDI as required A Direct host connection Crossover cable B LAN Connection
103. ing Used when describing internal FLASH of Freescale MPC5500 microcontrollers Argument YES or NO IPS BASE Description Internal Peripheral System base address Argument IPS address SERIAL NUM Description If this parameter is present PEEDI will program a unique serial number on the given FLASH location with each flash program command this way if PEEDI is used in production each board programmed will get an unique serial number The parameter has tree arguments FILE path to a text file which contains the last serial number that is programmed The file must contain only one line with the number with no leading trailing spaces or any other characters For example start of file gt 341 end of file gt Each time PEEDI programs a board it loads the file gets the last serial number increments it and stores the new value back in the file and so if the file resides on a TFTP or a FTP server the server must allow write access upload of the file File may also resides on a MMC SD card or in the PEEDI internal EPPROM file system note that each EEPROM has a limited number of writes ADDRESS where the serial number will be programmed must be aligned to the serial number bits width WIDTH bits width of the serial number value 16 32 64 Currently the SERIAL NUM parameter is supported for external NOR FLASH chips Atmel DataFlash SPI chips and Atmel AT91SAM7 devices Arguments FILE ADDRESS WIDTH Section OS PEEDI User
104. ing support Added Atmel AT91SAM9263 DataFlash programming support Added Freescale MCF5272 BDM support June 2007 Added Analog Devices Blackfin debug support Added Analog Devices Blackfin FLASH programming support Added memory and or commands Added flash multi verify and flash multi blank commands March 2007 Added Freescale BDM ColdFire debug support Added Freescale BDM ColdFire FLASH programming support Added Command Line Interface on the RS232 line Added second possible argument of RESET TIME in ARM TARGET section Added DBGREQ OUTPUT in ARM TARGET section Added NAND FLASH YAFFS support Added JFFS2 NO EM NAND FLASH CFG argument Added info ctrl command Added clock command Added jtag command November 2006 Added Freescale Nexus enabled MPC5500 debug support Added Freescale MPC5500 FLASH programming support Added NAND FLASH JFFS2 support Added NAND FLASH support on XScale CPUs Added WAKEUP TIME in XScale TARGET section Added info spr command Added memory read64 and memory write64 commands Added execute command September 2006 Complemented STR7 family specifics Added AUTO LOCK parameter to the STR7 family FLASH section Added memory test command August 2006 Added NAND FLASH support Added ALLOW ZERO KEYS in TMS470 family FLASH section Added support of using expression instead of a value in the commands Added clock command Replaced sample configuration files
105. l 42 www ronetix at Using PEEDI Description List of blocks to be marked as bad Argument Block numbers separated by comma ERASE BAD BLOCKS Description If this parameter is se to YES PEEDI will try to erase even the bad NAND blocks Argument YES NO WARNING If you erase blocks factory marked as bad there is no way to detect which were the bad blocks SWAP BI Description If this parameter is se to YES PEEDI will swap the bad block marker ECC byte with a spare one This option is applicable for MX21 MX25 IMX27 MX31 and iMX35 targets only Argument YES NO OOB INFO Description How to deal with the Out Of Band OOB spare page bytes Spare bytes are extra bytes added to the page Argument JFFS2 data bytes will be read from the image file spare bytes will be filled with ECC data 6 bytes for 512 bytes page 24 bytes for 2048 bytes page JFFS2 NO EM like JFFS2 but PEEDI does not write erase clean markers RAW data and spare bytes will be loaded from the image file default if OOB INFO parameter is missing YAFFS like RAW but bad blocks are skipped FF only data bytes will be read from the image file spare bytes will be set to OXFF AT91SAM9 Atmel AT91SAM9 hardware ECC BLACKFIN ECC ADI Blackfin hardware ECC IMX ECC Freescale iMX hardware ECC LPC_ECC NXP LPC hardware ECC OMAP3_ECC TI Omap3 hardware ECC PXA_ECC Marvell PXA3XX hardware ECC ONENAND OneNAND hard
106. lash program command Argument YES or NO AUTO LOCK Description Do or do not lock affected FLASH sectors if supported from FLASH after program operation this would prevent FLASH form accidental write or erase operations Argument YES or NO CPU CLOCK Description The CPU clock after the initialization Used when describing internal FLASH of Atmel AT91SAM7 Philips LPC2000 and FreeScale MAC7100 or MCF5200 series microcontrollers PEEDI User s manual 39 www ronetix at Using PEEDI Argument Frequency in kHz SECURE FLASH Description Do or do not secure FLASH to avoid external reading operations This disables the JTAG interface until the whole FLASH is erased so any JTAG operations are impossible after FLASH is programmed and secured Used when describing internal FLASH of Atmel AT91SAM7 series microcontrollers Argument YES or NO SET VECTORS CHECKSUM Description Set this parameter to YES if you want PEEDI to automatically calculate and set the exception vectors checksum at address 0x14 while programming FLASH This check sum is required by the microcontroller bootloader as evidence that valid user application resist in the FLASH so the control will be passed to it Used when describing internal FLASH of Philips LPC2000 series microcontrollers Argument YES or NO DATA BANK Description Set this parameter to YES if your device has flash data bank bank1 Used when describing internal FLASH of ST STR7 series microcontrolle
107. lash with one memory write command PEEDI doesn t use the Read Busy signal The INIT section of the config file must include the initialization for the chip select and the GPIOs because the Flash Programmer doesn t make any initialization The NAND Flash devices may have blocks that are invalid when they are shipped An invalid block is one that contains one or more bad bits Additional bad blocks may develop with use The factory identifies invalid blocks before shipping by programming data other than FFh x8 or FFFFh x16 into the first spare location of the first or second page of each bad block PEEDI automatically detects the bad blocks and reports them using the flash info and flash query commands Once detected the bad blocks are protected against erasing and programming On demand PEEDI can be forced to try to erase the existing bad blocks It is also possible to force blocks as bad To erase all blocks including the bad blocks set the ERASE BAD BLOCKS parameter to YES After PEEDI restart the command flash erase will erase all blocks WARNING A If you erase blocks factory marked as bad there is now way to detect which were the bad blocks Make sure you have saved the output of the flash query command so you can mark again the bad blocks as bad To force marking of blocks 4 27 and 1002 as bad set BAD_BLOCKS parameter like this BAD_BLOCKS 4 27 1002 After PEEDI restart the flash info command will mark the
108. lect ARM Ethernet driver Remote A connection Remote connection driver Name No driver selected Filename Filename Descriptions Available connection drivers 3 a E 7 x Configuration SAM ethernet driver ARM senal driver ARM seral parallel driver Cancel Help Heartbeat Enabled Disabling heartbeat will disable host timeout and packet resend Browse NL IN BY Endian Lith Big Remove There i no need ta specify the endianness of Angel targets LIF Cancel Help PEED User s manual 68 WWW ronetix at Using PEEDI Than click Configure and enter the IP address of your PEEDI and click OK on both dialogs to close them Remote A connection E A xl Remote connection driver M ame ARM ethernet driver Filename jraetherdriver l Descriptions Remote 4 Ethernet driver 1999 2000 4AM Ltd Communications driver for use with Angel Debug Monitor Configuration address undefined Configure Cha eee ethernet connection Target IP address i dz 158 3 53 E Cancel Help Heartbeat e Enabled Disabling heartbeat will disable host timeout and packet resend T Endian Lite Big There i no need ta specify the endianness of Angel targets LIF Cancel Help Here expand the new created item and right click on its sub item On the appeared context menu click Connect
109. length of all TAP controller in the JTAG chain JTAG CLOCK 10 12500 JTAG Clock in kHz 10 kHz JTAG clock for init operations and 12 5MHz for normal work TRST TYPE OPENDRAIN type of TRST output OPENDRAIN or PUSHPULL STARTUP_TIME AUTO wait until target reset pulse finished RESET TIME 20 length of RESET pulse in ms COREO ARM TDMI O TAP O 1S ARM7TDMI CPU COREO_STARTUP_MODE STOP 300 Stop 300ms after reset COREO_INIT INIT_COREO init section for this core COREO_BREAKMODE soft use software breakpoints COREO BREAK PATTERN OXDFFFDFFF software breakpoint pattern COREO_FLASHO FLASH_COREO flash section for this core COREO ENDIAN LITTLE COREO WORKSPACE 0xc00000 OxEOO core endian workspace for FLASH programmer COREL ARMOTDMI 1 TAP 1 is ARM9TDMI CPU CORE1_STARTUP_MODE RESET Stop immediately CORE1_INIT INIT_CORE1 init section for this core CORE1_BREAKMODE soft use software breakpoints CORE1_BREAK_PATTERN OXDFFFDFFF software breakpoint pattern CORE1_FLASHO FLASH_CORE1 flash section for this core CORE1 ENDIAN LITTLE core endian CORE1 VECTOR CATCH MASK 0x10 i CORE1_WORKSPACE 0xA00000 0x20600 catch data abort exceptions workspace for FLASH programmer Each core has its own TCP port number to wait for a debug session The port number is the number specified in the DEBUGER section of the target configuration file plus the number of the core For
110. must be driven by the GPIO pins This way you can use all the PEEDI CLI commands flash program memory read etc on the defined virtual region as the whole device is directly visible in the memory space of the target Actually PEEDI emulates this behavior by accessing physically the device only through the memory window provided by the CPU external address space and driving the higher address lines of the device depending on the address that is requested to be accessed This feature of PEEDI helps programming FLASH chips which are bigger than the visible external asynchronous memory space COREn VMEM Description Defines a memory region which is virtually mapped to big external memory mapped device Argument Start address and length in bytes of the virtual memory region COREn VMEM WINDOW Description Defines a memory window to physically access the external memory mapped device t e the memory region where the device is mapped into the CPU memory space Argument Start address and length in bytes of the memory window COREn VMEM PINS Description List of the GPIO pins connected to the higher external device address lines that are not connected to the CPU address bus starting from lowest to highest separated by comma The GPIO pins must belong to the same GPIO port Argument Pxy where x is the GPIO port A J and y is the bit number 0 15 Imagining that we want to virtually map on address 0x30000000 an 8MB FLASH that is conn
111. n RAM used for agent which allows much faster programming Argument Valid base address within RAM and length in bytes separated by comma COREn DATASPACE Description Base and length of a region in RAM used for agent which allows much faster programming If this parameter is present PEEDI will use the workspace for storing only the agent code and the dataspace for the agent data This is useful when using internal RAM for agent programming where the internal RAM is code or data only for example Blackfin CPUs Argument Valid base address within RAM and length in bytes separated by comma COREn DCC PORT Description TCP port the targets DCC channel to be routed to Argument 1024 to 65535 and optional type of the transfer 8 32 bit COREn PATH Description This parameter defines the default path to be used if only a file name without the full path is provided to a PEEDI command Argument DEFAULT PATH COREn FILE Description This parameter defines the default memory multi load command s arguments This parameter may have two or three arguments The first argument is the file to be programmed The second argument is the file type BIN SREC IHEX or ELF The third argument is mandatory for binary files and optional for all other types of files it is the address where the file should be loaded Argument FILE FORMAT ADDRESS COREn_LOCKOUT_RECOVERY Description If this parameter is present PEEDI automatically exec
112. n Word RCW PEEDI sets a hardware breakpoint at this address to halt the core immediately out of reset Argument The reset vector address COREn RCW Description When this parameter is present PEEDI overrides the Reset Configuration Words with the values provided Argument Reset Configuration Word High Reset Configuration Word Low COREn MMU PTBASE PEEDI User s manual 2g www ronetix at Using PEEDI Description This parameter defines the physical memory address where PEEDI looks for the virtual address of the array with the two page table pointers If this configuration parameter is present and the MMU translation is enabled if PEEDI fails to translate the effective address to a physical one using BAT translation it tries a page translation For more information see chapter CPU specific considerations Argument Address of the of the pointer to the two page pointers array For example of this section see the example configuration files in the appendix of this document section PLATFORM MPC5200 This section describes the MPC5200 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT COREn LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE MPC5200 and a TAP number separated by comma COREn BOOT ADDR Description Normally the boot address for PowerPC i
113. n one region is defined PEEDI begins to check every memory access operation if it falls into a defined memory region If the memory operation is out of the defined regions PEEDI interrupts the operation and issues an error This is made so because when an access is made to an invalid memory address via the BDM the ColdFire CPU refuses to respond to any further memory operations until reset Argument Start and end addresses of the desired memory region separated by comma For example of this section see the example configuration files in the appendix of this document section PLATFORM BLACKFIN This section describes the Blackfin cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the HESET TIME COREn BREAK PATTERN PEEDI User s manual 30 WWW ronetix at Using PEEDI COREn DCC PORT COREn_ LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE BF522 BF525 BF527 BF531 BF532 BF533 BF534 BF535 BF536 BF537 BF538 BF539 BF542 BF544 BF548 BF549 BF561A BF561B and a TAP number separated by comma The following parameters are not mandatory They are used to define a virtual memory region corresponding to an external memory mapped device that is bigger than the visible external asynchronous memory space The higher address lines of the device that are not connected to the CPU address buss
114. n to the server and work there This way no specific software is installed on the developer s PC so it is very easy to set another working environment for a new developer for the project just add a new user on the server and make a copy of the project source and make files in the user s home directory Of course any source control tool such as CVS or Visual Source Safe can be used for synchronizing the project files In this configuration all devices the server the developers PCs and all PEEDIs must be connected in a common LAN An example of multiple programmer development Linux Server X server TFTP Samba arm elf gcc arm elf Id arm elf insight Ethernet Hub SKN M N S cen Y PEEDI Ao O eS CP Target S Target CS Target Linux Workstation Linux Workstation Windows Workstation Cygwin X terminal PEEDI User s manual 11 www ronetix at Introduction 1 2 PEEDI in the manufacturing process PEEDI can be used in the manufacture process as a tool for testing the device after it is assembled and as a FLASH programmer to program the device firmware In both scenarios the host computer is not required because all the operations that must be performed can be formed as script files and executed using the PEEDI s front panel interface If all the necessary files are stored on the MMC SD card the Ethernet connection is not required as well 1 2 1 PEEDI as a standalone FLASH programmer
115. nected to PEEDI via JTAG or SWD Serial Wire Debug It has all the parameters described in the PLATFORM ARM section except the COREn VECTOR CATCH MASK COREn BREAK PATTERN COREn DCC PORT and COREn LOCKOUT RECOVERY The PLATFORM CortexM3 SWD section has no JTAG CHAIN parameter and its clock parameter is named SWD CLOCK and has the same format as the JTAG CLOCK parameter About the CORE parameter COREn Description Core declaration Argument Type of CORE CortexM3 and a TAP number separated by comma COREn SWO Description This parameter is allowed only for the PLATFORM CortexM3 SWD section It tells PEEDI to open a TCP port and listen for incoming telnet connections PEEDI checks for new incoming telnet connection only when the target CPU is halted If a telnet session is opened to that TCP port PEEDI will forward all stimulus data for the given stimulus channel In order for the CPU to transmit stimulus messages you need to enable this functionality This can be done by the target application or by PEEDI using the target INIT script see chapter ST STM32 family Argument TCP port number stimulus channel 0 31 and optional type of the transfer 8 16 or 32 For example of this section see the example configuration files in the appendix of this document Section PLATFORM CortexA8 This section describes the Cortex A8 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn VECTO
116. nnection name select Angel JEENI Connection rdiserv type and click Create Create New Connection Method Mame PEEDI Type MAN ares PEEDI User s manual 70 WWW ronetix at Using PEEDI In the just opened Connection Editor select Processor and other options you desire the important thing here is to select Ethernet connection and fill the IP address of your PEEDI Than click OK and close the Connection Organizer Angel JEEMI rdiserv Connection Editor Mame PEED Type Angel JEENI Connection rdisery Log Connection to file uaux Connection Download Troubleshooting Advanced Processor ARM TDMI vi w Little Endian Serial connection Serial Port defaults a Baud e default d with parallel connection Parallel Port LPT 1 E Ethernet connection to hast 192 158 368 rdiserv adp ethernet 132 1 58 3 53 cpu ARM TD MI littleendian Connect Uk Cancel Revert PEEDI User s manual 71 WWW ronetix at Using PEEDI Now click Target gt Connect to Target to open the Connection Chooser dialog FA Builder for default bld File Edit Project Build Debug Target Version Config Windows Help m nS amp mb s B Filename default bld default con Qhello bld hello c Eresource bld resource Eeacme E hpsery standard d rdiserw multiice rdiser v adp stand nedsery standard Load Module F nar
117. ntally The keys are reported every time the FLASH is programmed Every time PEEDI first tries to unlock FLASH using the default keys OxFFFFFFFF if fails it uses the keys pointed out in the target configuration file This way you can erase and program the FLASH without the need of changing the keys for each operation because during FLASH erase the keys are automatically set to OXFFFFFFFF In TMS470 devices that have Memory Security Module MSM if the currently programmed MSM keys are different from OxFFFFFFFF you have to put this unlock sequence in the INIT section INIT TMS470 dummy read the four keys m r Ox0000ffe0 m r Ox0000ffe4 m r Ox0000ffe8 m r Ox0000ffec PEEDI User s manual 51 WWW ronetix at Using PEEDI try to unlock the device using the correct MSM keys w OxFFFFF 00 OxXXXXXXXX w OxFFFFF704 OXxXXXXXXXX w OXFFFFF708 OxXXXXXXXX w OXFFFFF7OC OxXXXXXXXX 3 3 5 fa Where 0xXXXXXXXX s are the right MSM keys The four word passwords location in the internal FLASH for the MSM1 is placed starting from the last eight words of the first flash sector Please see the datasheet of your TMS470 CPU to check the right addresses of the keys in FLASH memory and the addresses of the registers where the keys have to be entered These passwords are used to insecure the device in case it has been partly secured The ALLOW ZERO KEYS FLASH section parameter is used to protect the device from unwanted permanent locking of the device
118. nual 93 www ronetix at Using PEEDI COREn INIT Description Section to be executed in order to initialize the target Argument COREn FLASHm Name of the section Description This parameter points a section which contains the target FLASH description If multiple FLASH chips configurations are present on the target each chip configurations must be described in different section where m should start from O and increment with each new section If single FLASH chip configuration is used the m integer number may be skipped When working with the programmer the first FLASH is selected as current by default To work on another FLASH use the flash set command to select it The multiple FLASH support could also be used to describe different profiles for the same FLASH for example with different program method type or different image file specified This way you can easy switch to the desired profile using the flash set command Argument COREn ENDIAN Name of a section containing FLASH parameters Description Core endian little big Argument COREn VECTOR LITTLE or BIG CATCH MASK Description opecifies which interrupts exceptions to be trapped i e break if an interrupt or exception occurs ARMY and XSCALE cores only Catch vector mask bit meaning S INN E Fa ma Reseved D Aboni P Abot SWi Undefined Argument Value specifying the desired bit mask COREn_BREAKMODE Description Defa
119. o TEXT Description Display a line of text Useful for printing info in scripts Arguments The text to be displayed Example echo Initializing SDRAM Type jtag help in PEEDI command line for more information Syntax beep FREQUENCY DURATION Description Beep using given frequency and duration Useful for signaling end of scripts execution Arguments Frequency in Hz and duration in milliseconds Example beep 1000 500 Type jtag help in PEEDI command line for more information Syntax Target detach attach Description Set PEEDI debug interface in High Z Arguments detach attach Example target show current interface state target detach set interface in High Z target attach set interface to normal mode Syntax quit Description Quit telnet session Arguments None Example quit PEEDI User s manual 82 www ronetix at Using PEEDI info Syntax info SUBCOMMAND Description Show information about specified topic Arguments SUBCOMMAND subcommand specifying the needed information Example info config info flash Syntax info flash Description Show target FLASH configuration information Arguments None Example info flash info registers Syntax info registers CORE a11 all Description Show current CPU registers values of current specified all cores Arguments CORE core to show its registers values all list all core registers values all list all modes registers values
120. o load a target configuration file which describes the specifics of the given target this includes CPU type FLASH type and metrics RAM address and size etc The target configuration file includes also some settings of PEEDI itself like license keys baud rates of the serial port etc The target configuration file can be loaded from TFTP FTP or HTTP server MMC SD card or the internal EEPROM AII INI files have standard format sections are closed in square brackets comments begin with character and occupy the rest of the line The configuration file consists of several mandatory sections and others which can be named freely Multiple PEEDIs may load single shared target configuration file but you need to fill in it all PEEDIs licenses Section LICENSE Listed in this section are all the license keys that are acquired they will unlock specific features of PEEDI If there is an FILE parameter in this section PEEDI will try to load the licenses from this file The file is searched for an LICENSE section containing licenses Example LICENSE KEY ARM7_ARM9 1111 2222 3333 4 KEY UPDATE 29AUG2006 5555 6666 7777 8 LICENSE FILE tftp 192 168 0 1 licenses txt section DEBUGGER PROTOCOL This section describes the protocol used with the host debugger Two debugger protocols are supported so far the GDB Remote and the Angel debug protocol REMOTE PORT Description TCP port to be used for accepting connections Argument
121. observed that the presence of the ADI USB JTAG debug interface BF535 Spartan FPGA interferes the normal PEEDI operation seen with some EZ KIT and STAMP boards Some BlackFin boards do not work reliably with low JTAG clock so if you experience problems in the INIT section please use 2MHz init JTAG clock 3 5 Boot sequence On power up if the front panel buttons are pressed the bootloader is started If not PEEDI tries to load the configuration file After that it checks if the target is powered Then if the RESET TIME is bigger than O it asserts the target RST and waits the specified time After that if COREn STARTUP MODE is set to RESET PEEDI sets the target in debug mode which assures that no instructions are executed when the target RST is released Next the target RST is released and PEEDI waits the WAKEUP TIME After that the initial JTAG clock is set If the COREn STARTUP MODE is RUN it switches to the normal JTAG clock and the target is left running Else it checks if the COREn STARTUP MODE is STOP and if yes it waits the specified period and stops the target Then the init section is processed After that the JTAG clock is switched to its normal speed Note that Different cores may have different COREn STARTUP MODE parameter set The following diagram shows the boot sequence PEEDI User s manual 56 WWW ronetix at Using PEEDI Both Front Buttons Start BOOT loader na Get Configuration File from TFTF FTP MMC E
122. of the field in the task structure that contains the task name Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma CODE START Description Size and offset of the field in the task structure that contains the address of the task code section Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma DATA START Description Size and offset of the field in the task structure that contains the address of the task data section Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma BSS START PEEDI User s manual 45 www ronetix at Using PEEDI Description Size and offset of the field in the task structure that contains the address of the task bss section Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma CONTEXT Description Size and offset of the field in the task structure that contains saved task context Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma CONTEXT REG Description Using this parameter multiple times you can define which registers are saved in the task context Argument Name as listed by info registers PEEDI command and offset of a register saved in the task context separated by comma Section SERIAL
123. ong ADDRESS where the value is to be written MASK mask to be used for the AND operation Example memory and 0x1000 0x5555AAAA memory and8 0x1000 Ox5A memory and16 0x1000 Ox55AA memory and32 0x1000 0x5555AAAA memory and64 0x1000 0x55555555AAAAAAAA memory crc Syntax memory crc ADDRESS LENGTH CRC Description Calculate or check CRC32 on a given memory region Arguments ADDRESS beginning of region LENGTH length of region CRC crc to check Example memory crc 0x100000 1024 memory crc 0Ox100000 1024 Ox1DF37A8C memory load Syntax memory load FILE FORMAT OFFSET 1 Description PEEDI User s manual 87 www ronetix at Using PEEDI Load image file into target memory If no arguments are provided last used will be taken Default first used arguments are taken from COREn FILE of target configuration file While file is loaded PC will be set at start of the image or at entry point if provided by the image file Arguments FILE the image file to be loaded FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format SEES Must be provided for binary files because they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset Example memory load tftp 192 168 1 1 image bin bin 0x1000 memory load tftp 192 168 1 1 image elf elf memory multi load Syntax memory
124. ous sources While in CLI you can copy files from and to local EEPROM and SD MMC card or FTP TFTP or HTTP servers You can create remove and rename directories and files on the MMC SD card For more information see the description of transfer card and eeprom commands 3 14 1 File path convention PEEDI can get files from local EEPROM and MMC SD card or TFTP FTP and HTTP server It can store files on all the previous locations except HTTP server However the download speed from HTTP and FTP servers is times faster than TFTP servers FAT12 FAT16 and FA32 formatted MMC SD cards are supported but there is no support for long file names so all files should be named using the 8 3 DOS name convention or using names up to twelve characters This file path syntax can be used to point the desired location Note If the file path is skipped the per core default path will be used The default cores path is defined in the target configuration file using the COREn PATH parameter Full path will be used in the entire manual for clear understanding Note If the IP adaress is skipped the default server IP will be used The default server IP can be set using the fconfig RedBoot command Full path will be used in the entire manual for clear understanding tftp 192 168 1 1 subdirectory f1le TFTP server 192 168 1 1 will be requested for subdirectory file tftp subdirectory file TFTP default server IP will be requested for subairectory file f
125. put Controlled from a parameter in config file JTAG TDO Test Data Out signal from the target to PEEDI Connects to the target TDO line Returned JTAG Clock alee mpu Connects to the target RTCK line GDBACK Input Not Used A Push Pull or JTAG Reset TRST Open Drain Resets the JTAG TAP controller on the target output Driver type is specified in config file RESET ai Penal Resets the target system PEEDI User s manual 106 www ronetix at O Output z i lt i i k i i A E Y ol I C2 no co 00 N O al A Co NO O j J O Specifications RS232 Connector DB9F female PL e 1 9 Pin Description Not connected 9 Not connected ARM14 JTAG cable adapter schematic http download ronetix info peedi doc schematics peedi_arm14 paf PEEDI ARM TARGET Ji 1 in VREF Vref out 33 2 1 3 out TCK 2 4 TRST in 3 5 out TDI 4 ete 6 TDI in 5 7 out TMS 6 8 7 TMS in e i HEADER 2x7 n 10 TCK in 9 A e 11 n TDO 10 48 amp 12 TDO out 11 b 13 in RTCK RST in 12 14 13 15 NC 14 9 116 17 NC 18 19 out TRST pus 20 bidir RST B J2 ue 1 1 2 RTCK TCK 7 a A Tile PEEDI ARM14 Module ADAPTER 3 Company RONETIX yy Rev 1 0 EMEN Au
126. r elf formats all the code will be shifted regarding the specified offset Example flash multi verify Zall tftp 192 168 1 1 image elf elf flash multi verify 0 2 ftp 192 168 1 1 image bin bin 0x100 flash verify Syntax flash verify FILE FORMAT OFFSET Description Verify target FLASH with image file If no arguments are provided last used with the flash program command will be taken Arguments FILE the image file to be verified with FORMAT format of image file bin binary file ihex Intel HEX format srec Motorola S record format elf ELF format GEESE Must be provided for binary files because they don t have any address information If provided with ihex srec or elf formats all the code will be shifted regarding the specified offset Example flash verify tftp 192 168 1 1 image elf elf flash verify tftp 192 168 1 1 image bin bin 0x1000 flash dump Syntax flash dump ADDRESS LENGTH FILE Description Dump target FLASH to a file If no arguments are provided last used will be taken Arguments ADDRESS beginning of memory region LENGTH length of memory region FILE file to store the image All path except HTTP server are accepted Example flash dump O 1024 tftp 192 168 1 1 ram bin flash read Syntax flash read ADDRESS COUNT Description Read and show FLASH memory contents Useful for NAND SPI and DataFlash FLASH types i e chips which are not visible through the CPU memory map For
127. r support in FLASH programmer July 2008 Added Cortex M3 support Added ST STM32 FLASH support Added flash this option ST STM32 FLASH command Added new GDB registers frame support for MPC5500 targets June 2008 Added flash this secure AT91SAM7 FLASH command Added flash read command description Licenses now can be loaded from an external file Fixed DCC example code DBGHEQ OUTPUT is now available for all JTAG targets May 2008 Added Freescale PowerQUICC II Pro MPC83XX support Added beep command Added COREn_MEMMAP config parameter for Blackfin Added support of 2048 bytes of TFTP transfer packet size March 2008 Added flash this hidden generic FLASH command Added flash this nvmbit AT91SAM7 FLASH command Added WDKICK_TIME in ARM TARGET section Complemented break add command February 2008 Added note about TMS470 s AWD in CPU specific considerations Added echo command January 2008 Added ARM11 support Added Blackfin NFC programming support Added Blackfin SPI FLASH programming support Added ALE_ASSERT RELEASE CLE ASSERT RELEASE NAND config parameters Added Freescale MCF5206 BDM support PEEDI User s manual 3 WWW ronetix at Change log Reworked reset command to accept target reset options November 2007 Added Analog Devices Blackfin DataFlash programming support September 2007 Added JTAG TDO DELAY CFG parameter Added Analog Devices Blackfin NAND FLASH programm
128. rec or elf formats all the code will be shifted regarding the specified offset Example flash verify tftp 192 168 1 1 image elf elf Flash verify tftp 192 168 1 1 image bin bin 0x1000 memory dump Syntax memory dump ADDRESS LENGTH FILE Description Dump target memory to a file If no arguments are provided last used will be taken Arguments ADDRESS beginning of memory region LENGTH length of memory region FILE file to store the image All path except HTTP server are accepted Example memory dump O 1024 tftp 192 168 1 1 ram bin memory test Syntax memory test ADDRESS LENGTH Description Test target RAM region Arguments ADDRESS beginning of memory region LENGTH length of memory region Example memory test 0x100000 1024 flash Syntax flash SUBCOMMAND Description Manage target FLASH Subcommand must be provided Arguments SUBCOMMAND subcommand specifying the FLASH operation Example flash erase flash set Syntax Flash set FLASH Description Show set current FLASH target section Arguments FLASH FLASH section number desired to be current Example Flash set flash set 1 PEEDI User s manual 89 WWW ronetix at Using PEEDI flash blank Syntax flash blank ADDRESS LENGTH Description Check FLASH region if it is blank i e filled with OxFF If no arguments are provided last used will be taken Default first used region is whole FLASH Arguments ADDRESS beginning of FL
129. rom a TFTP FTP HTTP server or a MMC SD card and programmed in configurable data blocks 0 5 64KB Which means there is no theoretical maximum size limit of the image to be programmed Q PEEDI does not connect to a Philips LPC2XXX device What should do A First make sure the pull down resistor that enables the JTAG interface is not more than 1k and second verify that the CORE STARTUP MODE parameter gives the device at least 100ms to run PEEDI User s manual 118 www ronetix at FAQ Q Whende buging mixed ARM Thumb code using gdb insight the debugger can not step in from ARM to Thumb function What to do A Use the si step one instruction command in the gdb insight several times to step in to the desired Thumb function PEEDI User s manual 119 www ronetix at Glossary 6 Glossary A Alias Agent B Breakpoint Big endian C CLI Cygwin Current core D Default server DCC G GDB Host Hardware breakpoint I Insight Image J JTAG M MMC SD card P PC H HedBoot PEEDI User s manual User defined alias of a command including its arguments Small program downloaded into the target which is used for faster operations A user defined point where execution stops so that a debugger can examine the state of memory and registers Memory organization where the least significant byte of a word is at the highest address and the most significant byte is at the lowest address in t
130. rs Argument YES or NO PROTECTION KEYO PROTECTION KEY3 Description These four parameters define the four FLASH security keys that are used to unlock the FLASH for erasing and writing Used when describing internal FLASH of TI TMS470 series microcontrollers Argument C style 32bit HEX value ALLOW ZERO KEYS Description This parameter is used to prohibit programming of new Memory Security Module keys that are all 0x00000000 because this will permanently lock the TMS against debugging and programming Used when describing internal FLASH of TI TMS470 series microcontrollers Argument YES or NO CPU Description Target CPU Used when describing NAND SPI or Atmel DataFlash Argument AT91RM9200 AT91SAM9261 AT91SAM9263 AT91SAMT MX21 iMX25 MX27 IMX31 MX35 iMX51 BF5XX BF52X BF54X MPC83XX TMS320DM355 LPC2XXX LPC318X MLC PXA3XX SPI DIV Description SPI divider AT91RM9200 Fspi MCK 2 SPI DIV AT91SAM9261 Fspi MCK SPI DIV Used when describing Atmel DataFlash Argument PEED User s manual 40 www ronetix at Using PEEDI Divider value nSPl Description SPI controller to use Used when describing Atmel DataFlash Argument 0 or 1 nCS Description Chip select to use Used when describing Atmel DataFlash Argument 0 to 3 SPI SPCK Description This describes which PIO is dedicated to the SPI SPCK signal Used when describing Atmel DataFlash Argument controller peripheral pin for example PIOA A 2 PIOA
131. s OxFFF00100 or 0x00000100 depending on the Reset Configuration Word RCW PEEDI sets a hardware breakpoint at this address to halt the core immediately out of reset Argument The reset vector address For example of this section see the example configuration files in the appendix of this document Section PLATFORM MPC8500 This section describes the MPC8500 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT COREn LOCKOUT RECOVERY and COREn VECTOR CATCH MASK including some additional parameters COREn Description Core declaration Argument Type of CORE MPC8500 and a TAP number separated by comma COREn MMU TRANS Description This parameter sets the default MMU translation address For example the default Linux kernel address is 0xC0000000 Argument Address of virtual address of the memory region which is physically mapped to address 0 COREn_MMU_PTBASE Description This parameter defines the physical memory address where PEEDI looks for the virtual address of the array with the two page table pointers If this configuration parameter is present and the MMU translation is enabled if PEEDI fails to translate PEED User s manual 29 WWW ronetix at Using PEEDI the effective address to a physical one using BAT translation it tries a page translation For more information see chapter CPU specific considerations Argument Address of the of th
132. s manual 44 www ronetix at Using PEEDI This section contains parameters which help PEEDI to scan the target OS task list BASE Description Size and address of the first task item in the item list Argument oize of the item pointer in bytes and the address of it separated by comma the address may be represented by a path to a file ex tftp 192 168 1 1 task base this way PEEDI will dynamically get the base from external file that could be auto generated by the makefile using command like this nm vmlinux grep w init task gt tftproot task base This way you don t need to change the PEEDI CFG every time the base address is changed from build to build NEXT Description Size and offset of the field in the task structure that contains the address of the next task structure in the task list Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma NEXT THREAD Description Size and offset of the field in the task structure that contains the address of the next thread of the multithreaded task in the task list Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma PID Description Size and offset of the field in the task structure that contains the unique task ID Argument Size of the filed in bytes and the offset of it from the beginning of the task structure separated by comma NAME Description Size and offset
133. s on the next reset The only way to un secure the device is to use ISP command to erase the FLASH This can be made with the Philips LPC2000 FLASH utility For more information about the LPC2000 securing code protection read the LPC2000 user manual 3 4 4 Freescale MAC7100 family The Freescale MAC7100 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files In program FLASH the address range from 0x0400 to 0x041F is used to set the FLASH security If there is user code this could secure the FLASH incidentally so avoid placing code there flash erase chip perform MASS ERASE flash lock write at address OXFC100414 OxFFFFFFFCO enable flash security PEEDI User s manual 49 WWW ronetix at Using PEEDI If the Flash security is enabled the only way to unlock the device is to perform JTAG Lockout Recovery procedure PEEDI executes a JTAG Lockout Recovery during reset processing if the MAC7100 flash is secured and if the configuration file contains CORE LOCKOUT RECOVERY clkd 3 4 5 ST STR7 family The ST STR7 family devices need a special FLASH section in the target configuration file for more information see Section FLASH and Appendix A Sample target configuration files In the STR7 microcontrollers several memory regions may be mapped at address 0x00000000 including the internal FLASH So these are the
134. sequential or other damages Failure in handling which leads to defects are not covered under this warranty The warranty is void under any self made repair operation except exchanging the fuse RONETIX warrants PEEDI firmware for a period of 12 months following the date of purchase i e every reported bug will be fixed and an update will be made available PEEDI User s manual 123 www ronetix at Appendix A Appendix A Sample target configuration files Please use this link to download the most recent version of the sample target configuration files ht to download ronetix info peedi ctg examples peedi config files zi PEEDI User s manual 124 www ronetix at
135. subdirectory file card subdirectory file MMC SD card will be searched for subdirectory file eep file Local EEPROM will be searched for file EEPROM file system if flat i e directories are not supported Keep in mind it has very limited storage space tenths of kilobytes file The default path to the file will be used got from the COREn PATH configuration parameter PEEDI User s manual 77 WWW ronetix at Using PEEDI 3 14 2 CLI commands PEEDI has full functional telnet command line interface CLI which provides many useful commands It has vary easy to use help system and command auto complete so instead of flash program you could type only fl pr or you could just hit TAB to auto complete the command or subcommand If you are unsure about some command arguments hit TAB again and the command help will be printed so you can continue writing your command line An expression can also be used instead of a value in a command The expression can include only the four main math operations and And it is interpreted without priority from left to right e g memory read 4 0x1000 32 32 help Syntax help COMMAND SUBCOMMAND Description Shows help about command or a subcommand Arguments COMMAND command which help will be shown COMMAND SUBCOMMAD subcommand which help will be shown Example help help halt help flash program transfer Syntax transfer SOURCE DESTINATION Description Copy fil
136. t add hard ADDRESS Description Set hardware break point No more than two hardware break points can be set Arguments ADDRESS address of the break Example breakpoint add hard 0x400040 breakpoint add watch Syntax breakpoint add watch ADDRESS ACCESS TYPE Description Set watch point Unlimited number of watch points can beset Arguments ADDRESS address of value to be watched for access ACCESS access type to break on r read access Ww write access rw any access TYPE type of watched value 8 value is 8 bit byte 16 value is 16 bit half word 32 value is 32 bit word Example breakpoint add watch 0x400040 32 r breakpoint delete Syntax breakpoint delete ID all Description Delete break or watch point Arguments ID id number of break or watch point desired to be removed taken using breakpoint list command all if provided all break and watch points will be deleted Example breakpoint delete 7 breakpoint delete all breakpoint list Syntax breakpoint list CORE Description List all set break and watch points for the current or specified core Arguments PEED User s manual 96 www ronetix at Using PEEDI CORE core s break and watch points to be listed Example breakpoint list breakpoint list 1 card Syntax card SUBCOMMAND Description Manage MMC SC card files Subcommand must be provided Arguments SUBCOMMAND subcommand specifying the operation Example card
137. thor ILKO ILIEV 7 17 2005_14 59 Sheet 1 of 1 The ARM14 JTAG cable adepter is available for free upon request PEED User s manual 107 www ronetix at Specifications ARM20 JTAG cable adapter schematic http download ronetix info peedi doc schematics peedi_arm20 paf ADAPTER PEEDI ARM20 PEEDI ARM TARGET Ji J2 1 in VREF Vref out 1 2 2 3 out TCK TRST in 3 4 4 o 5 out TDI TDI in 5 6 6 m o e 7 out TMS TMS in 7 8 8 le e out GDBRQ TCK in HEADER 2x10 10 10 m o 11 in TDO RTCK out 11 12 12 o e 13 in RTCK TDO out 13 14 14 l 15 GDBACK RST in 15 16 16 a S O 17 NC GDBRQ in 17 18 18 o 19 out TRST GDBACK out 19 20 bidir RST 20 9 Title PEEDI ARM20 Module ADAPTER Company RONETIX SZ9 Rev 1 0 Author ILKO ILIEV 7 17 2005_14 50 Sheet of ARM10 JTAG cable adapter schematic http download ronetix info peedi doc schematics peedi arm10 pdf PEEDI J 1 in VREF ARM TARGET 2 3 out TCK 14 4 J 5 out TDI RTCK out 1 6 Ni TRST in 2 7 out TMS 3 E ES TCK in 4 9 NC 5
138. tp user password 192 168 1 1 subdirectory fi le FTP server 192 168 1 1 will be requested for subdirectory file from the current working directory right after the login of user with password ftp user password 192 168 1 1 subdirectory file FTP server 192 168 1 1 will be requested for subdirectory file from server root directory using user and password credentials to login ftp 192 168 1 1 subdirectory file FTP server 192 168 1 1 will be requested for subdirectory file using user anonymous and password guest to login ftp user password subdirectory file PEEDI User s manual 76 WWW ronetix at Using PEEDI FTP default server IP will be requested for subdirectory file from the current working directory right after the login of user with password ftp user password subdirectory f1le FTP default server IP will be requested for subdirectory file from server root directory using user and password credentials to login ftp subdirectory file FTP default server IP will be requested for subdirectory file from the current working directory right after the login of user anonymous with password guest ftp subdirectory file FTP default server IP will be requested for subdirectory file from server root directory right after the login of user anonymous with password guest http 192 168 1 1 subdirectory file HTTP server 192 168 1 1 will be requested for subdirectory file http subdirectory file HTTP default server IP will be requested for
139. ult breakpoint mode Use to force the usage of hardware break points when debugging in FLASH or when working with GDB v5 3 where the hbreak command does not work Argument Note SOFT software breakpoints will be used HARD hardware breakpoints will be used The ARM EmbeddedICE logic has hardware resources for two break conditions never mind break or watch points The use of software breakpoints allows unlimited number of them but this still requires the hardware resource of one break watch point Software breakpoints are possible only if the code is executed from RAM since the deisred instruction to be breaked on is exchanged with special pattern In breaf you can use up to two watchpoints or hardware breakpoints or one watchpoint or hardware breakpoint and unlimited number of software breakpoints This means that you may use only one watch point and still debug normally in RAM But if your code is in ROM FLASH you must use hardware breakpoints so if you have set one break or watch point you can still do signle step step in and step out but if you have set two watch or break points only continue is possible after the target breaks since the debuger needs a temorary break point to achieve the step functionality PEEDI User s manual 24 WWW ronetix at Using PEEDI COREn BREAK PATTERN Description Software breakpoint pattern Argument 32 bit value COREn WORKSPACE Description Base and length of a region i
140. updated You can use the first way and a wait command to automate this in the INIT section of the target configuration file INIT XSCALE break add watch Oxffff001C w 32 set watchpoint on FIQ vector start target wait to break start again with updated vectors go wait 30000 stop E go If the vectors are set during code download they will be automatically updated if defined AUTO If you want the target to be stopped after it is initialized just remove the last two lines from the previous example of the XScale init section Avoid using code that potentially could invalidate the mini instruction cache during debug Don t use MCR p15 0 rd c7 c5 1 instead use MCR p15 0 rd c7 c5 Disable CONFIG XSCALE CACHE ERRATA Workaround for XScale cache errata option when building Linux kernel 3 4 10 NAND FLASH PEEDI is able to program all NAND chips with 8 and 16 bits bus and up to 8Gbits of size Generally the NAND Flash programming is CPU independent but the given target must comply with the following hardware requirements The CPU must have a direct access to the NAND Flash chip PEEDI User s manual 52 WWW ronetix at Using PEEDI 1 To be able to write read data from to the NAND Flash with one memory transaction command 2 To be able to write ADDRESSES and COMMANDS ALE and CLE to the NAND Flash with one memory transaction command 3 To be able to ASSERT and RELEASE the chip select ALE and CLE of the NAND F
141. utes a JTAG Lockout Recovery procedure during reset processing if the MAC7100 STR9 or AVR32 flash is secured Argument YES NO for STR9 and AVR32 devices For MAC7100 devices 7 bit value for the CFMCLKD register used during the JTAG Lockout Recovery Calculate this parameter based on the reset system clock PLL disabled For example 19 CLKD for 8MHz system clock 9 CLKD for 4MHz system clock PEED User s manual 25 www ronetix at Using PEEDI COREn OS Description This parameter points to a section which contains parameters that defines the target Operating System This guides PEEDI to scan the target OS tasks and pass the list to the host debugger Argument A name of a section containing the OS parameters For example of this section see the example configuration files in the appendix of this document Section PLATFORM ARM 1 This section describes the ARM11 cores connected to PEEDI It has all the parameters described in the PLATFORM ARM section except the COREn BREAK PATTERN COREn DCC PORT and COREn LOCKOUT RECOVERY About the CORE parameter COREn Description Core declaration Argument Type of CORE ARM1136 ARM1156 or ARM1176 and a TAP number separated by comma The cores differ by the cp15 registers For example of this section see the example configuration files in the appendix of this document Section PLATFORM CortexM3 Section PLATFORM CortexM3 SWD These sections describe the CortexM3 cores con
142. ware ECC DAVINCI ECC TI DaVinci Hardware ECC 4 bytes per 512 bytes data DAVINCI ECC HWe 512 DaVinci hardware ECC 6 bytes per 512 bytes data DAVINCI ECC HWe 512 2610 DaVinci hardware ECC 6 bytes per 512 bytes data with workaround for a JFFS2 bug in Linux kernel 2 6 10 DAVINCI ECC HW10 512 DaVinci hardware ECC 10 bytes per 512 bytes data DAVINCI UBL DESCIPTOR MAGIC Description Descriptor magic the first 32 bit value in the UBL descriptor It set to non zero value programming of the file image is relocated with one NAND Flash page 512 or 2048 bytes The skipped page is used for the UBL descriptor and it is filled by PEEDI Used when describing NAND FLASH for TI DaVInci CPU Argument Value PEEDI User s manual 43 www ronetix at Using PEEDI DAVINCI UBL DESCIPTOR ENTRY POINT Description This value will be programmed at offset Ox4 in the UBL descriptor Used when describing NAND FLASH for TI DaVinci CPU Argument Value DAVINCI UBL DESCIPTOR LOAD ADDR Description Used when describing NAND FLASH for TI DaVInci CPU Argument Value DAVINCI UBL MAX IMAGE SIZE Description Used by PEEDI to print a warning if the programmed file size exceeds this limit Used when describing NAND FLASH for TI DaVinci CPU Argument Value ALLOW SHADOW MODIFY Description This parameter is used to prohibit programming erasing of Shadow FLASH memory because this may permanently lock the MPC5500 device against debugging and programm
143. with a link for download July 2006 Added COREn PATH configuration parameter in TARGET section Added COREn FILE configuration parameter in TARGET section FILE XXXX parameters replaced by single FILE parameter in FLASH sections Changed File Path Convention Added memory verify command Added flash dump command Added execution of the scripts defined in target configuration file from CLI Added source code of example target side DCC functions June 2006 Added TI TMS470 series microcontroller support Added Atmel DataFlash support Added ucLinux debugging support Added DCC over TCP support Added memory multi load command Improved XScale exception vectors handling April 2006 Added ST STR7 series microcontroller support Added FLASH auto detect March 2006 Added Intel XScale CPU support Added Freescale MAC7100 series microcontroller support Reworked target connect procedure see Boot procedure Removed STARTUP TIME configuration parameter Added WAKEUP TIME configuration parameter February 2006 The sample target configuration file spitted to three separated files Complemented Philips LPC2000 family specifics Removed boot script explanation in RedBoot configuration January 2006 Added flash multi program command PEEDI User s manual 4 www ronetix at Change log a o a Complemented Multiple core support December 2005 Added Philips LPC2000 series microcontroller support Added
144. y access 8 value is 8 bits byte long 16 value is 16 bits half word long 32 value is 32 bits word long 64 value is 64 bits double word long value is string ADDRESS where the value is to be written VALUE the very value COUNT how many consecutive values to be written if not provided count 1 is assumed Example memory write 0x1000 Ox5555AAAA memory write8 0x1000 Ox5A memory writel6 0x1000 0x55AA memory write32 0x1000 0x5555AAAA memory write64 0x1000 0x55555555AAAAAAAA memory write 0x1000 hi there memory write 0x1000 Ox5555AAAA 8 memory write memory or Syntax memory orTYPE ADDRESS MASK Description Make logical OR with and apply to target memory PEEDI User s manual 86 Www ronetIx at Using PEEDI Arguments TYPE memory access 8 mask is 8 bits byte long 16 maskis 16 bits half word long 32 maskis 32 bits word long 64 maskis 64 bits double word long ADDRESS where the value is to be written MASK mask to be used for the OR operation Example memory or 0x1000 Ox5555AAAA memory or8 OQx1000 Ox5A memory or16 0x1000 0x55AA memory or32 0x1000 0x5555AAAA memory or64 0x1000 0x55555555AAAAAAAA memory and Syntax memory andTYPE ADDRESS MASK Description Make logical AND with and apply to target memory Arguments TYPE memory access 8 mask is 8 bits byte long 16 maskis 16 bits half word long 32 maskis 32 bits word long 64 maskis 64 bits double word l

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