USER MANUAL - Oho
Contents
1. S Sol T 382829ANd 1 K shen EE CO sng 3b HN Se a Na ruo uorsaen gsn 07031 diy 4oieqnba4 SW dapun sped aapios paiunou You o o x amp ka ds gt G z O O 5 bai JE o aal ea N N LO o ea co X Co KO O L Q o Oo tc Cc o PN O Ss O GOP XC3S200 USER S MANUAL 0 91 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 13 Module Layout Top View 1c3 SN74CB3T16211 DS E DE SE to 5 amp RS e WS S zz seu ol E ES kas 5 KR EE ED H EE 8 D i TH g 8 E A A SS St e SE DS R36 R31 End iL EI EI 21 1 1 O DA DO O Add EH OOOO OO OD OO DQ DD Ina SN74CB3T16244 Si gd WS ES HH E Foot FL AST Paz MOLBLYB CON3 ou Car S ZEOOCH StOdocH oo GOP XC3S200 USER S MANUAL 0 91 Page 32 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 14 Module Layout Bottom View DOO OOO OO Oooo ODDDDDdDdDD DOOD OOOO Oo sooo oO oO OD DODO OOO DD DOO YOON Y j 5 GOP XC3S200 USER S MANUAL 0 91 Page 33 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 15 Assembly variants Different assembly options can be delivered GODIL2. o IN to doaz enen BK e zsn A EETU use45 8031 Erp enen CZ A sla paa 9037 YBEE ENEN gt P sla Bac Si paa 9037 upEE ENEN P CT mos wa 62TH paa 031 s 212131 ener B E NIS ES 8 1 paa E031 S82v828 TSOTL AST S8ev828 ZSITL er m NDILS3L e 00 CI bere ZNId EZNId ZZNId LIZENS EI TTZ9TLEBIPANS 4199 0 1 3NDD ONS Dt 071 T022n ANI23n 071 071 ONS gt BX12H9 O T Gu 0 1 0 1 gt 083 0 1 gt nud 0 1 D eod Det gt 9 108 0 1 gt 2210H8 0 1 TAJAN di 071 Dt Ong rom Xnu22n SHL O T BSN TSN O T TO S3 OW 0 1 Z S3 TH O T 911 53 3 129 071 TH S3 2 199 0 I IBBTIDN 39BTSEIX 20BT90N 3B675E3X O02 199n 3e05565x TITI gt atx199 O T D 1139 0 1 gt Sx199 9 1 gt 91139701 24199 0 1 gt 84739 dr 63129 dI zB ER 8 EE 98 ZB E8 kB E 98 UN 88 A19 BB 68 GG 96 Sti 3 EC eti ENEN sid ONG enin Wie KE EE TE TATII O T gt 114199 Det ang 0 1 TE ZE ER FE Isi Z5 ON TE SS Ez 19 0 1 211199 0 14 033n z43un dl ang ANTI 9438n O T xne33n 2022n Dt SE EIS ES v6 GE Gnen ener 86 nsi TOL ISOU nog ES ES Sz ISOW O I Inoa Get 8 UC O I 87053 0 1 O T Dei xnu35n D22n Ong 2181 0 1 9 0 1 Guil 8 12H1 0 15 Am 071 X10H1 D I Cap 0 1
3. 12 FPGA Design SU DOIN AA AA AA 29 13 Module Layout Top Rl Y 32 14 Module Layout Bottom AA AA AA 33 15 Assembly valtalils xou ee ea 34 16 Technical Spot CN 35 17 E na aa en sss 36 18 USER MANUAL RavisSiOnS oooo oocoooooo oo nnn nena than nn aeu a EX au ea ERYR RE aM ena 37 GOP XC3S200 USER S MANUAL 0 91 Page 3 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de GOP XC3S200 USER S MANUAL 0 91 Page 4 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 Introduction GODIL is a low cost and versatile Spartan 3E FPGA module with an optional DIL 0 6 48 or 40 pin connector to replace legacy DIL devices or IDC headers only in a 0 1 grid Many additional features like USB future upgrade make it useful and flexible 2 1 VVVVVVVVVV VV YYVYVYVYVYV N N Vy V V V V V V GODIL Features Low cost XC3S500E 4VQG100C FPGA a member of the XILINX Spartan 3E family optional XC3S250E 4VQG100C or XC3S100E 4VQG100C FPGA SPI Flash configuration device Future USB update choice of 0 6 48 or 40 pin DIL connector with almost arbitrary VCC or GND connection by jumpers or 2 x 50 pin IDC 0 1 headers only Xilinx Parallel Cable IV or Platform USB Il Cable compatible download connector 14pin 2mm an OHO Elektronik low cost programmer is also available GOP LCP 32 16 Mbit user SP
4. 44 gt Connection to the 48 pin DIL plug to pin44 via level shifter LHCLKO IC3 pin47 10 1 0 LOSN 3 F10 pin lt 45 gt Connection to the 48 pin DIL plug to pin45 via level shifter LHCLK1 IC3 pin46 11 l O LO4P 3 F11 pin lt 46 gt Connection to the 48 pin DIL plug to pin46 via level shifter LHCLK2 IC3 pin45 12 1 0 LO4N 3 F12 pin lt 47 gt Connection to the 48 pin DIL plug to pin47 via level shifter LHCLK3 IC3 pin44 13 IP SOUT sout TUSB3410 serial data output TUSB3410 14 GND GND Connection to the GND Layer of the PCB 15 1 0 LO4N 3 F15 pin lt 2 gt Connection to the 48 pin DIL plug to pin2 via level shifter LHCLK4 IC3 pin41 16 1 0 LO4N 3 F16 pin lt 3 gt Connection to the 48 pin DIL plug to pin3 via level shifter LHCLK5 IC3 pin40 17 1 0 LO4N 3 F17 pin lt 6 gt Connection to the 48 pin DIL plug to pin6 via level shifter LHCLK6 IC3 pin36 18 1 0 LO4N 3 F18 pin lt 5 gt Connection to the 48 pin DIL plug to pind via level shifter LHCLK7 IC3 pin37 19 GND GND a Connection to the GND Layer of the PCB 20 VCCO 3 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 21 VCCAUX VCC2V5 VCCAUX must be 2 5V 22 l O LO7P 3 F22 pin 8 Connection to the 48 pin DIL plug to pin8 via level shifter IC3 pin33 23 1 O LO7N 3 F23 pin lt 9 gt Connection to the 48 pin DIL plug to pin9 via level shifter IC3 pin32 a RER GE cso FPGA SPI configuration memory chip select 25 l O LOIN 2 CTS cts CLEAR TO SEND CTS to TUSB3410 INIT B I
5. 49 gt C13 A13 not on DIL C14 A14 pin lt 13 gt I O P40 pin lt 11 gt P41 I O pin lt 14 gt C15 A15 GND pin 125 C16 A16 pin lt 15 gt I O P36 pin lt 13 gt P35 I O pin lt 16 gt C17 A17 GND pin lt 14 gt C18 A18 pin lt 17 gt I O P53 pin lt 15 gt P54 I O pin lt 18 gt C19 A19 GND 2 pin lt 16 gt C20 A20 pin lt 19 gt I O P57 pin 175 P58 I O pin lt 20 gt C21 A21 GND pin lt 18 gt C22 A22 pin lt 21 gt I O P60 pinz195 P61 I O pin lt 22 gt C23 A23 GND pin lt 20 gt C24 A24 pin lt 23 gt I O P62 P63 I O pin lt 24 gt C25 A25 GND As an example to put VSS GND to a GODIL40 module on pin 20 place a jumper between header pins C23 and A23 GOP XC3S200 USER S MANUAL 0 91 Page 21 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 7 CON4G 2 Right Header Connector Pinout Table FPGA pin Direction Signal name Pin row Pin row Signal name Direction FPGA pin 48 40pins B D 48 40pins B1 D1 pin lt 48 gt l O P91 P12 I O pin lt 47 gt B2 D2 B3 D3 pin lt 46 gt I O P11 pin lt 40 gt P10 I O pin lt 45 gt B4 D4 pin lt 39 gt s B5 D5 pin lt 44 gt I O P9 pin lt 38 gt P90 I O pin lt 43 gt B6 D6 pin lt 37 gt B7 D7 pin lt 42 gt I O P5 pin
6. Connection to the 40 pin DIL plug to pin19 via level shifter IC1 pin48 18 l O LO2N 1 F58 pin lt 18 gt Connection to the 40 pin DIL plug to pin20 via level shifter IC1 pin47 19 l O LOSP 1 F60 pin lt 19 gt Connection to the 40 pin DIL plug to pin21 via level shifter RHCLKO IC1 pin45 20 1 0 LO3N 1 F61 pin lt 20 gt Connection to the 40 pin DIL plug to pin22 via level shifter RHCLK1 IC1 pin44 21 l O LO6P 1 F67 pin lt 21 gt Connection to the 40 pin DIL plug to pin27 via level shifter RHCLK6 IC1 pin39 22 l O LOGN 1 F68 pin lt 22 gt Connection to the 40 pin DIL plug to pin28 via level shifter RHCLK7 IC1 pin37 23 1 0 LO7P 1 F70 pin lt 23 gt Connection to the 40 pin DIL plug to pin29 via level shifter IC1 pin36 24 l O LO7N 1 F71 pin lt 24 gt Connection to the 40 pin DIL plug to pin30 via level shifter IC1 pin35 25 IO LO3N O F86 pin lt 25 gt Connection to the 40 pin DIL plug to pin31 via level shifter GOP XC3S200 USER S MANUAL 0 91 Page 26 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de GCLK7 IC1 pin34 26 IO LO2N O F84 pin lt 26 gt Connection to the 40 pin DIL plug to pin32 via level shifter GCLK5 IC1 pin32 27 V O L02P 0 F83 pin lt 27 gt Connection to the 40 pin DIL plug to pin33 via level shifter GCLK4 IC1 pin31 28 1 0 LO1P O F78 pin lt 28 gt Connection to the 4
7. Dachau Germany www oho elektronik de 18 USER MANUAL Revisions Version Date Comments V0 901 20 08 2009 Prerelease V0 91 31 12 2009 Added dimensioning GOP XC3S200 USER S MANUAL 0 91 Page 37 of 37
8. distributed RAM 20 dedicated advanced multipliers 18x18 4 Digital Clock Managers DCMs Lots of I O standards but GODIL supports LVCMOS33 and LVTTL only Wide multiplexers fast look ahead carry logic 8 global clock nets JTAG interface with user access Free powerful VHDL VERILOG schematics simulation design software available Webpack Unlimited reprogrammability Xilinx Spartan 3E Disadvantages The following items are not relevant in most cases However they should be used as a checklist to query wheather an application is affected VV VV VVV WV No single chip solution needs a configuration source like a platform FLASH 3 different supply voltages required core voltage 1 2V VCCAUX 2 5V I O voltage I Os are not 5V tolerant High quiescent current in the range of tens of milliamps for each of the supply voltages for XC3S500E Design is not protected against copyright theft configuration bitstream can be recorded Lower performance FPGA compared to the luxury Virtex2 pro or Virtex4 5 6 FPGA s especially not all LUTs have RAM shift register capabilities DLLs in the DCM s have higher jitter than PLLs More modern Spartan 3A is less expensive has more I O features but only 200k in VAG100 package GOP XC3S200 USER S MANUAL 0 91 Page 6 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 5 GODIL48 Board with DIL connector Top And Bottom View GOP XC3S200 USER S MANU
9. document please contact mrandelzhofer oho elektronik de serious hints are very appreciated Trademarks All brand names or product names mentioned are trademarks or registered trademarks of their respective holders PAL and GAL are registered trademarks of Lattice Semiconductor Corp GOP XC3S200 USER S MANUAL 0 91 Page 2 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 1 Table of contents 1 Table of contents Em 3 MI aee lU Deni o E 5 2 1 C PM T P UE 5 2 2 SGODUL Applications bs lsm mm alan 5 23 Xilinx Spartan SE XC3S500E VQG100C Features EEN 6 2 4 Xilinx Spartan 3E Disadvantages ANEN 6 2 5 GODIL48 Board with DIL connector Top And Bottom View oo 7 2 6 GODIL50 Board with IDC headers Top And Bottom View oom 8 3 GODIL Board Overview Mr P 9 Sala ei Re e NEE 10 2 KM EE 12 Oo APO GE 13 SS NEE AA NA AA AA AA 14 39 ONG AA AA ANN C E 15 4 About GODIL I O Voltage LAG ena aa Ro na ana ek asa 16 5 Detailed XC3S500E 4VQG100C FPGA Pinout Table ee 17 6 CON4G 1 Left Header Connector Pinout Table 21 7 CON4G 2 Right Header Connector Pinout Table 22 8 CON4GS3 Test Connector Pinout Table 23 9 CONT DIL48 Connector Pinout Table r ane RE 24 10 CONT DIL40 Connector Pinout Table baa LAGARI masa 26 11 CON 1 DIL Connector Layout and Dimensioning r ssssssrssss 28
10. lt 26 gt Connection to the 48 pin DIL plug to pin26 via level shifter RHCLK5 IC1 pin40 67 1 0 LO6P 1 F67 pin lt 27 gt Connection to the 48 pin DIL plug to pin27 via level shifter RHCLK6 IC1 pin39 68 1 0 LOEN 1 F68 pin lt 28 gt Connection to the 48 pin DIL plug to pin28 via level shifter RHCLK7 IC1 pin37 69 IP SW2 sw2 switch 2 low active VREF1 CONS pin14 70 O_LO7P_1 F70 pin lt 29 gt Connection to the 48 pin DIL plug to pin29 via level shifter IC1 pin36 71 O LO7N 1 F71 pin lt 30 gt Connection to the 48 pin DIL plug to pin30 via level shifter IC1 pin35 72 GND GND Connection to the GND Layer of the PCB 73 VCCO 1 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 74 NCCAUX VCC2V5 gt VCCAUX must be 2 5V 75 TMS FTMS FPGA JTAG chain CON2 pin4 JTAG TMS via serial resistor to support 3 3V download via 120ohms adapter 76 TDO FTDO FPGA JTAG chain CON2 pin8 77 TCK FTCK FPGA JTAG chain CON2 pin6 JTAG TCK via serial resistor to support 3 3V download via 120ohms adapter 78 YO LO1P 0 F78 pin lt 34 gt Connection to the 48 pin DIL plug to pin34 via level shifter IC1 pin29 79 l O LOIN O F79 pin lt 35 gt Connection to the 48 pin DIL plug to pin35 via level shifter IC1 pin30 80 VCCINT VCC1V2 SS Internal core Voltage 1 2V 81 GND GND Connection to the GND Layer of the PCB 82 VCCO 0 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 83 I O_LO2P_0 F83 pin lt 33 gt Connection to the 48 pin DIL plug to pin
11. lt 36 gt P4 I O pin lt 41 gt B8 D8 V pin lt 35 gt B9 D9 pin lt 40 gt I O P2 pin lt 34 gt P3 I O pin lt 39 gt B10 D10 pin lt 33 gt B11 D11 pin lt 38 gt I O P98 pin lt 32 gt P92 I O pin lt 37 gt B12 D12 pin lt 31 gt B13 D13 pin lt 50 gt Input only P88 not on DIL P85 I O pin lt 36 gt B14 D14 pin lt 30 gt B15 D15 pin lt 35 gt UO P79 pin lt 29 gt P78 I O pin lt 34 gt B16 D16 pin lt 28 gt B17 D17 pin lt 33 gt I O P83 pin lt 27 gt P84 I O pin lt 32 gt B18 D18 pin lt 26 gt i GND B19 D19 pin lt 31 gt I O P86 pin lt 25 gt P71 I O pin lt 30 gt B20 D20 pin lt 24 gt GND B21 D21 pin lt 29 gt I O P70 pin lt 23 gt P68 I O pin lt 28 gt B22 D22 pin lt 22 gt GND B23 D23 pin lt 27 gt I O P67 pin lt 21 gt P66 I O pin lt 26 gt B24 D24 GND D25 pin lt 25 gt I O P65 As an example to put VCC 5V D2 and D3 or D3 and D4 GOP XC3S200 USER S MANUAL 0 91 Page 22 of 37 to a GODIL40 module on pin 40 place a jumper between header pins OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 8 CON4G 3 Test Connector Pinout Table Pin FPGApin Schema UCF function net name port Comment routed to name E1 GND GND Power ground plane connection E2 I O_LO8N_2 VS1 tvs1 TUSB3410 I2C connection over analog switch VS1 IC10 p
12. modules can be assembled with the following Spartan 3E FPGAs XC3S500E VQG100C XC3S250E_VQG100C XC3S100E VQG100C The SPI Flash M25P32 is assembled for XC3S500E FPGAs The SPI Flash M25P16 is assembled for XC3S250E and XC3S100E FPGAs Different sizes like M25P40 for faster erase time can be custom assembled level shifter can be omitted and an industrial version of the whole module can be ordered please talk to us For a future extension an USB full speed interface option is planned Table of orderable GODIL standard options Ordering code Connector type Comment GODIL XC3S500E plain board 500k S3E FPGA without connectors GODIL XC3S250E 250k S3E FPGA without connectors GODIL40 XC3S500E 40 pin DIL mounted 500k S3E FPGA bottom 40DIL connector top headers GODIL40 XC3S250E 250k S3E FPGA bottom 40DIL connector top headers GODIL48 XC3S500E 48 pin DIL mounted 500k S3E FPGA bottom 48DIL connector top headers GODIL48 XC3S250E 250k S3E FPGA bottom 48DIL connector top headers GODIL50 XC3S500E 2 x 50 pin female 500k S3E FPGA 2x bottom female headers 50 pin GODIL50 XC3S250E headers mounted 250k S3E FPGA 2x bottom female headers 50 pin A XC3S100E FPGA can be ordered from 10 pieces A 3 3V version without level shifters can be ordered from 10 pieces GOP XC3S200 USER S MANUAL 0 91 Page 34 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho e
13. not affected The level shifters introduce a delay of 0 25ns maximum Further on the shifters do not clamp the outputs to their VCC of 3 3V They can be lifted up by pullups to a maximum of 7V The GODIL module I Os have 1 5k pullups to 5V The level shifters can be bypassed by soldering 0603 resistors in parallel to the shifter for any UO if higher source currents are needed GOP XC3S200 USER S MANUAL 0 91 Page 16 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 Detailed XC3S500E 4VAG100C FPGA Pinout Table Pin FPGApin Schema UCF function net name port Comment routed to name 1 PROG B prog FPGA configuration reset signal active low can be driven CONS pin13 by the TUSB3410 or SW2 by jumper 2 l O L01P 3 F02 pin lt 40 gt Connection to the 48 pin DIL plug to pin40 via level shifter IC3 pin54 3 O LOIN 3 F03 pin lt 39 gt Connection to the 48 pin DIL plug to pin39 via level shifter IC3 pin53 4 O LO2P 3 F04 pin lt 41 gt Connection to the 48 pin DIL plug to pin41 via level shifter IC3 pin52 5 I O LO2N 3 F05 pin lt 42 gt Connection to the 48 pin DIL plug to pin42 via level shifter VREF3 IC3 pin51 6 VCCINT VCC1V2 Internal core Voltage 1 2V 7 GND GND Connection to the GND Layer of the PCB 8 VCCO 3 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 9 I O_LO3P_3 F09 pin lt
14. 0 USER S MANUAL 0 91 Page 27 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 11 CON 1 DIL Connector Layout and Dimensioning GODIL48 module top view for 48 pin DIL mode CD w Ei HHHHH Moge tone Nono fe heleke Hole kelelle le No Lolo lolol GOE OC0000000000002000000000000 0 63 0mm 74 0mm s 76 5Mmm max DDDDDDDDDDDDDDDDDDDDDDDDD SL EDD E ED DE DEE DE ED EE DEI DEE E E E LG ogetehesspohen op em Cr e J gt 28 0mm 33 0mm GOP XC3S200 USER S MANUAL 0 91 Page 28 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de GODIL40 module top view for 40 pin DIL mode 69 0mm 74 0mm s 76 5mm max SEI EA E E EA EA E EL EL EI EK EX EA E Ei EL EI D E EI EL Oo a n 3 SET OOOO0OoOoOO0O0oOO0OO0O0O0OO Oo D Ee SEI EIDEI DD E EE OB fo Do GO EE 09 0 DE DE du impnmmpuuuugadd vj kl 28 0mm 33 0mm 12 FPGA Design Support VHDL and UCF design templates for 50 48 and 40 pin configurations are available GOP XC3S200 USER S MANUAL 0 91 Page 29 of 37 Schematics Z T n us G 8G 0 6007 80 9T og 8k 11009 r4aquiny iueun2og 200 11009 UL NYHIYO TZZ98 JazoyziapueyN hq ubrs q 8149 125910 470PNY Z 9 N09 DND NO0I110 NODYIDHNI 201 MINOGLMIT3 0HO se 200000000000000 00000000000 T 9 NOJ ZEdGEH 9TdGZH
15. 0 pin DIL plug to pin34 via level shifter IC1 pin29 29 IO LO1N O F79 pin lt 29 gt Connection to the 40 pin DIL plug to pin35 via level shifter IC1 pin30 30 1 0 LOSP O F85 pin lt 30 gt Connection to the 40 pin DIL plug to pin36 via level shifter GCLK6 IC1 pin33 31 UO F92 pin lt 31 gt Connection to the 40 pin DIL plug to pin37 via level shifter IC3 pin50 32 1 0 LO7P 0 F98 pin lt 32 gt Connection to the 40 pin DIL plug to pin38 via level shifter GCLK2 IC3 pin34 33 IO LO1N 3 F03 pin lt 33 gt Connection to the 40 pin DIL plug to pin39 via level shifter IC3 pin53 34 1 0 LO1P 3 F02 pin lt 34 gt Connection to the 40 pin DIL plug to pin40 via level shifter IC3 pin54 35 I O LO2P 3 F04 pin lt 35 gt Connection to the 40 pin DIL plug to pin41 via level shifter IC3 pin52 36 IO LO2N 3 F05 pin lt 36 gt Connection to the 40 pin DIL plug to pin42 via level shifter VREF3 IC3 pin51 37 1 0 LO5P O F90 pin lt 37 gt Connection to the 40 pin DIL plug to pin43 via level shifter GCLK10 IC3 pin48 38 1 0 LOSP 3 F09 pin lt 38 gt Connection to the 40 pin DIL plug to pin44 via level shifter LHCLKO IC3 pin47 39 I O_LO3N_3 F10 pin lt 39 gt Connection to the 40 pin DIL plug to pin45 via level shifter LHCLK1 IC3 pin46 40 l O LO4P 3 F11 pin lt 40 gt Connection to the 40 pin DIL plug to pin46 via level shifter LHCLK2 IC3 pin45 GOP XC3S20
16. 3 F05 pin lt 42 gt Connection to the 48 pin DIL plug to pin42 via level shifter VREF3 IC3 pin51 43 O L05P 0 F90 pin lt 43 gt Connection to the 48 pin DIL plug to pin43 via level shifter GCLK10 IC3 pin48 44 IO LOS3P 3 F09 pin lt 44 gt Connection to the 48 pin DIL plug to pin44 via level shifter LHCLKO IC3 pin47 45 1 0 LOSN 3 F10 pin lt 45 gt Connection to the 48 pin DIL plug to pin45 via level shifter LHCLK1 IC3 pin46 46 l O LO4P 3 F11 pin lt 46 gt Connection to the 48 pin DIL plug to pin46 via level shifter LHCLK2 IC3 pin45 47 l O LO4N 3 F12 pin lt 47 gt Connection to the 48 pin DIL plug to pin47 via level shifter LHCLK3 IC3 pin44 48 l O LO5N O0 F91 pin lt 48 gt Connection to the 48 pin DIL plug to pin48 via level shifter GCLK1 1 IC3 pin43 GOP XC3S200 USER S MANUAL 0 91 Page 25 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 10 CON1 DIL40 Connector Pinout Table Pin FPGA pin Schema UCF function net name port Comment routed to name 1 l O LO4N 3 F16 pin lt 1 gt Connection to the 40 pin DIL plug to pin3 via level shifter LHCLK5 IC3 pin40 2 l O LOEN O F95 pin lt 2 gt Connection to the 40 pin DIL plug to pin4 via level shifter IC3 pin39 3 l O LO4N 3 F18 pin lt 3 gt Connection to the 40 pin DIL plug to pind via level shifter LHCLK7 IC3 pin37 4 1 0 LO4N
17. 3 F17 pin lt 4 gt Connection to the 40 pin DIL plug to pin6 via level shifter LHCLK6 IC3 pin36 5 I O LOGP O F94 pin lt 5 gt Connection to the 40 pin DIL plug to pin7 via level shifter IC3 pin35 6 I O LO7P 3 F22 pin lt 6 gt Connection to the 40 pin DIL plug to pin8 via level shifter IC3 pin33 7 I O LO7N 3 F23 pin lt 7 gt Connection to the 40 pin DIL plug to pin9 via level shifter IC3 pin32 8 l O LO3N 2 F33 pin lt 8 gt Connection to the 40 pin DIL plug to pin10 via level shifter GCLK13 IC3 pin30 9 I O LOSP 2 F32 pin lt 9 gt Connection to the 40 pin DIL plug to pin11 via level shifter GCLK12 IC3 pin29 10 UO F34 pin lt 10 gt Connection to the 40 pin DIL plug to pin12 via level shifter IC3 pin31 11 O_LO6P_2 F40 pin lt 11 gt Connection to the 40 pin DIL plug to pin13 via level shifter GCLK2 IC1 pin46 12 1 0 LOGN 2 F41 pin lt 12 gt Connection to the 40 pin DIL plug to pin14 via level shifter GCLK3 IC1 pin54 13 l O LO7N 3 F36 pin lt 13 gt Connection to the 40 pin DIL plug to pin15 via level shifter GCLK15 IC1 pin53 14 l O L04P 2 F35 pin lt 14 gt Connection to the 40 pin DIL plug to pin16 via level shifter GCLK14 IC1 pin52 15 l O LOIP 1 F53 pin lt 15 gt Connection to the 40 pin DIL plug to pin17 via level shifter IC1 pin51 16 l O LO1N 1 F54 pin lt 16 gt Connection to the 40 pin DIL plug to pin18 via level shifter IC1 pin50 17 1 0 Lo2P 1 F57 pin lt 17 gt
18. 3 and D13 both are GCLK inputs and in a regular grid GND and VCC connections With 2 54mm 0 1 jumpers GND and VCC must be plugged accordingly to the emulated DIL device to supply the module with 3 5 5V There are two DIL connectors a 48 pin connector and a 40 pin connector which mechanically also allows for a USB option In an IDC only application it is recommended to solder 2 female headers on the bottom side no DIL connector must be assembled The I Os of the FPGA are fed through level shifter devices 74CB3T 16211 which makes the FPGA 1 Os tolerant to input voltages up to 7V These level shifters can be bypassed through 0603 series resistors all l Os as a custom assembly or selected signals in the lab Please note that the level shifter devices reduce the ability of the FPGA I Os to source current but sink current is not affected Some dual purpose I Os are used on the test connector see the mentioned chapter A crystal oscillator with an output frequency of 49 152MHz is connected to GCLK9 of the FPGA That oscillator must be enabled by a jumper on CONS 1 2 There are 2 small tactile switches for user interaction connected to FPGA input only pins SW1 is a high active signal which is also connected to the TUSB3410 DSR input SW2 is a low active signal which can be jumpered on CONG for resetting the TUSB3410 or reconfiguation of the FPGA see the SPI port chapter GOP_XC3S200 USER S MANUAL 0 91 Page 10 of 37 OHO
19. 33 via level shifter GCLK4 IC1 pin31 84 UO LO2N O F84 pin lt 32 gt Connection to the 48 pin DIL plug to pin32 via level shifter GCLK5 IC1 pin32 85 IO LOSP O F85 pin lt 36 gt Connection to the 48 pin DIL plug to pin36 via level shifter GCLK6 IC1 pin33 86 l O LO3N O F86 pin lt 31 gt Connection to the 48 pin DIL plug to pin31 via level shifter GOP XC3S200 USER S MANUAL 0 91 Page 19 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de GCLK7 IC1 pin34 87 GND GND Connection to the GND Layer of the PCB pa Wa SE alo external input only at connector D13 PIN lt 50 gt via pin50 series resistor of 120ohms 89 I O_LO4N_0 F89 m49 XOSC crystal oscillator input GCLK9 90 I O_LO5P_0 F90 pin lt 43 gt Connection to the 48 pin DIL plug to pin43 via level shifter GCLK10 IC3 pin48 91 l O LO5N O F91 pin lt 48 gt Connection to the 48 pin DIL plug to pin48 via level shifter GCLK11 IC3 pin43 92 UO F92 pin lt 37 gt Connection to the 48 pin DIL plug to pin37 via level shifter IC3 pin50 93 GND GND Connection to the GND Layer of the PCB 94 I O_LO6P_0 F94 pin lt 7 gt Connection to the 48 pin DIL plug to pin7 via level shifter IC3 pin35 95 I O_LO6N_0 F95 pin lt 4 gt Connection to the 48 pin DIL plug to pin4 via level shifter IC3 pin39 96 VCCAUX VCC2V5 VCCAUX must be 2 5V 97 VCCO 0 VCC3V3 LV
20. AL 0 91 Page 7 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 6 GODIL50 Board with IDC headers Top And Bottom View GOP XC3S200 USER S MANUAL 0 91 Page 8 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 GODIL Board Overview 2mm 14pin 2 54mm 9pin 2mm 14pin JTAG PORT TestConnector SPI PORT eeeeeee 10000002 0000000020 eee e le e e e e e 0 1 e e 0 q IDC u Cu uc IDC conn optional conn ector e 2 ME ector ee 9 43 40 pin 9 pin md pin e dil for socket for vec lt gt lt vec amp e amp gnd e gnd access jumper 10 max 459 jumper FPGA or or e pins general e general purpose e 09 gap purpose I Os O O 1 Os 6 e e e o GOP XC3S200 USER S MANUAL 0 91 Page 9 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 1 YO Distribution 48 I Os of the Xilinx XC3S500E 4VQG100C FPGA are attached commonly to 2 different connector types to a SMD DIL connector CON1 with 48 or 40 pins or to two 50 pin IDC headers CON4G 1 and CON4G 2 In a DIL application beside the DIL connector also 2 IDC male headers must be soldered on the PCB top side These IDC connectors contain the 48 I Os 2 extra input only pins C1
21. CE pin13 handskae signal LED6 also controls red led6 26 O_LO2P_2 DOUT pin lt i gt Connection to the 48 pin DIL plug to pin1 via level shifter DOUT IC3 pin42 27 ka a ae tmosi SPI Flash MOSI Pin E4 testconnector over 330 ohms GOP XC3S200 USER S MANUAL 0 91 Page 17 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 28 VCCINT VCC1V2 Internal core Voltage 1 2V 29 GND GND Connection to the GND Layer of the PCB 30 IP RTS rts TUSB3410 output Ready to Send VREF2 IC6 pin20 handshake signal led5 also controls red led5 31 VCCO 2 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 32 I O_LO3P_2 F32 pin lt 11 gt Connection to the 48 pin DIL plug to pin11 via level shifter GCLK12 IC3 pin29 33 l O LO3N 2 F33 pin lt 10 gt Connection to the 48 pin DIL plug to pin10 via level shifter GCLK13 IC3 pin30 34 UO F34 pin lt 12 gt Connection to the 48 pin DIL plug to pin12 via level shifter IC3 pin31 35 YO L04P 2 F35 pin lt 16 gt Connection to the 48 pin DIL plug to pin16 via level shifter GCLK14 IC1 pin52 36 l O LO7N 3 F36 pin lt 15 gt Connection to the 48 pin DIL plug to pin15 via level shifter GCLK15 IC1 pin53 37 GND GND Connection to the GND Layer of the PCB 38 IP_L05P_2 F38 c13 GCLK0 CON4G 1 external input SE C13 PIN lt 49 gt via pinag series resistor o ohms 39 IP L05P 2 SW1 swi switch 1 hig
22. CMOS33 LVTTL I O Voltage 3 3V 98 I O_LO7P_0 F98 pin lt 38 gt Connection to the 48 pin DIL plug to pin38 via level shifter GCLK2 IC3 pin34 99 I O_LO7N_0 HSW thsw HSWAP configuration mode pin driven low during HSWAP configuration by D1 T1G 2 Pin E8 testconnector over 330 ohms 100 TDI FTDI FPGA JTAG chain CON2 pin10 JTAG TDI via serial resistor to support 3 3V download via 120ohms adapter GOP XC3S200 USER S MANUAL 0 91 Page 20 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 6 CON4G 1 Left Header Connector Pinout Table FPGA pin Direction Signal name Pin row Pin row Signal name Direction FPGA pin 48 40pins C A 48 40pins P26 I O pin lt 1 gt C1 A1 V C2 A2 in lt 2 gt I O P15 P16 I O pin lt 3 gt C3 A3 GND pin 1 V4 C4 A4 pin 4 I O P95 pin lt 2 gt P18 I O pin lt 5 gt C5 A5 GND E pin lt 3 gt Va C6 A6 pin lt 6 gt I O P17 pin lt 4 gt P94 I O pin lt 7 gt C7 A7 GND pin lt 5 gt I C8 A8 pin lt 8 gt I O p22 pin lt 6 gt P23 I O pin 9 C9 A9 GND pin lt 7 gt I C10 A10 pin lt 10 gt I O P33 pin lt 8 gt P32 I O pin lt 11 gt C11 A11 SND pin lt 9 gt I V C12 A12 pin lt 12 gt I O P34 pin lt 10 gt P38 Input only pin lt
23. E LC Gti S96 B C NIN NIM oan es CJ E TITI St Sd CC st GAT ES NIN NIN i GT C NIN E 69H C NIN NIV Gay ees T64 Ino cu CH va SAN ru GZNI SENI SAY by 2ENI SAT SCHT GENI DCHT SAN E TENI ZENI ECHT SCHT SENI SENI A Did une Gad ZENIT SENI SENI GENI TENI ENI ENI SAT bNI SENI GAT SNI 2 NI BENI C G BOSS S 89 80 600c 80 9T eg 84 11009 LASGWNN iueun2og TU 2292200 TPL 300 11909 31LII soar poor peer peor too NYHIYO TZ 88 49j0uz epueg 4 hg ubtsaq a seo sen e9 f seo sed 8 AIS TSS8TG TOPNY MINOG LMIT3 0HO 5 5 Page 31 of 37 LA 1S8CTO lc LBE UNM Hn T1 x1 ONS 29n BIN INAS dWOI 009d NHn3 xeu HUDD nc 1NIIIN nee Tute t sad Tea lo z86Ed1 135 INO 22 UND xew Uu NOHS NI d P imnbs INO xnu33n 090 200 8S13 IS uds 13539 dJ ld dM1ZIHYM NIS DND DN KO 1NOS dd vin BTLEASNL und ROL 8Taan 110419 Pal JIN 81531 ON3dSNS PISIL N3938n SININ 8 8Sn OCE LI Bi 5TH Na Traa peiunou ou ZHUZT SBONS d rnz Ute xeu guggg nee IK ezo zzo 0 1 29N D 135 Ino JI UND T3 ZBZIANd NOHS NI 4 Iu i linga Ino ra
24. Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de The following table show the function of the various status leds led colour function 1 green lights when the FPGA is configurd 2 red lights when the FPGA is NOT configurd 3 red SIN signals serial data sent from the FPGA to the TUSB3410 also available on non USB modules 4 red SOUT signals serial data from the TUSB3410 to the FPGA also available on non USB modules but not usable 5 red RTS signals serial handshake sent from the FPGA to the TUSB3410 also available on non USB modules 6 red CTS signals serial handshake sent from the TUSB3410 to the FPGA also available on non USB modules but not usable 7 red DTR signals FPGA reconfiguration sent from the TUSB3410 to the FPGA also available on non USB modules but not usable 8 green VS2 is a free signal on the FPGA rarely used for I2C eeprom programming with the USB option 9 red CSO signals access of the SPI FLASH can be during configuration or by FPGA user activity on the I O pin 10 red normally not mounted 11 red normally not mounted As a future option a full speed USB interface is available on the bottom side of the board GOP XC3S200 USER S MANUAL 0 91 Page 11 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 2 Test connector 7 Os are available to the front side tes
25. GODIL USER MANUAL V 0 91 OHO Elektronik www oho elektronik de Author M Randelzhofer OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO Elektronik Michael Randelzhofer Rudolf Diesel Str 8 85221 Dachau Germany WEB www oho elektronik de EMAIL info oho elektronik de Phone 49 8131 339230 FAX 449 8131 339294 2005 2009 OHO Elektronik Michael Randelzhofer All rights reserved Disclaimer Under no circumstances OHO Elektronik Michael Randelzhofer is liable for conseguential costs losses damages lost profits Any schematics pcb or program parts are under the copyright of OHO Elektronik Michael Randelzhofer and can only be reproduced by permission of this company The contents of this USER S MANUAL are subject to change without notice However the main changes are listed in the revision table at the end of this document Products of OHO Elektronik Michael Randelzhofer are not designed for use in life support systems where malfunction of these products could result in personal injury The products of OHO Elektronik Michael Randelzhofer are intended for use in a laboratory test environment or for OEM s only They can generate radio freguency energy depending on the downloaded design and application which can disturb local radio or TV eguipment and so they have not been tested to be CE compliant If you encounter any technical problems or mistakes in this
26. I FLASH Operating voltage from 3 5V to 5 5V switching regulator for core voltage 1 2V Voltage translators for 5V UO compatibility pullups to 5V Voltage translators can be selectively bridged by series resistors Onboard clock oscillator with 49 152 MHz for audio or RS232 applications up to 9 status or user leds 2 user tact switches 2 configuration jumper A 9 pin test connector for probing internal signals or using the OHO DY1 debug display Reverse plug in protection Easy to reuse Professional design manufactured on a 4 layer PCB made in Germany GODIL Applications Replacement of discontinued 24 48 pin 0 6 DIL devices IP core development system for legacy or brand new DIL chips OEM Spartan 3E FPGA module with up to 48 l O s and 2 input onlies Fast evaluation of Xilinx Spartan 3E FPGA s Hardware platform for VHDL VERILOG logic design courses Robotics High logic density applications at tight space constraints GOP_XC3S200 USER S MANUAL 0 91 Page 5 of 37 2 3 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de Xilinx Spartan 3E XC3S500E_VQG100C Features Document 1 lists lots of goodies here are the best facts VV VVVVVVV V 2 4 Modern SRAM based 90nm 500k Gate low cost FPGA 9312 4 input function generators 4656 can be RAM or dual ported RAM or shift registers SPI FLASH can be used as configuration memory SelectRAM hierarchical memory 20 x 18kbit Blockram 73kbit
27. Katia Dem Gute D22n ONS INIJIN Ess O T Dot 07I O T a790dd o nen 0 1 Tat 86 65 Bet AGT SWLI AILA TZNId BZNId 6TNId 8TNId ZTNId 9TNId STNId tNId Pano ETNId talya BAZA ENEN az 1014 enin Snzn ONS enm 65NId 919 en anza ZTNId GT TENId UNId anza 6 NId 8 NId Z NId 3 NId S NId ENEN T eere sene ENEN ZNTN NId ENEN NId E NId 3 es enm spe era aro las UKS T a ener T NId 9078 T CH NIN NIN oan Gata 894 9 8v CH bard 994 Z9 9b9 tata TA NIN NI oan Tata 294 T9 894 09 br A CJ Bata SIT 66H NIN NIN Crd AA Tra d 88 86H TA Ord Td 2G 96H A 8 u c NIN NIV oan aga 984 G eeu ocu 60 9t CC b84 64 FEH 84 GE e u pir h NIN NIN SAT 68a 824 SE EET eeu CH EEN 62d Tb Wd L at 683 rat CO 9cu uacit8d 884 OCI BEI CH 64 E bhzd CH 8t asa CC 864 ZE NIN ec I 64 EE geu C4 ceu pai CH reu L 284 ez 8Td CH boi cc 9T 803 v6 bT C4 geu C SAT 69H 063 20 ZTO NIN NIN 603 8T NIN DS LO C 89H C 99t ZE DD FE
28. LO4N 3 F18 pin lt 5 gt Connection to the 48 pin DIL plug to pind via level shifter LHCLK7 IC3 pin37 6 l O LO4N 3 F17 pin lt 6 gt Connection to the 48 pin DIL plug to pin6 via level shifter LHCLK6 IC3 pin36 7 O LO6P O F94 pin lt 7 gt Connection to the 48 pin DIL plug to pin7 via level shifter IC3 pin35 8 I O LO7P 3 F22 pin lt 8 gt Connection to the 48 pin DIL plug to pin8 via level shifter IC3 pin33 9 I O LO7N 3 F23 pin lt 9 gt Connection to the 48 pin DIL plug to pin9 via level shifter IC3 pin32 10 l O LO3N 2 F33 pin lt 10 gt Connection to the 48 pin DIL plug to pin10 via level shifter GCLK13 IC3 pin30 11 l O Lo3P 2 F32 pin lt 11 gt Connection to the 48 pin DIL plug to pin11 via level shifter GCLK12 IC3 pin29 12 UO F34 pin lt 12 gt Connection to the 48 pin DIL plug to pin12 via level shifter IC3 pin31 13 l O LO6P 2 F40 pin lt 13 gt Connection to the 48 pin DIL plug to pin13 via level shifter GCLK2 IC1 pin46 14 l O LOGN 2 F41 pin lt 14 gt Connection to the 48 pin DIL plug to pin14 via level shifter GCLK3 IC1 pin54 15 l O LO7N 3 F36 pin lt 15 gt Connection to the 48 pin DIL plug to pin15 via level shifter GCLK15 IC1 pin53 16 l O L04P 2 F35 pin lt 16 gt Connection to the 48 pin DIL plug to pin16 via level shifter GCLK14 IC1 pin52 17 1 O LO1P 1 F53 pin lt 17 gt Connection to the 48 pin DIL plug to pin17 via level shifter IC1 pin51 18 l O LO1
29. N 1 F54 pin lt 18 gt Connection to the 48 pin DIL plug to pin18 via level shifter IC1 pin50 19 l O Lo2P 1 F57 pin lt 19 gt Connection to the 48 pin DIL plug to pin19 via level shifter IC1 pin48 20 l O LO2N 1 F58 pin lt 20 gt Connection to the 48 pin DIL plug to pin20 via level shifter IC1 pin47 21 1 0 LOSP 1 F60 pin lt 21 gt Connection to the 48 pin DIL plug to pin21 via level shifter RHCLKO IC1 pin45 22 l O LOSN 1 F61 pin lt 22 gt Connection to the 48 pin DIL plug to pin22 via level shifter RHCLK1 IC1 pin44 23 l O L04P 1 F62 pin lt 23 gt Connection to the 48 pin DIL plug to pin23 via level shifter RHCLK2 IC1 pin43 24 l O LOAN 1 F63 pin lt 24 gt Connection to the 48 pin DIL plug to pin24 via level shifter RHCLK3 IC1 pin42 GOP XC3S200 USER S MANUAL 0 91 Page 24 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 25 1 0 LO5P 1 F65 pin lt 25 gt Connection to the 48 pin DIL plug to pin25 via level shifter RHCLK4 IC1 pin41 26 1 0 LO5N 1 F66 pin lt 26 gt Connection to the 48 pin DIL plug to pin26 via level shifter RHCLK5 IC1 pin40 27 1 0 LO6P 1 F67 pin lt 27 gt Connection to the 48 pin DIL plug to pin27 via level shifter RHCLK6 IC1 pin39 28 1 0 LOEN 1 F68 pin lt 28 gt Connection to the 48 pin DIL plug to pin28 via level shifter RHCLK7 IC1 pin37 29 1 0 LO7P 1 F70 pin l
30. O LO1P 1 F53 pin lt 17 gt Connection to the 48 pin DIL plug to pin17 via level shifter IC1 pin51 54 UO LOIN 1 F54 pin lt 18 gt Connection to the 48 pin DIL plug to pin18 via level shifter IC1 pin50 GOP XC3S200 USER S MANUAL 0 91 Page 18 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 55 VCCO 1 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 56 VCCINT VCC1V2 Internal core Voltage 1 2V 57 O LO2P 1 F57 pin lt 19 gt Connection to the 48 pin DIL plug to pin19 via level shifter IC1 pin48 58 UO LO2N 1 F58 pin lt 20 gt Connection to the 48 pin DIL plug to pin20 via level shifter IC1 pin47 59 GND GND Connection to the GND Layer of the PCB 60 1 0 LOSP 1 F60 pin lt 21 gt Connection to the 48 pin DIL plug to pin21 via level shifter RHCLKO IC1 pin45 61 l O LO3N 1 F61 pin lt 22 gt Connection to the 48 pin DIL plug to pin22 via level shifter RHCLK1 IC1 pin44 62 IO LO4P 1 F62 pin lt 23 gt Connection to the 48 pin DIL plug to pin23 via level shifter RHCLK2 IC1 pin43 63 1 0 LO4N 1 F63 pin lt 24 gt Connection to the 48 pin DIL plug to pin24 via level shifter RHCLK3 IC1 pin42 64 GND GND Connection to the GND Layer of the PCB 65 IO LO5P 1 F65 pin lt 25 gt Connection to the 48 pin DIL plug to pin25 via level shifter RHCLK4 IC1 pin41 66 UO LOSN 1 F66 pin
31. d with supplies from 3 5 to 5 5 volts since core and auxiliary voltages are generated with on board regulators An onboard switching voltage regulator produces the FPGA core voltage of 1 2V The regulator 6 can source up to 800mA Another 2 low drop regulators generate the VCCAUX voltage of 2 5V and the VCCO voltage of 3 3V sourcing up to 300mA 5 The module has a simple schottky diode as a protection against reverse insertion or reverse power connection Even so care should be taken when plugging the module ATTENTION Please note that a voitage above 6V on the module GND and VCC pins will destroy the voltage regulators on the module Especially the switching regulator is sensitive to overvoltage Therefore the maximum of 5 5V module supply voltage must never be exceeded GOP XC3S200 USER S MANUAL 0 91 Page 15 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 4 About GODIL I O Voltage Levels The Spartan3E FPGA series offer a broad variety of I O voltage standards However on the GODIL module only the LVCMOS33 and LVTTL standards are supported These standards are required for the level shifters 7 for conversion of 5V TTL levels as well as 5V CMOS levels These level shifters work bidirectionally without the need of controlling their direction Please note that the level shifter devices reduces the ability of the FPGA 1 Os to source current sink current is
32. es see 2 3 and 4 Pressing SW1 before powering the GODIL module skips the configuration process and the FPGA awaits configuring from the JTAG port only The JTAG connector has a jumper feature on pins 1 2 which enables programming of the I2C eeprom for the TUSB3410 USB interface with a special FPGA design Pins 12 and 14 of the connector allows measurement of the internal voltages V1V2 and V2V5 only if the USB option is assmbled GOP XC3S200 USER S MANUAL 0 91 Page 13 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 3 4 SPI Port The onboard SPI Flash M25P16 or M25P32 can be programmed directly with Software versions prior to ISE10 1 via the SPI port CON3 When using the Xilinx USB II programmer insure that pin13 is grounded which holds the FPGA in a reset state during programming When the port is not used some jumper positions at CON3 are used for the following module features CONS pin1 2 enables the onboard crystal oscillator CONS pin13 14 allows SW to reconfigure the FPGA CONS pin12 14 allows SW2 to reset the TUSB3410 CONS pin1 1 12 always resets the TUSB3410 v v v v Avoid using other jumper positions otherwise the module may not be able to configure from the SPI FLASH GOP XC3S200 USER S MANUAL 0 91 Page 14 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 3 5 Power Supply The module can be powere
33. h active GCLK1 IC6 pin14 also triggers DSR on TUSB3410 M2 also allows FPGA JTAG configuration only when depressed before applying power to the module 40 l O LO6P 2 F40 pin lt 13 gt Connection to the 48 pin DIL plug to pin13 via level shifter GCLK2 IC1 pin46 41 IO LOGN 2 F41 pin lt 14 gt Connection to the 48 pin DIL plug to pin14 via level shifter GCLK3 IC1 pin54 42 1 0 LOGN 2 M1 tm1 M1 configuration mode pin driven low during configuration M1 by D1 T1G 2 Pin E7 testconnector over 330 ohms 43 l O LO7P 2 SIN sin MO configuration mode pin driven high during MO IC6 pin17 configuration by led pullup TUSB3410 serial data input also controls led3 red 44 UO LO7N 2 DIN tdin SPI FLASH data out DIN IC4 pin2 Pin E5 testconnector over 330 ohms 45 VCCO 2 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 46 VCCAUX VCC2V5 VCCAUX must be 2 5V 47 O_LO8P_2 VS2 vs2 TUSB3410 I2C connection over analog switch VS2 IC10 pin2 also controls led8 green led8 48 HO LO8N 2 VS1 tvs1 TUSB3410 I2C connection over analog switch VS1 IC10 pin6 Pin E2 testconnector over 120ohms 49 I O_LO9P_2 VSO tvs0 Pin E3 testconnector over 120ohms VSO 50 I O LO9N 2 CCLK tcclk SPI FLASH configuration clock CCLK IC4 pin6 Pin E6 testconnector over 330ohms 51 DONE DONE FPGA configuration ready strobe 1 fpga configured 52 GND GND Connection to the GND Layer of the PCB 53 l
34. in6 Pin E2 testconnector over 120ohms E3 UO Lo9P 2 VSO tvsO Pin E3 testconnector over 120ohms VSO E4 sc us bara tmosi SPI Flash MOSI Pin E4 testconnector over 330 ohms E5 I O LO7N 2 DIN tdin SPI FLASH data out DIN IC4 pin2 Pin E5 testconnector over 330 ohms E6 l O LO9N 2 CCLK tcclk SPI FLASH configuration clock CCLK IC4 pin6 Pin E6 testconnector over 3300hms E7 l O LOEN 2 M1 tm1 M1 configuration mode pin driven low during configuration M1 by D1 T1G 2 Pin E7 testconnector over 330 ohms E8 l O LO7N O HSW thsw 7 HSWAP configuration mode pin driven low during HSWAP configuration by D1 T1G 2 Pin E8 testconnector over 330 ohms E9 VIN VIN 5V input voltage protected by a 0603 Oohm resistor GOP_XC3S200 USER S MANUAL 0 91 Page 23 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 9 CON1 DIL48 Connector Pinout Table Pin FPGApin Schema UCF function net name port Comment routed to name 1 l O Lo2P 2 DOUT pin lt i gt Connection to the 48 pin DIL plug to pin1 via level shifter DOUT IC3 pin42 2 l O LOAN 3 F15 pin lt 2 gt Connection to the 48 pin DIL plug to pin2 via level shifter LHCLK4 IC3 pin41 3 l O LO4N 3 F16 pin lt 3 gt Connection to the 48 pin DIL plug to pin3 via level shifter LHCLK5 IC3 pin40 4 110 LOGN O F95 pin lt 4 gt Connection to the 48 pin DIL plug to pin4 via level shifter IC3 pin39 5 I O
35. lektronik de 16 Technical Specifications FPGA Xilinx XC3S500E 4VAG100C Spartan 3E FPGA or Xilinx XC3S250E 4VAG100C Spartan 3E FPGA or Xilinx XC3S100E 4VQG100C Spartan 3E FPGA Supply Voltage on any PIN 3 5 5 5V Size 74 x 33mm 76 x 33mm incl USB connector Height PCB to Top max 9mm Height PCB to Bottom max 12mm Weight max 30g GOP_XC3S200 USER S MANUAL 0 91 Page 35 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 17 Literature gt 1 DS312 Xilinx Spartan 3E Complete Data Sheet http www xilinx com support documentation data sheets ds312 pdf gt 2 DS097 Xilinx Parallel Cable IV http www xilinx com support documentation data_sheets ds097 paf gt 3 DS300 Xilinx Platform Cable USB http www xilinx com support documentation data_sheets ds300 paf gt 4 DS593 Xilinx Platform Cable USB II http www xilinx com support documentation data_sheets ds593 paf gt 5 LP3982 National Semiconductor LDO CMOS Regulator http www national com ds LP LP3982 pdf gt 6 L6928 ST High Efficiency Monolithic Synchronious Step Down Regulator http www st com stonline products literature ds 1 1051 pdf gt 7 TI SN74CB3T16211 24 Bit Fet Bus Switch http focus ti com lit ds symlink sn74cb3t16211 pdf 8 TI USB Microcontroller http www ti com lit gon tusb3410 GOP_XC3S200 USER S MANUAL 0 91 Page 36 of 37 OHO Elektronik Rudolf Diesel Str 8 D 85221
36. t 29 gt Connection to the 48 pin DIL plug to pin29 via level shifter IC1 pin36 30 l O LO7N 1 F71 pin lt 30 gt Connection to the 48 pin DIL plug to pin30 via level shifter IC1 pin35 31 l O LO3N O F86 pin lt 31 gt Connection to the 48 pin DIL plug to pin31 via level shifter GCLK7 IC1 pin34 32 IO LO2N O F84 pin lt 32 gt Connection to the 48 pin DIL plug to pin32 via level shifter GCLK5 IC1 pin32 33 l O LO2P O F83 pin lt 33 gt Connection to the 48 pin DIL plug to pin33 via level shifter GCLK4 IC1 pin31 34 1 0 LO1P O F78 pin lt 34 gt Connection to the 48 pin DIL plug to pin34 via level shifter IC1 pin29 35 IO LO1N O F79 pin lt 35 gt Connection to the 48 pin DIL plug to pin35 via level shifter IC1 pin30 36 l O LOSP O F85 pin lt 36 gt Connection to the 48 pin DIL plug to pin36 via level shifter GCLK6 IC1 pin33 37 UO F92 pin lt 37 gt Connection to the 48 pin DIL plug to pin37 via level shifter IC3 pin50 38 l O LO7P 0 F98 pin lt 38 gt Connection to the 48 pin DIL plug to pin38 via level shifter GCLK2 IC3 pin34 39 IO LO1N 3 F03 pin lt 39 gt Connection to the 48 pin DIL plug to pin39 via level shifter IC3 pin53 40 WO LO1P 3 F02 pin lt 40 gt Connection to the 48 pin DIL plug to pin40 via level shifter IC3 pin54 41 l O LO2P 3 F04 pin lt 41 gt Connection to the 48 pin DIL plug to pin41 via level shifter IC3 pin52 42 l O LO2N
37. t connector CON4G 3 for debugging purposes These I Os are dual purpose pins in the FPGA configuration phase no active low input must be applied to any pin The test connector is primarily intended for probes to an oscilloscope or logic analyzer But since a power supply is also provided on the connector it is ideally suited for small hardware extensions or debug modules like the 3 digit OHO DY1 display module GOP XC3S200 USER S MANUAL 0 91 Page 12 of 37 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 3 3 JTAG Port The FPGA is the only member in the JTAG chain connected to CON2 The FPGA normally configures from the SPI FLASH devices M25P16 or M25P32 for debugging JTAG configuration is always also possible The SPI Flash can be programmed via its dedicated programming header CON3 However indirect programming via the JTAG chain with ISE10 1 and newer SW is recommended The configuration status of the FPGA is shown by the red status led2 and the green status led1 If the FPGA is not configured red led2 is lit and the green led1 is dark If the FPGA is configured green led1 is lit and the red led2 is dark The FPGA JTAG chain is routed to the Xilinx standard 2mm 14pin JTAG port connector CON by serial resistors enabling JTAG programming with 3 3V voltage levels The 2mm connector is supported by the OHO GOPLCP and the Xilinx products parallel cable IV and platform USB cabl
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