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UM10120 Volume 1: LPC213x User Manual

1. jal Volume 1 Chapter 5 VIC Bit 23 22 21 20 19 18 17 16 Symbol z AD1 BOD I2C1 ADO EINT3 EINT2 Access R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPI SSP SPIO I2C0 PWMO Access R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCore1 ARMCored E WDT Access R W R W R W R W R W R W R W R W Table 35 Software Interrupt register VICSoftlnt address OxFFFF F018 bit description Bit Symbol Value Description Reset value 31 0 See VICSoftInt 0 Do not force the interrupt request with this bit number Writing 0 bit allocation zeroes to bits in VICSoftInt has no effect see VICSoftIntClear table Section 5 4 2 Force the interrupt request with this bit number 5 4 2 Software Interrupt Clear register VICSoftlntClear OXFFFF F01C This register allows software to clear one or more bits in the Software Interrupt register without having to first read it Table 36 Software Interrupt Clear register VICSoftIntClear address OxFFFF F01C bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 Symbol AD1 BOD Il C1 ADO EINT3 EINT2 Access WO WO WO WO WO WO WO WO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPH SSP SPIO I2C0 PWMO Access WO WO WO WO WO WO WO WO Bit 7 6 5 4 3 2 1 0 Symb
2. 00 00 eee 5A 5 6 5 Solution 3 re enable FIQs at the beginning of the 5 4 8 FIQ Status register VICFIQStatus IRQ liandlerz ui iaia ania ONE 61 OxFFFF FO04 0c eee ee eee 55 5 7 VIC usage notes 0c cece cece 61 5 4 9 Vector Control registers 0 15 VICvectCntl0 15 OxFFFF F200 23C 0005 55 Chapter 6 Pin configuration 6 1 LPC2131 2132 2134 2136 2138 pinout 64 6 2 Pin description for LPC2131 2 4 6 8 66 Chapter 7 Pin Connect Block 7 1 Features ii cis isses ir nee Rn 73 7 4 2 Pin function Select register 1 PINSEL1 7 2 Applications 0cccee nanan 73 OxE002 C004 eee eee 75 73 Description a n nanna nanna nannan 73 743 Pin function Select register 2 PINSEL2 74 Regi d ipti 73 OxE002 C014 0 0 e eee 77 egister escrip lOM a te oe ee a eae est 7 4 4 Pin function select register values 78 7 4 1 Pin Function Select Register 0 PINSELO OxE002 CO00 022 0c 74 Chapter 8 General Purpose Input Output ports GPIO 8 1 FO atures ac core Rem ds 79 8 4 Register description 79 8 2 Applications llle 79 8 4 1 GPIO Pin Value register 0 and 1 IOOPIN 8 3 Pin description 00seeeeeeee 79 OxEO02 8000 and IO1PIN OxE002 8010 80 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 264 Philips Semiconductors UM1
3. 9 4 Architecture The architecture of the UARTO is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UARTO The UARTO receiver block UORX monitors the serial input line RXDO for valid input The UARTO RX Shift Register UORSR accepts valid characters via RXDO After a valid character is assembled in the UORSR it is passed to the UARTO RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UARTO transmitter block UOTX accepts data written by the CPU or host and buffers the data in the UARTO TX Holding Register FIFO UOTHR The UARTO TX Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TXDO The UARTO Baud Rate Generator block UOBRG generates the timing enables used by the UARTO TX block The UOBRG clock input source is the VPB clock PCLK The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers UOIER and UOIIR The interrupt interface receives several one clock wide enables from the UOTX and UORX blocks Status information from the UOTX and UORX is stored in the UOLSR Control information for the UOTX and UORX is stored in the UOLCR Koninklijke Philips Electronics N V 2005 All rights reserved User
4. 35 Table 25 Reset Source identificator Register RSIR address OxEO1F C180 bit description 37 Table 26 VPB divider register map 38 Table 27 VPB Divider register VPBDIV address OxEO1F C100 bit description 39 Table 28 MAM Responses to program accesses of various YDES cioe rcr ERA pp 45 Table 29 MAM responses to data and DMA accesses of various types sseseeeeeee rene 45 Table 30 Summary of MAM registers 46 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 MAM Control Register MAMCR address OxEO1F C000 bit description 46 MAM Timing register MAMTIM address OxEO1F C004 bit description 46 VIC register map 0 0c eee eee 49 Software Interrupt register VICSoftInt address OxFFFF F018 bit allocation 50 Software Interrupt register VICSoftInt address OxFFFF F018 bit description 51 Software Interrupt Clear register VICSoftIntClear address OxFFFF FO01C bit allocation 51 Software Interrupt Clear register VICSoftIntClear address OxFFFF F010C bit description 51 Raw Interrupt status register VICRawintr addre
5. SYSTEM CONTROL BLOCK OxEO1F FFFF VPB PERIPHERAL 127 VPB PERIPHERALS 428 126 NOT USED 0xE007 0000 VPB PERIPHERAL 27 OxE006 C000 SSP VPB PERIPHERAL 25 OxEO006 4000 10 BIT AD1 LPC2138 VPB PERIPHERAL 24 0xE006 0000 PC1 VPB PERIPHERAL 14 22 0xE003 8000 VPB PERIPHERAL 13 0xE003 4000 VPB PERIPHERAL 12 0xE003 0000 VPB PERIPHERAL 11 OxE002 C000 VPB PERIPHERAL 10 0xE002 8000 VPB PERIPHERAL 9 0xE002 4000 VPB PERIPHERAL 8 OxE002 0000 VPB PERIPHERAL 7 OxE001 C000 VPB PERIPHERAL 6 0xE001 8000 VPB PERIPHERAL 5 0xE001 4000 VPB PERIPHERAL 4 0xE001 0000 VPB PERIPHERAL 3 0xE000 C000 VPB PERIPHERAL 2 0xE000 8000 VPB PERIPHERAL 1 0xE000 4000 VPB PERIPHERAL 0 0xE000 0000 Fig 5 VPB peripheral map Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 11 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 2 Memory map 2 2 LPC2131 2132 2134 2136 2138 memory re mapping and boot block 2 2 1 Memory map concepts and operating modes The basic concept on the LPC2131 2 4 6 8 is that each memory area has a natural location in the memory map This is the address range for which code residing in that area is written The bulk of each memory space remains permanently fixed in the same location eliminating the need to have portions of the code designed to run in different address ranges Because of the location of the interr
6. cece eee 90 UARTO Line Control Register UOLCR OxE000 COOC annann 90 UARTO Line Status Register UOLSR OxE000 C014 Read Only 91 UARTO Scratch pad register UOSCR OxE000 CO1C 1 eee 92 UARTO Transmit Enable Register UOTER OxE000 C030 eee eee eee 93 Architecture 0000 eee eee eee 93 Chapter 10 Universal Asynchronous Receiver Transmitter 1 UART1 10 1 FealUr S scsu o o ne eee ae 95 10 3 7 UART1 FIFO Control Register U1FCR 10 2 Pindescription 002000 95 OxE001 0008 102 10 3 Register description 55 gg 10 3 8 UART1 Line Control Register UTLCR OxE001 000C sseulssessssn 103 10 3 1 UART1 R Buffer R 1RBR DRE DOUH MEER peus ie Only 98 1099 UART1 Modem Control Register U1MCR 10 3 2 UART1 Transmitter Holding Register U1THR CRED PEND ER Ge 9900 Only sansa OxEO01 0000 when DLAB 0 Write Only 98 10 3 10 UART1 Line Status Register U1LSR 10 3 3 UART1 Divisor Latch Registers 0 and 1 U1DLL 0xE001 0014 Read Only isinsi nui 104 0xE001 0000 and U1DLM 0xE001 0004 when 10 3 11 UART1 Modem Status Register U1MSR DLAB 1 98 OxE001 0018 LPC2134 6 8 only 106 10 34 UART1 Baud rate calculation g9 10 312 UARTI Eben pad register UTSCR 2 U OxE001 001C 02 106 10 3 5 ART1 I Enable R 1IER E dos hen DLAB OI U gg 10 3 13 UART1 Transmit E
7. 31 21 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 15 4 8 PWM Control Register PWMPCR 0xE001 404C The PWM Control Register is used to enable and select the type of each PWM channel The function of each of the bits are shown in Table 159 Table 159 PWM Control Register PWMPCR address 0xE001 404C bit description Bit Symbol Value Description Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 2 PWMSEL2 1 Selects double edge controlled mode for the PWM 2 output 0 0 Selects single edge controlled mode for PWM2 3 PWMSELS 1 Selects double edge controlled mode for the PWMS output 0 0 Selects single edge controlled mode for PWM3 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 190 Philips Semiconductors UM10120 ja Volume 1 Chapter 15 PWM Table 159 PWM Control Register PWMPCR address 0xE001 404C bit description Bit Symbol Value Description Reset value 4 PWMSEL4 1 Selects double edge controlled mode for the PWM4 output 0 0 Selects single edge controlled mode for PWM4 5 PWMSEL5 1 Selects double edge controlled mode for the PWM5 output 0 0 Selects single edge controlled mode for PWM5 6 PWMSEL6 1 Selects double edge con
8. Bit Symbol Description Reset value 4 0 MSEL PLL Multiplier value Supplies the value M in the PLL frequency 0 calculations Note For details on selecting the right value for MSEL see Section 3 7 9 PLL frequency calculation on page 31 6 5 PSEL PLL Divider value Supplies the value P in the PLL frequency 0 calculations Note For details on selecting the right value for PSEL see Section 3 7 9 PLL frequency calculation on page 31 7 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined PLL Status register PLLSTAT OXEO1F C088 The read only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read as well as the PLL status PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see Section 3 7 7 PLL Feed register PLLFEED OxEO1F CO8C Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 29 Philips Semiconductors UM1 01 20 ja Volume 1 3 7 5 3 7 6 3 7 7 Chapter 3 System Control Block Table 16 PLL Status register PLLSTAT address 0xE01F C088 bit description Bit Symbol Description Reset value 4 0 MSEL Read back for the PLL Multiplier value This is the value currently 0 used by the PLL 6 5 PSEL Read back
9. Allows individual pin configuration 7 2 Applications The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions 7 3 Description The pin connect block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin The only partial exception from the above rule of exclusion is the case of inputs to the A D converter Regardless of the function that is selected for the port pin that also hosts the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings However valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case proper interface circuit is active in between the physical pin and the A D module In all other cases a part of digital logic necessary for the digital function to be performed will be active and will disrupt proper behavior of the A D 7 4 Regi
10. User manual Rev 01 24 June 2005 127 Philips Semiconductors UM10120 ie Volume 1 Chapter 11 I C interfaces Reception of the own Slave Address and one or more Da bytes all are acknowledged more Data bytes DATA A e Last data byte received is yd Not Acknowledged gt A PORS Arbitration lost as Master and addressed as Slave Reception of the General Call address and one or gt GENERAL CALL Last data byte is Not A PORS Acknowledged Arbitration lost as Master and addressed as Slave by A General Call Fig 31 Format and States in the Slave Receiver mode 88H gt l From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits This number contained in I2STA corresponds to a defined state of th bus Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 128 Philips Semiconductors UM1 01 20 m Volume 1 Chapter 11 I C interfaces Reception of the own Slave Address and one or more Data bytes all are Acknowledged o P co Arbitration lost as Master and addressed as Slave J Last data byte transmitted Switched to Not Addressed Slave AA bit in I2CON 0 From Master to Slave From Slave to Master DATA A Any number of data bytes and their associated Acknowledge bits This number contained in I2STA corresponds to a def
11. 24 June 2005 24 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 3 System Control Block Wakeup enable one bit of EXTWAKE VPB Read of EXTWAKE EINTi to Wakeup Timer Figure 11 VPB Bus Data GLITCH FILTER EXTPOLARi EINTi Interrupt Flag one bit of EXTINT EXTMODEi Reset Write 1 to EXTINTi Fig 9 External interrupt logic 3 6 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000 This allows code running in different memory spaces to have control of the interrupts 3 6 1 Memory Mapping control register MEMMAP 0xE01F C040 Whenever an exception handling is necessary the microcontroller will fetch an instruction residing on the exception corresponding address as described in Table 2 ARM exception vector locations on page 12 The MEMMAP register determines the source of data that will fill this table Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 25 Philips Semiconductors UM1 01 20 ja Volume 1 3 6 2 Chapter 3 System Control Block Table 12 Memory Mapping control register MEMMAP address OxEO1F C040 bit description Bit Symbol Value Description Reset value 1 0 MAP 00 Boot Loader Mode Interrupt vectors are re mapped to Boot 00 Block 01 User Flash Mode Interru
12. 2ADR is loaded with the part s own slave address and the general call bit GC e The I C interrupt enable and interrupt priority bits are set e The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON and the serial clock frequency for master modes is defined by loading CRO and CR1 in I2CON The master routines must be started in the main program The I C hardware now begins checking the I C bus for its own slave address and general call If the general call or the own slave address is detected an interrupt is requested and I2STAT is loaded with the appropriate state information I C interrupt service When the I C interrupt is entered I2STAT contains a status code which identifies one of the 26 state services to be executed The State service routines Each state routine is part of the I C interrupt routine and handles one of the 26 states Adapting State services to an application The state service examples show the typical actions that must be performed in response to the 26 12C state codes If one or more of the four 12C operating modes are not used the associated state services can be omitted as long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of timeout during IC operations in order to trap an inoperative bus or a lost service routine 11 9 Software example 11 9 1 Initialization routine Example to initialize 12
13. User manual Rev 01 24 June 2005 150 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 12 SPI 12 2 9 Mode Fault The SSEL signal must always be inactive when the SPI block is a master If the SSEL signal goes active when the SPI block is a master this indicates another master has selected the device to be a slave This condition is known as a mode fault When a mode fault is detected the mode fault MODF bit in the status register will be activated the SPI signal drivers will be de activated and the SPI mode will be changed to be a slave 12 2 40 Slave Abort A slave transfer is considered to be aborted if the SSEL signal goes inactive before the transfer is complete In the event of a slave abort the transmit and receive data for the transfer that was in progress are lost and the slave abort ABRT bit in the status register will be activated 12 3 Pin description Table 126 SPI pin description Pin Name SCKO Type Input Output Pin Description Serial Clock The SPI is a clock signal used to synchronize the transfer of data across the SPI interface The SPI is always driven by the master and received by the slave The clock is programmable to be active high or active low The SPI is only active during a data transfer Any other time it is either in its inactive state or tri stated SSELO Input Slave Select The SPI slave select signal is an active low signal that indicates which sla
14. 1 Data byte will be transmitted ACK bit will received ACK has ba received been returned 0xB8 Data byte in I2DAT Load data byteor X 0 0 0 Last data byte will be transmitted and has been transmitted ACK bit will be received ACK has been Load data byte X 0 0 1 Data byte will be transmitted ACK bit will received be received 0xCO Data byte in I2DAT No I2DAT action or 0 0 0 0 Switched to not addressed SLV mode no has been transmitted recognition of own SLA or General call NOT ACK has been address received No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 No I2DAT action or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free No I2DAT action 1 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O0 logic 1 A START condition will be transmitted when the bus becomes free 0xC8 Last data byte in No I2DAT action or 0 0 0 0 Switched to not addressed SLV mode no I2DAT has been recognition of own SLA or General call transmitted AA 0 address ACK has been No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode received Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 No I2DAT action or 1 0 0 0 Switched to not
15. 11 7 5 11 7 6 11 7 7 11 7 8 Chapter 11 I C interfaces I C Slave Address register I2ADR I2CO I2COADR 0xE001 COOC and I2C1 I2C1ADR address 0xE005 C00C These registers are readable and writable and is only used when an I C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is the general call bit When this bit is set the general call address 0x00 is recognized Table 112 I C Slave Address register IZADR I2CO I2COADR address 0xE001 COOC and I2C1 I2C1ADR address 0xE005 CO00C bit description Bit Symbol Description Reset value 0 GC General Call enable bit 0 7 1 Address The I C device address for slave mode 0x00 I C SCL High duty cycle register I2SCLH I2CO I2COSCLH 0xE001 C010 and 12C1 I2C1SCLH OxE0015 C010 Table 113 I2C SCL High Duty Cycle register I2SCLH I2CO I2COSCLH address OxE001 C010 and I2C1 I2C1SCLH address 0xE005 C010 bit description Bit Symbol Description Reset value 15 0 SCLH Count for SCL HIGH time period selection 0x0004 I C SCL Low duty cycle register IPSCLL I2CO IZCOSCLL OxE001 C014 I2C1 I2C1SCLL 0xE0015 C014 Table 114 1 C SCL Low Duty Cycle register I2SCLL I2CO I2COSCLL address 0xE001 C014 and I2C1 I2C1SCLL address 0xE005 C014 bit description Bit Symbol Description Reset value 15 0 SCLL Count for SCL LOW time period selection 0x0004 Selecting the appropriate I C data rate and dut
16. Pins P0 1 and P0 16 can be selected to perform EINTO function EINT1 Input External Interrupt Input 1 See the EINTO description above Pins P0 3 and P0 14 can be selected to perform EINT1 function Important LOW level on pin P0 14 immediately after reset is considered as an external hardware request to start the ISP command handler More details on ISP and Serial Boot Loader can be found in Flash Memory System and Programming chapter on page 216 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 16 Philips Semiconductors UM10120 ia Volume 1 Chapter 3 System Control Block Table 4 Pin summary Pin name Pin Pin description direction EINT2 Input External Interrupt Input 2 See the EINTO description above Pins P0 7 and P0 15 can be selected to perform EINT2 function EINT3 Input External Interrupt Input 3 See the EINTO description above Pins P0 9 P0 20 and P0 30 can be selected to perform EINT3 function RESET Input External Reset input A LOW on this pin resets the chip causing I O ports and peripherals to take on their default states and the processor to begin execution at address 0x0000 0000 3 3 Register description All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 5 Summary of system control registers Name Description Access Reset
17. 1 CPHA 1 162 ii OxE006 8018 atus register T 13 3 8 Semiconductor Microwire frame format 162 J 0 aab ma cine S Tr Tevet aoa S 1339 S A s 13 4 8 SSP Masked Interrupt register SSPMIS 3 etup and hold time requirements on CS with 0xE006 801C 169 respect to Skin berowite mode 164 1349 SSP Interrupt Clear Register SSPICR 13 4 Register description 164 OxE006 8020 sss 169 Chapter 14 Timer Counter TIMERO and TIMER1 14 1 Features 2 0 cc isse vee ieee ra rn 170 14 5 5 Prescale Register PR TIMERO TOPR 14 2 Applications 00e ee aee 170 0xE000 400C and a sin eH T1PR OxE000 800C 175 14 3 Description cR RR 170 P E 14 5 6 Prescale Counter Register PC TIMERO TOPC 14 4 Pin description lsusess 170 0xE000 4010 and TIMER1 14 5 Register description 171 T1PC OxE000 8010 00 175 14 5 1 Interrupt Register IR TIMERO TOIR 14 5 7 Match Registers MRO MR3 175 OxE000 4000 and TIMER1 14 5 8 Match Control Register MCR TIMERO TOMCR T1IR OXE000 8000 173 OxE000 4014 and TIMER1 T1MCR 14 5 2 Timer Control Register TCR TIMERO TOTCR OxE000 8014 sisse 176 OxE000 4004 and TIMER1 T1TCR 14 5 9 Capture Registers CRO CR3 177 OxE000 8004 2 2 eee eee 173 14 5 10 Capture Control Register CCR TIMERO TOCCR 14 5 3 Count Control Regist
18. Philips Semiconductors UM1 01 20 iz Volume 1 11 8 1 11 8 2 Chapter 11 I C interfaces Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 29 Before the master transmitter mode can be entered I2CON must be initialized as follows Table 117 I2CONSET used to initialize Master Transmitter mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 X The I C rate must also be configured in the I2SCLL and I2SCLH registers I2EN must be set to logic 1 to enable the 12C block If the AA bit is reset the 12C block will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus In other words if AA is reset the I C interface cannot enter a slave mode STA STO and SI must be reset The master transmitter mode may now be entered by setting the STA bit The 12C logic will now test the I C bus and generate a start condition as soon as the bus becomes free When a START condition is transmitted the serial interrupt flag SI is set and the status code in the status register I2STAT will be 0x08 This status code is used by the interrupt service routine to enter the appropriate state service routine that loads I2DAT with the slave address and the data direction bit SLA W The SI bit in ICON must then be reset before the serial transfer can continue When the sla
19. User manual Rev 01 24 June 2005 109 Philips Semiconductors UM1 01 20 ij Volume 1 Chapter 11 I C interfaces for F S mode I C bus devices in the microcontrollers datasheet This is sometimes a useful capability but intrinsically limits alternate uses for the same pins if the I C interface is not used Seldom is this capability needed on multiple 12C interfaces within the same microcontroller Pull up resisor Pull up resisor SDA PC BUS SCL SDA SCL LPC2131 2 4 6 8 OTHER DEVICE WITH I C INTERFACE OTHER DEVICE WITH 1 C INTERFACE Fig 20 I C bus Configuration 11 4 Pin description Table 104 I C Pin Description Pin Type Description SDAO 1 Input Output I C Serial Data SCLO 1 Input Output 12C Serial Clock 11 5 I2C operating modes In a given application the IC block may operate as a master a slave or both In the slave mode the I C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested If the processor wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted If bus arbitration is lost in the master mode the 12C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer 11 5 4 Master Transmitter mod
20. Vss P0 14 EINT1 SDA1 P1 22 PIPESTAT1 P0 13 MAT1 1 P0 12 MAT1 0 P0 11 CAP1 1 SCL1 P1 23 PIPESTAT2 P0 10 CAP1 0 P0 9 RXD1 PWM6 EINT3 P0 8 TXD1 PWM4 002aab406 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 65 Philips Semiconductors UM10120 Volume 1 Chapter 6 Pin Configuration P0 21 PWM5 AD1 6 CAP1 3 P0 22 AD1 7 CAP0 0 MATO O RTXC1 P1 19 TRACEPKT3 RTXC2 Vss VDDA P1 18 TRACEPKT2 P0 25 AD0 4 AOUT P0 26 AD0 5 P0 27 AD0 0 CAPO 1 MATO 1 P1 17 TRACEPKT1 P0 28 ADO0 1 CAPO0 2 MATO 2 P0 29 AD0 2 CAP0 3 MATO 3 P0 30 AD0 3 EINT3 CAP0 0 P1 16 TRACEPKTO XTAL2 VDD 64 P1 27 TDO 63 VREF 62 XTAL1 61 60 P1 28 TDI 59 Vssa 58 P0 23 LPC2134 2136 2138 57 RESET 56 P1 29 TCK 55 P0 20 MAT1 3 SSEL1 EINT3 54 P0 19 MAT1 2 MOSI1 CAP1 2 53 P0 18 CAP1 3 MISO1 MAT1 3 52 P1 30 TMS 51 50 Vss 49 VBAT BM OL oaol ollm ma LO BS CO MD Ol rl oN ToL mPOA OT OP POY PY PY PY CO OD C G e l OO art r GOT OwA x o OSIDES AHO Es Zaz J S gt SCZ gt E gt ZAF AQAZO fa ZED lt ra x x x u w o gt sO Pipa tsk o O09 8 S Ste ur VV x Q eg Sgauggzc Fafy i EEBERLII S SA 2O 2O908A o a amp og9 SSJ o x amp a x O o ua og 288 2 227 e ox SN amp ese ss D amp amp amp Fig 17 LPC2134 6 8 64 pin package P1 20 TRACESYNC P0 17 CAP1 2
21. address Table 107 I C register map 2 0 0 eee eee ee 118 OxE002 000C bit description 154 Table 108 12C Control Set register IZCONSET 12C0 Table 132 SPI Interrupt register SOSPINT address I2COCONSET address 0xE001 C000 and I2C1 OxE002 001C bit description 155 I2C1CONSET address 0xE005 C000 bit Table 133 SSP pin descriptions 156 description 0 eee eee eee 119 Table 134 SSP register map 2000ee eae 165 Table 109 12C Control Set register I2CONCLR I2C0 Table 135 SSP Control Register 0 SSPCRO address I2COCONCLR address 0xE001 C018 and I2C1 OxE006 8000 bit description 165 I2C1CONCLR address 0xE005 C018 bit Table 136 SSP Control Register 1 SSPCR1 address description o beber staki eee psu es 120 OxE006 8004 bit description 166 Table 110 12C Status register I2STAT I2C0 I2COSTAT Table 137 SSP Data Register SSPDR address address 0xE001 C004 and I2C1 I2C1STAT OxE006 8008 bit description 167 address 0xE005 C004 bit description 121 Table 138 SSP Status Register SSPDR address Table 111 12C Data register I2DAT I2CO I2CODAT OxE006 800C bit description 167 address 0xE001 C008 and I2C1 I2C1DAT Table 139 SSP Clock Prescale Register SSPCPSR address 0xE005 C008 bit description 121 address 0xE006 8010 bit description 167 Table 112 12C Slave Address register IBADR 12C0 Ta
22. c aS n 245206 5 Sa zc 225wu o aa so Soir n x amp lt x O s Wwa t Qo om 0 non E 5 T ou z LI S ox D n o oo o oa E o Fig 15 LPC2131 64 pin package Koninklijke Philips Electronics N V 2005 All rights reserved Rev 01 24 June 2005 64 User manual Philips Semiconductors UM10120 Volume 1 Chapter 6 Pin Configuration P0 21 PWM5 CAP1 3 P0 22 CAPO 0 MATO O RTXC1 P1 19 TRACEPKT3 RTXC2 Vss VDDA P1 18 TRACEPKT2 P0 25 AD0 4 AOUT P0 26 AD0 5 P0 27 AD0 0 CAPO 1 MATO 1 P1 17 TRACEPKT1 P0 28 ADO0 1 CAPO0 2 MATO 2 P0 29 AD0 2 CAP0 3 MATO 3 P0 30 AD0 3 EINT3 CAP0 0 P1 16 TRACEPKTO Fig 16 LPC2132 64 pin package XTAL2 VDD 64 P1 27 TDO 63 VREF 62 XTAL1 61 55 P0 20 MAT1 3 SSEL1 EINT3 54 P0 19 MAT1 2 MOSI1 CAP1 2 53 P0 18 CAP1 3 MISO1 MAT1 3 52 P1 30 TMS 60 P1 28 TDI 51 59 Vssa 58 P0 23 56 P1 29 TCK 57 RESET LPC2132 50 Vss 49 VBAT Nilo oaol ollm Nt OO S LO BS CO Salolle oN ToL PPP mL OOO OT OL PO PY TO PC CO C CO s 2258285 2E222328 X sc eCeree oes eee fea a alkEw lt a x x x x u lu coo o m ld 0mg9 O09 8 Sts us VE 9 22 BESNBESZZE E F 9 a SITOS S SA 29 223538 S a amp ss Ou 4 a o x 9 1 x O l ou a a ao AL a tr nD O M ou S as 5 B Oo a amp P1 20 TRACESYNC P0 17 CAP1 2 SCK1 MAT1 2 P0 16 EINTO MATO 2 CAPO 2 P0 15 EINT2 P1 21 PIPESTATO VDD
23. 01 24 June 2005 69 Philips Semiconductors UM10120 E Volume 1 Table 56 Pin description continued Chapter 6 Pin Configuration Symbol Pin Type Description P0 27 AD0 0 114 y o P0 27 General purpose digital input output pin CAPO 1 MATO 1 r ADO 0 A D converter 0 input 0 This analog input is always connected to its pin CAPO 1 Capture input for Timer 0 channel 1 O MATO 1 Match output for Timer 0 channel 1 P0 28 ADO 1 13 4 yo P0 28 General purpose digital input output pin CAPO 2 MATO 2 l ADO 1 A D converter 0 input 1 This analog input is always connected to its pin CAPO 2 Capture input for Timer 0 channel 2 O MATO 2 Match output for Timer 0 channel 2 P0 29 ADO 2 14 4 yo P0 29 General purpose digital input output pin CAPO 3 MATO 3 l ADO 2 A D converter 0 input 2 This analog input is always connected to its pin I CAPO 3 Capture input for Timer 0 Channel 3 O MATO 3 Match output for Timer 0 channel 3 P0 30 AD0 3 15 4 yo P0 30 General purpose digital input output pin EINTS CAPO O l ADO 3 A D converter 0 input 3 This analog input is always connected to its pin EINT3 External interrupt 3 input CAPO 0 Capture input for Timer 0 channel 0 P0 31 17181 O P0 31 General purpose digital output only pin Note This pin MUST NO
24. 0x17 4 0x0007 9000 0X0007 9FFF 24 0x18 4 0x0007 A000 0X0007 AFFF 25 0x19 4 0x0007 B000 0X0007 BFFF 26 0x1A 4 0x0007 C000 0X0007 CFFF 20 6 Flash content protection mechanism The LPC2131 2 4 6 8 is equipped with the Error Correction Code ECC capable Flash memory The purpose of an error correction module is twofold Firstly it decodes data words read from the memory into output data words Secondly it encodes data words to be written to the memory The error correction capability consists of single bit error correction with Hamming code Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 221 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 20 Flash Memory The operation of ECC is transparent to the running application The ECC content itself is stored in a flash memory not accessible by user s code to either read from it or write into it on its own A byte of ECC corresponds to every consecutive 128 bits of the user accessible Flash Consequently Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first ECC byte Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second ECC byte etc Whenever the CPU requests a read from user s Flash both 128 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a corr
25. 13 3 1 Texas Instruments Synchronous Serial SSI frame format Figure 38 shows the 4 wire Texas Instruments synchronous serial frame format supported by the SSP module Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 157 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 13 SSP transfer Fig 38 Texas Instruments synchronous Serial frame format a single and b continuous back to back two frames 4 to 16 bits a Single frame transfer 4 to 16 bits 4 to 16 bits b Continuous back to back frames transfer 13 3 2 13 3 3 For device configured as a master in this mode CLK and FS are forced LOW and the transmit data line DX is tristated whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data FS is pulsed HIGH for one CLK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic On the next rising edge of CLK the MSB of the 4 to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been
26. 9 8 P0 20 00 GPIO Port 0 20 0 01 Match 1 3 Timer 1 10 SSEL SSP 11 EINT3 11 10 P0 21 00 GPIO Port 0 21 0 01 PWM5 10 Reserved ll2 or AD1 6I51 11 Capture 1 3 Timer 1 13 12 P0 22 00 GPIO Port 0 22 0 01 Reservedl ll2l or AD1 713 10 Capture 0 0 Timer 0 11 Match 0 0 Timer 0 15 14 P0 23 00 GPIO Port 0 23 0 01 Reserved 10 Reserved 11 Reserved 17 16 P0 24 00 Reserved 0 01 Reserved 10 Reserved 11 Reserved 19 18 P0 25 00 GPIO Port 0 25 0 01 ADO 4 10 Reserved or Aout DAC l2II3 11 Reserved Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 76 Philips Semiconductors UM10120 ja Volume 1 Chapter 7 Pin Connect Block Table 59 Pin function Select register 1 PINSEL1 address 0xE002 C004 bit description Bit Symbol Value Function Reset value 21 20 P0 26 00 GPIO Port 0 26 0 01 ADO 5 10 Reserved 11 Reserved 23 22 P0 27 00 GPIO Port 0 27 0 01 ADO 0 10 Capture 0 1 Timer 0 11 Match 0 1 Timer 0 25 24 P0 28 00 GPIO Port 0 28 0 01 ADO 1 10 Capture 0 2 Timer 0 11 Match 0 2 Timer 0 27 26 P0 29 00 GPIO Port 0 29 0 01 ADO 2 10 Capture 0 3 Timer 0 11 Match 0 3 Timer 0 29 28 P0 30 00 GPIO Port 0 30 0 01 ADO 3 10 EINT3 11 Capture 0 0 Timer 0 31 30 P0 31 00 GPO Port only 0 01 Reserved 10 Reserved 11 Reserved 1 Available on LPC2131 2 Available on LPC2132 3 Ava
27. Details of the registers appear in the description of each function Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 45 Philips Semiconductors UM1 01 20 Volume 1 Chapter 4 MAM Module Table 30 Summary of MAM registers Name Description Access Reset Address valuel MAMCR Memory Accelerator Module Control Register R W 0x0 OxEO1F C000 Determines the MAM functional mode that is to what extent the MAM performance enhancements are enabled See Table 31 MAMTIM Memory Accelerator Module Timing control R W 0x07 OxEO1F C004 Determines the number of clocks used for Flash memory fetches 1 to 7 processor clocks 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 4 7 MAM Control Register MAMCR 0xE01F C000 Two configuration bits select the three MAM operating modes as shown in Table 31 Following Reset MAM functions are disabled Changing the MAM operating mode causes the MAM to invalidate all of the holding latches resulting in new reads of Flash information as required Table 31 MAM Control Register MAMCR address 0xE01F C000 bit description Bit Symbol Value Description Reset value 1 0 MAM mode 00 MAM functions disabled 0 control 01 MAM functions partially enabled 10 MAM functions fully enabled 11 Reserved Not to be used in the application 7 2 Reserved user sof
28. Figure 42 which covers both single and continuous transfers SSEL MOSI MISO 4 to 16 bits a Motorola SPI frame format single transfer with CPOL 1 and CPHA 1 Fig 42 SPI frame format with CPOL 1 and CPHA 1 In this configuration during idle periods The CLK signal is forced HIGH SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case of a single word transmission the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transmissions the SSEL pins remains in its active LOW state until the final bit of the last word has been captured and then returns to its idle state as described above In general for continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer Semiconductor Micro
29. Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 15 PWM includes four capture inputs to save the timer value when an input signal transitions and optionally generate an interrupt when those events occur The PWM function is in addition to these features and is based on match register events The ability to separately control rising and falling edge locations allows the PWM to be used for more applications For instance multi phase motor control typically requires three non overlapping PWM outputs with individual control of all three pulse widths and positions Two match registers can be used to provide a single edge controlled PWM output One match register PWMMRO controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMRO match occurs Three match registers can be used to provide a PWM output with both edges controlled Again the PWMMRO match register controls the PWM cycle rate The other match registers control the two PWM edge positions Additional double edge controlled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge contr
30. SSP Important the SSPCPSR value must be properly initialized or the SSP controller will not be able to transmit data corectly In case of an SSP operating in the master mode the CPSDVSRmqmi 2 while in case of the slave mode CPSDVSR pin 12 SSP Interrupt Mask Set Clear register SSPIMSC 0xE006 8014 This register controls whether each of the four possible interrupt conditions in the SSP controller are enabled Note that ARM uses the word masked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 140 SSP Interrupt Mask Set Clear register SSPIMSC address 0xE006 8014 bit description Bit Symbol Description Reset value 0 RORIM Software should set this bit to enable interrupt when a Receive 0 Overrun occurs that is when the Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTIM Software should set this bit to enable interrupt when a Receive 0 Timeout condition occurs A Receive Timeout occurs when the Rx FIFO is not empty and no new data has been received nor has data been read from the FIFO for 32 bit times 2 RXIM Software should set this bit to enable interrupt when the Rx 0 FIFO is at least half full 3 TXIM Software should set this bit to enab
31. This means that the AA bit may be used to temporarily isolate the 12C block from the I2C bus Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 129 Philips Semiconductors UM10120 ia Volume 1 Table 120 Master Transmitter mode Chapter 11 I C interfaces Status Status of the I2C bus Application software response Next action taken by I C hardware Code and hardware To From I2DAT To I2CON I2CSTAT STA STO SI AA 0x08 A START condition Load SLA W X 0 0 X SLA W will be transmitted ACK bit will has been transmitted be received 0x10 A repeated START Load SLA Wor X X As above condition hasbeen pag SLA R X X SLA W will be transmitted the 12C block transmitted will be switched to MST REC mode 0x18 SLA W has been Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will transmitted ACK has be received been received No I2DAT action or 1 0 X Repeated START will be transmitted No I2DAT action or 0 1 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x20 SLA W has been Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will transmitted NOT ACK be received has been received Nig I2DAT actionor 1 0 0 X Repeated START will be transmitted No I
32. To have them come up as GPIO pins do not connect a bias resistor and ensure that any external driver connected to P1 26 RTCK is either driving high or is in high impedance state during Reset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 238 Philips Semiconductors UM10120 a volume 1 Chapter 21 EmbeddedICE 21 6 Register description The EmbeddedICE logic contains 16 registers as shown in Table 221 below The ARMT7TDMI S debug architecture is described in detail in ARM7TDMI S rev 4 Technical Reference Manual ARM DDI 0234A published by ARM Limited and is available via Internet at http www arm com Table 221 EmbeddedlCE logic registers Name Width Description Address Debug Control 6 Force debug state disable interrupts 00000 Debug Status 5 Status of debug 00001 Debug Comms Control Register 32 Debug communication control register 00100 Debug Comms Data Register 32 Debug communication data register 00101 Watchpoint 0 Address Value 32 Holds watchpoint 0 address value 01000 Watchpoint 0 Address Mask 32 Holds watchpoint 0 address mask 01001 Watchpoint 0 Data Value 32 Holds watchpoint 0 data value 01010 Watchpoint 0 Data Mask 32 Holds watchpoint 0 data mask 01011 Watchpoint 0 Control Value 9 Holds watchpoint 0 control value 01100 Watchpoint 0 Control Mask 8 Holds watchpoint 0 control mask 01101 Watchpoint 1 Add
33. User System mode eexaceteGheatees die 248 23 4 8 FIQ mode csse he eae ew 248 23 3 2 RMHOST LED DRUSI 245 23 4 9 Handling exceptions lusus 248 23 3 3 RMTarget lsseseseeeeeseesess 245 234 10 RealMonitor exception handling 248 PU IN Hed AMO ee ciega quus 246 234 11 RMTarget initialization 249 zi eos ipiis PERImonild Penes eris 23 4 12 Code example cc astrnat screenees 249 A ING StaCkS4 os edad Pee i i 2242 IRQmode sees 547 499 HeaMonior bulld OBHODS sede deeex ace 29 23 4 3 Undef mode sa rrrssercsarieprsrcvesis 247 Chapter 24 Supplementary information 24 1 Abbreviations 000ce eee eee 255 24 2 Disclaimers ese eid mx an 256 24 3 Trademarks 000 cece cece eens 256 PHILIPS Koninklijke Philips Electronics N V 2005 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Date of release 24 June 2005 Published in The Netherlands
34. VIC 5 4 8 FIQ Status register VICFIQStatus OxFFFF F004 This is a read only register This register reads out the state of those interrupt requests that are enabled and classified as FIQ If more than one request is classified as FIQ the FIQ service routine can read this register to see which request s is are active Table 48 FIQ Status register VICFIQStatus address OxFFFF F004 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 smoot Lo LL Access RO RO RO RO RO RO RO RO Bit 23 22 21 20 19 18 17 16 Symbol ADi BOD 2C1 ADO EINT3 EINT2 Access RO RO RO RO RO RO RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPI1 SSP SPIO 12C0 PWMO Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCore ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 49 FIQ Status register VICFIQStatus address OxFFFF F004 bit description Bit Symbol Description Reset value 31 0 See A bit read as 1 indicates a coresponding interrupt request being enabled 0 VICFIQStatus classified as IRQ and asserted bit allocation table 5 4 9 Vector Control registers 0 15 ViCvectCntl0 15 OXFFFF F200 23C These are a read write accessible registers Each of these registers controls one of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 the lowest Note that disabling a vectored
35. condition is transmitted the SI bit is set and the status code in the I2STAT register is 0x08 This status code is used to vector to a state service routine which will load the slave address and Write bit to the I2DAT register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes now are 0x18 0x20 or 0x38 for the master mode or 0x68 0x78 or OxBO if the slave mode was enabled by setting AA to 1 The appropriate actions to be taken for each of these status codes are shown in Table 120 to Table 123 4 Read Data Transferred n Bytes Acknowledge A Acknowledge SDA low z From Master to Slave A Not acknowledge SDA high From Slave to Master S START Condition P STOP Condition Fig 21 Format in the Master Transmitter mode Master Receiver mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to the I C Data register I2DAT and then clear the SI bit In this case the data direction bit R W should be 1 to indicate a read Koninklijke Philips Electronics N V 2005 All right
36. divider and the VPB clock PCLK clocks the prescaler the bit frequency is PCLK CPSDVSR SCR 1 SSP Control Register 1 SSPCR1 0xE006 8004 This register controls certain aspects of the operation of the SSP controller Table 136 SSP Control Register 1 SSPCR1 address 0xE006 8004 bit description Bit Symbol Value Description Reset value 0 LBM Loop Back Mode 0 0 During normal operation 1 Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI respectively 1 SSE SSP Enable 0 0 The SSP controller is disabled 1 The SSP controller will interact with other devices on the serial bus Software should write the appropriate control information to the other SSP registers and interrupt controller registers before setting this bit 2 MS Master Slave Mode This bit can only be written when the 0 SSE bit is 0 The SSP controller acts as a master on the bus driving the 0 SCLK MOSI and SSEL lines and receiving the MISO line 1 The SSP controller acts as a slave on the bus driving MISO line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave 0 mode MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MISO 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Koninklijke Philips
37. or simply an error in elapsed time since the RTC was activated While the signal from RTCX1 2 pins can be used to supply the RTC clock at anytime selecting the PCLK as the RTC clock and entering the Power down mode will cause a lapse in the time update Also feeding the RTC with the PCLK and altering this timebase during system operation by reconfiguring the PLL the VPB divider or the RTC prescaler will result in some form of accumulated time error Accumulated time errors may occur in case RTC clock source is switched between the PCLK to the RTCX pins too Once the 32 kHz signal from RTCX1 2 pins is selected as a clock source the RTC can operate completely without the presence of the VPB clock PCLK Therefore power sensitive applications i e battery powered application utilizing the RTC will reduce the power consumption by using the signal from RTCX1 2 pins and writing a 0 into the PCRTC bit in the PCONP power control register see Section 3 8 Power control on page 33 18 6 Reference clock divider prescaler The reference clock divider hereafter referred to as the prescaler allows generation of a 32 768 kHz reference clock from any peripheral clock frequency greater than or equal to 65 536 kHz 2 x 32 768 kHz This permits the RTC to always run at the proper rate regardless of the peripheral clock rate Basically the Prescaler divides the peripheral clock PCLK by a value which contains both an integer portion and
38. 0 enables the Receive Data Available interrupt 0 Interrupt for UARTO It also controls the Character Receive Enable Time out interrupt 0 Disable the RDA interrupts 1 Enable the RDA interrupts 1 THRE UOIER 1 enables the THRE interrupt for UARTO The 0 Interrupt status of this can be read from UOLSR 5 Enable 0 Disable the THRE interrupts 1 Enable the THRE interrupts 2 RX Line UOIER 2 enables the UARTO RX line status interrupts 0 Status The status of this interrupt can be read from UOLSR 4 1 Interrupt Enable 0 Disable the RX line status interrupts 1 Enable the RX line status interrupts L3 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined UARTO Interrupt Identification Register UOIIR OXEO00 C008 Read Only The UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an UOIIR access If an interrupt occurs during an UOIIR access the interrupt is recorded for the next UOIIR access Table 80 UARTO Interrupt Identification Register UOIIR address 0xE000 C008 read only bit description Bit Symbol Interrupt Pending Value Description Reset value Note that UOIIR 0 is active low The pending interrupt can 1 be determined by evaluating UOIIR 3 1 At least one interrupt is pending No pending interrupts 3 1 Interrupt Identification 011 UO
39. 0 EXTMODEO 0 Level sensitivity is selected for EINTO 0 1 EINTO is edge sensitive 1 EXTMODE1 0 Level sensitivity is selected for EINT1 0 1 EINT1 is edge sensitive 2 EXTMODE2 0 Level sensitivity is selected for EINT2 0 1 EINT2 is edge sensitive 3 EXTMODE3 0 Level sensitivity is selected for EINT3 0 1 EINT3 is edge sensitive 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined External Interrupt Polarity register EXTPOLAR OxEO1F C14C In level sensitive mode the bits in this register select whether the corresponding pin is high or low active In edge sensitive mode they select whether the pin is rising or falling edge sensitive Only pins that are selected for the EINT function see Pin Connect Block chapter on page 73 and enabled in the VICIntEnable register Section 5 4 4 Interrupt Enable register VICIntEnable OxFFFF F010 on page 52 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register and should write the corresponding 1 to the EXTINT register before enabling initializing or re enabling the interrupt to clear the EXTINT bit that could be set by changing the polarity Table 11 External Interrupt Polarity register EX
40. 0xE000 0000 The WDMOD register controls the operation of the watchdog as per the combination of WDEN and RESET bits Table 187 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0 or 1 Debug Operate without the watchdog running 1 0 Watchdog Interrupt Mode debug with the Watchdog interrupt but no WDRESET enabled When this mode is selected a watchdog counter underflow will set the WDINT flag and the watchdog interrupt request will be generated 1 1 Watchdog Reset Mode operate with the watchdog interrupt and WDRESET enabled When this mode is selected a watchdog counter underflow will reset the microcontroller While the watchdog interrupt is also enabled in this case WDEN 1 it will not be recognized since the watchdog reset will clear the WDINT flag Once the WDEN and or WDRESET bits are set they can not be cleared by software Both flags are cleared by an external reset or a watchdog timer underflow WDTOF The Watchdog Time Out Flag is set when the watchdog times out This flag is cleared by software WDINT The Watchdog Interrupt Flag is set when the watchdog times out This flag is cleared when any reset occurs Once the watchdog interrupt is serviced it can be disabled in the VIC or the watchdog interrupt request will be generated indefinitely Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 213 Philips Semiconductors
41. 1 22 6 Register description Chapter 22 Embedded Trace The ETM contains 29 registers as shown in Table 224 below They are described in detail in the ARM IHI 0014E document published by ARM Limited which is available via the Internet at http www arm com Table 224 ETM registers Name Description Access Register encoding ETM Control Controls the general operation of the ETM R W 000 0000 ETM Configuration Code Allows a debugger to read the number of RO 0000001 each type of resource Trigger Event Holds the controlling event WO 000 0010 Memory Map Decode Control Eight bit register used to statically configure WO 000 001 1 the memory map decoder ETM Status Holds the pending overflow status bit RO 000 0100 System Configuration Holds the configuration information using the RO 000 0101 SYSOPT bus Trace Enable Control 3 Holds the trace on off addresses WO 000 0110 Trace Enable Control 2 Holds the address of the comparison WO 000 0111 Trace Enable Event Holds the enabling event WO 000 1000 Trace Enable Control 1 Holds the include and exclude regions WO 000 1001 FIFOFULL Region Holds the include and exclude regions WO 000 1010 FIFOFULL Level Holds the level below which the FIFO is WO 000 1011 considered full ViewData event Holds the enabling event WO 000 1100 ViewData Control 1 Holds the include exclude regions WO 000 1101 ViewData Co
42. 130 UODLM 0x00 and UODLL 0x82 will enable UARTO with UART Opaudrate 96 15 baud Table 78 Some baud rates available when using 20 MHz peripheral clock PCLK 20 MHz Desired UODLM UODLL 96 errorl Desired UODLM UODLL 96 errorl baud rate hex dec baud rate hex dec 50 0x61A8 25000 0 4800 0x0104 260 0 1603 75 0x411B 16667 0 0020 7200 Ox00AE 174 0 2235 110 0x2C64 11364 0 0032 9600 0x0082 130 0 1603 134 5 0x244E 9294 0 0034 19200 0x0041 65 0 1603 150 0x208D 8333 0 0040 38400 0x0021 33 1 3573 300 0x1047 4167 0 0080 56000 0x0021 22 1 4610 600 0x0823 2083 0 0160 57600 0x0016 22 1 3573 1200 0x0412 1042 0 0320 112000 0x000B 11 1 4610 1800 0x02B6 694 0 0640 115200 0x000B 11 1 3573 2000 0x0271 625 0 224000 0x0006 6 6 9940 2400 0x0209 521 0 0320 448000 0x0003 3 6 9940 3600 0x015B 347 0 0640 1 Relative error calculated as actual baudrate desired baudrate 1 Actual baudrate based on Equation 1 UARTO Interrupt Enable Register UOIER 0xE000 C004 when DLAB 0 The UOIER is used to enable the three UARTO interrupt sources Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 87 Philips Semiconductors UM10120 Volume 1 9 3 6 Chapter 9 UARTO Table 79 UARTO Interrupt Enable Register UOIER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR UOIER
43. 15 5 2 Description 000eeceeeeeeee 48 OxXFFFF F100 130 s ies nk ecu ts dod 56 inti 5 4 11 Default Vector Address register VICDefVectAddr 5 3 Register description 48 54 ue ist Liu 50 OXFFFF F034 000 56 TOMUS iba zi p Ol CE 5 4 12 Vector Address register VICVectAdar 5 4 1 Software Interrupt register VICSoftlnt OXFFFF F030 eoo suni erh o eLk REIS 56 OxFFFF FO18 XN QU eee Gnas 50 5 4 13 Protection Enable register VICProtection 5 4 2 Software Interrupt Clear register VICSoftIntClear OXFFFF F020 oaaao aunan 56 OxFFFF F01C 0005 51 55 iniareukeaurees 57 5 4 3 Raw Interrupt status register VICRawiIntr rup j ACES ea a kamak ne a aiem OxFFFF F008 naonnana nnn 52 5 6 Spurious interrupts leues 59 5 4 4 Interrupt Enable register VICIntEnable 5 6 1 Details and case studies on spurious OxFFFF F010 20 200 eee 52 intetrupls ol ERAS Lu Lees 59 5 4 5 Interrupt Enable Clear register VICIntEnClear 5 6 2 Workaround lessseeseeeeeeeee 60 OxFFFF F014 0 000 eee 53 5 6 3 Solution 1 test for an IRQ received during a write 5 4 6 Interrupt Select register VICIntSelect to disable IRQS 1er ce Deeded os 60 OxFFFF F00C 20000 53 5 6 4 Solution 2 disable IRQs and FIQs using separate 5 4 7 IRQ Status register VICIRQStatus writes to the CPSR 61 OxFFFF F000
44. 16 1 PLLC PLL Connect When PLLC and PLLE are both set to one and aftera 0 valid PLL feed connects the PLL as the clock source for the microcontroller Otherwise the oscillator clock is used directly by the microcontroller See PLLSTAT register Table 16 7 2 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined The PLL must be set up enabled and Lock established before it may be used as a clock source When switching from the oscillator clock to the PLL output or vice versa internal circuitry synchronizes the operation in order to ensure that glitches are not generated Hardware does not insure that the PLL is locked before it is connected or automatically disconnect the PLL if lock is lost during operation In the event of loss of PLL lock it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation PLL Configuration register PLLCFG 0xE01F C084 The PLLCFG register contains the PLL multiplier and divider values Changes to the PLLCFG register do not take effect until a correct PLL feed sequence has been given see Section 3 7 7 PLL Feed register PLLFEED 0xE01F CO8C on page 30 Calculations for the PLL frequency and multiplier and divider values are found in the PLL Frequency Calculation section on page 31 Table 15 PLL Configuration register PLLCFG address 0xE01F C084 bit description
45. 171 UM10120 Chapter 14 TIMERO and TIMER1 Philips Semiconductors jal Volume 1 Table 145 TIMER COUNTERO and TIMER COUNTER register map Generic Description Access Reset TIMER TIMER Name value COUNTERO COUNTER1 Address amp Name Address amp Name IR Interrupt Register The IR can be written to clear R W 0 OxE000 4000 OxE000 8000 interrupts The IR can be read to identify which of TOIR T1IR eight possible interrupt sources are pending TCR Timer Control Register The TCR is used to control R W 0 OxE000 4004 OxE000 8004 the Timer Counter functions The Timer Counter can TOTCR T1TCR be disabled or reset through the TCR TC Timer Counter The 32 bit TC is incremented every R W 0 OxE000 4008 OxE000 8008 PR 1 cycles of PCLK The TC is controlled through TOTC T1TC the TCR PR Prescale Register The Prescale Counter below is R W 0 OxE000 400C OxE000 800C equal to this value the next clock increments the TC TOPR T1PR and clears the PC PC Prescale Counter The 32 bit PC is a counter which R W 0 OxE000 4010 OxE000 8010 is incremented to the value stored in PR When the TOPC T1PC value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface MCR Match Control Register The MCR is used to control R W 0 0xE0004014 OxE000 8014 if an interrupt is generated and if the TC is reset TOMCR T1MCR when a Match occurs MRO Match Reg
46. 20 25 50 75 11 8 Details of I2C operating modes The four operating modes are Master Transmitter Master Receiver Slave Receiver Slave Transmitter Data transfers in each mode of operation are shown in Figures 29 to 33 Table 116 lists abbreviations used in these figures when describing the 12C operating modes Table 116 Abbreviations used to describe an I C operation Abbrevation Explanation S Start Condition SLA 7 bit slave address R Read bit high level at SDA W Write bit low level at SDA A Acknowledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P Stop condition In Figures 29 to 33 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in the I2STAT register At these points a service routine must be executed to continue or complete the serial transfer These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in I2STAT is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in tables from Table 120 to Table 124 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 123
47. 5 show different views of the peripheral address space Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 9 Philips Semiconductors UM10120 I3 Volume 1 Chapter 2 Memory map address decoding for each peripheral All peripheral register addresses are word aligned to 32 bit boundaries regardless of their size This eliminates the need for byte lane mapping hardware that would be required to allow byte 8 bit or half word 16 bit accesses to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately VECTORED INTERRUPT CONTROLLER OxFFFF F000 4G 4K OxFFFF C000 AHB PERIPHERAL 126 OxFFFF 8000 AHB PERIPHERAL 125 OxFFFF 4000 AHB PERIPHERAL 124 OxFFFF 0000 OxFFE1 0000 AHB PERIPHERAL 3 OxFFEO C000 AHB PERIPHERAL 2 OxFFEO 8000 AHB PERIPHERAL 1 OxFFEO 4000 AHB PERIPHERAL 0 OxFFEO 0000 Fig 4 AHB peripheral map Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 10 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 2 Memory map
48. 56 Connection of interrupt sources to the Vectored continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 257 Philips Semiconductors UM10120 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Volume 1 Interrupt Controller VIC 57 Pin description 20 02s eee 67 Pin connect block register map 73 Pin function Select register 0 PINSELO address OxE002 C000 bit description Pin function Select register 1 PINSEL1 address OxE002 C004 bit description 76 Pin function Select register 2 PINSEL2 OxE002 C014 bit description 78 Pin function select register bits 78 GPIO pin description 79 GPIO register Map 0 0 0 eee 79 GPIO Pin Value register 0 IOOPIN address OxE002 8000 bit description 80 GPIO Pin Value register 1 IO1PIN address OxE002 8010 bit description 80 GPIO Output Set register 0 IOOSET address OxE002 8004 bit description 81 GPIO Output Set register 1 IO1SET address OxE002 8014 bit description 81 GPIO Outpu
49. 8 frame FIFOs for both transmit and receive 4to 16 bits frame 13 2 Description The SSP is a Synchronous Serial Port SSP controller capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer Data transfers are in principle full duplex with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data Table 133 SSP pin descriptions Interface pin name function y Pin Name Type t Pin Description SPI SSI Microwire SCK1 y o SCK CLK SK Serial Clock SCK CLK SK is a clock signal used to synchronize the transfer of data It is driven by the master and received by the slave When SPI interface is used the clock is programmable to be active high or active low otherwise it is always active high SCK1 only switches during a data transfer Any other time the SSP either holds it in its inactive state or does not drive it leaves it in high impedance state Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 156 Philips Semiconductors UM10120 ja Volume 1 Table 133 SSP pin descriptions Chapter 13 SSP Interface pin name function Pin Name Type a SPI ssi SSEL1 O SSEL
50. 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Chapter 24 Supplementary information UARTO FIFO Control Register UOFCR address OxE000 C008 bit description 90 UARTO Line Control Register UOLCR address OxE000 C000 bit description 91 UARTO Line Status Register UOLSR address OxE000 C014 read only bit description 91 UARTO Scratch pad register UOSCR address OxE000 C010 bit description 92 UARTO Transmit Enable Register UOTER address 0xE000 C030 bit description 93 UART1 pin description 95 UART1 register map 4 97 UART1 Receiver Buffer Register U1RBR address 0xE001 0000 when DLAB 0 Read Only bit description 98 UART1 Transmitter Holding Register U1THR address 0xE001 0000 when DLAB 0 Write Only bit description 98 UART1 Divisor Latch LSB register U1DLL address 0xE001 0000 when DLAB 1 bit description 2l ellen 99 UART1 Divisor Latch MSB register U1DLM address 0xE001 0004 when DLAB 1 bit description 000020 eee eae 99 Some baud rates available when using 20 MHz peripheral clock PCLK 20 MHz 99 UART1 Interrupt Enable Register U1IER address 0xE001 0004 when DLAB 0 bit description llle 100 UART1 Interrupt Identification Register U1IIR address 0xE001 0008 rea
51. C interfaces Status Status of the I2C bus Application software response Next action taken by I C hardware Code and hardware To From I2DAT To I2CON I2CSTAT STA STO SI AA 0x08 A START condition Load SLA R X 0 0 X SLA R will be transmitted ACK bit will be has been transmitted received 0x10 A repeated START Load SLA R or X 0 X As above condition has been gag SLA W X 0 X SLA W will be transmitted the 12C block transmitted will be switched to MST TRX mode 0x38 Arbitration lostin NOT No I2DAT action or 0 0 0 X I2C bus will be released the 12C block will ACK bit enter a slave mode No I2DAT action 1 0 0 X A START condition will be transmitted when the bus becomes free 0x40 SLA R has been No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit transmitted ACK has will be returned been received No I2DAT action 0 0 0 1 Databyte wil be received ACK bit will be returned 0x48 SLA R has been No I2DAT action or 1 0 0 X Repeated START condition will be transmitted NOT ACK transmitted has been received No I2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x50 Data byte has been Read data byte or 0 0 0 0 Data byte will be received NOT ACK bit received ACK has will be returned been returned Read data byte 0 0 0 1 Data byte will b
52. Chapter 18 RTC LPC2131 2 4 6 8 Fig 53 RTC 32kHz crystal oscillator circuit Table 185 gives the crystal parameters that should be used C is the typical load capacitance of the crystal and is usually specified by the crystal manufacturer The actual C influences oscillation frequency When using a crystal that is manufactured for a different load capacitance the circuit will oscillate at a slightly different frequency depending on the quality of the crystal compared to the specified one Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table 185 that belong to a specific C_ The value of external capacitances Cx and Cy specified in this table are calculated from the internal parasitic capacitances and the CL Parasitics from PCB and package are not taken into account Table 185 Recommended values for the RTC external 32 kHz oscillator Cx1j components Crystal load capacitance Maximum crystal series External load capacitors Cy4 cx C resistance Rs 11 pF lt 100 KQ 18 pF 18 pF 13 pF lt 100 kQ 22 pF 22 pF 15 pF lt 100 kQ 27 pF 27 pF Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 211 Semiconductors 19 1 Features UM10120 Chapter 19 Watchdog Timer Rev 01 24 June 2005 User manual ET nternally resets chip if not periodically reloaded Debug mode Enab
53. Control RX Trigger Reserved Reserved Reserved TX FIFO RXFIFO FIFO WO 0x00 OxE000 C008 Register Reset Reset Enable UOLCR Line Control DLAB Set Stick Even Parity Number Word Length Select R W 0x00 OxE000 C00C Register Break Parity Parity Enable of Stop Select Bits UOLSR Line Status RX FIFO TEMT THRE BI FE PE OE DR RO 0x60 0xE000 C014 Register Error UOSCR Scratch Pad 8 bit Data R W 0x00 OxE000 C01C Register UOTER Transmit Enable TXEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W 0x80 OxE000 C030 Register 1 Reset value relects the data stored in used bits only It does not include reserved bits content euinjoA S10 onpuooiruieg Sdijiud OLYVN 6 1e1deu2 Oc LOLINN Philips Semiconductors UM1 01 20 ja Volume 1 9 3 1 9 3 2 9 3 3 Chapter 9 UARTO UARTO Receiver Buffer Register UORBR 0xE000 C000 when DLAB 0 Read Only The UORBR is the top byte of the UARTO Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only Since PE FE and BI bits correspond to the byte sitting on the top of the RBR FIFO i e the one that will be read in the next read from t
54. Divider values PSEL Bits PLLCFG bits 6 5 Value of P 00 1 01 2 10 4 11 8 Table 21 PLL Multiplier values MSEL Bits PLLCFG bits 4 0 Value of M 00000 1 00001 2 00010 3 00011 4 11110 31 11111 32 PLL example System design asks for Fosc 10 MHz and requires CCLK 60 MHz Based on these specifications M CCLK Fosc 60 MHz 10 MHz 6 Consequently M 125will be written as PLLCFG 4 0 Value for P can be derived from P Feco CCLK x 2 using condition that Feco must be in range of 156 MHz to 320 MHz Assuming the lowest allowed frequency for Foco 156 MHz P 156 MHz 2 x 60 MHz 1 3 The highest Feco frequency criteria produces P 2 67 The only solution for P that satisfies both of these requirements and is listed in Table 20 is P 2 Therefore PLLCFG 6 5 1 will be used Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 32 Philips Semiconductors UM1 01 20 E Volume 1 Chapter 3 System Control Block 3 8 Power control 3 8 1 3 8 2 The LPC2131 2 4 6 8 supports two reduced power modes Idle mode and Power down mode In Idle mode execution of instructions is suspended until either a Reset or interrupt occurs Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution Idle mode eliminates power used by the process
55. EINT3 0 receives the state of all of its associated pins from the pins receivers along with signals that indicate whether each pin is selected for the EINT function The external interrupt logic handles the case when more than one pin is so selected differently according to the state of its Mode and Polarity bits In Low Active Level Sensitive mode the states of all pins selected for the same EINTx functionality are digitally combined using a positive logic AND gate n High Active Level Sensitive mode the states of all pins selected for the same EINTx functionality are digitally combined using a positive logic OR gate n Edge Sensitive mode regardless of polarity the pin with the lowest GPIO port number is used Selecting multiple pins for an EINTx in edge sensitive mode could be considered a programming error The signal derived by this logic is the EINTi signal in the following logic schematic Figure 9 For example if the EINT3 function is selected in the PINSELO and PINSEL1 registers for pins P0 9 P0 20 and P0 30 and EINT3 is configured to be low level sensitive the inputs from all three pins will be logically ANDed When more than one EINT pin is logically ORed the interrupt service routine can read the states of the pins from the GPIO port using the IOOPIN and IO1PIN registers to determine which pin s caused the interrupt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01
56. ER rerba 210 Chapter 19 Watchdog Timer 19 1 FeatureS ecce Rs 212 19 4 2 Watchdog Timer Constant register WDTC 19 2 Applications 0 eee eee es 212 0xE000 0004 DEDE 214 19 3 Description i esee gig Tete _ Watchdog Feed register Pree 19 4 Register description 213 OxE000 0008 nanana nananana 214 i g PROM ne tnt eS ipiam ii 19 4 4 Watchdog Timer Value register WDTV 19 4 1 Watchdog Mode register WDMOD OxE000 000C 222s eee 214 a 213 195 Blockdiagram eene 214 Chapter 20 Flash Memory System and Programming 20 1 Flash Boot Loader 216 20 8 5 Read memory address no of bytes 225 202 JFeal teS oco o x RE deve 216 20 8 6 Prepare sector s for write operation start sector 203 Applications sese esses 216 HMI SFG SBCtOP MUNDI sedia 225 20 4 Description 216 20 8 7 Copy RAM to Flash Flash address RAM l solde anny Som RECEN LO address no of bytes gt 226 20 4 1 Memory map after any TeSet nuun 216 20 88 Go lt address gt lt mode gt 227 20 4 2 Criterion for valid user code 217 20 8 9 Erase sector s lt start sector number gt lt end 20 4 3 Communication protocol 218 secor nimbe aeaa erea i A 297 20 4 4 ISP command format lusus 218 20 8 10 Blank check sector s sector number end 20 4 5 ISP response format llus 218 en s
57. External interrupt registers 20 Table 8 External Interrupt Flag register EXTINT address OxEO1F C140 bit description 21 Table 9 Interrupt Wakeup register INTWAKE address OxEO1F C144 bit description 22 Table 10 External Interrupt Mode register EXTMODE address OxEO1F C148 bit description 23 Table 11 External Interrupt Polarity register EXTPOLAR address OxEO1F C14C bit description 23 Table 12 Memory Mapping control register MEMMAP address OxEO1F C040 bit description 26 Table 13 PLL registers lllsllseesesssse 27 Table 14 PLL Control register PLLCON address OxEO1F C080 bit description 29 Table 15 PLL Configuration register PLLCFG address OxEO1F C084 bit description 29 Table 16 PLL Status register PLLSTAT address OxEO1F C088 bit description 30 Table 17 PLL Control bit combinations 30 Table 18 PLL Feed register PLLFEED address OxEO1F CO080C bit description 31 Table 19 Elemens determining PLLs frequency 31 Table 20 PLL Divider values 0 32 Table 21 PLL Multiplier values 32 Table 22 Power control registers 33 Table 23 Power Control register PCON address OxEO1F COCO bit description 34 Table 24 Power Control for Peripherals register PCONP address 0xE01F COCA bit description
58. Fig 55 Fig 56 Fig 57 Fig 58 Fig 59 Fig 60 Fig 61 Fig 62 CPHA 0 and CPHA 1 148 SPI block diagram 0 0 0 cee eee 155 Texas Instruments synchronous serial frame format a single and b continuous back to back two frames Cui PEPPER 158 SPI frame format with CPOL 0 and CPHA 0 a single and b continuous transfer 159 SPI frame format with CPOL 0 and CPHA 1 160 SPI frame format with CPOL 1 and CPHA 0 a single and b continuous transfer 161 SPI frame format with CPOL 1 and CPHA 1162 Microwire frame format single transfer 163 Microwire frame format continuos transfers 164 Microwire frame format continuos transfers 164 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 179 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 179 Timer block diagram 00000 180 PWM block diagram ssesessss 183 Sample PWM waveforms 184 RTC block diagram 0 02 02 eee eee 200 RTC prescaler block diagram 209 RTC 32kHz crystal oscillator circuit 211 Watchdog block diagram 215 Map of lower memory after reset 217 Boot process flowchart 220 IAP Parameter passing 232 EmbeddedICE debug environment block i To 611 ERE Pr DEM US 239 ETM debu
59. First In First Out GPIO General Purpose Input Output NA Not Applicable PLL Phase Locked Loop POR Power On Reset PWM Pulse Width Modulator RAM Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter VIC Vector Interrupt Controller VPB VLSI Peripheral Bus Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 255 Philips Semiconductors UM10120 ja Volume 1 24 2Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products con
60. I2CO 10 Capture 0 0 Timer 0 11 Reserved 7 6 P0 3 00 GPIO Port 0 3 0 01 SDAO I2CO 10 Match 0 0 Timer 0 11 EINT1 9 8 P0 4 00 GPIO Port 0 4 0 01 SCKO SPIO 10 Capture 0 1 Timer 0 11 ADO 6 11 10 P0 5 00 GPIO Port 0 5 0 01 MISOO SPIO 10 Match 0 1 Timer 0 11 ADO 7 13 12 P0 6 00 GPIO Port 0 6 0 01 MOSIO SPIO 10 Capture 0 2 Timer 0 11 Reservedl ll2 or AD1 0 5 15 14 P0 7 00 GPIO Port 0 7 0 01 SSELO SPIO 10 PWM2 11 EINT2 17 16 P0 8 00 GPIO Port 0 8 0 01 TXD UART1 10 PWM4 11 Reservedl ll2 or AD1 1 3 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 74 Philips Semiconductors UM10120 Volume 1 Chapter 7 Pin Connect Block Table 58 Pin function Select register 0 PINSELO address 0xE002 C000 bit description Bit Symbol Value Function Reset value 19 18 P0 9 00 GPIO Port 0 9 0 01 RxD UART1 10 PWM6 11 EINT3 21 20 P0 10 00 GPIO Port 0 10 0 01 Reservedl l2 or RTS UART1 BI 10 Capture 1 0 Timer 1 11 Reservedl ll2 or AD1 213 23 22 PO 11 00 GPIO Port 0 11 0 01 Reservedl l2 or CTS UART1 51 10 Capture 1 1 Timer 1 11 SCL1 I2C1 25 24 P0 12 00 GPIO Port 0 12 0 01 Reservedll2 or DSR UART1 51 10 Match 1 0 Timer 1 11 Reservedl ll2 or AD1 3 8 27 26 P0 13 00 GPIO Port 0 13 0 01 Reservedl ll2 or DTR UART1 ISI 10 Match 1 1 Timer 1 11 Reserved I2 or
61. IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself the interrupt is simply changed to the non vectored form Table 50 Vector Control registers 0 15 VICvectCntl0 15 OXFFFF F200 23C bit description Bit Symbol Description Reset value 4 0 int request The number of the interrupt request or software interrupt assigned to this 0 sw int assig vectored IRQ slot As a matter of good programming practice software should not assign the same interrupt number to more than one enabled vectored IRQ slot But if this does occur the lowernumbered slot will be used when the interrupt request or software interrupt is enabled classified as IRQ and asserted 5 IRQslot en When 1 this vectored IRQ slot is enabled and can produce a unique ISR 0 address when its assigned interrupt request or software interrupt is enabled classified as IRQ and asserted 31 6 Reserved user software should not write ones to reserved bits The value read NA from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 55 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 5 VIC 5 4 10 Vector Address registers 0 15 VICVectAddr0 15 OXFFFF F100 13C These are a read write accessible registers These registers hold the addresses of the Interrupt Service routines ISRs for the 16 vectored IRQ slots Tabl
62. LOW Since this can occur only at the end of a serial byte the 12C block generates no further clock pulses Figure 27 shows the arbitration procedure SCL Line 1 2 3 4 8 9 1 Another device transmits identical serial data 2 Another device overrules a logic dotted line transmitted thi master by pulling the SDA line low Arbitration is lost and this 1C enters Slave Receiver mode 3 This FC is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted This C will not generate clock pulses for the next byte Data on SDA originates from the new master once it has won arbitration Fig 27 Arbitration procedure Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 116 Philips Semiconductors UM1 01 20 ij Volume 1 11 6 6 11 6 7 11 6 8 Chapter 11 I C interfaces The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device If two or more master devices generate clock pulses the mark duration is determined by the device that generates the shortest marks and the space duration is determined by the device that generates the longest spaces Figure 28 shows the synchronization procedure SDA Line X X 1 3 1 Y Y SCL Line le 2 High Low period period 1 Another device pulls the SCL line low before thi has tim
63. LPC2134 6 8 Description Analog Inputs The A D converter cell can measure the voltage on any of these input signals Note that these analog inputs are always connected to their pins even if the Pin Multiplexing Register assigns them to port pins A simple self test of the A D Converter can be done by driving these pins as port outputs Note if the A D converter is used signal levels on analog input pins must not be above the level of Va4 at any time Otherwise A D converter readings will be invalid If the A D converter is not used in an application then the pins associated with A D inputs can be used as 5 V tolerant digital IO pins Warning while the ADC pins are specified as 5 V tolerant see Table 56 Pin description on page 67 the analog multiplexing in the ADC block is not More than 3 3 V Vppa 10 should not be applied to any pin that is selected as an ADC input or the ADC reading will be incorrect If for example ADO 0 and ADO 1 are used as the ADCO inputs and voltage on ADO 0 4 5 V while ADO 1 2 5 V an excessive voltage on the ADO 0 can cause an incorrect reading of the ADO 1 although the ADO 1 input voltage is within the right range Vref Reference Voltage Reference This pin is provides a voltage reference level for the A D converter s VppA Vssa Power Analog Power and Ground These should be nominally the same voltages as Vpp and Vss but should be isolated to minimize noise and error K
64. Locked Loop PLL 26 Pe 374 Reoister d ipti 27 3 10 1 Register description 38 i age eei I ees Piao nearest 8 10 2 VPBDIV register VPBDIV OXEO1F C100 38 PLLCON OXEO1F C080 ee 28 3 11 Wakeup timer nasaanaszssaasunsassunnusas 39 3 7 3 PLL Configuration register PLLCFG 3 12 Brown out detection 40 OxEO1F C084 0 02 29 3 13 Code security vs debugging 41 Chapter 4 Memory Acceleration Module MAM 4 1 Introduction 2 ice cde cee nn 42 4 3 MAM blocksS 00 e cece eee eens 43 4 2 Operation se tek eR RARE Rn rn RR 4 UR 42 4 3 1 Flash memory bank 05 43 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 263 Philips Semiconductors UM10120 E Volume 1 4 3 2 Instruction latches and data latches 44 4 3 3 Flash programming Issues 44 4 4 MAM operating modes 44 4 5 MAM configuration esses 45 4 6 Register description 45 Chapter 5 Vectored Interrupt Controller VIC Chapter 24 Supplementary information 4 7 MAM Control Register MAMCR OxE01F C000 46 4 8 MAM Timing register MAMTIM OXEO1F C004 46 4 9 MAM usage notes lesse 47 5 1 Features ea n rm Rm 48 5 4 10 Vector Address registers 0 15 VICVectAddr0
65. NA reserved bits The value read from a reserved bit is not defined 1 Available in LPC2134 6 8 only In all other LPC213x parts this bit is Reserved UART1 Interrupt Identification Register U1IIR 0xE001 0008 Read Only The U1IIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an U1IIR access If an interrupt occurs during an U1IIR access the interrupt is recorded for the next U1IIR access Table 95 UART1 Interrupt Identification Register U1IIR address 0xE001 0008 read only bit description Bit Symbol Value Description Reset value 0 Interrupt Note that U1IIR 0 is active low The pending 1 Pending interrupt can be determined by evaluating U1IIR 3 1 0 At least one interrupt is pending 1 No interrupt is pending Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 100 Philips Semiconductors UM1 01 20 a Volume 1 Chapter 10 UART1 Table 95 UART1 Interrupt Identification Register U1IIR address 0xE001 0008 read only bit description Bit Symbol Value Description Reset value 3 1 Interrupt U1IER 3 1 identifies an interrupt corresponding to 0 Identification the UART1 Rx FIFO All other combinations of U1IER 3 1 not listed above are reserved 100 101 111 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA 110 2b Character Time out Indica
66. Philips Semiconductors UM1 01 20 fai Volume 1 Chapter 11 I C interfaces Con Other Master sends Repeated Start earlier Retry Fig 33 Simultaneous repeated START conditions from two masters Time limit STA Flag STO Flag SDA Line SCL Line Start condition Fig 34 Forced access to a busy I2C bus 2 STA Flag Y 1 1 SDA Line y SCL Line le Start sse m 1 Unsuccessful attempt to send a Start condition 2 SDA Line released 3 Succcessful attempt to send a Start condition state 08H is entered Fig 35 Recovering from a bus obstruction caused by a low level on SDA 11 8 14 12C State service routines This section provides examples of operations that must be performed by various I C state service routines This includes e Initialization of the l2C block after a Reset e C Interrupt Service Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 138 Philips Semiconductors UM1 01 20 iz Volume 1 11 8 15 11 8 16 11 8 17 11 8 18 Chapter 11 I C interfaces e The 26 state service routines providing support for all four I2C operating modes Initialization In the initialization example the 12C block is enabled for both master and slave modes For each mode a buffer is used for transmission and reception The initialization routine performs the following functions
67. Power On Reset POR and Brown Out Detection BOD circuits CPU operating voltage range of 3 0 V to 3 6 V 3 3 V 10 with 5 V tolerant I O pads Industrial control Medical systems Access control Point of sale Communication gateway Embedded soft modem General purpose applications 1 4 Device information Table 1 LPC2131 2132 2134 2136 2138 device information Device Number of On chip On chip Number of Number of Note pins SRAM FLASH 10 bit ADC 10 bit DAC channels channels LPC2131 64 8 kB 32 kB 8 LPC2132 64 16 kB 64 kB 8 1 LPC2134 64 16 kB 128 kB 16 1 UART1 with full modem interface LPC2136 64 32 kB 256 kB 16 1 UART1 with full modem interface LPC2138 64 32 kB 512 kB 16 1 UART1 with full modem interface Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 4 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 1 Introductory information 1 5 Architectural overview The LPC2131 2 4 6 8 consists of an ARM7TDMI S CPU with emulation support the ARM7 Local Bus for interface to on chip memory controllers the AMBA Advanced High performance Bus AHB for interface to the interrupt controller and the VLSI Peripheral Bus VPB a compatible superset of ARM s AMBA Advanced Peripheral Bus for connection to on chip peripheral functions The LPC2131 2 4 6 8 configures the ARM7TDMI S processor in little endian byte ord
68. Register U1THR address 0xE001 0000 when DLAB 0 Write Only bit description Bit Symbol Description Reset value 7 0 THR Writing to the UART1 Transmit Holding Register causes the data NA to be stored in the UART1 transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available UART1 Divisor Latch Registers 0 and 1 U1DLL 0xE001 0000 and U1DLM 0xE001 0004 when DLAB 1 The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used to divide the VPB clock PCLKk in order to produce the baud rate clock which must be 16x the desired baud rate Equation 2 The U1DLL and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and UiDLM contains the higher 8 bits of the divisor A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in U1LCR must be one in order to access the UART1 Divisor Latches Details on how to select the right value for U1DLL and U1DLM can be found later on in this chapter Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 98 Philips Semiconductors UM1 01 20 ia Volume 1 10 3 4 10 3 5 Chapter 10 UART1 2 clk UARTI baudrate 16 x 16 x UIDLM UIDLL Table 91 UART1 Divisor Latch LSB register U1DLL address 0xE001 0000 when DLAB 1 bit descr
69. Rev 01 24 June 2005 107 Philips Semiconductors UM10120 B Volume 1 Chapter 10 UART1 p U1THR i U1TSR d I U1DLL E U1DLM p U1RBR l U1RSR U1INTR pL Lt PA 2 0 PWRITE VPB INTERFACE Fig 19 LPC2131 2 4 6 8 UART1 block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 108 Semiconductors 11 1 Features UM10120 Chapter 11 I C interfaces I2CO and I C1 Rev 01 24 June 2005 User manual ET Standard I2C compliant bus interfaces that may be configured as Master Slave or Master Slave Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Programmable clock to allow adjustment of I C transfer rates Bidirectional data transfer between masters and slaves Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus may be used for test and diagnostic purposes 11 2 Applications 11 3 Description Interfaces to external IC standard parts such as serial RAMs LCDs tone generators A typical 1 C bus configuration is shown in Figure 20 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus Data transfer from a master tra
70. SCK1 MAT1 2 P0 16 EINTO MATO 2 CAPO 2 P0 15 RH EINT2 AD1 5 P1 21 PIPESTATO VDD Vss P0 14 DCD1 EINT1 SDA1 P1 22 PIPESTAT1 P0 13 DTR1 MAT1 1 AD1 4 P0 12 DSR1 MAT1 0 AD1 3 P0 11 CTS1 CAP1 1 SCL1 P1 23 PIPESTAT2 P0 10 RTS1 CAP1 0 AD1 2 P0 9 RXD1 PWM6 EINT3 P0 8 TXD1 PWM4 AD1 1 002aab407 6 2 Pin description for LPC2131 2 4 6 8 Pin description for LPC2131 2 4 6 8 and a brief explanation of corresponding functions are shown in the following table Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 66 Philips Semiconductors UM10120 ja Volume 1 Table 56 Pin description Chapter 6 Pin Configuration Symbol Pin Type Description P0 0 to P0 31 y o Port 0 Port 0 is a 32 bit I O port with individual direction controls for each bit Total of 30 pins of the Port 0 can be used as a general purpose bi directional digital I Os while P0 31 is output only pin The operation of port 0 pins depends upon the pin function selected via the pin connect block Pin P0 24 is not available P0 0 TXDO 1901 yo P0 0 General purpose digital input output pin PWM1 O TXDO Transmitter output for UARTO O PWM1 Pulse Width Modulator output 1 P0 1 RxDO0 2112 y o P0 1 General purpose digital input output pin PWMS EINTO l RxDO0 Receiver input for UARTO O PWM3 Pulse W
71. State change information is stored in UTMSR 2 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 RTSiL Output Request To Send Active low signal indicates that the UART1 would like to transmit data to the external modem The complement value of this signal is stored in U1MCR 1 1 LPC2134 6 8 only Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 95 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 10 UART1 10 3 Register description UART1 contains registers organized as shown in Table 76 The Divisor Latch Access Bit DLAB iscontained in U1LCR 7 and enables access to the Divisor Latches Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 96 soog eunf pc LO Ady jenuew sasn 16 peniesei SUBH IV S002 A N Soluoa9 3 Sdiliyd exfipiuiuoy Table 88 UART1 register map Name Description Bit functions and addresses Access Reset Address MSB LSB valuel BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO U1RBR Receiver Buffer 8 bit Read Data RO NA OxE001 0000 Register DLAB 0 U1THR Transmit Holding 8 bit Write Data WO NA OxE001 0000 Register DLAB 0 U1DLL Divisor Latch LSB 8 bit Data R W 0x01 0xE001 0000 DLAB 1 U1DLM Divisor Latch MSB 8 bit Data R W 0x00 OxE001 0004 DLAB 1 U1IER Interrupt Enable Reserved R
72. TIMERO TOMCR 0xE000 4014 and TIMER1 T1MCR 0xE000 8014 The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 149 Table 149 Match Control Register MCR TIMERO TOMCR address 0xE000 4014 and TIMER1 T1MCR address OxEO000 8014 bit description Bit Symbol Value Description Reset value 15 12 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 11 MR3S 1 Stop on MR3 the TC and PC will be stopped and TCR 0 will be set to 0 if MR3 matches 0 the TC 0 Feature disabled 10 MR3R 1 Reset on MR3 the TC will be reset if MR3 matches it 0 0 Feature disabled 9 MRSI 1 Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC 0 0 This interrupt is disabled 8 MR2S 1 Stop on MR2 the TC and PC will be stopped and TCR 0 will be set to 0 if MR2 matches 0 the TC 0 Feature disabled 7 MR2R 1 Reset on MR2 the TC will be reset if MR2 matches it 0 0 Feature disabled 6 MR2I 1 Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC 0 0 This interrupt is disabled 5 MR1S 1 Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches 0 the TC 0 Feature disabled 4 MR1R 1 Reset on MR1 the TC will be reset if
73. The time of break detection is dependent on UOFCR O Note The break interrupt is associated with the character at the top of the UARTO RBR FIFO 0 Break interrupt status is inactive 1 Break interrupt status is active 5 Transmitter THRE is set immediately upon detection of an empty UARTO THR and is 1 Holding cleared on a UOTHR write Register Empty UOTHR contains valid data THRE 1 UOTHR is empty 6 Transmitter TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when 1 Empty either the UOTSR or the UOTHR contain valid data MER 0 UOTHR and or the UOTSR contains valid data 1 UOTHR and the UOTSR are empty 7 Errorin RX UOLSR T is set when a character with a Rx error such as framing error parity 0 FIFO error or break interrupt is loaded into the UORBR This bit is cleared when the RXFE UOLSR register is read and there are no subsequent errors in the UARTO FIFO 0 UORBR contains no UARTO RX errors or UOFCR 0 0 1 UARTO RBR contains at least one UARTO RX error 9 3 10 UARTO Scratch pad register UOSCR 0xE000 C01C The UOSCR has no effect on the UARTO operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the UOSCR has occurred Table 85 UARTO Scratch pad register UOSCR address 0xE000 C01C bit description Bit Symbol Description Reset valu
74. This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Prescale Register PR TIMERO TOPR OxE000 400C and TIMER1 T1PR OxE000 800C The 32 bit Prescale Register specifies the maximum value for the Prescale Counter Prescale Counter Register PC TIMERO TOPC OxE000 4010 and TIMER1 T1PC OxEO00 8010 The 32 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc Match Registers MRO MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 175 Philips Semiconductors UM10120 Bb Volume 1 Chapter 14 TIMERO and TIMER1 14 5 8 Match Control Register MCR
75. UM1 01 20 ia Volume 1 19 4 2 19 4 3 19 4 4 Chapter 19 WDT Table 188 Watchdog Mode register WDMOD address 0xE000 0000 bit description Bit Symbol Description Reset value 0 WDEN WDEN Watchdog interrupt Enable bit Set Only 0 1 WDRESET WDRESET Watchdog Reset Enable bit Set Only 0 2 WDTOF WDTOF Watchdog Time Out Flag 0 Only after external reset 3 WDINT WDINT Watchdog interrupt Flag Read Only 0 TA Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Watchdog Timer Constant register WDTC 0xE000 0004 The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below OxFF will cause OxFF to be loaded to the WDTC Thus the minimum time out interval is Tpci x 256 x 4 Table 189 Watchdog Timer Constatnt register WDTC address 0xE000 0004 bit description Bit Symbol Description Reset value 31 0 Count Watchdog time out interval 0x0000 OOFF Watchdog Feed register WDFEED 0xE000 0008 Writing OxAA followed by 0x55 to this register will reload the watchdog timer to the WDTC value This operation will also start the watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the watchdog A valid feed sequence m
76. UORBR Read indication character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THRE UOIIR Read if source of interrupt or THR writell 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 9 3 9 UARTO Line Status Register UOLSR OxE000 C014 Read Only 3 For details see Section 9 3 1 UARTO Receiver Buffer Register UORBR 0xE000 C000 when DLAB 0 Read Only 4 For details see Section 9 3 6 UARTO Interrupt Identification Register UOIIR OXE000 C008 Read Only and Section 9 3 2 UARTO Transmit Holding Register UOTHR OxE000 C000 when DLAB 0 Write Only Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 89 Philips Semiconductors UM1 01 20 ja Volume 1 9 3 7 9 3 8 Chapter 9 UARTO The UARTO THRE interrupt UOIIR 3 1 001 is a third level interrupt and is activated when the UARTO THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UARTO THR FIFO a chance to fill up with data to eliminate many THRE inte
77. VECTORS FROM FLASH SRAM OR BOOT BLOCK 0x0000 0000 Note Memory regions are not drawn to scale Fig 6 Map of lower memory is showing re mapped and re mappable areas LPC2138 with 512 kB Flash Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 14 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 2 Memory map 2 3 Prefetch abort and data abort exceptions The LPC2131 2 4 6 8 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region The regions are Areas of the memory map that are not implemented for a specific ARM derivative For the LPC2131 2 4 6 8 this is Address space between On Chip Non Volatile Memory and On Chip SRAM labelled Reserved Address Space in Figure 2 and Figure 6 For 32 kB Flash device this is memory address range from 0x0000 8000 to Ox3FFF FFFF for 64 kB Flash device this is memory address range from 0x0001 0000 to Ox3FFF FFFF for 128 kB Flash device this is memory address range from 0x0002 0000 to Ox3FFF FFFF for 256 kB Flash device this is memory address range from 0x0004 0000 to Ox3FFF FFFF while for 512 kB Flash device this range is from 0x0008 0000 to Ox3FFF FFFF Address space between On Chip Static RAM and the Boot Block Labelled Reserved Address Space in Figure 2 For 8 kB SRAM device this is memory address range from 0x400
78. VS VL sorrak N A N AA N N N N sett N 7 y CPHA 0 Cycle CPHA CPHA 1 vosi ceha CO ami Kara ET Bray BTSY are a7 ETEK Fig 36 SPI data transfer format CPHA 0 and CPHA 1 The data and clock phase relationships are summarized in Table 125 This table summarizes the following for each setting of CPOL and CPHA When the first data bit is driven When all other data bits are driven When data is sampled Table 125 SPI data to clock phase relationship CPOL and CPHA settings Firsta data driven Other data driven Data sampled CPOL 0 CPHA 0 Prior to first SCK rising edge SCK falling edge SCK rising edge CPOL 0 CPHA 1 First SCK rising edge SCK rising edge SCK falling edge CPOL 1 CPHA 0 Prior to first SCK falling edge SCK rising edge SCK falling edge CPOL 1 CPHA 1 First SCK falling edge SCK falling edge SCK rising edge The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave and the setting of the CPHA variable When a device is a master the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted At this point the master can activate the clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 148 Phil
79. W OxE002 4028 DOM 5 Day of month value in the range of 1 to 28 29 30 R W OxE002 402C or 31 depending on the month and whether it is a leap year Ul DOW 3 Day of week value in the range of 0 to 6l R W OxE002 4030 DOY 9 Day of year value in the range of 1 to 365 366 for R W OxE002 4034 leap years Ul MONTH 4 Month value in the range of 1 to 12 R W OxE002 4038 YEAR 12 Year value in the range of 0 to 4095 R W OxE002 403C 1 These values are simply incremented at the appropriate intervals and reset at the defined overflow point They are not calculated and must be correctly initialized in order to be meaningful Leap year calculation The RTC does a simple bit comparison to see if the two lowest order bits of the year counter are zero If true then the RTC considers that year a leap year The RTC considers all years evenly divisible by 4 as leap years This algorithm is accurate from the year 1901 through the year 2099 but fails for the year 2100 which is not a leap year The only effect of leap year on the RTC is to alter the length of the month of February for the month day of month and year counters Alarm register group The alarm registers are shown in Table 180 The values in these registers are compared with the time counters If all the unmasked See Section 18 4 7 Alarm Mask Register AMR 0xE002 4010 on page 204 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is clea
80. Wait logic Figure 13 shows a simplified block diagram of the Memory Accelerator Module data paths In the following descriptions the term fetch applies to an explicit Flash read request from the ARM Pre fetch is used to denote a Flash read of instructions beyond the current processor fetch address Flash memory bank There is one bank of Flash memory with the LPC2131 2 4 6 8 MAM Flash programming operations are not controlled by the MAM but are handled as a separate function A boot block sector contains Flash programming algorithms that may be called as part of the application program and a loader that may be run to allow serial programming of the Flash memory Memory Address Flash Memory Bank BUFFERS Memory Data BUS INTERFACE ARM Local Bus Fig 13 Simplified block diagram of the Memory Accelerator Module MAM Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 43 Philips Semiconductors UM1 01 20 ja Volume 1 4 3 2 4 3 3 Chapter 4 MAM Module Instruction latches and data latches Code and Data accesses are treated separately by the Memory Accelerator Module There is a 128 bit Latch a 15 bit Address Latch and a 15 bit comparator associated with each buffer prefetch branch trail and data Each 128 bit latch holds 4 words 4 ARM instructions or 8 Thumb instructions Also associated with each buffer a
81. a read operation Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application 12C may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the 12C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer 0 Write 1 Read Data Transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START Condition P STOP Condition L From Master to Slave O From Slave to Master Fig 25 Format of Slave Transmitter mode Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 113 Philips Semiconductors UM1 01 20 m Volume 1 Chapter 11 I C interfaces 11 6 I C Implementation and operation Figure 26 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks 11 6 1 Input filters and output stages Input signals are s
82. addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free No I2DAT action 1 0 0 01 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 134 Philips Semiconductors UM1 01 20 ia Volume 1 11 8 5 11 8 6 11 8 7 Chapter 11 I C interfaces Miscellaneous States There are two I2STAT codes that do not correspond to a defined I C hardware state see Table 124 These are discussed below I2STAT z OxF8 This status code indicates that no relevant information is available because the serial interrupt flag SI is not yet set This occurs between other states and when the I C block is not involved in a serial transfer I2STAT 0x00 This status code indicates that a bus error has occurred during an I C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the internal 12C block signals When a bus error occurs SI is set To recover from a bus error
83. alarm NA 5 AMRDOY When 1 the Day of Year value is not compared for the alarm NA 6 AMRMON When 1 the Month value is not compared for the alarm NA 7 AMRYEAR When 1 the Year value is not compared for the alarm NA Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations The various registers are packed into 32 bit values as shown in Table 175 Table 176 and Table 177 The least significant bit of each register is read back at bit 0 8 16 or 24 The Consolidated Time Registers are read only To write new values to the Time Counters the Time Counter addresses should be used Consolidated Time register 0 CTIMEO OxE002 4014 The Consolidated Time Register 0 contains the low order time values Seconds Minutes Hours and Day of Week Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 204 Philips Semiconductors UM10120 ja Volume 1 18 4 10 18 4 11 18 4 12 Chapter 18 RTC Table 175 Consolidated Time register 0 CTIMEO address 0xE002 4014 bit description Bit Symbol Description Reset value 5 0 Seconds Seconds value in the range of 0 to 59 NA 7 6 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 13 8 Minutes Minut
84. and IO1DIR 0xE002 8018 This register is used to control the direction of the pins when they are configured as GPIO port pins Direction bit for any pin must be set according to the pin functionality Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 81 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 8 GPIO Table 70 GPIO Direction Register 0 IOODIR address 0xE002 8008 bit description Bit Symbol Value Description Reset value 31 0 POxDIR Direction control bits Bit 0 in IOODIR controls PO 0 0x0000 0000 Bit 30 in IOODIR controls P0 30 0 Controlled pin is input 1 Controlled pin is output Table 71 GPIO Direction Register 1 IO1DIR address 0xE002 8018 bit description Bit Symbol Value Description Reset value 31 0 P1xDIR Direction control bits Bit 0 in IO1DIR controls P1 0 0x0000 0000 Bit 30 in IO1DIR controls P1 30 0 Controlled pin is input 1 Controlled pin is output 8 5 GPIO usage notes 8 5 1 8 5 2 Example 1 sequential accesses to IOSET and IOCLR affecting the same GPIO pin bit State of the output configured GPIO pin is determined by writes into the pin s port IOSET and IOCLR registers Last of these accesses to the IOSET IOCLR register will determine the final output of a pin In case of a code IO0DIR 0x0000 0080 pin P0 7 configured as output IO0CLR 0x0000 0080 P0 7 goes LOW IO0S
85. and P0 28 e CAPO 3 1 pin P0 29 e CAP1 0 1 pin PO 10 e CAP1 1 1 pin PO 11 e CAP1 2 2 pins P0 17 and P0 19 e CAP1 3 2 pins P0 18 and P0 21 Timer Counter block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 14 5 3 Count Control Register CTCR TIMERO TOCTCR 0xE000 4070 and TIMER1 T1TCR OxEO00 8070 on page 174 MATO 3 0 Output External Match Output 0 1 When a match register 0 1 MR3 0 equals MAT1 3 0 the timer counter TC this output can either toggle go low go high or do nothing The External Match Register EMR controls the functionality of this output Match Output functionality can be selected on a number of pins in parallel It is also possible for example to have 2 pins selected at the same time so that they provide MAT1 3 function in parallel Here is the list of all MATCH signals together with pins on where they can be selected e MATO 0 2 pins P0 3 and P0 22 e MATO 1 2 pins P0 5 and P0 27 e MATO 2 2 pin P0 16 and P0 28 e MATO 3 1 pin P0 29 e MAT1 0 1 pin PO 12 MAT1 1 1 pin PO 13 e MAT1 2 2 pins P0 17 and P0 19 e MAT1 3 2 pins P0 18 and P0 20 14 5 Register description Each Timer Counter contains the registers shown in Table 145 More detailed descriptions follow Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005
86. as listed here Improper setting of this value may result in incorrect operation of the device 7 3 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 4 9 MAM usage notes When changing MAM timing the MAM must first be turned off by writing a zero to MAMCR A new value may then be written to MAMTIM Finally the MAM may be turned on again by writing a value 1 or 2 corresponding to the desired operating mode to MAMCR For system clock slower than 20 MHz MAMTIM can be 001 For system clock between 20 MHz and 40 MHz Flash access time is suggested to be 2 CCLKs while in systems with system clock faster than 40 MHz 3 CCLKs are proposed Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 47 UM10120 Chapter 5 Vectored Interrupt Controller VIC NNNM Rev 01 24 June 2005 User manual E 5 1 Features ARM PrimeCell Vectored Interrupt Controller 32 interrupt request inputs 16 vectored IRQ interrupts 16 priority levels dynamically assigned to interrupt requests Software interrupt generation 5 2 Description The Vectored Interrupt Controller VIC takes 32 interrupt request inputs and programmably assigns them into 3 categories FIQ vectored IRQ and non vectored IRQ The programmable assignment scheme means that priorities of interrupts from the various periph
87. be received and ACK will been returned be returned 0x78 Arbitration lost in No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK SLA R W as master will be returned General call address No jaDAT action X 0 0 1 Databyte will be received and ACK will has been received be returned ACK has been returned 0x80 Previously addressed Read data byte or X 0 0 0 Data byte will be received and NOT ACK with own SLV will be returned address DATA has Read data byte X 0 0 1 Databyte will be received and ACK will been received ACK be returned has been returned 0x88 Previously addressed Read data byte or 0 0 0 0 Switched to not addressed SLV mode no with own SLA DATA recognition of own SLA or General call byte has been address received NOT ACK Readdatabyteor 0 0 0 1 Switched to not addressed SLV mode has been returned Own SLA will be recognized General call address will be recognized if I2ADR O logic 1 Read data byte or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Read data byte 1 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O0 logic 1 A START condition will be transmitted when the bus becomes free 0x90 Previously addressed Read data byte or X 0 0 0 Data byte will be received and NOT ACK with General Call will be returned DATA byt
88. be set up and tested properly Details and case studies on spurious interrupts This chapter contains details that can be obtained from the official ARM website http Avww arm com FAQ section under the Technical Support link http www arm com support faqip 367 7 html What happens if an interrupt occurs as it is being disabled Applies to ARM7TDMI If an interrupt is received by the core during execution of an instruction that disables interrupts the ARM7 family will still take the interrupt This occurs for both IRQ and FIQ interrupts For example consider the following instruction sequence MRS r0 cpsr ORR r0 r0 4I Bit OR F Bit disable IRQ and FIQ interrupts MSR cpsr c r0 If an IRQ interrupt is received during execution of the MSR instruction then the behavior will be as follows e The IRQ interrupt is latched Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 59 Philips Semiconductors UM1 01 20 ia Volume 1 5 6 2 5 6 3 Chapter 5 VIC The MSR cpsr rO executes to completion setting both the bit and the F bit in the CPSR The IRQ interrupt is taken because the core was committed to taking the interrupt exception before the bit was set in the CPSR The CPSR with the bit and F bit set is moved to the SPSR_IRQ This means that on entry to the IRQ interrupt service routine you can see the unusual effect that an IRQ inte
89. being acknowledged cleared and further IRQs being disabled Similar code may also be applied to the FIQ handler in order to resolve the first issue This is the recommended workaround as it overcomes both problems mentioned above However in the case of problem two it does add several cycles to the maximum length of time FIQs will be disabled Solution 2 disable IRQs and FIQs using separate writes to the CPSR MRS r0 cpsr ORR r0 r0 I Bit disable IRQs MSR cpsr c r0 ORR r0 r0 4F Bit disable FIQs MSR cpsr c r0 This is the best workaround where the maximum time for which FlQs are disabled is critical it does not increase this time at all However it does not solve problem one and requires extra instructions at every point where IRQs and FIQs are disabled together Solution 3 re enable FIQs at the beginning of the IRQ handler As the required state of all bits in the c field of the CPSR are known this can be most efficiently be achieved by writing an immediate value to CPSR_C for example MSR cpsr_c I_Bit 0R irg_MODE IRQ should be disabled FIQ enabled ARM state IRQ mode This requires only the IRQ handler to be modified and FIQs may be re enabled more quickly than by using workaround 1 However this should only be used if the system can guarantee that FIQs are never disabled while IRQs are enabled It does not address problem one 5 7 VIC usage notes If user code is running from an on chip RAM and
90. bit as bus Master Own Slave Address Write has been received ACK has been returned Data will be received and ACK will be returned STA is set to restart Master mode after the bus is free again 1 Write 0x24 to I2CONSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up Slave Receive mode data buffer 4 Initialize Slave data counter Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 143 Philips Semiconductors UM1 01 20 iz Volume 1 5 Chapter 11 I C interfaces Exit 11 9 24 State 0x70 General call has been received ACK has been returned Data will be received and ACK returned 11 9 25 aR OUO N gt Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit State 0x78 Arbitration has been lost in Slave Address R W bit as bus Master General call has been received and ACK has been returned Data will be received and ACK returned STA is set to restart Master mode after the bus is free again ar O N gt Write 0x24 to I2CONSET to set the STA and AA bits Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit 11 9 26 State 0x80 Previously addressed with own Slave Address Data has been received and ACK
91. byte Arbitration lost and addressed as C posi cd Slave M To corresponding states in Slave mode From Master to Slave From Slave to Master DATA A Any number of data bytes and their associated Acknowledge bits This number contained in I2STA corresponds to a defined state of tP bus Fig 29 Format and States in the Master Transmitter mode Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 126 Philips Semiconductors UM10120 Volume 1 Chapter 11 I C interfaces Successful transmission to a Slave Transmitter Next transfer started with a Repeated Start condition Not Acknowledge Arbitration lost in Slave Address or Acknowledge bit Arbitration lost and addressed as Slave DATA e received after the Slave p Address i gt Other Master continues AORA Other Master continues To corresponding states in Slave mode From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits This number contained in I2STA corresponds to a defined state of tP bus Fig 30 Format and States in the Master Receiver mode D d d B To Master transmit mode entry MT Other Master continues i i Koninklijke Philips Electronics N V 2005 All rights reserved
92. core is halted An example of this would be to set the first breakpoint to 1 For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 237 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 21 EmbeddedICE trigger on an access to a peripheral and the second to trigger on the code segment that performs the task switching Therefore when the breakpoints trigger the information regarding which task has switched out will be ready for examination The watchpoints can be configured such that a range of addresses are enabled for the watchpoints to be active The RANGE function allows the breakpoints to be combined such that a breakpoint is to occur if an access occurs in the bottom 256 bytes of memory but not in the bottom 32 bytes The ARM7TDMI S core has a Debug Communication Channel function in built The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state The debug communication channel is accessed as a co processor 14 by the program running on the ARM7TDMI S core The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow The debug communication ch
93. following Table 184 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 209 Philips Semiconductors UM10120 ja Volume 1 Chapter 18 RTC For example if PREFRAC bit 14 is a one representing the fraction 1 2 then half of the cycles counted by the 13 bit counter need to be longer When there is a 1 in the LSB of the Fraction Counter the logic causes every alternate count whenever the LSB of the Fraction Counter 1 to be extended by one PCLK evenly distributing the pulse widths Similarly a one in PREFRAC bit 13 representing the fraction 1 4 will cause every fourth cycle whenever the two LSBs of the Fraction Counter 10 counted by the 13 bit counter to be longer Table 184 Prescaler cases where the Integer Counter reload value is incremented Fraction Counter PREFRAC Bit 14 1 13 12 11 109 8 7 6 54 3 2 1 0 1 10 0000 0000 0000 100 0000 0000 0000 18 7 RTC external 32 kHz oscillator component selection The RTC external oscillator circuit is shown in Figure 53 Since the feedback resistance is integrated on chip only a crystal the capacitances Cx and Cy need to be connected externally to the microcontroller Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 210 Philips Semiconductors UM1 01 20 ia Volume 1
94. for the PLL Divider value This is the value currently 0 used by the PLL y Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 8 PLLE Read back for the PLL Enable bit When one the PLL is currently 0 activated When zero the PLL is turned off This bit is automatically cleared when Power down mode is activated 9 PLLC Read back for the PLL Connect bit When PLLC and PLLE are both 0 one the PLL is connected as the clock source for the microcontroller When either PLLC or PLLE is zero the PLL is bypassed and the oscillator clock is used directly by the microcontroller This bit is automatically cleared when Power down mode is activated 10 PLOCK Reflects the PLL Lock status When zero the PLL is not locked 0 When one the PLL is locked onto the requested frequency 1541 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined PLL Interrupt The PLOCK bit in the PLLSTAT register is connected to the interrupt controller This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock When the interrupt occurs PLOCK 1 the PLL may be connected and the interrupt disabled PLL Modes The combinations of PLLE and PLLC are shown in Table 17 Table 17 PLL Control bit combinations PLLC PLLE PLL Function
95. is the START flag Setting this bit causes the I C interface to enter master mode and transmit a START condition or transmit a repeated START condition if it is already in master mode When STA is 1 and the I C interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the I C interface is already in master mode and data has been transmitted or received it transmits a repeated START condition STA may be set at any time including when the I C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register When STA is 0 no START condition or repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the I2C bus if it the interface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 119 Philips Semiconductors UM1 01 20 ij Volume 1 11 7 2 Chapter 11 I C interfaces STO is the STOP flag Setting this bit causes the I C interface to transmit a ST
96. not write ones to reserved bits NA The value read from a reserved bit is not defined 15 4 2 PWM Timer Control Register PWMTCR 0xE001 4004 The PWM Timer Control Register PWMTCR is used to control the operation of the PWM Timer Counter The function of each of the bits is shown in Table 157 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 187 Philips Semiconductors UM1 01 20 ja Volume 1 15 4 3 15 4 4 15 4 5 Chapter 15 PWM Table 157 PWM Timer Control Register PWMTCR address 0xE001 4004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the PWM Timer Counter and PWM Prescale 0 Counter are enabled for counting When zero the counters are disabled 1 Counter Reset When one the PWM Timer Counter and the PWM 0 Prescale Counter are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 3 PWM Enable When one PWM mode is enabled PWM mode causes 0 shadow registers to operate in connection with the Match registers A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set followed by the occurrence of a PWM Match 0 event Note that the PWM Match re
97. on PWMMR1 an interrupt is generated when PWMMR1 matches the value in the PWMTC This interrupt is disabled 1 PWMMR1R Reset on PWMMR 1 the PWMTC will be reset if PWMMR1 matches it This feature is disabled o l2 o0 5 PWMMR1S Stop on PWMMR1 the PWMTC and PWMPC will be stopped and PWMTCR O will be set to 0 if PWMMR1 matches the PWMTC This feature is disabled O 6 PWMMR2I Interrupt on PWMMR2 an interrupt is generated when PWMMR2 matches the value in the PWMTC This interrupt is disabled 7 PWMMR2R Reset on PWMMR2 the PWMTC will be reset if PWMMR2 matches it This feature is disabled Oo o 8 PWMMR2S Stop on PWMMR2 the PWMTC and PWMPC will be stopped and PWMTCR O will be set to 0 if PWMMR2 matches the PWMTC This feature is disabled 9 PWMMRS3I 1 Interrupt on PWMMR3 an interrupt is generated when PWMMR3 matches the value in the PWMTC 0 This interrupt is disabled 10 PWMMRSR 1 Reset on PWMMR3 the PWMTC will be reset if PWMMR3 matches it 0 This feature is disabled Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 189 Philips Semiconductors UM10120 B Volume 1 Chapter 15 PWM Table 158 Match Control Register MCR TIMERO TOMCR address 0xE000 4014 and TIMER1 T1MCR address OxEO000 8014 bit description Bit Symbol Value Description Reset value 11 PWMMRS3S 1 S
98. operation of the modem interface U1MCR A 0 the complement value of this signal is stored in U1MSR 4 State change information is stored in UTMSR 0 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 Input Data Carrier Detect Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged In normal operation of the modem interface U1MCRI 4 0 the complement value of this signal is stored in U1MSRI 7 State change information is stored in U1 MSR3 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 DSR1I I Input Data Set Ready Active low signal indicates if the external modem is ready to establish a ommunications link with the UART1 In normal operation of the modem interface U1MCR A 0 the complement value of this signal is stored in U1 MSR 5 State change information is stored in U1TMSR 1 and is a source for a priority level 4 interrupt if enabled U1IER S 1 DTR1lJ Output Data Terminal Ready Active low signal indicates that the UART1 is ready to establish connection with external modem The complement value of this signal is stored in U1MCR O RII Input Ring Indicator Active low signal indicates that a telephone ringing signal has been detected by the modem In normal operation of the modem interface U1MCR 4 0 the complement value of this signal is stored in Uf MSR 6
99. performance penalty Due to their tiny size and low power consumption these microcontrollers are ideal for applications where miniaturization is a key requirement such as access control and point of sale With a wide range of serial communications interfaces and on chip SRAM options of 8 16 32 kB they are very well suited for communication gateways and protocol converters soft modems voice recognition and low end imaging providing both large buffer size and high processing power Various 32 bit timers single or dual 10 bit 8 channel ADC s 10 bit DAC PWM channels and 47 GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems 16 32 bit ARM7TDMI S microcontroller in a tiny LQFP64 package 8 16 32 kB of on chip static RAM and 32 64 128 256 51 2 kB of on chip Flash program memory 128 bit wide interface accelerator enables high speed 60 MHz operation In System In Application Programming ISP IAP via on chip boot loader software Single Flash sector or full chip erase in 400 ms and 256 bytes programming in 1 ms EmbeddedICE and Embedded Trace interfaces offer real time debugging with the on chip RealMonitor software and high speed tracing of instruction execution One LPC2131 2 or two LPC2134 6 8 8 channel 10 bit A D converters provide s a total of up to 16 analog inputs with conversion times as low as 2 44 us per
100. required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at least one of the optional reads or writes of the SPI data register must take place in order to clear the SPIF status bit Exception conditions Read Overrun A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the processor and a new transfer has completed The read buffer containing valid data is indicated by the SPIF bit in the status register being active When a transfer completes the SPI block needs to move the received data to the read buffer If the SPIF bit is active the read buffer is full the new receive data will be lost and the read overrun ROVR bit in the status register will be activated Write Collision As stated previously there is no write buffer between the SPI block bus interface and the internal shift register As a result data must not be written to the SPI data register when a SPI data transfer is currently in progress The time frame where data cannot be written to the SPI data register is from when the transfer starts until after the status register has been read when the SPIF status is active If the SPI data register is written in this time frame the write data will be lost and the write collision WCOL bit in the status register will be activated Koninklijke Philips Electronics N V 2005 All rights reserved
101. s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only If the on chip PLL system or the boot loader is used the input clock frequency is limited to an exclusive range of 10 MHz to 25 MHz The oscillator output frequency is called Fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations etc elsewhere in this document Fosc and CCLK are the same value unless the PLL is running and connected Refer to the Section 3 7 Phase Locked Loop PLL on page 26 for details and frequency limitations The onboard oscillator in the LPC2131 2 4 6 8 can operate in one of two modes slave mode and oscillation mode In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF Cc in Figure 7 drawing a with an amplitude of at least 200 mVrms The X2 pin in this configuration can be left not connected If slave mode is selected the Fosc signal of 50 50 duty cycle can range from 1 MHz to 50 MHz External components and models used in oscillation mode are shown in Figure 7 drawings b and c and in Table 6 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cys need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C and Rs Capacitance Cp in Figure 7 drawing c represents the parallel package capacitance and should not be larger than 7 pF Par
102. sensitive mode when the pin is in its active state e g if EINT2 is selected to be low level sensitive and a low level is present on the corresponding pin this bit can not be cleared this bit can be cleared only when the signal on the pin becomes high 3 EINTS In level sensitive mode this bit is set if the EINT3 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT3 function is selected for its pin and the selected edge occurs on the pin Up to three pins can be selected to perform the EINT3 function see P0 9 P0 20 and P0 30 description in Pin Configuration chapter on page 64 This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state e g if EINT3 is selected to be low level sensitive and a low level is present on the corresponding pin this bit can not be cleared this bit can be cleared only when the signal on the pin becomes high 7 4 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 21 Philips Semiconductors UM1 01 20 ia Volume 1 3 5 3 3 5 4 Chapter 3 System Control Block Interrupt Wakeup register INTWAKE 0xE01F C144 Enable bits in the INTWAKE register allow the external interrupts to w
103. set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 101 Philips Semiconductors UM1 01 20 ja Volume 1 Table 96 Chapter 10 UART1 UART1 interrupt handling U1IIR 3 0 valuel 0001 Priority Interrupt Type Interrupt Source Interrupt Reset None None 0110 Highest RX Line Status Error OEBI or PEI or FEI or BIISI U1LSR Reads 0100 Second RX Data Available Rx data available or trigger level reached in FIFO U1RBR Read or U1FCRO 1 UART1 FIFO drops below trigger level 1100 Second Character Time out Minimum of one character in the RX FIFO and no U1RBR Readl4l indication character input or removed during a time period depending on how many characters are in FIFO and what the trigger
104. slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag SI is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine The appropriate action to be taken for each of these status codes is detailed in Table 104 The slave receiver mode may also be entered if arbitration is lost while the 12C block is in the master mode see status 0x68 and 0x78 If the AA bit is reset during a transfer the I C block will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the 12C block does not respond to its own slave address or a general call address However the C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the I2C block from the I C bus Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 125 Philips Semiconductors UM10120 m Volume 1 Chapter 11 I C interfaces MT Successful transmission to a Slave Receiver Next transfer started with a Repeated Start condition i T gt I Not Acknowledge received after the Slave Address To Master receive mode Not Acknowledge entry received after a Data A MR byte gt alae tnd E AORA Other Master AORA Other Master continues continues Data
105. the P1 16 P1 31 Output use of alternate functions 8 4 Register description LPC2131 2 4 6 8 has two 32 bit General Purpose I O ports Total of 30 input output and a single output only pin out of 32 pins are available on PORTO PORT1 has up to 16 pins available for GPIO functions PORTO and PORT are controlled via two groups of 4 registers as shown in Table 63 Table 63 GPIO register map Generic Description Access Reset PORTO PORT1 Name valuel Address amp Name Address amp Name IOPIN GPIO Port Pin value register The current R W NA OxE002 8000 OxE002 8010 state of the GPIO configured port pins can IOOPIN 101 PIN always be read from this register regardless of pin direction Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 79 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 8 GPIO Table 63 GPIO register map Generic Description Access Reset PORTO PORT1 Name valuel Address amp Name Address amp Name IOSET GPIO Port Output set register This register R W 0x0000 0000 OxE002 8004 OxE002 8014 controls the state of output pins in IOOSET IO1SET conjunction with the IOCLR register Writing ones produces highs at the corresponding port pins Writing zeroes has no effect IODIR GPIO Port Direction control register This R W 0x0000 0000 OxE002 8008 OxE002 8018 register individually controls the direction of IOODIR 101DIR e
106. the LS bits were converted e g 000 NA identifies channel 0 001 channel 1 29 27 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 30 OVERUN This bit is 1 in burst mode if the results of one or more conversions was were lost 0 and overwritten before the conversion that produced the result in the LS bits In non FIFO operation this bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared when this 0 register is read and when the ADCR is written If the ADCR is written while a conversion is still in progress this bit is set and a new conversion is started 16 4 3 A D Global Start Register ADGSR 0xE003 4008 Software can write this register to simultaneously initiate conversions on both A D controllers This register is available in LPC2134 6 8 devices only Table 165 A D Global Start Register ADGSR address 0xE003 4008 bit description Bit Symbol Value Description Reset value 150 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 16 BURST 1 The AD converters do repeated conversions at the rate selected by their CLKS fields 0 scanning if necessary through the pins selected by 1s in their SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher nu
107. the beginning of each cycle unless the output is a constant low Double edge controlled PWM outputs can have either edge occur at any position within a cycle This allows for both positive going and negative going pulses Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses Software must release new match values before they can become effective May be used as a standard timer if the PWM mode is not enabled A 32 bit Timer Counter with a programmable 32 bit Prescaler Four 32 bit capture channels take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The PWM is based on the standard Timer block and inherits all of its features although only the PWM function is pinned out on the LPC2131 2 4 6 8 The Timer is designed to count cycles of the peripheral clock PCLK and optionally generate interrupts or perform other actions when specified timer values occur based on seven match registers It also Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 181
108. the master transmitter mode by loading I2DAT with SLA W Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 124 Philips Semiconductors UM1 01 20 m Volume 1 11 8 3 Slave Receiver mode Chapter 11 I C interfaces In the slave receiver mode a number of data bytes are received from a master transmitter see Figure 31 To initiate the slave receiver mode I2ADR and I2CON must be loaded as follows Table 118 I2COADR and I2C1ADR usage in Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol own slave 7 bit address GC The upper 7 bits are the address to which the I C block will respond when addressed by a master If the LSB GC is set the I C block will respond to the general call address 0x00 otherwise it ignores the general call address Table 119 IZCOCONSET and I2C1CONSET used to initialize Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 1 The I C bus rate settings do not affect the 12C block in the slave mode I2EN must be set to logic 1 to enable the I2C block The AA bit must be set to enable the 12C block to acknowledge its own slave address or the general call address STA STO and SI must be reset When I2ADR and I2CON have been initialized the 12C block waits until it is addressed by its own slave address followed by the data direction bit which must be 0 W for the IC block to operate in the
109. timing and control logic generates the timing and control signals for serial byte handling This logic block provides the shift pulses for I2DAT enables the comparator generates and detects start and stop conditions receives and transmits acknowledge bits controls the master and slave modes contains interrupt request logic and monitors the I C bus status Control register I2ICONSET and I2CONCLR The I C control register contains bits used to control the following 12C block functions start and restart of a serial transfer termination of a serial transfer bit rate address recognition and acknowledgment Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 117 Philips Semiconductors UM10120 Volume 1 11 6 9 Chapter 11 I C interfaces The contents of the 12C control register may be read as IZCONSET Writing to IIBCONSET will set bits in the I C control register that correspond to ones in the value written Conversely writing to IICONCLR will clear bits in the I2C control register that correspond to ones in the value written Status decoder and Status register The status decoder takes all of the internal status bits and compresses them into a 5 bit code This code is unique for each I2C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine processes a particular bus status T
110. transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of the 8 bit control frame to be shifted out onto the SO pin CS remains LOW for the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP Each bit is driven onto SI line on the falling edge of SK The SSP in turn latches each bit on the rising edge of SK At the end of the frame for single transfers the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter that causes the data to be transferred to the receive FIFO Note The off chip slave device can tristate the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier or when the CS pin goes HIGH For continuous transfers data transmission begins and ends in the same manner as a single transfer However the CS line is continuously asserted held LOW and transmission of data occurs back to back The control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edg
111. when DLAB 0 Read Only The U1RBR is the top byte of the UART1 RX FIFO The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UTLCR must be zero in order to access the U1RBR The U1RBR is always Read Only Since PE FE and BI bits correspond to the byte sitting on the top of the RBR FIFO i e the one that will be read in the next read from the RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UTLSR register and then to read a byte from the U1RBR Table 89 UART1 Receiver Buffer Register U1RBR address 0xE001 0000 when DLAB 0 Read Only bit description Bit Symbol Description Reset value 7 0 RBR The UART1 Receiver Buffer Register contains the oldest undefined received byte in the UART1 RX FIFO UART1 Transmitter Holding Register U1THR 0xE001 0000 when DLAB 0 Write Only The U1THR is the top byte of the UART1 TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UTLCR must be zero in order to access the U1THR The U1THR is always Write Only Table 90 UART1 Transmitter Holding
112. when transferred 0 SPI data is transferred MSB bit 7 first 1 SPI data is transferred LSB bit O first 7 SPIE Serial peripheral interrupt enable 0 0 SPI interrupts are inhibited 1 A hardware interrupt is generated each time the SPIF or MODF bits are activated 11 8 BITS When bit 2 of this register is 1 this field controls the 0000 number of bits per transfer 1000 8 bits per transfer 1001 9 bits per transfer 1010 10 bits per transfer 1011 11 bits per transfer 1100 12 bits per transfer 1101 13 bits per transfer 1110 14 bits per transfer 1111 15 bits per transfer 0000 16 bits per transfer 1542 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined SPI Status Register SOSPSR 0xE002 0004 The SOSPSR register controls the operation of the SPIO as per the configuration bits setting Table 129 SPI Status Register SOSPSR address 0xE002 0004 bit description Bit Symbol Description Reset value 2 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 3 ABRT Slave abort When 1 this bit indicates that a slave abort has 0 occurred This bit is cleared by reading this register 4 MODF Mode fault when 1 this bit indicates that a Mode fault error has 0 occurred This bit is cleared by reading this register then writing the SPIO control register Koninklijke Philips Electronics N V 2
113. 0 0x1f ORR ri ri 0x1b MSR CPSR c rl Keep top 32 bytes for flash programming routines Refer to Flash Memory System and Programming chapter SUB sp r2 0x1F Initialize the Abort mode stack for RealMonitor BIC ri r0 0x1f ORR ri ri 0x17 MSR CPSR c rl Keep 64 bytes for Undef mode stack SUB sp r2 0x5F Initialize the IRQ mode stack for RealMonitor and User BIC ri r0 0x1f ORR ri ri 0x12 MSR CPSR c rl Keep 32 bytes for Abort mode stack SUB sp r2 0x7F Return to the original mode MSR CPSR_c r0 Initialize the stack for user application Keep 256 bytes for IRQ mode stack SUB sp r2 0x17F RRR RRR RRR RRR RRR R RRR RRR RRR RR ERR RRR RRR 2 2 4f 21 2 05 ff 4 fff RRR ERR RE KERR ERR EEK Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 250 Philips Semiconductors UM10120 ia Volume 1 Chapier 23 RealMonitor Setup Vectored Interrupt controller DCC Rx and Tx interrupts generate Non Vectored IRQ request rm_init_entry is aware of the VIC and it enables the DBGCommRX and DBGCommTx interrupts Default vector address register is programmed with the address of Non vectored app irgDispatch mentioned in this example User can setup Vectored IRQs or FIQs here RRR RRR RRR RE RR RRR RRR RRR RRR RR ER RRR RRR RRR RRR RRR RRR RRR RRR RR RR RRR REE o VICBaseAddr EQU OxFFFFF000 VIC Base address VICDefVectA
114. 0 Sample PWM waveforms Table 153 Set and reset inputs for PWM Flip Flops PWM Channel Single Edge PWM PWMSELn 0 Double Edge PWM PWMSELn 1 Set by Reset by Set by Reset by 1 Match 0 Match 1 Match oL Match 1 1 2 Match 0 Match 2 Match 1 Match 2 3 Match 0 Match 3 Match 2 2 Match 3 2 4 Match 0 Match 4 Match 3 Match 4 5 Match 0 Match 5 Match 4 2 Match 5 21 6 Match 0 Match 6 Match 5 Match 6 1 Identical to single edge mode in this case since Match 0 is the neighboring match register Essentially PWM1 cannot be a double edged output 2 Itis generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM outputs that are possible Using PWM 2 PWM4 and PWM6 for double edge PWM outputs provides the most pairings 15 2 1 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 184 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 15 PWM 2 Each PWM output will go low when its match value is reached If no match occurs i e the match value is greater than the PWM rate the PWM output remains continuously high 15 2 2 Rules for double edge controlled PWM outputs Five rules are used to det
115. 0 0 PLL is turned off and disconnected The system runs from the unmodified clock input 0 1 The PLL is active but not yet connected The PLL can be connected after PLOCK is asserted 1 0 Same as 00 combination This prevents the possibility of the PLL being connected without also being enabled 1 1 The PLL is active and has been connected as the system clock source PLL Feed register PLLFEED 0xE01F CO08C A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect The feed sequence is 1 Write the value OxAA to PLLFEED 2 Write the value 0x55 to PLLFEED Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 30 Philips Semiconductors UM1 01 20 ja Volume 1 3 7 8 3 7 9 Chapter 3 System Control Block The two writes must be in the correct sequence and must be consecutive VPB bus cycles The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation If either of the feed values is incorrect or one of the previously mentioned conditions is not met any changes to the PLLCON or PLLCFG register will not become effective Table 18 PLL Feed register PLLFEED address OxEO1F C08C bit description Bit Symbol Description Reset value 7 0 PLLFEED The PLL feed sequence must be written to this register in order for 0x00 PLL configuration
116. 0 2000 to Ox7FFF CFFF for 16 kB SRAM device this is memory address range from 0x4000 4000 to Ox7FFF CFFF while for 32 kB SRAM device this range is from 0x4000 8000 to Ox7FFF CFFF Address space between 0x8000 0000 and OxDFFF FFFF labelled Reserved Adress Space Reserved regions of the AHB and VPB spaces See Figure 3 Unassigned AHB peripheral spaces See Figure 4 Unassigned VPB peripheral spaces See Figure 5 For these areas both attempted data access and instruction fetch generate an exception In addition a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or VPB peripheral address Within the address space of an existing VPB peripheral a data abort exception is not generated in response to an access to an undefined address Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself For example an access to address 0xE000 D000 an undefined address within the UARTO space may result in an access to the register defined at address OxE000 C000 Details of such address aliasing within a peripheral space are not defined in the LPC2131 2 4 6 8 documentation and are not a supported feature Note that the ARM core stores the Prefetch Abort flag along with the associated instruction which will be meaningless in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the il
117. 00 SPIO I2C UART1 and UARTO are IRQ gt bitl0 bit9 bit7 and bit6 0 VICIntEnable 0x0000 06C0 SPIO I2C UART1 and UARTO are enabled interrupts gt bitl0 bit9 bit 7 and bit6 1 VICDefVectAddr 0x holds address at what routine for servicing non vectored IRQs i e UARTI and I2C starts VICVectAddr0 0x holds address where UARTO IRQ service routine starts VICVectAddrl 0x holds address where SPIO IRQ service routine starts VICVectCntl0 0x0000 0026 interrupt source with index 6 UART0 is enabled as the one with priority 0 the highest VICVectCntli 0x0000 002A interrupt source with index 10 SPI0 is enabled as the one with priority 1 After any of IRQ requests SPIO 12C UARTO or UART1 is made microcontroller will redirect code execution to the address specified at location 0x0000 0018 For vectored and non vectored IRQ s the following instruction could be placed at 0x0000 0018 LDR pc pc 0xFF0 This instruction loads PC with the address that is present in VIC VectAddr register Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 62 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 5 VIC In case UARTO request has been made VICVectAddr will be identical to VICVectAddrO while in case SPIO request has been made value from VICVectAddr1 will be found here If neither UARTO nor SPIO have generated IRQ request but UART1
118. 00 4038 OxE000 8038 TOCR3 T1CR3 EMR External Match Register The EMR controls the R W 0xE000 403C 0xE000 803C external match pins MATn 0 3 MATO 0 3 and TOEMR T1EMR MAT1 0 3 respectively CTCR Count Control Register The CTCR selects between R W Timer and Counter mode and in Counter mode selects the signal and edge s for counting OxEO000 4070 OxE000 8070 TOCTCR T1CTCR 1 Reset value relects the data stored in used bits only It does not include reserved bits content 14 5 1 Interrupt Register IR TIMERO TOIR OXEO000 4000 and TIMER1 T11R 0xE000 8000 The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 146 Interrupt Register IR TIMERO TOIR address 0xE000 4000 and TIMER1 T1IR address 0xE000 8000 bit description Bit Symbol Description Reset value 0 MRO Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt Interrupt flag for match channel 1 0 2 MR2 Interrupt Interrupt flag for match channel 2 0 3 MR3 Interrupt Interrupt flag for match channel 3 0 4 CRO Interrupt Interrupt flag for capture channel 0 event 0 5 CR1 Interrupt Interrupt flag for capture channel 1 event 0 6 CR2 Interrupt Inte
119. 005 All rights reserved User manual Rev 01 24 June 2005 153 Philips Semiconductors UM1 01 20 Volume 1 12 4 3 12 4 4 12 4 5 Chapter 12 SPI Table 129 SPI Status Register SOSPSR address 0xE002 0004 bit description Bit Symbol Description Reset value 5 ROVR Read overrun When 1 this bit indicates that a read overrun has 0 occurred This bit is cleared by reading this register 6 WCOL Write collision When 1 this bit indicates that a write collision 0 has occurred This bit is cleared by reading this register then accessing the SPI data register 7 SPIF SPI transfer complete flag When 1 this bit indicates when a SPI 0 data transfer is complete When a master this bit is set at the end of the last cycle of the transfer When a slave this bit is set on the last data sampling edge of the SCK This bit is cleared by first reading this register then accessing the SPI data register Note this is not the SPI interrupt flag This flag is found in the SPINT register SPI Data Register SOSPDR 0xE002 0008 This bi directional data register provides the transmit and receive data for the SPI Transmit data is provided to the SPI by writing to this register Data received by the SPI can be read from this register When a master a write to this register will start a SPI data transfer Writes to this register will be blocked from when a data transfer starts to when the SPIF status bit is set a
120. 0120 Volume 1 8 4 2 GPIO Output Set register 0 and 1 IOOSET OxEO002 8004 and IO1SET OxE002 8014 81 8 4 3 GPIO Output Clear register 0 and 1 IOOCLR OxE002 800C and IO1CLR OxE002 801C 81 8 4 4 GPIO Direction Register 0 and 1 IOODIR OxE002 8008 and IO1DIR OxE002 8018 81 8 5 8 5 1 8 5 2 8 5 3 Chapter 24 Supplementary information GPIO usage notes 82 Example 1 sequential accesses to IOSET and IOCLR affecting the same GPIO pin bit 82 Example 2 immediate output of Os and 1s ona GPIO Port RR RRRRERRREIAS 82 Writing to IOSET IOCLR vs IOPIN 83 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UARTO 9 1 Features 0 2 cee eee eee eee 84 9 2 Pin description 0 cence eee 84 9 3 Register description 84 9 3 1 UARTO Receiver Buffer Register UORBR OxE000 C000 when DLAB 0 Read Only 86 9 3 2 UARTO Transmit Holding Register UOTHR OxE000 C000 when DLAB 0 Write Only 86 9 3 3 UARTO Divisor Latch Registers 0 and 1 UODLL 0xE000 C000 and UODLM 0xE000 C004 when DEAB 1 5 rS Bees de 86 9 3 4 UARTO Baud rate calculation 87 9 3 5 UARTO Interrupt Enable Register UOIER OxE000 C004 when DLAB 0 87 9 3 10 9 3 11 9 4 UARTO Interrupt Identification Register UOIIR OxE000 C008 Read Only 88 UARTO FIFO Control Register UOFCR OxE000 C008
121. 1 24 June 2005 142 Philips Semiconductors UM1 01 20 m Volume 1 11 9 19 11 9 20 11 9 21 11 9 22 11 9 23 Chapter 11 I C interfaces State 0x50 Data has been received ACK has been returned Data will be read from I2DAT Additional data will be received If this is the last data byte then NOT ACK will be returned otherwise ACK will be returned Read data byte from I2DAT into Master Receive buffer Decrement the Master data counter skip to step 5 if not the last data byte Write OxOC to I2CONCLR to clear the SI flag and the AA bit Exit Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Master Receive buffer pointer Exit co OOF OON State 0x58 Data has been received NOT ACK has been returned Data will be read from I2DAT A Stop condition will be transmitted 1 Read data byte from I2DAT into Master Receive buffer 2 Write 0x14 to I2CONSET to set the STO and AA bits 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Exit Slave Receiver States State 0x60 Own Slave Address Write has been received ACK has been returned Data will be received and ACK returned Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2ZCONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit ar O N gt State 0x68 Arbitration has been lost in Slave Address and R W
122. 11 8 6 IPSTAT OXF8 ee sees 135 11 9 28 State 0x90 00 0 00002 145 11 8 7 I2STAT 0x00 lesse 135 11 9 29 State 0x98 80 145 11 8 8 Some special cases usse 136 11 9 30 State OxAO ce 145 11 8 9 Simultaneous repeated START conditions from 11 9 31 Slave Transmitter States 145 two masters cece eceeeeeeee 136 11 9 32 State OxA8 0 eee ee eee 145 11 8 10 Data transfer after loss of arbitration 136 11 9 33 State OxBO 0 ee eee e eee 145 11 811 Forced access to the I2C bus 136 11 9 84 State OxB8 008 146 11 9 85 State OxCO 0 eee eee eee 146 11 9 86 State OxC8 0008 146 Chapter 12 SPI Interface SPIO 12 1 Features 00 cece eee eee eee 147 12 2 1 SPI overview 0c cece eee eee 147 12 2 Description llle eens 147 12 2 2 SPI data transfers 005 147 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 266 Philips Semiconductors UM10120 ja Volume 1 Chapter 24 Supplementary information 12 2 8 General information 149 12 4 1 SPI Control Register 12 2 4 Master operation 0055 149 SOSPCR OxE002 0000 152 12 2 5 Slave operation n a naana anunua 150 12 4 2 SPI Status Register 12 2 6 Except
123. 16 0x0001 0000 External Interrupt 3 EINT3 17 0x0002 0000 ADCO A D Converter 0 end of conversion 18 0x0004 0000 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 57 Philips Semiconductors UM10120 ja Volume 1 Table 55 Connection of interrupt sources to the Vectored Interrupt Controller VIC Chapter 5 VIC Block Flag s VIC Channel and Hex Mask I2C1 SI state change 19 0x0008 0000 BOD Brown Out detect 20 0x0010 0000 ADC1 A D Converter 1 end of conversionlil 21 0x0020 0000 1 LPC2134 6 8 Only Interrupt request masking and selection rc LOGIC SOURCE ENABLE VECTORADDR VECTADDRO 31 0 VECTORCNTL 5 0 31 0 Vector interrupt 1 1 Priority1 VECTIRO4 VECTADDR1 31 0 Priority2 1 Vector interrupt 15 does VECTIRQ15 DEFAULT VECTORADDR VECTADDR15 31 0 31 0 Priority15 nVICIRQIN VICVECTADDRIN 31 0 Fig 14 Block diagram of the Vectored Interrupt Controller VIC Non vectored IRQ interrupt logic PE or pans ire IRQ VECTIRQO HARDWARE IRQ PRIORITY 7 highest priority Address select for interrupt dd aa ADDROUT 31 0 nVICIRQ VICVECT Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 58 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 5 VIC 5 6 Spurious interrupts 5 6 1 Spurio
124. 2 0xE002 401C The Consolidate Time register 2 contains just the Day of Year value Table 177 Consolidated Time register 2 CTIME2 address 0xE002 401C bit description Bit Symbol Description Reset value 11 0 Day of Year Day of year value in the range of 1 to 365 366 for leap years NA 31 12 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Time counter group The time value consists of the eight counters shown in Table 178 and Table 179 These counters can be read or written at the locations shown in Table 179 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 205 Philips Semiconductors UM1 01 20 ja Volume 1 18 4 13 18 4 14 Chapter 18 RTC Table 178 Time counter relationships and values Counter Size Enabled by Minimum value Maximum value Second 6 Clk1 see Figure 51 0 59 Minute 6 Second 0 59 Hour 5 Minute 0 23 Day of Month 5 Hour 1 28 29 30 or 31 Day of Week 3 Hour 0 6 Day of Year 9 Hour 1 365 or 366 for leap year Month 4 Day of Month 1 12 Year 12 Month or day of Year 0 4095 Table 179 Time counter registers Name Size Description Access Address SEC 6 Seconds value in the range of 0 to 59 R W OxE002 4020 MIN 6 Minutes value in the range of 0 to 59 R W OxE002 4024 HOUR 5 Hours value in the range of 0 to 23 R
125. 2 4 6 8 from capturing the bus or line activity that wakes it up Idle mode is more appropriate than power down mode for devices that must capture and respond to external activity in a timely manner To summarize on the LPC2131 2 4 6 8 the Wakeup Timer enforces a minimum reset duration based on the crystal oscillator and is activated whenever there is a wakeup from Power down mode or any type of Reset 3 12 Brown out detection The LPC2131 2 4 6 8 includes 2 stage monitoring of the voltage on the Vpp pins If this voltage falls below 2 9 V the Brown Out Detector BOD asserts an interrupt signal to the Vectored Interrupt Controller This signal can be enabled for interrupt in the Interrupt Enable register see Section 5 4 4 Interrupt Enable register VICIntEnable OxFFFF F010 on page 52 if not software can monitor the signal by reading the Raw Interrupt Status register see Section 5 4 3 Raw Interrupt status register VICRawIntr OxFFFF F008 on page 52 The second stage of low voltage detection asserts Reset to inactivate the LPC2131 2 4 6 8 when the voltage on the Vpp pins falls below 2 6 V This Reset prevents alteration of the Flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage The BOD circuit maintains this reset down below 1 V at which point the Power On Reset circuitry maintains the overall Reset Both the 2 9 V and 2 6 V thresholds include some h
126. 2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x28 Data byte in I2DAT Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will has been transmitted be received aes been No I2DAT action or 1 0 X Repeated START will be transmitted No I2DAT action or 0 1 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x30 Data byte in I2DAT Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will has been transmitted be received I c hasbeen NojppATactionor 1 0 0 X Repeated START will be transmitted l No I2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x38 Arbitration lost in No I2DAT action or 0 0 0 X I2C bus will be released not addressed SLA R W or Data slave will be entered bytes No I2DAT action 1 0 0 X ASTART condition wil be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 130 Philips Semiconductors UM10120 ia Volume 1 Table 121 Master Receiver mode Chapter 11 I
127. 3 11 7 4 Chapter 11 I C interfaces Table 109 I2C Control Set register IZCONCLR I2C0 I2COCONCLR address 0xE001 C018 and I2C1 I2C1CONCLR address 0xE005 C018 bit description Bit Symbol Description Reset value STAC START flag Clear bit 0 I2ENC 12C interface Disable bit 0 7 s Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined AAC is the Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit in the I2CONSET register Writing 0 has no effect SIC is the 12C Interrupt Clear bit Writing a 1 to this bit clears the SI bit in the I2CONSET register Writing O has no effect STAC is the Start flag Clear bit Writing a 1 to this bit clears the STA bit in the IACONSET register Writing O has no effect I2ENC is the I C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the I2CONSET register Writing 0 has no effect I C Status register I2STAT I2CO I2COSTAT OxE001 C004 and I2C1 I2C1STAT 0xE005 C004 Each 12C Status register reflects the condition of the corresponding I C interface The I C Status register is Read Only Table 110 I C Status register IBSTAT I2CO I2COSTAT address 0xE001 C004 and 12C1 I2C1STAT address 0xE005 C004 bit description Bit Symbol Description Reset value 2 0 These bits are unused and are always 0 0 7 3 Status These bits give the actual status information about t
128. 34 6 8 only P0 7 SSELO 31 2 y o P0 7 General purpose digital input output pin PWM2 EINT2 l SSELO Slave Select for SPIO Selects the SPI interface as a slave O PWM2 Pulse Width Modulator output 2 l EINT2 External interrupt 2 input Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 67 Philips Semiconductors UM10120 ia Volume 1 Table 56 Pin description continued Chapter 6 Pin Configuration Symbol Pin Type Description P0 8 TXD1 33 4 yo P0 8 General purpose digital input output pin PWM4 AD1 1 o TXD1 Transmitter output for UART1 O PWM4 Pulse Width Modulator output 4 l AD1 1 A D converter 1 input 1 This analog input is always connected to its pin Available in LPC2134 6 8 only P0 9 RxD1 34 2 yo P0 9 General purpose digital input output pin PWMB EINTS RxD1 Receiver input for UART1 O PWM6 Pulse Width Modulator output 6 l EINT3 External interrupt 3 input P0 10 RTS1 35 4 yo P0 10 General purpose digital input output pin CAP1 0 AD1 2 O RTS1 Request to Send output for UART1 Available in LPC2134 6 8 only l CAP1 0 Capture input for Timer 1 channel 0 l AD1 2 A D converter 1 input 2 This analog input is always connected to its pin Available in LPC2134 6 8 only P0 11 CTS1 37 3 y o P0 11 General purpose dig
129. 34 Crystal illat 18 3 7 6 PLL Modes 2 020000eeeeee 30 i LYSE OSOAN iis ait ee 3 7 7 PLL Feed register PLLFEED 0xE01F CO8C 30 3 5 External interrupt inputs 20 3 78 PLL and Power down mode 31 3 5 1 Register description BDEDEE 20 379 PLL frequency calculation 31 3 5 2 External Interrupt Flag register EXTINT 3 7 10 Procedure for detrmining PLL settings 32 OxEO1F C140 DIDI 20 EUG PLLexample is dite eiat teas 32 3 5 3 peo register INTWAKE 35 3 8 Power control 200eeceeceeeeees 33 xEO1F C144 002202000 2 eee e 354 External Interrupt Mode register EXTMODE 3 8 1 Register description RTT DICE 33 3 8 2 Power Control register OxEO1F C148 2 20 000 5 22 355 Ext Int t Polarit ister EXTPOLAR PCON OXEO1F COCO 33 P xternal Interrupt Polarity register 3 8 3 Power Control for Peripherals register PCONP OxEO1F C14C 220 020055 23 356 Multiple ext lint tpi 24 OxEO1F COCA 222 2005 34 P PARS SA erna Denn giei sin Seis 3 8 4 Power control usage notes 35 h ped riis d MAIER x0 a Seen ee een eer ere 35 i emory Mapping control register 3 9 1 Reset Source Identification Register RSIR OxEO1F C040 2 220 00055 25 OxEO1F C180 2 220000 5 37 3 6 2 Memory mapping control usage notes 26 ad 3 10 VPB divider sleessss 38 3 7 Phase
130. 3600 18 4320 19 6608 24 5760 25 0000 o tit Fo Echo lt setting gt Table 197 ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LFs turns echo off Write to RAM lt start address gt lt number of bytes gt The host should send the data only after receiving the CMD_SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum should be of the actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 J
131. 4080 bit description Bit Symbol Description Reset value 12 0 Prescaler Integer Contains the integer portion of the RTC prescaler value 0 1543 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Prescaler Fraction register PREFRAC 0xE002 4084 This is the fractional portion of the prescale value and may be calculated as PREFRAC PCLK PREINT 1 x 32768 Table 183 Prescaler Integer register PREFRAC address 0xE002 4084 bit description Bit Symbol Description Reset value 14 0 Prescaler Fraction Contains the integer portion of the RTC prescaler value 0 15 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Example of prescaler usage In a simplistic case the PCLK frequency is 65 537 kHz So PREINT int PCLK 32768 1 2 1 and PREFRAC PCLK PREINT 1 x 32768 1 With this prescaler setting exactly 32 768 clocks per second will be provided to the RTC by counting 2 PCLKs 32 767 times and 3 PCLKs once In a more realistic case the PCLK frequency is 10 MHz Then Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 208 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 18 RTC PREINT int PCLK 32768 1 304 and PREFRAC PCLK PREINT 1 x 32768 5 760 In
132. 5 20 8 4 Write to RAM start address gt 20 10 JTAG Flash programming interface 236 number of bytes gt 00 224 Chapter 21 EmbeddedICE logic 21 1 Features isa c oras a ee ee 237 21 3 Description 00 c cece eee eens 237 21 2 Applications 00 eee eee 237 21 4 Pin description sesese 238 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 269 Philips Semiconductors UM10120 fa Volume 1 Chapter 24 Supplementary information 21 5 Reset state of multiplexed pins 238 21 7 Block diagram 22 00 eee eee eee 239 21 6 Register description 239 Chapter 22 Embedded Trace Macrocell ETM 22 1 FeatUres i cece etek eee ae racha 240 22 4 Pin description 00 e eee eee 241 22 2 Applications 00 e eee eee 240 22 5 Reset state of multiplexed pins 241 22 3 Description iiec arn hn 240 22 6 Register description 242 22 3 1 ETM configuration 0 240 22 7 Block diagram Lsse 243 Chapter 23 RealMonitor 23 1 Featutes irre Rn ERE UREERA 244 23 44 SVC mode 20202 eee 247 232 Applications sse 244 23 4 5 Prefetch Abort mode 248 23 3 Description sese 244 ze Data hd LEE 249 23 3 1 RealMonitor components 245 3 4
133. 8 register R W 0 OxFFFF F220 VICVectCntl9 Vector control 9 register R W 0 OxFFFF F224 VICVectCntl10 Vector control 10 register R W 0 OxFFFF F228 viCVectCntl11 Vector control 11 register R W 0 OxFFFF F22C VICVectCntl12 Vector control 12 register R W 0 OxFFFF F230 VICVectCntl13 Vector control 13 register R W 0 OxFFFF F234 ViCVectCntl14 Vector control 14 register R W 0 OxFFFF F238 VICVectCntl15 Vector control 15 register R W 0 OxFFFF F23C 1 Reset value relects the data stored in used bits only It does not include reserved bits content 5 4 VIC registers 5 4 1 The following section describes the VIC registers in the order in which they are used in the VIC logic from those closest to the interrupt request inputs to those most abstracted for use by software For most people this is also the best order to read about the registers when learning the VIC Software Interrupt register VICSoftint OxFFFF F018 The contents of this register are ORed with the 32 interrupt requests from the various peripherals before any other logic is applied Table 34 Software Interrupt register VICSoftlnt address OxFFFF F018 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 sma Access R W R W R W R W R W R W R W R W Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 50 Philips Semiconductors UM10120
134. 9 SPI frame format with CPOL 0 and CPHA 0 a single and b continuous transfer SCK SSEL MOSI MISO mM 4 to 16 bits gt a Motorola SPI frame format single transfer with CPOL 0 and CPHA 0 b Motorola SPI frame format continuous transfer with CPOL 0 and CPHA 0 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data is transferred to the MOSI pin Now that both the master and slave data have been set the SCK master clock pin goes HIGH after one further half SCK period The data is now captured on the rising and propagated on the falling edges of the SCK signal Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 159 Philips Semiconductors UM1 01 20 ia Volume 1 13 3 5 Chapter 13 SSP In the case of a single word transmission after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back trans
135. AD 1 4131 29 28 P0 14 00 GPIO Port 0 14 0 01 Reservedll2 or DCD UART1 1 10 EINT1 11 SDA1 I2C1 31 30 P0 15 00 GPIO Port 0 15 0 01 Reserved or RI UART1 BSI 10 EINT2 11 Reservedl ll2 or AD1 5131 1 Available on LPC2131 2 Available on LPC2132 3 Available on LPC2134 6 8 7 4 2 Pin function Select register 1 PINSEL1 OxE002 C004 The PINSEL1 register controls the functions of the pins as per the settings listed in following tables The direction control bit in the IOODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 75 Philips Semiconductors UM10120 ja Volume 1 Chapter 7 Pin Connect Block Table 59 Pin function Select register 1 PINSEL1 address 0xE002 C004 bit description Bit Symbol Value Function Reset value 1 0 P0 16 00 GPIO Port 0 16 0 01 EINTO 10 Match 0 2 Timer 0 11 Capture 0 2 Timer 0 3 2 P0 17 00 GPIO Port 0 17 0 01 Capture 1 2 Timer 1 10 SCK SSP 11 Match 1 2 Timer 1 5 4 P0 18 00 GPIO Port 0 18 0 01 Capture 1 3 Timer 1 10 MISO SSP 11 Match 1 3 Timer 1 7 6 P0 19 00 GPIO Port 0 19 0 01 Match 1 2 Timer 1 10 MOSI SSP 11 Capture 1 2 Timer 1
136. AT I2C1DAT master or slave receive mode data that has been received may be read from this register I2ADR I C Slave Address Register Contains the 7 bit slave R W 0x00 OxE001 COOC 0xE005 COOC address for operation of the I C interface in slave mode I2COADR I2C1ADR and is not used in master mode The least significant bit determines whether a slave responds to the general call address I2SCLH SCH Duty Cycle Register High Half Word Determines R W 0x04 OxE001 C010 OxE005 C010 the high time of the 12C clock I2COSCLH I2C1SCLH I2SCLL SCL Duty Cycle Register Low Half Word Determines R W 0x04 OxE001 C014 OxEO005 C014 the low time of the I2C clock I2nSCLL and I2nSCLH I2COSCLL I2C1SCLL together determine the clock frequency generated by an 12C master and certain times used in slave mode I2CONCLR I2C Control Clear Register When a one is written toa WO NA OxE001 C018 OxE005 C018 bit of this register the corresponding bit in the 12C control I2COCONCLR 12C1CONCLR register is cleared Writing a zero has no effect on the corresponding bit in the 12C control register 1 Reset value relects the data stored in used bits only It does not include reserved bits content Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 118 Philips Semiconductors UM1 01 20 iz Volume 1 11 7 1 Chapter 11 I C interfaces I C Control Set register IZCONSET I2CO I2COCONSET 0xE001 C000 a
137. Address valuel External Interrupts EXTINT External Interrupt Flag Register R W 0 OxEO1F C140 EXTWAKE External Interrupt Wakeup Register R W 0 OxEO1F C144 EXTMODE External Interrupt Flag register R W 0 OxEO1F C148 _ EXTPOLAR External Interrupt Wakeup Register R W 0 OxEO1F C14C Memory Mapping Control MEMMAP Memory Mapping Control R W 0 0xE01F C040 Phase Locked Loop PLLCON PLL Control Register R W 0 0xE01F C080 PLLCFG PLL Configuration Register R W 0 OxEO1F C084 PLLSTAT PLL Status Register RO 0 OxEO1F C088 PLLFEED PLL Feed Register WO NA OxEO1F C08C Power Control PCON Power Control Register R W 0 OxEO1F COCO PCONP Power Control for Peripherals R W 0x03BE OxEO1F COCA VPB Divider VPBDIV VPB Divider Control R W 0 OxEO1F C100 Reset RSID Reset Source Identification Register R W 0 OxEO1F C180 Code Security Debugging CSPR Code Security Protection Register RO o OxEO1F C184 1 Reset value relects the data stored in used bits only It does not include reserved bits content Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 17 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 3 System Control Block 3 4 Crystal oscillator While an input signal of 50 50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC2131 2 4 6 8 if supplied to its input XTAL1 pin this microcontroller
138. B VLSI peripheral bus TMS9 TDI 3 XTAL2 TRST TeK TDO XTAL1 RST TEST DEBUG o LPC2131 2132 2134 2136 2138 INTERFACE u ie SYSTEM amp 5 FUNCTIONS ARM7TDM S o lt system 5 clock VECTORED N CONTROLLER ARN7 local bus x AMBA AHB Advanced High performance Bus AHB TO VPB VPB BRIDGE DIVIDER AHB DECODER SCLO 1 iU gt C KE c ONG 1 SDAO 1 8 x CAPO CAPTURE SCKO 1 COMPARE SPI AND SSP MOSIO 1 8 x MAT TIMER O TIMER 1 C SERIAL INTERFACES MISOO 1 SSELO 1 ABONA A D CONVERTERS TXDO 1 Ao oe UARTO UART RXDO 1 DSR1 1 cTS1 1 RTS1 0 DTR1 AOUTO D A CONVERTER 5 DCD1 RHC RTXC1 REAL TIME CLOCK RTXC2 ii TE Ka Vear PURPOSE I O ee TIMER PWMe 1 PWMO C y SYSTEM CONTROL nd 002aab067 1 LPC2134 2136 2138 only 2 LPC2132 2134 2136 2138 only 3 Pins shared with GPIO Fig 1 LPC2131 2 4 6 8 block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 7 Semiconductors UM10120 Chapter 2 LPC2131 2 4 6 8 Memory Addressing 2 1 Memory maps Rev 01 24 June 2005 User manual The LPC2131 2 4 6 8 incorporates several distinct memory regions shown in the following figures Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping which is described later i
139. C Interface as a Slave and or Master 1 Load I2ADR with own Slave Address enable general call recognition if needed 2 Enable I C interrupt 3 Write 0x44 to I2CONSET to set the I2EN and AA bits enabling Slave functions For Master only funcitons write 0x40 to I2ZCONSET 11 9 2 Start Master Transmit function Begin a Master Transmit operation by setting up the buffer pointer and data count then initiating a Start Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 139 Philips Semiconductors UM1 01 20 iz Volume 1 Chapter 11 I C interfaces Initialize Master data counter Setup the Slave Address to which data will be transmitted and add the Write bit Write 0x20 to I2ZCONSET to set the STA bit Set up data to be transmitted in Master Transmit buffer Initialize the Master data counter to match the length of the message being sent Exit o c A UN 11 9 3 Start Master Receive function 11 9 4 11 9 5 11 9 6 11 9 7 11 9 8 Begin a Master Receive operation by setting up the buffer pointer and data count then initiating a Start Initialize Master data counter Set up the Slave Address to which data will be transmitted and add the Read bit Write 0x20 to I2ZCONSET to set the STA bit Set up the Master Receive buffer Initialize the Master data counter to match the length of the message to be received Exit ona
140. CCESS BUSY INVALID SECTOR PARAM ERROR Description This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to Flash Flash address RAM address gt no of bytes gt Table 201 ISP Copy command Command Input C Flash Address DST Destination Flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRO Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 256 512 1024 4096 Return Code CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 256 512 1024 4096 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again o
141. CO External Match Control 0 Determines the functionality of External Match 0 Table 152 00 shows the encoding of these bits 7 6 EMC1 External Match Control 1 Determines the functionality of External Match 1 Table 152 00 shows the encoding of these bits 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 Table 152 00 shows the encoding of these bits 11 10 EMC3 External Match Control 3 Determines the functionality of External Match 3 Table 152 00 shows the encoding of these bits 15 12 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 178 Philips Semiconductors UM1 01 20 Bb Volume 1 Chapter 14 TIMERO and TIMER Table 152 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 MATn m pin is LOW if pinned out 10 Set the corresponding External Match bit output to 1 MATn m pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 14 6 Example timer operation Figure 46 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer c
142. CONTROL REGISTER CAPTURE REGISTER 0 B a CAPTURE REGISTER 1 p TIMER COUNTER CE PCLK PRESCALE COUNTER RESET ENABLE MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Note that the capture register 3 cannot be used on TIMERO CAPTURE REGISTER 2 CAPTURE REGISTER 3 Fig 48 Timer block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 180 Semiconductors 15 1 Features UM10120 Chapter 15 Pulse Width Modulator PWM Rev 01 24 June 2005 User manual iE LPC2131 2 4 6 8 Pulse Width Modulator is based on standard Timer Counter 0 1 described in the previous chapter Application can choose among PWM and match functions available 15 2 Description Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs or a mix of both types The match registers also allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation An external output for each match register with the following capabilities Setlow on match Set high on match Toggle on match Do nothing on match Supports single edge controlled and or double edge controlled PWM outputs Single edge controlled PWM outputs all go high at
143. DOM When 1 an increment of the Day of Month value generates an interrupt NA 4 IMDOW When 1 an increment of the Day of Week value generates an interrupt NA 5 IMDOY When 1 an increment of the Day of Year value generates an interrupt NA 6 IMMON When 1 an increment of the Month value generates an interrupt NA 7 IMYEAR When 1 an increment of the Year value generates an interrupt NA Alarm Mask Register AMR OxE002 4010 The Alarm Mask Register AMR allows the user to mask any of the alarm registers Table 174 shows the relationship betweenthe bits in the AMR and the alarms For the alarm function every non masked alarm register must match the corresponding time counter for an interrupt to be generated The interrupt is generated only when the counter comparison first changes from no match to match The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register ILR If all mask bits are set then the alarm is disabled Table 174 Alarm Mask Register AMR address 0xE002 4010 bit description Bit Symbol Description Reset value 0 AMRSEC When 1 the Second value is not compared for the alarm NA 1 AMRMIN When 1 the Minutes value is not compared for the alarm NA 2 AMRHOUR When 1 the Hour value is not compared for the alarm NA 3 AMRDOM When 1 the Day of Month value is not compared for the alarm NA 4 AMRDOW When 1 the Day of Week value is not compared for the
144. Data in for JTAG interface P1 29 TCK 5616 y o P1 29 General purpose digital input output pin l TCK Test Clock for JTAG interface P1 30 TMS 5216 y o P1 30 General purpose digital input output pin TMS Test Mode Select for JTAG interface P1 31 TRST 2018 yo P1 31 General purpose digital input output pin I TRST Test Reset for JTAG interface RESET 571 l External reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 TTL with hysteresis 5 V tolerant XTAL1 6218 l Input to the oscillator circuit and internal clock generator circuits XTAL2 6118 O Output from the oscillator amplifier RTXC1 318 l Input to the RTC oscillator circuit RTXC2 518 O Output from the RTC oscillator circuit Vss 6 18 25 42 Ground 0 V reference 50 Vssa 59 l Analog Ground 0 V reference This should nominally be the same voltage as Vss but should be isolated to minimize noise and error Vpp 23 43 51 l 3 3 V Power Supply This is the power supply voltage for the core and I O ports VbppA 7 Analog 3 3 V Power Supply This should be nominally the same voltage as Vpp but should be isolated to minimize noise and error This voltage is used to power the ADC s VREF 63 l A D Converter Reference This should be nominally the same voltage as Vpp but should be isolated to minimize noise and error Level on this pin is use
145. E002 0000 bit description Bit Symbol Value Description Reset value 1 0 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 2 BitEnable 0 The SPI controller sends and receives 8 bits of data per 0 transfer 1 The SPI controllert sends and receives the number of bits selected by bits 11 8 3 CPHA Clock phase control determines the relationship between 0 the data and the clock on SPI transfers and controls when a slave transfer is defined as starting and ending Data is sampled on the first clock edge of SCK A transfer 0 starts and ends with activation and deactivation of the SSEL signal 1 Data is sampled on the second clock edge of the SCK A transfer starts with the first clock edge and ends with the last sampling edge when the SSEL signal is active 4 CPOL Clock polarity control 0 0 SCK is active high SCK is active low 5 MSTR Master mode select 0 0 The SPI operates in Slave mode 1 The SPI operates in Master mode Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 152 Philips Semiconductors UM10120 ja Volume 1 12 4 2 Chapter 12 SPI Table 128 SPI Control Register SOSPCR address 0xE002 0000 bit description Bit Symbol Value Description Reset value 6 LSBF LSB First controls which direction each byte is shifted 0
146. ET 0x0000 0080 P0 7 goes HIGH IO0CLR 0x0000 0080 P0 7 goes LOW pin PO 7 is configured as an output write to IOODIR register After this PO 7 output is set to low first write to IOOCLR register Short high pulse follows on PO 7 write access to IOOSET and the final write to IOOCLR register sets pin PO 7 back to low level Example 2 immediate output of Os and 1s on a GPIO port Write access to port s IOSET followed by write to the IOCLR register results with pins outputting Os being slightly later then pins outputting 1s There are systems that can tolerate this delay of a valid output but for some applications simultaneous output of a binary content mixed Os and 1s within a group of pins on a single GPIO port is required This can be accomplished by writing to the port s IOPIN register Following code will preserve existing output on PORTO pins PO 31 16 and PO 7 0 and at the same time set PO 15 8 to 0xA5 regardless of the previous value of pins PO 15 8 IOOPIN IO0PIN amp amp 0xFFFFOOFF 0x0000A500 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 82 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 8 GPIO 8 5 3 Writing to IOSET IOCLR vs IOPIN Write to IOSET IOCLR register allows easy change of port s selected output pin s to high low level at a time Only pin bit s in IOSET IOCLR written with 1 will be set to high low level w
147. Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 166 Philips Semiconductors UM1 01 20 Volume 1 Chapter 13 SSP 13 4 3 SSP Data Register SSPDR 0xE006 8008 13 4 4 13 4 5 Software can write data to be transmitted to this register and read data that has been received Table 137 SSP Data Register SSPDR address 0xE006 8008 bit description Bit Symbol Description Reset value 15 0 DATA Write software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1 indicating that the Tx FIFO is not full If the Tx FIFO was previously empty and the SSP controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received If the data length is less than 16 bits software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SSP controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bits the data is right justified in this field with higher order bits filled with Os SSP Status Register SSPSR 0xE006 800C This read only register reflects the current status of the SSP co
148. F014 software to clear one or more bits in the Interrupt Enable register VICSoftInt Software Interrupt Register The contents of this register are R W 0 OxFFFF F018 ORed with the 32 interrupt requests from various peripheral functions VICSoftIntClear Software Interrupt Clear Register This register allows WO 0 OxFFFF F01C software to clear one or more bits in the Software Interrupt register VICProtection Protection enable register This register allows limiting R W 0 OxFFFF F020 access to the VIC registers by software running in privileged mode VICVectAddr Vector Address Register When an IRQ interrupt occurs the R W 0 OxFFFF F030 IRQ service routine can read this register and jump to the value read ViCDefVectAddr Default Vector Address Register This register holds the R W 0 OxFFFF F034 address of the Interrupt Service routine ISR for non vectored IRQs VICVectAddrO Vector address 0 register Vector Address Registers 0 15 R W 0 OxFFFF F100 hold the addresses of the Interrupt Service routines ISRs for the 16 vectored IRQ slots VICVectAddr1 Vector address 1 register R W 0 OxFFFF F104 VICVectAddr2 Vector address 2 register R W 0 OxFFFF F108 ViCVectAddr3 Vector address 3 register R W 0 OxFFFF F10C ViCVectAddr4 Vector address 4 register R W 0 OxFFFF F110 ViCVectAddr5 Vector address 5 register R W 0 OxFFFF F114 ViCVectAddr6 Vector address 6 register R W 0 OxFFFF F118 ViCVe
149. FS Microwire CS Pin Description Slave Select Frame Sync Chip Select When the SSP is a bus master it drives this signal from shortly before the start of serial data to shortly after the end of serial data to signify a data transfer as appropriate for the selected bus and mode When the SSP is a bus slave this signal qualifies the presence of data from the Master according to the protocol in use When there is just one bus master and one bus slave the Frame Sync or Slave Select signal from the Master can be connected directly to the slave s corresponding input When there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISO1 O MISO DR M SI M SO S Master In Slave Out The MISO signal transfers serial data from the slave to the master When the SSP is a slave serial data is output on this signal When the SSP is a master it clocks in serial data from this signal When the SSP is a slave and is not selected by SSEL it does not drive this signal leaves it in high impedance state MOSI VO MOSI DX M DR S SO M SI S Master Out Slave In The MOSI signal transfers serial data from the master to the slave When the SSP is a master it outputs serial data on this signal When the SSP is a slave it clocks in serial data from this signal 13 3 Bus description
150. FWD I C interrupt routine Determine the 12C state and which state routine will be used to handle it 1 Read the I C status from I2STA 2 Use the status value to branch to one of 26 possible state routines Non mode specific States State 0x00 Bus Error Enter not addressed Slave mode and release bus 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit Master States State 08 and State 10 are for both Master Transmit and Master Receive modes The R W bit decides whether the next state is within Master Transmit mode or Master Receive mode State 0x08 A Start condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit will be received 1 Write Slave Address with R W bit to I2DAT 2 Write 0x04 to I2CONSET to set the AA bit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 140 Philips Semiconductors UM1 01 20 iz Volume 1 Chapter 11 I C interfaces Write 0x08 to IZCONCLR to clear the SI flag Set up Master Transmit mode data buffer Set up Master Receive mode data buffer Initialize Master data counter Exit N DO oO Ff CO 11 9 9 State 0x10 11 9 10 11 9 11 11 9 12 11 9 13 A repeated Start condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit will be received Write Slave Address with
151. IER S3 1 identifies an interrupt corresponding to the 0 UARTO Rx FIFO All other combinations of UOIER 3 1 not listed above are reserved 000 100 101 111 1 Receive Line Status RLS 010 2a Receive Data Available RDA 110 2b Character Time out Indicator CTI 001 3 THRE Interrupt 5 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 6 FIFO Enable These bits are equivalent to UOFCR O 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 88 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 9 UARTO Interrupts are handled as described in Table 81 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The UOIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UARTO RLS interrupt UOIIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTO Rx input overrun error OE parity error PE framing error FE and break interrupt BI The UARTO Rx error condition that set the interrupt can be observed via UOLSR 4 1 The interrupt is cleared upon an UOLSR read The UARTO RDA interrupt UOIIR 3 1 010 shares the second level priority with the CTI int
152. IOOSET address 0xE002 8004 bit description Bit Symbol Description Reset value 31 0 POxSET Output value SET bits Bit 0 in IOOSET corresponds to PO 0 0x0000 0000 Bit 31 in IOOSET corresponds to P0 31 Table 67 GPIO Output Set register 1 IO1SET address 0xE002 8014 bit description Bit Symbol Description Reset value 31 0 P1xSET Output value SET bits Bit 0 in IO1SET corresponds to P1 0 0x0000 0000 Bit 31 in IO1SET corresponds to P1 31 GPIO Output Clear register 0 and 1 IOOCLR OxE002 800C and IO1CLR OxE002 801C This register is used to produce a LOW level at port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register Writing O has no effect If any pin is configured as an input or a secondary function writing to IOCLR has no effect Table 68 GPIO Output Clear register 0 IOOCLR address 0xE002 800C bit description Bit Symbol Description Reset value 31 0 POxCLR Output value CLEAR bits Bit 0 in IOOCLR corresponds to 0x0000 0000 PO 0 Bit 31 in IOOCLR corresponds to P0 31 Table 69 GPIO Output Clear register 1 IO1CLR address 0xE002 801C bit description Bit Symbol Description Reset value 31 0 P1xCLR Output value CLEAR bits Bit 0 in IO1CLR corresponds to 0x0000 0000 P1 0 Bit 31 in IO1CLR corresponds to P1 31 GPIO Direction Register 0 and 1 IOODIR OxE002 8008
153. IRQ and asserted reading from this register returns the address in the Vector Address Register for the highest priority such slot lowest numbered such slot Otherwise it returns the address in the Default Vector Address Register Writing to this register does not set the value for future reads from it Rather this register should be written near the end of an ISR to update the priority hardware 5 4 13 Protection Enable register VICProtection OXFFFF F020 This is a read write accessible register This one bit register controls access to the VIC registers by software running in User mode Table 54 Protection Enable register VICProtection address OxFFFF F020 bit description Bit Symbol Value Description Reset value 0 VIC access 0 VIC registers can be accessed in User or privileged mode 0 1 The VIC registers can only be accessed in privileged mode 31 1 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 56 Philips Semiconductors UM10120 ja Volume 1 5 5 Interrupt sources Chapter 5 VIC Table 55 lists the interrupt sources for each peripheral function Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller but may have several internal interrupt flags Individual interrupt flags may also represen
154. LR to clear the SI flag 4 Set up Slave Transmit mode data buffer 5 Increment Slave Transmit buffer pointer 6 Exit 11 9 34 State 0xB8 Data has been transmitted ACK has been received Data will be transmitted ACK bit will be received Load I2DAT from Slave Transmit buffer with data byte Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Slave Transmit buffer pointer Exit ar OO N gt 11 9 35 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 36 State 0xC8 The last data byte has been transmitted ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 146 UM10120 Chapter 12 SPI Interface SPIO Rev 01 24 June 2005 User manual ET Semiconductors 12 1 Features Single complete and independent SPI controller Compliant with Serial Peripheral Interface SPI specification Synchronous Serial Full Duplex Communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8to 16 bits per transfer 12 2 Descriptio
155. M10120 ja Volume 1 Chapier 18 RTC 18 4 Register description The RTC includes a number of registers The address space is split into four sections by functionality The first eight addresses are the Miscellaneous Register Group Section 18 4 2 The second set of eight locations are the Time Counter Group Section 18 4 12 The third set of eight locations contain the Alarm Register Group Section 18 4 14 The remaining registers control the Reference Clock Divider The Real Time Clock includes the register shown in Table 168 Detailed descriptions of the registers follow Table 168 Real Time Clock RTC register map Name Size Description Access Reset Address valuel ILR 2 Interrupt Location Register R W OxE002 4000 CTC 15 Clock Tick Counter RO ii OxE002 4004 CCR 4 Clock Control Register R W 2 OxE002 4008 CIIR 8 Counter Increment Interrupt Register R W OxE002 400C AMR 8 Alarm Mask Register R W d OxE002 4010 CTIMEO 32 Consolidated Time Register 0 RO 0xE002 4014 CTIME1 32 Consolidated Time Register 1 RO OxE002 4018 CTIME2 32 Consolidated Time Register 2 RO i OxE002 401C SEC 6 Seconds Counter R W 7 OxE002 4020 MIN 6 Minutes Register R W OxE002 4024 HOUR 5 Hours Register R W 7 OxE002 4028 DOM 5 Day of Month Register R W OxE002 402C DOW 3 Day of Week Register R W 0xE002 4030 DOY 9 Day of Year Register R W 2 OxE002 4034 MONTH 4 Months Reg
156. MERO ARMCore1 ARMCoreO WDT Access RO RO RO RO RO RO PO RO Table 39 Raw Interrupt status register VICRawlnir address OxFFFF F008 bit description Bit Symbol Value Description Reset value 31 0 See 0 The interrupt request or software interrupt with this bit number is 0 VICRawintr bit negated allocation 1 The interrupt request or software interrupt with this bit number is table negated 5 4 4 Interrupt Enable register VICIntEnable OXFFFF F010 This is a read write accessible register This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ Table 40 Interrupt Enable register VICIntEnable address OxFFFF F010 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol Access R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Symbol B ADi BOD 1201 ADO EINT3 EINT2 Access R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPI1 SSP SPIO 12C0 PWMO Access R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMERI TIMERO ARMCorei ARMCore0 WDT Access R W R W R W R W R W R W R W R W Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 52 Philips Semiconductors UM10120 ja Volume 1 Chapter 5 VIC Table 41 Interrupt Enable register VICIn
157. MR1 matches it 0 0 Feature disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 This interrupt is disabled 2 MROS 1 Stop on MRO the TC and PC will be stopped and TCR 0 will be set to 0 if MRO matches 0 the TC 0 Feature disabled 1 MROR 1 Reset on MRO the TC will be reset if MRO matches it 0 0 Feature disabled 0 MROI 1 Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 0 This interrupt is disabled Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 176 Philips Semiconductors UM10120 Bb Volume 1 Chapter 14 TIMERO and TIMER 14 5 9 Capture Registers CRO CR3 Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges 14 5 10 Capture Control Register CCR TIMERO TOCCR 0xE000 4028 and TIMER1 T1CCR 0xE000 8028 The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the s
158. NSET and I2CONCLR 117 11 8 15 Initialization llle 139 11 6 9 Status decoder and Status register 118 11 8106 l Cinterruptservice 139 11 7 Register description 055 118 11 8 17 The State service routines 139 1174 I C Control Set register IICONSET I2CO 11 8 48 Adapting State services to an application 139 I2COCONSET 0xE001 C000 and I2C1 11 9 Software example 139 I2C1CONSET OxE005 C000 119 11 9 1 Initialization routine 139 11 7 2 12C Control Clear register BCONCLR I2C0 11 9 2 Start Master Transmit function 139 I2COCONCLR 0xE001 C018 and 12C1 11 9 3 Start Master Receive function 140 I2C1CONCLR OxE005 C018 120 11 9 4 I2C interrupt routine lilius 140 11 7 3 12C Status register I2STAT I2C0 I2COSTAT 11 9 5 Non mode specific States 140 OxE001 C004 and 12C1 I2C1STAT 11 9 6 State 0x00 140 OxE005 C004 20 2 eee eee 121 11 9 7 Master States 000000 140 11 7 4 12C Data register IBDAT I2C0 I2CODAT 11 9 8 State 0x08 nuanua nananana 140 0xE001 C008 and 12C1 11 9 9 State 0x10 nnana naana 141 I2C1DAT OxE005 CO008 121 11 9 10 Master Transmitter States 141 11 7 5 12C Slave Address register IBADR 12C0 11 9 11 State 0x18 0005 141 I2COADR OxE001 COOC a
159. ONSET and I2C1CONSET used to configure Slave mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 1 I2EN must be set to 1 to enable the 12C function AA bit must be set to 1 to acknowledge its own slave address or the general call address The STA STO and SI bits are set to 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 112 Philips Semiconductors UM1 01 20 fj Volume 1 Chapter 11 I C interfaces After IBADR and I2CONSET are initialized the I C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status register I2STAT Refer to Table 122 for the status codes and actions 0 Write 1 Read Data Transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START Condition P STOP Condition RS Repeated START condition L From Master to Slave O From Slave to Master Fig 24 Format of Slave Receiver mode 11 5 4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will be 1 indicating
160. OP condition in master mode or recover from an error condition in slave mode When STO is 1 in master mode a STOP condition is transmitted on the I2C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically Sl is the 12C Interrupt Flag This bit is set when the 12C state changes However entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case While SI is set the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is high it is unaffected by the state of the SI flag SI must be reset by software by writing a 1 to the SIC bit in I2CONCLR register AA is the Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The address in the Slave Address Register has been received 2 The general call address has been received while the general call bit GC in IZADR is set 3 A data byte has been received while the 12C is in the master receiver mode 4 A data byte has been received while the 12C is in the addre
161. PIPESTAT1 Pipeline Status bit 1 Standard I O port with internal pull up Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 70 Philips Semiconductors UM10120 ja Volume 1 Table 56 Pin description continued Chapter 6 Pin Configuration Symbol Pin Type Description P1 23 36 5 y o P1 23 General purpose digital input output pin PIPESTAT2 O PIPESTAT2 Pipeline Status bit 2 Standard I O port with internal pull up P1 24 3216 y o P1 24 General purpose digital input output pin TRACECLK O TRACECLK Trace Clock Standard I O port with internal pull up P1 25 EXTINO 2816 y o P1 25 General purpose digital input output pin l EXTINO External Trigger Input Standard I O with internal pull up P1 26 RTCK 2416 y o P1 26 General purpose digital input output pin y o RTCK Returned Test Clock output Extra signal added to the JTAG port Assists debugger synchronization when processor frequency varies Bi directional pin with internal pull up Note LOW on this pin while RESET is LOW enables pins P1 31 26 to operate as Debug port after reset P1 27 TDO 6416 y o P1 27 General purpose digital input output pin O TDO Test Data out for JTAG interface P1 28 TDI 6016 y o P1 28 General purpose digital input output pin TDI Test
162. PWMMR3 and the PWMTC clears PWM3 in either single edge mode or double edge mode and sets PWM4 if it is in double edge mode PWMMR4 PWM Match Register 4 PWMMR4 can be enabled through PNMMCR to R W 0 OxE001 4040 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMR4 and the PWMTC clears PWMA in either single edge mode or double edge mode and sets PWMB if it is in double edge mode PWMMR5 PWM Match Register 5 PWMMR5 can be enabled through PNMMCR to R W 0 OxE001 4044 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMRS5 and the PWMTC clears PWM5 in either single edge mode or double edge mode and sets PWM6 if it is in double edge mode Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 186 Philips Semiconductors UM10120 ja Volume 1 Table 155 Pulse Width Modulator PWM register map Chapter 15 PWM Name Description Access Reset Address valuelt PWMMR6 PWM Match Register 6 PWMMR6 can be enabled through PWMMCR to R W 0 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMRS6 and the PWMTC clears PWM6 in either single edge mode or double edge mode OxE001 4048 PWMPCR PWM Control Register En
163. R W bit to I2DAT Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Master Transmit mode data buffer Set up Master Receive mode data buffer Initialize Master data counter Exit N oc fF cnm Master Transmitter States State 0x18 Previous state was State 8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received Load I2DAT with first data byte from Master Transmit buffer Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Master Transmit buffer pointer Exit ar O N State 0x20 Slave Address Write has been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit State 0x28 Data has been transmitted ACK has been received If the transmitted data was the last data byte then transmit a Stop condition otherwise transmit the next data byte 1 Decrement the Master data counter skip to step 5 if not the last data byte 2 Write 0x14 to I2CONSET to set the STO and AA bits Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 141 Philips Semiconductors UM1 01 20 iz Volume 1 Chapter 11 I C interfaces Write 0
164. R_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command Erase sector s Table 213 IAP Erase sector s command Command Input Erase Sector s Command code 5219 Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in kHz Return Code CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR Result None Description This command is used to erase a sector or multiple sectors of on chip Flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 233 Philips Semiconductors UM10120 I3 Volume 1 Chapter 20 Flash Memory 20 9 4 Blank check sector s 20 9 5 20 9 6 Table 214 IAP Blank check sector s command Command Input Blank check sector s Comm
165. SR address Table 153 Set and reset inputs for PWM Flip Flops 184 OxE002 0004 bit description 153 Table 154 Pin summary 00 0 eee eee eee 185 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 259 Philips Semiconductors UM10120 ja Volume 1 Table 155 Pulse Width Modulator PWM register map 186 Chapter 24 Supplementary information Table 184 Prescaler cases where the Integer Counter reload Table 156 PWM Interrupt Register PWMIR address value is incremented 210 OxE001 4000 bit description 187 Table 185 Recommended values for the RTC external Table 157 PWM Timer Control Register PWMTCR 32 kHz oscillator Cx1 x2 components 211 address 0xE001 4004 bit description 188 Table 186 Watchdog register map 213 Table 158 Match Control Register MCR TIMERO TOMCR Table 187 Watchdog operating modes selection 213 address 0xE000 4014 and TIMER1 T1MCR Table 188 Watchdog Mode register WDMOD address address 0xE000 8014 bit description 189 OxE000 0000 bit description 214 Table 159 PWM Control Register PWMPCR address Table 189 Watchdog Timer Constatnt register WDTC OxE001 404C bit description 190 address 0xE000 0004 bit description 214 Table 160 PWM Latch Enable Register PWMLER address Table 190 Watchdog Feed reg
166. T be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1 0 to P1 31 y o Port 1 Port 1 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 1 pins depends upon the pin function selected via the pin connect block Pins 0 through 15 of port 1 are not available P1 16 1616 y o P1 16 General purpose digital input output pin TRACEPKTO O TRACEPKTO Trace Packet bit 0 Standard I O port with internal pull up P1 17 1216 y o P1 17 General purpose digital input output pin TRACEPKT1 o TRACEPKT1 Trace Packet bit 1 Standard I O port with internal pull up P1 18 gl6l y o P1 18 General purpose digital input output pin TRACEPKT2 O TRACEPKT2 Trace Packet bit 2 Standard I O port with internal pull up P1 19 416 y o P1 19 General purpose digital input output pin TRACEPKTS O TRACEPKT3 Trace Packet bit 3 Standard I O port with internal pull up P1 20 48 6 y o P1 20 General purpose digital input output pin TRACESYNC O TRACESYNC Trace Synchronization Standard I O port with internal pull up Note LOW on this pin while RESET is LOW enables pins P1 25 16 to operate as Trace port after reset P1 21 446 y o P1 21 General purpose digital input output pin PIPESTATO O PIPESTATO Pipeline Status bit 0 Standard l O port with internal pull up P1 22 4016 y o P1 22 General purpose digital input output pin PIPESTAT1 o
167. TDMI S Debug Architecture uses the existing JTAG port as a method of accessing the core The scan chains that are around the core for production test are reused in the debug state to capture information from the databus and to insert new information into the core or the memory There are two JTAG style scan chains within the ARMT7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two real time watchpoint registers together with a control and status register One or both of the watchpoint registers can be programmed to halt the ARM7TDMI S core Execution is halted when a match occurs between the values programmed into the EmbeddedICE logic and the values currently appearing on the address bus databus and some control signals Any bit can be masked so that its value does not affect the comparison Either watchpoint register can be configured as a watchpoint i e on a data access or a break point i e on an instruction fetch The watchpoints and breakpoints can be combined such that The conditions on both watchpoints must be satisfied before the ARM7TDMI core is stopped The CHAIN functionality requires two consecutive conditions to be satisfied before the
168. TER TIMER CONTROL REGISTER PRESOALEREGISTER PWM CONTROL REGISTER Note this diagram is intended to clarify the function of the PWM rather than to suggest a specific design implementation Fig 49 PWM block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 183 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 15 PWM A sample of how PWM values relate to waveform outputs is shown in Figure 50 PWM output logic is shown in Figure 49 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits The match register selections for various PWM outputs is shown in Table 153 This implementation supports up to N 1 single edge PWM outputs or N 1 2 double edge PWM outputs where N is the number of match registers that are implemented PWM types can be mixed if desired The waveforms below show a single PWM cycle and demonstrate PWM outputs under the following conditions The timer is configured for PWM mode The match register values are as follows Match 0 is configured to reset the timer counter MRO 100 PWM rate when a match event occurs MR1 41 MR2 78 PWM2 output Control bits PWMSEL2 and PWMSELA are set MR3 53 MR4 27 PWM4 output MR5 65 PWM5 output EE cur PWM4 ws 111341 7 L LL Gg Jg 0 27 41 538 65 78 100 counter is reset Fig 5
169. THRE 1 event This delay is provided to give the CPU time to write data to U1THR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently the U1THR is empty The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt U1IIR 3 1 001 The modem interrupt U1IIR 3 1 000 is available in LPC2134 6 8 only It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins DCD DSR or CTS In addition a low to high transition on modem input RI will generate a modem interrupt The source of the modem interrupt can be determined by examining U1MSR 3 0 A UTMSR read will clear the modem interrupt UART1 FIFO Control Register U1FCR OxEO01 0008 The U1FCR controls the operation of the UART1 RX and TX FIFOs Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 102 Philips Semiconductors UM10120 B Volume 1 Chapter 10 UART1 Table 97 UART1 FIFO Control Register UTFCR address 0xE001 0008 bit description Bit Symbol Value Description Reset value 0 FIFO Enable 0 UART1 FIFOs are disabled Must not be used in the application 0 1 Active high enable for both UART1 Rx and TX FIFOs and U1FCR 7 1 access This bit must be set for proper UART1 operation A
170. TIME2 address Table 213 IAP Erase sector s command 233 OxE002 401C bit description 205 Table 214 IAP Blank check sector s command 234 Table 178 Time counter relationships and values 206 Table 215 IAP Read Part Identification command 234 Table 179 Time counter registers 206 Table 216 IAP Read Boot code version number Table 180 Alarm registers 200020000 207 comrarnd gie dure be or RORIS Sus 234 Table 181 Reference clock divider registers 208 Table 217 IAP Compare command 235 Table 182 Prescaler Integer register PREINT address Table 218 Reinvoke ISP 2 00 0 eee ee 235 OxE002 4080 bit description 208 Table 219 IAP Status codes Summary 235 Table 183 Prescaler Integer register PREFRAC address Table 220 EmbeddedICE pin description 238 OxE002 4084 bit description 208 Table 221 EmbeddedICE logic registers 239 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 260 Philips Semiconductors UM10120 I3 Volume 1 Table 222 ETM configuration 00 240 Table 223 ETM pin description 241 Table 224 ETM registers l lees lees 242 Table 225 RealMonitor stack requirement 247 Table 226 Abbreviations lisse eee eee 255 Chapte
171. TO contains mechanism that enables software flow control implementation 9 2 Pin description Table 72 UARTO pin description Pin Type Description RXDO Input Serial Input Serial receive data TXDO Output Serial Output Serial transmit data 9 3 Register description UARTO contains registers organized as shown in Table 73 The Divisor Latch Access Bit DLAB is contained in UOLCR 7 and enables access to the Divisor Latches Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 84 soog eunf pc LO Ady jenuew sasn ss peniesei SUBH IV S002 A N 910 93 sdiliug exfipiuiuoy Table 73 UARTO register map Name Description Bit functions and addresses Access Reset Address MSB LSB valuel BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO UORBR Receiver Buffer 8 bit Read Data RO NA 0xE000 C000 Register DLAB 0 UOTHR Transmit Holding 8 bit Write Data WO NA OxE000 C000 Register DLAB 0 UODLL Divisor Latch LSB 8 bit Data R W 0x01 0xE000 C000 DLAB 1 UODLM Divisor Latch MSB 8 bit Data R W 0x00 OxE000 C004 DLAB 1 UOIER Interrupt Enable Reserved Reserved Reserved Reserved Reserved Enable Enable Enable R W 0x00 OxE000 C004 Register RX Line THRE RX Data DLAB 0 Status Interrupt Available Interrupt Interrupt UOIIR Interrupt ID FIFOs Enabled Reserved Reserved IIR3 IIR2 IIR1 IIRO RO 0x01 0xE000 C008 Register UOFCR FIFO
172. TPOLAR address OxEO1F C14C bit description Bit Symbol Value Description Reset value 0 EXTPOLARO 0 EINTO is low active or falling edge sensitive depending on 0 EXTMODEO 1 EINTO is high active or rising edge sensitive depending on EXTMODEO 1 EXTPOLAR1 0 EINT1 is low active or falling edge sensitive depending on 0 EXTMODE 1 1 EINT1 is high active or rising edge sensitive depending on EXTMODE 1 2 EXTPOLAR2 0 EINT2 is low active or falling edge sensitive depending on 0 EXTMODE2 1 EINT2 is high active or rising edge sensitive depending on EXTMODE2 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 23 Philips Semiconductors UM1 01 20 I3 Volume 1 3 5 6 Chapter 3 System Control Block Table 11 External Interrupt Polarity register EXTPOLAR address OxEO1F C14C bit description Bit Symbol Value Description Reset value 3 EXTPOLAR3 0 EINTS is low active or falling edge sensitive depending on 0 EXTMODE3 1 EINT3 is high active or rising edge sensitive depending on EXTMODE3 TA Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Multiple external interrupt pins Software can select multiple pins for each of EINT3 0 in the Pin Select registers which are described in chapter Pin Connect Block on page 73 The external interrupt logic for each of
173. TRY Define exception table Instruct linker to place code at address 0x0000 0000 z os EM ret et EP es e AREA exception table CODE LDR pc Reset Address LDR pc Undefined Address LDR pc SWI Address LDR pc Prefetch Address LDR pc Abort Address NOP Insert User code valid signature here Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 249 Philips Semiconductors UM10120 ia Volume 1 Chapier 23 RealMonitor LDR pc pc O0xFF0 Load IRQ vector from VIC LDR PC FIQ_Address Reset_Address DCD __init Reset Entry point Undefined_Address DCD rm_undef_handler Provided by RealMonitor SWI_Address DCD 0 User can put address of SWI handler here Prefetch_Address DCD rm_prefetchabort_handler Provided by RealMonitor Abort_Address DCD rm_dataabort_handler Provided by RealMonitor FIQ_Address DCD 0 User can put address of FIQ handler here AREA init_code CODE ram_end EQU 0x4000xxxx Top of on chip RAM init ERR RRRR AREER RR ER RRR RRR RRR RR ER RRR RRR RRR fff f fff fg RRR KER f f 2 f f f 2 fff RR KKK Set up the stack pointers for various processor modes Stack grows downwards RRR RR ERR RRR RR RRR RRR RRR RRR RR ER RRR 2 2 2 2 RR ERR fff 2 fff 2 4 ER RRR ERR REE LDR r2 ram_end Get top of RAM MRS r0 CPSR Save current processor mode Initialize the Undef mode stack for RealMonitor use BIC ri r
174. UM10120 Volume 1 LPC213x User Manual wee Rev 01 24 June 2005 User manual P IB BUS r Document information Info Content Keywords LPC2131 LPC2132 LPC2134 LPC2136 LPC2138 LPC2000 LPC213x ARM ARM7 embedded 32 bit microcontroller Abstract An initial LPC213x User Manual revision PHILIPS Philips Semiconductors UM1 01 20 a volume 1 LPC2131 2 4 6 8 UM Revision history Rev Date Description 01 20050624 Initial version Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 2 Semiconductors UM10120 Chapter 1 General information Rev 01 24 June 2005 User manual Ml 1 1 Introduction 1 2 Features The LPC2131 32 34 36 38 microcontrollers are based on a 16 32 bit ARM7TDMI S CPU with real time emulation and embedded trace support that combines the microcontroller with 32 kB 64 kB 128 kB 256 kB and 512 kB of embedded high speed Flash memory A 128 bit wide memory interface and a unique accelerator architecture enable 32 bit code execution at maximum clock rate For critical code size applications the alternative 16 bit Thumb Mode reduces code by more than 30 with minimal
175. W OxE002 400C counters will generate an interrupt when they are incremented AMR 8 Alarm Mask Register Controls which of the R W OxE002 4010 alarm registers are masked CTIMEO 32 Consolidated Time Register 0 RO OxE002 4014 CTIME1 32 Consolidated Time Register 1 RO OxE002 4018 CTIME2 32 Consolidated Time Register 2 RO OxE002 401C Interrupt Location Register ILR OxE002 4000 The Interrupt Location Register is a 2 bit register that specifies which blocks are generating an interrupt see Table 170 Writing a one to the appropriate bit clears the corresponding interrupt Writing a zero has no effect This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 202 Philips Semiconductors UM1 01 20 ia Volume 1 18 4 4 18 4 5 18 4 6 Chapter 18 RTC Table 170 Interrupt Location Register ILR address 0xE002 4000 bit description Bit Symbol Description Reset value 0 RTCCIF When one the Counter Increment Interrupt block generated an interrupt NA Writing a one to this bit location clears the counter increment interrupt 1 RTCALF When one the alarm registers generated an interrupt Writing a one to NA this bit location clears the alarm interrupt 7 22 Reserved user software should not write ones to rese
176. a device is a slave serial data is input on this signal 12 4 Register description The SPI contains 5 registers as shown in Table 127 All registers are byte half word and word accessible Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 151 Philips Semiconductors UM10120 Volume 1 Chapter 12 SPI Table 127 SPI register map Name Description Access Reset Address valuel SOSPCR SPI Control Register This register controls the R W 0x00 OxE002 0000 operation of the SPI SOSPSR SPI Status Register This register shows the RO 0x00 OxE002 0004 status of the SPI SOSPDR SPI Data Register This bi directional register R W 0x00 OxE002 0008 provides the transmit and receive data for the SPI Transmit data is provided to the SPIO by writing to this register Data received by the SPIO can be read from this register SOSPCCR SPI Clock Counter Register This register R W 0x00 OxE002 000C controls the frequency of a masters SCKO SOSPINT SPI Interrupt Flag This register contains the R W 0x00 OxE002 001C interrupt flag for the SPI interface 1 Reset value relects the data stored in used bits only It does not include reserved bits content 12 4 4 SPI Control Register SOSPCR 0xE002 0000 The SOSPCR register controls the operation of the SPIO as per the configuration bits setting Table 128 SPI Control Register SOSPCR address 0x
177. a fractional portion The result is not a continuous output at a constant frequency some clock periods will be one PCLK longer than others However the overall result can always be 32 768 counts per second Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 207 Philips Semiconductors UM1 01 20 I3 Volume 1 18 6 1 18 6 2 18 6 3 Chapter 18 RTC The reference clock divider consists of a 13 bit integer counter and a 15 bit fractional counter The reasons for these counter sizes are as follows 1 For frequencies that are expected to be supported by the LPC2131 2 4 6 8 a 13 bit integer counter is required This can be calculated as 160 MHz divided by 32 768 minus 1 4881 with a remainder of 26 624 Thirteen bits are needed to hold the value 4881 but actually supports frequencies up to 268 4 MHz 32 768 x 8192 2 The remainder value could be as large as 32 767 which requires 15 bits Table 181 Reference clock divider registers Name Size Description Access Address PREINT 13 Prescale Value integer portion R W OxE002 4080 PREFRAC 15 Prescale Value fractional portion R W OxE002 4084 Prescaler Integer register PREINT 0xE002 4080 This is the integer portion of the prescale value calculated as PREINT int PCLK 32768 1 The value of PREINT must be greater than or equal to 1 Table 182 Prescaler Integer register PREINT address 0xE002
178. ables PWM outputs and selects PWM channel R W 0 types as either single edge or double edge controlled OxE001 404C PWMLER PWM Latch Enable Register Enables use of new PWM match values R W 0 0xE001 4050 1 Reset value relects the data stored in used bits only It does not include reserved bits content 15 4 4 PWM Interrupt Register PWMIR 0xE001 4000 The PWM Interrupt Register consists of eleven bits Table 156 seven for the match interrupts and four reserved for the future use If an interrupt is generated then the corresponding bit in the PWMIR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 156 PWM Interrupt Register PWMIR address 0xE001 4000 bit description Bit Symbol Description Reset value 0 PWMMRO Interrupt Interrupt flag for PWM match channel 0 0 1 PWMMA1 Interrupt Interrupt flag for PWM match channel 1 0 2 PWMMR2 Interrupt Interrupt flag for PWM match channel 2 0 PWMMR3 Interrupt Interrupt flag for PWM match channel 3 0 7 4 s Reserved user software should not write ones to reserved bits 0000 The value read from a reserved bit is not defined 8 PWMMRA Interrupt Interrupt flag for PWM match channel 4 0 9 PWMMR5 Interrupt Interrupt flag for PWM match channel 5 0 10 PWMMR amp 6 Interrupt Interrupt flag for PWM match channel 6 0 15 11 Reserved user software should
179. ach port pin IOCLR GPIO Port Output clear register This WO 0x0000 0000 OxE002 800C OxE002 801C register controls the state of output pins IOOCLR 101CLR Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register Writing zeroes has no effect 1 Reset value relects the data stored in used bits only It does not include reserved bits content 8 4 4 GPIO Pin Value register 0 and 1 IOOPIN OxE002 8000 and IO1PIN 0xE002 8010 This register provides the value of the GPIO pins Register s value reflects any outside world influence on the GPIO configured pins only Monitoring of non GPIO configured port pins using IOPIN register will not be valid since activities on non GPIO configured pins are not indicated in the IOPIN register Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin The only partial exception from the above rule of exclusion is in the case of inputs to the A D converter Regardless of the function that is selected for the port pin that also hosts the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings However valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case proper interface circuit is active in between the physical pin and the A D module In all other cases a
180. actual baudrate desired baudrate 1 Actual baudrate based on Equation 2 UART1 Interrupt Enable Register U1IER 0xE001 0004 when DLAB 0 The U1IER is used to enable the four UART1 interrupt sources Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 99 Philips Semiconductors UM1 01 20 Volume 1 10 3 6 Chapter 10 UART1 Table 94 UART1 Interrupt Enable Register U1IER address 0xE001 0004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR U1IER 0 enables the Receive Data Available 0 Interrupt interrupt for UART1 It also controls the Character Enable Receive Time out interrupt 0 Disable the RDA interrupts Enable the RDA interrupts 1 THRE U1IER 1 enables the THRE interrupt for UART1 0 Interrupt The status of this interrupt can be read from Enable U1LSR 5 0 Disable the THRE interrupts Enable the THRE interrupts 2 RX Line U1IER 2 enables the UART1 RX line status 0 Interrupt interrupts The status of this interrupt can be read Enable from U1LSR 4 1 0 Disable the RX line status interrupts Enable the RX line status interrupts 3 Modem U1IER 3 enables the modem interrupt The status 0 Status of this interrupt can be read from U1MSR S 0 Interrupt 0 Disable the modem interrupt Enable 7 Enable the modem interrupt 74 Reserved user software should not write ones to
181. ake up the processor if it is in Power down mode The related EINTn function must be mapped to the pin in order for the wakeup process to take place It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place This arrangement allows additional capabilities such as having an external interrupt input wake up the processor from Power down mode without causing an interrupt simply resuming operation or allowing an interrupt to be enabled during Power down without waking the processor up if it is asserted eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application For an external interrupt pin to be a source that would wake up the microcontroller from Power down mode it is also necessary to clear the corresponding bit in the External Interrupt Flag register Section 3 5 2 on page 20 Table9 Interrupt Wakeup register INTWAKE address OxEO1F C144 bit description Bit Symbol Description Reset value 0 EXTWAKEO When one assertion of EINTO will wake up the processor from 0 Power down mode 1 EXTWAKE1 When one assertion of EINT1 will wake up the processor from 0 Power down mode 2 EXTWAKE2 When one assertion of EINT2 will wake up the processor from 0 Power down mode 3 EXTWAKE3 When one assertion of EINT3 will wake up the processor from 0 Power down mode 13 4 Reserved user software should not write ones to reser
182. alMonitor is pre programmed in the on chip ROM memory boot sector When enabled It allows user to observe and debug while parts of application continue to run Refer to Section 23 4 How to enable Realmonitor on page 247 for details RealMonitor components As shown in Figure 60 RealMonitor is split in to two functional components DEBUGGER Host RDI 1 5 1 REALMONITOR DLL RMHOST RDI 1 5 1 RT RealMonit JTAG Unit Ld protocol DCC transmissions over the JTAG link Taraet TARGET BOARD RMTARGET arget AND PROCESSOR APBMEATION Fig 60 RealMonitor components RMHost This is located between a debugger and a JTAG unit The RMHost controller RealMonitor dll converts generic Remote Debug Interface RDI requests from the debugger into DCC only RDI messages for the JTAG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User Guide ARM DUI 01374 RMTarget This is pre programmed in the on chip ROM memory boot sector and runs on the target hardware It uses the EmbeddedICE logic and communicates with the host using the DCC For more details on RMTarget functionality see the RealMonitor Target Integration Guide ARM DUI 01424 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 245 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 23 RealMonitor 23 3 4 How RealMonitor wor
183. ame time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 150 Capture Control Register CCR TIMERO TOCCR address 0xE000 4028 and TIMER1 T1CCR address 0xE000 8028 bit description Bit Symbol Value Description Reset value 0 CAPORE 1 Capture on CAPn 0 rising edge a sequence of 0 then 1 on CAPn 0 will cause CROto 0 be loaded with the contents of TC This feature is disabled O 1 CAPOFE Capture on CAPn 0 falling edge a sequence of 1 then 0 on CAPn 0 will cause CRO to 0 be loaded with the contents of TC This feature is disabled 2 CAPOI eo Interrupt on CAPn 0 event a CRO load due to a CAPn 0 event will generate an interrupt This feature is disabled Oo o 3 CAP1RE Capture on CAPn 1 rising edge a sequence of 0 then 1 on CAPn 1 will cause CR1 to 0 be loaded with the contents of TC This feature is disabled o 4 CAP1FE Capture on CAPn 1 falling edge a sequence of 1 then 0 on CAPn 1 will cause CR1 to 0 be loaded with the contents of TC This feature is disabled 5 CAP1I Interrupt on CAPn 1 event a CR1 load due to a CAPn 1 event will generate an interrupt O This feature is disabled O o 6 CAP2RE Capture on CAPn 2 rising edge A sequence of 0 then 1 on CAPn 2 will cause CR2to 0 be loaded with the contents of TC This feature is disab
184. ameters Fc Cj Rg and Cp are supplied by the crystal manufacturer Choosing an oscillation mode as an on board oscillator mode of operation limits Fosc clock selection to 1 MHz to 30 MHz LPC2131 2 4 6 8 LPC2131 2 4 6 8 Fig 7 Oscillator modes and models a slave mode of operation b oscillation mode of operation c external crystal model used for Cx1 x2 evaluation Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 18 Philips Semiconductors UM10120 E Volume 1 Chapter 3 System Control Block Table 6 Recommended values for Cx1 x2 in oscillation mode crystal and external components parameters Fundamental Crystal load Maximum crystal External load oscillation frequency capacitance C series resistance Rg capacitors Cy1 cx2 Fc 1 MHz 5 MHz 10 pF NA NA 20 pF NA NA 30 pF 3000 58 pF 58 pF 5 MHz 10 MHz 10 pF lt 300 O 18 pF 18 pF 20 pF lt 300 Q 38 pF 38 pF 30 pF lt 300 Q 58 pF 58 pF 10 MHz 15 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF 2200 38 pF 38 pF 30 pF 1400 58 pF 58 pF 15 MHz 20 MHz 10 pF 2200 18 pF 18 pF 20 pF 1400 38 pF 38 pF 30 pF 800 58 pF 58 pF 20 MHz 25 MHz 10 pF lt 160 0 18 pF 18 pF 20 pF 900 38 pF 38 pF 30 pF 500 58 pF 58 pF 25 MHz 30 MHz 10 pF 1300 18 pF 18 pF 20 pF 500 38 pF 38 pF 30 pF NA NA fosc Selec
185. an application uses interrupts interrupt vectors must be re mapped to on chip address 0x0 This is necessary because all the exception vectors are located at addresses 0x0 and above This is easily achieved by configuring the MEMMAP register see Section 3 6 1 Memory Mapping control register MEMMAP OxEO1F C040 on page 25 to User RAM mode Application code should be linked such that at 0x4000 0000 the Interrupt Vector Table IVT will reside Although multiple sources can be selected VICIntSelect to generate FIQ request only one interrupt service routine should be dedicated to service all available present FIQ request s Therefore if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 61 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 5 VIC do and how to process the interrupt request However it is recommended that only one interrupt source should be classified as FIQ Classifying more than one interrupt sources as FIQ will increase the interrupt latency Following the completion of the desired interrupt service routine clearing of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers VICRawIntr VICFIQStatus and VICIRQStatus Also before the next interrupt can
186. and code 5346 Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY SECTOR NOT BLANK INVALID SECTOR Result ResultO0 Offset of the first non blank word location if the Status Code is SECTOR NOT BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank check a single sector use the same Start and End sector numbers Read Part Identification number Table 215 IAP Read Part Identification command Command Input Read part identification number Command code 5446 Parameters None Return Code CMD SUCCESS Result ResultO0 Part Identification Number see Table 206 LPC213x Part Identification numbers on page 228 for details Description This command is used to read the part identification number Read Boot code version number Table 216 IAP Read Boot code version number command Command Input Read boot code version number Command code 5546 Parameters None Return Code CMD SUCCESS Result Result0 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number Koninklijke Philips Electronics N V 2005 All r
187. and control register changes to take effect PLL and Power down mode Power down mode automatically turns off and disconnects the PLL Wakeup from Power down mode does not automatically restore the PLL settings this must be done in software Typically a routine to activate the PLL wait for lock and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wakeup It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power down mode This would enable and connect the PLL at the same time before PLL lock is established PLL frequency calculation The PLL equations use the following parameters Table 19 Elemens determining PLL s frequency Element Description Fosc the frequency from the crystal oscillator external osicillator Feco the frequency of the PLL current controlled oscillator CCLK the PLL output frequency also the processor clock frequency M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register The PLL output frequency when the PLL is both active and connected is given by CCLK M x Fosc or CCLK Foco 2 x P The CCO frequency can be computed as Foco CCLK x 2 x P or Feco Fosc x Mx 2 x P The PLL inputs and settings must meet the following e Fogc is in the range of 10 MHz to 25 MHz e CCLK is i
188. and or I C were the reason content of VICVectAddr will be identical to VICDefVectAddr Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 63 UM10120 Chapter 6 Pin configuration Rev 01 24 June 2005 User manual Semiconductors 6 1 LPC2131 2132 2134 2136 2138 pinout P0 21 PWMB5 CAP1 3 P0 22 CAPO 0 MATO O XTAL2 Vpp 64 P1 27 TDO 63 VREF 62 XTAL1 61 60 P1 28 TDI 59 Vssa 58 P0 23 57 RESET 56 P1 29 TCK 55 P0 20 MAT1 3 SSEL1 EINTS 54 P0 19 MAT1 2 MOSI1 CAP1 2 53 P0 18 CAP1 3 MISO1 MAT1 3 52 P1 30 TMS 51 50 Vss 49 VBAT P1 20 TRACESYNC P0 17 CAP1 2 SCK1 MAT1 2 RTXC1 P0 16 EINTO MATO 2 CAPO 2 P1 19 TRACEPKT3 P0 15 EINT2 RTXC2 P1 21 PIPESTATO Vss VDD VDDA Vss P1 18 TRACEPKT2 P0 14 EINT1 SDA1 P0 25 AD0 4 EP ADT P1 22 PIPESTAT1 P0 26 AD0 5 P0 13 MAT1 1 P0 27 ADO 0 CAPO 1 MATO 1 P0 12 MAT1 0 P1 17 TRACEPKT1 P0 28 AD0 1 CAP0 2 MAT0 2 P0 29 AD0 2 CAP0 3 MATO 3 P0 30 AD0 3 EINT3 CAP0 0 P1 16 TRACEPKTO P0 11 CAP1 1 SCL1 P1 23 PIPESTAT2 P0 10 CAP1 0 P0 9 RXD1 PWM6 EINT3 P0 8 TXD1 PWM4 N fof la loll e foo io jo r j o o o o T 7 77 N QNI QI TO L PY QI CO CO C 002aab068 s9s5069852rc222380 X Sree 2a eb gt 26 po amp 20 a Fu lt tr D x x x iu w a ul z S zog orwWwW FOgQ Soo lt N gt TS TUS x ares P SESESIE amp
189. annel data and control registers are mapped in to addresses in the EmbeddedICE logic 21 4 Pin description Table 220 EmbeddedICE pin description Pin Name Type Description TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine TCK Input Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edgetriggered clock with the TMS and TCK signals that define the internal state of the device TDI Input Test Data In This is the serial data input for the shift register TDO Output Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge of the TCK signal nTRST Input Test Reset The nTRST pin can be used to reset the test logic within the EmbeddedlCE logic RTCK Output Returned Test Clock Extra signal added to the JTAG port Required for designs based on ARM7TDMI S processor core Multi ICE Development system from ARM uses this signal to maintain synchronization with targets having slow or widely varying clock frequency For details refer to Multi ICE System Design considerations Application Note 72 ARM DAI 0072A 21 5 Reset state of multiplexed pins On the LPC2131 2 4 6 8 the pins above are multiplexed with P1 31 26 To have them come up as a Debug port connect a weak bias resistor 4 7 10 kQ depending on the external JTAG circuitry between Vss and the P1 26 RTCK pin
190. apter 20 Flash Memory ISP command sbort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command Interrupts during ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts RAM used by ISP command handler ISP commands use on chip RAM from 0x4000 0120 to 0x4000 01FF The user could use this area but the contents may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 The maximum stack usage is 256 bytes and it grows downwards RAM used by IAP command handler Flash programming commands use the top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards RAM used by RealMonitor The RealMonitor uses on chip RAM from 0x4000 0040 to 0x4000 011F he user cou
191. are not supported Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell Vectored Interrupt Controller PL190 documentation 5 3 Register description The VIC implements the registers shown in Table 33 More detailed descriptions follow Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 48 Philips Semiconductors UM10120 ja Volume 1 Chapter 5 VIC Table 33 VIC register map Name Description Access Reset Address value VICIRQStatus IRQ Status Register This register reads out the state of RO 0 OxFFFF F000 those interrupt requests that are enabled and classified as IRQ VICFIQStatus FIQ Status Requests This register reads out the state of RO 0 OxFFFF F004 those interrupt requests that are enabled and classified as FIQ VICRawilntr Raw Interrupt Status Register This register reads out the RO 0 OxFFFF F008 state of the 32 interrupt requests software interrupts regardless of enabling or classification VICIntSelect Interrupt Select Register This register classifies each of the R W 0 OxFFFF FO0C 32 interrupt requests as contributing to FIQ or IRQ VICIntEnable Interrupt Enable Register This register controls which of the R W 0 OxFFFF F010 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ VICIntEnCIr Interrupt Enable Clear Register This register allows WO 0 OxFFFF
192. ash available for user code and data is 500 K bytes in 512K devices On the other hand in case of the LPC2131 2 4 6 microcontroller all 32 64 128 256 K of Flash are available for user s application Table 192 Flash sectors in LPC2131 LPC2132 LPC2134 LPC2136 and LPC2138 Sector Sector Address Range T N q o co Number Size kB za kg O0 EG La zB R SR EA RS 0 4 0X0000 0000 0X0000 OFFF b d de amp amp 1 4 0X0000 1000 0X0000 1FFF B Ge amp 2 4 0X0000 2000 0X0000 2FFF Sox X amp amp 3 4 0X0000 3000 0X0000 3FFF s 3 4 4 0X0000 4000 0X0000 4FFF F g 5 4 0X0000 5000 0X0000 5FFF ue amp 6 4 0X0000 6000 0X0000 6FFF E d amp F 34 7 4 0X0000 7000 0X0000 7FFF t E 4 amp 8 32 0x0000 8000 0X0000 FFFF 9 32 0x0001 0000 0X0001 7FFF s F 5 10 0x0A 32 0x0001 8000 0X0001 FFFF ECCE 11 0x0B 32 0x0002 0000 0X0002 7FFF 12 0x0C 32 0x0002 8000 0X0002 FFFF An 13 0x0D 32 0x0003 0000 0X0003 7FFF 3 14 0X0E 32 0x0003 8000 0X0003 FFFF E 4 15 0x0F 32 0x0004 0000 0X0004 7FFF 16 0x10 32 0x0004 8000 0X0004 FFFF 17 0x11 32 0x0005 0000 0X0005 7FFF 18 0x12 32 0x0005 8000 0X0005 FFFF 19 0x13 32 0x0006 0000 0X0006 7FFF 20 0x14 32 0x0006 8000 0X0006 FFFF 21 0x15 32 0x0007 0000 0X0007 7FFF 22 0x16 4 0x0007 8000 0X0007 8FFF 23
193. at is asserted and enabled in the SSPIMSC When an SSP interrupt occurs the interrupt service routine should read this register to determine the cause s of the interrupt Table 142 SSP Masked Interrupt Status register SSPMIS address 0xE006 801C bit description Bit Symbol Description Reset value 0 RORMIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full and this interrupt is enabled 1 RTMIS This bit is 1 when there is a Receive Timeout condition and 0 this interrupt is enabled Note that a Receive Timeout can be negated if further data is received 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt 0 is enabled 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty and this 0 interrupt is enabled 7 5 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined SSP Interrupt Clear Register SSPICR 0xE006 8020 Software can write one or more one s to this write only register to clear the corresponding interrupt condition s in the SSP controller Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO or disabled by clearing the corresponding bit in SSPIMSC Table 143 SSP interrupt Clear Register SSPICR address 0xE006 8020 bit description Bit Symbol Description Reset value 0 RORIC Writing a 1 to this bit clears the f
194. ata input to SSP slave l CAP1 2 Capture input for Timer 1 channel 2 P0 20 MAT1 3 5512 yo P0 20 General purpose digital input output pin SSELT EINTS O MAT1 3 Match output for Timer 1 channel 3 l SSEL1 Slave Select for SSP Selects the SSP interface as a slave l EINT3 External interrupt 3 input PO 21 PWM5 1 yo P0 21 General purpose digital input output pin AD1 6 CAP1 3 O PWM5 Pulse Width Modulator output 5 l AD1 6 A D converter 1 input 6 This analog input is always connected to its pin Available in LPC2134 6 8 only l CAP1 3 Capture input for Timer 1 channel 3 PO 22 AD1 7 2 yo P0 22 General purpose digital input output pin CAPO 0 MATO 0 l AD1 7 A D converter 1 input 7 This analog input is always connected to its pin Available in LPC2134 6 8 only l CAPO 0 Capture input for Timer 0 channel 0 O MATO 0 Match output for Timer 0 channel 0 P0 23 58l yo P0 23 General purpose digital input output pin PO 25 ADO 4 95B yo P0 25 General purpose digital input output pin Aout ADO0 4 A D converter 0 input 4 This analog input is always connected to its pin O Aout D A converter output Available in LPC2132 4 6 8 only P0 26 AD0 5 10 4 y o P0 26 General purpose digital input output pin ADO 5 A D converter 0 input 5 This analog input is always connected to its pin Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev
195. ation code A a LOW level after reset at the P0 14 pin is considered as an external hardware equest to start the ISP command handler Assuming that proper signal is present on X1 pin when the rising edge on RESET pin is generated it may take up to 3 ms before P0 14 is sampled and the decision on whether to continue with user code or ISP handler is made If P0 14 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution P0 14 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Pin P0 14 that is used as hardware request for ISP requires special attention Since P0 14 is in high impedance mode after reset it is important that the user provides external hardware a pull up resistor or other device to put the pin in a defined state Otherwise unintended entry into ISP mode may occur 20 4 4 Memory map after any reset The boot block is 12 kB in size and resides in the top portion starting from 0x0007 D000 of the on chip flash memory After any reset the entire boot block is also mapped to the top of the on chip memory space i e the boot block is also visible in the memory region starting from the address Ox7FFF D000 The flash boot loader is desig
196. attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal START condition is transmitted state 0x08 is entered and the serial transfer continues If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed pulled LOW the 12C hardware performs the same action as described above In each case state 0x08 is entered after a successful START condition is transmitted and normal serial transfer continues Note that the CPU is not involved in solving these bus hang up problems Bus error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame Examples of illegal positions are during the serial transfer of an address byte a data bit or an acknowledge bit The I C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave When a bus error is detected the 12C block immediately switches to the not addressed slave mode releases the SDA and SCL lines sets the interrupt flag and loads the status register with 0x00 This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 124 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 137
197. be serviced it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed This write will clear the respective interrupt flag in the internal interrupt priority hardware In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnCIr register which in turn clears the related bit in the VICIntEnable register This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the respective bits in VICSoftIlnt For example if VICSoftInt 0x0000 0005 and bit 0 has to be cleared VICSoftIntClear 0x0000 0001 will accomplish this Before the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future VICSoftIntClear 0x0000 0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt The only way you could perform return from interrupt is by disabling the interrupt at the VIC using VICIntEnCIr Example Assuming that UARTO and SPIO are generating interrupt requests that are classified as vectored IRQs UARTO being on the higher level than SPIO while UART1 and I C are generating non vectored IRQs the following could be one possibility for VIC setup VICIntSelect 0x0000 00
198. bit in the SPSR will be set The routine would therefore assume that it could not have been entered via an IRQ Problem 2 FIQs and IRQs are both disabled by the same write to the CPSR In this case if an IRQ is received during the CPSR write FIQs will be disabled for the execution time of the IRQ handler This may not be acceptable in a system where FIQs must not be disabled for more than a few cycles Workaround There are 3 suggested workarounds Which of these is most applicable will depend upon the requirements of the particular system Solution 1 test for an IRQ received during a write to disable IRQs Add code similar to the following at the start of the interrupt routine SUB lr lr 4 Adjust LR to point to return STMFD Spli uu lt Get some free regs MRS lr SPSR See if we got an interrupt while TST lr 4I Bit interrupts were disabled LDMNEFD sp pc If so just return immediately The interrupt will remain pending since we haven t acknowledged it and will be reissued when interrupts Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 60 Philips Semiconductors UM1 01 20 ja Volume 1 5 6 4 5 6 5 Chapter 5 VIC are next enabled Rest of interrupt routine This code will test for the situation where the IRQ was received during a write to disable IRQs If this is the case the code returns immediately resulting in the IRQ not
199. bit is 0 Brown Out Detection remains operative 0 during Power down mode such that its Reset can release the microcontroller from Power down model When PD and this bit are both 1 the BOD circuit is disabled during Power down mode to conserve power When PD is 0 the state of this bit has no effect 7 3 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 1 Since execution is delayed until after the Wakeup Timer has allowed the main oscillator to resume stable operation there is no guarantee that execution will resume before Vpp has fallen below the lower BOD threshhold which prevents execution If execution does resume there is no guarantee of how long the microcontroller will continue execution before the lower BOD threshhold terminates execution These issues depend on the slope of the decline of Vpp High decoupling capacitance between Vpp and ground in the vicinity of the microcontroller will improve the likelinood that software will be able to do what needs to be done when power is being lost Power Control for Peripherals register PCONP 0xE01F COC4 The PCONP register allows turning off selected peripheral functions for the purpose of saving power This is accomplished by gating off the clock source to the specified peripheral blocks A few peripheral functions cannot be turned off i e the Watchdog timer GPIO the Pin Connect block and the System Con
200. ble 140 SSP Interrupt Mask Set Clear register SSPIMSC I2COADR address 0xE001 COOC and l2C1 address 0xE006 8014 bit description 168 I2C1ADR address 0xE005 CO000C bit Table 141 SSP Raw Interrupt Status register SSPRIS description we seme e dn 122 address 0xE006 8018 bit description 168 Table 113 12C SCL High Duty Cycle register I2SCLH I2CO Table 142 SSP Masked Interrupt Status register SSPMIS I2COSCLH address 0xE001 C010 and l2C1 address OxEO006 801C bit description 169 I2C1SCLH address 0xE005 C010 bit Table 143 SSP interrupt Clear Register SSPICR address description iso gx psg DER REY RELY 122 OxE006 8020 bit description 169 Table 114 12C SCL Low Duty Cycle register I2SCLL I2CO Table 144 Timer Counter pin description 171 I2COSCLL address 0xE001 C014 and l2C1 Table 145 TIMER COUNTERO and TIMER COUNTER1 I2C1SCLL address 0xE005 C014 bit register Map 1 eee eee 172 description ses cerr cee ee eee 122 Table 146 Interrupt Register IR TIMERO TOIR address Table 115 Example I C clock rates issue 123 OxE000 4000 and TIMER1 T1lIR address Table 116 Abbreviations used to describe an I C OxE000 8000 bit description 173 Operation leui eem RE REA med ariete 123 Table 147 Timer Control Register TCR TIMERO TOTCR Table 117 12CONSET used to initialize Master Transmitter address 0xE000 4004 and TIMER1 T1TCR MOJE s durante pees foot ae
201. ble bits that control whether each external interrupt will cause the processor to wake up from Power down mode See Table 9 EXTMODE The External Interrupt Mode Register controls R W 0 OxEO1F C148 whether each pin is edge or levelsensitive EXTPOLAR The External Interrupt Polarity Register controls R W 0 OxEO1F C14C which level or edge on each pin will cause an interrupt 1 Reset value relects the data stored in used bits only It does not include reserved bits content External Interrupt Flag register EXTINT OXEO1F C140 When a pin is selected for its external interrupt function the level or edge on that pin selected by its bits in the EXTPOLAR and EXTMODE registers will set its interrupt flag in this register This asserts the corresponding interrupt request to the VIC which will cause an interrupt if interrupts from the pin are enabled Writing ones to bits EINTO through EINTS in EXTINT register clears the corresponding bits In level sensitive mode this action is efficacious only when the pin is in its inactive state Once a bit from EINTO to EINT3 is set and an appropriate code starts to execute handling wakeup and or external interrupt this bit in EXTINT register must be cleared Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future Important whenever a change of external interrupt operating mode i e active level edge is performed including the init
202. c Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 188 Philips Semiconductors UM10120 B Volume 1 Chapter 15 PWM 15 4 6 PWM Match Registers PWMMRO PWMMR6 The 32 bit PWM Match register values are continuously compared to the PWM Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the PWM Timer Counter or stop the timer Actions are controlled by the settings in the PWMMCR register 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter The function of each of the bits is shown in Table 158 Table 158 Match Control Register MCR TIMERO TOMCR address 0xE000 4014 and TIMER1 T1MCR address OxEO000 8014 bit description Bit Symbol Value Description 0 PWMMROI 1 Interrupt on PWMMRO an interrupt is generated when PWMMRO matches the value in the PWMTC This interrupt is disabled Reset value 0 1 PWMMROR Reset on PWMMRO the PWMTC will be reset if PWMMRO matches it This feature is disabled o o 2 PWMMROS Stop on PWMMRO the PWMTC and PWMPC will be stopped and PWMTCR O will be set to 0 if PWMMRO matches the PWMTC This feature is disabled O 3 PWMMR11 Interrupt
203. ce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of Vpp ramp in the case of power on the type of crystal and its electrical characteristics if a quartz crystal is used as well as any other external circuitry e g capacitors and the characteristics of the oscillator itself under the existing ambient conditions Once a clock is detected the Wakeup Timer counts 4096 clocks then enables the on chip circuitry to initialize When the onboard modules initialization is complete the processor is released to execute instructions if the external Reset has been deasserted In the case where an external clock source is used in the system as opposed to a crystal connected to the oscillator pins the possibility that there could be little or no delay for oscillator start up must be considered The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 39 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 3 System Control Block Any of the various Resets can bring the microcontroller out of power down mode as can the external interrupts EINT3 0 plus the RTC interrupt if the RTC is operating from its own oscillator on the RTCX1 2 pins When one of these interrupts is enabled
204. ch Abort exception when a breakpoint is reached or a Data Abort exception when a watchpoint is hit These exceptions are handled by the RealMonitor exception handlers that inform the user by way of the debugger of the event This allows user application to continue running without stopping the processor RealMonitor considers user application to consist of two parts aforeground application running continuously typically in User System or SVC mode abackground application containing interrupt and exception handlers that are triggered by certain events in user system including IRQs or FIQs Data and Prefetch aborts caused by user foreground application This indicates an error in the application being debugged In both cases the host is notified and the user application is stopped Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 246 Philips Semiconductors UM1 01 20 ia Volume 1 Chapier 23 RealMonitor Undef exception caused by the undefined instructions in user foreground application This indicates an error in the application being debugged RealMonitor stops the user application until a Go packet is received from the host When one of these exceptions occur that is not handled by user application the following happens RealMonitor enters a loop polling the DCC If the DCC read buffer is full control is passed to rm ReceiveData RealMon
205. channel Single 10 bit D A converter provides variable analog output LPC2132 4 6 8 only Two 32 bit timers external event counters with four capture and four compare channels each PWM unit six outputs and watchdog Low power Real time clock with independent power and dedicated 32 kHz clock input Multiple serial interfaces including two UARTs 16C550 two Fast 12C 400 kbit s SPI and SSP with buffering and variable data length capabilities Vectored interrupt controller with configurable priorities and vector addresses Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 3 Philips Semiconductors UM1 01 20 ia Volume 1 1 3 Applications Chapter 1 Introductory information Up to 47 of 5 V tolerant general purpose I O pins in tiny LQFP64 package Up to nine edge or level sensitive external interrupt pins available 60 MHz maximum CPU clock available from programmable on chip Phase Locked Loop PLL with settling time of 100 us On chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz or with external oscillator from 1 MHz to 50 MHz Power saving modes include Idle and Power down Individual enable disable of peripheral functions as well as peripheral clock scaling down for additional power optimization Processor wake up from Power down mode via external interrupt or Real time Clock Single power supply chip with
206. ctAddr7 Vector address 7 register R W 0 OxFFFF F11C ViCVectAddr8 Vector address 8 register R W 0 OxFFFF F120 ViCVectAddr9 Vector address 9 register R W 0 OxFFFF F124 ViCVectAddr O Vector address 10 register R W 0 OxFFFF F128 VICVectAddr11 Vector address 11 register R W 0 OxFFFF F12C Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 49 UM10120 Philips Semiconductors ja Volume 1 Chapter 5 VIC Table 33 VIC register map Name Description Access Reset Address valuet ViCVectAddr12 Vector address 12 register R W 0 OxFFFF F130 VICVectAddr13 Vector address 13 register R W 0 OxFFFF F134 VICVectAddr14 Vector address 14 register R W 0 OxFFFF F138 VICVectAddr15 Vector address 15 register R W 0 OxFFFF F13C VICVectCntlO Vector control 0 register Vector Control Registers 0 15 each R W 0 OxFFFF F200 control one of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 the lowest VICVectOntl1 Vector control 1 register R W 0 OxFFFF F204 VICVectCntl2 Vector control 2 register R W 0 OxFFFF F208 VICVectOntl3 Vector control 3 register R W 0 OxFFFF F20C VICVectCntl4 Vector control 4 register R W 0 OxFFFF F210 VICVectCntl5 Vector control 5 register R W 0 OxFFFF F214 VICVectCntl6 Vector control 6 register R W 0 OxFFFF F218 VICVectCntl7 Vector control 7 register R W 0 OxFFFF F21C VICVectCntl8 Vector control
207. ctor O of the flash If the signatures match then the execution control is transferred to the user code by loading the program counter with 0x0000 0000 Hence the user flash reset vector should contain a jump instruction to the entry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a Ox3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the Host In response to this host should send the same string Synchronized lt CR gt lt LF gt The auto baud routine looks at Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 217 Philips Semiconductors UM1 01 20 ia Volume 1 20 4 3 20 4 4 20 4 5 20 4 6 20 4 7 Chapter 20 Flash Memory the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host Host should respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz the response from the host shoul
208. d Interrupt Controller VIG coss p e Rx eh RV EDS TRES YU 58 LPC2131 64 pin package 64 LPC2132 64 pin package 65 LPC2134 6 8 64 pin package 66 LPC2131 2 4 6 8 UARTO block diagram 94 LPC2131 2 4 6 8 UART1 block diagram 108 I C bus Configuration isses 110 Format in the Master Transmitter mode 111 Format of Master Receive mode 112 A Master Receiver switches to Master Transmitter after sending Repeated START 112 Format of Slave Receiver mode 113 Format of Slave Transmitter mode 113 2C serial interface block diagram 115 Arbitration procedure 116 Serial clock synchronization 117 Format and States in the Master Transmitter MOOG T 126 Format and States in the Master Receiver MOJE soucieux dee Rune Ec Red 127 Format and States in the Slave Receiver mode 128 Format and States in the Slave Transmitter MOE imc beu veo d iebe a wende 129 Simultaneous repeated START conditions from two MasterS 22 2 itso mis DA bere pas 138 Forced access to a busy I C bus 138 Recovering from a bus obstruction caused by a low level on SDA 20 000 cence eee eee 138 SPI data transfer format Fig 37 Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Fig 44 Fig 45 Fig 46 Fig 47 Fig 48 Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Fig 54
209. d as a reference for A D convertor Veat 49 l RTC Power Supply 3 3 V on this pin supplies the power to the RTC 1 Bidirectional pin Plain input 3 State Output 10 ns Slew rate Control TTL with Hysteresis 5 V Tolerant Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 71 Philips Semiconductors UM1 01 20 ia Volume 1 2 3 4 5 6 7 8 Chapter 6 Pin Configuration Bidirectional Input Glitch Filter pulses shorter than 4 ns are ignored 3 State Ouptut 10 ns Slew rate Control TTL with Hysteresis 12C Pad 400 kHz Specification Open Drain 5 V Tolerant Bidirectional Input Glitch Filter pulses shorter than 4 ns are ignored Analog I O digital receiver disable 3 State Output 10 ns Slew Rate Control TTL with Hysteresis 5 V Tolerant Bidirectional Analog l O digital receiver disable 3 State Output 10 ns Slew Rate Control TTL with Hysteresis DAC enable output Bidirectional pin Plain input 3 State Output 10 ns Slew rate Control TTL with Hysteresis Pull up 5 V Tolerant Input TTL with Hysteresis 5 V Tolerant pulses shorter than 20 ns are ignored Analog like pads having ESD structures only Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 72 Semiconductors 7 1 Features UM10120 Chapter 7 Pin Connect Block Rev 01 24 June 2005 User manual ij
210. d be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly the crystal frequency should be greater than or equal to 10 MHz The on chip PLL is not used by the boot code Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Section 20 8 ISP commands on page 222 Communication protocol All ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra CR and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format ISP command format Command Parameter 0 Parameter_1 Parameter_n lt CR gt lt LF gt Data Data only for Write commands ISP response format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response n CR LF Da
211. d only bit description iiec nne Soe Gude ed ee 100 UART1 interrupt handling 102 UART1 FIFO Control Register U1FCR address OxE001 0008 bit description 103 UART1 Line Control Register U1LCR address OxE001 000C bit description 103 UART1 Modem Control Register U1MCR address 0xE001 0010 LPC2134 6 8 only bit description llsileeeeeeseses 104 Table 100 UART1 Line Status Register U1LSR address OxE001 0014 read only bit description 104 Table 101 UART1 Modem Status Register U1MSR address 0xE001 0018 LPC2134 6 8 only bit description 0 eee eee ee 106 Table 102 UART1 Scratch pad register U1SCR address OxE001 0014 bit description 106 Table 103 UART1 Transmit Enable Register U1TER address 0xE001 0030 bit description 107 Table 104 12C Pin Description 0005 110 Table 105 I2COCONSET and Il2C1CONSET used to continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 258 Philips Semiconductors UM10120 ja Volume 1 Chapter 24 Supplementary information configure Master mode 111 Table 130 SPI Data Register SOSPDR address Table 106 I2COCONSET and I2C1CONSET used to OxE002 0008 bit description 154 configure Slave mode 112 Table 131 SPI Clock Counter Register SOSPCCR
212. ddrOffset EQU 0x34 LDR r0 VICBaseAddr LDR ri app_irqDispatch STR ri r0 VICDefVectAddrOffset BL rm_init_entry Initialize RealMonitor enable FIQ and IRQ in ARM Processor MRS rl CPSR get the CPSR BIC ri r1 0xC0 enable IRQs and FIQs MSR CPSR c rl update the CPSR ERR RRR AREER RR ERR RRR RRR RRR KERR RRR RRR f f fff 2 fff 2 fff 2 ff 2 2 4 f f 0 ff f Get the address of the User entry point RRR RR RRR RR RRR RRR RRR RRR RR RRR RRR RRR RRR RRR RR ERR RRR RRR RRR RR RR RR RRR REE RK LDR lr User_Entry MOV pc lr RRR RRRR RRR RRR RRR RR RRR R RRR RRR RR 212 02 ff 21 RRR RR RRR RRR RE 4 ZA AA AAA Non vectored irq handler app irgDispatch RRR RRR RR RR RE RR RRR RRR f fff f f RRR 2 24221 2 0 210 2 0f 2 RRR ER RRR RRR RRR RR ER RRR ERR EEK AREA app irqDispatch CODE VICVectAddrOffset EQU 0x30 app irqDispatch enable interrupt nesting STMFD sp r12 r14 MRS r12 spsr Save SPSR in to r12 MSR cpsr_c 0x1F Re enable IRQ go to system mode User should insert code here if non vectored Interrupt sharing is required Each non vectored shared irq handler must return to the interrupted instruction by using the following code 1 D D MSR cpsr c 0x52 Disable irg move to IRQ mode MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr STR r1 r0 VICVectAddrOffset Acknowledge Non Vectored irq has finished LDMFD sp r12 r14 r0 Restore regist
213. disables additional debugging and error checking code in RealMonitor RM OPT BUILDIDENTIFIER ZFALSE This option determines whether a build identifier is built into the capabilities table of RMTarget Capabilities table is stored in ROM RM OPT SDM INFO FALSE SDM gives additional information about application board and processor to debug tools RM OPT MEMORYMAP FALSE This option determines whether a memory map of the board is built into the target and made available through the capabilities table RM OPT USE INTERRUPTS TRUE This option specifies whether RMTarget is built for interrupt driven mode or polled mode RM FIFOSIZEZNA This option specifies the size in words of the data logging FIFO buffer CHAIN VECTORS FALSE Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 253 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 23 RealMonitor This option allows RMTarget to support vector chaining through WHAL ARM HW abstraction API Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 254 UM10120 Chapter 24 Supplementary information were Rev 01 24 June 2005 User manual Ml 24 1Abbreviations Table 226 Abbreviations Acronym Description ADC Analog to Digital Converter BOD Brown Out Detection CPU Central Processing Unit DAC Digital to Analog Converter Doc Debug Communications Channel FIFO
214. dog by writing OxAA followed by 0x55 to the WDFEED register Watchdog should be fed again before the watchdog counter underflows to prevent reset interrupt When the Watchdog counter underflows the program counter will start from 0x0000 0000 as in the case of external reset The Watchdog Time Out Flag WDTOF can be examined to determine if the watchdog has caused the reset condition The WDTOF flag must be cleared by software Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 212 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 19 WDT 19 4 Register description 19 4 1 The watchdog contains 4 registers as shown in Table 186 below Table 186 Watchdog register map Name Description Access Reset Address valuel WDMOD Watchdog Mode register This register contains R W 0 OxE000 0000 the basic mode and status of the Watchdog Timer WDTC Watchdog Timer Constant register This register R W OxFF OxE000 0004 determines the time out value WDFEED Watchdog Feed sequence register Writing OXAA WO NA OxE000 0008 followed by 0x55 to this register reloads the Watchdog timer to its preset value WDTV Watchdog Timer Value register This register reads RO OxFF 0xE000 000C out the current value of the Watchdog timer 1 Reset value relects the data stored in used bits only It does not include reserved bits content Watchdog Mode register WDMOD
215. dress should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD SUCCESS Source and destination data are equal COMPARE ERROR Followed by the offset of first mismatch COUNT ERROR Byte count is not a multiple of 4 ADDR ERROR ADDR NOT MAPPED PARAM ERROR Description This command is used to compare the memory contents at two locations Compare result may not be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes are re mapped to flash boot sector Example M 8192 1073741824 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the flash address 0x2000 ISP Return codes Table 209 ISP Return codes Summary Return Mnemonic Description Code 0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary 4 SRC ADDR NOT MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST ADDR NOT MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicab
216. ductors 23 1 Features UM10120 Chapter 23 RealMonitor Rev 01 24 June 2005 User manual E RealMonitor is a configurable software module which enables real time debug RealMonitor is developed by ARM Inc Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide ARM DUI 01424 It applies to a specific configuration of RealMonitor software programmed in the on chip ROM boot memory of this device Refer to the white paper Real Time Debug for System on Chip available at http www arm com support White Papers OpenDocument for background information Allows user to establish a debug session to a currently running system without halting or resetting the system Allows user time critical interrupt code to continue executing while other user application code is being debugged 23 2 Applications Real time debugging 23 3 Description RealMonitor is a lightweight debug monitor that allows interrupts to be serviced while user debug their foreground application It communicates with the host using the DCC Debug Communications Channel which is present in the EmbeddedICE logic RealMonitor provides advantages over the traditional methods for debugging applications in ARM Systems The traditional methods include Angel a target based debug monitor e Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Alt
217. e In this mode data is transmitted from master to slave Before the master transmitter mode can be entered the I2CONSET register must be initialized as shown in Table 105 I2EN must be set to 1 to enable the I C function If the AA bit is 0 the 12C interface will not Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 110 Philips Semiconductors UM1 01 20 zi Volume 1 11 5 2 Chapter 11 I C interfaces acknowledge any address when another device is master of the bus so it can not enter slave mode The STA STO and SI bits must be 0 The SI Bit is cleared by writing 1 to the SIC bit in the I2ZCONCLR register Table 105 I2COCONSET and I2C1CONSET used to configure Master mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The 12C interface will enter master transmitter mode when software sets the STA bit The 12C logic will send the START condition as soon as the bus is free After the START
218. e 7 0 Pad A readable writable byte 0x00 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 92 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 9 UARTO 9 3 11 UARTO Transmit Enable Register UOTER 0xE000 C030 LPC2131 2 4 6 8 s UOTER enables implementation of software flow control When TXEn 1 UARTO transmitter will keep sending data as long as they are available As soon as TXEn becomes 0 UARTO transmittion will stop Table 86 describes how to use TXEn bit in order to achieve software flow control Table 86 UARTO Transmit Enable Register UOTER address 0xE000 C030 bit description Bit Symbol Description Reset value 6 0 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written to the THR is output 1 on the TXD pin as soon as any preceding data has been sent If this bit is cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software implementing software handshaking can clear this bit when it receives an XOFF character DC3 Software can set this bit again when it receives an XON DC1 character
219. e 1 Chapter 12 SPI Table 132 SPI Interrupt register SOSPINT address 0xE002 001C bit description Bit Symbol Description Reset value 0 SPI Interrupt SPI interrupt flag Set by the SPI interface to generate an interrupt Cleared 0 Flag by writing a 1 to this bit Note this bit will be set once when SPIE 1 and at least one of SPIF and WCOL bits is 1 However only when the SPI Interrupt bit is set and SPIO Interrupt is enabled in the VIC SPI based interrupt can be processed by interrupt handling software 7 Reserved user software should not write ones to reserved bits The value NA read from a reserved bit is not defined 12 5 Architecture The block diagram of the SPI solution implemented in SPIO interface is shown in the Figure 37 MOSI IN MOSI OUT MISO IN MISO OUT SPI SHIFT REGISTER SPI CLOCK GENERATOR amp SPI Interrupt DETECTOR SPI REGISTER VPBBus INTERFACE SPI STATE CONTROL SCK OUT EN MOSI OUT EN OUTPUT MISO OUT EN ENABLE LOGIC Fig 37 SPI block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 155 UM10120 Chapter 13 SSP Controller SPI1 Rev 01 24 June 2005 User manual i Semiconductors 13 1 Features Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buses Synchronous Serial Communication Master or slave operation
220. e 51 Vector Address registers VICVectAddr0 15 addresses OxFFFF F100 13C bit description Bit Symbol Description Reset value 31 0 IRQ_vector When one or more interrupt request or software interrupt is are enabled 0x0000 0000 classified as IRQ asserted and assigned to an enabled vectored IRQ slot the value from this register for the highest priority such slot will be provided when the IRQ service routine reads the Vector Address register VICVectAddr Section 5 4 10 5 4 11 Default Vector Address register VICDefVectAddr OxFFFF F034 This is a read write accessible register This register holds the address of the Interrupt Service routine ISR for non vectored IRQs Table 52 Default Vector Address register VICDefVectAddr address OxFFFF F034 bit description Bit Symbol Description Reset value 31 0 IRQ_vector When an IRQ service routine reads the Vector Address register 0x0000 0000 VICVectAddr and no IRQ slot responds as described above this address is returned 5 4 12 Vector Address register VICVectAddr OXFFFF F030 This is a read write accessible register When an IRQ interrupt occurs the IRQ service routine can read this register and jump to the value read Table 53 Vector Address register VICVectAddr address OxFFFF F030 bit description Bit Symbol Description Reset value 31 0 IRQ_vector If any of the interrupt requests or software interrupts that are assigned to a 0x0000 0000 vectored IRQ slot is are enabled classified as
221. e SK after the LSB of the frame has been latched into the SSP Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 163 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 13 SSP SK WV n cs V V V U V sof pe me LLLI ps i i i I i 8 bit control fel LIS BOE 4 to 16 bits gt 4 to 16 bits gt output data output data Fig 44 Microwire frame format continuos transfers 13 3 9 Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW Masters that drive a free running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK Figure 45 illustrates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave CS must have a setup of at least two times the period of SK on which the SSP operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period _ seruP sk noLp sk Fig 45 Microwire frame format continuos transfers 13 4 Register description The SSP contains 9 registers as shown in Table 134 All registers are byte half word and word accessible Koninklijke Philips Electr
222. e TXEn bit in order to achieve software flow control Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 106 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 10 UART1 Table 103 UART1 Transmit Enable Register U1TER address 0xE001 0030 bit description Bit Symbol Description Reset value 6 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent If this bit cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software can clear this bit when it detects that the a hardware handshaking TX permit signal LPC2134 6 8 CTS otherwise any GPlO external interrupt line has gone false or with software handshaking when it receives an XOFF character DC3 Software can set this bit again when it detects that the TX permit signal has gone true or when it receives an XON DC1 character 10 4 Architecture The architecture of the UART1 is shown below in the block diagram The VPB interface provides a communications link between
223. e has been Readdatabyte X 0 0 1 Data byte will be received and ACK will received ACK has be returned been returned Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 132 Philips Semiconductors UM10120 ie Volume 1 Table 122 Slave Receiver mode Chapter 11 I C interfaces Status Status of the I2C bus Code and hardware I2CSTAT 0x98 Previously addressed with General Call DATA byte has been received NOT ACK has been returned Application software response To From I2DAT To I2CON STA STO SI Read data byte or 0 0 0 AA Next action taken by I C hardware Switched to not addressed SLV mode no recognition of own SLA or General call address Read data byte or 0 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O logic 1 Read data byteor 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Read data byte 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O0 logic 1 A START condition will be transmitted when the bus becomes free OxAO A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX No STDAT action 0 or Switched to not add
224. e of the SPI data transfer 5 Read the SPI status register 6 Read the received data from the SPI data register optional 7 Go to step 3 if more data is required to transmit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 149 Philips Semiconductors UM1 01 20 ia Volume 1 12 2 5 12 2 6 12 2 7 12 2 8 Chapter 12 SPI Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore if the optional read of the SPI data register does not take place a write to this register is required in order to clear the SPIF status bit Slave operation The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave This process assumes that any prior data transfer has already completed It is required that the system clock driving the SPI logic be at least 8X faster than the SPI 1 Set the SPI control register to the desired settings 2 Write the data to transmitted to the SPI data register optional Note that this can only be done when a slave SPI transfer is not in progress 3 Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last sampling clock edge of the SPI data transfer 4 Read the SPI status register 5 Read the received data from the SPI data register optional 6 Go to step 2 if more data is
225. e received ACK bit will be returned 0x58 Data byte has been Read data byte or 1 0 0 X Repeated START condition will be received NOT ACK transmitted has been returned Read data byte or 0 1 0 X STOP condition will be transmitted STO flag will be reset Read data byte 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 131 Philips Semiconductors UM10120 Volume 1 Table 122 Slave Receiver mode Chapter 11 I C interfaces Status Status of the I2C bus Application software response Next action taken by I C hardware pede Tm and hardware To From I2DAT To l2CON I2CSTAT STA STO SI AA 0x60 Own SLA W has No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK been received ACK will be returned has been returned Ng I2DAT action X 0 0 1 Databyte wil be received and ACK will be returned 0x68 Arbitration lost in No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK SLA R W as master will be returned Own SLA W has No I2DAT action X 0 0 1 Databyte wil be received and ACK will been received ACK be returned returned 0x70 General call address No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK 0x00 has been will be returned received ACK has Nig I2DAT action X 0 0 1 Databyte will
226. e used when a valid user program is present in the internal flash memory and the P0 14 pin is not accessible to force the ISP mode This command does not disable the PLL hence itis possible to invoke the bootloader when the part is running off the PLL In such case the ISP utility should pass the PLL frequency after autobaud handshake Another option is to disable the PLL before making this IAP call IAP Status codes Table 219 IAP Status codes Summary Status Mnemonic Description Code 0 CMD SUCCESS Command is executed successfully 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on a word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary 4 SRC ADDR NOT MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 235 Philips Semiconductors UM1 01 20 Volume 1 Chapter 20 Flash Memory Table 219 IAP Status codes Summary Status Mnemonic Description Code 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value INVALID_SECTOR Sector number is invalid SECTOR_NOT_BLANK Sector is not blank 9 SECTOR NOT PREPARED Command to prepare sector for
227. ection is dependent on UOFCR O Note A parity error is associated with the character at the top of the UARTO RBR FIFO 0 Parity error status is inactive 1 Parity error status is active Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 91 Philips Semiconductors UM1 01 20 ag volume 1 Chapter 9 UARTO Table 84 UARTO Line Status Register UOLSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value 3 Framing Error When the stop bit of a received character is a logic 0 a framing error occurs 0 FE An UOLSR read clears UOLSR 3 The time of the framing error detection is dependent on UOFCRO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UARTO RBR FIFO 0 Framing error status is inactive 1 Framing error status is active 4 Break Interrupt When RXDO is held in the spacing state all 0 s for one full character 0 Bl transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXDO goes to marking state all 1 s An UOLSR read clears this status bit
228. ection will be applied before data are provided to the CPU When a write request into the user s Flash is made write of user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of user s Flash memory is erased corresponding ECC bytes are also erased Once an ECC byte is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written into the Flash memory in groups of 4 bytes or multiples of 4 aligned as described above 20 7 Code Read Protection CRP Code read protection is enabled by programming the flash address location 0x1FC User flash sector 0 with value 0x8765 4321 2271560481 Decimal Address 0x1FC is used to allow some room for the fiq exception handler When the code read protection is enabled the JTAG debug port external memory boot and the following ISP commands are disabled Read Memory Write to RAM e Go Copy RAM to Flash The ISP commands mentioned above terminate with return code CODE READ PROTECTION ENABLED The ISP erase command only allows erasure of all user sectors when the code read protection is enabled This limitation does not exist if the code read protection is not enabled IAP commands are not affected by the code read protection Important CRP is active inactive once the device has gone through a power cycle 20 8 ISP commands The following comma
229. ed a complete high time The other device effectively determines the shorter high period 2 Another device continues to pull the SCL line low after thi has timed a complete low time and released SCL The PC clock generator is forced to wait until SCL goes high The other device effectively determines the longer low period 3 The SCL line is released and the clock generator begins timing the high time Fig 28 Serial clock synchronization A slave may stretch the space duration to slow down the bus master The space duration may also be stretched for handshaking purposes This can be done after each bit or after a complete byte transfer the 12C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred The serial interrupt flag SI is set and the stretching continues until the serial interrupt flag is cleared Serial clock generator This programmable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched off when the 12C block is in a slave mode The I C output clock frequency and duty cycle is programmable via the IC Clock Control Registers See the description of the IPCSCLL and I2CSCLH registers for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above Timing and control The
230. ed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case if number of results are more than number of parameters Parameter passing is illustrated in the Figure 57 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 2 returned by the Blankcheck sector s command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at OX7FFF FFFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP LOCATION Ox7ffffffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 2 or unsigned long command unsigned long result command unsigned long Ox result unsigned long Ox Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 Koninklijke Philips Electronics N V 2005 A
231. een bes dits 124 address 0xE000 8004 bit description 174 Table 118 I2COADR and I2C1ADR usage in Slave Receiver Table 148 Count Control Register CTCR TIMERO mode xot stus etu t uentum iE 125 TOCTCR address 0xE000 4070 and TIMER 1 Table 119 IZCOCONSET and Il2C1 CONSET used to initialize T1TCR address 0xE000 8070 bit Slave Receiver mode 0 125 description e serer enn 00 eee eee eee 174 Table 120 Master Transmitter mode 130 Table 149 Match Control Register MCR TIMERO TOMCR Table 121 Master Receiver mode 131 address 0xE000 4014 and TIMER1 T1MCR Table 122 Slave Receiver mode 0 132 address 0xE000 8014 bit description 176 Table 123 Slave Transmitter mode 134 Table 150 Capture Control Register CCR TIMERO TOCCR Table 124 Miscellaneous States lusus 136 address 0xE000 4028 and TIMER1 T1CCR Table 125 SPI data to clock phase relationship 148 address 0xE000 8028 bit description 177 Table 126 SPI pin description 0 151 Table 151 External Match Register EMR TIMERO TOEMR Table 127 SPl register map 00055 152 address 0xE000 403C and TIMER1 T1EMR Table 128 SPI Control Register SOSPCR address addressOxE000 803C bit description 178 OxE002 0000 bit description 152 Table 152 External match control 179 Table 129 SPI Status Register SOSP
232. egister DACR address 0xE006 C000 bit description Bit Symbol Value Description Reset value 5 0 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 15 6 VALUE After the selected settling time after this field is written witha 0 new VALUE the voltage on the Aout pin with respect to Vssa is VALUE 1024 Veer 16 BIAS 0 The settling time of the DAC is 1 us max and the maximum 0 current is 700 vA 1 The settling time of the DAC is 2 5 us and the maximum current is 350 pA 3147 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 198 Philips Semiconductors UM1 01 20 fal Volume 1 Chapter 17 A D Converter 17 4 Operation Bits 19 18 of the PINSEL1 register Section 7 4 2 Pin function Select register 1 PINSEL1 OXE002 C004 on page 75 control whether the DAC is enabled and controlling the state of pin P0 25 ADO 4 AOUT When these bits are 10 the DAC is powered on and active The settling times noted in the description of the BIAS bit are valid for a capacitance load on the Aour pin not exceeding 100 pF A load impedance value greather than that value will cause settling time longer than the specified time Koninklijke Philips Electronics N V 2005 Al
233. egister VPBDIV address 0xE01F C100 bit description Bit Symbol Value Description Reset value 1 0 VPBDIV 00 VPB bus clock is one fourth of the processor clock 00 01 VPB bus clock is the same as the processor clock 10 VPB bus clock is one half of the processor clock 11 Reserved If this value is written to the VPBDIV register it has no effect the previous setting is retained 7 2 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Crystal oscillator or Processor clock external clock source CCLK Fosco VPB VPB Clock DIVIDER PCLK Fig 12 VPB divider connections 3 11 Wakeup timer The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions This is important at power on all types of Reset and whenever any of the aforementioned functions are turned off for any reason Since the oscillator and other functions are turned off during Power down mode any wakeup of the processor from Power down mode makes use of the Wakeup Timer The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution When power is applied to the chip or some event caused the chip to exit Power down mode some time is required for the oscillator to produ
234. egister OxE001 4014 0 0 cece eee eee 189 PWMIR OxE001 4000 187 45 4 8 PWM Control Register PWMPCR 15 4 2 PWM Timer Control Register PWMTCR DxEO 1 404C oaaao nnana 190 OXEDO1 4004 odore eb 187 1549 PWM Latch Enable Register PWMLER OxE001 4050 02 191 Chapter 16 Analog to Digital Converter ADC 16 1 Features 2 22 a are memes 193 16 4 2 A D Data Register ADODR OxE003 4004 and 162 Description 00cce eee ees 193 AD1DR OxE006 0004 196 16 3 Pindescription 0eeeeeeees 193 1643 ai pud Register ADGSR 366 16 4 Register description 194 16 5 o A a E 197 16 4 1 A D Control Register ADOCR 0xE003 4000 and er s Tauei CDM MEE AD1CR OxEO06 0000 ssssssese 194 16 5 1 Hardware triggered conversion 197 16 5 2 Interrupts 0 2 cee ee eee 197 16 5 3 Accuracy vs digital receiver 197 Chapter 17 Digital to Analog Converter DAC 17 1 Feat res cle nce eta reme 198 17 3 DAC Register DACR 0xE006 C000 198 17 2 Pin description esseseee 198 17 4 Operation cue RI x xs 199 Chapter 18 Real Time Clock 18 1 Features oe e nmn 200 18 4 7 Alarm Mask Register AMR 0xE002 4010 204 18 2 Descriptloticincivisccsterien hehe 200 18 4 8 Consolidated time registers 204 18 3 Architecture cccceeeeeees 200 1849 ees nda register 0 CTIMEO na ae
235. egister and the internal shift register A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read of the SPI data register returns the value of the read data buffer The SPI clock counter register controls the clock rate when the SPI block is in master mode This needs to be set prior to a transfer taking place when the SPI block is a master This register has no function when the SPI block is a slave The I Os for this implementation of SPI are standard CMOS I Os The open drain SPI option is not implemented in this design When a device is set up to be a slave its I Os are only active when it is selected by the SSEL signal being active Master operation The following sequence describes how one should process a data transfer with the SPI block when it is set up to be the master This process assumes that any prior data transfer has already completed 1 Set the SPI clock counter register to the desired clock rate 2 Setthe SPI control register to the desired settings 3 Write the data to transmitted to the SPI data register This write starts the SPI data transfer 4 Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last cycl
236. elatively small less than 25 and may be minimized in ARM rather than Thumb code through the use of the conditional execution feature present in all ARM instructions This conditional execution may often be used to avoid small forward branches that would otherwise be necessary Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above The Branch Trail Buffer captures the line to which such a non sequential break occurs If the same branch is taken again the next instruction is taken from the Branch Trail Buffer When a branch outside the contents of Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 42 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 4 MAM Module the Prefetch and Branch Trail Buffer is taken a stall of several clocks is needed to load the Branch Trail buffer Subsequently there will typically be no further instructionfetch delays until a new and different branch occurs 4 3 MAM blocks 4 3 1 The Memory Accelerator Module is divided into several functional blocks A Flash Address Latch and an incrementor function to form prefetch addresses e A 128 bit Prefetch Buffer and an associated Address latch and comparator e A 128 bit Branch Trail Buffer and an associated Address latch and comparator A 128 bit Data Buffer and an associated Address latch and comparator Control logic
237. er AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space Each AHB peripheral is allocated a 16 kB address space within the AHB address space LPC2131 2 4 6 8 peripheral functions other than the interrupt controller are connected to the VPB bus The AHB to VPB bridge interfaces the VPB bus to the AHB bus VPB peripherals are also allocated a 2 megabyte range of addresses beginning at the 3 5 gigabyte address point Each VPB peripheral is allocated a 16 kB address space within the VPB address space The connection of on chip peripherals to device pins is controlled by a Pin Connect Block see chapter Pin Connect Block on page 73 This must be configured by software to fit specific application requirements for the use of peripheral functions and pins 1 6 ARM7TDMI S processor The ARM7TDMI S is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically w
238. er CTCR TIMERO 0xE000 4028 and TIMER1 T1CCR TOCTCR 0xE000 4070 and TIMER1 TTTCR 0xE000 8028 iced vRPRA PR Re RI 177 0xE000 8070 lle 174 145 11 External Match Register EMR TIMERO TOEMR 14 5 4 Timer Counter TC TIMERO TOTC OxE000 403C and TIMER1 T1EMR 0xE000 4008 and TIMER1 T1TC OxE000 8008 175 OxE000 803C lsseeeseseess 178 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 267 Philips Semiconductors UM10120 ja Volume 1 Chapter 24 Supplementary information 14 6 Example timer operation 179 14 7 Architecture 2 0 0 cece eee eee 180 Chapter 15 Pulse Width Modulator PWM 15 1 Features essse ne eae Rra RR Ua 181 15 4 3 PWM Timer Counter 15 2 Description 0ccee eese 181 PWMTC OxE001 4008 188 15 2 1 Rules for single edge controlled PWM 15 4 4 PWM Prescale Register PWMPR outpuls sssssssss ee 184 OxEO01 400C 0 eee eee eee 188 15 2 2 Rules for double edge controlled PWM 15 4 5 PWM Prescale Counter register PWMPC OUTPUNS sss echa siting Gd e s eram tae 185 denis Sena A E CLAU DU ger ee 188 A atch Registers 15 3 Pin description Pa TO pa UD 185 PWMMRO PWMMR6 189 15 4 Register description MU EPA em 185 154 7 PWM Match Control Register PWMMCR 19 4 1 PWM Interrupt R
239. erals can be dynamically assigned and adjusted Fast Interrupt reQuest FIQ requests have the highest priority If more than one request is assigned to FIQ the VIC ORs the requests to produce the FIQ signal to the ARM processor The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply start dealing with that device But if more than one request is assigned to the FIQ class the FIQ service routine can read a word from the VIC that identifies which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but only 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot 0 has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non vectored IRQs to produce the IRQ signal to the ARM processor The IRQ service routine can start by reading a register from the VIC and jumping there If any of the vectored IRQs are requesting the VIC provides the address of the highest priority requesting IRQs service routine otherwise it provides the address of a default routine that is shared by all the non vectored IRQs The default routine can read another VIC register to see what IRQs are active All registers in the VIC are word registers Byte and halfword reads and write
240. ermine the next value of a PWM output when a new cycle is about to begin 1 The match values for the next PWM cycle are used at the end of a PWM cycle a time point which is coincident with the beginning of the next PWM cycle except as noted in rule 3 A match value equal to 0 or the current PWM rate the same as the Match channel 0 value have the same effect except as noted in rule 3 For example a request for a falling edge at the beginning of the PWM cycle has the same effect as a request for a falling edge at the end of a PWM cycle When match values are changing if one of the old match values is equal to the PWM rate it is used again once if the neither of the new match values are equal to 0 or the PWM rate and there was no old match value equal to 0 If both a set and a clear of a PWM output are requested at the same time clear takes precedence This can occur when the set and clear match values are the same as in or when the set or clear value equals 0 and the other value equals the PWM rate If a match value is out of range i e greater than the PWM rate value no match event occurs and that match channel has no effect on the output This means that the PWM output will remain always in one state allowing always low always high or no change outputs 15 3 Pin description Table 154 gives a brief summary of each of PWM related pins Table 154 Pin summary Pin Type Descripti
241. error parity error 0 FIFO or break interrupt is loaded into the U1RBR This bit is cleared when the UTLSR RXFE register is read and there are no subsequent errors in the UART1 FIFO U1RBR contains no UART1 RX errors or U1 FCR 0 0 UART1 RBR contains at least one UART1 RX error Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 105 Philips Semiconductors UM1 01 20 B Volume 1 Chapter 10 UART1 10 3 11 UART1 Modem Status Register U1MSR 0xE001 0018 LPC2134 6 8 only The U1MSR is a read only register that provides status information on the modem input signals UTMSR 3 0 is cleared on U1MSR read Note that modem signals have no direct affect on UART1 operation they facilitate software implementation of modem signal operations Table 101 UART1 Modem Status Register U1MSR address 0xE001 0018 LPC2134 6 8 only bit description Bit Symbol Value Description Reset value O Delta CTS Set upon state change of input CTS Cleared on an U1MSR read 0 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 Delta DSR Set upon state change of input DSR Cleared on an U1MSR read 0 0 No change detected on modem input DSR 1 State change detected on modem input DSR 2 Trailing Edge RI Set upon low to high transition of input RI Cleared on an UTMSR read 0 0 No change detected on modem input RI 1 Low to high transitio
242. errupt UOIIR 3 1 110 The RDA is activated when the UARTO Rx FIFO reaches the trigger level defined in UOFCR 7 6 and is reset when the UARTO Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR 3 1 110 is a second level interrupt and is set when the UARTO Rx FIFO contains at least one character and no UARTO Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UARTO Rx FIFO activity read or write of UARTO RSR will clear the interrupt This interrupt is intended to flush the UARTO RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 81 UARTO interrupt handling UOIIR 3 0 Priority Interrupt Type Interrupt Source Interrupt Reset valuell 0001 None None 0110 Highest RX Line Status Error OEL or PEL or FEI or BIL UOLSR Readl2 0100 Second RX Data Available Rx data available or trigger level reached in FIFO UORBR Read or UOFCRO 1 UARTO FIFO drops below trigger level 1100 Second Character Time out Minimum of one character in the Rx FIFO and no
243. ers SUBS pc r14 4 Return to the interrupted instruction user interrupt did not happen so call rm irghandler2 This handler is not aware of the VIC interrupt priority hardware so trick Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 Philips Semiconductors UM1 01 20 ia Volume 1 Chapier 23 RealMonitor rm_irghandler2 to return here I H STMFD sp ip pc LDR pc rm irghandler2 rm irqhandler2 returns here MSR cpsr c 0x52 Disable irq move to IRQ mode MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr H STR r1 r0 VICVectAddrOffset Acknowledge Non Vectored irq has finished LDMFD sp r12 r14 r0 Restore registers SUBS pc r14 4 Return to the interrupted instruction END 23 5 RealMonitor build options RealMonitor was built with the following options RM_OPT_DATALOGGING FALSE This option enables or disables support for any target to host packets sent on a non RealMonitor third party channel RM_OPT_STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM_OPT_SOFTBREAKPOINT T RUE This option enables or disables support for software breakpoints RM_OPT_HARDBREAKPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_HARDWATCHPOINT TRUE Enabled for cores with EmbeddedICE RT This device u
244. es value in the range of 0 to 59 NA 15 14 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 20 16 Hours Hours value in the range of 0 to 23 NA 23 21 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 26 24 Day Of Week Day of week value in the range of 0 to 6 NA 31 27 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Consolidated Time register 1 CTIME1 0xE002 4018 The Consolidate Time register 1 contains the Day of Month Month and Year values Table 176 Consolidated Time register 1 CTIME1 address 0xE002 4018 bit description Bit Symbol Description Reset value 4 0 Day of Month Day of month value in the range of 1 to 28 29 30 or 31 NA depending on the month and whether it is a leap year 7 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 11 8 Month Month value in the range of 1 to 12 NA 15 12 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 27 16 Year Year value in the range of 0 to 4095 NA 31 28 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Consolidated Time register 2 CTIME
245. eserved Reserved Reserved Enable Enable Enable Enable R W 0x00 OxE001 0004 Register Modem RX Line THRE RX Data DLAB 0 Status Status Interrupt Available interrupt2 Interrupt Interrupt U1IIR Interrupt ID FIFOs Enabled Reserved Reserved IIR3 IIR2 IIR1 IRO RO 0x01 0xE001 0008 Register U1FCR FIFO Control RX Trigger Reserved Reserved Reserved TXFIFO RXFIFO FIFO WO 0x00 0xE001 0008 Register Reset Reset Enable U1LCR Line Control DLAB Set Stick Even Parity Number Word Length Select R W 0x00 OxE001 000C Register Break Parity Parity Enable of Stop Select Bits U1MCRI2 Modem Control Reserved Reserved Reserved Loop Reserved Reserved RTS DTR R W 0x00 OxE001 0010 Register Back U1LSR Line Status RX FIFO TEMT THRE BI FE PE OE DR RO 0x60 0xE001 0014 Register Error U1MSRE Modem Status DCD RI DSR CTS Delta Trailing Delta Delta RO 0x00 OxE001 0018 Register DCD Edge RI DSR CTS U1SCR Scratch Pad 8 bit Data R W 0x00 OxE001 001C Register U1TER Transmit Enable TXEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W 0x80 OxE001 0030 Register 1 Reset value relects the data stored in used bits only It does not include reserved bits content 2 Modem specific features are available in LPC2134 6 8 only euinjoA S10 onpuooiuieg Sdijiud LLHVh 0L Je1deu2 Oc LOLINN Philips Semiconductors UM1 01 20 ja Volume 1 10 3 1 10 3 2 10 3 3 Chapter 10 UART1 UART1 Receiver Buffer Register U1RBR 0xE001 0000
246. eset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 1 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 1 Latch Match 1 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 2 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 2 Latch Match 2 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 3 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 3 Latch Match 3 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 4 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 4 Latch Match 4 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 5 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 5 Latch Match 5 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 6 Enable PWM Writing a one to this bit allows the last value wri
247. ferred onto the MISO line of the master Master s MOSI pin is enabled One half period later valid master data is transferred to the MOSI line Now that both the master and slave data have been set the SCK master clock pin becomes LOW after one further half SCK period This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 161 Philips Semiconductors UM1 01 20 ia Volume 1 13 3 7 13 3 8 Chapter 13 SSP device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured SPI format with CPOL 1 CPHA 1 The transfer signal sequence for SPI format with CPOL 1 CPHA 1 is shown in
248. for wakeup and its selected event occurs an oscillator wakeup cycle is started The actual interrupt if any occurs after the wakeup timer expires and is handled by the Vectored Interrupt Controller However the pin multiplexing on the LPC2131 2 4 6 8 see chapters Pin Configuration on page 64 and Pin Connect Block on page 73 was designed to allow other peripherals to in effect bring the device out of Power down mode The following pin function pairings allow interrupts from events relating to UARTO or 1 SPI 0 or 1 or the IC RxDO EINTO SDA EINT1 SSELO EINT2 RxD1 EINT3 DCD1 EINT1 RI1 EINT2 SSEL1 EINT3 To put the device in Power down mode and allow activity on one or more of these buses or lines to power it back up software should reprogram the pin function to External Interrupt select the appropriate mode and polarity for the Interrupt and then select Power down mode Upon wakeup software should restore the pin multiplexing to the peripheral function All of the bus or line activity indications in the list above happen to be low active If software wants the device to come out of power down mode in response to activity on more than one pin that share the same EINTi channel it should program low level sensitivity for that channel because only in level mode will the channel logically OR the signals to wake the device The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2131
249. g environment block diagram 243 RealMonitor components 245 RealMonitor as a state machine 246 Exception handlers 0000 249 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 262 Philips Semiconductors UM10120 Volume 1 24 6 Contents Chapter 24 Supplementary information Chapter 1 General information 1 1 Introduction lessen 3 1 6 ARM7TDMI S processor sess 5 1 2 Features in cnc et eee hn nr 3 1 7 On chip Flash memory system 6 1 3 Applications 2 0 00 cece eee eee 4 1 8 On chip Static RAM SRAM 6 1 4 Device information Lseeese 4 1 9 Block diagram eseesees 7 1 5 Architectural overview sese 5 Chapter 2 LPC2131 2 4 6 8 Memory Addressing 2 1 Memory maps 20002e eee eens 8 2 2 1 Memory map concepts and operating modes 12 2 2 LPC2131 2132 2134 2136 2138 memory 2 2 2 Memory re mapplng senten nen 13 re mapping and boot block 12 2 3 Prefetch abort and data abort exceptions 15 Chapter 3 System Control Block 3 1 Summary of system control block functions 16 3 7 4 PLL Status register 3 2 Pin description 000ce0eeeeee 16 PLLSTAT OxEO1F C088 29 3 3 Register description 00 17 3 7 5 PLL Interrupt lores 30
250. generation and checking 0 1 Enable parity generation and checking l 5 4 Parity Select 00 Odd parity Number of 1s in the transmitted character andthe 0 attached parity bit will be odd 01 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 103 Philips Semiconductors UM1 01 20 a Volume 1 Chapter 10 UART1 Table 98 UART1 Line Control Register U1LCR address 0xE001 000C bit description Bit Symbol Value Description Reset value 6 Break Control 0 Disable break transmission 0 1 Enable break transmission Output pin UART1 TXD is forced to logic 0 when U1LCR 6 is active high 7 Divisor Latch 0 Disable access to Divisor Latches 0 Access Bit DLAB Enable access to Divisor Latches 10 3 9 UART1 Modem Control Register U1MCR 0xE001 0010 LPC2134 6 8 only The U1MCR enables the modem loopback mode and controls the modem output signals Table 99 UART1 Modem Control Register U1MCR address 0xE001 0010 LPC2134 6 8 only bit description Bit Symbol Value Description Reset value 0 DTR Control Source for modem output pin DTR This bit reads as 0 when 0 modem loopback mode is active 1 RTS Control Source for modem output pin RTS This bit reads as 0 when 0 modem loopback mode is active 3 2 Reser
251. gister that determines the PWM rate PWM Match 0 must be set up prior to the PWM being enabled Otherwise a Match event will not occur to cause shadow register contents to become effective 7 4 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined PWM Timer Counter PWMTC 0xE001 4008 The 32 bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the PWMTC will count up through the value OxFFFF FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed PWM Prescale Register PWMPR 0xE001 400C The 32 bit PWM Prescale Register specifies the maximum value for the PWM Prescale Counter PWM Prescale Counter register PWMPC 0xE001 4010 The 32 bit PWM Prescale Counter controls division of PCLK by some constant value before it is applied to the PWM Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The PWM Prescale Counter is incremented on every PCLK When it reaches the value stored in the PWM Prescale Register the PWM Timer Counter is incremented and the PWM Prescale Counter is reset on the next PCLK This causes the PWM TC to increment on every PCLK when PWMPR 0 every 2 PCLKs when PWMPR 1 et
252. gister values The PINSEL registers control the functions of device pins as shown below Pairs of bits in these registers correspond to specific device pins Table 61 Pin function select register bits PINSELO and PINSEL1 Values Function Value after Reset 00 Primary default function typically GPIO 00 port 01 First alternate function 10 Second alternate function 11 Reserved The direction control bit in the IOODIR IO1DIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Each derivative typically has a different pinout and therefore a different set of functions possible for each pin Details for a specific derivative may be found in the appropriate data sheet Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 78 UM10120 Chapter 8 General Purpose Input Output ports GPIO wee Rev 01 24 June 2005 User manual ET 8 1 Features Direction control of individual bits Separate control of output set and clear All I O default to inputs after reset 8 2 Applications e General purpose I O Driving LEDs or other indicators Controlling off chip devices Sensing digital inputs 8 3 Pin description Table 62 GPIO pin description Pin Type Description P0 0 P 31 Input General purpose input output The number of GPIOs actually available depends on
253. gisters 202 Table 201 ISP Copy command 226 Table 170 Interrupt Location Register ILR address Table 202 ISP Go command 0 00 227 OxE002 4000 bit description 203 Table 203 ISP Erase sector command 227 Table 171 Clock Tick Counter Register CTCR address Table 204 ISP Blank check sector command 228 OxE002 4004 bit description 203 Table 205 ISP Read Part Identification number Table 172 Clock Control Register CCR address comimnand i sss exu EE ERR 228 OxE002 4008 bit description 203 Table 206 LPC213x Part Identification numbers 228 Table 173 Counter Increment Interrupt Register CIIR Table 207 ISP Read Boot code version number address 0xE002 400C bit description 204 COMMANG usse ears 228 Table 174 Alarm Mask Register AMR address Table 208 ISP Compare command 229 OxE002 4010 bit description 204 Table 209 ISP Return codes Summary 229 Table 175 Consolidated Time register 0 CTIMEO address Table 210 IAP Command Summary 231 OxE002 4014 bit description 205 Table 211 IAP Prepare sector s for write operation Table 176 Consolidated Time register 1 CTIME1 address COMMANG sso uiime badaeenlariweee 232 OxE002 4018 bit description 205 Table 212 IAP Copy RAM to Flash command 233 Table 177 Consolidated Time register 2 C
254. gital function selected and yet get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 197 UM10120 Chapter 17 Digital to Analog Converter DAC NENNEN Rev 01 24 June 2005 User manual iT This peripheral is available in LPC2132 4 6 8 devices 17 1 Features 10 bit digital to analog converter Resistor string architecture Buffered output Power down mode Selectable speed vs power 17 2 Pin description Table 166 gives a brief summary of each of DAC related pins Table 166 DAC pin description Pin Type Description AOUT Output Analog Output After the selected settling time after the DACR is written with a new value the voltage on this pin with respect to Vasa is VALUE 1024 Veer VREF Reference Voltage Reference This pin provides a voltage reference level for the D A converter VppA Vssa Power Analog Power and Ground These should be nominally the same voltages as Va and Vsgp but should be isolated to minimize noise and error 17 3 DAC Register DACR 0xE006 C000 This read write register includes the digital value to be converted to analog and a bit that trades off performance vs power Bits 5 0 are reserved for future higher resolution D A converters Table 167 DAC R
255. guring via peripheral dedicated registers the user s application has no need to access the PCONP in order to start using any of the on board peripherals Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application All other bits declared to be Reserved or dedicated to the peripherals not used in the current application must be cleared to 0 Reset has two sources on the LPC2131 2 4 6 8 the RESET pin and Watchdog Reset The RESET pin is a Schmitt trigger input pin with an additional glitch filter Assertion of chip Reset by any source starts the Wakeup Timer see description in Section 3 11 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 35 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 3 System Control Block Wakeup timer in this chapter causing reset to remain asserted until the external Reset is de asserted the oscillator is running a fixed number of clocks have passed and the on chip circuitry has completed its initialization The relationship between Reset the oscillator and the Wakeup Timer are shown in Figure 11 The Reset glitch filter allows the processor to ignore external reset pulses that are very short and also determines the minimum duration of RESET that must be asserted in order to guarantee a chip reset Once asserted RESET pin can be deasserted o
256. h is enabled in modes 1 and 2 2 The MAM actually uses latched data if it is available but mimics the timing of a Flash read operation This saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock Table 29 MAM responses to data and DMA accesses of various types Data Memory Request Type MAM Mode 0 1 2 Sequential access data in latches Initiate Fetch Initiate Fetch Use Latched Data Sequential access data not in latches Initiate Fetch Initiate Fetch Initiate Fetch Non sequential access data in latches Initiate Fetchl Initiate Fetchl Use Latched Data Non sequential access data not in latches Initiate Fetch Initiate Fetch Initiate Fetch 1 The MAM actually uses latched data if it is available but mimics the timing of a Flash read operation This saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock 4 5 MAM configuration After reset the MAM defaults to the disabled state Software can turn memory access acceleration on or off at any time This allows most of an application to be run at the highest possible performance while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required 4 6 Register description All registers regardless of size are on word address boundaries
257. has been returned Additional data will be read 11 9 27 ON OOF WYP Read data byte from I2DAT into the Slave Receive buffer Decrement the Slave data counter skip to step 5 if not the last data byte Write OxOC to I2CONCLR to clear the SI flag and the AA bit Exit Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Slave Receive buffer pointer Exit State 0x88 Previously addressed with own Slave Address Data has been received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 2 3 Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Exit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 144 Philips Semiconductors UM1 01 20 m Volume 1 11 9 28 11 9 29 11 9 30 11 9 31 11 9 32 11 9 33 Chapter 11 I C interfaces State 0x90 Previously addressed with general call Data has been received ACK has been returned Received data will be saved Only the first data byte will be received with ACK Additional data will be received with NOT ACK 1 Read data byte from I2DAT into the Slave Receive buffer 2 Write OxOC to I2CONCLR to clear the SI flag and the AA bit 3 Exit State 0x98 Previously addressed with general call Data has been received NOT ACK has been returned Recei
258. he 12C interface Ox1F The three least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is OxF8 there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined I2C states When any of these states entered the SI bit will be set For a complete list of status codes refer to tables from Table 120 to Table 123 I C Data register I2DAT I2CO I2CODAT OxE001 C008 and 12C1 I2C1DAT OxE005 C008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register only while it is not in the process of shifting a byte when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 111 I C Data register I2DAT I2CO I2CODAT address 0xE001 C008 and I2C1 I2C1DAT address 0xE005 C008 bit description Bit Symbol Description Reset value 7 0 Data This register holds data values that have been received or are to 0 be transmitted Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 121 Philips Semiconductors UM1 01 20 m Volume 1
259. he RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UOLSR register and then to read a byte from the UORBR Table 74 UARTO Receiver Buffer Register UORBR address 0xE000 C000 when DLAB 0 Read Only bit description Bit Symbol Description Reset value 7 0 RBR The UARTO Receiver Buffer Register contains the oldest undefined received byte in the UARTO Rx FIFO UARTO Transmit Holding Register UOTHR 0xE000 C000 when DLAB 0 Write Only The UOTHR is the top byte of the UARTO TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UOTHR The UOTHR is always Write Only Table 75 UARTO Transmit Holding Register UOTHR address 0xE000 C000 when DLAB 0 Write Only bit description Bit Symbol Description Reset value 7 0 THR Writing to the UARTO Transmit Holding Register causes the data NA to be stored in the UARTO transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available UARTO Divisor Latch Registers 0 and 1 UODLL OxE000 C000 and UODLM 0xE000 C004 when DLAB 1 The UARTO Divisor Latch is part of the UARTO Baud Rate Generator and holds the value used to divide the VPB clock PCLKk in order to produce the baud ra
260. hen it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 210 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 5040 Table 211 Copy RAM to Flash 5110 Table 212 Erase sector s 5240 Table 213 Blank check sector s 5340 Table 214 Read Part ID 5440 Table 215 Read Boot code version 5510 Table 216 Compare 5610 Table 217 Reinvoke ISP 5748 Table 218 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 231 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 20 Flash Memory COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n Command parameter table ARM REGISTER r ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESULT n Command result table Fig 57 IAP Parameter passing 20 9 1 Prepare sector s for write operation This command makes flash write erase operation a two step process Table 211 IAP Prepare sector s for write opera
261. here are 26 possible bus states if all four modes of the 12C block are used The 5 bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set by hardware and remains stable until the interrupt flag is cleared by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 11 7 Register description Each I C interface contains 7 registers as shown in Table 107 below Table 107 I C register map Name Description Access Reset l CO Address 1 C1 Address value and Name and Name I2CONSET PC Control Set Register When a one is written to a bit R W 0x00 OxE001 C000 OxE005 C000 of this register the corresponding bit in the I C control I2COCONSET 12C1CONSET register is set Writing a zero has no effect on the corresponding bit in the 12C control register I2STAT I C Status Register During I C operation this register RO OxF8 OxE001 C004 OxE005 C004 provides detailed status codes that allow software to I2COSTAT I2C1STAT determine the next action needed I2DAT I C Data Register During master or slave transmit mode R W 0x00 OxE001 C008 OxE005 C008 data to be transmitted is written to this register During I2COD
262. hes Mode 1 MAM partially enabled Sequential instruction accesses are fulfilled from the holding latches if the data is present Instruction prefetch is enabled Non sequential instruction accesses initiate Flash read operations see note 2 below This means that all branches cause memory fetches All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent Mode 2 MAM fully enabled Any memory request code or data for a value that is contained in one of the corresponding holding latches is fulfilled from the latch Instruction prefetch is enabled Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 44 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 4 MAM Module Table 28 MAM Responses to program accesses of various types Program Memory Request Type MAM Mode 0 1 2 Sequential access data in latches Initiate Fetchl2l Use Latched Use Latched Datal Datal Sequential access data not in latches Initiate Fetch Initiate Fetch Initiate Fetchl Non sequential access data in latches Initiate Fetchl Initiate FetchUJ2 Use Latched Datal l Non sequential access data not in latches Initiate Fetch Initiate Fetchl 1 Initiate Fetch 1 Instruction prefetc
263. hese bits should be 1 In hardware scan mode any value containing 1 to 8 ones All zeroes is equivalent to 0x01 15 8 CLKDIV The VPB clock PCLK is divided by this value plus one to produce the clock for the 0 A D converter which should be less than or equal to 4 5 MHz Typically software should program the smallest value in this field that yields a clock of 4 5 MHz or slightly less but in certain cases such as a high impedance analog source a slower clock may be desirable 16 BURST 1 The AD converter does repeated conversions at the rate selected by the CLKS field 0 scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversons will not start 0 Conversions are software controlled and require 11 clocks Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 194 Philips Semiconductors UM10120 ja Volume 1 Chapter 16 A D Converter Table 163 A D Control Register ADOCR address 0xE003 4000 and AD1CR address 0xE006 0000 bit description Bit Symbol Value Description Reset value 19 17 CLKS This field selec
264. hile one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM7TDMI S processor also employs a unique architectural strategy known as THUMB which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue The key idea behind THUMB is that of a super reduced instruction set Essentially the ARM7TDMI S processor has two instruction sets The standard 32 bit ARM instruction set A 16 bit THUMB instruction set The THUMB set s 16 bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM s performance advantage over a traditional 16 bit processor using 16 bit registers This is possible because THUMB code operates on the same 32 bit register set as ARM code THUMB code is able to provide up to 65 of the code size of ARM and 160 of the performance of an equivalent ARM processor connected to a 16 bit memory system Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 5 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 1 Introductory information The ARM7TDMI S processor is described in detail in the ARM7TDMI S Datasheet that can be found on official ARM website 1 7 On chip Flash memory system The LPC2131 2 4 6 8 incorporates a 32 64 128 256 and 512 kB Flash memor
265. hile those written as O will remain unaffected However by just writing to either IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary data containing mixture of Os and 1s on a GPIO port Write to IOPIN register enables instantaneous output of a desired content on a parallel GPIO Binary data written into the IOPIN register will affect all output configured pins of that parallel port Os in the IOPIN will produce low level pin outputs and 1s in IOPIN will produce high level pin outputs In order to change output of only a group of port s pins application must logically AND readout from the IOPIN with mask containing Os in bits corresponding to pins that will be changed and 1s for all others Finally this result has to be logically ORred with the desired content and stored back into the IOPIN register Example 2 from above illustrates output of 0xXA5 on PORTO pins 15 to 8 while preserving all other PORTO output pins as they were before Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 83 UM10120 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UARTO Rev 01 24 June 2005 User manual D Semiconductors 9 1 Features 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator e PC2131 2 4 6 8 UAR
266. his bit is significant only when the START field contains 010 111 In these cases 0 Start conversion on a falling edge on the selected CAP MAT signa 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 195 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter 16 4 2 A D Data Register ADODR 0xE003 4004 and AD1DR 0xE006 0004 Table 164 A D Data Register ADODR address 0xE003 4004 and AD1DR address 0xE006 0004 bit description Bit Symbol Description Reset value 5 0 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 15 6 V VREF When DONE is 1 this field contains a binary fraction representing the voltage on NA the Ain pin selected by the SEL field divided by the voltage on the Vppa pin Zero in the field indicates that the voltage on the Ain pin was less than equal to or close to that on Vssa while 0x3FF indicates that the voltage on Ain was close to equal to or greater than that on Vngr 23 16 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 26 24 CHN These bits contain the channel from which
267. hough both of these methods provide robust debugging environments neither is suitable as a lightweight real time monitor Angel is designed to load and debug independent applications that can run in a variety of modes and communicate with the debug host using a variety of connections such as a serial port or ethernet Angel is required to save and restore full processor context and the occurrence of interrupts can be delayed as a result Angel as a fully functional target based debugger is therefore too heavyweight to perform as a real time monitor Multi ICE is a hardware debug solution that operates using the EmbeddedICE unit that is built into most ARM processors To perform debug tasks such as accessing memory or the processor registers Multi ICE must place the core into a debug state While the processor is in this state which can be millions of cycles normal program execution is suspended and interrupts cannot be serviced Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 244 Philips Semiconductors UM1 01 20 ia Volume 1 23 3 1 23 3 2 23 3 3 Chapter 23 RealMonitor RealMonitor combines features and mechanisms from both Angel and Multi ICE to provide the services and functions that are required In particular it contains both the Multi ICE communication mechanisms the DCC using JTAG and Angel like support for processor context saving and restoring Re
268. ialization of an external interrupt the corresponding bit in the EXTINT register must be cleared For details see Section 3 5 4 External Interrupt Mode register EXTMODE OxEO1F C148 and Section 3 5 5 External Interrupt Polarity register EXTPOLAR OxEO1F C140 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 20 Philips Semiconductors UM10120 I3 Volume 1 For example if a system wakes up from power down using a low level on external Chapter 3 System Control Block interrupt O pin its post wakeup code must reset the EINTO bit in order to allow future entry into the power down mode If the EINTO bit is left set to 1 subsequent attempt s to invoke power down mode will fail The same goes for external interrupt handling More details on power down mode will be discussed in the following chapters Table8 External Interrupt Flag register EXTINT address OxEO1F C140 bit description Bit Symbol 0 EINTO Description In level sensitive mode this bit is set if the EINTO function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINTO function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform the EINTO function see P0 1 and P0 16 description in Pin Configuration chapter page 64 This bit is cleared by writing a one to it e
269. idth Modulator output 3 l EINTO External interrupt O input P0 2 SCLO0 22131 yo P0 2 General purpose digital input output pin CAPO 0 y o SCLO I CO clock input output Open drain output for IC compliance l CAPO 0 Capture input for Timer 0 channel 0 P0 3 SDA0 2613 yo P0 3 General purpose digital input output pin MATO O EINT1 y o SDAO 2C0 data input output Open drain output for IPC compliance O MATO 0 Match output for Timer 0 channel 0 EINT1 External interrupt 1 input P0 4 SCKO 27 4 y o P0 4 General purpose digital input output pin CAPO 1 AD0 6 yo SCKO Serial clock for SPIO SPI clock output from master or input to slave l CAPO 1 Capture input for Timer 0 channel 0 l ADO 6 A D converter 0 input 6 This analog input is always connected to its pin P0 5 MISOO 29 41 yo P0 5 General purpose digital input output pin MATO 1 ADO 7 y o MISOO Master In Slave OUT for SPIO Data input to SPI master or data output from SPI slave O MATO 1 Match output for Timer 0 channel 1 l ADO 7 A D converter 0 input 7 This analog input is always connected to its pin P0 6 MOSIO 30 4 yo P0 6 General purpose digital input output pin CAPO 2 AD1 0 y o MOSIO Master Out Slave In for SPIO Data output from SPI master or data input to SPI slave l CAPO 2 Capture input for Timer 0 channel 2 l AD1 0 A D converter 1 input 0 This analog input is always connected to its pin Available in LPC21
270. ights reserved User manual Rev 01 24 June 2005 234 Philips Semiconductors UM10120 ja Volume 1 Chapter 20 Flash Memory 20 9 7 Compare lt address1 gt lt address2 gt no of bytes gt 20 9 8 20 9 9 Table 217 IAP Compare command Command Input Compare Command code 5646 ParamO DST Starting Flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRO Starting Flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 Return Code CMD SUCCESS COMPARE ERROR COUNT ERROR Byte count is not a multiple of 4 ADDR ERROR ADDR NOT MAPPED Result ResultO0 Offset of the first mismatch if the Status Code is COMPARE ERROR Description This command is used to compare the memory contents at two locations The result may not be correct when the source or destination includes any of the first 64 bytes starting from address zero The first 64 bytes can be re mapped to RAM Reinvoke ISP Table 218 Reinvoke ISP Command Compare Input Command code 5716 Return Code None Result None Description This command is used to invoke the bootloader in ISP mode This command maps boot vectors configures P0 1 as an input and sets the vpb divider register to 0 before entering the ISP mode This command may b
271. ilable on LPC2134 6 8 7 4 3 Pin function Select register 2 PINSEL2 OXE002 C014 The PINSEL2 register controls the functions of the pins as per the settings listed in Table 60 The direction control bit in the IO1DIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Warning use read modify write operation when accessing PINSEL2 register Accidental write of 0 to bit 2 and or bit 3 results in loss of debug and or trace functionality Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 77 Philips Semiconductors UM1 01 20 Volume 1 7 4 4 Chapter 7 Pin Connect Block Table 60 Pin function Select register 2 PINSEL2 0xE002 C014 bit description Bit Symbol Value Function Reset value 1 0 Reserved user software should not write ones NA to reserved bits The value read from a reserved bit is not defined 2 GPIO DEBUG 0 Pins P1 36 26 are used as GPIO pins P1 26 RTCK 1 Pins P1 36 26 are used as a Debug port 3 GPIO TRACE 0 Pins P1 25 16 are used as GPIO pins P1 20 TRACESYNC 1 Pins P1 25 16 are used as a Trace port 31 4 Reserved user software should not write ones NA to reserved bits The value read from a reserved bit is not defined Pin function select re
272. include reserved bits content Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 27 Philips Semiconductors UM1 01 20 m Volume 1 Chapter 3 System Control Block rper urere Direct PHASE FREQUENCY DETECTOR DIV BY M MSEL lt 4 0 gt MSEL 4 0 Fig 10 PLL block diagram 3 7 2 PLL Control register PLLCON OxEO1F C080 The PLLCON register contains the bits that enable and connect the PLL Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given see Section 3 7 7 PLL Feed register PLLFEED OxEO1F CO8C and Section 3 7 3 PLL Configuration register PLLCFG 0xE01F C084 on page 29 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 28 Philips Semiconductors UM1 01 20 ial Volume 1 3 7 3 3 7 4 Chapter 3 System Control Block Table 14 PLL Control register PLLCON address OxEO1F C080 bit description Bit Symbol Description Reset value 0 PLLE PLL Enable When one and after a valid PLL feed this bit will 0 activate the PLL and allow it to lock to the requested frequency See PLLSTAT register Table
273. ined state of th bus Fig 32 Format and States in the Slave Transmitter mode 11 8 4 Slave Transmitter mode In the slave transmitter mode a number of data bytes are transmitted to a master receiver see Figure 32 Data transfer is initialized as in the slave receiver mode When I2ADR and I2CON have been initialized the 12C block waits until it is addressed by its own slave address followed by the data direction bit which must be 1 R for the I C block to operate in the slave transmitter mode After its own slave address and the R bit have been received the serial interrupt flag SI is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Table 123 The slave transmitter mode may also be entered if arbitration is lost while the 12C block is in the master mode see state 0xBO If the AA bit is reset during a transfer the 12C block will transmit the last byte of the transfer and enter state OXCO or 0xC8 The I C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset the 12C block does not respond to its own slave address or a general call address However the I2C bus is still monitored and address recognition may be resumed at any time by setting AA
274. ion conditions 150 SOSPSR 0xE002 0004 153 12 2 7 Read Overrun 202000 ulus 150 12 4 3 SPI Data Register SOSPDR 0xE002 0008 154 12 2 8 Write Collision 200005 150 12 4 4 SPI Clock Counter Register SOSPCCR 12 2 9 Mode Fault 00 e eee eee 151 OxE002 000C eee eee eee 154 12 240 Slave Abort 20000 151 12 4 5 SPI Interrupt register 12 3 Pindescription 0 00005 151 SOSPINT OxE002 001C 154 12 4 Register description Qo a ere EIE et m e 151 12 5 Architecture 00 000 cee eee eee 155 Chapter 13 SSP Controller SPI1 13 1 F atures 22 colis eee wee Emus 156 13 4 1 SSP Control Register 0 13 2 Description 0 0 000eeeees 156 SSPCRO OxE006 8000 165 13 3 Busdescription c cceeeeeeee 157 1942 SEC Ee T Test hic eed Synchronous Seral Sal 5 1343 SSP Data Register SSPDR 0xE006 8008 167 urs ee ea 13 4 4 SSP Status Register 3 rame format 000 0005 158 SSPSR 0xE006 800C 167 es or Rad or iEEand Clack Phase E 13 4 5 SSP Clock Prescale Register SSPCPSR MN AE ABAL A ADHA A S Mn OxE006 8010 sulusssslssss 167 13 3 4 SPI format with CPOL 0 CPHA 0 159 A 13 3 5 SPI format with CPOL 0 CPHA 1 eM OS gael ele re 13 3 6 SPI format with CPOL 1 CPHA 2 0 161 1347 SSP Raw Int gt Stat eee isti SSPRIS i 13 3 7 SPI format with CPOL
275. ips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 174 Philips Semiconductors UM1 01 20 Volume 1 14 5 4 14 5 5 14 5 6 14 5 7 Chapter 14 TIMERO and TIMER1 Table 148 Count Control Register CTCR TIMERO TOCTCR address 0xE000 4070 and TIMER1 T1TCR address 0xE000 8070 bit description Bit Symbol Value Description Reset value 3 2 Count When bits 1 0 in this register are not 00 these bits select 00 Input which CAP pin is sampled for clocking Select 99 CAPn 0 CAPO 0 for TIMERO and CAP1 0 for TIMER1 01 CAPn 1 CAPO 1 for TIMERO and CAP1 1 for TIMER1 10 CAPn 2 CAPO 2 for TIMERO and CAP1 2 for TIMER1 11 CAPn 3 CAPO 3 for TIMERO and CAP1 3 for TIMER1 Note If Counter mode is selected for a particular CAPn input in the ThCTCR the 3 bits for that input in the Capture Control Register TRhCCR must be programmed as 000 However capture and or interrupt can be selected for the other 3 CAPn inputs in the same timer 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Timer Counter TC TIMERO TOTC 0xE000 4008 and TIMER1 T1TC OxE000 8008 The 32 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFF FFFF and then wrap back to the value 0x0000 0000
276. ips Semiconductors UM1 01 20 ia Volume 1 12 2 3 12 2 4 Chapter 12 SPI When a device is a slave and CPHA is set to 0 the transfer starts when the SSEL signal goes active and ends when SSEL goes inactive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the last clock edge where data is sampled General information There are four registers that control the SPI peripheral They are described in detail in Section 12 4 Register description on page 151 The SPI control register contains a number of programmable bits used to control the function of the SPI block The settings for this register must be set up prior to a given data transfer taking place The SPI status register contains read only bits that are used to monitor the status of the SPI interface including normal functions and exception conditions The primary purpose of this register is to detect completion of a data transfer This is indicated by the SPIF bit The remaining bits in the register are exception condition indicators These exceptions will be described later in this section The SPI data register is used to provide the transmit and receive data bytes An internal shift register in the SPI block logic is used for the actual transmission and reception of the serial data Data is written to the SPI data register for the transmit case There is no buffer between the data r
277. iption The Timer Counter is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers It also includes four capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt 14 4 Pin description Table 144 gives a brief summary of each of the Timer Counter related pins Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 170 Philips Semiconductors UM1 01 20 B Volume 1 Chapter 14 TIMERO and TIMER1 Table 144 Timer Counter pin description Pin Type Description CAPO 3 0 Input Capture Signals A transition on a capture pin can be configured to CAP1 3 0 load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Capture functionality can be selected from a number of pins When more than one pin is selected for a Capture input on a single TIMERO 1 channel the pin with the lowest Port number is used If for example pins 30 P0 6 and 46 P0 16 are selected for CAPO 2 only pin 30 will be used by TIMERO to perform CAPO 2 function Here is the list of all CAPTURE signals together with pins on where they can be selected e CAPO 0 3 pins P0 2 P0 22 and P0 30 e CAPO 1 2 pins P0 4 and P0 27 e CAPO 2 3 pin P0 6 P0 16
278. iption Bit Symbol Description Reset value 7 0 DLLSB The UART1 Divisor Latch LSB Register along with the U1DLM 0x01 register determines the baud rate of the UART1 Table 92 UART1 Divisor Latch MSB register U1DLM address 0xE001 0004 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLMSB The UART1 Divisor Latch MSB Register along with the UiDLL 0x00 register determines the baud rate of the UART1 UART1 Baud rate calculation Example Using UART1 paudrate Equation 2 from above it can be determined that system with PCLK 20 MHz U1DL 130 U1DLM 0x00 and U1DLL 0x82 will enable UART1 with UART 1bauarate 9615 baud Table 93 Some baud rates available when using 20 MHz peripheral clock PCLK 20 MHz Desired U1DLM U1DLL 96 errorl Desired U1DLM U1DLL 96 errori baud rate hex dec baud rate hex dec 50 0x61A8 25000 0 4800 0x0104 260 0 1603 75 0x411B 16667 0 0020 7200 Ox00AE 174 0 2235 110 0x2C64 11364 0 0032 9600 0x0082 130 0 1603 134 5 0x244E 9294 0 0034 19200 0x0041 65 0 1603 150 0x208D 8333 0 0040 38400 0x0021 33 1 3573 300 0x1047 4167 0 0080 56000 0x0021 22 1 4610 600 0x0823 2083 0 0160 57600 0x0016 22 1 3573 1200 0x0412 1042 0 0320 112000 0x000B 11 1 4610 1800 0x02B6 694 0 0640 115200 0x000B 11 1 3573 2000 0x0271 625 0 224000 0x0006 6 6 9940 2400 0x0209 521 0 0320 448000 0x0003 3 6 9940 3600 0x015B 347 0 0640 1 Relative error calculated as
279. is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event corresponds to the one selected by bits 1 0 in the CTCR register the Timer Counter register will be incremented Effective processing of the externaly supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the high low levels on the same CAP input in this case can not be shorter than 1 PCLK Table 148 Count Control Register CTCR TIMERO TOCTCR address 0xE000 4070 and TIMER1 T1TCR address 0xE000 8070 bit description Bit Symbol Value Description Reset value 1 0 Counter This field selects which rising PCLK edges can increment 00 Timer Timer s Prescale Counter PC or clear PC and increment Mode Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 10 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 11 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 Koninklijke Phil
280. ister WDFEED address OxE001 4050 bit description 192 OxE000 0008 bit description 214 Table 161 ADC pin description 193 Table 191 Watchdog Timer Value register WDTV address Table 162 ADC registers esee 194 OxE000 000C bit description 214 Table 163 A D Control Register ADOCR address Table 192 Flash sectors in LPC2131 LPC2132 LPC2134 0xE003 4000 and AD1CR address LPC2136 and LPC2138 221 OxE006 0000 bit description 194 Table 193 ISP command summary 223 Table 164 A D Data Register ADODR address Table 194 ISP Unlock command 223 OxE003 4004 and AD1DR address Table 195 ISP Set Baud Rate command 223 OxE006 0004 bit description 196 Table 196 Correlation between possible ISP baudrates and Table 165 A D Global Start Register ADGSR address external crystal frequency in MHz 224 OxE003 4008 bit description 196 Table 197 ISP Echo command 224 Table 166 DAC pin description 198 Table 198 ISP Write to RAM command 225 Table 167 DAC Register DACR address 0xE006 C000 bit Table 199 ISP Read memory command 225 description roh RE Ce 198 Table 200 ISP Prepare sector s for write operation Table 168 Real Time Clock RTC register map 201 COMMANA i ssc edhe wb arte D 226 Table 169 Miscellaneous re
281. ister 0 MRO can be enabled through the R W 0 OxE000 4018 OxE000 8018 MCR to reset the TC stop both the TC and PC TOMRO T1MRO and or generate an interrupt every time MRO matches the TC MR1 Match Register 1 See MRO description R W 0 OxE000 401C OxE000 801C TOMR1 T1MR1 MR2 Match Register 2 See MRO description R W 0 OxE000 4020 OxE000 8020 TOMR2 T1MR2 MR3 Match Register 3 See MRO description R W 0 OxE000 4024 OxE000 8024 TOMR3 T1MR3 CCR Capture Control Register The CCR controls which R W 0 OxE000 4028 OxEO000 8028 edges of the capture inputs are used to load the TOCCR T1CCR Capture Registers and whether or not an interrupt is generated when a capture takes place CRO Capture Register 0 CRO is loaded with the value of RO 0 OxE000 402C OxE000 802C TC when there is an event on the CAPn 0 CAPO0 0 or TOCRO T1CRO CAP1 0 respectively input CR1 Capture Register 1 See CRO description RO 0 OxE000 4030 0xE000 8030 TOCR1 T1CR1 CR2 Capture Register 2 See CRO description RO 0 OxE000 4034 OxE000 8034 TOCR2 T1CR2 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 Philips Semiconductors UM10120 ja Volume 1 Table 145 TIMER COUNTERO and TIMER COUNTER1 register map Chapter 14 TIMERO and TIMER1 Generic Description Name Access Reset TIMER TIMER COUNTERO COUNTER1 Address amp Name Address amp Name CR3 Capture Register 3 See CRO description RO OxEO0
282. ister R W OxE002 4038 YEAR 12 Years Register R W j 0xE002 403C ALSEC 6 Alarm value for Seconds R W OxE002 4060 ALMIN 6 Alarm value for Minutes R W 2 OxE002 4064 ALHOUR 5 Alarm value for Seconds R W D OxE002 4068 ALDOM 5 Alarm value for Day of Month R W n OxE002 406C ALDOW 3 Alarm value for Day of Week R W 7 0xE002 4070 ALDOY 9 Alarm value for Day of Year R W E OxE002 4074 ALMON 4 Alarm value for Months R W 2 OxE002 4078 ALYEAR 12 Alarm value for Year R W 0xE002 407C PREINT 13 Prescaler value integer portion R W 0 OxE002 4080 PREFRAC 15 Prescaler value integer portion R W 0 OxE002 4084 1 Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset These registers must be initialized by software if the RTC is enabled Reset value relects the data stored in used bits only It does not include reserved bits content Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 201 Philips Semiconductors UM1 01 20 ia Volume 1 18 4 1 18 4 2 18 4 3 Chapter 18 RTC RTC interrupts Interrupt generation is controlled through the Interrupt Location Register ILR Counter Increment Interrupt Register CIIR the alarm registers and the Alarm Mask Register AMR Interrupts are generated only by the transition into the interrupt state The ILR separately enables CIIR and AMR interrupts Each bit in CIIR corresponds to one of the time co
283. ital input output pin CAP1 1 SCL1 l CTS1 Clear to Send input for UART1 Available in LPC2134 6 8 only CAP1 1 Capture input for Timer 1 channel 1 y o SCL1 I C1 clock input output Open drain output for 12C compliance P0 12 DSR1 38 4 yo P0 12 General purpose digital input output pin MAT1 0 AD1 3 l DSR1 Data Set Ready input for UART1 Available in LPC2134 6 8 only O MAT1 0 Match output for Timer 1 channel 0 AD1 3 A D converter input 3 This analog input is always connected to its pin Available in LPC2134 6 8 only P0 13 DTR1 39 41 y o P0 13 General purpose digital input output pin MAT1 1 AD1 4 O DTR1 Data Terminal Ready output for UART1 Available in LPC2134 6 8 only Oo MAT1 1 Match output for Timer 1 channel 1 AD1 4 A D converter input 4 This analog input is always connected to its pin Available in LPC2134 6 8 only P0 14 DCD1 4113 y o P0 14 General purpose digital input output pin EINT1 SDA1 DCD1 Data Carrier Detect input for UART1 Available in LPC2134 6 8 only EINT1 External interrupt 1 input y o SDA1 I C1 data input output Open drain output for 12C compliance Note LOW on this pin while RESET is LOW forces on chip boot loader to take over control of the part after reset P0 15 RI1 45 4 yo P0 15 General purpose digital input output pin EINT2 AD1 5 l RI Ring Indicator input for UART1 Available in LPC2134 6 8 only l EINT2 External interrupt 2 inpu
284. itor internal function If the DCC write buffer is free control is passed to rm TransmitData RealMonitor internal function If there is nothing else to do the function returns to the caller The ordering of the above comparisons gives reads from the DCC a higher priority than writes to the communications link RealMonitor stops the foreground application Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped 23 4 How to enable Realmonitor 23 4 1 23 4 2 23 4 3 23 4 4 The following steps must be performed to enable RealMonitor A code example which implements all the steps can be found at the end of this section Adding stacks User must ensure that stacks are set up within application for each of the processor modes used by RealMonitor For each mode RealMonitor requires a fixed number of words of stack space User must therefore allow sufficient stack space for both RealMonitor and application RealMonitor has the following stack requirements Table 225 RealMonitor stack requirement Processor Mode RealMonitor Stack Usage Bytes Undef 48 Prefetch Abort 16 Data Abort 16 IRQ 8 IRQ mode A stack for this mode is always required RealMonitor uses two words on entry to its interrupt handler These are freed before nested interrupts are enabled Undef mode A stack for this mode is always required RealMonitor use
285. ks In general terms the RealMonitor operates as a state machine as shown in Figure 61 RealMonitor switches between running and stopped states in response to packets received by the host or due to asynchronous events on the target RMTarget supports the triggering of only one breakpoint watchpoint stop or semihosting SWI at a time There is no provision to allow nested events to be saved and restored So for example if user application has stopped at one breakpoint and another breakpoint occurs in an IRQ handler RealMonitor enters a panic state No debugging can be performed after RealMonitor enters this state SWI Abort LI Sa STOPPED Fig 61 RealMonitor as a state machine A debugger such as the ARM eXtended Debugger AXD or other RealMonitor aware debugger that runs on a host computer can connect to the target to send commands and receive data This communication between host and target is illustrated in Figure 60 The target component of RealMonitor RMTarget communicates with the host component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While user application is running RMTarget typically uses IRQs generated by the DCC This means that if user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic in the processor generates a Prefet
286. l Rev 01 24 June 2005 136 Philips Semiconductors UM1 01 20 iz Volume 1 11 8 12 11 8 13 Chapter 11 I C interfaces If an uncontrolled source generates a superfluous START or masks a STOP condition then the I C bus stays busy indefinitely If the STA flag is set and bus access is not obtained within a reasonable amount of time then a forced access to the I C bus is possible This is achieved by setting the STO flag while the STA flag is still set No STOP condition is transmitted The 12C hardware behaves as if a STOP condition was received and is able to transmit a START condition The STO flag is cleared by hardware see Figure 34 I C bus obstructed by a low level on SCL or SDA An I C bus hang up occurs if SDA or SCL is pulled LOW by an uncontrolled source If the SCL line is obstructed pulled LOW by a device on the bus no further serial transfer is possible and the 12C hardware cannot resolve this type of problem When this occurs the problem must be resolved by the device that is pulling the SCL bus line LOW If the SDA line is obstructed by another device on the bus e g a slave device out of bit synchronization the problem can be solved by transmitting additional clock pulses on the SCL line see Figure 35 The I C hardware transmits additional clock pulses when the STA flag is set but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free The 12C hardware
287. l rights reserved User manual Rev 01 24 June 2005 199 UM10120 Chapter 18 Real Time Clock eee Rev 01 24 June 2005 User manual E 18 1 Features e Measures the passage of time to maintain a calendar and clock e Ultra Low Power design to support battery powered systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year Dedicated 32 kHz oscillator or programmable prescaler from VPB clock Dedicated power supply pin can be connected to a battery or to the main 3 3 V 18 2 Description The Real Time Clock RTC is a set of counters for measuring time when system power is on and optionally when it is off It uses little power in Power down mode On the LPC2131 2 4 6 8 the RTC can be clocked by a separate 32 768 KHz oscillator or by a programmable prescale divider based on the VPB clock Also the RTC is powered by its own power supply pin Vgar which can be connected to a battery or to the same 3 3 V supply used by the rest of the device 18 3 Architecture RTC OSCILLATOR CLK32k CLOCK GENERATOR REFERENCE CLOCK DIVIDER PRESCALER TIME COMPARATORS i AEM COUNTERS REGISTERS COUNTER INCREMENT ALARM MASK Counter INTERRUPT ENABLE s enables REGISTER INTERRUPT GENERATOR Fig 51 RTC block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 200 Philips Semiconductors U
288. latched SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCRO control register Clock Polarity CPOL and Clock Phase CPHA control When the CPOL clock polarity control bit is LOW it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 158 Philips Semiconductors UM1 01 20 I3 Volume 1 13 3 4 Chapter 13 SSP The CPHA control bit selects the clock edge that captures data and allows it to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the CPHA phase control bit is LOW data is captured on the first clock edge transition If the CPHA clock phase control bit is HIGH data is captured on the second clock edge transition SPI format with CPOL 0 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 0 CPHA 0 are shown in Figure 39 4 to 16 bits _ gt 4 to 16 bits Fig 3
289. ld use this area if RealMonitor based debug is not required The Flash boot loader does not initialize the stack for RealMonitor Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 219 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 20 Flash Memory 20 4 14 Boot process flowchart INITIALIZE CRP ENABLED WATCHDOG FLAG SET ENABLE DEBUG USER CODE VALID ENTER ISP MODE PO 14 LOWZ EXECUTE INTERNAL USER CODE RUN AUTO BAUD AUTO BAUD SUCCESSFUL Yes RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER Code read protection Fig 56 Boot process flowchart 20 5 Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers The following table indicate the correspondence between sector numbers and memory addresses for LPC2131 2 4 6 8 devices containing 32 64 128 256 and 512K bytes of Flash respectively IAP ISP and RealMonitor routines are located in the boot block The Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 220 Philips Semiconductors UM10120 ja Volume 1 Chapter 20 Flash Memory boot block is present at addresses 0x0007 D000 to 0x0007 FFFF in all devices ISP and IAP commands do not allow write erase go operation on the boot block Because of the boot block the amount of Fl
290. le 6 COUNT ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR NOT BLANK Sector is not blank 9 SECTOR NOT PREPARED FOR Command to prepare sector for write operation was WRITE OPERATION not executed 10 COMPARE ERROR Source and destination data not equal 11 BUSY Flash programming hardware interface is busy Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 229 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 20 Flash Memory Table 209 ISP Return codes Summary Return Mnemonic Description Code 12 PARAM_ERROR Insufficient number of parameters or invalid parameter 13 ADDR_ERROR Address is not on word boundary 14 ADDR_NOT_MAPPED Address is not mapped in the memory map Count value is taken in to consideration where applicable 15 CMD_LOCKED Command is locked 16 INVALID CODE Unlock code is invalid 17 INVALID BAUD RATE Invalid baud rate setting 18 INVALID STOP BIT Invalid stop bit setting 19 CODE READ PROTECTION Code read protection enabled ENABLED 20 9 IAP Commands For in application programming the IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table point
291. le interrupt when the Tx 0 FIFO is at least half empty 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined SSP Raw Interrupt Status register SSPRIS 0xE006 8018 This read only register contains a 1 for each interrupt condition that is asserted regardless of whether or not the interrupt is enabled in the SSPIMSC Table 141 SSP Raw Interrupt Status register SSPRIS address 0xE006 8018 bit description Bit Symbol Description Reset value 0 RORRIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTRIS This bit is 1 if when there is a Receive Timeout condition Note 0 that a Receive Timeout can be negated if further data is received RXRIS This bit is 1 if the Rx FIFO is at least half full 0 TXRIS This bit is 1 if the Tx FIFO is at least half empty 1 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 168 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 13 SSP 13 4 8 SSP Masked Interrupt register SSPMIS 0xE006 801C 13 4 9 This read only register contains a 1 for each interrupt condition th
292. leared until the watchdog underflows or Interrupt an external reset occurs Fig 54 Watchdog block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 215 UM10120 Chapter 20 Flash Memory System and Programming Rev 01 24 June 2005 User manual Ml Semiconductors 20 1 Flash Boot Loader The Boot Loader controls initial operation after reset and also provides the means to accomplish programming of the Flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the Flash memory by the application program in a running system 20 2 Features n System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the boot loader software and a serial port This can be done when the part resides in the end user board n Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code 20 3 Applications The flash boot loader provides both In System and In Application programming interfaces for programming the on chip flash memory 20 4 Description The flash boot loader code is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user applic
293. led O 7 CAP2FE Capture on CAPn 2 falling edge a sequence of 1 then 0 on CAPn 2 will cause CR2to 0 be loaded with the contents of TC This feature is disabled 8 CAP2I Interrupt on CAPn 2 event a CR2 load due to a CAPn 2 event will generate an interrupt O This feature is disabled Oo O 9 CAP3RE Capture on CAPn 3 rising edge a sequence of 0 then 1 on CAPn 3 will cause CR3 to 0 be loaded with the contents of TC This feature is disabled Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 177 Philips Semiconductors UM1 01 20 B Volume 1 Chapter 14 TIMERO and TIMER1 Table 150 Capture Control Register CCR TIMERO TOCCR address 0xE000 4028 and TIMER1 T1CCR address 0xE000 8028 bit description Bit Symbol Value Description Reset value 10 CAP3FE 1 Capture on CAPn 3 falling edge a sequence of 1 then 0 on CAPn 3 will cause CR3 to 0 be loaded with the contents of TC 0 This feature is disabled 11 CAPSI 1 Interrupt on CAPn 3 event a CR3 load due to a CAPn 3 event will generate an interrupt O 0 This feature is disabled 1542 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 14 5 11 External Match Register EMR TIMERO TOEMR 0xE000 403C and TIMER1 T1EMR 0xE000 803C The External Match Register provides both control and status of
294. led by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Programmable 32 bit timer with internal pre scaler e Selectable time period from Tpci x 256 x 4 to Teci x 29 x 4 in multiples of Tpcik X 4 19 2 Applications The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the watchdog will generate a system reset if the user program fails to feed or reload the watchdog within a predetermined amount of time For interaction of the on chip watchdog and other peripherals especially the reset and boot up procedures please read Section 3 9 Reset on page 35 of this document 19 3 Description The watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OXFF causes OxFF to be loaded in the counter Hence the minimum watchdog interval is Tpci x 256 x 4 and the maximum watchdog interval is Tpc_ x 232 x 4 in multiples of Tpci x 4 The watchdog should be used in the following manner Set the watchdog timer constant reload value in WDTC register Setup mode in WDMOD register Start the watch
295. legal address This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 15 UM10120 Chapter 3 System Control Block NNNM Rev 01 24 June 2005 User manual ET 3 1 Summary of system control block functions The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices These include Crystal Oscillator External Interrupt Inputs Memory Mapping Control PLL Power Control Reset VPB Divider Wakeup Timer Each type of function has its own register s if any are required and unneeded bits are defined as reserved in order to allow future expansion Unrelated functions never share the same register addresses 3 2 Pin description Table 4 shows pins that are associated with System Control block functions Table 4 Pin summary Pin name Pin Pin description direction X1 Input Crystal Oscillator Input Input to the oscillator and internal clock generator circuits X2 Output Crystal Oscillator Output Output from the oscillator amplifier EINTO Input External Interrupt Input 0 An active low high level or falling rising edge general purpose interrupt input This pin may be used to wake up the processor from Idle or Power down modes
296. level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THREE U1IIR Read if source of interrupt or THR write 000012 Fourth Modem Status CTS or DSR or RI or DCD MSR Read 10 3 7 1 Values 0000 see Table note 2 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 LPC2134 6 8 only 3 For details see Section 10 3 10 UART1 Line Status Register U1LSR 0xE001 0014 Read Only 4 For details see Section 10 3 1 UART1 Receiver Buffer Register U1RBR 0xE001 0000 when DLAB 0 Read Only 5 For details see Section 10 3 6 UART1 Interrupt Identification Register U1IIR OxE001 0008 Read Only and Section 10 3 2 UART1 Transmitter Holding Register U1THR 0xE001 0000 when DLAB 0 Write Only The UART1 THRE interrupt U1IIR 3 1 001 is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the U1THR at one time since the last
297. limit of the CPU The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle A block diagram of the PLL is shown in Figure 10 PLL activation is controlled via the PLLCON register The PLL multiplier and divider values are controlled by the PLLCFG register These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL Since all chip operations including the Watchdog Timer are dependent on the PLL when it is providing the chip clock accidental changes to the PLL setup could result in unexpected behavior of the microcontroller The protection is accomplished by a feed sequence similar to that of the Watchdog Timer Details are provided in the description of the PLLFEED register Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 26 Philips Semiconductors UM10120 I3 Volume 1 3 7 1 Chapter 3 System Control Block The PLL is turned off and bypassed following a chip Reset and when by entering Power down mode The PLL is enabled by software only The program must configure and activate the PLL wai
298. ll attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UART1 RBR FIFO Framing error status is inactive Framing error status is active 4 Break Interrupt BI When RXD1 is held in the spacing state all 0 s for one full character transmission 0 start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all 1 s An U1LSR read clears this status bit The time of break detection is dependent on U1FCR O Note The break interrupt is associated with the character at the top of the UART1 RBR FIFO Break interrupt status is inactive Break interrupt status is active 5 Transmitter Holding Register Empty THRE THRE is set immediately upon detection of an empty UART1 THR and is cleared on 1 a U1THR write U1THR contains valid data U1THR is empty 6 Transmitter TEMT is set when both U1THR and U1TSR are empty TEMT is cleared when 1 Empty either the U1TSR or the U1THR contain valid data TEMT U1THR and or the U1TSR contains valid data U1THR and the U1TSR are empty 7 Errorin RX U1LSR 7 is set when a character with a RX error such as framing
299. ll rights reserved User manual Rev 01 24 June 2005 230 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 20 Flash Memory typedef void IAP unsigned int unsigned int IAP iap entry Setting function pointer iap entry IAP IAP LOCATION Whenever you wish to call IAP you could use the following statement iap entry command result The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS ARM Developer Suite You could also call the IAP routine using assembly code The following symbol definitions can be used to link IAP routine and user application lt SYMDEFS gt ARM Linker ADS1 2 Build 826 Last Updated Wed May 08 16 12 23 2002 Ox7 ffff90 T rm init entry 0x7fffffa0 A rm undef handler Ox7fffffb0 A rm prefetchabort handler Ox7fffffc0 A rm dataabort handler Ox7fffffd0 A rm irghandler Ox7fffffe0 A rm irghandler2 Ox7 fffff0 T iap entry As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning t
300. lly cleared Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs any value written to the PWM Match registers has no effect on PWM operation For example if PWM2 is configured for double edge operation and is currently running a typical sequence of events for changing the timing would be e Write a new value to the PWM Match1 register Write a new value to the PWM Match2 register Write to the PWMLER setting bits 1 and 2 at the same time The altered values will become effective at the next reset of the timer when a PWM Match 0 event occurs Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 191 Philips Semiconductors UM10120 B Volume 1 Chapter 15 PWM The order of writing the two PWM Match registers is not important since neither value will be used until after the write to PWMLER This insures that both values go into effect at the same time if that is required A single value may be altered in the same way if needed The function of each of the bits in the PWMLER is shown in Table 160 Table 160 PWM Latch Enable Register PWMLER address 0xE001 4050 bit description Bit Symbol Description Reset value 0 Enable PWM Writing a one to this bit allows the last value written to the PWM 0 Match 0 Latch Match 0 register to be become effective when the timer is next r
301. manual Rev 01 24 June 2005 93 Philips Semiconductors UM10120 ja Volume 1 Chapter 9 UARTO NTXRDY TXDO li UOTHR M UOTSR a NBAUDOUT RCLK NRXRDY UORBR UORSR oom OINTR UOIER x pL LT UoIIR UOFCR UOLSR UOSCR UOLCR PA 2 0 PSEL PSTB PWRITE PD 7 0 Niece PRIS AR MR PCLK Fig 18 LPC2131 2 4 6 8 UARTO block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 94 Semiconductors 10 1 Features UM10120 Chapter 10 Universal Asynchronous Receiver Transmitter 1 UART1 Rev 01 24 June 2005 User manual li 10 2 Pin description UARTI is identical to UARTO with the addition of a modem interface 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Standard modem interface signals included LPC2134 6 8 only LPC2131 2 4 6 8 UART1 provides mechanism that enables implementation of either software or hardware flow control Table 87 UART1 pin description Pin RXD1 Type Input Description Serial Input Serial receive data TXD1 Output Serial Output Serial transmit data CTS1Ul DCD1l1 Input Clear To Send Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1 In normal
302. mbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversons will not start 0 Conversions are software controlled and require 11 clocks 23 17 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 196 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter Table 165 A D Global Start Register ADGSR address 0xE003 4008 bit description Bit Symbol Value Description Reset value 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversion is 0 started 000 No start this value should be used when clearing PDN to 0 001 Start conversion now 010 Start conversion when the edge selected by bit 27 occurs on P0 16 EINTO MATO 2 CAPO 2 pin 011 Start conversion when the edge selected by bit 27 occurs on P0 22 TD3 CAP0 0 MATO 0 pin 100 Start conversion when the edge selected by bit 27 occurs on MATO 1 101 Start conversion when the edge selected by bit 27 occurs on MATO 3 110 Start conversion when the edge selected by bit 27 occurs on MAT1 0 111 Start conversion when the edge selected by bit 27 occ
303. mbol Value Description Reset value 31 0 See 0 The interrupt request with this bit number is assigned to the IRQ 0 VICIntSelect category bit allocation 4 The interrupt request with this bit number is assigned to the FIQ table category 5 4 7 IRQ Status register VICIRQStatus OXFFFF F000 This is a read only register This register reads out the state of those interrupt requests that are enabled and classified as IRQ It does not differentiate between vectored and non vectored IRQs Table 46 IRQ Status register VICIRQStatus address OxFFFF F000 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol s Access RO RO RO RO RO RO RO RO Bit 23 22 21 20 19 18 17 16 Symbol AD1 BOD I2C1 ADO EINT3 EINT2 Access RO RO RO RO RO RO RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPI1 SSP SPIO I2C0 PWMO Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCore1 ARMCoreO gt WDT Access RO RO RO RO RO RO PO RO Table 47 IRQ Status register VICIRQStatus address OxFFFF F000 bit description Bit Symbol Description Reset value 31 0 See A bit read as 1 indicates a coresponding interrupt request being enabled 0 VICIRQStatus classified as IRQ and asserted bit allocation table Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 54 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 5
304. mer Counter 1 power clock control bit 1 3 PCUARTO UARTO power clock control bit 1 4 PCUART1 UART1 power clock control bit 1 5 PCPWMO PWMO power clock control bit 1 6 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 7 PCI2CO The l CO interface power clock control bit 1 8 PCSPIO The SPIO interface power clock control bit 1 9 PCRTC The RTC power clock control bit 1 10 PCSPI1 The SSP interface power clock control bit 1 11 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 12 PCADO A D converter 0 ADCO power clock control bit 1 Note Clear the PDN bit in the ADOCR before clearing this bit and set this bit before setting PDN 1843 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 19 PCI2C1 The I C1 interface power clock control bit 1 20 PCAD1 A D converter 1 ADC1 power clock control bit 1 Note Clear the PDN bit in the AD1CR before clearing this bit and set this bit before setting PDN 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Power control usage notes After every reset the PCONP register contains the value that enables all interfaces and peripherals controlled by the PCONP to be enabled Therefore apart from proper confi
305. microcontroller See Table 23 PCONP Power Control for Peripherals Register This R W 0x0018 17BE OxE01F COC4 register contains control bits that enable and disable individual peripheral functions Allowing elimination of power consumption by peripherals that are not needed 1 Reset value relects the data stored in used bits only It does not include reserved bits content Power Control register PCON 0xE01F COCO The PCON register contains two bits Writing a one to the corresponding bit causes entry to either the Power down or Idle mode If both bits are set Power down mode is entered Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 33 Philips Semiconductors UM1 01 20 ia Volume 1 3 8 3 Chapter 3 System Control Block Table 23 Power Control register PCON address 0xE01F COCO bit description Bit Symbol Description Reset value 0 IDL Idle mode when 1 this bit causes the processor clock to be stopped 0 while on chip peripherals remain active Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution 1 PD Power down mode when 1 this bit causes the oscillator and all 0 on chip clocks to be stopped A wakeup condition from an external interrupt can cause the oscillator to restart the PD bit to be cleared and the processor to resume execution 2 PDBOD When PD is 1 and this
306. missions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured SPI format with CPOL 0 CPHA 1 The transfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 40 which covers both single and continuous transfers 4 to 16 bits a Motorola SPI frame format single transfer with CPOL 0 and CPHA 1 Fig 40 SPI frame format with CPOL 0 and CPHA 1 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI pin is enabled After a further one half SCK period both master and slave valid data is enabled onto their respective transmission lines At the same time the SCK is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the ri
307. mmand Command Input E Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID SECTOR SECTOR NOT PREPARED FOR WRITE OPERATION CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to erase one or more sector s of on chip Flash memory The boot block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 227 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 20 Flash Memory 20 8 10 Blank check sector s sector number end sector number Table 204 ISP Blank check sector command Command I Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS SECTOR NOT BLANK followed by Offset of the first non blank word location Contents of non blank word location INVALID SECTOR PARAM ERROR Description This command is used to blank check one or more sectors of on chip Flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block Example 2 3 lt CR gt lt LF gt blank checks the flash
308. n 12 2 4 SPI overview SPI is a full duplex serial interfaces It can handle multiple masters and slaves being connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends 8 to 16 bits of data to the slave and the slave always sends a byte of data to the master 12 2 2 SPI data transfers Figure 36 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing you should notice in this timing diagram is that it is divided into three horizontal parts The first part describes the SCK and SSEL signals The second part describes the MOSI and MISO signals when the CPHA variable is 0 The third part describes the MOSI and MISO signals when the CPHA variable is 1 In the first part of the timing diagram note two points First the SPI is illustrated with CPOL set to both 0 and 1 The second point to note is the activation and de activation of the SSEL signal When CPHA 1 the SSEL signal will always go inactive between data transfers This is not guaranteed when CPHA 0 the signal can remain active Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 147 Philips Semiconductors UM10120 im Volume 1 Chapter 12 SPI sorotsi N N N NV N VS
309. n UARTO TX FIFO and reset the pointer logic This bit is self clearing 5 3 0 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 6 RX Trigger These two bits determine how many receiver 0 Level UARTO FIFO characters must be written before an 00 interrupt is activated Trigger level O 1 character or 0x01 01 Trigger level 1 4 characters or 0x04 10 Trigger level 2 8 characters or 0x08 11 Trigger level 3 14 characters or OxOE UARTO Line Control Register UOLCR 0xE000 CO0C The UOLCR determines the format of the data character that is to be transmitted or received Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 90 Philips Semiconductors UM10120 a volume 1 Chapter 9 UARTO Table 83 UARTO Line Control Register UOLCR address 0xE000 CO00C bit description Bit Symbol Value Description Reset value 1 0 Word Length 00 5 bit character length 0 Select 01 6 bit character length 10 7 bit character length 11 8 bit character length 2 Stop Bit Select 0 1 stop bit 0 1 2 stop bits 1 5 if VOLCR 1 0 00 l 3 Parity Enable 0 Disable parity generation and checking 0 1 Enable parity generation and checking 5 4 Parity Select 00 Odd parity Number of 1s in the transmitted character andthe 0 attached parity bit will be odd 01 E
310. n detected on RI 3 Delta DCD Set upon state change of input DCD Cleared on an U1MSR read 0 0 No change detected on modem input DCD 1 State change detected on modem input DCD 4 CTS Clear To Send State Complement of input signal CTS This bit is connected 0 to UTMCR 1 in modem loopback mode 5 DSR Data Set Ready State Complement of input signal DSR This bit is connected 0 to UTMCR 0 in modem loopback mode 6 Rl Ring Indicator State Complement of input RI This bit is connected to 0 U1MCR 2 in modem loopback mode 7 DCD Data Carrier Detect State Complement of input DCD This bit is connected to 0 U1MCR 3 in modem loopback mode 10 3 12 UART1 Scratch pad register U1SCR 0xE001 001C The U1SCR has no effect on the UART1 operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred Table 102 UART1 Scratch pad register U1SCR address 0xE001 0014 bit description Bit Symbol Description Reset value 7 0 Pad A readable writable byte 0x00 10 3 13 UART1 Transmit Enable Register U1TER 0xE001 0030 LPC2131 2 4 6 8 s UTTER enables implementation of software and hardware flow control When TXEn 1 UART1 transmitter will keep sending data as long as they are available As soon as TXEn becomes 0 UART1 transmittion will stop Table 103 describes how to us
311. n the range of 10 MHz to Fmax the maximum allowed frequency for the microcontroller determined by the system microcontroller is embedded in e Feco is in the range of 156 MHz to 320 MHz Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 31 Philips Semiconductors UM1 01 20 I3 Volume 1 3 7 10 3 7 11 Chapter 3 System Control Block Procedure for detrmining PLL settings If a particular application uses the PLL its configuration may be determined as follows 1 Choose the desired processor operating frequency CCLK This may be based on processor throughput requirements need to support a specific set of UART baud rates etc Bear in mind that peripheral devices may be running from a lower clock than the processor see Section 3 10 VPB divider on page 38 2 Choose an oscillator frequency Fosc CCLK must be the whole non fractional multiple of Fosc 3 Calculate the value of M to configure the MSEL bits M CCLK Fosc M must be in the range of 1 to 32 The value written to the MSEL bits in PLLCFG is M 1 see Table 21 4 Find a value for P to configure the PSEL bits such that Feco is within its defined frequency limits Feco is calculated using the equation given above P must have one of the values 1 2 4 or 8 The value written to the PSEL bits in PLLCFG is 00 for P 1 01 for P 2 10 for P 4 11 for P 8 see Table 20 Table 20 PLL
312. n this section 4 0 GB 3 75 GB 3 5 GB 3 0 GB RESERVED ADDRESS SPACE 2 0 GB BOOT BLOCK REMAPPED FROM ON CHIP FLASH MEMORY RESERVED ADDRESS SPACE 32 kB ON CHIP STATIC RAM LPC2136 2138 16 kB ON CHIP STATIC RAM LPC2132 2134 8 kB ON CHIP STATIC RAM LPC2131 1 0 GB RESERVED ADDRESS SPACE LPC2138 TOTAL OF 256 kB ON CHIP NON VOLATILE MEMORY TOTAL OF 128 kB ON CHIP NON VOLATILE MEMORY TOTAL OF 64 kB ON CHIP NON VOLATILE MEMORY TOTAL OF 32 kB ON CHIP NON VOLATILE MEMORY Fig 2 System memory map OxFFFF FFFF OxF000 0000 0xE000 0000 0xC000 0000 0x8000 0000 0x4000 8000 0x4000 7FFF 0x4000 4000 0x4000 3FFF 0x4000 2000 0x4000 1FFF 0x4000 0000 0x0008 0000 0x0007 FFFF 0x0004 0000 0x0003 FFFF 0x0002 0000 0x0001 FFFF 0x0001 0000 0x0000 FFFF 0x0000 8000 0x0000 7FFF 0x0000 0000 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 8 Philips Semiconductors UM10120 ja Volume 1 Chapter 2 Memory map 4 0 GB OxFFFF FFFF AHB PERIPHERALS OxFFEO 0000 RESERVED 4 0 GB 2 MB OxFFDF FFFF Notes AHB section is 128 x 16 kB blocks totaling 2 MB VPB section is 128 x 16 kB blocks totaling 2 MB OxF000 0000 THOME OxEFFF FFFF RESERVED 0xE020 0000 3 5 GB 2 MB OxEO1F FFFF VPB PERIPHERALS 0xE000 0000 3 5 GB Fig 3 Peripheral memory map Figures 3 through
313. nable Register U1TER 10 3 6 UART1 Interrupt Identification Register U1IIR EIO OAU EESE s 0xE001 0008 Read Only 100 10 4 Architecture lees ene eee 107 Chapter 11 I C interfaces 1 C0 and I C1 11 1 Features 2oco cl i IRE 109 11 5 2 Master Receiver mode 111 11 2 Applications seeenennnne 109 11 5 3 Slave Receiver mode 112 11 3 Description sse 109 11 5 4 Slave Transmitter mode 113 114 Pindescription sls 110 11 6 FC Implementation and operation IM 2 11 6 1 Input filters and output stages 114 Ti 5 operaning HIBOOSe coste pbi dins 110 162 Address Register ADDR 116 11 5 1 Master Transmitter mode 110 11 6 3 Comparator 0 0c eee eee 116 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 265 Philips Semiconductors UM10120 I3 Volume 1 Chapter 24 Supplementary information 11 6 4 Shiftregister I2DAT 116 11 8 12 I C bus obstructed by a low level on SCL or 11 6 5 Arbitration and synchronization logic 116 SDA oec esee ine mein fd eene 137 11 6 6 Serial clock generator 117 11 849 B s eror 2 heni Tete teehee head 137 11 6 7 Timing and control 00 117 11 8 14 C State service routines 138 11 6 8 Control register IBCO
314. nce the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled Example C 0 1073774592 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x4000 8000 to the flash address 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 226 Philips Semiconductors UM10120 ja Volume 1 Chapter 20 Flash Memory 20 8 8 Go lt address gt lt mode gt 20 8 9 Table 202 ISP Go command Command Input G Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Instead of address if string tEST is entered the program residing in reserved test area will be executed Mode T Execute program in Thumb Mode A Execute program in ARM mode Return Code CMD_SUCCESS ADDR_ERROR ADDR NOT MAPPED CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to execute a program residing in RAM or Flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled Example G 0 A lt CR gt lt LF gt branches to address 0x0000 0000 in ARM mode Erase sector s start sector number end sector number Table 203 ISP Erase sector co
315. nd I2C1 I2C1CONSET 0xE005 C000 The I2CONSET registers control setting of bits in the I2CON register that controls operation of the 12C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be set Writing a zero has no effect Table 108 I2C Control Set register IZCONSET I2C0 I2COCONSET address 0xE001 C000 and I2C1 I2C1CONSET address 0xE005 C000 bit description Bit Symbol Description Reset value 1 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 2 AA Assert acknowledge flag See the text below 3 SI 12C interrupt flag 0 4 STO STOP flag See the text below 0 5 STA START flag See the text below 0 6 I2EN 12C interface enable See the text below 0 Y Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined I2EN 12C Interface Enable When I2EN is 1 the 12C interface is enabled I2EN can be cleared by writing 1 to the I2ENC bit in the IICONCLR register When I2EN is 0 the I2C interface is disabled When I2EN is 0 the SDA and SCL input signals are ignored the I2C block is in the not addressed slave state and the STO bit is forced to 0 I2EN should not be used to temporarily release the I C bus since when I2EN is reset the I2C bus status is lost The AA flag should be used instead STA
316. nd l2C1 I2C1ADR 11 9 12 State 0x20 0 0 4 141 address OXEO05 C00C 122 11 9 13 State 0x28 002 000 ee 141 11 7 6 12C SCL High duty cycle register IPSCLH I2CO0 11 9 14 State 0x80 0 0 esee 142 I2COSCLH 0xE001 C010 and 12C1 I2C1SCLH 11 9 15 State 0x38 00005 142 OxE0015 C010 eee eee 122 11 9 16 Master Receive States 142 11 7 7 12C SCL Low duty cycle register IBSCLL I2CO 11 9 17 State 0x40 0 eee eee 142 I2COSCLL 0xE001 C014 l2C1 l2C1SCLL 11 9 18 State 0x48 2 0 004 142 OxE0015 COTA irii sire irasi nnani 122 11 9 19 State 0x50 2 0 4 143 11 7 8 Selecting the appropriate 1 C data rate and duty 11 9 20 State 0x58 0 2 eee eee 143 OVCE i ase sos eus Se e sc hen 122 11 9 24 Slave Receiver States 143 11 8 Details of I2C operating modes 123 11 9 22 State 0x60 0008 143 11 8 1 Master Transmitter mode 124 11 923 State 0x68 2 eee eee eee 143 11 8 2 Master Receiver mode 124 11 9 24 State 20x70 Rae EE wi 144 11 8 3 Slave Receiver mode sss 125 11 9 85 State Ox78 00 eee 144 11 8 4 Slave Transmitter mode 129 11 9 26 State Ox80 6 eee eee 144 11 85 Miscellaneous States 0 135 11 927 State 0x88 62 62 eee eee eee 144
317. nd the status register has not been read Table 130 SPI Data Register SOSPDR address 0xE002 0008 bit description Bit Symbol Description Reset value 7 0 DataLow SPI Bi directional data port 0x00 15 8 DataHigh If bit 2 of the SPCR is 1 and bits 11 8 are other than 1000 some 0x00 or all of these bits contain the additional transmit and receive bits When less than 16 bits are selected the more significant among these bits read as zeroes SPI Clock Counter Register SOSPCCR 0xE002 000C This register controls the frequency of a master s SCK The register indicates the number of PCLK cycles that make up an SPI clock The value of this register must always be an even number As a result bit 0 must always be 0 The value of the register must also always be greater than or equal to 8 Violations of this can result in unpredictable behavior Table 131 SPI Clock Counter Register SOSPCCR address 0xE002 000C bit description Bit Symbol Description Reset value 7 0 Counter SPIO Clock counter setting 0x00 The SPIO rate may be calculated as PCLK SPCCRO value The PCLK rate is CCLK VPB divider rate as determined by the VPBDIV register contents SPI Interrupt register SOSPINT OxE002 001C This register contains the interrupt flag for the SPIO interface Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 154 Philips Semiconductors UM1 01 20 jal Volum
318. nds are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 222 Philips Semiconductors UM10120 Volume 1 20 8 1 20 8 2 Chapter 20 Flash Memory Table 193 ISP command summary ISP Command Usage Descibed in Unlock U lt Unlock Code gt Table 194 Set Baud Rate B lt Baud Rate gt lt stop bit gt Table 195 Echo A lt setting gt Table 197 Write to RAM W lt start address gt lt number of bytes gt Table 198 Read Memory R lt address gt lt number of bytes gt Table 199 Prepare sector s for P lt start sector number gt lt end sector number gt Table 200 write operation Copy RAM to Flash C lt Flash address gt lt RAM address gt lt number of bytes gt Table 201 Go G lt address gt lt Mode gt Table 202 Erase sector s E lt start sector number gt lt end sector number gt Table 203 Blank check sector s lt start sector number gt lt end sec
319. ned to run from this Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 216 Philips Semiconductors UM1 01 20 I3 Volume 1 Chapter 20 Flash Memory memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 64 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 The reset vector contains a jump instruction to the entry point of the flash boot loader software 2 0 GB 12 kB BOOT BLOCK Ox7FFF FFFF RE MAPPED FROM TOP OF FLASH MEMORY 2 0 GB 12kB BOOT BLOCK INTERRUPT VECTORS Ox7FFF D000 0x0007 FFFF 12 kB BOOT BLOCK RE MAPPED TO HIGHER ADDRESS RANGE 0x0007 D000 ACTIVE INTERRUPT VECTORS 0 0 GB FROM THE BOOT BLOCK 0x0000 0000 Note Memory regions are not drawn to scale Fig 55 Map of lower memory after reset 20 4 2 Criterion for valid user code Criterion for valid user code The reserved ARM interrupt vector location 0x0000 0014 should contain the 2 s complement of the check sum of the remaining interrupt vectors This causes the checksum of all of the vectors together to be 0 The boot loader code disables the overlaying of the interrupt vectors from the boot block then checksums the interrupt vectors in se
320. nly when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the microcontroller Assuming that an external crystal is used in the crystal oscillator subsystem after power on the RESET pin should be asserted for 10 ms For all subsequent resets when crystal oscillator is already running and stable signal is on the X1 pin the RESET pin needs to be asserted for 300 ns only When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the Boot Block At that point all of the processor and peripheral registers have been initialized to predetermined values External and internal Resets have some small differences An external Reset causes the value of certain pins to be latched to configure the part External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins so those latches are not reloaded during an internal Reset Pins that are examined during an external Reset for various purposes are P1 20 TRACESYNC P1 26 RTCK see chapters Pin Configuration on page 64 and Pin Connect Block on page 73 Pin P0 14 see Flash Memory System and Programming chapter on page 216 is examined by on chip bootloader when this code is executed after every Reset It is possible for a chip Reset to occur during a Flash programming or erase operation The Flash memory will interrupt the ongoing operati
321. no cc ro dev fo eA cod 228 20 4 6 ISP data format s n 218 20 8 11 Read Part Identification number 228 20 4 7 ISP flow control llle esses 218 20 8 12 Read Boot code version number 228 20 4 8 ISP command SOOM es pansa danad pa ae 219 20 8 13 Compare lt address1 gt lt address2 gt 20 4 9 Interrupts during ISP 0 219 lt no of bytes gt 229 20 4 0 Interrupts during IAP 0 218 20 8 14 ISP Return codes essere 229 20 4 11 RAM used by ISP command handler 219 20 9 IAP Commands natn as 230 20 4 12 RAM used by IAP command handler 2 er do omma MO aa 2s 20 4 13 RAM used by RealMonitor 219 SA repare sector s for write operation 20 4 14 Boot process flowchart 220 A onc protease ance rt eremecin a AUS E Hininga 220 2094 Blankcheck sectors sess 234 20 6 Flash content protection mechanism 221 20 9 5 Read Part Identification number 234 20 7 Code Read Protection CRP 222 20 9 6 Read Boot code version number 234 20 8 ISPcommands 222 20 9 7 Compare address1 lt address2 gt 20 8 1 Unlock unlock code 223 no of bytes sisse eee 235 20 8 2 Set Baud Rate baud rate stop bit 223 20 9 8 Reinvoke ISP 000 0 eee eee 235 20 83 Echo lt setting gt 0000 224 20 9 9 IAP Status codes 23
322. not be used 0011 4 bit transfer 0100 5bittransfer 0101 6 bit transfer 0110 7 bit transfer 0111 8 bit transfer 1000 9Qbit transfer 1001 10 bit transfer 1010 11 bit transfer 1011 12 bit transfer 1100 13 bit transfer 1101 14 bit transfer 1110 15 bit transfer 1111 16 bit transfer 5 4 FRF Frame Format 00 00 SPI 01 SSI 10 Microwire 11 This combinationion is not supported and should not be used Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 165 Philips Semiconductors UM1 01 20 ja Volume 1 13 4 2 Chapter 13 SSP Table 135 SSP Control Register 0 SSPCRO address 0xE006 8000 bit description Bit Symbol Value Description Reset value 6 CPOL Clock Out Polarity This bit is only used in SPI mode 0 SSP controller captures serial data on the first clock transition 0 of the frame that is the transition away from the inter frame state of the clock line 1 SSP controller captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock line 7 CPHA Clock Out Phase This bit is only used in SPI mode 0 0 SSP controller maintains the bus clock low between frames SSP controller maintains the bus clock high between frames 15 8 SCR Serial Clock Rate The number of prescaler output clocks per 0x00 bit on the bus minus one Given that CPSDVR is the prescale
323. nsmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released The LPC2131 2 4 6 8 I C interfaces are byte oriented and have four operating modes master transmitter mode master receiver mode slave transmitter mode and slave receiver mode The I C interfaces complie with entire I C specification supporting the ability to turn power off to the LPC2131 2 4 6 8 without causing a problem with other devices on the same C bus see The I C bus specification description under the heading Fast Mode and notes for the table titled Characteristics of the SDA and SCL I O stages Koninklijke Philips Electronics N V 2005 All rights reserved
324. ntrol 2 Holds the include exclude regions WO 000 1110 ViewData Control 3 Holds the include exclude regions WO 000 1111 Address Comparator 1 to 16 Holds the address of the comparison WO 001 xxxx Address Access Type 1 to 16 Holds the type of access and the size WO 010 xxxx Reserved 000 xxxx Reserved 100 xxxx Initial Counter Value 1 to 4 Holds the initial value of the counter WO 101 00xx Counter Enable 1 to 4 Holds the counter clock enable control and WO 101 01xx event Counter reload 1 to 4 Holds the counter reload event WO 101 10xx Counter Value 1 to 4 Holds the current counter value RO 101 11xx Sequencer State and Control Holds the next state triggering events 110 00xx External Output 1 to 4 Holds the controlling events for each output WO 110 10xx Reserved 110 11xx Reserved 111 Oxxx Reserved 111 1xxx Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 242 Philips Semiconductors UM10120 ja Volume 1 Chapter 22 Embedded Trace 22 7 Block diagram The block diagram of the ETM debug environment is shown below in Figure 59 APPLICATION PCB CONNECTOR TRACE PORT ANALYZER TRIGGER PERIPHERAL PERIPHERAL running JTAG deb icd INTERFACE UNIT EMBEDDEDICE LAN Fig 59 ETM debug environment block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 243 Semicon
325. ntroller Table 138 SSP Status Register SSPDR address 0xE006 800C bit description Bit Symbol Description Reset value 0 TFE Transmit FIFO Empty This bit is 1 is the Transmit FIFO is empty 1 0 if not 1 TNF Transmit FIFO Not Full This bit is O if the Tx FIFO is full 1 if not 1 2 RNE Receive FIFO Not Empty This bit is 0 if the Receive FIFO is 0 empty 1 if not 3 RFF Receive FIFO Full This bit is 1 if the Receive FIFO is full 0 if 0 not 4 BSY Busy This bit is 0 if the SSP controller is idle or 1 if it is 0 currently sending receiving a frame and or the Tx FIFO is not empty 7 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined SSP Clock Prescale Register SSPCPSR 0xE006 8010 This register controls the factor by which the Prescaler divides the VPB clock PCLK to yield the prescaler clock that is in turn divided by the SCR factor in SSPCRO to determine the bit clock Table 139 SSP Clock Prescale Register SSPCPSR address 0xE006 8010 bit description Bit Symbol Description Reset value 7 0 CPSDVSR This even value between 2 and 254 by which PCLK is divided 0 to yield the prescaler output clock Bit 0 always reads as O Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 167 Philips Semiconductors UM1 01 20 ia Volume 1 13 4 6 13 4 7 Chapter 13
326. ny transition on this bit will automatically clear the UART1 FIFOs 1 RX FIFO Reset 0 No impact on either of UART1 FIFOs 0 1 Writing a logic 1 to UTFCR 1 will clear all bytes in UART1 Rx FIFO and reset the pointer logic This bit is self clearing 2 TX FIFO Reset 0 No impact on either of UART1 FIFOs 0 1 Writing a logic 1 to U1FCR 2 will clear all bytes in UART1 TX FIFO and reset the pointer logic This bit is self clearing 5 3 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 6 RX Trigger Level These two bits determine how many receiver UART1 FIFO 0 characters must be written before an interrupt is activated 00 trigger level 0 1 character or 0x01 01 trigger level 1 4 characters or 0x04 10 trigger level 2 8 characters or 0x08 11 trigger level 3 14 characters or OxOE 10 3 8 UART1 Line Control Register U1LCR 0xE001 000C The U1LCR determines the format of the data character that is to be transmitted or received Table 98 UART1 Line Control Register U1LCR address 0xE001 000C bit description Bit Symbol Value Description Reset value 1 0 Word Length 00 5 bit character length 0 Select 01 6 bit character length 10 7 bit character length 11 8 bit character length 2 Stop Bit Select 0 1 stop bit 0 1 2 stop bits 1 5 if U1LCR 1 0 00 3 Parity Enable 0 Disable parity
327. observable and controllable through the bus interface PWMMCR PWM Match Control Register The PWMMCR is used to control if an R W 0 OxE001 4014 interrupt is generated and if the PWMTC is reset when a Match occurs PWMMRO PWM Match Register 0 PWMMRO can be enabled through PWMMCR to R W 0 OxE001 4018 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMRO and the PWMTC sets all PWM outputs that are in single edge mode and sets PWM1 if it is in double edge mode PWMMR1 PWM Match Register 1 PWMMR 1 can be enabled through PNMMCR to R W 0 OxE001 401C reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMR 1 and the PWMTC clears PWM1 in either single edge mode or double edge mode and sets PWMe if it is in double edge mode PWMMR2 PWM Match Register 2 PWMMR2 can be enabled through PNMMCR to R W 0 OxE001 4020 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMR2 and the PWMTC clears PWMe in either single edge mode or double edge mode and sets PWMS if it is in double edge mode PWMMR3 PWM Match Register 3 PWMMR3 can be enabled through PNMMCR to R W 0 OxE001 4024 reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between
328. of its own the application can install the RealMonitor low level exception handlers directly into the vector table of the processor Although the irq handler must get the address of the Vectored Interrupt Controller The easiest way to do this is to write a branch instruction address into the vector table where the target of the branch is the start address of the relevant RealMonitor exception handler Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 248 Philips Semiconductors UM10120 ja Volume 1 23 4 11 23 4 12 Chapier 23 RealMonitor Real monitor supplied exception vector handlers RM_UNDEF_HANDLER RM_PREFETCHABORT_HANDLER RM_DATAABORT_HANDLER RM_IRQHANDLER ABORT Sharing IRQs between ReaMonitor and User IRQ handler RM IRQHANDLER2 APP IRQDISPATCH APP IRQHANDLERe Fig 62 Exception handlers RMTarget initialization While the processor is in a privileged mode and IRQs are disabled user must include a line of code within the start up sequence of application to call rm_init_entry Code example The following example shows how to setup stack VIC initialize RealMonitor and share non vectored interrupts MPORT rm_init_entry PORT rm_prefetchabort_handler PORT rm_dataabort_handler PORT rm_irqhandler2 PORT rm_undef_handler PORT User_Entry Entry point of user application DE32
329. ol UART1 UARTO TIMER TIMERO ARMCore ARMCore0 WDT Access WO WO WO WO WO WO WO WO Table 37 Software Interrupt Clear register VICSoftIintClear address OxFFFF F01C bit description Bit Symbol Value Description Reset value 31 0 See 0 Writing a 0 leaves the corresponding bit in VICSoftlnt unchanged 0 VICSoftintClea 1 r bit allocation table Writing a 1 clears the corresponding bit in the Software Interrupt register thus releasing the forcing of this request Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 51 Philips Semiconductors UM10120 Volume 1 5 4 3 Raw Interrupt status register VICRawintr OxFFFF F008 This is a read only register This register reads out the state of the 32 interrupt requests and software interrupts regardless of enabling or classification Table 38 Raw Interrupt status register VICRawlnir address OxFFFF F008 bit allocation Reset value 0x0000 0000 Chapter 5 VIC Bit 31 30 29 28 27 26 25 24 Symbol s i Access RO RO RO RO RO RO RO RO Bit 23 22 21 20 19 18 17 16 Symbol AD1 BOD I2C1 ADO EINT3 EINT2 Access RO RO RO RO RO RO RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPH SSP SPIO 12C0 PWMO Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TI
330. olled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occurs prior to the falling edge and negative going PWM pulses when the falling edge occurs prior to the rising edge Figure 49 shows the block diagram of the PWM The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 182 Philips Semiconductors UM10120 B Volume 1 Chapter 15 PWM MATCH REGISTER 0 SHADOW REGISTER 0 LOAD ENABLE MATCH REGISTER 1 Me REGISTER 1 LOAD ENABLE MATCH REGISTER 2 l E eee REGISTER 2 lo ENABLE MATCH REGISTER 3 E E mo ENABLE e 5HADOW REGISTER 4 dr LOAD ENABLE Me Erapow REGISTER 5 dir LOAD ENABLE ISHADOW REGISTER 6 LOAD ENABLE MATCH REGISTER 5 MATCH REGISTER 4 MATCH REGISTER 6 Match 0 PWM1 PWMENA1 R EN MATCH 0 PWMSEL2 S l iun LATCH ENABLE REGISTER CLEAR PT vux S Q MATCH CONTROL REGISTER Ld PWMENA2 R EN Interrupt Register n lal PWMSEL3 PWM3 CONTROL rw s R EN PWMSEL4 PWM4 Hs s PWMENA4 M 6 0 INTERRUPT STOP ON MATCH RESET ON MATCH PWMSEL5 hw z a PWM5 mE PWMENA5 R EN PWM6 S Q PWMENA6 S PRESCALE COUNTER R EN PWMENA1 6 PWMSEL2 6 MAXVAL RESET PRESCALE REGIS
331. on PWM1 Output Output from PWM channel 1 PWM2 Output Output from PWM channel 2 PWM3 Output Output from PWM channel 3 PWM4 Output Output from PWM channel 4 PWM5 Output Output from PWM channel 5 PWM6 Output Output from PWM channel 6 15 4 Register description The PWM function adds new registers and registers bits as shown in Table 155 below Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 185 Philips Semiconductors UM1 01 20 Bb Volume 1 Chapter 15 PWM Table 155 Pulse Width Modulator PWM register map Name Description Access Reset Address valuel PWMIR PWM Interrupt Register The PWMIR can be written to clear interrupts R W 0 OxE001 4000 The PWMIR can be read to identify which of the possible interrupt sources are pending PWMTCR PWM Timer Control Register The PWMTCR is used to control the Timer R W 0 OxE001 4004 Counter functions The Timer Counter can be disabled or reset through the PWMTCR PWMTC PWM Timer Counter The 32 bit TC is incremented every PWMPR 1 R W 0 OxE001 4008 cycles of PCLK The PWMTC is controlled through the PWMTCR PWMPR PWM Prescale Register The PWMTC is incremented every PWMPR 1 R W 0 OxE001 400C cycles of PCLK PWMPC PWM Prescale Counter The 32 bit PC is a counter which is incremented R W 0 OxE001 4010 to the value stored in PR When the value in PWMPR is reached the PWMTC is incremented The PWMPC is
332. on 5 2 on page 5 13 in Embedded Trace Macrocell Specification ARM IHI 0014E PIPESTAT 2 0 Output Pipe Line status The pipeline status signals provide a cycle by cycle indication of what is happening in the execution stage of the processor pipeline TRACESYNC Output Trace synchronization The trace sync signal is used to indicate the first packet of a group of trace packets and is asserted HIGH only for the first packet of any branch address TRACEPKT 3 0 Output Trace Packet The trace packet signals are used to output packaged address and data information related to the pipeline status All packets are eight bits in length A packet is output over two cycles In the first cycle Packet 3 0 is output and in the second cycle Packet 7 4 is output EXTIN O Input External Trigger Input 22 5 Reset state of multiplexed pins On the LPC2131 2 4 6 8 the ETM pin functions are multiplexed with P1 25 16 To have these pins come as a Trace port connect a weak bias resistor 4 7 KQ between the P1 20 TRACESYNC pin and Vss To have them come up as port pins do not connect a bias resistor to P1 20 TRACESYNC and ensure that any external driver connected to P1 20 TRACESYNC is either driving high or is in high impedance state during Reset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 241 Philips Semiconductors UM10120 ja Volume
333. on and hold off the completion of Reset to the CPU until internal Flash high voltages have settled Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 36 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 3 System Control Block Watchdog reset Power down COUNT 2 EINTO Wakeup EINT1 Wakeup EINT2 Wakeup EINT3 Wakeup RTC Wakeup Reset to the on chip circuitry Reset to PCON PD WAKEUP TIMER START Oscillator output F Osc VBP Read of PDBIT in PCON Fig 11 Reset block diagram including the wakeup timer 3 9 1 Reset Source Identification Register RSIR OXEO1F C180 This register contains one bit for each source of Reset Writing a 1 to any of these bits clears the corresponding read side bit to 0 The interactions among the four sources are described below Table 25 Reset Source identificator Register RSIR address OxEO1F C180 bit description Bit Symbol Description Reset value POR Assertion of the POR signal sets this bit and clears all of the other bits see text in this register But if another Reset signal e g External Reset remains asserted after the POR signal is negated then its bit is set This bit is not affected by any of the other sources of Reset EXTR Assertion of the RESET signal sets this bit Ths bit is cleared by POR see text but is not affected by WDT or BOD
334. onics N V 2005 All rights reserved User manual Rev 01 24 June 2005 164 Philips Semiconductors UM10120 ja Volume 1 Table 134 SSP register Chapter 13 SSP map Name Description SSPCRO Control Regi Access Reset value Address ster 0 Selects the serial clock R W 0x0000 OxEO006 8000 rate bus type and data size SSPCR1 Control Regi ster 1 Selects master slave R W 0x00 OxE006 8004 and other modes SSPDR Data Register Writes fill the transmit FIFO R W 0x0000 OxE006 8008 and reads empty the receive FIFO SSPSR Status Register RO 0x03 OxE006 800C SSPCPSR Clock Prescale Register R W 0x00 OxE006 8010 SSPIMSC Interrupt Mask Set and Clear Register R W 0x00 OxE006 8014 SSPRIS Raw Interrupt Status Register R W 0x04 OxE006 8018 SSPMIS Masked Interrupt Status Register RO 0x00 OxE006 801C SSPICR SSPICR Interrupt Clear Register WO NA OxE006 8020 1 Reset value relects the data stored in used bits only It does not include reserved bits content 13 4 4 SSP Control Register 0 SSPCRO 0xE006 8000 This register controls the basic operation of the SSP controller Table 135 SSP Control Register 0 SSPCRO address 0xE006 8000 bit description Bit Symbol Value Description Reset value 3 0 DSS Data Size Select This field controls the number of bits 0000 transferred in each frame Values 0000 0010 are not supported and should
335. oninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 193 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter 16 4 Register description The A D Converter registers are shown in Table 162 Table 162 ADC registers Generic Description Access Reset ADO AD1 Name valuel Address Address amp Name amp Name ADCR A D Control Register The ADCR register must be written R W 0x0000 0001 OxE003 4000 OxE006 0000 to select the operating mode before A D conversion can ADOCR AD1CR occur ADDR A D Data Register This register contains the ADC s R W undefined OxE003 4004 OxE006 0004 DONE bit and when DONE is 1 the 10 bit result of the ADODR AD1DR conversion ADGSR A D Global Start Register This address can be written in WO 0x00 OxE003 4008 the ADO address range to start conversions in both A D ADGSR converters simultaneously 1 Reset value relects the data stored in used bits only It does not include reserved bits content 16 4 1 A D Control Register ADOCR OxE003 4000 and AD1CR 0xE006 0000 Table 163 A D Control Register ADOCR address 0xE003 4000 and AD1CR address 0xE006 0000 bit description Bit Symbol Value Description Reset value 7 0 SEL Selects which of the ADO 7 0 AD1 7 0 pins is are to be sampled and converted For 0x01 ADO bit 0 selects Pin ADO 0 and bit 7 selects pin ADO 7 In software controlled mode only one of t
336. or itself memory systems and related controllers and internal buses In Power down mode the oscillator is shut down and the chip receives no internal clocks The processor state and registers peripheral registers and internal SRAM values are preserved throughout Power down mode and the logic levels of chip pins remain static The Power down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chip is suspended Power down mode reduces chip power consumption to nearly zero Entry to Power down and Idle modes must be coordinated with program execution Wakeup from Power down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost incomplete or repeated Wake up from Power down mode is discussed further in Section 3 11 Wakeup timer on page 39 A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Register description The Power Control function contains two registers as shown in Table 22 More detailed descriptions follow Table 22 Power control registers Name Description Access Reset Address valuel PCON Power Control Register This register contains R W 0x00 OxEO1F COCO control bits that enable the two reduced power operating modes of the
337. ount is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 47 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated Prescale counter Timer amer E 859 g 3g 9 pF 4 jJ Timer o D 2 reset Iterrupt Fig 46 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled ex LLP V VN NNI NI poen Timer counter 4 8 A e a a HN RN counter enable Iterrupt Fig 47 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 179 Philips Semiconductors UM10120 ja Volume 1 Chapter 14 TIMERO and TIMER1 14 7 Architecture The block diagram for TIMER COUNTERO and TIMER COUNTERT is shown in Figure 48 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTRRUPT REGISTER CONTROL iren NDS INTERRUPT ns Pa STOP ON MATCH RESET ON MATCH LOAD 3 0 CAPTURE
338. part of digital logic necessary for the digital function to be performed will be active and will disrupt proper behavior of the A D Table 64 GPIO Pin Value register 0 IOOPIN address 0xE002 8000 bit description Bit Symbol Description Reset value 31 0 POxVAL GPIO pin value bits Bit 0 in IOOPIN corresponds to PO 0 Bit 31 in IOOPIN Undefined corresponds to P0 31 Table 65 GPIO Pin Value register 1 IO1PIN address 0xE002 8010 bit description Bit Symbol Description Reset value 31 0 P1xVAL GPIO pin value bits Bit 0 in IO1PIN corresponds to P1 0 Bit31 in IO1PIN Undefined corresponds to P1 31 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 80 Philips Semiconductors UM1 01 20 ja Volume 1 8 4 2 8 4 3 8 4 4 Chapter 8 GPIO GPIO Output Set register 0 and 1 IOOSET OxE002 8004 and IO1SET 0xE002 8014 This register is used to produce a HIGH level output at the port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a HIGH level at the corresponding port pins Writing O has no effect If any pin is configured as an input or a secondary function writing to IOSET has no effect Reading the IOSET register returns the value of this register as determined by previous writes to IOSET and IOCLR or IOPIN as noted above This value does not reflect the effect of any outside world influence on the I O pins Table 66 GPIO Output Set register 0
339. pt vectors are not re mapped and reside in Flash 10 User RAM Mode Interrupt vectors are re mapped to Static RAM 11 Reserved Do not use this option Warning Improper setting of this value may result in incorrect operation of the device 7 2 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Memory mapping control usage notes The Memory Mapping Control simply selects one out of three available sources of data sets of 64 bytes each necessary for handling ARM exceptions interrupts For example whenever a Software Interrupt request is generated the ARM core will always fetch 32 bit data residing on 0x0000 0008 see Table 2 ARM exception vector locations on page 12 This means that when MEMMAPT 1 0 210 User RAM Mode a read fetch from 0x0000 0008 will provide data stored in 0x4000 0008 In case of MEMMAPT 1 0 200 Boot Loader Mode a read fetch from 0x0000 0008 will provide data available also at Ox7FFF E008 Boot Block remapped from on chip Bootloader 3 7 Phase Locked Loop PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only The input frequency is multiplied up into the CCLK with the range of 10 MHz to 60 MHz using a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 in practice the multiplier value cannot be higher than 6 on the LPC2131 2 4 6 8 due to the upper frequency
340. r 24 Supplementary information continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 261 Philips Semiconductors UM10120 Volume 1 24 5 Figures Chapter 24 Supplementary information Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 LPC2131 2 4 6 8 block diagram 7 System memory Map 202 cee eee ee 8 Peripheral memory map 05 9 AHB peripheral map 0 eee 10 VPB peripheral map llle 11 Map of lower memory is showing re mapped and re mappable areas LPC2138 with 512 kB IASI sy cancer ni ahats adores 14 Oscillator modes and models a slave mode of operation b oscillation mode of operation c external crystal model used for Cx1 x2 evaluation 18 Fosc selection algorithm 19 External interrupt logic 04 25 PLL block diagram 0c eee eee 28 Reset block diagram including the wakeup timer 37 VPB divider connections 39 Simplified block diagram of the Memory Accelerator Module MAM 20000 eee eens 43 Block diagram of the Vectore
341. rame was received when NA RxFIFO was full interrupt 1 RTIC Writing a 1 to this bit clears the Receive Timeout interrupt NA 7 2 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 169 UM10120 Chapter 14 Timer Counter TIMERO and TIMER1 Rev 01 24 June 2005 User manual E Semiconductors Timer CounterO and Timer Counter1 are functionally identical except for the peripheral base address 14 1 Features e A 32 bit Timer Counter with a programmable 32 bit Prescaler Counter or Timer operation e Up to four 32 bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Setlow on match Set high on match Toggle on match Do nothing on match 14 2 Applications Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer 14 3 Descr
342. re 32 4 1 Multiplexers that select the requested word from the 128 bit line Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data which are captured in the Data latch This speeds up sequential Data operations but has little or no effect on random accesses Flash programming Issues Since the Flash memory does not allow accesses during programming and erase operations it is necessary for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy This is accomplished by asserting the ARM7TDMI S local bus signal CLKEN Under some conditions this delay could result in a Watchdog time out The user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the Flash memory In order to preclude the possibility of stale data being read from the Flash memory the LPC2131 2 4 6 8 MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed 4 4 MAM operating modes Three modes of operation are defined for the MAM trading off performance for ease of predictability Mode 0 MAM off All memory requests result in a Flash read operation see note 2 below There are no instruction prefetc
343. red when a one is written to bit one of the Interrupt Location Register ILR 1 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 206 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 18 RTC Table 180 Alarm registers Name Size Description Access Address ALSEC 6 Alarm value for Seconds R W OxE002 4060 ALMIN 6 Alarm value for Minutes R W OxE002 4064 ALHOUR 5 Alarm value for Hours R W OxE002 4068 ALDOM 5 Alarm value for Day of Month R W OxE002 406C ALDOW 3 Alarm value for Day of Week R W OxEO002 4070 ALDOY 9 Alarm value for Day of Year R W OxEO02 4074 ALMON 4 Alarm value for Months R W OxE002 4078 ALYEAR 12 Alarm value for Years R W OxE002 407C 18 5 RTC usage notes If the RTC is used Vgar must be connected to either pin V3 or an independent power supply external battery Otherwise Vgar should be tied to the ground Vss No provision is made in the LPC2131 2 4 6 8 to retain RTC status upon the Vgar power loss or to maintain time incrementation if the clock source is lost interrupted or altered Since the RTC operates using one of two available clocks the VPB clock PCLK or the 32 kHz signal coming from the RTCX1 2pins any interruption of the selected clock will cause the time to drift away from the time value it would have provided otherwise The variance could be to actual clock time if the RTC was initialized to that
344. reset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 37 Philips Semiconductors UM1 01 20 Volume 1 Chapter 3 System Control Block Table 25 Reset Source identificator Register RSIR address 0xE01F C180 bit description Bit Symbol Description Reset value 2 WDTR This bitis set when the Watchdog Timer times out and the WDTRESET see text bit in the Watchdog Mode Register is 1 It is cleared by any of the other sources of Reset 3 BODR This bit is set when the 3 3 V power reaches a level below 2 6 V Ifthe seet text Vpp voltage dips from 3 3 V to 2 5 V and backs up the BODR bit will be set to 1 Also if the Vpp voltage rises continuously from below 1 V to a level above 2 6 V the BODR will be set to 1 too This bit is not affected by External Reset nor Watchdog Reset Note only in case a reset occurs and the POR 0 the BODR bit indicates if the Vpp voltage was below 2 6 V or not TA Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 3 10 VPB divider 3 10 1 3 10 2 The VPB Divider determines the relationship between the processor clock CCLK and the clock used by peripheral devices PCLK The VPB Divider serves two purposes The first is to provides peripherals with desired PCLK via VPB bus so that they can operate at the speed chosen for the ARM processor In order
345. ress Value 32 Holds watchpoint 1 address value 10000 Watchpoint 1 Address Mask 32 Holds watchpoint 1 address mask 10001 Watchpoint 1 Data Value 32 Holds watchpoint 1 data value 10010 Watchpoint 1 Data Mask 32 Holds watchpoint 1 data mask 10011 Watchpoint 1 Control Value 9 Holds watchpoint 1 control value 10100 Watchpoint 1 Control Mask 8 Holds watchpoint 1 control mask 10101 21 7 Block diagram The block diagram of the debug environment is shown below in Figure 58 JTAG PORT Serial parallel EMBEDDEDICE interface INTERFACE EMBEDDED PROTOCOL ICE a CONVERTER Host running ARM7TDMI S debugger TARGET BOARD Fig 58 EmbeddedICE debug environment block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 239 Semiconductors 22 1 Features UM10120 Chapter 22 Embedded Trace Macrocell ETM Rev 01 24 June 2005 User manual iT Closely track the instructions that the ARM core is executing e External trigger input 10 pin interface All registers are programmed through JTAG interface Does not consume power when trace is not being used THUMB instruction set support 22 2 Applications As the microcontroller has significant amounts of on chip memories it is not possible to determine how the processor core is operating simply by observing the external pins The ETM provides real time trace capabilit
346. ressed SLV mode no recognition of own SLA or General call address No STDAT action 0 or Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O logic 1 No STDAT action 1 or Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free No STDAT action 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR O0 logic 1 A START condition will be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 133 Philips Semiconductors UM10120 fal Volume 1 Table 123 Slave Transmitter mode Chapter 11 I C interfaces Status Status of the I2C bus Application software response Next action taken by I C hardware pode im mieie To From I2DAT To I2CON I2CSTAT STA STO SI AA 0xA8 Own SLA R hasbeen Load data byteor X 0 0 0 Last data byte will be transmitted and received ACK has ACK bit will be received been returned Load data byte X 0 0 1 Data byte will be transmitted ACK will be received 0xBO Arbitration lost in Load data byteor X 0 0 0 Last data byte will be transmitted and SLA R W as master ACK bit will be received Own SLA R has been Load data byte x 5
347. rrupt flag for capture channel 2 event 0 7 CR3 Interrupt Interrupt flag for capture channel 3 event 0 14 5 2 Timer Control Register TCR TIMERO TOTCR 0xE000 4004 and TIMER1 T1TCR 0xE000 8004 The Timer Control Register TCR is used to control the operation of the Timer Counter Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 173 Philips Semiconductors UM1 01 20 Volume 1 14 5 3 Chapter 14 TIMERO and TIMER1 Table 147 Timer Control Register TCR TIMERO TOTCR address 0xE000 4004 and TIMER1 T1TCR address 0xE000 8004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are 0 enabled for counting When zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 7 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Count Control Register CTCR TIMERO TOCTCR 0xE000 4070 and TIMER1 T1TCR 0xE000 8070 The Count Control Register CTCR is used to select between Timer and Counter mode and in Counter mode to select the pin and edge s for counting When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2
348. rrupt has just been taken while the bit in the SPSR is set In the example above the F bit will also be set in both the CPSR and SPSR This means that FIQs are disabled upon entry to the IRQ service routine and will remain so until explicitly re enabled FIQs will not be reenabled automatically by the IRQ return sequence Although the example shows both IRQ and FIQ interrupts being disabled similar behavior occurs when only one of the two interrupt types is being disabled The fact that the core processes the IRQ after completion of the MSR instruction which disables IRQs does not normally cause a problem since an interrupt arriving just one cycle earlier would be expected to be taken When the interrupt routine returns with an instruction like SUBS pc lr 4 the SPSR IRQ is restored to the CPSR The CPSR will now have the bit and F bit set and therefore execution will continue with all interrupts disabled However this can cause problems in the following cases Problem 1 A particular routine maybe called as an IRQ handler or as a regular subroutine In the latter case the system guarantees that IRQs would have been disabled prior to the routine being called The routine exploits this restriction to determine how it was called by examining the bit of the SPSR and returns using the appropriate instruction If the routine is entered due to an IRQ being received during execution of the MSR instruction which disables IRQs then the I
349. rrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UARTO THR FIFO has held two or more characters at one time and currently the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occurs and the THRE is the highest interrupt UOIIR 3 1 001 UARTO FIFO Control Register UOFCR 0xE000 C008 The UOFCR controls the operation of the UARTO Rx and TX FIFOs Table 82 UARTO FIFO Control Register UOFCR address 0xE000 C008 bit description Bit Symbol Value Description Reset value 0 FIFO Enable 0 UARTO FIFOs are disabled Must not be used in the 0 application 1 Active high enable for both UARTO Rx and TX FIFOs and UOFCR 7 1 access This bit must be set for proper UARTO operation Any transition on this bit will automatically clear the UARTO FIFOs 1 RX FIFO 0 No impact on either of UARTO FIFOs 0 Reset 4 Writing a logic 1 to UOFCR 1 will clear all bytes in UARTO Rx FIFO and reset the pointer logic This bit is self clearing 2 TX FIFO 0 No impact on either of UARTO FIFOs 0 Reset 1 Writing a logic 1 to UOFCR 2 will clear all bytes i
350. rved bits The NA value read from a reserved bit is not defined Clock Tick Counter Register CTCR 0xE002 4004 The Clock Tick Counter is read only It can be reset to zero through the Clock Control Register CCR The CTC consists of the bits of the clock divider counter Table 171 Clock Tick Counter Register CTCR address 0xE002 4004 bit description Bit Symbol Description Reset value 14 0 Clock Tick Prior to the Seconds counter the CTC counts 32 768 clocks per NA Counter second Due to the RTC Prescaler these 32 768 time increments may not all be of the same duration Refer to the Section 18 6 Reference clock divider prescaler on page 207 for details 15 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Clock Control Register CCR 0xE002 4008 The clock register is a 5 bit register that controls the operation of the clock divide circuit Each bit of the clock register is described in Table 172 Table 172 Clock Control Register CCR address 0xE002 4008 bit description Bit Symbol Description Reset value 0 CLKEN Clock Enable When this bit is a one the time counters are enabled NA When it is a zero they are disabled so that they may be initialized 1 CTCRST CTC Reset When one the elements in the Clock Tick Counter are NA reset The elements remain reset until CCR 1 is changed to zero 3 2 CTTEST Test Enable These bit
351. s 12 words while processing an undefined instruction exception SVC mode RealMonitor makes no use of this stack Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 247 Philips Semiconductors UM1 01 20 ja Volume 1 23 4 5 23 4 6 23 4 7 23 4 8 23 4 9 23 4 10 Chapter 23 RealMonitor Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler User System mode RealMonitor makes no use of this stack FIQ mode RealMonitor makes no use of this stack Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and user application RealMonitor exception handling To function properly RealMonitor must be able to intercept certain interrupts and exceptions Figure 62 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the exception sharing they must provide function such as app_IRQDispatch Depending on the nature of the exception this handler can either e Pass control to the RealMonitor processing routine such as rm irghandler2 e Claim the exception for the application itself such as app IRQHandler In a simple case where an application has no exception handlers
352. s reserved User manual Rev 01 24 June 2005 111 Philips Semiconductors UM1 01 20 ie Volume 1 Chapter 11 I C interfaces When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible status codes are 0x68 0x78 or OxBO For details refer to Table 121 0 Write 4 Read Data Transferred n Bytes Acknowledge A Acknowledge SDA low O From Master to Slave A Not acknowledge SDA high From Slave to Master S START Condition P STOP Condition Fig 22 Format of Master Receive mode After a repeated START condition IC may switch to the master transmitter mode STATE SEAL To Data Transferred n Bytes Acknowledge A Acknowledge SDA low L From Master to Slave A Not acknowledge SDA high L From Slave to Master S START Condition P STOP Condition SLA Slave Address Fig 23 A Master Receiver switches to Master Transmitter after sending Repeated START 11 5 3 Slave Receiver mode In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode user write the Slave Address register IZADR and write the 12C Control Set register IZCONSET as shown in Table 106 Table 106 I2COC
353. s should always be zero during normal NA operation 4 CLKSRC lfthis bit is 0 the Clock Tick Counter takes its clock from the Prescaler NA as on earlier devices in the Philips Embedded ARM family If this bit is 1 the CTC takes its clock from the 32 kHz oscillator that s connected to the RTCX1 and RTCX2 pins see Section 18 7 RTC external 32 kHz oscillator component selection for hardware details 7 5 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Counter Increment Interrupt Register CIIR OXE002 400C The Counter Increment Interrupt Register CIIR gives the ability to generate an interrupt every time a counter is incremented This interrupt remains valid until cleared by writing a one to bit zero of the Interrupt Location Register ILR 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 203 Philips Semiconductors UM1 01 20 ia Volume 1 18 4 7 18 4 8 18 4 9 Chapter 18 RTC Table 173 Counter Increment Interrupt Register CIIR address 0xE002 400C bit description Bit Symbol Description Reset value 0 IMSEC When 1 an increment of the Second value generates an interrupt NA 1 IMMIN When 1 an increment of the Minute value generates an interrupt NA 2 IMHOUR When 1 an increment of the Hour value generates an interrupt NA 3 IM
354. sectors 2 and 3 20 8 11 Read Part Identification number Table 205 ISP Read Part Identification number command Command J Input None Return Code CMD SUCCESS followed by part identification number in ASCII see Table 206 Description This command is used to read the part identification number Table 206 LPC213x Part Identification numbers Device ASCII dec coding Hex coding LPC2131 196353 0x0002 FF01 LPC2132 196369 0x0002 FF11 LPC2134 196370 0x0002 FF12 LPC2136 196387 0x0002 FF23 LPC2138 196389 0x0002 FF25 20 8 12 Read Boot code version number Table 207 ISP Read Boot code version number command Command K Input None Return Code CMD SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byteO Minor gt Description This command is used to read the boot code version number Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 228 Philips Semiconductors UM10120 ia Volume 1 Chapter 20 Flash Memory 20 8 13 Compare lt address1 gt lt address2 gt lt no of bytes gt 20 8 14 Table 208 ISP Compare command Command Input Address1 DST Starting Flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting Flash or RAM address of data bytes to be compared This ad
355. ses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_SEMIHOSTING FALSE This option enables or disables support for SWI semi hosting Semi hosting provides code running on an ARM target use of facilities on a host computer that is running an ARM debugger Examples of such facilities include the keyboard input screen output and disk I O RM_OPT_SAVE_FIQ_REGISTERS TRUE This option determines whether the FIQ mode registers are saved into the registers block when RealMonitor stops RM_OPT_READBYTES TRUE Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 252 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 23 RealMonitor RM_OPT_WRITEBYTES TRUE RM_OPT_READHALFWORDS TRUE RM_OPT_WRITEHALFWORDS TRUE RM_OPT_READWORDS TRUE RM OPT WRITEWORDS TRUE Enables Disables support for 8 16 32 bit read write RM OPT EXECUTECODE FALSE Enables Disables support for executing code from execute code buffer The code must be downloaded first RM OPT GETPC TRUE This option enables or disables support for the RealMonitor GetPC packet Useful in code profiling when real monitor is used in interrupt mode RM EXECUTECODE SIZEZNA execute code buffer size Also refer to RM OPT EXECUTECODE option RM OPT GATHER STATISTICS FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor RM DEBUG FALSE This option enables or
356. sing edges of the SCK signal In the case of a single word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 160 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 13 SSP 13 3 6 SPI format with CPOL 1 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 1 CPHA 0 are shown in Figure 41 4 to 16 bits gt a Motorola SPI frame format single transfer with CPOL 1 and CPHA 0 4 to 16 bits gt 4 to 16 bits b Motorola SPI frame format continuous transfer with CPOL 1 and CPHA 0 Fig 41 SPI frame format with CPOL 1 and CPHA 0 a single and b continuous transfer In this configuration during idle periods The CLK signal is forced HIGH SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW which causes slave data to be immediately trans
357. soon as the Flash has completed the previous access The prefetched line is latched by the Flash module but the MAM does not capture the line in its prefetch buffer until the ARM core presents the address from which the prefetch has been made If the core presents a different address from the one from which the prefetch has been made the prefetched line is discarded The Prefetch and Branch Trail buffers each include four 32 bit ARM instructions or eight 16 bit Thumb instructions During sequential code execution typically the Prefetch Buffer contains the current instruction and the entire Flash line that contains it The MAM uses the LPROT O0 line to differentiate between instruction and data accesses Code and data accesses use separate 128 bit buffers 3 of every 4 sequential 32 bit code or data accesses hit in the buffer without requiring a Flash access 7 of 8 sequential 16 bit accesses 15 of every 16 sequential byte accesses The fourth eighth 16th sequential data access must access Flash aborting any prefetch in progress When a Flash data access is concluded any prefetch that had been in progress is re initiated Timing of Flash read operations is programmable and is described later in this section In this manner there is no code fetch penalty for sequential instruction execution when the CPU clock period is greater than or equal to one fourth of the Flash access time The average amount of time spent doing program branches is r
358. ss OxFFFF F008 bit allocation Raw Interrupt status register VICRawintr address OxFFFF F008 bit description 52 Interrupt Enable register VICIntEnable address OxFFFF F010 bit allocation Interrupt Enable register VICIntEnable address OxFFFF F010 bit description 53 Software Interrupt Clear register VICIntEnClear address OxFFFF F014 bit allocation Software Interrupt Clear register VICIntEnClear address OxFFFF F014 bit description 53 Interrupt Select register VICIntSelect address OxFFFF FOOC bit allocation Interrupt Select register VICIntSelect address OxFFFF FOOC bit description 54 IRQ Status register VICIRQStatus address OxFFFF F000 bit allocation IRQ Status register VICIRQStatus address OxFFFF F000 bit description 54 FIQ Status register VICFIQStatus address OxFFFF F004 bit allocation 55 FIQ Status register VICFIQStatus address OxFFFF F004 bit description 55 Vector Control registers 0 15 VICvectCntl0 15 OxFFFF F200 23C bit description 55 Vector Address registers VIC VectAddr0 15 addresses OxFFFF F100 13C bit description 56 Default Vector Address register VICDefVectAddr address OxFFFF F034 bit description 56 Vector Address register VICVectAddr address OxFFFF F030 bit description 56 Protection Enable register VICProtection address OxFFFF F020 bit description
359. ss comparators 1 Data Comparators 0 Data tracing is not supported Memory Map Decoders 4 Counters 1 Sequencer Present No Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 240 Philips Semiconductors UM10120 ja Volume 1 Chapter 22 Embedded Trace Table 222 ETM configuration Resource number type Small External Inputs 2 External Outputs 0 FIFOFULL Present Yes Not wired FIFO depth 10 bytes Trace Packet Width 4 8 1 For details refer to ARM documentation Embedded Trace Macrocell Specification ARM IHI 0014E 22 4 Pin description Table 223 ETM pin description Pin Name TRACECLK Type Output Description Trace Clock The trace clock signal provides the clock for the trace port PIPESTAT 2 0 TRACESYNC and TRACEPKT 3 0 signals are referenced to the rising edge of the trace clock This clock is not generated by the ETM block It is to be derived from the system clock The clock should be balanced to provide sufficient hold time for the trace data signals Half rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page 3 27 in ETM7 Technical Reference Manual ARM DDI 0158B for example circuits that implements both half rateclocking and shifting of the trace data with respect to the clock For TRACECLK timings refer to secti
360. ssed slave receiver mode The AA bit can be cleared by writing 1 to the AAC bit in the IICONCLR register When AA is 0 a not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 12C is in the master receiver mode 2 A data byte has been received while the 12C is in the addressed slave receiver mode I C Control Clear register IZCONCLR I2C0 I2COCONCLR 0xE001 C018 and I2C1 I2C1CONCLR 0xE005 C018 The I2CONCLR registers control clearing of bits in the I2CON register that controls operation of the 12C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be cleared Writing a zero has no effect Table 109 I2C Control Set register IZCONCLR I2CO I2COCONCLR address 0xE001 C018 and I2C1 I2C1CONCLR address 0xE005 C018 bit description Bit Symbol Description Reset value 1 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined AAC Assert acknowledge Clear bit SIC 12C interrupt Clear bit 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 120 Philips Semiconductors UM1 01 20 ie Volume 1 11 7
361. ster VICIntEnClear address OxFFFF F014 bit description Bit Symbol Value Description Reset value 31 0 See 0 Writing a 0 leaves the corresponding bit in VICIntEnable 0 VICIntEnClear unchanged bit allocation Writing a 1 clears the corresponding bit in the Interrupt Enable table register thus disabling interrupts for this request 5 4 6 Interrupt Select register VICIntSelect OXFFFF F00C This is a read write accessible register This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ Table 44 Interrupt Select register VICintSelect address 0xFFFF F00C bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol a Access R W R W R W R W R W R W R W R W Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 53 Philips Semiconductors UM10120 I3 Volume 1 Chapter 5 VIC Bit 23 22 21 20 19 18 17 16 Symbol AD1 BOD I2C1 ADO EINT3 EINT2 Access R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPI SSP SPIO I2C0 PWMO Access R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCore1 ARMCored E WDT Access R W R W R W R W R W R W R W R W Table 45 Interrupt Select register VICIntSelect address OxFFFF F00C bit description Bit Sy
362. ster receiver modes A special case occurs if another master simultaneously generates a repeated START condition see Figure 33 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the 12C hardware detects a repeated START condition on the I C bus before generating a repeated START condition itself it will release the bus and no interrupt request is generated If another master frees the bus by generating a STOP condition the 12C block will transmit a normal START condition state 0x08 and a retry of the total serial data transfer can commence 11 8 10 Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes see Figure 27 Loss of arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78 and OxBO see Figure 29 and Figure 30 If the STA flag in I2CON is set by the routines which service these states then if the bus is free again a START condition state 0x08 is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 11 8 11 Forced access to the I C bus In some applications it may be possible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL Koninklijke Philips Electronics N V 2005 All rights reserved User manua
363. ster description The Pin Control Module contains 2 registers as shown in Table 57 below Table 57 Pin connect block register map Name Description Access Reset value Address PINSELO Pin function select Read Write 0x0000 0000 OxE002 C000 register 0 PINSEL1 Pin function select Read Write 0x0000 0000 OxE002 C004 register 1 PINSEL2 Pin function select Read Write See Table 60 OxE002 C014 register 2 1 Reset value relects the data stored in used bits only It does not include reserved bits content Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 73 Philips Semiconductors UM10120 ja Volume 1 Chapter 7 Pin Connect Block 7 4 4 Pin Function Select Register 0 PINSELO 0xE002 C000 The PINSELO register controls the functions of the pins as per the settings listed in Table 61 The direction control bit in the IOODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Table 58 Pin function Select register 0 PINSELO address 0xE002 C000 bit description Bit Symbol Value Function Reset value 1 0 P0 0 00 GPIO Port 0 0 0 01 TXD UARTO 10 PWM1 11 Reserved 3 2 PO 1 00 GPIO Port 0 1 0 01 RxD UARTO 10 PWM3 11 EINTO 5 4 P0 2 00 GPIO Port 0 2 0 01 SCLO
364. t l AD1 5 A D converter 1 input 5 This analog input is always connected to its pin Available in LPC2134 6 8 only Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 68 Philips Semiconductors UM10120 E Volume 1 Table 56 Pin description continued Chapter 6 Pin Configuration Symbol Pin Type Description PO 6 EINTO 46 2 yo P0 16 General purpose digital input output pin MATO 2 CAPO 2 EINTO External interrupt 0 input O MATO 2 Match output for Timer 0 channel 2 l CAPO 2 Capture input for Timer 0 channel 2 PO 17 CAP1 2 4711 yo P0 17 General purpose digital input output pin SCK1 MAT1 2 l CAP1 2 Capture input for Timer 1 channel 2 yo SCK1 Serial Clock for SSP Clock output from master or input to slave O MAT1 2 Match output for Timer 1 channel 2 PO 18 CAP1 3 5alt yo P0 18 General purpose digital input output pin MISO1 MAT1 3 l CAP1 3 Capture input for Timer 1 channel 3 y o MISO1 Master In Slave Out for SSP Data input to SPI master or data output from SSP slave O MAT1 3 Match output for Timer 1 channel 3 PO 19 MAT1 2 54 y o P0 19 General purpose digital input output pin MOSI1 CAP1 2 9 MAT1 2 Match output for Timer 1 channel 2 y o MOSI1 Master Out Slave In for SSP Data output from SSP master or d
365. t Clear register 0 IOOCLR address OxE002 800C bit description 81 GPIO Output Clear register 1 IO1CLR address OxE002 801C bit description 81 GPIO Direction Register 0 IOODIR address OxE002 8008 bit description 82 GPIO Direction Register 1 IO1DIR address OxE002 8018 bit description 82 UARTO pin description 84 UARTO register map 00 5 85 UARTO Receiver Buffer Register UORBR address 0xE000 C000 when DLAB 0 Read Only bit description 86 UARTO Transmit Holding Register UOTHR address 0xE000 C000 when DLAB 0 Write Only bit description 86 UARTO Divisor Latch LSB register UODLL address 0xE000 C000 when DLAB 1 bit description 20000 ec eee eee 87 UARTO Divisor Latch MSB register UODLM address 0xE000 C004 when DLAB 1 bit description 2 200 0c e eee eee 87 Some baud rates available when using 20 MHz peripheral clock PCLK 20 MHz 87 UARTO Interrupt Enable Register UOIER address 0xE000 C004 when DLAB 0 bit description 00000 eee ee eee 88 UARTO Interrupt Identification Register UOIIR address 0xE000 C008 read only bit description 00000 cece eee 88 UARTO interrupt handling 89 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table
366. t for the PLL to Lock then connect to the PLL as a clock source Register description The PLL is controlled by the registers shown in Table 13 More detailed descriptions follow Warning Improper setting of the PLL values may result in incorrect operation of the device Table 13 PLL registers Name PLLCON Description PLL Control Register Holding register for updating PLL control bits Values written to this register do not take effect until a valid PLL feed sequence has taken place Access Reset Address valuel R W 0 OxEO1F C080 PLLCFG PLL Configuration Register Holding register for updating PLL configuration values Values written to this register do not take effect until a valid PLL feed sequence has taken place RW o0 OxEO1F C084 PLLSTAT PLL Status Register Read back register for PLL control and configuration information If PLLCON or PLLCFG have been written to but a PLL feed sequence has not yet occurred they will not reflect the current PLL state Reading this register provides the actual values controlling the PLL as well as the status of the PLL RO 0 OxEO1F C088 PLLFEED PLL Feed Register This register enables loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation WO NA OxEO1F CO8C 1 Reset value relects the data stored in used bits only It does not
367. t forced mode Boot code Interrupt vectors are not re mapped and are found in the bottom of the Flash memory UserRAM Software Activated by a User Program as desired Interrupt vectors are mode activation by re mapped to the bottom of the Static RAM User program Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 12 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 2 Memory map 2 2 2 Memory re mapping In order to allow for compatibility with future derivatives the entire Boot Block is mapped to the top of the on chip memory space In this manner the use of larger or smaller flash modules will not require changing the location of the Boot Block which would require changing the Boot Loader code itself or changing the mapping of the Boot Block interrupt vectors Memory spaces other than the interrupt vectors remain in fixed locations Figure 6 shows the on chip memory mapping in the modes defined above The portion of memory that is re mapped to allow interrupt processing in different modes includes the interrupt vector area 32 bytes and an additional 32 bytes for a total of 64 bytes The re mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries The vector contained in the SRAM external memor
368. t more than one interrupt source Table 55 Connection of interrupt sources to the Vectored Interrupt Controller VIC Block Flag s VIC Channel and Hex Mask WDT Watchdog Interrupt WDINT 0 0x0000 0001 P Reserved for Software Interrupts only 1 0x0000 0002 ARM Core Embedded ICE DbgCommRx 2 0x0000 0004 ARM Core Embedded ICE DbgCommTX 3 0x0000 0008 TIMERO Match 0 3 MRO MR1 MR2 MR3 4 0x0000 0010 Capture 0 3 CRO CR1 CR2 CR3 TIMER1 Match 0 3 MRO MR1 MR2 MR3 5 0x0000 0020 Capture 0 3 CRO CR1 CR2 CR3 UARTO Rx Line Status RLS 6 0x0000 0040 Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI UART1 Rx Line Status RLS 7 0x0000 0080 Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI II PWMO Match 0 6 MRO MR1 MR2 MR3 MR4 MR5 MR6 8 0x0000 0100 12C0 SI state change 9 0x0000 0200 SPIO SPI Interrupt Flag SPIF 10 0x0000 0400 Mode Fault MODF SPI1 SSP TX FIFO at least half empty TXRIS 11 0x0000 0800 Rx FIFO at least half full RXRIS Receive Timeout condition RTRIS Receive overrun RORRIS PLL PLL Lock PLOCK 12 0x0000 1000 RTC Counter Increment RTCCIF 13 0x0000 2000 Alarm RTCALF System Control External Interrupt 0 EINTO 14 0x0000 4000 External Interrupt 1 EINT1 15 0x0000 8000 External Interrupt 2 EINT2
369. tEnable address OxFFFF F010 bit description Bit Symbol Description Reset value 31 0 See When this register is read 1s indicate interrupt requests or software interrupts 0 ViCintEnable that are enabled to contribute to FIQ or IRQ bit allocation When this register is written ones enable interrupt requests or software table interrupts to contribute to FIQ or IRQ zeroes have no effect See Section 5 4 5 Interrupt Enable Clear register VICIntEnClear OXFFFF F014 on page 53 and Table 43 below for how to disable interrupts 5 4 5 Interrupt Enable Clear register VICIntEnClear OXFFFF F014 This is a write only register This register allows software to clear one or more bits in the Interrupt Enable register see Section 5 4 4 Interrupt Enable register VICIntEnable OxFFFF F010 on page 52 without having to first read it Table 42 Software Interrupt Clear register VICIntEnClear address OxFFFF F014 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 symbol j j Access WO WO WO WO wO WO WO WO Bit 23 22 21 20 19 18 17 16 Symbol s AD1 BOD I2Ci ADO EINT3 EINT2 Access WO WO WO WO WO WO WO WO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINTO RTC PLL SPM SSP SPIO 2C0 PWMO Access WO WO WO WO WO WO WO WO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCoret ARMCore0 WDT Access WO WO WO WO WO WO WO WO Table 43 Software Interrupt Clear regi
370. ta Data only for Read commands ISP data format The data stream is in UU encode format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the received bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the receiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes A description of UU encode is available at http Awww wotsit org ISP flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 218 Philips Semiconductors UM1 01 20 ja Volume 1 20 4 8 20 4 9 20 4 10 20 4 11 20 4 12 20 4 13 Ch
371. te clock which must be 16x the desired baud rate Equation 1 The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UARTO Divisor Latches Details on how to select the right value for UODLL and UODLM can be found later on in this chapter Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 86 Philips Semiconductors UM1 01 20 I3 Volume 1 9 3 4 9 3 5 Chapter 9 UARTO 1 clk UARTO baudrate 16 x 16 x UODLM UODLL Table 76 UARTO Divisor Latch LSB register UODLL address 0xE000 C000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB The UARTO Divisor Latch LSB Register along with the UODLM 0x01 register determines the baud rate of the UARTO Table 77 UARTO Divisor Latch MSB register UODLM address 0xE000 C004 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLMSB The UARTO Divisor Latch MSB Register along with the UODLL 0x00 register determines the baud rate of the UARTO UARTO Baud rate calculation Example Using UARTOpaudrate Equation 1 from above it can be determined that system with PCLK 20 MHz UODL
372. ter and is cleared when 0 Ready the UART1 RBR FIFO is empty RDR 0 UIRBR is empty 1 U1RBR contains valid data Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 104 Philips Semiconductors UM10120 jal Volume 1 Chapter 10 UART1 Table 100 UART1 Line Status Register U1LSR address 0xE001 0014 read only bit description Bit Symbol 1 Overrun Error OE Value Description Reset value The overrun error condition is set as soon as it occurs An U1LSR read clears 0 U1LSR 1 UTLSR 1 is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full In this case the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost Overrun error status is inactive Overrun error status is active ml Parity Error PE When the parity bit of a received character is in the wrong state a parity error 0 occurs An U1LSR read clears U1LSR 2 Time of parity error detection is dependent on U1FCR 0 Note A parity error is associated with the character at the top of the UART1 RBR FIFO Parity error status is inactive Parity error status is active 3 Framing Error FE When the stop bit of a received character is a logic 0 a framing error occurs An 0 U1LSR read clears U1LSR 3 The time of the framing error detection is dependent on U1FCRO Upon detection of a framing error the RX wi
373. the CPU or host and the UART1 The UART1 receiver block U1RX monitors the serial input line RXD1 for valid input The UART1 RX Shift Register U1 RSR accepts valid characters via RXD1 After a valid character is assembled in the U1RSR it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART1 transmitter block U1TX accepts data written by the CPU or host and buffers the data in the UART1 TX Holding Register FIFO U1THR The UART1 TX Shift Register U1TSR reads the data stored in the U1THR and assembles the data to transmit via the serial output pin TXD1 The UART1 Baud Rate Generator block U1BRG generates the timing enables used by the UART1 TX block The U1BRG clock input source is the VPB clock PCLK The main clock is divided down per the divisor specified in the U1DLL and U1DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The modem interface contains registers Uf MCR and U1MSR This interface is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks Status information from the U1TX and U1RX is stored in the U1LSR Control information for the U1TX and U1RX is stored in the U1LCR Koninklijke Philips Electronics N V 2005 All rights reserved User manual
374. the STO flag must be set and SI must be cleared This causes the 12C block to enter the not addressed slave mode a defined state and to clear the STO flag no other bits in ICON are affected The SDA and SCL lines are released a STOP condition is not transmitted Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 135 Philips Semiconductors UM1 01 20 m Volume 1 Chapter 11 I C interfaces Table 124 Miscellaneous States Status Status of the I2C bus Application software response Next action taken by I C hardware pede im ad ieie To From IDDAT To I2CON I2CSTAT STA STO SI AA OxF8 No relevant state No I2DAT action No I2CON action Wait or proceed current transfer information available SI 0 0x00 Bus error during MST No I2DAT action 0 1 0 X Only the internal hardware is affected in or selected slave the MST or addressed SLV modes In all modes due to an cases the bus is released and the 12C illegal START or block is switched to the not addressed STOP condition State SLV mode STO is reset 0x00 can also occur when interference causes the I C block to enter an undefined state 11 8 8 Some special cases The 12C hardware has facilities to handle the following special cases that may occur during a serial transfer 11 8 9 Simultaneous repeated START conditions from two masters A repeated START condition may be generated in the master transmitter or ma
375. the external match pins MAT 0 3 Table 151 External Match Register EMR TIMERO TOEMR address 0xE000 403C and TIMER1 T1EMR address0xE000 803C bit description Bit Symbol Description Reset value 0 EMO External Match 0 This bit reflects the state of output MATO 0 MAT1 0 whether or not this 0 output is connected to its pin When a match occurs between the TC and MRO this output of the timer can either toggle go low go high or do nothing Bits EMR 5 4 control the functionality of this output 1 EM1 External Match 1 This bit reflects the state of output MATO 1 MAT1 1 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR1 this output of the timer can either toggle go low go high or do nothing Bits EMR 7 6 control the functionality of this output 2 EM2 External Match 2 This bit reflects the state of output MATO 2 MAT 1 2 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR2 this output of the timer can either toggle go low go high or do nothing Bits EMR 9 8 control the functionality of this output 3 EM3 External Match 3 This bit reflects the state of output MATO S MAT1 3 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR3 this output of the timer can either toggle go low go high or do nothing Bits EMR 11 10 control the functionality of this output 5 4 EM
376. this case 5 760 of the prescaler output clocks will be 306 305 1 PCLKs long the rest will be 305 PCLKs long In a similar manner any PCLK rate greater than 65 536 kHz as long as it is an even number of cycles per second may be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC does not contain a zero then not all of the 32 768 per second clocks are of the same length Some of the clocks are one PCLK longer than others While the longer pulses are distributed as evenly as possible among the remaining pulses this jitter could possibly be of concern in an application that wishes to observe the contents of the Clock Tick Counter CTC directly Section 18 4 4 Clock Tick Counter Register CTCR 0xE002 4004 on page 203 To clock tick PCLK counter clock VPB Clock CLK UNDERFLOW 15 BIT FRACTION COUNTER 13 BIT INTEGER COUNTER DOWN COUNTER RELOAD COMBINATORIAL LOGIC Extend reload 13 BIT RELOAD INTEGER REGISTER PREINT VPB Bus Fig 52 RTC prescaler block diagram 18 6 4 Prescaler operation The Prescaler block labelled Combination Logic in Figure 52 determines when the decrement of the 13 bit PREINT counter is extended by one PCLK In order to both insert the correct number of longer cycles and to distribute them evenly the ombinatorial Logic associates each bit in PREFRAC with a combination in the 15 bit Fraction Counter These associations are shown in the
377. tion On chip PLL used in application ISP used for initial code download External crystal oscillator used MIN f 10 MHz t 3 MAX foso 25 MHz MAX fosc 50 MHz MAX fosa 30 MHz MIN f 1 MHz MIN f 1 MHz C C Figure 7 mode a and or b Figure 7 mode a Figure 7 mode b Fig 8 Fosc selection algorithm Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 19 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 3 System Control Block 3 5 External interrupt inputs 3 5 1 3 5 2 The LPC2131 2 4 6 8 includes four External Interrupt Inputs as selectable pin functions The External Interrupt Inputs can optionally be used to wake up the processor from Power down mode Register description The external interrupt function has four registers associated with it The EXTINT register contains the interrupt flags and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the microcontroller from Power down mode The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters Table 7 External interrupt registers Name Description Access Reset Address valuel EXTINT The External Interrupt Flag Register contains R W 0 OxE01F C140 interrupt flags for EINTO EINT1 EINT2 and EINT3 See Table 8 INTWAKE The Interrupt Wakeup Register contains four R W 0 OxEO1F C144 ena
378. tion command Command Prepare sector s for write operation Input Command code 5019 Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID SECTOR Result None Description This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 232 Philips Semiconductors UM10120 ja Volume 1 Chapter 20 Flash Memory 20 9 2 Copy RAM to Flash Table 212 IAP Copy RAM to Flash command 20 9 3 Command Input Copy RAM to Flash Command code 5110 Param0 DST Destination Flash address where data bytes are to be written This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1024 4096 Param3 System Clock Frequency CCLK in kHz Return Code CMD_SUCCESS SRC_ADDR_ERROR Address not a word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADD
379. to achieve this the VPB bus may be slowed down to one half or one fourth of the processor clock rate Because the VPB bus must work properly at power up and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus the default condition at reset is for the VPB bus to run at one quarter speed The second purpose of the VPB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 12 Because the VPB Divider is connected to the PLL output the PLL remains active if it was running during Idle mode Register description Only one register is used to control the VPB Divider Table 26 VPB divider register map Name Description Access Reset Address valuel VPBDIV Controls the rate of the VPB clock in relation to R W 0x00 OxEO1F C100 the processor clock 1 Reset value relects the data stored in used bits only It does not include reserved bits content VPBDIV register VPBDIV OxE01F C100 The VPB Divider register contains two bits allowing three divider values as shown in Table 27 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 38 Philips Semiconductors UM1 01 20 Volume 1 Chapter 3 System Control Block Table 27 VPB Divider r
380. to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Table 199 ISP Read memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD SUCCESS followed by actual data UU encoded gt ADDR ERROR Address not on word boundary ADDR NOT MAPPED COUNT ERROR Byte count is not a multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to read data from RAM or Flash memory This command is blocked when code read protection is enabled Example R 1073741824 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x4000 0000 Prepare sector s for write operation start sector number end sector number gt This command makes flash write erase operation a two step process Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 225 Philips Semiconductors UM10120 Volume 1 20 8 7 Chapter 20 Flash Memory Table 200 ISP Prepare sector s for write operation command Command Input P Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SU
381. top on PWMMR3 The PWMTC and PWMPC will be stopped and PWMTCR O will 0 be set to 0 if PWMMR3 matches the PWMTC This feature is disabled O 12 PWMMR4AI Interrupt on PWMMR4 An interrupt is generated when PWMMR4 matches the value 0 in the PWMTC This interrupt is disabled Reset on PWMMR4 the PWMTC will be reset if PWMMR4 matches it 0 This feature is disabled Stop on PWMMR4 the PWMTC and PWMPC will be stopped and PWMTCR O will 0 be set to 0 if PWMMR4 matches the PWMTC This feature is disabled 13 PWMMR4R O o 14 PWMMR4S oO 15 PWMMRS5I Interrupt on PWMMR565 An interrupt is generated when PWMMR5 matches the value 0 in the PWMTC This interrupt is disabled Reset on PWMMR5 the PWMTC will be reset if PWMMR5 matches it 0 This feature is disabled Stop on PNMMR5 the PWMTC and PWMPC will be stopped and PWMTCR O will 0 be set to 0 if PWMMR5 matches the PWMTC This feature is disabled 16 PWMMR5R Oo o 17 PWMMR5S 18 PWMMRelI Interrupt on PWMMRE an interrupt is generated when PWMMR6 matches the value 0 in the PWMTC This interrupt is disabled Reset on PWMMR6 the PWMTC will be reset if PWMMR6 matches it 0 This feature is disabled Stop on PNWMMR6 the PWMTC and PWMPC will be stopped and PWMTCR O will 0 be set to 0 if PWMMR6 matches the PWMTC This feature is disabled 19 PWMMR6R Oo o 20 PWMMR6S
382. tor CTI 001 3 THRE Interrupt 000 4 Modem Interrupt l 54 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 6 FIFO Enable These bits are equivalent to U1FCR O 0 1 LPC2134 6 8 only For all other LPC213x devices 000 combination is Reserved Interrupts are handled as described in Table 83 Given the status of U1IIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UART1 RLS interrupt U1IIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1RX input overrun error OE parity error PE framing error FE and break interrupt BI The UART1 Rx error condition that set the interrupt can be observed via U1LSR 4 1 The interrupt is cleared upon an U1LSR read The UART1 RDA interrupt U1IIR 3 1 010 shares the second level priority with the CTI interrupt U1IIR 3 1 110 The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1 FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt U1IIR 3 1 110 is a second level interrupt and is
383. tor number gt Table 204 Read Part ID J Table 205 Read Boot code version K Table 207 Compare M lt address1 gt lt address2 gt lt number of bytes gt Table 208 Unlock lt unlock code gt Table 194 ISP Unlock command Command U Input Unlock code 2313049 Return Code CMD SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock flash Write Erase and Go commands Example U 23130 lt CR gt lt LF gt unlocks the flash Write Erase amp Go commands Set Baud Rate baud rate stop bit gt Table 195 ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 230400 Stop bit 1 2 Return Code CMD SUCCESS INVALID BAUD RATE INVALID STOP BIT PARAM ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 223 Philips Semiconductors UM1 01 20 ja Volume 1 20 8 3 20 8 4 Chapter 20 Flash Memory Table 196 Correlation between possible ISP baudrates and external crystal frequency in MHz ISP Baudrate vs 9600 19200 38400 57600 115200 230400 External Crystal Frequency 10 0000 11 0592 12 2880 14 7456 15
384. trol block Some peripherals particularly those that include analog functions may consume power that is not clock dependent These peripherals may contain a separate disable control that turns off additional circuitry to reduce power Each bit in PCONP controls one of the peripherals The bit numbers correspond to the related peripheral number as shown in the VPB peripheral map Figure 5 VPB peripheral map in the LPC2131 2 4 6 8 Memory Addressing chapter If a peripheral control bit is 1 that peripheral is enabled If a peripheral bit is O that peripheral is disabled to conserve power For example if bit 19 is 1 the I C1 interface is enabled If bit 19 is 0 the I C1 interface is disabled Important valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 34 Philips Semiconductors UM1 01 20 E Volume 1 3 9 Reset 3 8 4 Chapter 3 System Control Block Table 24 Power Control for Peripherals register PCONP address 0xE01F COCA bit description Bit Symbol Description Reset value 0 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 1 PCTIMO Timer Counter 0 power clock control bit 1 2 PCTIM1 Ti
385. trolled mode for the PWM6 output 0 0 Selects single edge controlled mode for PWM6 8 7 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 9 PWMENA1 1 The PWM output enabled 0 0 The PWM1 output disabled 10 PWMENA2 1 The PWM output enabled 0 0 The PWM2 output disabled 11 PWMENAS 1 The PWMS output enabled 0 0 The PWMS output disabled 12 PWMENA4 1 The PWM4 output enabled 0 0 The PWMA output disabled 13 PWMENAS 1 The PWM5 output enabled 0 0 The PWMBS output disabled 14 PWMENA6 1 The PWM6 output enabled 0 0 The PWM6 output disabled Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 15 4 9 PWM Latch Enable Register PWMLER 0xE001 4050 The PWM Latch Enable Register is used to control the update of the PWM Match registers when they are used for PWM generation When software writes to the location of a PWM Match register while the Timer is in PWM mode the value is held in a shadow register When a PWM Match 0 event occurs normally also resetting the timer in PWM mode the contents of shadow registers will be transferred to the actual Match registers if the corresponding bit in the Latch Enable Register has been set At that point the new values will take effect and determine the course of the next PWM cycle Once the transfer of new values has taken place all bits of the LER are automatica
386. ts the number of clocks used for each conversion in Burst mode and the 000 number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits and 4 clocks 3 bits 000 11 clocks 10 bits 001 10 clocks 9bits 010 9 clocks 8 bits 011 8 clocks 7 bits 100 7 clocks 6 bits 101 6 clocks 5 bits 110 5 clocks 4 bits 111 4 clocks 3 bits 20 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 21 PDN 1 The A D converter is operational 0 0 The A D converter is in power down mode 23 22 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversion is 0 started 000 No start this value should be used when clearing PDN to 0 001 Start conversion now 010 Start conversion when the edge selected by bit 27 occurs on P0 16 EINTO MATO 2 CAPO 2 pin 011 Start conversion when the edge selected by bit 27 occurs on P0 22 TD3 CAP0 0 MATO 0 pin 100 Start conversion when the edge selected by bit 27 occurs on MATO 1 101 Start conversion when the edge selected by bit 27 occurs on MATO 3 110 Start conversion when the edge selected by bit 27 occurs on MAT1 0 111 Start conversion when the edge selected by bit 27 occurs on MAT1 1 27 EDGE T
387. tten to the PWM 0 Match 6 Latch Match 6 register to be become effective when the timer is next reset by a PWM Match event See Section 15 4 7 PWM Match Control Register PWMMCR 0xE001 4014 7 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 192 UM10120 Chapter 16 Analog to Digital Converter ADC Semiconductors 16 1 Features Rev 01 24 June 2005 User manual ET 10 bit successive approximation analog to digital converter one in LPC2131 2 and two in LPC2134 6 8 Input multiplexing among 8 pins Power down mode Measurement range 0 to 3 V 10 bit conversion time 2 2 44 us Burst conversion mode for single or multiple inputs Optional conversion on transition on input pin or Timer Match signal Global Start command for both converters LPC2134 6 8 only 16 2 Description Basic clocking for the A D converters is provided by the VPB clock A programmable divider is included in each converter to scale this clock to the 4 5 MHz max clock needed by the successive approximation process A fully accurate conversion requires 11 of these clocks 16 3 Pin description Table 161 gives a brief summary of each of ADC related pins Table 161 ADC pin description Pin Type ADO 7 0 Input amp AD1 7 0
388. tware should not write ones to reserved NA bits The value read from a reserved bit is not defined 4 8 MAM Timing register MAMTIM 0xE01F C004 The MAM Timing register determines how many CCLK cycles are used to access the Flash memory This allows tuning MAM timing to match the processor operating frequency Flash access times from 1 clock to 7 clocks are possible Single clock Flash accesses would essentially remove the MAM from timing calculations In this case the MAM mode may be selected to optimize power usage Table 32 MAM Timing register MAMTIM address 0xE01F C004 bit description Bit Symbol Value Description Reset value 2 0 MAM fetch 000 0 Reserved 07 cycle_timing 001 1 MAM fetch cycles are 1 processor clock CCLK in duration 010 2 MAM fetch cycles are 2 CCLKs in duration 011 3 MAM fetch cycles are 3 CCLKs in duration 100 4 MAM fetch cycles are 4 CCLKs in duration 101 5 MAM fetch cycles are 5 CCLKs in duration Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 46 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 4 MAM Module Table 32 MAM Timing register MAMTIM address OxEO1F C004 bit description Bit Symbol Value Description Reset value 110 6 MAM fetch cycles are 6 CCLKs in duration 111 7 MAM fetch cycles are 7 CCLKs in duration Warning These bits set the duration of MAM Flash fetch operations
389. une 2005 224 Philips Semiconductors UM1 01 20 ja Volume 1 20 8 5 20 8 6 Chapter 20 Flash Memory Table 198 ISP Write to RAM command Command Ww Input Start Address RAM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS l ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE READ PROTECTION ENABLED Description This command is used to download data to RAM Data should be in UU encoded format This command is blocked when code read protection is enabled Example W 1073742336 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x4000 0200 Read memory lt address gt no of bytes gt The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the checksum of the received bytes If the check sum matches then the host should respond with OK lt CR gt lt LF gt
390. unters If CIIR is enabled for a particular counter then every time the counter is incremented an interrupt is generated The alarm registers allow the user to specify a date and time for an interrupt to be generated The AMR provides a mechanism to mask alarm compares If all nonmasked alarm registers match the value in their corresponding time counter then an interrupt is generated The RTC interrupt can bring the microcontroller out of power down mode if the RTC is operating from its own oscillator on the RTCX1 2 pins When the RTC interrupt is enabled for wakeup and its selected event occurs XTAL1 2 pins associated oscillator wakeup cycle is started For details on the RTC based wakeup process see Section 3 5 3 Interrupt Wakeup register INTWAKE OxEO1F C144 on page 22 and Section 3 11 Wakeup timer on page 39 Miscellaneous register group Table 169 summarizes the registers located from 0 to 7 of A 6 2 More detailed descriptions follow Table 169 Miscellaneous registers Name Size Description Access Address ILR 2 Interrupt Location Reading this location RAN OxE002 4000 indicates the source of an interrupt Writing a one to the appropriate bit at this location clears the associated interrupt CTC 15 Clock Tick Counter Value from the clock RO OxE002 4004 divider CCR 4 Clock Control Register Controls the function of R W OxE002 4008 the clock divider CIIR 8 Counter Increment Interrupt Selects which R
391. upt vectors on the ARM7 processor at addresses 0x0000 0000 through 0x0000 001C as shown in Table 2 below a small portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 3 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature Section 3 6 Memory mapping control on page 25 Table 2 ARM exception vector locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort instruction fetch memory fault 0x0000 0010 Data Abort data access memory fault 0x0000 0014 Reserved Note Identified as reserved in ARM documentation this location is used by the Boot Loader as the Valid User Program key This is descibed in detail in Flash Memory System and Programming chapter on page 216 0x0000 0018 IRQ 0x0000 001C FIQ Table3 LPC2131 2 4 6 memory mapping modes Mode Activation Usage Boot Hardware The Boot Loader always executes after any reset The Boot Block Loader activation by interrupt vectors are mapped to the bottom of memory to allow mode any Reset handling exceptions and using interrupts during the Boot Loading process User Software Activated by Boot Loader when a valid User Program Signature is Flash activation by recognized in memory and Boot Loader operation is no
392. urs on MAT1 1 27 EDGE This bit is significant only when the START field contains 010 111 In these cases 0 1 Start conversion on a falling edge on the selected CAP MAT signal 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 16 5 Operation 16 5 1 Hardware triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal The choices include conversion on a specified edge of any of 4 Match signals or conversion on a specified edge of either of 2 Capture Match pins The pin state from the selected pad or the selected Match signal XORed with ADCR bit 27 is used in the edge detection logic 16 5 2 Interrupts An interrupt request is asserted to the Vectored Interrupt Controller VIC when the DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the VIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read 16 5 3 Accuracy vs digital receiver The AIN function must be selected in corresponding Pin Select register see Pin Connect Block on page 73 in order to get accurate voltage readings on the monitored pin For pin hosting an ADC input it is not possible to have a have a di
393. us interrupts are possible in the ARM7TDMI based microcontrollers such as the LPC2131 2 4 6 8 due to asynchronous interrupt handling The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC If the VIC state is changed between the moments when the core detects an interrupt and the core actually processes an interrupt problems may be generated Real life applications may experience the following scenarios 1 VIC decides there is an IRQ interrupt and sends the IRQ signal to the core 2 Core latches the IRQ state 3 Processing continues for a few cycles due to pipelining 4 Core loads IRQ address from VIC Furthermore It is possible that the VIC state has changed during step 3 For example VIC was modified so that the interrupt that triggered the sequence starting with step 1 is no longer pending interrupt got disabled in the executed code In this case the VIC will not be able to clearly identify the interrupt that generated the interrupt request and as a result the VIC will return the default interrupt VicDefVectAddr OxFFFF F034 This potentially disastrous chain of events can be prevented in two ways 1 Application code should be set up in a way to prevent the spurious interrupts from occurring Simple guarding of changes to the VIC may not be enough since for example glitches on level sensitive interrupts can also cause spurious interrupts 2 VIC default handler should
394. ust first be completed before the Watchdog is capable of generating an interrupt reset Until then the watchdog will ignore feed errors Once OxAA is written to the WDFEED register the next operation in the Watchdog register space should be a WRITE 0x55 to the WDFFED register otherwise the watchdog is triggered The interrupt reset will be generated during the second PCLK following an incorrect access to a watchdog timer register during a feed sequence Table 190 Watchdog Feed register WDFEED address 0xE000 0008 bit description Bit Symbol Description Reset value 7 0 Feed Feed value should be OxAA followed by 0x55 NA Watchdog Timer Value register WDTV 0xE000 000C The WDTV register is used to read the current value of watchdog timer Table 191 Watchdog Timer Value register WDTV address 0xE000 000C bit description Bit Symbol Description Reset value 31 0 Count Counter timer value 0x0000 00FF 19 5 Block diagram The block diagram of the Watchdog is shown below in the Figure 54 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 214 Philips Semiconductors UM10120 ja Volume 1 Chapter 19 WDT Feed Feed error sequence V WDTV register SHADOW BIT WDMOD Register 1 Counter is enabled only when the WDEN bit is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be c
395. ve address and the direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in I2STAT are possible There are 0x18 0x20 or 0x38 for the master mode and also 0x68 0x78 or 0xBO if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 120 After a repeated start condition state 0x10 The I C block may switch to the master receiver mode by loading I2DAT with SLA R Master Receiver mode In the master receiver mode a number of data bytes are received from a slave transmitter see Figure 30 The transfer is initialized as in the master transmitter mode When the start condition has been transmitted the interrupt service routine must load I2DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in I2CON must then be cleared before the serial transfer can continue When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in I2STAT are possible These are 0x40 0x48 or 0x38 for the master mode and also 0x68 0x78 or OxBO if the slave mode was enabled AA 1 The appropriate action to be taken for each of these status codes is detailed in Table 121 After a repeated start condition state 0x10 the I C block may switch to
396. ve is currently selected to participate in a data transfer Each slave has its own unique slave select signal input The SSEL must be low before data transactions begin and normally stays low for the duration of the transaction If the SSEL signal goes high any time during a data transfer the transfer is considered to be aborted In this event the slave returns to idle and any data that was received is thrown away There are no other indications of this exception This signal is not directly driven by the master It could be driven by a simple general purpose I O under software control On the LPC2131 2 4 6 8 unlike earlier Philips ARM devices the SSELO pin can be used for a different function when the SPIO interface is only used in Master mode For example pin hosting the SSELO function can be configured as an output digital GPIO pin and used to select one of the SPIO slaves MISOO Input Output Master In Slave Out The MISO signal is a unidirectional signal used to transfer serial data from the slave to the master When a device is a slave serial data is output on this signal When a device is a master serial data is input on this signal When a slave device is not selected the slave drives the signal high impedance MOSIO Input Output Master Out Slave In The MOSI signal is a unidirectional signal used to transfer serial data from the master to the slave When a device is a master serial data is output on this signal When
397. ved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 4 Loopback Mode The modem loopback mode provides a mechanism to perform 0 Select diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver Input pin RXD1 has no effect on loopback and output pin TXD1 is held in marking state The four modem inputs CTS DSR RI and DCD are disconnected externally Externally the modem outputs RTS DTR are set inactive Internally the four modem outputs are connected to the four modem inputs As a result of these connections the upper four bits of the UTMSR will be driven by the lower four bits of the U1MCR rather than the four modem inputs in normal mode This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U1MCR 0 Disable modem loopback mode 1 Enable modem loopback mode 7 5 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 10 3 10 UART1 Line Status Register U1LSR 0xE001 0014 Read Only The U1LSR is a read only register that provides status information on the UART1 TX and RX blocks Table 100 UART1 Line Status Register UTLSR address 0xE001 0014 read only bit description Bit Symbol Value Description Reset value O Receiver Data U1LSR O0 is set when the UTRBR holds an unread charac
398. ved bits NA The value read from a reserved bit is not defined 14 BODWAKE When one a BOD interrupt will wake up the processor from 0 Power down mode 15 RTCWAKE When one assertion of an RTC interrupt will wake up the 0 processor from Power down mode External Interrupt Mode register EXTMODE OxEO1F C148 The bits in this register select whether each EINT pin is level or edge sensitive Only pins that are selected for the EINT function see chapter Pin Connect Block on page 73 and enabled via the VICIntEnable register Section 5 4 4 Interrupt Enable register VICIntEnable OxFFFF F010 on page 52 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register and should write the corresponding 1 to the EXTINT register before enabling initializing or re enabling the interrupt to clear the EXTINT bit that could be set by changing the mode Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 22 Philips Semiconductors UM1 01 20 fal Volume 1 3 5 5 Chapter 3 System Control Block Table 10 External Interrupt Mode register EXTMODE address 0xE01F C148 bit description Bit Symbol Value Description Reset value
399. ved data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit State OxAO A Stop condition or repeated Start has been received while still addressed as a Slave Data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit Slave Transmitter States State 0xA8 Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received Load I2DAT from Slave Transmit buffer with first data byte Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Transmit mode data buffer Increment Slave Transmit buffer pointer Exit o c 2 WD State 0xBO Arbitration lost in Slave Address and R W bit as bus Master Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received STA is set to restart Master mode after the bus is free again 1 Load I2DAT from Slave Transmit buffer with first data byte 2 Write 0x24 to I2CONSET to set the STA and AA bits Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 145 Philips Semiconductors UM1 01 20 iz Volume 1 Chapter 11 I C interfaces 3 Write 0x08 to I2CONC
400. ven Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity 6 Break Control 0 Disable break transmission 0 1 Enable break transmission Output pin UARTO TXD is forced to logic 0 when UOLCR 6 is active high 7 Divisor Latch 0 Disable access to Divisor Latches 0 Access Bit DLAB 4 Enable access to Divisor Latches 9 3 9 UARTO Line Status Register UOLSR OxE000 C014 Read Only The UOLSR is a read only register that provides status information on the UARTO TX and RX blocks Table 84 UARTO Line Status Register UOLSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value O Receiver Data UOLSRO is set when the UORBR holds an unread character and is cleared 0 Ready when the UARTO RBR FIFO is empty RDR 0 UORBR is empty 1 UORBR contains valid data 1 Overrun Error The overrun error condition is set as soon as it occurs An UOLSR read clears 0 OE UOLSR1 UOLSR1 is set when UARTO RSR has a new character assembled and the UARTO RBR FIFO is full In this case the UARTO RBR FIFO will not be overwritten and the character in the UARTO RSR will be lost 0 Overrun error status is inactive 1 Overrun error status is active 2 Parity Error When the parity bit of a received character is in the wrong state a parity error 0 PE occurs An UOLSR read clears UOLSR 2 Time of parity error det
401. veys no licence or title under any patent copyright or mask work right to these Chapter 24 Supplementary information products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification 24 3Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus wordmark and logo are trademarks of Koninklijke Philips Electronics N V Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 256 Philips Semiconductors UM10120 Chapter 24 Supplementary information ja Volume 1 24 4 Tables Table 1 LPC2131 2132 2134 2136 2138 device information lisse 4 Table 2 ARM exception vector locations 12 Table 3 LPC2131 2 4 6 8 memory mapping modes 12 Table 4 Pinsummary cee eee eee 16 Table 5 Summary of system control registers 17 Table 6 Recommended values for Cx1 x in oscillation mode crystal and external components parameters 0 e cee eee eee 19 Table 7
402. wire frame format Figure 43 shows the Microwire frame format for a single frame Figure 44 shows the same format when back to back frames are transmitted Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 162 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 13 SSP cs uU D uU uU JU o we f j je d n i il 8 bit control 9 TED gt 4 to 16 bits output data Fig 43 Microwire frame format single transfer Microwire format is very similar to SPI format except that transmission is half duplex instead of full duplex using a master slave message passing technique Each serial transmission begins with an 8 bit control word that is transmitted from the SSP to the off chip slave device During this transmission no incoming data is received by the SSP After the message has been sent the off chip slave decodes it and after waiting one serial clock after the last bit of the 8 bit control message has been sent responds with the required data The returned data is 4 to 16 bits in length making the total frame length anywhere from 13 to 25 bits In this configuration during idle periods The SK signal is forced LOW CS is forced HIGH The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in the bottom entry of the
403. write operation was FOR WRITE OPERATION not executed 10 COMPARE ERROR Source and destination data is not same 11 BUSY Flash programming hardware interface is busy 20 10 JTAG Flash programming interface Debug tools can write parts of the flash image to the RAM and then execute the IAP call Copy RAM to Flash repeatedly with proper offset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 236 Semiconductors 21 1 Features UM10120 Chapter 21 EmbeddedlCE logic Rev 01 24 June 2005 User manual Mmi No target resources are required by the software debugger in order to start the debugging session Allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Inserts instructions directly in to the ARM7TDMI S core The ARM7TDMI S core or the System state can be examined saved or changed depending on the type of instruction inserted Allows instructions to execute at a slow debug speed or at a fast system speed 21 2 Applications The EmbeddedICE logic provides on chip debug support The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI S core present on the target system 21 3 Description The ARM7
404. x08 to I2CONCLR to clear the SI flag Exit Load I2DAT with next data byte from Master Transmit buffer Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Master Transmit buffer pointer Exit oO AN Oo Cc A O 11 9 14 State 0x30 Data has been transmitted NOT ACK received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 15 State 0x38 Arbitration has been lost during Slave Address Write or data The bus has been released and not addressed Slave mode is entered A new Start condition will be transmitted when the bus is free again 1 Write 0x24 to I2CONSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 16 Master Receive States 11 9 17 State 0x40 Previous state was State 08 or State 10 Slave Address Read has been transmitted ACK has been received Data will be received and ACK returned 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 18 State 0x48 Slave Address Read has been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 0
405. xE002 4014 22000 02 eeeeee 18 4 Register description 201 184 10 Consolidated Time register 1 CTIME1 18 4 1 RTC interrupts 0 000 eee ee 202 OxE002 4018 2 aaan nanana 205 18 4 2 Miscellaneous register group TM 202 18 4 11 Consolidated Time register 2 CTIME2 18 4 3 Interrupt Location Register OxE002 401C cc csecceseesvnasress 205 BERE OxE002 4000 A RRS 202 18 4 12 Time counter group 205 18 4 4 Clock Tick Counter Register CTCR 18 4 13 Leap year calculation 206 0xE002 4004 E E E E A 203 18 4 14 Alarm register group 206 18 4 5 Clock Control Register CCR 0xE002 4008 203 18 5 RTC sade n tes 207 18 4 6 Counter Increment Interrupt Register CIIR j usag Sete ea E OxE002 400C csse 203 18 6 Reference clock divider prescaler 207 continued gt gt Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 268 Philips Semiconductors UM10120 Volume 1 Chapter 24 Supplementary information 18 6 1 Prescaler Integer register PREINT 18 6 3 Example of prescaler usage 208 OxE002 4080 00000 208 18 6 4 Prescaler operation 209 18 6 2 Prescaler Fraction register PREFRAC 18 7 RTC external 32 kHz oscillator component 0xE002 4084 0 eee eee eee 208 Selection asc ste nce edo rad eR
406. xadecimal nottaion and data accessed as words to originate from adresses with address lines 0 and 1 being 0 addresses ending with 0 4 8 and C in hexadecimal notation This rule applies to both off and on chip memory usage The SRAM controller incorporates a write back buffer in order to prevent CPU stalls during back to back writes The write back buffer always holds the last data sent by software to the SRAM This data is only written to the SRAM when another write is requested by software the data is only written to the SRAM when software does another write If a chip reset occurs actual SRAM contents will not reflect the most recent write request i e after a warm chip reset the SRAM does not reflect the last write operation Any software that checks SRAM contents after reset must take this into account Two identical writes to a location guarantee that the data will be present after a Reset Alternatively a dummy write operation before entering idle or power down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 6 Philips Semiconductors UM10120 Volume 1 1 9 Block diagram Chapter 1 Introductory information cas INTERNAL INTERNAL SRAM FLASH CONTROLLER CONTROLLER 1 32 64 128 256 512 kB FLASH T VP
407. xcept in level sensitive mode when the pin is in its active state e g if EINTO is selected to be low level sensitive and a low level is present on the corresponding pin this bit can not be cleared this bit can be cleared only when the signal on the pin becomes high Reset value 1 EINT1 In level sensitive mode this bit is set if the EINT1 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT1 function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform the EINT1 function see P0 3 and P0 14 description in Pin Configuration chapter on page 64 This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state e g if EINT1 is selected to be low level sensitive and a low level is present on the corresponding pin this bit can not be cleared this bit can be cleared only when the signal on the pin becomes high 2 EINT2 In level sensitive mode this bit is set if the EINT2 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT2 function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform the EINT2 function see PO 7 and P0 15 description in Pin Configuration chapter on page 64 This bit is cleared by writing a one to it except in level
408. y and Boot Block must contain branches to the actual interrupt handlers or to other instructions that accomplish the branch to the interrupt handlers There are three reasons this configuration was chosen 1 To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account 2 Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space 3 To provide space to store constants for jumping beyond the range of single word branch instructions Re mapped memory areas including the Boot Block and interrupt vectors continue to appear in their original location in addition to the re mapped address Details on re mapping and examples can be found in Section 3 6 Memory mapping control on page 25 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 13 Philips Semiconductors UM10120 ja Volume 1 Chapter 2 Memory map 0x8000 0000 2 0 GB 12 kB BOOT BLOCK Ox7FFF FFFF RE MAPPED FROM TOP OF FLASH MEMORY 20GB 12kB BOOT BLOCK INTERRUPT VECTORS RESERVED ADDRESSING SPACE 0x4000 8000 0x4000 7FFF 32 kB ON CHIP SRAM 1 0 GB SRAM INTERRUPT VECTORS 0x4000 0000 Ox3FFF FFFF RESERVED ADDRESSING SPACE 0x0008 0000 12 kB BOOT BLOCK RE MAPPED TO HIGHER ADDRESS RANGE 0x0007 FFFF 512 kB FLASH MEMORY 0 0 GB ACTIVE INTERRUPT
409. y cycle Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle I2SCLH defines the number of PCLK cycles for the SCL high time I2SCLL defines the number of PCLK cycles for the SCL low time The frequency is determined by the following formula fpc being the frequency of PCLK 3 PC E pcLK b frequency I2 CSCLH 12CSCLL The values for I2SCLL and I2SCLH should not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the 12 C bus specification defines the SCL low time and high time at different values for a 400 kHz 12C rate The value of the register must ensure that the data rate is in the I C data rate range of 0 through 400 kHz Each register value must be greater than or equal to 4 Table 115 gives some examples of I2C bus rates based on PCLK frequency and I2SCLL and I2SCLH values Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 122 Philips Semiconductors UM1 01 20 ie Volume 1 Chapter 11 I C interfaces Table 115 Example I2C clock rates I2SCLL I C Bit Frequency kHz at PCLK MHz I2SCLH 4 5 10 16 20 40 60 8 125 10 100 25 40 200 400 50 20 100 200 320 400 100 10 50 100 160 200 400 160 6 25 31 25 62 5 100 125 250 375 200 5 25 50 80 100 200 300 400 2 5 12 5 25 40 50 100 150 800 1 25 6 25 12 5
410. y for deeply embedded processor cores It outputs information about processor execution to a trace port A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand 22 3 Description 22 3 1 The ETM is connected directly to the ARM core and not to the main AMBA system bus It compresses the trace information and exports it through a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace or PC trace shows the flow of execution of the processor and provides a list of all the instructions that were executed Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis Trace information generation can be controlled by selecting the trigger resource Trigger resources include address comparators counters and sequencers Since trace information is compressed the software debugger requires a static image of the code being executed Self modifying code can not be traced because of this restriction ETM configuration The following standard configuration is selected for the ETM macrocell Table 222 ETM configuration Resource number type Small Pairs of addre
411. y hostile or competitive eyes The following feature of the LPC2131 2 4 6 8 allows an application to control whether it can be debugged or protected from observation Details on the way Code Read Protection works can be found in the Flash Memory System and Programming chapter on page 216 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 41 Semiconductors UM10120 Chapter 4 Memory Acceleration Module MAM Rev 01 24 June 2005 User manual iT 4 1 Introduction 4 2 Operation The MAM block in the LPC2131 2 4 6 8 maximizes the performance of the ARM processor when it is running code in Flash memory but does so using a single Flash bank Simply put the Memory Accelerator Module MAM attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls The LPC2131 2 4 6 8 uses one bank of Flash memory compared to the two banks used on predecessor devices It includes three 128 bit buffers called the Prefetch Buffer the Branch Trail Buffer and the data buffer When an Instruction Fetch is not satisfied by either the Prefetch or Branch Trail Buffer nor has a prefetch been initiated for that line the ARM is stalled while a fetch is initiated for the 128 bit line If a prefetch has been initiated but not yet completed the ARM is stalled for a shorter time Unless aborted by a data access a prefetch is initiated as
412. y system respectively This memory may be used for both code and data storage Programming of the Flash memory may be accomplished in several ways over the serial builtin JTAG interface using In System Programming ISP and UARTO or by means of In Application Programming IAP capabilities The application program using the IAP functions may also erase and or program the Flash while the application is running allowing a great degree of flexibility for data storage field firmware upgrades etc When the LPC2131 2 4 6 8 on chip bootloader is used 32 64 128 256 500 kB of Flash memory is available for user code The LPC2131 2 4 6 8 Flash memory provides minimum of 10 000 erase write cycles and 10 years of data retention 1 8 On chip Static RAM SRAM On chip Static RAM SRAM may be used for code and or data storage The on chip SRAM may be accessed as 8 bits 16 bits and 32 bits The LPC2131 2 4 6 8 provide 8 16 32 kB of static RAM respectively The LPC2131 2 4 6 8 SRAM is designed to be accessed as a byte addressed memory Word and halfword accesses to the memory ignore the alignment of the address and access the naturally aligned value that is addressed so a memory access ignores address bits 0 and 1 for word accesses and ignores bit 0 for halfword accesses Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 addresses ending with 0 2 4 6 8 A C and E in he
413. ynchronized with the internal clock and spikes shorter than three clocks are filtered out The output for I2C is a special pad designed to conform to the 12C specification Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 114 Philips Semiconductors UM10120 m Volume 1 Chapter 11 I C interfaces INPUT FILTER zen L1 OUTPUT SHIFT REGISTER STAGE BIT COUNTER S ARBITRATION amp a SYNC LOGIC z INPUT TIMING amp FILTER CONTROL SCL LOGIC OUTPUT SERIAL CLOCK STAGE GENERATOR I2CONSET I2CONCLR CONTROL REGISTER amp SCL DUTY I2SCLH CYCLE REGISTERS I2SCLL Staus gt STATUS STATUS bus gt DECODER REGISTER I2STAT E 8 Fig 26 I C serial interface block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 115 Philips Semiconductors UM1 01 20 m Volume 1 11 6 2 11 6 3 11 6 4 11 6 5 Chapter 11 I C interfaces Address Register I2ADDR This register may be loaded with the 7 bit slave address 7 most significant bits to which the 1 C block will respond when programmed as a slave transmitter or receiver The LSB GC is used to enable general call address 0x00 recognition Comparator The comparator compares the received 7 bit slave address with its own slave address 7 most significant bits in IBADR It also compares the first received 8 bit b
414. ysteresis In normal operation this hysteresis allows the 2 9 V detection to reliably interrupt or a regularly executed event loop to sense the condition Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 40 Philips Semiconductors UM1 01 20 ai Volume 1 Chapter 3 System Control Block But when Brown Out Detection is enabled to bring the LPC2131 2 4 6 8 out of Power Down mode which is itself not a guaranteed operation see Section 3 8 2 Power Control register PCON 0xE01F COCO the supply voltage may recover from a transient before the Wakeup Timer has completed its delay In this case the net result of the transient BOD is that the part wakes up and continues operation after the instructions that set Power Down Mode without any interrupt occurring and with the BOD bit in the RISR being 0 Since all other wakeup conditions have latching flags see Section 3 5 2 External Interrupt Flag register EXTINT OXEO1F C140 and Section 18 4 3 Interrupt Location Register ILR OxE002 4000 on page 202 a wakeup of this type without any apparent cause can be assumed to be a Brown Out that has gone away 3 13 Code security vs debugging Applications in development typically need the debugging and tracing facilities in the LPC2131 2 4 6 8 Later in the life cycle of an application it may be more important to protect the application code from observation b
415. yte with the general call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested Shift register IZDAT This 8 bit register contains a byte of serial data to be transmitted or a byte which has just been received Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT While data is being shifted out data on the bus is simultaneously being shifted in I2DAT always contains the last byte present on the bus Thus in the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in I2DAT Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the 12C block immediately changes from master transmitter to slave receiver The 12C block will continue to output clock pulses on SCL until transmission of the current serial byte is complete Arbitration may also be lost in the master receiver mode Loss of arbitration in this mode can only occur while the 12C block is returning a not acknowledge logic 1 to the bus Arbitration is lost when another device on the bus pulls this signal

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