Service Manual - Basic Four Model 2460 Fixed Media Disk Drive
Contents
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4. CHAPTER 4 SPARE PARTS LIST REMOVAL REPLACEMENT PROCEDURES 4 1 INTRODUCTION This chapter contains the spare parts list Table 4 1 and removal replacement procedures Figure 4 1 shows component locations TABLE 4 1 SPARE PARTS LIST Item MM Part Number Number Number Description 1 290000 B903028 01 Disc Controller PCB 2 290010 200098 Main Logic PCB i 290020 200083 Motor Control PCB 4 290030 200138 Terminator 5 290100 400384 001 Power Supply Assy 6 293010 330410 Head Disc Assy 4 1 MAIN LOGIC PCB TERMINATOR PCB MOTOR CONTROL PCB POWER SUPPLY HEAD DISC ASSEMBLY Figure 4 1 Component Locations 4 2 REMOVAL REPLACEMENT PROCEDURES Removal Replacement procedures are given for spared parts 4 2 1 8 9 10 HEAD DISC ASSEMBLY HDA Remove ac power from host CPU Open host CPU cabinet to gain access to Disc Drive Remove ac power from Disc Drive power supply Remove four screws securing HDA to host CPU cabinet CAUTION When removing connectors J6 and J7 R W Heads and Servo Head be careful not to bend the pins Damage may occur to the printed wiring Disconnect and tag all cables and connectors from Main Logic PCB Remove Main Logic PCB located on top of HDA Remove Motor Control PCB located on bottom of HDA Remove dc power supply located on bottom of HDA Replace Disc Drve and reverse steps 8 thru l Ensure that all cables and connectors are secure 4 2 2 POWER SUPPLY A
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7. is found the shift register This is the processor clock that is used to define the beginning and end of the data processing cycle in the processor On the rising edge of this clock all data from the current cycle is strobed into desti nations and the new instruction for the upcoming cycle is strobed into the instruction pipeline register This is one of the major clock signals that controls the processor This clock overlaps and lags TO This clock defines the loading of the next fetch address for the processor instruction Write or Sync Detected WRITE and SYNDET This signal is the logical OR of the signals X H or This is the differential balanced line write clock to the disc unit This signal is the servo clock re transmitted by the controller This is done to absorb some of the cable and interface delays This is the serial data that is to be written on the disc during a write operation All data to the disc will pass through this line WDTAX WRITE ZERO ZEROR ZROSAV X or 1 This is the differential balanced line write data signal to the disc unit This passes all data signals to be written to the disc This flag is controlled by the processor It is used to control the direction of data flow to move data from the memory to the disc This signal indicates that the general counter has counted down to zero This is the raw zero result flag from the 2901 This is the saved output of the zero
8. outlet The measured voltage must be less than 1 8 volts ac b Switch the source circuit breaker off Measure the resistance between the green and white wires at the wall outlet The resistance must be less than the value shown below for the applicable circuit breaker rating CB Rating Resistance 15 amperes 0 30 ohms 20 amperes 0 25 ohms 30 amperes 0 15 ohms If either measurement in steps a or b above is not less than the value given request the customer to provide a power source that meets these requirements Remove cabinet covers to gain access to the Disc Drive Disconnect and tag all cables from the Main Logic PCB connectors J2 bus and J9 radial Disconnect power supply plug at rear of cabinet Lock Spindle and Head Carriage locks Remove the four screws holding drive to host CPU cabinet Remove the Disc Drive from the cabinet Make pre power checks refer to paragraph 2 3 1 Replace Disc Drive in cabinet Unlock Spindle and Head Carriage locks Reconnect all tagged cables Reconnect power supply plug at rear of cabinet Replace covers Plug ac line into power source 2 3 2 3 1 PRE POWER CHECKS Verify that the input primary power voltage and the Disc Drive power supply are configured in the same range 1 following ac voltage ranges are available in the Disc Drive 100 120 220 and 240 volts ac 2 select the correct voltage range to match the ac input voltage locate the Voltage S
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11. 144720 CR11 iE 1N4739 SCR1 50563153 cro t 1N4720 I I I I I I I I I I 1 I CR10 1N4004 l I Q I I 1E9 IN 164 OUT o CR12 I 1N4004 I 1 cidem m LEE J Reference Only Will Not Be Maintained 24V 5 AMP 7 AMP PECK 24V RETURN 5V 4 AMP 5V 12V RETURN 5V 2 AMP 12V 0 3 AMP 5 18 SIC en 4 zn 4 eat Iv var Did b 3H2S 1 i I I t I i 1 5 4104 l HITOS HWOS b SOLIINNOD A EN eaa 377 A4 av eae di T RENI t I 1 l l I i IST TTD m 7 oy 4 l AZI NSF er LIAM AOBZ NO v2 217 Rea A ANANI APZI A007 vb EE Ig ev 5 9 gt AUN Abet 122 30O123 vvO2 5 7023 a 205400 av 3 7 N n SORA 53 2 1029 NS me ew e m 55 95 72 YIWAOYSN HL 2 20112373S FOVLION Base 5 19 Reference Only Will Not Be Maintained 1N3A1Y3Hl 39v3uns XOL BN ENE 3SIMY3HLO ATAAW AS S Pam SS31NN 39Nvu31O1 LAS PIS wesen 5 20 Reference Only Will Not Be Maintained Wve9eva QDLPVNIHIS uu gon 39Nvu3101 El 687002 J e sr
12. 3 cm Width 16 6 inches 42 2 cm Depth 20 0 inches 50 8 cm Weight 47 pounds 21 3 kg POWER Ac Power 100 vac 120 VAC 220 VAC or 240 VAC 50 or 60 Hz 425 Watts Max De Power 24 VDC 5 7 55 VDC 52 DA 5 VDC 5 4A 24 VDC Return 12 VDC F 52 0 7A 1 3 TABLE 1 1 SPECIFICATIONS continued Parameters Characteristics ENVIRONMENTAL 1 4 Temperature Humidity GENERAL Capacity formatted Number of discs Number of data heads Number of data cylinders Number of Diagnostic cylinders Bytes per cylinders Bytes per track Track density Recording density Data transfer rate Recording code Interface code Rotational speed Rotational latency average Rotational latency maximum Positioning speed Single cylinder Average Maximum Start Time Stop Time 65 F to 75 F 18 to 24 C 40 to 60 non condensing 66 Megabytes 1 3 1116 0 1115 excluding diagnostic 5 2 6 with Switch 10N 5 ON 1118 1122 60 480 20 160 960 Tracks per inch double density 6 430 Bits per inch 1 04 Megabytes per second 3 100 RPM 9 7 milliseconds 21 5 milliseconds Maximum Milliseconds Typical Milliseconds 10 8 48 45 90 85 30 seconds 60 seconds CHAPTER 2 INSTALLATION AND OPERATION 2 1 GENERAL This chapter contains complete installation and operation instructions for the Disc Drive 2 2 UNPACKING PAC
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15. DURING WRITE DATA MOVES TO REAR OF WINDOW Figure 3 6 3 5 FAULT ISOLATION Table 3 1 lists the Fault Isolation procedures for the Disc Drive lists the Status Bit information troubleshooting the Disc Drive TABLE 3 1 Data Window Adjustment Table 3 2 Both tables are designed as an aid in FAULT ISOLATION Spindle Rotation Rotation does not start Spindle lock Incorrect or missing voltage at Main PCB connector J4 OFF signal J4 4 is 5 VDC should be volts for rotation Defective Motor Control Assembly Suggested Action Place in Unlock position Check power supply Check microprocessor reset signal on Main Logic PCB should be false Check Power On reset POR should be false Check power reset PRST should be false Check J1 5 of Motor Control Assembly for 12 volts LED voltage Check fuse in Motor Control Assembly TABLE 3 1 FAULT ISOLATION continued Spindle Rotation Possible Cause Suggested Action Rotation does Defective Photocell Check for open LED defective not start Circuit Board connector or phototransistor Defective Spindle Manually rotate spindle in clock Motor wise directly only viewed from bottom to ensure motor is not binding If motor is binding replaced Disc Drive NOTE Rotation in opposite directions may damage disc Spindle rotates Carriage Lock Place in Unlock position and stops after about one Defective Motor Replace Motor Control
16. NOIINNILS3G 1009 1 1101p re i pu OH3H15 2000 2000 e 191597 u a i wW15H85 989998 90101 2000 8OSbL vag 6 1N223 OL SLISPL 9090 E 7008 6 A4 7 Reference Only Will Not Be Maintained 30 HS 620 06 2 8912100103 nos aiseq 3 H 14HS O 13HS 4 AYIHO 2 AYINO az GGG 24194060 U t d 761714101616 Zi 9208 tabla tet 211 0 68 q owes 6615 lt 2 Zi W YH er wea 0 4 49526 4 A4 8 Reference Only Will Not Be Maintained 40 HS Buonecasos nos 3iseq was enga 2 Line1 O Al 93 AG rt 196 TE weg 8 3 168 2 HLdHS S 1iHS 9 A4 9 Reference Only Will Not Be Maintained 40 HS m le 620806 12 o ssec 3iseq 7 lt r 93dgQ1M 164 cl 2 O SCHEITERN zava c LSISbL ort z DLESIL 9 gt Sen 2 d 9 T n gt s y MO z ea 2wa 9 5 61 3 vet S wa 6 ae G i SIE 5 9 mE gm Si 13 0 9 1 ind Ga O x lt quel NENT omadi C aE gt sum
17. R46 Set input to 1 Volt Division 0 1 Volt Division with non indicating probe Vertical display mode to ADD Channel 2 INVERTED Position trace near top of graticule Time base 0 2 ms TRIGGER SLOPE TRIGGER SOURCE Channel 2 dc coupled NOTE Adjust R351 near R46 for 5V Figure 3 5 ADJUSTING R351 Figure 3 5 Write Current Adjustment 3 4 3 DATA WINDOW ADJUSTMENT For this adjustment you must first write all ones then make the adjustments while reading all ones Do not use Head 2 Do not use any tracks which could contain customer data Write as many sectors on one track as possible for best display With an oscilloscope use the following procedure refer to Figure 2 3 for adjustment location 3 8 Scope Tektronix 465 or equivalent Probes Two X10 attenuation Channel 1 to TP13 Window ground to TP2 Set input to display 0 5 Volt Division 50 MV Division with non indicating X10 probes Channel 2 to TP9 Data ground to TP2 Set input to display 0 5 Volt Division 50 MV Division with non indicating X10 probes Vertical display mode CHOPPED Channel 2 should NOT be inverted Time base 0 1 us with X10 mag TRIGGER SOURCE Channel 1 dc coupling NORMAL mode Adjust R32 so Positive Going edge of Data is in center of low going Window pulse Figure 3 6 NOTE It is normal for the display to jitter FRONT OF WINDOW NOTE DURING READ REAR OF WINDOW
18. SY 1 1 21 0 272 2 2 AS 2041 LOGI soar 006 Sv TNI 200W Mad OUN 135 57 b9 9 29 19 69 85 4S 95 55 oS S 25 15 Id 2001 7001 1001 LOgQ TNI 1d GOUW PON 73S 1 1 El er 2 C 1 21 21 1 Et 27 21 2 2 2 1 1 2 2 amp er 2 21 2 2 6 2 21 21 2 2 62 1 100 26 Siuw LSAW Livw 2Ggw CN GNI 9 VIN COGI XIDI SPIN EGIW gw 200 XXLF EUW E ON ILYN 1009 bIUN 216014 AS ASt ms asr ung Nm NINO n E Oe OI tg ld E OVW auvWwc Dow 2001 2 1 2000 4084 290 VWOSH 9 JOYNI UND ANI QI UN 6OUW 000 LOUW 19H 20 2 2 2 1 1 0 zn 1 1 21 2 4 21 6 1 1 16 Reference Only Will Not Be Maintained i amp iii i I a i i od e M HC EN H nn i i i H wid HE s RARO i i H i i i 05 DRIN mdr io
19. The Microprocessor does three things for each instruction cycle it executes the present instruction function it fetches the next instruction and it computes the next fetch address next address and stack logic The Microprocessor does the following 1 Translate I O commands issued by the CPU into commands that the Disc Drive recognizes 2 Performs error checking of information passed between Disc Drive and CPU 3 Detects particular conditions and then issues interrupt commands to the CPU 4 Provides Controller and Disc Drive status information to the CPU 5 Implements Direct Memory Access DMA transfer between Disc Drive and Main Memory 6 Sychronizes timing A2 1 3 DMA LOGIC The DMA Logic consists of the following 1 DMA Interface Logic 2 DMA Read Write Cycle 3 DMA Priority A2 1 4 INTERRUPT LOGIC The Interrupt Logic consists of a mask F F and an interrupt F F If the mask F F is set and the interrupt F F is set an interrupt will be sent to the CPU DMAINT A2 1 5 I O LOGIC The I O interface logic provides flags used for branch offset by the micropro cessor These flags are part of the command word which comes from the CPU or flags which indicate valid data is on the output data lines A2 2 2 1 6 CRC LOGIC The CRC Logic is responsible for generating and checking the cyclic redundancy check bytes for the header and data records on the disc A2 1 7 RADIAL LOGIC The Radial Int
20. results bit from the 2901 to be used for testing in the next processor cycle 9 SECTION 4 REFERENCE DATA A4 1 92 v9 C929 wen P wen nea an ton Ewan Ewen cog GOO CT Da Exe OM pm OM pum 385 Foi 2241 s o gt Lu sao ra m iem EF La In Den eaen Pisa gaon Eoen eaen 5 zm SID 0ID lt pu gt Len j iren ren rn ren tren tma tren Iren 9u ID t Hn t o Dem Hen ASSY 19 R een f oen e 99N ten sen toon SLI MD HHO CID lt gt LIO HO IND gt l4 an Caen Esen fan aen Pan Son Saag ezo D i am sen f sen aen 5 asa Eon gaen t aon am HT Sr tam pro Bu z00 ID eg D C omn fon f oen Fosa Poen Esen t LID FU SID CIO OD 18 ely go A 918 6 vin Even t ven ven ven v ven ven ven f von 292 O 29 ET O 19 Gi A4 2 Reference Only Will Not Be Maintained Zu MC n INN t Ei LNOD 23 15 Vis 90826 19815 ANOS SELL A uonessocuco ONIMV8O 3195 LON 00 o01 S310NV 010 XXX 0 XX vex 931312345 3SIMB3HLO SS31Nn
21. the 2460 Fixed Media Disc Drive to a Basic Four data processor in a system configuration See Figure A 1 for a typical system interconnect diagram BUS CABLE CONTROLLER RADIAL CABLE TERMINATOR Figure A 1 System Interconnection Al 2 PHYSICAL DESCRIPTION The Disc Controller hereafter referred to as the Controller is a single PCB plugged directy into the main card cage of the processor system Two cables Radial Cable P N 902622 and Bus Cable P N 902687 connect the controller to the Disc Drive complete pin to pin listing of these cables is given in Figure A 2 Al 2 CONTROLLER PCB Figure A 2 BUS CABLE UNIT SELECT TAG RADIAL CABLE WRITE CABLE SERVO CABLE N I READ DATA e READ CLOCK ____ dg WRITE CLOCK SEEK END UNIT SELECTED SECTOR ne FINDER 07 WON Ol C EA 4 Q tO 1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 5 7 4 3 2 4 4 4 4 Q r2 ONN TAG 1 TAG 2 TAG 3 CYLINDER HEAD ADDRESS SELECT CONTROL 1 WRITE GATE 2 READ GATE FAULT CLEAR REZERO 2048 READ STATUS USED FOR HIGH ORDER CYLINDER ADDRESS DURING TAG 2 TIME BIT BON ES z a pas BEEN EE _ 256 o s DISC MAIN LOGIC PCB Disc Interface and Tag Bus Decode Al 3 PHYSICAL REQUIREMENTS Al 3 1 PHYSICAL ENVELOPE The Controller is housed on a standard Basic Four printed circuit board PCB with a
22. 3 Physical Envelope e lt s lt e o e s wc cw o o o Mounting s e s e e e e o e o o o Al 3 Data Reliability 0 lt 0 0 0 0 0 o Al 3 MAINTENANCE General Description lt o A2 1 Controller ROM 0 e o o 2 l Microprocessor s s s o o o 2 2 DIA LOSTO s Wen DID Interrupt Logic e s lt e e e ow a LIO LOSL du ee OO re ees wD CRC Logic s s 0 0 0 0 c e A2 3 Radial Logic 4 4 4 s s s e e e e e 0 e e e e e o Bus Logic 6 e e e o v 2 3 Interface Requirements s 0 0 2 3 Electrical Interface s s 0 0 o o o 2 3 CPU Interface s e e e o o o 2 3 GLOSSARY OF SIGNAL NAMES Glossary e A3 1 REFERENCE DATA LIST OF ILLUSTRATIONS Page System Interconnection e Disc Interface and Tag Bus Decode s lt Al 2 Block Diagram of Contr oller amp Uc A 1 A iii APPENDIX A SECTION 1 INTRODUCTION 1 1 GENERAL DESCRIPTION The Disc Controller provides the interface between the CPU and Disc Drive It interfaces
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24. 5 ASL 6 LAS 6 LHS SZ ERS g 77 HLHS Vv3HSIV BO isa 6 LHS 737997 ls 6LAS A 2799 eins 6 LAS Ear 6495 6 LAS gar t Sls SOLES ZA FLAS LHS HHH sas 9 05 27 LHS 23750 FSAZLIT 208 ii LIT 39 Oo R SAS la 9 LAS 5 572 E Es 77 22H if b 2 XONI d 5 Q OST D LHS SVG Jo jg wr age s 495 nC 2 ci Re 277 gt 7H m3 2 215 22150 574 22 DI It s 50171000 UU wi As IT ove 7E Y EU ENE MIS EH 57 20 lt 7 27 2 Y 297 7129 4 C wl 1 l1 z Aue 2766 ee TS 7 207 27189 x397 872 epo H gt 2155 7 24 0 Z 2 g ASt ey LHS DET THEY 62 LFO PIT 5 10 Reference Only Will Not Maintained 660002 60002 6 viaa xj mes g 0599 Du WVYDV O DLLVIN3H2S su ES PZ e LHS E LHS 0 4 4195 Ol LHS 2 LAS LHS 4 185 8 IHS GLAS 74195 7175 7 185 49 GLAS LHS l 4 MN 5 3185 LIMA 742 NO NC 173 ose 9 ESOS Ed AGI j DS Ge ATVIS OS 09 gt 8957 I AS 9 ee Ha gels S
25. Assembly minute Control Assembly Defective Photocell Replace Disc Drive Circuit Board Speed Control not Defective Main Logic PCB being sensed by Microprocessor Spindle Motor has Replace Disc Drive excessive drag Spindle rotates Fault Condition being Check Fault Status but unit does sensed not come Ready or Ready condi Intermittent power Replace Power Supply tion comes and supply failure goes Defective Main Logic Replace Main Logic PCB PCB Defective Motor Replace Motor Control Assembly Control Assembly Defective Disc Drive Replace Disc Drive 3 10 TABLE 3 1 Incorrect state on Unit Selected J9 21 Selected unit does not issue status Select unit does not accept commands Select Unit issue Seek Error Select Unit fails to issue Index Symptom Fails to move to new Address Continuous Seek Error condition FAULT ISOLATION continued Command Status Transfers Possible Cause Suggested Action Device address select switch 10N Open Cable Detect true Jl J2 pin 28 Unit Select Tag or Unit Address missing or mistimed Device Not Ready Tag and bus data malfunction Defective servo action Defective circuit Servo Head fails to READ Refer to Table 2 1 for switch definition Check controller cable and connectors Check controller cable and connectors Replace Main Logic PCB Check controller cable and connectors Replace M
26. Basic Four Model 2460 Fixed Media Disc Drive BFISD 8052 Service Manual Basic Four Information Systems The information contained herein is proprietary to and considered a trade secret of Assistance Inc All rights reserved No part of this publication may be reproduced recorded or stored in a retrieval system or transmitted in any form or by any means whether electronic mechanical photographic or otherwise without prior written permission of the Basic Four Information Systems Division of Management Assistance Inc Ail Rights Reserved BFISD 8052 Copyright 1981 by Management Assistance Inc All specifications are subject to change without notice Basic Four and MAI are registered trademarks of Management Assistance Inc Printed in the United States of America Basic Four Information Systems Division Management Assistance Inc 14101 Myford Road Tustin California 731 5100 iy ae CHAPTER 1 ER W N IS tS NNN Y ON Qn amp Co CHAPTER 2 N NN NN NN N N N e Un Co CO CO Co FS Ny S e Co N m CHAPTER 3 N Q N B3 N om CO CO CO CO CO Uy CO LI CO LI UW Qn CO IS TABLE INTRODUCTION OF CONTENTS General Description Figure 1 1 Physical Description Head Disc Assembly Mai
27. KING PROCEDURE The Disc Drive is normally shipped as part of a data processing system and unpacking packing instructions are included in the appropriate system manual When the Disc Drive is shipped as a replacement unit the following procedures should be followed 1 Visually inspect the container for damage Report any damage immediately 2 Remove Disc Drive from container and place on work surface 3 Visually inspect for loose bent or broken parts Report any damage immediately 4 The head carriage and spindle locks refer to paragraphs 2 2 1 and 2 2 2 are in the locked position for shipment If received in the unlocked position DO NOT INSTALL THIS DISC DRIVE 5 When shipping a Disc Drive back to the factory ensure that the spindle lock and head carriage lock are properly installed locked and the Disc Drive is packed to prevent damage in shipment 2 2 1 HEAD CARRIAGE LOCK Power not being applied to the unit place the Disc Drive in a flat position with the Main Logic PCB facing up The head carriage lock is located at one end of the unit indicated by arrow on the mechanism CAUTION Avoid manual rotation of the spindle or movement of the carriage Damage to the disc surface may occur 2 1 Pull up on the head carriage lock until free from its locked position Rotate the head carriage lock to the unlock position as shown in Figure 2 1 The head carriage lock must be placed back in its locked position when th
28. ROL WRITE GATE READ GATE e BE A FAT CLEAR 3 FAULT CLEAR 1 2 16 x p USED FOR HIGH ORDER CYLINDER ADDRESS DURING TAG 2 TIME U IT EUN ENE EE ENTER 51 26 7 16 ENEN Px DISC MAIN LOGIC PCB 2 7 2 3 3 DC VOLTAGE CHECK Power is applied to the Disc Drive from the host CPU control panel To apply power complete the following steps refer to system manual for detailed system information 1 Place power switch in ON position 2 When READY indicator comes on the dc voltage checks may be done using the following procedure Locate connector J3 the Main Logic PCB of the Disc Drive b Test the following voltages Connector J3 Voltage Check Pin 1 GND Pin 2 24VDC 1 2VDC Pin 3 5VDC 0 25VDC Pin 4 12VDC 0 60VDC Pin 5 5VDC 0 25VDC Pin 6 GND 3 If voltages are not within tolerance refer to paragraph 3 4 1 2 4 CONTROLS AND INDICATORS Controls for the Disc Drive are located on the host CPU control panel There are two indicator lamps LEDs mounted on the Main Logic PCB near J8 A green lamp will indicate a READY status A red lamp will indicate a FAULT status Connector J8 is provided to test the following signals Connector J8 Function Pin 3 READY Pin 4 GND Pin 5 ON CYL Pin 6 FAULT Pin 7 PWR ON Pin 8 T5V Note Pins 1 and 2 not used 2 8 2 5 SWITCHES AND JUMPERS Drive Address Write Enable
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30. SSEMBLY Remove ac power from the host CPU Open host CPU cabinet to gain access to Disc Drive Remove ac power plug at rear of Disc Drive power supply Remove Disc Drive refer to paragraph 4 2 1 Disconnect dc power supply connector J3 from Main Logic PCB Remove six screws securing power supply to the deckplate Remove power supply Replace new power supply in Disc Drive and reverse steps 7 thru l Apply power to host CPU 4 2 3 MAIN LOGIC PCB AND MOTOR CONTROL PCB When removing PCBs disconnect and tag all cables and connectors Ensure when replacing PCBs that all cables and connectors are secure NOTE When replacing Main Logic PCB remove and save terminator CHAPTER 5 REFERENCE DATA Title Main Logic PCB Schematic Motor Speed Control Schematic Power Supply CP353 1 Power Supply Model 2981 Filtered Power Supplies Terminator PCB Schematic Drawing Number 200098 200099 200083 200084 17048 2981 902 330357 200138 200139 a CORRER EEE PEER Dar 8 Jm SEE LEBEN BRE SRI EPEE OW BS C ara E a re af Lal zB Ut D Ded hr p 5 210 tw AL 4 5 o Rr doe o 1 a h ERBER FARA DE 8 m z g TP36 154 26 7 a
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32. ain Logic PCB See Head Positioning Servo Replace Main Logic PCB See Head Positioning Servo Head Positioning Servo Possible Cause Command transfer circuitry defect Defective circuitry or connection Suggested Action Replace Main Logic PCB Defective servo circuitry on Main Logic PCB If fault continues with operational spare installed and spindle speed and write cir cuits are not the source of the fault replacement of the disc drive is recommended Fault connection to servo read head check J6 Fault connection to voice coil actuator check J5 Incorrect voltage check J3 Carriage locked 3 11 TABLE 3 1 Symptom Seeks to incor rect cylinder address Symptom Fault is set with each attempt to write data Data is written incorrectly and faults does not set Symptom Reads header fields and data fields correct ly but will not read newly written data or servo system Head Positioning Servo Possible Cause Defective circuitry FAULT ISOLATION continued Suggested Action Defective signal from controller or fault in the interface cable Defective circuitry on Main Logic PCB If symptom continues with operational spare installed and controller and cable are not the source of the fault replacement of the disc drive is recommended Seek ma be correct and method of checking for correct seek locatio may be defective This could be caused
33. al Block Diagram CYLINDER NUMBERING HEA DATA BAND DATA BAND 2 D LANDING ZONES 4 A DATA BAND 0 SERVO BAND CYLINDER 1120 CYLINDER O HEAD ARM ASSEMBL HEAD 1 UPPER ARM HEAD 2 T A DISC in SERVO HEAD HERD LOWER ARM SIDE VIEW OF DISC AND HEADS Figure 3 2 Data Head Positions 3 3 DIAGNOSTIC TESTS There are two types of diagnostic tests available for the Disc Drive Silver A5 and FORMAP For a complete functional description of Silver A5 and FORMAP refer to the appropriate User s Manual 3 3 1 GENERAL DESCRIPTION OF SILVER A5 Silver A5 is divided into two groups 1 Group 1 is designed to check most controller functions and the disc drive s ability to seek and read 2 Group 2 uses the Diagnostic Cylinders to write and format Checks are performed on the controller s ability to detect various errors such as ID Alternate Cylinder and CRC In order to run Group 2 the Manual Intervention option must be selected 3 3 2 GENERAL DESCRIPTION OF FORMAP FORMAP s basic function is to format the surface of the disc create a map of all flaws and to store the map on the subject disc However several of FORMAP s options can be used for diagnostic purposes The six options are 1 Surface Read will read the full surface of the disc and report all exceptions to normal status which is 40 HEX 2 Fault Map Report will display the contents of the fault map which contains all flagged tra
34. al is the controller reset from the system It is used to reset all of the important functions in the controller for power on or for the bootstrap This signal generated by the DMA transfer logic is used to indicate that the first third of a DMA transfer cycle is underway This output of the DMA control ROM is used to set the address enable flip flop on the next clock edge This is the received servo clock from the disc unit This clock is used to time the flow of data from the controller to the disc unit during a write data transfer The clock is also re transmitted to the disc unit H or L These are the differential balanced line signals for the disc servo clock This clock is always kept in sync with the servo pattern on the disc surface Sector This signal from the disc unit indicates that the heads are currently positioned over the beginning of any sector except sector Zero This signal is used to set the D flag any time that the D register is loaded from the processor This signal is used by the processor to set the DMA request latch This output of the control ROM is used to set the strobe flip flop on the next clock edge This is serial data that has been read from the disc This signal is zero at all times when the read flag is not set Serial output of the parallel to serial shift register Set the S flag On the Count of 5 This term is used to set the S flag during read operations in anticipati
35. alanced line signals that carry read data from the disc unit to the controller This signal is the logical OR of the ready and on cylinder signals from the disc unit When this signal is true a data transfer may occur This flag is controlled by the processor It is used to control the flow of data from the disc unit to the memory This signal from the disc unit is used to determine that the disc unit is rotating and up to speed and no fault exists This signal is used by the processor to reset the MASK and INT flip flops XX 00 thru 25 These are the raw ROM outputs that feed the inputs of the instruction pipeline register These bits are not used any where else since it is the output of the pipeline register that is used while the next instruction fetch is in progress ROMXX ROMYY RSHFT RST RTXX SADDEN SCLK SCLKX SCTR SDFLAG SDMAQ SDMST SERIN SEROUT SETS5 XX 00 thru 25 These are the outputs of the ROM pipeline buffer that contains the instruction for the 2901 part of the processor This buffer is loaded on the rising edge of TO 26 thru 39 These are the raw ROM output bits that are used directly in the next address computation logic The results of the next address computation are strobed into the address register at the rising edge of TO This signal is used by the processor to control the inputs to the shift registers in the 2901 for a right shift operation This sign
36. and Diagnostic mode are selected on Switch ION located on the Main Logic PCB see Table 2 1 for Switch selection The Sector switch 12K is also located on the Main Logic PCB see Table 2 1 for Switch selection TABLE 2 1 SWITCH SELECTION Switch 10 1 Drive Select Address Bit Binary Weight 1 Drive Select Address Bit Binary Weight 2 Drive Select Address Bit Binary Weight 4 Reserved Diagnostic Mode Reserved ON Write Enable All Data Heads 8 DUST ON MENO AO Sector Number SW No Position Binary Weighted 1 OFF Not used FF 0 1 ON 32 64 Must be in off position SW5 must be placed in ON position when using Diagnostic mode A11 OFF Drive 0 2 9 Jumpers are preset at the factory and shall not be removed Verify all jumpers are in correct location 2 10 Three Pin W4 1 2 we 2 3 W7 1 2 Wi4 2 3 W11 1 2 W12 2 3 W16 1 2 1 W2 W3 W5 W6 W9 W10 W13 Jumper contacts are listed as follows Two Pin CHAPTER 3 MAINTENANCE 3 1 GENERAL DESCRIPTION This chapter provides a block diagram functional description adjustment procedures and troubleshooting procedures 3 2 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION FIGURE 3 1 The Parallel Interface communicates with all functional assemblies of the Disc Drive and the Controller Its major function is to control and monitor head positioning spindle speed and status information The Servo
37. ansactions X 0 thru 7 This is the processor output bus data on this bus is moved from the processor to any of several destinations Set Head Tag This signal is used by the disc unit to determine that the data on the disc control bus is head address information thru 7 This is the CPU input bus This bus is used to transfer information from the controller to the CPU This signal from the disc unit is used to indicate that the heads are currently positioned over the beginning of the track which is also the beginning of sector zero Literally In Sync The state of this flip flop is used to permit data flow when the bit counter is in sync with the data flow This signal in the DMA interrupt logic is used to interrupt the CPU any time this signal is true and MASK is also true 1 thru 3 These are the 1 0 control signals from the CPU decoding these bits the appropriate I O action can be determined A3 3 IOACTV LDADRH LDADRL LDBREG LDCLB LDCMB LDDREG LDLDB LDPC LDSR LDSTAT LDUDB LSHFT MASK MDOX A3 4 This signal in the I O control logic is true any time that the c troller detects its address in conjunction with a COXX command signal remains true for the duration of the I O transfer Load the High Address Register This signal is used by the proc to strobe the contents of the processor output bus into the uppe byte of the DMA address counter Load Lower A
38. by a read write fault Write Data Transfer Possible Cause Incorrect switch setting or circuit defect Reads data difficultly Suggested Action See Table 2 2 for switch definition Multiple heads selected can be checked at TP20 which will be high if more than one head is selected Act Unsafe condition is checked at 1 which will be high if there are not write transitions with Write Gate true or write transitions with Write Gate false See following section Read Data Transfer Read Data Transfer Possible Cause Defect in write oper ation Suggested Action Replace Main Logic PCB TABLE 3 1 FAULT ISOLATION continued Read Data Transfer Possible Cause suggested Action Defect in Read cir Check all cable connections cuitry Replace Main Logic PB Replace terminator Symptom Fails to read but will per form a write operation with out a Fault If read error persists after replacement of Main Logic PCB and terminator and if cable connections are correct it is possible that the format being used is erroneous If format is correct replacement of the disc drive is recommended TABLE 3 2 STATUS BIT DESCRIPTION 0 MULTIPLE HEAD SELECT indicates that more than one head was selected 1 NO WRITE DATA indicates that transitions in write current failed to occur with WRITE GATE active 2 NO WRITE GATE indicates that write curr
39. circuits head positioner assembly and Servo Head align the three Read Write heads over a specified track location The Servo circuits drive the heads to the landing zone upon detection of a low power condition or if both On Track and the Move modes are detected These circuits also monitor voice coil speed The Read Write heads and the Read Write circuits perform the reading and writing of flux changes onto the disc There are three data heads and one Servo head Head 1 and head 2 utilize the top surface head 0 and the Servo head utilize the bottom surface of the disc Figure 3 2 The Spindle Motor is a brushless permanent magnet dc motor The speed of the motor is controlled by a closed loop optical position encoder and a frequency to voltage converter The Serial Interface communicates with the Controller and handles the transfer of data and timing signals PARALLEL INTERFACE HEAD POSITION SERVO CIRCUITS HEAD POSITIONER SEQUENCING STATUS AND OTHER CIRCUITS CIRCUITS LINEAR VOICE COIL MOTOR READ WRITE HEADS HD2 SERVO READ AND R W CIRCUITS SERVO HEAD SPINDLE ASM BRUSHLESS DC MOTOR SPEED CONTROL CIRCUITS SERIAL INTERFACE DATA HANDLING CIRCUITS INDEX AND SECTOR MARK WRITE GATE WRITE CLOCK WRITE DATA NRZ READ GATE READ CLOCK NRZ READ DATA INDEX MARK SECTOR MARK SERVO CLOCK DESIGNATES DIFFERENTIAL SIGNALS Figure 3 1 Function
40. cks and their assigned alternate tracks 3 Selected Track Certification will read original data of a track store it test the track and if found bad or manually reassigned copy that data to the alternate track and flag the original as bad REQUIRES OPTION 4 TO HAVE BEEN RUN PREVIOUSLY IN A FAULT MAP CREATED BY OPTION 4 4 Full Surface Certification will destroy the contents of the whole disc test it for flaws create a new map and write a bootstrap in sector zero The serial is kept in the map and once assigned cannot be changed REQUIRES AUTHORIZATION 5 Logical Sector to Sector Head Cylinder will convert the logical sector number to the location of the disc surface by physical sector head and cylinder 6 Sector Zero Recovery will rewrite the bootstrap in sector zero using the serial stored in the map REQUIRES OPTION 4 TO HAVE BEEN RUN PREVIOUSLY IN A FAULT MAP CREATED BY OPTION 4 3 3 3 4 ADJUSTMENT PROCEDURES 3 4 1 POWER SUPPLY ADJUSTMENTS One of two types of power supplies are found on the Disc Drive P N CP353 1 and Model 2981 Regardless of which type is found the Disc Drive must be removed from the system before the power supply can be removed for adjustment Once removed the power supply can be placed near to and recon nected to the Disc Drive To remove power supply for adjustments use the following procedure 10 11 12 13 3 4 NOTE There is no power switch l
41. contains the necessary circuitry for positioning the heads and transferring data and status information via the Controller to a host CPU This manual contains physical and functional descriptions installation operation procedures spare parts lists and maintenance procedures Figure 1 1 Model 2460 Fixed Media Disc Drive 1 1 1 2 PHYSICAL DESCRIPTION The Disc Drive stores data on both sides of a single disc using two moving heads per surface full head area is dedicated to servo information for track following seeking and timing A microprocessor controls positioning during track seeks provides interface control and monitors disc drive operation The major assemblies of the Disc Drive are Head Disc Assembly HDA Main Logic Printed Circuit Board PCB Motor Control PCB Photocell PCB Frame Assembly Power Supply Assembly and Terminator 1 2 1 HEAD DISC ASSEMBLY The Head Disc Assembly is a contamination resistant enclosure which contains the disc spindle assembly voice coil actuator head carriage read write _ heads and filter assemblies 1 2 2 MAIN LOGIC PCB The Main Logic PCB contains all the circuitry associated with read write data transfers interface transfers head positioning and control 1 2 3 MOTOR CONTROL PCB The Motor Control PCB contains all the circuitry associated with driving the spindle motor This circuitry receives On Off command from the Main Logic PCB and spindle rotational feedback f
42. d 1 1 3 i 3 i Title Date pet T od t Covered Fold and staple H EE eer E dl i Name ipmen e ARE M bod doof sd i Address Manual Change Request Equ RE Rd WE NS e nb i 3 Service Information Systems 3 UL Q x a tion of requested changes Ip Reason for requested change Prepared By Manual No Pages effected Descr 6531916 QILINN IHL NI Q31IVN 31 AHVSS3O3N 3SV1SOd ON pj 08926 usn PIOJ N 10171 ou eouejsissy 3 UOISIAIG SWS SAS uoneunoju INOY 21529 38 TIM 39 150 VO VINVS 8857 ON LINHId 55775 15813 TIVW A1d34 SS3NISn8
43. ddress Register This strobe is used by the process to strobe the contents of the processor output bus into the lowe byte of the DMA address counter Load the Buffer Register This signal is used during data trans to load the D register from either the memory or the disc deper on the direction of data flow This signal is used by the processor to load the contents of the processor output bus into the lower byte of the general counter This signal is used by the processor to load the contents of the processor output bus into the high byte of the general counter This is a strobe generated by the processor that is used to load contents of the processor into the D register Load Lower Disc Bus Control Register This strobe which is gene by the processor is used to clock the contents of the processor put bus into the lower disc bus control register This signal is used by the processor to control the contents of control ROM page control flip flop Load the Shift Register This signal is used during the write c ation to parallel load the shift register with data This signal is used by the processor to strobe the contents of t processor output bus into the status register Load Upper Disc Bus Control Register This strobe is generated the processor and is used to clock the contents of the processor output bus into the upper disc control bus register This signal is used by the processor to control the inputs to th shift registers in th
44. e 4 1 4 3 4 3 4 3 4 4 LIST OF ILLUSTRATIONS Figure Model 2460 Fixed Media Disc Drive Spindle and Head Carriage Lock Disc Drive Voltage Selection e e o Main Logic PCB e e o Interface Cable Pin Assignments and Bus Functional Block Diagram Data Head Positions lt s o Power Supply Adjustments P N CP353 1 Power Supply Adjustments Model 2981 Write Current Adjustment o Data Window Adjustment e e lt o Component Locations lt o RI ub d dx AES Ne CO N i LIST OF TABLES 1 1 Specifications e e 2 1 Switch Selection 0 0 o 3 1 Fault Isolation s e e e o 3 2 Status Bit Description 4 1 Spare Parts List s s s 0 0 0 e o Decode rd 09 N OS FS AL N Page 1 3 2 9 3 9 3 13 4 1 CHAPTER 1 INTRODUCTION 1 1 GENERAL DESCRIPTION FIGURE 1 1 The Model 2460 Fixed Media Disc Drive hereafter referred to as the Disc Drive is a fixed media mass memory device used for data storage with a maximum memory capacity of 66 Megabytes The Disc Drive contains a single linear voice coil head positioner with three data read write heads and one servo read only head It has a spindle assembly with a single 14 inch disc and brushless dc drive motor It
45. e 2901 for a left shift operation XX 00 thru 14 These are the main frame memory address lines This signal in the DMA interrupt logic is used to enable the DMA interrupt request line to the CPU X 0 thru 7 memory This is the unbuffered memory bus from the main f This is a bi directional data bus MIDCY MRST MUXN NAX ODOX OFL OFLSAV ONCYL OUTEN POP 00 QOSAV Q7 Q7SAV ROSAV R7SAV This signal generated by the DMA control logic is used to indicate that the middle third of a DMA data transfer is now in progress This is the master reset signal from the CPU backplane lor 2 These are the raw clocks that are used to generate the signals TO and Tl During clock changeover these signals may con tain truncated clocks X 0 thru 3 These signals form the least significant four bits of the next processor address Since many different signals may be gated into these bus this forms the basis for N way branches X 0 thru 7 These are the output data lines from the CPU This information is used to determine the controller address or to transfer data from the CPU to the controller This is the raw overflow status bit from the 2901 This is the saved overflow bit form the 2901 to be used for testing in the next processor cycle This signal from the disc unit indicates that the disc unit is on a cylinder and not seeking Output Enable This signal is used to disable the disc b
46. e Disc Drive is moved SPINDLE LOCK Figure 2 1 Spindle and Head Carriage Lock 2 2 2 SPINDLE LOCK Power not being applied to the unit and the Disc Drive still in the flat posi tion locate the spindle lock near the center of the unit opposite the voice coil motor as shown in Figure 2 1 WARNING Ensure power has not been applied to the unit when the spindle lock is placed in its unlocked position The Spindle motor must not be manually rotated when unlocked At this time the fan is free to move and can present a hazard to the Service Representative Place the spindle lock lever in the unlocked position refer to Figure 2 1 The spindle lock must be placed back in its locked position when the Disc Drive is moved 2 3 INSTALLATION PROCEDURE The following procedures detail the necessary steps to be followed when installing a replacement Disc Drive l 2 3 10 11 12 13 14 15 Verify the power switch is OFF and the ac line cord is not connected Check that the ac line includes a third wire earth ground that meets or exceeds the requirements of the National Electrical Code This can be checked by the following procedures a Locate the circuit breaker that is to supply power to the host system With a digital volt meter set to measure 20 volts ac and the circuit breaker turned on measure the drop between the green and white wires at the power source for the system wall
47. e page control bits in the CPU DMACK DMAINT DMAR DMASTB DOXX DTAX E INSYC FAULT FX HTAG IDOX INDEX INSYNC INT IONX DMA Acknowledge This signal from the CPU is used to determine that the current DMA request has been granted and the next memory cycle belongs to the DMA logic This is the DMA interrupt request line in the CPU backplane This is the output of the DMA request latch This signal is true any time that the processor wants to initiate a DMA cycle This is the DMA request bus signal on the CPU backplane DMA Strobe This signal is generated by the DMA interface control logic This signal is true during the last third of the DMA cycle and is used to strobe read data into the controller and to advance the address counter This signal in the I O control logic is true any time that the signal IOACTV is true and the DOXX command is detected from the CPU This signal is used to transfer data from the CPU to the controller X 0 thru 7 This is the output from a multiplexer that can switch from either the shift register or the memory data bus into the S register Enable INSYNC This signal is controlled by the processor and is used by the processor to control the state of the INSYNC flip flop This signal from the disc unit is used to determine that the disc unit has detected a condition that could lead to the destruction of data The disc is therefore interlocked from further data tr
48. ee e 4 OI IOLUINIWYITL g Z reni ALON 3SIMH3H1O to sura A uam 22 SAL s v AS 2005 22 12 AS AP 2 8 lt ef ATVII ngi 742 NO 49 I i I XIIS re 0 I I LINVA SOLIIS SE det RON VP XIAN 45 AA RE PEP ORE 27 ST 5 2 lt lt 2 SOS i e TES REESE 127 s d Sv TUUM TS gt TEO e A ape tt NSS AA a A _ gt z _ LO gt 755 LINN 1 I 6 3 N i 1 U I I gt LINN 735 2 IM E 755 LINN 971 73S LINN ID 5 21 Reference Only Will Not Be Maintained APPENDIX DISC CONTROLLER FOR MODEL 2460 FIXED MEDIA DISC DRIVE SECTION 1 Al 1 Al 2 Al 3 Al 3 1 1 3 2 1 4 SECTION 2 2 1 ADI A2 1 2 A2 1 3 A2 1 4 A2 1 5 A2 1 6 22 147 A2 1 8 A2 2 A2 2 1 A2 2 2 SECTION 3 A3 1 SECTION 4 Figure 1 2 3 TABLE OF CONTENTS Page INTRODUCTION General Description lt 0 e Al 1 Physical Description s 0 gt e Al l Physical Requirements s s 0 Al
49. election PCB at the rear of the power supply mounted on drive frame Figure 2 2 VOLTAGE SELECTOR WAFER SLIDING DOOR ES si gt SAT S WAFER SLOT FRONT VIEW REAR VIEW Ta WY am ex FUSE PULLER Figure 2 2 Disc Drive Voltage Selection ae Voltage is selected by the position of this small PCB The fuse pull lever situated above the PCB is pushed to the left to remove the fuse b With the fuse removed the selected voltage is read directly from the PCB If a change in voltage is required extract the PCB and reinsert it so that it is properly positioned for the required ac voltage designation 100 120 220 240 ce Check the fuse value A four amp fuse is used with 100 and 120 volts ac a two amp fuse is used with 220 and 240 volts ac d Place the fuse pull lever in the extreme right hand position and insert the correct value fuse into the fuse holder e No power supply modification is required for changing from 60 cycle to 50 cycle sources 2 4 3 Locate the Main Logic PCB Figure 2 3 and verify that connectors switch settings and jumpers are in their correct position The connectors are listed as follows for Switch Settings and Jumpers refer to paragraph 2 5 Connector Jl J2 J3 J4 J5 J6 J7 J8 J9 2 3 2 INTERFACE CABLING Description Terminator connector or daisy chain cable connector from to another Disc Drive in system Bus cable connector to
50. ent was sensed when WRITE GATE was not active 3 OFF TRACK WRITE indicates that the R W heads were not within acceptable track following limits while WRITE GATE was active 4 READ ONLY indicates that WRITE GATE became active while the Disc Drive was not WRITE ENABLED 5 PLO LOCK ERROR indicates that the PLO signal was not correctly synchronized 6 NOT USED always zero 7 POWER FAULT indicates that spindle was already spinning when power was applied 8 MULTI TAG indicates that two or more tag lines were simultaneously active 9 READ AND WRITE indicates that both READ GATE and WRITE GATE were simultaneously active 3 13 TABLE 3 2 STATUS BIT DESCRIPTION continued 10 OFF CYLINDER indicates that the positioner was not ON CYLINDER while WRITE GATE was active SEEK TIMEOUT indicates that the positioner failed to return to track 0 with 900 msec or it failed to complete a seek operation within 130 msec SPEED ERROR indicates that the disc failed to reach or failed to run at operating speed GUARD BAND ERROR indicates that the positioner entered the inner or outer guard bands while performing a seek or restore operation ILLEGAL CYLINDER indicates that the disc file was commanded to seek to a cylinder address which does not exist in the drive DIAGNOSTIC CYLINDER ERROR indicates that the positioner has not moved to one of the Diagnostic Cylinders Cylinder Address Register 2 to 7
51. erface Logic is responsible for the assembly disassembly of the disc serial DATAl It provides flags for branch offsets to indicate to the microprocessor when each process has been completed A2 1 8 BUS LOGIC The Disc Bus Interface Logic sends commands to the disc drive and receives FAULT SKERR READY ONCLY SCTR and INDEX from the drive A2 2 INTERFACE REQUIREMENTS A2 2 1 ELECTRICAL INTERFACE l Signal Levels All signals will be at standard TTL levels 0 1 to 04 VDC equals logical low 2 4 to Vcc VDC equals logical high The clock and data lines to the disc are differential balanced line drivers receivers 2 Termination All TTL signals that pass through lines exceeding 2 feet in length are terminated with 220 Ohm pull up and 330 Ohm pull down resistors 3 Drivers Receivers All TTL line drivers are 7438 or equivalent line drivers All interface receiver lines are standard TTL input A2 2 2 CPU INTERFACE The CPU Interface signals are as follows l Master Reset 2 Clock Phase 1 and 2 3 I O Control Registers 1 thru 3 4 Output Data Bits O thru 7 2 3 A2 4 8 9 10 Memory Address Bits 0 thru 14 Memory Address Bit 15 Memory Data Bits O thru 7 DMA Acknowledge DMA Request DMA Interrupt Read Enable A3 1 16WAY ADDEN BOX BINDX BRDY BSCTR BYTE CHCLK CLKEN CLRCRC CLTAG CPHX CRC SECTION 3 GLOSSARY OF SIGNAL NAMES GLOSSARY This output
52. he processor clocks on and off for testing and single cycle operation with the WCS This signal is used by the processor to reset the CRC generator checker Set Cylinder Tag This signal is used by the disc unit to determine that the information on the disc control bus in cylinder address information X 1 or 2 These are timing clocks from the CPU The controller runs from these clocks during read data operations and at all other times except during a write data operation This signal switches the CRC data into the serial write data stream This signal is enabled by CRCENB A3 1 CRCDTA CRCENB CRCERR CRY CRYIN CRYSAV CTTAG DATAEN DBX UK DECCNT DFLAG DFLG DIXX DKBSX DMX DMA15 This is the serial CRC information that is generated by the CRC chip for a write operation This signal is used during write data transfers to enable the writing of the CRC This signal is directly controlled by the processor This signal is generated by the CRC chip to indicate that the CRC that was read in was in error This is the raw carry output of the 2901 This signal is controlled by the ROM and is used to gate one zero or carry saved into the carry input of the 2901 This is the saved output of the carry output from the 2901 to be used for testing carries or shift operations in the next processor cycle Control Tag This signal is used by the disc unit to determine that the information on
53. ll connectors and components mounted thereon Al 3 2 MOUNTING The Controller is installed in the card cage of a standard Basic Four data pro cessing system All clearances and airflow provisions normal to the Basic Four system are observed Al 4 DATA RELIABILITY The data reliability of the Controller is subject to the data reliability limits of the disc unit These limits are 1 Soft Error Rate Recoverable Errors Not more than one error in 1010 o bits of data transferred 2 Hard Error Rate Non Recoverable Errors Not more than one error in 1013 pits 1 3 SECTION 2 MAINTENANCE A2 1 GENERAL DESCRIPTION Maintenance of the Controller is limited to replacement of the Controller This section will explain the Controller function only as an aid to the Service Representatives in troubleshooting A Functional Block Diagram is given in Figure 3 1 and described below CONTROL ROM FIRMWARE DMA LOGIC INTERRUPT LOGIC I 0 LOGIC CRC LOGIC RADIAL LOGIC BUS LOGIC Figure A 3 Block Diagram of Controller MIROPROCESSOR DISC UNIT A2 1 1 CONTROLLER ROM The Control ROM FIRMWARE automatically initiates the following 1 The Reset Routine 2 The Idle Loop 3 The Transfer Preparation Routine 4 Search ID Routine A2 1 A2 1 2 MICROPROCESSOR The Microprocessor initiates tests or controls the entire operations of the Controller as specified by firmware
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55. n Logic PCB Motor Control PCB Photocell PCB e e Frame Assembly Power Supply Assembly Terminator s e Disc Drive Specifications INSTALLATION AND OPERATION General s s Unpacking Packing Procedure Head Carriage Lock Spindle Lock o Installation Procedure Pre Power Checks Interface Cabling Dc Voltage Check Controls and Indicators Switches and Jumpers MAINTENANCE General Description Block Diagram Functional Diagnostic Tests General Discription of General Description of Adjustment Procedures e e e Description Silver 5 FORMAP Power Supply Adjustments e Power Supply P N CP353 1 Power Supply Model 2981 Write Current Adjustment Data Window Adjustement Fault Isolation e Figure Page f NN FS NNN iS iS 2 1 2 1 2 1 2 2 2 3 2 4 2 5 2 8 2 8 2 9 3 1 3 1 3 3 3 3 3 3 3 4 3 4 2 9 3 6 3 7 3 8 2 9 CHAPTER 4 CHAPTER 5 APPENDIX A iv TABLE OF CONTENTS continued SPARE PARTS LIST REMOVAL REPLACEMENT Introduction e s s 9 e gt gt gt Removal Replacement Procedures Head Disc Assembly HDA Power Supply Assembly PROCEDURES Main Logic PCB and Motor Control REFERENCE DATA DISC CONTROLLER Pag
56. ocated on the dc power supply Power will be applied when the power cord is connected Remove ac power from the host CPU Open host CPU cabinet to gain access to Disc Drive if required Remove ac power plug at rear of Disc Drive power supply Remove Disc Drive Disconnect dc power supply connector J3 from Main Logic PCB Remove six retaining screws securing power supply to deckplate Remove power supply Locate adjustments refer to Figure 3 3 or 3 4 With power supply removed reconnect power cable to J3 of the Main Logic PCB Reconnect ac power plug to power supply Apply power to host CPU Ad just voltages If power supply will not meet tolerance it must be replaced Turn OFF power at host CPU 14 Disconnect power supply from Main Logic PCB 15 Disconnect ac power plug from power supply 16 Reinstall new power supply in Disc Drive 17 Apply power to host CPU 18 Test voltages Measurements will be done at connector J3 at the right rear of the Main Logic Ground meter at C186 on side with C186 designator Check voltage on J3 Pin 2 24VDC 1 2VDC Pin 5 5VDC 0 25VDC Pin 3 5VDC 0 25VDC Pin 4 12VDC 0 60VDC Pins 1 and 6 are ground Use only an insulated shank screwdriver Damage may occur to the power supply Adjusting of power supply will require a long five inch insulated shank screwdriver with 1 8 inch blade 3 4 1 1 Power Supply P N CP353 1 Three voltages 5 5 and 24 must be adjus
57. of the next address control ROM is used to indicate that a 16 way branch is required This signal is generated by the DMA control logic and is used to gate the contents of the DMA address counter onto the main frame memory address bus This signal is true throughout any DMA cycle 0 to 7 These are the outputs of the D register The D register is used to buffer data until it can be written into its destination This signal is the synchronized and buffered version of the index signal from the disc This synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This signal is the synchronized and buffered version of RDY This synchronization is necessary to prevent a metastable flip flop in the next address logic This signal is the synchronized and buffered version of the logical OR of the index and sector signals from the disc This synchroni zation is necessary to prevent a metastable flip flop in the address logic for the processor This signal is generated by the bit counter on each eighth bit during a data transfer to determine the byte boundaries This signal is used by the processor to control the clock changeover logic In addition to loading the least significant bit of the processor output bus into the clock control flip flop this signal initates the series of events necessary to insure a smooth changeover from one clock to another This is a test signal that is used to gate t
58. on of loading data into the S register so that by the time that the processor responds to the S flag the data will be there 7 SFLAG SFLG SGNSAV SIGN SINT SKERR SMDCY SRX SRTXX STDC SYNDET TO 1 W SD WCLKX WDATA This is the synchronized and buffered output of the S flag The synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This is the raw output of the S flag flip flop S flag is set when data is loaded into the S register and cleared when data is read from the S register This is the saved output of the sign bit from the 2901 to be used for testing in the next processor cycle This is the raw sign bit from the 2901 This signal is used by the processor to control the state of the signals MASK and INT Seek Error This signal from the disc unit is used to determine that the disc has not completed a seek within a specified time interval and therefore the servo is lost and needs to be re oriented by a rezero operation This output of the DMA control ROM is used to set the mid cycle signal flip flop on the next clock edge X 0 thru 7 Shift register parallel output bit This output of the DMA control ROM is used to set the RTXX flip flop on the next clock edge Set the Disc Control This signal is used to load the disc transfer control flags from the processor This signal is true when the sync pattern 16
59. rom the Photocell PCB 1 2 4 PHOTOCELL PCB The Photocell PCB contains three infrared light emitting diodes and phototransistors used to monitor and control spindle motor rotation 1 2 5 FRAME ASSEMBLY The Frame Assembly is designed to contain the standard assemblies of the Disc Drive 1 2 6 POWER SUPPLY ASSEMBLY The Power Supply Assembly is an integrated power supply that will operate from 50 or 60 Hertz and at a selectable input voltage of 100 120 220 or 240 volts ac 1 2 1 2 7 TERMINATOR The Terminator is a signal line terminator for the last drive connected to a Controller 1 3 DISC DRIVE SPECIFICATIONS Table 1 1 list the Disc Drive specifications WARNING This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions manual may cause interference to radio communications as temporarily permitted by regulation It has not been tested for compliance with the limits for Class A Computing Devices pursuant to Subpart J of Part 15 of FCC Rules which are designed to provide reasonable protection against such interference Operation of this equipment in a residential area is likely to cause interference in which case the User at his own expense will be required to take whatever measures may be required to correct the interference TABLE 1 1 SPECIFICATIONS Parameters Characteristics PHYSICAL Height 6 8 inches 17
60. ssor This is the input output line for RAM bit O in the 2901 Whether this line is an input or an output is determined by the type of shift oper ation that is in progress This is the I O line for RAM bit 7 in the 2901 Whether this line is an input or an output is determined by the type of shift operation that is in progress 1 These are the differential balanced line signals from the disc that carry the read data clock When the read gate is asserted this signal may be used to clock data in from the disc unit This is the received read data from the disc unit The data takes the form of serial NRZ data that is clocked in using the read clock This is the received read clock from the disc unit This clock is used to time the flow of data from the disc unit to the controller during a read data operation Read the Lower Disc Bus Control Register This strobe generated by the processor is used to gate the contents of the lower disc bus control register into the processor data input bus This signal is used in the data bus control logic to enable the out put of the data mux onto the processor data input bus Read Disc Upper Bus Control Register This strobe is generated by the processor and is used to gate the contents of the upper disc bus control register into the processor data input bus Reset the D flag necessary This signal is used to reset the D flag whenever Le These are the differential b
61. ted by reaching through holes inside the power supply chassis as shown in Figure 3 3 The 12 is not adjustable Voltage Ad justment Wire Color Leaving Supply 24V R20 Red return is Brown 5 RAO Black return is Grey 5V R38 Yellow return is Grey 12V Not Adj Orange return is Grey 5 VOLT ADJUSTMENT R38 24 VOLT ADJUSTMENT 5 VOLT ADJUSTMENT R20 R40 Figure 3 3 Power Supply Adjustments P N CP353 1 3 4 1 2 Power Supply Model 2981 On this power supply the adjustments are visible externally as shown in Figure 3 4 Voltage Ad justment Wire Color Leaving Supply 24V R3 Black with White Lettering return is Yellow 5V R14 Red return is Solid Black 5V R20 Brown return is Solid Black 12V Not Adj Orange re urn is Solid Black R20 5 VOLT ADJUSTMENT R14 5 VOLT ADJUSTMENT R3 24 VOLT ADJUSTMENT Figure 3 4 Power Supply Adjustments Model 2981 3 4 2 WRITE CURRENT ADJUSTMENT For this adjustment you must be writing all ones Do not use Head 2 Do not use any tracks which could contain customer data Write as many sectors on one track as possible for best display With an oscilloscope use the following procedure refer to Figure 2 3 for adjustment location Scope Tektronix 465 or equivalent Probes Two X10 attenuation Channel 1 to side of R46 facing transistors Set input to 1 Volt Division 0 1 Volt Division with non indicating X10 probe Channel 2 to other side of
62. the Controller Dc power supply connector Motor Control connector Voice Coil connector Servo head and Data head connector Data heads 1 and 2 connector Control Panel connector used for LEDs in identifying malfunctions in Disc Drive Radial cable connector to the Controller The Bus cable J2 P N 902687 and Radial cable J9 P N 902622 are connected directly from the Disc Drive to the Controller in the host CPU Figure 2 4 gives Interface Cabling Pin assignments and Bus Tag Decode information 2 5 TO CONTROL PANEL SWITCH WRITE CURRENT ADJUSTMENT DATA WINDOW ADJUSTMENT e TP13 oo J9 OO Mesi R32 25 gt lt R46 2 R351 BUS A DRIVE ADDRESS SEL SWITCH SECTOR SWITCH 1 5 c c A HEAD 1 HEAD 2 SERVO HEAD HEAD 0 VOICE COIL TERMINATOR MOTOR CONTROL POWER SUPPLY DRIVE ADDRESS SELECTION 10N 1 THRU 10N 3 WRITE PROTECT 10N 7 DIAGNOSTIC MODE 10N 5 Figure 2 3 Main Logic PCB 2 6 CONTROLLER PCB Figure 2 4 Interface Cable Pin Assignments and Bus Tag Decode BUS CABLE UNIT SELECT TAG P3 RADIAL CABLE J9 WRITE CABLE 4 SERVO CABLE 2 READ DATA 6 8 43 gt gt qa Y rS PY i u O C1 CO WON HB O Ny m a WRITE CLOCK wo N NN CO O s A61 TAG 2 TAG 3 CYLINDER HEAD ADDRESS SELECT CONT
63. the disc control bus is control information This signal is used by the DMA control logic to gate the contents of the D register onto the main frame memory data bus This signal is true throughout a DMA cycle only when the controller is performing a disc data read operation X 0 thru 7 This is the processor data input bus Disc Generated Clock This clock is either the disc servo clock or the disc read clock as the occasion demands This signal is used by the processor to decrement the general counter and test for zero result This is the synchronized output of the D flag The synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This is the raw output of the D flag This flag is set at time that the D register is loaded and cleared when data is read from the D register This signal in the I O control logic is true when IOACTV is true and the controller detects the DIXX command from the CPU This signal is used to transfer data from the controller to the CPU X 0 thru 9 These are the disc control bus signals The information on this bit is used by the disc unit as either control information head addresses or as a cylinder address X 0 thru 7 This is the outputs of the S register that are directed to the processor input Ihis is the most significant address bit from the DMA address logic to the memory page control in the CPU This bit is converted to the appropriat
64. us output lines when the controller is first powered up This is to prevent the random control information contained in the registers from cauing the disc unit to force a fault Once the registers assume a known state this signal can be enabled This signal is used to indicate that the next address for the pro cessor instruction will come from the contents of the address stack register This is the 1 0 line for bit 0 of the Q register in the 2901 Whether this line is an input or an output is determined by whether there is a right or left shift operation in progress This is the saved output of the QO bit in the 2901 to be used for right shift operations in the Q register This line is the I O for bit 7 of the Q register in the 2901 Whether this line is an input or an output is dependent on the type of shift operation in progress This is the saved output of bit 7 of the Q register to be used in left shift operations for the Q register in the 2901 in the next processor cycle This is the save output of RAM bit 0 in the 2901 to be used in left shift operations in the RAM This is the saved output of RAM bit 7 from the 2901 to be used in left shift operations in the next processor cycle RADX RAMO RAM7 RCLKX RDATA RDCLK RDDLB RDDMX RDDUB RDFLAG RDTAX RDY READ READY RINT ROXX 0 thru 8 These are the ROM address bits used to fetch the next instruction from the control ROM for the proce
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