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Model 64601A Timing Analysis Control Board Service Manual

1. HE STOP m a s g D a 5 m s 2 k gt a i ape 330 1 4 3 25 3 25 9 E T 7 2 3 l si Ne 10 044 09 LJ 0 a U38 TRIGGER HRIN ENABLE 3 PHRCLK COUNTER Ir HREN HROUT 5 4 1 0 037 DELAY 4 ECL 2 HRIN COUNTER HRCLK FF ice HROUT 0 U1 SAMPLE an CLOCK 1 3 PHRCLK COUNTER HROUT 4 0 U36 WINDOW HAIN COUNTER x 13 cNTROUT 5 20 NC po ad J6 SEE NOTE B HROUT 5 25 BIT HOLDING REGISTERS SEE NOTE A Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC NOTE A Only the holding register part of Ul Mfr Part N 36 37 38 15 shown on this schematic LN DU EET NO a x For the remainder see the following service sheets U10 11 15 71 73 1820 2193 MC10176L MURS U36 37 7 U1 36 37 38 1NB4 5008 1NB4 5008 U1 36 37 38 25 BIT SHIFT REGISTER HOLDING REG INPUT HR OUTPUT HOLDING REGISTER CLOCKS PARTS ON THIS SCHEMATIC 25 BIT COUNTER U9 12 14 70 72 RESISTOR PACKS COUNTER INPUT amp POLARITY SELECT LATCHED TC COUNTER START LATCHED INPUT RESET CLEARS START COUNTING INDICATOR LOADS COUNTER FROM HIGH WHILE COUNTING HR amp
2. 4 37 Softkey Setup For running PV test repeatedly h M1 Adjustment Locator 5 2 System Block Diagram 8 2 Control Board Block Diagram vm Sample Rate Clock Block 8 6 Sample Clock OST Term Generators Block 8 8 Trigger Enable Circuit Block Diagram 2 8 10 Tracepoint Selector Block 8 12 Display Driver Block 8 14 Service Sheet 1 CPU isa rex 8 25 Service Sheet 2 130 Bit Control Shift Register 8 27 Service Sheet 3 Sample 1 8 29 Service Sheet 4 Term Generator 2 8 31 Service Sheet 5 Term Generator B dace ie Wierd nue e avec 8 33 Service Sheet 5 Trigger Enable 1 1 8 35 Service Sheet 6 Tracepoint Selection 2 8 3 7 Service Sheet 7 Display Addressing m 8 39 Service Sheet 8 Display 8 41 LIST OF TABLES Title Page Specifications e ERR E enda Ud TATE 1 3 Performance Tests VS Schematic 4 2 Reference Designators and Abbrevations
3. C96 CTL 8 30 Theory and Schematics Model 64601A ICs ON THIS SCHEMATICS LE ENTRIG4A lt D D FF DURATION SELECTION P O DURATION TRANSITION 428 SELECTOR CONFIGURATION U28 HIGHS CONNECT TIMING BUS Ref Des HP Part No Mfr Part No ue Non U13 1820 0815 MC10121P AR U27 1820 0802 MC10 102P U28 20 1730 7415273 P O TIMING ANALYSIS CONTROL BOARD 64601 66501 u 3558 2 2 182071 TERM GENERATOR U31 1858 0054 1 566 o U32 1821 0002 CA3054 HE RESET 5 034 1820 1320 MC10216L 2 Qs 999999 V HE MEMFUL 1 U35 42 1820 1946 MC10117L XE TRI63 5 XE TRIG4 5 PARTS ON THIS SCHEMATIC Re4 200 A 161 5 H To X 162 695 4 200 ENTER LEAVE 8 18 23 27 29 32 34 35 Pw TRANSITION NET R4 6 13 15 23 26 TRIGGER 893 200 SELECTOR we gt U16 18 184 26 29 30 33 41 RESISTOR PACKS z 5 AND OR TRIGGER DURATION i FO Sey LE ENTRIG3A V gt COMBINATION PROGRAMMING PN PN 31 4 3 25 11 90 Je j IC POWER SUPPLY U30 45 CAPACITORS TO GROUNDS C18 240PF M LE ENTRIG1A 2 2 15 2 6 os quee LE ENTRIG2A 12 200NS 500 5 1US NC U13 27 34 35 42 028 irem 12 7 10 C20 04UF 15 B 205 505 1005 P O ic _ HC E 19 7 621 4UF Ne p 2005 50US 1
4. TRIGGER ENABLE L tr ce U18A 1 s i o 1 MM 5 AE E e w tg oe o 73 CBC10 5 2 m I Q TTI 9 es a E I5 4 TEST 22 5 v a 2 5 11 3 5 33 e 2 o 99 5 all ri Ie 9 ah U19 1 5 N 027 NO U31 T er 5 gt 8 a 55 amp 9 a 9 T TT R2i 9 R22 8 5 E 5 T TREE 9 9 5 3 ed 9 898611 o 8 5 18 0 9 21 36 u47 lll 68 8 ur 8 HE TR x 9 96 9 9 9 ze m U47A gt 8 o LE TE 2 TEST m 97 9 6 GND id NORM 3 NORM 5 J7 I n 0 3 8 8 TEST 9 9 9 2 5 EE U57 a 8 9 9 9 o 2 a 9 9 9 TP8 E 1 97 oed eg e a ib N N N 9 9 9 gt 966 U67 U69 U71 4 973 074 gt 076 979 U81 R 5 R 89 077 8 5 9 9 7 2 9 8 5 1 2 5 9 WNDWCLK 9 SAMPLE CLOCK 2 5 988 U91 U97 i n M d x gt e S o 5 u Y T T T T 94 95 c96___ TP12 R38
5. DATA FROM THE PROBE IS SAMPLED ON BOTH THE RISING amp FALLING EDGE OF EACH CLOCK SIGNAL Figure 8 4 Sample Clock Waveforms CTL 8 7 Theory and Schematics Model 64601A TERM GENERATORS FROM FROM 130 BIT REGISTER 130 BIT REGISTER 1 1 TERM GENERATOR ACQUISITION TRIG GERS MAY BE HIGH OR LOW TRUE 1 I Vi OIHIN3 3 OIHLIN3 lt l lISNVHIV JH 4 XE TRIG 1 TRANSITION ACQUISITION ENTER DURATION gt TRIGGER LEAVE DECODER o COMBINATION z XE TRIG 2 AND OR PATTERN o Ta ENTER HE TRIG A 2 LEAVE PATTERN DURATION 3 LESS THAN 028 31 32 34 4 GREATER U13 34 35 THAN U27 42 eS ees Se WSR se ut suspa a ee ere a z TO TRIGGER E ENABLE D gt D E PC BS B TERM GENERATOR HE TRIG AeLATCH B HE LTRIG B SNS ONIWIL pup iiec ES Bl n Figure 8 5 Term Generators Block Diagram CTL 8 8 Theory and Schematics Model 64601A 8 30 TERM GENERATORS Figs 8 4 8 11 8 12 8 31 The term generators receive combine and qualify the trigger s from the acquisition board s There are two term generators A and B on a timing control board Thus an A trigger trigger or a B Lat
6. M 5 i5 2 048 064 Q 0 2 42 TIMING CONTROL BOARD 64601 66501 J7 0 5 wu 2 CTL 8 28 Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC P O TIMING ANALYSIS CONTROL BOARD 64601 66501 NORMAL SAMPLE RATE CLOCK GENERATOR uc Ref Des HP Part No Mfr Part No TEST a 2 U1 1NB4 5008 ee U4 1820 1359 MC10174P PV STOP GATES 05 23 1820 1225 10231 i 11 T SS NORMAL U7 1820 1320 MC10216L x ne s dne 08 z MET D p 10 E9 1820 0920 MC1692L UB 022 1820 2664 MC1678L iD 9 H SCLKOUT OF U24 1820 0796 MC1662L Tu U40 1820 1225 MC10231P gt U48 1820 0780 DS8831N a DRIVER 056 PROBE e 13 Po spr 1po V LE PHI2 N Q 064 1820 1052 MC10125L SPF 1BPF C10 10P T 5 R7 t C ECL 2 200MHZ 1K DRIVER a A ee TE 088 EINES DRIVERS 8 PARTS ON THIS SCHEMATIC c TS 54 5 12 ECL gy 3 10 00 o d Lu 15 6 0248 9 8 1HZ 100MHZ E VETE s H 10 7 1HZ 100MHZ ON 7 6 1 2 4 6 d 400 3 LE RUN y CLOCKS SHOULD A PERFECT SQUARE 5 nega DNS Ay M EL 7N R12 5 5 WAVE 50 DUTY CYCLE lt 2 C8 ds E
7. BLANK DATAEN 9 H GRATEN CURSOR H GRATICULE LEXER PARALLEL TO SERIAL L DOT1 L DOT2 Ref Des HP Part No Mfr Part No U56 1820 1196 SN74LS174N 057 59 1818 1596 HM6147P 3 060 1820 1677 SN74S374N 077 1816 1308 931422 079 64601 10002 U80 64601 10001 U81 1820 1076 SN74S174N U82 1820 1197 5 74 500 083 1820 1158 SN74S51N U88 1820 1322 SN74S02N U97 1820 1451 5 74538 098 1820 1191 5 745175 099 1820 0686 SN74S11N U100 1820 0693 SN74S74N 0101 1820 0683 SN74S04N PARTS ON THIS SCHEMATIC C83 STATUS 4 35 37 075 RESISTOR IC POWER SUPPLY CONFIGURATION 25MHZ OUTPUT LATCH 5 U82 83 88 97 25MHZ DOT DATA 1 H SERTALDATA 4 8 H INTEN 12 L BLANK 1 5 amp 2 ME EIE 18 5 P U57 59 9 _H INTEN 4 H VIDEN GRATICULE R37 200 E 960 H GRATEN 10 056 79 81 98 99 101 22 19 077 3 25 e m w0 o o ojo PINS 2 5 2 UNCONNECTED Figure 8 17 Service Sheet 9 Display Driver CTL 8 41 Product Line Sales Support Key Key Product Line Analytical CM Components Computer Systems Sales only CH Computer Systems Hardware Sales and Services CS Computer Systems Software Sales and Services E Electronic Instruments amp Measurement Systems M Medical Products MP Medical Products Primary
8. 80 20 100UDC 1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC 01 80 20 100UDC CE O1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 204 100UDC CE 180PF 5 100UDC CER SPF 2G00UDC CER 18PF 5 200UDC CER 0 30 01 80 20 100UDC CER O1UF 80 20 100UDC CER 240PF 5 300UDC MICA 3600PF SOVDC 04UF S0UDC SO0UDC 200UDC CER AUF SOVDC OIUF 80 2 100UDC CER O1UF 100UDC CER 01UF 100UDC 100UDC 100UDC O1UF 80 20 100UDC 01UF 80 20 100UDC O1UF 80 20 100UDC O1UF 100UDC Q1UF 80 100UDC 1 80 20 100UDC 01 80 20 100UDC 20932 28480 28480 28480 28480 28480 28480 28480 28480 28480 22136 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 22136 28480 28480 28480 28480 28480 28480 See introduction to this section for ordering information Indicates factory selected value S024E0200RD689D 0160 3874 0160 3874 0160 2055 0160 3829 0160 2055 0160 2055 0160 2055 0160 2055 0150 2055 DMiSEF241J0300uV1CR 0160 5415 0160 5343 2342 3874 0160 5341 0160 2055 0160 2055 0160 2055 0160 3875 0160 2055 0160 4813 0160 2055 0160 2055 0160 4492 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 205
9. ss una 111 m A TERM GENERATOR m m 5 5 2 2 m m d o ACQUISITION TRIG gt gt gt U34 4 J5 ie ll GERS MAY BE HIGH 5 D gt 2 OR LOW TRUE 2 gt amp gt gt o od 2 2 C34 R25 26 b Q 11 35 ho XE TRIG 1 ACQUISITION MER x gt TRIGGER LEAVE SEC CHEE U27 11 12 COMBINATION 111 2 i 5288 5 1 HE TRIG A one T SSI yas U47 lll 66 8 2 LEAVE 27 9 U idi 9 PATTERN DURATION 3 LESS THAN 8 28 31 32 34 4 58 U13 34 35 THAN U27 42 EL M e GND N l L 2 tu ip cme ee coe gt 5 9 TRIGGER U52 2 D a 8 U57 8 ENABLE in 5 gt XE TRIG HE TRANSIT LE PDUR gt PATTERN MUSTBE a B B B TERM GENERATOR RE RISE uz e s CUS y mW mO n a Y m a i n SAMEASA GREATER THAN SPECIFIED K L L H LESS THAN SPECIFIED H H TRANSITION LEAVING H H TRANSITION ENTERING C83 R35 AeLATCH B HE LTRIG B C86 TP11 R37 C92 C93 SNA
10. 00 11 12 H 25MHZ q H CHARADB 12 12 8 DATA RAM H CHARADO RAM 4KX4 BLANKING RAM RAM 4KX4 KH CHARAD2 1 j MH CHARADA O a Ku cHmns C s H CHARADB 8 C H CHARADA 5 5 C H CHARADA 5 7 7 CHARADS 5 H CHARADS 6 48 H CHARAD7 H CHARADS 17 C H CHARAD 16 CHARAD7 16 H H ECHARADS 45 15 17 16 14 H CHARADS ENHANCEMENT RAM 4 162 163 WRITE 162 READ 163 WRITE 162 READ 163 WRITE Lr L DO 11 L 12 5MHZ H 12 5MHZ H LCNTO 3 oOx II L RDRAM MODE REGISTER L POP 10 L MODEN 4 2 1 4 3 1v S Ho O 2 1 3 1V 2 1 3 4 A 2 1 A 5 CURSOR ii H INTENSITY Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC L 12 5MHZ i 12 5 7 PRESENT PAST SHIFT REG FORMAT ROM POSITION WITHIN CHARACTER ROM po VHT PROM 256X4 A CHARACTER H 42 5MHZ L PROGRAM VHT A PROM 258X4 DATA 4 3 12 5MHZ SYNCHRONIZING MULTIP IL sus 2 ll sepe
11. 2524623 Replaceable Parts List 6 4 List of Manufacturer s Code Varo ean 6 7 64601A E PETENS 8 16 Logic 1 8 23 111 General Information Model 64601A Ape mI 72272222 Mew Control Board is Analys iming Figure 1 1 Model 6h601A T CTL 1 0 General Information Model 64601A SECTION I GENERAL INFORMATION 1 1 INTRODUCTION 1 2 This Service Manual contains information required to install test and service the Hewlett Packard Model 64601A Timing Analysis Control Board Operating instructions are provided in a separate Operating Manual supplied with the instrument It should be kept with the instrument for use by the operator 1 3 Shown on the title page is a microfiche part number This number can be used to order 4X6 inch microfilm transparencies of the manual Each microfiche contains up to 96 photoduplicates of the manual pages 1 4 INSTRUMENTS COVERED BY THIS MANUAL 1 5 Attached to the instrument or printed on the printed circuit board is the repair number The repair number is in the form 000040000 It is in two parts the first four digits and the letter are the repair prefix and the last five are the suffix The prefix is the same for all identical instruments The suffix
12. 4 39 Performance Tests and Troubleshooting Model 64601A 4 87 SUPPLEMENTARY BOARD ID TEST 4 88 The board ID circuits have stable signatures when opt test is pressed If the Timing Boards are not then listed on the screen the ID eircuitry is not working Check the ID circuitry signatures at U88 and 089 CTL 4 40 Performance Tests and Troubleshooting Model 64601A 4 89 The following figures 4 18 to 4 26 show the operator softkey sequence needed to run a single PV test repeatedly for signature analysis purposes Each PV test corresponds to one signature loop Signature lists are given following the figures ADRS DEVICE UNIT 0 7925 DISC MEMORY 2608 PRINTER 64000 64000 THIS 64000 1 2 5 4 5 6 Y Figure 4 18 Press opt test 200 MHz Timing Performance Verification 11 58 8149 Slot ID Module Tested 1004 200 MHz Timing Data Acquisition 0 j iH 200 MHz Timing Controi j 4H 200 MHz Timing Data Acquisition Timing analyzer control board avsilabie for AIMB stimulus STATUS Awaiting command _ run slot Figure 4 19 the slot number CTL 4 41 Performance Tests and Troubleshooting Model 64601A MHz Timing Performance Verification 11757815 Fri 15 Jan Module Tested Failed 200 Timing Data Acquisition 1001 200 Timing Control i 4H 200 Timing Data Acquisition Timing analyzer control boar
13. RETURN d Press execute RETURN 5 11 Adjustment a Connect the probe to the 64602A acquisition board through the timing cable Leave the probe leads disconnected b Connect channel A of the scope to testpoint 1 Since this is a coaxial test point no ground clip is necessary c Set up CHANNEL A VOLTS DIV to 01 100mv div with the X10 probe and AC couple the input d Set up HORIZ DISPLAY to MAG X10 and MAIN e Set up TIME DIV to 10ns div This is actually 1ns div since MAG X10 has been selected f If no signal is present adjust the trimmer capacitor on the upper middle part of the board until a sinusoidal signal is observed try to adjust the capacitor to the middle of the range when the sinusoid is observed NOTE USE NON CONDUCTIVE ALIGNMENT TOOL ONLY ISOLATION IS REQUIRED g The sinusoidal waveform should have an amplitude of 100 to 150mV and a frequency of 200MHz 2 periods screen on 1ns div CIL 5 3 Adjustments Model 64601A SAMPLE RATE OSCILLATOR CALIBRATION continued h CTL 5 4 To determine if the oscillator is stable tap the collector of the high frequency transistor lightly with the blade of a small screwdriver to see if the oscillator will come back to a stable 200MHz oscillation HIGH FREQUENCY TRANSISTOR 0 lt collector located below the trimmer If the oscillator will not come back with the correct oscillation readjust the trimmer ca
14. 64000 Logic Development System Model 64601A Timing Analysis Control Board LA Packar CERTIFICATION Hewlett Packard Company certifies that this product met its published specifications at the time of shipment from the factory Hewlett Packard further certifies that its calibration measurements are traceable to the United States National Bureau of Standards to the extent allowed by the Bureau s calibration facility and to the calibration facilities of other International Standards Organization members WARRANTY This Hewlett Packard system product is warranted against defects in materials and workmanship for a period of 90 days from date of installation During the warranty period HP will at its options either repair or replace products which prove to be defective Warranty service of this product will be performed at Buyer s facility at no charge within HP service travel areas Outside HP service travel areas warranty service will be performed at Buyer s facility only upon HP s prior agreement and Buyer shall pay HP s round trip travel expenses In all other cases products must be returned to a service facility designated by HP For products returned to HP for warranty service Buyer shall prepay shipping charges to HP and HP shall pay shipping charges toreturn the product to Buyer However Buyer shall pay all shipping charges duties and taxes for products returned to HP from another country HP warrants that its s
15. HF OS FACA P2FH high 8267 CFFC 9366 810 FOHS 8267 03 amp 6F 036F 8100 4 32 75 17 5 09 75 17 4 32 4 99 12 T5 17 1 78 0 17 0 01 SA 0 65 0 01 74 1 4 4 99 0 17 0 01 0 17 4 99 0 17 0 01 4 99 0 17 0 01 DEN pov DEV DEY DCU PCV DCV DEV DCV PEN DEV PEV DCV DEY DCV PCV DEV PEY DEV DPEN DEY DEV DOY DCV pou U 32 11 4 99 32 12 0 17 DOY U 52 13 0 01 DOV 32 14 4 99 PEN U 34e 1 high U ge 2 B10C U 34e 3 O36F U 34 4 8108 ij 34e 6 Sec U 34 7 H HS L 34 9 See U 34 11 0000 34 12 0000 U 34 13 B7PU 54 14 05809 U 35 21 high U 39 amp OS6F U 395 3 8106 4 0588 0 35e 5 n6P4 U 35 amp 8483 U 35 7 U 35e 9 low LJ 33 10 0598 U 352 11 e aH U 35 12 3738 35 13 37PL 0 355 p U 35 15 HUHS U 36 0000 20260 U 36 3 8204 36 8198 U 36 6 high U 36 7 low U 36 8 PROPS U 36 9 2CP3 U 36 10 8195 36 12 FSS 36 13 HOS 36 14 FS 36 18 high 36 17 0000 TOTLZ 0260 36 18 low 56 19 high 36 20 high 36 24 WFOS 37 1 0000 CTOTLZ 0260 U 37 3 133A lJ 32 4 3314 U 37 6 high LU 37 low tici C e U 37 8 37 9 37 10 U 37 12 5 32 14 37 1 32 PP17 1005 74 FS 9 e 7 HF OS FSS high 0000 CTOTLZ 0260 0 37 18 37 19 0 37 20 U 37 24 U 38 1 low high high HF OS 0000 CTOTLZ 0260 u 38 U 38 U 38 U 38
16. L GLTCHMEM 9 4 p 4 y 3 18 A 5 2 8 52 1496486 L BLNKMEM lt s U69 64 12 13 52 17 9 lt L POP 25 1 OMM 18 9 Eo E R34 1 LZHSYN 19 p x 16 A wit m use PT e oL 3 25 200 s VHE TO 069 C30 39 51 59 C1 3 15 17 P O 1 80 65 70 33 44 45 47 28 37 38 R38 100 uaa 2758 85 82 52 61 64 71 227 i 5 78 9 01UF 13528276 O4UF Ri TUF C86 10UF e 299999 29999999 2999999999 5 222222 088 89 101 aia NZ o oju 0 b bal ba bai z z lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt a IRIN 2 3i E E BE SIRE 1 EM E Sth ct Neal eal eon 1 15925085 9 SRS Rodded 8 HEBO zs 882 Figure 8 9 Service Sheet 1 CPU Interface CTL 8 25 TIMING CONTROL BOARD 64601 66501 2 I a i TP2 5 B 8 on 5 9 e e U36 9 U37 e 9 TEST 9 779 jg RORM NORM aw 5 8 049 E 9 9 70 065 C73 72 U68 71 85 087 C94 J5 FESP 40 1 067 088 62 s Le
17. 1070 1071 1072 1073 1074 41075 41075 41077 21078 81079 81080 1U81 21082 1083 1184 1085 A1U86 1187 1U88 21089 1190 1091 1092 1093 1094 81095 11096 41097 41098 41099 10100 10101 A1 XU1 A1XU13 1XU17 ALXU19 amp 1XU21 ALXU22 e1Xu28 1XU31 ALXUZ2 A1XU36 ALXU37 A1XU38 amp 1XU44 A1XU46 A1XU47 A1XU48 ALXUS4 A1XUSS e1XuS6 A1XUS7 Table 6 2 1858 0054 1810 0281 1821 0002 1820 0780 1820 1052 1820 1946 1820 0817 1820 1788 1810 0271 1920 0802 820 0815 1820 1196 1818 1596 1818 1596 1818 1596 1820 1677 1820 0629 1820 1077 1820 0693 1820 1052 1810 0271 1820 1944 1820 0802 1810 0271 1820 1400 1810 0272 1820 2193 1810 0272 1820 2193 1820 0817 1810 0280 1820 1641 1816 1308 1820 1430 64601 10002 64601 10001 1820 1076 1820 1197 1820 1188 1820 0693 1820 1917 1820 1173 1810 0272 1820 1322 1820 0269 1820 2799 1820 1216 1820 1196 1820 1196 1820 1475 820 1475 1820 1430 1820 1451 1820 1191 1820 0686 1820 0693 1820 0683 1200 0541 1200 0607 1200 0607 1200 0607 1200 0607 1200 0607 1200 0639 1200 0607 1200 0638 1200 0541 1200 0541 1200 0541 1200 0639 1200 0607 1200 0638 1200 0607 1200 0607 1200 0607 1200 0607 1200 0539 gt t ba b NN meo neo G Description TRA
18. O TATT VIDEO ENABLE GATE H 25MHZ 9 L LOADEN HOLDOFF vat tO NT 5 8 L HOLDOFF 13 L HORTZBLANK 2 ugga 2 H VIDEOEN 9 1 Ou 1 2 VERT SYNC 11 L VERTBLANK 1 S VERTICAL L PROGRAM 13 U848 SYNCHRONIZING NORMAL PROGRAMMING MODE SELECTOR HORIZONTAL BLANKING NC 5 TP10 15 p MUX CHAR TERMINAL COUNT 3 9 L L PROGRAM n 1 12 5MHZ 1 57 u62 HORIZ SYNC 18 ol usia 6 Ne L LOADEN 14 2 15 VERT SY ERT SYNC E VERTICAL BLANKING 0 9 9 yN s E g L CNTALD ROW TERMINAL COUNT 11 12 5 2 3 1 5 43 C 12 P po c 7 K HORIZ SYNC A E VERT SYNC 14 n U14 7 NT DOT LINE TERMINAL COUNT 45 e z R34 41K 2 5 NN 0 061 63 84 12 94 95 H CHARADO 11 Ge 1 L STARTADR 12 6 1 00 11 START ADDRESS LATCH START ADDRESS LATCH H CHARADO H CHARAD1 H CHARAD2 CHARACTER ROW COUNTER CTR DIV 16 R U96 14 14 H CHARAD4 BD con 80 C03 TE CHARA HORIZ SYNC 50 4 H CHARADS sag a 3 33 H CHARADS 546 5 E 12 H CHARADB SAMO 5 He cr 12 H CHARAD10 547 e s 233 H CHARAD S i 8 ts E35 11 H CHARAD11 Z 12 DOT LINE COUNTER CTR DIV 16 R 3CT 15 Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC
19. ORM NORM 9g i 0 8 g TEST 9 9 9 2 a 056 I 3 U57 U58 059 060 N i 9 MEE 2 9 9 8 1226324 e b E o 9 9 R A 967 2 5 o Un 973 U74 2 076 u79 g 18 v 8 5 8 9 9 9 9 9 9 T 9 t 9 S 9 e uso ust L A b d 2 8 2 B 8 8 I Y Y Y Y 94 95 P1 TP12 R38 85 25 MHz VERT SYNC HORIZ SYNC HORIZ amp GLITCH DT MOTHERBOARD DATA GLITCH BLANKING CHAR HORIZ SYNC amp START CHAR ADDRESS i EON DISPLAY COUNTERS RAN DOT LINE POSITION DOT LINE COUNTER 4 FORMAT ROM VIDEO ENABLE VERT BLANKING DUAL THRESH INTENSITY CURSOR BLANKING GLITCH DATA CHARACTER SEGMENTS Theory and Schematics Model 64601A PRESENT PAST SHIFT REG CTL 8 40 25 2 MUX amp SYNCHRONIZING LATCH VID INVID MOTHERBOARD 1 1 1 8 1 1 1 8 8 1 1 1 P O TIMING ANALYSIS CONTROL BOARD DISPLAY GENERATOR L ENHANMEM 64601 66501 L BLNKMEM L GLTCHMEM i 12 86 H CHARADO 11 R34 5 ANN VHT TO USB U100 s L DATAMEM
20. PAG MET Figure 4 10 f highs lows high low transitions and low This pattern is shifted by one dot in eac ion o lternat inuous a 0 t is a con This h of the following high transitions lays isp ht di eig Characters Exercised Data Characters High lasting four dots followed by a high low transition Low lasting four dots followed by a low high transition High low transitions Low high transitions Enhancement Characters None CTL 4 30 Performance Tests and Troubleshooting Model 64601A Press NEXT PAGE to CONTINUE Figure 8 11 This is the 16 channel version of figure 4 6 shifted by one dot in each of the next eight displays Characters Exercised Data Characters Low continuous on every channel Enhancement Characters Graticule every fourth dot Cursor alternates with the graticule CTL 4 31 Performance Tests and Troubleshooting Model 64601A Figure 4 12 This is the 16 channnel version of figure 4 7 shifted by one dot in each of the next eight patterns This is a shifting pattern of highs lasting four dots high low transitions lows lasting four dots and then low high transitions Characters Exercised Data Characters High lasting for four dots and then alternating with four dot lows Low lasting for four dots and then alternating with four dot highs Enhancement Characters Graticu
21. RESISTOR PACKS POWER SUPPLY CONFIGURATION U3 U5 19 21 40 54 55 RESISTOR U2 20 41 53 68 72 lt oO oO H o UNCONNECTED PINS U2 U20 U41 053 068 072 7 10 3 5 4 4 10 8 10 THE 25 BIT HOLDING REGISTER PART U38 IS SHOWN ON SHEET 2 Figure 8 1 Service Sheet 6 Trigger Enable Circuit CTL 8 35 CHANGE 1 Theory and Schematics Model 64601A a TIMING CONTROL BOARD C6 U18A n i TRACEPOINT SELECTION b cd gt c 2 y 1 Fan s 07 i U17 is gl 2 1 3 NET f 130 TRACEPOINT 5 A 5 C8C10 5 5 5 5 9 Eck N HR SELECT 1 1 E 15 n s i et IIIS 1 EG REX 1 a 9o ENIMBTR 5 bo TER i dd 9 8 3 89 TP5 5 all ls 9 A TR 5 465 7 So U30 U31 81 934 A tc r gt amp 5 EET la RES FE LE TE AND HE TR DRIVE a ri 9 amp e R21 9 b R22 TRACEPOINT CLOCK LATCH M 3 a llle SELECT 9 6 5 i 6 48 9 2888 8 8 DLCKSEL GRACE 966 T mm 1 9 8 35 ua U46 U47 lll 66 5 POINT TRACEPOINT HE TRIG DLY e 9 U37 2 8 i 5
22. 1 1 1 1 9 Description re er eee 1 2 1 14 Specifications EC E E rere 1 3 II INSTALLATION 2 ei Bde coe oe e aaa Barat 2 1 2 1 Introduction e 2 1 2 3 Initial TIE 2 1 2 5 Preparation for Use 2 7 Installation Instructions ERE 2 1 2 24 Operating Storage and Shipment Environments 2 h III E doe 3 L PERFORMANCE TESTS amp E Vrbs 4 1 4 2 Introduction T ens 4 8 Troubleshooting 1 2 4 16 Physical Setup See 4 18 Keyboard Setup All 15 Tests PTT CER RE AN dt do 4 4 4 20 Keyboard Setup One 5 5 4 22 Explanation of the Test Descriptions EORR A UE SS quwi RR 4 5 4 26 Test 1 Serial 4 6 4 20 Test 2 Run Halt Reset 4 32 Test 3 Trigger 4 8 4 36 Test 4 Delay Counter amp Trigger Position 2 1 9 4 40 Test 5 Window Counter M E 2 4 11 4 45 Test 6 Rates Interval 4 12
23. 5 6 5 21 Adjustment for 16 Channel System Rh R6 5 7 REPLACEABLE PARTS See Ee 6 1 5 1 ntre metion es eeen 6 1 6 3 4 6 1 6 5 Replaceable Parts ADS SA 6 1 6 7 Ordering ee ee ee 6 2 6 10 Spare Parts Kit lee I 6 2 6 12 Direct Mail Order BUS ERE I ESOS e ncn do tese Nn 6 2 MANUAL CHANGES e EU UN 7 1 THEORY AND SCHEMATICS CEDERE PE Mee TA 8 1 8 1 Introduction a 2 8 1 8 3 Logic Convention wa bw teat 8 1 8 8 Theory and Block 2 8 3 8 56 Mnemonics vo d ba e oe 2 225 8 16 Figure 0 P nus mH Pree PROP 1 H on 1 Ov 1 1 PRPRPPRRRPPO Q9 99 00 0000 00 O0 00 00 CO wu Model 64601A Table of Contents LIST OF ILLUSTRATIONS Title Page Model 64601A Timing Analysis Control Board 1 0 Timing Configuration e EE 2 2 Timing Bus Cables 229 ERE DUE COP ERR d 2 4 PV Test Display 16 channel 4 4 Display Driver Test Patterns Figures 4 2 to 4 16 4 22 Inter Module Bus
24. LE TE 11 ECL LE TEARM 10 U21C 71 7 2 LE TEARM 2 26 2 5 4 2 5 2 28 HE RESTARTEN HE RESTARTEN LE ENLATCHB HE TR HE LTRIGB HE TRIGA HE TE 12 15 ECL 1310540 9 o HE BLATCHR 5 200 P O u53 3 25 TRACEPOINT SOURCE SELECTION NC NC LE ENLATCHB HE LTRIGB 2 HE BATT LE ENTRIGA ECL NC uss a HE TRIGA NC HE TRIGB LE ENTRIGB M LE ENTRIGA cge NC E HE TRIGB PF LE ENTRIGB 57 POSTQUALIFY CIRCUIT HE TR 5 ECL 5 y NC 4 jJU18A 200 3 25 1 TR DRIVES TE NC 10 0 LE TE RESTART LATCH 12 11 2 Om 7 7 HE TEDRIVE 2 LE ENDRIVIE 2 30 DRIVE 10 E ECL 14 11 U87C 5 LE ENPVTRIG NC 9 13 LE TR 697 0 3 251 20 7 916 281 LOCKOUT 11 HE PROCRESET HE RESET 1 5 7 LE PVTRIG 78 4 5 Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC Ref Des HP Part No U3 1820 2359 05 1820 1225 054 67 19 21 1820 0802 055 1820 0815 069 1820 1400 074 1820 0817 038 1NB4 5008 Mfr Part No F10014PC MC10231P MC10102P MC10121P MC10104P MC10131P PARTS ON THIS SCHEMATIC C97 98 R16 17 02 20 41 53 68 72
25. 3 ASU di 4 low 8 3 amp FS83 21 7 high 21 10 CUZO 21 11 CB 21 12 7733 21 15 45008 21 14 _ 0 21 18 CHA 36 1 0000 CTL h 57 Performance Tests and Troubleshooting Model 64601A U 36 40 1 high U 64 15 low U 36 4 CH73 U 40 3 U 66 1 high U 36 6 high U 40 4 low U 66 2 ASU u 36 2 low U 40 ARGS U 56 3 C625 U 36 8G 40 6 low 66 4 508 U 36 9 8594 U 40 2 U 66 ASU 36 10 CHAS 40 9 U 66 6 ASU U 36 12 SHH U 40 10 6PPA4 U 66 10 U 36 13 40 11 1001 U 66 11 2503 U 36 14 OHH U 40 12 2508 U 66 13 high U 38 18 high 40 13 low U 66 15 507 35 17 0000 U 40 14 APPA U 69 3 AHH U 36 18 low 49 3 CHAS U 69 6 79 36 19 high U 49 22 ASU U 89 7 93284 U 36 20 high 49 11 lew U 69 9 APPF U 35 24 508 U 49 15 n P9 U 69 12 CHP U 37 1 0000 U 50 1 high 86 2 4906 U 37 3 2H21 lJ SU 2 ASU U 86 3 79 U 37 4 U 50 4 ASU U 86 12 508 32 6 high 50 9 2H21 U 86 14 CHIP 27 7 low U 50 11 high 37 amp 0680 U 50 14 ASU 37 9 ADP U 51 1 high 37 10 ASU U 51 2 8594 U 37 12 U Si 4 AOS U 37 13 508 U 51 amp HFAC U 37 14 6HH U 51 2 ASU U 37 18 high U 51 10 HFAC 37 17 0000 U 51 11 asuy U 37 18 low U 51 12 U 37 19 high U 91 14 low U 37 20 high U 1 high 0 37 24 508 U 50 2 U 38 1 0000 U 52 3 385 38 3 HFC U 52 high U
26. FIGURE 4 1 a With the operating system initialized and awaiting a command press the softkey labeled opt test you may have to keep pressing the etc softkey until you see opt test on the screen Or you may type option test in lower case b Press RETURN You should see a listing of all the optional boards that are present in your mainframe along with their slot numbers c in the 64601A timing control board slot number RETURN d Press softkey e Press softkey slot f Type in the 64601A timing control board slot number g Press softkey repeated h Press RETURN As shown in Figure 4 1 the screen will now show all 15 Control Board PV tests Tests that pass will be indicated by 0 failures will be indicated by 1 The screen will also show the number of times the tests are run the number failures RESULTS Slot 6 200NHz Timing CONTROL BOARD Tue TESTED 2 SHORT FAILED 1 TER amp TRIG POSH TRANSITION TRIG pa ANE OR 5 B FOLLOWED EY STATUS Awaiting command _ run slot 6 Depedted _ eee m SRE TURN Figure 4 1 PV Test Display 16 channel system CTL 4 4 Performance Tests and Troubleshooting Model 64601A 4 20 KEYBOARD SETUP For running one PV test repeatedly 4 21 run one test at time repeatedly for signature analysis perform the following steps Fig
27. If there is no sales office listed for your area contact one of these headquarters offices NORTH CENTRAL AFRICA Hewlett Packard S A 7 Rue du Bois du Lan CH 1217 MEYRIN 1 Switzerland Tel 022 83 12 12 Telex 27835 hpse Cable HEWPACKSA Geneve ASIA Hewlett Packard Asia Ltd 6th Floor Sun Hung Kai Centre 30 Harbour Rd G P O Box 795 HONG KONG Tel 5 832 3211 Telex 66678 HEWPA HX Cable HEWPACK HONG KONG CANADA Hewlett Packard Canada Ltd 6877 Goreway Drive MISSISSAUGA Ontario L4V 1M8 Tel 416 678 9430 Telex 610 492 4246 EASTERN EUROPE Hewlett Packard Ges m b h Lieblgasse 1 72 A 1222 VIENNA Austria Tel 222 2365110 Telex 13 4425 HEPA A NORTHERN EUROPE Hewlett Packard S A Uilenstede 475 NL 1183 AG AMSTELVEEN The Netherlands 999 NL 1180 AZ AMSTELVEEN The Netherlands Tel 20 437771 OTHER EUROPE Hewlett Packard S A 7 tue du Bois du Lan CH 1217 MEYRIN 1 Switzerland Tel 022 83 1212 Telex 27835 hpse Cable HEWPACKSA Geneve MEDITERRANEAN AND MIDDLE EAST Hewlett Packard S A Mediterranean and Middle East Operations Atrina Centre 32 Kifissias Ave Maroussi ATHENS Greece Tel 682 88 11 Telex 21 6588 HPAT GR Cable HEWPACKSA Athens EASTERN USA Hewlett Packard Co 4 Choke Cherry Road Rockville MD 20850 Tel 301 258 2000 MIDWESTERN USA Hewlett Packard Co 5201 Tollview Drive ROLLING MEADOWS IL 60008 Tel 312 255 9
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29. S830 CTOTLZz0024 U 63 6 0000 CTOTLZx 0024 63 8 3836 CTOTLZz12318 U 63 9 0000 CTOTLZz 1253519 U 63 10 high U 63 12 383A CTOTLZz12218 U 83 13 high U 7 1 high U 76 2 HOF U 76 4 6037 U 76 6 2493 76 10 F urF U 76 12 CANS 76 14 CUAS U 76 18 high UPF amp 1269 S80H P316 U 77 6 5632 77 7 BAFC LU 77 8 low U 77 10 CUS uU 77 12 77 13 high U 77 14 high U 77 16 CAHS 77 17 high 0 77 18 low U 77 19 low U 77 20 high U 77 21 8779 U 77 22 high 78 1 high U 78 2 Besa CTOTL Zi 0024 U Z high 78 Low U 7 amp 8 low U 78 low 78 high JU 78 FESB U 28 10 high 78 11 AHAU 78 12 9023 Land M M Por og CRS OF TO NDE CR Li CTL 4 88 U 28 13 CULA U 78 14 AU 73 78 18 Sse U 29 1 low U 79 2 iow 79 3 856 U 79 4 L 29 E AUTA U 79 amp 79 7 9025 79 9 0 28 79 10 C384 uU 79 11 j 79 12 2033 U 79 13 Tow U 79 14 law J 79 15 Low a 580H U 80 CIC u 80 2 u go 816 U 86 2034 CHR tN DS U 80 6 FF3L 8 2 C584 U 30 8054 80 10 Cesar U 80 11 H49C U 80 12 368C Wi 80 138 Low 80 14 low 80 15 low U 8i 1 high U ai 2 Ble 3 CUS 81 4 MUAL U 81 U 81 6 81 7 SHA U 81 9 0000 CTOTLZ 12519 U 81 10 APCS U 81 11 SH6n U 81 12 14 U 81 13 2826 200019 U 61 14 1281 U 81 18 H0
30. U 38 38 U 38 10 38 12 U 38 13 u 38 14 U 38 15 38 17 TONT 4293 1334 high low ACP 3 high 98062 FSS HF OS FSS high 0000 CTOTLZz0260 U 38 18 UJ 38 19 U 38 20 U 38 24 39 01 U 39 U 39 6 U 39 9 U 4 1 U 40 3 low high high HF OS PPL 4984 low 4293 high 0000 CTOTLZ 0003 40 U 40 7 U 40 9 U 40 10 U 40 11 40 12 U 40 14 42 1 U 42 3 U 42 4 42 U 42 6 42 7 U 42 9 U 42 10 HF OS 0000 934 acP3 08000 HF 03 9 49 high CFFC 9366 810C low high Performance Tests and Troubleshooting Model 64601A Li 42 11 42 12 42 13 42 14 42 15 43 43 2 43 03 43 4 43 6 43 7 43 43 11 43 12 43 13 43 14 46 g 000 COND OR CB p SUF CF EF oca CP 3 3F64 high high AUSE OF amp F ACA 0636 high HOH HOHS sete ALA 4 53 3 17 S 44 3 1 4 22 4 97 PEY DEV PCY DEVY PLY DEV PCV DOY DOV DOY PEN DOV PCV DEVY POV DCU PCY DEV PCV DEY DEY DEV PEY DEY DOY DOV DEY pcu Li LJ Uu u u u u Lu u ui Uu u 0 0 u u 5 Ll 5 U u u st u u 3 U LJ u u s 50 9 30 10 30 11 90 18 50 14 51 01 31 2 Bie 4 aile 31 7 51 10 51 11 51 12 51 14 gg 1 52 2 5p 3 52 5 gen 6 52 12 13 55 2 55 4 55 5 55 6 Se UV 55 9 1334 lo
31. a The acquisition board DACs are set for an always trigger condition lasting a specified time b The delay counter U37 and the trigger enable counter U38 are set to zero c LE PDUR gt B is programmed true or LOW and HE BTRANSIT false or LOW In other words we specify level triggering and require the duration circuits to time out while the pattern is still true 4 53 Test Steps Description of software execution 1 H TRIG DLY is initialized false or LOW 2 The duration circuits are programmed for a 200us duration The DAC thresholds set to cause an always trigger for longer than 200us H TRIG DLY should be true at the status register U85 4 3 H TRIG DLY is initialized false 4 With the duration circuits still set for 200us the DACs are programmed to cause an acquisition board trigger signal lasting less than 200us H TRIG DLY should be false CTL 4 14 Performance Tests and Troubleshooting Model 64601A 4 54 TEST 8 TRANSITION TRIGGER B 000 test steps 123 4 55 Purpose This test checks the term generator transition circuits U42 and Uh3 Thresholds which simulate particular pattern programmed into the acquisition board DACs and the glitch chip U27 on the acquisition board is programmed to trigger on that pattern 4 56 Theory The B term generator transition circuit will cause a trigger on a transition away from or leaving the specified pattern when HE BTRA
32. 1 85 P1 CIRCUIT IMB INTERFACE U3 5 19 21 67 74 TRIGGER ENABLE COUNTER Theory and Schematics Model 64601A 130 HOLDING REG HE ENTRIG oj T g rl 2 lt 5 ul N u I CTL 8 34 TERM GENERATORS B HE LTRIGB TRIGGER ENABLE A SELECT MODE 1 SINGLE 2 SINGLE B 3 BOTH AeB 4 SEQUENTIAL PATTERN AeBLATCHED TRIGGER P O TIMING ANALYSIS CONTROL TRIGGER ENABLE 1 200 g 3 25 P O 941 TO BOARD 64601 66501 470 3 251 P O HE DCLK HE TR TR DRIVES IMB 6 ECL 7 0678 5 3 TRIGGER ENABLE COUNTER P 0 U38 9 stant Q H2 HE ENTRIG 69 7 70 1 15 ONE SHOT w SEE NOTE EN 5 ON SERVICE 14 ONE SHOT SHEET 2 IN 1 8 34 LE ENDRIVTR lt 78 LE TRDRIVE HE HRCLK 59 HE WNDNCLK CNTR CLK 24 AST4 AST2 HROUT ME DRIVE ONE SHOT OUT ENTAIG 6 ECL 3 7 J189 HE MASKME 2 1000 Le HE ENTAIG 4 HEATEST_ INTERNAL EX TERNAL HE ME 7 TRIGGER ENABLE HE MASKME 6 JU54B 2 HE MASKTE GATING HE MASKTE 114 E 1 43 HE PROCRESET 2 29 LE ENDRIVME 2 HE TRIGTEST 22 27
33. 4 U 82 1 Low U 82 2 Law U 92 3 high U 8 4 lou U 82 5 low 82 6 high U 82 8 high 82 9 low 32 10 high U 82 11 iow 82 12 high U 82 13 high U 83 1 amp 37P U 83 2 HCC ih 85 3 3934 CTOTL Z s129518 U 83 4 0000 U 83 4046 85 6 P301 U 85 8 1281 amp i 7 COOP U 83 10 14 Lu u Li ij V st f 85 15 14 84 1 high 2 0000 J 84 3 3834 CTOTLZx 024 U 84 4 high U 64 0000 U 84 6 3834 U 84 8 low U 84 9 high U 84 10 high 0 84 11 0000 84 12 high U 84 13 high U 38 low U 86 high 88 low u 88 H046 U BB 301 88 10 9PCU 88 11 low U 88 12 U35z2 88 13 FCSE U 89 low BY low U 89 low oye low U 89 low uU 89 11 low U 90 4 low 90 high 0 90 46 high U 9 7 low U 9 Low U 90 10 Low U 90 11 low U 90 12 high U 90 14 high 90 18 high SOG d fa Y DR eO cn U Pie amp high Sie 2 high U Pie 9 high U 91 30 high U 91 11 high U 91 12 high U 91 13 high U 91 14 high U 91 18 nigh U 92 1 high uU 92 2 high U 92 5 low Pee 7 iow uU 92 9 high 92 19 low U 92 12 high U 92 18 high U 93 1 high U 93 2 low oa low U 93 7 low U 93 9 high 93 10 high 93 12 high 935 15 high U 94 1 high 94 2 0000 CTOTLZ 125 19 3 uU 94 high 94 iow Fe low uU 4 Low U 94 high uU 94 SOSA CTOTLZz0024 94 10 high 94 11 UPF6 94 12 1269 U 94 13 SBOH U 94 14 PBIS U 94
34. END OF TRACE H TRIG DLY TRACEPOINT U47 a 9 8 U57 X TRIG 1 Qquvoaus3HIOnN TRIGGERS A B LB TERM TRIGGER TRACEPOINT GENERATORS HE PATT ENABLE SELECTION pub dh TP8 i X TRIG 2 FROM ACQUISITION BOARDS 974 B B RUN HALT U77 7 HE DLCK SYNC 9 sng DNIWIL C83 R35 R37 86 TP11 R36 LE TE W CTL 8 24 QHVOSH3HLONW Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC 16 16 12 L D0 11 OE 9 P O TIMING ANALYSIS CONTROL BOARD 64601 66501 3 Y CPU INTERFACE Ref Des HP Part No Mfr Part No pe BOARD ID 1001H 2 TP11 e 16 049 64 1820 1052 MC10125L 8 069 1820 1400 10104 L 00 7 L D0 7 L 2 4 076 1820 1641 SN74LS365AN gt B 5 4 wc 2008248 0 15 5 ues 1820 1917 74LS240N 81 86a 9 2 086 1820 1173 MC10124L 6 HE RESET H U88 1820 1322 SN74S02N E u89 1820 0269 SN7403N 4 ANALYZER 090 1820 279
35. MC101768L 2106331 MC101761L MC1 0131P 2106103 SN741 S365SAN SN741 81616N 64601 10002 64601 10001 SN748174N SN74LS00N SN74851N SN74874N SN74L8240N MC10124l 2106331 SN74802N SN740 3N 1820 2799 SN74LS138N SN741 8174N SN74LS174N 93581606 93816DC 741 81616N 38N 3173 SN74811N SN74874N SN74804N 1200 0541 1200 0607 1200 0607 1200 0607 1200 0607 1200 0607 1200 0659 1200 0607 1200 0638 1200 0541 1200 0541 1200 0541 1200 0639 1200 0607 1200 0638 1200 0607 1200 0607 1200 0607 1200 0607 1200 0539 CTL 6 7 Replaceable Parts Model 64601A Table 6 2 Replaceable Parts List Reference Designation Description S CKET IC 18 CONT 3L 28480 1200 0539 SOCKET IC 18 28480 1200 0539 16 CONT DJ IP 8L 1 22 CONT DI 2848 1200 0612 SOCKET IC 16 CONT 01 PS 2 1200 0607 A1XU58 1200 0539 ALXUS9 1200 0539 ALXU76 1200 0607 A1 XU77 1200 0612 1 078 1200 0607 gt 16 CONT 28480 1200 0607 50 16 CONT SL 28480 1200 0607 14 CONT 28480 1200 0638 S CKET IC 20 CONT Y 28480 1200 0639 SOCKET IC 14 CONT IP SL 28480 1200 0638 079 1200 0607 1 80 1200 0607 61XU84 1200 0638 61XU85 1200 0639 A1XU88 1200 0638 14 CONT 28480 1200 0638 16 CONT 45 1200 0607 gt 16 CONT D 28 1200 0607 16 CONT DXP SLDR 1200 0607
36. Packard Sales Service Office for service or repair attach tag showing owner with address complete instrument repair number and a description of the service required 2 31 Original Packing Containers and materials identical to those used in factory packing are available through Hewlett Packard Offices Mark the container FRAGILE to ensure careful handling In any correspondence refer to the instrument by model number and complete repair number CTL 2 5 Installation Model 64601A 2 32 Other Packing The following general instructions should be used for repacking with commercially available materials a CTL 2 6 Wrap instrument in heavy plastic or paper If shipping to Hewlett Packard Office or Service Center attach tag indicating type of service required return address model number and complete repair number Use a strong shipping container A double wall carton made of 350 pound test material is adequate Use a layer of shock absorbing material 70 to 100 mm 3 to inches thick around all sides of the instrument to provide firm cushioning and prevent movement inside container Seal shipping container securely Mark shipping container FRAGILE to ensure careful handling In any correspondence refer to instrument by model number and complete repair number Operation Model 64601A SECTION III OPERATION The operation of the Model 64601A is a function of the system software Comp
37. S 4 i 2 8 8 _ 12 gt MODE ADDR REG LATCH 12 x 3 z i zi 3 lt lt 9 DATA o 3 o INTENSITY 453855 GLITCH DUAL THRESH GRATICULE BLANKING CHAR RSOR L HORIZ SYNC k START PRESENT MID ADDRESS BLANKING PAST VERT SYNC CHAR DISPLAY 4 poi ROW RAM GLITCH CHAR MUX DATA pus ROM SYNCHRONIZING LATCH VID bor DOT LINE CHARACTER 3 T 4 LINE POSITION FORNA SEGMENTS 2 COUNTER 25MHz 12 5MH2 HORIZ amp VIDEO ENABLE VERT BLANKING MOTHERBOARD VIO9K9 soraeueqog pue Theory and Schematics Model 64601A 8 48 DISPLAY DRIVER Figs 8 7 8 15 8 16 8 49 The timing analyzer has its own display driver which provides the timing characters enhancements and blanking to the mainframe for display The mainframe receives the display driver video programs the display to start at a particular portion of the screen supplies horizontal and vertical synchronizing pulses and selects the order and number of the probe channels displayed 8 50 The display driver produces a 512 by 240 dot display Each character is two dots wide in the 8 channel mode a character is 30 dots high and in the 16 channel mode 15 dots high 8 51 The display driver has two modes of operation In the programming mode the mainframe presets the character counter the character row counter and the dot line counter with starting addresse
38. SANTA CLARA WILMINGTON ALTO SOMERVILLE SUNNY VALE CAZENOVIA NORTH ADAMS FLORENCE PHILADELPHIA See introduction to this section for ordering information 85008 94042 46711 75057 92129 16701 02876 06226 19108 6 9 Replaceable Parts Model 64601A NOTES CTL 6 10 Manual Changes Model 64601A SECTION VII MANUAL CHANGES This section normally contains information for backdating this manual for models with repair numbers prior to the one shown on the title page Because this edition includes the information for the first repair number there is no backdating material CTL 7 1 Manual Changes Model 64601A NOTES 7 2 Theory and Schematics Model 64601A SECTION VIII THEORY AND SCHEMATICS 8 1 INTRODUCTION 8 2 This section contains block diagrams theory of operation mnemonic tables and schematics Some theory of operation is also given in SECTION 8 3 LOGIC CONVENTION 8 4 Logic states are defined as follows 0 False negated inactive unasserted state 1 True active or asserted state 8 5 Voltage levels representing logic states LOW L The more negative of two voltage levels HIGH H The more positive of two voltage levels 8 6 Signals may be either high true or low true as indicated by the mnemonics on the service sheets 8 7 The 64601A includes both TIL and ECL ICs Worst case voltage levels for troub
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41. The HOLD state in which the timing analyzer has triggered and is told by a second analyzer to hold its data 3 The RESET state in which the timing analyzer is told by another analyzer to RESET and watch for another trigger condition CTL 4 38 4 85 4 86 10 Performance Tests and Troubleshooting Model 64601A POST QUALIFY MODE RESET DACs are set for an always trigger condition Stimulus board drives LTE true DACs are programmed for a trigger condition LTE is set false This should initiate a RESET Since the DACs are set for trigger the measurement should still be running incomplete because LTE did reset the analyzer and there was still no trigger DACs are set for an always trigger condition The analyzer should trigger and stop the measurement FOST QUALIFY MODE HOLD DACs are set for always trigger Test board drives HTR true Stimulus board drives LTE true DACs are set for never trigger Stimulus board drives LTE false There should still be a trigger because HTR which is a HOLD line in the POSTQUALIFY mode is still true HOLD prevents a RESTART The stimulus board now drives HTR true The timing analyzer is still programmed for the POST QUALIFY MODE but it no longer drives HTR DACs are set for never trigger Initiate a HOLD from the stimulus board by driving HTR true Set the DACs for always trigger Verify that HOLD HTR prevents a trigger
42. The supplementary tests use different access instructions They are described after the the regular 15 PV tests 4 5 Signature analysis instructions and tables are given at the end of the section 4 6 The performance verification tests are also used in troubleshooting 1 They help to isolate troubles to particular blocks and within particular blocks 2 Each test corresponds to a one signature loop when running signature analysis 4 7 Each test is shown on the mainframe screen as bracket group of O s The 0 s correspond to steps ina particular test When the board fails a test step the 0 for that step becomes a 1 CTL 4 1 Performance Tests and Troubleshooting Model 64601A 4 8 TROUBLESHOOTING TECHNIQUES 4 9 Although each of the PV tests checks a specific circuit block signals from other blocks are used A failure in one block can be caused by failures in blocks upstream When failures occur on a given PV test check the schematics in TABLE 4 1 below for each test Table h 1 Performance Tests VS Schematic NUMBER TEST CHECK ON SCHEMATIC d SERIAL PROGRAMMING 1 2 2 RUN HALT RESET 1 7 3 TRIGGER 4 5 6 m DELAY COUNTER AND TRIGGER POSITION 1 5 WINDOW 1 6 RATES INTERVAL 5 7 LESS THAN INTERVAL 5 8 TRANSITION TRIGGER B 5 9 DISPLAY DRIVER 8 9 10 RATES INTERVAL A m 11 LESS THAN INTERVAL m 12 TRANSITION TRIGGER A m 13 AND 4 5 6 14 OR 4 5 6 15 B FOLLOWED BY A 4 5 6 4 10 Check bo
43. U 98 2 4743 98 3 7079 U 98 4 FFA 0 98 4AA4 98 6 APP U 98 7 98 9 38365 CTOTLZ2 25037 98 10 8766 98 11 CUYO 98 12 87656 98 13 9684 98 14 0000 98 15 383A 99 41 3836 CTOTLZ 0001 U 99 2 3836 2 0028 U 99 3 14 U 99 4 SHEA U 99 5 U 99 6 SH64 U 99 8 BAA 99 9 SUH 99 10 6uH 99 11 46854 99 12 3834 CTOTLZ 0001 99 13 high U100 1 high U100 2 8424 0100 35 0000 2 12519 U100 4 high 1100 5 0100 4 9907 Ui00 8 106 Ui 9 993F U100 10 high 4100 11 0000 CTOTLZz12519 4100 12 6900 0100 13 high U101 1 39836 U101 2 0000 U101 4 low U101 5 0000 CTOTLZ 25038 0101 10 low 0101 11 high U1 01 12 high 11101 13 low 6460160 Timing DISPLAY TEST HUAL MODE Qual high ST Lao Lo Lo 1T LI U U u J Lj u u U U u U Uu U U 0 us u 0 U U U TA THRESHOLD CLOCK THRESHOLD SP L THRESHOLD Performance Tests and Troubleshooting Model 64601A Control Board AND PATTERN ttl ttl cation of ST SP START tp 10 cation of QUAL STOP cation of CLOCK cation of GROUND L 56 1 high Sbe 2 lou S6 low S6 2 high 567 9 high 58 10 high 50 12 low 50 18 high S7 1 Peis SBH 37 3 1289 4 UPF6 u7 9 8779 2 6 gePu 7 S7 7 WOE 277 high
44. aquisition board Not used on the 200MHz system Enables trigger into the term generator from a fourth acquisition board Not used on the 200MHz system Selects the sample clock frequency Enable display glitch memory Holding register clock Clocks programming into the 130 1 control register Horizontal synchronizing signal for display from the mainframe Inverse video to motherboard Load enable Enables presetting the display counters with an address for the display RAMs during the programming mode Load duration Clocks in pattern duration specification Latched B trigger signal HE TRIGB must be false A trigger will occur when A occurs anytime after B Mask master enable Masks the IMB master enable signal Must be low if ME from the IMB is to enable the trigger HE MASKTE H MEMFUL L MEMWRT L MODEN HE PATT H PATTOUT BNC LE PDUR gt A LE PDUR gt B HE phi2C1l HE phi2C2 HE phi2 L PROGRAM LE PVCLK HE PVSTOP Theory and Schematics Model 64601A DEFINITION Mask trigger enable Masks the IMB trigger enable signal Must be low if TE from the IMB is to enable the trigger Memory full Indicates when memory has been completely filled with good data at least once Status bit to processor Enables write to display memory Mode enable Enables display mode register Pattern trigger Internal trigger signal after being qualified by term generators but
45. l 4 high U le 38345 CTOTLZ 0025 gt U 1 amp 0000 TOTLZ 0024 U l 7 0000 U amp 1 9 38360 CTOTLZz0001 61 10 high U 51 11 CC3A 61 12 LU 61 13 35834 CTOTLZ 0024 U 61 14 3834 U 61 19 3836 CTOTLZ 0024 U 2 1 high 62 2 high U 2 3 0000 CTOTLZ 1 2519 U 62 4 0000 CTOTLZz125819 U 62 5 0000 CTOTLZz 12519 0 62 6 3836 TOTLZ 0024 U amp 2 3836 TOTLZ 0024 U 2 9 0 62 10 4352 62 11 1166 U 62 12 38034 CTOTLZ 00012 U 62 13 3936 U 82 14 high U 82 18 Low U 63 1 high 0 63 2 3836 CTOTLZ 0024 U 63 4 high 63 5 383A TOTLZ 0024 U 63 6 0000 CTOTLZ0024 U 63 8 3836 CTOTLZ 12518 U 63 9 0000 CTOTLZz1298192 U 63 10 high U 63 12 383A TOTLZ 12518 0 63 13 high U 76 1 high 76 2 HOeF U 76 4 6037 U 76 6 2493 U 76 10 FeUF 76 12 CAHS 76 14 CU43 U 76 15 high 77 1 U 77 2 1289 0 77 3 S80H U 77 4 P816 U 77 U 77 6 5632 U 77 7 SAFC U 77 8 low U 77 10 CUAJ3 U 77 12 Four U 77 13 high U 77 14 high 77 16 77 17 high 77 18 low U 77 19 Low 77 20 high 0 77 21 8779 77 02 high 0 28 1 high 78 2 3836 CTOTLZ0024 78 3 high 78 4 low U 78 low U 78 6 low 28 2 high 28 9 FC68 28 10 high 78 11 78 12 9023 U 78 13 U 78 14 78 15 U 79 1 U 79 2 U 79 3 U 79 4 U 79 5 U 79 6 U 79 7 U 79 9 U 79 10 U 79 11 U 79 12 U 79 13
46. option test RETURN b The screen should list all the option boards installed in your system Type in the slot number for the 64601A control board RETURN Press softkey run d Press softkey slot e The screen should list the timing analyzer boards in the system Type in the slot number for the 64601A control board f Press softkey test g The screen should list the 15 control board PV tests Type in 10 h Type in cal RETURN CTL 5 6 Adjustments Model 64601A 5 21 16 channel adjustment procedure Rh through R6 When test 10 is displayed nine digits are shown five in braces and four brackets We are concerned only with the four bracket digits four digits in brackets should all be O If they are not procede as follows 1 Adjust until the second digit from the right is 0 2 Adjust R5 until the third digit from the right is 0 Adjust R until the fourth digit from the right is O The first digit from the right should be 0 when the other three are 0 Press the stop softkey RETURN ON W Press the end softkey RETURN CTL 5 7 Adjustments Model 64601A NOTES 5 8 Replaceable Parts Model 64601A SECTION VI REPLACEABLE PARTS 6 1 INTRODUCTION 6 2 This section contains information for ordering parts Table 6 1 lists abbreviations used in the parts list and throughout the manual Table 6 2 lists all replaceable parts in reference designato
47. ttl Location of ST SP START tp 12 Location of QUAL STOP tp 12 Location of CLOCK tp 11 Location of GROUND gnd Til U age 49 85 19888 LJ 0 42 12 Low ij 3 49 13 1888 Uu U 58 4 low U bA f YARE LI U 64 12 CHF L ij 64 13 low i U 85 FiSu CT TOTLZ 0005 u oo acea u u 8 1888 0 V d Qi PO 82 FA413 u low u U 85 ASP U U Sse low 85 9 7158 u 85 11 CHE Lu U 85 12 CLOC u U 85 18 FABE 0 u 88 14 1483 LI U 89215 r 21 0 uU BIG 8208 T U 85 17 low u U 85 18 338A LJ U 85 19 U CTOTLZ 008 u 0 u U gi OS fU CTL 4 82 neq edge pos edge pos kigh 13H7 63758 644p 10 L3H 10 10 0000 i 10 10 10 CH od OQ DO lt TLZ 0130 10 10 637 10 11 HUAC 10 12 10 13 HUAC 10 1 2 10 1 ABAD 122 high 11 6421 11 228 11 87P5 11 11 6451 11 H228 11 0000 2 0120 10 87P5 TET 11 12 11 13 P202 11 14 H ul 11 15 2779 15 high 13 2047 13 87P5 13 low 13 P202 15 9 low ON GG gt O po b OPI MG Dr V ix i f Rad UM 1 ped CA DU Pao b Q c Oi Cs Pod 4 2 15 e 15 15 U 19 210 11 12 13 14 low H0111 Q779 3
48. 0093 73 6 8U8H 0 73 7 8006 CTL 4 54 Performance 646016 Timing Control Board DELAY COUNTER amp TRIG NORM MODE POSITION 4 DATA THRESHOLD HIGH ttl amp ecl CLOCK THRESHOLD ttl ST SP L Location Location Location Location TTL i Uu u u 0 u i 49 4 49 5 49 12 49 13 64 4 54 12 54 13 85 1 gae 2 THRESHOLD tti of ST SP START tp of QUAL STOP tp 12 of CLOCK tp 11 of GROUND and ASHE 7551 CUBI low 9 5840 081 5931 AH26 78P9 7331 UH28 0052 ELBI PEAH 584U 77A PPS 7396 4019 Cui amp 7Fi S31 9205 71975 iow HLY 4019 high EP ER high HOLS SOF 1 Tests and Troubleshooting Model 64601A UH 58029 Temporarily connect U13 pins 12 and 14 together 12 neg edge pas edge neq edge U 9i1 3 U 91 4 HEO 0000 CTOTLZ 0199 91 5 U 91 6 U 91 12 U 91 13 0 91 18 Uile 3 uigi 9 0000 high BP 22 NISI 1FH6 4913 u bhagh REP 76FZ 4 BP Yer 23P7 TG6F2 2587 75 76F2 0000 CoH high low 666 0080 56 12 PSAI 36 13 8032 36 14 PIAI 56 123 high 356 17 0900 36 18 low 36 19 high 36 20 high 46 24 8032 32 01 0000 37 3 1P2U 32 4 UNS 32 8 high 37 7 7 low 37 8 9200 37 9 ABUU 37 10 0000 47 12 PHAI 32 13 8032 37 14 PSA1 37 19 high 37 17 0000 i EOS ME ME Y t GN es d 4 55 Performance Tests and
49. 1001 4 1 8 0 5181 64 1 8 0 1001 C4 1 8 TO 1001 F C4 1 8 TO 301R F 4 1 8 0 12301 C4 1 8 T0 1501 F 4 1 8 0 4328 4 1 8 0 261 0 CA4 1 8 TU 162R F 4 1 8 0 398 2 C4 1 8 T0 39R2 F 4 1 8 0 3982 6 5 1 Replaceable Parts Model 64601A Table 6 2 Replaceable Parts List Con t Reference HP Part Designation Number Description Mfr Part Number 1R21 0757 0391 A1R22 0257 0391 ALR22A 757 0391 61623 1624 0757 0407 A1R25 0757 0416 ALR26 0757 0416 1R27 0757 0416 ALR28 0757 0416 41829 0752 0407 A1R30 0757 0407 RESISTOR 39 2 1 129M F TC 24546 4 1 8 TO0 39R2 F RESISTOR 39 2 1 125W F T 24546 C4 1 8 T0 39R2 F RESISTOR 39 2 1 125W F T 4 24546 C4 1 8 T 39R2 F RESISTOR 200 1 1254 2 24546 C4 1 8 T0 201 F RESISTOR 200 24546 C4 1 8 T0 201 F TOR 511 24546 C4 1 8 T0 S11R F RESISTOR 511 T 24546 C4 1 8 TO0 S11R F RESISTOR 511 T 24546 4 1 8 T0 S11R F RESISTOR 511 T 24546 4 1 8 0 5118 RESISTOR 200 100 24546 C4 1 8 T0 201 F RESISTOR 200 0 100 24546 C4 1 8 T0 201 F ONUN O TA TT TY 7 TF e 81831 0257 0426 1632 0257 0427 1633 0757 0414 ALR34 0257 0280 AIRSS 0757 0401 1 3K 1X 125W F 0 100 24546 C4 1 8 T0 1301 F SISTOR 1 8 1 125W 0 100 24546 C4 1 8 T0 1501 F SSISTOR 432 1 125W 0 100 24546 C4 1 8 T0 432R F RESISTOR 1K 1X 125W F 0 100 24548 C4 1 8 T0 1001 F RESISTO
50. 12 APCS 4101 10 low 94 6 low U 97 13 3834 U101 11 high U 94 7 high TOTLZ 12518 0101 12 high 94 9 3834 U 98 1 high 4101 13 Low TOTLZ 0024 U 98 2 AUA 94 10 high 98 3 977H 94 11 UPF amp U 98 4 7457 94 12 1249 98 5 4 U 94 13 SBOH U 98 6 729P U 94 14 16 U 98 2 4AA4 94 15 8984 U 98 9 3836 U 95 1 high TOTLZ 25037 95 2 0000 U 98 10 874A 12519 98 11 090 U 95 3 high 98 12 BAR 95 4 high 98 13 9684 95 5 low 98 14 0000 U 95 6 low U 98 15 3834 U 95 7 high U 99 1 3834 CTOTLZ 0001 CTL 4 92 Adjustments Model 64601A SECTION V ADJUSTMENTS 5 1 INTRODUCTION 5 2 This section describes adjustments and checks required to return the instrument to peak operating capability after repairs have been made 5 3 SAFETY REQUIREMENTS 5 4 Although this instrument has been designed in accordance with international safety standards general safety precautions must be observed during all phases of operation service and repair of the instrument Failure to comply with precautions listed in the Safety Summary at the front of this manual or with specific warnings given throughout the manual could result serious injury or death or damage to equipment Service adjustments should be performed only by qualified service personnel 5 5 EQUIPMENT REQUIRED 5 6 HP 64000 series mainframe 2 HP 64602 66501 200MHz Data Acq Boards 2 HP 64604
51. 12 CULA 78 14 7 28 18 USSR 79 1 iow U 79 2 high 79 3 99866 U 79 4 u 79 5 APS 79 U 79 9023 uU 79 aua U 79 10 9286 uU 29 11 7923 79 12 PH28 0 79 13 low U 29 14 lou 1 29 15 low U 80 1 580 U 8 2 Cac 80 3 HO 2F 4 CUIA TNT u 80 PEIS U 80e PH28 80 5 7923 80 7 9286 80 9 CH6 amp F U 80 10 8556 U 80 11 2900 U 80 12 8424 U 80 13 low U 80 14 lau U 80 15 low U Bl 1 high U 81 2 HUAI U 81 3 CUAS U Bi 4 HUAI U 81 suns U 81 6 CAHS 81 7 U 81 0000 CTOTLZS125919 U 81 10 APCS i 81 11 SHOA 0 81 12 14 81 13 3834 CTOTLZ 0001 U 81 14 883F 81 15 C383 U 82 1 Low U 82 2 low U 32 3 high 82 4 low U 82 low U 82 6 high U 82 amp high U 80 9 Low U 82 10 high Performance Tests and Troubleshooting Model 64601A U 62 11 lou U 82 high U 32 15 high 83 1 637P U 82 2 83 3 3836 TOTLZ 12518 gt 83 4 0000 CTOTLZ 1 2819 U 83 8 9 U 6 95 U 83 8 883F 0 83 9 88556 U 83 10 U 83 13 14AP U 84 1 high LU 84 2 0000 U 84 3 3836 CTOTLZ 0024 U 84 4 high uU 54 0000 U 84 5 383 U 84 8 low 84 9 high U 84 10 high U 84 11 0000 U 84 12 high U 84 13 high U 88 1 low U 8g 2 high U 88 4 low u 88 8 C383 U 88 9 9902 38 10 FF2A U 88 11 low U 88 12 4352 88 15 68 89 1 low 69 20 low U 89 4 low a low U 89 8 low U 89 11 l
52. 14 0000 U 38 15 high u 67 10 UFO U 17 18 low U 38 17 0000 U 67 11 1UAF U 34 1 high 38 18 low 67 12 3745 34 135 045C U 38 19 high ij 67 13 low 34 14 FA6H U 38 20 high U 67 14 HUSA U 34 18 F036 U 38 24 37U6 71 1 high 35 10 U 43 1 high 71 2 1UA F U 35 11 C amp CC U 43 2 high 0 71 3 2UUC LU 35 12 768H 43 4 SFAS 71 4 S3HC U 395 13 045C U 43 low Uu 71 7U03 Ue 35 15 72H6 43 2 51 U 71 6 1UAF U 36 1 000 U 43 9 high U 71 7 246 36 3 9020 43 10 low U 71 10 S3HC U 36 4 692C U 43 11 72H6 LU 71 11 29PH U 36 6 high 43 12 2H6 71 12 1446 U 35 7 low 43 13 Capo U 71 13 29 U 36 9 49P7 U 43 14 Cero U 71 14 14U6 U 36 10 692C U 43 15 0000 71 15 6P70 36 12 0000 49 6920 U 23 1 high U 36 13 3706 U 49 7 U 73 2 FFUS 36 14 0000 49 11 low U 73 3 8277 36 15 high 49 15 6909 73 4 P116 U 36 17 0000 0 54 1 high 73 5 790 U 36 18 low U 54 2 448 uU 73 6 FFUB u 36 19 high S4 3 148 U 73 7 8277 U 36 20 high U 34 4 9 01 73 10 P116 36 24 3706 54 5 73 11 U 37 1 0000 U S4 6 CPSH U 73 12 CPSH 37 UCAS U 54 7 U 73 13 U 37 4 1 U 54 9 3745 U 73 14 CPSH U 37 amp high 54 10 26746 73 18 7003 U 37 97 low 54 11 74053 U 86 2 7205 U 37 8 FUHA U 54 12 448 U 86 3 0000 37 9 6909 U 54 13 low U 86 12 3746 37 10 7337 U 54 14 4048 86 14 89 1 37 12 0000 U 54 15 3U7P 37 1
53. 16 60 17 60 19 61 1 ble 2 ble 3 H zF P816 CO1C SBOH ATP FSUE high 3834 1166 1166 edge edge pos pos pos 61 4 high U bl 3836 CTOTLZ 0025 bl 0000 TOTLZ 0024 U 61 9 383A 22000102 U 61 10 high 61 11 CCEA 61 12 CC34 U 61 13 3836 CTOTLZ 0024 U 61 14 383A U 61 18 383A CTOTLZ 0024 U 62 1 high U 62 2 high U 62 0000 CTOTLZ 12519 62 4 0000 CTOTLZ 12519 U 62 0000 2 128199 U 62 6 3836 CTOTLZ 0024 gt U 62 7 3834 CTOTLZ 0024 3 0 amp 2 9 USA U 52 10 0352 U 62 11 1166 U 62 12 38360 CTOTLZ O001 U 82 15 3834 U 62 14 high U 62 15 low U 63 1 high 63 2 3836 CTOTLZz0024 U 63 4 high U 63 5 3836 CTOTLZ 0024 U 635 6 0000 0024 U 63 8 3836 12518 gt 63 0000 CTOTLZz12919 U 63 10 high U 63 12 38356 CTOTLZz12518 63 13 high 76 7 1 high 76 2 H 2F 75 4 6037 76 6 2493 76 10 FSUF 76 12 CAHS 76 14 CUR 28 18 high 777 1 UPF65 77 1269 77 3 SB0H Cee eco oo oe C c U 77 4 816 U 77 uU 77 6 9682 U 77 7 SAFC uU 77 low U 77 10 CUA3 77 12 F amp UF 77 13 high U 77 14 high 0 77 16 CAHS U 77 17 high U 77 18 low 77 19 low 0 77 20 high U 77 21 8779 u 77 22 high 28 1 high U 70 2 3836 TOTLZ 0024 gt 78 3 high U 28 4 low U 78 5 low 78 6 low 28 2 high 28 9 FCB U 78 10 high U 28 11 AHAL 78 12 902 28
54. 2 0965 2 6 3248 7 7 1965 77 9 3248 7 10 u9es 7 12 3242 7 13 0965 7 15 0968 10 1 high 10 FS0C 3 4 10 3HUF 10 6 FS0C P285 10 9 0000 10 10 8402 10 11 1914 10 12 279 10 15 1904 10 14 279 0 10 18 6728 11 1 high 11 2 9433 11 3 4 HFP2 6 943 11 9 0000 10 HFP2 11 11 FOFS 11 12 CC97 11 13 FOFS CTL 4 75 Performance Tests and Troubleshooting Model 64601A U 11 14 CC U 56 19 high 054 100 0709 U 11 1 288A U 36 20 high 54 11 21655 13 1 high U 36 24 UFSC U 54 12 uU 13 2 9905 U 32 010 0000 U 54 13 low U 13 3 5222 U 37 3 10CA U 54 14 U 13 4 HFP2 u 37 4 28FH 54 15 0 13 5 low U 32 6 high 58 1 high U 13 Low U 37 7 lou ll SS 2 H916 13 2 FOF 0 32 8 U BE 4 U 13 9 lou U 37 9 916 0055 5 Fuse U 13 10 low U 37 10 0000 U 55e 6 low U 13 11 06097 U 37 12 0000 U 95 7 low 13 12 0002 U 37 15 UJC U 55 9 Q0HPA4 U 13 13 2084 U 37 14 0000 53 10 13 14 high U 37 159 high U 55 11 u 13 15 low 37 17 0000 U 55 12 3242 U 27 1 high U 37 18 low U 35 13 3220 U 27 high 0 32 19 high 4 3535 14 758 0 27 3 5806 U 37 20 high U 55 15 low U 27 4 9433 U 37 24 U96C U 67 1 high 27 low U 38 1 0000 U 67 2 Low U 27 6 POCP U 38 3 6728 67 3 law 27 7 U 38 4 10 U 67 4 CHAF U 27 9 high U 38 6 high U 67 96 U 27 10 low 38 7 lo
55. 305 859 2900 A CH CM CS E MS Hewlett Packard Co 5750B Hoover Blvd Suite 123 TAMPA FL 33614 Tel 813 884 3282 A CH CM CS E M Georgia Hewlett Packard Co 0 Box 105005 30348 ATLANTA GA 2000 South Park Place ATLANTA GA 30339 Tel 404 955 1500 Telex 810 766 4890 A CH CM CS E MP Hawaii Hewlett Packard Co Kawaiahao Plaza Suite 190 567 South King Street HONOLULU HI 96813 Tel 808 526 1555 A CH E MS Illinois Hewlett Packard Co Box 1607 304 Eldorado Road BLOOMINGTON IL 61701 Tel 309 662 9411 CH MS Hewlett Packard Co 1100 31st Street Suite 100 DOWNERS GROVE IL 60515 Tel 312 960 5760 CH CS Hewlett Packard Co 5201 Tollview Drive ROLLING MEADOWS IL 60008 Tel 312 255 9800 Telex 910 687 1066 A CH CM CS E MP Indiana Hewlett Packard Co P O 50807 7301 Shadeland Avenue INDIANAPOLIS IN 46250 Tel 317 842 1000 A CH CM CS E MS lowa Hewlett Packard Co 1776 22nd Street Suite 1 WEST DES MOINES IA 50262 Tel 515 224 1435 CH MS Hewlett Packard Co 2415 Heinz Road IOWA CITY IA 52240 Tel 319 351 1020 CH E MS Kansas Hewlett Packard Co 7804 East Funston Road Suite 203 WICHITA KA 67207 Tel 316 684 8491 CH Kentucky Hewlett Packard Co 10300 Linn Station Road Suite 100 LOUISVILLE KY 40223 Tel 502 426 0100 A CH CS MS Louisiana Hewlett Packard Co 0 Box 1449 KENNER LA 70063 160 James Drive East ST RO
56. 41 02 Telex 410770F A CH E MS P Hewlett Packard France 64 rue Marchand Saillant F 6 1000ALENCON Tel 16 33 29 04 42 Hewlett Packard France Boite Postale 503 F 25026 BESANCON 28 rue de la Republique F 25000 BESANCON Tel 16 81 83 16 22 CHM Hewlett Packard France 13 Place Napoleon F 29000 BREST Tel 16 98 03 38 35 Hewlett Packard France Chemin des Mouilles Boite Postale 162 F 69130 ECULLY Cedex Tel 16 78 833 81 25 Telex 3106 17F A CH CS E MP Hewlett Packard France Tour Lorraine Boulevard de France F 91035 EVRY Cedex Tel 16 6 077 96 60 Telex 692315F E Hewlett Packard France 5 avenue Raymond Chanas F 38320 EYBENS Tel 16 76 25 81 41 Telex 980124 HP GRENOB EYBE CH Hewlett Packard France Centre d Affaire Paris Nord B timent Amp re 5 tage Rue de la Commune de Paris Boite Postale 300 F 93153 LE BLANC MESNIL Tel 16 1 865 44 52 Telex 211032F CH CS E MS Hewlett Packard France Parc d Activit s Cadera Quartier Jean Mermoz Avenue du Pr sident JF Kennedy F 33700 MERIGNAC Tel 16 56 34 00 84 Telex 550105F CH E MS Hewlett Packard France Immueble Les 3 B Nouveau Chemin de la Garde ZAC de Bois Briand F 44085 NANTES Cedex Tel 16 40 50 32 22 CH Hewlett Packard France 125 rue du Faubourg Bannier F 45000 ORLEANS Tel 16 38 68 01 63 Hewlett Packard France Zone Industrielle de Courtaboeuf Avenue des Tropiques F 91947 Les Ulis Cedex ORSAY Tel 6 907 78 25
57. 4101 11 high 14101 12 high 0101 1535 Low CTL 4 89 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Board DISPLAY TEST ARD PATTERN QUAL MODE VH 39836 Qual high DATA THRESHOLD ttl CLOCK THRESHOLD tt ST SP QL THRESHOLD ttl Location of ST SP START tp 10 pes edge Location of QUAL STOR US9 12 Ug1 13 pos edge Location of CLOCK tp edge Location of GROUND gnd TTL U 56 1 high 58 16 SAFC u S6 2 high U 58 17 5632 U 56 5 high U 59 41 P816 U 56 7 high U 59 2 580H U 56 9 high U 59 3 1249 U 56 10 high U 59 4 UPFS U 56 12 low 59 5 8779 U 56 15 high U 59 amp 52 815 59 7 2693 U 57 580H U 59 8 high U 52 1249 59 10 low U 57 UPF amp 59 12 ACP2 U S7 8279 U 59 13 HUZA U 52 aaPu 59 14 4521 LJ GP HORE 59 15 98650 CO 6 OF f DO K U S7 high 59 16 SAFC 57 12 4cpe 60 1 Low 0 52 13 HURA 60 2 816 57 14 4521 60 3 HO2F U 57 15 986 U 60 4 6037 57 16 SAFC 60 C 1C U 37 17 563 0 60 6 9549 U 58 1 816 U 60 7 2693 U S8 2 U 60 8 9549 U HE 3 1249 U 50 9 4AA4 U GE UPFS U 60 11 0000 U S8 8779 CTOTL Z3 u 58 6 60 12 Hoe U 58 7 5037 U 60 13 U S8 8 high U 60 14 01 983 10 low 0 80 18 Seon 0 58 12 ACPZ U 60 16 63 58 13 HURA U 60 17 U 58 14 4321 61 1 3836 U 58 13 986 CTOTLZz12518 U l 2 1166 U l e 3 1166 CTL 4 90 U
58. 57 10 low ACP2 HURA 4521 9860 SAFC 5632 pol HE OH 12409 UPF amp 8279 6037 high 58 10 low 4CP2 HUZA 4521 099 12 or U 81 13 tp 8 SaF UC 35632 P816 S80 1269 UPF amp a779 U 58 16 38 17 U 59 1 So U 59 U 9 U Sg U m U 39 2693 U 59 8 high 59 10 low U 39 12 ACP2 U 59 135 HU2 59 14 4321 59 185 9860 59 15 SAFC U 59 17 5632 U 60 1 low U 60 2 P816 U 60 3 HO2F 50 4 6037 U 60 COICC U 9549 U 60 7 2693 LU 60 8 9549 U 60 9 4664 60 11 0000 CTOTLZ 12519 U 60 12 HO2F U 60 13 P816 60 14 CMC U 60 15 5580H U 60 16 amp 37P U 60 17 FSUF U l 1 38365 CTOTLZ 12518 01 2 1166 U bl 3 1166 NECS Cr p tito 35836 pas edge pos edge pos edge U le high U ble 3835 2 0 URE U 61 amp 0000 CTOTLZZz 0024 U l 2 8000 U bl 9 35838 000107 61 10 high U 61 11 034 U 61 12 CC34 U 61 13 3836 TOTLZ 0024 U 61 14 383A U 81 18 3836 TOTLZ 0024 U 62 1 high amp 2 2 high U 62 3 0000 CTOTLZz12519 4 0000 CTOTLZz 125192 62 0000 CTOTLZz 125919 U 62 6 383n CTOTLZ 0024 U 62 7 3838 CTOTLZz00242 U 62 9 usse 2 10 1352 U 62 11 1166 U 62 12 3838 CTOTLZ00012 i 62 13 39356 U 62 14 high U 62 15 low U 63 1 high CTL 4 87 Performance Tests and Troubleshooting Model 64601A U 53 2 383A CTOTLZ 0024 i 3 4 haigh U 63
59. 58 4 2H21 U 52 6 8594 U 38 6 high U 52 12 508 U 38 7 low 82 15 HFAC 38 8 U 55 1 high U 38 9 high uU 3535 2 ANP U 38 10 vAPF U 55 4 2PP U 38 12 6HH9 U 55 PHHU U 38 12 AS08 uU S5 6 low U 38 14 uU 88 02 low U 38 19 high U 58 9 FCAS U 38 17 8000 U 33 10 lou U 38 18 low U 55 11 CAIP U 38 19 high U 55 12 ASU U 38 20 high 0 55 15 U 38 24 2508 U 55 14 734C U 39 1 8 U 55 18 low U 39 HFAC 64 3 0000 U 39 6 low U 64 7 ASA 39 9 U 54 11 aF85 CTL 4 58 646018 Ti RATES T NORM MODE DATA THRE CLOCK THR ST 3P QL Location Location Location Location U 44 44 U 44 44 U 44 U 44 44 44 U 44 9 U 44 11 U 44 12 U 44 13 44 14 44 15 U 44 16 U 44 17 0 44 18 U 44 19 49 4 U 49 5 49 12 U 49 13 85 1 U 85 2 85 3 4 Cn p 4 U 85 18 U 85 19 U 86 Performance Tests and Troubleshooting Model 61601A wing Control Board NTERVAL SHOLD HIGH ttl amp ecl ESHOLO ttl THRESHOLD tti of ST SP START of QUAL STOP ef CLOCK tp 1 of GROUND hagh 4999 SCCe F 74C 159C 3PA42 CRC C7 0H OHF A F036 AUCF FiFi H3A 3P 30 3078 3299 C233 low 627 u7F low 6969 FOSS OFAC OPOP WPF USPH low UIC BP a 4431 amp FCU CCUS low H18U F036 7205 tp 1 Temporarily connec
60. And if there second Acquisition Board it will go in the next higher slot In other words Acquisition Boards are installed on either side of the Control Board SEE FIGURE 2 1 2 11 Up to two Acquisition Boards may be installed with one Control Board forming one Timing Analysis Subsystem 2 12 Inter Module Bus IMB 2 13 Some systems may contain a combination of a timing analyzer and another type of analysis subsystem The Inter Module Bus located at the upper left hand corner of the timing boards when viewing from the component side connects two or more analysis modules together for controlling and arming purposes For example a Timing Analyzer may arm a State Analyzer and vice versa 2 14 The IMB ribbon cable W3 on the 64601A parts list is connected the 64601A control board Although 64602A acquisition boards have an inter module bus jack there is no electrical connection between this IMB jack and the rest of the board The 64602A communicates with the IMB through the 64601A control board Since there is no electrical connection to the 64602A IMB jack and the rest of the board this jack may have a ribbon cable connected to it for mechanical support 2 15 Probe Bus 2 16 The timing analyzer communicates with the system under test by means of the 64604A Timing Probe The probe cable W2 on the 64602A parts list connects to the probe bus located on the top center of of the 64602A acquisition board 2 17 Clock Ca
61. BENE xe EN EE Pop iy ip fp ip ip EN TE m JR ur voir Poe rr EN 5 m Tn ON Vd TE T pu H H EN 8 E n i rir EN EE m pap WE WO E Fir e PAGE tao PET INDE Figure 4 5 This is the third pattern for signature analysis Characters Exercised Data Characters High following every glitch character High low transition alternating every eight dots Enhancement Characters Cursor alternating on for four dots off for 12 dots Graticule alternating continuous for 32 dots then off for 32 dots Dual Threshold following every high low transition Glitch following every dual threshold character Blanking lasts for four dots on the part of the display where there is no cursor CTL 4 25 Performance Tests and Troubleshooting Model 64601A Press NEXT FAGE to CONTINUE Figure 4 6 This display is repeated eight times and shifted by one dot Characters Exercised Data Characters Low continuous on all channels Enhancement Characters Graticule every fourth dot Cursor continuous except for graticule columns CTL 4 26 Performance Tests and Troubleshooting Model 64601A e e Eeee p EEE TT Figure 4 7 This is a pattern of highs lasting four dots high low transitions lows last ing
62. DEY DEY DEY DEY DEY DCV DCV DEVY 90 6 PSAF 90 14 593 Uu 90 15 high U 91 1 05983 0 91 2 CUSSU U 9 1 3 0500 91 4 59365 TOTLZ 0207 U 91 0000 TOTLZ 0002 U 91 6 high 91 2 5934 TOTLZ 0001 U 91 12 5934 U 91 13 5935 91 18 5934 Performance Tests and Troubleshooting Model 64601A ECL 27 14 207H 38 24 FCSF 0 22 18 0000 U 42 1 high U 10 high U 34 1 high 42 2 3936 d 10 HC17 34 2 7P7F 42 4 59348 U 10 C223 U 34 6 091 U 42 5 Acer 10 H911 34 13 16PA U 42 amp PAAR U 10 3H61 34 14 AUHP 49 7 P762 U 10 HC17 U 36 1 0000 49 11 low U 10 Caes U 38 35 ASAF 0 49 18 FEC U 1 0000 U 36 6 high U 54 1 high U 10 10 H911 U 38 2 low 54 PSHH U 10 11 687 0 36 9 2 U 54 3 4 H j Cm CH bb ji FG gt LU 10 12 16P4 U 36 12 0000 S4 AUER U 10 15 F687 U 36 13 FCSF 54 APUP 10 14 lepa U 36 14 0000 U 54e 6 2570 10 13 56 15 high U 24 7 POPs Lu 11 high U 36 17 0000 U 54 9 PESE u tie U 35 18 low 54 10 1242 11 3 FAGY U 36 19 high U P71U u 11 AGAC U 36 20 high 54 12 11 009 U 36 24 FUCSF U 24 13 low U 11 6 2642 U 37 0000 54 14 PSHH 2 FAS U 37 1H36 U 54 18 CIP uU 11 9 0000 37 HPU amp U 55 21 high U 11 10 4040 uU 37 high U S5 2 FEC U 11 11 He0e u 37 low SS 4 009A U 11 12 3662 37 U 55e 3 334 U 31 13 H202 i 37 10 0000 d gge
63. Disconnect all channels from any signal source that is leave the probes disconnected 5 18 8 1 Keyboard Setup Use the following procedure to adjust R1 R3 a Press softkey option test RETURN b The screen should list all the option boards installed in your system in the slot number for the 64601A control board RETURN c Press softkey run d Press softkey slot e The screen should list the timing analyzer boards in the system Type in the slot number for the 64601A control board f Press softkey test The screen should list all the Control Board tests g in 6 h Type in cal RETURN CTL 5 5 Adjustments Model 64601A 5 19 8 Channel Adjustment R1 through Test 6 consists of nine test steps five in braces four in brackets 500000 0000 are concerned only with the four in brackets 11 four should be 0 If they are not procede as follows 1 Adjust R1 until the second digit from the right is O 2 Adjust R2 until the third digit from the right is O 3 Adjust R3 until the fourth digit from the right is 0 4 The first bracket digit indicates whether the others are correct It Should now be 0 also 5 Press the stop softkey 6 Press the end softkey 5 20 16 Channel Keyboard Setup Rh through Use the following procedure to adjust Rh R system containing a second 64602A acquisition board a Press softkey
64. Fe WEG s g 8 SS ue g B g Ill SEG 22 g SS E SS W SS W s we FE B EE p SS N SS g TEU g SS mH a a 1 el D m EB D a r Figure 4 3 This is an alternating pattern of high low transitions low high transitions glitches graticule and cursor This is the first pattern for signature analysis Characters Exercised Data Characters High low low high transition characters Two every eight dots Enhancement Characters Intensity alternating every 12 dots Graticule on for 32 dots then blanked for 32 dots Cursor alternating on for four dots off for 12 dots Blanking on for four dots off for four dots during the time the graticule is of Glitches Two every eight dots CTL 4 23 Performance Tests and Troubleshooting Model 64601A Vee Se SR Se Se ES f 98 1821 ik E fs SS SS P TP TP FS Y VE SS TP VE TP T2198 1921 22 188188 ae te P 4 Pl NI rm 4 Dal UC m This is the same as the previous pattern but for 16 channels This is the second pattern for signature analysis 4 24 Performance Tests and Troubleshooting Model 64601A OM
65. H TRIG DLY L VID L VSYN HE WNDWCLK H 12 5MHz L 12 5MHz 25MHz CLK Theory and Schematics Model 6h601A DEFINITION Trigger drives trigger enable The received HE TR from the IMB is used to drive the IMB LE TE line Enables trigger for performance verification Trigger signal qualified by the A term generator Trigger signal qualified by the B term generator Trigger plus delay Tracepoint the position of the trigger in in memory plus any delay added by the timing analyzer s delay counter or by another analyzer via the IMB Video from display driver to motherboard Vertical synchronizing signal for display from the mainframe Window clock counters Clock to window U36 and trigger enable U38 Derived from the 25MHz mainframe system clock Used as the timing display character clock since each timing character is two dots wide Mainframe system clock frequency Used by the timing display as the dot CTL 8 21 Theory and Schematics Model 64601A 3 T 1 Yr YI 27 ES NOTES ETCHED CIRCUIT BOARD FRONT PANEL MARKING REAR PANEL MARKING MANUAL CONTROL SCREWDRIVER ADJUSTMENT ELECTRICAL TEST POINT TP WITH NUMBER NUMBERED WAVEFORM NUMBER CORRESPONDS TO ELECTRICAL TEST POINT NO LETTERED TEST POINT NO MEASUREMENT AID PROVIDED H Hl H H WIRE COLORS ARE GIVEN BY NUMBERS IN PARENTHESES USING THE RESISTOR COLOR CODE 925 ISWHT RED GRN 0 BLACK 5 GREEN
66. Intensity alternations cannot be shown in the manual but will be described Although the purpose of the patterns is primarily to generate signatures defects in the displays may help to isolate problems For example address line shorts may put one character adjacent to another An open line might take away a character that should be there Or perhaps one character will be substituted for another eg glitch for cursor Look primarily for irregularities and discontinuities Examples of possible problems Irregularities Misshapen characters Glitch instead of normal data or vice versa Adjacent line shorts may show up as adjacent graticules cursors etc Blanks instead of characters Highs instead of lows or vice versa Transition characters subsituted for other data characters or vice versa CTL 4 21 Performance Tests and Troubleshooting Model 64601A Presse NEXT PAGE to CONTINUE Figure 4 2 This display checks the proper centering of the pattern The bar at the bottom and the brackets are generated by the mainframe The timing analyzer display driver puts out the dot pattern which should be centered within the brackets as shown Problems might be in the Start Address Latches U92 93 or the Row Char or Line Counters U78 94 96 CTL 4 22 Performance Tests and Troubleshooting Model 64601A F EF c wu SS 8 m SS m SS 2 Er EI SEE
67. Location of GQLUaL STOP tp 12 Location of CLOCK tp 11 Location of GROUND gnd TTL U S6 1 high U U 56 2 high U S6 3 0092 9 56 4 4204 U 58 5 6226 0 55 4 S731 u U 56 9 Gear u CTOTLZZz 0048 u 56 10 low 0 U 55 11 23HP U 55 12 FRAC U 56 13 C443 56 14 100 U 56 15 4319 U 4166 U 57 SAP U U 57 57 57 Lu E D ae F19H Uu 2c32 u 57 3902 U U 57 923F U TOTLZ 32768 U 57 10 2656 57 11 9 u 57 12 amp 545 U U 57 13 1A8H u 52 14 HCHC u U 57 15 682U U 57 16 U 57 17 94AF u U 58 416C U U sg U 58 58 58 U 58 U 58 ONO Ub BG Pj BW he 9upc U 2C32 u C NO 2usc u neg edge pos edge edge S8 8 58 10 58 11 58 12 58 13 58 14 58 15 58 16 58 17 59 21 59 02 59 03 59 4 59 5 59 6 59 7 59 B 39 10 9 5 1 1 39 12 39 13 39 14 59 18 39 16 39 17 aos 1 bp 2 p 3 ban 4 62 F19H TOTLZ 62 6 b 7 2490 923F CTOTL Z7 327658 995 S351 654 LA8H HCHC 824 JAAF 4160 09 ausc 19 FUP C ange 2186 923F oUPC T TLZ 32768 4F AH C883 AGAS 1 HCHC 682u OP SC JAA lou Sour Jc low 923r 09AP CT TLZs65552 993F 9990 4319 923F dudo U 52 9 PSUF U 62 10 high U 2 11 PSUF 62 12 4319 U 62 14 431 U 62 15 low 65 1 4319 U 6
68. M SAUDI ARABIA Modern Electronic Establishment Hewlett Packard Division 0 Box 281 Thuobah AL KHOBAR Tel 864 46 78 Telex 671 106 HPMEEK SJ Cable ELECTA AL KHOBAR CH CS E M P Modern Electronic Establishment Hewlett Packard Division 0 Box 1228 Redec Plaza 6th Floor JEDDAH Tel 644 38 48 Telex 4027 12 FARNAS SJ Cable ELECTA JEDDAH CH CS E M P Modern Electronic Establishment Hewlett Packard Division 2728 RIYADH Tel 491 97 15 491 63 87 Telex 202049 MEERYD SJ CH CS E M P SCOTLAND See United Kingdom SINGAPORE Hewlett Packard Singapore Sales Pte Ltd Box 58 Alexandra Post Office SINGAPORE 9115 6th Floor Inchcape House 450 452 Alexandra Road SINGAPORE 0511 Tel 631788 Telex HPSGSO RS 34209 Cable HEWPACK Singapore A CH CS E MS P Dynamar International Ltd Unit 05 11 Block 6 Kolam Ayer Industrial Estate SINGAPORE 1334 Tel 747 6 188 Telex RS 26283 CM SOUTH AFRICA Hewlett Packard So Africa Ltd 0 Box 120 Howard Place CAPE PROVINCE 7450 Pine Park Center Forest Drive Pinelands CAPE PROVINCE 7405 Tel 53 7954 Telex 57 20006 A CH CM E MS P Hewlett Packard So Africa Pty Ltd Box 37099 92 Overport Drive DURBAN 4067 Tel 28 4178 28 4179 28 4110 Telex 6 22954 CH CM SALES amp SUPPORT OFFICES Arranged alphabetically by country Hewlett Packard So Africa Pty Ltd 6 Linton Arcade 511 Cape Road L
69. NC NC IMB DRIVE TRACEPOINT SELECTION INTERNAL GENERATION LE ENIMBTR 9 10 LE TR N 11 12 NC 13 EXTERNAL IMB Ref 036 039 048 050 051 052 066 Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC Des 37 1NB4 5008 1820 1993 1820 0780 1820 1946 1820 0817 1820 1788 1820 1944 HP Part No Mfr Part No MC10158L DS8831N 1011 MC10131P F10016DC MC10130L HE TEDRIVE 1 6 TRACEPOINT LATCH WINDOW COUNTER LE TRORIVE 78 6 TRIGGER POSITION P O U36 HE TRACEPOINT LATCHED x START CTA OUT 9 TERT VHE ONE SHOT NC O O NC EN HE HRCLK 14 NORMAL ONE SHOT HE STOP G 3 HE WNDNCLK 8 CNTA CLK SEE NOTE HE RESET 24 dva AST2 HROUT ONE SHOT OUT SEE NOTE A ON SERVICE SHEET 2 TRIGGER POSITION INDICATOR WITHIN 8 BIT SAMPLE HE TCO 1 26 is duplicated both service sheet 2 and 7 PARTS ON THIS SCHEMATICS J6 053 65 RESISTOR PACKS POWER SUPPLY CONFIGURATION 16 5 4 8 048 8 5 2 5 2 u39 2 16 116 050 52 66 UNCONNECTED PINS U53 PIN 4 RESISTOR PAKS U53 65 U65 5 7 10 1 alm o THE 25 BIT HOLDING REGISTER SECTIONS OF U36 037 ARE SHOWN ON SHEET 2 Figure 8 15 Service Sheet 7 Tracepoint Selection CTL 8 3
70. O Box 795 5th Floor Sun Hung Kai Centre 30 Harbour Road HONG KONG Tel 5 8323211 Telex 66678 HEWPA HX Cable HEWPACK HONG KONG E CH CS P CET Ltd 1402 Tung Way Mansion 199 203 Hennessy Rd Wanchia HONG KONG Tel 5 729376 Telex 85148 CET HX CM Schmidt amp Co Hong Kong Ltd Wing On Centre 28th Floor Connaught Road C HONG KONG Tel 5 455644 Telex 74766 SCHMX HX ICELAND Elding Trading Company Inc Hafnarnvoli Tryggvagotu 0 Box 895 IS REYKJAVIK Tel 1 58 20 1 63 03 M INDIA Computer products are sold through Blue Star Ltd All computer repairs and maintenance service is done through Computer Maintenance Corp Blue Star Ltd Sabri Complex Il Floor 24 Residency Rd BANGALORE 560 025 Tel 55660 Telex 0845 430 Cable BLUESTAR A CH CM CS E Blue Star Ltd Band Box House Prabhadevi BOMBAY 400 025 Tel 422 3101 Telex 011 3751 Cable BLUESTAR Blue Star Ltd Sahas 414 2 Vir Savarkar Marg Prabhadevi BOMBAY 400 025 Tel 422 6155 Telex 011 4093 Cable FROSTBLUE A CH CM CS E M Blue Star Ltd Kalyan 19 Vishwas Colony Alkapuri BORODA 390 005 Tel 65235 Cable BLUE STAR A Blue Star Ltd 7 Hare Street CALCUTTA 700 001 Tel 12 01 31 Telex 021 7655 Cable BLUESTAR AM Blue Star Ltd 133 Kodambakkam High Road MADRAS 600 034 Tel 82057 Telex 04 1 379 Cable BLUESTAR AM Blue Star Ltd Bhandari House 7th 8th Floors 91 Nehru P
71. OF 59 1064 OF 1601 3298 000 3716 F036 h 71 Performance Tests and Troubleshooting Model 64601A 646016 Timing Control LESS THAN INTERVAL NORM MODE DATA THRESHOLD HIGH CLOCK THRESHOLD ttl ST SP QL THRESHOLD Location of ST SP START Location of QLUAGL STOP Location of CLOCK Location of GROUND TTL U 28 1 high U 28 2 low 28 3 AFAR U 28 4 C197 0 28 8 low 28 6 low 28 7 HAHA U 28 8 7020 U 28 9 low U 28 11 9386 U 28 12 high 28 18 Geer 28 19 Low 31 1 4 53 DCW 31 2 5 12 DENY 31 3 85 1 DEV 31 7 4 8 12 DOV 31 5 4 37 DOV 31 6 4 94 PCY 7 STP DCV SI 8 3 17 DEV 31 9 0 93 DEV 31 10 0 16 DEY 31 11 0 01 DEVY 31 12 5 17 DOY 31 13 0 64 DEV 0 01 DCU 31 18 4 37 31 16 4 52 DCV 1 4 98 DCU 2 0 17 DEVY 32 03 0 01 DOV 4 0 17 DEV CTL 4 72 Board 12 11 ttl amp 12 32 5 32 6 32 7 32 8 32 9 32 10 32 11 32 12 32 13 32 14 49 4 49 5 49 12 49 13 85 1 85 2 85 3 89 4 35 5 85 6 85 7 85 9 85 12 85 14 85 15 85 16 85 17 85 18 85 19 86 5 86 7 86 10 86 11 9 1 90 2 90 3 90 4 90 5 YH S936 edge pos edge pos edge 0 01 0 03 U F2 low uo SA UZEZ P762 AJAG 9226 Ho 7020 H780 P SAF C197 low AJAB 3936 AACS OA 9266 PSAF 74F9 Q6HC 29 2H low 9266 DEY DEY
72. Ref Des HP Part No Mfr Part No 061 64 1820 0629 5 745112 062 1820 1077 5 745157 063 84 1820 0693 5 74574 078 96 1820 1430 5 741 5161 082 1820 1197 5 741 500 092 93 1820 1196 5 741 5174 094 95 1820 1475 93516 099 1820 0686 SN74S11N 0101 1820 0683 SN74S04N PARTS ON THIS SCHEMATIC R38 IC POWER SUPPLY CONFIGURATION 14 5 U61 62 78 92 96 U63 82 84 99 101 R34 HT 1K TO U61 63 78 84 94 95 Figure 8 16 Service Sheet 8 Display Addressing CTL 8 39 C23 C58 9 834 2 0101 IMB TIMING 8 89 99 64601 66501 em r2 ps U18A 1 TF HE 5 al ww 2 I 2 a Yi g Sy elitr hir o 18 5 2 T 7 TFF n i Q1 z n o ot TITO es 35 22 5 US 8 5 T TP2 d 1 G 9 N e 29 T 99 5 ell 15 T uaj 1 023 S eR 427 031 S 11 ME S i S E ho er 8 2 a amp O v l SN t 9 o 9 BC T TT R21 i R22 8 s 7 thos 5 5 8 9 8 9 PREO 8 5 s eet 88 Os 99 u T 5 T e o 9 5 2B 7 l U47A 8 9 0 0 6
73. S A Los Flamencos 145 San Isidro Casilla 1030 LIMA 1 Tel 41 4325 41 3703 Telex Pub Booth 25306 CMEMP PHILIPPINES The Online Advanced Systems Corporation Rico House Amorsolo Cor Herrera Street Legaspi Village Makati 0 Box 1510 Metro MANILA Tel 85 35 81 85 34 91 85 32 21 Telex 3274 ONLINE A CH CS E M Electronic Specialists and Proponents Inc 690 B Epifanio de los Santos Avenue Cubao QUEZON CITY 0 Box 2649 Manila Tel 98 96 81 98 96 82 98 96 83 Telex 40018 42000 ITT GLOBE MACKAY BOOTH PORTUGAL Mundinter Intercambio Mundial de Com rcio SARL 0 Box 2761 Avenida Antonio Augusto de Aguiar 138 P LISBON Tel 19 53 21 31 53 21 37 Telex 16691 munter p M Soquimica Av da Liberdade 220 2 1298 LISBOA Codex Tel 56 21 81 2 3 Telex 13316 SABASA Telectra Empresa T cnica de Equipmentos El ctricos S A R L Rua Rodrigo da Fonseca 103 0 Box 2531 P LISBON 1 Tel 19 68 60 72 Telex 12598 CH CS E P PUERTO RICO Hewlett Packard Puerto Rico 0 Box 4407 CAROLINA Puerto Rico 00628 Calle 272 Edificio 203 Urb Country Club RIO PIEDRAS Puerto Rico Tel 809 762 7255 A CH CS QATAR Computearbia 0 Box 2750 DOHA Tel 883555 Telex 4806 CHPARB Eastern Technical Services 4747 DOHA Tel 329 993 Telex 4156 EASTEC DH Nasser Trading amp Contracting 1563 DOHA Tel 22170 23539 Telex 4439 NASSER DH
74. SRO MS Medical Products Secondary SRO P Personal Computation Products Sales only for specific product line Support only for specific product line IMPORTANT These symbols designate general product line capability They do not insure sales or support availability for all products within a line at all locations Contact your local sales office for information regarding locations where HP support is available for specific products HP distributors are printed in italics ANGOLA Telectra Empresa T cnica de Equipamentos R Barbosa Rodrigues 41 1 DT Caixa Postal 6487 LUANDA Tel 35515 35516 EMP ARGENTINA Hewlett Packard Argentina S A Avenida Santa Fe 2035 Martinez 1640 BUENOS AIRES Tel 798 5735 792 1293 Telex 17595 BIONAR Cable HEWPACKARG A E CH CS P Biotron S A C LM e l Av Paseo Colon 221 Piso 9 1399 BUENOS AIRES Tel 30 4846 30 1851 Telex 17595 BIONAR M AUSTRALIA Adelaide South Australia Office Hewlett Packard Australia Ltd 153 Greenhill Road PARKSIDE S A 5063 Tel 272 5911 Telex 82536 Cable HEWPARD Adelaide A CH CM E MS P Brisbane Queensland Office Hewlett Packard Australia Ltd 10 Payne Road THE GAP Queensland 4061 Tel 30 4133 Telex 42133 Cable HEWPARD Brisbane A CH CM E M P Canberra Australia Capital Territory Office Hewlett Packard Australia Ltd 121 Wollongong Street FYSHWICK A C T 2609 Tel 80 4244 Telex 62650 Cable HEWPARD Canberra CH CM E
75. Tel 877 199 Cable HEWPACK Wellington CH CM E P 0 Northrop Instruments amp Systems Ltd 369 Khyber Pass Road 0 Box 8602 AUCKLAND Tel 794 091 Telex 60605 AM Northrop Instruments amp Systems Ltd 110 Mandeville St 0 Box 8388 CHRISTCHURCH Tel 486 928 Telex 4203 AM Northrop Instruments amp Systems Ltd Sturdee House 85 87 Ghuznee Street 0 Box 2406 WELLINGTON Tel 850 091 Telex NZ 3380 AM NORTHERN IRELAND See United Kingdom NORWAY Hewlett Packard Norge A S Folke Bernadottes vei 50 Box 3558 N 5033 FYLLINGSDALEN Bergen Tel 05 16 55 40 Telex 16621 hpnas n CH CS E MS Hewlett Packard Norge A S Osterndalen 18 Box 34 N 1345 OSTERAS Tel 02 17 11 80 Telex 16621 hpnas n A CH CM CS E M P OMAN Khimjil Ramdas 0 Box 19 MUSCAT Tel 722225 745601 Telex 3289 BROKER MB MUSCAT Suhail 8 Saud Bahwan 169 MUSCAT Tel 734 201 3 Telex 3274 BAHWAN MB PAKISTAN Mushko amp Company Ltd 1 B Street 43 Sector F 8 1 ISLAMABAD Tel 26875 Cable FEMUS Rawalpindi Mushko amp Company Lid Oosman Chambers Abdullah Haroon Road KARACHI 0302 Tel 524131 524132 Telex 2894 MUSKO PK Cable COOPERATOR Karachi Electr nico Balboa S A Calle Samuel Lewis Ed Alfa Apartado 4929 PANAMA 5 Tel 64 2700 Telex 3483 ELECTRON PG ACMEMP PERU C a Electro M dica
76. Total skew from probe tip Within pod 1 5ns Pod to pod 3 0ns Conditions Input signal VH 1 0 VL 1 6V VTH at 1 3V Input slew rate 25 V ns Sample rate accuracy typically 002 Probe characteristics Input 2 100K ohms 2 shunted by lt 6pf Drive requirements Minimum input amplitude 600mV P P Minimum input overdrive 200mV or 25 of input amplitude whichever is greater Minimum input pulse width 3 0ns at threshold Dynamic range 10V Maximum input Threshold accuracy 50mV or 2 whichever is greater Hysteresis Typically 50mV Glitch Mode Maximum sample rate 100MHz Minimum width 3 0ns at threshold Maximum width sample period less 4 Ons CTL 1 3 General Information Model 64601A Specifications continued Triggering Time duration accuracy 20 2ns Minimum width for narrower than trigger 6ns typical Minimum width for transition trigger 6ns typical Displayed position accuracy 4 samples in Wide Sample Dual Threshold and Glitch Modes 8 samples in Fast Sample Mode Delay from input to external BNC drive Typically 60ns Delay from input to internal IMB drive Typically 55ns Dead time for post qualify measurement reset Typically 50ns the time required to fill the memory with the selected amount of pre trigger information Reset time for duration trigger To meet the duration specifications the trigger duty cycle must be no greater
77. Troubleshooting Model 64601A high 9 Dga high 0030 8032 OF E high P1U low low U 37 180 low 32 19 high 0 J 37 20 high U U 37 24 8032 Li Se U 38 1 0000 38 0 U 38 4 1720 0 38 6 high U U 38 7 low LJ U 38 8 66656 u 55 U Bae 9 high uU i 38 10 F708 0 U 38 12 PS61 u U 38 13 8032 u U 38 14 PSA Lu low uU 38 15 high U 55 11 UH94 U 38 1 000 55 12 6696 38 18 low 55 13 U 38 19 high U 55 14 7063 38 20 high U 64 3 0000 38 24 80202 U 64 7 FPP 40 1 high U 64 11 5841 U 40 3 PPFP U 654 15 CUBI 40 5 U 66 1 high 40 2 PPFP U bb 2 7331 U 4 9 yapa U 65 2614 U 40 10 6666 U 64 4 8032 6 40 140 PFEP U 56 0000 U 40 12 86032 U 66 H517 U 40 14 66466 U 66 10 E708 49 3 ZH26 U 66 11 8032 49 7 7331 U 65 13 HEL U 49 11 CUBI 49 15 3844 U SO 1 high 50 2 7331 uU S 4 7331 U SO 2 low U SU 1P2 i 0 10 dow U 50 11 U g el high LU uS0 14 7331 u S1 high uU Sa 00350 u Si 31 qe 7331 0851 09 low 51 10 FaF U 81 11 9331 U 51 12 8032 U 51 14 CUSI 51 15 high PCR P gt Fd CTL 4 56 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Board WINDOW COUNTER 5 NORM MODE DATA THRESHOLD HIGH ttl amp ecl CLOCK THRESHOLD ttl ST SP QL THRESHOLD ttl Location of ST SP START tp 12 L
78. U 79 14 U 79 15 U 80 1 U 80 2 U 80 3 U 80 4 U 80 5 U 80 6 U 80 7 U 80 9 U 80 10 U 80 11 U 80 12 U 80 13 U 80 14 U 80 15 U 81 1 U 81 2 U 81 3 U 81 4 U 8i 5 U 81 6 81 7 U 81 9 TOTLZ U 81 10 81 11 U 81 12 U 81 13 CTOTL ZZ U 81 14 81 15 U 82 1 U 82 2 82 3 U 82 4 U 82 5 U 82 6 U AUS 352 low high 9860 AHAL AU 3 CUA 9023 980022 9286 7923 PH2e low low low SS OH Coc H ZF P3816 28 7923 9286 CHEF 8556 1216 424 low low high high HUAT HUAL 6UHO CAHS SHS A 0000 12519 APCS SHOA 14AP 3836 0001 agar C383 low low high low low high high Performance Tests and Troubleshooting Model 64601A U 82 9 Low U 82 10 high U 82 11 low U 82 12 high U 82 13 high 83 1 amp 37P U 83 2 U 83 2 383A 7 12518 0 83 4 0000 CTOTLZ 12519 83 5 F637 83 68 0942 0 83 8 883F 0 83 9 8556 0 83 10 14 0 85 11 0000 83 12 0000 U 83 13 14 U 84 1 high U 84 2 0000 U 84 2 3834 CTOTLZ 0024 U 84 4 high U 84 0000 U 84 6 383A U 84 8 low U 84 9 high U 84 10 high U 84 11 0000 U 84 12 high U 84 15 high U 88g 1 low U 88 2 high 0 88 4 low 6 383A 88 8 C383 88 9 0942 U 88 10 7457 U 88 11 low U 88 12 U352 U 88 13 FC amp 8 U 89 11 low U 89 2 low U 89 4 low 89 5 low 89 8 low 89 11 low 90 4 low U 90 high U 90 6 high U 7 low U 90 9 low U 90 1
79. UPSD U 1 4 P2CA U 85 U 85 0 89 4 1 6 high 6418 Z07281 01 2 low UP So 89 low U 8 low low U 89 SCIES i 9 low 117F U 91 2471 Li 18 low low U 91 2471 U l AGP UP SU 91 u 13 high low 91 4 0000 u C14 AGP 2252 U 15 high low U 91 5 8000 0 1 0000 UP S 0781 CTOTLZz0920 low 91 6 high U 1 18 lou WP So 0 91 2 46FC U 31 19 high 85 15 high U 91 9 high U 1 20 high U 85 16 UPAO U 91 10 high 1 24 high i 88 17 low 0 91 11 high 4 7 1776 U 85 18 3C12 91 12 U 4 9 88 19 91 13 high U 4 14 A9P7 U B 73F6 U 91 14 high U 58 4 A418 U 86 6 high 91 15 2471 U 10 high 86 7 2471 1101 8 73F6 U 10 2 6196 uU 86 10 low U10i v UPSO U 10 3 1776 U 86 11 high 10 4 SAIU 88 1 low U 10 16CC amp 7 e i St vM iu iege deb 88 2 high Lu 10 U 88 3 0000 U i 1776 CTOTLZz07812 uU 10 AYP 83 4 8495 U 10 10 Sau CTOTLZ 07B 12 U 10 11 40PF U ag 3 08000 10 12 P2984 CTOTL 12207 10 13 40PF Uu 88 6 1000 LU 10 14 P284 CTOTL ZZ 07812 U 10 15 9874 U tle 1 high 4 47 Performance Tests and Troubleshooting Model 64601A ih 11 2 11 3 u 11 4 uU 11 3 uU 11 11 7 U 11 9 U 11 10 U 11 11 u DUI U 11 13 U 11 14 U 11 15 u 13 4 u 13 7 uU 13 11 13 13 U 15 1 15 2 U 15 3 15 4
80. a software program the actions of a hardware state machine or random logic signals 1 11 The Timing Analyzer consists of Model 64601A Timing Control Board and from one to two Timing Data Acquisition Boards 1 12 Up to two Acquisition Boards may be combined to form a Timing Analyzer with as many as 16 channels 1 13 Logic Analyzers within one Mainframe may be connected together using the Inter Module Bus IMB One possible use of the IMB is to allow a State Analyzer to trigger a Timing Analyzer 1 1 SPECIFICATIONS 1 15 Instrument specifications are listed in Table 1 1 These specifications are the performance standards or limits against which the instrument is tested CTL 1 2 General Information Model 64601A Table 1 1 Specifications Includes Models 64601A Control Board 64602A 8 Channel Acquisition and 64604A 8 Channel Timing Probes Sample rates Wide Sample Mode variable from 2Hz to 200MHz Glitch mode variable from 2Hz to 100MHz Dual Threshold same as Wide Sample Mode Fast Sample 4OOMHz Memory length Wide Sample Glitch amp Dual Threshold Modes 1060 samples hooMHz 8110 samples Memory width 8 channel system Wide 1 8 channels Dual Threshold Glitch and 400MHz modes 4 channels Memory width 16 channel system two acquisition boards Double the width for a single 8 channel system Resolution
81. before delay is inserted External trigger may also be asserted at this point Pattern trigger output to the BNCh jack on the mainframe Pattern duration greater than specifies Enables triggering on patterns with durations greater than specified by the A term generator High for less than durations Pattern duration greater than B specifies Enables detection of patterns with durations greater than specified by the B term generator False or high for less than widths Derived from phi2 sample clock Used to clock the delay counter 1 HE DLCLK delay from the IMB is not selected Derived from phi2 sample clock Clocks the position counter which determines exact trigger position an eight bit sample group Also used to derive H WNDWCLK for the window and trigger enable counters Sample clock from sample rate generator to the acquisition boards Selects programming mode for timing display This mode is used for loading the display RAMs When high the display or normal mode is selected Performance verification sample clock from the mainframe Stops the sample clock during performance verification CTL 8 19 Theory and Schematics Model 64601A MNEMONIC XE PVTRIG L POP HE PROCRESET H RCNTRO 3 RESET HE RESTARTEN LE RUN H SCLKOUT BNC3 L STARTADR HE STOP H TCO H TC1 H TC2 LE TEARM LE TEDRIVE HE TR HE TRDRIVE CTL 8 20 DEFINITION Used instead of
82. control circuits the address latches and the RAMs CTL 4 16 Performance Tests and Troubleshooting Model 64601A 4 60 TEST 10 RATES INTERVAL A 16 CH ONLY 00000 0000 test steps 12345 6789 This is the same as TEST 6 above for the B term generator 4 61 TEST 11 LESS THAN INTERVAL A 16 Ch Only 0000 test steps 1234 This is the same as TEST 7 above for the B term generator 4 62 TEST 12 TRANSITION TRIGGER A 16 Ch Only 000 test steps 123 This is the same as TEST 8 for the B term generator CTL 4 17 Performance Tests and Troubleshooting Model 6h601A 5 63 TEST 13 AND 16 Ch Only 0000 test steps 1234 4 64 Purpose This test checks the AND OR combination circuits U13 U17 U34 U35 HE AND is set high 4 65 Theory In a 16 channel two acquisition board system each acquisition board provides a trigger signal to the control board via the timing bus These two triggers XE TRIG1 and XE TRIG2 from pods 1 and 2 are ANDed or ORed in the combination circuits When the two triggers are both high and HE AND is high they are ANDed When the one or both of the triggers are low and HE AND is low they are ORed and XE TRIG2 may be programmed as either high true or low true by XE TRIGPOL out of the glitch chip U27 on the acquisition board Hence the X designation 4 66 Test Steps Description of software execution 1 With HE AND high XE TRIG1 and XE
83. four dots and then low high transitions This display is shifted by one dot in each of the next eight displays not shown Characters Exercised Data Characters High Alternating every four dots Low Alternating every four dots High low transitions Low high transitions Enhancement Characters Graticule continuous Cursor continuous Intensify all CTL 4 27 Performance Tests and Troubleshooting Model 64601A Press CONTINUE Figure 4 8 This pattern is displayed eight times and shifted by one dot each time Characters Exercised Data Characters Low continuous on all channels Enhancement Characters Intensity alternating pattern imposed on the continuous lows shifted in each display Cursor on for four dots off for two on for two off for one then repeating CTL 4 28 Performance Tests and Troubleshooting Model 64601A Figure 4 9 This is a pattern of four highs and a glitch then four lows and a glitch The pattern is shifted by one dot in each of the following eight displays Characters Exercised Data Characters High lasting four dots followed by a glitch then four lows Low lasting four dots followed by a glitch then four highs Enhancement Characters Graticule continuous Cursor continuous Intensity all CTL 4 29 Performance Tests and Troubleshooting Model 64601A E INT ENLI C Era
84. high 17 2 614H 17 3 1 2 U 17 4 IFS U 17 5 low U 17 6 low U 17 7 SPH1 U 17 9 low U 17 10 low 17 11 U 17 12 2F99 U 17 13 8474 U 17 14 7551 U 17 15 low U 34 1 high U 34 2 34 3 8 30 49 11 49 15 S4 1 54 2 54 3 54 4 S4 5 54 6 54 7 54 9 55 11 55 12 55 13 PHIL AAHS AAHS 9 637 high 8H30 9 ACS 2607 4568 9 low ACA 61 4H 01P rcog AAHS FATA P6PC low e6F62 high 7HC AP 22 SCCF 862 46FH CIFU low CAFU H1 t high F62 1268 8670 low low Hi0 Low 5938 P6PC DHF 3 low AUSH SUS low high Performance Tests and Troubleshooting Model 6h601A u u u u Li u U n f E 1 7 1 71 71 71 7 1 ame 71 9 b pl 930F 197P 47 9 930F 197P 0000 TOTLZ 0130 u Uu u U LI u u J 0 0 U Uu U u 71 10 71 11 71 12 71 13 71 14 71 1 73 1 73 2 73 3 73 4 73 5 73 6 73 7 73 9 HF 47 49463 2441 49653 24H1 1268 high 04C2 4521 8H26 0402 521 0000 CTOTLZz0130 u u u U 73 10 73 11 73 12 73 1 2 73 14 73 15 2668 AP 22 AP Ze 8 9 4 81 Performance Tests and Troubleshooting Model 64601A 646016 Timing Control Board B F LLOWED BY d 18 NORM MODE DATA THRESHOLD HIGH trl CLOCK THRESHOLD ttl STOP Ql THRESHOLD
85. high high 14 42 12 43 4 43 7 49 3 49 7 49 11 49 15 50 9 54 6 34 11 uS 4 583 11 59 13 57 6 67 11 55 s 59 59 21 71 71 7i 21 71 71 71 71 10 21 11 71 12 71 13 7 1 Swi 1 4 71 18 O OO b DP TO MPO 73 735 2 Pod i WN OO Cn b bi fO SAF 1 SAF C8gu A413 low Low H SA 66HC U33H C7PF 29 0 9249 0051 F145 6036 AGP AQP high high 5036 1363 29 0 eHuu 636 AGP 1363 H93S F145 Hoes F145 9249 high 0178 802P HOC 73F6 0128 802P 9 H9C9 CX3H C7PF C33H C7PF 0178 8059 high high 73F6 ASP Performance Tests and Troubleshooting Model 64601 646015 Timing Control Board RUN HALT RESET NORM MODE 2 DATA THRESHOLD HIGH tti amp CLOCK THRESHOLD vti ST 8P QL location Location Location Location THRESHOLD ttl of ST SP START of GUAL STOP tp 12 of GROUND 0 88 32 CTOTLZ0002 U 85 2 10 uU 85 35 uU 35 4 low U B 1UF U 85 6 low U 35 7 Glue U 85 8 low i 9 010 Uu 85 12 U 83 14 O1UF U 835 19 01 9F U 35 16 U 85 17 low 35 18 QF 85 19 QIE 12 U 86 0000 U 86 7 high U 86 10 U 86 11 019 U 0 1 0154 U 30 2 0102 U 90 3 0153 90 4 lou U e U 90 amp LU 90 7 low U 90 9 low U 90 10 low U 90 11 low 90 12 high U 90 13
86. however is assigned sequentially and is different for each instrument The contents of this manual apply to instruments with the repair number prefix es listed under REPAIR NUMBERS on the title page 1 6 An instrument manufactured after the printing of this manual may have a repair number prefix that is not listed on the title page This unlisted repair number prefix indicates that the instrument is different from those described in this manual The manual for this newer instrument is accompanied by a Manual Changes supplement This supplement contains change information that explains how to adapt the manual for the newer instrument 1 7 In addition to change information the supplement contains information for correcting errors in the manual To keep this manual as current possible Hewlett Packard recommends that you periodically request the latest Manual Changes supplement The supplement for this manual is identified with the manual print date and part number both of which appear on the manual title page Complimentary copies of the supplement available from Hewlett Packard 1 8 For information concerning repair number prefix that is not listed on the title page or in the Manual Changes supplement contact your nearest Hewlett Packard Office CTL 1 1 General Information Model 64601A 2 9 DESCRIPTION 1 10 The Timing Analyzer is used to monitor information flow in the time domain The information may be
87. indicate the quantity required and address the order to the nearest Hewlett Packard office 6 9 To order a part that is not listed in the replaceable parts table include the instrument model number instrument repair number the description and function of the part and the number of parts required Address the order the nearest Hewlett Packard office 6 10 SPARE PARTS KIT 6 11 A service kit is available To order please contact your local sales and service representative 6 12 DIRECT MAIL ORDER SYSTEM 6 13 Within the USA Hewlett Packard can supply parts through a direct mail order system Advantages of using the system are as follows a Direct ordering and shipment from the HP Parts Center in Mountain View California b No Maximum or minimum on any mail order there is a minimum order a mount for parts ordered through a local HP office when the orders require billing and invoicing c Prepaid transportation A small handling charge for each order d No invoices to provide these advantages a check or money order must accompany each order 6 14 Mail order forms and specific ordering information are available through your local HP office Addresses and phone numbers are located at the back of this manual CTL 6 2 Replaceable Parts Model 64601A Table 6 1 Reference Designators and Abbreviations REFERENCE DESIGNATORS assembly motor battery capacitor coupler diode de
88. low U 11 14 3649 U 37 12 0000 u low 11 15 Crise U 352 158 ECHE ues CAP U 13 1 high 37 14 0000 LI Low be 2 20599 U 37 153 high LU S3 HP U amp 3 6143 37 17 0000 U 55 12 3 4 AJAG U 37 18 Low U 39 135 CP654 3 5 low U 37 19 high U 55 15 lou 6 low U 37 20 high 67 high 7 H202 37 24 U amp 7 low x Low U 38 1 0000 67 low low 0 38 3 U 67 FCSF 369 38 4 1H36 U 657 35603 0000 U 38 68 high U 67 GP Ys 7 9 iPod od LD Of AY ik OME CH pi PO CSC uU 28 Low amp 7 FCSF high uU 38 high U 67 10 P762 lou U 38 10 2482 U 82 11 8628 high 38 12 0000 U 67 12 FCSF high ij 38 13 U 67 13 low 2642 U 38 14 0000 U 67 14 HU12 low U 38 15 high U 67 15 5924 FAG u 38 17 0000 U 71 1 high high 38 18 law U 71 2 8628 J Low U 38 19 high 71 3 26602 U 27 11 7947 U 38 20 high U 71 4 PPUP U 27 12 7947 27 13 207 iPod H G PO DOG MP GI DUC H i i Cu gt i PO Pa MM 1 1 G 4 73 Performance Tests and Troubleshooting Model 64601A U 71 5 P71U U 71 8628 U 71 7 3603 U 71 9 0000 U 71 10 PPUP U 71 11 28H7 71 12 CP64 U 71 13 28H7 71 14 CP64 71 15 0094 U 73 1 high U 73 2 8830 73 3 PPA 73 4 82AF 73 5 AA
89. u 1 3 1 4 1 6 1 7 1 12 1 13 1 14 1 15 1 17 5314 820A high low FSS HF OS FSS high 0000 CTOTLZ 0260 1 18 1 19 1 20 10 1 10 2 10 10 10 10 6 10 7 10 9 10 10 10 11 10 12 10 13 10 14 10 18 11 1 libe 11 3 11 4 11 8 11 4 11 7 11 9 Lib 0 low high high HF03 high 3213 9909 0004 5701 3213 9909 FSS CC 1 87PU 87PU 4793 high 9346 F9HS CP SS 936586 F9HS FOS CTL 4 51 Performance Tests and Troubleshooting Model 64601A u u u 11 10 11 11 11 12 11 13 11 14 19 02 19 3 19 5 19 7 19 9 CTL h 52 CP OS FOF 1 FoF 1 P360 2C0u high 06PA 6434 CPSS low low FoF lou P 350 0614 2G0U 0614 Low high OF OF 0635 3964 2cou OF 6F 0636 FSS 5944 3939 LAgF 3539 1 9 37U1 high HSSH S736 3964 low low 3539 low P2FH 1 9 0614 9701 08414 low high APEP OSAC CFA 4432 HF DS u u U u u u u u 19 10 19 11 19 12 19 13 19 14 21 041 di 2 21 3 21 5 ale 21 7 21 10 21 11 21 12 21 13 21 14 21 18 27 1 evn g d 7 2 4 27 6 d 7 2 9 27 11 27 12 27 13 27 14 31 04 31 2 31 3 31 4 31 8 31 6 31 7 31 8 31 9 31 10 31 11 31 12 31 13 31 14 31 15 51 16 32 1 32 2 32 3 3 4 32 5 32 6 32 7 32 8 3d 9 32 10 CFA9 high low HF OS low high B7 FF BP 64 32 80105 1410
90. u u 0 Uu u Li u 3 4 32 37 7 37 8 32 9 37 10 37 12 37 13 37 14 32 18 37 17 37 18 37 19 37 2 37 24 380 1 38 3 8 4 38 6 8 7 38 9 38 10 38 12 38 13 38 14 38 15 38 17 38 18 38 19 38 20 38 24 42 42 p 42 4 42 6 4 9 lt 7 49 11 49 15 54 f a4 g4 4 5 4 94 u4 1 4 11 ug 12 34 13 24 14 34 15 s O CH d OP PO o 55 1 55 2 high low 3780 PHAP UZEO 0000 5206 0000 high 0000 low high high 3746 0000 GP 76 F8H1 high low high OF OL 0000 3206 0000 high 0000 low high high 746 high FOSS high UZEO Low PHAP high F746 F746 9F01 1064 659 058 5706 S667 1601 F746 lou F246 0770 high PHAP u ue 4 maw 6 um oy oe 9 55 10 5612 8 13 2 1 82 57 7 57 9 67 10 67 11 67 12 67 13 82 14 71 7 1 71 2 71 7 3 71 4 71 7 6 7 1 7 71 9 71 10 71 711 71 12 71 15 71 15 23 041 Pao 235 7 3 23 73 23 23 10 73 11 73 12 23 13 73 14 73 19 86 2 85 3 86 12 865 13 fr r O E g i b iN PO 7 SUF low Low 0770 Low SUAS UFFO 8305 low high UZF ND low 3206 CIEE 3206 3746 WPF O 37U6 low high CSCC 1PUC 1601 2C2H CHCE OOO 1PUC QU7H SECS U H 6305 TZIE high 1250 905 3294 1290 0000 6905 10654
91. uU de uU Lee 6 U 1S8 7 uU 19 g u 15 10 U 15 11 U 18 12 15 13 18 14 15 15 U 17 3 17 4 u i 7 u 11 u 19 7 U 21 6 21 10 U 21 12 U 24 53 U 24 7 24 11 uU 24 12 U 27 4 U 27 6 uU 27 7 U 34 13 u 35 7 39 13 U 36 1 CTOTLZz 36 3 U 36 4 4 48 AF14 CAFF 9249 14 AGP HAHH 146A 1486 6HC 9 66H HAHH 1485 6HC 9 60H high 1 Casu OAH SAF 1 Cagu AGP RFCS PCPH FAI F711 16CC 9 PCPH F711 16CC 98 HCO BEP 136 PeCA P2CA 40 PF SAL AF14 BHA C6FF P294 P284 paga 0000 0520 A418 36 6 36 7 36 8 35 9 365 10 36 12 36 13 36 14 38 18 36 17 TOTLZ Li u 0 u TOTLZ 0 u 1 LJ u U 3 U uUi u 36 18 36 19 36 20 36 24 52 1 37 3 37 4 37 6 37 7 high Low low low 418 AYP high APP high 0000 05209 low high high hiqh 0000 209 6AHC 0051 high low 1SP 2 HAA low AYP high AGP high 0000 TOTLZ 0520 u u LI 32 18 32 19 37 20 37 24 38 1 low high high high 0000 CTOTLZ 0520 u U u Li u u 0 u u u 38 3 8 4 38 6 38 7 48 8 38 10 38 12 358 13 38 14 38 15 380 17 TOTLI Z 0 u 38 18 38 38 20 38 24 42 6 9924 high low low high 8 0ca APP high APP high 0000 0520 low high
92. 0 0 Box 92105 LOS ANGELES CA 90009 Tel 213 970 7500 Telex 910 325 6608 CH CM CS MP Hewlett Packard Co 3200 Hillview Avenue PALO ALTO CA 94304 Tel 415 857 8000 CH CS E Hewlett Packard Co 0 Box 15976 95813 4244 So Market Court Suite SACRAMENTO CA 95834 Tel 916 929 7222 A CH CS E MS Hewlett Packard Co 9606 Aero Drive P O Box 23333 SAN DIEGO 92123 Tel 619 279 3200 CH CM CS E MP Hewlett Packard Co 2305 Camino Ramon C SAN RAMON CA 94583 Tel 415 838 5900 CH CS Hewlett Packard Co 0 Box 4230 Fullerton CA 92631 363 Brookhollow Drive SANTA ANA CA 92705 Tel 714 641 0977 A CH CM CS MP Hewlett Packard Co 3003 Scott Boulevard SANTA CLARA CA 95050 Tel 408 988 7000 Telex 910 338 0586 A CH CM CS E MP Hewlett Packard Co 5703 Corsa Avenue WESTLAKE VILLAGE CA 91362 Tel 213 706 6800 E CH CS SALES amp SUPPORT OFFICES Arranged alphabetically by country Colorado Hewlett Packard Co 24 Inverness Place East ENGLEWOOD CO 80112 Tel 303 771 3455 Telex 910 935 0785 A CH CM CS E MS Connecticut Hewlett Packard Co 47 Barnes Industrial Road South 0 Box 5007 WALLINGFORD CT 06492 Tel 203 265 7801 A CH CM CS E MS Florida Hewlett Packard Co 0 Box 24210 33307 2901 N W 62nd Street FORT LAUDERDALE FL 33309 Tel 305 973 2600 CH CS E MP Hewlett Packard Co Box 13910 6177 Lake Ellenor Drive ORLANDO FL 32809 Tel
93. 0 low CTL 4 91 Performance Tests and Troubleshooting Model 64601A 90 11 low U 95 9 383A U 99 2 383 90 12 high CTOTLZz0024 TOTLZ 0025 _ 90 14 high 95 10 8984 99 3 144P U 90 15 high 95 11 SAFC 99 4 SHEA 0 91 6 high 95 12 5632 0 99 5 SHoA U 91 7 high U 95 13 82PU 99 6 HOA 0 91 9 high 95 14 8779 99 B7AA U 91 10 high U 95 15 1166 97 9 SUHO U 91 11 high 98 1 high U 99 10 GUHO U 91 12 high U 96 2 383A 99 11 AAAS 91 13 high 20024 0 99 12 3836 U 91 14 high U 96 3 lou 2 0001 U 91 15 high 96 4 high 99 13 high 0 92 1 high U 96 high 0100 21 high 92 2 high U 96 8 high 0100 22 A424 92 5 low U 96 7 high 0100 3 0000 0 92 7 low U 96 9 383A TOTLZ 12519 U 92 9 high TOTLZ 0001 U100 4 high U 92 10 low U 96 10 4352 U100 31F8 92 12 high 96 11 4CP2 U100 amp 09U2 U 92 15 high U 96 12 HuU2A 100 8 93 high 0 96 13 4521 1100 9 637 93 2 low 96 14 98860 0100 10 high U 93 5 low U 96 15 CC34 Ut00 11 0000 93 7 Low 97 1 TOTLZ 12519 U 93 9 high 0 97 2 87 4100 12 1716 93 10 high U 97 3 P746 U100 13 high U 93 12 high U 97 4 48684 4101 1 3834 U 93 15 high U 97 5 ala 4101 2 0000 U 94 1 high 0 97 6 C126 Widi 4 low 94 2 0000 97 8 C126 U101 5 0000 TOTLZz12519 U 97 9 0022 TOTLZ 25038 U 94 3 high 97 10 0000 U101 6 3836 94 4 low U 97 11 9684 CTOTLZz25037 94 5 low 97
94. 0005 C23 AUF 200US 500US 1 5 2 jus 2 3 247 75 2 U31 3 7 10 13 032 N 1 10 100 ETC Q R13 1 3K Sab ais 11 14 R4 1 c22 K 10PF dv dv U28 HIGHS CONNECT gt D 031 OUTPUTS PINS 8 29 RESISTOR PAKS 1 O TO 5 2V 5 50 500 ETC SCHMITT NOT FIRE FOR LESS THAN an Eun TRIGGER 16 CHANNEL DURATION ADJUSTMENTS R4 6 7 R25 511 RESISTOR 018 UNCONNECTED PINS R2 018 NONE U26 4 5 6 s U33 8 10 U41 3 5 R1 U53 22 LE AND 2 LE PDUR gt A 5 U68 4 10 U26 33 41 47A 4 00 7 16 15 14 13 12 11 10 9 RH 123452678 815 432 o z x lt M ui r 3 25 072 8 0 HE ATRANSIT O29 uem d 1 5 6 2 7 4 MIO NONE 2 4 Figure 8 12 Service Sheet 4 Term Generator A CTL 8 31 CHANGE 1 TIMING DUM amp s 9 9 64601 66501 mij 82 rs pa rs Re a U18A gt LL ale 2 1 5 8 T U7 5 010 911 017 IN 2 S Mn E T N 8 10 5 e 2 5 5 OD S a u1 S I I 9 on 9 0 6 a 15 E 55 TP4 TEST R22A Il 5 x 8 bo TP2 d g S e 1 99 5 re amp l 55 u32 18 L1 S 8 eg
95. 0030 U 90 14 Olur Z 0 004 U 90 18 high 11 gnd 12 pos peg ME x edog edge adge U 91 010 01370 U 91 2 TOTLZ 0119 U 91 3 016H U 91 4 Q1lUF CTOTLZz 0233 U 91 5 0000 CTOTLZz 00112 U 91 6 high U 91 Z CTOTLZ 0004 U 91 9 high U 91 10 hiin 0 91 11 high U 91 12 O1UF TOTLZ 0002 U 91 15 high U 91 14 high 0 91 18 high U101 0000 U101 1 3 1 4 1 6 1 7 1 12 1 13 1 14 1 18 1 17 1 18 1 19 1 20 1 24 u ai 5 13 19 9 19 13 21 13 wan 9 aan 4 23 36 01 36 3 Zo 4 36 b 36 7 36 8 36 9 36 10 36 12 36 13 36 14 36 15 36 17 36 18 36 19 356 20 low high low high low low 0002 low high low low high high 5002 0002 0002 0002 0002 0002 0002 0002 0002 low low low high low 0000 low law low 0002 low high low tow high high CTL 4 49 Performance Tests and Troubleshooting Model 64601A u 36 24 0002 E 37 1 low U 37 3 high u 37 4 high uU 37 amp high U 37 Z lou U 32 9 low uU 37 10 jaw U 37 12 law U 37 15 0002 37 14 low U 37 15 high U 37 17 low U 37 18 low 37 19 high U 3 20 haigh U 37 24 0002 38 1 tow u 3B 5 law U 38 4 high 38 6 high 58 2 lou U 38 8 0000 CTOTLZz0432 38 9 high U 38 10 high U 38 12 leow U 38 13 000 38 14 low U 38 17 low U 38 18 low U 38 19 high Uu 38 20 high 38 24 0002 U 1 4 0002 U 81 12 0002 52 12 0002
96. 05 292 1330 CH CS E MS New York Hewlett Packard Co Computer Drive South ALBANY NY 12205 Tel 518 458 1550 Telex 710 444 4691 A CH E MS Hewlett Packard Co 0 Box 9600 Main Street CLARENCE NY 14031 Tel 716 759 8621 CH Hewlett Packard Co 200 Cross Keys Office Park FAIRPORT NY 14450 Tel 716 223 9950 CH CM CS E MS Hewlett Packard Co 7641 Henry Clay Bivd LIVERPOOL NY 13088 Tel 315 451 1820 A CH CM E MS Hewlett Packard Co No 1 Pennsylvania Plaza 55th Floor 34th Street amp 8th Avenue MANHATTAN NY 10001 Tel 212 971 0800 CH CS E M Hewlett Packard Co 250 Westchester Avenue WHITE PLAINS NY 10604 Tel 914 328 0884 CM CH CS E Hewlett Packard Co 3 Crossways Park West WOODBURY NY 11797 Tel 516 921 0300 Telex 510 221 2183 A CH CM CS E MS e 0 UNITED STATES Cont d Texas North Carolina Hewlett Packard Co 0 Box 26500 27420 5605 Roanne Way GREENSBORO NC 27409 Tel 919 852 1800 A CH CM CS E MS Ohio Hewlett Packard Co 9920 Carver Road CINCINNATI OH 45242 Tel 513 891 9870 CH CS MS Hewlett Packard Co 16500 Sprague Road CLEVELAND OH 44130 Tel 216 243 7300 A CH CM CS E MS Hewlett Packard Co 962 Crupper Ave COLUMBUS OH 43229 Tel 614 436 1041 CH CM CS E Hewlett Packard Co 0 Box 280 330 Progress Rd DAYTON OH 45449 Tel 513 859 8202 A CH CM E MS Oklahoma Hewlett Packard Co P O Box 75609 73147 304 N Meridian Suite
97. 1 BROWN 6 BLUE 2 RED 7 VIOLET 3 ORANGE 8 GRAY 4 YELLOW 9 WHITE OPTIMUM VALUE SELECTED AT FACTORY TYPICAL VALUE SHOWN PART MAY HAVE BEEN OMITTED UNLESS OTHERWISE INDICATED RESISTANCE OHMS CAPACITANCE IN PICOFARADS INDUCTANCE IN MICROHENRIES MICROPROCESSOR PART OF NO CONNECTION CLOCKWISE END OF VARIABLE RESISTOR COMMON CONNECTIONS ALL LIKE DESIGNATED POINTS ARE CONNECTED NUMBER ON WHITE BACKGROUND OFF PAGE CONNECTION LARGE NUMBER ADJACENT SERVICE SHEET NUMBER FOR OFF PAGE CONNECTION CIRCLED LETTER OFF PAGE CONNECTION BETWEEN PAGES OF SAME SERVICE SHEET w INDICATES SINGLE SIGNAL LINE NUMBER OF LINES ON A BUS 2 2 STD 20 09 81 CTL 8 22 Table 8 2 Logic Symbols GENERAL All signals flow from left to right relative to the symbol s orientation with inputs on the left side of the symbol and outputs on the right side of the symbol the symbol may be reversed if the dependency notation is a single term All dependency notation is read from left to right relative to the symbol s orientation An external state is the state of an input or output outside the logic symbol An internal state is the state of an input or output inside the logic symbol internal states are True High SYMBOL CONSTRUCTION Some symbols consist of an outline or combination of outlines together with one or more qualifying symbols and the representation of input and output lines INPUT
98. 1 12 cut See FIGURE 2 2 4 XE TRIG from Acq 5 XE TRIG from Acq 11 H MEMFUL from Acq 12 H MEMFUL from Acq 15 HE RESET from Contr 19 H RUN from Contr 20 L PVC from Contr TIMING BUS 1 ACQ BOARD 2 TIMING BUS 2 ACQ BOARDS Figure 2 2 Timing Bus Cables 2 4 Installation Model 64601A 2 24 OPERATING STORAGE AND SHIPMENT ENVIRONMENTS CAUTION THE GLITCH U27 AND ENCODER U22 25 CHIPS ON THE 64602A ACQUISITION BOARD ARE VERY SENSITIVE TO STATIC THEY SHOULD BE LEFT IN CONDUCTIVE FOAM UNTIL INSTALLATION GROUNDING STRAPS AND A GROUNDED WORK STA TION ARE RECOMMENDED WHEN HANDLING THE ICS 2 25 Operating Environment 2 26 The Model 64601A may be operated in environments within the limits show below It should be protected from temperature extremes which cause condensation within the instrument Temperature 10 to 107 degrees Celsius Humidity 5 to 80 relative humidity Altitude m 4 600 m 15 000 ft 2 27 Storage Environment 2 28 The Model 64601A may be stored or shipped in environments within the following limits 40 to 70 degrees Celsius Humidity 2 5 to 80 relative humidity Altitude iiec EA 15 000 m 50 000 ft 2 29 Packing 2 30 Tagging for Service If the instrument is to be shipped to Hewlett
99. 10 H14P 08000 FCSF FCLF Performance Tests and Troubleshooting Model 64601A CTL 4 63 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Beard TRANSITION TRIGGER 3 FCG NORM MODE UH Temporarily connect U13 pins 12 and 14 together DATA THRESHOLD HIGH ttl amp CLOCK THRESHOLD ttl ST SP O0L THRESHOLD ttl Location of ST SP START tp 12 neg edge Location of QUAL STOP tp 12 edge location of CLOCK tp 11 pos edge Location TTL U 49 of GROUND 9 Fle 4 FOR 49 3242 Z 0207 u U 49 1 low Uu 91 0000 0 LJ 49 1 U 85 85 u 85 U 85 85 U gie U 85 SD XM CS CH Gi PFE CH P U 85 12 U 85 14 U 85 18 83 16 U 85 17 85 18 U 85 19 uU 88 U 85 7 U 86 10 86 11 90 1 90 2 9 3 U 90 4 LU 90 90 6 90 12 0 90 13 U 90 14 TOTLZ 0001 U 90 15 U 91 1 U 91 2 CTL 4 64 HiS FC27 2 9 CUSA 3242 FAAC 3244 BAPE Pog Hala 7FCS 1632 low 3535385 FC27 583 FC27 7FCS 4999 FOHA 4524 low 324F high H458 high ncn U 91 3 ADC CTOTLZ 00019 91 6 high 91 7 FCS CTOTLZz0001 U 91 9 high 91 10 high U 91 11 high 91 12 FC27 U 91 15 FCA U 91 14 high U 91 15 FC2 Co 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 10 15 11 15 12 15 13 1
100. 127 NO u31 ET g 7 m No er a ri g 8 8 SS 9 9 a 8 T E R21 r 9 R21 R22 5 DOE 5 Lider g 9 9 9 o 8 2820 o 8 8950 O S 047 lll 688 5 442 U44 U46 s 9 037 U38 8 T e st 5 5 8 F U47A e a 9 Q TEST _ 7 9 0 6 GND NORM NORM 9 05 0 9 TEST 9 9 9 E a 8 U57 U58 a 961 8 5 8 9 o 9 8 l LIC9T m 9 9 9 R 6 967 OR o U71 973 074 2 076 979 E e 59 5 E 8 5 9 T 9 9 1 4 2 e o o o b T N 5 9 9 e g usj u93 97 5 8 3 8 t a o T Y 5 T T Y D C94 95 C96 P1 85 R38 FROM 130 BIT REGISTER ACQUISITION TRIG GERS MAY BE HIGH OR LOW TRUE m m z z 4 od 2 N gt gt XE TRIG 1 ACQUISITION TRIGGER COMBINATION XE TRIG 2 AND OR U13 34 35 Sn8 ONIWIL SNS DNIWIL TERM GENERATORS i e TERM GE
101. 16 499 9333 CH Quebec Hewlett Packard Canada Ltd 17500 South Service Road Trans Canada Highway KIRKLAND Quebec H9J 2M5 Tel 514 697 4232 A CH CM CS E MP P Hewleit Packard Canada Ltd Les Galeries du Valion 2323 Du Versont Nord STE Quebec G1N 4C2 Tel 418 687 4570 CH CHILE Jorge Calcagni y Cia Ltda Arturo Buhrle 065 Casilla 16475 SANTIAGO 9 Tel 222 0222 Telex Public Booth 440001 ACMEM Olympia Chile Ltda Av Rodrigo de Araya 1045 Casilla 256 V SANTIAGO 21 Tel 02 22 55 044 Telex 240 565 OLYMP CL Cable Olympiachile Santiagochile CH CS P CHINA People s Republic of China Hewlett Packard Rep Office 0 Box 418 1A Lane 2 Luchang St Beiwei Rd Xuanwu District BEIJING Tel 33 1947 33 7426 Telex 22601 CTSHP CN Cable 1920 A CH CM CS E P COLOMBIA Instrumentaci n H A Langebaek amp Kier S A Carrera 4A No 524 26 Apartado Aereo 6287 BOGOTA 1 D E Tel 212 1466 Telex 44400 INST CO Cable AARIS Bogota COSTA RICA Cientifica Costarricense S A Avenida 2 Calle 5 San Pedro de Montes de Oca Apartado 10159 SAN JOSE Tel 24 38 20 24 08 19 Telex 2367 GALGUR CR CYPRUS Telerexa Ltd 0 Box 4809 14C Stassinos Avenue NICOSIA Tel 62698 Telex 2894 LEVIDO CY EMP DENMARK Hewlett Packard A S Datavej 52 DK 3460 BIRKEROD Tel 02 81 66 40 Telex 37409 hpas dk A CH CM CS E MS P Hewlett Packard A S Rol
102. 185 89868 U 98 1 high 95 2 0000 9 U 92 3 high U 95 4 high 95 3 Low eae 6 low U 95 2 high U 95 9 REA 0024 U 95 10 898A LU 95 11 SAFC 95 12 S632 tl M EN U 95 13 92 14 87929 uU 95 18 1156 96 1 high U 96 2 3836 CTOTLZ 0024 96 3 low 0 98 4 high U 96 high U Po amp high U 96 high U 98 9 3834 CTOTLZz0001 95 10 U3Sz 0 95 11 4CPa U 96 12 HUZ 96 13 321 U 98 14 986C U 98 185 97 1 U 92 2 BAA 92 3 ASHS U 97 4 97 UAUC 97 5 1 92 8 LSPA 92 9 97 10 00600 97 11 9680 97 12 APCS 0 97 13 3834 CTOTL Zz12918 98 1 high U 98 2 U 98 4 QPEL U 98 5 U 98 8 729P 98 7 45854 U 98 9 SESS CTOTLZ 25037 5 U 98 10 BFAR U 93 11 090 98 12 BFAR 1 98 15 9680 U 98 14 0000 U 98 18 3836 99 1 0001 gt U 99 2 383A CTOTL 2 002 U 99 3 14 99 4 SH64 U 99 5 Performance Tests and Troubleshooting Model 64601A U 99 6 HOA U 99 amp BPA U 99 9 SUHO U 99 10 6UH U 99 11 4664 0 99 10 3836 CTOTLZ0001 U 99 13 high U100 i high ui00 2 368C Widd 3 0000 2 12519 gt 0100 4 high Ui00 HOSC 0100 66 P301 ui 8G Parr 100 F 4C46 0100 10 high 1100 11 8000 14100 12 Hast 100 13 high 0101 11 3835 4101 2 10000 U101 4 low 4101 0000 TOTLZ 250 38 4101 10 dow
103. 1941 061 N 079 992 92 o 2 z 95 051 695 092 9 B 6S9 t H 6dl 692 92 i E 9 U76 U74 82 6 85 8 e 5 9 12 078 077 8 9 o Sin 8 5 073 2 C96 U71 919 gt 9 5 89N 067 219 6 2 son 042 42 65 662 N e T U97 L62 069 682 882 282 1141 982 o 5 e t M 2 582 C94 Adjustments Figure 5 1 CTL 5 2 Adjustments Model 64601A 5 7 SAMPLE RATE OSCILLATOR CALIBRATION 5 8 Setup 5 9 1 the coaxial testpoint for the oscillator is located at the very top center of the board when viewing from the component side The oscillator transistor 01 and its trimmer capacitor C7 are located at the top of the board between U7 and U8 See figure 5 1 5 10 Using the mainframe keyboard and softkeys configure the timing analyzer for the oscillator adjustment as follows a Press softkey timing then RETURN The screen should show the trace specification b Verify that the mode is wide sample and the sample rate is 200 MHz c Press the softkeys trigger on entering POD1 0
104. 200 0 OMM X 9 01121 2104201 RCUR ECL LINE RCUR TPL 2 INP 04713 MC10216L IC RCUR ECL LINE RCUR QUAD 2 INP 04713 MC1692L NETUORK RES 10 SIP330 0 OMM X 9 01121 2104331 IC FF ECL D M S POS EDGE TRIG COM CLOCK 04713 MC10176L n M 7 O A1U11 1820 2193 1U12 1810 0272 A1U13 1820 0815 8103 4 1810 0272 ALUIS 1820 2193 41016 1810 0271 IC FF ECL D M S PDS EDGE TRIG COM CLOCK 04713 MC10176L NETWORK RES 10 SIP330 0 OHM X 9 01121 2106321 GATE ECL AND OR 04713 MC10121P NETWORK RES 10 81P330 0 OHM X 9 01121 2104331 IC FF ECL D M S POS EDGE TRIG COM CLOCK 04713 MC10176L NETUDRK RES 10 5 200 0 OHM X 9 01121 2104201 41017 1820 0815 ALUIBA 1810 0281 A1U18 1810 0541 81019 1820 0802 61420 1810 0271 GATE AND OR 04713 MC10121P NETWORK RES 10 SIP100 0K OHM X 9 01121 2106104 NETWORK RES 6 SIP MULTI VALUE 28480 1810 0541 IC GATE ECL NOR QUAD 2 INP 04713 MC10102P NETWORK RES 10 S8IP200 0 OMM X 9 01121 2106201 N pon NS GD NG bes amp 1U21 1820 0802 amp lU22 1820 2664 1820 1225 A124 1820 0796 a1ues 1810 0272 IC ECL NOR QUAD 2 INP 04713 MC10102P CNTR ECL RI QUINARY R S POS EDGE TRIG 04713 MC16781 FF ECL D M S DUAL 04713 MC10231P IC GATE ECL NOR QUAD 2 INP 04713 MC1662L NETWORK RES 10 SIP330 0 OHM X 9 01121 2106331 NETWORK RES 10 SIP200 0 X 9 01121 2104201 IC GATE ECL NOR QUAD 2 INP 04713 MCi0 02P IC FF TTL LS D TYPE POS EDGE TRIG COM 01295 SN741 8273N NETWORK RES 16 DIP3
105. 3 3 0000 Z OFLOO U 53 4 H125 amp 3 8 4319 U 63 6 H125 U 63 high 83 9 Low U 83 10 high 653 11 0000 CTOTLZzZQFLO U 63 12 high U 63 13 low U 76 1 923F CTOTLZ 32764 3 0 75 3902 76 3 GaP U 75 4 2490 U 76 5 5351 U 76 6 2186 76 7 58383 U 76 9 U 76 10 2UCH U 76 11 Cease U 76 12 C073 U 76 13 AHCC U 76 14 5 U 76 18 923F CTOTLZZ32764 U 77 7 1 19 U 77 PUSE 77 X 09 CTL 4 67 Performance Tests and Troubleshooting Model 64601A 4150 KE U 94AF u u low AHCC U 835 6 high U 85 2 C292 U fe 8 low i B 9 U 83512 85 14 C883 91 10 2 0048 91 11 CTOTLZ 765 91 12 91 13 91 14 923F 552 high high 923F SCAN 85 15 low AABE 85 16 5351 TOTLZ 0040 U 85 17 low 91 15 high 85 18 93P7 was high cove 85 19 high U 92 CCHU high 88 1 low 92 9 3P7 U 77 18 low U 88 2 high U 92 5351 77 19 9925 U 88 2 0000 U YE F265 u 77 20 923F TOTLZ 99213 92 C893 CTOTLZZz0018 U 88 4 0000 U 92 7 2498F 77 21 SUP CTOTLZ 98537 92 9 9 77 22 high 88 5 923 TOTLZ 0040 81 1 low TOTLZ OFLO U 22 10 cues U 81 2 loq 88 6 0000 U 92 11 U 81 3 95050 99215 gt 92 12 HICA U 81 4 low 88 3 low 92 13 AHCC U 81 5 low 88 9 high U 92 14 C252 U 81 5 Cars 88 10 lo
106. 3 2709 55 1 high U 37 14 0000 U Si 2 69C9 37 15 high U SS 4 6P70 U 37 17 0000 U 55 6 Low U 37 18 low 0 55 7 low U 37 19 high U 58 9 ZUZP 37 20 high U 95 10 low U 37 24 3716 U S3 11 Firs CTL 4 60 Performance Tests and Troubleshooting Model 64601A 646016 Timing Control Board LESS THAN INTERVAL 7 NORM MODE VH S935 THRESHOLD HIGH ttl amp Temporarily connect U13 CLOCK THRESHOLD ttl pins 12 and 14 together ST SP QL THRESHOLD ttl Location of ST SP START tp 12 nag edge Location of QUAL STOP tp 12 pes edge Location of CLOCK tp 11 pos edge Location of GROUND gnd TTL U 44 1 high J 47 6 0 16 DEN U 90 14 8934 44 2 low U 47 7 0 01 DPEN U 90 18 high 44 3 HHHU uU 47 8 4 99 DCU U 91 1 0582 44 AUA2 U 47 9 0 16 DCU U Pie 2 CUO 44 low U 47 10 0 01 DEY U 91 3 0508 U 44 6 low U 42 11 4 99 PEN 91 4 5934 44 7 BHFF U 47 12 0 91 DCN 91 8 0000 44 8 5153 47 13 0 01 PEN U 9 1 6 high 44 9 low U 47 14 0 04 U 91 2 3935 U 44 11 5938 49 4 r3u U 91 12 8936 44 12 high U 49 PPA 91 13 U 44 13 8067 49 12 low U 91 14 high 44 14 SFL U 49 13 FOC U 91 18 S936 44 18 Low U 85 1 59204 44 16 high 85 2 44 18 8874 88 3 44 19 low 85 4 PARE u 46 4 53 DON 8 5 5 AAG amp 9226 7 U 46 2 5 17 85 1 2 46 3 8 11 DEN oge U 46 4 3 17 DCV U 85 9 Ho
107. 30 0 OHM X 8 01121 3168331 NETWORK RES 16 DIP6 8K OHM X 8 01121 316B682 TRANSISTOR ARRAY 16 PLSTC DIP 28480 1858 0054 1426 1810 0271 4127 4820 0802 1128 1850 71730 1129 1810 0402 1030 1810 0243 1031 1858 0054 CP Pom TRANSISTOR ARRAY 14 CER DIP 31 585 045 NETWORK RES 10 SIP200 0 OHM X 9 01121 2104201 IC RCUR ECL LINE RCUR TPL 2 INP 04713 MC10216L GATE ECL DUAL 04713 MC10117L IC DELAY 28480 1 4 55008 1032 1821 0002 81033 1810 0271 1034 1820 1520 1035 1820 1946 ALUS6 1 4 5008 OOO NIG IC DELAY 28480 1NR4 5008 IC DELAY 28480 1 4 5008 IC MUXR DATA SEL ECL QUAD 2 INP 04713 MC10158L IC FF ECL D M S DUAL 04713 MC10231P NETUORK RES 10 SIP200 0 OHM X 9 01121 2104201 611137 1484 5008 27058 1 4 5008 81139 1820 1993 1040 1820 1225 1041 1810 0271 GATE ECL DUAL 04713 MC10117L IC GATE ECL NOR QUAD 2 1NP 04713 MC10102P IC FF TTL LS D TYPE PDS EDGE TRIG COM 01295 SN74LS273N NETWORK RES 16 DIP330 0 OHM X 8 01121 3168331 A1U42 1820 1946 1045 1820 0802 81144 1820 1730 1145 1810 0402 N P5 ooo See introduction to this section for ordering information Indicates factory selected value CTL 6 6 Reference Designation A1U46 ALU47A 1047 21048 41049 21050 61051 1052 1053 1154 1455 81056 41057 1058 1459 1U60 1U61 21062 61063 1064 1465 1166 41067 21068 41069
108. 32 RESTSTOR 261 RESISTOR 162 SMB FEM PC 50 SM SNP M PC 50 OHM SMB FEM PC 0 0HM H MLD 100NH 10 1050 261 6 H ML D 120NH 10 105DX 26LG IN DIA 25 IN LG STL MALE PLUG MALE PLUG MALE PLUG SI PDz180MM FTzAGHZ 1K 102 C 1K 102 C 8 00 10 C 1K 10 C 8 1K 10 CS ADJ 1 TRN ADI 1 TRN 500 10 C SYIDE ADJ 1 TRN 1 1 x x 2 d 1 SW F 1 125W F T 1 129W F T 14 125W F TC 1 1 39 2 1 39 2 1 125W 1 39 2 1 125W 0 100 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 72136 28480 28480 28480 28480 28480 28480 28480 28480 56289 28480 28480 28480 28480 80 28480 28480 28480 28480 28480 25403 20480 80 28480 24546 24546 24546 24546 24546 See introduction to this section for ordering information Indicates factory sele cted value Replaceable Parts List Con t Mfr Part Number 0160 2055 0160 2055 0160 2055 0160 4813 0160 2055 0160 2055 0150 2055 0160 2055 0150 2055 0160 2055 0160 2055 0160 2055 DM1SF201J0300UU1CR 0160 2055 0160 2055 0160 4808 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 1500106 9020 2 1500106 9020 2 1500106X9020582 0160 4822 0160 3569 1901 0040 1250 0543 0 1189 1250 0543 1250 1189 9100 2247 9100 2248 1480 0116 64601 85001 64601 85002 2100 3351 4 1 8 0 1001 24 1 8 0
109. 4 40 Test 7 Less Than Interval 4 14 4 54 Test 8 Transition Trigger e Sees 4 15 4 59 Test 9 Display Driver X 4 16 4 60 Test 10 Rates Interval A 16 Ch Only 4 17 4 61 Test 11 Less Than Interval A 16 Ch Only 4 17 4 62 Test 12 Transition Trigger A 16 Ch Only 4 17 4 63 Test 13 2 16 Ch Only 4 18 4 67 Test 14 2 16 Ch Only 4 19 4 70 Test 15 B Followed by A 16 Ch Only h 20 4 74 Supplementary Display 4 21 4 75 Inter Module Bus Performance Verification 4 37 4 87 Supplementary Board ID Test PP 4 0 4 90 Signature 1 4 46 Model 64601A Table of Contents VII Vill TABLE OF CONTENTS CONT ADJUSTMENTS x EEE t svp 5 1 Introduction i desee edens dese te oae ee dd ae D TE 5 3 Safety 5 iSi as 5 1 5 5 Equipment 5 1 5 7 Sample rate Oscillator Calibration SU sd ux 5 3 5 12 Trigger Duration Calibration RRR ENE DD 5 17 Bakrdware SetuP yy asus sasata aa 5 5 5 18 Keyboard Setup for 8 Channel Adjustment R1 R3 5 5 5 19 Adjustment for 8 Channel System R1 R3 5 6 5 20 Keyboard Setup for 16 Channel Adjustment R4 R
110. 4 Timing Probes 2 HP 64604 61601 Timing Cables HP 1722B Scope or equivalent HP 5314A Universal Counter or equivalent HP 10017 Probe or equivalent BNC Coaxial Cable approx 1 meter long Alignment Tool Small Screwdriver HP 64110 66503 Extender Board Part of 64934A Service Kit 4 Extended coaxial clock cables Part of 64934B Service Kit HP 3 way extended timing bus cable Part of 649348 Service Kit CTL 5 1 Adjustments Model 64601A 9ED 86H b e 9 A 5 610 9 SZzH b O 812 viH ely sin 19 t 9 M e 2 2 512 3 vin 8 zn 12 0 9 g 5 N 5 en 920 629 zu 9 29 gz 422 941 kdl 48 0iH gha 62 5 sen B xO ail a 3 N EN 2 D ozu 91 619 WHON sig S a 3 22 02 lt dl 22 a N og E 91u 2 TT oe 5 9 2 F z F 8S9 159 949 lt 552 s 5 52 S9 H H I H N 5 652 152 0 H 6v2 092 890 62H LV2 9V2 ben SrO RE rr ES evo vO 2 0v2 U37 862 6 2 LEO U100 U101 R38 0
111. 41 13 4 13 1 18 tas 18 15 1 1 15 15 15 1 15 1 15 1 15 1 15 1 1 3 4 te sd I U b GIO low HHL 4764 PPUF 1 low high 777P 3CCcu PPUF 777P 3CCU 0000 130 1 2 3 4 6AA7 PSAC 5555 PSAC 5555 high PASS HAAF low low PSAC low low 4764 LHP low high CP17 55 14 589 15 54 7 654 11 CP17 F33U ASUG FSU 4996 2939 high high HPCS CP17 2939 0781 972P 4996 low 2939 4996 F3SU B94F Low HF SY high BIFU 0498 A7 6H 8622 6476 290 CIFU low Hist high HF SY CEUS UC7H A3CL low low H16 low CSF Uol CU low Pun Performance Tests and Troubleshooting Model 64601A LI Uu Li u LJ 54 18 7 1 71 9 7 T 4 W 71 1 71 1 5 4 3 POS iF m gt 1 10 71 711 71 712 71 13 71714 23 vi A uu 23 7 3 d 1 low nign ELEZ 8823 4P FEQI CIL 8823 0000 TOTL Zz0130 9Ap9 PHU UUA PHUA USUA UC H hioh AAT A 249 NIHA HOC AAT A 245 0000 20180 76H 2AFP AFGH 24FP F29U CTL 4 79 Performance T sts and Troubleshooting Model 64601A 646016 Timing Control Board 14 NORM MODE DATA THRESHOLD HIGH ttl amp CLOCK T
112. 4319 U 93 10 HPUA 93 11 6P3C U 98 12 94AF U 95 15 U 98 14 9vuUuPc U 95 18 U 96 1 high U 96 2 923 CTOTL Z 505552 U 96 ONT 96 uu22 96 193 U 96 605948 96 high U 95 4319 U 96 10 U 96 11 AJAS U 98 12 168H U 96 13 HCHC U 96 14 Bau U 98 18 89HF GSI UD Performance Tests and Troubleshooting Model 64601A CTL 4 69 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Board RATES INTERVAL A NORM MODE DATA THRE CLOCK THR ST SP QL Location Location Location Location TTL gg 1 28 2 28 3 U 28 4 ag 5 28 6 U 7 U 28 8 28 uU 28 11 U 28 12 28 13 U 28 14 d 28 15 U 28 16 28 17 28 18 U 298 197 U 49 4 U 49 5 U 49 12 85 15 85 16 U 85 17 iu 85 18 85 19 U 86 CTL 4 70 SHOLD HIGH ttl ESHOLD ttl THRESHOLD tti of ST SP START of QUAL STUP of CLOCK tp 11 of GROUND gnd high 4999 Hist CCUS 1590 3631 DHEA 135 UA CS SP 30 3073 USPH UP OP low 2904 low PHAP F036 29C4 OP OF UFFO USPH low uic3 SPA 4631 OF OS CRUS low HIBU FOSS 329 12 amp 7 U 86 10 U 86 11 U 90 041 0 2 U 90 3 U 90 4 U 9 f U 90 6 uU 90 13 U 90 14 neg pos pag 036 O SFA3 6914
113. 5 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 4813 01460 3875 0160 4492 0160 2055 0160 2055 DMISF241J03004U1CR 0160 5415 0160 5343 0160 5342 0160 5874 0160 5341 0160 2055 0160 2058 9160 2055 0160 2 0160 0160 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2 Reference Designation A1C71 1 72 A1C73 1C74 AIC7S ALC7S 1 77 ALC78 1679 A1C80 61081 A1C82 A1CB83 1C84 A1C8S5 1C86 A1C87 A1C88 AlCEy 81090 A1C91 1 92 81093 1C94 AIC AICI A1C97 A1C98 ACRI 1J1 AlJa ALIS ALTA A1L2 A1MP1 ALMP2 AMPS ALP1 1 2 ALPS AIRI AiRi ALIKE ALRS AIRA ALRS ALRG ALR AIRS AIRS AIR10 2 11 1812 1615 1614 AIRIS 116 1617 A1R18 ARID ALR20 Table 6 2 HP Part Number 0160 2055 0160 2055 0100 2055 0160 4813 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2035 0160 2055 0160 2055 0140 0198 0160 2055 0160 2055 0160 4808 0160 2055 0180 2055 0160 2055 0100 2055 0150 2055 0160 2055 0160 2055 0180 0374 0180 0374 0180 0374 0160 4822 0160 3569 1901 0040 1250 0543 1250 1189 1250 0543 1250 1189 9100 1480 0116 64601 85001 64601 85002 1258 0182 1258 0182 1258 0182 1854 0591 2100 2109 2100 2100 2100 0280 0280 0757 0427 0257 0414 0698 3132 075 0257 0391 0757 0391 x oO wu O OO OO 75950 pnt once Replaceable Pa
114. 5 14 15 15 17 1 high U32H 7CSP P amp SA U32H 0000 9H9P 9H9P 4632 high PPCES 4243 8004 PPCES 4243 8095 1F3U 8095 7CSP high Performance Tests and Troubleshooting Model 64601A 17 2 PA12 37 18 low U 54 12 BPR 17 3 2135 U 37 19 high U 54 13 U 17 4 U 37 20 high U 54 14 aP72 17 5 Lew uU 37 24 966 54 15 4555 U 17 6 low 38 1 0000 U S5 1 high U 17 7 95 U 38 3 4632 U 5 2 MW916 U 17 9 low U 38 4 U 55 4 5691 17 10 low 38 6 high U 55 5 05980 U 17 11 1F3U U 38 7 low U 55 6 low U 17 12 0002 U 38 9 high 55 7 Low 17 13 7C5P U 38 10 U 55 9 4555 17 14 0002 U 38 12 0000 U 55 10 low U 17 15 low 38 13 U9 amp 8C 55 11 ULF U 34 6 uU 38 14 0000 5 12 3242 U 34 7 ACC U 38 15 high U 55 13 AZAN U 34 9 19 U 38 17 0000 55 14 U 34 13 3C8P 38 18 low U 55 15 low 34 14 1049 U 38 19 high U 82 1 high uU 34 15 FCA U 38 20 high U 67 2 Low U 35 10 UNA U 38 24 UFSC 67 3 Jou U 35 11 42 10 FC27 oF 4 FIPS U 35 12 2135 U 42 11 1935 U 5 USAC U 35 13 3CaP 42 12 PPC U 67 6 U 35 14 19 42 13 19 67 7 UFOS U 35 15 1ACE U 42 14 CAFI 67 9 UFAC u 36 1 0000 U 42 15 71P6 67 10 2242 U 36 3 CC7P U 43 1 high U 67 11 4218 U 36 4 7P9C 43 2 27 U 67 12 UJC U 36 6 high 43 3 1938 U 67 13 lo
115. 5H53 low 136F ZAP 2C uy 9 13CF 89 0000 50130 2 2 f 1 CAUL 137P 157P 644p high APC 6404 Low low CALL lou low 1 S7P 38H53 low high high FIPA 84541 TES 42 7 Ape 9 42 10 42 11 42 12 42 13 42 14 42 1 4e 1 54 3 54 4 u4 3 54 6 54 7 uae 9 54 10 54 11 54 114 54 13 54 14 54 15 Sse 1 sge 2 55 4 154 MU 55 6 SSe 7 mue fes s MP gt low high 13CF F102 Q high 0535 C036 GUS 5947 9puy1 42 FS2C OHSS C036 low CUS 716 high 1888 4862 CAPO low low 7169 low 80 0446 F102 low TARE CHF amp low high low 0 SH BP 42 ERI BP ag 1888 8259 apar low 6606 high high low U 69 3 0000 CTOTLZz 130 U 69 4 9949 U of low U 69 amp 0000 CTOTLZzO0170 69 BPa U 69 9 3240 69 10 U 69 11 U 89 18 4314 LJ 69 13 high U 59 14 035170 U Fie 1 high U 71 2 U 71 3 FRF 71 7 18HP uU 71 85 OHSS 71 6 1759 71 2 725F u71 9 0000 CTOTLZ 01 30 U 71 10 18HP 0 71 11 F36P U 71 12 0U46 U 71 18 F36P 71 14 0U46 uU 74 15 4862 U 25 21 high 73e 2 8949 U 73 5 FASS U 73 4 AQHA 0 73 9464 U 73 6 5949 25 2 FAD 73 9 0000 CTOTLZ 01 304 23 10 73 11 6U6F U 73 12 5947 U 73 135 eF U 73 14 5947 LU 75 15
116. 6 Ohaliav St JERUSALEM 94467 Tel 533 221 553 242 Telex 25231 AB PAKRD IL A Electronics Engineering Division Motorola Israel Ltd 16 Kremenetski Street 0 Box 25016 TEL AVIV 67899 Tel 3 338973 Telex 33569 Cable BASTEL Tel Aviv CH CM CS E M P ITALY Hewlett Packard Italiana S p A Traversa 99C Via Giulio Petroni 19 70124 BARI Tel 080 41 07 44 M Hewlett Packard Italiana S p A Via Martin Luther King 38 111 40132 BOLOGNA Tel 051 402394 Telex 511630 CH E MS Hewlett Packard Italiana S p A Via Principe Nicola 43G C 1 95 126 CATANIA Tel 095 37 10 87 Telex 970291 CP Hewlett Packard Italiana S p A Via G Di Vittorio 9 20063 CERNUSCO SUL NAVIGLIO Tel 2 903691 Telex 334632 A CH CM CS E MP P Hewlett Packard Italiana S p A Via Nuova San Rocco a Capodimonte 62 A 1 80131 NAPLES Tel 081 7413544 Telex 710698 A CH E Hewlett Packard Italiana S p A Viale G Modugno 33 16156 GENOVA PEGLI Tel 010 68 37 07 Telex 215238 EC Hewlett Packard Italiana S p A Via Turazza 14 1 35100 PADOVA Tel 049 664888 Telex 430315 A CH E MS Hewlett Packard Italiana S p A Viale C Pavese 340 1 00144 ROMA Tel 06 54831 Telex 610514 A CH CM CS E MS P Hewlett Packard Italiana S p A Corso Svizzera 184 10149 TORINO Tel 011 74 4044 Telex 221079 JAPAN Yokogawa Hewlett Packard Ltd 152 1 Onna 000 ATSUGI Kanagawa 243
117. 65 4 0002 0 66 11 0002 67 0002 67 9v 0002 lJ 67 12 0002 59 7 0002 59 9 0060 U 659 10 0002 U 89 110 0002 U 69 12 O19F U 69 13 high LU 69 14 G19F U 74 13 0002 85 2 0000 U 86 3 104 U 86 12 0002 U 86 14 0019F CTL h 50 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Board TRIGGER NORM MODE DATA THRESHOLD HIGH 3 CLOCK THRESHOLD tti ST P QL L L T Li Uu u u u J u Li Li U ocation CCA TI ocation ocation TL 49 4 49 5 49 12 49 13 8u 1 85 2 gie u 85 4 Be 85 6 85 7 85 8 85 9 95 11 85 12 95 13 8 14 5 15 85 16 85 17 85 18 85 19 Boe 8 85 7 85 10 86 11 90 01 90 2 90 3 9 0 2222 3 90 05 90 6 90 12 90 12 90 14 90 15 91 1 9 1 2 THRESHOLD ttl of ST SP START tp of QUAL GTOP tp 12 of CLOCK tp 11 of GROUND gnd 8195 SP o4 CFA 1426 HUOC 81985 7416 1264 F232 low 5663 low 723 USHC low USFS 3372 CFA HUOC 0093 4736 SP 64 amp P 07 5471 low SP 64 6P07 high CH35 1725 high 4730 ttl amp ecl 12 LJ u Uu u LJ neg pos neg 1 _ 9 1 9 1 91 6 91 7 91 12 91 13 91 15 Temporarily connect 013 pins 12 and 14 together 9543 0000 0090 high 1725 HUOC OH 4730 edge edae edge ECL 1000 TOTLZ 0260 0 LJ
118. 7 37 4 116 U 54 5 1941 U 15 5 528 U 37 6 high U S4 6 U 15 6 0158 37 7 low U 54 7 PFSH U 15 7 5831 U 37 9 U 54 9 FCSF U 15 10 8617 0 37 10 low U 54 10 1817 U 15 11 CoAF 37 12 0000 54 11 2600 U 15 12 840 U 37 18 FCSF 54 12 AHS2 U 15 13 C6 F 0 37 14 0000 U 4 12 low U 15 14 84uP U 32 18 high U 54 14 AH 2 U 15 15 6820 U 37 17 0000 U 54 18 468 U 17 1 high U 37 18 low U 55 1 high 17 2 46A2 U 37 19 high U S3 2 FBC 17 3 1498 37 20 high 55 4 33H U 17 4 8617 U 37 24 FCSF U 55 6 low 17 5 low U 38 1 0000 U 55 7 low U 17 6 low 58 3 55 9 0468 17 7 U 38 4 amp 48H U 55 10 low U 17 9 low U 38 6 high U 53 11 11 amp 17 10 low U 38 7 low U 335 12 2 U 17 11 84UP U 38 9 high 55 13 1264 U 17 12 0000 U 38 10 2082 55 15 low U 17 13 6870 U 38 12 0000 U 67 1 high U 17 14 0000 38 13 FCSF 0 67 2 low U 17 15 low 0 58 14 0000 U 67 3 low 0 34 1 high U 38 15 high 67 FCSF 34 6 90 amp P U 38 17 0000 U 67 6 0628 34 13 074 38 18 low 67 7 CP98 34 14 95276 38 19 high U 67 9 FCSF 34 15 high U 38 20 high U 67 10 P762 U 35 10 5P76 U 38 24 U 67 11 PAHU 35 12 1098 U 42 10 high U 67 13 low CTL h 62 CUPS high 06 amp 6 10 06F amp 8 0000 USFS 24 9 1204 2469 1264 ASIH high CSFP BHHS H14P CSFP WOPS 0000 SHH 1941 ASAU 1941 AGAL 265
119. 7 Theory and Schematics Model 64601A TIMING CONTROL BOARD 64601 66501 i z U1 1 5 5 FEST 5 N 8 7 MOTHERBOARD R10 11 R12 B a D 9 R13 R14 R15 18 R11 C12 27 C28 C29 026 c N 033 34 R25 R26 C35 R28 C36 TP6 R27 C53 C54 R31 R32 C55 R33 56 a a lt 2 I o DATA INTENSITY lt E GLITCH DUAL THRESH GRATICULE BLANKING Buh r BLANKING c Edd HAM GLITCH 2 amp DATA SYNCHRONIZING T LATCH 5 5 TP9 lt 2 o lt 2 DOT LINE CHARACTER 5 POSITION FORMAT SEGMENTS LINE ROM COUNTER C83 R35 HORIZ amp VERT BLANKING VIDEO ENABLE C93 CTL 8 38 P O TIMING ANALYSIS CONTROL BOARD DISPLAY ADDRESSING 64601 66501 25MHZ DIV 2 9 H 12 5 MHZ L 12 5MHZ 1 G d 9 oO HORIZONTAL SYNCHRONIZING H 12 5MHZ ss 9 1 12 5 27 9
120. 7466 low UZEO SF AS C3A 036 CTOTLZ 0001 U 90 15 U 91 01 U U 91 3 U 91 4 high 8309 8984H 947H FOSS TOTLZ 0207 U 1 0000 CTOTLZ 0002 U vie 6 91 7 high F036 CTOTLZ 0001 9 0 91 9 U 91 10 LU 91 11 U 91 12 0 91 13 U 91 14 91 15 high high high Foss F036 high 036 edge edge ECL 7 7 ae 2 5 2 7 2 9 7 12 2 13 2 10 10 10 10 10 10 10 9 10 10 10 11 10 12 10 13 10 14 10 15 11 1 11 1 1 m 11 11 6 11 7 11 9 11 10 11 12 11 13 gt Who M OO LA b DP DO KH P Gi fa high 49 7 89141 4OP 89141 49P7 89141 ADP 89H1 49p 89H1 89H1 high 64PS IFS 4U8C 141P 64PS LFS 0000 53 63P 3 CPA high AUP 9H7U AAC 4 7SUF PHY LU 0000 57 OP PH C577 i H P Of fb LA p 35 4 3 3 36 6 36 7 35 9 36 12 36 13 36 14 36 18 36 17 36 18 36 19 36 20 36 24 37 1 37 43 2043 high BHSH 4H6C low low CS77 low Uv FO SP OH 0000 2045 high low high high SAUP law 9H7 U high low C9 H3 79P 5 PSPS 04000 high U4C8 348P F036 high COHS SHH 4H6C uaca 0000 9FF8 high lou 4 0000 37U6 0000 high 0000 low high high 746 0000 Performance Tests and Troubleshooting Model 64601A Ll u
121. 8 The trigger enable circuit receives the qualified A B or B Latched signals from the term generators The trigger enable circuit can combine these signals into a pattern trigger HE PATT or it can form a trigger from external commands via the IMB 8 39 The glitch chip and the encoders on the acquisition board are between the probe and memory Before a new run they contain old data from the last run The trigger enable counter U38 is programmed to hold off a trigger for several clocks until the old data has been flushed from the system The trigger enable counter also allows a certain amount of pre trigger information to be viewed even in start trace modes Since the trigger enable counter and the window counter 036 are not fast enough to be clocked at the sample rate they are clocked by the window clock U40 which is one fourth the rate 8 40 trigger enable circuit may drive and be driven by the IMB The timing analyzer can enable or be enabled by other analyzers The trigger TR trigger enable TE or master enable ME lines from the Inter Module Bus may all be used to enable the timing analyzer The timing analyzer may also itself drive the TR TE and ME lines 8 41 The trigger enable circuit also has a Post Qualify Mode When the HE RESTARTEN restart enable line is high the IMB TE line acts as a restart line causing the timing analyzer to reset itself at the command of a second analyzer and look for ano
122. 8 PARTS THIS SCHEMATIC HE LTRIGB 88 6 2 HE AND DFE CONNECT CAPACITORS SELECTION 4 5 R TO GROUND NC P C48 50 53 58 L LOADUR 11 m 1 pun 35 ges je 20NS SONS 100NS NC R1 3 27 33 U44 2 15 2 ud 3 EM s e C54 U16 26 30 33 41 45 47A 68 72 RESISTOR PACKS Cs hes pas V mere mi a eeu ee cas noe ce 0 0 205 sus 1005 POWER SUPPLY ae as 045 E CONFIGURATION ET on y PUR 19 2005 5008 10005 9 C58 4UF 5 2 5 20 1 08 15 a 20005 50005 1MS 017 43 67 74 ol SE 0 A34 1 3K SNS 103 v i Ri 4K C57 A i EX U44 HIGHS CONNECT 4 5 80 500 5 amp 8K s MUST REMAIN 37 1013 SCHMITT ua 2 7 R33 432 TRIGGER 0 8 CHANNEL DURATION 9 RR sss RESISTOR PAKS 4 ADJUSTMENTS R1 3 DN 7 88 01 5 HA U26 33 41 474 16 15 14 13 12 11 10 9 12345678 El HE BTRANSIT RESISTOR PAK U18 UNCONNECTED PINS 92 2 44 LE PDUR gt B U18 _ NONE U26 _ 456 2 43 HE BTRANSIT U33 8 10 13 15 U41 3 5 R1 03 4 968 4 10 6 072 8 10 429 1 1 2 3 4 5 6 030 _ 72 HE BLATCHA 5 U45 wd Figure 8 13 Service Sheet 5 Term Generator B CTL 8 33 CHANGE 1 TIMING CONTROL BOARD 64601 66501 2705 1
123. 800 SOUTHERN USA Hewlett Packard Co Box 105005 450 Interstate N Parkway ATLANTA GA 30339 Tel 404 955 1500 WESTERN USA Hewlett Packard Co 3939 Lankershim Blvd LOS ANGELES CA 91604 Tel 213 877 1282 OTHER INTERNATIONAL AREAS Hewlett Packard Co Intercontinental Headquarters 3495 Deer Creek Road PALO ALTO CA 94304 Tel 415 857 1501 Telex 034 8300 Cable HEWPACK March 1983 5952 6900 HP distributors are printed in italics 64601 90904 1982 CA Replaces 64601 90901 February 1982 PRINTED U S A UPDATED DECEMBER 1983
124. 9 5 741 5259 STATUS 9 Y duy Gs HE STOP ADDRESS DECODER 091 1820 1216 8 741 5138 DMUX 1 U101 1820 0683 SN74S04N EN2 gt en HE HRCLK U85 SB 3 6 7 vi 1 00 zs 4 8 1 043 5 ou EE tre Lee EB E 1 03 2 aus LE PVCLK LE PVCLK 4 PARTS ON THIS SCHEMATIC ECL TTL 11 ey 1 04 E9 D F po v 0 05 7 15 7 086 4 L STARTADR 8 16 4 14 H L LO n Pj 3 13 A 8 4 5 C1 3 4 11 13 17 24 26 28 30 31 33 STATUS j s a 9 37 45 47 51 52 59 82 84 96 7 0 i 9 L MODEN 9 7 RS i E CONTROL LATCH 10 peer ADDRESSABL 0 ec 514 087 RESISTOR PACK TC 11 ES 12 2 Eu Loo _ i H DMUX 7 0 HE TCA ECL GLITCH 4 2 ad HE RUN BLANKING 6 3 7 5 CURSOR 10 14 5 4 POWER SUPPLY ro TS 4 13125 CONFIGURATION 42 j 1 05 2 LE RUN OE 5 7 Qua lets 8 220 20 16 8 8 00 4 H TRIGOUTEN 6 12 H 45 45 2 10 08 10 ECL ss 6 U85 U76 90 91 9 8 10 5 L PR 10 sc 9 45 Y 10 19 18 10 nm Pu 8 8 2D 8 L RUN 11 13 Ow 10 5R 10 BA PONENS CR o s 8 30 7 var 8 0860 14 10 38 10 g sg 6 9 40 9 10 48 10 BR DATVER TU z V L ENHANMEM 110 i 3 a 64 9 8 60 4 14 9 110 58 10 BR L DATAMEM g i 9 8 70 12 NT 5 5 048 4 10 78 10
125. A Tables for these signals are given on the service sheets for the term generators 4 and 5 XE TRIG1 and XE TRIG2 from the acquisition boards may be programmed to be either high true low true at the output of the glitch chip These signals are programmed low for entering transitions For 11 other situations they are high true b LE PDUR gt A pattern duration greater than A specifies is low or true only for greater than durations c HE TRANSITA is high or true only when transitions are specified 8 36 In the B term generator there is latched B circuit which allows a B trigger to be latched Then if an A trigger occurs afterwards HE LTRIGB will be true out of the B term generator The latched B trigger is mutually exclu sive with the normal B trigger signal HE TRIGB CTL 8 9 Theory and Schematics INTER MODULE BUS IMB SAMPLE CLOCK 2 CTL 8 10 TRIGGER ENABLE CIRCUIT HE TR LE TE IMB INTERFACE HE ME U3 5 19 21 67 74 WNDWCLK TRIGGER ENABLE COUNTER Model 64601A 130 BIT HOLDING REG XE PVTRIG HE ENTRIG HE MASKTE TERM GENERATORS B HE LTRIGB TRIGGER ENABLE A SELECT MODE 1 SINGLE 2 SINGLE PE PATT 3 BOTH PATTERN 4 SEQUENTIAL AeBLATCHED TRIGGER Figure 8 6 Trigger Enable Circuit Block Diagram Theory and Schematics Model 64601A 8 37 TRIGGER ENABLE CIRCUIT Figs 8 5 8 13 8 3
126. A 3 OKLAHOMA CITY OK 73107 Tel 405 946 9499 A CH E MS Hewlett Packard Co 3840 S 103rd E Avenue Logan Building Suite 100 TULSA OK 74145 Tel 918 665 3300 A CH CS M Oregon Hewlett Packard Co 9255 S W Pioneer Court WILSONVILLE OR 97070 Tel 503 682 8000 A CH CS E MS Pennsylvania Hewlett Packard Co 1021 8th Avenue KING OF PRUSSIA PA 19046 Tel 215 265 7000 A CH CM CS E MP Hewlett Packard Co 111 Zeta Drive PITTSBURGH PA 15238 Tel 412 782 0400 A CH CS E MP South Carolina Hewlett Packard Co 0 Box 21708 29221 Brookside Park Suite 122 1 Harbison Way COLUMBIA SC 29210 Tel 803 732 0400 CH E MS Tennessee Hewlett Packard Co 3070 Directors Row MEMPHIS TN 38131 Tel 901 346 8370 A CH MS Hewlett Packard Co Suite C 110 4171 North Mesa EL PASO TX 79902 Tel 915 533 3555 CH E MS Hewlett Packard Co 0 Box 42816 77042 10535 Harwin Street HOUSTON TX 77036 Tel 713 776 6400 A CH CM CS E MP Hewlett Packard Co 0 Box 1270 930 Campbell Rd RICHARDSON TX 75080 Tel 214 231 6101 A CH CM CS E MP Hewlett Packard Co 0 Box 32993 78216 1020 Central Parkway South SAN ANTONIO TX 78232 Tel 512 494 9336 CH CS E MS Utah Hewlett Packard Co Box 26626 84126 3530 W 2100 South SALT LAKE CITY UT 84119 Tel 801 974 1700 A CH CS E MS Virginia Hewlett Packard Co 0 Box 9669 23228 RICHMOND Va 23228 4305 Cox Road G
127. ANDed or ORed with a trigger from a second aquisition board 2 It can be armed by signals from the IMB 3 It can be delayed It can be qualified as to pattern duration and transition The final qualified trigger HE TRIG DLY that starts a trace is called tracepoint 8 45 The tracepoint selector receives the qualified pattern trigger HE PATT from the Trigger Enable Circuit The tracepoint selector can add delay to the timing trigger or it can ignore the timing trigger entirely and trigger the analyzer via the IMB 8 46 The tracepoint selector is also programmed by the 130 bit holding register to determine the amount of window between tracepoint in memory and the end of new acquisition That is the tracepoint selector generates HE STOP which stops the sample clock ending the trace 8 47 The tracepoint selector allows the mainframe to determine the exact position of tracepoint in memory This is necessary because the acquisition RAM is loaded from eight bit serial to parallel shift registers Thus the memory write pulses and the memory address counter clocks occur at one eighth sample frequency Without additional circuitry in the tracepoint selector the position of the trigger in memory could be known only to an eight bit group accuracy CTL 8 13 RI 9 8 AeTdstq 8 8 25 MHz MOTHERBOARD
128. APACITOR FXD 01UF 80 20 100 DC CAPACITOR FXD 01UF 80 20 100VDC CER CAPACITOR FXD 01UF 4 207 100UDC CER 25480 28480 28480 28480 28480 0160 2055 0100 2055 0150 2055 0160 2055 0140 3879 28480 52763 0160 3879 0121 0061 CAPACITOR FXD 01UF 20 100UDC CER TRMR CER S 5 18PF 3509 0160 3879 304322 S 5 718PF NPO CTL 6 4 CHANGE 1 0160 4383 0160 3874 0160 3874 0160 2055 0180 5879 0160 2055 0160 2055 0150 2055 0150 2055 0160 2055 0140 0199 0150 5415 0150 5243 0160 5342 8150 5874 0160 5341 0160 2055 0150 2055 0160 2055 0160 3875 0150 2055 0160 4813 0150 2055 0160 2055 0160 4492 0100 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0160 2055 0150 2055 0160 2055 0150 2055 0160 2055 0180 2055 0150 2055 0150 4813 0160 3875 0160 4492 0160 2055 0160 2055 0140 0199 0160 5415 0160 5343 0160 5342 0160 3874 0160 5341 0160 2055 0160 2055 0160 2055 0150 2055 0160 2055 0150 2055 0160 2055 0160 2055 0160 2055 0160 2055 0150 2055 0160 2055 01700 gt 9 995919 YO GO O 0 lt 099090 47099 29292922 93039092 929995902 99990 O OPO s CAPACITOR F XD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACIT R FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPA
129. B RETURN d The screen should show display like Figure 3 Inter Module Bus Performance Verification Tue 19 Oct 1982 31 12 Slot d ID Module description 3 1001 200 MHz Timing Analyzer 64601A TIME KRoard for IMB stimulus 2 1001 200 MHz Timing Analyzer 64601A TIME IME test results 1 Error RECEIVE 000000 DCLK LME LTE HTR RST HLDO DRIVE 0000 RNCA LME L TE HTR IMB stimulus board limitations 1 Not tested DRIVE 100000 CDCLE LME LTE HTR LTE RECEIVE 1000 CRNC4 LME LTE HTR TESTED 0 FAILED Figure h 17 Inter Module Bus Performance Verification 4 77 For this test there must be another analyzer either state timing present in the mainframe One analyzer is the test board and the other is the stimulus board 4 8 The test checks each of the IMB lines that are used commonly by the stimulus and test boards In figure 4 3 slot 3 contains the test board and slot T contains the stimulus board 4 79 All the test board lines that can be driven or received listed in the display under the heading IMB test results When six 0 5 000000 indicated for RECEIVE and four O s indicated for DRIVE all IMB lines pass satisfactorily CTL 4 37 Performance Tests and Troubleshooting Model 64601A 4 80 When the particular stimulus board used the test is unable to drive or receive certain lines those lines are indicated under the heading stimulus
130. CITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD ITOR FXD OR FXD CAPACITOR FXD CAPACTTOR FXD CAPAC TTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPAC LTOR FXD CAPACITOR FXD CAPACITOR FXD 6 8PF SPF 200UDC 10 5 200UDC SPF 200UDC C 01UF 80 20 100UDC O1UF 20 100UDC CER 1UF 80 20 100UDC CER O1UF 480 204 100UDC CER 1UF 80 20 100UDC CER O1UF 80 20Z 100UDC CER O1UF 80 20 100UDC CER 240PF 5 300UDC MICA 3600PF 50VDC 04UF SOVDC 4UF SOUDC GPF 200UDC CER 4UF S0UDC 80 20 100UDC CER O 1UF 80 20 100UDC CER O1UF 80 20 100UDC SPF 200UDC C O1UF 80 20 100UDC CER 180PF 5 100VDC CER OTUF 80 20 100UDC CER 010 80 20 100UDC CER 18PF 5 200UDC CER 0 30 OTUF 80 20 100UDC CER 01 80 20 100UDC CER O1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC 01UF 80 20 100UDC O1UF 80 20 100UDC
131. CS 73 6 8830 U 73 7 PPI U 73 9 0000 73 10 824F U 73 11 1PUP U 73 12 2570 u 73 13 1PUP U 73 14 2570 U 73 15 P71U U 86 2 U 85 3 0000 U 86 12 FCSF 86 14 FCIF CTL 4 74 Performance Tests and Troubleshooting Model 64601A 6460168 Timing Control Board TRANSITION TRIGGER A 12 NORM MODE UH FC27 DATA THRESHOLD HIGH ttl amp ecl CLOCK THRESHOLD tti ST SP QL THRESHOLD ttl Location af location of Location of ST SP START QUAL STOP tp CLOCK tp 11 tp 12 neg edge 12 pos edge pos edge Location of GROUND gnd TTL 49 4 71 4 49 3242 U 49 12 low U 47 13 916 U 82 1 FCA U B 2 Uu 85 3 CUBA 4 5 4 3242 85 5 U 88 6 2244 85 7 BAPE U 85 9 2H80 U 85 12 0 04 U 85 14 HAUD U 85 15 2 U 89 16 1632 U 85 17 low U 35 18 5435 U 88 19 FCA U 86 85 SAUF 85 7 FCA U 36 10 324F U 86 11 U 90 1 4299 U 90 2 FOHA U 90 3 4524 U 90 4 low 0 90 90 6 90 13 FAA U 50 14 FCA CTGTLZz0001 U 90 18 high U Fie 1 Anco U 91 2 U 91 3 0007 U 91 4 FCA TOTLZz0207 91 0000 CTOTLZz0002 91 6 high 91 7 FCA 200019 U 91 9 high 91 10 high U 91 114 high 91 12 FC27 U 91 13 2 U 91 14 high 0 91 18 FCA u U U 9 u 9 Uu U U U Uu U LU 0 U u U 1 P285 8403 7 7 1 high 7 3242 7 3 9635 2 4 3242
132. ERVRL CB THAN INTER DN TR V Oh OS CI p QE Ra mH m a 0 FOLLOWED BY A STATUS Awaiting command run 610 6 test 1 repeated Figure 4 25 Press repeated CTL 4 44 Performance Tests and Troubleshooting Model 64601A STATUS Awaiting command __ run siot 6 test 1 repeated Ail Tl Figure 4 26 Press RETURN CTL 4 45 Performance Tests and Troubleshooting Model 64601A 90 SIGNATURE ANALYSIS 4 91 The following 15 signature loops correspond to the previously given performance verification tests That is if a PV test fails the signature loop corresponding to that test For example if one of the test steps for TEST 1 SERIAL PROGRAMMING shows a 1 instead of a 0 in the bracket look at the signatures for LOOP 1 In order to take the Signatures run TEST 1 repeatedly using the procedure illustrated by the above figures 4 18 to 4 26 CTL 4 46 Performance Tests and Troubleshooting Model 64601A 64601A Timing Control Board SERIAL PROGRAMMING i NORM MODE DATA THRESHOLD HIGH ttl amp CLOCK THRESHOLD ttj ST SP QL THRESHOLD ttl Legation of ST SP START tp te neg edge Location of QUAL STOP tp 12 pos edge Location of CLOCK tp 11 neg edge Location of GROUND TTL ECL U 49 4 418 89 1 BHIS U 1 1 0000 U 49 5 dou TOTLZ 0781 CTOTLZ 0520 U 49 12 Low U 89 2 low u 1 3 0051 49 13 HSA U 9 3
133. GHT HEWLETT PACKARD COMPANY 1982 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A ALL RIGHTS RESERVED Manual Part Number 64601 90904 Microfiche Part Number 64601 90804 PRINTED OCTOBER 1982 UPDATED DECEMBER 1983 SAFETY SUMMARY The following general safety precautions must be observed during all phases of operation service and repair of this instrument Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the instrument Hewlett Packard Company assumes no liability for the customer s failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the instrument chassis and cabinet must be connected to an electrical ground The instrument is equipped with a three conductor ac power cable The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the instrument in the presence of flammable gases or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCU
134. HRESHOLD tti ST SP QL THRESHOLD ttl Location of ST SP START tp 12 Location of QUAL STOP tp 12 Location of CLOCK tp 11 Location of GROUND gnd VH 6044 neg edge edge pos edge TTL ECL 0 49 4 179F 10 1 high U 49 PAPC U 10 2 2540 49 12 low U 10 3 CH21 U 49 13 6F62 U 10 4 95290 U 64 4 low 10 8474 64 056 U 10 3542 U 64 12 3445 U 10 7 CH21 64 13 low U 10 9 0000 U 85 1 660641 TOTLZ 0130 gt CTOTLZz0004 U 10 10 SP90 U 85 2 179F U 10 11 U 85 3 HACU U 10 12 98 85 4 PAPC LU 10 13 H830 U 85 10 14 rcog U 85 6 low 0 10 15 6eSFF U 85 7 U ii 1 high 85 8 law U 11 2 0934 85 9 DPA U 11 3 0494 U 85 11 346 U 11 4 1535 35 12 U 11 1268 85 13 2056 11 6 0934 U 85 14 32 11 7 0494 85 15 6390 U 11 9 0000 85 15 1278 CTOTLZ 0130 89 17 low U 11 10 1535 U 35 18 0506 U 11 11 26462 U 88 19 6040 U 11 12 Ceci CTOTLZ 0004 U 11 13 2662 U 11 14 Ceci U 11 15 5958 U 13 1 high U 13 2 2607 U 13 3 46658 U 13 4 1533 13 low U 13 6 Low u13 7 2662 13 9 lou CTL h 80 U 13 10 low U 13 11 U 13 12 2799 U 13 13 5958 U 13 14 272851 13 15 low U 15 1 high U 15 2 U 15 3 656 U 15 4 1F53 15 5 5958 U 15 6 15 7 HASS U 15 9 0000 CTOTLZ 0130 U 19 10 1F53 U 19 11 SPH1 15 12 08 8 U 18 12 U 15 14 15 15 8474 17 1
135. Hewlett Packard Sverige AB Frotallisgatan 30 5 42132 VASTRA FROLUNDA Tel 031 49 09 50 Telex 854 17886 via Sp nga office CH E P SWITZERLAND Hewlett Packard Schweiz AG Clarastrasse 12 CH 4058 BASLE Tel 61 33 59 20 Hewlett Packard Schweiz AG 7 rue du Bois du Lan Case Postale 365 CH 1217 MEYRIN 1 Tel 0041 22 83 11 11 Telex 27333 HPAG CH CH CM CS Hewlett Packard Schweiz AG Allmend 2 CH 8967 WIDEN Tel 0041 57312111 Telex 53933 hpag ch Cable HPAG CH A CH CM CS E MS P SYRIA General Electronic Inc Nuri Basha Box 5781 DAMASCUS Tel 33 24 87 Telex 11216 ITIKAL SY Cable ELECTROBOR DAMASCUS E Middle East Electronics Place Azm 2308 DAMASCUS Tel 334592 Telex 11304 SATACO SY MP TAIWAN Hewlett Packard Far East Ltd Kaohsiung Office 2 68 2 Chung Cheng 3rd Road KAOHSIUNG Tel 241 2318 261 3253 CH CS E Hewlett Packard Far East Ltd Taiwan Branch 5th Floor 205 Tun Hwa North Road TAIPEI Tel 02 712 0404 Cable HEWPACK Taipei A CH CM CS E M P Ing Lih Trading Co 3rd Floor 7 Jen Ai Road Sec 2 TAIPEI 100 Tel 02 3948191 Cable INGLIH TAIPEI A THAILAND Unimesa 30 Patpong Ave Suriwong BANGKOK 5 Tel 235 5727 Telex 84439 Simonco TH Cable UNIMESA Bangkok A CH CS E M Bangkok Business Equipment Ltd 5 5 6 Dejo Road BANGKOK Tel 234 8670 234 8671 Telex 87669 BEQUIPT TH Cable BUSIQUIPT Bangkok TR
136. IG C IC GATE TTL LS NAND QUAD 2 INP 2 INP EDGE TRIG INP 9 TC VEDR TTL LS 3 TO 8 LINE 3 IC FF TTL LS IC FF TTL LS D TYPE POS IC CNTR TTL BIN SYNCHRO POS IC CNTR TTL 5 BIN SYNCHRO POS IC CNTR TTL LS BIN SYNCHRO POS GATE TTL NAND QUAD 2 1 FF TTL S D TYPE POS EDG IC GATE AND TPL 3 IN TRIG COM RIG COM EDGE TRIG EDG EDGE FF TTL 8 D TYPE POS EDGE TRIG IC INU TTL S HEX 1 INP SOCKET 24 CONT 24 CONT 24 CUNT LTT 16 CONT 14 CONT SOCKET IC 16 CONT 16 CONT 300 16 CONT SOCKET IC 16 CONT 18 CONT DXP SLDR 54013 84013 54013 01295 0129 01295 01295 04713 01121 04713 04713 01121 04713 01121 04713 01121 04713 28430 01295 01295 01295 01295 01295 04713 01121 01295 01298 28480 01295 01295 01295 02263 07263 01295 01295 01295 01295 01295 01295 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 28480 See introduction to this section for ordering information Indicates factory selected value Model 64601A Replaceable Parts List Con t Mfr Part Number 1858 0054 2104104 CA3045 DS8831N MC101251 01171 MC10131P F10016DC 2106201 MC10102P MC10121P SN74LS174N HM6147P 3 HM6147P 3 HM6147P 3 SN748374N SN74S112N SN748157N SN748574N MC10129L 2104201 MC101301 MC10102P 2104201 MC 10104P 2104331
137. INIDAD amp TOBAGO Caribbean Telecoms Ltd 50 A Jerningham Avenue 0 Box 732 PORT OF SPAIN Tel 62 442 13 62 44214 Telex 235 272 HUGCO WG CMEMP TUNISIA Tunisie Electronique 31 Avenue de la Liberte TUNIS Tel 280 144 EP Corema T ter Av de Carthage TUNIS Tel 253 821 Telex 12319 CABAM TN M TURKEY Teknim Company Ltd Caddesi No 7 Kavaklidere ANKARA Tel 275800 Telex 42155 TKNM TR E Medina Eldem Sokak 4 1 6 Yuksel Caddesi ANKARA Tel 175 622 M UNITED ARAB EMIRATES Emitac Ltd 0 Box 1641 SHARJAH Tel 354121 354123 Telex 68136 Emitac Sh CH CSEMP UNITED KINGDOM GREAT BRITAIN Hewlett Packard Ltd Trafalgar House Navigation Road ALTRINCHAM Chesire WA14 1NU Tel 061 928 6422 Telex 668068 A CH CS E M Hewlett Packard Ltd Oakfield House Oakfield Grove Clifton BRISTOL BS8 2BN Avon Tel 027 38606 Telex 444302 CH M P GREAT BRITAIN Cont d Hewlett Packard Ltd Fourier House 257 263 High Street LONDON COLNEY Herts AL2 1HA St Albans Tel 0727 24400 Telex 1 89527 16 CH CS E Hewlett Packard Ltd Quadrangle 106 118 Station Road REDHILL Surrey Tel 0737 68655 Telex 947234 CH CS E Hewlett Packard Ltd Avon House 435 Stratford Road SHIRLEY Solihull West Midlands B90 4BL Tel 021 745 8800 Telex 339105 CH Hewlett Packard Ltd West End House 41 High Street West End SOUTHAMPTON Hampshire 503 300 Tel 703 886767
138. ISVIN S IVNOIS 3 18VN3 H STOP END OF TRACE H TRIG DLY TRACEPOINT X TRIG 1 TERM GENERATORS TRIGGER ENABLE TRACEPOINT HE PATT SELECTION X TRIG 2 FROM ACQUISITION BOARDS RUN HALT QHVOSH3HLOW snd DNIWIL GYvVOgysHLOW RESET 00 011 DISPLAY HE GMC SYNC VIDEO iit aw LE ME CTL 8 26 1 P Q TIMING ANALYSIS CONTROL BOARD 130 BIT HOLDING REGISTER 64701 66501 3 25 ul Fl wl z w Fl l ul gt e x wl c co a of lt lt e amp N F uj X wh u MD 23 M E 1 e 4 1 4 4 9 FF Spel U73 2 yan dn E mf vja alaja aA aAA 6 o LE ENPVTRIG 2 6 LE ENDRIVTE 8 LE ENDRIVME 6 LE ENDRIVTR 8 LE ENTRIGA e LE ENTRIGB 8 6 1 oa J 6 HE RESET LE ENTRIG1A LE ENTRIG4A LE ENTRIG3A HE ATRANSIT LE PDUR gt A LE ENTRIG2A 1 LE ENTRIG1B LE ENTRIG4B
139. ITS Operating personnel must not remove instrument covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification of the instrument Return the instrument to a Hewlett Packard Sales and Service Office for service and repair to ensure that safety features are maintained DANGEROUS PROCEDURE WARNINGS Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed WARNING Dangerous voltages capable of causing death are present in this instrument Use extreme caution when handling testing and adjusting SS 1 1 76 Model 64601A Table of Contents TABLE OF CONTENTS Section Page I GENERAL INFORMATION Qu E 1 1 Introduction sti o atu due ana XE 2 1 1 4 Instruments Covered by this
140. LEN ALLEN Va 23060 Tel 804 747 7750 A CH CS E MS Washington Hewlett Packard Co 15815 5 37th Street BELLEVUE WA 98006 Tel 206 643 4000 A CH CM CS E MP Hewlett Packard Co Suite A 708 North Argonne Road SPOKANE WA 99206 Tel 509 922 7000 CH CS West Virginia Hewlett Packard Co 0 Box 4297 4604 MacCorkle Ave S E CHARLESTON WV 25304 Tel 304 925 0492 Wisconsin Hewlett Packard Co 150 S Sunny Slope Road BROOKFIELD WI 53005 Tel 414 784 8800 A CH CS E MP SALES amp SUPPORT OFFICES Arranged alphabetically by country URUGUAY Pablo Ferrando S A C e Avenida Italia 2877 Casilla de Correo 370 MONTEVIDEO Tel 80 2586 Telex Public Booth 901 A CM E M VENEZUELA Hewlett Packard de Venezuela C A 3A Transversal Los Ruices Norte Edificio Segre Apartado 50933 CARACAS 1071 Tel 239 4133 Telex 25146 HEWPACK A CH CS E MS P Hewlett Packard de Venezuela C A Calle 72 Entre 3H Y 3Y No 3H 40 Edificio Ada Evelyn Local B Apartado 2646 MARACAIBO Estado Zulia Tel 061 80 304 Hewlett Packard de Venezuela Calle Vargas Rondon Edificio Seguros Carabobo Piso 10 VALENCIA Tel 041 51 385 CH CS P Colimodio S A Este 2 Sur 21 148 Apartado 1053 CARACAS 1010 Tel 571 3511 Telex 21529 COLMODIO M ZIMBABWE Field Technical Sales 45 Kelvin Road North P B 3458 SALISBURY Tel 705 231 Telex 4 122 RH GEMP HEADQUARTERS OFFICES
141. LULLE LL LL ULL LLL CREFF LLL LULL LA TT EF LLL LPL UL LPL EPUA LETT ETLE LeeLee LLLP LE EIF ELT A Ar EEE A A EEA TTAF L Le Press PAGE to CONTINUE Figure 5 15 This is the 16 channel version of figure 4 10 It is an alternating pattern of data characters high low high low transitions and low high transitions The following eight patterns are each shifted by one dot There are no enhancement characters CTL 4 35 Performance Tests and Troubleshooting Model 64601A Figure 4 16 This is an alternating pattern of highs small transitions middles and lows The pattern is shifted by one dot in the following eight displays Characters Exercised Data Characters High alternate with dual threshold and low characters Low alternate with dual threshold and high characters Enhancement Characters Graticule repeated twice blanked twice repeated twice etc Cursor continuous Intensity cursor is intensified every other two dots and middles are intensified Dual Threshold alternate with highs and lows CTL 4 36 Performance Tests and Troubleshooting Model 64601A 4 75 INTER MODULE BUS PERFORMANCE VERIFICATION Supplementary PV test 4 76 This is a supplementary PV test To access this test press the following keys a Press opt test RETURN b Type the timing control board slot number RETURN c Press test IM
142. NERATOR TRANSITION ENTER LEAVE PATTERN DURATION U28 31 32 34 B TERM GENERATOR SAME AS A FROM 130 BIT REGISTER vV unad 31l LISNVYLV SH DURATION DECODER PATTERN 1 ENTER 2 LEAVE 3 LESS THAN 4 GREATER THAN U27 42 tt HE TRIG A HE TRIG AeLATCH B HE LTRIG B Theory and Schematics Model 64601A TO TRIGGER ENABLE LE PDUR gt XE TRIG HE TRANSIT H X L H L H H H H L H H CTL 8 32 PATTERN MUST BE GREATER THAN SPECIFIED LESS THAN SPECIFIED TRANSITION LEAVING TRANSITION ENTERING Theory and Schematics Model 64601A ICs ON THIS SCHEMATIC P O TIMING ANALYSIS CONTROL BOARD 64601 66501 TERM GENERATOR B n 4 OL E Ref Des HP Part No Mfr Part No XE TRIG3 017 1820 0815 10121 LE ENTRIG3B TRIGGER 34 1820 1320 10216 SELECTOR U AND OR U35 42 1820 1946 MC10117L TRIGGER ars 8 043 67 1820 0802 MC10102P lt X U44 1820 1730 SN74LS273N 4 2 8 u d 6 NE 10 i A 046 1858 0054 c e QG 2 m N q x 15 aly AX 58 6228 9225 SEX U47 1821 0002 CA3054 288 c50 ENTER LEAVE U74 1820 0817 MC10131P 4 18 m o 2 D TRANSITION NEEN Y DURATION TRANSITION R30 200 EN E 3 p D SELECTOR 4 one E B 3 25 i 908 HE TRIGB gt 6 DURATION PROGRAMMING 05
143. NSIT is true and LE PDUR gt B is false Under the same conditions the analyzer will trigger on a transition into or entering the pattern when the acquisition board trigger XE TRIG is low true The in the mnemonic indicates this signal can be programmed either low true or high true 4 57 Test Conditions a The delay counter U37 trigger enable counter U38 and window counter U36 are set to zero b HE BTRANSIT is high We want to trigger on a transition c LE PDUR B is high We are triggering transition not an interval d XE TRIG1 from the acq board is programmed low true for this test 4 58 Test Steps Description of software execution 1 During RESET the transition circuits are programmed for transition triggering the DAC thresholds are set up to simulate a pattern and the glitch chip is programmed to recognize that pattern During RUN H TRIG DLY should be false because there has been no transition 2 pattern on the input is changed This is a leaving transition H TRIG DLY should remain false because XE TRIG1 is low true 3 Setting the thresholds back to their original value is in effect an entering transition H TRIG DLY should go true 4 15 Performance Tests and Troubleshooting Model 64601A 4 59 TEST 9 DISPLAY DRIVER 00000000 test steps 12345678 The Display RAMs are loaded with eight different patterns and read out This tests the programming the mode
144. NSTSTOR ARRAY 16 PIN PLSTC NETUORK RES TRANSISTOR ARRAY 14 PIN C IC DRUR TTL LI DRUR QUAD IC XLTR ECL ECL IC GATE ECL DUAL IC FF ECL D M S DUAL O TTL QUAD 2 Replaceable Parts DIP 10 SIP100 0K OHM X 9 ER DIP CNTR ECL BIN SYNCHRO POS EDGE TRIG NETUORK RES 10 57 200 0 OHM X GATE ECL NOR QUAD 2 INP GATE ECL AND OR 9 FF TTL LS D TYPE POUS EDGE SITE CMOS 4096 4K STAT RAM CMOS 4096 AK STAT RAM CMOS 4096 4K STAT RAM FF TTL S D TYPE OCTL FF TTL 5 J K NEG IC MUXR DATA S LINE QUAD FF TTL D TYPE POS GE TRIG IC XLTR ECL ECL TO TTL QUAD 2 NETUORK RES 10 SIP200 0 DHM X INP 9 LOCH ECL D TYPE POS EDGE TRIG DUA IC GATE 1 NOR QUAD 2 INP NETWORK RES 10 SIP200 0 OHM X IC GATE ECL AND QUAD 2 INP NETWORK RES 10 S1P330 0 OHM X FF ECL D M S POS EDGE TRIG RK RES 10 81P330 0 OHM X IC FF ECL D M S POS ED TRIG IC FF ECL D M S DUAL NETWORK RES 10 GIP10 0K OHM X IC DRVR TTL LS BUS DRUR HEX 1 IC TTL L 1024 1K STAT RAM 9 9 COM CLOCK 9 COM CLOCK 9 INP 75 NS CNTR TTL LS BIN SYNCHRO POS EDGE IC 7611A S FORMAT ROM PROGRAMMED 5 FF TTL D TYPE POSG ED GATE TTL AND D R INV DUAL FF TTL 8 D TYPE POS TTL LS LINE DRYR DOCTI IC XLTR EC 1 ECL QUAD 2 NETWORK 8 IP330 0 OHM X IC GATE TTL S NOR QUAD 2 INP GATE TTL NAND QUAD 2 INP IC SN74LS259 R
145. OHSS U 24 1 high U 74 2 B CP LU 74 4 8PA2 0 74 HEBE 74 10 5949 74 11 6605 74 12 low 74 13 8P42 74 145 high Performance Tests and Troubleshooting Model 64601A CTL 4 83 Performance Tests and Troubleshooting Model 64601A 646016 Timing Control Board DISPLAY TEST ST PATTERN QUAL MODE Qual high DATA THRESHOLD 111 CLOCK THRESHOLD ttt ST SP QL THRESHOLD ttl ST SP START DUAL S S TOP CLOCK tp 8 GROUND gnd Location of Location of Location of Location of U 56 1 high U X6 Low U S6 high u S6 high S6 high 56 10 high 36 12 low U 56 18 high U S7 1 P816 U 57 uU 97 3 4 DC UH PO U S7 UPF amp Lp 57 87779 S7 amp BAPU U S7 7 U 57 8 high U 57 18 low uU 87 12 4CP2 U 57 15 Hues 57 14 521 U 527 19 Fear U 87 15 SAFC U 57 17 5632 U S8 J P816 U SE 2 S80H u SE 3 12059 uU S8 4 UPFS LU SE 5 8779 U 58 6 58 7 6037 U 58 8 high U 58 10 low 58 12 4CP2 U 58 18 HURA U 58 14 4521 U 58 15 9856 CTL 4 84 10 IGP or 1 58 16 58 17 en i zn o O OLA DS Gi PS 60 60 60 8 9 60 11 SO aA uU 81 13 SAFC 5632 PBLS SBOH 12 9 UPES 8779 2893 high low 4CP2 HUZA 4521 9857 SAFC S632 law PRLS HO2F 6037 CIC 9549 LAPS 9849 4AA4 0000 CTQTLZz12519 u 60 12 60 13 60 14 60 15 60
146. P Melbourne Victoria Office Hewlett Packard Australia Ltd 31 41 Joseph Street BLACKBURN Victoria 3130 Tel 890 6351 Telex 31 024 Cable HEWPARD Melbourne A CH CM CS E MS P Perth Western Australia Office Hewlett Packard Australia Ltd 261 Stirling Highway CLAREMONT W A 6010 Tel 383 2188 Telex 93859 Cable HEWPARD Perth A CH CM E MS P Sydney New South Wales Office Hewlett Packard Australia Ltd 17 23 Talavera Road P 0 Box 308 NORTH RYDE N S W 2113 Tel 887 1611 Telex 21561 Cable HEWPARD Sydney A CH CM CS E MS P AUSTRIA Hewlett Packard Ges m b h Grottenhofstrasse 94 Verkaufsburo Graz A 8052 GRAZ Tel 291 5 66 Telex 32375 CH E Hewlett Packard Ges m b h Lieblgasse 1 0 Box 72 1222 VIENNA Tel 0222 23 65 11 0 Telex 134425 HEPA A A CH CM CS E MS P BAHRAIN Green Salon 0 Box 557 BAHRAIN Tel 255503 255950 Telex 84419 Wael Pharmacy 0 Box 648 BAHRAIN Tel 256123 Telex 8550 WAEL BN EM SALES amp SUPPORT OFFICES Arranged alphabetically by country BELGIUM Hewlett Packard Belgium S A N V Blvd de la Woluwe 100 Woluwedal B 1200 BRUSSELS Tel 02 762 32 00 Telex 23 494 paloben bru A CH CM CS E MP P BRAZIL Hewlett Packard do Brasil 1 Lida Alameda Rio Negro 750 Alphaville 06400 BARUERI SP Tel 011 421 1311 Telex 011 33872 HPBR BR Cable HEWPACK Sao Paulo A CH CM CS E M P Hewlett Packard do Brasil 1
147. Q1 De M 1HZ 100MHZ E Y1 n L1 2 cg I RUN HALT GATES o j 5 9 12 1 2 E 1HZ 100MHZ R1 8 12 18 20 22 Ores U6 20 25 41 75 RESISTOR PACKS 1HZ 100MHZ E V 6 HE RESET HE RESET T M 1HZ 100MH2 13 R21 39 SEE NOTE PERFECT SQUARE WAVE SERVICE SHEET 2 ECL POWER SUPPLY asta ONE SHOT 192 100492 A xet 7 7 CONFIGURATION RST4 gp SHAPER NC R19 39 2 HE HRCLK 14 ONE SHOT FREQUENCY 1HZ 100MHZ 22 Sg 7 1 IN Ne SELECTOR e 5 9 M 8 Nc ECL 8 4 9 staat NC HE F2 7 L 3 25 U1 5 2 ue S come NC HE F 4 47195 0 6 al NC il 5 T wid LI euh LE PVCLK 14 gio a DIV 5 5 U4 299 e E CTR OUT p 22 249 WINDOW CLOCK 3 25 SOMHZ NOT USED 4 5 10 200 3 25 DRIVES TRIGGER ENABLE 038 08 100MHZ 8 p o AND WINDOW U36 COUNTERS i 23 3 25 VHE TO Ut P O as NC as 4 0 we 10 NC 50MHZ 020 45 16 5 2 NC Eod Z 25 2 25 2 HE WNDWCLK 5 6 7 048 04 5 7 8 22 24 40 Q lt d R18 39 Figure 8 11 Service Sheet 3 Sample Clock CTL 8 29 Theory and Schematics Model 64601A a ES TERM GENERATORS IN NTROL BOARD 55 Fe FROM FROM 64601 56501 130 BIT REGISTER 130 BIT REGISTER Z N ENTERING LEAVING LESS THAN
148. R 100 1X 125W F 0 100 24546 4 1 8 0 101 4 ALRIS 0257 0416 681837 0757 0407 1638 0757 0401 RESISTOR 511 1X 125W F 0 100 24546 C4 1 8 TU0 S11R F RESISTOR 200 1 125W F T 100 24546 4 1 8 70 201 RESISTOR 100 1 1254 F 0 100 24546 4 1 8 70 101 opo 1 1 1 2 amp 1TP3 A1TPA ALTPS COAXIAL TEST POINT 28480 1250 1737 TERMINAL TEST POINT PCB 00000 ORDER BY DESCRIPTION TERMINAL TEST POINT PER 00000 ORDER TERMINAL POINT PCB 00000 ORDER BY TERMINAL TEST POINT 00000 ORDER BY DESCRIPTION ec ALTPS 0360 0535 1TP7 0360 0535 1TP8 0360 0535 1 0360 0535 1 10 0360 0535 TERMINAL TE POINT PCB 00000 ORDER BY DESCRIPTION TERMINAL TE POINT PCE 00000 ORDER BY DESC TERMINAL TE POINT PCB 00000 ORDER BY DE TERMINAL TEST POINT PCR 00000 ORDER TERMINAL POINT PCB 00000 ORDER BY DESCRIPTION oono TERMINAL ST POINT PCR 00000 ORDER DESCRIPTION TERMINAI TE POINT PCE 00000 ORDER BY DESCRIPTION A1TP11 0360 0535 ALTP12 0360 0535 oo buys wee oD IC DELAY 28480 1 84 5008 NETWORK RES 10 SIP470 0 OHM X 9 01121 2104471 IC MISC ECL 14 INP 07263 F10014PC IC MUXR DATA SEL ECL 4 TO 1 LINE DUAL 04713 MC10174P FF ECL D M S DUAL 04713 MC10231P 1U1 1964 5008 eiua 1810 0273 A1U3 1820 2359 ALU4 1820 1359 eius 1820 1225 1U6 1810 0271 8107 1820 1320 8108 1820 0920 4109 1810 0272 1U10 1820 2193 NETUORK RES 10 SIP
149. RESETS OUTPUTS ENABLE AUTO OUTPUT RESET OUTPUT RESET ONE SHOT POWER SUPPLY CONFIGURATION 5 3 25 RESISTOR PAKS U9 12 14 70 72 3 25 U1 36 38 U10 11 15 71 73 Ol ojojo UNCONNECTED PINS U9 PINS 8 9 10 U12 PINS 8 9 10 U14 PINS 5 6 10 U70 PINS 8 9 10 U72 PINS 8 10 NOTE B 26 is duplicated on both service sheet 2 and 7 Figure 8 10 Service Sheet 2 130 Bit Control Shift Register CTL 8 27 Theory and Schematics Model 64601A WINDOW CLOCK 1Hz 100MHz 25Hz 25MHz 2Hz 200MHz BNCOUT TP1 2Hz 200MHz UX 24 Yn M U4 SAMPLE CLOCK 200MHz 200 MHz BUFFER FROM 130 BIT _HE F1 4 HR bved 6dl 8S2 U84 U101 0141 692 E 1S82 952 452 52 92H lt 0 v O gue gso rly eeu c u ely I u a S Hu 82 54829 sin 9L5 TP8 Nn 5 047 079 a D o 1 9 A eo 2 EO 9 Vcu o a 57 o 8 9 M e 2 8 1 078 en xn 629 29 zo o 5 C96 o ERE M e 9 e 9 N 5 1141 989 FESP i e o
150. S amp OUTPUTS 098 Some have a common Control Block with array of elements CHIP CONTROL FUNCTION BLOCK CTR DIV 16 COMMON po iil OUTPUT DEPENDENCY NOTATION COMMON CONTROL INPUTS ARRAY 4 5 5 ELEMENTS SIGNIFICANT ieee ELEMENT 14 INPUTS gt OUTPUTS MOST SIGNIFICANT ELEMENT CONTROL BLOCK All inputs and dependency notation affect the array elements directly Common outputs are located in the control block Control blocks may be above or below the array elements ARRAY ELEMENTS All array elements are controlled by the control block as a function of the dependency notation Any array element is independent ofall other array elements Unless indicated the least significant element is always closest to the control block The array elements are arranged by binary weight The weightsare indicated by powers of 2 shown in D LS 08 09 82 1 Table 8 2 Logic Symbols Cont d INPUTS Inputs are located on the left side of the symbol and are affected by their dependency notation Common control inputs are located in the control block and control the inputs outputs to the array elements according to the dependency notation Inputs to the array elements are located with the corresponding array element with the least significant element closest to the control block OUTPUTS Outputs are located on the right side of the symbol and are effected by their dependency notation C
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152. TCO 1 and H TC2 should all be low 4 Prior to reset the acquisition board RAM counters were programmed to FFFFH the counters should not be 0000H before reset 5 RAM counters should be OOOOH after reset 6 7 If there is second acquisition board these steps are the same as 4 and 5 above for the second board CTL 4 7 Performance Tests and Troubleshooting Model 64601A 4 32 TEST 3 TRIGGER 0000 test steps 1238 4 33 Purpose This test checks the trigger path from the timing bus through the delay counter U37 4 34 Conditions set up by the software a The trigger enable counter U38 the window counter U36 and the delay counter U37 are set for zero delay b HE AND HE ATRANSIT and HE BTRANSIT are set HIGH or true LE PDUR gt A LE PDUR gt B LE ENTRIGA and LE ENTRIGB are set HIGH or false d Pattern duration is set greater than 5ns 4 35 Test Steps Description of software execution The first step checks the trigger path from the term selector U55 through the delay counter 1 The 130 shift register is programmed for HE PATT high at U55 2 H TRIG DLY at the status register U85 4 should be high the following tbree steps the trigger path is checked from the trigger selectors U13 and U17 through the delay counter 2 130 bit shift register is re programmed so the analyzer itself will generate trigger when HE RESET is low HE RESET is set h
153. TRIG2 into U13 and 017 are both set low H TRIG DLY should be false or low at U85 h 2 Low XE TRIG1 and high XE TRIG2 H TRIG DLY should be low 3 High XE TRIG1 and low XE TRIG2 H TRIG DLY should be low h High XE TRIG1 and high XE TRIG2 H TRIG DLY should be high CTL 4 18 Performance Tests and Troubleshooting Model 64601A 4 67 TEST 1h OR 16 Ch Only 0000 test steps 1234 4 68 Purpose This is the same as the above test execpt that H EAND is false or low 4 69 Test Steps Description of software execution 1 Low XE TRIG1 and low XE TRIG2 H TRIG DLY should be low at U85 4 2 Low XE TRIG1 and high XE TRIG2 H TRIG DLY should be true or high High XE TRIG1 and low XE TRIG2 H TRIG DLY should be high High XE TRIG1 and high XE TRIG2 H TRIG DLY should be high CTL 4 19 Performance Tests and Troubleshooting Model 64u601A 4 70 TEST 15 B FOLLOWED BY A 16 Ch Only 00000 test steps 12345 4 71 Purpose This tests the programming the term generators the latching circuit 067 75 and the arming circuits U54 55 69 4 72 Theory The A and B term generators select and combine acquisition board triggers Besides AND OR combinations there is a B before A combination A signal satisfying the B term generator is latched and the analyzer then waits for an A signal to occur before triggering LE ENLATCHB into U55 must be low for the latched B mode 4 73 Test Steps Descri
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155. U47A 5 s TRIGGER 58 CIRCUIT HE RESET nese d i FROM TEST 9 9 9 a SAMPLE TRIGGER 3 U63 50 U51 us 3 TS 981 CLOCK 2 POSITION POSITION H TCO2 CPU 5 5 COUNTER INTERFACE 9 o o 5 8g FROM cus 9 TPS TRIGGER 2 USE CIRCUIT HE PATT RESET 18 8 8 1 CLOCK WNDWCLK WINDOW COMPLETE HE STOP COUNTER e 9 C93 86 TP11 C87 C88 C89 C90 C91 c R37 i o CTL 8 36 P O TIMING ANALYSIS CONTROL BOARD TRACEPOINT SELECTION HE PATT HE HRCLK HE WNDWCLK 64601 66501 WO e HE RESET DELAY CLOCK SELECTION ECL 2 s 9 jum 2 1 HE DCLK P 0 U37 HE PATT 75 START OUT ONE SHOT NC HE HRCLK 14 ONE SHOT jo IN 16 NC HE DLYCLK B cyte CLK 21 ue HE RESET 24121 23 M RST2 HROUT n ONE SHOT QUT SEE NOTE A DELAY COUNTER 6 G y COURIR LE ENIMBTR VHE TO U36 37 50 52 nro 6 74 LE TR 3 se HE PHI2C2 ON SERVICE SHEET 2 TRIGGER DELAY TRACEPOINT HE ENTRIG HE RESET NC NC VHE 3 25 ELS 0 065 TRACEPOINT ENABLE FF
156. UN HALT RESET HE DLCK LE TE LE ME CTL 8 4 SAMPLE H STOP END OF TRACE H TRIG DLY TRACEPOINT TRACEPOINT SELECTION VIDEO Figure 8 2 Timing Control Board Block Diagram 1 Theory and Schematics Model 64601A 8 18 TIMING CONTROL BOARD THEORY Fig 8 2 8 19 130 Bit Control Holding Register 8 20 The CPU programs the timing analyzer by loading 130 bits into a holding register consisting of the 25 bit registers in U1 36 37 38 and the 6 bit registers U10 11 15 71 and 73 The analyzer can be programmed to AND OR triggers from two acquistion boards sample at different rates up to 4OOMHz generate and combine up to two terms trigger on entering or leaving pettern transitions trigger on maximum or minimum pattern durations or delay for specified times after triggering 8 21 IMB Inter Module Bus 8 22 The IMB is the means by which the timing analyzer communicates with other analyzers such as state analyzer timing analyzer can be clocked or triggered or enabled externally It can also enable delay trigger another analyzer 8 23 Timing Bus 8 24 The timing bus is the means by which the control board communicates with one or two timing acquisition boards The control board sends the acquisition board sample clocks and RESET and RUN commands the acquisition board s sends the control board a trigger signal when the specified pattern is f
157. a acquisition board trigger during performance verifcation Can be either HIGH or LOW depending on whether ANDing or ORing triggers Power on pulse from motherboard Processor reset Used by the mainframe to drive HE RESET Row counter output Addresses to the Character Row RAM Master reset or initialization Enables restart on receipt of high going LE TE transition from the IMB Sets the Post Qualify mode which allows LE TE to act like a restart signal Enables run mode When high stops the sample clock Enables run mode on the acquisition board via the timing bus Sample clock output before the last divider connector Output to a BNC Start address Clocks in the starting address for the display Stops acquisition Window counter U36 output which deter mines the position of the trigger in memory ie the window in memory between tracepoint and the end of acquisition Determine the exact trigger position Status bits to mainframe Trigger position count within an eight sample clock group Trigger enable arm Will arm the trigger when L TE from the IMB is true Trigger enable drive Signal used by the timing analyzer to drive the IMB LE TE trigger enable line Trigger The timing analyser can be triggered or can assert a trigger on this IMB line Trigger drive Signal used by the timing analyzer to drive the IMB HE TR trigger line LE TRDRVTE HE TRIGTEST HE TRIGA HE TRIGB
158. after conditioning are sent out 16 differential inputs to the acquisition board 16 inputs go into glitch custom IC along with four sample clocks which determine the rate at which the acquisition board looks at data from the probe Except for Glitch Mode the triggering is asynchronous glitch chip s holding register has been programmed with the specified pattern during RESET will cause trigger only when the incoming pattern agrees with the specified The glitch chip also looks for glitches the glitch mode and will cause trigger if the glitch occurs at the time specified 8 12 In a timing analysis system the incoming data is constantly being stored in memory regardless of whether a trigger has occurred The encoders serialize the high speed data so it may be loaded into low speed RAM 8 13 When the glitch chip recognizes that incoming pattern is the same as what was previously programmed into its holding register it sends a trigger to the control board via the timing bus which connects the control board to the acquisition board 8 14 trigger selector 113 17 determines which acquisition board signal may become the trigger Triggers may be ANDed or ORed Durations or transitions may also be specified If the trigger signal satisfies the qualifications at this point and if the trigger has been enabled either internally or externally via the IMB from another analyzer the trigger will b
159. ard seating 4 11 Check cable connections All cables should be fastened securely The clock cables should be paired on the left or right two jacks The timing bus and IMB cables should have the pin 1 wire connected to pin 1 on the jack No cables other than the two listed in the 64601A Control Board manual parts list may be used for the timing bus 4 12 Check supply voltages Supply voltages from the mainframe 5V 5 2V should be within 5 The 3 25V should be within 3 CTL 4 2 Performance Tests and Troubleshooting Model 64601A 4 13 Isolate the problem to one board When failure occurs isolate the problem to either acg uisition board or the control board Check signatures on the timing bus whi ch connects the control board to the acquisition board s Look first at the signals HE RUN and HE RESET from the control board If these are good look at the return signals from the acquisition board s H MEMFUL XE TRIG1 2 two acqui sition board system H MEMFUL comes from the acquisition board in the lower numbered slot only 4 14 Check the programming In PV tests the mainframe stimulates the timing analyzer and v erifies correct operation by looking at the status registers Read each test description to see what is being stimulated Look at the signatures on the out puts of address decoders data latches and mode registers where the mainframe is stimulating that PV test circuit block Correct signa
160. bles 2 18 64601A control board will supply four sample clock signals to two acquisition boards via SMC jacks 21 J2 43 and Jl located on the top left hand part of the board when viewed from the component side 2 19 Each 64602A acqusition board requires two clock inputs from the control board Sample clocks are supplied from the control board to SMC jacks J1 and J2 on the top left hand part of the acqusition board 2 20 Clocks should be paired The left hand two jacks Jl and J2 on the control board should be connected to one acquisition board the right hand two jacks J3 and Jh should be connected to a second acquisition board CIL 2 3 Installation Model 64601A 2 21 Timing Bus 2 22 The timing bus is at the top right hand corner of the 64602A and 64601A timing boards when viewing from the component side The timing bus connects the timing Control Board to one or two Acquisition Boards 2 23 The timing Control and Acquisition Boards must be grouped together to allow the timing bus ribbon cable W1 on the 64601A parts list to connect the Control Board to the Acquisition Board When there are two Acquisition boards which are placed on either side of the Control Board a 3 position ribbon cable W2 on the 64601A parts list is used Use only the timing bus cable with the part number given the 64601A Control Board parts list The three position cable 64600 51603 is special split cable which has lines
161. board limitations 1 indicates those lines which cannot be tested In figure 4 3 for example the stimulus board in slot 7 cannot drive the DELAY CLOCK line and cannot receive from the BNC4 external connector Without this limitation listing those lines would normally show errors 4 81 Description 4 82 DCLK Same as HE DCLK GMC PDC 1 The stimulus board sends ten clocks over this line 2 The test board must receive ten and only ten clocks 3 83 LME LTE Same as LE ME LE TE LE TR 1 These three lines are initialized low 2 The stimulus board drives one line at a time high 3 The test board must see a high only on the exercised line 4 The three lines are initialized high 5 The stimulus board drives one line at a time low 6 The test board must see a low only on the exercised line 4 84 RST HLD Same lines as LE TE HE TR In the Post Qualify Mode and LTE have different functions than in the other timing analyzer modes HTR is a HOLD command from another analyzer over the IMB and LTE is the RESET command In the Post Qualify Mode the timing analyzer triggers independently then at some later time another analyzer can initiate a re run of the timing analayzer or tell it to hold its present data The Post Qualify Mode then consists of three possible states 1 NORMAL data acquisition state which the timing analyzer is acquiring data while looking for a trigger condition 2
162. ched Then A trigger signal may be generated A and B terms may be ANDed but the latched B and B triggers are mutually exclusive 8 32 The A term generator will be described One of the outputs of the AND OR trigger combination IC is a ramp moving down toward 5 2V U35 3 The ramp moves dow at a rate determined by the combination of capacitors and current sources turned on by the programming At some point the ramp will reach the schmitt trigger U34 threshold The schmitt will thus trigger sooner or later depending on the programmed duration 8 33 The other output of the AND OR trigger combination IC is a high going pulse into the transition circuit 027 One of the paths through U27 is delayed so that when the pulse finally goes low again a negative glitch occurs 027 9 8 34 When a trigger satisfies the conditions of the A term generator the output HE TRIGA at U42 3 is a positive going pulse This output can occur under four different conditions a Greater Than durations The pattern must last longer than the A term generator specifies b Less Than durations The pattern must last less than the A term generator specifies c Leaving transitions A trigger will occur when the pattern is leav ing the specified pattern d Entering transitions trigger will occur when the input data is entering the specified pattern 8 35 Three signals determine which of the above situations will cause an trigger HE TRIG
163. d availabie for AIMB stimulus STATUS Awaiting command Figure 4 20 Press run Verification fc 11757812 Fri 15 Tested Failed 200 MHz Timing Data Acquisition 200 MHz Timing Controi 0 200 MHz Timing bata Acquisition 0 Timing analyzer control board available for stimulus STATUS Awaiting command run repeated Figure 4 21 Press slot CTL 4 h2 Performance Tests and Troubleshooting Model 64601A Option Performance Yerification Timing Pata Acquisition 200 P Timing Control j 4H 200 MHz Timing Gata Acquisition STATUS Awaiting command print Figure 4 22 Type the slot number 200 MHz Timing Performance Verification 1 5 812 Fri 15 Jan Module Tested 200 MHz Timing Data Acquisition 0 200 MHz Timing Control 200 MHz Timing Data Acquisition Timing analyzer control board available for AINB stimulus STATUS Awaiting command run slot 6 Cepeated Figure 4 23 Press test CTL 4 43 Performance Tests and Troubleshooting Model 64601A 5 AVAILABLE zZ fHz Timing CONTROL BOAR SERIAL PROGRAMMING Cn p WINDOW RATES INTERVAL FB THAN IHT TRANSITION AND OR B FOLLOWED BY 5 8 5 i 1 i i i i lt STATUS Awaiting command run slot 6 test Figure 4 24 Type the test number TESTS AVAILABLE 20 MHz Timing CONTROL BOARD WINDOW S INT
164. dori 5 Chome UTSUNOMIYA Tochigi 320 Tel 0286 25 7155 CH CS E SALES amp SUPPORT OFFICES Arranged alphabetically by country Yokogawa Hewlett Packard Ltd Yasuda Seimei Nishiguchi Bidg 30 4 Tsuruya cho 3 Chome YOKOHAMA22 1 Tel 045 312 1252 CH CM E JORDAN Mouasher Cousins Company 0 Box 1387 AMMAN Tel 24907 39907 Telex 21456 SABCO JO ADCOM Ltd Inc Kenya P 0 Box 30070 NAIROBI Tel 331955 Telex 22639 Samsung Electronics Computer Division 76 561 Yeoksam Dong Kwangnam Ku 0 Box 2775 SEOUL Tel 555 7555 555 5447 Telex K27364 SAMSAN A CH CM CS E M P KUWAIT Al Khaldiya Trading amp Contracting 0 Box 830 Safat KUWAIT Tel 42 4910 41 1726 Telex 22481 Areeg kt CHEM Photo amp Cine Equipment 0 Box 270 Safat KUWAIT Tel 42 2846 42 3801 Telex 22247 Matin kt P LEBANON G M Dolmadjian Achrafieh 0 Box 165 167 BEIRUT Tel 290293 MP LUXEMBOURG Hewlett Packard Belgium S A N V Blvd de la Woluwe 100 Woluwedal B 1200 BRUSSELS Tel 02 762 32 00 Telex 23 494 paloben bru A CH CM CS E MP P MALAYSIA Hewlett Packard Sales Malaysia Sdn Bhd 1st Floor Bangunan British American Jalan Semantan Damansara Heights KUALA LUMPUR 23 03 Tel 943022 Telex MA3 1011 A CH E M P Protel Engineering 1917 Lot 6624 Section 64 23 4 Pending Road Kuching SARAWAK Tel 36299 T
165. e sent on to the delay counter 8 15 The delay counter U37 may be programmed to cause a delay from the time a trigger has come out of the glitch chip until the start of an actual trace in memory Memory is continuously be filled but good data does not occur until tracepoint trigger delay has occurred The delay counter is clocked internally by the sample clock or externally from the IMB DLCK if the delay must be synchronous 8 16 The programmable delay counter sends its terminal count to a tracepoint latch U51 The tracepoint latch may be loaded either by the internal trigger signal or by a trigger from another analyzer via the IMB 8 17 The tracepoint signal now goes to the programmable window trigger position counter 036 which determines how much post tracepoint memory will be filled The window counter s terminal count stops the sample clock and the memory address counters on the acquisition board By determining the size of the window between tracepoint end of acquisition the window counter determines the position of tracepoint in memory CTL 8 3 Theory and Schematics Model 64601A 64601A TIMING CONTROL BOARD 130 BIT HOLDING REGISTER YO CNV STVNDIS 3 18VN3 STVNDIS ONDISVIA S IVNOIS 3 18VN3 z 5 4 zs m 2 m s eu gt 2 TRIGGER HE PATT GENERATORS X TRIG 1 2 ACQUISITION 2 BOARDS 6 o 5 R
166. el R36 C25 R18 74 86 11 L ac c6 1 e d oo 1 f v fd Yt 54 C8C10 9 2 4 RZA l m ll 5 N Q R21 R22 t 9 C43 42 44 CRI 2 63 75 C76 070 972 77 S C78 5 gt C96 1 P1 TP6 C12 11 R12 28 27 C47 U75 U9 U43 e 2 n C79 C89 13 057 C30 TIMING U18A 9 Ex R 5 5 eres T amp vx c c 5 es III p oo U31 R24 C32 C31 C33 U33 C34 R25 R26 R27 35 R28 C36 tite 5 N ceeds 9 U47 998 amp 1 U47A e 059 9 n 5 9 9 9 8 083 978 979 5 5 b i e b 9 095 L 997 i 8 2 9 S 7 I 9 e TP12 R38 85 C23 C58 TP9 R34 Theory and Schematics Model 64601A 64601A TIMING CONTROL BOARD 130 BIT HOLDING REGISTER SAMPLE 2 RATE 22 CLOCK 42 HO QNV S IVNOIS 3 18VN3 STVNDIS DND
167. elex MA 70904 PROTEL Cable PROTELENG MALTA Philip Toledo Ltd Notabile Rd MRIEHEL Tel 447 47 455 66 Telex Media MW 649 P MEXICO Hewlett Packard Mexicana S A de C V Av Periferico Sur No 6501 Tepepan Xochimilco MEXICO D F 16020 Tel 676 4600 Telex 17 74 507 HEWPACK MEX A CH CS E MS P Hewlett Packard Mexicana S A de C V Ave Colonia del Valle 409 Col del Valle Municipio de Garza Garcia MONTERREY N L Tel 78 42 41 Telex 038 410 CH ECISA Jos Vasconcelos No 218 Col Condesa Deleg Cuauht moc MEXICO D F 06140 Tel 553 1206 Telex 17 72755 ECE ME M MOROCCO Dolbeau 81 rue Karatchi CASABLANCA Tel 304 1 82 3068 38 Telex 23051 22822 E Gerep 2 rue d Agadir Boite Postale 156 CASABLANCA Tel 272093 272095 Telex 23 739 P NETHERLANDS Hewlett Packard Nederland B V Van Heuven Goedhartlaan 121 NL 1181KK AMSTELVEEN 0 Box 667 1180 AR AMSTELVEEN Tel 020 47 20 21 Telex 13 216 HEPA NL A CH CM CS E MP P Hewlett Packard Nederland B V Bongerd 2 NL 2906VK CAPELLE A D IJSSEL 0 Box 41 NL 2900AA CAPELLE A D IJSSEL Tel 10 51 64 44 Telex 21261 HEPAC NL A CH CS E NEW ZEALAND Hewlett Packard N Z Ltd 169 Manukau Road Box 26 189 Epsom AUCKLAND Tel 687 159 Cable HEWPACK Auckland CH CM E P Hewlett Packard N Z Ltd 4 12 Cruickshank Street Kilbirnie WELLINGTON 3 0 Box 9443 Courtenay Place WELLINGTON 3
168. er type 8 54 The character ROM encodes data and formatting information into two dots of video The mainframe writes dots on the screen at a 25MHz rate but since each character is two dots wide 12 5MHz has been used up to this point in the display driver The two 12 5MHz parallel dots are therefore changed to serial information and synchronized with the 25MHz system clock in the output latch 8 55 Since data enhancements and blanking have taken different paths they need to be synchronized The output latch lines up the information so that the data may be enhanced and blanked and the resulting video is sent out to the mainframe CTL 8 15 Theory and Schematics Model 64601A 8 56 8 57 MNEMONICS Mnemomics are listed in alphabetical order following the slash following convention is used The a An L or H before the slash indicates active LOW or HIGH b An E after L or H but before the slash indicates an ECL signal c No E before the slash indicates a TTL signal d An X instead of L or H means the signal may be programmed as either active LOW or HIGH e The functional mnemonic appears after the slash Table 8 1 Mnemonics MNEMONIC DEFINITION HE AND Determines AND OR combination of XE TRIG signals from two ac quisition boards HE ATRANSIT A transition Enables an trigger on the transition leaving the specified pattern To trigger on entering transitions XE TRIG from the acquisition board must be LOW tr
169. eu 1200 0607 1XU89 1200 0638 amp 1XU90 1200 0607 61XU91 1200 0607 amp 1XU92 1200 0607 ALXUIS 1200 0607 28480 1200 0607 DIP DI 28480 1200 0607 DIP DI 28480 1200 0607 1 DIP D 28480 1200 0638 SO CKET IC DIP 28480 1200 0638 A1XU94 1200 0607 ALXUIS 1200 0607 A1XU96 1200 0607 ALXU97 1200 0638 amp 1XU101 1200 0638 Nicos 911 0410 1335 CRYSTAL 20 0MC 28480 0410 1335 8120 4094 CABLE TIMING 2 CONNECTOR 28480 8120 4094 8120 4093 k CABLE TIMING 3 28480 8120 4093 64620 61820 CABLE ASYNCHRONOUS INTER MODULE 28480 64620 61620 See introduction to this section for ordering information Indicates factory selected value CTL 6 8 50167 54013 00000 01121 01295 02111 04713 07263 11236 19701 20932 24546 25403 Replaceable Parts Model 04601A Table 6 3 List of Manufacturers Codes Zip m e FUJITSU LTD HITACHI ANY SATISFACTORY SUPPLIER CO S INSTR INC SEMICOND CMPNT DIV ELECTRONICS CORP ICONDUCTOR PRODUCTS CORNING GLASS WORKS BRADFORD AMPEREX EL CORP SEMICON MC DIV NATIONAL ICONDUCTOR CORP NING GLASS WORKS WILMINGTON HEWLETT PACKARD CO CORPORATE CORP SOLID STATE DIV ADVANCED MICRO DEVICES INC STET TRUSH INC ELECTRIC ELECTRO MOTIVE TRW INC PHILA TOKYO TOKYO MILWAUKEE DALLAS CITY IND PHOENIX MOUNTAIN VIEW BERN BRADFORD SLATERSUTLLE
170. f 55 8ms H TRIG DLY should be false at 55 7ms 4 A trigger should occur by the end of the 200us interval before 55 9ms In the following bracket steps the delay counter is checked against the memory address counters on the acquisition board When the delay counter times out it starts the window counter which determines the window in memory between tracepoint H TRIG DLY and the end of aquisition Since the window counter has been set to zero for this test it immediately stops H STOP the RAM counters when the delay counter times out 5 In steps 1 and 2 above when H TRIG DLY goes true during the 200us interval it starts the window counter Since the window counter has been set to zero H STOP immediately goes true stopping acquisition and leaving the RAM counters with a certain count This count is verified 6 This is similar to step 5 The RAM counters should be correct at the end of the second 200us interval in steps 3 and above CTL 4 9 Performance Tests and Troubleshooting Model 64601A DELAY COUNTER continued Because the RAM counters have a capacity of only 256 the above steps could pass when the delay counter is actually off by a multiple of 256 To avoid that possibility the mainframe processor clock is used to clock the delay window and position counters Since the processor clock is so much slower than the 200MHz timing analyzer sample clock only the lower 16 bits of the delay counter are loaded
171. formance Tests and Troubleshooting Model 64601A 645016 Timina Control Roard AND 13 HORM MODE DATA THRESHOLD HIGH ttl amp ecl CLOCK THRESHOLD ttl ST SP GL THRESHOLD tti Location of ST SP START tp 12 Location of QUAL STOP tp 12 Location of CLOCK tp 11 Location of GROUND and tp 7 49 4 830 49 5 a94r U 49 12 low Uu 49 13 HFSS U 64 4 low U U amp 5 POHI U 64 12 PUSO U 64 13 low U 85 1 60au CTOTLZ 0004 u U 85 2 HEI u 85 3 HACU LJ 0 85 4 894F U 32 amp 5 U G 6 low 0 85 02 85 8 low U U 88 9 U 85 11 PUSO u U 825 12 2H1C u U 89 13 POH 85 14 HUS2 U 89 15 6390 U u 85 16 1278 U 85 17 low LI U 35 18 0565 L U 85 19 600441 CTOTLZz 0004 U u u CTL 4 78 10 10 10 10 10 10 10 UH oC OF b LEP 10 10 10 11 10 12 4 t 10 13 10 14 10 15 11 11 ie pic px 11 11 11 CH p Who M 9 11 10 11 11 11 12 11 13 11 14 11 18 13 13 13 13 13 13 D oi 5 neg pos pos high b22H 1696 8C4C 2AAA 622H 1696 0000 CTOTLZ 0130 32HH 4996 323HH 4996 BIAC high UHCP 7PHU 4817 UC H UHCP 0000 CTOTLZ 0130 4817 4413 HHU 443 HHU 9 PPUF high 0281 972p 4817 low low UAL3 low t ORL edge edge u TOTLZ u 13
172. gative positive 5 negative SCR not recommended for SE field replacement SECT not separately SEMICON replaceable 1 SIL order by description SL oval head SPG oxide SPL SST SR peak STL printed circuit picofarads 10 12 TA farads phosphor bronze phillips peak inverse voltage positive negative positive part of polystyrene porcelain position s potentiometer peak to peak point peak working voltage rectifier radio frequency round head or right hand integrated circuit vacuum tube neon bulb photocell etc voltage regulator cable socket crystal tuned cavity network rack mount only root mean square reverse working voltage slow blow screw selenium section s semiconductor silicon silver slide spring special stainless steel split ring steel tantalum time delay toggle thread titanium tolerance trimmer traveling wave tube micro 10 6 variable dc working volts with watts working inverse voltage wirewound without CTL 6 3 Replaceable Parts Model 64601A Table 6 2 Replaceable Parts List HP Part Number Reference Designation Description Mfr Part Number 646014 TIMING ANALYSIS CONTROL BOARD 28480 646014 64601 66502 TIMING CONTROL BOARD 28480 64601 66502 0160 2055 0160 2055 0160 2055 0160 2055 0160 3879 CAPACITOR FXD 010 80 20 100VDC CAPACITOR FXD 010 80 20 100UDC C
173. ger occurs Enables the timing analyzer to drive the IMB LE TR trigger line true when a valid trigger occurs Enable IMB trigger Enables the IMB TR line to determine trace point externally Enables a latched trigger Causes a trigger if A occurs anytime following B Enables a performance verification trigger Enables a trigger out of the A term generator Enables a trigger out of the B term generator Enables a trigger into the A term generator from the acquisi tion board in the lower numbered slot CTL 8 17 Theory and Schematics Model 64601A MNEMONIC LE ENTRIG2A LE ENTRIG3A LE ENTRIGUA LE ENTRIG1B LE ENTRIG2B LE ENTRIG3B HE F1 HE F2 HE F3 HE Fh L GLTCHMEM HE HRCLK L HSYN L IVID L LOADEN L LOADUR HE LTRIGB HE MASKME CTL 8 18 DEFINITION Enables trigger into the A term generator from a second acquisiton board in the higher numbered slot Enables trigger into the A term generator from a third acquisition board Not used in a 200MHz system Enables a trigger into the A term generator from fourth acquisition board Not used in a 200MHz system Enables trigger into the B term generator from the acquisi tion board in the lower numbered mainframe slot Enables trigger into the B term generator from a second ac quisition board in the higher numbered mainframe slot Enables trigger into the B term generator froma third
174. igh H TRIG DLY should be low 3 XE PVTRIG is programmed high true to the trigger selectors U13 and 017 H TRIG DLY should be high at the status register U85 4 4 The trigger from each acquisition board can be programmed high true or low true If XE TRIG1 from the acquisition board in the lower numbered slot is high whether true or false step 2 above may fail Step 4 passes when XE TRIG1 is low CTL 4 8 Performance Tests and Troubleshooting Model 64601A 4 36 TEST DELAY COUNTER amp TRIG POSN 0000 0000000 test steps 1238 567891011 4 37 Purpose This test checks the delay counter U37 and the position counter 051 052 The tests braces compare the delay counter against software timer The delay counter must time out within 200us window in order to pass If the tests in braces fail it may mean that the 25MHz system clock in the mainframe or the 200MHz timing clock are significantly off in frequency 4 38 Conditions set up by the software For this test the window counter U36 and the trigger enable counter U38 are set to zero 4 39 Test Steps Description of software execution 1 The delay counter is loaded with a 1010 pattern resulting in a delay of 167 8ms H TRIG DLY should be false at 167 7ms 2 H TRIG DLY should go true sometime during the 200us interval between 167 7ms and 167 9ms 3 The delay counter is loaded with a 0101 pattern resulting in a delay o
175. ighedsvej 32 DK 8240 RISSKOV Tel 06 17 60 00 Telex 37409 hpas dk DOMINICAN REPUBLIC Microprog S A Juan Tom s Cotes No 60 Arroyo Hondo SANTO DOMINGO Tel 565 6268 Telex 4510 ARENTA DR RCA ECUADOR CYEDE Cia Ltda Avenida Eloy Alfaro 1749 Casilla 6423 CCI QUITO Tel 450 975 243 052 Telex 2548 CYEDE ED CMEP Hospitalar S A Robles 625 Casilla 3590 QUITO Tel 545 250 545 122 Telex 2485 HOSPTL ED Cable HOSPITALAR Quito M EGYPT International Engineering Associates 24 Hussein Hegazi Street Kasr el Aini CAIRO Tel 23829 21641 Telex IEA UN 93830 CH CS E M Informatic For Systems 22 Talaat Harb Street CAIRO Tel 759006 Telex 93938 FRANK UN CH CS P Egyptian International Office for Foreign Trade 2558 CAIRO Tel 650021 Telex 93337 EGPOR P EL SALVADOR IPESA de El Salvador S A 29 Avenida Norte 1216 SAN SALVADOR Tel 26 6858 26 6868 Telex 20539 EPISA ACH CM CSEP B SALES amp SUPPORT OFFICES Arranged alphabetically by country FINLAND Hewlett Packard Oy Revontulentie 7 SF 02 100 ESPOO 10 Tel 00358 0 4550211 Telex 9100 A CH CM CS E MS P Hewlett Packard Oy Aatoksenkalv 10 C SF 40720 72 JYVASKYLA Tel 941 216318 CH Hewlett Packard Oy Kainvuntie 1 SF 90 140 14 OULU Tel 981 338785 CH FRANCE Hewlett Packard France 2 1 Mercure Rue Berthelot F 13763 Les Milles Cedex AIX EN PROVENCE Tel 16 42 59
176. inton Grange PORT ELIZABETH 6001 Tel 041 302148 CH Hewlett Packard So Africa Pty Ltd 33345 Glenstantia 0010 TRANSVAAL 1st Floor East Constantia Park Ridge Shopping Centre Constantia Park PRETORIA Tel 982043 Telex 32163 Hewlett Packard So Africa Pty Ltd Private Bag Wendywood SANDTON 2144 Tel 802 5111 802 5125 Telex 4 20877 Cable HEWPACK Johannesburg A CH CM CS E MS P SPAIN Hewlett Packard Espafiola S A Calle Entenza 321 E BARCELONA 29 Tel 322 24 51 321 73 54 Telex 52603 hpbee A CH CS E MS P Hewlett Packard Espafiola S A Calle San Vicente S No Edificio Albia Il E BILBAO 1 Tel 423 83 06 A CH E MS Hewlett Packard Espa ola S A Crta de la Coru a Km 16 400 Las Rozas E MADRID Tel 1 637 00 11 CH CS M Hewlett Packard Espa ola S A Avda S Francisco Javier S no Planta 10 Edificio Sevilla 2 E SEVILLA 5 Tel 64 44 54 Telex 72933 A CS MS P Hewlett Packard Espa ola S A Calle Ramon Gordillo 1 Entlo 3 E VALENCIA 10 Tel 361 1354 CH P SWEDEN Hewlett Packard Sverige AB Sunnanvagen 14K S 22226 LUND Tel 046 13 69 79 Telex 854 17886 via Spanga office CH Hewlett Packard Sverige AB Vastra Vintergatan 9 S 70344 OREBRO Tel 19 10 48 80 Telex 854 17886 via Spanga office CH Hewlett Packard Sverige AB Skalholtsgatan 9 Kista Box 19 5 16393 SPANGA Tel 08 750 2000 Telex 854 17886 A CH CM CS E MS P
177. l U 46 5 4 36 DEY U 85 12 7020 46 6 4 89 DEV U 85 14 H780 U 46 7 5 17 DE U 85 15 PSAF U 46 8 5 17 DCV 85 16 C197 46 9 0 81 U 88 12 low 0 46 10 0 16 DCV U 85 18 AYAB U 45 11 0 01 DEY U 85 19 3934 U 46 12 17 U 86 8 U 46 13 0 54 DEY 86 7 593 U 46 14 0 01 DENY U 86 10 9266 U 46 15 4 36 DOV U 86 11 PSAF 46 16 4 03 DOV U 90 1 24 9 42 01 4 99 PEN U 90 2 06HC 47 2 0 16 DOV 90 3 292H 47 3 0 01 DENY U 90 4 low 42 4 0 16 DEN v0 9266 47 4 99 DEN U 90 6 CTL h 61 Performance Tests and Troubleshooting Model 64601A ECL U Se 2 7 24 MHz U 35 13 Q074F U 42 12 0133 U 5 3 7 24 MHz U 35 15 18 4 U 43 1 high U 7 2 7 24 MHz U 36 1 0000 U 43 2 high U 7 3 7 24 MHz U 36 3 2246 43 4 035 U 10 1 high U 36 4 U 43 5 low U 10 2 Feu U 36 6 high U 43 7 5831 10 3 3U67 U 36 7 low U 43 9 high 10 4 9103 36 9 P762 45 10 Low U 10 5 6870 U 36 10 8F3U U 45 11 18H4 U 10 6 190 36 12 0000 43 12 1S8H4 U 10 7 Bus U 36 13 U 43 13 10 10 9403 U 36 14 0000 43 14 41PP 10 11 PSH6 U 36 15 high U 49 3 8F3U U 10 12 074F U 36 17 0000 49 7 P7623 U 10 13 PSH U 36 18 low 0 49 11 low U 10 14 074 36 19 high U 49 18 FBC U 10 15 HFOP U 36 20 high U 34 1 high U 15 1 high U 36 24 FCSF U 54 2 U 15 2 0153 U 37 1 0000 U 54 3 AHSA U 15 3 5831 U 37 3 848H U 54 4 2482 U 15 4 861
178. lace NEW DELHI 110 024 Tel 682547 Telex 031 2463 Cable BLUESTAR A CH CM CS E M Blue Star Ltd 15 16 C Wellesley Rd PUNE 411011 Tel 22775 Cable BLUE STAR A Blue Star Ltd 2 2 47 1108 Bolarum Rd SECUNDERABAD 500 003 Tel 72057 Telex 0155 459 Cable BLUEFROST AE Blue Star Ltd T C 7 603 Poornima Maruthankuzhi TRIVANDRUM 695 013 Tel 65799 Telex 0884 259 Cable BLUESTAR E Computer Maintenance Corporation Ltd 115 Sarojini Devi Road SECUNDERABAD 500 003 Tel 310 184 345 774 Telex 031 2960 CH INDONESIA BERCA Indonesia 496 JKT Abdul 62 JAKARTA Tel 373009 Telex 46748 BERSAL IA Cable BERSAL JAKARTA BERCA Indonesia 0 2497 Jkt Antara Blag 17th Floor Medan Merdeka Selatan 17 JAKARTA PUSAT Tel 21 344 181 Telex BERSAL IA 5 BERCA Indonesia 0 Box 174 SBY Kutei No 11 SURABAYA Tel 68172 Telex 31146 BERSAL SB Cable BERSAL SURABAYA A EMP IRAQ Hewlett Packard Trading S A Service Operation Al Mansoor City 9B 3 7 BAGHDAD Tel 551 49 73 Telex 212 455 HEPAIRAQ IK CH CS IRELAND Hewlett Packard ireland Ltd 82 83 Lower Leeson Street DUBLIN 2 Tel 1 60 88 00 Telex 30439 A CH CM CS E M P Cardiac Services Ltd Kilmore Road DUBLIN 5 Tel 01 351820 Telex 30439 ISRAEL Eldan Electronic Instrument Ltd 1270 JERUSALEM 91000 1
179. lay line device signaling lamp misc electronic part amperes automatic frequency control amplifier beat frequency oscillator beryllium copper binder head bandpass brass backward wave oscillator counter clockwise ceramic cabinet mount only coeficient common K composition complete LH connector LIN cadmium plate LK WASH cathode ray tube LOG clockwise LPF deposited carbon M drive MEG MET FLM MET OX MFR MHZ MINAT MOM electrolytic encapsulated external farads flat head MOS fillister head MTG fixed MY giga 109 N germanium glass NE ground ed fuse filter integrated circuit jack relay inductor loud speaker meter microphone ABBREVIATIONS N O NOM henries hardware hexagonal NPO mercury hour s hertz intermediate freq impregnated incandescent include s insulation ed internal kilo 1000 left hand linear taper lock washer logarithmic taper low pass filter milli 10 3 meg 106 metal film metallic oxide manufacturer mega hertz miniature momentary metal oxide substrate mounting mylar nano 10 9 normally closed neon nickel plate mechanical part plug transistor resistor thermistor switch transformer terminal board test point normally open nominal negative positive zero zero temperature coefficient ne
180. le shooting and signature analysis purposes are follows data sheet specifications may be better than this TIL Voltage Levels ECL Voltage Levels Level Voltage Level Voltage LOW lt 0 8 LOW lt 1 50 HIGH gt 2 0 HIGH gt 1 10 CTL 8 1 2 8 Th TIMING ACQUISITION BOARD TIMING CONTROL BOARD Sample Rate Gen H STOP Threshold Trigger Selector Duration Term Gen TRIG OUT Encoder High Speed RAM Trigger Position Counter Delay Counter Glitch Det User Data Sampler Inputs Trigger gt Enable Counter 25MHz L VSYN VIDEO 3 L HSYN Timing Diagram INV VIDEO 3 Display Gen es 2 at Fung MOTHERBOARD BUS lt 0q ct 9 9 pue Theory and Schematics Model 64601A 8 8 TIMING SYSTEM THEORY Fig 8 1 8 9 The timing analyzer consists of either two or three boards In an 8 channel system there is one 8 channel acquisition board and one control board in the next higher mainframe slot One timing probe is connected to each acquisition board 8 10 The D A converters on the acquisition board set the probe thresholds The upper four channels can be programmed with an upper threshold and the lower four channels with a lower threshold for dual threshold operation 8 11 eight inputs go into the probe
181. les continuous Cursor continuous Intensify continuous CTL 4 32 Performance Tests and Troubleshooting Model 64601A This is the 16 channel version of figure 4 8 shifted by one dot in each of the next eight displays CTL 4 33 Performance Tests and Troubleshooting Model 64601A XE pM 2M MD DUM PM DU DEN D See EpbREEEREE lad aud Tas ag Tan a a S PR D Raed ead Seat ETRE SESEEESESESEESEEESZSSESS NT IHE Figure 4 14 This is the 16 channel version of figure 4 9 The following eight displays are each shifted by one dot The pattern consists of glitch characters every four dots followed by highs for four dots and then lows for four dots Intensity cursor and graticule are continuous CTL h 3h Performance Tests and Troubleshooting Model 64601A LULPUCFLRLETLPEPUTITLTLTETTTEEFLIEFPLFETTTELFEIEJETLTIPETULTLTITLTILTAT LEU LLLP ee LLL LLLP LLL LLL LLL LeeLee LPL LLLP LL LLL LPL LL LLLP LLU LeeLee LLL LLL Lee ELL EP LE LEP LEP EP LPL TITLE LLL LLL LFUTLELELPLJLERLDPETLTLIRFETLFUTLELELITTLECTEFUPLFTTLFEFELEIE FLELT UL LOL LLL LLL LLL LELUT G UL U EFU GU U EEU
182. lete system keyboard operation is beyond the scope of the service manual Please refer to the operator s manual 64601 90903 for the procedure CTL 3 1 Operation Model 64601A NOTES CTL 3 2 Performance Tests and Troubleshooting Model 64601A SECTION IV PERFORMANCE TESTS 4 1 SECTION IV TABLE OF CONTENTS Topic Paragraph Page Introduction ER epee Us Rua w dg Hegi 1 1 Troubleshooting techniques eer WAG pins dees E FEES 4 2 Physical setup conditions qM MR WIG ewe Keyboard setup for all 15 PV tests pp l18 2 2 x A erus 4 4 Keyboard setup for test YOO C ua 4 5 Explanation of PV 4 22 4 5 PV teste 4 26 6 Supplementary display 7 4 21 Supplementary IMB test E 4 15 2 4 37 Supplementary board ID Centon ses 44344 qoya s ana ESOT AA 4 40 Figures illustrating softkey sequence h 89 lh h1 Signature 1 1200 2 sia edd nee 4 46 4 2 INTRODUCTION 4 3 Performance verification tests check the major circuit blocks for proper operation giving the operator at least 90 confidence that the board is operating correctly 4 4 There are 15 PV Tests and 3 Supplementary Tests
183. mpedance state Mode M identifies an input that selects the mode of operation of an element and indicates the inputs and outputs depending on that mode Address A identifies the address inputs Transmission X identifies bi directional inputs and outputs that are connected together when the transmission input is true DEPENDENCY NOTATION SYMBOLS Address selects inputs outputs indicates binary range N Control permits action R Enable permits action S AND permits action V 2 X Negate compliments state Reset Input Set Input OR permits action Interconnection Transmission Mode selects action LS 08 09 82 2 C Analog Signal amp Bit Grouping gt Buffer Compare gt Dynamic 1 Exclusive OR L Hysteresis Interrogation Internal Connection Borrow Generate Borrow Input Borrow Output Borrow Propagate Carry Generate Carry Input Binary Coded Decimal DIR Binary Buffer Counter Decimal Adder Theory and Schematics Model 64601A Table 8 2 Logic Symbols Cont d OTHER SYMBOLS gt 2 Inversion O Negation X Nonlogic Input Output lt Open Circuit external resistor Open Circuit external resistor 21 OR Passive Pull Down internal resistor Q Passive Pull Up internal resistor T Postponed Shift Left or up LABELS Carry Output Carry Propagate Content Data Input Shift Right or down Solidus allows an input or ou
184. ocation of QUAL STOP tp 12 Location of CLOCK tp 11 Location of GROUND TTL U 49 4 CH73 U 49 5 ASU Uu U 49 12 low u 49 13 AQP U U 64 4 low u U 64 5 ASAP U 64 12 8285 u U 64 13 low u 85 1 u U 85 2 CH73 u U 85 3 8226 9 0 85 4 ASU 85 5 PBF u U 85 amp 429A U 85 2 H amp 41 U 35 amp Low 85 9 37H5 u U 85 11 gres U 85 12 U U 85 13 ASAF U 85 14 U 85 15 5284 U 85 16 Q UUZ U 85 17 low 85 18 1921 U 85 19 PO1U 86 5 49016 U 85 7 667U U 86 10 U 86 11 5284 90 1 C862 90 2 8485 U 90 3 4U2P uU 90 4 low 90 5 U 90 amp 5284 0 7 low U 90 9 Low neg pos ned 90 10 90 11 90 12 90 13 90 14 90 15 91 9 1 lt 91 91 9 1 m 91 91 91 10 91 11 91 12 91 13 91 14 91 15 N CS LH P IN Temporarily connect U13 pins 12 and 14 together low low high 46HH 5513 high AZU 46r 7 8000 0000 high S913 high high high POIL high 667i edge edge edge seve seot seee oare nee soet sose sose cone coso 7 1 high 77 2 499 2 3 HFAC 7 4 FUG 2 HFAC 7 9 7 10 HESE 7711 0000 7 12 FUP 7 13 HFAC 7 19 19 1 high 19 2 high 19 3 BFA 19 4 low 19 8 lou 19 7 CC99 19 9 a308 19 10 low 19 11 high 19 12 low 19 13 A508 19 14 low 19 19 1382 21 2U75 1 2
185. oftware and firmware designated by HP for use with an instrument will execute its programming instructions when properly installed on that instrument HP does not warrant that the operation of the instrument or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE EXCLUSIVE REMEDIES THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES HP SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY ASSISTANCE Product maintenance agreements and other customer assistance agreements are available for Hewlett Packard products For any assistance contact your nearest Hewlett Packard Sales and Service Office Addresses are provided at the back of this manual CW amp A 2 81 HEWLETT PACKARD SERVICE MANUAL MODEL 64601A TIMING ANALYSIS CONTROL BOARD REPAIR NUMBERS This Manual applies directly to Models with Repair Numbers prefixed 2350A COPYRI
186. ommon control outputs are located in the control block Outputs of array elements are located in the corresponding array element with the least significant bit closest to the control block CHIP FUNCTION The labels for chip functions are defined i e CTR counter MUX multiplexer DEPENDENCY NOTATION Dependency notation is always read from left to right relative to the symbol s orientation Dependency notation indicates the relationship between inputs outputs or inputs and outputs Signals having a common relationship will have a common number i e C7 and 7D C7 controls D Dependency notation 2 3 5 6 1 C7 is read as when 2 and 3 and 5 and 6 are true the input will cause the counter to increment by one count or the input C7 will control the loading of the input value 7D into the D flip flops The following types of dependencies are defined AND G OR V and Negate N denote Boolean relationship between inputs and outputs in any combination Interconnection Z indicates connections inside the symbol Control C identifies a timing input or a clock input of a sequential element and indicates which inputs are controlled by it Set S and Reset R specify the internal logic states outputs of an RS bistable element when the R or S input stands at its internal 1 state Enable EN identifies an enable input and indicates which inputs and outputs are controlled by it which outputs can be in their high i
187. ot call for operator intervention CTL 4 5 Performance Tests and Troubleshooting Model 64601A 3 26 TEST 1 SERIAL PROGRAMMING 00 test steps 12 4 27 Purpose This test verifies the programming of the 130 bit control register consisting of 01 U10 011 015 U36 U38 U71 and U73 130 bit register is the means for programming the timing analyzer 4 28 Test Steps Description of software execution 1 The 130 bit shift register is loaded with all HIGHs and a single LOW is walked through There should be one LOW and 129 HIGHs coming out the end of the shift register The last bit HE STOP U36 4 should be LOW 2 Perform the abcve test using 129 LOWs and a single HIGH CTL 4 6 Performance Tests and Troubleshooting Model 64601A 4 29 TEST 2 RUN HALT RESET 0000000 test steps 1234567 4 30 Purpose This test verifies that the L RUN bit at 1090 6 be exercised The L RUN bit stops the sample clock and disables the 64602A acquistion board memory address counters when it is high The test also verifies that the delay counter U37 the window counter U38 the trigger position counter U51 U52 and the acquisition board memory address counters can be reset to 0 4 31 Test Steps description of software execution 1 HE RESET is set high and the H HALT bit at U90 6 is set high 2 The H HALT bit at U90 6 is set low 3 U85 status bits H STOP H TRIG DLY H MEMFUL H
188. ound and memory has been filled 8 25 Motherboard 8 26 The motherboard is the mainframe bus which communicates power and CPU programming signals to the timing analyzer CTL 8 5 9 8 TL3 X20143 Xoo 2 erdueg g 200 MHz FROM 130 BIT HE F1 4 HR SAMPLE CLOCK 200MHz MUX 04 24 SEL TP1 2Hz 200MHz 2Hz 200MHz BNCOUT 1Hz 100MHz 25Hz 25MHz WINDOW CLOCK VIO9q9 pue Theory and Schematics Model 64601A 8 27 SAMPLE RATE CLOCK THEORY Figs 8 3 8 10 8 28 The sample rate clock determines the frequency at which the timing analyzer samples data The maximum clock frequency is 100MHz but data is sampled on both clock edges allowing a maximum sample rate of 200MHz in the Wide Sample Mode 8 29 In Fast Sample Mode the clock is split into two phases allowing four edges in the same time period thus effectively increasing the sample rate to 4OOMHz In the Fast Sample Mode the number of channels in an eight channel system is decreased from eight to four since every second channel is sampled at the second clock phase SAMPLE CLOCKS NORMAL GLITCH amp D T MODES HE PHI 2A 2B LE PHI 2A LE PHI 2B FAST SAMPLE 400 MHz MODE 5 ns p k HE PHI 2A LE PHI 2 2 5 k LE PHI 2B
189. ow U 90 4 low U 90 5 high U 90 6 high 90 7 low 90 9 low U 90 10 low U 90 11 low 90 12 high U 90 14 high 190 185 high U 91 6 high CTL 4 85 Performance Tests and Troubleshooting Model 64601A U 91 7 high U 91 9 high U 91 10 high U 91 11 high u 91 12 high U 91 13 high U 91 14 high U 91 15 high U 92 1 high 92 2 high 92 5 low 92 7 low 0 92 9 high 9 92 10 low 92 12 high U 92 18 high 0 93 1 high 0 93 020 low U 93 low U 93 7 low 93 9 hagh U 93 10 high U 93 12 high 0 93 15 high 94 1 high U 94 2 0000 TOTLZ 12519 94 3 high U 94 4 Low U 94 lou U 94 low 94 7 high 94 9 3836 TOTLZ 0024 U 94 10 high 94 11 U 94 12 12A U 94 13 3580H U 94 14 P816 94 15 8984 U 95 1 high 0 95 2 0000 TOTLZ 12519 U 95 3 high U 95 4 high U 95 85 low U 95 6 low 98 7 high U 95 9 3834 CTOTLZ 0024 U 98 10 89868 U 95 11 SAFC 0 95 12 3632 0 95 135 4 86 U 95 14 8779 U 95 18 1166 U 98 1 high U 96 2 383A TOTLZ 00284 96 3 low U 96 4 high U 96 high U 96 6 high U 95 7 high U 96 9 3836 CTOTLZz O01 U 965 10 USS U 96 11 2 U 98 18 HURA U 96 13 4521 U 96 14 9860 96 15 CCS3A 0 92 1 4743 97 2 8 97 3 8601 U 92 4 97 4743 U 97 6 U 92 8 92 9 QU22 U 97 10 0000 U 97 11 9584 97 12 APCS 92 13 3836 CTOTLZ 12519 gt U 98 1 high
190. pacitor and repeat the last step to ensure a stable oscillation Connect the scope probe BNC to INPUT A of the 5314A Universal Counter Set up the counter for NORM FREQ A 10Hz RESOLUTION positive SLOPE ATIN 1 and adjust LEVELA on the counter to approximately the middle position Connect the scope probe tip to TPh located between Ul and U20 and connect the ground lead of the scope probe to GND The counter should display 50MHz 0 01 49995kHz 50005kHz Press softkey Press RETURN Adjustments Model 64601A 5 12 TRIGGER DURATION CALIBRATION R1 through R6 5 13 Besides the previous sample rate oscillator adjustment there are six adjustments for trigger duration on the 64601A control board six pots R1 R6 are located at the top of the board when viewed from the component side last three adjustments Rh R6 are for 16 two acquisition board system ONLY 5 14 duration pots R1 R6 at the top of the 64601A control board deter mine the pattern duration required for triggering 5 15 Use PV tests 6 and 10 for adjustment of R1 through R6 For an 8 channel single acquisition board system only R1 R2 and R3 need to be adjusted 5 16 A slight readjustment may be necessary whenever the 64601A control board is moved to a different mainframe 5 17 Hardware Setup a Connect the timing probes to the data acquisition boards through the timing cables b
191. ption of software execution 1 HE TRIGA out of the A term generator is high and HE TRIGB is low H TRIG DLY should be low at U85 4 2 Both HE TRIGA and HE TRIGB are low H TRIG DLY should be low 3 HE TRIGA is low and HE TRIGB is high The B latch is now set H TRIG DLY should still be low 4 Both HE TRIGA and HE TRIGB are low H TRIG DLY should be low The B latch should remain set because there has been no RESET 5 HE TRIGA is high and HE TRIGB is low We now have an A trigger occurring after a latched trigger H TRIG DLY should be high 4 20 Performance Tests and Troubleshooting Model 64601A 4 74 SUPPLEMENTARY DISPLAY TEST Further confirmation of proper display driver operation may be be obtained visually by pressing the following softkeys sequence run slot __ display test Press RETURN and the first pattern appears This pattern verifies by corner brackets proper timing display centering You may observe other test patterns by continuing to press RETURN until the first pattern finally Fifteen unique patterns are illustrated in figures 4 2 to 4 16 last 11 patterns figures 4 5 to 4 16 are repeated eight times in the displays and shifted by one dot in each display The repetitions are not shown in the manual Except for the eight dot shift in the patterns following those shown in figures 4 5 to 4 16 the screen patterns should look similar to the illustrations
192. r order Table 6 3 contains the names and addresses that correspond to the manufacturers five digit code numbers 6 3 ABBREVIATIONS 6 4 Table 6 1 lists abbreviations used in the parts list the schematics and throughout the manual some cases two forms of the abbreviation are used one all in capital letters and one partial or no capitals This occurs because the abbreviations in the parts list are always capitals However in the schematics and other parts of the manual other abbreviation forms are used with both lowercase and uppercase letters 6 5 REPLACEABLE PARTS LIST 6 6 Table 6 2 is the list of replaceable parts and is organized as follows a Chassis mounted parts in alphanumerical order by reference designation b Electrical assemblies and their components in alphanumerical order by reference designation Miscellaneous parts The information given for each part consists of the following a The Hewlett Packard part number and the check digit b The total quantity Qty in the instrument c The description of the part d A five digit code that indicates the manufacturer e The manufacturer s part number The total quantity for each part is given only once at the first appearance of the part number in the list CTL 6 1 Replaceable Parts Model 64601A 6 7 ORDERING INFORMATION 6 8 To order a part listed in the replaceable parts table quote the Hewlewtt Packard part number and check digit
193. rigger information will be displayed When the delay counter times out it emits H TRIG DLY which starts the window counter When the window counter times out it emits H STOP which stops the sample clock and memory address counters and ends the trace The count preset into the window counter determines where H TRIG DLY will appear memory window then is the post tracepoint part of memory 4 43 Test conditions Processor generated clocks are used for this test and the delay counter is set to zero 4 44 Test Steps Description of software execution 1 The trigger enable and window counters are loaded to AAH Clock until one before the trigger enable counter should fire H TRIG DLY at the status register U85 4 should be false 2 Clock once more and HE ENTRIG from the trigger enable counter should go true causing a trigger at the status register 3 Clock until one before the window should close H STOP should be false out of the window counter Clock once more and the window should be shut causing H STOP at the status register U85 2 to be true 5 8 The trigger enable window counters are loaded to 155H and tested as above CTL h 11 Performance Tests and Troubleshooting Model 64601A 4 45 TEST 6 RATES INTERVAL 00000 0000 test steps 12345 6789 4 46 Purpose A user of the timing analyzer may specify pattern durations a trigger will then occur only when the pattern la
194. rts Model 64601A Description CAPACI TOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACTTOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD CAPACITOR FXD 10 CAPACITOR FXD 27 DIODE SWITCHI 1UF 80 20 100VDC CER i1UF 80 20X 100UDC D1UF 80 20 100UDC C 180PF 5 100UDC CER O1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC 01UF 80 20 100UDC O1UF 80 20 100UDC OT1UF 80 20 100UDC O1UF 80 20 100UDC 80 20 100UDC 200PF 5 300UDC MICA O1UF 80 20 100UDC CER 80 20 100UDC CER 470PF 4 54 100UDC CER O1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC OT1UF 80 20 100UDC O1UF 80 20 100UDC O1UF 80 20 100UDC 1OUF 10 20UDC TA 100 10 20UDC TA 100 10 20UDC TA 00 PF 5 100 VDC 5 200VDC CER NG 30V SOMA 2NS 00 35 8M SNP M PC 50 OHM CONNECTOR RF CONNECTOR RF INDUCTOR RF C INDUCTOR RF C PIN GRV 062 BOARD EJECTOR BOARD EJECTOR amp TRANSISTOR NP ST R TRMR STO R TRMR T R TRMR ISTOR TRMR STO R TRMR 100 81 1 IK 1 1K 1 301 3T 1 3K ESISTOR 1 5K RESISTOR 4
195. s for the display The mainframe also loads the display RAMs with data glitch blanking cursor intensify and graticule information In the normal mode the timing analyzer actually sends video and inverse video to the mainframe for display 8 52 The character counters are capable of counting 255 2 dot characters but are preset to less to allow for a left margin The dot line counters count the number of horizontal dot lines in the display Since only one line of a character is written ata time the dot line counter increments each time rizontal syne L HSYN pulses character row counter counts the number of character rows eight in 8 channel mode and increments every 30 lines in 8 channel mode or every 15 lines in 16 channel mode 8 53 The mainframe loads the encoded timing information into the display RAMs during the programming mode Since transitions require knowledge of past data RAM information is sent to a present past shift register which delays data by one dot during display Both old and new data are then sent to a character ROM which also receives information from the formatting ROM Since only one line of a character is written at a time and characters such as dualthresholds have middle information horizontal trace position is needed to format characters The formatting ROM after getting the horizontal position from the dot line counter outputs a 3 segment code which correlates horizontal position with charact
196. sts a given length of time In this test a trigger must not occur when the pattern lasts less than the given time The user may thus ensure that triggering does not occur on transients or shorter patterns This test checks the B term generator duration circuits U44 U46 U47 and the sample rate clock For a given sample rate the acquisition board memory address counters used to verify the accuracy the selected interval within 20 The tests in braces check each capacitor and current source at a different sample rate With ranges 1us the resolution is not good enough to verify the specs 4 47 Theory When tracepoint H TRIG DLY is generated the window counter U36 counts down to determine the amount of window between tracepoint in memory and the end of new acquisition When the window counter times out it generates H STOP stopping the sample clock and consequently the acquisition board RAM counter By setting the window counter 036 the delay counter U37 and the trigger enable counter U38 to zero the only delay between the acquisition board trigger XE TRIG and H STOP is that selected by the duration circuits in the term generators 4 12 Performance Tests and Troubleshooting Model 64601A RATES INTERVAL B continued 4 48 Test Steps Description of software execution The acquisition board memory address counters verify within 20 the accuracy of the duration circuits After each tes
197. t U13 pins 12 and 14 together 12 edge le edge pos edae U 85 7 F 36 U 86 10 UFO U 86 11 SFA 90 1 ARTF 90 2 68914 90 3 7466 U 90 4 low 0 90 UZEO U 90 6 SFAS 90 13 323299 U 90 14 F036 0 90 18 high U 91 1 6309 U 91 2 884H 91 3 94 0 91 4 036 TOTLZz0207 U 91 0000 U 91 6 high LU 91 7 F036 200012 U 91 12 F 36 91 13 FOSS U 91 15 036 35 ECL U Y 1 high U 7 2 49P7 U 7 3 BH U 7 4 AGP 7 5 89 1 7 9 A9P 7 7 10 89 U 7 12 49P7 U 7 13 89Hi1 U 7 18 89 1 U 10 1 high U 10 2 10 3 10 4 8 06 10 5 0877 U 10 6 U 10 7 9CAH U 10 10 8F06 U 10 11 822 U 10 12 045C U 10 13 8223 U 10 14 045C 0 10 18 A460C U 15 1 high 15 2 SFAS 15 3 15 4 3323 u 15 3104 U 15 SFAS U 15 7 APS1 15 10 3323 15 11 ROCF 15 12 U 15 13 39CF U 15 14 H8Uag 15 15 0877 U 17 1 high U 17 2 CACC 4 59 Performance Tests and Troubleshooting Model 64601A U 17 3 768H U 38 1 0000 U 55 12 U 17 4 3323 U 38 3 460C J 55 12 1406 U 17 low U 38 4 UCAS U 55 15 low U 17 amp low U 38 6 high U 1 high 17 7 S390F U 38 7 Low 67 2 UPFO U 17 9 low HU 38 9 high U 67 3 low u 17 10 UPFO 38 10 U 67 5 3746 LU 17 11 HBUB U 38 12 0000 U 82 65 246 17 12 0000 u 38 15 3746 67 7 374 U 17 13 0877 38 14 0000 U 67 9 3746 17
198. t step the counters are checked For the duration ciruits to pass the counters must fall within the allowable range 1 Duration circuits are set to 10us sample rate is 50 2 2 Duration is set to 100us sample rate is 200MHz 3 Duration is set to lus sample rate is 100MHz Duration is set to 50us sample rate is 4OMHz 5 Duration is set to 200us sample rate is 10MHz The following steps in brackets use single capacitor and different current sources If these steps pass and the previous ones fail the problem is likely to be a capacitor or the particular sample rate circuitry associated with the step that fails 6 Duration is set to 2us sample rate is 200MHz T Duration is set to 5us sample rate is 200MHz 8 Duration is set to 10us sample rate is 200MHz 9 The last test verifies that HTRIG DLY was true or HIGH in all previous test steps CTL 4 13 Performance Tests and Troubleshooting Model 64601A 9 TEST 7 LESS THAN INTERVAL B 0000 test steps 1234 4 50 Purpose In this test the duration circuits must time out before the trigger pattern ends If timeout occurs before the Acquisition Board trigger signal XE TRIG disappears the analyzer should trigger 4 51 Theory The term generator duration circuits ramp down from ground after receiving LOW trigger signal from 35 1 The mainframe processor programs the time it takes to fire the schmitt circuit U34 4 52 Conditions
199. than 40 BNC Drive Output signal swing in transition trigger mode Amplitude 2 0V typical Width at 50 10ns typical Output signal swing in width greater than trigger mode Amplitude 2 5V typical Width Input trigger width minus the selected duration Output signal swing in width less than trigger mode Amplitude same as in transition trigger mode Width same as in transition trigger mode Position occurs when trigger pattern disappears before the selected duration times out IMB Functions interconnection with other modules Master Enable LE ME drive receive Execute Halt only Trigger Enable LE TE drive receive Trigger HE TR drive receive Delay Clock HE DCLK receive only Storage Enable LE SE not used 1 4 Installation Model 64601A SECTION II INSTALLATION 2 1 INTRODUCTION 2 2 This section contains information for installing and removing the Model 64601A Included are initial inspection procedures preparation for use and instructions for repacking the instrument for shipment 2 3 INITIAL INSPECTION 2 4 Inspect the shipping container for damage If the shipping container or cushioning material is damaged it should be kept until contents of the shipment have been checked for completeness and the instrument has been checked mechanically and electrically Procedures for checking electrical performance are given in Section IV If
200. the contents are not complete if there is mechanical damage or defect or if the instrument does not the Performance Tests notify the nearest Hewlett Packard Office If the shipping container is damaged or if the cushioning material shows signs of stress notify the carrier as well as the Hewlett Packard Office Keep the shipping materials for carrier s inspection The HP office will arrange for repair or replacement at option without waiting for claim settlement 2 5 PREPARATION FOR USE 2 6 There are no specific preparation for use procedures except the actual installation of the boards in the Mainframe cardcage 2 7 INSTALLATION INSTRUCTIONS WARNING WHEN REMOVING OR INSTALLING THE TIMING ANALYZER BOARDS THE MAINFRAME A C LINE POWER MUST BE TURNED OFF CTL 2 1 Installation Model 64601A IMB CABLE CLOCK CABLES TIMING BUS CABLE PROBE BUS S ACQUISITION BOARD OPTIONAL CONTROL BOARD N Se X PROBE BUS ACQUISITION BOARD LOWEST NUMBERED SLOTS 02 J3 44 Figure 2 1 Timing Configuration CTL 2 2 Installation Model 64601A 2 8 Mainframe Configuration 2 9 Depending on the number of channels required the timing analyzer will use two or three card slots of the mainframe cardcage 2 10 One Timing Acquisition Board 64602A should be installed in the lowest numbered card slot available The Timing Control Board 646014 then goes in the next higher slot
201. ther trigger TE line acts like restart line in this mode and the TR line acts like a hold line preventing further resets 8 h2 The trigger enable circuit determines which term generator trigger HE TRIGA HE TRIGB HE LTRIGB will become the pattern trigger HE PATT that is sent on to the delay counter The latched B trigger and the B trigger are mutually exclusive but the A and B triggers may be anded CTL 8 11 8 110 130 BIT HR DLCKSEL FROM TRIGGER ENABLE CIRCUIT FROM SAMPLE CLOCK 2 HE RESET FROM TRIGGER ENABLE CIRCUIT HE PATT FROM SAMPLE CLOCK WNDWCLK uoI42e eg 4urodeoeJg 8 xoolgd 2 8 TRACEPOINT SELECTION ENIMBTR TR LE TE AND HE TR DRIVE TRACEPOINT LATCH U66 TRACE POINT TRIG DLY TRACEPOINT SELECT TRACEPOINT COUNTER EN HE TRIG DLY RESET TRIGGER TRIGGER 3 H T position POSITION C02 COUNTER EN RESET TRACE WINDOw COMPLETE HE STOP VTO9R9 sor4eueuog pue Zro wr TO CPU INTERFACE Theory and Schematics Model 64601A 8 43 SELECTOR Figs 8 6 8 14 8 44 Tracepoint is the start of a trace The acquisition board provides a trigger signal to the control board when the pattern specification is satisfied This trigger signal is further qualified in the control board 1 It can be
202. tput to have more than one function Tri State Causes notation and symbols to effect inputs outputs in an AND relationship and to occur in the order read from left to right User for factoring terms using algebraic techniques Information not defined Logic symbol not defined due to complexity J Input K Input Operand Transition Extension input or output Count Up Function Count Down MATH FUNCTIONS Arithmetic Logic Unit Comparator Divide By Equal To Greater Than Less Than Look Ahead Carry Generator Multiplier Subtractor CHIP FUNCTIONS Directional DMUX Demultiplexer FF Flip Flop MUX Multiplexer OCT Octal Random Access Memory Line Receiver Read Only Memory Segment Shift Register DELAY and MULTIVIBRATORS Astable 100 Delay Nonretriggerable Monostable NV Nonvolatile J lL Retriggerable Monostable 1 5 08 09 82 3 8 23 Theory and Schematics Model 64601A 64601A TIMING CONTROL BOARD TIMING CONTHOL BOARD 2 017 5 130 BIT HOLDING REGISTER 11 R12 09 R13 R14 R15 C18 Y L3 3H C12 FES Hh UM mU z T R oe ust 8 gt CLOCK 2 9984 18 68 l S amp ca 8 ll gt 9 SIVNDIS 3 18VN3 S IVNOIS ONDISVIN STVNDIS 318VN3 53 C54 C55 R31 R32 C56 R33 H STOP
203. trasse 1 D 4000 DUSSELDORF Tel 0211 5971 1 Telex 085 86 533 hpdd d A CH CS E MS P Hewlett Packard GmbH Vertriebszentrale Frankfurt Berner Strasse 117 Postfach 560 140 0 6000 FRANKFURT 56 Tel 0611 50 04 1 Telex 04 13249 hpffm d A CH CM CS E MP P Hewlett Packard GmbH Gesch ftsstelle Kapstadtring 5 D 2000 HAMBURG 60 Tel 040 63804 1 Telex 021 63 032 hphh d A CH CS E MS P Hewlett Packard GmbH Gesch ftsstelle Heidering 37 39 D 3000 HANNOVER 91 Tel 0511 5706 0 Telex 092 3259 A CH CM E MS P Hewlett Packard GmbH Geschiftsstelle Rosslauer Weg 2 4 D 6800 MANNHEIM Tel 0621 70050 Telex 0462105 ACE Hewlett Packard GmbH Gesch ftsstelle Messerschmittstrasse 7 D 7910 NEU ULM Tel 0731 70241 Telex 0712816 HP ULM D A C E Hewlett Packard GmbH Geschiftsstelle Neumeyerstrasse 90 D 8500 NURNBERG Tel 0911 52 20 83 87 Telex 0623 860 CH CM E MS P Hewlett Packard GmbH Gesch ftsstelle Eschenstrasse 5 0 8028 TAUFKIRCHEN Tel 089 6117 1 Telex 0524985 A CH CM E MS P GREAT BRITAIN See United Kingdom GREECE Kostas Karaynnis S A 8 Omirou Street ATHENS 133 Tel 32 30 303 32 37 371 Telex 215962 RKAR GR A CH CM CS E M P PLAISIO S A G Gerardos 24 Stournara Street ATHENS Tel 36 11 160 Telex 221871 P GUATEMALA IPESA Avenida Reforma 3 48 Zona 9 GUATEMALA CITY Tel 316627 314786 Telex 4192 TELTRO GU A CH CM CS E M P HONG KONG Hewlett Packard Hong Kong Ltd G P
204. tures may be traced back to where signals become incorrect 4 15 Check the status registers PV failure means the status registers for the control board service sheet 1 will have one or more incorrect output signatures The signa l path may then be traced back to the problem 4 16 PHYSICAL SETUP CONDITIONS FOR THE PV TESTS 4 17 Conditions for the following tests a Connect the timing pod to the 64602A acquisition boar d by means of timing cable 64604 61601 b Leave the probe leads disconnected so that the inputs are floating near ground c Make sure the two clock cables are securely connected Clock cables should be connected in pairs to either the two right or two left jacks d The timing bus cable should be connected to the jacks at the upper right hand corner when viewing from the component sic le of both the 64601A control board and the one or two 64602A acquis ition board s Only timing bus cables two or three position listed the 61601A parts list should be used e NOTE In noisy environments ground each probe input sing the ground lead for each probe Failure to do this may result in the PV display ing intermittent non existent failures CTL 4 3 Performance Tests and Troubleshooting Model 64601A 4 18 KEYBOARD SETUP For running all 15 PV tests repeatedly 4 19 To verify that the entire board is operating correctly perform the following steps on the mainframe keyboard
205. ue HE BLATCHR B latch reset Resets B latch for B Latched mode L BLNKMEM Enable display blanking memory HE BTRANSIT B transition Enables B trigger on the transition leaving the specified pattern To trigger on entering transitions XE TRIG from the acquisition board must be LOW true H CHARADO 11 Character address Addresses to display RAM from the character CTL 8 16 and line counters MNEMONIC L CNTRLD HE DLCLK L DATAMEM HE DLYCLKSEL L D0 15 HE D15 L ENHANMEM LE ENDRIVME LE ENPDRIVTE LE ENDRIVTR LE ENIMBTR LE HLATCHB LE ENPVTRIG LE ENTRIGA LE ENTRIGB LE ENT IG1A Theory and Schematics Model 64601A DEFINITION Counter load Clocks character dot line and character row counters in the display circuits during the programming mode During normal counting 12 5MHz clocks these counters Derived from L MEMWRT Delay clock timing analyzer delay counter U37 may be clocked externally over this IMB line Enable display data memory Delay clock select Selects a clock for the delay counter U37 which may be clocked internally or via the IMB Data lines from motherboard Programs the 130 bit register Derived from data line 15 Enable display enhancement memory Enables the timing analyzer to drive the IMB LE ME master enable line true when a valid trigger occurs Enables the timing analyzer to drive the IMB LE TE trigger enable line true when a valid trig
206. ures h 2 TO h 10 a Press softkey opt test RETURN b in the 64601A timing control board slot number RETURN Press softkey d Press softkey slot e in the 64601A timing control board slot number f Press softkey test g Type in the number of the test you wish to run h Press the soft key repeated RETURN 4 22 EXPLANATION OF THE TEST DESCRIPTIONS 4 23 There 15 9 in an 8 channel system performance verification tests for the timing control board Each of these tests has one or more test steps denoted by the 0 5 or 1 s within brackets A 0 in the bracket indicates a PASS for that test step and a 1 indicates FAIL 1 SERIAL PROGRAMMING 00 2 RUN HALT RESET 0000000 3 TRIGGER 0000 DELAY COUNTER amp TRIG POSN 0000 0000000 5 WINDOW 00000000 6 RATES INTERVAL B 00000 0000 T LESS THAN INTERVAL B 0000 8 TRANSITION TRIGGER B 000 9 DISPLAY DRIVER 00000000 10 RATES INTERVAL A 00000 0000 11 LESS THAN INTERVAL 0000 12 TRANSITION TRIGGER A ooo 13 AND 0000 14 OR 0000 15 B FOLLOWED BY A 00000 Not used in an 8 channel single acquisition board system 4 24 The numbered test steps described in each PV test correspond from left to right to the 0 s or 1 s within the displayed brackets 4 25 The numbered test steps describe the commands given by the system software They do n
207. w high uP amp 4 high ACF 3 HEUZ 4984 BP b4 6984 5264 HF 03 low high low ecP 4 high HF OS AIHA high FPCS 9842 187F S601 a7FF HF OS 4 PCS low PROS 4F H2 high 1425 1 4 low low AF HZ low 3314 P2FH 3896 CP OA low high 564 HF 0 3 HF 3 70402 uP 64 CTL 4 53 Performance Tests and Troubleshooting Model 64601A U 66 low 23 9 U 9 low U 75 10 08221 U 66 10 9862 U 73 11 18 F U 56 11 HF 3 U 73 12 5081 U 66 12 low U 73 13 187r U 56 13 high 73 14 5681 U 66 14 6099 73 15 P814 56 15 97264 U 24 1 high 67 1 high U 74 PZFH U 57 PeFH U 74 4 HFOS 57 3 CFA U 24 858 U amp 7 4 364 74 10 SUSH 67 74 11 1410 lJ 57 6 6 74 12 low 67 7 HF03 U 74 13 HFOS U 67 9 HF 3 U 74 14 high 67 10 SP64 U 86 2 0093 U 67 11 26H1 86 3 FSS 67 12 HFOS U 86 12 HOS U 57 14 1410 U 85 14 4984 69 1 high U 69 2 low 69 3 FSS 59 4 BUSH U 69 CFA U 69 6 FSS U 69 7 6P01 U 69 9 PCPS U 69 10 69 11 HFOS U 69 12 6984 U 69 13 high U 69 14 984 U 71 1 high 71 2 2 1 U 71 3 56 U 71 4 71 5 P814 71 6 2AHI 71 7 SOF 71 9 FSS u 1J u LI 71 10 AUZA 71 11 4632 U 71 12 3896 71 13 4532 U 71 14 3896 71 15 1FA4C U U U u U 73 1 high 73 2 8USH 73 3 8006 73 4 0324 73 5
208. w 67 6 09567 U 27 11 2099 U 28 9 high U 67 7 09585 27 128 2C99 U 38 10 PSuUG U amp 7 9 UFAC U 27 13 Pace U 38 12 0000 0 82 10 3242 27 14 POCP 38 13 US6C U 657 11 4P06 U 34 1 high U 38 14 0000 U 57 12 0966 U 34 2 POCP U 36 15 high U 67 13 low U 34 3 2099 U 38 17 0000 U 67 14 8521 U 34 4 POCP U 38 18 low U 67 18 high U 34 13 79CC U 38 19 high U 71 7 1 high 34 14 C29F U 38 20 high 71 2 4P06 U 35 1 high U 38 24 UJC 71 3 0957 35 2 2099 42 1 high 71 4 AASU u 35 3 U 42 2 high U 71 5 F165 U 35 4 uU 42 3 FU U 71 6 4POS U 35 5 9905 42 4 FCA 71 7 0957 35 6 5222 U 42 S 5865 71 9 0000 35 7 79CC U 42 6 9433 U 71 10 AAbU U 36 1 0000 U 42 7 71 11 8PF2 U 36 3 PCBS 49 2 3242 U 71 12 3220 U 36 4 u 49 11 low 71 13 8PF2 U 36 6 high 49 18 916 U 71 14 3220 36 7 low U 54 1 high 71 18 U 36 9 3242 U 54 2 F6F3 U 23 1 high U 36 12 0000 U S4 3 23 2 1H3 U 36 13 966 U 54 4 P5SU0 U 73 3 6348 36 14 0000 U 54 8 73 4 1 60 U 36 15 high U 54 6 HUA U 73 5 36 17 0000 54 7 HHS LU 23 6 21 3 U 36 16 low U 54 9 1966 U 73 7 6568 CTL 4 76 73 9 73 10 23 11 73 12 73 13 73 14 23 15 86 2 o 3 86 12 86 14 0000 1760 SOF HUAS OF F165 0000 0960 953 Performance Tests and Troubleshooting Model 64601A CTL 4 77 Per
209. w 92 15 CUl 81 low U 88 11 high 93 high uU 81 9 low U 88 12 high U eae U Gi i0 low 88 1 Low U 93 0 92 U 81 11 uU 90 29H31 Hog 1204 81 12 Low U 9 0 4279 93 2665 81 13 tow 90 3952 93 8731 81 14 high 90 Low 93 7 81 15 low u 90 high 95 9 923 82 1 0000 U 90 low TOTLZ 0040 CTOTLZz65552 U 90 7 9925 93 10 UU22 U 82 2 F24C 90 9 2656 U 93 11 23HP 82 3 923F 90 10 F995 93 12 H193 232768 90 11 U 93 15 C443 82 4 0000 90 12 high 93 14 1009 TOTLZz65552 90 13 0840 93 15 6054 a2 5 120 U 90 14 923F U 94 1 high TOTLZz65552 CTOTL Z 012323 U 94 2 923F 82 6 90 15 high CTOTLZz 659332 TOTLZ 65552 91 1 SAE u 94 3 CEHU uU 82 8 H125 91 2 yupi U 94 4 F265 82 9 high U 91 3 OPPE U 94 5 82 10 4319 U 91 4 923 0 94 6 CUed 82 11 high TOTLZ 0FLO 94 7 high U 82 12 low 91 5 0000 U 94 4519 U 82 13 low CTOTLZz99213 94 10 high U 88 1 high 91 6 high 94 11 19 U 85 2 low 91 7 925 94 12 2450 85 3 0204 CTOTLZZz0133 94 13 U 85 4 low U 91 9 923F 94 14 414C U 85 0692 CTOTLZ232764 94 15 HPUA Cn p DEPO d tfe CF b D fo st M G TO t V 4 68 U 98 1 high uU 98 2 923F TOTLZz 69552 92 3 HICA U 95 4 Cui U 95 95 2665 U 95 high 95
210. w U 36 7 low 43 4 U 67 14 89350 U 36 9 3242 0 43 low U 67 15 FCA U 36 10 7P9C U 43 6 H19F U 71 1 high U 36 12 0000 U 43 7 71 2 4218 36 13 0966 U 45 9 FOR U 71 3 U 36 14 0000 U 43 10 low U 71 4 A968 U 36 15 high U 43 11 16CC U 71 5 H9 58 U 36 17 0000 43 12 16CC U 71 6 4218 U 365 18 low 43 13 H19F U 71 2 CUCE U 36 19 high 43 14 H19F 71 9 Goon U 36 20 high U 43 15 0000 U 71 10 2968 U 36 24 0960 49 5 FPC U 71 11 8041 U 37 0000 49 7 3242 U 71 12 A740 U 37 38H U 49 11 low 71 13 84 41 37 U13P U 49 15 H916 71 14 4760 U 37 high U 4 1 high U 71 15 5991 U 37 low 4 2 8P72 U 23 1 high uU 37 Cus U 54 3 U 73 2 266 U 37 H916 U 54 4 250 73 3 Par U 37 10 lew U 54 5 3532 73 4 HHS U 37 12 0000 54 6 PUHE U 73 amp 50983 37 13 4960 54 7 H amp 55 U 73 6 266 U 37 14 0000 54 9 U96C U 73 2 P677 U 37 15 high S4 10 2643 U 73 9 0000 U 37 17 0000 54 11 H958 73 10 HHBU O OO s i d tet CTL 4 65 Performance Tests and Troubleshooting Model 64601A 73 11 3532 73 12 PUHS 73 13 3532 73 14 PUHS 25 18 H958 g s 2 5063 86 3 0000 86 12 U96C 85 14 0963 4 66 Performance Tests and Troubleshooting Model 64601A 6546016 Timing Control Board DISPLAY DRIVER 9 NORM MODE DATA THRESHOLD HIGH tti CLOCK THRESHOLD tti ST SP QL THRESHOLD trl Location of ST SP START tp 12
211. with a pattern The signature analyzer is gated ON during the following test steps only 7 The upper 8 bits of the delay counter are loaded with all 0 s and the lower 16 bits with 5555H H TRIG DLY at the status register 085 4 should be false one count before the delay counter is supposed to count out 8 H TRIG DLY should be true on the next count 9 The upper 8 bits of the delay counter are loaded with all 0 s and the lower 16 bits with 2AAAH H TRIG DLY should be false one count before overflow 10 The trigger should be true on the next count 11 This step checks the 3 bit trigger position counter At the end of step 4 H TCO should have been HIGH Then during step 7 H TC1 and H TC2 go HIGH at different times and finally all three H TCO H TC1 and H TC3 finish in a LOW state at the end of step 7 CTL 4 10 Performance Tests and Troubleshooting Model 64601A 4 40 TEST 5 WINDOW COUNTER 000000001 test steps 12345678 4 41 Purpose This test checks the window counter U36 and trigger enable counter U38 4 42 Theory The trigger enable counter the window counter and the delay counter are preset by the 130 bit shift register load during RESET The trigger enable counter prevents a trigger until old data has been flushed out of the acquisition board glitch chip and encoders The trigger enable counter also defines the depth of pre trigger information in memory Even in the start trace mode some pre t

Model 64601A Timing Analysis Control Board Service Manual

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