UG-6028GDEAF01 EVK user guide
Contents
1. UG 6028GDEAF01 Evaluation Kit User Guide Writer Kathy Huang Email Kathy huang univision com tw Version Preliminary Contents 1 REVISION HISTORY eege sashes nie a anaia a EE EE er 3 2 Ae ini ae neta de 4 3 SYMDO COTM TE 5 4 TIMMING CHARACTERISTICS ANN 6 4 1 80 Series MPU parallel Interface uk 6 4 2 6800 Series MPU parallel Interface uk 7 4 3 SPI IntertaCe ieee ce eege NEEN Ee Ve ege e dE ca ENEE NEE ENKE cere 8 5 EVK use introduction et 9 6 Power down and Power up Geouence EEN en 11 Z How touseGEbGb k mogdule eege EeeeSEESEEEEEN ENNEN SEENEN ENNEN de 12 7 1 Initial Step FIOW 2 20 ecce cece ccteeeececvedes dene cane eedenen dece ceca ccuecseerencececaneceuenssen skate 12 7 2 RD recommend Initial Code for 80 Interface ceceeeeeeeeeee EE 13 7 2 1 Sub Function for 80 Interface un 15 1 REVISION HISTORY Date Page Contents Version 2006 3 9 Preliminary Preliminary 0 0 2006 05 04 13 Initial setting Preliminary 0 1 Modify 04h reg 0x01 0x03 2006 05 09 5 Add note itmes Preliminary0 2 2006 05 10 12 Power on sequence Preliminary0 3 2005 05 25 11 Power down and Power up Sequence Preliminary 0 4 Univision 2 EVK Schematic JP1 SEP 525_35PIN R2 10K VCC DDIO2. Function for 80 Interface void Write_Register unsigned char data IOCLR Ox0000000ff reset DO D7 IOCLR bRS IOCLR nCs IOCLR nWR IOSET data IOSET nWR IOSET nCs IOSET bRS void Write_Parameter unsigned char data IOCLR 0x0000000ff reset DO D7 IOSET bRS IOCLR nCs IOCLR nWR IOSET data IOSET nWR IOSET nCs void Write_Command unsigned char Reg unsigned char data Write_Register Reg Write_Parameter data RD recommend Initial Code and Sub Function Note 1 For 80 series CPU interface 2 For 8bits DDRAM transfer 15
3. JP3 HEADER 3X2 EES b gt D gt EE DO OO Ohhh P2 HEADER 20X2 VO OO 8 CO GA Ga OO CSC O Ca h Ca h Ch CON2 D DDIO VSS CON2 Note The schematic is already remove R3 and D1 VSDH connect to GND 3 Symbol define D17 D9 These pins are 9 bit bi directional data bus to be connected to the MCU s data bus The D10 D17 are for command and data inputs 8bit parallel interface CSB These pins are CSB pins for master and slave driver IC This pin is the chip select input The chip is enabled for MCU communication only when CSB is pulled low CPU Selects the CPU type Low 80 series CPU High 68 Series CPU PS Selects parallel Serial interface type Low serial High parallel RDB For an 80 system bus interface read strobe signal active low For For an 68 system bus interface bus enable strobe active high When using SPl fix it to VDD or VSS level WRB For an 80 system bus interface write strobe signal active low For an 68 system bus interface read write select Low Write High Read When using SPI fix it to VDD or VSS level RESB Reset SEPS525F active low HV External Column Driving Power Supply LV Logic power supply GND Power supply ground Note1 Please grounding for no use data pin Note2 If you are not used RGB Interface please grounding VSYNC HSYNC Enable DOTCLK and floating VSYNCO Note3 If you are not used VDDIO please co
4. and PS ON Internal osc power off Write_Command rREDUCE_CURRENT 0x03 TO_05sec Reg 04h Action Normal current and PS OFF Write_Command rREDUCE_CURRENT 0x00 TO_05sec Reg 3Bh Action Screen Saver OFF Write_Command rSCREEN_SAVER_CONTEROL 0x00 Reg 02h Action Export 0 OSC with external resister Internal OSC ON Write_Command rOSC_CTL 0x41 Reg 03h Action FR 90Hz DIV 1 Write_Command rCLOCK_DIV 0x30 Reg 80h Action PDAC OFF DDAC OFF Reference Volt control with external resister Write_Command rlREF 0x00 Reg 08h Action set color R precharge time Write_Command rPRECHARGE_TIME_R 0x01 Reg 09h Action set color G precharge time Write_Command rPRECHARGE_TIME_G 0x01 Reg 0Ah Action set color B precharge tiem Write_Command rPRECHARGE_TIME_B 0x01 Reg 0Bh Action set color R precharge current Write_Command rPRECHARGE_Current_R 0x0a Reg 0Ch Action set color G precharge current Write_Command rPRECHARGE_Current_G 0x0a Reg 0Dh Action set color B precharge current Write_Command rPRECHARGE_Current_B 0x0a Reg 10h Action set color R dot driving current Write_Command rDRIVING_CURRENT_R 0x52 Reg 11h Action set color G dot driving current Write_Command rDRIVING_CURRENT_G 0x38 Reg 12h Action set color B dot driving current Write_Command rDRIVING_CURRENT_B 0x3a Reg 13h Action Col DO to D159 col normal display Write_Command rDISPLAY_MODE_SET 0x00 Reg 14h Action MPU mode Write_Command rRGB_IF 0
5. end Display on command Power down Sequence _ Display off Voc off Send Display off command 2 Power down Vppu 3 Delay 100ms when Vppu is reach 0 and panel is completely discharges 4 Power down Vpp Vss Ground 11 6 Power down and Power up Sequence To protect OLED panel and extend the panel life time the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Power up Vpp Send Display off command Display on Driver IC Initial Setting Clear Screen Voc Power up Vppu Delay 100ms when Vpp is stable Non D ht ee P 3 Vss Ground 7 Send Display on command Power down Sequence _ Display off Voc off Send Display off command 2 Power down Vppu 3 Delay 100ms when Vppu is reach 0 and panel is completely discharges 4 Power down Vpp Vss Ground 12 L Univision 7 How to use SEPS525F module 7 1 Initial Step Flow VDD ON Wait lms VDDH ON Wait ims Reset Driver IC walt tae Suggest all register Driver IC Initial Code Ber Display on Clear RAM Start Dispaly 7 2 RD recommend Initial Code for 80 Interface Reg 04h Action Normal current
6. idth a aE Data hold timing tous CSB hold timing ban notice All the timing reference is 10 and 90 of VDD Table 3 Serial peripheral interface Timing Characteristics 5 EVK use introduction Figure 4 EVK PCB and OLED Module Drivision The SEPS525F is COF type package that the connect pads are on the top of the module connector When finished assembled the module and EVK then push the locking pad to lock the module See the Figure 4 and Figured User can use leading wire to connect EVK with customer s system The example shows as Figure 6 Fig 6 EVK with test platform Note 1 Itis the external most positive voltage supply In this sample is connected to power supply Note 2 The leading wire has 14 pins totally in this case D17 D9 RDB RS WRB RESB CSB 10 6 Power down and Power up Sequence To protect OLED panel and extend the panel life time the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Power up Vpp Send Display off command Display on Driver IC Initial Setting Clear Screen Voc Power up Vppu Delay 100ms when Vpp is stable Non D ht ee P 3 Vss Ground 7 S
7. nnect to LV VDD 4 TIMMING CHARACTERISTICS 4 1 80 Series MPU parallel Interface Write Timming CSB RS WRB E DB 17 0 Figure 1 80 Series MPU 8 bit parallel Interface Timing Diagram We 2 8V Ta 25 a ECH Address hold timing tans Fa WS Address setup timing tass System cycle timing tcycs Write L pulse width twRLws 45 WRB Write H pulse width twRHws 45 Data setup timing toss 30 ns DB 17 0 Data hold timing tons ns notice All the timing reference is 10 and 90 S e VDD Table 1 80 Series MPU 8 bit parallel Interface Timing Characteristics 4 2 6800 Series MPU parallel Interface Write Timming CSB RS RWB WRB teLwe RDB DB 17 0 Figure 2 68 Series MPU 8 bit parallel Interface Timing Diagram VDD 2 8V Ta 25 c LE f sor cospmos wa MAX ns Address hold timing tAH6 Address setup timing EES System cycle timing tcycs ns Write L pulse width teLwe ns Write H pulse width tEHW6 ns ns DB 17 0 ns Table 2 68 Series MPU 8 bit parallel Interface Timing Characteristics notice All the timing reference is 10 and 90 VDD 4 3 SPI Interface Figure 3 Serial peripheral interface Timing Diagram VDD 2 8V Ia 257 E wm max unm ront Serial clock cycle SCL H pulse width SCL L pulse w
8. x31 Reg 16h Action 8btis dual transfer 65K support Write_Command rMEMORY_WRITE_MODE 0x66 Reg 17h Action Memory addr X start Write_Command rMX1_ADDR 0x00 Reg 18h Action Memory addr X end Write_Command rMX2_ADDR 0x9f Reg 18h Action Memory addr Y start Write_Command rMY1_ADDR 0x00 Reg 1Ah Action Memory addr Y end Write_Command rMY2_ADDR 0x7f Reg 20h Action Memory X start addr Write_Command rMEMORY_ACCESS_POINTER_X 0x00 Reg 21h Action Memory Y start addr Write_Command rMEMORY_ACCESS_POINTER_Y 0x00 Reg 28h Action Display duty ratio Write_Command rDUTY 0x7f Reg 29h Action Display start line Write_Command rDSL 0x00 Reg 2Eh Action Display First screen X start point Write_Command rD1_DDRAM_FAC 0x00 14 Reg 2Fh Action Display First screen Y start point Write_Command rD1_DDRAM_FAR 0x00 Reg 31h Action Display Second screen X start point Write_Command rD2_ DDRAM_SAR 0x00 Reg 32h Action Display Second screen Y start point Write_Command rD2_ DDRAM_SAR 0x00 Reg 33h Action Display size X start Write_Command rSCR1_FX1 0x00 Reg 34h Action Display size X end Write_Command rSCR1_FX2 0x9f Reg 35h Action Display size Y start Write_Command rSCR1_FY1 0x00 Reg 36h Action Display size Y end Write_Command rSCR1_FY2 0x7f Reg 06h Action Scan signal is high level at precharge period Dispaly ON Write_Command rDISP_ON_OFF 0x01 7 2 1 Sub
Download Pdf Manuals
Related Search