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TMS320C2X FIXED-POINT DSP USER'S GUIDE

1. GET OU FILOUT PA2 OUTPUT LAST FILTER OUTPUT IN FILIN PA2 INPUT NEW SIGNAL SAMPLE LRLK AR1 SIGNAL POINT AR1 TO SIGNAL DATA TO PROCESS ZAC CLEAR THE ACCUMULATOR MPYK 0 CLEAR THE P REGISTER RPTK 15 REPEAT MACD INSTRUCTION FOR 16 TAPS MACD COEF MULTIPLY ACCUMULATE SAMPLE DELAY APAC ACCUMULATE THE LAST PRODUCT SACH FILOUT 1 SAVE THE RESULT B PTS LOOP TO WAIT FOR NEXT SAMPLE PROGE label Pl END PROGL equ PROGE PROG PROGRAM CODE LENGTH COEFFICIENT DATA TO BE LOADED INTO ON CHIP RAM COEF label C1 START word 385 1196 1839 2009 word 1390 407 4403 19958 word 19958 4403 407 1390 word 2009 1839 1196 385 COEFE label END COEFL equ COEFFICIENT DATA LENGTH DATA PAGE 0 BLOCK B2 DATA MEMORY LABELS bss DRR 1 SERIAL PORT DATA RECEIVE REGISTER bss DXR 1 SERIAL PORT DATA TRANSMIT bss 1 TIMER REGISTER bss PRD 1 PERIOD REGISTER bss IMR 1 INTERRUPT MASK REGISTER bss GREG 1 GLOBAL MEMORY ALLOCATION REGISTER bss RSVRDO 5 bss B2 020
2. GUESS set 64h SQUARE ROOT OF X text SORT 55 STO SAVE STATUS REGISTER STO 55 1 STI SAVE STATUS REGISTER 5 1 LDPK 0 LOAD DATA PAGE POINTER 0 SSX SET SIGN EXTENSION MODE SPM1 LEFT SHIFT PR OUTPUT TO ACCUMULATOR SACL NUMBER SAVE X LARP 1 INITIALIZE VARIABLES FOR SQUARE ROOT LARK AR1 11 12 ITERATIONS LALK 800h ASSUME X IS LESS THAN 200h SACL GUESS SET INITIAL GUESS TO 800h SACL TEMPR SET FIRST INTERMEDIATE ROOT TO 800h SACH ROOT SET SQUARE ROOT VALUE TO 0 LAC NUMBER LOAD X INTO THE ACCUMULATOR SBLK 200n TEST IF X IS LESS THAN 200h BLZ SORTLP IF YES HE ROOT LAC GUESS 3 IF NO THEN REINITIALIZE SACL GUESS SET INITIAL GUESS TO 4000h SACL TEMPR SET FIRST INTERMEDIATE ROOT TO 4000h LARK AR1 14 15 ITERATIONS SQUARE ROOT LOOP SORTLP SQRA TEMPR SQUARE TEMPORARY INTERMEDIATE ROOT ZALH UMBER CHECK IF RESULT IS LESS THAN X SPAC BLZ EXTLP IF IT S NOT SKIP ROOT UPDATE ZALH TEMPR IF IT IS SET ROOT EQUAL TEMPR SACH ROOT NEXTLP LAC GUESS 15 SCALE DOWN GUESS BY 2 TO CONVERGE
3. PROCESSOR INITIALIZATION FOR THE 5320 25 RESET AND INTERRUPT VECTOR SPECIFICATION BRANCHES FOR EXTERNAL AND INTERNAL INTERRUPTS sect vectors RESET B INIT RS BEGINS PROCESSING HERE INTO ISRO 0 BEGINS PROCESSING HERE ISR1 BEGINS PROCESSING HERE INT2 ISR2 2 BEGINS PROCESSING HERE 18 RESET 16 TINT B TIME TIMER INTERRUPT PROCESSING RINT RCV SERIAL PORT RECEIVE PROCESSING XINT B XMT SERIAL PORT TRANSMIT PROCESSING USER PROC TRAP VECTOR PROCESSING BEGINS THE BRANCH INSTRUCTION PROGRAM MEMORY LOCATION 0 DIRECTS EXECUTION BEGIN HERE FOR RESET PROCESSING THAT INITIALIZES THE PROCESSOR WHEN RESET ES APPLIED THE FOLLOWING CONDITIONS ARE ESTABLISHED FOR THE STATUS AND OTHER INTERNAL REGISTERS ov OVM 1 INTM DP STO XXX 0 X ak 1 XXXXXXXXX ARB CNF SXM 11 HM FSM XF FO PM SII XXX 0 X al nbi 1 1 1 0 0 00 REGISTER ADDRESS DATA DRR 0000h XXXX XXXX XXXX XXXX DXR 0001 XXXX XXXX TE 0002h 22212 PRD 0003h XT ETI 0004 1111 1111 11
4. def 5 IMR INTERRUPT PROCESSING FOR EXTERNAL INTERRUPT THIS ROUTINE MAY BE INTERRUPTED BY INTERRUPT FROM THE EXTERNAL INTERRUPT INTO BUT NO OTHER ISR1 LARP 7 MAR AR7 ART 1 55 ST1 gt 7 AR7 ART 1 SST STO gt 7 AR7 ART 1 SACH ACCH gt AR7 AR7 AR7 1 SACL ACCL gt AR7 AR7 ART 1 LDPK 0 DP 0 PSHD IMR IMR TOS LACK 0001h MASK FOR INTO AND IMR MASK CURRENT IMR CONTENTS SACL IMR ACC IMR EINT ENABLE INTERRUPTS MAIN PROCESSING SECTION FOR ISR1 DINT DISABLE INTERRUPTS LDPK 0 DP 0 POPD IMR TOS IMR LARP AR7 AR7 ARP MAR r AR7 AR7 1 ZALS AR7 gt ACCL AR7 AR7 1 ADDH AR7 ACCH AR7 AR7 41 LST AR7 gt STO AR7 AR7 41 LST1 AR7 gt STI AR7 AR7 1 EINT ENABLE INTERRUPTS RE 5 32 Software Applications Memory Management 5 4 Memory Management 5 4 1 Block Moves The structure of the TMS320C2x memory map is programmable and can vary for each application Instructions are provided for moving blocks of data or pro gram memory configuring a block of on chip data RAM as program memory and defining part of external data memory as global Explanations
5. SACH 01 1 QI 1 2 QI QR ADD 2 15 1 4 QR SACH QR 1 QR 1 2 QI LAC PR 14 ACC 1 4 PR MPY QR P REGISTER 1 4 QI QR W APAC ACC 1 4 PR QI QR W SACH PR PR 1 2 PR QI QR W SPAC ACC 1 4 PR SPAC ACC 1 4 PR QI OR W SACH QR 1 QR 1 2 PR QI QR W LAC PI 14 ACC 1 4 PI MPY 01 P REGISTER 1 4 QI QR W APAC ACC 1 4 01 QR W SACH 1 PI 1 2 PI QI QR W SPAC ACC 1 4 PI SPAC ACC 1 4 PI QI OR W SACH QI 1 OI 1 2 PI QI QR W SEND 2 SMACRO PR PI QR QI CALCULATE Re P jQ AND Re P jQ LAC 15 ACC 1 2 PI SUB QR 15 ACC 1 2 PI QR SACH PI 1 2 PI QR ADDH QR ACC 1 2 PI QR QR SACH QR QR 1 2 PI QR CALCULATE Im P jQ AND Im P jQ LAC PR 15 ACC 1 2 PR ADD QI 15 ACC 1 2 PR QI SACH PR PR 1 2 PR QI SUBH zo AGC 1 2 PR QI QI DMOV QR OR OI SACH QR QR 1 2 PR QI SEND 4 MACRO PR PI QR QI W LT SW T REGISTER W COS 4 SIN PI 4 LAC OT 14 ACC 1 4 QI SUB QR 14 ACC 1 4 QI QR SACH 01 1 2 QI QR ADD
6. RESE INIT RS will begin processing here INTO B ISRO INTO PROCESSING B ESRI PROCESSING INT2 B ISR2 INT2 PROCESSING Space 16 16 RESERVED TIME TIN B TIME IMER INTERRUP PROCESSING RINT B RCV SERIAL PORT RECEIVE PROCESSING XINT B XMT SERIAL PORT TRANSMIT PROCESSING USER B PROC RAP VECTOR PROCESSING THE BRANCH INSTRUCTION AT LOCATION 0 DIRECTS EXECUTION TO BEGIN HERE FOR RESET PROCESSING INITIALIZE THE PROCESSOR WHEN RESET IS APPLIED THE FOLLOW I CONDITIONS ARE ESTABLISHED FOR THE STATUS AND OTHER INTERNAL REGISTER IN THIS EXAMPLE THE BRANCH INCLUDES THAT THE ARP IS SET TO 7 THE AUXILIARY REGISTIER POINTER IS NOT SET FROM RESET 5 4 Software Applications Processor Initialization ARP OV OVM 1 STO TTI 0 X 1 1 ARB SX
7. FF Xx TABLER LARP AR3 LRLK AR3 380 RPTK 127 TBLR DESTINATION ADDRESS PAGE 7 TRANSFER 128 VALUES MOVE DATA INTO DATA RAM RETURN TO CALLING PROGRAM 4 4 In cases where systems require that temporary storage be allocated in the pro gram memory TBLW can be used to transfer data from internal data memory to external program memory The code in Example 5 17 demonstrates how to do this Example 5 17 Moving Internal Data Memory to Program Memory With TBLW THIS ROUTINE USES THE TBLW INSTRUCTION TO MOVE DATA VALUES FROM INTERNAL DATA MEMORY TO EXTERNAL PROGRAM MEMORY THE CALLING ROUTINE MUST SPECIFY THE DESTINATION PROGRAM MEMORY ADDRESS IN THE ACCUMULATOR ASSUME THAT THE ACCUMULATOR CONTAINS THE ADDRESS IN PROGRAM MEMORY INTO WHICH THE DATA 15 TRANSFERRED TABLEW LARP AR4 LRLK AR4 380 SOURCE ADDRESS PAGE 7 RPTK 127 TRANSFER 128 VALUES TBLW MOVE DATA EXTERNAL PROGRAM RAM RE RETURN TO CALLING PROGRAM The IN and OUT instructions are used to transfer data between the data memory and the I O space as shown in Example 5 18 and Example 5 19 Example 5 18 Moving Data From I O Space Into Data Memory With IN
8. 5 74 c vices te senting bbs Een EP UE REN ES DECR erated emake eae 5 79 An o Point BT EE E eco crono iunt Di I 5 81 PID Control xsv Lc weet tae ine et Sa rug MEN VAN AREE 5 83 xxi xxii Table of Contents Chapter 3 Architecture The architectural design of the TMS320C2x emphasizes overall system speed communication and flexibility in processor configuration Control sig nals and instructions provide block memory transfers communication to slow er off chip devices and multiprocessing implementations Single cycle multi ply accumulate instructions two large on chip RAM Blocks eight auxiliary registers with a dedicated arithmetic unit a serial port a hardware timer and a faster I O for data intensive signal processing are features that increase throughput for DSP applications The TMS320C26 is similar to the TMS320C25 except for its internal memory configuration This is discussed in Section 3 4 and in Appendix B Topics in this chapter include Topic Page 3 4 Architectural Overview 3 2 3 2 Functional Block Diagram 3 6 3 3 Internal Hardware Summary 3 9 3 4 Memory Organization 531357 3 12 3 5 Central Arithmetic Logic Unit CALU 3 28 3 6 System Control 222222222222 22222 22222 3 35
9. 6 36 Interface of TMS320C25 to TCM29C16 6 38 Interface of TLC32040 to TMS320C2x 6 41 Synchronous Timing of TLC32040 to 5320 2 6 41 Asynchronous Timing of TLC32040 to 5 320 2 6 42 Interface of TLC7524 to 5320 2 6 42 Interface Timing of TLC7524 to 5320 2 6 43 Interface of TLC0820 to 5 320 2 6 44 Interface Timing of TLC0820 to 5320 2 6 45 l O Port Addressing 24 tse acinus SA ute bp I ICE D er 6 46 I O Port Processor to Processor Communication 6 47 Echo Ganceler actes ct e Ar LL cca race 6 48 High Speed Modem 6 49 Voice Coding System 6 49 Graphics System 6 50 Robot Axis Controller Subsystem 6 51 Instrumentation 2 222 6 51 EPROM Programming Adapter
10. 6 42 6 5 4 Analog to Digital A D Interface 6 43 65 05 E vy re Ks tec c son 6 46 6 6 System Applications 6 48 6 6 1 scs seve pe Ren PES 6 48 6 6 2 High Speed Modem 6 48 6 6 3 Voice Coding be cede Wi eat 6 49 6 6 4 Graphics and Image Processing 6 50 6 6 5 High Speed 1 6 51 6 6 6 Instrumentation and Numeric Processing 6 51 xiii Contents O gt TMS320C25 Digital Signal Processors A 1 TMS320C26 Digital Signal B 1 TMS320C28 Digital Signal C 1 SMJ320C2x Digital Signal Processors D 1 Instruction Cycle Timings E 1 TMSS320C2x Instruction Cycle Timings E 2 TMS320E25 EPROM Programming F 1 F 1 Using the EPRO
11. 3 42 Pipeline With External Data Bus Conflict 3 43 Pipeline Operation of Branch to On Chip RAM 3 44 Pipeline Operation of RET From On Chip RAM 3 44 TMS320C2x Status Register Organization 3 49 TMS320C26 Status Register Organization 3 50 Timer Block Diagram 1 3 52 Four Phase CIoCK eese ebe da ve BERE Pe Salad Saad d cus 3 56 BIO TimingrDIagraim eere re Edu eee eee 3 57 External Flag Timing Diagram 3 58 Interrupt Mask Register IMR 3 60 Internal Interrupt Logic 3 61 Interrupt Timing Diagram 5320 25 3 62 The DRR DXR Registers 3 64 Serial Port Block Diagram 3 65 Serial Port Transmit Timing 3 66 Serial Port Receive Timing Diagram 3 67 XV Figures 3 37 3 38 3 39 3 40 3 41 3 42 3 43 3 44 3 45 3 46 3 47
12. F 2 Vcc Vpp Jumper Settings for External F 3 EPROM Programming Data Format F 4 TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout F 5 FAST Programming Flowchart F 9 SNAP Pulse Programming Flowchart F 10 Programming Timing 11 EPROM Protection F 13 How the RBIT Fits Into the TMS320E25 Block Diagrams F 14 EPROM Protection Timing F 15 System Block G 2 Multimedia Speech Encoding and Modem Communication G 3 TMS320C25 to TLC32047 Interface 1 G 3 Typical DSP Combo G 6 DSP Combo Interface Timing G 7 General Telecom Applications G 9 Generic Telecom Application G 9 Generic Servo Control Loop G 12 Disk Drive Con
13. 3 22 PM Shift Modes Aidan Dosis Mined s De rer Re deans 3 33 Instruction Pipeline Sequence 3 40 Status Register Field Definitions 3 50 Interrupt Locations and Priorities 3 59 Serial Port Bits Pins and Registers 3 63 Global Data Memory Configurations 3 77 Indirect Addressing Arithmetic Operations 4 6 Bit Fields for Indirect Addressing 4 7 Instruction Symbols 4 12 Instruction Set Summary 4 14 Program Space and Time Requirements for u A Law Companding 5 69 256 Tap Adaptive Filtering Memory Space and Time Requirements 5 74 Bit Reversal Algorithm for an 8 Point Radix 2 DIT 5 77 FFT Memory Space and Time Requirements 5 81 Timing Parameters of TBP38L 165 35 Direct Interface to 5320 25 6 15 Timing Parameters of TBP38L165 35 to TMS320C25 Address Decoding 6 19 Wait States Required for Memory Peripheral
14. X 7 8000 0000 1 TFFF FFFE 8000 0 0 0 0 ACC X 8000 0000 F F F 8000 0 0 0 1 To E a ee 0000 0000 1 FF FF ACC 0 ADDC o 000 0000 0001 1 0000 0000 8000 ACC 1 8000 0000 00 7 0000 ADH 8 0 1 FF 5 63 Advanced Arithmetic Operations Example 5 39 shows an implementation of two 64 bit numbers added to each other to obtain a 64 bit result This example adds 32 bit parts and generates a carry C bit in the accumulator Example 5 39 64 Bit Addition TWO 64 BIT NUMBERS ARE ADDED TO EACH OTHER PRODUCING A 64 BIT RESULT THE NUMBERS X X3 X2 X1 X0 AND Y Y3 Y2 Y1 Y0 ARE ADDED RESULTING IN W W3 W2 W1 WO0 X3 X2 X1 X0 Y2 Y1 YO ee ee ene 3 W2 W1 WO ADD64 ZALH X1 ACC X1 00 ADDS X0 ACC X0 ADDS YO ACC X1 XO 00 YO Y1 ACC XO Y1 YO W1 WO SACL WO SAC 1 ZALH X3 ACC X3 00 ADDC X2 X3 X2 C ADDS Y2 ACC X3 X2 00 Y2 ADDH Y3 ACC X3 X2 Y2 C W3 W2 SACL W2 SACH W3 RE 5 64 As in addition the carry bit on the TMS320C25 is reset whenever the input scaling shifter or the P register value subtracted from the accumulator con tents generates a borrow into bit 31 Otherwise
15. 5 27 Computed GOTO xs arate aia pattie aati 5 28 Context Save 6320 25 5 30 Context Restore TMS320C25 5 31 Interrupt Service 5 32 Moving External Data to Internal Data Memory With BLKD 5 33 Moving Program Memory to Data Memory With BLKP 5 33 Moving Program Memory to Data Memory With 5 34 Moving Internal Data Memory to Program Memory With 5 34 Moving Data From I O Space Into Data Memory With IN 5 34 Moving Data From Data Memory to I O Space With 5 35 Configuring and Using On Chip RAM 5 37 Program Execution From On Chip Memory 5 39 Program Execution From On Chip Memory 5320 26 5 41 Using BIT and merenti ecl 5 45 Using BITT and BBNZ 1 2 7 7 2 5 45 Bit Reversed Carry Addition 5 48 FET Bit Reversals eed ere ero e es er te Ere 5 48 Using the ARO Test Bit to Calculate the Square Root of
16. 6 14 Interface Timing of TBP38L165 35 to TMS320C25 6 15 Interface of TBP38L 165 35 to 5320 25 6 17 Interface Timing of TBP38L 165 35 to TMS320C25 Address Decoding 6 18 One Wait State Memory Access Timing 6 20 Wait State Generator Design 6 21 Wait State Generator Timing 6 22 Interface of WS57C65F 12 to TMS320C25 6 23 Interface Timing of WS57C65F 12 to TMS320C25 6 24 Interface of TMS27C64 20 to TMS320C25 6 25 Interface Timing of TMS27C64 20 to 5320 25 6 26 Interface of CY7C169 25 to 5320 25 6 28 Interface Timing of CY7C169 25 to TMS320C25 6 29 Table of Contents Lg C CTI CTI CTI CTI 0009000 PUNIO TT N Figures Direct Memory Access Using a Master Slave 6 33 Direct Memory Access a PC Environment 6 34 Global Memory Communication
17. 5 IF SIGN IS POSITIVE LH NEGAT QUOTIENT IF NEGATIVE RETUR TO MAIN PROGRAM Example 5 35 Using SUBC for Fractional Division THIS ROUTINE IMPLEM DN1 DON ral LT MPY PAC SACH LAC ABS SACL ZALH ABS IF denominator AND numerator ARE NUMERA D D N IO IO IO I D JHO ENOM EMSGN ENOM ENOM UMERA ENOM EMSGN ONE UOT UOT UOT 5 GET SIGN QUOTII SAVE AL DIVISION NT SIGN OF QUOTIENT MAKE DENO ALIGN NUMERATOR ALIGNED DIVISION 15 CYCL DONE E DIVIDE LOOP INATOR POSITIVE BI CAN START HERE IF SIGN IS POSITIVE Gl NEGAT QUOTIENT IF NEGATIVE RETUR TO MAIN PROGRAM 5 59 Advanced Arithmetic Operations 5 6 7 Floating Point Arithmetic 5 60 Floating point numbers are often represented on microprocessors in a two word format of mantissa and exponent The mantissa is stored in one word The exponent the second word indicates how many bit positions from the left the decimal point is located If the mantissa is 16 bits a 4 bit exponent is suffi cient to express the location of the decimal point Because of its 16 bit word size the 16 4 bit floating point f
18. Interrupts The effects of an interrupt become apparent on the hardware when a interrupt acknowledge IACK signal is valid on the rising edge of CLKOUT2 This signifies the fetch of the first word of the interrupt vector If wait states are generated in the memory segment where the interrupt vector re sides an additional pulse occurs for each wait state added If this causes a problem with the external interface IACK can be gated with READY to ac cept only the last interrupt acknowledge pulse Note that the BIOZ instruction tests the level of the BIO pin during the instruction fetch phase of the pipeline Hold Hold Acknowledge The hold operation like that of interrupt takes se cond priority to algorithm execution therefore the hold will not be acknowl edged until after the currently running instruction is completed a minimum of three cycles This includes repeated instructions The next instruction after the final instruction executed before HOLDA is latched into the pipeline and executed two cycles after the HOLDA line goes inactive high The second instruction after the last instruction executed is fetched two cycles again after the HOLDA line goes inactive high If the HM bit of status register ST1 is set high the TMS320C25 stops execution and sits idle until the hold is removed This lowers power consumption by removing the drive of the memory address and control lines and also stopping major parts
19. 2 1 2 4 TMSS320C2x PinoutS 2 2 2 2 2 TMS320C2x Signal 2 4 cer enr 3 1 3 1 Architectural Overview 3 2 3 2 Functional Block 3 6 3 3 Internal Hardware Summary 3 9 3 4 Memory Organization 3 12 3 41 DAME urere at re tete nen E e oso d 3 12 34 2 Program Memory teretes eie 3 12 3 43 TMS320C2x Memory Maps 3 15 3 44 TMS320C26 Memory Maps 3 16 3 45 Memory Mapped Registers 3 22 3 4 6 Auxiliary Registers 3 22 3 4 4 Memory Addressing Modes 3 25 3 4 8 Memory to Memory Moves 3 27 3 5 Central Arithmetic Logic Unit 3 28 Scaling Shiller us Bb eB CPG 3 30 3 5 2 ALU and
20. QoOoooaononzim 9 o lt cg 1 5 CLKOUT1 CLKOUT2 HOLDA DX FSX X2 CLKIN 05 44 SS OS T See Pin Assignments Table Page 2 and Pin Nomenclature Table Page 3 for location and description of all pins PGA LCCC JLCC PIN ASSIGNMENTS voc maa E 5 Running Title Attribute Reference L3 29 K3 30 14 31 K4 32 L5 33 K5 34 K6 36 L7 37 K7 38 L8 39 14 15 BR CLKOUT1 CLKOUT2 CLKR CLKX Do D1 110 43 7 68 11 50 11 58 010 57 9 64 9 63 1 18 2 17 K10 45 E11 54 J2 25 F10 53 A7 67 E10 55 B11 60 G1 20 62 21 6 1 10 59 4 10 47 8 66 8 65 11 48 10 49 2 19 10 61 10 62 X2 CLKIN Appendix Title Attribute Reference 1 10 K11 44 L2 27 D11 56 G10 51 F11 52 Running Title Attribute Reference PIN NOMENCLATURE wwe wozt 5 V supply pins Ground pins Output from internal oscillator for crystal X2 CLKIN Input to internal oscillator from crystal or external clock CLKOUT1 Master clock output crystal or CLKIN frequency 4 CLKOUT2 A second clock output signal D15 DO 16 bit data bus D15 MSB through DO LSB Multiplexed between program data and spaces A15 A0 16 bit address bus A15 MSB through AO LSB PS DS IS Program data and I O space select signals RW Read write signal STRB Strobe signal
21. 3 30 3 5 3 Multiplier T and P Registers 3 32 3 67 System aera ae 3 35 3 6 1 Program Counter and Stack 3 35 3 6 2 Pipeline Operation 3 37 376 3 ROSU arenae 3 47 6 4 Status Registers One edP in 3 49 23 65 Timer Operation Mae er META aw RETE 3 52 3 6 0 Repeat Counter 3 53 3 6 7 Powerdown Modes TMS320C25 3 53 3 7 External Memory and I O Interface 3 54 3 7 4 Memory Combinations 3 54 3 7 2 Internal Clock Timing Relationships 3 56 3 7 8 General Purpose I O Pins BIO and 3 56 xi Contents xii ex SEE ocn ES ee 3 59 3 8 1 Interrupt Operation 3 59 3 8 2 External Interrupt Interface 3 60 3 92 5 5 use tm eus sede A tds edith ky od EA ste oka ad 3 63 3 9 1 Transmit and Receive Operations 3 65 3 9 2 Timing and Framin
22. GREG 0005h 1111 1111 0000 0000 RESERVED RINT TINT INT2 INTO MR 1111111111 X X X X X X text INIT ROVM DISABLE OVERFLOW MODE LDPK 0 POIN DP REGISTER TO DATA PAGE 0 LARP T POINT TO AUXILIARY REGISTER 7 LACK 3Fh LOAD ACCUMULATOR WITH 3Fh SACL 4 ENABLE ALL INTERRUPTS VIA IMR INTERNAL DATA MEMORY INITIALIZATION 5 3 Processor Initialization ZAC ZERO THE ACCUMULATOR LARK 7 60 POINT TO BLOCK B2 RPTK 31 SACL STORE ZERO IN ALL 32 LOCATIONS LRLK 7 200 POINT TO BLOCK BO RPTK 255 SACL ZERO ALL OF PAGES 4 AND 5 LRLK 7 300 POINT TO BLOCK Bl RPTK 255 SACL ZERO ALL OF PAGES 6 AND 7 THE PROCESSOR IS INITIALIZED THE REMAINING APPLICATION DEPENDENT PART OF THE SYSTEM BOTH ON AND OFF CHIP SHOULD NOW BE INITIALIZED ENABLE ALL INTERRUPTS Example 5 2 Processor Initialization TMS320C26 title INIT26 title 5320 26 PROCESSOR INITIALIZATION width 100 option x def RESET INTO INT1 INT2 def INT RINT XINT USER ref ISRO ISR1 ISR2 ref IME RCV XMT PROC Ls RESET AND INTERRUPT VECTOR SPECIFICATION BRANCHES FOR EXTERNAL AND INTERNAL INTERRUPTS
23. td MSC XY VALID uo h C2H id C2H R F ta C2H R XXX ARR VCC CONC OOO OMI KK AKI RR td M R tn M R DATA IN RRIA NR RAN Figure 7 One Wait State Memory Access Timing E 43 Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 tsun H tars I tsu IN RS I t tn IN ee 7 hsc tw RS SEN FETCH PKK KKK LOCATION 0 D15 D0 SRK KKK Se p PS PN 9 9 EXECUTION _ L Y XXXX X SIGNALST 555550500500 SEED XD xD xD xD IIRI ORY LACK ARK A SERIAL PORT XXXXXXXXXKKKK KKK KK KEK XXX KY CONTROLS XXXXX XR S RKTT 1 Control signals are DS IS R W and t Serial port controls are DX and FSX E 44 Appendix Title Attribute Reference Running Title Attribute Reference Figure 8 Reset Timing En cm c mm tsuIN th IN tw N INT2 INTO N tf IN 15 0 FETCH FETCHN 1 FETCHN 2 FETCH 1 gt td IACK ta IACK e 9 66666 ROXXXX XY NOX YY x X NM V VN YY VY AER RL
24. td C1 C2 k be Figure 4 Clock Timing E 40 Appendix Title Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB R W READY D15 D0 Running Title Attribute Reference am ta c1 S gt lt lt lg C1 S gt Ne 7 gt td C2 S td C2 S Z IN 4 tw SL tw SH gt tsu A 4 4 th A QO Xr 0 sl ms x ta A td SL R XX 50050005000 lt gt th SL R gt lsu DR Xo 50090505000 th D R l DATA IN Figure 5 Memory Read Timing E 41 Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 EE MEE 3d CLKOUT2 N N STRB N N PE RE tsu A th A A15 A0 Or PR POR 5 VB SU R W KRY vov ERY OER tsu D W 17 D15 D0 S DATAOUT 55 tenp tdis D gt Figure 6 Memory Write Timing 42 Appendix Title Attribute Reference CLKOUT1 CLKOUT2 READY D15 DO FOR READ OPERATION D15 DO FOR WRITE OPERATION MSC Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION th C2H R He ta MSC I th M R ta m R zg 77
25. Notes 3 Nis the program memory location for the current instruction 4 This example shows only the execution of single cycle instructions fetched from external program memory 3 82 Architecture General Description of the TMS320C26 3 11 General Description of the TMS320C26 The TMS320C26 is a spin off of the TMS320C25 It is processed in CMOS technology is capable of an instruction cycle time of 100 ns and is pin for pin and object code compatible with the TMS320C25 with the exception of the instructions for on chip memory configuration The TMS320C26 s enhance ment over the TMS320C25 is basically the larger on chip RAM see the block diagram in Figure 3 3 divided into 4 blocks with 1568 words altogether The three blocks B1 and B3 each with 512 x 16 bits are configurable as data or program memory The block B2 with 32 x 16 bits is identical with the same block of the TMS320C25 and is usable as data memory The ROM of the TMS320C26 consists of 256 words with a factory programmed bootloader In many applications the large internal memory of the TMS320C26 allows you to build single chip solutions with all data and programs internal and the option to reload programs or algorithms A memory size of 1568 words allows the TMS320C26 to handle a data array of for example 1024 words with an on chip program RAM of 512 words and additional 32 words of data RAM When using internal blocks as program memor
26. high to CLKOUT1 CLKOUT2 STRB high low CLKOUT1 CLKOUT2 STRB fall time CLKOUT1 CLKOUT2 STRB rise time tw CL CLKOUT1 CLKOUT low pulse duration 20 8 20 20 8 tw CH 0 2 high pulse duration 20 8 20 20 8 id C1 C2 high to CLKOUT2 low CLKOUT high to CLKOUT1 high etc 0 6 Q 6 T This parameter is not production tested NOTE 1 1 46 E 35 Running Title Attribute Reference timing requirements over recommended operating conditions see Note 1 CLKIN cycle time tw CIL CLKIN low pulse duration 25 ns see Note 2 tw CIH CLKIN high pulse duration 25 ns see Note 2 tsu S SYNC setup time before CLKIN low this SYNC hold time from CLKIN low NOTES 1 Q 1 4tc C 2 CLKIN duty cycle tw CIH l tc c1 must be within 40 60 CLKIN rise and fall times must be less than 5 ns A From Output Under Test o Point 1 CL 80 pF E 36 Appendix Title Attribute Reference Running Title Attribute Reference Figure 2 Test Load Circuit 90 MIN 0 a Input 24V 2 2V 0 8 V RES VoL MAX b Outputs Figure 3 Voltage Reference Levels MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions see Note 1 td C1 S STRB from CLKOUT1 if STRB is present Era E TEC A s
27. p 08000 0c000n 0 000 0 000 OF800h OFCOOh OFEOOh OFFOOh OFFFFh OFFFFh OFFFFh OFFFFh OFFFFh OFFFFh OFFFFh OFFFFh When a data memory address either direct or indirect corresponds to a global data memory address as defined by GREG BR is asserted low with DS to indicate that the processor wishes to make a global memory access External logic then arbitrates for control of the global memory asserting READY when the TMS320C2x has control The length of the memory cycle is controlled by the READY line One wait state timing is shown in Figure 3 47 Note that all signals not shown have the same timing as in the normal read or write case Figure 3 47 Global Memory Access Timing CLKOUT1 P MELLE e e db nho O e A15 A0 RO Valid OY BR DS LOOP BR D RO 55 91 MERC 77 0000000000000 READY SSN 5 SS 3 78 Architecture Multiprocessing and Direct Memory Access 3 10 3 The Hold Function The TMS320C2x supports direct memory access DMA to its local off chip program data and I O spaces Two signals HOLD and HOLDA are provided to allow another device to take control of the processor s buses Upon receiv ing a HOLD signal from an external device the processor acknowledges by bringing HOLDA low The processor then places its address and data buses as wel
28. This provides three choices or Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this directive is byte value valuey This syntax shows that byte must have at least one value parameter but you have the option of supplying additional value parameters separated by commas Information about Cautions This book may contain cautions caution describes a situation that could potentially damage your software or equipment This is what a caution looks like The information in a caution is provided for your protection Please read each caution carefully vi Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments General Digital Signal Processing Antoniou Andreas Digital Filters Analysis and Design New York NY McGraw Hill Company Inc 1979 Brigham E Oran The Fast Fourier Transform Englewood Cliffs Nu Prentice Hall Inc 1974 Burrus C S and Parks T W DFT FFT and Convolution Algorithms New York NY John Wiley and Sons Inc 1984 Digital Signal Processing Applications with the 5320 Family Texas Instruments 1986 Prentice Hall Inc 1987 Gold Bernard and Rader C M Digital Processing of Signals New York NY McGraw Hill Compan
29. ees rT INT2 INTO N 15 0 execute Notes 1 Nis the program memory location for the current instruction 2 lis the interrupt vector location in program memory for the active interrupt 3 For simplicity this example shows only the execution of single cycle instructions fetched from external program memory rather than multicycle instructions Three dummy execute cycles occur on an interrupt as shownin the timing dia gram for the TMS320C25 Figure 3 32 The IACK signal is asserted low dur ing CLKOUT1 low when the device initiates a fetch from the interrupt location Note that is a valid signal only when CLKOUT1 is low An external de vice can determine which interrupt had occurred by latching the address bus value present on A4 A1 with the rising edge of CLKOUT2 when IACK is low 3 63 Serial Port 3 9 Serial Port A full duplex on chip serial port provides direct communication with serial de vices such as codecs serial A D converters and other serial systems The in terface signals are compatible with codecs and many other serial devices with a minimum of external hardware The serial port may also be used for inter communication between processors in multiprocessing applications Both receive and transmit operations are double buffered on the TMS320C2x thus allowing a continuous bit stream even if FSX is an output The use of the frame
30. x x ob ab Application Oriented Operations EFFICIENTS TION X ASSUME THAT title ADAPTIVE FILTER def ADPFIR def X Y THIS 256 TAP ADAPTIVE FIR FILTER USES ON CHIP MEMORY BLOCK BO FOR AND BLOCK B1 FOR DATA SAMPLES EWES INPUT SHOULD B IN MEMORY WHEN CALLED THE OUTPUT WILL BE I EMORY LOCATION Y WHE RETURNED THE DATA PAGE IS 0 WHEN THE ROUTINE IS CALLED OEFFP set OFFOOh B0 PROGRA EMORY ADDRESS OEFFD set 0200h BO DATA MEMORY ADDRESS NE set 7Ah CONSTANT ONE DP 0 ETA set 7Bh ADAPTATION CONSTANT DP 0 RR set 7Ch SIGNAL ERROR DP 0 RRF set 7Dh ERROR FUNCTION DP 0 set 7Eh FILTER OUTPUT DP 0 set 7Fh NEWEST DATA SAMPLE DP 0 RSTAP set 0300h NEXT NEWEST DATA SAMPLE ASTAP set O3FFh OLDES DATA SAMPLE IMPULSE RESPONSE FIR FILTER DPFIR CNFP CONFIGURE BO AS PROGRAM 0 Clear the register LAC ONE 14 Load output rounding bit LARP AR3 LRLK AR3 LASTAP Point to the oldest sample IR RPTK 255 ACD COEFFP 256 tap FIR filter
31. 0 Port Address 1 See Section 4 1 The IN instruction reads 16 bit value from one of the external I O ports into the specified data memory location The IS line goes low to indicate an I O ac cess and the STRB R W and READY timings are the same as for an external data memory read Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ni IN STAT PA5 Read in word from peripheral on port address 5 Store in data memory location STAT or LRLK 1 520 Load AR1 with decimal 520 LARP 1 Load ARP with decimal 520 IN PA1 0 Read in word from peripheral on port address l Store in data memory location 520 Decrement AR1 to 519 Load the ARP with 0 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Load Accumulator With Shift LAC Direct label LAC shift Indirect abel LAC ind shift next ARP 0 lt lt 127 0 lt ARP lt 7 0 lt shift lt 15 defaults to 0 PC 1 5 PC dma x 2 shift ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affected by SXM 15 14 13 12 11 10 9 8 7 6 0 0 1 0 Shift 5 4 3 2 1 0 Indirect o 0 1 0 See Section 4 1 The contents of the specified data memory address are left shifted and loaded into the accumulator During shi
32. 2048 0800h EXTERNAL 65535 FFFFh DATA 0100000 MMRs 5 0005h 6 0006h RESERVED 95 005Fh 96 0060h BLOCK 2 127 007Fh 128 0080h RESERVED 511 01FFh 512 0200h BLOCK BO 1023 03FFh 1024 0400h BLOCK B1 1535 05FFh 1536 0600h ON CHIP BLOCK B3 2047 07FFh 0 15 0 1 3 4 7 8 11 12 15 16 511 WWW DATA 0100005 ON CHIP MMRs 5 0005h 6 0006h RESERVED 95 005Fh 96 0060h BLOCK B2 127 007Fh 128 0080h RESERVED 511 01FFh 512 0200h ECHIP BLOCK BO 1023 03FFh 1024 0400h OREEHIP BLOCK B1 1535 05FFh 1536 0600h ON CHIP BLOCK B3 2047 07FFh 0 15 0 1 3 4 7 8 11 12 15 16 511 w Running Title Attribute Reference Figure 1A Memory Maps E 14 Appendix Title Attribute Reference MEMORY MAPS AFTER 1 1 MP MC 1 PROGRAM 0 0000h INTERRUPTS AND RESERVED EXTERNAL 31 001Fh 32 0020h EXTERNAL 63999 F9FFh 64000 ON CHIP BLOCK BO 64511 FBFFh 64512 65023 FDFFh 65024 00 65535 FFFFh 2 MP MC 0 PROGRAM 0 0000h INTERRUPTS AND RESERVED BOOTLOAD ROM 255 00FFh 256 0100h RESERVED 4095 OFFFh 4096 1000h EXTERNAL 63999 F9FFh 64000 FAO0h
33. 6 11 6 3 Direct Memory Access DMA 6 32 642 5 6 35 6 5 Interfacing Peripherals 6 37 6 6 5 eee ee eee ee er ieee seer 6 48 6 1 System Control Circuitry 6 1 System Control Circuitry The system control circuitry performs functions that are critical for proper sys tem initialization and operation A powerup reset circuit design and a crystal oscillator circuit design are presented in this chapter The powerup reset circuit assures that a reset of the part occurs only after the oscillator is running and stabilized This oscillator circuit allows the use of third overtone crystals which are readily available at frequencies above 20 MHz Fora more detailed discus sion of system control circuitry refer to the application report Hardware Inter facing to the TMS320C25 literature number SPRAO144 6 1 1 Powerup Reset Circuit 6 2 The reset circuit shown in Figure 6 1 performs a powerup reset that is the TMS320C2x is reset when power is applied Note that the switch circuit must include debounce circuitry Driving the RS signal low initializes the processor Reset affects several registers and status bits see subsection 3 6 2 for a de tailed description of the effect of reset on processor status LL 1 Note Reset does not ha
34. X1 00 X1 X0 ACC X1 X0 00 YO ACC X1 X0 Y1 YO W1 WO e 0 n lt e ACL WO ALS X2 00 X2 gt gt Dp Q a N K 29 02 23 X3 X2 Y2 0 UJ lt N 5 65 Advanced Arithmetic Operations The second feature of the TMS320C25 that assists extended precision cal culations is the MPYU unsigned multiply instruction The MPYU instruction allows two unsigned 16 bit numbers to be multiplied and the 32 bit result to be placed in the product register in a single cycle Efficiency is gained by generat ing partial products from the 16 bit portions of a 32 bit or larger value instead of having to split the value into 15 bit or smaller parts Example 5 41 shows the implementation of multiplying two 32 bit numbers to obtain a 64 bit result The advantage in using the MPYU instruction can be ob served when executed on the TMS320C25 Example 5 41 32 x 32 Bit Multiplication TWO 32 BIT NUMBERS ARE MULTIPLIED PRODUCING A 64 BIT RESULT THE NUMBERS X X1 X0 AND Y Y1 Y0 ARE MULTIPLIED RESULTING IN W W3 W2 W1 WO0 X1 X0 1 0 X0 YO X1 YO X0 Y1 X1 Y1 pee W3 W2 W1 wo DETERMINE THE SIGN OF THE PRODUCT MPY32 ZAL
35. In syntax descriptions the instruction command or directive is in a bold typeface font and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown portions of a syntax that are in italics describe the type of information that should be entered Here is an example of a directive syntax asect section name address asect is the directive This directive has two parameters indicated by section name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of an instruction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit constant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets are actually part of the pathname they are not optional Style and Symbol Conventions Braces and indicatealist The symbol read as or separates items within the list Here s an example of a list
36. Indirect 0 1 1 1 1 1 0 0 See Section 4 1 The low order bits of the P register shifted as specified by the PM bits are stored in data memory Neither the P register nor the accumulator are affected by this instruction High order bits are taken from the high P register when the right shift by 6 mode is selected Low order bits are zero filled when left shifts are selected Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SPL DAT3 DP 4 PM 2 or SPL If current auxiliary register contains 515 Before Instruction After Instruction P OFE079844h P 0 079844 Data Data Memory 4567h Memory 9844h 515 515 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Set P Register Output Shift Mode SPM label SPM constant 0 lt constant lt 3 PC 1 PC Constant product register shift mode PM status bits Affects PM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NENDEONEREENEEXENGEEZN The two low order bits of the instruction word are copied into the PM field of status register ST1 The PM status bits control the P register output shifter This shifter has the ability to shift the P register output either one or four bits tothe left or six bits to the right orto perform no shift The bit combinations and their meanings are shown below PM ACTION 00 No shift of mul
37. 2 2 Table external memory 3 n np 3 2n nd 2 2 2 2 4 112 Assembly Language Instructions Example SPM LARP LRLK RPTK IAC 1 1 768 255 Multiply and Accumulate Select a shift right by 6 mode on PR output on PR output Configure block as program memory OFFXXh Use 1 to address block Bl Point to lowest location in RAM block B1 Compute 256 sum of product operations OFF00h Multiply accumulate and increment AR1 The following example shows register and memory contents before and after the third step repeat loop AR1 RPT PC PFC Data Memory 770 Program Memory 65282 P ACC Before Instruction After Instruction 302h AR1 303h OFDh RPT OFCh OFFO2h PC PFC OFFO3h Data 770 Program OFAAAh Memory OFAAAh 65282 458972h P OFFFF453Eh 723EC41h ACC o 7250266h C 4 113 MACD Multiply and Accumulate With Data Move Syntax Direct label MACD Indirect label MACD ind next ARP Operands 0 pma lt 65535 0 lt dma lt 127 0 lt next ARP lt 7 Execution 5320 25 2 2 PC gt MCS gt If repeat counter 0 Then ACC shifted register ACC dma gt T register dma x addressed by PFC register dma dma 1 Modify AR ARP and ARP as specified PFC
38. 6 20 Timing Parameters of WS57C64F 12 Interface to 5320 25 6 24 Timing Parameters of TMS27C64 20 Interface to 5320 25 6 26 Timing Parameters of CY7C169 25 Interface to TMS320C25 6 27 TMS320C2x Instructions by Cycle Class E 2 Cycle Timings for Cycle Classes When Not in Repeat Mode E 3 Cycle Timings for Cycle Classes When in Repeat E 5 Pin Nomenclature 5320 25 F 5 TMS320E25 Programming Mode Levels F 6 TMS320E25 EPROM Protect and Protect Verify Mode F 12 Data Converter CS ur sss unr Gilded temer dete aite id atero guna INO xd G 4 Switched Capacitor Filter ICS G 4 Telecom Devices cere ERE Rp aeu Rex Rd EA FR e ER G 8 Switched Capacitor Filter ICs G 8 Table of Contents LT90o0oodoQ ZONO A TT N Tables Voice Synthesizers sa asiu iiaa a Rede bate E E e iras G 10 Speech Memories G 10 Switched Capacitor Filter G 11 Control Related Devices G 13
39. Auxiliary register pointer buffer Whenever the ARP is loaded the old ARP value is copied to the ARB except during an LST instruction When the ARB is loaded via an LST1 instruction the same value is also copied to the ARP Auxiliary register pointer This three bit field selects the AR to be used in indi rect addressing When ARP is loaded the old ARP value is copied to the ARB register ARP may be modified by memory reference instructions when us ing indirect addressing and by the LARP MAR and LST instructions ARP is also loaded with the same value as ARB when an LST1 instruction is executed Carry bit This bit is set to 1 if the result of an addition generates a carry or reset to 0 if the result of a subtraction generates a borrow Otherwise it is re Set after an addition or set after a subtraction except if the instruction is ADDH or SUBH ADDH can only set and SUBH only reset the carry bit but cannot affect it otherwise These instructions will also affect this bit SC RC LST1 shift and rotate Two branch instructions BC and BNC have been provided to branch on the status of C C is set to 1 on a reset On chip ram configuration control bit If set to 0 block BO is configured as data memory otherwise block is configured as program memory CNF may be modified by the CNFD CNFP and LST1 instructions RS resets the to 0 Data memory page pointer The 9 bit DP register is concatenated with the 7 LS
40. Slides and Printing G 1 1 System Design Considerations G 2 Multimedia systems can include various grades of audio and video quality The most popular video standard currently used VGA covers 640 x 480 pixels with 1 2 4 and 8 bit memory mapped color Also 24 bit true color is sup ported and 1024 x 768 beyond VGA resolution has emerged There are two grades of audio The lower grade accommodates 11 25 kHz sampling for 8 bit monaural systems while the higher grade accommodates 44 1 kHz sampling for 16 bit stereo Audio specifications include a musical instrument digital interface MIDI with compression capability which is based on keystroke encoding and an input output port with a 3 disc voice synthesizer In the media control area video disc CD audio and CD ROM player interfaces are included Figure G 2 shows a multimedia subsystem Analog Interface Peripherals and Applications Figure G 2 Multimedia Applications The TLC32047 wide band analog interface circuit AIC is well suited for multi media applications because it features wide band audio and up to 25 kHz sampling rates TLC32047 is a complete analog to digital and digital to analog interface system for the TMS320 DSPs The nominal bandwidths of the filters accommodate 11 4 kHz and this bandwidth is programmable The application circuit shown in Figure G 2 handles both speech encoding and modem communication functions which are associated with mu
41. THIS ROUTINE USES THE IN INSTRUCTION TO MOVE DATA VALUES FROM THE SPAC INTO DATA MEMORY DATA ACCESSED FROM I O PORT 15 IS TRANSFERRED TO SUCCESSIV MEMORY LOCATIONS ON DATA PAGE 5 INPUT LARP AR2 Tj Lu AR2 2C0h DESTINATION ADDRESS PAGE 5 RPTK 63 TRANSFER 64 VALUES IN PA15 MOVE DATA INTO DATA RAM RE RETURN TO CALLING PROGRAM 5 34 Software Applications Memory Management Example 5 19 Moving Data From Data Memory to I O Space With OUT THIS ROUTINE USES THE OUT INSTRUCTION TO MOVE DATA VALUES FROM THE DATA MEMORY TO THE I O SPACE DATA IS TRANSFERRED TO I O PORT 8 FROM SUCCESSIVE MEMORY LOCATIONS ON DATA PAGE 4 OUTPUT LARP ARA LRLK AR4 200h SOURCE ADDRESS PAGE 4 RPTK 63 TRANSFER 64 VALUES OUT PA8 MOVE DATA FROM DATA RAM RE RETUR CALLING PROGRAM 5 4 2 Configuring On Chip RAM TMS320C2x The large amount of external memory and the configurability of on chip RAM simplify the downloading of data or program memory into the TMS320C2x Also since data in the RAM is preserved when redefining on chip RAM block BO can be configured dynamically as either data or program memory Figure 5 9 illustrates the changes in on chip RAM when switching
42. 0 0 0000h 255 00FFh 256 0100h 4095 OFFFh 4096 1000h 63999 F9FFh 64000 FA00h 64511 FBFFh 64512 65023 FDFFh 65024 00 65535 FFFFh PROGRAM INTERRUPTS AND RESERVED EXTERNAL EXTERNAL ON CHIP BLOCK BO ON CHIP BLOCK B1 ON CHIP BLOCK B3 PROGRAM INTERRUPTS AND RESERVED BOOTLOAD ROM RESERVED EXTERNAL ON CHIP BLOCK BO ON CHIP BLOCK B1 ON CHIP BLOCK B3 0 0000h 5 0005h 6 0006h 95 005Fh 96 0060h 127 007Fh 128 0080h 511 01FFh 512 0200h 1023 03FFh 1024 0400h 1535 05FFh 1536 0600h 2047 07FFh 2048 0800h 65535 FFFFh 0 0000h 5 0005h 6 0006h 95 005Fh 96 0060h 127 007Fh 128 0080h 511 01FFh 512 0200h 1023 03FFh 1024 0400h 1535 05FFh 1536 0600h 2047 07FFh 2048 0800h 65535 FFFFh Running Title Attribute Reference DATA ON CHIP MMRs RESERVED ON CHIP BLOCK B2 RESERVED DOES NOT EXIST DOES NOT EXIST DOES NOT EXIST DATA ON CHIP MMRs RESERVED ON CHIP BLOCK B2 RESERVED DOES NOT EXIST DOES NOT EXIST DOES NOT EXIST EXTERNAL w Nn 15 0 1 3 4 7 8 11 12 15 16 511 15 0 1 3 4 7 8 11 12 15 16 511 y o EXTERNAL y o EXTERNAL E 19
43. 0 8 LOAD LENGTH OF FFT IN ARO LRLK AR1 200h LOAD AR1 WITH DATA PAGE 4 ADDRESS LARP AR1 RPTK 7 IN 0 ONLY REAL VALUED INPUT 1ST 6 2ND STAGES COMBINED WITH DIVIDE BY 4 INTERSTAGE SCALING COMBO XOR XOI X1R X11 X2R X21 X3R X31 COMBO X4R X41 X5R X51 X6R X61 X7R X71 3RD STAGE WITH DIVIDE BY 2 INTERSTAGE SCALING ZERO XOR XOI PIBY4 X1R X1I X5R X5I W PIBY2 X2R X21 X6R X61 PI3BY4 X3R X3I X7R X7I W OUTPUT SAMPLES SUPPLYING IN SEQUENTIAL ORDER LRLK AR1 200h LOAD AR1 WITH DATA PAGE 4 ADDRESS RPTK T5 OUT PAO COMPLEX VALUED OUTPUT RE Table 5 4 shows execution speed program memory and data memory for an 8 point DIT FFT implementation using the TMS320C25 Table 5 4 FFT Memory Space and Time Requirements Words In Memory CPU Cycles Time Data Program us TMS320C25 17 153 178 17 8 5 81 Application Oriented Operations 5 7 5 PID Control 5 82 Control systems are concerned with regulating a process and achieving de sired behavior or output from the process A control system consists of three main components sensors actuators and a controller Sensors measure the behavior of the system Actuators supply the driving force to ensure the de sired behavior The controller generates actuator commands corresponding to the error conditions observed by the sensors and the
44. 1 PFC repeat counter 1 repeat counter Else ACC shifted register gt dma register dma x addressed by PFC register dma gt dma 1 Modify AR ARP and ARP as specified MCS 2 Affects C and OV affected by OVM and PM Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 0 1 0 1 1 1 0 0 E Data Memory Address Program Memory Address Indirect 0 1 0 1 1 1 0 0 See Section 4 1 Program Memory Address Description The MACD instruction multiplies a data memory value specified by dma by a program memory value specified by pma It also adds the previous product shifted as defined by the PM status bits to the accumulator The data and program memory locations on the TMS320C25 may be any non reserved on chip or off chip memory locations If the program memory is block BO of on chip RAM then the bit must be set to one Note that the upper eight bits of the program memory address should be setto OFFh in order 4 114 Assembly Language Instructions Multiply and Accumulate With Data Move MACD to address BO program RAM and the upper six bits of dma should be set to 0 to address a location below 1024 When used in the direct addressing mode the dma cannot be modified during repetition of the instruction If MACD ad dresses one of the memory mapped registers or external memory as a data memory location the effect of the instruction will be that of a MAC
45. 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SG Carry bit C is set to logic one Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Shift Accumulator Left SFL label SFL None 1 31 gt C 30 0 2 ACC 31 1 0 0 Affects C Not affected by SXM bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 The SFL instruction shifts the entire accumulator left one bit The least signifi cant bit is filled with a zero On the TMS320C2x the most significant bit is shifted into the carry bit C Note that SFL unlike SFR is unaffected by SXM 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SFL Before Instruction After Instruction ACC 0B0001234h ACC 060002468h C 4 157 Shift Accumulator Right Syntax Operands Execution Encoding Description Words Cycles Example 1 Example 2 4 158 label SFR None 1 PC If SXM 0 Then ACC 0 gt C ACC 31 1 ACC 30 0 and 0 2 ACC 31 If SXM 1 Then ACC 0 gt C ACC 31 1 gt 30 0 and ACC 31 gt ACC 31 Affects C Affected by SXM bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 The SFR i
46. 1 Digital Ground E 74AS04 inverter Figure 6 3 provides the 180 degree phase shift that a parallel oscillator requires The 4 7 kQ resistor provides the negative feed back that keeps the oscillator in a stable state that is the poles of the system are constrained in a narrow region about the jw axis of the s plane analog do main The 10 kQ potentiometer is used to bias the 74AS04 in the linear re gion In a third overtone oscillator the crystal fundamental frequency must be atte nuated so that oscillation is at the third harmonic This is achieved with an LC circuit that filters out the fundamental The impedance of the LC network must be inductive below and capacitive above the second harmonic The impedance of the LC circuit is given by L z o Therefore the LC circuit has a pole at sl 6 5 System Control Circuitry At frequencies significantly lower than p the 1 w C term in 3 becomes the dominating term while oL can be neglected This gives 2 joL foro lt lt o 5 In 5 the LC circuit appears inductive at frequencies lower than On the other hand at frequencies much higher than the oL term is the dominant term in 3 and 1 C can be neglected This gives 1 Z w jac foro gt gt op 6 The LC circuit in 6 appears increasingly capacitive as frequency increases above This is shown in Figure 6
47. Before Instruction After Instruction ACC 0B0001234h ACC 060002469h C C 4 141 ROR Rotate Accumulator Right Syntax Operands Execution Encoding Description Words Cycles Example 4 142 label ROR None 1 PC ACC 0 gt C 31 1 gt 30 0 before ROR 31 Affects Not affected by SXM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 The ROR instruction rotates the accumulator right one bit The LSB is shifted into the carry bit and the value of the carry bit from before the execution of the instruction is shifted into the MSB 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ROR Before Instruction After Instruction ACC o 0B0001234h ACC o 5800091 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Reset Overflow Mode ROVM label ROVM None 1 PC 0 gt status bit in status register STO Affects OVM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 The OVM status bit is reset to logic zero which disables the overflow mode If an overflow occurs with OVM reset the OV overflow flag is set and the overflowed result is placed in the accumulator OVM may also be loaded by the LST and SOVM instructions 1 Cycle
48. Example Store High P Register SPH Direct label SPH dma Indirect label SPH ind next ARP 0 dma x 127 0 lt next ARP lt 7 PC 1 PC PR shifter output 31 16 dma Affected by PM 15 14 13 1 7 6 5 4 3 2 1 0 2 11 10 9 8 Direct 9 1 1 1 1 0 1 Data Memory Address Indirect 1 1 1 1 1 0 1 See Section 4 1 The high order bits of the P register shifted as specified by the PM bits are stored in data memory Neither the P register nor the accumulator are affected by this instruction High order bits are sign extended when the right shift by 6 mode is selected Low order bits are taken from the low P register when left shifts are selected Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SPH DAT3 DP 4 PM 2 or SPH If current auxiliary register contains 515 Before Instruction After Instruction P OFE079844h OFE079844h Data Data Memory 4567h Memory 0E079h 515 515 4 163 SPL Store Low P Register Syntax Operands Execution Encoding Description Words Cycles Example 4 164 Direct label SPL dma Indirect label SPL ind next ARP 0 dma x 127 0 lt next ARP x 7 1 5 PC PR shifter output 15 0 gt dma Affected by PM 15 14 13 12 11 10 9 8 7 6 0 1 1 1 1 1 0 0 5 4 3 2 1 0
49. Execution Encoding Description Words Cycles Example 4 74 label CMPR constant 0 lt lt 3 PC 1 PC Compare AR ARP to ARO placing result in TC bit of status register ST1 Affects TC Not affected by SXM does not affect SXM The CMPR instruction performs the following comparisons dependent on the value of CM If CM 00 test if AR ARP ARO If CM 01 test if AR ARP lt ARO If CM 10 test if AR ARP gt ARO If CM 11 test if AR ARP ARO If the result of a test is true one is loaded into the TC status bit Otherwise TC is loaded with a zero The auxiliary registers are treated as unsigned inte gers in the comparison 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Before Instruction After Instruction ARO OFFFFh ARO OFFFFh AR4 7FFFh AR4 7FFFh re Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Configure Block as Data Memory CNFD label None PC 1 PC 0 RAM configuration control status bit Affects CNF On chip RAM block 0 is configured as data memory The block is mapped to locations 512 through 767 in data memory This instruction is the complement of the CNFP instruction and sets the CNF bit in status register ST1 to a zero is also loaded by the CNFP and LST1 instructions On the
50. LOAD ACCUMULATOR WITH EXPONENT BZ OUT CHECK FOR ZERO EXPONENT LT LACT DENORMALIZE NUMBER RE RETURN TO MAIN PROGRA OUT POINT TO MANTISSA ZALH LOAD ACCUMULATOR WITH RESULT RE RETURN TO MAIN PROGRA 5 61 Advanced Arithmetic Operations 5 6 8 Indexed Addressing The auxiliary register arithmetic unit ARAU makes it possible to calculate the next indirect address by increment decrement or by indexed addressing in parallel to the current arithmetic operation For example in the multiplication of two matrices the operation requires addressing across the rows incre menting the address by one or down the columns incrementing by n Example 5 38 gives the code for multiplying a row times a column of two 10x10 matrices The first matrix resides in data RAM block B1 and the second matrix resides in block BO Example 5 38 Row Times Column LARK LARP LRLK 2 0 0 25 INDEX 10 1 FOR ADDRESSING THE COLUMN 1 300h POINT AR1 TO THE START OF BLOCK B1 SET 0 TO PROG ADDRESS FOR PIPELINE INITIALIZE THE ACCUMULATOR 0 CLEAR THE PRODUCT REGISTER 9 REPEAT 10 TIMES AS MATRIX DIMENSION OFFOOh 0 ULTIPLY ROW TIMES COLUMN EXECUTE FINAL ACCUMULATION ACCUMULATOR CONT
51. Note that when considered in the absolute sense timings such as will have some finite tolerance although considerably less than that specified For example if STRB is used to generate a WE pulse for a device that specifies a minimum WE low pulse width the data sheet specification for STRB low pulse width must be used for a worst case design When you design a multiwait state generator and use the CLKOUT1 and CLKOUT2 signals for sequencing a state machine specifications t C2H R and t C2H R must be met Note that these signals are measured from CLKOUT2 If you design a single wait state you can logically combine MSC with the address and memory strobes to generate READY In the latter the pa rameters tg M R and must be met In either case both sets of param eters are tested and guaranteed Note thattq MSC is also a parameter As such tg MSC is given to locate MSC with respect to CLKOUT1 and CLKOUT for a multiwait state design In this case it would be inappropriate to relate the READY timing requirements from the CLKOUT1 signal when considering a single wait state generated directly from MSC 6 31 Direct Memory Access DMA 6 3 Direct Memory Access DMA 6 32 Some advanced hardware design concepts supported by the TMS320C2x in clude direct memory access DMA and global memory see Section 6 4 Di rect memory access can be used for multiprocessing by temporarily halting the execution
52. TAG External Memory and I O Interface NO TAG NO TAG oer perce NO TAG Serial Portos NO TAG NO TAG Multiprocessing and Direct Memory Access DMA NO TAG NO TAG General Description of the TMS320C26 NO TAG NO TAG General Description of the TMS320C28 NO TAG 3 1 Architectural Overview 3 1 Architectural Overview 3 2 Harvard Architecture The TMS320C2x high performance digital signal pro cessors like the TMS320C1x devices implement a Harvard type architecture that maximizes processing power by maintaining two separate memory bus structures program and data for full speed execution Instructions are in cluded to provide data transfers between the two spaces Externally the pro gram and data memory can be multiplexed over the same bus so as to maxi mize the address range for both spaces while minimizing the pin count of the device On Chip Memory The TMS320C25 provides increased flexibility in system design by two large on chip data RAM blocks a total of 544 16 bit words one of which is configurable either as program or data memory see Figure 3 1 The 5320 26 provides three large on chip RAM blocks configurable ei ther as separate program and data spaces or as three continuous data blocks to provide increased flexibility in system design An off chip 64K word directly addressable data
53. input on FSX for transmit operations and on FSR for receive operations Architecture Serial Port The transmit timing diagram is shown in Figure 3 35 The transmit operation begins when data is written into the data transmit register DXR The TMS320C2x begins transmitting data when the frame synchronization pulse FSX goes low while CLKX is high or going high The data starting with the MSB is then shifted out via the DX pin with the rising edge of CLKX When all bits have been transmitted an internal transmit interrupt XINT is generated on the rising edge of CLKX When the serial port is not transmitting DX is placed in the high impedance state Figure 3 35 Serial Port Transmit Timing Diagram E amp i 2 FSX TXM 1 DX PONE E CON D NE EE MSB LSB 4 8 16 Bits DX and FSX unaffected by assertion of the HOLD input Upon assertion of HOLD any serial port transmission in progress on the DX pin is completed before DX is placed in the high impedance state FSX remains configured as either an input or output remaining low if it is an output The receive operation is similar to the transmit operation The receive timing diagram is shown in Figure 3 36 Reception is initiated by a frame synchro nization pulse on the FSR pin After FSR goes low data on the DR pin is clocked into the RSR register on the TMS320C25 o
54. is defined by loading an 8 bit counter RPTC repeat counter If this repeat feature is used the instruction is executed and the RPTC is decremented until the RPTC goes to zero This feature is useful with many instructions such as NORM normalize contents of accumulator MACD multiply and accumulate with data move and SUBC conditional sub tract When used with some multicycle instructions such as MACD the re peat features can result in these instructions effectively executing in a single cycle The stack is 16 bits wide and eight levels deep The PC stack is accessible through the use of the PUSH and POP instructions Whenever the contents of the PC are pushed onto the top of the stack the previous contents of each level are pushed down and the bottom eighth location of the stack is lost Therefore data will be lost if more than eight successive pushes occur before a pop The reverse happens on pop operations Any pop after seven sequen tial pops yields the value at the bottom stack level All of the stack levels then contain the same value Two additional instructions PSHD and POPD push a data memory value onto the stack or pop a value from the stack to data memory These instructions allow a stack to be built in data memory for the nesting of subroutines interrupts beyond four eight levels Note that on the TMS320C2x the TBLR TBLW MAC MACD and BLKD BLKP instructions use a separate stack MCS microcall stack no level of
55. label BBZ pma ind next ARP 0 lt pma lt 65536 0 lt next ARP x 7 If test control TC status bit 0 Then pma PC Else PC 2 Modify AR ARP and ARP as specified Affected by TC bit 15 14 13 12 11 10 9 8 7 1 1 1 1 1 0 0 0 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address if TC 0 Otherwise con trol passes to the next instruction No AR or ARP modification occurrs if noth ing is speciified in those fields The pma can be either a symbolic or a numeric address Note that the TC bit is affected by the BIT BITT LST1 NORM RTC and STC instructions 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 2 2p Destination on chip ROM 3 3 3 2p Destination external memory 3 p 3 p 343p 3 p 3 p False Condition Destination anywhere 2 2 242p 2 2 Cycle Timings for a Repeat Execution not repeatable BBZ PRG325 If TC 0 325 is loaded into the program counter otherwise the program counter incremented by 2 4 47 Branch on Carry Syntax Operands Execution Encoding Description Words Cycles Example 4 48 label BC pma f ind next ARP 0 lt pma lt 65536 0 lt next ARP x 7 If carry bit C 1 Then pma PC Else PC 2 5 PC
56. 16 A BRANCH INSTRUCTION AT PROGRAM MEMORY LOCATION 0 DIRECTS PROCESSOR EXECUTION HERE INIT ROV DISABLE OVERFLOW MODE LDPK 0 POINT DP REGISTER TO DATA MEMORY PAGE 0 LOAD TIME CRITICAL CODE FROM EXTERNAL SOW MEMORY TO INTERNAL RAM LRLK AR1 PROGR POINT AR1 INTO RECONFIGURABLE BLOCK BO RPTK PROGL 1 LOAD REPEAT COUNTER WITH BLOCK LENGTH BLKP P1 START MOVE CODE FROM PROGRAM MEMORY TO ON CHIP RAM INITIALIZE PARAMETERS FOR EXECUTION LDPK 8 POL DP REGISTER TO DATA MEMORY PAGE 8 LACK 1 SET ACCUMULATOR TO 0001n SACL ONE STORE VALUE OF 1 LRLK AR1 COEFF 2 POI AR1 TO INTERNAL MEMORY ADDRESS RPTK COEFL 1 REPEAT COUNTER WITH BLOCK LENGTH CONF 1 BLOCKBO PROGRAMMEMORY B1 B3 DATAMEMORY B LPTS BRANCH TO ON CHIP EXECUTION ADDRESS SIGNAL PROCESSING CODE TO BE EXECUTED FROM ON CHIP RAM asect ONCHIP PGMBO PROG LABEL P1 START LPTS BIOZ GE WAIT FOR SIGNAL LOW B LPTS BRANCH IF SIGNAL HIGH GE OUT FILOUT PA2 OUTPUT LAST FILTER OUTPUT IN FILIN PA2 INPUT NEW SIGNAL SAMPLE LRLK AR1 SIGNAL POI AR1 TO SIGNAL DATA TO PROCESS ZAC CLEAR HE ACCUMULATOR 0 CLEAR THE P REGISITER RPTK 145 REPEAT MACD INSTRUCTION FOR 16 TAPS MACD COEF MULTIPLY ACCUMULATE SAMPLE DELAY APAC Accumulate the last product SACH FILOUT 1 Save the result B LPTS Loop to wait for next sample PROGE label P1 END PROGL equ PROGE PROG Program code lenth Coefficie
57. 3 7 TMS320C26 Block Diagram 3 8 TMS320C2x On Chip Data Memory 3 13 TMS320C26 On Chip Data Memory 3 14 Comparison of Internal RAM Configured as Data Space 3 18 Comparison of Internal RAM Configured as Program Space 3 18 TMS320C2x Memory Maps 3 19 TMS320C26 Memory Maps 3 20 Indirect Auxiliary Register Addressing Example 3 23 Auxiliary Register File 3 24 Methods of Instruction Operand Addressing 3 26 Central Arithmetic Logic Unit CALU 5320 2 3 29 Examples of TMS320C25 Carry Bit Operation 3 31 Program Counter Stack and Related Hardware 3 35 Three Level Pipeline Operation TMS320C25 3 38 Two Level Pipeline 3 38 TMS320C25 Standard Pipeline Operation 3 39 Pipeline Operation of ADD Followed by SACL 3 41 Pipeline Operation With Wait States
58. ACC Affected by PM 15 14 13 12 11 10 9 8 7 Direct 6 5 4 3 2 1 0 0 0 1 1 1 1 1 0 ER Data Memory Address Indirect 1 1 1 1 1 0 See Section 4 1 The T register is loaded with the contents of the addressed data memory loca tion and the product register is stored in the accumulator The shift at the out put of the product register is controlled by the PM status bits a Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution DAT36 DP 6 PM 0 TP If current auxiliary register contains 804 Before Instruction After Instruction Data Data Memory 62h Memory 62h 804 804 T 3h T 62h C C Assembly Language Instructions Load Register and Subtract Previous Product LTS Syntax Direct label LTS dma Indirect label LTS ind next ARP Operands 0 lt lt 127 0 next ARP lt 7 Execution PC 1 gt PC dma register ACC shifted register Affects OV affected by and OVM Affects C Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 0 1 1 o 1 1 Data Memory Address Indirect 0 1 0 1 1 o 1 1 See Section 4 1 Description The T register is loaded with the contents of the addressed data memory loca tion The contents of the product register shifted as defined by the contents of the PM status bits are subtracted from the accumulator The result is left in the accumu
59. CNFD CONFIGURE 5 DATA APAC SACH 1 Store the filter output NEG ADD X55 Add the newest input SACH ERR 1 E rr i x i y i LMS ADAPTATION OF FILTER COEFFICIENTS LT ERR MPY BETA PAC errf i beta err i ADD ONE 14 ROUND THE RESULT SACH ERRF 1 MAR X INCLUDE EWEST SAMPLE SACL AR2 COEFFD POI O THE COEFFICIENTS AR3 LASTAP POL THE DATA SAMPLES iT ERRF MPY AR2 P 2 beta err i x i 255 5 73 Application Oriented Operations Example 5 44 Adaptive Filter Routine Concluded ADAPT ZALR AR3 MPYA AR2 LOAD ACCH WITH b255 i amp ROUND b255 i 1 b255 i P 2 beta err i x i 254 STORE b255 i 1 4 4 Ne Ne SACH ZALR AR3 MPYA AR2 LOAD ACCH WITH b254 i amp ROUND b254 i 1 b254 i P 2 beta err i x i 253 STORE b254 i 1 SACH ZALR AR3 LOAD ACCH WITH b253 i ROUND MPYA AR2 iedo2523X Xr ww 1 5 B253 1 P P 2 beta err i x i 252 SACH STORE b253 i 1 ZALR AR3 LOAD ACCH WITH bl i amp ROUND MPYA AR2 bl i 1 bl i P P 2 beta err i x i 0 SACH I STORER GL ti lh ZALR LOAD ACCH WITH 0 1 amp ROUND APAC bO i 1 bO i P SACH STORE bO i 1 RE RETURN TO CALLING ROUTINE Table 5 2 provides data memory program memory and
60. Example ADD DAT1 3 DP 10 or ADD 3 If current auxiliary register contains 1281 Before Instruction After Instruction Data Data 1281 1281 e EL e C 4 26 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example 1 Add to Accumulator With Carry ADDC Direct label ADDC dma Indirect label ADDC ind next ARP 0 dma x127 0 lt next ARP x 7 PC 4 15 PC dma C gt ACC Affects OV and C affected by OVM 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 A Direct 0 0 0 0 0 0 1 1 Data Memory Address Indirect 0 1 0 0 0 0 1 1 See Section 4 1 The contents ofthe addressed data memory location and the value of the carry bit are added to the accumulator The carry bit is then affected in the normal manner The ADDC instruction can be used in performing multiple precision arithmetic 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ADDC DAT5 8 or ADDC If current auxiliary register contains 1029 Before Instruction After Instruction Data Data 1029 1029 e B 4 27 ADDC Aad to Accumulator With Carry Example 2 ADDC DAT5 DP 8 or ADDC If current auxiliary register contains 1029 Before Instruction After Instruction Data Data 1029 1029 ACC OFFFFFFFFh ACC 4 28 Assembly Language Instructi
61. Ko e n 1 Ka 2 This algorithm is implemented in Example 5 47 Software Applications Application Oriented Operations Example 5 47 PID Control title PID CONTROL def PID THIS ROUTINE IMPLEMENTS PID ALGORITHM UN set 0 OUTPUT OF CONTROLLER E set 1 LATES ERROR SAMPLE E 2 PREVIOUS ERROR SAMPLE E set 3 OLDES ERROR SAMPLE K1 set 4 GAIN CONSTAN K2 set 5 GAIN CONSTAN K3 set 6 GAIN CONSTAN text ASSUME DATA PAGE 0 IS SELECTED PID I 0 0 READ NEW ERROR SAMPLE LAC UN ACC u n 1 E2 LOAD T REG WITH OLDEST SAMPLE MPY K2 P K2 e n 2 TD El s ACG ug gt 1 w K2 e n 2 MPY K1 P Kl e n 1 TD EO ACC u n 1 Kl e n 1 K2 e n 2 MPY KO P KO e n APAC ACC u n 1 KO e n Kl e n 1 K2 e n 2 SACH UN 1 2 STORE OUTPUT OUT UN 1 SEND IT The PID loop takes 13 cycles to execute 1 3 us at a 40 MHz clock rate The TMS320 can also be used to implement more sophisticated algorithms such as state modeling adaptive control state estimation Kalman filtering and op timal control Other functions that can be implemented are noise filtering sta bility analysis and additional control loops 5 83 5 84 Software Applications Chapter 6 H
62. PBUS from the MUX that combines the internal data bus DBUS to create the external program data bus This disconnect takes place at the MUX For the TMS320E25 the internal nodes are left floating Figure 9 shows a portion ofthe TMS320C2x block diagram and includes the RBIT to show how it disconnects the external and internal program spaces Figure 9 How the RBIT Fits Into the TMS320E25 Block Diagrams 4K x 16 M program EPROM External 4 we Program Data Bus S Data Bus S 16 x 16 Multiplier Program Bus PREG Programming the RBIT has some side effects that may at first give the ap pearance that the device isn t operating properly However because enabling the RBIT protects the EPROM space this is normal operation These side ef fects include Instructions Some instructions that use the external program space for storage will not operate in the same manner when the RBIT is set For example on the TMS320E25 TBLW BLKP and similar commands may seem to work when used to transfer external program memory to the internal data space connected to DBUS However a transfer from the in ternal program space to the external bus will not work This happens be cause the RBIT feature is protecting this memory space Similarly the MAC instruction cannot read tables stored in external pro gram space In this case the data and program must be swapped sacrific ing one cycle pe
63. PC 8 bit constant auxiliary register AR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The 8 bit positive constant is loaded into the designated auxiliary register AR right justified and zero filled that is sign extension suppressed LARK is useful for loading an initial loop counter value into an auxiliary register for use with the BANZ instruction 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE p quos po 30 Cycle Timings for a Repeat Execution not repeatable LARK ARO 15 Before Instruction After Instruction Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Load Auxiliary Register Pointer LARP label LARP constant 0 constant lt 7 PC 1 PC ARP 2 ARB Constant ARP Affects ARP and ARB The auxiliary register pointer is loaded with the contents of the three LSBs of the instruction a 3 bit constant identifying the desired auxiliary register The old ARP is copied to the ARB field of status register ST1 ARP can also be mo dified by the LST LST1 and MAR instructions as well as any instruction that is used in the indirect addressing mode The LARP instruction is a subset of MAR that is the opcode is the same as MAR in the indirect addressing mode The following instruction has the same effect as LARP MAR constant Cycle Timings for a Single Ins
64. Serial port data receive register TIM Timer STO ST Status registers DXR Serial port data transmit register TR Temporary register Carry bit 3 6 Architecture Functional Block Diagram Figure 3 2 TMS320C25 E25 Block Diagram Program Bus ds DS X22 PS ogg X Xxoo Ha 8 e RETE E 9lelol amp sioi SIZ elsi 16 TNT 3 Program 1 2 0 ROM 16 16 EPROM A15 AQ 4096 X 16 RBIT 16 015 0 lt 116 116 16 Multiplier T 32 32 6 0 1 4 16 1 32 7 LSB From IR Shifter 0 16 ARP 3 3 3 Block B2 DATA PROG 32 X 16 RAM 256 X 16 Data RAM Block BO Block 1 256 X 16 Data Bus NOTE Shaded areas indicate a bus 3 7 Functional Block Diagram Figure 3 3 TMS320C26 Block Diagram Program Bus X2 CLKIN CLKOUT1 CLKOUT2 a INT 2 0 15 0 16 16 15 Bootload Program ROM 256 X 16 1 16 16 16 16 5 16 19 ARO 16 3 promi gt DP 9 Multipli AR3 16 n Shifter 0 16 ARA 16 43 ARB 16 6 16 7 16 16 v ji ARB 3 i Shifter 6 0 1 4 Fao RAM 32 X 16 Blo
65. Syntax Operands Execution Encoding Description Words Cycles Example Multiply Immediate MPYK label MPYK constant 4096 lt constant lt 4095 212 lt constant lt 212 1 PC 1 PC T register x constant gt P register Not affected by SXM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 i EN MEN 13 Bit Constant The contents ofthe T register are multiplied by the signed 13 bit constant The result is loaded into the P register The immediate field is right justified and sign extended before multiplication regardless of SXM 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable MPYK 9 Before Instruction After Instruction 7h 7h 4 4 2Ah OFFFFFFC1h 4 121 MPYS Multiply and Subtract Previous Product Syntax Direct label MPYS dma Indirect label MPYS ind next ARP Operands 0 lt lt 127 0 lt next ARP lt 7 Execution 1 PC ACC shifted P register gt ACC T register x dma P register Affects C and OV affected by OVM and PM Encoding 15 14 13 1 7 6 5 4 3 2 1 0 2 11 10 9 8 Direct 0 0 1 1 14 0 1 1 Data Memory Address Indirect 1 1 1 0 1 1 See Section 4 1 Description The contents of the T register are multiplied by the contents of the addressed data memory location The result is placed in the P register The previous prod u
66. Telex 92 7708 H 3 Crystals H 3 Crystals This section lists the commonly used crystal frequencies crystal specification requirements and the names of suitable vendors Table 1 1 lists the commonly used crystal frequencies and the devices with which they can be used Table 1 Commonly Used Crystal Frequencies 5320 25 40 96 2 When connected across X1 and X2 CLKIN of the TMS320 processor acrystal enables the internal oscillator see Figure F 1 The frequency of CLKOUT is one fourth the crystal fundamental frequency Crystal specification require ments are listed below Load capacitance 20 pF Series resistance 30 ohm Power dissipation 1 mW Parallel resonant crystals of 20 MHz and below use fundamental mode 25 MHz operation may require a third overtone crystal 40 MHz operation requires a third overtone crystal Figure H 1 Crystal Connection H 4 Crystal 27 B The TMS320C25 operating at 40 96 MHz requires a parallel resonant third overtone oscillator see subsection 6 1 2 for a detailed description of this oscil lator design If a packed clock oscillator is used oscillator design is of no con cern Memories Analog Converters Sockets and Crystals Crystals Vendors of crystals suitable for use with TMS320 devices are listed below RXD Inc Norfolk NB 800 228 8108 N E L Frequency Controls Inc Burlington WI 414 763 3591 CTS Knight Inc Contact the
67. Words Cycles Example 4 126 label NOP None PC 1 PC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 No operation is performed The NOP instruction affects only the PC NOP functions in the same manner as the MAR instruction in the direct addressing mode has the same opcode as MAR in the direct addressing mode with 0 The NOP instruction is useful as a pad or temporary instruction during program development 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution NOP Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Normalize Contents of Accumulator NORM label NORM ind TMS320C25 None TMS320C25 PC 1 5 PC If ACC 0 Then 1 gt TC Else if ACC 31 30 0 Then 0 gt ACC x 2 gt Modify AR ARP as specified Else 1 gt TC Affects TC 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 1 Modify AR 0 0 1 0 The NORM instruction is provided for normalizing a signed number that is con tained in the accumulator Normalizing a fixed point number separates it into a mantissa and an exponent To do this the magnitude of a sign extended number must be found ACC bit 31 is exclusive ORed with ACC bit 30 to deter mine if bit 30 is part of the magnitude or part of the sign extension If
68. constant lt 511 PC 1 PC Constant data memory page pointer DP status bits Affects DP 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 The DP data memory page pointer register is loaded with a 9 bit constant The DP and 7 bit data memory address are concatenated to form 16 bit direct data memory addresses DP gt 8 specifies external data memory DP 4 through 7 specifies on chip RAM blocks or B1 Block B2 is located in the upper 32 words of page 0 DP may also be loaded by the LST and LDP instruc tions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable LDPK 64 The data page pointer is set to 64 4 95 LPH Load High P Register Syntax Operands Execution Encoding Description Words Cycles Example 4 96 Direct label LPH Indirect label LPH ind next ARP 0 dma x127 0 x next ARP lt 7 PC 1 PC dma P register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 Data Memory Address Indirect 0 1 0 1 0 01 1 See Section 4 1 E A The P register high order bits are loaded with the contents of data memory The low order P register bits are unaffected The LPH instruction is particularly useful for restoring the high order bits of the P register after subroutine calls or interrupts Cycle Timings for a Single Instruction PI
69. 0000100010000000 0000000100010000 0000100001000000 0000001000010000 0000100011000000 0000001100010000 0000100000100000 0000010000010000 0000100010100000 0000010100010000 0000100001100000 0000011000010000 0000100011100000 0000011100010000 0000100000010000 0000100000010000 Bit Reversed carry gt gt Normal carry 5 48 Software Applications Advanced Arithmetic Operations Bit reversed carry addition is effective as a logical shifter that does not use the accumulator in any way Here are some other applications Suppose you want to do a decimation in frequency FFT In this case the DFT block size decreases by one half for every stage of the FFT When finished the DFT block size will be two and the address will be offset by one If you use a BANZ Not_done BRO excess code is eliminated in a tightly looped and reasonably efficient FFT Also the value of ARO can be used at the same time to access a bit reversed twiddle table lookup The advantage here is that the same lookup table will work for any size FFT smaller than the overall size of the table permits Inanother application ARO can be loaded with a single bit This bit is then shifted during each pass through the main loop and used as a test bit This testis a successive approximation approach to calculating the square root of a 32 bit integer Example 5 27 shows what the code will look like Compare this to the same algorithm in subsection 5 2 1 5 49 Advanc
70. 2 Emulator User s Guide literature number SPDUO55 The emulator architecture works closely with the user s system design to allow the user s memory to have maximum access times Areas of close interaction between the emulator and target system are Bus control READY timing and memory substitution Reset and hold Miscellaneous considerations Bus Control When the emulator is halted from the keyboard or any of the breakpoint func tions the current state of the device being emulated is extracted by the control processor This processor communicates with the emulated device over the emulated device s data bus Additional communication is generated by com mands entered from the keyboard Before communication between the control processor and the device being emulated begins the control processor generates an interlock sequence on the emulated device s HOLD input in order to define data bus ownership the target HOLD is deactivated this interlock prevents the target system from receiving an active HOLDA until the emulator has completed accessing the processor resources The emulator will not attempt to use the data bus until the interlock is successful thus guaranteeing that it will not try to use the data bus when HOLDA is asserted to the target system When communication between the control processor and the device being emulated is complete the hold interlock is released and the target syst
71. 30 0 constant x 2shift gt 30 0 ACC 31 gt 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Bit Constant The left shifted 16 bit immediate constant is exclusive ORed with the accumu lator leaving the result in the accumulator Low order bits below and high or der bits above the shifted value are treated as zeros thus not affecting the cor responding bits of the accumulator Note that the MSB most significant bit of the accumulator is not affected regardless of the shift code value 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable XORK OFFFFh 8 Before Instruction After Instruction ACC 012345678h ACC 12CBA978h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Zero Accumulator ZAC label ZAC None PC 1 PC 0 lt ACC 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 doc id 0 0 1 0 1 000 00 0 0 0 0 The contents of the accumulator are replaced with zero The ZAC instruction has been implemented as a special case of LACK ZAC assembles as LACK 0 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable ZAC Before Instruction After Instruction C C 4 191 ZALH Zero Low Accumulator and Load High Accumulator Syntax Direct
72. 4 or ADDT If current auxiliary register contains 639 Before Instruction After Instruction Data Data Memory 9h Memory 9h 639 639 OFF94h OFF94h ee eme C 4 35 ADLK Adad to Accumulator Long Immediate With Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 36 label ADLK constant shift 16 bit constant 0 lt shift lt 15 defaults to 0 PC 25 PC ACC constant x 2 Shift ACC If SXM 1 Then 32768 lt constant lt 32767 If SXM 0 Then 0 lt constant lt 65535 Affects OV affected by OVM and SXM Affects C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Bit Constant The 16 bit immediate value left shifted as specified is added to the accumu lator The result replaces the accumulator contents SXM determines whether the constant is treated as a signed 2s complement number or as an unsigned number The shift count is optional and defaults to zero 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable ADLK 5 8 Before Instruction After Instruction es cmm Assembly Language Instructions Add to Auxiliary Register Short Immediate ADRK Syntax label ADRK constant Operands 0 constant lt 255 Execution PC 1 5 PC AR ARP 8 bit positive constant gt AR ARP Encoding 15 14 13 12 10 9 8 7 6 5 4
73. 4 132 POP 4 133 POPD 4 134 PSHD 4 135 PUSH 4 136 RC 4 137 RET 4 138 RFSM 4 139 RHM 4 140 ROL 4 141 ROR 4 142 ROVM 4 143 RPT 4 144 RPTK 4 145 RSXM 4 146 RTC 4 147 RTXM 4 148 RXF 4 149 SACH 4 150 SACL 4 151 SAR 4 152 SBLK 4 154 SBRK 4 155 SC 4 156 SFL 4 157 SFR 4 158 SFSM 4 159 SHM 4 160 SOVM 4 161 SPAC 4 162 SPH 4 163 SPL 4 164 SPM 4 165 SQRA 4 166 SQRS 4 167 SST 4 168 SST1 4 170 SSXM 4 172 STC 4 173 STXM 4 174 SUB 4 175 SUBB 4 176 SUBC 4 177 SUBH 4 179 SUBK 4 180 SUBS 4 181 SUBT 4 182 SXF 4 183 instruction set continued 4 11 TBLR 4 184 TBLW 4 186 TRAP 4 188 XOR 4 189 XORK 4 190 ZAC 4 191 ZALH 4 192 ZALR 4 193 ZALS 4 194 instruction set summary 4 13 4 17 special groups 4 13 instructions accumulator 4 14 auxiliary register page pointer 4 15 branch call 4 16 control 4 17 and memory 4 16 individual descriptions 4 18 4 194 register and multiply 4 15 instrumentation 6 51 interface AIC 6 40 6 42 analog to digital A D 6 43 6 45 combo codec 6 37 6 40 digital to analog D A 6 42 interface timing analysis 6 29 6 31 interfacing memories 6 11 EPROMs 6 22 6 26 port buses and control signals 6 11 PROMs 6 12 6 19 read and write cycles 6 12 SRAMs 6 26 6 29 timing analysis 6 29 6 31 wait state generator 6 19 interfacing peripherals 6 37 interfacing PROMs address decoding 6 12 6 19 internal hardware 3 9 3 11 inte
74. 4 171 SSXM Set Sign Extension Mode Syntax Operands Execution Encoding Description Words Cycles Example 4 172 label SSXM None PC 1 gt PC 1 gt SXM status bit in status register ST1 Affects SXM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 The SSXM instruction sets the SXM status bit to logic 1 which enables sign extension on shifted data memory values for the following arithmetic instruc tions ADD ADDT ADLK LAC LACT LALK SBLK SUB and SUBT In addition SSXM affects the definition of the SFR instruction You can load SXM with the LST1 and RSXM instructions as well 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SSXM SXM is set enabling sign extension on subsequent instructions Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Set Test Control Flag STC label STC None PC 1 PC 1 TC test control flag in status register ST1 Affects TC 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 The TC test control flag in status register ST1 is set to logic one TC may also be loaded by the LST1 and instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution STC test control f
75. 5 V Ta 25 E 33 Running Title Attribute Reference CLOCK CHARACTERISTICS AND TIMING The SMJ320C26 can use either its internal oscillator or an external frequency source for a clock internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2 CLKIN see Figure 2 The frequency of CLKOUT1 is one fourth the crystal fundamental frequency The crystal should be either fundamental or overtone mode and parallel resonant with an effective series resistance of 30 ohms a power dissipation of 1 mW and be specified at a load capacitance of 20 pF Note that overtone crys tals require an additional tuned LC circuit see the application report Hard ware Interfacing to the TMS320C25 PARAMETER TEST CONDITIONS TYP UNIT fx Input clock frequencyt TA 55 MIN 6 7 40 0 C1 C2 Tg 125 C MAX T This parameter is not production tested CRYSTAL IU T Figure 1 Internal Clock Option external clock option An external frequency source can be used by injecting the frequency directly into X2 CLKIN with X1 left unconnected The external frequency injected must conform to the specifications listed in the table below switching characteristics over recommended operating conditions see Note 1 PARAMETER MIN MAX UNIT te C CLKOUT1 CLKOUT cycle time 100 600 E 34 Appendix Title Attribute Reference Running Title Attribute Reference td CIH C
76. 64 10 11 D7 12 D6 13 D5 14 D4 15 D3 16 D2 TMS320E25 68 PIN FZ 17 18 oR O AN oo lt lt lt lt lt lt TMS27C64 Table G 1 Pin Nomenclature TMS320E25 A12 MSB AO0 LSB On chip EPROM programming address lines CLKIN Clock oscillator input E EPROM chip select EPT EPROM test mode select G EPROM read verify select GND Ground PGM EPROM write program select Q8 MSB Q1 LSB Data lines for byte wide programming of on chip 8K bytes of EPROM RS Reset for initializing the device 5 V power supply 12 5 V power supply Programming and Verification Table 9 2 shows the programming levels that are required when program ming verifying and reading the EPROM cell Following the table are individual descriptions of each programming level Table G 2 TMS320E25 Programming Mode Levels Signal 5320 25 527 64 Protect E e o w w w wm 8 e 2 m ruse ve Emus rum qwe ec oP aeter 12 7 40 36 34 2 23 21 ADDR ADDR ADDR 24 3 a a o 6 appr anor x oas on pw x 1 LEGEND T TMS320E25 EPROM programming m
77. ALI A a qM ee ag ase Ete ak SACL 0 3 AR2 Data Space tel et tS SACL LAC SACL Write LAC Read Dummy M LAC AUXREG Two Word Instructions All two word instructions take an additional cycle to fetch the 16 bit immediate operand following the instruction mnemonic The first set of instructions for which this applies is the long immediate instructions The instruction mnemonic is followed by a 16 bit immediate operand to be executed in the ALU The second set applies to those instructions that use the PFC register as a second data addressing unit on some optimized instruc tions for example the multiply accumulate and block move instructions MAC MACD BLKP and BLKD In the second set the extra cycle appears only once in a repeat loop The third set involves conditional branches not tak en Program Counter Discontinuities Because the TMS320C25 is pipelined a change other than an increment in the program counter requires that the pipeline be flushed This applies to all branches subroutine calls software traps interrupttraps and returns The pipeline being three deep has the next instruction already loaded when the branch occurs At this point this instruc tion will not affect any
78. AUXREG Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 JUUUUUU UU uuu ADD 12 AR4 SUB 0 3 AR2 OR RET ADD SUB FE ADD ADD Interrupts are hardware generated discontinuities to the sequential accessing of the program counter The interrupt is executed based upon instruction execution complete rather than memory operation complete The instruction that is currently executing at the time of an interrupt executes completely The interrupt traps following the completion of that instruction before the start of the execution of the next instruction In this case the repeated instruction is con sidered one execution therefore the repeat loop finishes before the interrupt trap is taken This gives priority to the algorithm over the interrupt service The interrupt operation in reference to the pipeline execution is illustrated in the data sheet timing diagrams see Appendix A Note that when interrupt vectors reside in external memory running with one wait state there are two interrupt acknowledge IACK pulses If this is a problem the IACK line should be gated with READY Hardware Aspects of the Pipeline Viewing these effects on the pipeline at the hardware level requires additional explanation due to the lack of visibility
79. C26 indicates ready to receive BIO low host indicates data valid C26 inputs INTERRUPT high C26 indicates word was received BIO high host requests to transmit low C26 indicates ready to receive This is repeated as many times as needed BIO high host requests to transmit low C26 indicates ready to receive BIO low host indicates data valid C26 inputs CHECKSUM XF PAO C26 indicates CHECKSUM status HIGH pass LOW fail Synchronization word BIO high host requests transmit low C26 indicates ready to receive BIO low C26 branches to execute program data input but not used BRANCH PROG program is now running Handshake Figure 5 1 BIO ux NEM Host Requests 26 Ready Data Data Repeat Transmit to Receive Input Was Received Note The falling edge of BIO acts like a latch causing the C26 to input the data 5 7 Processor Initialization Figure 5 2 Sequence for 8 Bit Transfers 15 8 7 0 XXXXXXXX STATUS WORD INTERRUPT WORD 2x Length Transfers EN SYNCHRO DUMMY Figure 5 3 Sequence for 16 Bit Transfers 15 8 7 0 XXXXXXXX STATUS WORD XXXXXXXX INTERRUPT WORD XXXXXXXX PROGRAM LENGTH PROGRAM WORD 1 PROGRAM WORD 2 Length Transfers REPEAT CHECKSUM XXXXXXXX SYNCHRO DUMMY Note In all transfers the XF pin can be ignored as long as the host allows sufficient time for the C26 to get ready for the next transfe
80. Copyright 1996 Texas Instruments Incorporated
81. Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 32 Assembly Language Instructions Add to Accumulator With Sign Extension Suppressed ADDS Example ADDS DAT11 DP 6 or ADDS If current auxiliary register contains 779 Before Instruction After Instruction Data Data Memory OFO06h Memory OF006h 779 779 s 4 33 ADDT Aad to Accumulator With Shift Specified by T Register Syntax Operands Execution Encoding Description Words Cycles 4 34 Direct label ADDT dma Indirect label ADDT ind next ARP 0 lt dma x 127 0 x next ARP x 7 PC 1 2 PC x 2T register 3 0 ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affects OV affected by SXM and OVM Affects C 5 14 13 12 7 6 5 4 3 2 1 0 1 11 10 9 8 The data memory value is left shifted and added to the accumulator with the result replacing the accumulator contents The left shift is defined by the four LSBs ofthe T register resulting in shift options from 0 to 15 bits Sign extension on the data memory value is controlled by SXM Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions Add to Accumulator With Shift Specified by Register ADDT Example ADDT DAT127 DP
82. IDLE INSTRUCTION THIS ROUTINE SELECTS THE TASK APPROPRIATE FOR THE CURRENT SAMPLE CYCLE CALLS ASK AS A SUBROUTINE AND BRANCHES BACK TO THE IDLE TO WAIT FOR THE NEXT SAMPLE INTERRUPT WHEN THE SCHEDULED TASK HAS COMPLETED EXECUTIO IDLE WAIT FOR SAMPLE INTERRUP LAC SAMPLE FETCH SAMPLE COUNT VALUE SUB ONE DECREMENT THE SAMPLE COUNT BGEZ OVRSA X FOR END OF BAUD INTERVAL LACK 15 INIT COUNT FOR NEW BAUD INTERVAL OVRSAM SACL SAMPLE SAVE NEW COU VALUE ADLK SKSEQ ADD TASK TABLE BASE ADDRESS BLR READ SUBROUTINE TASK ADDRESS LAC EMP LOAD ACCUMULATOR FOR TASK CALL CALA EXECUTE APPROPRIATE TASK B WAIT TSKSEQ word DUMMY 7 5 UNUSED CYCLE word DUMMY 14 UNUSED CYCLE word DUMMY 13 UNUSED CYCLE word DUMMY 12 UNUSED CYCLE word BDCLK2 11 COMPUTE ENERGY E 11 word DUMMY 10 UNUSED CYCLE word OUT 9 COMMUNICATE WITH U CONTROLLER word DECODE 3 8 DECODE GE SCRAMBLED DIBIT word DEMODB 7 DEMODULATE IN MIDDLE OF BAUD word DUMMY 3 6 UNUSED CYCLE word AGCUPT 3 5 UPDATE AGC EVERY 3RD BAUD word DUMMY 4 UNUSED CYCLE word BDCLK1 3 COMPUTE ENERGY 3 word DUMMY 2 UNUSED CYCLE word DUMMY 1 UNUSED CYCLE word DUMMY O0 UNUSED CYCLE 5 28 Software Applications Interrupt Service Routine 5 3 Interrupt Service Routine Interrupts on the 5320 2 are prioritized and vectored When an interrupt occurs th
83. Modem AFE Data Converters G 15 Audio Video Analog Digital Interface Devices G 20 Commonly Used Crystal Frequencies H 4 Microprocessor and Microcontroller Tests J 5 532062 a oerte RUE abated REE meted ERO BT J 5 Examples tot d 1111 tm OANDAARWBNH O TT m 5 21 5 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 5 31 5 32 5 33 5 34 5 35 5 36 Processor Initialization 5320 25 5 3 Processor Initialization 5320 26 1 5 4 BIO XF Transfer 5 7 RS232 Transfer 5 12 TMS320C26BFNL Bootloader 5 17 SUDFOUTNES estes Sted Srila Man aie E is 5 22 Software Stack Expansion 5 24 Clock Divider Using Timer 5320 25 5 26 Instruction Repeating
84. Processing may be executed in a time and process dependent or selected way Following a specific time or data processing path may then result in se lecting one of several processing options You can program a simple computed GOTO in the TMS320C2x by using the CALA instruction This instruction uses the contents of the accumulator as the direct address of the call Thus the call address can be computed in the ALU as shown in Example 5 10 Example 5 10 Computed GOTO TASK CONTROLLER THIS MAIN TASK ROUTINE CONTROLS THE ORDER OF EXECUTION AND SCHEDULING OF TASKS WHEN AN INTERRUPT OCCURS THE INTERRUPT SERVICE ROUTINE IS EXECUTED TO PROCESS AND OUTPUT DATA SAMPLES AFTER THE INTERRUP SERVICE ROUTINE HAS COMPLETED THE PROCESSOR BEGINS XECUTION WITH THE INSTRUCTION FOLLOWING THE
85. Push all stack locations down level 15 14 13 12 11 10 9 8 7 6 5 4 37 22 4 0 Direct 9 1 0 1 0 1 00 Data Memory Address Indirect 1 0 1 0 1 0 See Section 4 1 The value from the data memory location specified by the instruction is trans ferred to the top of the stack The values are also pushed down in the lower seven locations 5320 2 of the stack as described in the instruction PUSH The lowest stack location is lost Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution PSHD DAT127 DP 3 or PSHD If current auxiliary register contains 511 Before Instruction After Instruction Data Data Memory 65h Memory 65h 511 511 Stack Stack 4 135 PUSH Push Low Accumulator Onto Stack Syntax Operands Execution Encoding Description Words Cycles Example 4 136 label PUSH None 1 PC Push all stack locations down one level ACC 15 0 2 TOS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 The contents of the lower half of the accumulator are copied onto the top of the hardware stack The stack is pushed down before the accumulator value is copied The hardware stack is a lastin first out stack with eight locations TMS320C2x If more than eight pushes due to CALA CALL PSHD PUSH or TRAP instructions occur before a pop the first data values written will
86. Q1 Q4 and driven through identical out put buffer circuits Since the internal clocks are very symmetric close tracking of these outputs results The large skews in these timings as shown in the data sheet are a factor of temperature and process Because there is no variation in process and negligible variation in temperature across a single device the skew of the outputs relative to the inputs is consistent for all outputs Regard less of the magnitude of such skews interfaces to the TMS320C25 can be de signed independently of these skews in most cases This section discusses three interface timings READY memory read and MSC For READY there are two pairs of related timings one timing can be met without the other one being met and the device still guaranteed to function properly These pairs of timings are ta SL R and td C2H R and th SL R and th C2H R These front end and back end READY timings are specified with re spect to STRB CLKOUT2 For zero wait state accesses READY is refer enced to STRB but for wait state accesses STRB remains low and another timing reference is required Note that the actual timings for each of these pa rameter pairs are identical and the timings with respect to CLKOUT2 and STRB are equivalent Therefore if READY timing meets the requirements with respect to one of these references but not necessarily the other the timing requirements of the device are satisfied regardless of the act
87. RS Reset input INT2 INT1 INTO External user interrupt inputs Microprocessor microcomputer mode select pin MSC Microstate complete signal IACK Interrupt acknowledge signal READY Data ready input Asserted by external logic when using slower devices to indicate that the current bus transaction is complete Bus request signal Asserted when the SMJ320C26 requires access to an external global data memory space External flag output latched software programmable signal Hold input When asserted SMJ320C26 goes into an idle mode and places the data address and control lines in the high impedance state Hold acknowledge signal Synchronization input Branch control input Polled by BIOZ instruction Serial data receive input Clock input for serial port receiver Frame synchronization pulse for receive input Serial data transmit output Clock input for serial port transmitter Frame synchronization pulse for transmit May be configured as either an input or an output t O Z denotes input output high impedance state Running Title Attribute Reference functional block diagram E 8 Appendix Title Attribute Reference N 2 d o Running Title Attribute Reference DATA RAM 32 x 16 BLOCK B2 BLOCK B3 RAM 512 x 16 BLOCK B1 RAM 512 x 16 BLOCK BO PROGRAM BUS zE
88. Resistance to solvents Per MIL STD 883C Method 2015 4 Table K 1 Microprocessor and Microcontroller Tests Test Sample Size Plastic Ceramic Operating life 125 C 5 0 V 1000 hrs Operating life 150 C 5 0 V 1000 hrs Storage life 150 C 1000 hrs Biased 85 C 85 percent RH 5 0 V 1000 hrs Autoclave 121 C 1 ATM 240 hrs Temperature cycle 65 to 150 C 1000 cyc Thermal shock 65 to 150 C 500 cyc Electrostatic discharge 2 kV Latch up CMOS devices only Mechanical sequence Thermal sequence Thermal mechanical sequence PIND Internal water vapor Solderability Solder heat Resistance to solvents Lead integrity Lead pull Lead finish adhesion Salt atmosphere Flammability UL94 VO Thermal impedance junction temperature does not exceed plasticity of package Table K 2 provides a list of the TMS320C2x devices the approximate number of transistors and the equivalent gates The numbers have been determined from design verification runs Table 2 TMS320C2x Transistors romes CMOS TMS320C25 160K TMS320E25 160K TMS320C26 160K TI qualification test updates are available upon request at no charge TI will consider performing any additional reliability test s if requested For more in formation on TI quality and reliability programs contact the nearest TI Field Sales Office J 5 4 6 Quality and Reliability Development Support Texas Instrumen
89. Running Title Attribute Reference Figure 1D Memory Maps E 20 Appendix Title Attribute Reference Running Title Attribute Reference interrupts and subroutines external interface The SMJ320C26 has three external maskable user interrupts INT2 INTO available for external devices that interrupt the processor Internal interrupts are generated by the serial port RINT and XINT by the timer TINT and by the software interrupt TRAP instruction Interrupts are prioritized with reset RS having the highest priority and the serial port transmit interrupt XINT having the lowest priority All interrupt locations are on two words boundaries so that branch instructions can be accommodated in those locations if desired A built in mechanism protects multicycle instructions from interrupts If an in terrupt occurs during a multicycle instruction the interrupt is not processed un til the instruction is completed This mechanism applies both to instructions that are repeated or become multicycle due to the READY signal The SMJ320C26 supports a wide range of system interfacing requirements Program data and I O address spaces provide interface to memory and I O thus maximizing system throughput I O design is simplified by having I O treated the same way as memory I O devices are mapped into the I O address space using the processor s external address and data busses in the same manner as memory mapped devices Interface to memory
90. SACH GUESS ADDH ROOT ADD CURRENT ROOT ESTIMATE SACH TEMPR UPDATE TEMPORARY ROOT VALUE BANZ SQRTLP REPEAT SPECIFIED NO OF ITERATIONS LAC ROOT LOAD THE ROOT OF X LSTI STL RESTORE STATUS REGISTER ST1 LS STO RESTORE STATUS REGISTER STO RE The hardware stack is allocated for use in interrupts subroutine calls pipe lined instructions and debugging The 5320 2 disables all interrupts when it takes an interrupt trap If interrupts are enabled more than one instruc tion before the return of the interrupt service routine the routine can also be interrupted thus using another level of the hardware stack This condition should be considered when managing the use of the stack When nesting sub routine calls each call uses a level of the stack The number of levels used by the interrupt must be remembered as well as the depth of the nesting of sub routines One level of the stack is reserved for debugging to be used for break point single step operations If debugging is not used this extra level is avail able for internal use 5 23 Program Control 5 22 Software Stack Provisions have been made on the TMS320C2x for extending the hardware stack into data memory This is useful for deep subroutine nesting or stack overflow protection Use the PUSH and POP instructions to access the hardware stack via the ac cumulator Two additional instructions PSHD and POPD are included in the instruction set so that the sta
91. STRB PS and DS lines The MSC line indicates at the rising edge of CLKOUT2 whether or not the cycle is the beginning of a new instruction fetch that is MSC active low indicates the completion of an instruction and the acquisition of another instruction The PS program select line indicates that the data bus is currently being used to fetch an instruction A step in the pipeline is not indicated since the PS line remains while the pipeline is fetching instructions externally To track the fetches the STRB line which frames external accesses must be monitored The PS line being active low does not necessarily mean that the device is fetching an instruction In the cases of table read write TBLR TBLW multiply accumulate MAC MACD and block transfer BLKP instructions the device uses the PS line active low to access tables To monitor external data memory fetches watch the data select DS line in conjunction with the STRB line An active low on the DS line indicates the data bus is currently being used to access data memory space This line remains low for two memory fetches in the case of an accumulator store followed by an ALU instruction both operating with off chip memory However two STRB pulses will identify the individual access Likewise the line remains low for many cycles in the case of a repeated instruction I O space access operates similarily to data space operation with the OUT and IN instructions replacing th
92. This special feature is implemented by a unique EPROM cell called the RBIT ROM protect bit cell Once the contents are programmed into the EPROM the RBIT can be programmed this prevents access to the EPROM contents and disables the microprocessor mode Once programmed the RBIT can be disabled only by erasing the entire EPROM array with ultravio F 12 5320 25 EPROM Programming EPROM Protection and Verification let light thereby maintaining security of all proprietary algorithms Program ming of the RBIT is accomplished by the EPROM protection cycle which consists of setting the PGM and 4 pins to a high level applying 12 5 0 25 V to both Vpp and and pulsing the Q8 pin to a low level The complete sequence of operations for programming the RBIT is shown in the flowchart of Figure 8 The required setups in the figure are detailed Table G 3 For more detailed information about how the RBIT works see subsection F 3 2 Figure 8 EPROM Protection Flowchart Program One Pulse of 3X ms 25 0 Duration EPROM Protect Setup Protect Verify Setup Program One 1 ms Pulse Device d Device Failed 3 d Passed 1 Yes No Protect Verify Setup Fail Verify RBIT Pass EPROM Protect Setup EPROM Protection and Verification F 3 2 How the RBIT Works When enabled the RBIT disconnects the internal program memory bus
93. To configure the processor after reset the following internal functions should be initialized Memory mapped registers Interrupt structure Mode control OVM SXM plus HM and FSM on TMS320C25 1 Memory control Auxiliary registers and the auxiliary register pointer ARP Data memory page pointer DP The OVM overflow mode TC test control flag and IMR interrupt mask reg ister bits are not initialized by reset The auxiliary register pointer ARP auxil iary register pointer buffer ARB and data memory page pointer DP are also not initialized by reset Example 5 1 and Example 5 2 show coding for initializing the TMS320C25 and 5320 26 respectively to the following machine state in addition to the initialization performed during the hardware reset All interrupts enabled OVM disabled DP set to zero ARP set to seven TMS320C25 and TMS320C26 LL Lu Internal memory filled with zeros Software Applications Processor Initialization Example 5 1 Processor Initialization TMS320C25 title PROC RESET INTO INT1 INT2 def def ref ref ESSOR INITIALIZATION INT IME RINT XINT USER ISRO ISR1 ISR2 RCV XMT PROC
94. continuous transmission If continuous transmission is stopped via software this initiation sequence must be repeated to restart the continuous mode op eration As shown in Figure 3 44 and Figure 3 45 RFSM may occur before a write to DXR regardless of the state of TXM If TXM 1 FSX is generated in a normal manner on the next rising edge of CLKX but only once If TXM 0 the TMS320C25 waits to transmit until FSX is pulsed but from then on the FSX input is ignored Note that just as in the case of continuous mode operation without sync pulses described in subsection 3 9 5 the first data written to DXR byte A is output twice unless DXR is reloaded before the second transmis sion is started It is important to consider this dummy cycle when using continu ous mode serial operation The receive timings are the same as those for the transmit operations with 0 The TMS320C25 waits to receive data until FSR is pulsed but there after the FSR input is ignored No dummy cycle is associated with the receive operation this is because DRR has a post buffering nature as opposed to the prebuffering nature of DXR Architecture Serial Port Figure 3 44 Continuous Transmit Operation Initialization Oe Bt Oe Oe Oe BO Re BO BC Ee Ee Bo a FSX axma LLL L 5 AT 6 6 6 4 4 8 3 3 3 8 9 4 4 O0 07 0 0 3 4 8 0 0 0 556955906060 0 DX F0 1 MSB LSB XIN
95. data pointer 3 9 data sheets SMJ320C2x 4 1 TMS320C25 A 1 TMS320C26 B 1 TMS320C28 C 1 TMS320E25 A 1 debugging tools K 1 development support K 1 K 4 Index 3 Index development systems K 1 analog interface board AIB2 K 1 emulator XDS 22 K 1 evaluation module EVM K 1 simulator K 1 development tool nomenclature K 4 device evolution K 2 TMP K 2 TMS K 2 TMX K 2 device nomenclature K 3 digital audio G 19 DINT 4 78 direct addressing 4 2 diagram 4 3 direct memory access DMA 3 5 3 75 See also DMA DIT 5 81 division 5 57 5 59 DMA 3 75 6 32 in a PC environment 6 34 master slave configuration 6 33 DMOV 3 27 4 79 download bootstrapping mode C26 See bootloader DP 3 9 DR 2 4 2 7 DRB 3 9 DRR 3 10 DS 3 16 DSP hotline ix DX 2 7 DXR 3 10 echo cancellation 6 48 EINT 4 81 emulator XDS 6 7 bus control 6 7 miscellaneous considerations 6 9 READY and memory substitution 6 8 TMS320C25 designs 6 9 EPROM adapter socket F 2 EPROM programmer F 2 Index 4 EPROM programming F 1 code protection F 12 F 15 data format F 4 erasure F 7 FAST programming F 7 F 9 output disable F 11 pin nomenclature F 5 program inhibit F 11 program verify F 8 programming modes F 6 programming the RBIT 12 15 protect verify F 15 RBIT operation F 14 RBIT side effects F 14 read mode F 11 SNAP pulse programming F 8 F 10 timing F 11 verificat
96. gt gt N 2 N 1 N Pa Pat Pipelining is reduced to two levels when execution is from internal program RAM due to the fact that an instruction in internal RAM can be fetched and de coded in the same cycle Thus separate prefetch and decode operations are not required as shown in Figure 3 17 Figure 3 17 Two Level Pipeline Operation 3 38 CLKOUT1 prefetch decode execute N 2 Pa 1 2 Pe N 1 N 1 s Pd be Pa The following paragraphs describe in detail the operation of the TMS320C25 pipeline This description in conjunction with Appendix NO gives suffi cient information for predicting the operation of the TMS320C25 for hardware interface optimization accurate program cycle counting and simulation mod elling Often itis notnecessary to understand the intricate detail of the pipeline to design with the TMS320C25 Therefore if you are not specifically interested in these details you can skip this description Architecture System Control The TMS320C25 executes most of its instructions in a single cycle because all the instructions are straight decodes and highly pipelined as opposed to mi crocode The basic pipeline operation is 3 25 cycles deep where the device sequence on any given cycle is fetching the third instruction decoding the se cond instruction and executing the first Figure 3 18 shows the internal op eration of
97. ox ox ox F FF X Xo X X Interrupt Service Routine title CONTEXT RESTORE def RESTOR CONTEXT RESTORE AT THE END OF A SUBROUTINE OR INTERRUPT ASSUME AR7 IS THE STACK POINTER AND AR7 105 ESTOR LARP AR7 ARP gt ARB 7 gt ARP AR7 105 MAR AR7 106 RESTORE AUXILIARY REGISTERS ARO THROUGH AR6 LAR AR6 106 ARG 7 107 LAR AR5 107 gt ARS 7 108 LAR AR4 08 7 109 LAR AR3 109 AR3 AR7 110 LAR AR2 110 gt AR2 AR7 111 LAR AR1 111 gt ARI AR7 112 LAR ARO 112 gt ARO AR7 113 RESTORE ALL EIGHT LEVELS OF THE HARDWARE STACK RPTK 7 PSHD 113 BOS 1 ART 114 114 STACK 2 AR7 115 115 STACK 3 AR7 116 116 STACK 4 AR7 117 117 STACK 5 AR7 118 118 STACK 6 ART 119 119 STACK 7 AR7 120 120 o TOS 8 AR7 121 THE RETURN PC IS NOW ON TOP OF THE STACK FOR THE RET INSTRUCTION
98. pin on the TMS320C2x Setting MP MC to a high maps in the block of off chip memory holding the pin at a low maps in the block of on chip ROM Conse quently compatible products that depend upon external memory from the ROM can be manufactured in a shorter time frame than the TMS320C2x Eventually the off chip memory device can be replaced by an on chip memory device at a lower cost because the PC board will not require any modification In another mapping technique the XF external flag pin is used to toggle the MP MC pin by dynamically enabling or disabling the on chip ROM Note that care must be taken and the instruction pipeline operation see subsection 3 6 2 must be understood when using this method Architecture Memory Organization 3 4 3 TMS320C2x Memory Maps The TMS320C2x provides three separate address spaces for program memory data memory and I O as shown in Figure 3 8 These spaces are distinguished externally by means of the PS DS and IS program data and I O space select signals The PS DS IS and STRB signals are active only for external bus accesses During an internal addressing cycle these signals remain inactive high thus preventing conflicts in memory addressing for ex ample when block BO is configured as program memory The on chip memory blocks BO B1 and B2 consist of a total of 544 words of RAM Program data RAM block BO 256 words resides in pages 4 and 5 of the data memory map when config
99. the carry bitis set because no borrow into bit 31 is required One exception to this case is the SUBH instruc tion which can only resetthe carry bit This allows the generation of the proper single carry when the subtraction from either the lower or upper half of the ac cumulator actually causes the borrow The following examples help to demon strate the significance of the carry bit for subtractions Software Applications Advanced Arithmetic Operations C LSB C LSB X 0000 0000 X 0000 0000 FOF OF 0 FFFF FFFF ME RR TR ETE X T7FFF X 7 FFFF i CONEGESE FFF 1 7 0 3000 0000 X 8000 0 0 0 0 ACC X 8000 0000 j 1 7 FFE FFF F 9 3000 0 0 0 0 0000 0000 ACC 0 FF FF F F ACC 0 SUBB o SUBB 0 FFFF FOESEBCOE 1 FFFF FFFE 0 8000 0 8000 ACC 0001 0 0 0 o SUBH ee ae eee o SUBH 0 0 8001 The coding in Example 5 40 shows the advantage of using the carry sta tus bit on the TMS320C25 Example 5 40 64 Bit Subtraction TWO 64 BIT NUMBERS ARE SUBTRACTED PRODUCING A 64 BIT RESULT THE NUMBER Y Y3 Y2 Y1 Y0 IS SUBTRACTED FROM X X3 X2 X1 X0 RESULTING IN W W3 W2 W1 W0 25 X3 X2 X1 XO UY3 X2 Yl X0 AR TOO A caet end itt ali e E W3 W2 W1 WO SUB64 ZALH X1
100. the opcode is 0890h Example 4 ADD 0 8 As Example 1 except that the contents of auxil iary register ARO are added to the current auxiliary register the op code is 08EOh Example 5 ADD 8 Asin Example 1 except that the contents of auxil iary register ARO are subtracted from the current auxiliary register the opcode is 08DOh Example 6 ADD 8 3 As in Example 1 except thatthe auxiliary register pointer ARP is loaded with the value 3 for subsequent instruc tions the opcode is 08ABh Example 7 ADD BR0 8 The contents of auxiliary register ARO are sub tracted from the current auxiliary register with reverse carry propa gation the opcode is 08COh Example 8 ADD 0 8 The contents of auxiliary register ARO are added to the current auxiliary register with reverse carry propagation the opcode is 08 Immediate Addressing Mode In immediate addressing the instruction word s contains the value of the im mediate operand The TMS320C2x has both single word 8 bit and 13 bit constant short immediate instructions and two word 16 bit constant long im mediate instructions The immediate operand is contained within the instruc tion word itself in short immediate instructions In long immediate instructions the word following the instruction opcode is used as the immediate operand The following short immediate instructions contain the immediate operand in the instruction word and execute within a single i
101. ures and the relationship of the input and output addressing in each case re veal that the address indexing is a bit reversed order as shown in Table 5 3 As aresult either the data input sequence or the data output sequence must be scrambled in association with the execution of the FFT 5 75 Application Oriented Operations Figure 5 13 An In Place DIT FFT With In Order Outputs and Bit Reversed Inputs Stage 1 Stage 2 Stage 3 0 1 2 3 LEGEND FOR TWIDDLE FACTOR Wo W 8 8 Wo W 8 W3 W Figure 5 14 An In Place DIT FFT With In Order Inputs but Bit Reversed Outputs Stage 1 Stage 2 Stage 3 LEGEND FOR TWIDDLE FACTOR Wo W B 4 2 4 W3 W 5 76 Software Applications Application Oriented Operations Table 5 3 Bit Reversal Algorithm for an 8 Point Radix 2 DIT FFT Index Bit Pattern Bit reversed Pattern Bit reversed Index 0 1 2 3 4 5 6 7 An addressing feature that uses reverse carry bit propagation allows the TMS320C25 to scramble the inputs or outputs while it is performing the I O The addressing mode is part of the indirect addressing implemented with the auxiliary registers and the associated arithmetic unit In this mode a derivative of indexed addressing a value index contained in ARO is either added to or subtracted from the auxiliary register being pointed to by the ARP However the carry bit is propagated in the reverse direction rather than the forward directi
102. 0010 1010 0110 1110 8 Point FFT Base Address XR 0 XR 4 XR 2 XR 6 XR 1 XR 5 XR 3 XR 7 Example 5 45 consists of lists of macros used in the implementation of FFTs 5 78 Software Applications Application Oriented Operations Example 5 45 FFT Macros COMBO 5 R1 11 R2 12 R3 13 R4 14 CALCULATE PARTIAL TERMS FOR R3 R4 AND 14 LAC R3 14 ACC 1 4 ADD R4 14 ACC 1 4 R3 R4 SACH R3 1 R3 1 2 R3 R4 SUB R4 15 ACC 1 4 R3 4 R4 1 2 R4 SACH R4 1 R4 1 2 R3 R4 LAC 13 14 ACC 1 4 ADD I4 14 ACC 1 4 I4 SACH 13 1 2 LIS 12 2 14 SUB 14 15 ACC 1 4 I4 1 2 14 SACH 14 1 14 1 2 I3 I4 CALCULATE PARTIAL TERMS FOR R2 R4 I2 AND 14 LAC R1 14 ACC 1 4 R1 ADD R2 14 ACC 1 4 R1 R2 SACH R1 1 R1 1 2 R1 R2 SUB R2 15 ACC 1 4 R1 R2 1 2 R2 ADD 14 15 1 4 R1 R2 I4 SACH R2 R2 1 4 R1 R2 I4 SUBH I4 ACC 1 4 R1 R2 I4 DMOV R4 14 R4 1 2 R3 R4 SACH R4 R4 1 4 R1 R2 14 LAC 11 14 ACC 1 4 11 ADD 12 14 1 4 I1 I2 SACH 11 1 I1 1 2 Il I2 SUB I2 15 ACC 1 4 11 I2 1
103. 2 12 SUB I4 15 ACC 1 4 I1 I2 14 SACH I2 I2 1 4 I1 I2 14 ADDH I4 ACC 1 4 Il I2 I3 I4 SACH I4 14 1 4 I1 12 13 14 CALCULATE PARTIAL TERMS FOR R1 R3 I1 AND I3 LAC 1 15 1 4 R1 R2 ADD R3 15 ACC 1 4 R1 R2 R4 SACH R1 R1 1 4 R1 R2 R3 R4 SUBH R3 1 4 R1 R2 R3 R4 SACH R3 R3 1 4 R1 R2 R3 LAC Ils 15 ACC 1 4 I1 I2 ADD ACC 1 4 Il I2 I4 SACH 11 212 1 4 12 14 SUBH 13 1 4 12 13 14 13 1 4 I2 I3 I4 SEND ZERO PR PI QR QI CALCULATE Re P Q AND Re P Q LAC PR 15 ACC 1 2 PR ADD QR 15 ACC 1 2 PR QR SACH PR PR 1 2 PR QR SUBH QR ACC 1 2 PR QR QR SACH QR QR 1 2 PR QR SUBH QI ACC 1 2 PI 4 QI QI SACH QI QI 1 2 PI QI SEND PIBY4 SMACRO PR PI QR QI W CALCULATE Im P Q AND Im P Q LAC 15 1 2 ADD 01 15 ACC 1 2 PI QI SACH PI PEU 1 2 QI LT W T REGISTER COS PI 4 SIN PI 4 LAC 01 14 ACC 1 4 QI SUB QR 14 ACC 1 4 QI QR 5 79 Application Oriented Operations Example 5 45 FFT Macros Continued
104. 2 Z 2 APAC 4 145 RSXM Reset Sign Extension Mode Syntax Operands Execution Encoding Description Words Cycles Example 4 146 label RSXM None 1 PC 0 gt SXM sign extension mode status bit Affects SXM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 The RSXM instruction resets the SXM status bit to logic zero which sup presses sign extension on shifted data memory values for the following arith metic instructions ADD ADDT ADLK LAC LACT LALK SBLK SUB and SUBT The RSXM instruction affects the definition of the SFR instruction SXM may also be loaded by the LST1 and SSXM instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RSXM SXM is reset disabling sign extension on subsequent instructions Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Reset Test Control Flag RTC label RTC None 1 0 TC test control flag in status register ST1 Affects TC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 The TC test control flag in status register ST1 is reset to logic zero TC can also be loaded by the LST1 and STC instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution
105. 2 2 Cycle Timings for a Repeat Execution not repeatable BLEZ PRG63 763 is loaded into the program counter if the accumulator is less than or equal to zero Assembly Language Instructions Block Move From Data Memory to Data Memory BLKD Syntax Direct label dma2 Indirect label next ARP Operands 0 lt dma1 lt 65535 0 lt dma2 lt 127 0 lt next lt ARP lt 7 Execution 2 gt MCS dma1 If repeat counter z 0 Then dma1 addressed by gt dma2 Modify AR ARP and ARP as specified PFC 1 PFC repeat counter 1 repeat counter Else dma1 addressed PFC dma2 Modify AR ARP and ARP as specified MCS 5 4 57 BLKD Block Move From Data Memory to Data Memory Encoding Description Words Cycles 4 58 Direct 1 0 1 Data Memory Address Data Memory Address 1 Indirect 1 14 1 0 ES See Section 4 1 Data Memory Address 1 Consecutive memory words are moved from a source data memory block to a destination data memory block The starting address lowest of the source block is defined by the second word of the instruction The starting address of the destination block is defined by either the dma contained in the opcode for direct addressing or the current AR for indirect addressing In the indi rect addressing mode both the current AR and ARP may be modified in
106. 3 2 1 0 Description The 8 bit immediate value is added right justified to the currently selected auxiliary register with the result replacing the auxiliary register contents The addition takes place in the ARAU with the immediate value treated as an 8 bit positive integer Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable Example ADRK 80h ARP 5 Before Instruction After Instruction ARS 4321h ARS 43A1h 4 37 AND AND With Accumulator Syntax Operands Execution Encoding Description Words Cycles 4 38 Direct label AND Indirect label AND next ARP 0 dma lt 127 0 lt next ARP x 7 PC 1 5 PC 15 0 AND dma 15 0 0 ACC 31 16 Not affected by SXM 15 14 13 12 7 6 5 4 3 2 1 0 11 10 9 8 Direct 0 1 1 1 0 E Data Memory Address 1 1 1 0 0 0 1 0 Indirect 0 1 0 See Section 4 1 The lower half of the accumulator is ANDed with the contents of the addressed data memory location The upper half of the accumulator is ANDed with all ze roes Therefore the upper half of the accumulator is always zeroed by the AND instruction Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions AND With Accumulator AND Example AND DAT16 D
107. 3 3 342p Destination external memory 3 p 3 p 343p 3 p 3 p Cycle Timings for a Repeat Execution not repeatable B PRG191 191 is loaded into the program counter the program continues running from that location Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch to Address Specified by Accumulator BACC label BACC None 15 0 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The branch uses the lower half of the accumulator bits 15 0 for the branch address 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 2 p Destination on chip ROM 3 3 3 p Destination external memory 3 p 3 p 342p 3 p 3 p Cycle Timings for a Repeat Execution not repeatable BACC Before Instruction After Instruction PC 16E4h PC 9545h ACC OF7FF9545h ACC OF7FF9545h 4 43 BANZ Branch on Auxiliary Register Not Zero Syntax Operands Execution Encoding Description Description Words Cycles 4 44 label BANZ ind next ARP 0 lt pma lt 65535 0 lt next ARP x 7 If AR ARP z 0 Then pma PC Else PC 2 gt PC Modify AR ARP as specified 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 See Section 4 1 Program Memory Address Control is passed to the designated program memory address if the cur rent auxil
108. 3 n nd 2p Table on chip ROM 3 n 2 3 n nd 2p Table in external memory 2 2 3 n np 2p 2 2 2 2 2 not repeatable Vil IX X XII IV V D 6 Instruction Cycle Timings Appendix SMJ320C2x Digital Signal Processors This appendix contains data sheet information on the SMJ320C2x digital sig nal processors family 1 SMJ320C2x Digital Signal Processors 2 SMJ320C2x Digital Signal Processors SMJ320C26 DIGITAL SIGNAL PROCESSOR SGUSO016 APRIL 1990 REVISED NOVEMBER 1992 68 PIN GB PIN GRID ARRAY CERAMIC TOP VIEW T m m gt c TSee Pin Assignments Table Page 2 and Pin Nomenclature Table Page 3 for location and description of all pins PRODUCTION DATA information is current as of publication date Copyright O 1992 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters 1 EXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 E 3 Running Title Attribute Reference 4 100 ns Instruction Cycle Time 1568 Words of Configurable On Chip Data Program RAM 256 Words of On Chip Program ROM 128K Words of Data Program Space Pin for Pin Compatible with the SMJ320C25 16 Input and 16 Output Channels 16 Bit P
109. 4 which is a plot of the magnitude of the impedance of the LC circuit of Figure 6 3 versus frequency Based on the discussion above the design of the LC circuit proceeds as fol lows choose the pole frequency approximately halfway between the crys tal fundamental and the third harmonic The circuit now appears inductive at the fundamental frequency and capacitive at the third harmonic In the oscillator of Figure 6 3 26 5 MHz which is approximately halfway between the fundamental and the third harmonic The values used in this case are determined by using C 20 pF then using 4 L 1 8 WH Figure 6 4 Magnitude of Impedance of Oscillator LC Network 6 6 Inductive Region Capacitive Region 0 1 wp is rad s Hardware Applications System Control Circuitry 6 1 3 User Target Design Considerations for the XDS The architecture for the TMS320C2x emulator XDS maximizes speed and performance No external serial logic levels have been added to any of the ad dress data or control signals other than those added to the setup times of READY RS BIO and HOLD and the propagation delay of HOLDA hold ac knowledge The additional loading on outputs induced by the XDS is compre hended in the XDS and TMS320C2x device design thus allowing the user the full drive as specified in the TMS320C2x device data sheet The DC loading characteristics of inputs is defined in Chapter 9 of the XDS 22 5320
110. 45 A2 DO 44 Al D6 43 PDACK Vss 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Vss Vss AO t Packages are shown for pinout reference only ADVANCE INFORMATION TMS320C2x Signal Descriptions 2 2 TMS320C2x Signal Descriptions The signal descriptions for the TMS320C2x devices are provided in this sec tion Table 2 1 lists each signal its pin location PGA PLCC and CER QUAD function and operating mode s that is input output or high imped ance state as indicated by O or Z The signals in Table 2 1 are grouped ac cording to function and alphabetized within that grouping Table 2 1 TMS320C2x Signal Descriptions Pin 0 2 Description PGA PLCCT Address Data Buses A15 MSB 110 43 Parallel address bus 15 MSB through AO LSB 14 K9 42 Multiplexed to address external data program memory or I O A13 L9 41 Placed in high impedance state in the hold mode K8 40 11 18 39 7 38 17 37 6 36 5 34 5 33 K4 32 L4 31 K3 30 L3 29 K2 28 K1 26 D15 MSB Parallel data bus D15 MSB through DO LSB Multiplexed to D14 transfer data between the TMS320C2x and external data pro D13 gram memory or I O devices Placed in the high impedance state D12 when not outputting or when RS or HOLD is asserted D11 D10 D9 D8 D7 D6 Interface Control Signals K10 45 Data program and I O space select signals Always high unless J10 47 low level asserted for communicating to a particular external
111. 9 8 7 1 1 1 1 1 1 1 0 1 See Section 4 1 Program Memory Address Description The current auxiliary register and ARP are modified as specified and the PC program counter is incremented by two and pushed onto the top of the stack The specified program memory address pma is then loaded into the PC Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address Words 2 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 2 2p Destination on chip ROM 3 3 3 2p Destination external memory 3 p 3 p 343p 3 p 3 p Cycle Timings for a Repeat Execution not repeatable 4 71 CALL Call Subroutine Example CALL PRG109 pma Before Instruction After Instruction PC 33h PC 6Dh Stack Stack 4 72 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Complement Accumulator CMPL label CMPL None 1 5 PC ACC gt contents of the accumulator replaced with its logical inversion 1s complement 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution CMPL Before Instruction After Instruction ACC 0F7982513h ACC 0867DAECh 4 73 CMPR Compare Auxiliary Register With Auxiliary Register ARO Syntax Operands
112. 9 8 7 6 5 4 3 2 1 0 Direct 0 1 0 10 Date Address Indirect o 1 0 0 0 0 1 0 See Section 4 1 Description TheLACT instruction loads the accumulator with a data memory value that has been left shifted The left shift is specified by the four LSBs of the T register resulting in shift options from 0 to 15 bits Using the T register s contents as a shift code provides a variable shift mechanism A Encoding LACT may be used to denormalize a floating point number if the actual expo nentis placed in the four LSBs ofthe T register and the mantissa is referenced by the data memory address Note that this method of denormalization can be used only when the magnitude of the exponent is four bits or less Words Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 87 LACT Load Accumulator With Shift Specified by Register Example 4 88 or LACT LACT DAT1 Data Memory 769 ACC If current auxiliary register contains 769 Before Instruction 1376h 98F7EC83h 3014h After Instruction 1376h ACC 13760h 3014h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example 1 Example 2 Load Accumulator Long Immediate With Shift LALK label LALK constant shift 16 bit constant 0 lt shift lt 15 default
113. BITLEN 2 cycles LARP AR2 BANZ AUTOB2 AR1 last bit in word B COMMON execute common download PG COPROL COPROCESSOR PARALLEL I O MODE BIOZ COPRO BIO low COPROCESSOR B GLITCH BIO high Made mistake COPRO LACK 0 SACL ODE init MODE 0 COPROCESSOR COMMON CALL READ read status word SACL EMORY P BI EMORY POSRD D3 download high BBZ BLOCK then gt BLOCK CONFIG LAC EMORY Store Statusword in SACL STATUS STATUS CALL READ read interrupt mask SACL INTER 2 CALL READ Read Program Length AND ASKFF mask unused bit SACL LENGTH t LAC STATUS 8 high Byte ANDK 0700n mask unused bit OR LENGTH High Byte and Low Byte Software Applications Processor Initialization SACL LENGTH into Program Length LRLK AR7 ADRESS Init address LAR AR6 LENGTH counter value BIT STATUS POSST D4 16 bit format high BBZ jOW8L AR7 No then go to LOW8L ZAC LOW16 BIOZ LOW16 BIO Input high RXF Set Ready Signal HIGH16 BIOZ READ16 BIO Input low B HIGH16 READ16 IN PAO Read Program Data SXF Reset Ready Signal ADD 0 AR6 Accumulate Checksum BANZ LOW16 AR7 Last Word SACL CHECK CALL READ read checksum CALL CHKSUM test checksum B BLOCK LOW8L CALL READ Read Program Data LSB AND MASKFF mask unused bit SACL WORD8L gt Low Byte CALL READ Read Program Data MSB SACL WORD8H gt hi
114. BO if it is configured as data memory and the data move function is continuous across the boundaries of blocks and B1 that is it works for locations 512 to 1023 The data move function cannot be used on external data memory If used on external data memory or memory mapped registers DMOV will read the specified memory location but will perform no other operations When data is copied from the addressed location to the next higher location the contents of the addressed location remain unaltered The data move function is useful in implementing the 2 1 delay encountered in digital signal processing The DMOV function is included in the LTD and MACD instructions see the LTD and MACD instructions or more information Words 1 Cycles Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 79 DMOV Data Move in Data Memory Example DMOV DAT8 DP 4 or DMOV If current auxiliary register contains 520 Before Instruction After Instruction Data Data Memory 43h Memory 43h 520 520 Data Data 521 521 4 80 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Enable Interrupt EINT label EINT None PC 1 PC 0 interrupt mode INTM status bit Affects INTM The interrupt mode flag INTM in the status register is cleared to logic 0 Maskable interrupts are enabled after the instructi
115. DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LPH DATO DP 4 or LPH If current auxiliary register contains 512 Before Instruction After Instruction Data Data Memory OF79Ch Memory OF79Ch 512 512 P 30079844h P F79C9844h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Load Auxiliary Register Long Immediate LRLK label LRLK constant 0 x auxiliary register x 7 0 constant x 65535 PC 2 gt PC Constant AR Not affected by SXM does not affect SXM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The 16 bit immediate value is loaded into the auxiliary register specified by the AR field The specified constant must be an unsigned integer and its value is not affected by SXM 2 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable LRLK AR3 3080h Before Instruction After Instruction AR3 7F80h ARS 3080h 4 97 LST Load Status Register STO Syntax Direct label LST dma Indirect label LST ind next ARP Operands 0 lt dma lt 127 0 lt next ARP lt 7 Execution 1 dma gt status register STO Affects ARP OV OVM and DP Does not affect INTM or ARB Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 0 1 0 1 0 000 o Data Memory Address Indirect 1 0 1 See Section
116. EXT and center pins 2 Connect the external Vcc to the pin labeled Vcc Figure F 2 shows the jumper setting placement for internal and external pow er The Vcc and Vpp pins are also shown Figure F 2 and Vpp Jumper Settings for External Power ND EE ETE EC E x EIDEM CM ELM LIE IEEE 71 Vcc Setting Vpp Setting Vpp B B INT INT Whenever supplying an external Vcc ground lead between the power supply and the programmer adapter F 3 Programming and Verification F 2 Programming and Verification TMS320E25 EPROM cell is similar to the TMS27C64 8K x 8 bit EPROM Their memories can be erased by using an ultraviolet light source and electri cally programmed by using the same family and device codes The TMS320E25 like the TMS27C64 requires a 5 V supply for reading and a 12 5 V supply for programming All programming signals are TTL level Loca tions may be systematically or randomly programmed as a singular or blocked address Unlike some EPROM cells that may require the high byte before the low byte each byte of data must be loaded into the TMS320E25 EPROM cell with the low byte preceding the high byte see Figure 3 To avoid memori zation of the pr
117. HOLDA ve A N 2 FETCH a a lt gt 1 EXECUTE lt m 6 et NOTE HOLD is an asynchronous input that can occur at any time during a clock cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of one CLKOUT2 cycle will occur Figure 13 HOLD Timing Part B E 48 Appendix Title Attribute Reference Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION te SCK 4 tw SCk tr SCK E e TID parc tw SCK s tsu Fs Su FS tsu DR N 8 16 Axe DR Figure 14 Serial Port Receive Timing FSR te SCK gt je tr SCK tw SCK PES ANA NEAN PAD 5 th FS d be tt SCK e td CH DX FSX INPUT 0 44 ta FL ce td CH DX gt lt td CH FS FSX i OUTPUT TXM 1 S Figure 15 Serial Port Transmit Timing E 49 Running Title Attribute Reference 25 40 1 000 24 89 0 980 24 38 0 960 MECHANICAL DATA i 23 88 0 940 F Ce a eee Se Te 20 52 0 808 TOP VIEW 20 19 0 795 MAX UNIT E Junction to free air 8 thermal resistance Junction to case 4 R
118. Instruments recom mends that these devices not be used in any production system because their expected end use failure rate is still undefined Only qualified produc tion devices are to be used Tl device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example N FN or GB and temperature range for example L Figure 1 provides a legend for reading the complete device name for any 5320 family member Development Support Device and Development Support Tool Nomenclature Figure K 1 TMS320 Device Nomenclature TMS 320 25 GB 1 TEMPERATURE RANGE PREFIX TMX experimental device H 50 TMP prototype device L Oto 70 S 55 to 100 C 55 to 125 C A 40to 85 C TMS qualified device SMJ MIL STD 883C PACKAGE TYPE plastic DIP J ceramic CER DIP JD ceramic DIP side brazed GB ceramic PGA TECHNOLOGY FZ ceramic CER QUAD FN plastic leaded CC C CMOS H FD ceramic leadless CC EOM EFEROM QFP quad flat pack DEVICE FAMILY 320 TMS320 Family DEVICE C1x DSP 10 14 15 16 17 C2x DSP 25 26 28 C3x DSP 30 31 C4x DSP 40 C5x DSP 50 51 53 K 3 Device and Development Support Nomenclature Figure 2 provides a legend for reading the part number for any TMS320 hardware or software development tool Figure 2 TMS320 Development Tool Nomenclature TMDS 32 4
119. J11 46 space Placed in high impedance state in the hold mode Data ready input Indicates that an external device is prepared for the bus transaction to be completed If the device is not ready READY 0 the TMS320C2x waits one cycle and checks READY again READY also indicates a bus grant to an external device after a BR bus request signal T Pin numbers apply to CER QUAD as well as to PLCC Input Output High impedance state 2 4 Pinouts and Signal Descriptions TMS320C2x Signal Descriptions Table 2 1 TMS320C2x Signal Descriptions Continued Pin 0 2 Description PGA PLCCT Interface Control Signals Continued R W H11 48 O Z Read write signal Indicates transfer direction when communicat ing to an external device Normally in read mode high unless low level asserted for performing a write operation Placed in high impedance state in the hold mode STRB H10 49 O Z Strobe signal Always high unless asserted low to indicate an ex ternal bus cycle Placed in high impedance state in the hold mode Multiprocessing Signals G11 50 Bus request signal Asserted when the TMS320C2x requires ac cess to an external global data memory space READY is as serted to the device when the bus is available and the global data memory is available for the bus transaction HOLD A7 67 Hold input When this signal is asserted the TMS320C2x places the data address and control lines in the high impedance state HOLDA E10 55 Hold ack
120. NO AO AO FSR R TX ALAS X BS X_B8X gt F0 1 F0 1 MSB LSB RINT iE t Read Read DRR DRR DRR DRR Loaded Loaded From RSR From RSR Continuous receive operation with FSM 1 is identical to that of burst mode operation with the exception that FSR is pulsed during reception of the final bit 3 71 Serial Port 3 9 5 Continuous Operation Without Frame Sync Pulses TMS320C25 3 72 The continuous mode of operation on the TMS320C25 allows transmission and reception of a continuous bit stream without requiring frame sync pulses every 8 or 16 bits This mode is selected by setting FSM 0 Figure 3 42 and Figure 3 43 show operation of the serial port for both states of TXM to illustrate differences in operation for each case FSM is initially set to one and frame sync pulses are required to initiate serial transfers Before the completion of the transmission that is before the next serial port interrupt the FSM must be reset to zero by means of an RFSM reset FSM instruction RFSM can occur either before or after the write to DXR or read from DRR From this point on the FSX and FSR inputs are ignored with transmission oc curring every CLKX cycle and reception occurring every CLKR cycle as long as those clocks are present If FSX is configured as an output it will remain low until FSM is set back to one and DXR is reloaded I
121. Operands Execution Encoding Description Words Cycles Example 4 140 label RHM None PC 1 PC 0 HM status bit in status register ST1 Affects HM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 instruction clears internal execution when acknowledging an active HOLD HM 1 When HM 0 the processor may continue execution out of internal memory but puts its external interface in a high impedance state HM can also be loaded by the LST1 and SHM instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RHM HM is reset implementing the TMS320C25 hold mode for on chip program execution Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Rotate Accumulator Left ROL label ROL None PC 1 PC 31 gt 30 0 gt ACC 31 1 C before ROL 0 Affects Not affected by SXM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0 The ROL instruction rotates the accumulator left one bit The MSB is shifted into the carry bit and the value of the carry bit from before the execution of the instruction is shifted into the LSB 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ROL
122. QR 15 ACC 1 4 QI QR SACH TOR fd QR 1 2 QI QR LAC PR 14 ACC 1 4 PR MPY 01 P REGISTER 1 4 QI QR W APAC ACC 1 4 PR QI QR W SACH PR PR 1 2 PR QI QR W SPAC ACC 1 4 PR SPAC ACC 1 4 PR QI QR W MPY QR P REGISTER 1 4 QI QR W SACH QR 1 QR 1 2 PR QI QR W LAC 14 1 4 SPAC i SAGE 1 4 PI QI OR W SACH 1 1 2 PI QI W P 1 4 1 4 PI QR W 01 1 7501 1 2 QI W SEND 5 80 Software Applications Application Oriented Operations Example 5 46 8 Point DIT FFT XOR set 00 XOI set 01 X1R set 02 X1I set 03 X2R set 04 21 set 05 X3R set 06 X31 set 07 X4R set 08 X41 set 09 X5R set 10 5 set 11 X6R set 12 X61 set 13 X7R set 14 X71 set 15 W set 16 WVALUE set 5A82h VALUE FOR SIN 45 OR COS 45 text INITIALIZE FFT PROCESSING EET SPM 0 NO SHIFT OF PR OUTPUT SSX SET SIGN EXTENSION MODE ROV RESET OVERFLOW MODE LDPK 4 SET DATA PAGE POINTER TO 4 LALK WVALUE GE WIDDLE FACTOR VALUE SACL W STORE SIN 45 OR COS 45 INPUT SAMPLES STORING IN BIT REVERSED ORDER LARK
123. Store low P register Set P register output shift mode Square and accumulate Square and subtract previous product scit ty iP e eae CE ESSE C X c l c l6 d l c N MO cA Za c c4 hb Ch X Sie 59 59 9 9 59 9 9 oon ao T These instructions are not included the SMJ32010 instruction set E 27 Running Title Attribute Reference Table 2 Instruction Set Summary continued BRANCH CALL INSTRUCTIONS NO INSTRUCTION BIT CODE WORDS 15 14 13 12 11 10 9 8 7 6 MNEMONIC DESCRITPION Branch unconditionally Branch to address specified by accumulator Branch on auxiliary register not zero Branch if TC bit 0 Branch if TC bit 0 Branch on carry Branch if accumu Branch if accumu Branch on I O sta Branch if accumu Branch on no carr Branch if no overt Branch if accumula ow Branch if accumulator 0 Branch on overflow Branch if accumulator 0 Call subroutine indirect Call subroutine Return from subrouti 000 420 4 N miro m NNN Bsa COA Oo Ba A n E H a AND DATA MEMORY
124. TBLW instructions and to address data memory when using the block move BLKD instruction Product Register A 32 bit product register used to hold the multiplier product The PR can also be accessed as the most or least significant words by using the SPH SPL store P register high low instructions Program Bus A 16 bit bus used to route instructions and data for the MAC and MACD 15 0 instructions Program Counter C 15 0 A 16 bit program counter used to address program memory The PC always contains the address of the next instruction to be executed The PC contents are updated following each instruction decode operation Program Memory Address 15 0 16 bit bus that carries the program memory address Bus Queue Instruction Register QIR 15 0 A 16 bit register used to store prefetched instructions Random Access RAM RAM block with 256 x 16 locations configured as either data or pro data or program gram memory 512 x 16 for TMS320C26 Random Access Memory RAM B1 A data RAM block organized as 256 x 16 locations 512 x 16 can be data only configured as program or data for TMS320C26 Random Access Memory RAM B2 A data RAM block organized as 32 x 16 locations data only Random Access A RAM block with 512 x 16 locations configured as either data or pro data or program 5 0 Sn gram memory TMS320C26 only Read Only Memory A ROM block 4096 x 16 256 x 16 for
125. THE LOWER 16 BITS OF THE P REGISTER MUST BE LOADED VIA THE T REGISTER AND THE STACK POINTER BE POINTING AT THE VALUE TO BE LOADED IN THE T REGISTER RESTORE THE LOW P REGISTER MAR SKIP T REGISTER AR7 122 X 122 gt TR AR7 121 MPYK 1 TR gt PRL RESTORE THE T REGISTER LP 121 gt TR AR7 122 MAR SKIP P REGISTER LOW AR7 123 RESTORE THE HIGH P REGISTER LPH 123 PRH AR7 124 RESTORE THE ACCUMULATOR ZALS 124 ACCL 7 125 125 ACCH ART 126 RESTORE THE STATUS REGISTERS LST 126 STO AR7 127 LST1 127 gt ST1 ART 128 RESTORE IS COMPLETE EIN ENABLE INTERRUPTS RE RETURN TO INTERRUPTS OR CALLING ROUTINE 5 31 Interrupt Service Routine 5 3 2 Interrupt Priority Interrupts on the TMS320C2x are prioritized in hardware This allows inter rupts that occur simultaneously to be serviced in a prioritized order Some times priority may be determined by frequency or rate of occurrence An infre quent but lengthy ISR might need to be interrupted by a more frequently oc curring interrupt In the routine of Example 5 13 the ISR for INT1 temporarily modifies the IMR to permit interrupt processing when an interrupt on INTO but no other interrupt occurs When the routine has finished processing the IMR is restored to its original state Example 5 13 Interrupt Service Routine title INTERRUPT SERVICE ROUTINE
126. TIM Timer ST0 ST1 Status registers DXR Serial port data trademark register TR Temporary register Carry bit Running Title Attribute Reference architecture The SMJ320C26 architecture is based on the SMJ320C25 with a different in ternal RAM and ROM configuration The SMJ320C26 integrates 256 words of on chip ROM and 1568 words of on chip RAM compared to 4K words of on chip ROM and 544 words of on chip RAM for the SMJ320C25 The SMJ320C26 is pin for pin compatible with the SMJ320C25 Increased throughput on the SMJ320C26 for many DSP applications is ac complished by means of single cycle multiply accumulate instructions with a data move option eight auxiliary registers with a dedicated arithmetic unit and faster necessary for data intensive signal processing The architectural design of the SMJ320C26 emphasizes overall speed com munication and flexibility in the processor configuration Control signals and instructions provide floating point support block memory transfers communi cation to slower off chip devices and multiprocessing implementations Three large on chip RAM blocks configurable either as separate program and data spaces or as three contiguous data blocks provide increased flexibility in system design Programs of upto 256 words can be masked into the internal program ROM The remainder of the 64K word program memory space is lo cated externally Large programs can execute at full speed from this
127. TMS320 member has one of three prefixes TMX TMP and TMS Texas Instruments recommends two of three possible prefix designators for its sup port tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS This development flow is de fined below Device Development Evolutionary Flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support Tool Development Evolutionary Flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been fully character ized and the quality and reliability of the device has been fully demonstrated Texas Instruments standard warranty applies bu Note Predictions show that prototype devices TMX or TMP will have a greater failure rate than the standard production devices Texas
128. TMS320C25 the next two instruction fetches immediately following a CNFD or CNFP instruction use the old value of On the TMS320C26 this instruction is not valid and is undefined 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution CNFD zero is loaded into the CNF status bit thus configuring block BO as data memory see memory maps in Section 3 4 4 75 Configure Block as Program Memory Syntax Operands Execution Encoding Description Words Cycles Example 4 76 label None PC 1 gt PC 1 RAM configuration control status bit Affects CNF On chip RAM block 0 is configured as program memory The block is mapped to locations 65280 through 65535 in program memory space This instruction is the complement of the CNFD instruction and sets the bit in status regis ter ST1 to a one is also loaded by the and LST1 instruction Configuring this block as program memory allows the use of the program counter as an address generator to access data from on chip RAM Used in conjunction with the repeat instructions this allows two data memory locations to be addressed simultaneously one from the auxiliary registers and one from the program counter Instructions that take advantage of this feature are the MAC MACD BLKD and BLKP instructions On the TMS320C25 the next two inst
129. TMS320C25 33 TMS320C25 50 5320 25 TMS320C26 TMS320C28 Table 1 1 provides an overview of the TMS320C2x generation of processors with comparisons of memory I O cycle timing and package type Table 1 1 TMS320C2x Processors Overview Memory On chip Off chip Ports t Package RAM EPROM Prog Data Type Ser Par DMA PGA PLCC CER Se aK em oak im _ memcs Se ak Gm oak em Ewsncm we 28 ew texte con 9 _ TSer serial Par parallel direct memory access concurrent Military version available contact nearest TI Field Sales Office for availability Military version planned contact nearest TI Field Sales Office for details PGA 68 grid array PLCC plastic leaded chip carrier CER surface mount ceramic leaded chip carrier CER QUAD QFP plastic quad flat package The TMS320C25 like all members of the TMS320C2x generation is pro cessed in CMOS technology The TMS320C25 is capable of executing 10 mil lion instructions per second Enhanced features such as 24 additional instruc tions 133 total eight auxiliary registers an eight level hardware stack 4K words of on chip program ROM a bit reversed indexed addressing mode and the low power dissipation inherent to the CMOS process contribute to the high performance The TMS320C25 33 is a 33 MHz version of the TMS320C25
130. TMS320C26 is similar to the TMS320C25 except for its internal memory configuration This is discussed in Section 3 4 and in Appendix B Topics in this chapter include Topic Page 2 1 3 TMS320C2x Pinouts E a 2 2 2 2 TMS320C2x Signal Descriptions 2 4 2 1 TMS320C2x Pinouts 2 1 TMS320C2x Pinouts Figure 2 1 shows pinouts of the PGA PLCC and CER QUAD packages for the TMS320C2x devices Note that the pinout and external dimensions of PLCC and CER QUAD are identical Figure 2 2 shows preliminary pinouts of the QFP package for the TMS320C28 device Figure 2 1 TMS320C2x Pin Assignments 68 Pin GB Pin Grid Array Ceramic Package Top View 122272 Ate 5s 6 AP 8 97 710 11 T O m m O O gt e 68 Pin FN Plastic Leaded Chip Carrier Package and 68 FZ CER QUAD Package Top View 5 CLKOUT1 CLKOUT2 2 2 and Signal Descriptions TMS320C2x Pinouts Figure 2 2 TMS320C28 Pin Assignments 80 Pin PH Quad Flat Package Top View z 326 25 855 665 c EE pp Sooke 2598zBtiumE D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 IACK 1 64 WAKEUP PDI 2 63 Vss Voc 3 62 A15 Voc 4 61 14 CLKX 5 60 A13 vss 6 59 A12 CLKR 7 58 Vss RS 57 A11 READY 9 56 A10 HOLD 55 AQ BIO 54 53 D15 52 Voc Vss 51 A7 D14 50 A6 D13 E vss 48 A5 D12 47 4 D11 46 A3 D10
131. The adapter socket has two sets of jumpers that indicate whether the power supply is internal from the EPROM programmer or external The adapter socket is shipped from the factory with the jumpers at the internal power set ting In some cases the EPROM programmer cannot supply the Vcc power needs of the TMS320E25 device so it becomes necessary to supply external Voc The following conditions will determine whether external power is needed The TMS320E25 s clock must be disabled during programming Because the device uses a dynamic logic for much of its internal circuitry the Ic c requirements for Vcc are significantly greater than a typical 27C64 type EPROM As a result many EPROM programmers sense this condition and erroneously indicate that the chip is plugged in backwards To prevent this from occurring a jumper connection and test point are available for an external 5 V logic supply This effectively bypasses the EPROM pro grammer s test and allows the device to be programmed TMS320E25 EPROM Programming Using the EPROM Programmer Adapter Socket Additionally a jumper and test point are available for the Vpp supply The Vpp signal is a pulsed signal and fully complies with the standards for a 27C64 EPROM device This option is never needed and the jumpers should be left in the internal position at all times To supply external Vcc 1 Findthe jumper nearestthe Vcc pin and move the jumper so that it is over the
132. Timings for a Repeat Execution not repeatable Before Instruction After Instruction PC 96h PC 37h Stack Stack Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Reset Serial Port Frame Synchronization Mode RFSM label RFSM None PC 1 PC 0 FSM status bit in status register ST1 Affects FSM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 The RFSM status bit resets the FSM status bit to logic zero In this mode exter nal FSR pulses are not required to initiate the receive operation for each word received but rather only one FSR pulse is required to initiate a continuous mode of operation The same holds true for FSX when 0 After the first FSR FSX pulse these inputs are then in a don t care state If 1 FSX is pulsed the first time DXR is loaded but remains low thereafter See Section 3 9 for further details on the operation of the serial port FSM may also be loaded by the LST1 and SFSM instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RESM FSM is reset putting the serial port in a mode of operation where frame synchronization pulses are not required This allows a continuous bit stream to be transmitted received without FSX FSR pulses every 8 16 bits 4 139 RHM Reset Hold Mode Syntax
133. Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SUBS DAT2 DP 16 or SUBS If current auxiliary register contains 2050 Before Instruction After Instruction Data Data Memory 0 003 0 003 2050 2050 Before Instruction After Instruction 4 181 SUBT Subtract from Accumulator with Shift Specified by Register Syntax Operands Execution Encoding Description Words Cycles Example 4 182 Direct label SUBT dma Indirect label SUBT ind next ARP 0 lt dma lt 127 0 lt next ARP lt 7 PC 1 x 2 T register 3 0 gt ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affects OV affected by SXM and OVM Affects C 5 14 13 1 T 6 5 4 3 2 1 0 1 2 11 10 9 8 Direct 9 1 0 0 0 1 1 0 E Data Memory Address Indirect 1 0 0 0 1 1 0 See Section 4 1 The data memory value is left shifted and subtracted from the accumulator The left shift is defined by the four LSBs of the T register resulting in shift op tions from 0 to 15 bits The result replaces the accumulator contents Sign ex tension on the data memory value is controlled by the SXM status bit Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SUBT DAT127 DP 4 or SUBT If current auxilia
134. Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ROVM The overflow mode bit OVM is reset disabling the overflow mode on any subsequent arithmetic operations 4 143 RPT Repeat Instructions as Specified by Data Memory Value Syntax Operands Execution Encoding Description Words Cycles Example 4 144 Direct label Indirect label RPT ind next ARP 0 lt dma x 127 0 next ARP x 7 PC 1 PC dma 7 0 gt RPTC E 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 0 1 01 1 Data Memory Address Indirect 0 1 0 0 1 0 1 1 See Section 4 1 The eight LSBs of the addressed data memory value are loaded into the repeat counter RPTC This causes the following instruction to be executed one time more than the number loaded into the RPTC provided that it is a repeatable instruction Interrupts are masked out until the next instruction has been executed the specified number of times Interrupts cannot be allowed during the RPT next instruction sequence because the RPTC cannot be saved dur ing a context switch The RPTC counter is cleared on a RS RPT and RPTK are especially useful for repeating instructions such as BLKP BLKD IN MAC MACD NORM OUT TBLR TBLW and others Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not
135. Until Interrupt IDLE label None TMS320C25 PC 1 PC 0 interrupt mode INTM status bit Affects INTM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The IDLE instruction forces the program being executed to wait until an inter ruptor reset occurs The PC is incremented only once and the device remains in an idle state until interrupted On the TMS320C25 INTM is automatically set to zero Execution of the IDLE instruction causes the TMS320C25 to enter the powerdown mode see subsection 3 6 7 The on chip timer continues to oper ate normally after execution of an IDLE instruction 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Interrupt destination on chip ROM 3 min waits for INT Interrupt destination external memory 342p min waits for INT Cycle Timings for a Repeat Execution not repeatable IDLE processor idles until reset or unmasked interrupt occurs 4 83 IN Input Data From Port Syntax Operands Execution Encoding Direct label Indirect label ind PA next ARP 0 lt dma lt 127 0 x next ARP lt 7 0 lt port address PA lt 15 PC 1 PC Port address address bus 0 0 address bus A15 A4 Data bus 015 00 dma 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 1 0 0 0 Port Address Data Memory Address Indirect Description Words Cycles Example 4 84
136. When the TIM register decrements to zero a timer interrupt TINT is generated In the follow ing cycle the contents of the PRD register are loaded into the TIM register In this way a TINT is generated every PRD 1 cycles of CLKOUT1 on the TMS320C25 You can read from or write to the timer and period registers on any cycle You can monitor the count by reading the TIM register and write a new counter peri od to the PRD register without disturbing the current timer count The timer will then start the new period after the current count is complete If both the PRD and TIM registers are loaded with a new period the timer begins decrementing the new period without generating an interrupt Thus you have complete con trol of the current and next periods of the timer For the TMS320C25 the TIM register is set to the maximum value on reset OFFFFh and the PRD register is also initialized by reset to OFFFFh The TIM register begins decrementing only after RS is deasserted If the timer is not used TINT should be masked The PRD register can then be used as a gener al purpose data memory location If you use TINT you should program the PRD and TIM registers before unmasking the TINT Example 5 8 shows the assembly code that implements the timer to divide down the CLKOUT1 signal To generate a 9600 Hz clock signal load the PRD register with 520 In the timer interrupt service routine the XF line is toggled The XF output is used also as a
137. a 0 modification will add ARO to itself The code would look this way lrlk ARO Value load a value into ARO larp ARO point the current ARP to ARO mar 0 add ARO to itself logical left shift 5 47 Advanced Arithmetic Operations Second for bit reversed carry addition in the ARAU the logic of the ARAU pro pogates the carries from any half adder to the right instead of left as in a nor mal addition In otherwords bit reversed carry addition works as if you were looking at the inputs and outputs with a mirror it reverses the order Note that this also causes the LSBs to swap places with the MSBs Two examples are given Example 5 25 shows ARO bit reverse added to itself ARP 0 Example 5 26 shows what is normally used in FFT bit reversals and other DSP algorithms ARP 0 with a mirror line drawn for reference Example 5 25 Bit Reversed Carry Addition LRLK ARO 07191h LARP ARO BRO Note carries propogate right G iC 1 0141 1 0 0041 1001 0 0 0 1 ARO qeu de 0 OS SO 0 30 00 41 1 1 00 O 1 1001000 lt New ARO gt C C gt C C gt gt last carry is lost Example 5 26 FFT Bit Reversals LRLK AR1 0800h LRLK ARO 0080h LARP ARI RPTK d MAR BRO Mirror Line LSB SB MSB LSB 0000100000000000 0000000000010000 BRO 0000000010000000 0000000100000000 ARl Bits 0000100000000000 0000000000010000
138. a CALL is made to the subroutine transferring control to that section of the program memory for execution and then returning to the calling routine via the RET instruction when execution has completed Example 5 6 Subroutines AUTOCORRELATIO THIS ROUTINE PERFORMS CORRELATION TWO VECTORS AND THEN CALLS SQUARE ROOT SUBROUTINE THAT WILL DETERMINE THE RMS AMPLITUDE OF THE WAVEFORM NERGY CALL SQRT SACL ENERGY SQUARE ROOT THIS SUBROUTINE DETERMINES THE SQUARE ROOT OF A NUMBER X THAT IS LOCATED IN THE LOW HALF OF THE ACCUMULATOR WHEN THE ROUTINE IS CALLED THE FRACTIONAL SQUARE ROOT OF XS TAKEN WHERE 0 X 1 AND WHERE 1 IS REPRESENTED BY 7FFFh THE RESULT IS RETURNED TO THE CALLING ROUTINE IN THE ACCUMULATOR STO set 60h SAVED STATUS REGISTER STO ADDRESS ST1 set 61h SAVED STATUS REGISTER ST1 ADDRESS NUMBER set 62h NUMBER X WHOSE SQUARE ROOT IS TAKEN TEMPR set 63h INTERMEDIATE ROOTS 5 22 Software Applications Program Control
139. a Long Integer 5 50 Using MACD for Moving 5 52 MUNDY Ru pam DP ERE Sohn 5 53 Multiply Accumulate Using the MAC Instruction TMS320C25 5 54 Multiply Accumulate Using the LTA MPY Instruction Pair 5 54 Using SORA e RUE E nn ui tiu e tact e 5 57 Divide 33 DY Or X sensus ditat se pr irc Sainte han GNO 5 58 Using SUBC for Integer Division 5 59 Using SUBC for Fractional Division 5 59 Using NORM for Floating Point Multiply 5 61 Table of Contents 5 37 5 38 5 39 5 40 5 41 5 42 5 43 5 44 5 45 5 46 5 47 Examples Using LACT for Denormalization 5 61 Row Times ur oec 5 62 64 Bit Additlon xs va a uk ane A eee 5 64 64 Bit Subtraction 5 65 32 x 32 Bit Multiplication 5 66 Implementing an IIR 5 70 256 Tap Adaptive FIR Filler 1 5 73 Adaptive Filter Routine Concluded
140. a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 2 2p Destination on chip ROM 3 3 3 2p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 2 2 2 2 Cycle Timings for a Repeat Execution not repeatable BV PRG610 If an overflow has occurred since the overflow flag was last cleared then 610 is loaded in the program counter and OV is cleared 4 67 BZ Branch if Accumulator Equals Zero Syntax Operands Execution Encoding Description Words Cycles Example 4 68 label BZ pma next ARP 0 lt pma lt 65535 0 x next ARP x 7 If ACC 0 Then pma gt PC Else PC 2 gt PC Modify AR ARP and ARP as specified 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the contents of the accumulator are equal to zero Otherwise control passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address 2 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination e
141. a carry is generated and the SUBH instruction can reset the carry bit only if a borrow is generated otherwise neither instruction can affect it Two branch instructions BC and BNC can execute branching on the status of the carry bit The SC RC and LST1 instructions can also be used to load the carry bit The carry bit is set to one on a hardware reset The SFL and SFR in place one bit shift to the left right instructions on the TMS320C2x and the ROL and ROR rotate to the left right instructions on the TMS320C25 implement shifting or rotating of the contents of the accumulator through the carry bit The SXM bit affects the definition of the SFR shift accu mulator right instruction When SXM 1 SFR performs an arithmetic right shift maintaining the sign of the accumulator data When SXM 0 SFR per forms a logical shift shifting out the LSB and shifting in a zero for the MSB The SFL shift accumulator left instruction is not affected by the SXM bit and be haves the same in both cases shifting out the MSB and shifting in a zero Re peat RPT or RPTK instructions may be used with the shift and rotate instruc tions for multiple shift counts 3 5 3 Multiplier T and P Registers 3 32 The 5320 2 utilizes 16 x 16 bit hardware multiplier which is capable of computing a signed or unsigned 32 bit product in a single machine cycle All multiply instructions except the MPYU multiply unsigned instruction on the TMS320C
142. adjustment All these parameters are software programmable making the AIC suitable for a variety of applica tions Table 9 has the description and characteristics of these devices Table H 9 Modem AFE Data Converters vo Press Rae Frowesor Pom e ewe Frowesces Compandingcodecmer pom e Frowesces Low powercodecrmer rom e TCM320AC36 Single supply codec filter and 25 2 Linear The AIC interfaces directly with serial input TMS320 DSPs which execute the modem s high speed encoding and decoding algorithms The TLC3204x fami ly performs level shifting filtering and A D and D A data conversion The DSP s many software programmable features provide the flexibility required for modem operations and make it possible to modify and upgrade systems easily Under DSP control the AIC s sampling rates permit designers to in clude fall back modes without additional analog hardware in most cases Phase adjustments can be made in real time so that the A D and D A conver sions can be synchronized with the upcoming signal In addition the chip has a built in loopback feature to support modem self test requirements Modem Applications For further information or application assistance please call TI Linear Applica tions at 214 997 3772 Figure G 11 High Speed V 32 Bis and Multistandard Modem With the TLC320AC01 AIC TLC320ACO1 ADC and DAC
143. allows a single instruction to be executed up to 256 times The repeat counter RPTC is loaded with either a data memory value RPT instruction or an immediate value RPTK instruc tion The value of this operand is one less than the number of times that the next instruction is executed Those instructions that are normally multicycle are pipelined when using the repeat feature and effectively become single cycle instructions The SMJ320C26 microprocessor implements acomprehensive instruction set that supports both numeric intensive signal processing operations as well as general purpose applications such as multiprocessing and high speed con trol For maximum throughput the next instruction is prefetched while the current one is being executed Since the same data lines are used to communicate to external data program or I O space the number of cycles may vary depend ing upon whether the next data operand fetch is from internal or external pro gram memory Highest throughput is achieved by maintaining data memory on chip and using either internal or fast program memory Table 1 lists the symbols and abbreviations used in Table 2 the instruction set summary Table 2 consists primarily of single cycle single word instructions Infrequently used branch and CALL instructions are multicycle The in struction set summary is arranged according to function and alphabetized within each functional grouping The symbol t indicates ins
144. an RF power amplifier family for hand held and mobile cellular phones System Design Considerations The size network complexity and com patibility requirements of telecommunications central office systems create demanding performance requirements Combo voice band filter performance is typically 0 15 dB in the passband Idle channel noise must be on the order of 15 dBrncO Gain tracking S Q and distortion must also meet stringent re quirements The key parameters for a SLIC device are gain longitudinal bal ance and return loss G 5 Telecommunications Applications Figure G 4 DSP Combo Interface TMS320C25 TCM320AC36 DOUT Codec IN Codec OUT 2 048 MHz nm 10 3900 v1 3900 6 5 4 3 2 5 01 nF 74504 745042017 74504 TCM320AC36 combo interfaces directly to the TMS320C25 serial port with a minimum of external components as shown in Figure G 4 Half of hex inverter U3 and crystal Y1 form an oscillator that provides clock timing to the TCM320AC36 The synchronous 4 bit counters U1 and U2 generate an 8 2 frame sync signal DCLKR on the TCM320AC36 is connected Vpp placing the combo in fixed data rate mode Two 20 kQ resistors connected to ANLGIN and MIC_GS set the gain of the analog input amplifier to 1 The timing is shown in Figure 9 5 G 6 Analog Interface Peripherals and Applications Telecommunications A
145. and I O devices of varying speeds is accomplished by using the READY line When transactions are made with slower devices the SMJ320C26 processor waits until the other device completes its function and signals the processor via the READY line the SMJ320C26 then continues execution A serial port provides communication with serial devices such as codecs seri al A D converters and other serial systems The interface signals are compat ible with codecs and many other serial devices with a minimum of external hardware The serial port may also be used for intercommunication between processors in multiprocessing applications The serial port has two memory mapped registers the data transmit register DXR and the data receive register DRR Both registers operate in either the byte mode or 16 bit word mode and may be accessed in the same manner as any other data memory location Each register has an external clock a framing signal and associated shift registers One method of multiprocessing may be implemented by programming one device to transmit while the others are in the receive mode E 21 Running Title Attribute Reference multiprocessing addressing modes E 22 The flexibility of the SMJ320C26 allows configurations to satisfy a wide range of system requirements The SMJ320C26 can be used as follows standalone processor A multiprocessor with devices in parallel E A multiprocessor with global memory sp
146. and data are stable PGM is pulsed The SNAP pulse programming algorithm uses pulses of 100 microseconds followed by abyte verification to determine if the addressed byte has been suc cessfully programmed Up to ten 100 microsecond pulses per byte are verified before a failure is recognized The programming mode is achieved when Vpp 13 0 V Vcc 6 5 V and G Vip and E Vj More than TMS320E25 can be programmed by con necting the devices in parallel with each other Locations may be programmed in any order When the SNAP pulse programming routine has been com pleted all bits are verified with Vcc Vpp 5 V F 2 4 Program Verify F 8 Programmed bits may be verified with Vpp 12 5 V when Vj E Vj and PGM Vip Figure 7 shows the timing of the program and verification opera tions for both FAST and SNAP pulse programming TMS320E25 EPROM Programming Programming Verification Figure F 5 FAST Programming Flowchart Address First Location Voc 6 0 25 V Vpp 12 5 V 0 25 V Program One 1 ms Pulse Pass p Device Pulse of 3X ms Failed Duration Increment Address Compare All Bytes to Original Data Fail Pass Device Passed Programming and Verification Figure F 6 SNAP Pulse Programming Flowchart Address First Location Vcc 6 5 Vpp 13 0 V Program Mode Program One Pulse
147. and exam ples of moving configuring and manipulating memory are provided in this section Since the TMS320C2x directly addresses a large amount of memory blocks of data or program code can be stored off chip in slow memories and then loaded on chip for faster execution Data can also be moved from on chip to off chip for storage or for multiprocessor data transfers The BLKD and BLKP instructions facilitate memory to memory block moves on the 5320 2 The BLKD instruction moves a block within data memory as shown in Example 5 14 Data may also be transferred between data memory and program memory by means of the TBLR and TBLW instructions The instructions IN and OUT are used to transfer data between the data memory and the space Example 5 14 Moving External Data to Internal Data Memory With BLKD THIS ROUTINE USES THE BLKD INSTRUCTION TO MOVE A BLOCK OF EXTERNAL DATA MEMORY DATA PAGES 8 AND 9 TO INTERNAL BLOCK DATA PAGES 6 AND 7 MOVED LARP AR2 LRLK AR2 300h DESTINATION IS BLOCK Bl RAM RPTK 255 REPEAT NEXT INSTRUCTION 256 TIMES BLKD 400 MOVE EXTERNAL BLOCK TO BLOCK B1 RE RETURN TO MAIN PROGRAM For systems that have external program memory but no external data memory BLKP can be used to move program memory blocks into data memory Example 5 15 demonstrates how to use the BLKP instructio
148. as specified by immediate value Reset sign extension mode Reset test control flag Set carry bit Set hold mode Set overflow mode Store status register STO Store status register ST1 Set sign extension mode Set test control flag Software interrupt 2 oi ie oo Moma io SCOOP gt gt 0 6 OQ O0 gt m e kh oU C cee oooEEooooco t These instructions are not included in the SMJ32010 instruction set t This instruction replaces CNFD and CNFP in the SMJ320C25 instruction set E 29 Running Title Attribute Reference development support E 30 Together Texas Instruments and its authorized third party suppliers offer an extensive line of development support products to assist the user in all aspects of TMS320 second generation based design and development These prod ucts range from development and application software to complete hardware development and evaluation systems Table 3 lists the development support products for the second generation TMS320 devices System development may begin with the use
149. be lost with each succeeding push 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution PUSH Before Instruction After Instruction Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Reset Carry Bit RC label RC None 1 0 carry bit C in status register ST1 Affects C 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 The carry bit C in status register ST1 is reset to logic zero The carry bit may also be loaded directly by the LST1 and SC instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RC carry bit C is reset to logic zero 4 137 Return From Subroutine Syntax Operands Execution Encoding Description Words Cycles Example 4 138 label RET None TOS 2 PC Pop stack one level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 13 1 1 0 0 0 1 0 0 1 1 0 The contents of the top stack register are copied into the program counter The stack is then popped one level RET is used with CALA and CALL for subrou tines 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 Destination on chip ROM 3 3 Destination external memory 2 Cycle
150. be saved and restored see subsection NO TAG 3 8 2 External Interrupt Interface Interrupts may be asynchronously edge or level triggered In the functional logic organization for INT 2 0 shown in Figure 3 31 the external interrupt INTO is connected to an edge triggered flip flop The INTO signal is ORed with the interrupt edge flip flop Q output and synchronized with internal quarter phases 1 and 2 to produce an interrupt signal In this way the device can han dle both edge triggered and level triggered interrupts 3 61 Interrupts Figure 3 31 3 62 Internal Interrupt Logic Diagram IACK DINT From Q D Data Bus Interrupt Mask Interrupt Register Mode Interrupt INTM do lt Idle EINT IACK Priority Decode To PC Interrupt i Processor Register Interrupt Active Machine State Logic for each external interrupt From Internal Interrupts Due to the level sensitivity of the external interrupts and the synchronization of the interrupts first on Q2 then on Q1 of the following machine cycle the INT line must be set to an inactive high at least two cycles before the enabling interrupts EINT If this criteria is not met the TMS320C25 will immediately take the interrupt trap following the EINT plus the next instruction If the INTM bit and mask register have been properly enabled the interrupt sig nal is accepted by the
151. benefit from the high throughput multipro cessing and data memory expansion capabilities of the TMS320C2x Figure 6 36 Instrumentation System 5320 2 Interface A D D A Analog Interface 6 51 6 52 Hardware Applications 5320 25 5320 25 Digital Signal Processors This appendix contains data sheet information on the TMS320C25 digital sig nal processors family which includes the following devices TMS320C25 TMS320C25 33 TMS320C25 50 TMS320E25 Refer to Appendix B for data sheet information on the TMS320C26 to Appen dix C for the TMS320C28 and to Appendix D for the military versions A 1 5320 25 5320 25 Digital Signal Processors 2 5320 25 5320 25 Digital Signal Processors TMS320C26 Digital Signal Processor This appendix contains data sheet information on the TMS320C26 digital sig nal processor B 1 TMS320C26 Digital Signal Processor B 2 TMS320C26 Digital Signal Processor Appendix TMS320C28 Digital Signal Processor This appendix contains data sheet information on the TMS320C28 digital sig nal processor C 1 TMS320C28 Digital Signal Processor 2 TMS320C28 Digital Signal Processor Instruction Cycle Timings This appendix details the instruction cycle timings for the TMS320C2x proces sor Instructions are first
152. control algorithms pro grammed in the controller The controller typically consists of an analog or digi tal processor Analog control systems are usually based on fixed components and are not programmable They are also limited to using single purpose characteristics of the error signal such as P proportional integral and D derivative or a combination These limitations along with other disadvantages of analog Systems such as component aging and temperature drift are reasons why digital control systems increasingly replace analog systems in most control ap plications Digital control systems that use a microprocessor microcontroller are able to implement more sophisticated algorithms of modern control theory such as state models deadbeat control state estimation optimal control and adaptive control Digital control algorithms deal with the processing of digital signals and are similar to DSP algorithms The TMS320C2x instruction set can there fore be used very effectively in digital control systems The most commonly used algorithm in both analog and digital control systems is the PID Proportional Integral and Derivative algorithm The classical PID algorithm is given by u t Kelt edt KE The PID algorithm must be converted into a digital form for implementation on a microprocessor Using a rectangular approximation for the integral the PID algorithm can be approximated as u n 1 Ky e n
153. data memory to data memory instruction cannot be used to read these registers The DXR and DRR registers are mapped into locations 0 and 1 in the data ad dress space The XSR and RSR registers are not directly accessible through software Architecture Serial Port Figure 3 33 The DRR and DXR Registers Address MSB LSB 0001h If the serial port is not being used the DXR and DRR registers can be used as general purpose registers In this case the CLKR or FSR should be con nected to a logic low to prevent a possible receive operation from being initi ated Three bits in status register ST1 are used to control the serial port operation FO TXM and FSM The FO format bit defines whether data to be transmitted and received is an 8 bit byte or a 16 bit word If FO 0 the data is formatted in 16 bit words If FO 1 the data is formatted in 8 bit bytes In the 8 bit mode only the eight least significant bits are used for transmit receive operations The FO bit is loaded by the FORT format serial port registers instruction On reset FO is set to 0 The TXM transmit mode bit is used to determine if the frame synchronization pulse for the transmit operation is generated externally or internally If TXM 1 the FSX pin becomes an output pin and a framing pulse is produced on the FSX pin every time the DXR register is loaded This framing pulse is synchro nized with the rising edge of CLKX If TXM 0 the FSX pin becomes an
154. data or registers so itis cleared from the pipeline There fore two dead execution cycles are inserted while waiting for the pipeline to reload The device takes only one additional cycle if the destination of the branch is in on chip RAM block 0 The pipeline is only two deep in this case and takes only one cycle to reload Figure 3 22 shows a branch from normal execution to an address in on chip RAM and NO TAG shows an example of a return executed from on chip RAM to a location in off chip memory System Control Figure 3 22 Pipeline Operation of Branch to On Chip Clock UU ULN T te CLKOUT1 CLKOUT2 STRB Address Data Decode INTRAM DATARAM Status Execute AUXREG 3 44 Q2 Cycle 1 Q3 BV Q4 Cycle 2 Q1 Q2 Q3 Q4 OFFOOh Q1 Cycle 3 Q2 Q3 ADD 12 Q4 R4 Q1 Cycle 4 Q2 Q3 SUB Q4 SUB Cycle 5 Q1 SUB 12 AR4 Q2 Q3 ADDH SUB Architecture System Control Figure 3 23 Pipeline Operation of RET From RAM Clock CLKOUT1 CLKOUT2 STRB Address Data Decode INTRAM DATARAM Status Execute
155. dress and the contents of ARO subtracted from it after the access 0 Contents of AR ARP used as the data memory dress and the contents of ARO added to it after the access BRO Contents of AR ARP are used as the data memory ad dress and the contents of ARO subtracted from it with re verse carry rc propagation after the access BRO Contents of AR ARP are used as the data memory ad dress and the contents of ARO added to it with reverse carry rc propagation after the access There are two main types of indirect addressing with indexing Regular indirect addressing with increment or decrement and Indirect addressing with indexing based on the value of ARO Indexing by adding or subtracting the contents of ARO or Indexing by adding or subtracting the contents of ARO with the carry propagation reversed for FFTs on the TMS320C2x In either case the contents ofthe auxiliary register pointed to by the ARP regis ter are used as the address of the data memory operand Then the ARAU per forms the specified mathematical operation on the indicated auxiliary register Additionally the ARP may be loaded with a new value All indexing operations are performed on the current auxiliary register in the same cycle as the original instruction Indirect auxiliary register addressing allows for post access adjustments of the auxiliary register pointed to by the ARP The adjustment may be an increment or de
156. fixed or adapted If the coef ficients are adapted or updated with time then another factor impacts the com putational capacity This factor is the requirement to adapt each of the coeffi cients usually with each sample The MPYA or MPYS and ZALR instructions on the TMS320C25 aid with this adaptation to reduce the execution time A means of adapting the coefficients on the TMS320C2x is the least mean square LMS algorithm given by the following equation i 1 by i 2B x i k where x i y i andy i b x i k Quantization errors in the updated coefficients can be minimized if the result is obtained by rounding rather than truncating For each coefficient in the filter at a given point in time the factor 2 B e i is a constant This factor can then be computed once and stored in the T register for each of the updates Thus the computational requirement has become one multiply accumulate plus rounding Without the new instructions the adaptation of each coefficient is five instructions corresponding to five clock cycles This is shown in the follow ing instruction sequence 5 71 Application Oriented Operations AR2 COEFFD LOAD ADDRESS OF COEFFICIENTS AR3 LASTAP LOAD ADDRESS OF DATA SAMPLES LARP AR2 T ERRF errf 2 B e i ZALH AR3 ACC bk i 2 16 ADD ONE 15 ACC bk i 2 16 2 15 MPY 2 A
157. from accumulator long immediate with shift T Cycles using full speed on chip external program memory t Theseinstructions are not available on the TMS32020 Instruction Set Summary Continued z T send scout sue Suse 1 S say ays K 19 Running Title Attribute Reference SUBT Subtract from accumulator with shift specified by T m register XORK Exclusive OR immediate with accumulator with shift ZALH Zero low accumulator and load high accumulator ZALRt Zero low accumulator and load high accumulator with 1 1 rounding ZALS Zero low accumulator load low accumulator with no sign extension Cycles using full speed on chip external program memory These instructions are not available on the TMS32020 K 20 Appendix Title Attribute Reference 07E00h 04E00h 0D004h OCE15h OFF80h OCE25h OFB80h OF980h OF880h 05E80h OF480h OF180h OFA80h 09000h 05700h OF280h OFDOOh OFCOOh OF380h 05F80h 0F780h OF580h OF080h OF680h OCE24h OFE80h OCE27h OCE50h OCE04h OCEO5h OCE3Ch OCEO1h 05600h OCEO0h OCEOEh OCE1Fh 08000h 02000h 0 00 042008 00001 030008 10 4 15 5 Running Title Attribute Reference K 21 Running Title Attribute Reference AR constant 0CO00h constant osem 9 K 22 App
158. functions the ARAU on the TMS320C25 performs functions as follows IR 7 0 gt gt AR ARP Add 8 bit immediate value to the current AR AR ARP IR 7 0 gt AR ARP A Subtract 8 bit immediate value to the current AR Architecture Memory Organization AR ARP rcARO Bit reversed indexing add ARO with reverse carry rc propagation see subsection NO TAG AR ARP rcARO Bit reversed indexing subtract ARO with reverse carry rc propagation see subsection NO TAG Although the ARAU is useful for address manipulation in parallel with other op erations it may also serve as an additional general purpose arithmetic unit since the auxiliary register file can directly communicate with data memory The ARAU implements 16 bit unsigned arithmetic whereas the CALU imple ments 32 bit 2s complement arithmetic Instructions provide branches depen dent on the comparison of the auxiliary register pointed to by ARP with ARO The BANZ instruction permits the auxiliary registers to be used also as loop counters The three bit auxiliary register pointer buffer ARB shown in Figure 3 8 pro vides storage for the ARP on subroutine calls and interrupts 3 4 7 Memory Addressing Modes The TMS320C2x can address a total of 64K words of program memory and 64K words of data memory The on chip data memory is mapped into the 64K word data memory space The on chip ROM in the TMS320C25
159. give the name of each device and where the data sheet for that device is located in order to obtain further specification informa tion if desired Data sheets for EPROM memories are located in the MOS Memory Data Book literature number SMYDO08 TMS27C64 TMS27C128 TMS27C256 TMS27C512 Another EPROM memory TMS27C291 292 is described in a data sheet lit erature number SMLS2914 The TCM29C13 14 16 17 codecs and filters are described in the data sheet beginning on page 2 111 of the Telecommunications Circuits Data Book liter ature number 5 001 An analog interface for the DSP using a codec and filter is provided by the TCM29C18 19 data sheet literature number SCTO21 The data sheet for the TLC32040 analog interface circuit is provided in the n terface Circuits Data Book literature number SLYDOO2 In the same book are data sheets for A D and D A converters The names of the devices are as follows TLC0820 TLC1205 1225 TLC7524 Memories Analog Converters Sockets and Crystals 2 Sockets Sockets The sockets produced by Texas Instruments are designed for high density packaging needs The production sockets and burn in test sockets for PGA PLCC and CER QUAD packages are compatible with the TMS320C2x devices For additional information about sockets contact the nearest sales office Or Texas Instruments Incorporated Connector Systems Dept M S 14 3 Attleboro MA 02703 617 699 5242 5269
160. in Figure G 11 is for illustration only In reality one single TMS320C5x DSP can implement high speed modem functions Advanced Digital Electronics Applications for Consumers G 6 Advanced Digital Electronics Applications for Consumers With the extensive use of the TMS320 DSPs in consumer electronics much electromechanical control and signal processing can be done in the digital do main Digital systems generally require some form of analog interface usually in the form of high performance ADCs and DACs Figure G 12 shows the general performance requirements for a variety of applications Figure G 12 Applications Performance Requirements MSPS 300 Instrumentation 100 30 Broadcasting Bits 4 5 6 7 8 9 10 Performance Application Advanced Television System Design Considerations Advanced Digital Television ADTV is a technology that uses digital signal processing to enhance video and audio presentations and to reduce noise and ghosting Be cause of these DSP techniques a variety of features can be implemented in cluding frame store picture in picture improved sound quality and zoom The bandwidth requirements remain at the existing 6 MHz television allocation From the IF intermediate frequency output the video signal is converted by an 8 bit video ADC The digital output can be processed in the digital domain to provide noise reduction interpolati
161. industrial control machines office machines advertisements novelty items exercise machines and learning aids Dedicated speech synthesis chips are effective in low cost applications The speech synthesis technology provided by the dedicated chips is either LPC li near predictive coding or CVSD continuously variable slope delta modula tion Table 5 shows the characteristics of the TI voice synthesizers Table H 5 Voice Synthesizers Synthesis On Chip External Data Rate Method 0 Memory Bits Bits Sec 5 50 4 10 20 32 64 128 VROM 1200 2400 Tl has low cost memories that are ideal to use with speech synthesis chips Texas Instruments can also be of assistance in developing and processing the speech data that is used in these speech synthesis systems Table 6 shows speech memory devices of different capabilities Additionally audio filters are outlined in Table H 7 Table H 6 Speech Memories TSP60Cxx Family of Speech ROMs TSPeocts TSP60C19 TSP60C20 TSP60C80 TSP60C81 Se For use with TSP50C1x TSP50C4x TSP50C4x TSP50C4x TSP50C1x G 10 Analog Interface Peripherals and Applications Dedicated Speech Synthesis Applications Table H 7 Switched Capacitor Filter ICs Function TLC2470 Differential audio filter amplifier TLC2471 Differential audio filter amplifier Roos Power Out Power Down 500 es es No No CLK 50 CLK 100 T
162. input pin The TMS320C2x then waits for an external synchronization pulse before beginning transmission On a reset TXM is setto zero configuring FSX to be an input The TXM bit can be loaded by the LST1 STXM or RTXM instruc tions The FSM frame synchronization mode status register bitis used to determine whether frame sync pulses are required for each serial port transfer When FSM 1 frame sync pulses are required consequently they are not required when FSM 0 FSM is set by the SFSM set frame synchronization mode instruction and cleared by the RFSM reset frame synchronization mode instruction When FSM 1 and frame sync pulses are required an FSX pulse will cause the XSR to be loaded with data from the DXR and transmission will begin If an FSX is presented prior to the last bit of the current transmission the XSR will be reloaded from the DXR thus aborting the current transmission and immediately beginning a new one The frame sync mode is useful in communicating to PCM highways For ATT T1 and CCITT G711 712 lines the processor can communicate directly in these formats by counting the transmitted received bytes in software and per forming SFSM RFSM instructions as needed to set reset the FSM bit 3 65 Serial Port 3 91 Transmit and Receive Operations The transmit and receive sections of the serial port are implemented separate ly to allow independent transmit and receive operations Externally the serial port i
163. input and clock timing relationships shown in timing diagrams as compared with the actual data sheet specifications If interpreted incorrectly the specifications may sug gest that interfacing to the device is more constrained than necessary Without exception the TMS320C25 meets every specification given in the data sheet Appendix A Some timings are specified more conservatively than others due to yield distributions etc but each TMS320C25 is guaranteed by Texas Instruments to conform explicitly with the minimum values as stated in the tables and shown in the timing diagrams of the data sheet 6 29 Interfacing Memories 6 30 Clock input and internal clock timing relationships must be considered in the interpretation of output timing characteristics and requirements At the clock input to the device only the rising edges of the clock are used to initiate transi tions on internal clocks and output signals Thus with an input clock of a stable frequency regardless of duty cycle variation within specifications extremely symmetric timing is exhibited throughout the device A significant conse quence of this is that CLKOUT1 CLKOUT2 and STRB timing skew with re spect to each other and high and low pulse widths are integer multiples of Q the input clock period or one fourth of the output clock period to within a few nanoseconds This occurs because transitions on the output signals are initi ated directly from the internal clocks
164. instruction see the DMOV instruction description MACD functions in the same manner as MAC with the addition of data move for block BO B1 or B2 Otherwise the effects are the same as for MAC This feature makes MACD useful for applications such as convolution and trans versal filtering When the MACD instruction is repeated the program memory address con tained in the PC PFC is incremented by one during its operation This enables accessing a series of operands in memory When used with RPT or RPTK MACD becomes a single cycle instruction once the RPT pipeline is started o M Note The data move function for MACD can occur only within the data blocks BO B2 of the on chip RAM can also be used for the TMS320C26 Words 2 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Table in on chip RAM 3 44d 5 d 2p Table in on chip ROM 4 5 d 5 d 2p Table in external memory 4 p 5 d p 5 d 3p Cycle Timings for a Repeat Execution Table in on chip RAM 2 n 2 2n nd 2 2 2 2 Table on chip ROM 3 n 3 2n nd 3 n 2p 3 2n nd 2p 3 2n nd Table in external memory 3 n np 3 2n nd 2 3 n np 2 2 2 4 115 MACD Multiply and Accumulate With Data Move Example SPM 0 Select no shift mode on PR output SOV Set overflow mode CNFP Configure
165. internal hardware summary table Assembly Language Instructions Addressing modes and format descriptions Instruction set summary listed according to function Alphabetized individual instruction descriptions with examples Software Applications Software application examples for the use of various TMS320C2x instruction set features Hardware Applications Hardware design techniques and application examples for interfacing to memories peripherals or other microcomputers microprocessors XDS design considerations System applications How to Use This Manual Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Appendix H Appendix Appendix J Appendix K Eleven appendices are included to provide additional information TMS320C25 Digital Signal Processor Electrical specifications timing and mechanical data for the TMS320C25 devices TMS320C26 Digital Signal Processor Data sheet information for the TMS320C26 digital signal processor TMS320C28 Digital Signal Processor Data sheet information for the TMS320C28 digital signal processor SMJ320C2x Digital Signal Processors Data sheet information for the SMJ320C2x digital signal processors family Instruction Cycle Timings Listings of the number of cycles for an instruction to execute in a given memory configuration on the TMS320C25 TMS320E25 EPROM Programming Programming hardware description and methodology Analog Interf
166. is a down counter that is continuously clocked by CLKOUT1 Figure 3 26 Timer Block Diagram 3 52 Crystal or External Clock CLKOUT1 The TIM register is set to the maximum value OFFFFh on reset for the TMS320C25 The PRD register on the TMS320C25 is also initialized by reset to OFFFFh See Example 5 1 TIM register begins decrementing only after RS is deasserted Following this the TIM and PRD registers may be re loaded under program control See subsection 3 6 3 for reset information The TIM register data memory location 2 holds the current count of the timer At every CLKOUT1 cycle the TIM register is decremented by one The PRD register data memory location 3 holds the starting count for the timer A timer interrupt TINT is generated every time the timer decrements to zero The tim er is reloaded with the value contained in the period PRD register within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular intervals of PRD 1 cycles of CLKOUT1 This feature is useful for control operations and for synchronously sampling or writing to peripherals By programming the PRD register from 1 to 65 535 OFFFFh a TINT can be Architecture System Control generated every 2 to 65 536 cycles on the TMS320C25 A PRD register value of zero is not allowed The timer and period registers can be read from or written to on any cycle The count can be monitored by rea
167. is mapped into the program memory space when in the microcomputer mode The memory maps which change with the configuration of block BO B1 and B3 are described in detail in subsections 3 4 3 and 3 4 4 The 16 bit data address bus DAB addresses data memory in one of the fol lowing two ways 1 By the direct address bus DRB using the direct addressing mode for example ADD 10h or 2 Bythe auxiliary register file bus AFB using the indirect addressing mode for example ADD Operands are also addressed by the contents of the program counter in the immediate addressing mode Figure 3 12 illustrates operand addressing in the direct indirect and immedi ate addressing modes 3 25 Memory Organization Figure 3 12 Methods of Instruction Operand Addressing Instruction Direct Addressing Instruction Indirect Addressing Instruction Po or A In the direct addressing mode the 9 bit data memory page pointer DP points to one of 512 pages each page consisting of 128 words The data memory address dma specified by the seven LSBs of the instruction points to the desired word within the page The address on the direct address bus DRB is formed by concatenating the 9 bit DP with the 7 bit dma In the indirect addressing mode the currently selected 16 bit auxiliary register AR ARP addresses the data memory through the auxiliary register file bus AFB While the selected auxiliary regi
168. its content Refer to Section 4 1 for further information on memory addressing Code ex amples using many of the instructions are given in Chapter NO TAG Software Applications 4 18 Assembly Language Instructions Syntax Operands Execution Example Instructions EXAMPLE Direct label EXAMPLE dma shift Indirect label EXAMPLE ind shift next ARP Immediate abel EXAMPLE constant Each instruction begins with an assembler syntax expression The optional comment field that concludes the syntax is not included in the syntax expres sion Space s are required between each field label command operand and comment fields as shown in the syntax The syntax example illustrates both direct and indirect addressing as well as immediate addressing in which the operand field includes constant The indirect addressing operand options including bit reversed BR addres sing are as follows TMS320C25 0 0 BRO BRO 0 lt dma lt 127 0 lt next ARP lt 7 0 lt constant lt 255 Operands may be constants or assembly time expressions referring to memory and register addresses pointers shift counts and a variety of constants The operand values used in the example syntax are shown PC 1 PC ACC dma x 2 shift ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affects OV affected by OVM and SXM Affects C EXAMP
169. listed in a table according to cycle classification Then each class of instructions is listed in another table showing the number of cycles required for a TMS320C2x instruction to execute in a given memory configuration singly or in repeat mode The column headings in the tables indi cate the program source location PI PE or PR and data destination or source DI or DE defined as follows DE The instruction executes from internal program memory RAM The instruction executes from internal program memory ROM The instruction executes from external program memory The instruction executes using internal data memory The instruction executes using external data memory The number of cycles required for each instruction is given in terms of the pro gram data memory and I O access times as defined in the following listing p Program memory wait states Represents the number of clock cycles the device waits for external program memory to respond to an access Ta is the TMS320C2x access time in nanoseconds maximum required for an external memory access with no wait states T mem is the memory ac cess time and is the clock period 4 crystal frequency p 0 lf Tmem lt Tac p 1 If Tac lt Tmem Tp p 2 If Tp Tac lt Tmem lt Tp x 2 Tac p k If Tp x K 1 Tac lt Tmem lt Tp x Tac Data memory wait states Represents the number of cycles the device must wait for external data
170. loaded into the accumulator shifted as spe cified by the PM status bits 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution PAC PM 0 Before Instruction After Instruction 144h 144h C C Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Pop Top of Stack to Low Accumulator POP label POP None PC 1 PC TOS gt ACC 15 0 0 ACC 31 16 Pop stack one level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 The contents of the top of the stack TOS copied to the low accumulator and the stack is popped after the contents are copied The upper half of the accumulator is set to all zeros The hardware stack is a last in first out stack with eight TMS320C2x loca tions Any time a pop occurs every stack value is copied to the next higher stack location and the top value is removed from the stack After a pop the bottom two stack words will have the same value Because each stack value is copied if more than seven pops due to POP POPD or RET instructions occur before any pushes occur all levels of the stack contain the same value No provision exists to check stack underflow 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution POP Before Instructio
171. local distributor H 5 H 6 Memories Analog Converters Sockets and Crystals Appendix I ROM Codes The size of a printed circuit board must be considered in many DSP applica tions To fully utilize the board space Texas Instruments offers two options that reduce the chip count and provide a single chip solution to its customers These options incorporate 4K words of on chip program from either a mask programmable ROM or an EPROM This allows the customer to use a code customized processor for a specific application while taking advantage of the following Greater memory expansion Lower system cost Less hardware and wiring Smaller PCB If used often the routine or entire algorithm can be programmed into the on chip ROM of a TMS320 DSP TMS320 programs can also be expanded by us ing external memory this reduces chip count and allows for a more flexible program memory Multiple functions are easily implemented by a single de vice thus enhancing system capabilities TMS320 Development Tools are used to develop test refine and finalize the algorithms The microprocessor microcomputer MP MC mode is available on all ROM coded TMS320 DSP devices when accessing either on chip or off chip memory is required The microprocessor mode is used to develop test and refine a system application In this mode of operation the 5320 acts as a standard microprocessor by using external program memory When the algorit
172. low When the Y output is brought low the TLC7524 is enabled and the data appearing on the data bus is latched into the D A converter by STRB The controlling soft ware for the D A interface is given on page 11 204 of Linear and Interface Cir cuits Applications Volume 3 Peripheral Drivers Data Acquisition Systems Hall Effect Devices literature number 5 003 published by Texas Instru ments Figure 6 26 Interface Timing of TLC7524 to TMS320C2x 15 00 15 94 CMS o 2 WR STRB 0 52 _ 7 015 00 DamOu 0 6 5 4 Analog to Digital A D Interface The TMS320C2x can be interfaced to 8 bit A D converters such as the TLC0820 However because the control circuitry of the TLC0820 operates much more slowly than the TMS320C2x it cannot be directly interfaced In the TLC0820 to TMS320C2x interface design shown in Figure 6 27 the following logic devices are used in the interface circuit L A 3 line to 8 line decoder SN74ALS138 A quad 2 input NAND gate SN74LS00 A hex inverter SN74LS04 A quad 2 input OR gate SN74LS32 A quad D type flip flop SN74LS175 m m m 6 43 Interfacing Peripherals Figure 6 27 Interface of TLC0820 to TMS320C2x Address Bus 16 74ALS138 TLC0820 Data Bus 74LS138 decodes the addresses assigned to the TLC0820 One of the addresses is used for a write operation the other is used f
173. lower order 16 bitfield ofthe accumulator and the remain der is in the high order 16 bits of the accumulator SUBC provides the normally expected results for division when both the denominator and numerator are positive The denominator is affected by the SXM bit If SXM 1 then the de nominator must have a 0 value in the MSB If SXM 0 then any 16 bit denomi nator value will produce the expected results The numerator which is in the accumulator must initially be positive that is bit 31 must be 0 and must re main positive following the accumulator shift which occurs during the SUBC operation If the 16 bit numerator contains less than 16 significant bits the numerator may be placed in the accumulator left shifted by the number of leading nonsig nificant zeroes The number of executions of SUBC is reduced from 16 by that number One leading zero is always significant Note that SUBC affects OV butis notaffected by OVM and therefore the accu mulator does not saturate upon positive or negative overflows when this instruction is executed Words 1 4 177 SUBC Conditional Subtract Cycles Example 4 178 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RP TK SUBC or RPTK SUBC 15 DAT2 DP 4 25 If current auxiliary register contains 514 Before Instruction After Instruction Data Data 514 514 C Assembly Language
174. memory space Programs can also be downloaded from slow external memory to high speed on chip RAM A data memory address space of 64K words is included to facilitate implementation of DSP algorithms The VLSI implementation of the SMJ320C26 incorporates all of these features as well as many others in cluding a hardware timer serial port and block data transfer capabilities 32 bit ALU accumulator The SMJ320C26 32 bit Arithmetic Logic Unit ALU and accumulator perform a wide range of arithmetic and logic instructions the majority of which execute in a single clock cycle The ALU executes a variety of branch instructions de pendent on the status of the ALU or a single bit in a word These instructions provide the following capabilities Branch to an address specified by the accumulator Normalize fixed point numbers contained in the accumulator Test a specified bit of a word in data memory One input to the ALU is always provided from the accumulator and the other input may be provided from the Product Register PR of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus Af ter the ALU has performed the arithmetic or logical operations the result is stored in the accumulator Appendix Title Attribute Reference scaling shifter Running Title Attribute Reference The 32 bit accumulator is split into two 16 bit segments for storage in data memory Additional shifters a
175. memory address space is included to facilitate implementa tions of DSP algorithms The large on chip 4K word masked ROM on the TMS320C25 can reduce the cost of systems thus providing for a true single chip DSP solution see Figure 3 1 Programs of up to 4K words can be masked into the internal pro gram ROM The remainder of the 64K word program memory space is located externally Large programs can execute at full speed from this memory space Programs may also be downloaded from slow external memory to on chip RAM for full speed operation The 4K word on chip EPROM on the TMS320E25 allows realtime code devel opment and modification for immediate evaluation of system performance Instructions can be executed from the EPROM at full speed The EPROM is equipped with a security mechanism allowing you to protect proprietary in formation A programming adapter socket is available from Texas Instruments that provides 68 to 28 pin conversion for programming with standard PROM programmers Refer to Appendix NO TAG for details Architecture Architectural Overview Figure 3 1 TMS320C2x Simplified Block Diagram 5 Gnd v V Data Prog Data RAM 288 Word nterrupts b 256 Word Data 16 1568 Word 5320 26 Multiprocessor Interface 4 K Words ROM EPROM a x TMS320C25 E25 j Multiplier Serial 32 Bit ALU ACC terface Shifters Address 16 Timer Arithmetic
176. memory to respond to an access This num ber is calculated in the same way as the p number memory wait states Represents the number of cycles the device must wait for external I O memory to respond to an access This number is calculated in the same way as the p number Other abbreviations used in the tables and their meanings are as follows br int INT ext n Branch from Internal program memory Interrupt External program memory The number of times an instruction is executed when using the RPT or RPTK instruction D 1 TMS320C2x Instruction Cycle Timings D 1 TMS320C2x Instruction Cycle Timings Table D 1 lists the TMS320C2x instructions according to cycle classification Table D 2 and Table D 3 show the number of cycles required for a given TMS320C2x instruction to execute in a given memory configuration when executed as a single instruction or in the repeat mode respectively Table D 1 TMS320C2x Instructions by Cycle Class INSTRUCTION ADD ADDC ADDH ADDS ADDT AND BIT BITT LAC LACT LPH LT LTA LTD LTP LTS MPY MPYS MPYU PSHD OR RPT SQRA SQRS SUB SUBB SUBC SUBH SUBS SUBT ZALH ZALR ZALS RPT not repeatable Lo POPD SACH SACL SAR SPH SPL SST SST ABS ADRK CMPL CMPR CNFD CNFP DINT EINT FORT LACK LARK LARP LDPK MAR MPYK NEG NOP NORM POP PUSH RC RFSM RHM ROL ROR ROVM RPTK RSXM RTC RTXM RXF SBRK SC SFL SFR SFSM SHM SOVM SPAC SPM SSXM STC ST
177. moreEPROM EPROM BOOTLOAD AR1 LEPROM AR2 080h AR2 GREG AR7 EPROM 1 AR3 ADRESS 2 MASKFF 8 AR3 AR1 moreEPROM AR7 GREG OFF80h Ck ck ck ck ck ck Ck ck ck kk ck kk Ck kk kk Sk kk KKK KK KKK KKK Entry Global DS Load length AR1 Entry Norm DS load destination point to LOW word only load lower 8 bits get upper 8 bits store value reloading clears MSB s Mask upper bits Finished load Set normal DS Accu B ranch 5 21 Program Control 5 2 Program Control 5 2 1 Subroutines To facilitate the use of the TMS320C2x in general purpose high speed proces sing a variety of instructions are provided for software stack expansion sub routine calls timer operation single instruction loops and external branch control Descriptions and examples of how to use these features of the TMS320C2x are given in this section The TMS320C2x has a 16 bit program counter PC and a eight level hard ware stack for PC storage The CALL and CALA subroutine calls store the cur rent contents of the program counter on the top of the stack The RET return from subroutine instruction then pops the top of the stack to the program counter Example 5 6 illustrates the use of a subroutine to determine the square root of a 16 bit number Processing proceeds in the main routine to the point where the square root of a number should be taken At this point
178. n 2p 2 2 2 1 2 Source data in external memory 2 2 2 2 2 2 2 2 2 2 OF400h If current auxiliary register contains 1030 1 Before Instruction After Instruction Data Data Memory 7F98h Memory 7F98h 62464 62464 Data Data Memory OFFE6h Memory OFFE6h 62465 62465 Data Data Memory 9522h Memory 9522h 62466 62466 dma2 Before Instruction After Instruction Data Data Memory 7F98h Memory 7F98h 1030 1030 Data Data Memory 9315h Memory OFFE6h 1031 1031 Data Data Memory 2531h Memory 9522h 1032 1032 4 59 Block Move From Program Memory to Data Memory Syntax Operands Execution Encoding Description 4 60 Direct label BLKP dma Indirect label BLKP pma ind next ARP 0 lt pma lt 65535 0 dma lt 127 0 next ARP lt 7 PC 2 gt PC PFC gt MCS If repeat counter 0 Then addressed by PFC dma Modify AR ARP and ARP as specified PFC 1 repeat counter 1 repeat counter Else pma addressed by PFC dma Modify AR ARP and ARP as specified MCS 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 o Data Memory Address Program Memory Address 1 0 0 See Section 4 1 Program Memory Address Consecutive memory words are moved from a source program memory block to a destination data memory block The
179. of one or more processors to allow another processor to read from or write to the halted processor s local off chip memory Direct memory access to external program data memory is performed by using the HOLD and HOL DA signals Multiprocessing is typically a master slave configuration where the master may initialize a slave by downloading a program into its program memory space and or by providing the slave with the necessary data to complete a task In a typical TMS320C2x direct memory access scheme the master may be a general purpose CPU another TMS320C2x or perhaps even an analog to digital converter A simple TMS320C2x master slave configuration is shown in Figure 6 18 The master TMS320C2x takes complete control of the slave s external memory by asserting HOLD low via its external flag XF This causes the slave to place its address data and control lines in a high imped ance state By asserting RS in conjunction with HOLD the master processor can load the slave s local program memory with the necessary initialization code on reset or powerup The two processors can be synchronized by using the SYNC pin to make the transfer over the memory bus faster and more effi cient After control of the slave s buses is given up to the master processor the slave alerts the master to this fact by asserting HOLDA This signal may be tied to the master TMS320C2x s BIO pin The slave s XF pin may be used to indicate to the ma
180. of the internal CPU circuits from switching and drawing power This can be used as a hardware powerdown mode If the HM bitis low the TMS320C25 continues executing any instruction that can be executed with on chip resources only This means both program and data reside in on chip memory The device will continue to operate normal ly unless an off chip access is required by an instruction at which time the pro cessor adds wait states until the hold state is removed When running from on chip resources with HM 0 the processor acknowledges HOLD with HOLDA during a multicycle instruction On Chip Program Access When you execute from on chip resources the pipeline is visible only in the MSC line which signals microstate complete when active low on the rising edge of CLKOUT2 Note that executing from on chip program memory does not allow instruction accessing of external data Architecture 3 6 3 Reset System Control memory to run in a single cycle The normal operation of the instruction takes only two quarter phases of the execution cycle to fetch the on chip data memory whereas off chip access requires all four quarter phases The pipe line is however optimized to handle a repeated instruction that accesses ex ternal data memory with only one extra cycle for the first external fetch External Program Data Access Visibility of the pipeline when using external program and data memory requires a monitoring of the MSC
181. one wait state ready condition for global memory access The signature test subtracts the value of a B instruction OFF80h from the re sulting combined 16 bits of the first two words in location 08000h If a zero is returned in the accumulator it indicates that a branch was found The TMS320C26 performs this test in global memory by setting GREG 080h If a B instruction is present it indicates that a valid EPROM may have been found The C26 performs the same test in normal data space by setting GREG 0h Ifa B instruction is present again mode 3 is aborted and mode 2 RS232 serial port operation is entered The downloading then continues until all of BO B1 and B3 are filled with data 1536 words If additional data recovery is needed your downloaded program can take over The memory to be loaded is recovered from the lower 8 data bits 00 07 in a HI LO HI LO order The upper byte is masked out The byte ordering for the first few words including the test branch is shown in Figure 5 8 Figure 5 8 External Memory Byte Ordering 5 16 Ext Global Mem Int Data Mem D15 D8 D7 DO D15 DO 08000 XXXXXXXX 11111111 xxxxxxxx 10000000 H B 0FF80h 0200h 08003h P H Prog_Addr 0201h 08004h 08006h 11111111 In this mode no checksum is performed because no host connection is used to perform the download If you still want a checksum your program can per form this task Software Applic
182. or high no later than 20 ns 5 ns after STRB goes low If READY is high then the memory peripheral access is completed with the present machine cycle If READY is low the access is extended to the next machine cycle that is a wait state is introduced The number of wait states required depends on the access time t4 of the particular memory device or pe ripheral If t4 40 ns no wait states are required If 40 ns t4 140 ns one wait state must be inserted In general N wait states are required for a particu lar access if TMS320C25 100 1 40 ns lt ta lt 100N 40 ns Interfacing Memories Figure 6 9 One Wait State Memory Access Timing STRB KX KX Xai PS DS IS UJ KX ni X8 XXX KKK KEY 920092009026 946945093 Ready KH 69 094 D15 DO For Read Operation D15 DO 25 For Write Data Out Operation gt y M 0M MSC ERY RK KOK The information on the number of wait states required for a memory or periph eral access is summarized in Table 6 3 Table 6 3 Wait States Required for Memory Peripheral Access 6 20 Number Of Wait TMS320C25 States Required Access Time ta lt 40 ns 40 ns lt ta lt 140 ns 140 ns lt ta lt 240 ns 240 ns ta 340 ns 340 ns tg 440 ns Design and timing of a wait state generator are shown in Figure
183. parallel download from an I O port Mode 2 serial download from an RS232 port 1 Mode 3 external memory EPROM download Note In all three modes The download begins at data block BO 0200h in internal space and con tinues until the length specified by the download mode is reached The appropriate memory blocks are then configured as program and execu tion transfers to the first address in program block BO OFAOOh The ROM interrupt vector table uses AR modification To save context onaninterrupt the user defined vector table in program block should not modify the auxiliary registers This is especially important in external global memory downloads in which an unmodified B ranch instruction is used to identify valid code Ifthe RS signal is nota clean TTL signal the various processor sections may not be properly synchronized with each other This is because the RS pin does not have an internal Schmidt trigger built into it It is there fore recomended that you use a Schmidt triggered gate with an RC time constant and external switch to avoid this 5 1 1 1 Mode 1 Parallel Download From an Port 5 6 You can perform a parallel download through a parallel interface to a host pro cessor via parallel I O port zero Both 8 and 16 bit wide data words be transferred BIO and XF are used as handshake signals to the host If the BIO signal is low at reset a parallel I O mode download
184. reading the instruction from program memory must be executed only once thus allowing the rest of the executions to operate in a single cycle 5 26 Software Applications Program Control Programs such as those implementing digital filters require loops that execute in a minimum amount of time Example 5 9 shows the use of the RPT or RPTK instructions Example 5 9 Instruction Repeating THIS ROUTINE USES THE RPT INSTRUCTION TO SET UP THE LOOP COUNTER IN ONE CYCLE HE FOLLOWING EQUATION IS IMPLEMENTED IN THIS ROUTINE 10 ORT aR THIS ROUTINE ASSUMES THAT THE VALUES ARE LOCATED IN RAM BLOCK BO AND THE Y VALUES IN BLOCK Bl WHEN REPLACING RPT NUM WITH RPTK 9 THE PROGRAM WILL EXECUTE THE SAME WAY SERIES LARP CNFP CONFIG BLOCK BO AS PROGRAM MEMORY LACK 9 SET COUNTER TO 9 SACL NUM NUM 9 LRLK AR4 300h POINT AT BEGINNING OF DATA MPYK Oh CLEAR P REGISTER ZAC CLEAR ACCUMULATOR RPT NUM EXECUTE NEXT INSTRUCTION 10 TIMES MULTIPLY ACCUMULATE INCREMENT APAC RE RETURN TO MAIN PROGRAM 5 27 Program Control 5 2 5 Computed GOTOs
185. repeatable RPT DAT127 31 SFR or RPT If current auxiliary register contains 4095 SFR Before Instruction After Instruction Data Data 4095 4095 ACC 12345678h acc o 12345h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Repeat Instructions as Specified by Immediate Value RPTK label RPTK constant 0 constant lt 255 PC 1 PC Constant gt RPTC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The 8 bit immediate value is loaded into the RPTC repeat counter This causes the following instruction to be executed one time more than the number loaded into the RPTC provided that it is a repeatable instruction Interrupts are masked out until the next instruction has been executed the specified num ber of times Interrupts cannot be allowed during the RPT next instruction se quence because the RPTC cannot be saved during a context switch The RPTC is cleared on a RS RPT and RPTK are especially useful for repeating instructions such as BLKP BLKD IN MAC MACD NORM OUT TBLR TBLW and others 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable LRLK AR2 200h Load AR2 with the address of X LARP 2 ZAC Clear the accumulator MPYK 0 Clear the P register RPTK 2 Repeat next instruction 3 times SORA Compute X 2 Y
186. request control of the bus The length of the memory cycle is controlled by the READY line Architecture Architectural Overview Direct Memory Access The TMS320C2x supports direct memory access DMA to its external program data memory using the HOLD and HOLDA sig nals Another processor can take complete control of the TMS320C2x external memory by asserting HOLD low This causes the TMS320C2x to place its ad dress data and control lines in the high impedance state Signaling between the external processor and the TMS320C2x can be performed by using inter rupts On the TMS320C2x two modes are available a mode in which execu tion is suspended during assertion of HOLD and a concurrent DMA mode in which the TMS320C2x continues to execute its program while operating from internal RAM or ROM thus greatly increasing throughput in data intensive ap plications 3 5 Functional Block Diagram 3 2 Functional Block Diagram The functional block diagram shown in Figure 3 2 and Figure 3 3 outlines the principal blocks and data paths within the TMS320C2x processors Further details of the functional blocks are provided in the succeeding sections Refer to Section 3 3 Internal Hardware Summary for definitions of the symbols used in Figure 3 2 The block diagram also shows all of the TMS320C2x interface pins Figure 3 3 shows the block diagram of the TMS320C26 The 5320 2 architecture is built around two major buses the prog
187. set E 26 Appendix Title Attribute Reference Running Title Attribute Reference Table 2 Instruction Set Summary continued AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC DESCRIPTION 12 11 10 9 8 7 6 K Add to auxiliary register short immediate Compare auxiliary register with auxiliary register ARO Load auxiliary register Load auxiliary register short immediate Load auxiliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate QC cu e o Qo ex X9 ex QE C INSTRUCTION BIT CODE MNEMONIC DESCRIPTION 11 10 9 8 7 6 Add P register to accumulator Load high P register Load T register Load T register and accumulator previous product Load T register accumulate previous product and move data Load T register and store P register in accumulator Load T register and subtract previous product Multiply and accumulate Multiply and accumulate with data move Multiply with T register store product in P register Multiply and accumulate previous product Multiply immediate Multiply and subtract previous product Multiply unsigned Load accumulator with P register Subtract P register from accumulator Store high P register
188. shifted as defined by the PM status bits are added to the accumulator and the result is placed in the accumulator The contents of the specified data memory address are also copied to the next higher data memory address This instruction is valid for blocks B1 and B2 and is also valid for block BO if block BO is configured as data memory The data move function is continuous across the boundary of blocks BO and B1 but cannot be used with external data memory or memory mapped registers This function is described under the instruction DMOV Note that if used with external data memory the function of LTD is identical to that of LTA Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions Load Register Accumulate Previous Product and Move Data LTD Example LTD DAT126 DP 7 PM 0 or LTD If current auxiliary register contains 1022 Before Instruction After Instruction Data Data Memory 62h Memory 62h 1022 1022 Data Data Memory Memory 62h 1023 1023 T T 62h e acc X B ACC A 4 107 LTP Load T Register and Store P Register Accumulator Syntax Operands Execution Encoding Description Words Cycles Example 4 108 Direct abel LTP Indirect label LTP ind next ARP 0 lt dma x 127 0 next ARP lt 7 PC 1 PC dma T register shifted P register
189. sign extension SXM does not affect the definition of certain instructions for example the ADDS instruction suppresses sign extension regardless of SXM This bit is set and reset by the SSXM and RSXM instructions and may also be loaded by LST1 SXM is set to 1 by RS Test control flag bit The TC bit is affected by the BIT BITT CMPR LST1 and NORM instructions The TC bit is set to a 1 if a bit tested by BIT or BITT is a 1 if a compare condition tested by CMPR exists between ARO and another AR pointed to by ARP or if the exclusive OR function of the two MSBs of the accumulator is true when tested by a NORM instruction Two branch instruc tions BBZ and BBNZ provide branching on the status of the TC 3 51 System Control Transmit mode bit TXM 1 configures the serial port s FSX pin to be an out put In this mode a pulse is produced on FSX when DXR is loaded Transmis sion then starts on the DX pin 0 configures the FSX pin to be an input is set and reset by the STXM and RTXM instructions and may also be loaded by LST1 RS resets TXM to 0 XF pin status bit This status bit indicates the state of the XF pin a general purpose output pin XF is set and reset by the SXF and RXF instructions or may be loaded by LST1 XF is set to 1 by RS 3 6 5 Timer Operation The TMS320C2x provides a memory mapped 16 bit timer TIM register and a 16 bit period PRD register as shown in Figure 3 26 The on chip timer
190. synchronize its internal clock thereby allowing the processors to run in lock step operation Multiple TMS320C2x devices are synchronized by using common SYNC and external clock inputs A negative transition on SYNC sets each processor to internal quarter phase one Q1 This transition must occur synchronously with the rising edge of CLKIN On the TMS320C25 there is atwo CLKIN cycle delay following the cycle in which SYNC goes low before the synchronized Q1 OCCUIS The timing diagram for the SYNC input is shown in Figure 3 46 for the TMS320C2x Architecture Multiprocessing and Direct Memory Access DMA Figure 3 46 Synchronization Timing Diagram TMS320C25 SYNC N 4 RS CLKOUT1 EE NL x NE CLKOUT2 ee Normally SYNC is applied while RS is active If SYNC is asserted after a reset the following can occur 1 The processor machine cycle is reset to Q1 provided that the timing re quirements for SYNC are met If SYNC is asserted at the beginning of Q1 Q3 or Q4 the current instruction is improperly executed If SYNC is as serted at the beginning of Q2 the current instruction is executed properly 2 If SYNC does not meet the timing requirements unpredictable processor operation occurs A reset should then be executed to place the processor back in a known state 3 10 2 Global Memory For multiprocessing applications the TMS320C2x
191. the usual manner In the direct addressing mode dmaz2 is used as the destination address for the block move but is not modified upon repeated executions of the instruction Thus the contents of memory at the dma2 address will be the same as the contents of memory at the last dma1 address in a repeat se quence RPT or RPTK must be used with the BLKD instruction in the indirect addres sing mode if more than one word is to be moved The number of words to be moved is one greater than the number contained in the repeat counter RPTC atthe beginning of the instruction Atthe end of this instruction the RPTC con tains zero and if using indirect addressing AR ARP will be modified to con tain the address after the end of the destination block Note that the source and destination blocks do nothave to be entirely on chip or off chip However BLKD cannot be used to transfer data from a memory mapped register to any other location in data memory The PC points to the instruction following BLKD after execution Interrupts are inhibited during a BLKD operation used with RPT or RPTK 2 Assembly Language Instructions Block Move From Data Memory to Data Memory BLKD Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Source data in on chip RAM 3 34d 342p 3 d 2p Source data in external memory 4 d 4 2d 4 d 2p 4 2d 2p Cycle Timings for a Repeat Execution Source data in on chip RAM 2 n 2 n nd 2
192. the PC stack is used Architecture System Control 3 6 2 Pipeline Operation Instruction pipelining consists of the sequence of external bus operations that occurs during instruction execution The prefetch decode execute pipeline is essentially invisible to the user except in some cases where the pipeline must be broken such as for branch instructions In the operation of the pipeline the prefetch decode and execute operations are independent which allows instruction executions to overlap Thus during any given cycle three different instructions can be active each at a different stage of completion resulting in the three level pipeline on the TMS320C2x The difference in pipeline levels does not necessarily affect instruction execu tion speed but merely changes the fetch decode sequence Most instructions execute in the same number of cycles regardless of whether they are executed from internal RAM ROM or external program memory The effects of pipelining are included in the instruction cycle timings for the TMS320C25 listed in Appendix NO TAG Additional PC related hardware see Figure 3 15 is provided on the TMS320C25 to allow three level pipelining for higher performance Included in the related hardware are the prefetch counter PFC the 16 bit microcall stack MCS register the instruction register IR and the queue instruction register QIR In the three level pipeline on the TMS320C25 the PFC contains the add
193. the TMS320C25 pipeline in reference to quarter phases 1 through 4 01 04 Figure 3 18 TMS320C25 Standard Pipeline Operation Clock CLKOUT1 CLKOUT2 STRB Address Data Decode RAMRD Execute Status AUXREG RAMWR Cycle 1 Cycle 2 Cycle 3 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 STUUUUUUU 8 uh INST1 INST2 INST3 INSTO INST2 INST ACC INSTO ACC INST INST INST 0 1 1 2 INSTO ARAU LOAD INST1 ARAU LOAD INST2 ARAU LOAD gt Ho OL The TMS320C25 machine cycle externally referenced by the falling edges of the CLKOUT1 signal consists of four internal cycles or CLKIN cycles This allows internal operations of the pipeline to execute as fast as 1 4 the machine cycle The sequence of a general instruction execution in the pipeline is shown in Table 3 5 3 39 System Control Table 3 5 Instruction Pipeline Sequence 3 40 New PC is output on address bus External read of instruction External read of instruction External read of instruction Instruction decode Instruction decode ARAU execution On chip RAM access ARAU execution On chip RAM access load new AR value update ARP ALU execution ALU execution Load accumulator 4 1 Lad status register When using
194. the value by adding 1 2 LSB that is the 15 low bits bits 0 14 of the accumulator are set to zero and bit 15 of the accumulator is set to one ZALR is a derivative instruction from ZALH Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ZALR DAT3 DP 32 or ZALR If current auxiliary register contains 4099 Before Instruction After Instruction Data Data Memory 01 01 4099 4099 77FFFFh ACC 3F018000h 4 193 ZALS Zero Accumulator Load Low Accumulator with Sign Extension Suppressed Syntax Operands Execution Encoding Description Words Cycles Example 4 194 Direct label ZALS dma Indirect label ZALS ind next ARP 0 lt dma lt 127 0 next ARP x 7 PC 1 PC 0 ACC 31 16 dma ACC 15 0 Not affected by SXM Direct 0 1 Data Memory Address NN Indirect 0 1 0 0 0 0 0 1 See Section 4 1 The contents of the addressed data memory location are loaded into the 16 low order bits of the accumulator The upper half of the accumulator is zeroed The data is treated as 16 bit unsigned number rather than a 2s complement number Therefore there is no sign extension with this instruction regardless of the state of SXM ZALS behaves the same as a LAC instruction with no shift and SXM 0 ZALS is useful for 32 bit arithmetic
195. to 1 T Pin numbers apply to CER QUAD as well as to PLCC t Input Output High impedance state Note See Appendix C for TMS320C28 signal descriptions 2 7 2 8 Pinouts and Signal Descriptions IMPORTANT NOTICE Texas Instruments Incorporated reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current TI warrants performance of its semiconductor products and related software to current specifications in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Please be aware that TI products are not intended for use in life support appliances devices or systems Use of TI product in such applications requires the written approval of the appropriate TI officer Certain applications using semiconductor devices may involve potential risks of personal injury property damage or loss of life In order to minimize these risks adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards Inclusion of TI products in such applicatio
196. to Zero Syntax Operands Execution Encoding Description Words Cycles Example 4 46 label BBNZ pma ind next ARP 0 lt pma lt 65536 0 lt next ARP x 7 If test control TC status 1 Then pma PC Else PC 2 2 PC Modify AR ARP and ARP as specified Affected by TC bit 15 14 13 12 11 10 9 8 7 1 1 1 1 1 0 Oo 1 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address if TC 1 Otherwise con trol passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or nu meric address Note that the TC bit may be affected by the BIT BITT CMPR LST1 NORM RTC and STC instructions 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p 3 p 3 p False Condition Destination anywhere 2 2 242p 2 2 Cycle Timings for a Repeat Execution not repeatable 2 PRG650 If TC 1 650 is loaded into the program counter otherwise the program counter is incremented by 2 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch on Bit Equal to Zero BBZ
197. to form the 16 bit data memory ad dress Indirect addressing accesses data memory through the eight auxiliary registers In immediate addressing the data is embedded in the instruction word s In direct addressing the instruction word contains the lower seven bits of the data memory address This field is concatenated with the nine bits of the data memory page pointer to form the full 16 bit address Thus memory is paged Appendix Title Attribute Reference Running Title Attribute Reference in the direct addressing mode with a total of 512 pages each page containing 128 words E 23 Running Title Attribute Reference repeat feature instruction set E 24 Eight auxiliary registers ARO AR7 provide flexible and powerful indirect ad dressing To select a specific auxiliary register the Auxiliary Register Pointer ARP is loaded with a value from 0 through 7 for ARO through AR7 respective ly There are seven types of indirect addressing auto increment auto decrement post indexing by either adding or subtracting the contents of ARO single indi rect addressing with no increment or decrement and bit reversal addressing used in FFTs with increment or decrement All operations are performed on the current auxiliary register in the same cycle as the original instruction fol lowed by an ARP update A repeat feature used with instructions such as multiply accumulates block moves I O transfers and table read writes
198. to zero 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable SBLK 5 12 Before Instruction After Instruction ACC 3FCOEFh ACC 3F70EFh C C Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Subtract From Auxiliary Register Short Immediate SBRK label SBRK constant 0 constant lt 255 PC 1 5 PC AR ARP 8 bit positive constant gt AR ARP 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 The 8 bit immediate value is subtracted right justified from the currently se lected auxiliary register with the result replacing the auxiliary register contents The subtraction takes place in the ARAU with the immediate value treated as an 8 bit positive integer 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable SBRK OFFh ARP 7 Before Instruction After Instruction 4 155 SC Set Carry Bit Syntax Operands Execution Encoding Description Words Cycles Example 4 156 abel SC None PC 1 PC 1 carry bit C in status register ST1 Affects C 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 The carry bit C in status register ST1 is setto logic one The carry bit may also be loaded directly by the LST1 and RC instructions
199. ty 100 us Increment Address Last No Address Yes Address First Location X Program One Pulse tw 100 us No i i Interactive Increment Verify Fail Address One Byte Mode Pass Yes No Last Address Yes t Voc Vpp 5 0 V 10 Device Failed Final Compare Verification All Bytes to Fail Original Data AE Pass Device Passed F 10 TMS320E25 EPROM Programming Programming Verification Figure F 7 Programming Timing 4 Program Verity gt VIH 12 0 Address Stable Address N 1 IL 2 VIH VOH Q8 Q1 Data In Stable Data Out Valid ViL VoL a 7 22 VCC HI VIH VIL PGM VIH VIL G VIH VIL F 2 5 Program Inhibit Programming can be inhibited by maintaining a high level input on the E pin or PGM pin F 2 6 Read The EPROM contents can be read outside of the programming cycle if the RBIT ROM protect bit has not been programmed The read mode is accom plished by setting E to zero and pulsing G low The contents of the EPROM location selected by the value on the address inputs appear 07 00 F 2 7 Output Disable During the EPROM programming process the EPROM data outputs can be disabled if desired by setting the output disable mode Depending upon the application the output disable mode can be selected by setting either
200. uonnoex3 LTA MPY Implementation Break Even Point S c 2 lt gt 9 10 11 8 Number of Multiply Accumulates to Be Performed 5 55 Advanced Arithmetic Operations Figure 5 12 Program Memory vs Number of Multiply Accumulates Program Memory in Words 5 56 MAC Implementation 4 LTA MPY Implementation Break Even Point 1 2 3 4 5 6 7 8 9 10 11 Number of Multiply Accumulates to Be Performed In numerical analysis it is often necessary to square numbers as well as add or subtract The TMS320C2x has two instructions SQRA and SQRS that ac complish this in a single machine cycle The result of the previous operation in the PR is first added to the accumulator if SQRA is used or subtracted from the accumulator if SQRS is used Then the data value addressed is squared and the result is stored in the PR Example 5 32 uses the SQRA instruction to perform the computation Software Applications Advanced Arithmetic Operations Example 5 32 Using SQRA THIS ROUTINE USES THE SQRA INSTRUCTION TO COMPUTE THE SQUARE OF THE DISTANCE BETWEEN TWO POINTS WHERE D 2 IS DEFINED AS FOLLOWS D 2 XA XB 2 YA YB 2 DIST LAC XA SUB XB SACL AT XT XA XB LAC YA SUB YB SACL XT YT YA YB SORA XT XT 2 ZAC ACC 0 SQRA YT P YT 2 ACC XT 2 APA
201. 0 N A N TLC04 14 Low pass Butterworth filter CLK 100 G 8 Analog Interface Peripherals and Applications Telecommunications Applications Figure G 6 General Telecom Applications e gs Neighborhood Cellular Concentrator 4 Phone 5087 Tone HVLI HCombo TCM29C23 Combo TCM5089 Encoder TCM1060 1030 TMS320xx DSP TCM5092 T Cell Base TGAP90x TCM5094 Station 20 VBAP Combo TCM153x Ringer TGAP901 Answering gt Machine 3 Central Office Toll Office TCM1520 Detector TSP50C1x Speech Synthesis TCM29C13 Combo TP3054 Combo PBX TCM1060 30 Transient Suppres sors TP305x 9050 51 HVLI HCombo TCM29Cxx DSP Memory Logic TCM1520 5089 TCM3105 EEREN Phones Phones 5320 DSP TCM291x Combo TCM29Cxx Combo Figure G 7 Generic Telecom Application TLC320AC01 Fine Tune Echo Cancel TMS320C25 Echo Canceler RS 232 pois TMS320C25 I F Telephone Line Control Receiver TLC320AC01 G 9 Dedicated Speech Synthesis Applications G 3 Dedicated Speech Synthesis Applications For dedicated speech synthesis applications Texas Instruments offers a fami ly of dedicated speech synthesizer chips This technology has been used in a wide range of products including games toys burglar alarms fire alarms automobiles airplanes answering machines voice mail
202. 0 lt constant lt 255 1 ACC 8 bit positive constant gt Affects OVM and C affected by OVM Not affected by SXM 15 14 13 12 1 109 8 7 6 5 4 3 2 1 0 The 8 bit immediate value is added right justified to the accumulator with the result replacing the accumulator contents The immediate value is treated as an 8 bit positive number regardless of the value of SXM 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable ADDK 5h Before Instruction After Instruction es em C 4 31 ADDS Aad to Accumulator With Sign Extension Suppressed Syntax Direct label ADDS Indirect abel ADDS next ARP Operands 0 lt dma 3127 0 next ARP lt 7 Execution PC 1 ACC dma ACC dma is a 16 bit unsigned number Affects OV affected by OVM Affects C Not affected by SXM 5 14 13 12 7 6 5 4 3 2 1 0 1 11 10 9 8 Direct 9 1 0 0 1 0 0 1 Data Memory Address Indirect 1 0 o 1 0 0 1 See Section 4 1 Description The contents of the specified data memory location are added with sign exten sion suppressed The data is treated as a 16 bit unsigned number regardless of SXM The accumulator behaves as a signed number Note that ADDS pro duces the same results as an ADD instruction with SXM 0 anda shift count of 0 Encoding Words Cycles
203. 00 4 1 011 5 42 70 31 20 6 203000 7 1 000 8 0 111 9 0 110 10 0 101 11 0 100 12 0 011 13 0 0 1 0 14 0 001 MSB 15 0 000 Words 1 Cycles 4 52 Assembly Language Instructions Test Bit BIT Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example BIT Oh 8h DP 488 or BIT 8 If current auxiliary register contains OF400h Data Before Instruction Data After Instruction F400h F400h TC Oh TC 1h 4 53 BITT Test Bit Specified by T Register Syntax Direct label BITT dma Indirect label BITT ind next ARP Operands 0 lt dma 3127 0 x next ARP lt 7 Execution PC 1 PC dma bit at bit address 15 register 3 0 TC Affects TC Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 1 0 e a PS 1 Data Memory Address Indirect 1 0 1 0 1 1 1 See Section 4 1 Description The BITT instruction copies the specified bit of the data memory value to the TC bit of status register ST1 Note that the BIT CMPR LST1 and NORM instructions also affect the TC bit in status register ST1 The bit address is spe cified by a bit code value contained in the LSBs of the T register as given in the following table Bit Code Bit Address 3210 LSB 0 1111 1 1110 2 1222021 3 1100 4 1011 5 010 6 001 7 1000 8 Ae T 9 0110 10 0101 HI 0100 12 0011 13 0010 14 0001 MSB 15 0000 Word
204. 023 1024 0000h 0005 0006 005F 0060 007Fh 0080h O1FFh 0200h O2FFh 0300h O3FFh 0400h 65 535 OFFFFh Memory Organization Data On Chip Memory Mapped Registers Page 0 On Chip Block B2 On Chip Block BO Pages 4 5 On Chip Block 1 Pages 6 7 Data On Chip Memory Mapped Registers On Chip Block B2 di Does Not 2 0 On Chip Block 1 Pages 6 7 3 19 Memory Organization Figure 3 9 TMS320C26 Memory Maps Program 0000h Interrupts and Reserved 001Fh External 0020h External FFFFh If MP MC 1 Microprocessor Mode Program 0000h Interrupts and Reserved 001Fh External 0020h External F9FFh FA00h On Chip FBFFh Block BO 00 FDFFh FEOOh FFFFh If MP MC 1 Microprocessor Mode 3 20 Program 0000h 0000h Interrupts and Reserved Bootload ROM 00FFh 0005h 0100h 0006h Reserved 005Fh OFFFh 0060h 1000h 007Fh 0080h 01FFh 0200h External 03FFh 0400h O5FFh 0600h 07FFh 0800h FFFFh It MP MC 0 Microcomputer Mode Memory Maps After a CONF 0 Instruction and After Reset Program Interrupts and Reserved Bootload ROM If MP MC 0 Microcomputer Mode a Memory Maps After a CONF 1 Instruction Data On Chip Memory Mapped Registers On Ch
205. 0C2x Data Sheets in Appendix A For further information about read and write operation see subsection 3 7 3 Throughout this chapter Q is used to indicate the duration of a quarter phase of the output clock CLKOUT1 or CLKOUT2 Memory interfaces discussed in this chapter assume that the TMS320C2x is running at 40 MHz that is 25 ns In a read cycle the following sequence occurs 1 Near the beginning of the machine cycle CLKOUT1 goes low the ad dress bus and one of the memory select signals PS DS or IS becomes valid goes high to indicate a read cycle 2 STRBgoeslownoless than tgy a 12 ns after the address bus is valid 3 Early in the second half of the cycle the READY input is sampled READY must be stable low or high at the 5320 25 no later than ta sL R 20 ns after STRB goes low 4 With no wait states READY is high data must be available no later than ta SL la A tsu a 2Q 23 ns after STRB goes low The sequence of events that occurs during an external write cycle is the same as the above with the following differences 1 R W goes low to indicate a write cycle 2 The data bus begins to be driven approximately concurrently with STRB going low 3 After STRB goes high the data bus must enter a high impedance state no later than tgis p 15 ns 6 2 1 Interfacing PROMs 6 12 Program memory in a TMS320C2x system can be implemented through the use of P
206. 1 PC 16 LSBs of ACC x 28hift gt dma Not affected by SXM 5 14 13 1 10 9 8 7 6 5 4 3 2 1 0 1 2 11 Direct 1 1 0 0 Data Memory Address Indirect 1 1 0 0 See Section 4 1 The low order bits of the accumulator are shifted left O to 7 bits on the TMS320C2x as specified by the shift code and stored in data memory The low order bits are filled with zeros and the high order bits are lost The accu mulator itself is unaffected Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SACL DAT11 1 DP 4 or SACL 1 If current auxiliary register contains 523 Before Instruction After Instruction ACC 7C638421h acc x 70638421h Data Data 523 523 4 151 Store Auxiliary Register Syntax Operands Execution Encoding Description Words Cycles 4 152 Direct label SAR AR Indirect label SAR AR ind next ARP 0 lt dma x 127 0 lt auxiliary register AR x 7 0 next ARP x 7 PC 1 PC AR gt dma 15 14 13 12 11 7 0 1 1 1 0 10 9 8 6 5 4 3 2 1 0 1 0 ah a onm Indirect 0 1 1 1 0 See Section 4 1 The contents of the designated auxiliary register AR are stored in the ad dressed data memory location When you are modifying the contents of the current auxiliary register in the in direct addressing mode SAR ARn when n ARP stores the
207. 10 TMS320C10 14 25 TMS320C14 TMS320E14 P14 TMS320C15 LC15 TMS320E15 P15 TMS320C15 25 TMS320E15 25 TMS320C16 TMS320C17 LC17 TMS320E17 P17 222222 LLLLLLLLLLLL LLL GENERATION Fixed Point Generations NS Floating Point Generations Plans for expansion of the TMS320 family include more spinoffs of the existing generations as well as more powerful future generations of digital signal pro cessors The TMS320 family combines the high performance and specialized features necessary in digital signal processing DSP applications with an extensive program of development support including hardware and software develop ment tools product documentation textbooks newsletters DSP design work shops and a variety of application reports See Appendix K for a discussion of the wide range of development tools available General Description The combination of the TMS320 s Harvard type architecture separate pro gram and data buses and its special digital signal processing instruction set provide speed and flexibility to execute 12 8 MIPS million instructions per se cond The TMS320 family optimizes speed by implementing functions in hardware that other processors implement through software or microcode This hardware intensive approach provides the design engineer with power previously unavailable on a single chip The TMS320C2x generation includes six members TMS320C25
208. 13 The ARB ARP DP IMR OVM and TC bits are not initialized by reset Therefore it is critical that you initialize these bits in software following re set Execution starts from location 0 of program memory when the RS signal is tak en high Note that if RS is asserted while in the hold mode normal reset opera tion occurs internally but all buses and control lines remain in the high imped ance state Uponrelease of HOLD and RS execution starts from location zero The 5320 2 be held in the reset state indefinitely p M A A AA Note Reset does not have internal Schmidt hysteresis To insure proper reset op eration avoid slow rise and fall times 3 6 4 Status Registers Two status registers STO and ST1 contain the status of various conditions and modes The status registers can be stored into data memory and loaded from data memory thus allowing the status of the machine to be saved and restored for interrupts and subroutines All status bits are written to and read from using LST LST1 and SST SST1 instructions respectively with the ex ception of INTM which cannot be loaded via an LST instruction Figure 3 24 shows the organization of both status registers indicating all sta tus bits contained in each Note that the DP ARP and ARB registers are shown as separate registers in the processor block diagram of Figure 3 2 Because these regi
209. 2 2 Instruction Set Summary 4 13 4 3 Individual Instruction Descriptions 4 18 Software Applications 5 1 5 1 Processor Initialization 5 2 5 1 1 TMS320C26 Download Bootstrapping Modes 5 6 52 Program Control iek reena a a a 5 22 5 25 ERE EE IU 5 22 5 2 2 Software fae ties ee dae eee wed ad 5 24 5 23 Timer Operation 5 25 5 2 4 Single Instruction LOOPS 5 26 5 25 Computed 5 28 5 3 Interrupt Service Routine 5 29 5 3 1 Context Switching 5 29 5 9 2 Interrupt Prionty 5 32 5 4 Memory Management 5 33 5 41 Block MOVOS cerime nls Ste oe E Se us 5 33 5 4 2 Configuring On Chip RAM 5 35 5 4 8 Using O
210. 20C2x This shift is performed while the data is being transferred to the data bus for storage The contents of the accumulator re main unchanged When the ACCH data is shifted left the LSBs are transferred from the ACCL and the MSBs are lost When is shifted left the LSBs are zero filled and the MSBs are lost The TMS320C2x supports floating point operations for applications requiring a large dynamic range The NORM normalization instruction performs left shifts to normalize fixed point numbers contained in the accumulator The LACT load accumulator with shift specified by the T register instruction de normalizes a floating point number by arithmetically left shifting the mantissa through the input scaling shifter The shift count in this case is the value of Architecture Central Arithmetic Logic Unit CALU the exponent specified by the four low order bits of the T register TR ADDT and SUBT add to subtract from accumulator with shift specified by the T regis ter instructions have also been provided to allow additional arithmetic opera tions The accumulator overflow saturation mode may be programmed through the SOVM ROVM set reset overflow mode instructions When the accumu lator is in the overflow saturation mode and an overflow occurs the overflow flag is set and the accumulator is loaded with either the most positive or the most negative number depending upon the direction of overflow The value of t
211. 25 Figure 6 6 27 74ALS04 inverter rise time tPLH 11 ns max Total address access time ta A tsu A ta A SL 22 ns Total enable access time ta s H tsu A ta E SL 18 ns max T Becauseta E SL ta A SL thespecificationta A dominates performance Alltiming compari max TMP38L 165 35 access time from chip enable 20 ns max t t sons are made from strobe low The second design example illustrates the interface of PROMs to the TMS320C25 using address decoding An approach that can be used to meet the READY timing requirements is shown in Figure 6 7 This design utilizes one address decoding scheme to generate READY and a second address de coding scheme to enable the different memory banks In this design the me mories with no wait states are mapped at the upper half upper 32K of the pro gram space The lower half is used for memories with one or more wait states This decoding is implemented with the 74AS20 four input NAND gate Interfacing Memories Address decoding is implemented by the 74AS138 This decoding separates the program space into eight segments of 8K words each The first four of these segments lower 32K of address space are enabled by the YO 1 Y2 and Y3 outputs of the 74AS138 These segments are used for memories with one or more wait states The other four segments select memories with no wait states the TBP38L165s are mappedin segment 5 starting a
212. 25 perform a signed multiply operation in the multiplier That is the two numbers being multiplied are treated as 2s complement numbers and the result is a 32 bit 2s complement number As shown in Figure 3 13 the fol lowing two registers are associated with the multiplier 1 A 16 bit temporary register TR that holds one of the operands for the multiplier A 32 bit product register PR that holds the product Architecture Central Arithmetic Logic Unit CALU The output of the product register can be left shifted 1 or 4 bits This is useful for implementing fractional arithmetic or justifying fractional products The out put of the PR can also be right shifted 6 bits to enable the execution of up to 128 consecutive multiply accumulates without the possibility of overflow LT load T register instruction normally loads the TR to provide one oper and from the data bus and the MPY multiply instruction provides the se cond operand also from the data bus A multiplication can also be performed with an immediate operand using the MPYK instruction In either case a prod uct can be obtained every two cycles Two multiply accumulate instructions MAC and MACD fully utilize the com putational bandwidth of the multiplier allowing both operands to be processed simultaneously The data for these operations may reside anywhere in internal or external memory or can be transferred to the multiplier each cycle via the prog
213. 281 0 0 2 L 2 5 1 4 floppy disk 8 1600 BPI magnetic tape QUALIFICATION Sus TMDX prototype TMDS qualified S W FORMATT 0 object code 1 source code DEVICE FAMILY 32 TMS320 family PRODUCT TYPE SEQUENCE NUMBERt 4 software 6 hardware 8 upgrade MODELft GENERATIONt 11 XDS 11 1 22 XDS 22 2 C2x 88 upgrade kits 3 C3x 4 4 5 5 OPERATING SYSTEMT FORMATT 02 C1x VAX VMS 1 Tl tagged 08 C1x IBM MS PC DOS 5 COFF 22 C2x VAX VMS 28 C2x IBM MS PC DOS 32 C3x VAX VMS 38 C3x IBM MS PC DOS 42 C4x VAX VMS 48 C4x IBM MS PC DOS 52 C5x VAX VMS 58 C5x IBM MS PC DOS 1 Software only Hardware only 4 Development Support A D interface 6 43 6 45 A law 5 68 ABS 4 23 ACC 3 9 accumulator 3 9 3 30 carry bit 3 31 adapter socket See EPROM programmer adaptive filtering 5 71 ADD 4 25 ADDC 4 27 ADDH 4 29 addition 3 31 C25 and C26 5 64 ADDK 4 9 4 31 address bus 3 9 address bus A15 A0 2 4 addressing modes 3 25 3 26 direct 3 25 indirect 3 25 ADDS 4 32 ADDT 4 34 ADLK 4 9 4 36 ADRK 4 9 4 37 ADTV G 18 AFB 3 9 AIB2 K 1 ALU 3 9 3 30 analog converters H 2 Index analog interface peripherals advanced digital applications G 18 G 20 audio video analog digital interface devices G 20 digital audio G 19 video signal processing G 19 applications G 1 G 20 disk drive appli
214. 3 041 Q1 Q2 Clock CLKOUT1 l l l l CLKOUT2 1 1 l 1 1 1 1 1 1 STRB J 1 1 1 1 Address ADD 12 AR4 Wait State SACL 0 3 AR2 Wait State OR Decode ADD SACL RAM ADD Read SACL Write Execute ADD Dummy AUXREG Multiplexed External Data Bus The external data bus is multiplexed to sup port all three memory spaces of the TMS320C25 Therefore external fetches to multiple spaces in the same instruction add additional machine cycles to the pipeline execution of the instruction This is due to the fact that the external fetch takes a full cycle whereas the internal equivalent takes two quarter phases and can be included in the execution stage of the three deep pipeline Accessing the data memory space is controlled by setting of the data page pointer or the value contained in the auxiliary register used in any instruction Also affecting the pipeline is the access of the I O bus or the tables in program memory thatis IN OUT TBLR and TBLW Figure 3 21 shows how the pipe line processes an instruction with external program and data access 3 42 Architecture System Control Figure 3 21 Pipeline With External Data Bus Conflict Clock CLKOUT1 CLKOUT2 STRB PS DS Address Data Decode EXTRAM Execute Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q2 Q4 Q1 Q2 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 manuun
215. 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 Input data from port 2 1 1 1 1 1 1 1 2 2 1 1 Complement accumulator Compare auxiliary register with ARO Configure block as data memory Configure block as program memory Configure block as data program memory Disable interrupt Data move in data memory Enable interrupt Format serial port registers Idle until interrupt LAC Load accumulator with shift LACK LACT LALK LAR Load auxiliary register Load accumulator short immediate Load accumulator with shift specified by T register Load accumulator long immediate with shift K 17 Running Title Attribute Reference LARK Load auxiliary register short immediate LARP Load auxiliary register pointer Load data memory page pointer T Cycles using full speed on chip external program memory These instructions are not available on the TMS32020 This instruction configures RAM blocks BO B1 on the TMS320C26 replacing instructions CNFD and CNFP Instruction Set Summary Continued ae T register accumulate previous product move PYRE MEYS Mev NEG NOP NORM ORK 22 out PAG PORD ao a a a ay aya aya K 18 Appendix Title Attribute Reference Running Title Attribute Reference Store auxiliary register SBLK Subtract
216. 3 48 4 1 4 2 Ld ELA po LL f I E ubt bs NVa Boo Tipp d ppl tg ee ee Burst Mode Serial Port Transmit Operation 3 68 Burst Mode Serial Port Receive Operation 3 68 Byte Mode DRR Operation 5320 25 3 69 Serial Port Transmit Continuous Operation 1 3 70 Serial Port Receive Continuous Operation 1 3 70 Serial Port Transmit Continuous Operation 0 3 72 Serial Port Receive Continuous Operation FSM 0 3 72 Continuous Transmit Operation Initialization 3 74 Continuous Receive Operation 3 74 Synchronization Timing Diagram 7 5320 25 3 76 Global Memory Access Timing 3 77 TMS320C25 Hold Timing Diagram 3 80 Direct Addressing Block Diagram 4 3 Indirect Addressing Block Diagram 4 4 BIO XF Handshake 5 7 Sequ
217. 4 1 Description Status register STO is loaded with the addressed data memory value Note that the INTM interrupt mode bit is unaffected by LST ARB is also unaffected even though a new ARP is loaded If a next ARP value is specified via the indi rect addressing mode the specified value is ignored Instead ARP is loaded with the value contained within the addressed data memory word The LST instruction is used to load status register STO after interrupts and sub routine calls The STO contains the status bits OV overflow flag bit OVM overflow mode bit INTM interrupt mode bit ARP auxiliary register pointer and DP data memory page pointer These bits were stored by the SST instruction in the data memory word as follows 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Ame Words Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 98 Assembly Language Instructions 1 2 3 4 Load Status Register STO LST LARP 0 LST data memory word addressed the contents auxiliary register ARO is loaded into status register STO except for the INTM bit Note that even though a next ARP value is Specified that value is ignored and even though a new ARP is loaded the old ARP is not loaded into ARB LST 60h DP 0 Before In
218. 6 10 and Figure 6 11 respectively In the case of one wait state time t4 in Figure 6 11 is the time from address valid to memory select of the particular device that requires the wait state This corresponds to the propagation delay through the address decode logic For a 74AS138 decoder t4 10 ns max Time to is the time from memory select going low to CLKOUT2 going low t2 tp tsu 11 ns 20 ns 31 ns Time tg is the time from CLKOUT2 going low to READY going high t3 19 ns 5 ns 24 ns Hardware Applications Interfacing Memories READY must remain high until it is sampled again shortly after CLKOUT1 goes high In Figure 6 10 READY remains high well after CLKOUT1 goes high On the falling edge of CLKOUT2 J 1 and 1 are the inputs to the J K flip flop this places the flip flop in a toggle mode When CLKOUT2 goes low Q goes back to logic 1 READY goes low and stays low until one of the inputs of the 74AS30 is pulled low To implement two wait states a second J K flip flop is utilized as shown in Figure 6 10 This delays READY going high by an additional machine cycle see Figure 6 11 If more wait states are required additional J K flip flops must be included in the wait state generator design Figure 6 10 Wait State Generator Design 1kQ 5 NM 1 2 74ALS20A 3 10 1 2 74ALS114A t t le 4 74 530 1 2 74ALS20A Ready to TMS320C25 From 1 2 74ALS114A T
219. 8 4 10 IMR 3 10 3 60 IN 4 84 5 34 indexed addressing 5 62 indirect addressing 4 4 4 8 arithmetic operations 4 6 bit fields 4 7 diagram 4 4 format examples 4 8 symbols used 4 5 types of 4 5 initialization 5 2 C25 5 3 C26 5 4 examples 5 3 5 5 processor configuration 5 2 TMS320C26 download bootstrapping mode See bootloader instruction cycle timings C25 5 2 instruction register 3 10 instruction set 4 11 example 4 19 4 22 ABS 4 23 ADD 4 25 ADDC 4 27 ADDH 4 29 ADDK 4 31 ADDS 4 32 ADDT 4 34 ADLK 4 36 ADRK 4 37 AND 4 38 ANDK 4 40 APAC 4 41 B 4 42 BACC 4 43 BANZ 4 44 BBNZ 4 46 BBZ 4 47 BC 4 48 BGEZ 4 49 BGZ 4 50 BIOZ 4 51 BIT 4 52 BITT 4 54 BLEZ 4 56 BLKD 4 57 BLKP 4 60 BLZ 4 63 Index 5 Index instruction set continued 4 11 BNC 4 64 BNV 4 65 BNZ 4 66 BV 4 67 BZ 4 68 CALA 4 69 CALL 4 71 CMPL 4 73 CMPR 4 74 CNFD 4 75 4 76 CONF 4 77 DINT 4 78 DMOV 4 79 EINT 4 81 FORT 4 82 IDLE 4 83 IN 4 84 LAC 4 85 LACK 4 86 LACT 4 87 LALK 4 89 LAR 4 90 LARK 4 92 LARP 4 93 LDP 4 94 LDPK 4 95 LPH 4 96 LRLK 4 97 LST 4 98 LST1 4 100 LT 4 103 LTA 4 104 LTD 4 106 LTP 4 108 LTS 4 109 MAC 4 111 MACD 4 114 MAR 4 117 MPY 4 119 MPYA 4 120 MPYK 4 121 MPYS 4 122 MPYU 4 123 NEG 4 125 NOP 4 126 NORM 4 127 OR 4 129 ORK 4 130 Index 6 instruction set continued 4 11 OUT 4 131 PAC
220. 9 o2 16 218105 8 QIR 16 16 16 STO 16 R W 16 ST1 16 STRE RPTC 8 16 Sm BR 16 18 DR XF 1eNMUX 16 CLKR HOLD d FSR HOLDA PC 16 DX MSC 16 CLKX 0 16 16 ae ntis Tack ones 5807 ADDRESS 15 PROGRAM ROM A 16 paisa 1 INSTRUCTION foa a6 16 3 D15 D0 16 1 PROGRAM BUS DATA BUS 16 16 16 16 SHIFTER 0 16 MUX 91 1 gt MULTIPLIER AR3 16 DP 9 7LSB PR 32 ARB 16 o FROM 2 16 2 E e 3 SHIFTER 6 0 1 4 16 LUD DATA PROG DATA PROG DATA PROG 32 RAM 512 x 16 ACCH 16 ACCL 16 32 16 16 16 16 DATA BUS LEGEND ACCH Accumulator high IFR Interrupt flag register PC Program counter ACCL Accumulator low IMR interrupt mask register PFC Prefetch counter ALU Arithmetic logic unit IR Instruction register Repeat instruction counter ARAU Auxiliary register arithmetic unit MCS Microcall stack GREG Global memory allocation register ARS Auxiliary register pointer buffer QIR Queue instruction register RSR Serial port receive shift register ARP Auxiliary register pointer PR Product register XSR Serial port to transmit shift register DP Data memory page pointer PRD Product register for timer ARO AR7 Auxiliary registers E 9 DRR Serial port data receive register
221. A MEMORY PAGE 0 SPM 0 NO SHIFT ON PRODUCT REGISTER OUTPUT LARP ARA USE AUXILIARY REGISTER 4 SET ARP 4 LARK AR4 PRD POINT AR4 TO PERIOD REGISTER LALK OFFFFh SET ACCUMULATOR TO OOOOFFFFh SACL 2 PERIOD REGISTER WITH MAXIMUM VALUE SACL ENABLE ALL INTERRUPTS VIA IMR ZAC CLEAR ACCUMULATOR SACH CLEAR GREG TO MAKE ALL MEMORY LOCAL LOAD TIME CRITICAL CODE FROM EXTERNAL SLOW MEMORY TO INTERNAL RAM LARP 1 USE AUXILIARY REGISTER 1 SET ARP 1 AR1 PROGR POINT AR1 TO RECONFIGURABLE BLOCK BO RPTK PROGL 1 LOAD REPEAT COUNTER WITH BLOCK LENGTH BLKP P1_START OVE CODE FROM PROG MEMORY TO ON CHIP RAM INITIALIZE PARAMETERS FOR EXECUTION LDPK 6 x DP REGISTER TO DATA MEMORY PAGE 6 LACK 1 SET ACCUMULATOR 0001 SACL ONE STORE VALUE OF 1 AR1 COEFF i AR1 TO INTERNAL MEMORY ADDRESS RPTK COEFL 1 REPEAT COUNTER WITH BLOCK LENGTH BLKP C1 START OVE DATA FROM PROG MEMORY TO ON CHIP RAM CNFP CONFIGURE BLOCK B0 AS PROGRAM MEMORY LEIS LOAD ACC WITH PROG ADDR IN INTERNAL RAM BACC BRANCH TO ON CHIP EXECUTION ADDRESS SIGNAL PROCESSING CODE TO BE EXECUTED FROM ON CHIP RAM asect on chip 0FF00h PROG label P1 START LPTS BIOZ GE WAIT FOR INPUT SIGNAL B LPTS BRANCH IF NO SIGNAL 5 39 Memory Management
222. AINS PRODUCT The algorithm in Example 5 38 executes in 22 machine cycles The key to this performance is the parallel addressing of both multiplicands simultaneously The operation is made possible by the use of the data bus to fetch one multipli cand and the program bus to fetch the other The auxiliary register indexes down the column of one matrix while the PC generates incremental addres sing of each row of the other matrix Each cycle of the repeat loop performs the following operations 1 Accumulates the previous product 2 Multiplies the row element times the column element 3 Increments the row address and 4 Indexes the column address 5 6 9 Extended Precision Arithmetic 5 62 Numerical analysis floating point computations or other operations may re quire arithmetic to be executed with more than 32 bits of precision Since the TMS320C2x processors are 16 32 bit fixed point devices software is required forthe extended precision of arithmetic operations A subroutine that performs the extended arithmetic function for the TMS320C25 is provided in the exam ples of this section The technique consists of performing the arithmetic by parts similar to the way in which longhand arithmetic is done Software Applications Advanced Arithmetic Operations The TMS320C25 has two features that help to make extended precision cal culations more efficient One of the features is the carry status bit This bit is
223. AL BATA80 15 37 0 605 NOM 68 pin GB grid array ceramic package 28 448 1 120 VIEW 15 37 0 605 27 422 1 080 NOM R Junction to free air 9JA thermal resistance Junction to case PeJC thermal resistance 4 572 0 180 1 397 0 055 2 794 0 110 1 143 0 045 3 556 0 140 3 048 0 120 0 508 0 020 Jl 1 575 0 062 0 406 0 016 1 473 0 058 2 54 0 100 4 gt 9909000690 2 54 1 00 _ 1 778 0 070 NOM 68 PLACES E 1 27 0 050 NOM 0o0oommorcmnmr 9 9 9 ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES E 52 Appendix Title Attribute Reference TMS320E25 EPROM Programming This appendix describes the TMS320E25 EPROM cell The TMS320E25 in corporates a 4K x 16 bit EPROM which is implemented from a standard TMS27C64 EPROM cell This expands the capabilities of the TMS320E25 in the areas of prototyping early field testing and production Key features of the EPROM cell include standard programming techniques with verification capability of all bits The EPROM cell features an internal mechanism for security purposes This prevents all proprietary data from be ing read and thereby protec
224. BITT and BBNZ THIS ROUTINE USES THE BITT INSTRUCTION TO TEST THE CONDITION OF AN EXTERNAL MUX A BIT IN HE MUX IS SIGNIFICANT ONLY WHEN PRIOR PROCESSING HAS DESIGNATED THE BIT TO BE ACTIVE INDIVIDUAL PROCESSING WILL TAKE PLACE BASED UPON HE STATE OF THE ESTED BIT THE BITS AR TESTED EACH TIME A TIMER INTERRUPT OCCURS TIME SST STO SAVE STATUS REGISTER STO LDPK 0 LARP AR3 LAR AR3 BCNT LOAD COUNT OF ACTIVE BITS LRLK AR4 BTBL THE BIT TABLE ADDRESS IN DAT PA8 READ IN VALUE B LTEST 4 TMLOOP LT KRT LOAD BIT CODE BITT DAT TESI SPECIFIED BIT BBNZ LTES BRANCH IF BIT IS ONE LTEST BANZ TMLOOP 4 LST STO d ELOAD THE STATUS REGISTER ABLE INTERRUPTS RE RETUR O INTERRUPTED ROUTINE z Fd 5 45 Advanced Arithmetic Operations 5 6 Advanced Arithmetic Operations 5 6 1 5 46 The TMS320C2x provides instructions such as MACD SQRA SUBC and NORM that facilitate efficient execution of arithmetic intensive DSP algo rithms Explanations and examples of how to use these instructions with over flow management and for data move multiplication accumulation division floa
225. Bs of an instruction word to form a direct memory address of 16 bits DP may be modified by the LST LDP and LDPK instructions 3 50 Architecture System Control 0 1 CNFO and CNF1 are the on chip RAM configuration control bits forthe TMS320C26 Depending on the status of these 2 bits one of the 4 figuration modes can be selected RS resets both and CNF1 to 0 Format bit When set to 0 the serial port registers are configured as 16 bit registers When set to 1 the port registers are configured to receive and transmit eight bit bytes FO may be modified by the FORT and LST1 instruc tions FO is reset to 0 Frame synchronization mode bit This bit indicates whether the serial port op erates with or without frame sync pulses When FSM 1 the serial port op erationis initiated following a frame sync pulse on the FSX FSR inputs When FSM 0 the FSX FSR inputs are ignored and the serial port operates contin uously with no frame sync pulses required The bit is set to 1 by a reset Table 3 6 Status Register Field Definitions Continued Hold mode bit When HM 1 the processor halts internal execution when acknowledging an active HOLD When HM 0 the processor may continue execution out of internal program memory but puts its external interface in a high impedance state This bit is set to 1 by a reset Interrupt mode bit When setto 0 all unmasked interrupts are enabled When set to 1 all maskabl
226. C ACC XT 2 YT 2 D 2 RET RETURN TO MAIN PROGRAM When performing multiply and accumulate operations you may choose to shift the product before adding it to the accumulator You can do both simulta neously with the MAC instruction by using the product shift mode on the TMS320C2x This mode controlled by two bits in the PM field of status register shifts the value from the PR while itis transferred to the accumulator The contents of the PR are not shifted 5 6 6 Division Division is implemented on the TMS320C2x by repeated subtractions using SUBC a special conditional subtract instruction Given a 16 bit positive nu merator and denominator the repetition of the SUBC command 16 times pro duces a 16 bit quotient in the low accumulator and a 16 bit remainder in the high accumulator SUBC implements binary division in the same manner as is commonly done in long division The numerator is shifted until subtracting the denominator no longer produces a negative result For each subtraction that does not produce a negative answer a one is putin the LSB of the quotient and then shifted The shifting of the remainder and quotient after each subtraction produces the sep aration of the quotient and remainder in the low and high halves of the accumu lator There are similarities between long division and the SUBC method of division Both methods are used to divide 33 by 5 in Example 5 33 The condition of the denominator le
227. C25 provides two modes of operation that allow the use of a con tinuous stream of serial data When FSM 1 frame sync pulses are required Because DXR is double buffered continuous operation is achieved even if TXM 1 Writing to DXR during a serial port transmission does not abort the transmission in progress but instead DXR stores that data until XSR can be reloaded As long as DXR is reloaded before the CLKX rising edge on the final bit being transmitted the FSX pulse will go high on the rising edge of CLKX during the transmission of the final bit and fall on the next rising edge when transmission of the word just loaded begins If DXR is not reloaded within this period and FSM 1 the DX pin will be placed in a high impedance state for at least one CLKX cycle until DXR is reloaded as described in the previous section Figure 3 40 and Figure 3 41 show the timing diagrams for the con tinuous operation with frame sync pulses Architecture Serial Port Figure 3 40 Serial Port Transmit Continuous Operation FSM 1 FSX TXM 1 TAE TREE ES al DX CAL CAS XEXE XB X BBX Ci X_C2 FO 1 MSB LSB XINT t t t t DXR XSR DXR XSR Loaded Loaded Loaded Loaded With B With C Figure 3 41 Serial Port Receive Continuous Operation FSM 1 IN AO AO CN NO AO OO AO AO
228. CC bk i 2 16 errf x i 2 15 SACH SAVE bk i 1 When the MPYA and ZALR instructions on the TMS320C25 are used the adaptation reduces to three instructions corresponding to three clock cycles as shown in the following instruction sequence Note that the processing order has been slightly changed to incorporate the use of the MPYA instruction This is due to the fact that the accumulation performed by the MPYA is the accu mulation of the previous product AR2 COEFFD LOAD ADDRESS OF COEFFICIENTS AR3 LASTAP LOAD ADDRESS DATA SAMPLES LARP AR2 T ERRF errf 2 B e i ZALR AR3 ACC bk i 2 16 2 15 MPYA 2 2 ACC DK i 2 l16 F Grrf x r Sik F 729 15 PREG errf x i k 1 SAVE bk i 1 SACH Example 5 43 shows a routine to filter a signal and update the coefficients Example 5 44 provides the conclusion to the adaptive FIR filter routine for the TMS320C25 Adaptive filter length is restricted both by execution time and memory Due to the adaptation there is more processing to be completed per sample and the adaptation itself dictates that the coefficients be stored in the reconfigurable block of on chip RAM Thus the practical limit of an adaptive filter with no ex ternal data memory is 256 taps 5 72 Software Applications Example 5 43 256 Adaptive FIR Filter Dd
229. CCITT G 721 16 kbps sub band coding and linear predictive coding are frequently used in voice transmission and storage The speed of the TMS320C2x in performing arithmetic computations normaliza tion and bit manipulation enables itto implement these functions usually inter nally that is with no external devices Figure 6 33 shows a voice coding sys tem consisting of a TMS320C2x DSP 29 16 codec or TLC32040 AIC and optional external memory Figure 6 33 Voice Coding System 29 16 TMS320C2x Codec Analog or Interface TLC32040 AIC External Data Memory Optional 6 49 System Applications 6 6 4 Graphics and Image Processing In graphics and image processing applications a signal processor s ability to interface with a host processor is important The TMS320C2x multiprocessor interface enables it to be used in a variety of host coprocessor configurations see Figure 6 34 for an example of a graphics system configuration Graph ics and image processing applications can use the large directly addressable external data memory space and global memory capability to share graphical images in memory with a host processor thus minimizing data transfers In dexed indirect addressing modes on the TMS320C2x allow matrices to be pro cessed row by row when matrix multiplication is performed for 3 D image rota tion translation and scaling Figure 6 34 Graphics System Control DSP GSP Data
230. CKSUM or SYNCHRONIZATION words Figure 5 4 Building LENGTH From STATUS and PROGRAM LENGTH Words STATUS PROGRAM LENGTH D on t Care Word Bits D7 D6 D4 D2 DO XX XXX 5 9 Processor Initialization 5 10 PROGRAM WORD 1 or 2 BIO XF transfers The next LENGTH program words are then loaded into the internal RAM fol lowed by external data RAM at 0800h In the 8 bit mode two words are trans ferred for each complete program word That is 4K transfers will result in up to 2K program words received Also note that the maximum length can extend past the last address of block B3 into external data memory by 512 words In the 8 bit mode the byte sequence is low to high CHECKSUM 1 or 2 BIO XF transfers The CHECKSUM word verifies the correct result ofthe transfer The checksum is defined as the lower 16 bits of the sum of all program words transferred The checksum does not include any control words or the final checksum sent by the host After completing the program transfer the host transmits a precalcu lated checksum and the C26 returns the status on the XF line and port PAO The checksum status definitions are shown below In the 8 bit mode the byte sequence is low to high 0 or 00h indicates a checksum error 1 or PAOZOFFh indicates a correct checksum Note If checksum error occurs this will cause the normal BIO XF hand shake to fail A host timeout loop cou
231. CPU cycles for a 256 tap adaptive FIR filter implementation using the TMS320C25 Note that n 256 in the table Table 5 2 256 Tap Adaptive Filtering Memory Space and Time Requirements Words In Memory CPU Cycles Data Program 5 74 Software Applications Application Oriented Operations 5 7 4 Fast Fourier Transforms FFT Fourier transforms are an important tool used often in digital signal processing systems The purpose of the transform is to convert information from the time domain to the frequency domain The inverse Fourier transform converts in formation back to the time domain from the frequency domain Implementa tions of Fourier transforms that are computationally efficient are known as Fast Fourier Transforms FFTs The theory and implementation of FFTs has been discussed in an application report in the book Digital Signal Processing Ap plications with the TMS320 Family literature number SPRAO12A The TMS320C25 reduces the execution time of all FFTs by virtue ofits 100 ns instruction cycle time In addition to the shorter cycle time an addressing fea ture has been added to the TMS320C25 which provides execution speed and program memory enhancements for radix 2 FFTs As demonstrated Figure 5 13 and Figure 5 14 the inputs or outputs of an FFT are not in se quential order that is they are scrambled The scrambling of the data ad dressing is a direct result of the radix 2 FFT derivation Observation of the fig
232. Cancellation Digital signal processing is extensively used in telecommunications applica tions In echo cancellation an adaptive FIR filter performs the modeling rou tine and signal modifications required to adaptively cancel the echo caused by impedance mismatches in telephone transmission lines The TMS320C25 s large on chip RAM of 544 words and on chip ROM of 4K words allow it to execute a 256 tap adaptive filter 32 ms echo cancellation without external data or program memory Figure 6 31 shows a common configuration for an echo canceller that uses a TCM29C16 codec interface Figure 6 31 Echo Canceler TMS29C16 Line Interface CODEC TMS320C25 6 6 2 High Speed Modem 6 48 In high speed modems a signal processor performs functions such as modu lation demodulation adaptive equalization and echo cancellation The TMS320C2x large memory space allows it to support multiple standards such as Bell 103 Bell 212A V 22 bis V 29 V 32 and V 33 as well as proprietary algorithms The modem shown in Figure 6 32 consists of the host interface controller DSP and analog front end Hardware Applications System Applications Figure 6 32 High Speed Modem DSP Controller Digital Bus VO Analog Host 570 42 Interface Controller DAA TMS320C2x TLC32040 AIC Phone Lines 6 6 3 Voice Coding Voice coding techniques such as full duplex 32 kbps adaptive differential pulse code modulation
233. D AT 202 SACH STORE HIGH WORD AT 203h RET RETURN TO MAIN PROGRAM The pipelining of the MAC and MACD instructions incurs a certain amount of overhead in execution In those cases where speed is more critical than pro gram memory it may be beneficial to use LTA or LTD and MPY instructions rather than MAC MACD Example 5 30 and Example 5 31 show an imple mentation of multiply accumulates using the MAC instruction Example 5 31 shows an implementation of multiply accumulates using the LTA MPY instruc tion pair Figure 5 11 and Figure 5 12 provide graphically the information necessary to determine the efficiency of use for each of the techniques 5 53 Advanced Arithmetic Operations 5 30 Multiply Accumulate Using the MAC Instruction TMS320C25 CLOCK TOTAL CLOCK PROGRAM TOTAL PROGRAM CYCLES CYCLES MEMORY MEMORY LARP ARI 1 LRLK AR1 300h 2 2 CNFP ZAC MPYK 0 RPTK N 1 OFFOOh 2 APAC 11 N 1 10 Example 5 31 Multiply Accumulate Using the LTA MPY Instruction Pair CLOCK TOTAL CLOCK PROGRAM TOTAL PROGRAM CYCLES CYCLES MEMORY MEMORY ZAC 11 1 C1 LTA D2 H MPY C2 4 2 2N lt LTA DN MPY CN 1 APAC 2 2N 1 2 2N 5 54 Software Applications Advanced Arithmetic Operations Figure 5 11 Execution Time vs Number of Multiply Accumulates TMS320C25 YyOO D
234. DRR Loaded From RSR 3 69 Serial Port When TXM 1 FSX is an output and the serial port register DXR is loaded a framing pulse is generated on the next rising edge of CLKX The XSR is loaded with the current contents of DXR while FSX is high and CLKX is low Transmission begins when FSX goes low while CLKX is high or is going high Figure 3 37 shows the timing for the byte mode FO 1 XINT is generated on the rising edge of CLKX after all 8 or 16 bits have been transmitted and DX is placed inthe high impedance state If DXR is reloaded before the next rising edge of CLKX after XINT FSX will again be generated as shown and XSR will be reloaded The receive operation is similar to the transmit operation The contents of RSR are loaded into DRR while CLKR is low just after reception of the last bit sent by the transmitting device see Figure 3 38 RINT is generated on the next rising edge of CLKR and DRR may be read at any time before the reception of the final bit of the next transmission When operating in the byte mode the eight MSBs of the DRR are the contents of the eight LSBs of the DRR prior to reception of the current byte as shown in Figure 3 39 for the TMS320C25 Figure 3 39 Byte Mode DRR Operation TMS320C25 Initial Condition X Y After 1st Receive Byte After 2nd Receive A Byte B 3 9 4 Continuous Operation Using Frame Sync Pulses TMS320C25 3 70 The TMS320
235. E PR DI PR DE Cycle Timings for a Repeat Execution Example SUBB DAT5 DP 8 Or SUBB If current auxiliary register contains 1029 Before Instruction After Instruction Data Data 1029 1029 C C In the above example C is originally zeroed presumably from the result of a previous subtract instruction that performed a borrow The effective operation performed was 6 6 0 1 generating another borrow and resetting carry again in the process The SUBB instruction can be usedin performing multiple precision arithmetic 4 176 Assembly Language Instructions Conditional Subtract SUBC Syntax Direct label SUBC dma Indirect label SUBC ind next ARP Operands 0 lt dma 127 x nex ARP lt 7 Execution PC 1 PC x 215 2 output If ALU output 2 0 Then ALU output x 2 1 ACC Else ACC x 2 gt ACC Affects OV Affects C Not affected by OVM no saturation is affected by SXM Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 0 0 0 14 1 1 Data Memory Address Indirect 1 0 0 0 1 1 1 See Section 4 1 Description The SUBC instruction performs conditional subtraction which may be used for division The 16 bit numerator is placed in the low accumulator and the high accumulator is zeroed The denominator is in data memory SUBC is executed 16 times for 16 bit division After completion of the last SUBC the quotient of the divisionis in the
236. E04h STO 7E04h ST1 0593h ST1 6190h 4 102 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Load T Register LT Direct label Indirect label LT ind next ARP 0 dma x 127 0 lt next ARP x 7 PC 1 PC dma T register 15 14 13 1 7 6 5 4 3 2 1 0 2 11 10 9 8 Direct 0 0 1 1 1 1 00 Data Memory Address Indirect 0 0 1 1 1 1 00 See Section 4 1 The T register is loaded with the contents of the specified data memory ad dress dma The LT instruction may be used to load the T register in prepara tion for multiplication See the LTA LTD LTP LTS MPY MPYK MPYA MPYS and MPYU instructions Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LT DAT24 DP 8 or LT If current auxiliary register contains 1048 Before Instruction After Instruction Data Data 1048 1048 4 103 LTA Load T Register Accumulate Previous Product Syntax Operands Execution Encoding Description Words Cycles 4 104 Direct label LTA Indirect label LTA ind next ARP 0 lt dma x 127 0 x next ARP x 7 PC 1 PC dma T register ACC shifted P register ACC Affects OV affected by OVM and PM Affects C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Diect 0 1 1 3 1 0 1 Data M
237. END OF LOOP TEST RE RETURN TO CALLING ROUTINE 5 37 Memory Management 5 4 3 Using On Chip RAM for Program Execution 5 38 To use on chip memory block BO for program execution you must first load this memory with executable code from external memories while it is config ured as data memory On chip executionis initiated by using the CNFP instruc tion to reconfigure block BO as program memory and performing a branch or call to an on chip RAM address By configuring block BO as program memory and executing from this internal memory you can achieve full speed execution in systems using slower external memory Example 5 21 illustrates how to write a program to be loaded into and executed from on chip memory One group of instructions the branch call instructions are impacted by the location of execution Normally by using labels the assembler properly deter mines the location to which a branch is taken Because the code is relocated prior to execution from on chip memory it is necessary to alter the address de termined by the assembler for branch instructions This alteration is necessary so that the branch address that is determined can be consistent with the ad dress space used during execution In Example 5 21 this is accomplished by use ofthe asect directive The asect directive simply indicates that the named section isto be assembled as if it were at the specified address The addresses defined within this named section
238. FFh 2 9200 Does Not P 4 7 F9FFh 03FFh Exist ages lt rn 0400h On Chip d Not Pages 8 11 Block Bi xist FBFFh Lin 05FFh FCOOh 0600h On Chip Does Not 12 4 FDFFh Mane CM Exist ages 12 15 rn FEO0h 0800h PARAL External Pages 16 511 FFFFh FFFFh If MP MC 1 If MP MC 0 Microprocessor Mode Microcomputer Mode d Memory Maps After a CONF 3 Instruction 3 21 Memory Organization 3 4 5 Memory Mapped Registers The six registers mapped into the data memory space are listed in Table 3 2 and are shown in the block diagram of Figure 3 2 The memory mapped registers may be accessed in the same manner as any other data memory location with the exception that block moves using the BLKD block move from data memory to data memory instruction cannot be performed from the memory mapped registers Table 3 3 Memory Mapped Registers Register Address Name Location Definition DRR 15 0 0 Serial port data receive register DXR 15 0 Serial port data transmit register 15 0 Timer register IMR 5 0 GREG 7 0 Interrupt mask register Global memory allocation register 1 2 PRD 15 0 3 Period register 4 5 3 4 6 Auxiliary Registers 3 22 The TMS320C2x provides a register file containing eight auxiliary registers ARO AR7 This section discusses each register s function and how an auxil iary register is selected and stored The auxiliary registers may be used for in
239. Fine Tune Es Echo Cancel 5320 25 5 Echo Canceler Transmitter Telephone Line v y o Control Receiver Figure G 11 shows a V 32 bis modem implementation using the TMS320C25 and a TLC320AC01 The upper TMS320C25 performs echo cancellation and transmit data functions while the lower TMS320C25 performs receive data and timing recovery functions The echo canceler simulates the telephone channel and generates an estimated echo of the transmit data signal The TLC320AC01 performs the following functions RS 232 Serial TMS320C25 C5x UF TLC320AC01 Upper TLC320ACO01 D A Path Converts the estimated echo as com puted by the upper TMS320C25 into an analog signal which is subtracted from the receive signal Upper TLC320ACO01 A D Path Converts the residual echo to a digital sig nal for purposes of monitoring the residu alecho andcontinuously training the echo canceler for optimum performance The converted signal is sent to the upper TMS320C25 G 16 Analog Interface Peripherals and Applications Modem Applications Lower TLC320AC01 D A Path Converts the upper TMS320C25 transmit output to an analog signal performs a smoothing filter function and drives the DAC Lower TLC320AC01 D A Path Converts the echo free receive signal to a digital signal which is sent to the lower TMS320C25 to be decoded a a Note Modem Implementation in Figure G 11 The example
240. INT BIO RS hold after CLKOUT1 high see Note 6 2021 1 T This parameter is not production tested NOTES 1 Q 1 4te C 3 A15 A0 PS DS IS RW and BR timings are all included in timings referenced as address 4 DelaysbetweenCLKOUT1 CLKOUT2 edges andSTRB edges trackeach other resultingin tw SL and ty SH being 2Q with no wait states 5 Read data access time is defined as ta A tsu A tw SL tsu D R 6 RS INT and BIO are asynchronous inputs and can occur at any time during a clock cycle However if the specified setup time is met the exact sequence shown in the timing diagram will occur INT BIO fall time must be less than 8 ns HOLD TIMING switching characteristics over recommended operating conditions see Note 1 PARAMETER TYP MAX UNIT td C1L AL HOLDA low after CLKOUT1 low ot 10 tdis AL A HOLDA low to address three state 0 18 tdis C1L A Address three state after CLKOUT1 low HOLD mode see Note 7 td HH AH HOLD high to HOLDA high ten A C1L Address driven before CLKOUT1 low HOLD mode see Note 7 timing requirements over recommended operating conditions see Note 1 td C2H H HOLD valid after CLKOUT2 high Q 24 E 38 Appendix Title Attribute Reference Running Title Attribute Reference NOTES 1 Q 1 4te C 7 A15 A0 PS DS IS STRB and R W timings are all included in timings referenced as address SERIAL PORT TIMING switching characteristics over recommended o
241. IY RO KKK Figure 9 Interrupt Timing Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION Nf Nf NU NOU NL zu NGI 7247 FETARE O 15 0 PC N 1 PC N 2 PC N 3 OR BRANCH ADDRESS th IN tsu IN ss NE Figure 10 BIO Timing a td XF OX EERE QC oe OQ omm Qmm PC N PC N 1 PC N 2 PC N 3 AD Figure 11 External Flag Timing E 46 Appendix Title Attribute Reference CLKOUT1 CLKOUT2 STRB HOLD 15 0 R W D15 DO HOLDA FETCH EXECUTE Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION NS LUE OMNI Pap e td C2H H see note OO 9 XK Q Q Q NX QA XQ 0 NO ldis C1L A 9 j tdis AL A AEN ld C1L AL N N 1 lt eae NOTE A HOLD is an asynchronous input that can occur at any time during a clock cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of CLKOUT2 cycle will occur Figure 12 HOLD Timing Part A E 47 Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION gt ten A C1L STRB _ NK lt tg C2H H see note A HOLD XD R W 8507 D15 DO 3 td HH AH
242. Instructions Syntax Operands Execution Encoding Description Words Cycles Example Subtract from High Accumulator SUBH Direct label SUBH dma Indirect label SUBH ind next ARP 0 lt dma x 127 0 lt next ARP x 7 1 PC ACC dma x 216 2 Affects OV affected Affects C 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Direct 9 1 E Data Memory Address Indirect o See Section 4 1 A o A The contents of the addressed data memory location are subtracted from the upper 16 bits of the accumulator The 16 low order bits of the accumulator are unaffected The result is stored in the accumulator The carry bit C on the TMS320C2x is reset if the result of the subtraction generates a borrow other wise C is unaffected The SUBH instruction can be used for performing 32 bit arithmetic Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SUBH DAT33 6 or SUBH If current auxiliary register contains 801 Before Instruction After Instruction Data Data 801 801 ACC 0A0013h acc 1 60013h C C 4 179 SUBK Subtract from Accumulator Short Immediate Syntax Operands Execution Encoding Description Words Cycles Example 4 180 label SUBK constant 0 constant lt 255 PC 1 gt PC ACC 8 bit positive consta
243. Instructions The TMS320C 2x instruction set supports numeric intensive signal processing operations as well as general purpose applications such as multiprocessing and high speed control TMS320C1x source code is upward compatible with TMS320C2x source code The TMS320C26 is similar to the TMS320C25 except for its internal memory configuration This is discussed in Section 3 4 and in Appendix B This chapter describes the assembly language instructions for the TMS320C2x microprocessor Topics include Topic Page 41 Memory Addressing Modes 4 2 4527 4 11 4 3 Individual Instruction Descriptions 4 18 4 1 Memory Addressing Modes 4 1 4 1 1 4 2 Memory Addressing Modes The TMS320C2x instruction set provides three memory addressing modes 1 Direct addressing mode Indirect addressing mode Immediate addressing mode Both direct and indirect addressing can be used to access data memory Direct addressing concatenates seven bits of the instruction word with the nine bits of the data memory page pointer to form the 16 bit data memory address Indi rect addressing accesses data memory through the auxiliary registers In im mediate addressing the data is based on a portion of the instruction word s The following sections describe each addressing mode and give the opcode formats and some examples
244. It is capable of an instruction cycle of 120 ns It is architecturally identical to the 40 MHz ver sion of the TMS320C25 andis pin for pin and object code compatible with the TMS320C25 The TMS320C25 50 is a high speed version of the TMS320C25 It is capable of an instruction cycle time of 80 ns Itis architecturally identical to the 40 MHz version of the TMS320C25 andis pin for pin and object code compatible with the TMS320C25 1 4 Introduction General Description The TMS320E25 is identical to the TMS320C25 except that the on chip 4K word program ROM is replaced with a 4K word on chip program EPROM On chip EPROM allows realtime code development and modification for im mediate evaluation of system performance The 5320 26 is pin for pin and object code compatible except for RAM configuration instructions with the TMS320C25 It is capable of an instruction cycle time of 100 ns The enhancement over the TMS320C25 consists of a larger configurable on chip RAM divided into 4 blocks for a total 1568 word program data space The TMS320C26 is similar to the TMS320C25 except for its internal memory configuration This is discussed in Section 2 4 and in Ap pendix B The TMS320C28 is object code compatible with the TMS320C25 Itis capable of an instruction cycle time of 100 ns The TMS320C28 contains an expanded 8K words of on chip program ROM and an added power down mode which conserves power while saving the contents of on chip S
245. LC04 14 Low pass Butterworth filter 50 TLC10 2 l fil 2 10 20 General purpose dual filter CLK 100 Speech Synthesis Development Tools Software System EVM Code development tool SEB System emulator board Speech SEB60Cxx System emulator boards for speech SAB Speech audition board memories SD85000 PC based speech analysis system For further information on these speech synthesis products please call Linear Applications at 214 997 3772 Servo Control Disk Drive Applications G 4 Servo Control Disk Drive Applications Figure G 8 Several years ago most servo control systems used only analog circuitry However the growth of digital signal processing has made digital control theory a reality Figure G 8 shows a block diagram of a generic digital control system using a DSP along with an ADC and DAC Generic Servo Control Loop TMS320 Based Digital Controller y n Sensor In a DSP based control system the control algorithm is implemented via soft ware No component aging or temperature drift is associated with digital con trol systems Additionally sophisticated algorithms can be implemented and easily modified to upgrade system performance System Design Considerations TMS320 DSPs have facilitated the de velopment of high speed digital servo control for disk drive and industrial con trol applications Disk drives have increased storage capacity from 5 mega bytes t
246. LE Example Instructions Encoding Description Words Cycles 4 20 An example of the instruction operation sequence is provided describing the processing that takes place when the instruction is executed Conditional ef fects of status register specified modes are also given Those bits in the TMS320C2x status registers affected by the instruction are also listed Direct 0 0 0 0 fol Data Memory Address Indirect o 0 0 0 See Section 4 1 Immediate 1 0 0 13 Bit Constant Opcode examples are shown of both direct and indirect addressing or of the use of an immediate operand Instruction execution and its effect on the rest of the processor or memory con tents are described Any constraints on the operands imposed by the proces sor or the assembler are discussed The description parallels and supple ments the information given by the execution block 1 The digit specifies the number of memory words required to store the instruc tion and its extension words Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution The table shows the number of cycles required for a given TMS320C2x instruction to execute in a given memory configuration when executed as a single instruction or in the repeat mode The column headings in the tables in dicate the program source location Pl PE or PR and data destination or source DI or DE defined as follows Assem
247. Logic Unit The TMS320C2x performs 2s complement arithmetic using the 32 bit ALU and accumulator The ALU is a general purpose arithme tic unit that operates using 16 bit words taken from data RAM or derived from immediate instructions or using the 32 bit result of the multiplier s product reg ister In addition to the usual arithmetic instructions the ALU can perform Bool ean operations providing the bit manipulation ability required of a high speed controller The accumulator stores the output from the ALU and is the second input to the ALU The accumulator is 32 bits in length and is divided into a high order word bits 31 through 16 and a low order word bits 15 through 0 Instructions are provided for storing the high and low order accumulator words in memory Multiplier The multiplier performs a 16 x 16 bit 2s complement multiplication with a 32 bit result in a single instruction cycle The multiplier consists of three elements the T register P register and multiplier array The 16 bit T register temporarily stores the multiplicand the P register stores the 32 bit product Multiplier values come from data memory from program memory when using the MAC MACD instructions or immediately from the MPYK multiply immedi ate instruction word The fast on chip multiplier allows the device to perform efficiently the fundamental DSP operations such as convolution correlation and filtering 3 3 Architectural Overview 3 4 The TM
248. M Programmer Adapter Socket F 2 F 1 1 Supplying External Power F 2 F 2 Programming and Verification F 4 Men ER SOL eU OE LEER C Ee dC ES C le F 7 2 22 FAST Programming ios to eub e t e o e cu e bees F 7 2 3 SNAP Pulse Programming F 8 2 4 Program Verity oe us ceu sr RE us F 8 L2 Program MUO rere en Ree Rex Ree x ROO GR ACER B F 11 F26 Read tate M uice tai Mud Ut ut rU F 11 F27 Output Disable re eo RO RUPEE ee i F 11 EPROM Protection and Verification F 12 F 3 1 EPROM Protection F 12 F 3 2 How the RBIT F 14 F 3 3 Protect Verify F 15 Analog Interface Peripherals and G 1 G 1 Multimedia Applications G 2 G 1 1 System Design Considerations G 2 G 1 2 Multimedia Related Devices G 4 G 2 Telecommunications Applications G 5 G 3 Dedicat
249. MBER TMDX3268828 TMDX3268821T E 31 Running Title Attribute Reference absolute maximum ratings over specified temperature range unless otherwise noted t Supply voltage range Vegt x sere cerex he E Eee CA E Re CR 0 3 7 input voltage Tange 0 3 Vto7 V Output voltage range 0 3Vto7V Continuous power dissipation 1 0 W Storage temperature range 55 C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t All voltages are with respect to Vss y This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields These circuits have been qualified to protect this device against electrostatic discharges ESD 4 A of up to 2 kV according to MIL STD 883C Method 3015 however it is advised that precautions be taken to avoid application of any voltage higher than maximum rated voltages to th
250. MOS or fast advanced Schottky TTL may cause line reflections ringing above input thresholds on input lines to the XDS Series termination resistors 22 to 68 ohms can help eliminate this prob lem In some cases where significant additional signal length is added to XDS outputs the series resistors on the XDS may not be sufficient to control reflec tions In this case additional corrective actions may be necessary Clock Source The XDS does not support the use ofa crystal in the target sys tem The emulator s clock source can be selected from three sources A clock with TTL levels driven up the target cable on pin F11 PGA or pin 35 PLCC socketed changeable crystal on the emulator board Y1 or A socketed changeable canned TTL oscillator on the EMU 09 Hardware Applications 6 2 Interfacing Memories Interfacing Memories The following buses port and control signals provide system interface to the TMS320C2x processor 16 bit address bus A15 0 16 bit data bus D15 DO Serial port PS DS IS program data I O space select R W read write and STRB strobe READY and MSC microstate complete HOLD and HOLDA hold acknowledge INT 2 0 and IACK interrupt acknowledge BIO branch control and XF external flag m m m m m m m m m SYNC synchronization and BR bus request TMS320C2x can be interfaced with PROMs EPROMs and static RAMs The speed
251. MS320C25 s CLKOUT2 RS e T Connections to other devices in the system that require two wait states Inputs not used by other devices should be pulled up Connections to other devices in the system that require one wait state Inputs not used by other devices should be pulled up Connections to other devices in the system that require zero wait states Inputs not used by other devices should be pulled up 6 21 Interfacing Memories Figure 6 11 Wait State Generator Timing 6 2 3 6 22 N N N NY NY UN NAA Nef AN 12 25 6 One Wait N Lp State 19 4 33 READY uod FD PS DS IS LY ba 0 Two Wait MEMSEL BS Wee States READY Interfacing EPROMs EPROMs can be a valuable tool for debugging 5320 2 algorithms during the prototyping stages of a design and may even be desirable for production Two different EPROM interfaces to the TMS320C2x are discussed a direct in terface of an EPROM that requires no wait states and EPROM interfaces that require one and two wait states A direct interface similar to that used for PROMs may be implemented when EPROM access time meets the 5320 2 timing specifications A Texas Instruments TMS27C292 35 2K x 8 bit EPROM can interface directly to the TMS320C25 with wait states The TMS27C 292 35 is a CMOS EPROM with access times of 35 ns from valid address and 25 ns from chip selec
252. MS320C28 TMS320C26 External ROM External ROM External FBFF 00 External FBFF 00 New Block FDFF FEO0 FEFF FF00 B3 New Block FFFF FFFF 3 18 Architecture Figure 3 8 TMS320C2x Memory Maps Program 0 0000h Interrupts and Reserved 31 001Fh External 32 0020h External 65 535 OFFFFh If MP MC 1 Microprocessor Mode Program 0 0000h Interrupts and Reserved 31 001Fh External 32 0020h External 65 279 OFEFFh 65 280 OFFOOh On Chip Block BO 65 535 OFFFFh If MP MC 1 Microprocessor Mode Memory Maps After a CNFD Instruction Program 0 0000h Interrupts and Reserved On Chip 31 001Fh ROM EPROM 32 0020h On Chip 4015 OFAFh CEROMIBOM 4016 OFBOh Reserved 4095 OFFFh 4096 1000h External 65 535 OFFFFh If MP MC 0 Microcomputer Mode on TMS320C25 95 96 127 128 511 512 767 768 1023 1024 0000h 0005 0006 005F 0060 007Fh 0080h O1FFh 0200h 02FFh 0300h O3FFh 0400h 65 535 OFFFFh b Memory Maps After a CNFP Instruction Program 0 0000h Interrupts and Reserved On Chip 81 001Fh ROM EPROM 32 0020h On Chip 4015 OFAFh ROM EPROM 4016 OFBOh Reserved 4095 OFFFh 4096 1000h External 65 279 OFEFFh 65 280 OFFOOh Block BO 65 535 OFFFFh If MP MC 0 Microcomputer Mode on TMS320C25 95 96 127 128 511 512 767 768 1
253. MSB AND MODIFI S CARE OF R I DUNDANT SIGN BIT IS INITIALIZED WITH EC ES AR5 MC MA MB NORMALIZED THIS SUBROUTINE PERFORMS FLOAT THE INPUTS AND OUTPUTS ARE OF 2 EC SINCE THE MANTISSAS MA AND LEFT SHIE ADJUSTED APPROPRIATELY FOR EXAMPL WHERE A 0 1 2 2 1 0 01 2 6 2 B 0 1 2 5 MULT EA ADD EB SACL EC LT A MPY B PAC H SFL LARP AR5 LAR AR5 EC NORM SACH MC SAR AR5 EC RE RETURN TO MAIN PROGRAM Floating point implementation programs often require denormalization as well as normalization to return results in a 16 bit format Example 5 37 illustrates the denormalizing of numbers that were normalized with the NORM instruc tion This program assumes that the mantissa is in the accumulator and that the exponent is in an auxiliary register which is the format of the NORM instruction after execution Example 5 37 Using LACT for Denormalization THIS ROUTINE DENORMALIZES NUMBERS NORMALIZED BY THE NORM INSTRUCTION NORM THE DENORMALIZED NUMBER WILL BE IN THE ACCUMULATOR DENORM LARP 1 USE AR1 TO POINT AT BLOCK BO LRLK AR1 200h SAR STORE EXPONENT AT 200h SACH STORE MANTISSA AT 201h LAC
254. Memory PROM 54256 or DRAM SRAM Optional Display Display Interface 534070 Color Palette VRAM 6 50 Hardware Applications System Applications 6 6 5 High Speed Control High speed control applications such as robotics use the TMS320C2x gener al purpose features for bit manipulation logical operations timing synchro nization and fast data transfers 10 million 16 bit words per second In addi tion to the numeric intensive control functions typical of robotic applications the TMS320C2x provides a host interface whereby a robot can communicate to a central host processor see Figure 6 35 The TMS320C2x is also used in the closed loop systems of disk drives for signal conditioning filtering high speed computing and multichannel multiplexing Figure 6 35 Robot Axis Controller Subsystem Robot Arm Position Shaft Encoder System 5320 2 Interface Pressure Controller CPU A D D A Wait State i Memory Address To Peripherals Axis or SRAM Decode n Optional 6 6 6 Instrumentation and Numeric Processing Instrumentation such as spectrum analyzers requires a large data memory space anda processor such as the TMS320C2x that is capable of performing long length FFTs and generating high precision functions with minimal exter nal hardware Figure 6 36 shows an example of an instrumentation system Numeric processing applications
255. Modify AR ARP and ARP as specified Affected by TC bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address if the carry bit C is high Otherwise control passes to the next instruction Note that no AR or ARP mod ification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address Note that the carry bit C is affected by all add subtract and accumulate instructions as well as the ABS LST1 NEG RC SC rotate and shift instruc tions The carry bit is not affected by execution of BC BNC or nonarithmetic instructions 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 242p Cycle Timings for a Repeat Execution not repeatable BC PRG512 If the carry bit 1 512 is loaded into the program counter Otherwise the PC is incremented by 2 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch if Accumulator Greater Than or Equal to Zero BGEZ label BGEZ pma ind next AHP 0 lt pma lt 65536 0 x next ARP x 7 If ACC 2 0 Then pma PC Else PC 2 gt PC Modi
256. None PC 15 PC shifted P register gt ACC Affects OV affected by PM and OVM Affects C Not affected by SXM The contents of the P register are shifted as defined by the PM status bits and added to the contents of the accumulator The result is left in the accumulator APAC is not affected by the SXM bit of the status register the P register is al ways sign extended The APAC instruction is a subset of the LTA LTD MAC MACD MPYA and SQRA instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution APAC PM 0 Before Instruction After Instruction 4 41 Branch Unconditionally Syntax Operands Execution Encoding Description Words Cycles Example 4 42 label B pma ind next ARP 0 lt pma lt 65535 0x next ARP x 7 pma PC Modify AR ARP and ARP as specified 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified and control passes to the designated program memory address pma Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 242p Destination on chip ROM
257. Note that SST may be used to store status register STO anywhere in data memory while SST in the direct addressing mode is forced to page O Words Cycles 4 168 Assembly Language Instructions Store Status Register STO SST Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example SST DAT96 DP don t care or SST If current auxiliary register contains 96 Before Instruction After Instruction Status Status Register 0A408h Register 0A408h STO STO Data Data Memory OAh Memory 0A408h 96 96 4 169 SST1 Store Status Register ST1 Syntax Direct label SST1 dma Indirect abel SST1 ind next ARP Operands 0 lt dma 3127 0 lt next ARP lt 7 Execution 1 PC status register ST1 dma Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 1 1 0 0 1 Data Memory Address Indirect 0 1 1 1 1 00 1 See Section 4 1 Description Status register ST1 is stored in data memory In the direct addressing mode status register ST1 is always stored in page 0 regardless of the value of the DP register The processor automatically forces the page to be 0 and the spe cific location within that page is defined in the instruction Note that the DP reg ister is not physically modified This allows the storage of the DP in the data memory on interrupts etc in the direct addressing mode without having to change th
258. O ACC W3 W2 SACL W2 SAVE w2 SACH W3 SAVE W3 DONE RET 5 67 Application Oriented Operations 5 7 Application Oriented Operations 5 7 1 5 68 Companding The TMS320C2x efficiently implements many common digital signal proces sing algorithms The architecture discussed in Chapter 3 supports features that solve numerically intensive problems usually characterized by multiply accumulates Some device specific features that aid in the implementation of specific algorithms include companding filtering Fast Fourier Transforms FFT and PID control These applications require I O performed either in par allel or serial Hardware requirements for I O are discussed Chapters and 6 In the area of telecommunications one of the primary concerns is the I O band width in the communications channel One way to minimize this bandwidth is by companding COMpress exPAND Companding is defined by two interna tional standards A law and u law both based on the compression of the equivalent of 13 bits of dynamic range into an 8 bit code The standard employed in the United States and Japan is u law the European standard is A law Detailed descriptions and code examples of both types are presented in an application report on companding routines included in the book Digital Signal Processing Applications with the TMS320 Family literature number SPRAO0124 The technique of companding allows the digital sample i
259. O space the number of cycles required to execute a particular instruction may further vary depending on whether the next instruction fetch is from internal or external program memory Instruction execution and operation of the pipeline are discussed in subsection 3 6 2 and in the succeeding subsections Architecture External Memory I O Interface 3 7 2 Internal Clock Timing Relationships The crystal or external clock source frequency is divided to produce an internal four phase clock The four phases are defined by CLKOUT1 and CLKOUT2 as shown in Figure 3 27 Figure 3 27 Four Phase Clock Phase Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT1 T cm WE IEEE CLKOUT2 EXON dh WENN SE cs Q2 Q4 3 7 3 General Purpose I O Pins BIO and The TMS320C2x has two general purpose pins that are software controlled The BIO pin is a branch control input pin and the XF pin is an external flag out put pin The BIO pin is useful for monitoring peripheral device status It is especially useful as an alternative to using an interrupt when it is necessary not to disturb time critical loops When the BIO input pin is active low execution of the BIOZ instruction causes a branch to occur 3 57 External Memory and I O Interface In Figure 3 28 BIO is sampled at the end of 04 The timing diagram shown is for a sequence of single cycle single word instructions without branches lo
260. ON CHIP BLOCK BO 64511 FBFFh 64512 EXTERNAL 65023 FDFFh 65024 FEO0h EXTERNAL 65535 FFFFh 2048 0800h EXTERNAL 65535 FFFFh 2048 0800h EXTERNAL 65535 FFFFh Running Title Attribute Reference DATA 0 0000 ON CHIP MMRs 5 0005h 6 0006h RESERVED 95 005Fh 96 0060h ECAP BLOCK B2 127 007Fh 128 0080h RESERVED 511 01FFh 512 0200h NoT EXIST 1023 03FFh 1024 0400h SCHIP BLOCK B1 1535 05FFh 1536 0600h ON CHIP BLOCK B3 2047 07FFh 0 15 0 1 3 4 7 8 11 12 15 16 511 WWW DATA 0100009 ON CHIP MMRs 5 0005h 6 0006h RESERVED 95 005Fh 96 0060h BLOCK 2 127 007Fh 128 0080h RESERVED 511 01FFh 512 0200h EXIST 1023 03FFh 1024 0400h SILCHIP BLOCK B1 1535 05FFh 1536 0600h ON CHIP BLOCK B3 2047 07FFh 0 15 0 1 3 4 7 8 11 12 15 16 511 v w w w Nn Running Title Attribute Reference Figure 1B Memory Maps E 16 Appendix Title Attribute Reference Running Title Attribute Reference MEMORY MAPS AFTER CONF 2 1 MP MC 1 PROGRAM DATA Vo 0 0000h 0 0000h 0 INTERRUPTS ON CHIP EXTERNAL AND RESERVED t es 31 001Fh _ ETERNAN 8 00068 i 32 0020h 95 005Fh RE 96 0060h O
261. OPERATIONS NO INSTRUCTION BIT CODE WORDS 15 14 13 12 11 10 9 MNEMONIC DESCRITPION Block move from data memory to data memory Block move from program memory to data memory Data move in data memory Format serial port registers Input data from port Output data to port Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag Set serial port frame synchronization mode Set serial port transmit mode Set external flag Table read Table write RJ mA mA mA mA ed SAC pu eil Rd OS C OC 000000000 ua ats T These instructions are not included in the SMJ32010 instruction set E 28 Appendix Title Attribute Reference Running Title Attribute Reference Table 2 Instruction Set Summary concluded CONTROL INSTRUCTIONS NO INSTRUCTION BIT CODE WORDS 15 8 7 6 MNEMONIC DESCRIPTION Test bit Test bit specified by T register Configure RAM blocks as Data or program Disable interrupt Enable interrupt Idle until interrupt Load status register STO Load status register ST1 No operation Pop top of stack to low accumulator Pop top of stack to data memory Push data memory value onto stack Push low accumulator onto stack Reset carry bit Reset hold mode Reset overflow mode Repeat instruction as specified by data memory value Repeat instruction
262. OV function is useful for implementing algorithms that use the 2 1 delay operation such as convolutions and digital filtering where data is being passed through a time window The data move function can be used anywhere within blocks BO B1 and B2 and block B3 with the TMS320C26 It is continuous across the boundary of blocks BO and B1 but cannot be used with off chip data memory The MACD multiply and accumulate with data move and the LTD load T register accumulate previous product and move data instructions use the data move function The TBLR TBLW table read write instructions allow words to be transferred between program and data spaces TBLR is used to read words from on chip ROM or off chip program ROM RAM into the data RAM TBLW is used to write words from on chip data RAM to off chip program RAM 3 27 Central Arithmetic Logic Unit CALU 3 5 Central Arithmetic Logic Unit CALU 3 28 The TMS320C2x central arithmetic logic unit CALU contains a 16 bit scaling shifter a 16 x 16 bit parallel multiplier a 32 bit arithmetic logic unit ALU a 32 bit accumulator ACC and additional shifters at the outputs of both the ac cumulator and the multiplier This section describes the CALU components and their functions Figure 3 13 is a block diagram showing the components of the CALU In the figure note that SFL and SFR indicate shifts to the left or right respectively The following steps occur in the implementation of
263. P 4 or AND If current auxiliary register contains 528 Before Instruction After Instruction Data Data Memory OFFh Memory OFFh 528 528 ACC 12345678h ACC 00000078h 4 39 ANDK AND Immediate With Accumulator With Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 40 7 46 5 24 3 2 A 0 Indirect 16 Bit constant label ANDK constant shift 16 bit constant 0 lt shift lt 15 defaults to 0 PC 2 5 PC 30 0 AND constant x 2 shift gt 30 0 0 ACC 31 and all other bit positions unoccupied by shifted constant Not affected by SXM 15 14 13 12 11 10 9 8 The 16 bit immediate constant is left shifted as specified and ANDed with the accumulator The result is left in the accumulator Low order bits below and high order bits above the shifted value are treated as zeros clearing the corre sponding bits in the accumulator Note that the accumulator s most significant bit is always zeroed regardless of the shift code value 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable ANDK OFFFFh 12 Before Instruction After Instruction ACC 12345678h ACC 02345000h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Add P Register to Accumulator APAC label
264. P system data conversion re quirements Combo codecs are single chip pulse code modulated encoders and decoders PCM codecs designed to perform the encoding A D conver sion and decoding D A conversion as well as the antialiasing and smooth ing filtering functions Since combo codecs perform these functions in a single 300 mil DIP package at low cost they are extremely economical for providing system data conversion functions Combo codecs interface directly to the TMS320C2x by means of the serial port and provide a companded PCM coded digital representation of analog input samples This PCM code is easily translated into linear form by the 5320 2 for use in processing The design discussed here and shown in Figure 6 21 uses a Texas Instruments 29 16 codec interfaced through using the serial port of the TMS320C25 The TMS320C2x serial port provides direct synchronous communication with serial devices The interface signals are compatible with codecs and other se rial components so that minimal external hardware is required Externally the serial port interface is implemented via the following pins on the TMS320C25 DX transmitted serial data CLKX transmit clock FSX transmit framing synchronization signal DR received serial data CLKR receive clock FSR receive framing synchronization signal O C L 6 37 Interfacing Peripherals Data on DX DR are clocked by CLKX and CLKR respective
265. PROM Signiture If found mode 3 download is entered high Stop bit has been high since reset low start bit this bit is timed for baud rate DATA 7 high signals end of start bit for baud rate detect DATA 6 rest of data bits for baud rate detect are don t care DATA 5 don t care DATA 4 don t care DATA 3 don t care DATA 2 don t care DATA 1 don t care DATA 0 don t care high Stop bit 1 end of baud rate detect transfer high stop bit 2 low start bit begin STATUS word transfer UJ UU UJ UU UJ UU UJ UJ UJ UJ UO UJ UJ UJ 000oooooooooooQoe DATA 7 This process is repeated until all the control words program words and checksum have been transferred Finally one final word SYNCH is used to hold the C26 momentarily before execution of the users program t BIO high Stop bit signals end of CHECKSUM HIGH transfer XF PAO C26 indicates CHECKSUM status HIGH pass Low fail BIO low C26 branches to execute program data input but not used BRANCH PROG program is now running 5 12 Software Applications Processor Initialization Figure 5 6 Sequence for RS232 Transfer 8 Data Bits Only BAUD DETECT WORD Herne 2x Length Transfers ge SYNCHRO DUMMY Configuration Word Definitions BAUD DETECT 1 RS232 transfer The first word transmitted by the host detects the baud rate by sampling the low period of the start bit In this case the stop bits have been previously hold ing th
266. PUT WILL BE IN MEMORY LOCATION Y WHEN RETURNED COEFFP set OFFOOh BO PROGRA EMORY ADDRESS COEFFD set 0200 BO DATA MEMORY ADDRESS ONE 7Ah CONSTANT ONE DP 6 BETA Set 7Bh ADAPTATION CONSTANT DP 6 ERR set 7 SIGNAL ERROR DP 6 ERRF set 7Dh ERROR FUNCTION DP 6 Y 7Eh FILTER OUTPUT DP 6 X Set 7Fh NEWES DATA SAMPLE DP 6 FRSTAP set 0380 NEXT NEWEST DATA SAMPLE LASTAP set O3FFh OLDES DATA SAMPLE FINITE IMPULSE RESPONSE FIR FILTER ADPFIR CNFP CONFIGURE AS PROGRAM PYK 0 CLEAR THE P REGISTER LAC ONE 14 LOAD OUTPUT ROUNDING BIT LARP AR3 LRLK AR3 LASTAP s POIN O THE OLDEST SAMPLE FIR RPTK 127 ACD COEFFP 128 FIR FILTER CNFD CONFIGURE 0 5 DATA APAC SACH Y 1 STORE THE FILTER OUTPUT NEG ADD X 5 ADD THE NEWE INPU SACH ERR 1 ERR N X N Y N LMS ADAPTATION OF FILTER COEFFICIENTS LT ERR MPY BETA 128 TAP FIR FILTER PAC ERRF N BETA ERR N ADD ONE 14 ROUND THE RESUL SACH ERRF 1 LARP AR3 LARK ARLTZT 128 COEFFICIENTS TO UPDATE AR2 COEFFD i POI O THE COEFFICIENTS AR3 LASTAP POI O THE DATA SAMPLES DMOV X INCLUDE NEWEST SAMPLE iT ERRFE PY AR2 P 2 BETA ERR N X N ADAPT ZALH AR3 LOAD ACCH WITH AK N ADD ONE 15 LOAD ROUNDING BIT APAC AK N 1 AK N P MPY AR2 P 2 BETA ERR N X N K SACH 0 AR1 STORE AK N 1 ADAPT AR2
267. PY B1 LTD D MPY BO SACH 1 OUT YN PA1 5 70 INPUT NEW VALUE XN LOAD ACCUMULATOR WITH XN y n 1 b1 d n 2 b2 YN IS THE OUTPUT OF THE FILTER Software Applications Application Oriented Operations FIR filters also benefit from the faster instruction cycle time An FIR filter re quires many more multiply accumulates than does the IIR filter with equivalent sharpness at the cutoff frequencies and distortion and attenuation in the pass bands and stopbands The TMS320C2x can help solve this problem by mak ing longer filters feasible to implement This is accomplished by allowing the coefficients to be fetched from program memory at the same time as asample is being fetched from data memory The simple implementation of this process uses the MACD instruction with the RPT RPTK instruction RPTK 255 MACD COEFFP The coefficients on the TMS320C25 may be stored anywhere in program memory reconfigurable on chip RAM on chip ROM or external memories When the coefficients are stored in on chip ROM or externally the entire on chip data RAM may be used to store the sample sequence Ultimately this al lows filters of up to 512 taps to be implemented on the TMS320C25 The filter executes at full speed or 100 ns per tap as long as the memory supports full speed execution 5 7 3 Adaptive Filtering With FIR IIR filtering the filter coefficients may be
268. RAM BO B1 and B2 Key Features 1 2 Key Features Key features of the TMS320C2x devices are listed below Those that pertain to a particular device are followed by the device name within parentheses d Lo B B E O O LI DI UUO O O Instruction cycle timing 80 ns 5320 25 50 100 ns TMS320C25 TMS320E25 TMS320C26 and 5320 28 120 ns TMS320C25 33 544 word programmable on chip data RAM 1568 word configurable program data RAM TMS320C26 only 4K word on chip program ROM TMS320C25 TMS302C25 33 and TMS320C25 50 8K word on chip program ROM TMS320C28 only Secure 4K word on chip program EPROM TMS320E25 128K word total data program memory space 32 bit ALU accumulator 16 x16 bit parallel multiplier with a 32 bit product Single cycle multiply accumulate instructions Repeat instructions for efficient use of program space and enhanced execution Block moves for data program management On chip timer for control operations Up to eight auxiliary registers with dedicated arithmetic unit Up to eight level hardware stack Sixteen input and sixteen output channels 16 bit parallel shifter Wait states for communication to slower off chip memories peripherals Serial port for direct codec interface Synchronization input for synchronous multiprocessor configurations Introduction COCO O O Key Features Global data memory interface TMS320C1x source code upward compatibilit
269. ROM Codes ROM Codes A TMS320 ROM code may be submitted in one of the following formats the preferred media is 5 1 4 in floppies 5 1 4 in Floppy Tl tagged or COFF format from cross assembler EPROM TMS320 TMS320E14 TMS320E15 TMS320E17 TMS320E25 EPROM others TMS27C64 PROM 285166 TBP28S86 Modem BBS Tl tagged or COFF format from cross assembler When code is submitted to Texas Instruments for masking the code is refor matted to accommodate the TI mask generation system System level verifi cation by the customer is therefore necessary Although the code has been re formatted it is important that the changes remain transparent to the user and do not affect the execution of the algorithm The formatting changes involve the removal of address relocation information the code address begins at the base address of the ROM in the TMS320 device and progresses without gaps to the last address of the ROM on the TMS320 device and the addition of data in the reserved locations of the ROM for device ROM test Note that because these changes have been made a checksum comparison is not a valid means of verification With each masked device order the customer must sign a disclaimer stating Theunits to be shipped againstthis order were assembled for expediency purposes on a prototype that is non production qualified manufacturing line the reliability of which is not fully characterized Therefore the antici pated
270. ROMs Two different approaches for interfacing PROMs to the 5320 2 can be taken depending on whether or not any of the memories in the system require wait states When no wait states are required for any of the memories READY can be tied high and the interface to the PROMs be comes a direct connection In this first approach address decoding is not re quired because the system contains only a small amount of one type of memory When some of the system memories require wait states address de coding must be performed to distinguish between two or more memory types with different access times In the second approach a valid READY signal that Hardware Applications Interfacing Memories meets the TMS320C2x timing requirements must be provided An efficient method of accomplishing this is to use one section of circuitry to generate the address decode and a second independent section to generate the READY signal These two approaches are discussed in this section For more detailed information see Hardware Interfacing to the TMS320C25 literature number SPRA0144 An example of a no wait state memory system is the direct PROM interface design shown in Figure 6 5 In this design the TMS320C25 is interfaced with the Texas Instruments TBP38L1 65 35 a low power 2K x 8 bit PROM The in terface timing for the design of Figure 6 5 is shown in Figure 6 6 The same techniques can be used with all TMS320C2x devices The TMS320C25 expec
271. RSHIB 127 007Fh EXTERNAL 128 0080h RESERVED PAGE 1 3 511 01FFh 512 0200h DOES NOT 63999 F9FFh EXIST gt spices 1024 02000 BLOCK 8 11 64512 FCO0h 1535 05FFh ON CHIP 1536 0600h BLOCK B1 CHE 65023 FDFFh 65024 00 2048 95001 EXTERNAL EXTERNAL 16 511 65535 FFFFh 65535 FFFFh 2 0 PROGRAM DATA 0 0000h INTERRUPTS 0 0000 ON CHIP j AND RESERVED MMRs ENTERS BOOTLOAD ROM 5 0005h 15 255 00FFh 6 0006h RESERVED 256 0100h RESERVED 95 005Fh PAGE 0 4095 OFFFh 96 0060h 4096 1000h ON CHIP BLOCK B2 127 007Fh EXTERNAL 128 0080h RESERVED 511 01FFh 512 0200h OES NOT EXIST 63999 F9FFh 64000 FAO0h On cup 0400 NOT BLOCK BO EAST 64511 FBFFh 1535 05FFh 64512 ON CHIP 1536 0600h ON CHIP BLOCK B1 BLOCK B3 65023 FDFFh 2047 07FFh 65024 00 2048 0800h EXTERNAL EXTERNAL 65535 FFFFh 65535 FFFFh PAGE 1 3 PAGE 4 7 PAGE 8 11 PAGE 12 15 PAGE 16 511 WWW oo 17 Running Title Attribute Reference Figure 1C Memory Maps E 18 Appendix Title Attribute Reference MEMORY MAPS AFTER CONF 3 1 1 0 0000h 31 001Fh 32 0020h 63999 F9FFh 64000 64511 FBFFh 64512 FC00h 65023 FDFFh 65024 00 65535 FFFFh 2
272. RTC test control flag is reset to logic zero 4 147 RTXM Reset Serial Port Transmit Mode Syntax Operands Execution Encoding Description Words Cycles Example 4 148 label RTXM None 1 PC 0 transmit mode status bit Affects TXM mode bit 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 The RTXM instruction resets the TXM status bit which configures the serial port transmit section in a mode where it is controlled by an FSX external fram ing pulse The transmit operation is started when an external FSX pulse is ap plied TXM may also be loaded by the LST1 and STXM instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RTXM IXM is reset configuring FSX as an input Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Rest External Flag RXF label RXF None 1 0 external flag and status bit Affects XF 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 The pin and status bit in status register ST1 are reset to logic zero may also be loaded by the LST1 and SXF instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution RXF XF pin and status bit are reset
273. S X1 ACCL S XX XXXX XXXX XXXX X XOR Y1 5 SACH SIGN 1 SAVE THE PRODUCT SIGN 0 1 TAKE THE ABSOLUTE VALUE OF BOTH X AND Y ABSX ZALH X1 ACC X1 00 ADDS X0 ACC X0 ABS SACH X1 SAVE X1 SACL xO SAVE X0 l ABSY ZALH Y1 ACC Y1 00 ADDS YO ACC Y1 YO ABS SACH Yl SAVE Y1 SACL YO SAVE YO MULTIPLY X AND Y TO PRODUCE W MULT LT T x0 PYU YO T X0 P X0 YO SPL WO SAVE wo SPH Wil SAVE PARTIAL wi PYU Yl T X0 P X0 Y1 LTP X1 T X0 YO ACC X0 Y1 PYU YO T P X1 YO ACC X0 Y1 ADDS Wl T XI P X1 YO 5 66 Software Applications Advanced Arithmetic Operations ACC 0 1 X0 Y0 2 16 MPYA Yl IT P XI1 Y1 ACC X1 YO XO Yl X0 YO 2 16 SACL Wl SAVE wi SACH W2 SAVE PARTIAL w2 ZALS W2 P X1 Y1 ACC X1 YO X0 Y1 2 16 BNC SU TEST FOR CARRY FROM W2 ADDH ONE SUM APAC ACC 1 1 X1 YO X0 Y1 2 16 SACL W2 SAVE w2 SACH W3 SAVE W3 EST THE SIGN OF THE PRODUCT NEGATE IF NEGATIVE LAC SIGN BZ DONE RETURN IF POSITIVE ZALH W1 1 ud ADDS WO ACC W1 WO CMPL ADD ONE ACC WO AND CARRY GENERATION SACL WO SAVE WO SACH W1 SAVE Wl ZALS W2 ACC 00 2 ADDH W3 ACC W3 w2 CMPL ADDC ZER
274. S320C2x scaling shifter has a 16 bit input connected to the data bus and a 32 bit output connected to the ALU The scaling shifter produces a left shift of 0 to 16 bits on the input data as programmed in the instruction The LSBs of the output are filled with zeros and the MSBs may be either filled with zeros or sign extended depending upon the state of the sign extension mode bit of status register ST1 Additional shift capabilities enable the processor to perform numerical scaling bit extraction extended arithmetic and overflow prevention Memory Interface The TMS320C2x local memory interface consists of a 16 bit parallel data bus 015 00 a 16 bit address bus A15 A0 three pins for data program memory or I O space select DS PS and IS and various system control signals The R W signal controls the direction of a data transfer and the STRB signal provides a timing signal to control the transfer When us ing on chip program RAM ROM EPROM or high speed external program memory the TMS320C2x runs at full speed without wait states The use of a READY signal allows wait state generation for communicating with slower off chip memories Up to eight levels of hardware stack are provided for saving the contents of the program counter during interrupts and subroutine calls Instructions are avail able for saving the device s complete context PUSH and POP instructions permit a level of nesting restricted only by the amount of availabl
275. SFL performs a logical left shift SFR performs logical or arithmetic right shifts depending on the state of the SXM bitin the status regis ter A one in the SXM bit corresponding to sign extension enabled causes an arithmetic shift to be performed In addition to the shift instructions data can be left shifted 0 to 15 bits when the accumulator is loaded by using aLAC instruction and left shifted 0 to 7 bits on the TMS320C2x when storing from the accumulator by using SACH or SACL instructions These shifts can be used for loading numbers into the high 16 bits of the accumulator and renormalizing the result of a multiply The in coming left shift of 0 to 15 bits can be supplied in the instruction itself or can be taken from the lowest four bits of the T register Left shifts of data fetched from data memory are available for loading the accumulator LAC LACT ad ding to the accumulator ADD ADDT and subtracting from the accumulator SUB SUBT The contents of the P register may also be shifted prior to accu mulation You can perform a logical right or left shift on the TMS320C25 in parallel with another instruction without disturbing the accumulator multiplier or any other part of the ALU Two important features of the ARAU besides its capacity to increment decriment and index make this possible First to double the value of a number you need only to add it to itself Simply stated the ARAU can have the current ARP 0 such that
276. SR FSX DR DX EODR EODX NUPNUENJ NU INSUPNA NP PLP I 6 41 Interfacing Peripherals Figure 6 24 Asynchronous Timing of TLC32040 to TMS320C2x U lf LP LF H l For further information regarding the AIC interface see page 11 196 of Linear and Interface Circuits Applications Volume 3 Peripheral Drivers Data Ac guisition Systems Hall Effect Devices literature number SLYAOOS pub lished by Texas Instruments 6 5 3 Digital to Analog D A Interface The high speed operation of the internal logic circuitry of the TLC7524 8 bit digital to analog D A converter allows an interface to the TMS320C2x with a minimum of external circuitry Figure 6 25 shows the interface circuitry which consists of one SN74ALS138 3 to 8 line decoder used to decode the address of the peripheral Figure 6 25 Interface of TLC7524 to 5320 2 TMS320C2x Address Bus 16 74ALS138 D Vo Viet256 Where D Digital Input TLC7524 Vref D0 D7 OUT1 OUT2 6 42 Hardware Applications Interfacing Peripherals When the TMS320C2x executes an OUT instruction see Figure 6 28 the peripheral address is placed on the address bus and the IS line goes low indi cating that the address on the bus corresponds to an I O port and not external data or program memory A low level at IS enables the 74ALS138 decoder and the Y output corresponding to the address on the bus is brought
277. T 5 75 b feb PID CONO a c viov nerve 5 82 Hardware Applications 6 1 6 1 System Control Circuitry 6 2 6 1 1 Powerup Reset Circuit 6 2 6 1 2 Crystal Oscillator Circuit 6 5 6 1 3 User Target Design Considerations for the XDS 6 7 6 2 interfacing Memories 6 11 6 21 Interfacing PROMS 6 12 6 22 Wait State Generator 6 19 6 23 Interfacing EPROMS 6 22 6 2 4 Interfacing Static RAMS 6 26 6 2 5 Interface Timing Analysis 1 6 29 6 3 Direct Memory Access DMA 6 32 6 4 Global 6 35 6 5 Interfacing Peripherals 6 37 6 5 1 Combo Codec Interface 6 37 6 5 2 gt AlC Interfaces need ni bey Creer nbi PES 6 40 6 5 3 Digital to Analog D A Interface
278. T IN t RFSM XSR XSR Loaded Reloaded DXR Loaded With A Figure 3 45 Continuous Receive Operation Initialization Ar 6 0 0 4 3 3 3 9 8 0 00 0 0 0 4 8 3 4 00 6 0 0 4 8 9 4 M Urt 0 6 6 0 0 0 8 4 040 0707 PA 0999000994 005094 00005959 400059299 07002929 070059294 0005059 AAA RFSM DRR Loaded From RSR 3 75 Multiprocessing and Direct Memory Access DMA 3 10 Multiprocessing and Direct Memory Access DMA The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements Some of the system configurations using the 5320 2 as follows 1 A standalone system single processor A multiprocessor with devices in parallel a Ahost slave multiprocessor with shared global data memory space or c A peripheral processor interfaced using processor controlled signals to another device These system configurations are made possible by three specialized features of the TMS320C2x the synchronization function utilizing the SYNC input the global memory interface and the hold function implemented with the HOLD and HOLDA pins The following sections describe these functions in detail 3 10 1 Synchronization 3 76 In a multiprocessor environment the SYNC input can be used to greatly ease interface between processors This input is used to cause each TMS320C2x inthe system to
279. TA SA FSX axm ey Ne di Se ep uit 969090000006 600020060 555099999906 66655099000 5 TXM 0 en A7 X A8 X B X B2 X B3 X_B4 X B5 X B6 X B7 X B8 X C1 X C2 MSB LSB XINT N 1 t DXR Loaded RESM With B XSR DXR XSR Loaded Loaded Loaded From DXR With C Figure 3 43 Serial Port Receive Continuous Operation FSM 0 om _ EON ANG ANG ANG ANG ANG ANG NG fi Read RFSM DRR DRR Read DRR Loaded DRR Loaded From RSR From RSR 3 73 Serial Port 3 9 6 Initialization of Continuous Operation Without Frame Sync Pulses 3 74 FSM is normally initialized during an XINT or RINT service routine to enable or disable FSX and FSR respectively for the next serial port operation It is necessary to start this mode with FSM 1 so that the first data transferred out of the serial port is the data written to the DXR register Otherwise the serial port starts transmitting the contents of the shift register before loading it with the value stored in the DXR register Upon each completion of a data packet transmission itloads the data contained in the DXR register into the shift regis ter and continues transmitting After the first frame pulse has been generated by or sent to the TMS320C25 the FSM bit must be reset to 0 using the RFSM instruction This must be done before the next serial port interrupt to ensure
280. TMS320C26 8192 x 16 for TMS320C28 Repeat Counter 7 0 An 8 bit counter to control the repeated execution of a single instruction Serial Port Data DRR 15 0 A 16 bit memory mapped serial port data receive register Only the Receive Register eight LSBs are used in the byte mode Serial Port Data Transmit DXR 15 0 A 16 bit memory mapped serial port data transmit register Only the Register eight LSBs are used in the byte mode 3 10 Architecture Internal Hardware Summary Table 3 1 TMS320C2x Internal Hardware Concluded Serial Port Receive Shift RSR 15 0 A 16 bit register used to shift in serial port data from the RX pin RSR Register contents are sent to the DRR after a serial transfer is completed RSR is not directly accessible through software Serial Port Transmit Shift XSR 15 0 A 16 bit register used to shift out serial port data onto the DX pin XSR Register contents are loaded from DXR at the beginning of a serial port transmit operation XSR is not directly accessible through software Shifters Shifters are located at the ALU input the accumulator output and the product register output Also an in place shifter is located within the ac cumulator Status Registers Temporary STO ST1 Two 16 bit status registers that contain status and control bits A 16 bit Register 15 0 register that holds either an operand for the multiplier or a shift code for the scaling shifter Temporary Register TR 15 0 A 16 bit regist
281. TMS320C2x User s Guide SPRUO14C October 1992 i TEXAS INSTRUMENTS Chapter 1 Introduction The TMS320 family of 16 32 bit single chip digital signal processors combines the flexibility of a high speed controller with the numerical capability of an array processor offering an inexpensive alternative to custom VLSI and multichip bit slice processors for signal processing The TMS32010 the first digital signal processor in the TMS320 family was introduced in 1982 Since that time the TMS320 family has established itself as the industry standard for digital signal processing The powerful instruction set inherent flexibility high speed number crunching capabilities and innova tive architecture make these high performance cost effective processors ideal for many telecommunications computer commercial industrial and mil itary applications _ Throughout this document TMS320C2x refers to the 5320 25 TMS320C25 33 TMS320C25 50 TMS320E25 TMS320C26 and TMS320C28 unless stated otherwise Where applicable ROM includes the on chip EPROM of the TMS320E25 Topics this chapter include Topic Page 1 2 General Description 2222 22222 1 2 1 25 1 6 1 8 General Description 1 1 General Description The 5320 family currently con
282. TTING THE MAIN PROGRAM DETERMINE WHERE 2 STORE THE STACK CONTENTS FROM WHERE RECOVER THEM STACK LARP 2 USE AR2 BNZ PO IF POPD IS NEEDED GO TO PO POP ELSE SAVE PROGRAM COUNTER RPTK 6 LOAD REPEAT COUNTER PSHD PUT MEMORY IN STACK BACC RETURN TO MAIN PROGRAM PO POP SAVE PROGRAM COUNTER MAR ALIGN STACK POINTER RPTK 6 LOAD REPEAT COUNTER PORD STACK REALIGN STACK POINTER BACC RETURN TO MAIN PROGRAM 5 24 Software Applications Program Control 5 2 3 Timer Operation The TMS320C2x 16 bit on chip timer and its associated interrupt perform vari ous functions at regular time intervals On the TMS320C25 the timer is a down counter that is continuously clocked by CLKOUT1 and counts PRD 1 cycles of CLKOUT1 By programming the period PRD register from 1 to 65 535 OFFFFh a timer interrupt TINT can be generated every 2 to 65 536 cycles A period register value of zero is not allowed Two memory mapped registers operate the timer The timer TIM register data memory location 2 holds the current count of the timer At every CLKOUT1 cycle the TIM register is decremented by one The PRD register data memory location 3 holds the starting count for the timer
283. VM set the overflow flag OV is set and the accumulator is set to the largest representable 32 bit positive 7FFFFFFFh or negative 80000000h number according to the direction of overflow OVM may also be loaded by the LST and ROVM instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SOVM overflow mode bit OVM is set enabling the overflow mode on any subsequent arithmetic operations 4 161 SPAC Subtract P Register From Accumulator Syntax Operands Execution Encoding Description Words Cycles Example 4 162 label SPAC None PC 1 PC ACC shifted P register gt Affects OV affected by PM and OVM Affects C Not affected by SXM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 The contents of the P register shifted as defined by the PM status bits are sub tracted from the contents of the accumulator The result is stored in the accu mulator Note that SPAC is unaffected by SXM the P register is always sign extended The SPAC instruction is a subset of LTS MPYS and SQRS 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SPAC PM 0 Before Instruction After Instruction Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles
284. VUUUUY UUOmRWNUUOOUUmNUUUUUJ oP Ac 4 15 Instruction Set Table 4 4 Instruction Set Summary Continued 16 Bit Opcode MSB LSB Mnemonic and Description AND DATA MEMORY OPERATIONS Branch unconditionally Branch to address specified by accumulator Branch on auxiliary register not zero Branch if TC bit 0 Branch if TC bit 0 Branch on carry Branch if accumulator 0 Branch if accumulator gt 0 Branch on I O status 0 Branch if accumulator lt 0 Branch if accumulator lt 0 Branch on no carry Branch if no overflow Branch if accumulator 0 Branch on overflow Branch if accumulator 0 Call subroutine indirect Call subroutine Return from subroutine Software interrupt 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1 mn AND DATA MEMORY OPERATIONS Mnemonic and Description 16 Bit Opcode MSB LSB Block move from data memory to data memory Block move from program memory to data memory Data move in data memory Format serial port registers Input data from port Output data to port Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag Set serial port frame synchronization mode Set serial port transmit mode Set external flag Table read Table write Assembly Language Instructions Instruction Set Table 4 4 Instruction Set Summary Continued Mnemonic and Description Words 16 Bit Opc
285. XM SUBK SXF ZAC ADDK ADRK LACK LARK LDPK MPYK RPTK SBRK SPM SUBK and ZAC not repeatable ADLK ANDK LALK LRLK ORK SBLK allnot repeatable B BANZ BBNZ BBZ BGEZ BGZ BIOZ BLEZ BLZ BNC BNV BNZ BV BZ CALL all not repeatable BACC CALA RET TRAP not repeatable IDLE not repeatable D 2 Instruction Cycle Timings TMS320C2x Instruction Cycle Timings Table D 2 Cycle Timings for Cycle Classes When Not in Repeat Mode a e o e e Ea o f e o9 IE RN NN NN VI Table in on chip RAM 3 44d Table in on chip ROM 4 Table in external memory 4 p 5 d p True Conditions Destination on chip RAM 2 2 Destination on chip ROM 3 3 Destination external memory 3 p 3 p False Condition Destination anywhere 2 2 Destination on chip RAM 2 2 Destination on chip ROM 3 3 Destination external E Xl Table in on chip RAM 2 2 d Table in on chip ROM 3 3 d Table in external memory 3 p Table on chip RAM 2 34d 3 p 4 d p Table in on chip ROM not applicable Table in external memory 2 p 342p 4 d 2p TMS320C2x Instruction Cycle Timings Table D 2 Cycle Timings for Cycle Classes When Not in Repeat Mode Concluded 3 3 d 2 Source data in external memory 4 d 4 2d 4 2d 2p Ta
286. a 130 ns max valid An EPROM interface with two wait states is shown in Figure 6 14 in which the TMS27C64 20 is interfaced to the TMS320C25 The TMS27C64 20 is a CMOS 8K x 8 bit EPROM with an access time of 200 ns The timing diagram is shown in Figure 6 15 STRB high to WS57C64F 12 output disable 6 24 Hardware Applications Interfacing Memories Figure 6 14 Interface of TMS27C64 20 to TMS320C25 TMS320C25 TMS27C64 20 74ALS244A 74AS138 Wait State Generator Two Wait States TMS27C64 20 6 25 Interfacing Memories Figure 6 15 Interface Timing of TMS27C64 20 to TMS320C25 CLKOUT1 CUN UN OR ON CLKOUT2 to DTSTR N PS RW XXX X misao XSS ee ty MEMSEL READY t3 gt le ty Table 6 5 summarizes the most critical timing parameters of the TMS27C64 20 interface to the TMS320C25 Table 6 5 Timing Parameters of TMS27C 64 20 Interface to TMS320C25 Description Symbol Used In Value Figure 6 15 Address valid to MEMSEL low TMS320C25 address valid to 527 64 20 data valid STRB high to TMS27C64 20 output disable 18 8 ns max For detailed information regarding EPROM interfacing see the application re port Hardware Interfacing to the TMS320C25 literature number SPRA014A 6 2 4 Interfacing Static RAMs Interfacing external RAM to the TMS320C 2x can be useful for expand
287. a location in program memory to a data memory location specified by the instruction The program memory ad dress is defined by the low order 16 bits of the accumulator For this operation areadfrom program memory is performed followed by a write to data memory In the repeat mode TBLR effectively becomes a single cycle instruction and the program counter that contains the ACCL is incremented once each cycle If the MP MC on the TMS320C25 is low at the time of execution of this instruction and the program memory address used is less than 4096 an on chip ROM location will be read Words 1 4 184 Assembly Language Instructions Table Read TBLR Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Table in on chip RAM 2 2 d 3 p Table on chip ROM 3 3 d 4 p 4 d p Table in external memory 3 p 4 2 4 d 2p Cycle Timings for a Repeat Execution Table in on chip RAM 1 n 1 2 2 2 1 2 Table on chip ROM 2 n 2 n nd 3 n p 3 n nd p 3 n 3 n nd Table in external memory 2 n np 1 2 2 2n nd np 3 n np 2 2 TBLR DAT6 DP 4 or TBLR If current auxiliary register contains 518 Before Instruction After Instruction Program Program Memory 306h Memory 306h 23 23 Data Data Memory 75h Memory 306h 518 518 4 185 TBLW Table Write Syntax Direct label TBLW dma Indirect
288. a repeat instruction that requires the use of the external bus is executing with HM 0 and a hold occurs the hold state is entered after the current bus cycle If this situation occurs with HM 1 the hold state will not be entered until the repeat count is completed HM is set and reset by the SHM set hold mode and RHM reset hold mode instructions respectively All interrupts are disabled while HOLD is active with HM 1 If an interrupt is received during this period the interrupt is latched and remains pending Therefore HOLD itself does not affect any interrupt flags or registers When HM 0 interrupts function normally Architecture Multiprocessing and Direct Memory Access Figure 3 48 TMS320C25 Hold Timing Diagram HOLD R N N 018 0 fetch pie NH pe 2 y gt HOLDA Notes 1 Nis the program memory location for the current instruction 2 This example shows only the execution of single cycle instructions fetched from external program memory 3 81 Multiprocessing and Direct Memory Access DMA Figure 3 48 TMS320C25 Hold Timing Diagram Continued eom WO NS NS KS KS MS I SSK SJ HOLD 15 0 2 2 N 3 N 4 PS DS RAW E 0 24 21506 in n n fetch rie 2 N43 N 4 1 Dummy N 2 execute 4 gt lt gt lt gt lt 4 gt lt HOLDA
289. a typical ALU instruction 1 Data is fetched from the RAM on the data bus 2 Datais passed through the scaling shifter and the ALU where the arithme tic is performed and 3 The result is moved into the accumulator One input to the ALU is always provided from the accumulator and the other input may be transferred from the product register PR ofthe multiplier or from the scaling shifter that is loaded from data memory Architecture Central Arithmetic Logic Unit CALU Figure 3 13 Central Arithmetic Logic Unit CALU TMS320C2x Program Bus Data Bus 16 Shifter SX or 0 0 16 TR 16 0 15 Multiplier gt PR 32 SX Shifter 6 0 1 4 4 0 32 SX 32 16 lt gt 16 ACCL 16 k o 3 SFL 0 7 Data Bus 16 Y 16 3 29 Central Arithmetic Logic Unit CALU 3 5 1 Scaling Shifter The TMS320C2x provides a scaling shifter that has a 16 bit input connected to the data bus and a 32 bit output connected to the ALU see Figure 3 13 The scaling shifter produces a left shift of 0 to 16 bits on the input data as pro grammed in the instruction The LSBs of the output are filled with zeros and the MSBs may be either filled with zeros or sign extended depending upon the status programmed into the SXM sign extension mode bit of status regis ter The TMS320C2x also contains several other shifters which allow it
290. ace peripheral processor interfaced via processor controlled signals to another device For multiprocessing applications the SMJ320C26 has the capability of allo cating global data memory space and communicating with that space via the BR bus request and READY control signals Global memory is data memory shared by more than one processor Global data memory access must be arbi trated The 8 bit memory mapped GREG global memory allocation register specifies part of the SMJ320C26 s data memory as global external memory The contents of the register determine the size of the global memory space If the current instruction addresses a location within that space BR is asserted to request control of the data bus The length of the memory cycle is controlled by the READY line SMJ320C26 supports DMA direct memory access to its external pro gram data memory using the HOLD and HOLDA signals Another processor can take complete control of the SMJ320C26 s external memory by asserting HOLD low This causes the SMJ320C26 to place its address data and control lines in a high impedance state and assert HOLDA The SMJ320C26 instruction set provides three memory addressing modes di rect indirect and immediate addressing Both direct and indirect addressing can be used to access data memory In di rect addressing seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer
291. ace Peripherals and Applications Discussion of various analog input output devices that interface directly to TMS320 DSPs and their applications Memories Analog Converters Sockets and Crystals Listings of the Tl memories analog converters and sockets available to support the TMS320C2x devices in DSP applications Crystal specifications and vendors ROM Codes Discussion of ROM codes mask options and the procedure for implementation Quality and Reliability Discussion of Texas Instruments quality and reliability criteria for evaluating performance Development Support Listings of the hardware and software available to support the TMS320C2x devices Read This First Style Symbol Conventions Style and Symbol Conventions This document uses the following conventions Program listings program examples interactive displays filenames and symbol names are shown in a special typeface similar to a typewriter s Examples use abold version of the special typeface for emphasis interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays Such as prompts command output error messages etc Here is a sample program listing 0011 0005 0001 field gt 2 0012 0005 0003 field 2 4 0013 0005 0006 field 6 3 0014 0006 even Here is an example of a system prompt and a command that you might enter C csr a user ti simuboard utilities
292. achieve constant improvement in quality and reliability cM Note Texas Instruments reserves the right to make changes in MOS semiconduc tor test limits procedures or processing without notice Unless prior ar rangements for notification have been made advises all customers to re verify current test and manufacturing conditions prior to relying on published data SSS sass J 1 Reliability Stress Tests J 1 Reliability Stress Tests J 2 Accelerated stress tests are performed on new semiconductor products and process changes to ensure product reliability excellence The typical test envi ronments used to qualify new products or major changes in processing are L High temperature operating life Storage life Temperature cycling Biased humidity Autoclave Electrostatic discharge Package integrity Electromigration be Eb B dq Channel hot electrons performed on geometries less than 2 0um Typical events or changes that require internal requalification of product in clude 1 New die design shrink or layout 1 Wafer process baseline control systems flow mask chemicals gases dopants passivation or metal systems Packaging assembly baseline control systems or critical assembly equipment Piece parts such as lead frame mold compound mount material bond wire or lead finish Manufacturing site TI reliability control systems extend beyond qualification Total rel
293. address manipulation thus freeing it for other operations 3 23 Memory Organization Figure 3 11 Auxiliary Register File 3 24 Auxiliary Register 7 AR 16 Auxiliary Register 6 AR6 16 gt Auxiliary Register 5 AR5 16 Auxiliary Register 4 AR4 16 Auxili Auxili T uxiliar uxiliar Auxiliary Register 3 AR3 16 3 Register 3 Register Auxiliary Register 2 AR2 16 LSB Pointer Buffer Auxiliary Register 1 AR1 16 46 A int ARP 3 ARP 3 Auxiliary Register 0 ARO 16 16 2 MUX 3 In B Out In A 3 Auxiliary Register Arithmetic 3 Unit ARAU 16 3 LSB Auxiliary Register File Bus AFB 16 3 or IR 3MSB J 3 MSB Data Bus 16 16 Data Bus 16 As shown in Figure 3 11 auxiliary register 0 ARO or the eight LSBs of the instruction registers can be connected to one of the inputs of the ARAU The other input is fed by the current AR being pointed to by ARP AR ARP refers to the contents of the current AR pointed to by ARP The ARAU performs the following functions ARO gt AR ARP Index the current AR by adding a 16 bit integer contained in ARO ARO AR ARP Index the current AR by subtracting a 16 bit integer contained in ARO 1 AR ARP Increment the current AR by one AR ARP 1 AR ARP Decrement the current AR by one AR ARP gt AR ARP AR ARP is unchanged In addition to the above
294. affected by all arithmetic operations of the accumulator ABS ADD ADDC ADDH ADDK ADDS ADDT ADLK APAC LTA LTD LTS MAC MACD 5 NEG SBLK SPAC SQRA SQRS SUB SUBB SUBC SUBH SUBK SUBS and SUBT The carry bit is also affected by the rotate and shift accumulator instructions ROL ROR SFL and SFR or may be explicitly mo dified by the load status register ST1 LST1 reset carry RC and set carry SC instructions For proper operation the overflow mode bit should be reset OVM 0 so thatthe accumulator results will not be loaded with the saturation value Note that this means that some additional code may be required if over flow of the most significant portion of the result is expected The carry bit is set whenever the addition of a value from the input scaling shift er orthe P register to the accumulator contents generates a carry out of bit 31 Otherwise the carry bit is reset because the carry out of bit 31 is a zero One exception to this case is the ADDH instruction which can only set not reset the carry bit This allows the accumulation to generate the proper single carry when the addition to either the lower or upper half of the accumulator actually causes the carry The following examples help to demonstrate the significance of the carry bit on the TMS320C25 for additions MSB LSB C MSB LSB FREE FF FF acc X FFFF FFF FFFF FF 0000 0000
295. also be loaded by the LST1 and RFSM instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SFSM 5 is set putting the serial port in a mode operation where frame synchronization pulses are required for each word to be transmitted or received 4 159 SHM Set Hold Mode Syntax Operands Execution Encoding Description Words Cycles Example 4 160 label SHM None 1 PC 1 HM status bit in status register ST1 Affects HM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 The SHM instruction halts internal execution when acknowledging an active HOLD HM 1 When HM 0 the processor may continue execution out of internal memory but puts its external interface in a high impedance state This bit is set to 1 by a reset 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SHM HM is set Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Set Overflow Mode SOVM label SOVM None PC 1 PC 1 overflow mode OVM status bit Affects OVM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 The OVM status bit is set to logic one which enables the overflow saturation mode If an overflow occurs with O
296. am RAM speeds processing and cuts overall system costs The SMJ320C26 provides three separate address spaces for program memory data memory and I O The on chip memory is mapped into either the data memory or program memory space depending upon the choice of memory configuration The instruction configuration parameter is used as follows to configure the blocks BO B1 and B3 as program or as data memory 0 Data Data Program Data 1 2 Program Program 3 Program Program Regardless of the configuration the user may still execute from external pro gram memory The SMJ320C26 provides a ROM of 256 words The ROM is sufficient to allow the programming of a bootstrap program and interrupt handler or to imple ment self test routines The SMJ320C26 has six registers that are mapped into the data memory space at the locations 0 5 a serial port data receive register serial port data transmit register timer register period register interrupt mask register and global memory allocation register Appendix Title Attribute Reference Running Title Attribute Reference MEMORY MAPS AFTER A RESET OR CONF 0 1 MP MC 1 PROGRAM 0 0000h INTERRUPTS AND RESERVED EXTERNAL 31 001Fh 32 0020h EXTERNAL 65535 FFFFh 2 MP MC 0 PROGRAM 0 0000h INTERRUPTS AND RESERVED BOOTLOAD ROM 255 00FFh 256 0100h RESERVED 4095 OFFFh 4096 1000h EXTERNAL 65535 FFFFh 2048 0800h EXTERNAL 65535 FFFFh
297. an add instruction for example ADD 12 AR4 the device fetches the instruction in cycle 1 During Q2 and Q3 of cycle 2 the instruction is decoded This includes the ALU command decode as well as generation of the data operand fetch address In this case the address comes from an auxil iary register During Q4 of cycle 2 and Q1 of cycle 3 the operand is fetched from the RAM location The increment of the auxiliary register is performed during Q3 and Q4 of cycle 2 and the value is loaded into the auxiliary register in Q1 of cycle 3 The ARP is also updated in Q1 of cycle 3 During Q2 and Q3 of cycle 3 the data is passed through the barrel shifter to execute the 12 bit left shift and the data is added by the ALU to the contents in the accumulator In Q4 of the third cycle the ALU result is loaded into the accumulator The sta tus of the ALU operation is loaded into the status register in Q1 of the fourth cycle The bits being loaded into the status register at this time consist of the current ALU status and the ARP associated with the next instruction 1 2 3 4 2 1 2 3 4 3 1 2 3 4 In the case of a store instruction for example SACL 0 3 2 the device operates the first two cycles in the same manner as the ADD instruction In Q1 and Q2 ofthe third cycle the data in the accumulator is passed through a barrel shifter left shifted 3 bits and zero filled The lower 16 bits of the shifted value are written to the ad
298. ange of digital signal processing applications such as telecom munications modems image processing speech processing spectrum anal ysis audio processing digital filtering high speed control graphics and other computation intensive applications With a 100 ns instruction cycle time and an innovative memory configuration the SMJ320C26 performs operations necessary for many real time digital sig nal processing algorithms Since most instructions require only one cycle the SMJ320C26 is capable of executing ten million instructions per second On chip programmable data program RAM of 1568 words of 16 bits on chip pro gram ROM of 256 words direct addressing of up to 64K words of external program and 64K words of data memory space and multipro 68 PIN FJ AND FD cessor interface features for sharing global memory minimize unneces sary data transfers to take full advantage of the capabilities of the processor The SMJ320C26 scaling shifter has a 16 bit input connected to the data bus and a 32 bit output connected to the ALU The scaling shifter pro duces a left shift of 0 to 16 bits on the input data as programmed in the instruction The LSBs of the output are filled with zeroes and the MSBs may be either filled with zeroes or sign extended depending upon the status programmed into the SXM sign extension mode bit of status register ST1 LEADED AND LEADLESS CERAMIC CHIP CARRIER PACKAGEST TOP VIEW
299. anty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Certain applications using semiconductor products may involve potential risks of death personal injury or severe property or environmental damage Critical Applications SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be directed to TI through a local SC sales office In order to minimize risks associated with the customer s applications adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Nor does TI warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used
300. arallel Interface Directly Accessible External Data Memory Space Global Data Memory Interface 16 Bit Instruction and Data Words 32 Bit ALU and Accumulator Single Cycle Multiply Accumulate Instructions 0 to 16 Bit Scaling Shifter Bit Manipulation and Logical Instructions Instruction Set Support for Floating Point Operations Adaptive Filtering and Extended Precision Arithmetic Block Moves for Data Program Management Repeat Instructions for Efficient Use of Program Space Eight Auxiliary Registers and Dedicated Arithmetic Unit for Indirect Addressing Serial Port for Direct Codec Interface Synchronization Input for Multiprocessor Configurations Wait States for Communications to Slow Off Chip Memories Peripherals On Chip Timer for Control Operations Three External Maskable User Interrupts Input Pin Polled by Software Branch Instruction Programmable Output Pin for Signalling External Devices 1 6 um CMOS Technology Single 5 V Supply Packaging 68 Pin Leaded Ceramic Chip Carrier FJ Suffix 68 Pin Leadless Ceramic Chip Carrier FD Suffix 68 Pin Grid Array Ceramic Package GB Suffix Military Operating Temperature Range 55 to 125 C Appendix Title Attribute Reference Running Title Attribute Reference description The SMJ320C26 Digital Signal Processor is a member of the TMS320 family of VLSI digital signal processors and peripherals The TMS320 family sup ports a wide r
301. ardware Applications The TMS320C2x has the power and flexibility to satisfy a wide range of system requirements The 128K word address space for program and data memory can be used to interface external memories or to implement single chip solu tions Peripheral devices can be interfaced to the TMS320C2x to perform ana log signal acquisition at different levels of signal quality Information and examples on how to interface the TMS320C2x to external de vices are presented in this section The examples given are general enough to be adapted easily for a particular system requirement For more detailed in formation refer to the application reports included in the book Digital Signal Processing Applications with the TMS320 Family Volume literature number SPRA012A Refer also to the application report Hardware Interfacing to the TMS320C25 literature number SPRAO14A published separately Appendix G discusses analog interface peripherals and their applications and Appendix H provides listings and brief information regarding Tl memories and analog conversion devices that are used in many of the applications in this chapter The TMS320C26 is similar to the TMS320C25 except for its internal memory configuration This is discussed in Section 3 4 and in Appendix B Topics in this chapter include Topic Page 6 1 System Control Circuitry 6 2 6 2 Interfacing Memories
302. are absolute with respectto the specified ad dress The section may then be placed in any area of program memory by the linker and relocated at runtime to its fixed location for execution as is shown in this example The code in Example 5 22 for the TMS320C26 is equivalent to the code in Example 5 21 written for the rest of the TMS320C2x Software Applications Example 5 21 Program Execution from Memory Memory Management title ON CHIP RAM PROGRAM EXECUTION EXAMPLE width 96 option X text RESET B INIT BRANCHES FOR EXTERNAL OR INTERNAL INTERRUPTS FOLLOW HERE AT THE DESIGNATED LOCATIONS AS REQUIRED Space 32 16 A BRANCH INSTRUCTION AT PROGRAM MEMORY LOCATION 0 DIRECTS PROCESSOR EXECUTION HERE 2 INITIALIZ THE PROCESSOR DISABLE OVERFLOW MODE SSXM SET SIGN EXTENSION LDPK 0 POINT DP REGISTER TO DAT
303. arks of Digital Equipment Corp PC DOS is a trademark of International Business Machines Corp Sun 3 is a trademark of Sun Microsystems Inc UNIX is a registered trademark of UNIX Systems Laboratories XDS is a trademark of Texas Instruments Incorporated Read This First If You Need Assistance If you want to Request more information about Texas Instruments Digital Signal Processing DSP products Order Texas Instruments documentation Ask questions about product operation or report suspected problems Report mistakes in this document or any other TI documentation If You Need Assistance Do this Write to Texas Instruments Incorporated Market Communications Manager MS 736 P O Box 1443 Houston Texas 77251 1443 Call the TI Literature Response Center 800 477 8924 Call the DSP hotline 713 274 2320 Send your comments to Texas Instruments Incorporated Technical Publications Manager MS 702 Box 1443 Houston Texas 77251 1443 Read This First Contents PIV CUUNCUIO IN EE EE DE rc rc e Sa dae e at ar cata E es 1 1 2 1 General Description e panied A riis 1 2 1 2 tn dee aa a dee 1 6 1 3 Typical Applications 1 8 Pinouts and Signal Descriptions
304. ately t4 which is the time it takes for the capacitor C4 to be charged to 1 5 V This is approximately the voltage at which the reset input switches from a logic level 0 to a logic level 1 The capacitor voltage is given by v Vool e 1 where R4C4 is the reset circuit time constant Solving 1 for gives t R C 2 For example setting the following 1 Voc 5V C4 0 47 uF 1 5 gives t t4 167 ms In this case the reset circuit of Figure 6 1 can generate a low pulse of long enough duration 167 ms to ensure the stabilization of the oscillator upon powerup in most systems 6 4 Hardware Applications System Control Circuitry 6 1 2 Crystal Oscillator Circuit The crystal oscillator circuit shown in Figure 6 3 is designed to operate at 40 96 MHz Since crystals with fundamental oscillation frequencies of 30 MHz and above are not readily available a parallel resonant third overtone oscilla tor is used If a packed clock oscillator is used oscillator design is of no con cern The master clock frequency of 40 96 MHz is chosen because it can be conve niently converted to the timing signals of interface circuits used by the commu nications industry A combo codec example is given in subsection 6 5 1 Figure 6 3 Crystal Oscillator Circuit TMS320C25 5V fcrystal 740804 p icd CLKIN t MW t 47 74AS04 0 1 uF 10kQ C 20 pF L 1 8 uH
305. ations Processor Initialization Example 5 5 TMS320C26BFNL Bootloader TMS320C26BFNL Bootloader 1 15 92 title Texas Instruments TMS320C26 Bootloader mmregs MEMORY set 060h Temporary Register LENGTH set 061h Program Length CHECK set 062h Checksum MASKFF set 063h Low Byte Mask WORD8L set 064h Low Byte Data Word WORD8H set 065h High Byte Data Word BITLEN set 066h RS232 bit length MODE set 067h Functional mode STATUS set 07Eh Statusword INTER set 07Fh Interrupt Word kk ck ck Ck ck ck ck 0k ck kk ck Ck ck ck ck ck kk ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck kk ck ko ck ko Sk ke kx Sk A ko POSST set OBh Statusbit Position POSRD set OCh Reset Downl Bit Pos 1 set 09n Block Config Bitl Po BCB2 set 08h Block Config Bit2 Po ADRESS 0200 Data Adress of PROG set OFAOOh Prog Adress of BO EPROM set 08000h EPROM address EPROM Set OBFFh EPROM length RESET AND INTERRUPTS B START AR7 Reset B PROG 2 ARO Interrupt 0 B PROG 4 AR0 Interrupt 1 B PROG 6 ARO Interrupt 2 space 16 16 reserve 16 words B PROG 8 ARO Timer Interrupt B PROG 10 AR0 Serial Port Int B PROG 12 AR0 Serial Port Int B PROG 14 AR0 Software Interrupt DOWNLOAD PROGRAM AREA GLITCH START ldpk 0 rsxm lac
306. ble in on chip RAM 3 3 d Table in on chip ROM 4 4 d Table in external memory 4 d p Interrupt destination on chip ROM 3 minimum waits for INT Interrupt destination external memory 3 2 minimum waits for INT D 4 Instruction Cycle Timings TMS320C2x Instruction Cycle Timings Table D 3 Cycle Timings for Cycle Classes When in Repeat Mode _ n ome we oe n eem 7 m mp nmm VI Table in on chip RAM 2 2 2 3 n 2p 2 2 3 2n nd Table in on chip ROM 3 n 2 3 n 2p 2 2 3 2n nd Table in external memory 2 3 n np 2p 2 2 2 not repeatable VIII not repeatable XI Table in on chip RAM 1 1 2 2 2 n nd Table in on chip ROM 2 n 2 n nd Table in external memory 2 1 2 2 2 2 2 Table on chip RAM 1 2 n nd 2 Table on chip ROM not applicable Table in external memory 1 n np 1 2 2 2 2 2 2 XIII Source data in on chip RAM 2 2 n nd 2 2 2 2 2 n nd Source data in external memory 242n42nd 3 n nd 2p 2 2n 2nd 2 2n 2nd 2p X Table in on chip RAM 2 2 n nd 3 n 2p
307. block BO as program memory OFFXXh LARP 3 Use AR3 to address block Bl 3 1023 Point to highest location in RAM block Bl RPTK 255 Compute ak sample of a length 256 convolution MACD OFF00h Multiply accumulate shift data word in block B1 and decrement AR3 The following example shows register and memory contents before and after the third step repeat loop Before Instruction After Instruction AR1 3FDh AR1 3FCh RPT OFDh RPT OFCh PC PFC OFFO2h PC PFC OFFO3h Data Data Memory 23h Memory 23h 1021 1021 Data Data Memory 7FCh Memory 23h 1022 1022 Program Program Memory OFAAAh Memory OFAAAh 65282 65282 P 458972h P OFFFF453Eh ACC 723EC41h ACC 76975 C 4 116 Assembly Language Instructions Modify Auxiliary Register MAR Syntax Direct label MAR dma Indirect label MAR next ARP Operands 0 lt dma 127 0x next ARP lt 7 Execution PC 1 PC Modifies ARP AR ARP as specified by the indirect addressing field acts as a NOP in direct addressing Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 0 1 0 1 0 1 Data Memory Address Indirect 1 0 1 0 1 0 1 See Section 4 1 Description TheMAR instruction acts as a no operation instruction in the direct addressing mode In the indirect addressing mode the auxiliary registers and the ARP are modified however no use is made of the memory being referenced MAR is used only to modify the auxiliary registers
308. bly Language Instructions DI DE Example Instructions EXAMPLE The instruction executes from internal program memory RAM The instruction executes from internal program memory ROM The instruction executes from external program memory The instruction executes using internal data memory The instruction executes using external data memory The number of cycles required for each instruction is given in terms of the pro gram data memory and I O access times as defined in the following listing p Program memory wait states Represents the number of clock cycles the device waits for external program memory to respond to an ac cess Tac is the access time in nanoseconds maximum required by the TMS320C2x for an external memory access to be made with no wait states is the memory device access time and is the clock period 4 crystal frequency p 0 If Tmem lt Tac p 2 If Tp Tac lt Tmem S Tp X 2 If Tp x 1 Tac lt Tmem lt Tp x k Data memory wait states Represents the number of cycles the device must wait for external data memory to respond to an access This number is calculated in the same way as the p number memory wait states Represents the number of cycles the device must wait for external I O memory to respond to an access This num ber is calculated in the same way as the p number Other abbreviations used in the tables and th
309. c 1 CNF1 HM FSM FO TXM PM ST1 X 1 1 1 0 1 1 1 0 0 00 REGISTER ADDRESS DATA DRR 0000h XXXX XXXX XXXX XXXX x DXR 0001h XXXX XXXX XXXX XXXX 0002 1111 1111 1111 1111 PRD 0003h XXXX XXXX XXXX XXXX IMR 0004n 1111 1111 11XX XXXX a GREG 0005n 1111 1111 0000 0000 RESERVED XIN RINT TINT INT2 INTO IMR 1111111111 X X X X X X def INIT BO 0200 DATA MEMORY BLOCK BO B2 Set 0060H DATA MEMORY BLOCK B2 IMR set 4 INTERRUPT MASK REGISTER TEXT INIT ROV DISABLE OVERFLOW MODE LDPK 0 POI O DATA MEMORY PAGE 0 LARP 7 POI AUXILIARY REGISTER 7 CONF 0 CONFIGURE ALL INTERNAL RA BLOCKS AS DATA MEMORY LACK LOAD ACCUMULATOR WITH INTERRUPT MASK SACL IMR ENABLE ALL INTERRUPTS INTERNAL DATA MEMORY INITIALIZATION Sect INIT RAM ZAC ZERO THE ACCUMULATOR LARK 7 2 POI O BLOCK B2 RPTK 31 SACL STORE ZERO IN ALL 32 LOCATIONS RLK AR7 BO POI O BLOCK BO LARK AR6 5 REPEAT LOOP1 6 TIMES LOOP1 RPTK 255 ZEROING BLOCK BO B1 AND B3 SACL ZERO THE PAGES 4 15 LARP AR6 BANZ 00 1 7 REPEAT 6 TIMES THE PROCESSOR IS INITIALIZED THE REMAINING APPLICATION DEPENDENT PART OF THE SYSTEM BOTH ON AND OFF CHIP SHOULD NOW BE INITIALIZED EINT ENABLE ALL INTERRUPTS Processor Initialization 5 1 1 TMS320C26 Download Bootstrapping Modes The TMS320C26 boot program allows three types of download Mode 1
310. cated in external memory Because of variations in pipelining due to instruc tions prior to and following the BIOZ instruction this timing may vary There fore it is recommended that several cycles of setup be provided if BIO is to be recognized on a particular cycle Figure 3 28 BIO Timing Diagram 3 58 CLKOUT2 IN Sep Gee oe em Branch Next Next Instruction BIOZ Address Instruction N 3 or Branch fetch lt N 1 pie N 2 Address BIO XXX KX KX 55005 Valid The external flag output pin is set to a high level by the SXF set external flag instruction and reset to a low level by the RXF reset external flag instruc tion XF is set high by RS The relationship between the time the SXF RXF instruction is fetched before the pin is set or reset is shown in Figure 3 29 As with BIO the timing shown for is for a sequence of single cycle single word instructions lo cated in external memory Actual timing may vary with different instruction se quences Architecture External Memory I O Interface Figure 3 29 External Flag Timing Diagram CLKOUT1 STRB 15 0 fetch XF SXF XF RXF Notes 1 Nis the program memory location for the current instruction 2 This example shows only the execution of single cycle
311. cations G 12 G 14 modem applications G 15 G 17 data converters G 15 multimedia G 2 G 4 modem communication G 3 related devices G 4 speech encoding G 3 system design consideration G 2 servo control G 12 G 14 related devices G 13 speech synthesis G 10 development tools G 11 memory G 10 voice synthesizers G 10 telecommunications G 5 G 9 general applications G 9 related devices G 7 telecom devices G 8 AND 4 38 4 9 4 40 APAC 4 41 application oriented operations 5 68 adaptive filtering 5 71 5 76 bit reversed addressing 5 77 companding 5 68 fast Fourier transforms 5 75 5 81 FFT inputs and outputs 5 76 FFT macros 5 79 FIR IR filters 5 70 PID control 5 82 applications 1 8 AR 3 9 3 24 Index 1 Index ARAU 3 9 ARB 3 9 architectural overview 3 2 arithmetic logic unit ALU 3 3 diagram 3 3 direct memory access 3 5 memory interface 3 4 multiplier 3 3 multiprocessing 3 4 on chip memory 3 2 serial port 3 4 architecture 3 1 arithmetic logic unit ALU 3 3 3 9 3 30 arithmetic operations 5 46 5 67 division 5 57 5 59 using SUBC 5 57 5 59 extended precision arithmetic 5 62 5 67 addition 5 64 multiplication 5 66 subtraction 5 65 floating point 5 60 5 62 denormalization 5 61 using LACT 5 61 using NORM 5 61 indexed addressing 5 62 moving data 5 51 using MACD 5 52 multiplication 5 53 5 57 measuring efficiency 5 55 using LTA MPY 5 54 us
312. ce 1 12C0h 777 4 167 SST Store Status Register STO Syntax Direct label SST dma Indirect label SST ind next ARP Operands 0 lt dma 3127 0 lt next ARP lt 7 Execution PC 1 PC status register STO dma Encoding 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Direct 0 1 1 1 1 0 0 0 Data Memory Address Indirect 1 1 1 1 0 0 See Section 4 1 Description Status register STO is stored in data memory In the direct addressing mode status register STO is always stored in page 0 regardless of the value of the DP register The processor automatically forces the page to be 0 and the specific location within that page is defined in the instruction Note that the DP register is not physically modified This allows storage of the DP register in the data memory on interrupts etc in the direct addressing mode without having to change the DP In the indirect addressing mode the data memory address is obtained from the auxiliary register se lected See the LST instruction for more information The SST instruction can be used to store status register STO after interrupts and subroutine calls The STO contains the status bits OV overflow flag OVM overflow mode INTM interrupt mode ARP auxiliary register pointer and DP data memory page pointer The status bits are stored in the data memory word as follows 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 ow epp wn
313. chip ROM not applicable Table in external memory 2 p 3 d p 3 2p 4 d 2p Cycle Timings for a Repeat Execution Table in on chip RAM 1 2 2 3 n nd p 3 n nd Table in on chip ROM not applicable Table in external memory 1 1 2 2 2 2 2 2 2 TBLW DATS DP 32 or TBLW If current auxiliary register contains 4101 Before Instruction After Instruction ACC 257h ACC 257h Data Data Memory 4339h Memory 4339h 4101 4101 Program Program Memory 306h Memory 4339h 257 257 4 187 TRAP Software Interrupt Syntax Operands Execution Encoding Description Words Cycles Example 4 188 label TRAP None PC 1 stack 30 PC Not affected by INTM does not affect INTM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The TRAP instruction is a software interrupt that transfers program control to program memory location 30 and pushes the program counter plus one onto the hardware stack The instruction at location 30 may contain a branch instruction to transfer control to the TRAP routine Putting PC 1 onto the stack enables an RET instruction to pop the return PC points to instruction after the TRAP from the stack 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 2 p Destination on chip ROM 3 3 3 p Destination external memory 3 p 3 p 342p 3 p 3 p Cycle Tim
314. cidentally with signal processing via software control Referto the TLC32040 data sheet for detailed information on timing and device functions The AIC is easily interfaced to the 5320 2 serial ports as shown in Figure 6 22 The TMS320C2x can communicate with the AIC either synchro nously or asynchronously depending on the information in the control register The operating sequence for synchronous communication with the TMS320C2x shown in Figure 6 23 is as follows 1 The FSX or FSR pin is brought low 2 One 16 bit word is transmitted or one 16 bit word is received 3 The FSX or FSR pin is brought high 4 The EODX or EODR pin emits a low going pulse Hardware Applications Interfacing Peripherals For asynchronous communication the operating sequence is similar but FSX and FSR do not occur at the same time see Figure 6 24 For proper opera tion the bit in the TMS320C2x control register should be set to 0 so that the FSX pin of the TMS320C2x is configured as an input the format FO sta tus bitis set to 0 and the AIC WORD BYTE pin is at logic high After each re ceive and transmit operation the TMS320C2x asserts an internal receive RINT and transmit XINT interrupt which may be used to control program execution Figure 6 22 Interface of TLC32040 to TMS320C2x TMS320C2x TLC32040 MSTR CLK FSX DX FSR DR Shift CLK Figure 6 23 Synchronous Timing of TLC32040 to TMS320C2x SHIFT CLK F
315. ck B2 DATA PROG RAM 5 2X16 Block B3 DATA PROG RAM 512 X 16 Block B1 3 32 DATA PROG RAM 512 X 16 Block BO 32 16 ACCL 16 Data Bus NOTE Shaded areas indicate a bus 3 8 Architecture Internal Hardware Summary 3 3 Internal Hardware Summary The 5320 2 internal hardware implements functions that other proces sors typically perform in software or microcode For example the device con tains hardware for single cycle 16 x 16 bit multiplication data shifting and ad dress manipulation This hardware intensive approach provides computing power previously unavailable on a single chip Table 3 1 presents a summary of the TMS320C2x internal hardware This summary table which includes the internal processing elements registers and buses is alphabetized within each functional grouping All of the symbols used in this table correspond to the symbols used in the block diagram of Section 3 2 the succeeding block diagrams in this section and the text throughout this document Table 3 1 TMS320C2x Internal Hardware Accumulator ACC 31 0 A 32 bit accumulator split in two halves ACCH accumulator high and ACCH 31 16 ACCL accumulator low Used for storage of ALU output ACCL 15 0 Arithmetic Logic Unit ALU A 32 bit twos complement arithmetic logic unit having two 32 bit input ports and one 32 bit output port feeding the accum
316. ck may be directly stored to and recovered from data memory Asoftware stack can be implemented by using the POPD instruction at the be ginning of each subroutine in order to save the PC in data memory Then be fore returning from a subroutine a PSHD is used to put the proper value back onto the top of the stack When the stack has seven values stored on it and two or more values are to be put on the stack before any other values are popped off a subroutine that expands the stack is needed such as shown in Example 5 7 In this example the main program stores the stack starting location in memory in AR2 and indi cates to the subroutine whether to push data from memory onto the stack or pop data from the stack to memory If a zero is loaded into the accumulator before calling the subroutine the subroutine pushes data from memory to the stack If a one is loaded into the accumulator the subroutine pops data from the stack to memory Because the CALL instruction uses the stack to save the program counter the subroutine pops this value into the accumulator and utilizes the BACC branch to address specified by accumulator instruction to return to the main program This prevents the program counter from being stored into a memory location The subroutine in Example 5 7 uses the BANZ branch on auxiliary register not zero instruction to control all of its loops EXampie 5 7 Software Stack Expansion THIS ROUTINE EXPANDS THE STACK WHILE LE
317. configura tions On chip memory is configured by a reset or by the CNFD and CNFP instruc tions Block BO is configured as data memory by executing CNFD or reset A CNFP instruction configures block BO as program memory TMS320C26 The reconfigurable memory space of the 5320 26 is different in both the number of configurable blocks and the size ofthe blocks For the TMS320C2x only 256 words in Block BO are reconfigurable using the CNFD and CNFP instructions The TMS320C26 has three reconfigurable blocks B0 B1 B3 each 512 words in length Four possible configurations for the three blocks of the TMS320C26 are set with the immediate instruction CONF The configuration instructions CNFD and CNFP are not defined for the TMS320C26 and CONF is not defined for the TMS320C2x Because the start and stop addresses of internal memory are not the same applications using the reconfigurable memory of the TMS320C2x will need to be redefined The memory maps and block descriptions are given in subsec tion 3 4 3 and in Appendix B 5 35 Memory Management Figure 5 9 On Chip RAM Configurations Program Data Bus Bus Memory Mapped Registers Block B2 Block BO Block B1 Memory Mapped Registers Block B2 Program Data Bus Bus Block BO Block B1 Configuring block BO as program memory is useful for implementing adaptive filters or similar applications at full speed with only on chip memories Example 5 20 illustra
318. cost and power limitations imposed by a particular application de termine the selection of a specific memory device If speed and maximum throughput are desired the 5320 2 can run with no wait states In this case memory accesses are performed in a single machine cycle Alternative ly slower memories can be accessed by introducing an appropriate number of wait states or slowing down the system clock The latter approach is more appropriate when interfacing to memories with access times slightly longer than those required by the TMS320C2x at full speed When wait states are required the number of wait states depends on the memory access time see subsection 6 2 3 With no wait states the READY input to the TMS320C2x be pulled high If one or more wait states are quired the READY input must be driven low during the cycles in which the TMS320C2x enters a wait state The TMS320C2x implements two separate and distinct memory spaces pro gram space 64K words and data space 64K words Distinction between the two spaces is made through the use of the PS program space and DS data space pins A third space the space is also available for interfacing with peripherals This space is selected by the IS I O space pin and is discussed in Section 6 5 Interfacing Memories The following brief discussion describes the TMS320C2x read and write cycles For the memory read and write timing diagrams refer to the TMS32
319. crement by one or it may be based upon the contents of ARO Bit reversed addressing modes on the TMS320C2x allow efficient I O to be performed for the resequencing of data points in a radix 2 FFT program The direction of carry propagation in the ARAU is reversed when this mode is se lected and ARO is added to subtracted from the current auxiliary register Typi cal use of this addressing mode requires that ARO first be set to a value corre 4 5 Memory Addressing Modes sponding to one half of the array size and AR ARP be set to the base address of the data the first data point See subsection 5 7 4 for an FFT example using bit reversed addressing modes Indirect addressing can be used with all instructions except immediate oper and instructions and instructions with no operands The indirect addressing format is as follows 15 14 13 12 11109 8 7 6 5 4 3 21 0 a 2 Bits 15 through 8 contain the opcode and bit 7 1 defines the addressing mode as indirect Bits 6 through 0 contain the indirect addressing control bits Bit 6 contains the increment decrement value IDV The IDV determines whether ARO will be used to increment or decrement the current auxiliary reg ister If bit 6 0 an increment or decrement if any by one occurs to the current auxiliary register If bit 1 ARO may be added to or subtracted from the cur rent auxiliary register as defined by bits 5 and 4 Bits 5 and 4 control the arithmetic operation
320. ct shifted as defined by the PM status bits is also subtracted from the accu mulator Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example MPYS DAT13 DP 6 PM 0 or MPYS If current auxiliary register contains 781 Before Instruction After Instruction Data Data 781 781 36h 2 54h ACC o 1Eh 4 122 Assembly Language Instructions Multiply Unsigned MPYU Syntax Direct label MPYU dma Indirect abel MPYU ind next ARP Operands 0 lt dma lt 127 x next ARP lt 7 Execution PC 1 PC Unsigned T register x unsigned dma P register Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 0 0 1 1 1 1 E Data Memory Address Indirect 1 1 0 0 1 1 1 1 See Section 4 1 Description The unsigned contents of the T register are multiplied by the unsigned con tents of the addressed data memory location The resultis placed in the P reg ister Note that the multiplier acts as a 17 x17 bit signed multiplier for this instruction with the MSB of both operands forced to zero The shifter at the output of the P register will always invoke sign extension on the P register when PM 3 right shift by 6 mode Therefore this shift mode should not be used if unsigned products are desired The MPYU instruction is particularly useful for computing multiple precision products such as when m
321. d point numbers Addition and subtraction can be computed in floating point by using ADDT and SUBT Example 5 36 shows a floating point multiply on the TMS320C25 The man tissas are assumed to be in Q15 format Q15 one of the various types of Q format is a number representation commonly used when performing opera tions on noninteger numbers Q format the Q number 15 015 denotes how many digits are located to the right of the binary point A 16 bit number in Q15 format therefore has an assumed binary point immediately to the right of the most significant bit Since the most significant bit constitutes the sign of the number the numbers in Q15 may take on values from 1 represented by 0 99997 to 1 Software Applications Example 5 36 Using NORM for Floating Point Multiply TH ARE NORMALIZED T OF EITHER 0 OR 1 IN THE ACCUMULATOR Advanced Arithmetic Operations TING POINT MULTIPLY USING THE NORM INSTRUCTION E FORM MC CAN BE NORMALIZED WITH A EXPONENT OF THE RESULT 15 E MULTIPLICATION OF THE TWO NUMBERS AND B AND 0 1 2 4 PROCEEDS AS FOLLOWS NORMALIZED RESULT EC EXPONENT OF R NORMALIZATION ACC MA MB ESULT BEFORE TAKE AR5 FINDS
322. d READY are pulled up with resistors on the emulator the impedance of the powered down target system can assert a control signal or load the data bus so that the XDS cannot function properly The conductive foam on the XDS target cable must be removed along with the foam on the logic show pod prior to XDS powerup Failure to do so can also cause the PROCESSOR SYNC LOST 1160 error TMS320C25 Designs Using HOLD and HOLDA When the target system as serts HOLD active low while the emulator is processing user invoked com mands requiring access of the device under emulation resources the target will not receive HOLDA until the command is complete When interfacing to dynamic RAM in the target system use READY rather than HOLD to insert refresh cycles A user invoked command could hold off HOLDA long enough to lose charge in the dynamic cells Likewise if the ad dress lines to the DRAMs not buffered the refresh cycle in a RAS ONLY REFRESH system could conflict with the emulator system that controls ad dressing during command processing 6 9 System Control Circuitry 6 10 Stack Usage An interrupt is used to halt the device being emulated thereby using one of the emulated device stack locations When an XDS is to be used the applications programmer should reserve one level of the stack for code de velopment Transmission Line Phenomena Because the XDS target cable is approxi mately 20 inches use of advanced C
323. data converters G 15 MP MC 2 5 MPY 4 119 5 54 MPYA 4 120 MPYK 4 9 4 121 MPYS 4 122 MPYU 4 123 MSC 2 6 MULT 3 10 Index 8 multimedia applications G 2 multimedia related devices G 8 multiplexed external data bus 3 42 multiplication 5 53 5 57 C25 5 66 multiplier 3 3 3 10 3 32 multiprocessing 3 75 3 81 global memory 3 76 hold function 3 78 3 81 synchronization 3 75 NEG 4 125 NOP 4 126 NORM 4 127 numeric processing 6 51 on chip EPROM 3 12 on chip memory 3 2 on chip program access 3 46 on chip program execution example 5 41 on chip RAM 3 12 configuration 5 35 5 37 configuration diagram 5 36 program execution 5 38 on chip ROM 3 12 1 1 OR 4 129 ORK 4 9 4 130 oscillator circuit diagram 6 5 LC circuit 6 5 magnitude of impedance 6 6 OUT 4 131 5 35 overflow management 5 46 P 3 10 P register PR 3 32 PAB 3 10 PAC 4 132 PC 3 10 period register 3 10 3 10 PID control 5 82 pin assignments 2 2 pinouts 2 1 pipeline hardware 3 45 pipeline operation 3 37 3 47 ADD followed by SACL 3 41 branch to on chip RAM 3 44 C25 3 39 decode 3 37 execute 3 37 fetch 3 37 instruction sequence 3 40 prefetch 3 37 RET from on chip RAM 3 45 three level 3 38 two level 3 38 wait states 3 41 with external data bus conflict 3 43 PLCC CLCC adapter socket F 2 POP 4 133 POPD 4 134 powerdown modes C25 3 53 powerup re
324. ddress if the carry bit C is low Otherwise control passes to the next instruction Note that no AR or ARP modification occurs when nothing is specified in those fields The pma can be either a symbolic or a numeric address Note that the carry bit C is affected by all add subtract and accumulate instructions as well as the ABS LST1 NEG RC SC rotate and shift instruc tions The carry bit is not affected by execution of the BC BNC or nonarith metic instructions 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 242p Cycle Timings for a Repeat Execution not repeatable BNC PRG325 1f the carry bit 0 325 is loaded into program counter Otherwise the PC is the incremented by 2 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch if No Overflow BNV label BNV ind next ARP 0 lt pma lt 65535 0 lt next ARP x 7 If overflow OV status bit 0 Then pma PC Else PC 2 gt PC and 0 gt OV Modify AR ARP and ARP as specified Affects OV affected by OV 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 d 1 1 0 315 1 1 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP ar
325. de 85 C ambient temperature with an 85 relative humidity RH Typical bias voltage is 5V and ground on alternating pins Autoclave pressure cooker Temperature cycle Thermal shock PIND Plastic packaged devices exposed to moisture at 121 Cusing apressure of one atmosphere above normal pressure The pressure forces moisture permeation of the package and accelerates corro sion mechanisms if present on the device Exter nal package contaminants can also be activated and caused to generate inter pin current leakage paths Device exposed to severe temperature extremes in an alternating fashion 65 C for 15 minutes and 150 C for 15 minutes per cycle for at least 1000 cycles Package strength bond quality and consistency of assembly process are stressed in this environment Test similar to the temperature cycle test but in volving a liquid to liquid transfer per MIL STD 883C Method 1011 Particle Impact Noise Detection test A nonde structive test to detect loose particles inside a de vice cavity J 3 Reliability Stress Tests J 4 Mechanical Sequence Fine and gross leak Mechanical shock PIND optional Vibration variable frequency Constant acceleration Fine and gross leak Electrical test Thermal Sequence Fine and gross leak Solder heat optional Temperature cycle 10 cycles minimum Thermal shock 10 cycles minimum Moisture resistance Fine and gross leak Electrical test P
326. ding the TIM register A new counter period can be written to the period register without disturbing the current timer count The timer will then start the new period after the current count is complete If both the PRD and TIM registers are loaded with a new period the timer begins decrementing the new period without generating an interrupt Thus the pro grammer has complete control of the current and next periods of the timer If the timer is not used either TINT is to be masked or all maskable interrupts are to be disabled by a DINT instruction The PRD register can then be used as ageneral purpose data memory location If TINT is used the PRD and TIM registers are to be programmed before unmasking the TINT 3 6 6 Repeat Counter The repeat counter RPTC is an 8 bit counter which when loaded with a num ber N causes the next single instruction to be executed N 1 times The RPTC can be loaded with a number from 0 to 255 using either the RPT repeat or RPTK repeat immediate instructions This results in a maximum of 256 executions of a given instruction RPTC is cleared by reset The repeat feature can be used with instructions such as multiply accumulates MAC MACD block moves BLKD BLKP I O transfers IN OUT and table read writes TBLR TBLW These instructions which are normally multicycle are pipelined when using the repeat feature and effectively become single cycle instructions For example the table read instruction
327. direct addressing of data memory or for temporary data storage Indirect auxiliary register addressing see NO allows placement of the data memory address of an instruction oper and into one of the auxiliary registers These registers are pointed to by a three bit auxiliary register pointer ARP that is loaded with a value from 0 through 7 designating ARO through ART respectively The auxiliary registers andthe ARP may be loaded either from data memory or by an immediate oper and defined in the instruction The contents of these registers may also be stored in data memory Chapter 4 describes the programming of the indirect addressing mode Architecture Memory Organization Figure 3 10 Indirect Auxiliary Register Addressing Example Auxiliary Register File Data Memory ARO 053 7h Location 1 5150 000h Internal Auxiliary 03FFh Register 0400h Pointer AR2 JOE 9F Ch External in STO arp o 1 1 oF F 3 A n AR4 103 Bh OFFFFh 5 26B 1h AR6 0008h AR7 843 Dh The auxiliary register files 0 7 on the TMS320C2x are connected to the auxiliary register arithmetic unit ARAU shown in Figure 3 11 The ARAU may autoindex the current auxiliary register while the data memory location is being addressed Indexing by either 1 or by the contents of ARO may be per formed As a result accessing tables of information does not require the cen tral arithmetic logic unit CALU for
328. does not require one of the processors to be halted Global memory can be used in various digital signal processing tasks such as filters or modems where the algorithm being implemented may be divided into sections with a distinct processor dedicated to each section In this multipro cessor scheme the first and second processors may share global data memory as well as the second and third the third and fourth etc Arbitration logic is required to determine which section of the algorithm is executing and which processor has access to the global memory With multiple processors dedicated to distinct sections of the algorithm throughput may be increased via pipelined execution By loading the global register GREG you can program the size of the global memory between 256 and 32K locations in data memory After global memory is defined in the GREG the TMS320C2x asserts the BR bus request signal before each global memory access The BR signal stays low on back to back cycles in the TMS320C25 The processor then inserts wait states until a bus grant is given by asserting the READY line Figure 6 20 illustrates such a glob al memory interface Because the processors can be synchronized by using the SYNC pin the arbitration logic can be simplified and the address and data bus transfers can be more efficient see subsection 3 10 1 for information on synchronization The SYNC pin on the TMS320C2x may also be used to synchronize several proc
329. dress specified by the current auxiliary register During Q3 and 04 of the third cycle the index register ARO is added to the contents of the current auxiliary register and loaded back into the current auxiliary register in Q1 ofthe fourth phase In Q1 of the fourth cycle the auxiliary register pointer is changed to AR2 There is no execution phase ofthis instruction Figure 3 19 shows the ADD and SACL instructions operating back to back in a program sequence It is assumed that both instructions reside in external zero wait state memory and that the data resides in on chip RAM Architecture System Control Figure 3 19 Pipeline Operation of ADD Followed by SACL Clock CLKOUT1 CLKOUT2 STRB Address Data Decode RAM Execute AUXREG Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 JUUUUU UU UU ULL LLL ADD 12 AR4 ADD ADD Read SACL Write Dummy WD When the device is reading instructions out of on chip ROM the basic internal operation of the pipeline is the same The only difference is that the control lines that is STRB PS and R W are inactive If the device is fetching the instructions from on chip RAM the pipeline is shortened to 2 5 cycles since the device can fetch the instruction in half a cycle as opposed to the full cycle required in an external o
330. ds if on chip RAM is used for program memory while still leaving 32 locations for intermediate storage See subsection 3 4 3 for memory map configurations In the TMS320C26 of the 1568 words 32 words block B2 are always data memory and all other words are programmable as either data or program memory as shown in Figure 3 5 A data memory size of 1568 words allows the TMS320C26 to handle a data array of 1536 words while still leaving 32 locations for intermediate storage When using BO B1 or B3 as program memory instructions can be downloaded from external program memory into on chip RAM and then executed The TMS320C2x can address a total of 64K words of data memory The on chip data memory and internally reserved locations are mapped into the lower 1K words of the data memory space Data memory is directly expandable up to 64K words while still maintaining full speed operation A READY line is pro vided for interface to slower less expensive memories such as DRAMs 3 4 2 Program Memory On chip program RAM ROM EPROM or high speed external program memory can be used at full speed with no wait states Alternatively the READY line can interface the TMS320C2x to slower less expensive external memory A total of 64K words of memory space is available Internal RAM block BO can be configured as program memory using instructions for that purpose Execu tion from this block can be initiated after the memory space has been reconfi g
331. e target logic generates a READY high condition the device appears to com plete the memory cycle by driving DS PS IS or STRB to their inactive states at their normal switching times The device under emulation is held not ready for at least one extra clock cycle or until the memory substitution data is avail able The memory substitution data is then driven onto the data bus on reads while all bus control signals at the target connector are high Additional wait states can be added with the use of the target READY line In this case the memory control lines model the target access timing However the program cycle countis affected by the additional cycles internal to the emu lator s access of the dynamic RAM Since the system responds to the READY line the target must eventually return a valid READY high on each access Miscellaneous Considerations When the XDS is powered up the device under emulation is placed in the run mode with all memory substitution turned off The control processor does not attempt to communicate with the device under emulation until you communi cate with the emulator If the target system is asserting RS HOLD or not READY continuously to the device under emulation the control processor cannot gain control of the device under emulation and reports a PROCESSOR SYNC LOST 1160 error This condition can be caused by a powered up emu lator plugged into a powered down target system Although the RS HOLD an
332. e BIO line high and the start bit drives the line low The next bit is data and must be driven high Since the data is received MSB first the synchroniza tion word sent to the serial port may be 1xxxxxxx The low period of the start bit is sampled by using a software timing loop The C26 then times out the re maining data bits dummy bits and waits for the next start bit BIO going low Note that the serial link is not interrupt driven and therefore uses all of the avail able processor overhead for timing the incoming data stream STATUS 1 RS232 transfer The second word sent to the C26 is the 8 bit STATUS word The bit fields are given below Bits DO D1 and D2 are the MSBs of the program length Bit D3 selects the reset download mode 0 reset only no download 1 start download of the program Bit D4 selects the transmission memory format 0 8 bit format 1 16 bit format not allowed in serial mode Bits D4 D7 should be set low Do not use them Processor Initialization INTERRUPT 1 RS232 transfer The third word defines the interrupt and final memory configuration to be installed after bootstrapping During the bootload process blocks BO B1 and are configured as data and are always loaded first This word is loaded into the C26 with a single transfer with the upper bits being masked off The config uration is as follows Bits 00 05 are loaded into the interrupt mask register IMR Bits D6 amp D7 define
333. e DP In the indirect addressing mode the data memory address is obtained from the auxiliary register selected See the LST1 instruction for more information SST1 is used to store status bits after interrupts and subroutine calls ST1 con tains the status bits ARB auxiliary register pointer buffer CNF RAM configu ration control TC test control SXM sign extension mode XF external flag FO serial port format TXM transmit mode and the PM product regis ter shift mode ST1 on the TMS320C2x also contains the status bits C carry bit HM hold mode and FSM frame synchronization mode The bits loaded into status register ST1 from the data memory word are as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the TMS320C26 bits 12 and 7 hold and CNF1 respectively see the CONF instruction for decoding Note that SST1 may be used to store status register ST1 anywhere in data memory while SST1 in the direct addressing mode is forced to page 0 Words 1 Cycles 4 170 Assembly Language Instructions Store Status Register ST1 55 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example 55 DAT97 DP don t care or SSTl If current auxiliary register contains 97 Before Instruction After Instruction Status Status Register 0A7EO0h Register OA7EOh STI STi Data Data Memory OBh Memory 7 97 97
334. e OV status bit is set The carry bit C on the TMS320C2x is always reset to zero by the execution of this instruction 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 23 ABS Absolute Value of Accumulator Example ABS Before Instruction After Instruction e IE mw C es Fem C 4 24 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Add to Accumulator With Shift ADD Direct label ADD shift Indirect label ADD shift next ARP 0 dma x 127 0 lt next ARP lt 7 0 lt shift lt 15 defaults to 0 PC 1 PC ACC x 2 shift 4 ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affects OV affected by OVM and SXM Affects C 15 1 11 10 9 8 7 6 5 4 3 2 1 0 4 13 12 Direct 0 0 0 0 Data Memory Address Indirect o 0 0 0 See Section 4 1 The contents of the addressed data memory location are left shifted and add edtothe accumulator During shifting low order bits are zero filled High order bits are sign extended if SXM 1 and zero filled if SXM 0 The result is stored in the accumulator Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 25 ADD Aad to Accumulator With Shift
335. e RAM The interrupts used in these devices are maskable All control operations are supported on the 5320 2 by an on chip memory mapped 16 bit timer a repeat counter three external maskable user interrupts and internal interrupts generated by serial port operations or by the timer A built in mechanism protects from instructions that are repeated or be come multicycle due to the READY signal and from holds and interrupts Serial Port An on chip full duplex serial port provides direct communication with serial devices such as codecs serial A D converters and other serial sys tems The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware The two serial port memory mapped registers the data transmit receive registers may be operated in ei ther an 8 bit byte or 16 bit word mode Each register has an external clock in put a framing synchronization input and associated shift registers Multiprocessing Applications The TMS320C2x has the capability of allo cating global data memory space and communicating with that space via the BR bus request and READY control signals The 8 bit memory mapped global memory allocation register GREG specifies up to 32K words of the TMS320C2x data memory as global external memory The contents of the reg ister determine the size of the global memory space If the current instruction addresses an operand within that space BR is asserted to
336. e addressed data memory location The result is placed in the P register Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution MPY DAT13 DP 8 or MPY If current auxiliary register contains 1037 Before Instruction After Instruction Data Data 1037 1037 P P 4 119 Multiply Accumulate Previous Product Syntax Direct label MPYA dma Indirect label MPYA ind next ARP Operands 0 lt dma lt 127 0 lt next ARP lt 7 Execution PC 1 PC ACC shifted P register register x dma register Affects C and OV affected by OVM and PM 5 14 13 1 7 6 5 4 3 2 1 0 1 2 11 10 9 8 Direct 0 0 1 1 141 0 1 0 m Data Memory Address Indirect 1 1 1 0 10 See Section 4 1 Description The contents of the T register are multiplied by the contents of the addressed data memory location The result is placed in the P register The previous prod uct shifted as defined by the PM status bits is also added to the accumulator Encoding Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example MPYA DAT13 6 PM 0 or MPYA If current auxiliary register contains 781 Before Instruction After Instruction Data Data 781 781 P 36h P 2Ah ACC 54h ACC o 8Ah 4 120 Assembly Language Instructions
337. e and the control signals go to an inactive state logic high Refer to Chapter 5 for the effect instructions have on I O Interfacing to memory and devices of varying speeds is accomplished by using the READY line When communicating with slower devices the TMS320C2x processor waits until the other device completes its function signals the processor via the READY line and continues execution see Chapter 6 3 7 4 Memory Combinations The exact sequence of operations performed as instructions execute depends on the areas in memory where the instructions and operands are located There are eight possible combinations of program and data memory because information can be located in internal RAM external memory or internal ROM EPROM available on TMS320C25 TMS320E25 The eight possible com binations are 1 Program Internal RAM Data Internal PI DI 2 Program Internal RAM Data External PI DE 3 Program External Data Internal PE DI 3 55 External Memory and I O Interface 3 56 4 Program External Data External PE DE 5 Program Internal ROM Data Internal PR DI on the 5320 25 6 Program Internal EPROM Data Internal PR DI on the TMS320E25 7 Program Internal ROM Data External PR DE on the 5320 25 8 Program Internal EPROM Data External PR DE on the 5320 25 Appendix E provides cycle timings for instructions both when repeated and when not repeated The following is a summary of program ex
338. e corresponding flag is set in the interrupt flag register IFR If the corresponding bit in the interrupt mask register IMR is set and interrupts are enabled INTM 0 then interrupt processing begins When the interrupt vector is loaded into the program counter interrupts are disabled INTM 1 and a branch is made to the appropriate routine via the branch instruction stored at the associated vector location Since all interrupts are disabled interrupt processing will proceed without further interruption un less the interrupt service routine ISR re enables interrupts Unless the interrupt service routines are simple I O handlers the processing in each ISR generally must assure that the processor context is preserved dur ing execution The context must be saved before the routine executes and must be restored when the routine is finished A common routine or routines individualized for each interrupt may be used to secure the context of the pro cessor during interrupt processing Context switching is also useful for subrou tine calls especially when extensive use is made of the stack or auxiliary regis ters Code examples of context switching and an interrupt service routine are provided in this section 5 3 1 Context Switching Context switching commonly required when processing a subroutine call or interrupt may be quite extensive or simple depending on the system require ments On the TMS320C2x the program counter is stored aut
339. e interrupts are disabled INTM is set and reset by the DINT and EINT instructions RS and IACK also set INTM INTM has no effect on the unmaskable RS interrupt Note that INTM is unaffected by the LST instruction Overflow flag bit As a latched overflow signal OV is set to 1 when overflow occurs in the ALU Once an overflow occurs the OV remains setuntil a reset BV BNV or LST instruction clears the OV Overflow mode bit When setto 0 overflowed results overflow normally in the accumulator When set to 1 the accumulator is set to either its most positive or its most negative value upon encountering an overflow The SOVM and ROVM instructions set and reset this bit respectively LST may also be used to modify the OVM Product shift mode If these two bits are 00 the multiplier s 32 bit product is loaded into the ALU with no shift If PM 01 the PR output is left shifted one place and loaded into the ALU with the LSBs zero filled If PM 10 the PR outputis left shifted by four bits and loaded into the ALU with the LSBs zero filled PM 11 produces a right shift of six bits sign extended Note that the PR contents remain unchanged The shift takes place when transferring the contents of the PR to the ALU PM is loaded by the SPM and LST1 instruc tions The PM bits are cleared by RS Sign extension mode bit SXM 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter SXM 0 suppresses
340. e modified as specified Control then passes to the designated program memory address pma if the OV overflow flag is clear Otherwise the OV is cleared and control passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 2 2p Destination on chip ROM 3 3 3 2p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 242p 2 2 Cycle Timings for a Repeat Execution not repeatable BNV PRG315 315 is loaded into the program counter if the overflow flag is clear OV is cleared 4 65 BNZ Branch if Accumulator Not Equal to Zero Syntax Operands Execution Encoding Description Words Cycles Example 4 66 label ind next ARP 0 lt pma lt 65535 0 lt next ARP x 7 If ACC 0 Then pma gt Else PC 2 gt PC Modify AR ARP and ARP as specified 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 1 0 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the contents of the accumulator are not equal to zero Otherwise control passes to the next instruction Note that no AR
341. e save and ALU instruction A clear understanding of this information in conjunction with the data Appen dix E should be sufficient to predict the operation of the TMS320C25 pipeline Reset RS is a nonmaskable external interrupt that can be used at any time to put the TMS320C2x into a known state Reset is typically applied after pow erup when the machine is in a random state 3 47 System Control 3 48 Driving the RS signal low causes the TMS320C2x to terminate execution and forces the program counter to zero RS affects various registers and status bits At powerup the state of the processor is undefined For correct system operation after powerup a reset signal must be asserted low for at least three clock cycles to guarantee a reset of the device see Section NO TAG for other important reset considerations Processor execution begins at location 0 which normally contains a B branch statement to direct program execution to the system initialization routine also see Section NO TAG for an initializa tion routine example Section 4 1 provides system control circuitry design ex amples When an RS signal is received the following actions take place 1 RAM configuration bits are set so that all on chip RAM resides in data space 2 The program counter PC is set to 0 and the address bus A15 A0 is driv en with all zeros while RS is low 3 The data bus 015 00 is placed in the high impedance state 4 All m
342. e video D A TL5632 8 tm 2 8 Parallel 3 Parallel Triple flash A D TLC5703 3 Parallel Flash A D TLC5503 Parallel Flash A D TLC5502 5 1 Parallel For further information or application assistance please call TI Linear Applica tions at 214 997 3772 1 1 1 1 1 1 1 G 20 Analog Interface Peripherals and Applications Memories Analog Converters Sockets and Crystals This appendix provides product information regarding memories analog con verters and sockets which are manufactured by Texas Instruments and are compatible with the TMS320C2x Information is also given regarding crystal frequencies specifications and vendors The contents of the major areas in this appendix are listed below Topic Page H 1 Memories and Analog Converters H 2 25 5 157 H 3 246 4 H 1 Memories Analog Converters H 1 Memories and Analog Converters H 2 This section provides product information for EPROM memories codecs ana log interface circuits and A D and D A converters All of these devices can be interfaced with TMS320C2x processors see Chapter 6 for hardware interface designs Refer to Digital Signal Processing Applications with the TMS320 Family for additional information on interfaces using memories and analog conversion devices The following paragraphs
343. eJC thermal resistance 2 41 0 095 1 91 0 075 p r 0 28 0 011 x 0 18 0 007 2 16 0 085 1 65 0 065 0 38 0 015 FA 01300005 0 58 0 023 f 0 33 0 013 i 24 13 0 950 23 11 0 910 0 81 0 032 i 0 51 0 020 d b d b d b ch cb d b d b pm d b d b d n d h d h 0 89 0 035 0 51 0 020 1 27 0 050 aa eles I 3 43 0 135 0 25 0 010 0 76 0 030 064 0 025 292 11 5 ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES E 50 Appendix Title Attribute Reference Running Title Attribute Reference 24 38 0 960 23 88 0 940 JANICAL DATA 4 21 89 0 862 gt 24 38 0 960 23 88 0 940 TOP VIEW 21 89 0 862 MAX Junction to free air o RJA thermal resistance INDEX CORNER m 20 57 0 810 Junction to case i 20 07 0 790 d R JC thermal resistance 0 76 0 030 2 36 0 003 0 25 0 010 1 96 0 077 CHAM 0 71 0 028 0 56 0 022 1 27 0 050 ZA MA KUAK 1 40 0 055 0 20 0 008 R 1 27 0 050 1 14 0 045 e 91510990 3 050 0 120 45 CHAM 2 08 0 082 3PLS ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES WITH THE INCHES GOVERNING E 51 Bunning Title Attribute Ref 28 448 1 120 MECHANIC
344. ecution orga nized according to memory configuration PI DI or PR DI PE DI When both program and data memory are on chip the processor runs at full speed with no wait states Note that IN and OUT instructions have different cycle timings when program memory is internal IN requires two cycles to execute whereas OUT re quires only one cycle If external program memory is sufficiently fast this memory mode can run at full speed because internal data operations can occur coincidentally with exter nal program memory accesses If external program memory is not fast enough wait states may be gener ated by using the READY input PI DE PE DE or PR DE Additional cycles are required to execute instructions that reference an external data memory space At leasttwo cycles are required to execute read from ex ternal data memory instructions such as ADD LAR etc Further additional cycles may be required be cause of wait states if external data memory is not fast enough to be accessed within a single cycle Note however that the TMS320C2x has the capabil ity of executing write to external data memory instruc tions in a single cycle when program memory is inter nal two cycles are required if program memory is also external Additional cycles are also required in this case if external data memory is not sufficiently fast In all memory configurations where the same bus is used to communicate with external data program or I
345. ed a clock may be input to the device on this pin 2 6 Pinouts and Signal Descriptions TMS320C2x Signal Descriptions Table 2 1 TMS320C2x Signal Descriptions Continued Pin vo zt Description PGA PLCCT Serial Port Signals CLKR B9 64 Receive clock input External clock signal for clocking data from the DR data receive pin into the RSR serial port receive shift register Must be present during serial port transfers CLKX A9 63 Transmit clock input External clock signal for clocking data from the XSR serial port transmit shift register to the DX data trans mit pin Must be present during serial port transfers J1 24 Serial data receive input Serial data is received in the RSR serial port receive shift register via the DR pin DX 11 54 O Z Serial data transmit output Serial data transmitted from the XSR serial port transmit shift register via the DX pin Placed in high impedance state when not transmitting FSR J2 25 Frame synchronization pulse for receive input The falling edge ofthe FSR pulse initiates the data receive process beginning the clocking of the RSR FSX F10 53 Frame synchronization pulse for transmit input output The falling edge of the FSX pulse initiates the data transmit process begin ning the clocking of the XSR Following reset the default operat ing condition of FSX is as an input This pin may be selected by software to be an output when the TXM bit in the status register is set
346. ed Arithmetic Operations Example 5 27 Using the ARO Test Bit to Calculate the Square Root of a Long Integer 5 50 KKK KKK ck Ck ck KKK KKK KKK KKK KR KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KK KKK KKK LNG SQRT ASM Calculates the 16 bit sqrt of a long int long 1 9 long prototype id S 4 pe 2 This routine uses a succesive A K t ARO approximation technique that ds Assn holds both the test bit and AR2 the guess in ARx registers k SSS SSS SSS entry gt guess mem config pi di input hi cycles pos 243 d eee eres 0 neg 7 input lo E EM Ck CK global l1ng sqrt ing sqrt blez ret 0 i adrk 2 gt ARO sar ARO store ARO gt AR2 sar AR2 store AR2 gt AR3 lrlk ARO 08000h initial test bit lrlk AR2 08000h initial guess 0 This section performs successive aproximation more sar ARZ Store guess lt Square guess unsigned mpyu subh ACCU guess input subs 4 bgz too_hi BRO AR2 ARO gt gt 1 guess 2 gt input too_low mar 0 ARO add test bit if guess too low banz more AR1 more test bits b done too_hi mar 0 sub test bit if guess too high banz more AR1 mo
347. ed As Data Memory TMS320C26 TMS320C25 Address Address Address Address Pages Decimal Hexadecimal Pages Decimal Hexadecimal pe o 96 127 0060h 00F7h 96 127 0060 007 512 1023 0200h 03FFh 512 768 0200h 02FFh 1024 1536 0400h 05FFh 769 1024 0300h 03FFh Configured As Program Memory TMS320C26 TMS320C25 Address Address Address Address Pages Decimal Hexadecimal Pages Decimal Hexadecimal B2 is not configurable B2 is not configurable Bo 500 503 64000 64511 FAO0h FBFFh 510 511 65280 65535 FFOOh FFFFh 504 507 64512 65023 FCOOh FDFFh 1 is not configurable 508 511 65024 65535 FEOOh FFFFh As shown Table 3 2 along with Figure 3 6 Figure 3 7 there is no difference between the TMS320C25 26 data spaces except for the location of memory blocks therefore no data memory modification is necessary However for an internal program such as relocatable code the start and stop addresses of each RAM block must be considered 3 17 Memory Organization Figure 3 6 Comparison of Internal RAM Configured as Data Space 5320 25 5320 28 TMS320C26 0 Memory Mapped Memory Mapped 0 05h Registers Registers 05h Reserved Reserved 05Fh 060h 060h B2 B2 07Fh 07Fh 080h 080h 01FFh 01FFh 2FFh B1 E O3FFh 03FFh i _ O5FFh 0600h External B3 New RAM Block 07FFh 0800h External FFFF Figure 3 7 Comparison of Internal RAM Configured as Program Space TMS320C25 T
348. ed Speech Synthesis Applications G 10 G 4 Servo Control Disk Drive Applications G 12 G 5 Modem Applications G 15 G 6 Advanced Digital Electronics Applications for Consumers G 18 Memories Analog Converters Sockets and Crystals H 1 H 1 Memories and Analog Converters H 2 125 SOCKGIS note tere tente etai erst aute e Eta Ron EM RU a ee H 3 Eo Grystalszi estin ccd meets cons cca Meuron iu sedit cena ace t LUE DA E H 4 FROM 1 1 Quality and Reliability J 1 J 1 Reliability Stress Tests J 2 Development K 1 K 1 Device and Development Support Tool Nomenclature K 2 Table of Contents TMS320 Device Evolution 1 3 TMS320C2x Pin Assignments 2 2 TMS320C28 Pin Assignments 2 3 TMS320C2x Simplified Block Diagram 3 3 TMS320C25 E25 Block Diagram
349. eft shift of 1 bit Left shift of 4 bits Right shift of 6 bits 3 33 Central Arithmetic Logic Unit CALU 3 34 Left shifts specified by the PM value are useful for implementing fractional arithmetic or justifying fractional products For example the product of either two normalized 16 bit 2s complement numbers or two Q15 numbers con tains two sign bits one of which is redundant Q15 format one of the various types of Q format is a number representation commonly used when perform ing operations on noninteger numbers see subsection NO TAG for an ex planation and examples of Q15 representation The single bit left shift elimi nates this extra sign bit from the product when itis transferred to the accumula tor This results in the accumulator contents being formatted in the same man ner as the multiplicands Similarly the product of either a normalized 16 bit 2s complement or Q15 number and a 13 bit 2s complement constant con tains five sign bits four of which are redundant This is the case for example when using the MPYK instruction Here the four bit shift properly aligns the re sult as it is transferred to the accumulator Using the right shift PM value allows the execution of up to 128 consecutive multiply accumulate operations without the threat of an arithmetic overflow thereby avoiding the overhead of overflow management The shifter can be disabled to cause no shift in the product when working with integer or 32 b
350. eir meanings are as follows br int INT ext Branch from Internal program memory Interrupt External program memory The number of times an instruction is executed when using the RPT or RPTK instruction Refer to Appendix NO TAG for further information on instruction cycle classifi cations and timings 4 21 EXAMPLE Example Instructions Example ADD DAT1 3 DP 10 or ADD 3223 If current auxiliary register contains 1281 Before Instruction After Instruction Data Data 1281 1281 JL 9 C sample code presented the above format shows the effect of the code on memory and or registers The use of the carry bit C provided on the TMS320C25 is shown in the small box 4 22 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Absolute Value of Accumulator ABS label ABS None PC 1 PC ACC Affects OV affected by OVM Affects C Not affected by SXM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 If the contents of the accumulator are greater than or equal to zero the accu mulator is unchanged by the execution of ABS If the contents of the accumula tor are less than zero the accumulator is replaced by its 2s complement value Note that 80000000h is a special case When the overflow mode is not set the ABS of 80000000h is 80000000h In the overflow mode the ABS of 80000000h is 7FFFFFFFh In either case th
351. em can again receive hold acknowledge when HOLD is asserted At this point the emulator is waiting for another command from the keyboard Communication between the device being emulated and the control process occurs when DS PS IS and HOLDA are all high 6 7 System Control Circuitry 6 8 The target system should drive the data bus only when the following conditions are met HOLDA is active or Lj 05 PS or IS is active and R W is high The XDS hardware uses the data bus only while the above signals are inactive When these rules are not followed the XDS gives a PROCESSOR SYNC LOST 1160 error This error may also be caused by signal to signal shorts in the target system misalignment of the target connector poor grounding of the target connector or wiring errors on the target system READY and Memory Substitution Because the XDS adds one internal level of 7 ns in series with the READY in put your system is left with only 10 ns to generate READY This can be accom plished by generating READY with a 10 ns TIBPAL16R4 device READY should be generated from DS PS or IS and the decode of the address lines The target system must present a valid READY high on each external access even when using the XDS substitution memory Suggested implementation of READY logic on the target system should hold READY high until target memory requiring wait states is addressed The XDS provides two types of memory substitution
352. emory Address Indirect 0 1 1 1 1 0 1 See Section 4 1 The T register is loaded with the contents of the specified data memory ad dress dma The contents of the product register shifted as defined by the PM status bits are added to the accumulator with the result left in the accumulator The function of the LTA instruction is included in the LTD instruction Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions Load Register Accumulate Previous Product LTA Before Instruction Data 804 eB LTA DAT36 DP 6 PM Or LTA l1f current auxiliary register contains 804 After Instruction Data 804 T 62h ACC A 4 105 LTD Load T Register Accumulate Previous Product and Move Data Syntax Operands Execution Encoding Description Words 4 106 Direct label LTD Indirect label LTD ind next ARP 0 lt dma x 127 0 next ARP x 7 PC 1 PC dma T register dma 1 ACC shifted P register ACC Affects OV affected by OVM and PM Affects C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 0 0 Data Memory Address Indirect See Section 4 1 E E A A E register is loaded with the contents of the specified data memory ad dress dma The contents of the P register
353. emory and I O space control signals PS DS IS RW STRB and BR are deasserted by setting them to high levels while RS is low 5 All interrupts are disabled by setting the INTM interrupt mode bit to 1 Note that RS is nonmaskable The interrupt flag register IFR is reset to all zeros 6 Status bits are set For all TMS320C2x devices 0 gt OV 1 XF 05 FO 0 gt 0 gt CNF 0 gt 0 gt CNF 1 for the TMS320C26 1 gt SXM 0 gt PM 1 HM 1 gt and 1 gt FSM The remaining status bits on the 5320 2 are unchanged 7 The global memory allocation register GREG is cleared to make all memory local 8 The RPTC repeat counter is cleared 9 The DX data transmit pin is placed in the high impedance state Any transmit receive operations on the serial port are terminated andthe TXM transmit mode bit is reset to a low level This configures the FSX framing pulse to be an input A transmit receive operation may be started by fram ing pulses only after the removal of RS 10 The TIM register is set to the maximum value OFFFFh on reset Also the PRD register on the TMS320C25 is initialized by reset to OFFFFh See Example 5 1 TIM register begins decrementing only after RS is deasserted Architecture System Control 11 The IACK interrupt acknowledge signal is generated in the same manner as a maskable interrupt 12 The state of the RAM is undefined following RS
354. ence for 8 Bit Transfers 5 8 Sequence for 16 Bit Transfers 5 8 Building LENGTH From STATUS and PROGRAM LENGTH Words 5 9 RS232 Connection to the 5320 26 5 11 Sequence for RS232 Transfer 8 Data Bits Only 5 13 Building LENGTH From STATUS and PROGRAM LENGTH Words 5 14 External Memory Byte Ordering 5 16 On Chip RAM Configurations 5 36 MACD Operation 1 5 52 Execution Time vs Number of Multiply Accumulates TMS320C25 5 55 Program Memory vs Number of Multiply Accumulates 5 56 An In Place DIT FFT With In Order Outputs and Bit Reversed Inputs 5 76 An In Place DIT FFT With In Order Inputs but Bit Reversed Outputs 5 76 Powerup Reset Circuit 6 3 Voltage on TMS320C25 Reset Pin 6 4 Crystal Oscillator Circuit 6 5 Magnitude of Impedance of Oscillator LC 6 6 Direct Interface of TBP38L165 35 to 5320 25
355. endix Title Attribute Reference next dma ind next 03B00h dma ind next dma ind next OCFOOh 12 4 14 4 4 1 1 1 Running Title Attribute Reference K 23 Running Title Attribute Reference OGEOGR shift ind shift next ARP 06800h dma ind shift next 06000h AR AR ind next 07000h constant shift 0D003h K 24 Appendix Title Attribute Reference Running Title Attribute Reference dma ind next 04 00 dma ind next 04700h dma ind next 04400h dma ind next 04500h dma ind next 04600h ind next ARP 07B00h dma ind next ARP 04100h 4 0 4 4 4 0 4 4 1 4 4 K 25 IMPORTANT NOTICE Texas Instruments reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current Tl warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent deems necessary to support this warr
356. er MIL STD 883C Method 1014 5 Per MIL STD 883C Method 2002 3 1500g 0 5 ms Condition B Per MIL STD 883C Method 2020 4 Per MIL STD 883C Method 2007 1 20g Condition A Per MIL STD 883C Method 2001 2 20 kg Condition D Y1 Plane min Per MIL STD 883C Method 1014 5 To data sheet limits Per MIL STD 883C Method 1014 5 Per MIL STD 750C Method 1014 5 Per MIL STD 883C Method 1010 5 65 to 150 C Condition C Per MIL STD 883C Method 1011 4 55 to 125 C Condition B Per MIL STD 883C Method 1004 4 Per MIL STD 883C Method 1014 5 To data sheet limits Thermal Mechanical Sequence Fine and gross leak Temperature cycle 10 cycles minimum Constant acceleration Fine and gross leak Electrical test Electrostatic discharge Solderability Solder heat Salt atmosphere Lead pull Lead integrity Per MIL STD 883C Method 1014 5 Per MIL STD 883C Method 1010 5 65 to 150 C Condition C Per MIL STD 883C Method 2001 2 30 kg Y1 Plane Per MIL STD 883C Method 1014 5 To data sheet limits Per MIL STD 883C Method 3015 Per MIL STD 883C Method 2003 3 Per MIL STD 750C Method 2031 10 sec Per MIL STD 883C Method 1009 4 Condition A 24 hrs min Per MIL STD 883C Method 2004 4 Condition A Per MIL STD 883C Method 2004 4 Condition B1 Quality and Reliability Reliability Stress Tests Electromigration Accelerated stress testing of con ductor patterns to ensure acceptable lifetime of power on operation
357. er that holds either an operand for the multiplier or a shift code for the scaling shifter 15 0 16 bit memory mapped timer counter for timing control 0 Stack Stack 15 0 A4x16o0r8 x 16 hardware stack used to store the PC during interrupts or calls The ACCL and data memory values may also be pushed onto and popped from the stack 8 11 Memory Organization 3 4 Memory Organization 3 4 4 Data Memory The 5320 2 provides a total of 544 16 bit words of on chip data RAM of which 288 words are always data memory and the remaining 256 words may be configured as either program or data memory The TMS320C26 provides a total of 1568 words of 16 bit on chip RAM divided into four separate bolcks BO B1 B2 and B3 The TMS320C25 also provides 4K words of maskable program ROM while the TMS320E25 provides 4K words of EPROM This sec tion explains memory management using the on chip data and program memory memory maps memory mapped registers auxiliary registers memory addressing modes and memory to memory moves The 544 words of on chip data RAM are divided into three separate blocks BO 1 and 2 as shown in Figure 3 4 Of the 544 words 256 words block BO are configurable as either data or program memory by instructions provided for that purpose 288 words blocks B1 and B2 are always data memory A data memory size of 544 words allows the TMS320C2x to handle a data array of 512 words 256 wor
358. es wem uem 11 1 Servo Control Disk Drive Applications Figure G 10 shows the interfacing of the TMS320C14 and the TLC32071 Figure G 10 5320 14 TLC32071 Interface D0 D7 CSCNTRL A2 CSAN im Address Decode Logic WE DEN RESET TMS320C14 TLC32071 For further information on these servo control products please call TI Linear Applications at 214 997 3772 G 14 Analog Interface Peripherals and Applications Modem Applications G 5 Modem Applications High speed modems 9 600 bps and above require a great deal of analog sig nal processing in addition to digital signal processing Designing both high speed capabilities and slower fall back modes poses significant engineering challenges offers a number of analog front end AFE circuits to support various high speed modem standards TLC32040 TLC32044 TLC32046 TLC32047 and TLC320AC01 analog interface circuits are especially suited for modem applications by the tegration of an input multiplexer switched capacitor filters high resolution 14 bit ADC and DAC a four mode serial port and control and timing logic These converters feature adjustable parameters such as filtering characteris tics sampling rates gain selection sin x x correction TLC32044 TLC32046 and TLC32047 only and phase
359. es a variety of devices that interface directly to the TMS320 DSPs in rapidly expanding applications Topic Page G 1 Multimedia Applications G 2 G 2 Telecommunications Applications G 5 Dedicated Speech Synthesis Applications G 10 G 4 Servo Control Disk Drive Applications G 12 G 5 Modem Analog Front End Applications G 15 G 6 Advanced Digital Electronics Applications for Consumers G 18 G 1 Multimedia App lications G 1 Multimedia Applications Multimedia integrates different media through a centralized computer These media can be visual or audio and can be input to or output from the central computer via anumber of technologies The technologies can be digital based or analog based such as audio or video tape recorders The integration and interaction of media enhances the transfer of information and can accommo date both analysis of problems and synthesis of solutions Figure 9 1 shows both the central role of the multimedia computer and the multimedia system s ability to integrate the various media to optimize informa Figure G 1 System Block Diagram Video Input tion flow and processing Operator Input Video Monitor Multimedia Computer Facsimile Modem Image Sensor Music Input MIDI
360. ese high impedance circuits During storage or handling the device leads should be shorted together or the device should be placed in conductive foam Ina circuit unused inputs should always be connected to an appropriated logic voltage level preferably either Vcc or ground Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic Discharge Sensitive ESDS Devices and Assemblies available from Texas Instruments recommended operating conditions Vcc Supply voltage 4 5 5 5 5 E VIH High level input voltage 3 50 15 00 FSX CLKIN CLKR CLKX VIL Low level input voltage All others 7 0 IOH High level output current 300 loL Low level output current 2 TA 125 Minimum operating free air tem 55 perature 1 Maximum operating case tem C perature electrical characteristics over specified free air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN UNIT VoH High level output voltage Vec MINIOH 5 3 V MAX ii 27 V V V A A A VOL Low level output voltage 0 MIN IOL E 32 Appendix Title Attribute Reference Running Title Attribute Reference High impedance state output leakage current Vcc MAX Input current VI Vss to Voc ETE Supply current LR Ide HOLD pu M E Output capacitance All typical values at Vcc
361. essors to allow for execution of redundant fail safe systems SYNC per mits instruction broadcasting between several processors and lock step execution after initial synchronization 6 35 Global Memory Figure 6 20 Global Memory Communication TMS320C2x TMS320C2x BR Arbitration BR Logic B B U U F F F F E E R R 5 5 Sync Program Generation Program Memory Logic Memory 6 36 Hardware Applications Interfacing Peripherals 6 5 Interfacing Peripherals Most DSP systems implement some amount of I O by using peripherals in addition to any memory included in the system This usually includes analog input and output which can be performed through the parallel and serial I O ports on the TMS320C2x When you access the external parallel I O ports the access to the data bus is multiplexed over the same pins as for a program data memory access The I O space is selected by the IS signal going active low and the address of the port is placed on address bits 0 Address bits A15 A4 are held low This section describes hardware interfaces to a TCM29C16 combo codec a TLC32040 analog interface circuit AIC a digital to analog D A converter and an analog to digital A D 6 5 1 Combo Codec Interface Some areas of speech telecommunications and many other applications re quire low cost analog to digital A D and digital to analog D A converters Combo codecs are most effective in serving DS
362. etup ime before STRB eee noe 10221 as S4 tw SL STRB low pulse duration no wait states see Note 4 20 5 20 20 5 ms tw SH STRB high pulse duration between consecutive cycles see Note 4 XN T DaawiemddUmetomSTRBNg ow a Loh NNNM ENDE CRIT UL UN tdis D Data bus three state after STRB high write NES Qa ns tamso MSC valid from CLKOUTI tof 0 oof ms timing requirements over recommended operating conditions see Note 1 Read data access time from address time read cycle see Notes 3 and 5 E 37 Running Title Attribute Reference tsu D R Data read setup time before STRB high 23 th D R Data read hold time from STRB high INT EMEN td SL R READY valid after STRB low no wait states Q 22 td C2H R READY valid after CLKOUT2 high th SL R READY hold time after STRB low no wait states th C2H R READY hold after CLKOUT high td M R READY valid after MSC valid 2Q 25t th M R READY hold time after MSC valid RS INT BIO AND XF TIMING switching characteristics over recommended operating conditions see Note 1 PARAMETER MIN UNIT td RS CLKOUT1 low to reset state entered _ CLKOUTI to IACK valid t 0 8 s td XF XF valid before falling edge of STRB Q 12 timing requirements over recommended operating conditions see Note 1 LLL MN MAX UNT
363. f DXR is not reloaded with new data every XINT every 8 or 16 CLKX cycles depending on FO the last value loaded will be trans mitted on DX continuously Note that this is different from the case with FSM 1 where DX is placed into a high impedance state if DXR is not reloaded before transmission of the last bit of the current word in XSR For example if byte C is not loaded into DXR as indicated in Figure 3 42 bits of byte B 1 8 will be retransmitted instead of bits of byte C as shown For receive operations DRR is loaded from RSR and an RINT is generated every 8 or 16 CLKR cycles depending on FO regardless of whether or not DRR has been read An overrun of DRR is also possible with FSM 1 if DRR is not read before the next RINT The only way to stop continuous transmission or reception once started when FSM 0 is either to stop CLKX or CLKR or to perform an SFSM set FSM instruction Continuous transmission without frame sync pulses is very useful in communi cating directly to telephone system PCM highways For ATT T1 and CCITT G711 712 lines FSX and FSR pulses are generated only every 24 or 32 bytes By counting the transmitted and received bytes in software after an initial FSX or FSR and performing SFSM and RFSM instructions as required the TMS320C25 can easily be made to communicate in these formats Architecture Serial Port Figure 3 42 Serial Port Transmit Continuous Operation FSM 0 AN ANRINLNG NS NC
364. f SAVE CONTEXT SAVE ON SUBROUTINE CALL OR INTERRUPT ASSUME AR7 IS THE STACK POINTER AND AR7 128 SAVE LARP gt ARB 7 gt ARP ART 128 MAR ART 127 SAVE THE STATUS REGISTERS SSTl 8 gt 127 ART 126 SST STO gt 126 ART 125 SAVE THE ACCUMULATOR SACH ACCH gt 125 ART 124 SACL ACCL gt 124 ART 123 SAVE THE REGISTER SPM 0 NO SHIFT ON PR OUTPUT SPH PRH gt 123 ART 122 SPL PRL 122 AR7 121 SAVE THE T REGISTER MPYK 1 PR TR SPL TR 121 ART 120 SAVE ALL EIGHT LEVELS OF THE HARDWARE STACK RPTK 7 POPD gt TOS 8 gt 120 ART 119 STACK 7 119 118 STACK 6 118 AR7 117 STACK 5 gt 117 ART 116 STACK 4 gt 116 115 STACK 3 gt 115 AR7 114 STACK 2 114 113 BOS 1 o 113 ART 112 SAVE AUXILIARY REGISTERS ARO THROUGH ARG SAR ARO gt 112 AR7 111 SAR AR1 ARL gt 111 110 SAR AR2 AR2 gt 110 ART 109 SAR AR3 109 ART 108 SAR AR4 gt 108 ART 107 SAR ARS ARS gt 107 ART 106 SAR AR6 AR6 gt 106 ART 105 SAVE IS COMPLETE 5 30 Software Applications Example 5 12 Context Restore TMS320C25 D
365. fast static RAM at a fixed address and slower dynamic RAM at mappable addresses You are is respon sible for deselecting target memory residing in the same address of the emula tor s fast static memory if this emulator memory is mapped in Note that the target should not drive the data bus on a read This fast static emulator sub stitution memory consists of 8K words of fast static RAM which can be individ ually mapped in as 4K words of program memory starting at address 0000 and 4K words of data memory starting at location 0000 In this case the target sys tem cannot drive the data bus even though DS or PS is active Although this emulator static RAM can operate with zero wait states you can model target wait states by using the target READY signal However this requires the target System to eventually respond with a valid READY high The emulator gener ates wait states until it does The slower dynamic RAM controls bus access through the DS or PS control signals The target system can drive the data bus when PS or IS is asserted Emulator logic assures that DS PS and IS are returned to their inactive state when the dynamic RAM substitution memory uses the data bus on reads Hardware Applications System Control Circuitry The dynamic RAM substitution memory always uses more than one clock to return data An access to address space mapped to the dynamic substitution memory is accompanied by the assertion of DS or PS and STRB When th
366. for each mode Direct Addressing Mode In the direct memory addressing mode the instruction word contains the lower seven bits of the data memory address dma This field is concatenated with the nine bits of the data memory page pointer DP register to form the full 16 bit data memory address Thus the DP register points to one of 512 pos sible 128 word data memory pages and the 7 bit address in the instruction points to the specific location within that data memory page The DP register is loaded through the LDP load data memory page pointer LDPK load data memory page pointer immediate or LST load status register STO instruc tions ae Note The data page pointer is not initialized by reset and is therefore undefined after powerup The TMS320C2x development tools however utilize default values for many parameters including the data page pointer Because of this programs that do not explicitly initialize the data page pointer may execute improperly depending on whether they are executed on a TMS320C2x device or by using a development tool Thus it is critical that all programs initialize the data page pointer in software ee Assembly Language Instructions Memory Addressing Modes Figure 4 1 illustrates how the 16 bit data address is formed Figure 4 1 Direct Addressing Block Diagram Data Bus 16 7 7 LSBs From Instruction Register IR Direct addressing can be used with all instructions exce
367. found performing NOPs for the remainder of the repeat loop The first method is used to normalize a 32 bit number and yields a 5 bit expo nent magnitude The second method is used to normalize a 16 bit number and yields a 4 bit exponent magnitude If the number requires only a small amount of normalization the first method may be preferable to the second This results because Example 1 runs only until normalization is complete Example 2 al ways executes all 15 cycles of the repeat loop Specifically Example 1 is more efficient if the number requires five or less shifts If the number requires six or more shifts Example 2 is more efficient 4 128 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example OR With Accumulator OR Direct label OR dma Indirect label OR ind next ARP 0 dma x 127 0 lt next ARP x 7 PC 1 PC 15 0 OR dma ACC 15 0 ACC 31 16 gt 31 16 Not affected by SXM EN 14 13 12 1 10 9 8 7 6 5 4 2 1 0 Direct 0 1 1 1 0 1 EE Data Memory Address Indirect 1 0 0 1 1 0 1 See Section 4 1 The low order bits of the accumulator are ORed with the contents of the ad dressed data memory location The high order bits of the accumulator are ORed with all zeros Therefore the upper half of the accumulator is unaffected by this instruction Cycle Timings for a Single Instruc
368. fting low order bits are zero filled High order bits are sign extended if SXM 1 and zeroed if SXM 0 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LAC DAT6 4 DP 8 or LAC 4 If current auxiliary register contains 1030 Before Instruction After Instruction Data Data 1030 1030 C 4 85 LACK Load Accumulator Immediate Short Syntax Operands Execution Encoding Description Words Cycles Example 4 86 abel LACK constant 0 constant lt 255 PC 1 gt PC 8 bit positive constant Not affected by SXM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 The 8 bit constant is loaded into the accumulator right justified The upper 24 bits of the accumulator are zeroed that is sign extension is suppressed 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable LACK 15h Before Instruction After Instruction Assembly Language Instructions Load Accumulator With Shift Specified by Register LACT Syntax Direct label LACT dma Indirect label LACT ind next ARP Operands 0 lt lt 127 0 lt next ARP lt 7 Execution PC 1 PC dma x 2T register 3 0 gt If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affected by SXM 14 13 12 11 10
369. fy AR ARP and ARP as specified 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the contents of the accumulator are greater than or equal to zero Otherwise control passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric ad dress 2 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 2 2 2 2 Cycle Timings for a Repeat Execution not repeatable BGEZ PRG217 217 is loaded into the program counter if the accumulator is greater than or equal to zero 4 49 BGZ Branch if Accumulator Greater Than Zero Syntax Operands Execution Encoding Description Words Cycles Example 4 50 label BGZ ind nextARP 0 lt pma lt 65536 lt next ARP x 7 If ACC 0 Then pma PC Else PC 2 gt PC Modify AR ARP and ARP as specified 14 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the con
370. g Control 3 67 3 9 8 Burst Mode 3 68 3 9 4 Continuous Operation Using Frame Sync Pulses TMS320C25 3 69 3 9 5 Continuous Operation Without Frame Sync Pulses TMS320C25 3 71 3 9 6 Initialization of Continuous Operation Without Frame Sync Pulses 3 73 3 10 Multiprocessing and Direct Memory Access 3 75 3 10 1 Synchronization 3 75 3 10 2 Global 2 3 76 3 10 3 The Hold Function 3 78 3 11 General Description of the TMS320C26 3 82 3 12 General Description of the TMS320C28 3 83 Assembly Language Instructions 4 1 4 1 Memory Addressing Modes 4 2 4 1 1 Direct Addressing Mode 4 2 4 1 2 Indirect Addressing 4 4 4 1 3 Immediate Addressing 4 8 42 nsti ctlon SC obtento utes 4 11 4 2 1 Symbols and Abbreviations 4 11 4
371. gh Byte LAC CHECK ADD WORD8L Accumulate Checksum ADD WORD8H 8 Accumulate Checksum SACL CHECK LAC WORD8H 8 Modify Program Data OR WORD8L High Byte Low Byt SACL 0 AR6 Store Block BO 1 3 BANZ LOW8L AR7 Last Word CHKRID CALL READ read checksum LSB AND MASKFF mask unused bit SACL WORD8L CALL READ read checksum MSB SACL WORD8H LAC WORD8H 8 OR WORD8L High Byte Low Byt CALL CHKSUM test checksum CONFIGURE BO amp AND THEN WAIT FOR FOR START SIGNAL BIO 0 TO JUMP TO PROGRAM BLOCK BIT INTER BCB2 Block Config Bit2 1 conf 3 all Prog Memory POINTO H BIT INTER BCB1 Block Config Bit1 1 conf 2 0 1 Prog Mem POINTO CONF 1 BO Prog Memory POINTO LAC INTER init Interrupts SACL IMR Interrupt Word CALL READ dummy read for synchro NEED2 SSXM Processor Initialization READ READS WSTBIT STOK half_len WIBIT BIT ZEROBT READP HIGHST READP2 CHKSUM CHKOK 5 20 PROG ARO branch to user prog BO LAC MODE BZ READP MODE MULTIPROCESSOR gt RS232 link LARK AR2 0 init byte value BIOZ STOK AR1 wait for start bit falling edge B WSTBIT E Note The following sequence uses a shift and decriment arangemen
372. guration control TC test control SXM sign extension mode XF external flag FO serial port format TXM transmit mode and the PM product regis ter shift mode ST1 on the TMS320C25 also contains status bits C carry HM hold mode and FSM frame synchronization mode The bits loaded into status register ST1 from the data memory word are as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T On the TMS320C26 bits 12 and 7 hold CONFO and CNF1 respectively see the CONF instruction for decoding Assembly Language Instructions Cycles Example 1 Example 2 Example 3 Load Status Register 5711 LST1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LARP 3 LSTI The data memory word addressed by the contents auxiliary register AR3 replaces the status bits of status register 5 1 and AR3 is decremented LST1 61h DP 0 Before Instruction After Instruction Data Data Memory 0580h Memory 0580h 97 97 STO OACOOh STO 0CO00h ST1 0581h ST1 0580h LARP AR4 ARA 3FEh 15 1 Before Instruction After Instruction AR4 3FEh AR4 3FDh Data Data Memory 4F90h Memory 4F90h 1022 1022 STO OFC04h STO 5004h ST1 0E780h ST1 4F90h 4 101 LST1 Load Status Register ST1 Example 4 LARP AR4 ARA 3FEh Loti L Before Instruction After Instruction AR4 3FEh AR4 3FDh Data Data Memory 6190h Memory 6190h 1022 1022 STO OF
373. h bss RSVRD1 0180h DATA PAGE 4 BLOCK B0 DATA MEMORY LABELS BO bss PROGR PROGL LOCATIONS FOR INTERNAL PROGRAM CODE bss COEFF COEFL LOCATIONS FOR COEFFICIENT MEMORY bss FREEO 0100h PROGL COEFL DATA PAGE 6 BLOCK B1 DATA MEMORY LABELS B1 bss 1 RESERVED FOR DATA VALUE OF 1 bss FILOUT 1 FILTER OUTPUT SIGNAL VALUE bss FILIN 1 FILTER INPUT SIGNAL VALUE bss SIG 13 bss SIGNAL 1 LAST SIGNAL DELAY VALUE end 5 40 Software Applications Memory Management Example 5 22 Program Execution From On Chip Memory TMS320C26 file onchip26 title ON CHIP RAM PROGRAM EXECUTION EXAMPLE FOR THE TMS320C26 width 96 option X PGMBO set OFAOOh BLKSIZ set 00200h BLOCKSIZE OF TMS320C26 RESET 1 ARP ARI BRANCHES FOR EXTERNAL OR INTERNAL INTERRUPTS FOLLOW HERE AT THE DESIGNATED LOCATIONS AS REQUIRED Space 32 S RESET
374. has a BITT instruction in which the bit code is specified in the T register Because the T register can easily be modified BITT may be used to test all bits of a data word if placed within a loop or to test a bit location determined by past processing Software Applications Fundamental Logical and Arithmetic Operations Example 5 23 Using BIT BBZ THIS ROUTINE USES THE BIT INSTRUCTION TO TEST THE CONDITION OF AN EXTERNAL MUX BIT 4 DETERMINES THE UTILITY OF THE REMAINING DATA IF ZERO A COUNTER IS INCREMENTED IF ONE ADDITIONAL PROCESSING OCCURS AND THE COUNTER IS CLEARED THE ROUTINE IS INVOKED WHENEVER A TIMER INTERRUPT OCCURS 55 STO SAVE STATUS REGISTER STO LDPK 0 LARP IN DAT PA8 READ IN VALUE BIT DAT OBh TEST BIT 4 BBZ INCR BRANCH AND INCREMENT IF POSITIVE LARK AR3 0 CLEAR THE COUNTER LST STO RELOAD THE STATUS REGISTER EINT ENABLE INTERRUPTS RE RETUR O INTERRUPTED ROUTINE INCR AR INCREMENT THE COUNTER LST STO RELOAD THE STATUS REGISTER EINT ENABLE INTERRUPTS RE RETUR O INTERRUPTED ROUTINE Example 5 24 Using
375. he accumulator upon saturation is 7FFFFFFFh positive or 80000000h negative If the OVM overflow mode status register bit is reset and an over flow occurs the overflowed results are loaded into the accumulator without modification Note that logical operations cannot result in overflow The TMS320C2x can execute a variety of branch instructions that depend on the status of the ALU and accumulator These instructions include the BV branch on overflow and BZ branch on accumulator equal to zero In addi tion the BACC branch to address in accumulator instruction provides the ability to branch to an address specified by the accumulator Bit test instruc tions BIT and BITT which do not affect the accumulator allow the testing of a specified bit of a word in data memory The accumulator on the TMS320C25 also has an associated carry bit that is set or reset depending on various operations within the device The carry bit allows more efficient computation of extended precision products and addi tions or subtractions It is also useful in overflow management The carry bit is affected by most arithmetic instructions as well as the shift and rotate instruc tions It is not affected by loading the accumulator logical operations or other such nonarithmetic or control instructions It is also not affected by the multiply MPY MPYK and MPYU instructions but is affected by the accumulation pro cess in the MAC and MACD instructions Examp
376. he program transfer the host transmits Software Applications Processor Initialization a precalculated checksum and the C26 returns the status on the XF line and port PAO The checksum status definitions are shown below In the RS232 mode the byte sequence is low to high XF 0 or PAO 00h indicates a checksum error XF 1 indicates a correct checksum SYNCHRONIZATION 1 RS232 transfer After loading the CHECKSUM the value previously transmitted in the configu ration word reconfigures the internal memory and interrupts The C26 then waits for a falling edge on the BIO pin before program control is passed to the first address of BO If a checksum error has occurred this allows the host to check the status and possibly reboot the system When BIO goes low program control is always passed to the first address of program block BO regardless of the checksum status Note XF is driven high by reset and remains high to indicate that a transfer is in progress A high level on XF also indicates that a checksum is cor rect If needed a host timeout can be used to determine if the status indicates a transfer is in progress or a correct checksum has been re ceived 5 1 1 3 Mode 3 External Memory EPROM Download If the BIO signal is found to be high 39 2d cycles after reset a test is made to determine if external global memory is present If this fails a serial download mode 2 is performed It is recomme
377. hm has been finalized the designer may submit the code to Texas Instruments for masking into the on chip program ROM At that time the TMS320 becomes a microcomputer that executes customized programs out of the on chip ROM Should the code need changing or upgrading the TMS320 may once again be used in the microprocessor mode This shortens the field upgrade time and avoids the possibility of inventory obsolescence Figure 1 illustrates the procedural flow for TMS320 masked parts When or dering there is a one time nonrefundable charge for mask tooling A minimum production order per year is required for any masked ROM device ROM codes will be deleted from the TI system one year after the last delivery A digital signal processor with the EPROM option is the solution for low volume production orders The EPROM option allows for form factor emulation Field upgrades and changes are possible with the EPROM option ROM Codes Figure 1 TMS320 ROM Code Flowchart Customer TMS320 Design Customer Submits TMS320 New Code Release Form Print Evaluation and Acceptance Form PEAF Purchase Order for Mask Charge Prototypes TMS320 Code Texas Instruments Responds Customer Code Input into System Code Sent Back to Customer for Verification Customer Approves Algorithm Customer Approves No Prototypes Minimum Production Order Required TMS320 Production
378. iability con trols and management include a product reliability monitor and final product release controls MOS memories utilizing high density active elements serve as leading indicators in wafer process integrity at TI MOS fabrication sites en hancing all MOS logic device yields and reliability Thousands of logic devices per month are randomly tested to ensure product reliability and excellence Quality and Reliability Reliability Stress Tests Table 1 lists the microprocessor and microcontroller reliability tests the duration of the test and sample size The following terms define or describe these tests Average Outgoing Quality FIT Failure in Time Operating lifetest Amount of defective product in a population usu ally expressed in terms of parts per million PPM Estimated field failure rate in number of failures per billion power on device hours 1000 FIT 0 1 failure per 1000 device hours Device dynamically exercised at a high ambient temperature usually 125 C to simulate field usage that would expose the device to a much lower ambient temperature such as 55 C Using a derived high temperature a 55 C ambient fail ure rate can be calculated High temperature storage Biased humidity Device exposed to 150 C unbiased condition Bond integrity is stressed in this environment Moisture and bias used to accelerate corrosion type failures in plastic packages Conditions must inclu
379. iary register is not equal to zero Otherwise control passes to the next instruction The current auxiliary register and ARP are also modified as speci fied The current auxiliary register is either incremented or decremented from zero when the branch is not taken Note that the AR modification defaults to decrement current AR by one when nothing is specified making it compat ible with the TMS320C1x The pma can be either a symbolic or a numeric ad dress 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 242p Cycle Timings for a Repeat Execution not repeatable Assembly Language Instructions Branch Auxiliary Register Not Zero BANZ Example 1 BANZ PRG35 Before Instruction After Instruction or PC 46h PC 48h Example 2 BANZ PRG64 Before Instruction After Instruction PC 117h PC 64h or PC 117h dis Ten Note BANZ is designed for loop control using the auxiliary registers as loop count ers Using 0 or 0 allows modification of the loop counter by a variable step size Care must be exercised when doing this however because the auxiliary registers behave as modulo 65536 counters and zero may be passed without being detected if ARO 1 1 4 45 BBNZ Branch on TC Bit Not Equal
380. ically reset Note that the OV bit does not function as a carry bit It is set only when the absolute value of a number is too large to be represented in the accumulator and it is not reset except by specific instructions Another method of overflow management which applies to multiply accumu late operations is the use of the right shifter of the product register The right shifter which operates with no cycle overhead allows up to 128 accumula tions without the possibility of an overflow The least significant six bits of the product are lost and the MSBs are filled with sign bits This feature is initiated by setting the PM bits of status register ST1 to 11 with the SPM or LST1 instruc tions The TMSS320C2x also has a right shift of the accumulator using the SFR instruction to scale down the accumulator when it nears overflow Software Applications 5 6 2 Scaling 5 6 3 Shifting Data Advanced Arithmetic Operations Scaling the data coming into the accumulator or already in the accumulator is useful in signal processing algorithms This is frequently necessary in adapta tion or other algorithms that must compute and apply correction factors or normalize intermediate results Scaling and normalizing are implemented on the TMS320C2x via right and left shifts in the accumulator and shifts of data on the incoming path to the accumulator Right and left shifts of the accumulator can be performed using the SFL and SFR instructions
381. ices 1 2 serial port 3 4 3 63 3 74 block diagram 3 65 burst mode 3 68 continuous mode 3 69 3 74 data receive register 3 10 data transmit register 3 10 framing 3 67 receive timing diagram 3 67 registers 3 63 shift register 3 11 timing 3 67 transmit and receive 3 65 3 67 3 68 3 70 transmit shift register 3 11 transmit timing diagram 3 66 servo control disk drive applications G 12 servo control related devices G 13 SFL 4 157 SFR 4 158 SFSM 4 159 shift modes 3 33 shifters 3 11 shifting data 5 47 5 50 SHM 4 160 Index 10 short immediate addressing 4 9 signal descriptions 2 4 2 7 single instruction loops 5 26 SMJ320C2x data sheets D 1 SNAP pulse programming F 8 flowchart F 10 sockets H 3 software stack 5 24 software stack expansion 5 24 SOVM 4 161 SPAC 4 162 speech development tools G 11 memories G 10 synthesis applications G 10 SPH 4 163 SPL 4 164 SPM 4 165 SQRA 4 166 5 57 SQRS 4 167 SST 4 168 SST1 4 170 SSXM 4 172 STO 3 11 3 49 ST1 3 11 3 49 stack 3 11 3 35 static RAMs 6 26 6 29 status registers 3 49 data processing 5 43 field definitions 3 50 temporary register 3 11 STC 4 173 STRB 2 5 STXM 4 174 SUB 4 175 SUBB 4 176 SUBC 4 177 fractional division 5 59 integer division 5 59 SUBH 4 179 SUBK 4 9 4 180 subroutines 5 22 example 5 22 SUBS 4 181 SUBT 4 182 supply voltage 2 6 support tool evolution TMDS K 2 TMDX K 2 supp
382. ied 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 d 1 1 0 01 1 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the contents of the accumulator are less than zero Otherwise control passes to the next instruction Note that no AR or ARP modification occurs when nothing is speci fied in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 34p 343p False Condition Destination anywhere 2 2 2 2 2 2 Cycle Timings for a Repeat Execution not repeatable BLZ PRG481 481 is loaded into the program counter if the accumulator is less than zero 4 63 BNC Branch Syntax Operands Execution Encoding Description Words Cycles Example 4 64 label BNC f ind next ARF 0 lt pma lt 65535 0 lt next ARP lt 7 If carry bit C 2 0 Then pma PC Else PC 2 PC Modify AR ARP and ARP as specified Affected by C 15 14 13 12 11 10 9 8 7 0 1 0 1 14 M 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory a
383. imes N is defined by an eight bit repeat counter RPTC which is loaded by the RPT or RPTK instructions The instruction immediately following is then executed and the RPTC is decremented until it reaches zero When you use the repeat feature the instruction being repeated is fetched only once As aresult many multicycle instructions become single cycle when repeated This is especially useful for I O instructions such as TBLR TBLW IN OUT or BLKD BLKP Since the instruction is fetched and internally latched the program bus can be used to fetch or write a second operand in parallel to operations using the data bus With the instruction latched for repeated execution the program counter can be loaded with a data address and incremented on succeeding executions to fetch data in successive memory locations As an example the MAC instruction fetches the multiplicand from program memory via the program bus Simultaneously with the program bus fetch the second multiplicand is fetched from data memory via the data bus In addition to these data fetches preparation is made for accesses in the following cycles by incrementing the program counter and by indexing the auxiliary register TBLR is another exam ple of an instruction that benefits from simultaneous transfers of data on both the program and data buses In this case data values from a table in program memory may be read and transferred to data memory When repeated the program overhead of
384. in the fixed data rate mode requires the following external clock signals A2 048 MHz clock to be used as the master clock and 8 kHz framing pulses to initialize the data transfers Both of these signals can be derived from the 40 96 MHz system clock with appropriate divider circuitry This is the primary justification for selecting 40 96 MHz as the system clock frequency The clock divider circuit consists of a 74AS74 D type flip flop a 74HC390 decade counter and 74AS869 8 bit up down counter The hardware connections between these devices are shown in Figure 6 21 To generate the 2 048 MHz master clock for the combo codec a division by 20 of the 40 96 MHz system clock is required The 74HC390 contains on chip two divide by 2 and two divide by 5 counters Because the 74HC390 cannot be clocked with frequencies above approximately 27 MHz a 74AS74 config ured as a divide by 2 of the 40 96 2 clock is used The 74AS869 is configured to generate the 8 2 clock pulse the ripple carry output is 2 048 MHz 256 8 kHz This pulse is used by the TMS320C25 and codec as a framing pulse to initiate data transfers 6 39 Interfacing Peripherals 6 5 2 AIC Interface 6 40 The level of the analog input signal is controlled by using the 072 opamp connected in the inverting configuration see Figure 6 21 Using the 500 kQ potentiometer the gain of this circuit can be varied from 0 to 5 The output of the 0 01 uF coupli
385. ines whether there is an external EPROM in glob al memory For more information refer to subsection 5 1 1 3 The serial link is RS232 standard using TTL levels at the BIO and XF pins In this case the BIO pin receives the data from the host via an RS232 line receiv er and the XF pin sends status back to the host via a line driver The receive levels and data format are shown below Figure 5 5 RS232 Connection to the TMS320C26 RS232 DB25 5320 26 1 4 75189 2 TX v 1 4 75188 3 RX 7 GND gt C26 BIO 85232 TRANSMIT DATA Stop Bits TTL logic high 1 Start Bit TTL logic low 0 Data Bits MSB received first 2 Bits Bit D7 Processor Initialization C26 XF PIN RS232 RECEIVE DATA RX On reset XF is driven high indicating that a transfer has been initiated If the download is not successful and the checksum fails XF is driven low indicating a failure The host should wait until this time to poll the checksum verification status The levels are given below Logic high 1 Transmission in progress or checksum valid Logic low 0 Checksum error RS232 line levels are not TTL compatible RS232 line drivers and receivers such as the Texas Instruments 75188 and 75189 must be used to interface to the RS232 level Example 5 4 RS232 Transfer Protocol BIO high at reset signals either serial or EPROM load EPROM Global and normal data space is checked for an E
386. ing MAC 5 54 using SQRA 5 57 overflow management 5 46 scaling 5 47 shifting data 5 47 5 50 bit reversed carry addition 5 48 FFT bit reversals 5 48 other applications 5 49 ARP 3 9 assembly language instructions 4 1 auxiliary register arithmetic unit 3 9 auxiliary registers 3 9 3 22 3 25 bus 3 9 pointer 3 9 pointer buffer 3 9 Index 2 B 4 42 BACC 4 43 BANZ 4 44 BBNZ 4 46 5 45 BBZ 4 47 5 45 BC 4 48 BGEZ 4 49 BGZ 4 50 BIO 2 5 4 56 BIOZ 4 51 BIT 4 52 5 44 5 45 bit manipulation 5 44 bit reversed BR addressing 5 77 BITT 4 54 5 45 BLEZ 4 56 BLKD 3 27 4 57 5 33 BLKP 4 60 5 33 block BO 5 38 block diagram C26 3 8 C2x 3 7 block moves 3 27 5 33 BLZ 4 63 BNC 4 64 BNV 4 65 BNZ 4 66 bootloader 5 6 5 21 configuration words BAUD DETECT 5 13 CHECKSUM 5 10 5 14 INTERRUPT 5 9 5 14 PROGRAM LENGTH 5 9 5 14 PROGRAM WORD 5 10 5 14 STATUS 5 9 5 13 SYNCHRONIZATION 5 10 5 15 external memory EPROM download 5 15 5 21 byte ordering 5 16 parallel download 5 6 5 10 16 bit transfer sequence 5 8 8 bit transfer sequence 5 8 handshake example 5 7 transfer protocol 5 7 configuration words 5 9 5 13 5 15 program length 5 9 bootloader continued 5 6 5 21 serial download 5 11 5 15 program length 5 14 RS232 serial link 5 11 RS232 transfer protocol 5 12 RS232 transfer sequence 5 13 software listing 5 17 5 21 types of d
387. ing inter nal data memory or implementing additional RAM program memory Static RAM can be used as data memory to extend the TMS320C2x 544 word inter nal RAM When used as program memory object code can be downloaded into the RAM and executed In the first case the static RAM is mapped into the data space while in the second case it is mapped into the program space 6 26 Hardware Applications Interfacing Memories In cases where RAMs of different speeds are used separate schemes for ad dress decoding and READY generation can be used to meet READY timing requirements in a manner similar to that used for the PROM interface de scribed in subsection 6 2 1 RAMs with similar access times may then be grouped together in one segment of memory The static RAM for this interface is the Cypress Semiconductor CY7C169 25 4K x 4 bit static RAM This RAM has 25 ns access time from address tava and a 15 ns access time from chip enable ta cg Note that these access times are fast enough so that a wait state generator is not required for this interface If however RAMs that require wait states are used in the system the wait state generator described in subsection 6 2 2 can be used The design shown in Figure 6 16 utilizes an approach similar to the one de scribed in subsections 6 2 1 and 6 2 3 that is one address decoding scheme is used to generate READY and a second address decoding scheme enables the static RAM In this design RAMs with
388. ings for a Repeat Execution not repeatable TRAP Control is passed to program memory location 30 PC 1 is pushed on to the stack Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Exclusive OR with Accumulator X OR Direct label XOR dma Indirect label XOR _ ind next ARP 0 x lt 127 0 x next ARP lt 7 PC 1 PC 15 0 XOR dma gt 15 0 31 16 ACC 31 16 Not affected by SXM 5 1 7 6 5 4 3 2 1 0 1 4 13 12 11 10 9 8 Direct 0 1 1 1 0 0 Data Memory Address Indirect 0 1 0 0 1 100 See Section 4 1 The low half of the accumulator is exclusive ORed with the contents of the ad dressed data memory location The upper half of the accumulator is not af fected by this instruction Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution XOR DAT127 DP 511 or XOR If current auxiliary register contains 65535 Before Instruction After Instruction Data Data Memory OFOFOh Memory OFOFOh 65535 65535 ACC 12345678h ACC 1234A688h 4 189 XORK XOR Immediate with Accumulator with Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 190 label XORK constant shift 16 bit constant 0 lt shift lt 15 defaults to 0 PC 2 gt PC
389. inherent reliability of these prototype units cannot be expressly de fined and a release stating Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the device at the convenience of Texas Instruments Contact the nearest TI Field Sales Office for more information on procedures leadtimes and cost ROM Codes Appendix J Quality and Reliability The quality and reliability performance of Texas Instruments Microprocessor and Microcontroller Products which include the five generations of TMS320 digital signal processors relies on feedback from Our customers Our total manufacturing operation from front end wafer fabrication to final shipping inspection Product quality and reliability monitoring Our customer s perception of quality must be the governing criterion for judg ing performance This concept is the basis for Texas Instruments Corporate Quality Policy which is as follows For every product or service we offer we shall define the requirements that solve the customer s problems and we shall conform to those requirements without exception Texas Instruments offers a leadership reliability qualification system based on years of experience with leading edge memory technology as well as years of research in customer requirements Quality and reliability programs at TI are therefore based on customer input and internal information to
390. ining with the TMS320 development tools When technical questions arise regarding the TMS320 family contact the Texas Instruments TMS320 Hotline at 713 274 2320 Or keep informed on the latest and third party development support tools by accessing the DSP Bulletin Board Service BBS at 713 274 2323 The BBS serves 2400 1200 and 300 bps modems Also TMS320 application source code may be downloaded from the BBS Table 3 gives a complete list of SMJ320C26 software and hardware develop ment tools Appendix Title Attribute Reference Running Title Attribute Reference Table 3 Software and Hardware Support MACRO ASSEMBLER LINKER HOST COMPUTER DEC VAX IBM PC VAX SUN 3 HOST COMPUTER DEC VAX IBM PC VAX SUN 3 HOST COMPUTER DEC VAX IBM PC MODEL XDS 22 HOST COMPUTER IBM PC IBM PC t Includes assembler linker OPERATING SYSTEMS VMS MS PS DOS ULTRIX UNIX C COMPILER AND MACRO ASSEMBLER LINKER OPERATING SYSTEMS VMS MS PC DOS ULTRIX UNIX SIMULATOR OPERATING SYSTEMS VMS MS PC DOS EMULATOR POWER SUPPLY INCLUDED SOFTWARE DEVELOPMENT SYSTEM ON PC OPERATING SYSTEMS MS PC DOS MS PC DOS PART NUMBER TMDS3242250 0 8 TMDS3242850 0 2 TMDS3242260 0 8 TMDS3242550 0 8 PART NUMBER TMDS3242255 0 8 TMDS3242855 0 2 TMDS3242265 0 8 TMDS3242555 0 8 PART NUMBER TMDS3242251 0 8 TMDS3242851 0 2 PART NUMBER TMDS3262292 PART NU
391. instructions fetched from external program memory 3 59 Interrupts 3 8 3 8 1 Interrupts The TMS320C2x has three external maskable user interrupts INT2 INTO available for external devices that interrupt the processor Internal interrupts are generated by the serial port RINT and XINT by the timer TINT and by the software interrupt TRAP instruction Interrupts are prioritized with reset RS having the highest priority and the serial port transmit interrupt XINT having the lowest priority Interrupt Operation This subsection explains details interrupt organization and management Vec tor locations and priorities for all internal and external interrupts are shown in Table 3 7 The TRAP instruction used for software interrupts is not prioritized but is included here because it has its own vector location Each interrupt ad dress has been spaced apart by two locations so that branch instructions can be accommodated in those locations if desired Table 3 7 Interrupt Locations and Priorities 3 60 Interrupt Memory Location Priority MU External reset signal External user interrupt 0 External user interrupt 1 External user interrupt 2 Reserved locations Internal timer interrupt Serial port receive interrupt Serial port transmit interrupt TRAP instruction address When an interrupt occurs it is stored in the 6 bit interrupt flag register IFR This register is set by the external user interr
392. io DAC digital 32 37 8 Ux 557013 4 filter 16 18 44 1 48 kHz Digital audio Table H 2 Switched Capacitor Filter ICs Device Function 500 mW es es No TLC04 14 Low pass Butterworth filter ow For application assistance or additional information please call Linear Applications at 214 997 3772 TLC2470 Differential audio filter amplifier TLC2471 Differential audio filter amplifier CLK 50 TLC10 20 General purpose dual filter CLK 100 G 4 Analog Interface Peripherals and Applications Telecommunications Applications G 2 Telecommunications Applications The Tl linear product line focuses on three primary telecommunications appli cation areas subscriber instruments telephones modems etc central of fice line card products and personal communications Subscriber instruments include the TCM508x DTMF tone encoder family the TCM150x tone ringer family the TCM1520 ring detector and the TCM3105 FSK modem Central of fice line card products include the TCM29Cxx combo combined PCM filter plus codec family the TCM420x subscriber line control circuit family and the TCM1030 60 line card transient protector Personal communication PCN and cellular products include the TCM320AC3x family of 5 volt voice band au dio processors VBAP continues to develop new telecom integrated circuits such as a high perfor mance 3 volt combo family for personal communications applications and
393. iolet light Data is presented in parallel eight bits from pins D7 DO of the TMS320E25 to pins 08 01 of the TMS27C64 Once addresses and data are stable PGM is pulsed The pro gramming mode is achieved when Vpp 12 5 V PGM Vj Vcc 6 0 V G Vip and E Vj More than one 5320 25 can be programmed if these devices are connected in parallel with each other Locations can be pro grammed in any order FAST programming uses two types of programming pulses prime and final The length of the prime pulse is 1 ms After each prime pulse the byte being programmed is verified If correct data is read the final programming pulse is applied if correct data is not read an additional 1 ms prime pulse is applied upto a maximum of 25 times The final programming pulse is 3x times the num ber of prime programming pulses applied This sequence of programming and verifying is performed at Vcc 6 0 V and Vpp 12 5 V When the full FAST programming routine has been completed all bits are verified with Voc Vpp 5V F 7 Programming and Verification F 2 3 SNAP Pulse Programming The EPROM can be programmed by using the SNAP pulse programming algorithm as illustrated in the flowchart of Figure 6 programming time is greatly reduced to a nominal duration of one second Actual programming time varies as a function of the programmer that is being used Data is presented in parallel eight bits on pins Q8 through Q1 Once addresses
394. ion F 4 wiring diagram F 5 EPROMs 6 22 6 26 EVM K 1 EXAMPLE 4 19 extended precision arithmetic 5 62 5 67 addition 5 64 multiplication 5 66 subtraction 5 65 external memory interface 3 54 3 58 clock timing 3 56 pins 3 56 memory combinations 3 54 external program data access 3 47 fast Fourier transforms FFT 5 75 FAST programming F 7 flowchart F 9 FFT 5 81 FFT macros 5 79 FFT requirements 5 81 filtering 5 70 FIR filters 5 70 floating point arithmetic 5 60 denormalization 5 61 using LACT 5 61 using NORM 5 61 floating point multiply C25 5 61 FORT 4 82 Fourier transforms 5 75 framing control 3 67 FSR 2 7 FSX 2 7 functional block diagram 3 6 3 8 gates J 5 global memory 3 76 6 35 access timing 3 77 communication 6 36 configurations 3 77 global memory allocation register GREG 3 77 global register 3 9 graphics and image processing 6 50 GREG 3 9 3 77 ground pin 2 6 hardware applications 6 1 direct memory access DMA 6 32 6 34 global memory 6 35 interfacing memories 6 11 6 30 interfacing peripherals 6 37 6 47 system applications 6 48 6 52 Harvard architecture 3 2 HOLD 2 5 3 46 3 78 6 9 hold function 3 78 hold operation 3 46 hold timing 3 80 HOLDA 2 5 3 46 3 78 6 9 hotline ix y o addressing 6 46 pins 3 56 ports 6 46 processor communication 6 47 IACK 2 5 IDLE 4 83 IIR filters 5 70 Index immediate addressing 4
395. ip Block B2 Page 0 Pages 1 3 On Chip Block BO Pages 4 7 On Chip Block B1 Pages 8 11 On Chip Block B3 Pages 12 15 Pages 16 511 Data On Chip Memory Mapped Registers On Chip Block B2 Does Not Exist On Chip Block B1 Page 0 Pages 1 3 Pages 4 7 Pages 8 11 On Chip Block B3 Pages 12 15 Pages 16 511 Architecture Memory Organization Figure 3 9 TMS320C26 Memory Maps continued Program Program Data 0000h 0000h Interrupts Interrupts On Chip and Reserved and Reserved Memory Mapped 001Fh External 00FFh Bootload ROM Registers 0020h 0100h Reserved Page 0 eserve OFFFh On Chip 1000h Block B2 External Reserved Pages 1 3 External Pages 4 7 F9FFh FAI F9FFh AOON On Chip et Pages 8 11 Block BO On Chip EBEER FBFFh Block BO FC00h On Chi On Chi FCO0h i n Chip Block Bi On Chip 12 15 FDFFh FDFFh mE 00 00 External External External Pages 16 511 FFFFh FFFFh If MP MC 1 If MP MC 0 Microprocessor Mode Microcomputer Mode c Memory Maps After a CONF 2 Instruction Program Program Data 0000h 0000h Interrupts Interrupts On Chip and Reserved and Reserved Memory Mapped Registers 001Fh External Bootload ROM 0005h g 0020h 0006h Page 0 R Reserved eserved 005Fh 0060h On Chip 007Fh Block B2 External External 0080h Reserved Pages 1 3 01
396. ired Better fidelity translates into lower noise and distortion in the output signal The TMS57013DW 57014DW 1 bit digital to analog converters DAC clude an 8 times over sampling digital filter designed for digital audio systems such as CDPs DATs CDls LDPs digital amplifiers car stereos and BS tun ers They are also suitable for all systems that include digital sound processing like TVs VCRs musical instruments NICAM systems multimedia etc The converters have dual channels so that the right and left stereo signals can be transformed into analog signals with only one chip There are some func tions that allow the customers to select the conditions according to their appli cations such as muting attenuation de emphasis and zero data detection These functions are controlled by external 16 bit serial data from a controller like a microcomputer The TMS5703DW 57014DW adopt 129 tap FIR filter and third order A mod ulation to get 75 dB stop band attenuation and 96 dB SNR The output is PWM wave which facilitates analog signal through a low pass filter Table H 10 lists TI products for analog interfacing to digital systems Table H 10 Audio Video Analog Digital Interface Devices nee Bits Speed Channa Dual audio DAC digital filter TMS57013 4 16 18 32 37 8 44 1 48 kHz Analog interface TLC32071 A D 2 us D A 15 us 8 8 D TLC1550 10 Serial Parallel Parallel Parallel Parallel Tripl
397. is capable of allocating global data memory space and communicating with that space via the BR bus request and READY control signals Global memory is memory shared by more than one processor therefore ac cess to it must be arbitrated When using global memory the processor s ad dress space is divided into local and global sections The local section is used by the processor to perform its individual function and the global section is used to communicate with other processors A memory mapped global memory allocation register GREG specifies part of the TMS320C2x s data memory as global external memory GREG which is memory mapped at data memory address location 5 is an eight bit register connected to the eight LSBs of the internal D bus The upper eight bits of loca tion 5 are nonexistent and read as 1s 3 77 Multiprocessing and Direct Memory Access DMA The contents of GREG determine the size of the global memory space The legal values of GREG and corresponding global memory spaces are shown in Table 3 9 Note that values other than those listed in the table lead to frag mented memory maps Table 3 9 Global Data Memory Configurations GREG Value 000000XX Local Memory Range Words Range Global Memory Words 10000000 11000000 11100000 11110000 11111000 11111100 11111110 117111111 Q C CO 9 C303 225 OOo OOo
398. is implemented 2 Y n H k X n k where the H values stay the same and the X values are shifted each time the microprocessor performs one of the following series of multiplications similar to operations performed in FIR filters First Series Y 2 HO X2 H1 X1 H2 X0 Second Series 3 HO X3 H1 X2 H2 X1 Third Series Y 4 HO X4 H1 X3 H2 The MACD instruction which combines accumulate and multiply operations with a data move is tailored to the type of calculation shown in the summation equation above In order to use MACD the H values have been stored in block BO and configured as program RAM the X values have been read into block B1 of data RAM as shown in Figure 5 10 5 51 Advanced Arithmetic Operations Figure 5 10 MACD Operation Program Block BO OFFOOh OFFO1h OFFO2h Coefficients Data Block B1 Samples Also in Example 5 28 the summation in the above equation is performed in the reverse order that is from 2 to 0 because of the operation of the data move function This results in the oldest X value being used and discarded first Ifthe MACD instruction is replaced with the following two instructions then the MAC instruction can be utilized with the same results MAC DMOV In cases where many more than three MACD instructions are required the RPT or RPTK instructions may be used with MACD yielding the same com
399. ister TR The second operand is moved by the multiply instruction to the multiplier which then produces the productin the P register PR Before another multiply can be performed the contents of the PR must be moved to the accumulator A single multiply program is shown in Example 5 29 Pipe lining multiplies and PR moves makes it possible to perfom most multiply op erations in a single cycle common operation in DSP algorithms is the summation of products The MAC instruction normally performed in multiple cycles adds the contents of the PR to the accumulator and then simultaneously reads two values and mul tiplies them When you use the MAC instruction a data memory value is multi plied by a program memory value One of the operands can come from block B1 or B2 in on chip data memory while the other operand may come from block BO Block BO must be configured as program memory when it supplies the se cond operand Pipelining of the MAC instruction with a repeat instruction re sults in an execution time for each succeeding multiply and accumulate op eration of only one cycle THIS ROUTINE MULTIPLIES TWO VALUES IN DATA MEMORY LOCATIONS 200h AND 201h WITH HE RESULT STORED IN 202h AND 203h AR1 200h POINT AT BLOCK BO LARP 1 EP GET FIRST VALUE 200h MPY Wu ULTIPLY BY VALUE AT 2011 PAC PUT RESULT IN ACCUMULATOR SACL EF STORE LOW WOR
400. it precision operations This allows compatibility with TMS320C1x code to be maintained Note that the PM right shift is always sign extended regardless of the state of SXM The four least significant bits of the T register TR also define a variable shift through the scaling shifter for the LACT ADDT SUBT load add to subtract from accumulator with shift specified by the TR instructions These instruc tions are useful in floating point arithmetic where a number needs to be de normalized that is floating point to fixed point conversion The BITT bit test instruction allows testing of a single bit of a word in data memory based on the value contained in the four LSBs of the TR Architecture System Control 3 6 System Control System control on the TMS320C2x is supported by the program counter hard ware stack PC related hardware the external reset signal interrupts see Section NO TAG the status registers the on chip timer and the repeat count er The following sections describe the function of each of these components in system control and pipeline operation 3 6 1 Program Counter and Stack 5320 2 contains a 16 bit program counter PC and a hardware stack of eight locations for PC storage see Figure 3 15 The program count er addresses internal and external program memory in fetching instructions The stack is used during interrupts and subroutines Figure 3 15 Program Counter Stack and Related Ha
401. k OFFh Clear Checksum and load Mask sacl MASKFF 7 sach CHECK lark AR1 0 Load 1 1 words last accum call Test Loadl1 Test GLOBAL EPROM must return 0 5 17 Processor Initialization 5 18 READ FUNCTIONAL MODE 36 2d CYCLES AFTER RESET 0 COPROCESSOR PARALLEL I O LOAD BIO 1 MULTIPROCESSOR SERIAL MODE OR BYTE WIDE EPROM LOAD lt NEW bioz COPRO1 BIO low COPROCESSOR bnz MULTI Zero indicates gt 55 lark AR1 0 if pass test NORMAL data space call Test Load2 E bz MULTI Zero indicates B gt FAIL call Full_Load OK to load EPROM Cont F3 BO B1 amp as program NOP NOP adds extra latency B NEED2 Double B for CONF 3 latency MULTI MULTIPROCESSOR SERIAL ODE BIO INPUT WARNING First word must be 1 ONE to synchronize low period Treated as a dummy word Not used lark AR1 0 init bitlen counter LACK MODE 1 MULTIPROCESSOR UART AUTOBO bioz 5 wait for start bit b AUTOBO H STBIT BIOZ STBI T gt Bit length 3 AR0 cycles SAR AR1 BITLEN LARK AR2 9 wait for 8 bits 2 stop bit SACL MODE MODE 1 MULTIPROCESSOR AUTOB2 LAR AR1 BITLEN BANZ 5 wait
402. l as all control signals PS DS IS R W STRB in the high imped ance state The serial port output pins DX and FSX are not affected by HOLD Signaling between the external processor and the TMS320C2x can be per formed by using interrupts The timing for the HOLD and HOLDA signals is shown in Figure 3 48 HOLD has the same setup time as READY and is sampled at the beginning of quar ter phase 3 If the setup time is met it takes three machine cycles before the buses and control signals go to the high impedance state Note that unlike the external interrupts INT2 INTO HOLD is not a latched input The external device must keep HOLD low until it receives a HOLDA from the TMS320C2x If the TMS320C2x is in the middle of a multicycle instruction it will finish the instruction before entering the hold state After the instruction is completed the buses are placed in the high impedance state This also applies to instruc tions that become multicycle due to insertion of wait states or to the use of RPT RPTK instructions After HOLD is deasserted program execution resumes from the same point at which it was halted HOLDA is removed synchronously with HOLD as shown in Figure 3 48 If the setup time is met two machine cycles are required before the buses and control signals become valid HOLD is not treated as an interrupt If the TMS320C2x was executing the IDLE instruction before entering the hold
403. label ZALH dma Indirect label ZALH ind next ARP Operands 0 lt dma 3127 0 next ARP x 7 Execution PC 1 PC 0 ACC 15 0 dma ACC 31 16 Encoding 15 14 1 7 6 5 4 3 2 1 0 0 3 12 11 10 9 8 Direct 001 0 000 Data Memory Address Indirect 0 1 0 0 0 0 0 0 See Section 4 1 Description ZALH loads a data memory value into the high order half of the accumulator The low order bits of the accumulator are zeroed ZALH is useful for 32 bit arithmetic operations Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example ZALH DAT3 DP 32 Or ZALH If current auxiliary register contains 4099 Before Instruction After Instruction Data Data Memory 3F01h Memory 3F01h 4099 4099 ACC 77FFFFh ACC 3F010000h 4 192 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Zero Low Accumulator Load High Accumulator with Rounding ZALR Direct label ZALR Indirect label ZALR ind next ARP 0 dma x127 0 lt next ARP lt 7 PC 1 PC 8000h ACC 15 0 dma gt ACC 31 16 15 14 13 1 7 6 5 4 3 2 od 0 2 ld 10 9 8 Direct 9 1 1 1 o 1 1 E Data Memory Address Indirect 1 1 1 1 01 1 See Section 4 1 The ZALR instruction loads a data memory value into the high order half of the accumulator and rounds
404. label TBLW ind next ARP Operands lt lt 127 0 next ARP lt 7 Execution PC 1 5 PC PFC 2 MCS ACC 15 0 gt If repeat counter z 0 Then gt pma addressed PFC Modify AR ARP and ARP as specified 1 PFC repeat counter 1 repeat counter Else dma pma addressed by PFC Modify AR ARP and ARP as specified MCS 5 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 NND 0 0 1 Data Memory Address Indirect 1 0 1 1 0 0 1 See Section 4 1 Description The TBLW instruction transfers a word in data memory to program memory The data memory address is specified by the instruction and the program memory address is specified by the lower 16 bits of the accumulator A read from data memory is followed by a write to program memory to complete the instruction In the repeat mode TBLW effectively becomes a single cycle instruction and the program counter that contains the ACCL is incremented once each cycle If the MP MC on the TMS320C25 is low at the time of execution of this instruction and the program memory address used is less than 4096 an on chip ROM location will be addressed but not written to Words 4 186 Assembly Language Instructions Table Write TBLW Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Table in on chip RAM 2 34d 4 d p Table in on
405. lag is set to logic one 4 173 STXM Set Serial Port Transmit Mode Syntax Operands Execution Encoding Description Words Cycles Example 4 174 label STXM None PC 1 PC 1 status bit in status register ST1 Affects TXM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 The STXM instruction sets the TXM status bit to logic 1 which configures the serial port transmit section to a mode where the FSX pin behaves as an output A pulse is produced on the FSX pin each time the DXR register is loaded inter nally The transmission is initiated by the negative edge ofthis pulse TXM may also be loaded by the LST1 and RTXM instructions If the FSM status bit is a logic zero and serial port operation has already started the FSX pin will be driv en low if 1 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution STXM is set configuring FSX as an output Assembly Language Instructions Subtract from Accumulator with Shift SUB Syntax Direct label SUB shift Indirect abel SUB ind shift next ARP Operands 0 lt 127 0 next ARP lt 7 0 lt shift lt 15 defaults to 0 Execution PC 1 PC ACC dma x 2shift gt ACC If SXM 1 Then dma is sign extended If SXM 0 Then dma is not sign extended Affects OV affected b
406. lator k Words Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 109 LTS Load T Register and Subtract Previous Product Example 4 110 or 5 DAT36 Data Memory 804 ACC 7 DP lt 63 P z 0 If current auxiliary register contains 804 Before Instruction 62h h 5 o C After Instruction Memory 62h 62h OFFFFFFF6h Assembly Language Instructions Syntax Operands Execution Encoding Description Multiply and Accumulate MAC Direct label dma Indirect label MAC pma ind next ARP 0 lt pma lt 65535 0 dma x127 0 x next ARP lt 7 TMS320C25 PC 2 PC PFC gt MCS pma gt If repeat counter 0 Then ACC shifted P register ACC dma gt T register dma x addressed by PFC register Modify AR ARP and ARP as specified 1 gt PFC repeat counter 1 repeat counter Else ACC shifted P register dma gt T register dma x addressed by PFC register Modify AR ARP and ARP as specified MCS 5 PFC Affects C and OV affected by OVM and PM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0o 14 0 1 1 1 0 1 Data Memory Address Program Memory Address 0 1 0 1 1 1 0 1 See Section 4 1 Program Memor
407. lator OR with accumulator OR immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift Store low accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract Subtract from high accumulator Subtract from accumulator short immediate Subtract from low accumulator with sign extension suppressed Subtract from accumulator with shift specified by T register Exclusive OR with accumulator Exclusive OR immediate with accumulator with shift Zero accumulator Zero low accumulator and load high accumulator Zero low accumulator and load high accumulator with rounding Zero accumulator and load low accumulator with sign extension suppressed AOR OUD R UO UR HJ ES OR Re Og UO o DJ 4 14 Assembly Language Instructions Instruction Set Table 4 4 Instruction Set Summary Continued AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS Mnemonic and Description Words 16 Bit Opcode MSB LSB Add to auxiliary register short immediate Compare auxiliary register with auxiliary register ARO Load auxiliary regis
408. les of carry bit operation are shown in Figure 3 14 Figure 3 14 Examples of TMS320C25 Carry Bit Operation MSB LSB MSB LSB X FF F ACC X 0000 0 0 0 0 1 1 1 0000 0000 0 FPR SE X 8000 0000 1 0 1 OVM 0 0 87 40 10 00 0000 1 T oR oe FF F 1 0000 0 0 0 0 0 F F F ACC 0 ADD 0 SUBB Instruction Instruction 0 0000 0001 1 ie oe ce ol FF FE 3 31 Central Arithmetic Logic Unit CALU The value added to or subtracted from the accumulator shown in the exam ples of Figure 3 14 may come from either the input scaling shifter or the shift er at the output of the P register The carry bit is set if the result of an addition or accumulation process generates a carry it is reset to zero if the result of a subtraction generates a borrow Otherwise it is reset after an addition or set after a subtraction The ADDC add to accumulator with carry and SUBB subtract from accumu lator with borrow instructions provided on the TMS320C25 use the previous value of carry in their addition subtraction operation see these instructions in Chapter 4 for more detailed information The one exception to operation of the carry bit as shown in Figure 3 14 is in the use of the ADDH add to high accumulator and SUBH subtract from high accumulator instructions The ADDH instruction can set the carry bit only if
409. lt Opcode gt 11010 lt Y gt 0 AR ARP ARO AR ARP lt Opcode gt 1 1011 Y gt AR ARP ARO AR ARP Y 5 RP lt Opcode 21 11 00 Y gt EM AR ARP ARO AR ARP lt Opcode 511101 Y gt AR ARP ARO AR ARP Y gt lt gt 1 1110 Y gt gt 111106Y gt BRO AR ARP rcARO AR ARP lt Opcode 51 111 1 Yo BRO Y AR ARP rcARO gt Y gt AR The CMPR compare auxiliary register with ARO and BBZ BBNZ branch if TC bit equal not equal to zero instructions facilitate conditional branches based on comparisons between the contents of ARO and the contents of AR ARP The auxiliary registers may also be used for temporary storage via the load and store auxiliary register instructions LAR and SAR respectively 4 7 Memory Addressing Modes 4 1 3 4 8 The following examples illustrate the indirect addressing format Example 1 ADD 8 Add to the accumulator the contents of the data memory address defined by the contents of the current auxiliary register This data is left shifted 8 bits before being added The cur rent auxiliary register is autoincremented by one The opcode is 08AO0h as shown below 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 419 3 639 79 9 E 9 9 9 39 Example 2 ADD 8 As in Example 1 but with no autoincrement the opcode is 0880h Example 3 ADD 8 As in Example 1 except that the current auxiliary register is decremented by one
410. ltimedia appli cations TLC32047 TMS320 TMS320 Figure G 3 TMS320C25 CLKOUT FSX DX FSR DR CLKR CLKX DSP Encrypt Decrypt 9600 bps Modem V 32 bis TMS320 TLC32047 TMS320 DSP TLC32047 Interface Figure G 3 shows the interfacing of the TMS320C25 DSP to the TLC32047 AIC that constitutes the building blocks of the 9600 bps V 32 bis modem shown in Figure G 2 DX TMS320C25 to TLC32047 Interface TLC32047 MSTR CLK FSX FSR DR SHIFT CLK ANLG GND Multimedia Speech Encoding and Modem Communication Vocoder Speech Analysis 0 2 uF Cer 0 2 uF Cer A BAT 42 0 2 uF Cer eo 5V e 45V VDD DGTL GND lt 0 1 uF V V Phone Line 5V G 3 Multimedia Applications G 1 2 Multimedia Related Devices As shown in Table H 1 TI provides a complete array of analog and graphics interface devices These devices support the TMS320 DSPs for complete mul timedia solutions Table H 1 Data Converter ICs ET Resolution Conversion Vici 4 43 2 kHz Portable modem and speech multimedia 4 25 kHz Speech modem and multimedia TLC320AC01 Analog interface 5 V only Analog interface 11 4 kHz BW AIC TLC5602 Video DAC Parallel 25 kHz Speech and modems 19 2 kHz Speech and modems 1 s s veo Dual aud
411. ly These clocks are required only during serial transfers on the TMS320C25 Note that the TMS320C25 is double buffered Figure 6 21 Interface of TMS320C25 to TCM29C 16 Codec 45V 9320 25 TCM29C16 4 W 0 01 uF 100 KQ o Analog 100 kQ Output 74ALS04A 74AS869 5 40 96 MHz 1 l 10 ko i E 4 7 KQ 1 L lt w 74HC04 ap tur Analog Ground T 9 47 pF 5 L 1 8 pH ls Digital Ground dante 2 Serial port transfers are initiated by framing pulses the FSX and FSR pins for transmit and receive operations respectively For transmit operations the FSX pin can be configured as an input or an output This option is selected by the transmit mode TXM bit of status register ST1 In this design FSX is as sumed to be configured as an input therefore transmit operations are initiated by a framing pulse on the FSX pin Upon completion of receive and transmit operations an RINT serial port receive interrupt and an XINT serial port transmit interrupt are generated respectively Interface timing of the TMS320C25 to the TCM29C16 corresponds to the burst mode serial port transmit and receive operations shown in Figure 3 37 and Figure 3 38 re spectively Continuous mode operation with or without framing pulses is also possible 6 38 Hardware Applications Interfacing Peripherals The for
412. mat FO bit of status register ST1 is used to select the format 8 bit byte or 16 bit word of the data to be received or transmitted For interfacing the TMS320C25 to a codec the format bit should be set to 1 formatting the data in 8 bit bytes The TMS320C25 interfaces directly to the codec as shown in Figure 6 21 with no additional logic required The PCM u law data generated by the codec at the PCMOUT pin is read by the TMS320C25 from the data receive DR pin which is internally connected to the receive serial register RSR The data transmitted from the data transmit DX pin of the TMS320C25 is received by the PCMIN input of the codec During the digital to analog conversion this u law companded data must be converted back to a linear representation for use inthe TMS320C25 The resulting analog waveform is lowpass filtered by the codec s internal smoothing filter Therefore no additional filtering is re quired at the codec output PWRO Software companding routines appropri ate for use on the TMS320C25 are provided in the book Digital Signal Proces sing Applications with the TMS320 Family literature number SPRAO 124 The software required to initialize the TMS320C25 codec interface is provided in the combo codec interface section of the application report Hardware Inter facing to the TMS320C25 literature number SPRAO144A This report also presents detailed information regarding codec interfacing A combo codec configured
413. may take three or more cycles to execute but when repeated a table location can be read every cycle Note that not all instructions can be repeated see Section NO TAG and Appendix E for more information 3 6 7 Powerdown Modes TMS320C25 When operated in either of two powerdown modes the TMS320C25 enters a dormant state and requires approximately one half the power normally need ed to supply the device see the data sheet Appendix A Depending upon the application one powerdown mode is invoked by executing an IDLE instruction while the other mode is invoked by driving the HOLD input low while the HM status bit is set to one 3 53 Running Title Attribute Reference 3 54 While in a powerdown condition all of the internal contents of the TMS320C25 are retained This allows the operation to continue unaltered after the power down condition is terminated If the powerdown mode was entered by driving HOLD low with HM 1 the data and address buses and the interface control signals PS DS IS STRB and R W are all maintained in the high impedance state If the mode was entered by the IDLE instruction only the data bus goes to the high impedance state address bus and interface control signals are maintained in a steady state condition and can still be driven In accordance with the execution process the powerdown mode may be terminated either by removing the HOLD input or by applying an interrupt signal during the IDLE opera
414. mbler symbols equal to 0 or 1 Auxiliary register pointer 4 bit field specifying a bit code Branch control input Carry bit 2 bit field specifying compare mode On chip RAM configuration control bit Data memory address field Label assigned to data memory location n Data memory address Data page pointer Format status bit Frame synchronization mode bit Hold mode bit Interrupt mode flag bit Immediate operand field Addressing mode bit Microcall stack nnh hexadecimal number others are decimal values Overflow mode flag bit Overflow mode bit Product register Port address 15 assembler symbols equal to 0 through 15 Program counter Prefetch counter 2 bit field specifying P register output shift code Program memory address Label assigned to program memory location n 3 bit operand field specifying auxiliary register Repeat counter 4 bit left shift code Status register n STO or ST1 Sign extension mode bit Temporary register Test control bit Top of stack Transmit mode bit 3 bit accumulator left shift field XF pin status bit 4 12 Assembly Language Instructions Instruction Set Table 4 3 Instruction Symbols Continued Is assigned to An absolute value italics User defined items Optional items Contents of Alternative items one of which must be entered Blanks or spaces must be entered where shown 4 2 2 Instruction Set Summary Table 4 4 shows the instructio
415. me from PC disk storage or provided directly by the master CPU Figure 6 19 depicts a direct memory access using a PC environment In this configuration decode and arbitration logic is used to control the direct memory access When the address on the system bus resides in the local memory of the peripheral TMS320C2x this logic asserts the HOLD signal of the TMS320C2x while sending the master a not ready indication to allow wait states After the TMS320C2x acknowledges the direct memory access by as serting HOLDA READY is asserted and the information transferred 6 33 Direct Memory Access DMA Figure 6 19 Direct Memory Access in a PC Environment Master CPU Address Local Address Program Data Memory RAM Address Address Disk Controller zmaAo o Address Decode Arbitration HOLD Address Logic Data Ready HOLDA Local Address Program Data Memory RAM 6 34 Hardware Applications Global Memory 6 4 Global Memory For multiprocessing applications the external memory of the TMS320C2x can be divided into local and global sections Special registers and pins included onthe TMS320C2x allow multiple processors to share up to 32K words of glob al data memory space This implementation facilitates efficient shared data multiprocessing in which data is transferred between two or more processors Unlike a direct memory access DMA scheme reading or writing global memory
416. memory value is then loaded into the T register squared and stored in the P register Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SQRA DAT30 6 PM 0 or SQRA If current auxiliary register contains 798 Before Instruction After Instruction Data Data Memory OFh Memory OFh 798 798 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Square and Subtract Previous Product SQRS Direct label SQRS dma Indirect abel SQRS ind next ARP 0 x dma 127 x next ARP lt 7 1 PC ACC shifted P register ACC dma T register dma x dma P register Affects OV affected by PM and OVM Affects C 5 1 7 6 5 4 3 2 1 0 1 4 13 12 11 10 9 8 Direct 9 1 0 1 1 0 1 0 Data Memory Address Indirect 1 0 1 1 0 1 0 See Section 4 1 The contents ofthe P register shifted as defined by the PM status bits are sub tracted from the accumulator The addressed data memory value is then loaded into the T register squared and stored into the P register Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SQRS 9 DP 6 PM 0 or SORS If current auxiliary register contains 777 Before Instruction After Instruction Data Data 777 8h ACC 1450h
417. ming of the seri al port signals is compatible with the Tl Intel 29C1x series codecs The timing is also compatible with the AMI S3506 series codecs if the frame synchroniza tion signals are inverted Serial port transfers on the TMS320C25 are generally initiated by a frame sync pulse except when the continuous mode of operation is used with FSM 0 Frame sync pulses are input on FSX for transmit operations and on FSR for receive operations If FSM 1 frame sync pulses are required if FSM 0 they are not required FSM is set by the SFSM set frame synchronization mode instruction and cleared by the RFSM reset frame synchronization mode instruction Architecture Serial Port 3 9 3 Burst Mode Operation In burst mode serial port operation transfers are separated in time by periods of no serial port activity the serial port does not operate continuously For burst mode operation FSM must be set to one Timing of the serial port in this mode of operation is shown in Figure 3 37 and Figure 3 38 Figure 3 37 Burst Mode Serial Port Transmit Operation 5 1 E P o M e 020 MSB LSB XINT t t DXR DXR Loaded Reloaded XSR XSR Loaded Reloaded During CLKX Low Figure 3 38 Burst Mode Serial Port Receive Operation ANANI NINININI NINININI NINY FsR __ TN me B MSB LSB RINT N
418. n Example 5 15 Moving Program Memory to Data Memory with BLKP THIS ROUTINE USES THE BLKP INSTRUCTION TO MOVE DATA VALUES FROM PROGRAM MEMORY INTO DATA MEMORY SPECIFICALLY THE VALUES IN LOCATIONS 2 3 4 AND 5 IN PROGRAM MEMORY ARE MOVED TO LOCATIONS 512 513 514 AND 515 IN DATA MEMORY LARP AR2 SET REFERENCE FOR INDIRECT ADDRESSING LRLK AR2 512 LOAD BEGINNING OF BLOCK BO IN AR2 RPTK 3 SET UP LOOP BLKP 2h PUT DATA INTO DATA RAM RE RETURN TO MAIN PROGRAM 5 33 Memory Management The TBLR instruction is another method for transferring data from program memory into data memory When the TBLR instruction is used a calculated rather than predetermined location of a block of data in program memory may be specified for transfer A routine using this approach is shown in Example 5 16 Example 5 16 Moving Program Memory to Data Memory With TBLR THIS ROUTINE USES THE TBLR INSTRUCTION TO MOVE DATA VALUES FROM PROGRAM MEMORY INTO DATA EMORY BY USING THIS ROUTINE THE PROGRAM MEMORY LOCATION THE ACCUMULATOR FROM WHICH DATA IS TO BE MOVED TO A SPECIFIC DATA MEMORY LOCATIO CAN BE SPECIFIED ASSUME THAT THE ACCUMULATOR CONTAINS THE ADDRESS IN PROGRA MEMORY FROM WHICH TO TRANSFER THE DATA
419. n After Instruction neo aco 4 C C Stack Stack 4 133 POPD Pop Top of Stack to Data Memory Syntax Operands Execution Encoding Description Words Cycles Example 4 134 Direct label POPD dma Indirect label POPD ind next ARP 0 lt dma x 127 0 x next ARP lt 7 PC 1 PC TOS 2 dma POP stack one level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 1 1 d 0 1 0 Data Memory Address Indirect 1 1 1 1 0 1 0 See Section 4 1 The value from the top of the stack is transferred into the data memory location specified by the instruction The values are also popped in the lower seven locations TMS320C2x of the stack The hardware stack is described in the previous instruction POP The lowest stack location remains unaffected No provision exists to check stack underflow Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution POPD DAT100 DP 8 or POPD If current auxiliary register contains 1124 Before Instruction After Instruction Data Data Memory 55h Memory 92h 1124 1124 Stack Stack Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Push Data Memory Value Onto Stack PSHD Direct label PSHD dma Indirect label PSHD ind next ARP 0 lt dma x 127 0 lt next ARP gt 7 dma gt TOS 1
420. n Chip RAM for Program 5 38 5 5 Fundamental Logical and Arithmetic Operations 5 43 5 5 1 Status Register Effect on Data Processing 5 43 5 5 2 BitManipulation s cocci ree pee mr m p e Rep ER e ker eu 5 44 Table of Contents Contents 5 6 Advanced Arithmetic Operations 5 46 5 6 1 Overflow Management 5 46 cit e Eee 5 47 5 63 Shifting MULT Id CMULITque rus ber 5 47 5 6 4 Moving Data 0 2 5 51 5 6 5 Mu ltiplicatiori Ee Roe D ro tte evertere ev gp rt en 5 53 5 6 6 DIVISION iu o eee obe CFR Pete EE epo ter et or dere 5 57 5 6 7 Floating Point Arithmetic 5 60 5 6 8 Indexed Addressing 5 62 5 6 9 Extended Precision Arithmetic 5 62 5 7 Application Oriented Operations 5 68 5 4 Gompahding ces Veneria pe Med 5 68 5 752 FRIR Filtering eis or E RN RE 5 70 5 7 3 Adaptive Filtering 5 71 5 7 44 Fast Fourier Transforms FF
421. n From Texas Instruments Trademarks viii Speech Gray A H and Markel J D Linear Prediction of Speech New York NY Springer Verlag 1976 Jayant N S and Noll Peter Digital Coding of Waveforms Englewood Cliffs NJ Prentice Hall Inc 1984 Papamichalis Panos Practical Approaches to Speech Coding Englewood Cliffs NJ Prentice Hall Inc 1987 Rabiner Lawrence R and Schafer R W Digital Processing of Speech Signals Englewood Cliffs NJ Prentice Hall Inc 1978 Image Processing Andrews H C and Hunt B R Digital Image Restoration Englewood Cliffs NJ Prentice Hall Inc 1977 Gonzales Rafael C and Wintz Paul Digital Image Processing Reading MA Addison Wesley Publishing Company Inc 1977 Pratt William K Digital Image Processing New York NY John Wiley and Sons 1978 Digital Control Theory Jacquot R Modern Digital Control Systems New York NY Marcel Dekker Inc 1981 Katz P Digital Control Using Microprocessors Englewood Cliffs NJ Prentice Hall Inc 1981 Kuo B C Digital Control Systems New York NY Holt Reinholt and Winston Inc 1980 Moroney P Issues in the Implementation of Digital Feedback Compensators Cambridge MA The MIT Press 1983 Phillips C and Nagle H Digital Control System Analysis and Design Englewood Cliffs NJ Prentice Hall Inc 1984 MS and MS DOS are trademarks of Microsoft Corp VAX VMS and Ultrix are tradem
422. n Robot Control Sonar Processing Speaker Verification Laser Printer Control Image Processing Speech Enhancement Engine Control Navigation Speech Synthesis Motor Control Missile Guidance Text to Speech Radio Frequency Modems Telecommunications Automotive Echo Cancellation FAX Engine Control ADPCM Transcoders Cellular Telephones Vibration Analysis Digital PBXs Speaker Phones Antiskid Brakes Line Repeaters Digital Speech Adaptive Ride Control Channel Multiplexing Interpolation DSI Global Positioning 1200 to 19200 bps Modems X 25 Packet Switching Navigation Adaptive Equalizers Video Conferencing Voice Commands DTMF Encoding Decoding Spread Spectrum Digital Radio Data Encryption Communications Cellular Telephones Consumer Radar Detectors Robotics Hearing Aids Power Tools Numeric Control Patient Monitoring Digital Audio TV Security Access Ultrasound Equipment Music Synthesizer Power Line Monitors Diagnostic Tools Toys and Games Prosthetics Solid State Answering Fetal Monitors Machines Many of the TMS320C2x features such as single cycle multiply accumulate instructions 32 bit arithmetic unit large auxiliary register file with a separate arithmetic unit and large on chip RAM and ROM make the device particularly applicable in digital signal processing systems At the same time general pur pose applications are greatly enhanced by the large address spaces on chip timer serial port multiple interrupt struct
423. n every negative going edge of CLKR The first data bit is considered the MSB and RSR is filled ac cordingly After all the bits have been received as specified by FO an internal receive interrupt RINT is generated on the rising edge of CLKR and the con tents of RSR are transferred to DRR 3 67 Serial Port Figure 3 36 Serial Port Receive Timing Diagram CLKR FSR DR RINT le 8 or 16 Bits 3 9 2 Timing and Framing Control 3 68 Upon completion of a serial port transfer an internal interrupt is generated The RINT interruptis generated for a receive operation and XINT is generated for a transmit operation RINT and XINT are generated on the rising edge of CLKR and CLKX respectively after the last bit is transferred Note that if DRR is read before a RINT is received it will contain the data from the previous op eration Similarly if DXR is loaded more than once after an XINT is generated in the continuous transmission mode only the last value written will be loaded into XSR for the next transmit operation When the TMS320C2x is reset is cleared to zero and DX is placed the high impedance state Any transmit or receive operation that is in progress when the reset occurs is terminated The transmit framing synchronization pulse can be generated internally or ex ternally The maximum speed of the serial port is 5 MHz The ti
424. n example of a TMS320C2x l O port multiprocessing scheme as shown in Figure 6 30 The TMS70C42 may be mapped into the TMS320C2x I O space by using latches to store the transferred data In a single or multiple l O port multiprocessing configuration the four LSBs of the address bus are decoded to determine which of the 16 I O ports on the TMS320C2x is being accessed The TMS320C2x selects the I O space IS for its external bus and reads writes data using the IN OUT instructions Processor controlled signals between the TMS320C2x and the peripheral de vice indicate when data is available to be read This interprocessor commu nication is facilitated by using the input and output pins of the TMS70C42 or other peripheral processor In an multiprocessing configuration the port address space is limited and data transfers are relatively slow compared to a direct memory access or global memory configuration Figure 6 30 Port Processor to Processor Communication TMS320C2x TMS70C42 IS Control 6 47 System Applications 6 6 System Applications The TMS320C2x is used in a wide variety of systems Several applications in the areas of telecommunications graphics and image processing high speed control instrumentation and numeric processing are described in the follow ing paragraphs to illustrate basic approaches to system design with the TMS320C2x 6 6 1 Echo
425. n input for BIO in this example The output of XF will provide a 50 percent duty cycle clock signal as long as the main routine or other interrupt routines do not disable interrupts Interrupts may be disabled by direct or implied use of DINT or by executing instructions in the repeat mode The value for the PRD register is calculated as follows TMS320C25 CLKOUT1 PRD 1 2 x frequency of signal 10 MHz 520 1 2 x 9600 Hz 9597 Hz for divided signal 5 25 Program Control Example 5 8 Clock Divider Using Timer TMS320C25 SETUP FOR INTERRUPT SERVICE ROUTINE LALK 520 SACL LOAD THE PERIOD REGISTER LACK 8 OR DMA4 SACL DMA4 ENABLE THE TIMER INTERRUPT EINT ENABLE INTERRUPTS I O SERVICE ROUTINE TIME BIOZ SETI CHECK THE CURRENT STATE RXF XF WAS HIGH SET IT LOW EIN ENABLE INTERRUPTS RE RETURN TO INTERRUPTED CODE SET1 SXF WAS LOW SET IT HIGH EIN ENABLE INTERRUPTS RE RETURN TO INTERRUPTED CODE 5 2 4 Single Instruction Loops When programming time critical high computational tasks it is often neces sary to repeat the same operation many times For these tasks the TMS320C2x has repeat instructions that allow the execution of the next single instruction N 1 t
426. n set summary for the TMS320C2x processor which is a superset of the TMS320C1x instruction set Included in the instruc tion set are four special groups of instructions to improve overall processor throughput and ease of use Extended precision arithmetic ADDC SUBB MPYU BC BNC SC RC Adaptive filtering MPYA MPYS and ZALR Control and I O RHM SHM RTC STC RFSM and SFSM Accumulator and register SPH SPL ADDK SUBK ADRK SBRK ROL and ROR The instruction set summary is arranged according to function and alphabet ized within each functional grouping Additional information is presented in the individual instruction descriptions in the following section Instruction Set Table 4 4 Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS Mnemonic and Description 16 Bit Opcode MSB LSB Absolute value of accumulator Add to accumulator with shift Add to accumulator with carry Add to high accumulator Add to accumulator short immediate Add to low accumulator with sign extension suppressed Add to accumulator with shift specified by T register Add to accumulator long immediate with shift AND with accumulator AND immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator short immediate Load accumulator with shift specified by T register Load accumulator long immediate with shift Negate accumulator Normalize contents of accumu
427. nded that BIO pin be initialized at power up or reset to avoid inadvertently selecting the wrong mode The value of d is the number of wait states used at global memory address 08000h and be comes part of the delay before polling the status of BIO The presence of an EPROM is determined by a test pattern check for an un modified B instruction in the first download location Both global and normal data spaces are checked The test pattern must be found in the global data space but not in normal data space This bit pattern test was chosen because the ROM coded vector table uses ARP modification while branching to your vector table in block BO If your pro gram were also to use ARP modification the ARP buffer ARB would be over written and ARP recovery during an interrupt service routine would not be pos sible The conclusion is that the unmodified B instruction is an excellent test because you should never modify it Furthermore since most systems do not decode the global memory space when selecting external memory a random bit pattern resembling an unmodified branch instruction will be rejected as a valid EPROM signature Global memory decoding must therefore be used to download from external memory EPROM Processor Initialization It is impossible to download from an EPROM if the global memory select pin BR bus request is not used to enable the EPROM The advantage of this method is that BR can also be ORed with MSC to generate a
428. nformation corre sponding to a 13 bit dynamic range to be transmitted as 8 bit data For proces sing in the TMS320C2x it is necessary to convert the 8 bit logarithmic sign magnitude data to a 16 bit 2s complement linear format Prior to output the linear result must be converted to the compressed or companded format Table lookup or conversion subroutines may be used to implement these func tions Software routines for u law and A law companding flowcharts companding algorithms and detailed descriptions are provided in the application report on companding routines mentioned above The algorithm space and time re quirements for u law and A law companding on the TMS320C25 are given in Table 5 1 Software Applications Application Oriented Operations Table 5 1 Program Space and Time Requirements for u A Law Companding Memory Words Program Cycles Time us Requiredt Program Data Initialization Loop 5320 25 u Law Compression 74 45 Expansion 276 0 5 A Law Compression Expansion T Assuming initialization Worst case In expanding from the 8 bit data to the 13 bit linear representation table look up is very effective because the table length is only 256 words This is especial ly true for a microcomputer design because the TMS320C25 has 4K words of mask programmable ROM and the TMS320E25 has 4K words of EPROM The table lookup technique requires three instructions four words of program memory one data mem
429. ng capacitor drives the TCM29C16 s internal opamp This opamp is connected in the inverting configuration with unity gain feedback and input impedances having the same value of 100 kQ For applications such as modems speech control instrumentation and ana log interface for DSPs acomplete analog to digital A D and digital to analog D A input output system on a single chip may be desired The TLC32040 analog interface circuit AIC integrates on a single monolithic CMOS chip a bandpass switched capacitor antialiasing input filter 14 bit resolution A D and D A converters and alowpass switched capacitor output reconstruction filter The TLC32040 offers numerous combinations of master clock input fre quencies and conversion sampling rates which can be changed via digital processor control Four serial port modes on the TLC32040 allow direct interface to TMS320C2x processors When the transmit and receive sections of the AIC are operating synchronously it can interface to two SN54299 or SN74299 serial to parallel shift registers These shift registers can then interface in parallel to the 5320 2 to other 5320 digital signal processors or to external FIFO circuitry Output data pulses are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between two transmitted bytes A flexible control scheme is provided so that the functions of the AIC can be selected and adjusted coin
430. no performance overhead The sign extension mode option is used to determine whether or not the shifted data values fetched for ALU operations should be sign extended The SXM status bit controls this operation The SSXM instruction sets this bit to 1 for enabling sign extension and the RSXM instruction sets it to 0 for suppres sing sign extension This operation affects all the instructions that include a shift of the incoming data value that is ADD ADDT ADLK LAC LACT SBLK SFR SUB and SUBT The overflow mode option minimizes the effects of an arithmetic overflow by forcing the accumulator to saturate at the largest positive value or in the case of underflow the largest negative value The OVM status bit controls this op eration The overflow mode is enabled by setting the OVM bit to a 1 with the SOVM instruction and reset with the ROVM instruction This feature affects all arithmetic operations in the ALU 5 43 Fundamental Logical and Arithmetic Operations The product register shift mode option forces all products to be shifted before they are accumulated The products can be left shifted one bit to delete the extra sign bit when two 16 bit signed numbers are multiplied The products can be left shifted four bits to delete the extra sign bits in multiplying a 16 bit data value by a 13 bit constant The product shifter can also be used to shift all prod ucts six bits to the right to allow up to 128 product accumulatio
431. no wait states are mapped at the low er half lower 32K words of the TMS320C25 data space The upper half is used for memories with one or more wait states Figure 6 17 shows the timing for memory read and write cycles Table 6 6 summarizes the most critical timing parameters of the CY7C 169 25 interface to the TMS320C25 Table 6 6 Timing Parameters of CY7C 169 25 Interface to TMS320C25 Figure 6 17 CLKOUT1 low to TMS320C25 data bus entering the t4 15 ns max high impedance state MEMSEL low to CY7C169 25 driving the data bus 5 ns min MEMSEL low to CY7C169 25 data valid 15 ns max MEMSEL high to CY7C1 69 25 entering the high im t7 15 ns max pedance state Data setup time for a write 32 ns min Data holditime 75 ns min 6 27 Interfacing Memories Figure 6 16 Interface of CY7C 169 25 to TMS320C25 TMS320C25 CY7C169 25 MEMSEL 6 28 Hardware Applications Interfacing Memories Figure 6 17 Interface Timing of CY7C 169 25 to 5320 25 CLKOUT1 DS A15 A0 READY STRB R W MEMSEL TMS320C25 D15 DO CY7C169 25 D15 DO R W MEMSEL TMS320C25 D15 DO CY7C169 25 I O4 I O1 Read Cycle ONG t Write la tg gt 4 9 Cycle COR 5500 ED een 6 2 5 Interface Timing Analysis When interpreting TMS320C25 timing specifications particularly in the area of memory interface timing it is necessary to understand clock
432. nowledge signal Indicates that the TMS320C2x has gone into the hold mode and that an external processor may ac cess the local external memory of the TMS320C2x SYNC F2 19 Synchronization input Allows clock synchronization of two or more TMS320C2xs SYNC is an active low signal and must be asserted on the rising edge of CLKIN Interrupt and Miscellaneous Signals Branch control input Polled by BIOZ instruction If BIO is low the TMS320C2x executes a branch This signal must be active during the BIOZ instruction fetch IACK B11 60 Interrupt acknowledge signal Output is valid only while CLKOUT1 is low Indicates receipt of an interrupt and that the pro gram is branching to the interrupt vector location designated by 15 0 External user interrupt inputs Prioritized maskable by the in terrupt mask register and the interrupt mode bit Microprocessor microcomputer mode select pin for the TMS320C25 When asserted low microcomputer mode the pin causes the internal ROM to be mapped into the lower 4K words of the program memory map In the microprocessor mode the lower 4K words of program memory are external T Pin numbers apply to CER QUAD as well as to PLCC t Input Output High impedance state 2 5 TMS320C2x Signal Descriptions Table 2 1 TMS320C2x Signal Descriptions Continued Pin 0 2 Description PGA PLCCT Interrupt and Miscellaneous Signals Continued C10 59 Microstate complete
433. ns is understood to be fully at the risk of the customer using TI devices or systems TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Nor does TI warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Copyright 1992 Texas Instruments Incorporated Read This First About This Manual The purpose of this user s guide is to serve as a reference book for the 5320 2 digital signal processors Chapters 2 through 6 provide specific information about the architecture and operation of the devices Appendices A through E furnish electrical specifications and mechanical data How to Use This Manual 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 This document contains the following chapters Introduction Description and key features of the TMS320C2x generation of digital signal processors Pinouts and Signal Descriptions Package drawings for TMS320C2x devices Functional listings of the signals their pin locations and descriptions Architecture TMS320C2x design description hardware components and device operation Functional block diagram and
434. ns without the threat of an arithmetic overflow thereby avoiding the overhead of overflow management The shifter can be disabled to cause no shift in the product when working with integer or 32 bit precision operations This also maintains com patibility with TMS320C1x code These operations are controlled by the value contained in the PM bits of status register ST1 The SPM instruction sets the PM bits This feature affects all the instructions that use the product of the mul tiplier that is APAC LTA LTD LTP LTS MAC MACD MPYA MPYS PAC SPAC SPH SPL SQRA and SQRS 5 5 2 Bit Manipulation 5 44 The BIT instruction tests any of the 16 bits of the addressed data word The specified bit is copied into the TC of the status register The bit tested is speci fied by a bit code in the opcode of the instruction Both the BBZ branch on TC bit 0 and BBNZ branch on TC bit 1 instructions check the bit and allow branching to a service routine Bit testing is useful in control applications where a number of states or condi tions may be latched externally and read into the TMS320C2x via an IN instruction At this point individual bits can be tested and branches taken for appropriate processing Because the BIT instruction requires the bit code to be specified with the instruction it cannot be placed in a loop to test several different bits of a data word or bits determined by prior processing for efficient use The TMS320C2x also
435. nstruction cycle The length of the constant operand is instruction dependent Assembly Language Instructions Memory Addressing Modes ADDK Add to accumulator short immediate 8 bit absolute constant ADRK Add to auxiliary register short immediate 8 bit absolute constant LACK Load accumulator short immediate 8 bit absolute constant LARK Load auxiliary register short immediate 8 bit absolute constant LARP Load auxiliary register pointer 3 bit constant LDPK Load data memory page pointer immediate 9 bit constant MPYK Multiply immediate 13 bit 2s complement constant RPTK Repeat instruction as specified by immediate value 8 bit constant SBRK Subtract from auxiliary register short immediate 8 bit absolute constant SUBK Subtract from accumulator short immediate 8 bit absolute constant Example of short immediate addressing format RPTK 99 Execute the instruction following this instruction 100 times With the RPTK instruction the immediate operand is contained as a part of the instruction opcode The instruction format for RPTK is as follows 15 14 13 12 1110 9 8 76 5 4 3 2 1 0 1 1 0 0 1 0 1 1 8 Bit Constant For long immediate instructions the constant is a 16 bit value in the word fol lowing the opcode The 16 bit value can be optionally used as an absolute constant or as a 2s complement value ADLK Add to accumulator long immediate with shift absolute or 2s complement ANDK AND immediate with accumula
436. nstruction shifts the accumulator right one bit If SXM 1 the instruction produces an arithmetic right shift The sign bit MSB is unchanged and is also copied into bit 30 Bit 0 is shifted into the carry bit C If SXM 0 the instruction produces a logical right shift All of the accumulator bits are shifted by one bit to the right The least significant bit is shifted into the carry bit and the most significant bit is filled with a zero 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SFR SXM 0 Before Instruction After Instruction oosa seem SFR SXM 1 Before Instruction After Instruction ACC 0B0001234h ACC o 00800091 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Set Serial Port Frame Synchronization Mode SFSM SFSM None 1 PC 1 FSM status bit in status register ST1 Affects FSM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1 The SFSM instruction sets the FSM status bit to logic one In this mode an external FSR pulse is required for a receive operation and an external FSX pulse is required if 0 If 1 FSX pulses are generated in the nor mal manner every time the transmit shift register XSR is loaded See Section 3 7 for details on the operation of the serial port FSM may
437. nt gt ACC Affects C and OV affected by OVM Not affected by SXM 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 O0 1 0 0 13 1 0 1 Bi The 8 bit immediate value is subtracted right justified from the accumulator with the result replacing the accumulator contents The immediate value is treated as an 8 bit positive number regardless of the value of SXM 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable SUBK 12h Before Instruction After Instruction C Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Subtract from Low Accumulator with Sign Extension Supressed SUBS Direct label SUBS dma Indirect label SUBS ind next Ox dma x 127 0 lt next ARP lt 7 PC 1 5 PC ACC dma gt Affects OV affected by OVM Affects C Not affected by SXM 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Direct 0 1 1 0 1 E Data Memory Address Indirect o 1 See Section 4 1 4 i The contents of the addressed data memory location are subtracted from the accumulator with sign extension suppressed The data is treated as a 16 bit unsigned number regardless of SXM The accumulator behaves as a signed number SUBS produces the same result as a SUB instruction with SXM 0 a shift count of 0 Cycle
438. nt can be used to verify a failed handshake and is a good method to detect a failed checksum as well SYNCHRONIZATION 1 BIO XF transfer After loading the CHECKSUM the value previously transmitted in the configu ration word reconfigures the internal memory and interrupts The C26 then waits for a falling edge on the BIO pin before program control is passed to the first address of BO If a checksum error has occurred this allows the host to checkthe status and possibly rebootthe system When BIO goes low program control is always passed to the first address of program block BO regardless of the checksum status Note Because the XF pin is used as ahandshake signal during transfers with the host suitable software control must verify the correct sumcheck status Software Applications Processor Initialization 5 1 1 2 Mode 2 Serial Download From an RS232 Port 8 Data Bits 2 Stop Bits 1 Start Bit If the BIO signal is found to be high 39 2d cycles after reset a test is made to determine if external global memory EPROM mode 3 is present If this fails a serial download is performed It is recommended that you initialize the BIO pin at reset to avoid inadvertently selecting the wrong mode The value of dis the number of wait states for global memory address 08000h and be comes part of the delay before polling the BIO pin The presence of an unmodified B instruction in the global data space but not normal data space determ
439. nt data to be loaded into on chip RAM 5 41 Memory Management COEF 1 1 START word 385 1196 1839 2009 word 1390 407 4403 19958 word 19958 4403 407 1390 word 2009 1839 1196 385 COEFE label C1 END COEFL equ COEFE COEF Coefficient data length Data page 0 Block B2 Data memory labels bss DRR 1 Serial port data receive register bss DXR 1 Serial port data transmit register bss Timer register bss PRD 1 Period register bss IMR 1 Interrupt mask register bss GREG 1 Global memory allocation register bss RSVRDO 05Ah bss B2 020h bss RSVRD1 0180h Data page 4 Block BO Data memory labels BO bss PROGR PROGL Location for internal program code bss COEFF COEFL Location for coefficent memory bss FREE0 0100h PROGL COEFL Data page 6 block B1 data memory labels B1 bss ONE 1 Reserved for data value of 1 bss FILOUT 1 Filter output signal value bss FILIN 1 Filter input signal value bss SIG 13 bss SIGNAL 1 Last signal delay value end 5 42 Software Applications Fundamental Logical and Arithmetic Operations 5 5 Fundamental Logical and Arithmetic Operations Although the TMS320C2x instruction set is oriented toward digital signal pro cessing the same fundamental operations of a general purpose processor are included This secti
440. nterface is implemented using the six serial port pins Figure 3 34 shows the registers and pins used in transmit and receive operations Figure 3 34 Serial Port Block Diagram 3 66 A FSX CLKR CLKX XINT DX Data is clocked onto the DX pin from the XSR of the TMS320C25 by a CLKX signal Data is clocked into the RSR of the TMS320C25 from the DR pin by a CLKR signal CLKX and CLKR are required to be present only during actual serial port transfers and may be stopped at a valid logic level when no data is being transferred Data bits can be transferred in either 8 bit bytes or 16 bit words Data is clocked out to DX on the rising edges of CLKX while data is clocked in from DR on the falling edges of CLKR The MSB of the data is trans ferred first The and RSR are connected to the DXR and DRR respectively For transmit operations the contents of DXR are transferred to XSR when a new transmission begins For a receive operation the contents of RSR are trans ferred to DRR when all of the bits have been received Thus the serial port is double buffered because data may be transferred to or from the DXR or DRR while another transmit or receive operation is being performed Serial porttransfers on the TMS320C25 are generally initiated by a frame sync pulse The exception to this is when the continuous mode of operation is used with FSM 0 as described in a subsequent paragraph Frame sync pulses
441. ntheTMS32026 bit 7 is CNF1 and bit 12 is CNFO 3 OntheTMS32020 bits 5 6 and 9 of ST1 are ones Instruction Set Summary T using full speed on chip external program memory These instructions are not available on the TMS32020 K 14 Appendix Title Attribute Reference Running Title Attribute Reference ARP Auxiliary register pointer OV Accumulator overflow flag bit OVM Overflow mode bit INTM Interrupt mask bit DP Data memory page pointer ARB Auxiliary register pointer buffer CNF On chip RAM configuration control bit TC Test control flag bit SXM Sign extension mode bit FSM Frame synchronization mode bit XF XF pin status bit FO Format bit TXM Transmit mode bit PM Product shift mode bits Instruction Format Description 15 14 1312 11 10 9 8 7 6 5 4 1 2 OPCODE 0 Oo 1 0 3 OPCODE BR 4 OPCODE 5 OPCODE 6 OPCODE S PA B D 7 OPCODE 8 OPCODE 9 OPCODE K 10 OPCODE K 11 OPCODE AR K 12 OPCODE K 13 OPCODE K 14 OPCODE AR OPCODE K 15 OPCODE S OPCODE K Indirect Addressing Control Bits 6 5 4 3 2 1 0 IDV DEC NAR next ARP K 15 Running Title Attribute Reference IDV Increment decrement value INC Increment flag 1 increments auxiliary register DEC Decremen
442. o over 1 gigabyte in the past decade which equates to a 23 900 percent growth in capacity To accommodate these increasingly higher densities the data on the servo platters whether servo positioning or actual storage infor mation must be converted to digital electronic signals at increasingly closer points in relation to the platter pick off point The ADC must have increasingly higher conversion rates and greater resolution to accommodate the increasing bandwidth requirements of higher storage densities In addition the ADC con version rates must increase to accommodate the shorter data retrieval access time Analog Interface Peripherals and Applications Servo Control Disk Drive Applications Figure 6 9 shows a block diagram of a disk drive control system Figure 9 Disk Drive Control System Block Diagram SCSI Data Bus To lt gt SCSI RAM Bufer CSI Data Host Interface Buffer Data Sequencer Separator Control Servo TMS320C14 TMS2764 Demodulator v Address Decode Control Disk Head Select Control TLC32071 To From Disk Heads Spindle 5308 Table 8 lists analog digital interface devices used for servo control Table H 8 Control Related Devices Bee 58 Speed Gees omes 3 s osse Pr
443. ocessing systems The filters fall into two basic categories finite impulse response FIR and Infi nite impulse response IIR filters For either category of filter the coefficients of the filter weighting factors may be fixed or adapted during the course of the signal processing Presented in Digital Signal Processing Applications with the TMS320 Family literature number SPRAO124 an application report discusses the theory and implementation of digital filters The 100 ns instruction cycle time of the TMS320C25 reduces the execution time of all filters especially the IIR filters because fewer multiply accumu late routines are required Correspondingly the amount of data memory for samples and coefficients is not usually the limiting factor Because of sensitiv ity to quantization of the coefficients themselves IIR filters are usually imple mented in cascaded second order sections This translates to instruction code consisting of LTD MPY instruction pairs rather than MACDs Example 5 42 illustrates an implementation of a second order IIR filter Example 5 42 Implementing an IIR Filter EQUATIONS ARE USED TO IMPLEMENT AN IIR FILTER x n din Ijal dim 2 a2 d n bO d n 1 b1 d n 2 b2 THE FOLLOWING d n y n START IN XN PAO LAC XN 15 LT DNM1 MPY Al TD DNM2 MPY 2 SACH DN 1 ZAC MPY B2 LTD DNM1 M
444. ode MSB LSB Test bit Test bit specified by T register Configure block as data memory Configure block as program memory Configure block as data program memory Disable interrupt Enable interrupt Idle until interrupt Load status register STO Load status register ST1 No operation Pop top of stack to low accumulator Pop top of stack to data memory Push data memory value onto stack Push low accumulator onto stack Reset carry bit Reset hold mode Reset overflow mode Repeat instruction as specified by data memory value Repeat instruction as specified by immediate value Reset sign extension mode Reset test control flag Set carry bit Set hold mode Set overflow mode Store status register STO Store status register ST1 Set sign extension mode Set test control flag T CONF instruction is specific to the TMS320C26 instruction set the instructions CNFP are undefined 4 17 Individual Instruction Descriptions 4 3 Individual Instruction Descriptions Each instruction in the instruction set summary is described in the following pages Instructions are listed in alphabetical order Information such as as sembler syntax operands operation encoding description words cycles and examples is provided for each instruction An example instruction is pro vided to familiarize you with the special format used and to explain
445. ode produces these TMS27C64 signals ViH TTL high level Vip TTL low level ADDR byte address bit Vpp 12 5 0 25 V FAST or 13 0 25 V SNAP Voc 5 0 25 V Voc 1 6 0 25 V FAST or 6 5 V 0 25 V SNAP X don t care PULSE low going TTL pulse DIN byte to be programmed at ADDR QouT byte stored at ADDR F 6 TMS320E25 EPROM Programming F 2 1 Erasure Programming and Verification Before programming the memory must be erased by exposing high intensity ultraviolet light wavelength 2537 angstroms into the chip through its trans parent lid Note that normal ambient light contains the correct wavelength for erasure Therefore the window should be covered with an opaque label after programming the TMS320E25 The recommended minimum exposure dose UV intensity x exposure time is 15 watt seconds per square centimeter If lo cated about 2 5 centimeters above the transparent lid a typical filterless UV lamp with a 12 milliwatt per square centimeter output will erase the memory in 21 minutes After the memory is erased all bits are in a high state F 2 2 FAST Programming After erasure all memory bits in the cell are a logic one Logic zeros mustnow be programmed into their desired location The FAST programming algorithm shown in Figure F 5 is normally used to program the entire EPROM contents although individual locations may be programmed separately A programmed logic zero can be erased only by ultrav
446. of on chip operations or optimization of the pipeline execution The following paragraphs describe the effects of HOLD HOLDA RS interrupts accumula tor store on chip program access external data access and repeats as they are visible from the pins of the device In the cases of RS interrupts and HOLD HOLDA the effects on the pipeline are shown in the data sheet timing diagrams see Appendix A 3 45 System Control 3 46 Reset The reset interrupt is a totally nonmaskable interrupt When executed it stops operation of the pipeline and flushes the unexecuted parts The reset pulse must be at least three CLKOUT cycles wide After the second CLKOUT cycle has completed before the third rising edge of CLKOUT1 the device has brought all outputs into a high impedance state After the rising edge of RS the device begins to fetch the reset vector Since the pipeline is empty it does not execute the reset vector branch until two cycles later If the HOLD line is brought low during the active reset the device does not start the fetch of the reset vector until after the active HOLD is removed and the device deactivates the HOLDA line When HOLD is activated with RS to allow bootloading of the code the HOLDA line will go active low in three cycles regardless of whether or not the RS line has gone high This is useful in that the HOLDA line can be used to enable the release of the RS line and guarantee the required three cycle reset
447. of the simulator Software Devel opment System SWDS or emulator XDS along with an assembler linker These tools give the TMS320 user various means of evaluation from software simulation of the second generation TMS320s simulator to full speed in cir cuit emulation with hardware and software breakpoint trace and timing capa bilities XDS Software and hardware can be developed simultaneously by using the macro assembler linker C compiler and simulator for software development the XDS for hardware development and the Software Development System for both software development and limited hardware development Many third party vendors offer additional development support for the second generation TMS320s including assembler linkers simulators high level lan guages applications software algorithm development tools applications boards software development boards and in circuit emulators Refer to the TMS320 Family Development Support Reference Guide SPRU011A for fur ther information about TMS320 development support products offered by both Texas Instruments and its third party suppliers Additional support for the TMS320 products consists of an extensive library of product and applications documentation Three day DSP design workshops are offered by the Regional Technology Centers RTCs These workshops provide insight into the architecture and the instruction set of the second gen eration TMS320s as well as hands on tra
448. omatically on the hardware stack If there is any important information in the other TMS320C2x registers such as the status or auxiliary registers these must be saved by software command A stack in data memory identified by an auxiliary register is useful for storing the machine state when processing interrupts Example 5 11 and Example 5 12 show how to save and restore the state of the TMS320C25 Auxiliary register 7 AR7 in both examples is the stack point er As the stack grows it expands into lower memory addresses The status registers STO and ST1 accumulator ACCH and ACCL product register PR temporary register TR all eight levels of the hardware stack and the auxiliary registers ARO through AR6 are saved The routines in Example 5 11 and Example 5 12 are protected against inter rupts allowing context switches to be nested This is accomplished by the use ofthe MAR and MAR instructions at the beginning of the context save and context restore routines respectively Note that the last instruction of the con text save decrements AR7 while the context restore is completed with an addi tional increment of AR7 This prevents the loss of data if a context save or re store routine is interrupted 5 29 Interrupt Service Routine Example 5 11 Context Save TMS320C25 title CONTEXT SAVE de
449. on The result is a scrambling in the address access The procedure for generating the bit reversal address sequence is to load ARO with a value corresponding to one half the length of the FFT and to load anoth er auxiliary register for example AR1 with the base address of the data array Implementations of FFTs involve complex arithmetic as a result there are two data memory locations one real and one imaginary associated with every data sample Generally the samples are stored in memory in pairs with the real part in the even address locations and the imaginary part in the odd address location This means that the offset from the base address for any given sam ple is twice the sample index Real input data is easily transferred into the data memory and stored in the scrambled order with every other location in the data memory representing the imaginary part of the data 5 77 Application Oriented Operations The following list shows the contents of auxiliary register AR1 when ARO is ini tialized with a value of 8 8 point FFT and when data is being transferred by the code that follows MSB ARO 0000 AR1 0000 RPTK 7 IN BRO PAO AR1 0000 AR1 0000 AR1 0000 AR1 0000 AR1 0000 AR1 0000 AR1 0000 AR1 0000 0000 0010 0010 0010 0010 0010 0010 0010 0010 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 LSB 1000 0000 0000 1000 0100 1100
450. on explains basic operations of the TMS320C2x cen tral arithmetic logic unit CALU particularly accumulator operations the sta tus register effect on data processing and bit manipulation The TMS320C2x provides a complete set of logical operations including AND OR XOR and CMPL complement instructions This enables the de vice to perform any logical function These instructions can convert sign mag nitude to 2s complement or the reverse You can store the contents of the accumulator in data memory with the SACH and SACL instructions or in the stack with the PUSH instruction You can load the accumulator from data memory with the ZALH and ZALS instructions which zero the accumulator before loading the data value The ZAC instruc tion zeros the accumulator POP can be used to restore the accumulator con tents from the stack The accumulator is also affected by the ABS and NEG instructions ABS re places the contents of the accumulator with the absolute value of its contents NEG generates the arithmetic complement of the accumulator in complement form 5 5 1 Status Register Effect on Data Processing Three data processing options allow the ALU to automatically suppress sign extension manage overflow or scale product accumulations These options are enabled or disabled through bits in the status registers and function in par allel with normal execution of the instructions They cause no additional ma chine cycles and therefore
451. on following EINT executes This allows an interrupt service routine to re enable interrupts and execute a RET instruction before any other pending interrupts are processed Note that the LST instruction does not affect INTM See the DINT instruction for further information 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution EINT Unmasked interrupts are enabled and is LO Zero 4 81 FORT Format Serial Port Registers Syntax Operands Execution Encoding Description Words Cycles Example 4 82 abel FORT constant Constant or 1 PC 1 PC Constant format FO status bit Affects FO The format FO status bit is loaded by the instruction with the LSB specified in the instruction The FO bit is used to control the formatting of the transmit and receive shift registers of the serial port If FO 0 the registers are config ured to receive transmit 16 bit words If FO 1 the registers are configured to receive transmit 8 bit bytes FO is set to zero on a reset 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution FORT 1 FO status bit is loaded with 1 making the bit length of the serial port 8 bits Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Idle
452. on or averaging for digitally increased sharpness and higher quality audio The DSP digital output is converted back to analog by a video DAC as shown in Figure 9 13 Analog Interface Peripherals and Applications Advanced Digital Electronics Applications for Consumers Figure G 13 Video Signal Processing Basic System TV IF TMS320 Amplifier DSP Field System Controller Memory Video Signal Clock Generator VCRs compact disc and DAT players and PCs are a few of the products that have taken a major position in the marketplace in the last ten years The audio channels for compact disc and DAT require 16 bit A D resolution to meet the distortion and noise standards See Figure G 14 for a block diagram of a typi cal digital audio system Figure G 14 Typical Digital Audio Implementation Third Overtone Oscillator Circuit TMS57001 Digital Audio TMS57013 4 Dual 16 18 Sound Bit DAC Digital Filter Processor Analog Power Amplifier The motion and motor control systems usually use 8 to 10 bit ADCs for the lower frequency servo loop Tape or disc systems use motor or motion control for proper positioning of the record or playback heads With the storage me dium compressing data into an increasingly smaller physical size the position ing systems require more precision Advanced Digital Electronics Applications for Consumers The audio processing becomes more demanding as higher fidelity is requ
453. ons Add to High Accumulator Syntax Direct label ADDH dma Indirect label ADDH ind next ARP Operands 0 lt lt 127 0 next ARP lt 7 Execution PC 1 5 PC x 216 2 Affects OV affected by OVM Affects C Low order bits of the ACC not affected EN Encoding 14 13 12 11 10 9 8 6 5 4 3 2 1 0 Direct 9 Data Memory Address Indirect o See Section 4 1 E o o o E E o Description The contents of the addressed data memory location are added to the upper half of the accumulator bits 31 through 16 Low order bits are unaffected by ADDH The carry bit C on the 5320 2 is set if the result of the addition generates a carry otherwise C is unaffected The carry bit can only be set not reset by the ADDH instruction The ADDH instruction may be used in performing 32 bit arithmetic Words Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 29 ADDH Aad to High Accumulator Example DAT5 DP 8 or ADDH current auxiliary register contains 1029 Before Instruction After Instruction Data Data 1029 1029 4 30 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Add to Accumulator Short Immediate ADDK label ADDK constant
454. ons fractional arith metic or justifying fractional products The SMJ320C26 provides a memory mapped 16 bit timer for control opera tions The on chip timer TIM register is a down counter that is continuously clocked by CLKOUT1 A timer interrupt TINT is generated every time the tim er decrements to zero provided the timer interrupt is enabled The timer is re loaded with the value contained in the period PRD register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD 1 cycles of CLKOUT1 The SMJ320C26 provides a total of 1568 words of 16 bit on chip RAM divided into four separate blocks BO B1 B2 and B3 Of the 1568 words 32 words E 11 Running Title Attribute Reference block B2 are always data memory and all other blocks are programmable as either data or program memory A data memory size of 1568 words allows the SMJ320C26 to handle a data array of 1536 words while still leaving 32 loca tions for intermediate storage When using BO B1 or as program memory instructions can be downloaded from external memory into on chip RAM and then executed When using on chip program RAM ROM or high speed external program memory the SMJ320C26 runs at full speed without wait states However the READY line can be used to interface the SMJ320C26 to slower less expen sive external memory Downloading programs from slow off chip memory to on chip progr
455. oper order an inverter is placed in the circuit of Figure 4 and performs the necessary byte reversal for the TMS320E25 Figure F 3 EPROM Programming Data Format F 4 TMS320C25 On Chip TMS320C25 On Chip EPROM Program Memory Program Memory Programmer Word Format Byte Format Memory Byte Format with Adapter Socket 0 0000h 0 0000h 0 0000h 1 0001h 1 0001h 1 0001h 2 0002h 2 0002h 2 0002h 3 0003h 3 0003h 3 0003h 4 0004h 4 0004h 5 0005h 5 0005h 6 0006h 6 0006h 4095 0FFFh 7 0007h 7 0007h 8191 1FFFh Figure F 4 shows the wiring diagram when the TMS320E25 is programmed with the TMS27C64 in its 28 pin output form The illustration furnishes a table for each pin nomenclature onthe TMS27C64 with a description of that pin Pro gramming the code into the device should be done in the serial mode Although acceptable by some EPROM programmers the signature mode cannot be used on TMS320C25 device The signature mode will input a high level voltage 12 5 Vpc onto pin A9 Since the TMS320E25 EPROM cell is not designed for high voltage the cell will be damaged To prevent an accidental application of voltage Texas Instruments has inserted a 3 9 resistor between A9 of the TI programmer socket and the programmer itself TMS320E25 EPROM Programming Programming Verification Figure 4 TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout st e 527
456. operations Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ZALS 1 6 or ZALS If current auxiliary register contains 769 Before Instruction After Instruction Data Data Memory OF7FFh Memory OF7FFh 769 769 ACC 7FFO0033h ACC OF7FFh Assembly Language Instructions Chapter 5 Software Applications The TMS320C2x microprocessor microcomputer design emphasizes overall speed communication and flexibility Many instructions are tailored to digital signal processing tasks and provide single cycle multiply accumulates adap tive filtering support and many other features General purpose instructions support floating point extended precision logical processing and control ap plications This chapter provides explanations of how to use the various TMS320C2x pro cessor and instruction set features along with assembly language coding ex amples More information about specific applications can be found in the book Digital Signal Processing Applications with the TMS320 Family literature number SPRAO124 The assembly source code examples in this chapter contain directives and commands specific to the Texas Instruments Assembly Language Tools Pub lication TMS320 Fixed Point DSP Assembly Language Tools literature num ber SPRUO18B is highly recommended as a reference The TMS320C26 is similar to the TMS320C25 except for its inte
457. or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p 3 p False Condition Destination anywhere 2 2 242p 2 2 Cycle Timings for a Repeat Execution not repeatable BNZ PRG320 320 is loaded into the program counter if the accumulator does not equal zero Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch on Overflow BV label BV ind next ARP 0 lt pma lt 65535 0 lt next ARP x 7 If overflow OV status bit 1 Then pma PC and 0 gt OV Else PC 2 gt PC Modify AR ARP and ARP as specified Affects OV affected by OV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 51 0 1 1 1 1 0 000 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified and the over flow flag is cleared Control passes to the designated program memory ad dress pma if the OV overflow flag is set Otherwise control passes to the next instruction Note that no AR or ARP modification occurs if nothing is spe cified in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for
458. or a read operation The two different addresses are necessary to ensure that the correct number of waitstates is provided forthe write and read operations The controlling soft ware for the A D interface is given on page 11 206 of Linear and Interface Cir cuits Applications Volume 3 Peripheral Drivers Data Acquisition Systems Hall Effect Devices literature number SLYA003 published by Texas Instru ments 6 44 Hardware Applications Interfacing Peripherals With the TMS320C2x running at 20 MHz and the TLC0820 configured as slow memory three wait states are necessary to provide a write pulse of sufficient length After conversion has begun with the rising edge of the WR signal the TMS320C2x must wait at least 600 ns before the conversion result can be read Sufficient delay should be provided in software To read the conversion result an adequate number of wait states must be provided to allow for the data access time 320 ns minimum of the TLC0820 As shown in the IN instruction timing diagram of Figure 6 28 two wait states are provided when accessing port 1 Figure 6 28 Interface Timing of TLC0820 to TMS320C2x CLKOUTH 8B EAE fF F Ki CLKOUT2 See ee eee O A Bnw Adress Vaid 00 CG RD WR 22 4 NC READY EE M D15 DO I 6 45 Interfacing Peripherals 6 5 5 I O Ports I O design on the 5320 2 is treated the same way as memory The I O address space is distinguished f
459. or the ARP If a next ARP is specified the old ARP is copied to the ARB field of status register ST1 Note that any op eration that MAR performs can also be performed with any instruction that sup ports indirect addressing ARP may also be loaded by an LST instruction In the direct addressing mode MAR is a NOP Also the instruction LARP is a subset of MAR that is MAR 4 performs the same function as LARP 4 Words Cycles Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 117 Modify Auxiliary Register Example 1 MAR 1 Load the ARP with 1 Before Instruction After Instruction Example 2 MAR a Decrement current auxiliary register in this case AR1 Before Instruction After Instruction Example 3 MAR deed lncrement current auxiliary register AR1 and load ARP with 5 Before Instruction After Instruction 4 118 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Multiply MPY Direct label MPY dma Indirect label MPY next ARP 0 dma x 127 0 x nex ARP x 7 PC 1 PC T register x dma P register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 0 Data Memory Address Indirect 0 0 See Section 4 1 a E E E E EN The contents of the T register are multiplied by the contents of th
460. ormat functions most efficiently on the TMS320C2x The theory and implementation of floating point arithmetic has been presented in an application report in the book Digital Signal Processing Applications with the TMS320 Family literature number SPRAO 124 Operations in the TMS320C2x central ALU are performed in 2s complement fixed point notation To implement floating point arithmetic operands must be converted to fixed point for arithmetic operations and then converted back to floating point Conversion to floating point notation is performed by normalizing the input data that is shifting the MSB of the data word into the MSB of the internal memory word The exponent word then indicates how many shifts are re quired To multiply two floating point numbers the mantissas are multiplied and the exponents added The resulting mantissa must be renormalized since the input operands are normalized no more than one left shift is required to renormalize the result Floating point addition or subtraction requires shifting the mantissa so that the exponents of the two operands match The difference between the exponents is used to left shift the lower power operand before adding Then the output of the add must be renormalized 5320 2 instructions useful in floating point operations are the NORM LACT ADDT and SUBT instructions NORM may be used to convert fixed point numbers to floating point LACT may be used to convert back to fixe
461. ort tools nomenclature K 2 SXF 4 183 symbols 3 10 symbols and abbreviations 4 11 4 13 SYNC 2 5 3 75 synchronization 3 75 timing C25 3 76 system applications 6 48 echo cancellation 6 48 graphics and image processing 6 50 high speed control 6 51 instrumentation 6 51 modem 6 48 numeric processing 6 51 voice coding 6 49 system control 3 35 3 53 See also control circuitry 25 powerdown modes 3 53 diagram 3 35 hardware stack 3 35 pipeline operation 3 37 3 47 program counter 3 35 repeat counter 3 53 reset 3 47 status registers 3 49 3 52 timer 3 52 T register TR 3 32 TBLR 4 184 5 34 TBLW 4 186 5 34 telecom devices G 8 telecommunications applications G 5 DSP combo G 6 temporary register 3 11 TIM 3 11 TIM register 3 52 timer 3 11 5 25 timer block diagram 3 52 timer operation 3 52 Index timing BIO 3 57 external flag XF 3 58 memory 3 80 timing control 3 67 TLC32046 G 3 TLC32070 G 14 TMS320C25 1 4 data sheets A 1 5320 25 33 1 4 TMS320C25 50 1 4 TMS320C26 1 4 data sheet B 1 TMS320C26 block diagram 3 8 TMS320C26 description TMS320C28 1 1 1 7 2 3 data sheet C 1 TMS320C2x instruction cycle timings E 2 TMS320C2x block diagram 3 7 TMS320E25 1 4 TR 3 11 transistors J 5 TRAP 4 188 two word instructions 3 43 user design considerations 6 7 6 10 VCC 2 6 video signal processing G 19 voice coding 6 49 voice synthe
462. ory address used is less than 4096 an on chip ROM location will be read Words 2 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Table in on chip RAM 3 3 d 442p Table in on chip ROM 4 44d 442p Table in external memory 4 4 d p 443p Table in on chip RAM 2 2 2 2 2 2 Table in on chip ROM 2 3 n nd 2p Table in external memory 3 n np 2 2 3 n np 2p 2 2n nd np 2p 3 n np 2 2n nd np 4 61 BLKP Block Move From Program Memory to Data Memory Example 4 62 RPTK 2 BLKP pma dma 65120 If current auxiliary register contains 2048 Data Memory 65120 Data Memory 65121 Data Memory 65122 Data Memory 2048 Data Memory 2049 Data Memory 2050 Before Instruction 0A089h 2DCEh 3A9Fh Before Instruction 1234h 2005h OE98Ch After Instruction Data Memory 0A089h 65120 Data Memory 2DCEh 65121 Data Memory 3A9Fh 65122 After Instruction Data Memory 0A089h 2048 Data Memory 2DCEh 2049 Data Memory 3A9Fh 2050 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch if Accumulator Less Than Zero BLZ label BLZ ind next ARP 0 lt pma lt 65535 0 lt ARP x7 If ACC 0 Then pma PC Else PC 2 gt PC Modify AR ARP and ARP as specif
463. ory location 256 words of table memory and seven instruction cycles program in on chip ROM to execute LAC SAMPLE LOAD 8 DATA ADLK MUTABL ADD THE CONVERSION TABLE BASE ADDRESS TBLR SAMPLE READ THE CORRESPONDING LINEAR VALUE The above conversion could be programmed as a subroutine This would elim inate the need for a table but would increase execution time and require addi tional data memory locations When the output data has been determined in a system transmitting compan ded data a compression of the data must be performed The compression re duces the data back to the 8 bit format Unless memory for a table of length 16384 is acceptable the table lookup approach must be abandoned for con version routines Details of these implementations may be found in the ap plication report on companding Access to new companding code as it becomes available is provided via the TMS320 DSP Bulletin Board Service The bulletin board contains TMS320 source code from application reports included in Digital Signal Processing Ap plications with the TMS320 Family literature number SPRAO124A See the TMS320 Family Development Support Reference Guide literature number SPRUO 114 for information on how to access the bulletin board 5 69 Application Oriented Operations 5 7 2 Filtering Digital filters requirement for digital signal pr
464. ownload 5 6 BR 2 5 branches 3 32 BV 4 67 byte mode DRR operation 3 69 BZ 4 68 CAL 5 22 CALA 4 69 5 22 CALL 4 71 CALU 3 28 components of 3 28 3 34 central arithmetic logic unit CALU 3 9 3 28 ALU and accumulator 3 30 components of 3 28 3 34 diagram 3 29 multiplier 3 32 scaling shifter 3 30 shift modes 3 33 T and P registers 3 32 CLKOUT1 2 6 3 56 CLKOUT2 2 6 3 56 CLKR 2 7 CLKX 2 7 clock divider C25 5 26 clock phases 3 56 clock timing 3 56 CMPL 4 73 CMPR 4 74 CNFD 4 75 CNFP 4 76 code generation tools K 1 assembler linker K 1 C compiler K 1 digital filter design package K 1 combo codec interface 6 37 6 40 Index companding 5 68 comparison of internal RAM 3 18 computed GOTO 5 28 CONF 4 77 configuring on chip RAM 5 35 5 37 diagram 5 36 example 5 37 5 39 consumer electronics advanced digital applications G 18 advanced digital television G 18 digital audio G 19 video signal processing G 19 context restore C25 5 31 context save C25 5 30 context switching 5 29 continuous mode operation 3 69 3 74 control circuitry 6 2 crystal oscillator 6 5 emulator architecture 6 7 6 10 powerup reset 6 2 crystal oscillator circuit 6 5 crystals H 4 frequencies H 4 specifications H 4 vendors H 4 D A interface 6 42 DAB 3 9 DAC G 20 data bus 2 4 3 9 data bus 015 00 2 4 3 9 data memory 3 17 data moves 3 27 5 51
465. perating conditions see Note 1 PARAMETER MIN UNIT ta CH DX DX valid after CLKX rising edge see Note 8 80 ms td FL DX valid after FSX falling edge 0 see Note 8 id gH FS FSX valid after CLKX rising edge 1 timing requirements over recommended operating conditions see Note 1 wSck Serial clock CLKXIGLKR Tow pulse duration tses Noe 39 iw SCK Serial port clock CLKX CLKR high pulse duration see Note 9 80 tsu FS _ FSX FSR setup time before CLKX CLKR falling edge 0 NOTES 1 Q t 4te C 8 The last occurrence of FSX falling and CLKX rising 9 The duty cycle of the serial port clock must be within 40 60 Serial port clock CLKX CLKR rise and fall times must be less than 25 ns E 39 Running Title Attribute Reference PARAMETER MEASUREMENT INFORMATION Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 2 volts unless otherwise noted tcn m ie tye tn s lw CIL H tsu s tsu S SYNC os d CIH C td CIH C 6 5 r iw CL CLKOUT1 ta CIH C tw CH gt tc lt STRB ta cin c n tw CL CLKOUT2 td C1 C2 4 ta c1 c2 le F 2
466. pplications Figure DSP Combo Interface Timing FSX FSR Timing MSB LSB Timing MSB LSB Telecommunications Related Devices Data sheets for the devices in Table 3 are contained in the 1991 Telecommunications Circuits Databook literature number SCTD001B To request your copy contact your nearest Texas Instruments field sales office or call the Literature Response Center at 800 477 8924 For further information on these telecommunications products please call TI Linear Applications at 214 997 3772 G 7 Telecommunications Applications Table H 3 Telecom Devices Coding Clock Rates i Codec Filter 154 159 208 00 ana PBX Ine cares 715415206 e Incudes tb signal tempe a 16pin package 2048 f e Low cost DSP merce Crem se 8 Low cost DSP interiaco Rams _Upt0 4006 78 Extended requency range 048 e Low power ToMaocz0 National Semiconductor National Semiconductor Transient Suppressor Unless otherwise noted Table H 4 Switched Capacitor Filter ICs order Raro T Power Out Power Down TLC2470 Differential audio filter amplifier 500 mW TLC2471 Differential audio filter amplifier 3 5 2 500mW CLK 50 TLC10 20 General purpose dual filter CLK 100 N A 2 CLK 5
467. processor An IACK interrupt acknowledge signal is then generated The IACK clears the appropriate interrupt edge flip flop and disables the INTM latch The logic is the same for INT1 and INT2 In a typical interrupt INT2 INTO operation the interrupt is generated by negative going edge and the IFR bit is set Because INTM is disabled when the interrupt is acknowledged the level may continue to be present on the INT input without generating further interrupts If the level is removed before an EINT instruction is executed no further interrupts are generated If a low level continues to be present after the EINT another interrupt is generated after the EINT next instruction sequence In addition if the INT pin is pulsed between the previous IACK and EINT another interrupt is generated after EINT RET because the corresponding IFR bit is again set Architecture Interrupts Figure 3 32 shows an interrupt interrupt acknowledge and various other sig nals for the special case of single cycle instructions An interrupt generated during the current N fetch cycle still allows the fetch and execution of that instruction The N 1 and N 2 instructions are also fetched then discarded and the address N 1 is pushed onto the top of the stack The instruction is fetched again upon a return command from the interrupt routine Figure 3 32 Interrupt Timing Diagram TMS320C25 axa LVS NS Nf VS VST KTS eo NL LYS NL
468. pt CALL the branch instructions immediate operand instructions and instructions with no oper ands The direct addressing format is as follows 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 gp Bits 15 through 8 contain the opcode Bit 7 0 defines the addressing mode as direct and bits 6 through 0 contain the data memory address dma Example of Direct Addressing Format ADD 9 5 Add to accumulator the contents of data memory location 9 left shifted 5 bits 15 14 13 12 1 10 9 8 7 6 5 4 3 21 0 0 0 0 1 001 opcode of the ADD 9 5 instruction is 05 and appears bits 15 through 8 The notation nnh indicates nn is a hexadecimal number The shift count of 5h appears in bits 11 through 8 of the opcode The data memory address 09h appears in bits 6 through 0 4 3 Memory Addressing Modes 4 1 2 Indirect Addressing Mode The auxiliary registers AR provide flexible and powerful indirect addressing Eight auxiliary registers ARO AR7 are provided on the TMS320C2x To se lect a specific auxiliary register the auxiliary register pointer ARP is loaded with a value from 0 through 7 designating ARO through AR7 see Figure 4 2 Figure 4 2 Indirect Addressing Block Diagram 4 4 Data Bus 16 Auxiliary Registers 16 Bit Data Address The contents of the auxiliary registers may be operated upon by the auxiliary register arithmetic unit ARAU which implements 16 bit unsigned a
469. putational results but using less assembly code Example 5 28 Using MACD for Moving Data THIS ROUTINE IMPLEME D THAT 1 IS POI NTS A SINGLE PASS OF A THIRD ORDER F IR FILTER IT IS A MEMORY LOCATIONS THAT THI A E ACCUMULATOR AND P REGIST TING XO SSUMED THAT THE H AND X VALUES HAVE ALREADY BEEN LOADED INTO THEIR RESPECTIVE NOTE THAT THE MACD Hj ox ox ox a 3 LARP 1 MAC OFFOOh MACD OFFO1lh MACD OFF02h 5 52 NENNEN Ne MODE BUT IT IS NOT IMPLEMENTED INSTRUCTI ER ARE BOTH RESE TO ZERO ON MAY BE USED IN CONFIGURE BLOCK BO AS PROGRAM MEMORY AR1 SHOULD POI AT THE X VALUES P X0 H2 ACC X0 H2 X0 H2 X1 H1 ACC X0 H2 X1 H1 X2 HO CONFIGURE BLOCK AS DATA MEMORY R ETURN TO MAIN PROGRAM Software Applications 5 6 5 Multiplication Example 5 29 Multiply MUL Advanced Arithmetic Operations The TMS320C2x hardware multiplier normally performs 2s complement 16 bit by 16 bit multiplies and produces a 32 bit result in one processor cycle Asingle TMS320C2x instruction MPYU can be used to multiply two 16 bit un signed numbers To multiply two operands one operand must be loaded into the T reg
470. r 5 8 Software Applications Processor Initialization Configuration Word Definitions STATUS 1 transfer This is the first word sent to the C26 The bit fields for this word are given below Bits DO D1 D2 are the MSBs of the program length Bit D3 selects the reset download mode 0 reset only no download 1 start download of the program Bit D4 selects the transmission memory format 0 8 bit format 1 16 bit format not allowed in serial mode Bits 05 07 should be set low Do not use them INTERRUPT 1 BIO XF transfer This word defines the interrupt and final memory configuration to be installed after bootstrapping During the bootload process blocks BO B1 and B3 are configured as data and always loaded first This word is loaded into the C26 by a single transfer with the upper bits being masked off The configuration is as follows Bits 00 05 are loaded into the interrupt mask register IMR Bits D6 amp D7 define the memory configuration after download D7 D6 Program Memory Data Memory 0 0 BO B1 B2 B3 0 1 BO B1 B2 B3 1 0 BO B1 B2 PROGRAM LENGTH 1 transfer The third word to be transferred is the program length starting at block BO 0200h followed by B1 and B3 The 8 LSBs of the LENGTH word are com bined with bits DO D1 and D2 of the STATUS word to form the total program length up to 2K words in length The length does not include any of the con trol CHE
471. r on chip ROM fetch The instruction is fetched during Q4 and Q1 then decoded in Q2 and Q3 The rest of the pipeline tracks as de scribed above Some operations add additional machine cycles to the instruction execution without damaging the integrity of the program or hardware External wait states multiplexed data bus conflicts two word instructions and program counter discontinuities are included in these operations as described in the following paragraphs Wait States The TMS320C25 is designed to be interfaced to slower external devices through the use of hardware generated wait states This applies to the program data and memory spaces of the Harvard architecture Wait states are a direct delay on the instruction pipeline Each wait state inserted during the instruction fetch contributes an additional machine cycle in the pipe line execution of the instruction In addition any wait state incurred when accessing external data or I O space also contributes an additional machine cycle to the pipeline execution of the instruction This factor applies to all instructions Figure 3 20 describes how the pipeline reacts to wait states in external program memory Note that the wait state added in cycle 2 results in a no execution operation in cycle 4 8 41 System Control Figure 3 20 Pipeline Operation With Wait States Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 2 Q3 Q4 Q1 Q2 Q
472. r repeated instruction TMS320E25 EPROM Programming EPROM Protection and Verification Invalid microprocessor mode Microprocessor mode can t be used after enabling the RBIT because the PBUS is disconnected from the external program space F 3 3 Protect Verify Following the EPROM protect mode the protect verify mode reviews and veri fies the programming of the RBIT see Figure F 8 for accuracy When using this mode D7 outputs the state of the RBIT When RBIT 1 the EPROM is unprotected when RBIT 0 the EPROM is protected The EPROM protection and verification timings are shown in Figure F 10 Figure F 10 EPROM Protection Timing 4 Protect Verify Y Y Y Y ON M XX KMS ON ON 020 P020 029 01029 00 9 00 9 v VPP Vcc Voc 1 Vcc VIL PGM a SOV VIL VIH G VIL HI Z gt NEL ViL VOL VPP EPT 5 Vss RRIRIK RRN m T 12 5 V Vpp and 6 0 V Vcc for FAST Programming for SNAP Programming 13 0 V Vpp and 6 5 V Vcc TMS320E25 EPROM Programming Appendix Analog Interface Peripherals and Applications Texas Instruments offers many products for total system solutions including memory options data acquisition and analog input output devices This ap pendix describ
473. ram bus and the data bus The program bus carries the instruction code and im mediate operands from program memory The data bus interconnects various elements such as the central arithmetic logic unit CALU and the auxiliary register file to the data RAM Together the program and data buses can carry data from on chip data RAM and internal or external program memory to the multiplier in a single cycle for multiply accumulate operations The TMS320C2x has a high degree of parallelism for example while the data is being operated upon by the CALU arithmetic operations may also be imple mented in the auxiliary register arithmetic unit ARAU Such parallelism re sults in a powerful set of arithmetic logic and bit manipulation operations that may all be performed in a single machine cycle LEGEND ACCH Accumulator high IFR Interrupt flag register PC Program Counter ACCL Accumulator low IMR Interrupt mask register PFC Prefetch counter ALU Arithmetic logic unit IR Instruction register RPTC Repeat instruction counter ARAU Auxiliary register arithmetic unit MCS stack GREG Global memory allocation register ARB Auxiliary register pointer buffer QIR Queue instruction register RSR Serial port receive shift register ARP Auxiliary register pointer PR Product register XSR Serial port transmit shift register DP Data memory page pointer PRD Period register for timer ARO AR Auxiliary registers DRR
474. ram and data buses This provides for single cycle multiply accumulates when used with repeat RPT RPTK instructions Note that the DMOV portion of the MACD instruction will not function with external data memory address es On the TMS320C2x the MAC and MACD instructions can be used with both operands in either internal or external memory or one each in on chip RAM The SQRA square add and SQRS square subtract instructions pass the same value to both inputs of the multiplier for squaring a data memory val ue The MPYU instruction on the TMS320C2x performs an unsigned multiplica tion which greatly facilitates extended precision arithmetic operations The unsigned contents of the T register are multiplied by the unsigned contents of the addressed data memory location with the result placed in the P register This allows operands of greater than 16 bits to be broken down into 16 bit words and processed separately to generate products of greater than 32 bits After the multiplication of two 16 bit numbers the 32 bit product is loaded into the PR on the TMS320C2x The product from the PR may be transferred to the ALU Four product shift modes PM are available at the PR output and are useful when performing multiply accumulate operations and fractional arithmetic or when justifying fractional products The PM field of status register ST1 speci fies the PM shift mode as shown in Table 3 4 Table 3 4 PM Shift Modes No shift L
475. rdware To Program Program Bus 16 IR 6 16 R 6 Address Bus 4 v v 16 8x 16 E 16 The program counter addresses program memory either on chip or off chip via the program address bus PAB Through the PAB an instruction is fetched from program memory and loaded into the instruction register IR When the IR is loaded the PC is ready to start the next instruction fetch cycle The PC may address any on chip RAM blocks configured as program memory or the 3 35 System Control 3 36 on chip ROM provided on the TMS320C25 The PC also addresses off chip program memory through the external address bus A15 A0 and the external data bus D15 DO Data memory is addressed by the program counter during a BLKD instruction which moves data blocks from one section of data memory to another The contents of the accumulator may be loaded into the PC to implement com puted GOTO operations This can be accomplished using the BACC branch to address in accumulator or CALA call subroutine indirect instructions To start a new fetch cycle the PC is loaded either with PC 1 or with a branch address for instructions such as branches calls or interrupts In the case of conditional branches where the branch is not taken the PC is incremented once more beyond the location of the branch address The TMS320C2x also has a feature that allows the execution ofthe next single instruction N 1 times
476. re test bits larp AR2 Always 1 LSB error mar ARI subtract LSB done sar AR2 store final guess result zals load result in ACCU lar AR2 restore ARO amp AR2 lar ARO sbrk 2 restore ret ret O0 zac if input lt 0 ret then return 0 end Software Applications 5 6 4 Moving Data Advanced Arithmetic Operations Many DSP applications must perform convolution operations or other opera tions similar in form These operations require data to be shifted or delayed The DMOV LTD and MACD instructions can perform the needed data moves for convolution The data move function allows a word to be copied from the currently ad dressed data memory location in on chip RAM to the next higher location while the data from the addressed location is being operated upon that is by the CALU The data move and the CALU operation are performed in the same cycle In addition an ARAU operation may also be performed in the same cycle when using the indirect addressing mode The data move function is use fulin implementing algorithms such as convolutions and digital filtering where data is being passed through a time window It models the 2 1 delay operation encountered in those applications The data move function is continuous across the boundary of the on chip data memory blocks BO B1 and B2 How ever the data move function cannot be used if off chip memory is referenced In Example 5 28 the following equation
477. re the new configuration becomes effective This delay is one fetch cycle if execution is from internal program RAM On the TMS320C2x there is a delay of two fetch cycles if execution is from ROM or external program memory This is particularly important if program execution is from the loca tions around OFFOOh Accordingly a CNFP instruction must be placed at loca tion OFEFDh in external memory if execution is to continue from the first loca tion in block BO If a CNFP is placed at location OFEFDh and the instruction atlocation OFEFFh is atwo word instruction the second word ofthe instruction will be fetched from the first location in block BO If execution is from above location OFFOOh and block BO is reconfigured care must be taken to assure that execution resumes at the appropriate point in a new configuration Memory Organization The on chip program ROM can be mapped into the lower 4K words of program memory This ROM is enabled when MP MC is set to a logic low To disable the on chip ROM and use these lower addresses externally MP MC must be set to a logic high If all internal RAM blocks are configured as data memory a program address in the range FF00 to FFFFh accesses external program memory 3 4 4 TMS320C26 Memory Maps The memory map of the TMS320C26 is similar to that of the TMS320C25 and is shown in Figure 3 9 The on chip memory mapped register and block B2 with 32 words on page 0 are unchanged The ROM is reduced to 256
478. rect label OUT dma PA Indirect label OUT ind PA next ARP 0 dma x 127 0 lt next ARP x 7 0 lt port address PA x 15 PC 1 PC Port address PA address bus A3 AO 0 address bus A15 A4 dma data bus 015 DO 15 14 13 12 11 10 9 8 7 Direct 1 1 1 0 Port Address EX Data Memory Address Indirect 1 0 Port Address See Section 4 1 wo ary The OUT instruction writes a 16 bit value from data memory location to the specified I O port The IS line goes low to indicate an I O access and the STRB R W and READY timings are the same as for an external data memory write OUT is a single cycle instruction when in the PI DI memory configuration see Appendix NO TAG Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution ni OUT 78h 7 DP 4 Output data word stored in data memory location 78h to peripheral port address 7 Or OUT 0Fh Output data word referenced by current auxiliary register to peripheral on port address OFh 4 131 Load Accumulator With P Register Syntax Operands Execution Encoding Description Words Cycles Example 4 132 label PAC None PC 1 PC shifted P register ACC Affected by PM 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 527 20 0 0 0 1 0 1 0 0 The contents of the P register are
479. ress of the next instruction to be prefetched Once an instruction is prefetched the instruction is loaded into the IR unless the IR still contains an instruction cur rently executing in which case the prefetched instruction is stored in the QIR The PFC is then incremented and after the current instruction has completed execution the instruction in the QIR is loaded into the IR to be executed The PC contains the address of the next instruction to be executed and is not used directly in instruction fetch operations but merely serves as a reference pointer to the current position within the program The PC is incremented as each instruction is executed When interrupts or subroutine call instructions occur the contents of the PC are pushed onto the stack to preserve return link age to the previous program context The prefetch decode and execute operations of the pipeline are independent thus allowing instruction executions to overlap During any given cycle three different instructions can be active each at a different stage of completion Figure 3 16 shows the operation of the three level pipeline for single word single cycle instructions executing from either internal program ROM or exter nal memory with no wait states 3 37 System Control Figure 3 16 Three Level Pipeline Operation TMS320C25 CLKOUT1 prefetch decode execute gt N 1 sla 2 Pla N 1 N N 1 gt lt gt
480. result and shift ACC 10 0111111110111110 numerator left 0000000000000100 0010000000000000 14 14th SUBC command The result is 10 1000000000000000 positive Shift result left and replace 0000000000000001 1010000000000000 LSB with 1 0000000000000011 0100000000000001 15 Result is again positive Shift result 10 1000000000000000 left and replace LSB with 1 0000000000000000 11000000000000001 0000000000000001 1000000000000011 16 Last subtract Negative answer so 10 1000000000000000 discard result and shift ACC left 1111111111111101 0000000000000011 0000000000000110 Answer reached after 16 SUBC instructions Remainder Quotient 5 58 Software Applications Example 5 34 Using SUBC for Integer Division THIS ROUTINE IMPLEM DN1 DON s LT PY PAC SACH LAC ABS SACL LAC ABS IF denominator AND numerator ENTS INTEG NUMERA ENO EMSGN ENO ENO NUMERA RPTK 15 SUBC SACL LAC BGEZ ZAC SUB SACL LAC RET JOY ENOM UOT EMSGN ONE UOT UOT UOT GET SIGN QUOTII SAVE ER DIVISION GI NT SIGN OF QUOTIENT MAKE ENO ALIGN NUMERATOR ALIGNED DIVISION 16 DONE E DIVIDE LOOP Advanced Arithmetic Operations INATOR POSITIVE
481. ring the blocks BO and Bl as program memory B2 and B3 as data memory 4 77 DINT Disable Interrupt Syntax Operands Execution Encoding Description Words Cycles Example 4 78 label DINT None 1 PC 1 2 interrupt mode INTM status bit Affects INTM The interrupt mode INTM status bit is set to logic 1 Maskable interrupts are disabled immediately after the DINT instruction executes Note that the LST instruction does not affect INTM The unmaskable interrupt RS is not disabled by this instruction and the inter rupt mask register IMR is unaffected Interrupts are also disabled by a reset 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution DINT Maskable interrupts are disabled and INTM is to one Assembly Language Instructions Data Move Data Memory DMOV Syntax Direct label DMOV dma Indirect label DMOV ind znext ARP gt Operands 0 lt dma lt 127 lt next ARP lt 7 Execution PC 1 PC dma dma 1 Affected by CNF Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 1 0 10 10 Data Memory Address Indirect 1 0 1 0 1 1 0 See Section 4 1 Description The contents of the specified data memory address are copied into the con tents of the next higher address DMOV works only within the on chip data RAM blocks BO B1 and B2 It works within block
482. rithmetic The ARAU performs auxiliary register arithmetic operations in the same cycle as the execution of the instruction Note that the increment or decrement of the indicated AR is always executed after the use of that AR in the instruction In indirect addressing any location in the 64K data memory space can be ac cessed via the 16 bit addresses contained in the auxiliary registers These can be loaded by the instructions LAR load auxiliary register LARK load auxilia ry register immediate and LRLK load auxiliary register long immediate The auxiliary registers on the TMS320C2x can be modified by ADRK add to auxil iary register short immediate or SBRK subtract from auxiliary register short immediate The TMS320C2x auxiliary registers can also be modified by the MAR modify auxiliary register instruction or equivalently by the indirect ad dressing field of any instruction supporting indirect addressing AR ARP de notes the auxiliary register selected by ARP Assembly Language Instructions Memory Addressing Modes The following symbols are used in indirect addressing including bit reversed BR addressing Contents of AR ARP are used as the data memory ad dress Contents of AR ARP are used as the data memory ad dress then decremented after the access Contents of AR ARP are used as the data memory ad dress then incremented after the access 0 Contents of AR ARP are used as the data memory ad
483. rnal memory configuration This is discussed in Section 3 4 and in Appendix B Topics in this chapter include Topic Page Processor initialization 5 2 5 2 Program Control ee naaa a ae ea aaae ae 5 22 53 Service R OUa 000702 2722 5 29 5 4 Memory Management 5 33 5 5 Fundamental Logical and Arithmetic Operations 5 43 NO TAG Advanced Arithmetic Operations NO TAG NO TAG Application Oriented Operations NO TAG 5 1 Processor Initialization 5 1 Processor Initialization 5 2 Prior to the execution of a digital signal processing algorithm it is necessary to initialize the processor Generally initialization takes place anytime the pro cessor is reset When reset is activated by applying a low level voltage to the RS reset input for at least three cycles the TMS320C2x terminates execution and forces the program counter PC to zero Program memory location 0 normally contains a B branch instruction to direct program execution to the system initialization routine The hardware reset also initializes various registers and status bits After reset the processor should be initialized to meet the requirements of the system Instructions should be executed that set up operational modes memory pointers interrupts and the remaining functions necessary to meet system requirements
484. rom the local program data memory space by the IS signal IS goes low at the beginning of the memory cycle All other con trol signals and timing parameters are the same as those for the program data external memory interface The TMS320C2x software instructions can access 16 input and 16 output ports The four least significant bits of the address bus specify the particular port being accessed A pair of 74AS138s can be used to fully decode these address bits see Figure 6 29 Figure 6 29 I O Port Addressing 74AS138 VO PORT 15 PORT 14 PORT 13 PORT 12 PORT 11 5320 2 Signals 74 5138 2 A1 A0 A simple interface between two processors can be implemented by using up to 16 bidirectional I O ports connected to the TMS320C2x An interprocessor communication path can be formed by memory mapping peripherals to the I O ports of the TMS320C2x In this manner the TMS320C2x can connect to par allel A Ds registers FIFOs two port memories or other peripheral devices In a multiprocessing scheme intelligent peripherals can be memory mapped into the I O ports Here the TMS320C2x can communicate with UARTs gener al purpose microprocessors disk controllers video controllers or other pe ripheral processors 6 46 Hardware Applications Interfacing Peripherals Using an 8 bit general purpose microprocessor such as 5 TMS70C42 for a keyboard interface is a
485. rrupt flag register 3 10 interrupt acknowledge 2 5 interrupt mask register 3 10 interrupt mask register IMR 3 60 interrupt service routine ISR 5 29 5 32 Index interrupts 2 5 3 46 3 59 3 62 external interface 3 60 locations 3 59 logic diagram 3 61 operation 3 59 priorities 3 59 5 32 timing diagram 3 62 IR 3 10 IS 2 4 key features 1 6 LAC 4 85 LACK 4 9 4 86 LACT 4 87 LALK 4 9 4 89 LAR 4 90 LARK 4 9 4 92 LARP 4 93 LC circuit 6 5 LDP 4 94 LDPK 4 9 4 95 Literature Response Center ix logical and arithmetic operations 5 43 long immediate addressing 4 10 LPH 4 96 LRLK 4 9 4 97 LST 4 98 LST1 4 100 LT 4 103 LTA 4 104 5 54 LTD 4 106 LTP 4 108 LTS 4 109 Index 7 Index p law 5 68 4 111 MACD 4 114 MACD operation 5 52 MAR 4 117 masked parts 1 MCS 3 10 memories H 2 memory 26 maps 3 16 3 20 2 maps 3 15 3 19 addressing modes 4 2 blocks 3 12 3 16 3 17 combinations 3 54 data 3 12 DMA 3 5 global 3 76 interface 3 4 management 5 33 organization 3 12 program 3 12 memory organization 3 12 data memory 3 12 memory maps 3 15 program memory 3 12 3 14 C26 diagram 3 14 C2x diagram 3 13 memory mapped registers 3 22 microcall stack 3 10 microcall stack MCS register 3 36 microcomputer mode 2 5 microprocessor mode 2 5 military data sheets D 1 modem 6 48 modem applications G 15
486. ruction fetches immediately following a CNFD or CNFP instruction use the old value of CNF On the 5320 26 this instruction is not valid and is undefined 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution CNFP Ihe CNF bit is set to a logic 1 thus configuring block as program memory see memory maps in Section 3 4 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Configure Blocks as Data Program Memory TMS320C26 Only CONF label CONF constant o lt constant 3 PC 1 PC Constant program data memory configuration mode status bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 CNF1 CNFO The two low order CNF bits of the instruction word are copied into the CNFO CNF1 field of status register ST1 The CNFO and status bits config ure the on chip RAM blocks into program or data memory The bit combina tions and their meanings are shown below in the CONF mode decoding table 1 Cycle Timings for a Single Instruction Timings tora Singe instructor CONF Mode Decoding Table Los o9 po om p o p pp nu a CONF 2 Status register bit CNF1 is set to 1 and Status register bit is set to 0 thus configu
487. ry register contains 639 Before Instruction After Instruction Data Data 639 639 T OFF98h T OFF98h ACC OFDA5h OF7A5h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Set External Flag SXF label SXF None 1 1 external flag pin and status bit Affects XF 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1100000 1 1 0 1 The XF pin and the XF status bit in status register ST1 are set to logic 1 XF may also be loaded by the LST1 and RXF instructions 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SXF pin and status bit are set to logic 1 4 183 TBLR Table Read Syntax Direct label TBLR dma Indirect label TBLR ind next ARP Operands 0 lt dma lt 127 0 lt next ARP lt 7 Execution PC 1 5 PC PFC 2 MCS ACC 15 0 gt If repeat counter z 0 Then pma addressed by Modify AR ARP and ARP as specified PFC 1 PFC repeat counter 1 repeat counter Else pma addressed by PFC dma Modify AR ARP and ARP as specified MCS gt PFC Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 0 1 1 0 0 Data Memory Address Indirect 0 1 0 1 1 0 0 See Section 4 1 Description The TBLR instruction transfers a word from
488. s 1 Cycles 4 54 Assembly Language Instructions Test Bit Specified by T Register Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example BI Oh Value in T register points to bit 14 of data word DP 240 or BI If current auxiliary register contains 7800h Before Instruction After Instruction Data Data Memory 4DC8h Memory 4DC8h 7800h 7800h 4 55 BLEZ Branch if Accumulator Less Than or Equal to Zero Syntax Operands Execution Encoding Description Words Cycles Example 4 56 label BLEZ ind next ARP 0 lt pma lt 65535 0 lt next ARP x 7 If ACC lt 0 Then pma Else PC 2 2 PC Modify AR ARP and ARP as specified Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the contents of the accumulator are less than or equal to zero Otherwise control passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric ad dress 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition
489. s to 0 PC 2 PC Constant x 2shift_ ACC If SXM 1 Then 32768 lt constant lt 32767 If SXM 0 Then 0 x constant lt 65535 Affected by SXM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 16 Bit Constant The left shifted 16 bit immediate value is loaded into the accumulator The shifted 16 bit constant is sign extended if SXM 1 otherwise the high order bits of the accumulator pastthe shift are setto zero Note that the MSB of the accumulator can be set only if SXM 1 and a negative number is loaded shift count is optional and defaults to zero 2 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable OF794h 8 SXM 1 Before Instruction After Instruction ACC 12345678h ACC OFFF79400h C C LALK OF794h 8 SXM 0 Before Instruction After Instruction ACC 12345678h ACC 0F79400h 4 89 LAR Load Auxiliary Register Syntax Operands Execution Encoding Description Words Cycles 4 90 Direct label LAR dma Indirect label LAR _ AR ind next ARP 0 lt dma lt 127 0 lt auxiliary register AR lt 7 0 lt next ARP lt 7 PC 1 PC dma gt auxiliary register AR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 0 1 1 0 wm o Data Memory Address Indirect See Section 4 1 E E ES The contents of the specified data memory addre
490. set 6 2 6 4 PR 3 10 PRD 3 10 prefetch counter 3 10 processors overview 1 4 Product Information Center ix product register 3 10 program bus 3 10 program control 5 22 program counter PC 3 10 3 35 3 43 program execution 5 38 program memory 3 17 address bus 3 10 program verify F 8 PS 2 4 PSHD 4 135 pulse programming F 8 PUSH 4 136 Index QIR 3 10 quality and reliability J 1 J 5 queue instruction register 3 10 R W 2 5 RAM BO 3 10 RAM B1 3 10 random access memory data only 3 10 data or program 3 10 RBIT F 12 RC 4 137 read only memory 3 10 READY 2 4 registers auxiliary 3 22 DRR 3 64 DXR 3 64 indirect addressing 3 23 memory mapped 3 22 serial port 3 63 reliability stress tests J 2 microcontroller tests J 5 microprocessor tests J 5 test environments J 2 types of tests J 3 repeat counter 3 10 repeat counter RPTC 3 53 reset 2 6 3 46 3 47 reset circuit 6 2 6 4 diagram 6 3 RET 4 138 RFSM 4 139 RHM 4 140 robotics 6 51 ROL 4 141 ROM 3 10 ROM code flowchart 2 ROM code media I 3 ROM codes I 1 1 3 ROM protect bit F 12 ROR 4 142 Index 9 Index ROVM 4 143 RPT 4 144 5 27 RPTC 3 10 RPTK 4 9 4 145 RS 2 6 RSR 3 11 RSXM 4 146 RTC 4 147 RTXM 4 148 RXF 4 149 SACH 4 150 SACL 4 151 SAR 4 152 SBLK 4 9 4 154 SBRK 4 9 4 155 SC 4 156 scaling 5 47 scaling shifter 3 30 second generation dev
491. signal Asserted low and valid only during CLKOUT1 low when the TMS320C2x has just completed a memory operation such as an instruction fetch or a data memory read write MSC can be used to generate a one wait state READY signal for slow memory RS 8 65 Reset input Causes the TMS320C2x to terminate execution and forces the program counter to zero When RS is brought to a high level execution begins at location zero of program memory RS affects various registers and status bits XF D11 56 External flag output latched software programmable signal Used for signaling other processors in multiprocessor configura tions or as a general purpose output pin Supply Oscillator Signals CLKOUT1 11 58 Master clock output signal CLKIN frequency 4 CLKOUT1 rises atthe beginning of quarter phase 3 Q3 and falls at the beginning of quarter phase 1 Q1 CLKOUT2 D10 57 A second clock output signal CLKOUT2 rises at the beginning of 2 Q2 falls at the beginning of quarter phase 4 Q4 10 61 10 62 2 23 16 35 Four 5 V supply pins tied together externally BN Three ground pins tied together externally X2 CLKIN F11 52 T Pin numbers apply to CER QUAD as well as to PLCC t Input Output High impedance state Output pin from the internal oscillator for the crystal If a crystal is not used this pin should be left unconnected Input pin to the internal oscillator from the crystal If crystal is not us
492. sists of five generations TMS320C1x TMS320C2x TMS320C3x TMS320C4x and TMS320C5x see Figure 1 1 The family expansion includes enhancements of existing generations and more powerful new generations of digital signal processors Many features are common among these generations Some specific features are added in each processor to provide different cost performance tradeoffs Software compati bility is maintained throughout the family to protect the user s investment in ar chitecture Each processor has software and hardware tools to facilitate rapid design This document discusses the TMS320C2x devices TMS320C25 a CMOS 40 MHz digital signal processor capable of twice the performance of the TMS320C1x devices TMS320C25 33 a CMOS 33 MHz version of the TMS32025 TMS320C25 50 a CMOS enhanced speed 50 MHz version of the TMS320C25 TMS320E25 a version of the TMS320C25 40 MHz with on chip ROM replaced by secure on chip EPROM TMS320C26 aversion ofthe TMS320C25 40 MHz with expanded confi gurable program data RAM TMS320C28 a version of the TMS320C25 40 MHz with expanded 8K word on chip ROM and an added power down mode Introduction General Description Figure 1 1 TMS320 Device Evolution 2 gt ovormz ov z 5 RN TMS320C50 003 TMS320C51 N N TMS320C53 TMS320C25 TMS320E25 TMS320C25 33 TMS320C25 50 TMS320C26 TMS320C28 TMS320C
493. sizers G 10 VSS 2 6 wait state generator 6 19 design 6 21 memory peripheral access 6 20 timing 6 22 Index 11 Index 1 2 6 ZAC 4 191 X2 CLKIN 2 6 ZALH 4 192 XDS 22 K 1 ZALR 4 193 ZALS 4 194 XOR 4 189 XORK 4 9 4 190 XSR 3 11 Index 12 Running Title Attribute Reference NE di lt JA NMr 4 3 XJFPr48E T I lt gt TMS320C2x Reference Card Phone Numbers TI Customer Response Center CRC Hotline 800 232 3200 TMS320 DSP Hotline 713 274 2320 TMS320 DSP Bulletin Board Service 713 274 2323 Instruction Symbols ymbol Meaning ARn Auxiliary Register ARO and AR1 are predefined assembler symbols equal to 0 and 1 respectively ARP Auxiliary register pointer B Bit code BR Branch address D Data memory address or indirect addressing control bits dma Data memory address Indirect direct addressing mode 1 indirect 0 direct ind Indirect address 0 O for 20 0 0O BRO BRO for C25 italics User defined terms K Immediate value PA Port address pma Program memory address K 13 Running Title Attribute Reference 5 Shift count Options Status Register STO Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARP ov OVM 1 INTM DP Status Register STI Bits 15 14 13 12t 11 10 9 8 7t 6t 5t 4 3 2 1 0 ARB TC SXM C 1 1 HM FSM FO TXM PM T O
494. ss Decoding Description Symbol Used in Value Figure 6 8 Propagation delay through the 74AS04 Propagation delay through the 74AS138 5 ns max H to 6 22 Wait State Generator The READY input of the TMS320C2x allows it to interface with memory and peripherals that cannot be accessed in a single cycle The number of cycles in a memory or I O access is determined by the state of the READY input If READY is high when the TMS320C2x samples the READY input the memory access ends at the next falling edge of CLKOUT1 If READY is low the memory cycle is extended by one machine cycle and all other signals remain valid Figure 6 9 shows a one wait state memory access Note that for on chip program and data memory accesses the READY input is ignored Refer to Hardware Interfacing to the TMS320C25for detailed information regarding wait state generation You can automatically generate one wait state by using the microstate com plete MSC signal The MSC output is asserted low during CLKOUT 1 low to indicate the beginning of an internal or external memory or I O operation see Figure 6 9 By gating MSC with the address and PS DS and or IS you can generate a one wait state READY signal Note that MSC is a valid signal only when CLKOUT1 is low see page A 44 A wait state generator is an alternative approach for generating wait states when interfacing with memories and peripherals In this design READY must be valid low
495. ss are loaded into the desig nated auxiliary register AR The LAR and SAR store auxiliary register instructions can be used to load and store the auxiliary registers during subroutine calls and interrupts If an auxiliary register is not being used for indirect addressing LAR and SAR en able the register to be used as an additional storage register especially for swapping values between data memory locations without affecting the con tents of the accumulator Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions 1 LAR Data Memory 522 ARO Example 2 LARP Data Memory 617 AR4 ARO DAT10 DP 4 Before Instruction 18 gt LAR AR4 Before Instruction 32h 617h Load Auxiliary Register LAR After Instruction Data 522 ARO 18h After Instruction Data Memory 32h 617 AR4 32h Note LAR inthe indirect addressing mode ignores any AR modifications if the AR specified by the instruction is the same as that pointed to by the ARP There fore in Example 2 AR4 is not decremented after the LAR instruction 4 91 LARK Load Auxiliary Register Immediate Short Syntax Operands Execution Encoding Description Words Cycles Example 4 92 label LARK AH constant 0 constant x 255 0 lt auxiliary register AR x 7 PC 1
496. ss than the shifted numerator is deter mined by the sign of the result both the numerator and denominator must be positive when you use the SUBC command Thus you must determine the sign of the quotient and compute the quotient with the absolute value of the numerator and denominator 5 57 Advanced Arithmetic Operations Integer and fractional division can be implemented with the SUBC instruction as shown in Example 5 34 and Example 5 35 respectively When you imple ment a divide algorithm it is important to know if the quotient can be repre sented as a fraction and the degree of accuracy to which the quotient is to be computed For integer division the absolute value of the numerator must be greater than the absolute value of the denominator For fractional division the absolute value of the numerator must be less than the absolute value of the denominator Example 5 33 Divide 33 by 5 Long Division 000000000000110 Quotient 0000000000000101 000000000100001 110 101 11 Remainder SUBC Method 32 HIGH ACC LOW ACC 0 mmen 0000000000000000 0000000000100001 1 Numerator is loaded into 10 1000000000000000 denominator is left shifted 15 and 10 0111111111011111 subtracted from subtrac traction is negative so discard the result and shift the ACC left one bit 0000000000000000 0000000001000010 2 2nd subtract produces negative an 10 1000000000000000 swer so discard
497. starting address lowest of the source block is defined by the second word of the instruction The starting ad dress of the destination block is defined by either the dma contained in the op code for direct addressing or the current AR for indirect addressing In the indirect addressing mode both the ARP and the current AR may be modified in the usual manner In the direct addressing mode dma is used as the des tination address for the block move but is not modified by repeated executions of the instruction Thus the contents of memory at the dma address will be the same as the contents of memory at the last pma address in a repeat se quence RPT or RPTK must be used with the BLKP instruction if more than one word is to be moved The number of words to be moved is one greater than the num ber contained in the repeat counter RPTC at the beginning of the instruction At the end of this instruction the RPTC contains zero and if using indirect ad dressing AR ARP will be modified to contain the address after the end of the destination block Note that source and destination blocks do not have to be entirely on chip or off chip Assembly Language Instructions Block Move From Program Memory to Data Memory BLKP The PC points to the instruction following BLKP after execution Interrupts are inhibited during a BLKP operation If the pin on the 5320 25 is low at the time of execution of this instruction and the program mem
498. state it resumes executing IDLE once it leaves the hold state The hold function on the TMS320C25 has two distinct operating modes A mode in which execution is suspended during assertion of HOLD and A TMS320C25 concurrent DMA mode in which the TMS320C25 contin ues to execute its program while operating from internal RAM or ROM thus greatly increasing throughput in data intensive applications 3 79 Multiprocessing and Direct Memory Access DMA 3 80 The operating mode is selected by the HM hold mode status register bit on the TMS320C25 The HOLD signal is pulled low as shown in the first part of Figure 3 48 When HM 1 the TMS320C25 halts program execution and en ters the hold state directly When HM 0 the processor enters the hold state directly as shown in Figure 3 48 if program execution is from external memory or if external data memory is being accessed If program execution is from internal memory however and if no external data memory accesses are required the processor enters the hold state externally but program execution continues internally This allows more efficient system operation be cause a program may continue executing while an external DMA operation is being performed Program execution ceases until HOLD is removed if the processor is in a hold state with HM 0 andan internally executing program requires an external ac cess or if the program branches to an external address Also if
499. ster provides the data memory address and the data is being manipulated by the CALU the contents of the auxiliary register may be manipulated through the ARAU See Figure 3 12 for an ex ample of indirect auxiliary register addressing The direct and indirect addres sing modes are described in detail in Section NO TAG When an immediate operand is used it is contained either within the instruc tion word itself or in the case of 16 bit immediate operands in the word follow ing the instruction opcode 3 26 Architecture Memory Organization 3 4 8 Memory to Memory Moves The TMS320C2x provides instructions for data and program block moves and for data move functions that efficiently utilize the configurable on chip RAM The BLKD instruction moves a block within data memory and the BLKP instruction moves a block from program memory to data memory When used with the repeat instructions RPT RPTK the BLKD BLKP instructions effi ciently perform block moves from on or off chip memory Implemented in on chip RAM the DMOV data move function on the TMS320C2x is equivalent to that of the TMS320C1x DMOV allows a word to be copied from the currently addressed data memory location in on chip RAM to the next higher location while the data from the addressed location is being operated upon in the same cycle for example by the CALU An ARAU opera tion may also be performed in the same cycle when using the indirect addres sing mode The DM
500. ster when it has finished performing its task and needs to be repro grammed or requires additional data to continue processing In a multiple slave configuration priority of each slave s task may be determined by tying the slave s signals to the appropriate 2 0 pin on the master TMS320C2x Hardware Applications Direct Memory Access DMA Figure 6 18 Direct Memory Access Using a Master Slave Configuration TMS320C2x TMS320C2x Master Slave XF HOLD BIO HOLDA INTO INT2 Master Data Memory RAM Master Program Memory ROM A PC environment presents another example of a potential direct memory ac cess scheme in which a system bus the PC bus is used for data transfer In this configuration either the master CPU or a disk controller may place data onto the system bus which can be downloaded into the local memory of the TMS320C2x Here the TMS320C2x acts more like a peripheral processor with multifunction capability In a speech application for example the master can load the TMS320C2x s program memory with algorithms to perform such tasks as speech analysis synthesis or recognition and fill the TMS320C2x s data memory with the required speech templates In another application ex ample the TMS320C2x can serve as a dedicated graphics engine Programs can be stored in TMS320C2x program ROM or downloaded via the system bus into program RAM Data can co
501. sters do not have separate instructions for storing them into RAM they are included in the status registers As shown in Figure 3 24 several bits in the status registers are reserved and read as logic 1s by the LST and LST1 instructions Figure 3 24 TMS320C2x Status Register Organization 11 10 8 7 6 5 4 3 2 1 O0 15 14 13 12 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The status register ST1 of the TMS320C26 uses one of the unused bits and the CNF bit of the TMS320C25 to define the four configuration modes as de 3 49 System Control scribed above The bits are named CNFO and CNF1 and can be set by the instruction CONF const where const is a number between 0 and This two bit constant is loaded into the two status register bits CNFO and CNF1 Some additional instructions or functions may affect the status bits as indi cated in Table 3 6 The bits can also be modified by the LST1 instruction and both are set to 0 by RESET If TMS320C26 designs are started by using the TMS320C25 as a base consider defining the mask for loading the status register ST1 with the instruction LST1 in such a way that the TMS320C26 is also configured as de sired Figure 3 25 shows the two status registers of the TMS320C26 All bits be sides the redefined CNFO CNF in the TMS320C25 and the new CNF1 bit are unchanged Figure 3 25 TMS320C26 Status Register Organization 15 14 111 8 7 6 5 4 3 2 1 0 13 12 0 9 15 14 13 12 8 7 6 5 4 3 2 1 0
502. struction After Instruction Data Data Memory 2404h Memory 2404h 96 96 STO 6E00h STO 2604h ST1 0580h ST1 0580h LARP AR4 AR4 3FFh LST Before Instruction After Instruction AR4 3FFh AR4 3FEh Data Data Memory 0 06 OCEO6h 1023 1023 STO OFC04h STO 0 06 ST1 0E780h ST1 0E780h LARP AR4 AR4 3FFh LST ed Before Instruction After Instruction AR4 3FFh AR4 3FEh Data Data Memory OEEO4h Memory OEEO4h 1023 1023 STO OEEO0h STO OEEO4h ST1 0F780h ST1 0F780h 4 99 LST1 Load Status Register ST1 Syntax Operands Execution Encoding Description Words 4 100 Direct label LST1 Indirect label LST1 ind next ARP 0 lt dma x 127 0 x next ARP lt 7 PC 1 PC dma gt status register ST1 ARB ARP Affects ARP ARB CNF TC SXM XF FO TXM and PM Affects C HM and FSM 5320 25 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 1 0 0 0 1 Data Memory Address Indirect 1 0 1 0 0 0 1 See Section 4 1 Status register ST1 is loaded with the data memory value The bits of the data memory value which are loaded into ARB are also loaded into ARP to facili tate context switching Note that if a next ARP value is specified via the indirect addressing mode the specified value is ignored LST1 is used to load status bits after interrupts and subroutine calls ST1 con tains these status bits ARB auxiliary register pointer buffer CNF RAM con fi
503. sync mode FSM bit provides continuous operation that once initiated requires no further frame synchronization pulses No minimum CLKR CLKX frequency fmin 0 Hz is required for serial port operation The bits pins and registers that control serial port operation are listed in Table 3 8 Availability of a function on a particular device is also indicated Table 3 8 Serial Port Bits Pins and Registers 3 64 Serial Port Bits Pins Registers TMS320C25 FO Format bit Yes TXM Transmit mode bit Yes FSM Frame synchronization mode bit Yes CLKX Transmit clock signal CLKR Receive clock signal DX Transmitted serial data signal DR Received serial data signal FSX Transmit framing synchronization signal FSR Receive framing synchronization signal Data transmit register Data receive register Transmit shift register Receive shift register The serial port uses two memory mapped registers the data transmit register DXR that holds the data to be transmitted by the serial port and the data re ceive register DRR that holds the received data see Figure 3 33 Both reg isters operate in either the 8 bit byte mode or 16 bit word mode and may be accessed in the same manner as any other data memory location Each regis ter has an external clock a framing synchronization pulse and associated shift registers Any instruction accessing data memory can be used to read from or write to these registers however the BLKD block move from
504. t When slower less costly EPROMs are used a simple flip flop circuit see sub section 6 2 2 for wait state generator design can be used to generate one or more wait states Figure 6 12 shows an EPROM interface with one wait state where Wafer Scale WS57C64F 12 8K x 8 bit EPROMs are interfaced to the TMS320C25 The WS57C64F 12 is the slowest member of the WS57C64F EPROM series but still meets the specifications for one wait state With slower EPROMs however data output turnoff can be slow and must be taken into consideration in the design The WS57C64F 12s are mapped at address 2000h Figure 6 13 provides the interface timing diagram Hardware Applications Interfacing Memories Figure 6 12 Interface of WS57C65F 12 to TMS320C25 TMS320C25 WS57C64F 12 DO D1 D2 D3 D4 D5 D6 D7 74AS138 Wait State Generator One Wait State 1kQ WS57C64F 12 6 23 Interfacing Memories Figure 6 13 Interface Timing of WS57C65F 12 to TMS320C25 CLKOUT1 NN F NL CLKOUT2 DTSTR REND E CU MEMSEL N READY tg 4 Table 6 4 summarizes the most critical timing parameters of the WS57C64F 12 interface to the TMS320C25 Table 6 4 Timing Parameters of WS57C64F 12 Interface to TMS320C25 Description Symbol Used in Figure 6 13 Address valid to MEMSEL low STRB low to DTSTR low TMS320C25 address valid to WS57C64F 12 dat
505. t Negate accumulator Normalize contents of accumulator OR with accumulator OR immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift Store low accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract Subtract from high accumulator Subtract from accumulator short immediate Subtract from low accumulator with sign extension suppressed Subtract from accumulator with shift specified by T register Exclusive OR with accumulator Exclusive OR immediate with accumulator with shift Zero accumulator Zero low accumulator and load high accumulator Zero low accumulator and load high accumulator with rounding Zero accumulator and load low accumulator with sign extension suppressed 20 22 MES 9 q parca m qu 21 217 2 CR 6 3x 0 XQ RO Me GO eere CODOMA BABA AAD A 4 ooo T These instructions are not included in the SMJ32010 instruction
506. t address 8000h Note that in Figure 6 7 R W is used to enable the 7445138 This prevents bus conflict from occurring if an attempt is made to write to the PROMs Figure 6 8 shows the timing for the circuit shown in Figure 6 7 READY goes high 10 ns worst case after the address has become valid Hardware Applications Figure 6 7 Interface of TBP38L165 35 to 5320 25 TMS320C25 1 10 Interfacing Memories TBP38L165 35 DO K2 D1 L3 D2 K3 D3 L4 p D4 K4 D5 L5 AS D6 5 07 7 K6 A8 L7 A9 ad A10 2445138 m K9 2 L10 3 4 H E MEMSEL 1 ko 45V 5 V 744820 K10 iko Jt1 74AS30 B8 H10 gt 1 74 504 MEMSTRB E2 9 D8 D 10 D9 11 D10 13 D11 e 14 D12 Bo 15 D13 16 D14 B3 17 D15 A3 B4 A4 B5 5 TBP38L165 35 6 6 17 Interfacing Memories Figure 6 8 Interface Timing of TBP38L 165 35 to TMS320C25 Address Decoding CLKOUT1 Nf CLKOUT2 4 ta SL STRB isu A t MEMSTRB gt t ats ty Ps TRN e 00 QUU tp ke MEMSEL t3 most critical timing parameters of the TBP38L165 35 interface with ad dress decoding to the TMS320C25 are summarized in Table 6 2 6 18 Hardware Applications Interfacing Memories Table 6 2 Timing Parameters of TBP38L 165 35 to TMS320C25 Addre
507. t flag 1 decrements auxiliary register NAR New auxiliary register control bit 1 loads new ARP ARP Auxiliary register pointer amat shi recane ono 6 _ ind next 04A00h constant shift 000028 K 16 Appendix Title Attribute Reference Running Title Attribute Reference Instruction Set Summary Continued Description 1 ADRKt ND ANDK APAC Add to auxiliary register short immediate 410 gt 1 1 AND immediate with accumulator with shift 2 2 1 1 Branch unconditionally 3 2 3 1 AND with accumulator Add P register to accumulator BANZ Branch on auxiliary register not zero 3 2 BBNZ Branch if TC bit 0 3 2 BBZ Branch if TC bit 0 3 2 BCH Branch on carry 3 2 BGEZ Branch if accumulator gt 0 3 2 BGZ Branch if accumulator gt 0 3 2 BIOZ 3 2 BIT 1 1 BITT 1 1 BLEZ Branch if accumulator lt 0 3 2 BLKD BLKP BLZ Branch if accumulator lt 0 3 2 BNC 3 2 NV 3 2 N 3 2 Branch on overflow 3 2 Branch to address specified by accumulator Branch on status 0 Test bit Test bit specified by T register Block move from data memory to data memory 4 2 Block move from program memory to data memory 4 2 Branch on no carry 00 Branch if no overflow 00 Branch if accumulator 0 00 lt BZ CALA CALL CMPL CMPR CNFD CNFP CONF4 DINT DMOV EINT FORT IDLE Branch if accumulator 0 3 2 Call subroutine indirect 3 1 Call subroutine
508. t the output of the accumulator perform shifts while the data is being transferred to the data bus for storage The contents of the accumulator remain unchanged SMJ320C26 scaling shifter has a 16 bit input connected to the data bus and a 32 bit output connected to the ALU The scaling shifter produces a left shift of 0 to 16 bits on the input data as specified in the instruction word The LSBs of the output are filled with zeroes andthe MSBs may be either filled with zeroes or sign extended depending upon the value of the SXM sign extension mode bit of status register STO 16 x 16 bit parallel multiplier timer memory control The SMJ320C26 has a 16 x 16 bit hardware multiplier which is capable of computing a signed or unsigned 32 bit product in a single machine cycle The multiplier has the following two associated registers A 16 bit Temporary Register TR that holds one of the operands for the multiplier and A 32 bit Product Register PR that holds the product Incorporated into the SMJ320C26 instruction set are single cycle multiply ac cumulate instructions that allow both operands to be fetched simultaneously The data for these operations may reside anywhere in internal or external memory and can be transferred to the multiplier each cycle via the program and data buses Four product shift modes are available at the Product Register PR output that are useful when performing multiply accumulate operati
509. t to scale BITLEN for proper RS232 timing In this case the time in th loop is 1 2 the length of the start bit 2 lac BITLEN 6 BITLEN is scaled and subk 171 decremented by 8 3 for bgz half_len BITLEN 2 wait LARK AR3 7 number of bits 1 LARK ARO 1 bit number 1 value CALL BIT wait for a bit BANZ WTBIT AR1 last bit LARK ARO 0O stop bit value CALL BIT wait for stop bit SAR AR2 MEMORY LAC MEMORY RS232 byte value LARP AR7 E RE ACC read value LAR 1 BANZ 5 wait for bit BIOZ ZEROBT AR2 test bit value 0 MAR 0 bit value LARP ARO MAR 0 dble bit val for next bit RET COPROCESSOR gt intface BIOZ READP BIO Input high RXF Set Ready Signal BIOZ READP2 BIO Input low B HIGHST H IN MEMORY PAO Read value SXF Reset Ready Signal LAC MEMORY read value RET H 5 1 checksum LARK AR6 0FFh AR6 gt checksum OK SUB CHECK BZ CHKOK checksum OK RXF 0 checksum error LARK AR6 00h AR6 gt 00 checksum error SAR AR6 MEMORY H OU MEMORY PAO OUTPUT PORT gt checksum flag RE Software Applications Processor Initialization KKK KKK Ck ck ck KKK RK KKK KK KKK KKK KKK KKK KKK KEK KK KKK KKK KKK KKK KKK KKK KKK KKKKK KKK KKK KKK KKK KK KKK Full Load lrlk Test Load1 lark sar Test_Load2 lrlk lrlk adrk lac and add sacl lac banz sach sblk ret
510. tents of the accumulator are greater than zero Otherwise control passes to the next instruction Note that no AR or ARP modification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition S 242p Cycle Timings for a Repeat Execution not repeatable BGZ PRG342 342 is loaded into the program counter if the accumulator is greater than or equal to zero Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Branch I O Status Equal to Zero BIOZ label BIOZ ind next ARP 0 lt pma lt 65536 0 lt next ARP x 7 If BIO 0 Then pma gt Else PC 2 gt PC Modify AR ARP and ARP as specified 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 See Section 4 1 Program Memory Address The current auxiliary register and ARP are modified as specified Control then passes to the designated program memory address pma if the BIO pin is low Otherwise control passes to the next instruction Note that no AR or ARP mod ification occurs if nothing is specified in those fields The pma can be either a symbolic or a numeric address BIOZ in conj
511. ter Load auxiliary register short immediate Load auxiliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate T REGISTER P REGISTER AND MULTIPLY INSTRUCTIONS Mnemonic and Description Words 16 Bit Opcode MSB LSB Add P register to accumulator Load high P register Load T register Load T register and accumulate previous product Load T register accumulate previous product and move data Load T register and store P register in accumulator Load T register and subtract previous product Multiply and accumulate Multiply and accumulate with data move Multiply with T register store product in P register Multiply and accumulate previous product Multiply immediate Multiply and subtract previous product Multiply unsigned Load accumulator with P register Subtract P register from accumulator Store high P register Store low P register Set P register output shift mode Square and accumulate Square and subtract previous product px n pde c ptc oc OFF oO oo LLLI U U uU uu 27002 DORPVUVOOUVUUNDU
512. tes the use of the configuration modes to utilize block BO as data and program memory while executing from its on chip program ROM Note that a more definitive example of the use of the TMS320C25 for adaptive Memory Locations Data 0 5 0000h 0005h Data 96 127 0060h 007Fh Data 512 767 0200h 02FFh Data 768 1023 0300h 03FFh Memory Locations Data 0 5 0000h 0005h Data 96 127 0060h 007Fh Prog 65280 65535 OFFOOh OFFFFh Data 768 1023 0300h 03FFh filtering is provided in subsection NO TAG 5 36 Software Applications Example 5 20 Configuring and Using On Chip Memory Management title ADAPTIVE FILTER def ADPFIR def THIS 128 TAP ADAPTIVE FIR FILTER USES ON CHIP MEMORY BLOCK BO FOR COEFFICIENTS AND BLOCK Bl FOR DATA SAMPLES THE NEWEST INPUT SHOULD BE IN MEMORY LOCATION X WHEN CALLED THE OUT
513. the IMR or IFR The TMS320C2x has built in mechanism for protecting multicycle instruc tions from interrupts If an interrupt occurs during a multicycle instruction the interrupt is not processed until the instruction is completed This mechanism also applies to instructions that become multicycle due to the READY signal In addition the device does not allow interrupts to be processed when an instruction is being repeated via the RPT or RPTK instructions The interrupt is stored in the IFR until the repeat counter RPTC decrements to zero and then the interrupt is processed Even if the interrupt is not used while the TMS320C2x is processing the RPT or RPTK the interrupt will still be latched by IFR and pending until RPTC decrements to zero If both the HOLD line and an interrupt go active during a multicycle instruction or a repeat loop the HOLD takes control of the processor at the end of the instruction or loop When HOLD is released the interrupt is acknowledged Interrupts cannot be processed between EINT and the next instruction in a program sequence For example if an interrupt occurs during an EINT instruc tion execution the device always completes EINT as well as the following instruction before the pending interrupt is processed This insures that a RET can be executed before the next interrupt is processed assuming that a RET instruction follows the EINT The state of the machine upon receiving an inter rupt may
514. the DP register with the seven LSBs of the Global Memory Allocation GREG 7 An 8 bit memory mapped register for allocating the size of the global Register memory space Internal Hardware Summary Table 3 1 TMS320C2x Internal Hardware Continued Instruction Register A 16 bit register used to store the currently executing instruction Interrupt Flag Register IFR 5 A6 bit flag register used to latch the active low external user interrupts 2 0 the internal interrupts XINT RINT serial port transmit re ceive and TINT timer interrupts The IFR is not accessible through software Interrupt Mask Register A 6 bit memory mapped register used to mask interrupts Microcall Stack MCS 15 0 A single word stack that temporarily stores the contents of the PFC while the PFC is being used to address data memory with the block move BLKD BLKP multiply accumulate MAC MACD and table read write TBLR TBLW and table read write TBLR TBLW instruction Multiplier MULT A 16 x 16 bit parallel multiplier Period Register PRD 15 0 A 16 bit memory mapped register used to reload the timer Prefetch Counter 15 0 A 16 bit counter used to prefetch program instructions The con tains the address of the instruction currently being prefetched It is up dated when a new prefetch is initiated The PFC is also used to address program memory when using the block move BLKP multiply accu mulate MAC MACD and table read write TBLR
515. the G or the E pin on the TMS320E25 high The selection of the pin determines the duration for which the outputs pins 98 01 of the TMS27C64 are in the high impedance state During this mode pins 07 00 on the TMS320E25 are in the high impedance state EPROM Protection and Verification F 3 EPROM Protection and Verification This section describes the code protection feature of the EPROM cell an inter nal mechanism protects the customer s code from being illegally copied by its competitors Table 3 shows the programming levels required for protecting the EPROM contents and verifying that protection Following the table individ ual paragraphs describe the function of the protect and verify modes Table G 3 TMS320E25 EPROM Protect and Protect Verify Mode Levels SIGNALT TMS320E25 PIN TMS27C64 PIN EPROM PROTECT PROTECT VERIFY I X MEM sex 94 _ ERN DNE 0 302820 LEGEND T Signal names in accordance with TMS27C64 TTL high level low level TTL Voc 5 0 25 V Vpp 12 5 0 25 V FAST 13 0 25 V SNAP Voc 1 6 0 25 V FAST or 6 5 0 25 V 5 X don t care PULSE low going TTL level pulse RBIT ROM protect bit F 3 1 EPROM Protection The EPROM protection mechanism is used to prevent an intentional or acci dental reading of the memory contents this guarantees security of all propri etary algorithms
516. the memory configuration after download DZ D6 Program Memory Data Memory 0 0 BO B1 B2 B3 0 1 BO B1 B2 B3 1 0 BO B1 B3 B2 PROGRAM LENGTH 1 RS232 transfer The fourth word is the program length to be transferred starting at block BO 0200h followed by B1 and B3 The 8 LSBs of the LENGTH word are com bined with bits DO D1 and D2 of the STATUS word to form the total program length up to 2K words in length The length does not include any of the con trol CHECKSUM or SYNCHRONIZATION words Figure 5 7 Building LENGTH From STATUS and PROGRAM LENGTH Words 5 14 STATUS PROGRAM LENGTH D gt T Word Bits D7 D6 D5 D4 D3 D2 D1 ODO E L3 L2 L1 LO PROGRAM WORD 2 RS232 transfers each The next LENGTH program words are then loaded into the internal RAM fol lowed by external data RAM at 0800h In the RS232 mode two words are transferred for each complete program word That is 4K word transfers will re sult in up to 2K program words received Also note that the maximum length can extend past the last address of block B3 into external data memory by 512 words In the RS232 mode the byte sequence is low to high CHECKSUM 2 RS232 transfers The CHECKSUM word is used to verify correct result of the transfer The checksum is defined as the lower 16 bits of the sum of all program words trans ferred The checksum does not include any control words or the final check sum sent by the host After completing t
517. they are the same they are both sign bits and the accumulator is left shifted to elimi nate the extra sign bit The AR ARP is modified as specified to generate the magnitude of the expo nent Itis assumed that AR ARP is initialized before the normalization begins The default modification of the AR ARP is an increment Multiple executions of the NORM instruction may be required to completely normalize a 32 bit number in the accumulator Although using NORM with RPT or RPTK does not cause execution of NORM to fall out of the repeat loop automatically when the normalization is complete no operation is performed for the remainder of the repeat loop Note that NORM functions on both posi tive and negative 2s complement numbers 1 4 127 Normalize Contents of Accumulator Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution orn me me n n Example 1 31 Bit Normalization LARP 1 LARK 1 0 LOOP ORM BBZ LOOP Example 2 15 Bit Normalization ARP 1 LARK 1 15 RPTK 14 NORM Use AR1 for exponent storage Clear out exponent counter One bit is normalized 1f TC 0 magnitude not found yet Use AR1 to store the exponent Initialize exponent counter 15 bit normalization is specified yielding a 4 bit exponent and l6 bit mantissa NORM automatically stops shifting when the first significant magnitude bit is
518. ting point arithmetic indexed addressing and extended precision arith metic are included in this section Overflow Management The TMS320C2x has four features that can be used to handle overflow man agement the branch on overflow conditions accumulator saturation overflow mode product register right shift and accumulator right shift These features provide several options for overflow protection within an algorithm A program can branch to an error handler routine on an overflow of the accu mulator by using the BV branch on overflow instruction or bypass an error handler by using the BNV branch if no overflow instruction These instruc tions can be performed after any ALU operation that may cause an accumula tor overflow The overflow mode is a useful feature for DSP applications This mode simu lates the saturation effect characteristic of analog systems When enabled any overflow in the accumulator results in the accumulator contents being re placed with the largest positive value 7FFFFFFFh if the overflowed number is positive orthe largest negative value 80000000h if negative The overflow mode is controlled by the OVM bit of status register STO and can be changed by the SOVM set overflow mode ROVM reset overflow mode or LST load status register instructions Overflows can be detected in software by testing the OV overflow bit in status register STO When a branch is used to test the overflow bit OV is automat
519. tion PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution OR DAT8 DP 8 or OR Where current auxiliary register contains 510982 Before Instruction After Instruction Data Data Memory OF000h 1032 1032 e oem C C 4 129 ORK OR Immediate With Accumulator With Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 130 label constant shift 16 bit constant 0 lt shift lt 15 defaults to 0 PC 4 25 PC 30 0 OR constant 2shift ACC 30 0 ACC 31 ACC 31 Not affected by SXM 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 16 Bit Constant The left shifted 16 bit immediate constant is ORed with the accumulator The resultis left in the accumulator Low order bits below and high order bits above the shifted value are treated as zeroes The corresponding bits of the accumu lator are unaffected Note that the most significant bit of the accumulator is not affected regardless of the shift code value 2 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE 2 2 Cycle Timings for a Repeat Execution not repeatable ORK OFFFFh 8 Before Instruction After Instruction 12345678h ACC 12FFFF78h Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Output Data to Port OUT Di
520. tion For application and other information refer to the descriptions of the IDLE instruction in Chapter 4 and the hold function in subsection 3 10 3 Chapter Title Attribute Reference External Memory I O Interface 3 7 External Memory and I O Interface The TMS320C2x supports a wide range of system interfacing requirements Data program and I O address spaces provide interfacing to memory and I O thus maximizing system throughput The local memory interface consists of A 16 bit parallel data bus 015 00 A 16 bit address bus 15 0 Data program and I O space select DS PS and IS signals and Various system control signals The R W read write signal controls the direction of the transfer and STRB strobe provides a timing signal to control the transfer The 5320 2 I O space consists of 16 input and 16 output ports These ports provide the full 16 bit parallel I O interface via the data bus on the device A single input or output operation using the IN or OUT instructions typically takes two cycles however when used with the repeat counter the operation becomes single cycle I O design is simplified by having I O treated the same way as memory I O de vices are mapped into the address space using the processor s external address and data buses in the same manner as memory mapped devices When addressing internal memory the data bus must be in the high imped ance stat
521. tiplier output 01 Output left shifted 1 place and zero filled 10 Output left shifted 4 places and zero filled 11 Output right shifted 6 places sign extended LSB bits lost The left shifts allow the product to be justified for fractional arithmetic The right shift by six bits has been incorporated to implement up to 128 multiply accumulate processes without the possibility of overflow occurring PM may also be loaded by LST1 instruction 1 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution not repeatable SPM 3 Product register shift mode 3 is selected causing all subsequent transfers from the product register to the ALU to be shifted to the right six places 4 165 SQRA Square Accumulate Previous Product Syntax Operands Execution Encoding Description Words Cycles Example 4 166 Direct Indirect 1 1 1 0 0 1 See Section 4 1 Direct label SQRA dma Indirect abel SQRA ind next ARP 0 lt dma lt 127 0 lt next ARP lt 7 PC 1 PC ACC shifted register gt dma T register dma x dma register Affects OV affected by PM and OVM Affects C 15 14 13 12 11 10 9 8 7 6 0 0 1 1 1 0 0 1 5 4 3 2 1 0 Data Memory Address The contents of the P register shifted as defined by the PM status bits are add ed to the accumulator The addressed data
522. to be performed with AR ARP and ARO When set bit 5 indicates that an increment is to be performed If bit 4 is set a decrement is to be performed Table 4 1 shows the correspondence of bit pattern and arithmetic operation Table 4 1 Indirect Addressing Arithmetic Operations 4 6 Arithmetic Operation 5 No operation on AR ARP AR ARP 1 gt AR ARP AR ARP 1 gt AR ARP Reserved AR ARP ARO gt AR ARP ARO AR ARP ARO gt AR A AR ARP ARO AR ARP reverse carry propagation ARP reverse carry propagation AR ARP AR RP 0 0 1 1 0 0 1 1 Bit 3 and bits 2 through 0 control the auxiliary register pointer ARP Bit 3 NAR determines if a new value is loaded into the ARP If bit3 1 the contents of bits 2 through 0 Y next ARP are loaded into the ARP If bit 3 0 the con tents of the ARP remain unchanged Assembly Language Instructions Memory Addressing Modes Table 4 2 shows the bit fields notation and operation used for indirect ad dressing For some instructions the notation in Table 4 2 includes a shift code for example 0 8 3 where 8 is the shift code and Y 3 Table 4 2 Bit Fields for Indirect Addressing Instruction Field Bits Operation 15 876543210 Eome comes rete ees E RARE ARO ARAR lt Opcode 511001 Y gt BRO Y AR ARP rcARO gt AR ARP Y gt ARP
523. to logic zero 4 149 SACH Store High Accumulator With Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 150 Direct label SACH shift Indirect abel SACH ind shift next ARP 0 lt dma lt 127 0 lt next ARP lt 7 0 lt shift lt 7 defaults to 0 PC 1 PC 16 MSBs of ACC x 28hift _ dma Not affected by SXM 5 14 13 1 10 9 8 7 6 5 4 3 2 1 0 1 2 11 Direct Shift EJ Data Memory Address 0 1 1 1 1 1 The SACH instruction copies the entire accumulator into a shifter where it shifts the entire 32 bit number anywhere from 0 to 7 bits on the TMS320C2x Itthen copies the upper 16 bits of the shifted value into data memory The accu mulator itself remains unaffected a Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution SACH DAT10 4 4 or SACH 4 If current auxiliary register contains 522 Before Instruction After Instruction ACC 4208001h ACC 4208001h C C Data Data Memory Memory 4208h 522 522 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Store Low Accumulator With Shift SACL Direct label SACL shift Indirect abel SACL ind shift next ARP 0 lt dma lt 127 0 next ARP lt 7 0 lt shift lt 7 defaults to 0
524. to perform numerical scaling bit extraction extended precision arithmetic and overflow prevention These shifters are connected to the output of the multiplier and the accumulator 3 5 2 ALU and Accumulator 3 30 The TMS320C2x 32 bit ALU and accumulator implement a wide range of arith metic and logical functions the majority of which execute in a single clock cycle Once an operation is performed in the ALU the result is transferred to the accumulator where additional operations such as shifting may occur Data that is input to the ALU may be scaled by the scaling shifter The ALU is a general purpose arithmetic unit that operates on 16 bit words taken from data RAM or derived from immediate instructions In addition to the usual arithmetic instructions the ALU can perform Boolean operations that make possible the bit manipulation required of a high speed controller One input to the ALU is always provided from the accumulator and the other input may be provided from the product register PR of the multiplier or the input scaling shifter that has fetched data from the RAM on the data bus After the ALU has performed the arithmetic or logical operations the result is stored in the accumulator The 32 bit accumulator See Figure 3 13 is split into two 16 bit segments for storage in data memory ACCH accumulator high and ACCL accumulator low Shifters at the output of the accumulator provide a left shift of 0 to 7 places on the TMS3
525. tor with shift LALK Load accumulator long immediate with shift absolute or 2s complement LRLK Load auxiliary register long immediate ORK OR immediate with accumulator with shift SBLK Subtract from accumulator long immediate with shift ab solute or 2s complement XORK Exclusive OR immediate with accumulator with shift 4 9 Memory Addressing Modes Example of long immediate addressing format ADLK 16384 2 Add to the accumulator the value 16384 with a shift to the left of two effectively adding 65536 to the contents of the accumulator The ADLK instruction uses the word following the instruction opcode as the immediate operand The instruction format for ADLK is as follows 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 16 Bit Constant 4 10 Assembly Language Instructions Instruction Set 4 2 Instruction Set The following sections list the symbols and abbreviations used in the instruc tion set summary and in the instruction descriptions The complete instruction set summary is organized according to function A detailed description of each instruction is listed in the instruction set summary 4 2 1 Symbols and Abbreviations Table 4 3 lists symbols and abbreviations used in the instruction set summary in Table 4 4 and the individual instruction descriptions 4 11 Instruction Set Table 4 3 Instruction Symbols Port address Accumulator Auxiliary register pointer buffer Auxiliary register n ARO AR1 asse
526. trol System Block Diagram G 13 TMS320C14 TLC32071 G 14 High Speed V 32 Bis and Multistandard Modem With the TLC320ACO01 AIC G 16 Applications Performance Requirements G 18 Video Signal Processing Basic System G 19 Typical Digital Audio G 19 sorse d bah ae dr RR VA ate bd a DR RI H 4 TMS320 ROM Code Flowchart 1 2 TMS320 Device K 3 TMS320 Development Tool K 4 xvii Tables PepTPPTTPTTPTTOTTTYT do bb O1 amp Q I a OIN xviii TMS320C2x Processors Overview 41 1 4 Typical Applications of the TMS320 Family 1 8 TMS320C2x Signal Descriptions 2 4 TMS320C2x Internal Hardware 3 9 TMS320C25 26 Memory 3 17 Memory Mapped Registers
527. truction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LARP 1 Any succeeding instructions will use auxiliary register AR1 for indirect addressing 4 93 LDP Load Data Memory Page Pointer Syntax Operands Execution Encoding Description Words Cycles Example 4 94 Direct Indirect 0 1 0 1 0 0 10 See Section 4 1 Direct abel LDP dma Indirect label LDP ind next ARP 0 dma x127 0 x next ARP x 7 PC 1 PC Nine LSBs of dma data page pointer register DP status bits Affects DP 15 14 13 12 11 10 9 8 7 6 0 1 0 1 0 0 1 0 5 4 3 2 1 0 Data Memory Address The nine LSBs of the contents of the addressed data memory location are loaded into the DP data memory page pointer register The DP and 7 bit data memory address are concatenated to form 16 bit data memory addresses The DP may also be loaded by the LST and LDPK instructions 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution LDP DAT127 DP 511 or LDP If current auxiliary register contains 65535 Before Instruction After Instruction Data Data Memory OFEDCh Memory OFEDCh 65535 65535 DP 1FFh DP ODCh Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Load Data Memory Page Pointer Immediate LDPK label LDPK constant 0
528. tructions that not included in the SMJ320C25 instruction set Table 1 Instruction Symbols Seo 4 bit field specifying a bit code Appendix Title Attribute Reference Running Title Attribute Reference 2 bit field specifying compare mode Data memory address field Format status bit Addressing mode bit Immediate operand field Port address PAO through PA 15 are predefined assembler symbols equal to 0 through 15 respectively 2 bit field specifying P register output shift code 3 bit operand field specifying auxiliary register 4 bit left shift code Internal RAM configuration bits 3 bit accumulator left shift field E 25 Running Title Attribute Reference Table 2 Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS NO INSTRUCTION BIT CODE WORDS 15 14 13 12 11 10 9 8 7 6 MNEMONIC DESCRIPTION Absolute value of accumulator Add to accumulator with shift Add to accumulator with carry Add to high accumulator Add to accumulator short immediate Add to low accumulator with sign extension suppressed Add to accumulator with shift specified by T register Add to accumulator long immediate with shift AND with accumulator AND immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator immediate short Load accumulator with shift specified by T register Load accumulator long immediate with shif
529. ts data to be valid no later than 2Q 23 ns after STRB goes low This is 27 ns for a TMS320C25 operating at 40 MHz The access times of the TBP38L165 35 are 35 ns maximum from address ta a and 20 ns maximum from chip enable ta s On the TMS320C25 address becomes valid a minimum of tsu a Q 12 ns 13 ns before STRB goes low Therefore the data appears on the data bus within 27 ns after STRB goes low as required by the 5320 25 When a read cycle is followed by a write cycle take care to avoid bus conflict Bus conflict also may occur when a TMS320C25 write cycle is followed by a memory read cycle In this case the TMS320C25 data lines must be in a high impedance state before the memory starts driving the data bus Interfacing Memories Figure 6 5 Direct Interface of TBP38L 165 35 to TMS320C25 6 14 o A e e gt H 74ALS04 TBP38L165 35 0 A1 A2 A3 4 5 A8 A9 A10 TBP38L165 35 Hardware Applications Interfacing Memories Figure 6 6 Interface Timing of TBP38L165 35 to TMS320C25 CLKOUT1 tash STRB N CAT CAT X BE idig K T 146 D15 DO Data In The most critical timing parameters of the TBP38L 165 35 direct interface to the TMS320C25 are summarized in Table 6 1 Table 6 1 Timing Parameters of TBP38L 165 35 Direct Interface to 5320
530. ts offers an extensive line of development tools for the 5320 2 generation of DSPs including tools to evaluate the performance of the processors generate code develop algorithm implementations and ful ly integrate and debug software and hardware modules The following products support development of TMS320C2x based applica tions Code Generation Tools Optimizing ANSI C compiler TMS320C25 only Macro assembler linker Digital filter design package System Integration and Debug Tools Simulator Evaluation module EVM In circuit emulator XDS 22 Analog interface board AIB2 Each TMS320C2x support product is described in the TMS320 Family Devel opment Support Reference Guide literature number SPRU011C In addition more than 100 TMS320 third party developers provide support products to complement TI s offering For more information on third party support refer to the 1145320 Third Party Reference Guide literature number SPRUO524 To request a copy of either document contact the TI Literature Response Center at 800 477 8924 For information on pricing and availability contact the nearest TI Field Sales Office or authorized distributor K 1 Device and Development Support Nomenclature K 1 K 2 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle Texas Instruments assigns prefixes to the part numbers of all TMS320 devices and support tools Each
531. ts privileged information against possible copy right violations The mechanism also prevents the EPROM contents from be ing read An adapter socket part number TMDX32701 20 provides the 68 pin to 28 pin conversion that is necessary when programming the TMS320E25 Refer to the data sheet in Appendix A This appendix describes erasure programming and verification and EPROM protection and verification The major topics are as follows Topic Page F1 Using the EPROM Programmer Adapter Socket F 2 F2 Programming and F 4 EPROM Protection and Verification F 12 F 1 Using the EPROM Programmer Adapter Socket F 1 Using the EPROM Programmer Adapter Socket Most EPROM programmers have a 28 pin DIP type socket for use with EPROM devices such as the TMS27C64 In order to use this type of program mer to program a TMS320 40 pin DIP or PLCC CLCC you must use a special adapter that converts the programmer socket into a socket that can accept a TMS320E25 device Figure F 1 shows an example of a PLCC CLCC type adapter socket so that you can see the socket for the device and the portion that plugs into the EPROM programmer Figure F 1 EPROM Programming Adapter Socket F 1 1 F 2 TMS320E25 device plugs m into this socket t Plugs into an EPROM programmer or the R bit programmer Supplying External Power
532. ual skews be tween the two signals For the purpose of interface timing tq c2 s can be as sumed to be 0 ns with respect to other signals on the TMS320C25 The same is also true of ta c1 9 and tw sL these timings can be assumed to be Q and 2Q respectively These relationships are accounted for in specifications and device testing In memory read operations the two key timings ta A and ts py are related byta A tsu A tw SL tsu p R However whentheworstcasety s specifica tions are used in this equation to generate an expression for ta A the result differs from the specification for tga in the data sheet Both the specification for ta a and tsy p R are tested explicitly on the device and guaranteed This again justifies the assumption of tw SL to be 2Q with respect to other signals on the device This is confirmed by the fact that if tw SL 2Q is used to calcu Hardware Applications Interfacing Memories late ta A consistency results in all of these related timings If an interface is designed where tsu D R is met but ta a is not met because of actual signal skews the interface is still guaranteed to function with the TMS320C25 The same is true but is not as likely if an interface is designed where ta A is met but tsu D R is not Thus even if tw sL is actually less than 20 meeting either ta A OF tsu D R S still sufficentto guarantee a valid memory cycle because both parameters are guaranteed independently
533. ulator Auxiliary Register Arithmetic ARAU A 16 bit unsigned arithmetic unit used to perform operations on auxilia Unit ry register data Auxiliary Register File ARO AR7 A register file containing eight 16 bit auxiliary registers ARO AR7 15 0 used for addressing data memory temporary storage or integer arith metic processing through the ARAU Auxiliary Register File Bus AFB 15 0 A 16 bit bus that carries data from the AR pointed to by the ARP Auxiliary Register Pointer 2 0 3 bit register used to select one of five or eight auxiliary registers Auxiliary Register Pointer ARB 2 0 A 3 bit register used to buffer the ARP Each time the ARP is loaded Buffer the old value is written to the ARB except during an LST load status register instruction When the ARB is loaded with an LST1 the same value is also copied into ARP Central Arithmetic Logic Unit CALU The grouping of the ALU multiplier accumulator and scaling shifter 0 D 15 0 A 16 bit bus used to route data Data Memory Address Bus DAB 15 0 A 16 bit bus that carries the data memory address Data Memory Page Pointer DP 8 0 A 9 bit register pointing to the address of the current page Data pages are 128 words each resulting in 512 pages of addressable data memory space some locations are reserved Direct Data Memory Address DRB 15 0 Bus A 16 bit bus that carries the direct address for the data memory which instruction is the concatenation of
534. ultiplying two 32 bit numbers to yield a 64 bit prod uct Words 1 Cycles Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution 4 123 MPYU Multiply Unsigned Example MPYU DAT16 DP 4 or MPYU If current auxiliary register contains 528 Before Instruction After Instruction Data Data Memory OFFFFh Memory OFFFFh 528 528 T OFFFFh 4 124 Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Example Negate Accumulator NEG label NEG None PC 1 PC ACC x 1 gt Affects OV affected by OVM Affects C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 70 0 0 1 0 0 0 1 1 The contents of the accumulator are replaced with its arithmetic complement 25 complement The OV bit is set when taking the NEG of 80000000h If OVM 1 the accumulator contents are replaced with 7FFFFFFFh If OVM 0 the result is 80000000h The carry bit C on the TMS320C2x is reset to zero by this instruction for all nonzero values of the accumulator and is set to one if the accumulator equals zero 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Before Instruction After Instruction ACC OFFFFF228h ACC o ODD8h C C 4 125 Operation Syntax Operands Execution Encoding Description
535. unction with the BIO pin can be used to testif a peripheral is ready to send or receive data Polling the BIO pin by using BIOZ may be preferable to an interrupt when executing time critical loops 2 Cycle Timings for a Single Instruction PI DI PIDE PE DI PE DE PR DI PR DE True Conditions Destination on chip RAM 2 2 242p Destination on chip ROM 3 3 342p Destination external memory 3 p 3 p 343p False Condition Destination anywhere 2 2 242p Cycle Timings for a Repeat Execution not repeatable BIOZ PRG64 If the BIO pin is active low then a branch to location 64 occurs 4 51 Test Bit Syntax Direct label bit code Indirect abel BIT ind bit code next ARP Operands 0 lt dma lt 127 0 x next ARP lt 7 0 lt bit code lt 15 Execution PC dma bit at bit address 15 bit code TC Affects TC Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct 1 0 0 1 Bitcode Data Memory Address Indirect 1 0 0 1 See Section 4 1 Description The BIT instruction copies the specified bit of the data memory value to the TC bitof status register ST1 Note thatthe BITT CMPR LST1 and NORM instruc tions also affect the TC bit in status register ST1 A bit code value is specified that corresponds to a certain bit address in the instruction as given by the fol lowing table Bit Code Bit Address IT 0 9 8 LSB 0 Ah E Ld 1 1 dx 0 2 1 101 3 11
536. upts INT 2 0 and the internal in terrupts RINT XINT and TINT Each interrupt is stored in the IFR until itis rec ognized and then automatically cleared by the IACK interrupt acknowledge signal or the RS reset signal The RS signal is not stored in the IFR No instructions are provided for reading from or writing to the IFR The 5320 2 has a memory mapped interrupt mask register IMR for masking external and internal interrupts The layout of the register is shown in Figure 3 30 A 1 in bit positions 5 through 0 of the IMR enables the corre sponding interrupt provided that INTM 0 The IMR is accessible with both read and write operations but cannot be read using BLKD When the IMR is read the unused bits 15 through 6 are read as 1s The lower six bits are used to write to or read from the IMR Note that RS is not included in the IMR and therefore the IMR has no effect on reset Architecture Interrupts Figure 3 30 Interrupt Mask Register IMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XINT RINT TINT INT2 INT1 INTO The INTM interrupt mode bit which is bit 9 of status register STO enables or disables all maskable interrupts INTM 0 enables all the unmasked inter rupts and INTM 1 disables these interrupts The INTM is setto 1 by the JACK interrupt acknowledge signal the DINT instruction or a reset This bit is reset to 0 by the EINT instruction Note that the INTM does not actually modify
537. ure provision for external wait states and capability for multiprocessor interface and direct memory access 1 8 Introduction Typical Applications The TMS320C2x has the flexibility to be configured to satisfy a wide range of system requirements This allows the device to be applied in systems currently using costly bit slice processors or custom ICs These are examples of such system configurations 1 A standalone system using on chip memory Parallel multiprocessing systems with shared global data memory or Host peripheral coprocessing using interface control signals Introduction Chapter 2 Pinouts and Signal Descriptions The TMS320C2x generation digital signal processors are available in one or more of four package types The TMS320C25 40 MHz version only is avail able in a 68 pin grid array PGA package The TMS320C25 33 MHz 40 2 and 50 MHz versions and the 5320 26 are available in a plastic 68 lead chip carrier PLCC package The TMS320E25 is packaged in a ce ramic surface mount 68 lead chip carrier CER QUAD package The TMS320C28 is available in a 80 pin quad flat package QFP All TMS320 packages conform to JEDEC specifications Conversion sockets that accept PLCC and CER QUAD packages and have a PGA footprint are commercially available For more information refer to Ap pendix NO TAG When using the XDS emulator refer to subsection 6 1 3 for user target design considerations The
538. ured See subsection NO TAG for a description of instruction execution using various memory configurations Architecture Memory Organization Additionally the TMS320C25 is internally equipped with 4K words of program mable ROM This on chip program ROM can be mask programmed at the fac tory with a customer s program The TMS320E25 provides a 4K word on chip EPROM Either on chip ROM or EPROM allows program execution at full speed without the need for high speed external program memory The use of this memory also allows the external data bus to be freed for access of external data memory Figure 3 4 TMS320C2x On Chip Data Memory From From Program Counter Auxiliary Registers or or From Data Page Pointer Prefetch Counter and Direct Memory Address v v 16 16 16 Block B2 32 x 16 Data RAM Data Prog Block B1 RAM 256 x 16 256 x 16 Block BO To Program Bus Data Bus 16 Memory Organization Figure 3 5 TMS320C26 On Chip Data Memory RAM 32 x 16 RAM 512 x 16 Block B2 Block B3 From Auxiliary Registers From Data Memory Page Pointer From Program Counter Data Data Prog Data Prog RAM 512 x 16 Block B1 Data Prog RAM 512 x 16 Block BO gt 16 16 To Program Bus Data Bus y Mapping of the first 4K word block of off chip on chip program memory is user selectable by means of the MP MC microprocessor microcomputer
539. ured as data RAM and at addresses OFFOOh to OFFFFh when configured as program RAM Block B1 always data RAM resides in pages 6 and 7 while block B2 resides in the upper 32 words of page 0 Note that the remainder of page 0 is composed of the memory mapped registers and internally reserved locations and pages 1 3 of the data memory map consist of internally reserved locations The internally reserved locations may not be used for storage and their contents are undefined when read See subsection 3 4 4 for further information on the memory mapped reg isters The on chip RAM is mapped into either the 64K word data memory or program memory space depending on the memory configuration see Figure 3 5 The CNFD CNFP instructions are used to configure block BO as either data or program memory respectively The BLKP block move from program memory to data memory instruction may be used to download program in formation to block BO when it is configured as data RAM Then a CNFP config ure block as program memory instruction may be used to convert it to program RAM see the code example in subsection NO TAG Regardless of the config uration you may still execute from external program memory Note that when accessing internal program memory external control lines remain inactive Reset configures all internal RAM as data Note that due to internal pipelining when the CNFD or CNFP instruction is used to remap RAM block BO there is a delay befo
540. value of the aux iary register contents before it is incremented decremented or indexed by ARO Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Assembly Language Instructions 1 SAR or SAR ARO ARO Data Memory 798 Example 2 LARP ARO ARO DAT30 DP 6 Store Auxiliary Register SAR If current auxiliary register contains 798 Before Instruction 37h 18h SAR 0 0 ARO Data Memory 1025 Before Instruction 401h After Instruction ARO 37h Data Memory 37h 798 After Instruction ARO 802h Data Memory 401h 1025 4 153 SBLK Subtract From Accumulator Long Immediate With Shift Syntax Operands Execution Encoding Description Words Cycles Example 4 154 label SBLK constant shift 16 bit constant 0 lt shift lt 15 defaults to 0 PC 2 5 PC ACC constant x 2shift ACC If SXM 1 Then 32768 lt constant lt 32767 If SXM 0 Then 0 lt constant lt 65535 Affects OV affected by OVM and SXM Affects C 15 14 13 2 1 10 9 8 7 6 5 4 2 1 0 16 Bit Constant The immediate field of the instruction is subtracted from the accumulator The result replaces the accumulator contents SXM determines whether the constant is treated as a signed 2s complement number or as an unsigned number The shift count is optional and defaults
541. ve internal Schmidt hysterisis Avoid slow rise and fall times to insure proper reset operation LLLLL Hardware Applications System Control Circuitry Figure 6 1 Powerup Reset Circuit TMS320C25 RS 45V A8 1MQ 2 C4 0 47 uF se DGND For proper system initialization the reset signal must be applied for at least three CLKOUT cycles that is 300 ns for a TMS320C25 operating at 40 MHz Upon powerup it can take from several to hundreds of milliseconds before the system oscillator reaches a stable operating state Therefore the powerup re set circuit should generate a low pulse on the reset line until the oscillator is stable that is 100 to 200 ms The voltage on the reset pin RS is controlled by the R4C4 network see Figure 6 1 Afterareset this voltage rises exponentially according to the time constant R1C1 as shown in Figure 6 2 The Schmidt Trigger inverter in this case could be a 74HC14 If a TTL device were used the low level input current lij would initially cause the voltage to rise faster than expected 6 3 System Control Circuitry Figure 6 2 Voltage TMS320C25 Reset Pin Voltage ye V Vcc 1 e7t T Vcc V1 to 0 ty Time The duration of the low pulse on the reset pin is approxim
542. will be initiated Otherwise bootloader control passes to modes 2 and 3 The BIOZ BIO pin test is made 36 2d cycles after reset but it is recommended that the BIO pin be initialized at power up or reset The value of dis the number of wait states used at global memory address 08000h In this case a read of memory loca tion 08000h is used as a delay and is part of the global EPROM download op tion However the status of that test is not used until after the BIO pin has been polled Each transfer of program data from the host is accomplished through a BIO and XF handshake with the host A data transfer is initiated by the host driving Software Applications Processor Initialization the BIO pin low When the BIO pin goes low the C26 inputs the data from port address zero and stores it in the currently available memory location The C26 then drives the XF pin high to indicate to the host that the data has been re ceived The C26 then waits for the BIO pin to go high before setting the XF pin low The low status of the XF line can then be polled by the host to indicate that the C26 is ready for another piece of data Example 5 3 Transfer Protocol BIO low at reset initiates parallel I O mode BIO high host requests to transmit low C26 indicates ready to receive BIO low host indicates data valid C26 inputs STATUS XF high C26 indicates word was received BIO high host requests to transmit low
543. words and contains a multi purpose bootloader See Subsection NO TAG and Appendix B Additional RAM is included mak ing the TMS320C26 ideal for many applications If the TMS320C26 is in microcomputer mode the address space from 0 to OFFFh is internal External program memory selected via PS Program Se lect can be used starting at address 1000h The missing space from 0100h to OFFFh which would correspond to the larger ROM of the C25 E25 is also reserved If one or more of the blocks BO B1 or B3 is configured as program memory the program address space from hexadecimal FAOOh to FFFFh is in ternally reserved for these blocks and can not access external program memory If all internal RAM blocks are configured as data memory a program address in the range FAO0h to FFFFh accesses external program memory The external data memory selected with DS Data Select always starts at address 800h 2048 decimal regardless of the configuration mode of the in ternal memory Because internal memory blocks BO B1 and B3 new are of different size the internal data memory blocks of the TMS320C26 reside in pages 0 and 4 to 15 while those of the TMS320C25 reside in pages 0 and 4 to 7 Table 3 2 shows both processors and their internal memory locations Program memory is also affected by the different block sizes and the results are given in Table 3 2 Architecture Memory Organization Table 3 2 TMS320C25 26 Memory Blocks Configur
544. xternal memory 3 p 3 p 343p 3 p False Condition Destination anywhere 2 2 242p 2 2 Cycle Timings for a Repeat Execution not repeatable BZ PRG102 102 is loaded into the program counter if the accumulator is equal to zero Assembly Language Instructions Syntax Operands Execution Encoding Description Words Cycles Call Subroutine Indirect CALA label CALA None 1 TOS ACC 15 0 gt PC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 01 4 1 0 0 0 4 0 0 1 0 0 The current program counter is incremented and pushed onto the top of the stack Then the contents of the lower half of the accumulator are loaded into the PC The carry bit on the TMS320C25 is unaffected by this instruction The CALA instruction is used to perform computed subroutine calls 1 Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Destination on chip RAM 2 2 Destination on chip ROM 3 3 Destination external memory 3 p 3 p 342p 3 p 3 p Cycle Timings for a Repeat Execution not repeatable 4 69 Call Subroutine Indirect Example CALA Before Instruction After Instruction PC 25h PC 83h ACC 83h ACC 83h Stack Stack 4 70 Assembly Language Instructions Call Subroutine CALL Syntax label CALL f ind next Operands 0 pma lt 65535 lt next ARP lt 7 Execution 2 TOS pma PC Encoding 6 5 4 3 2 1 0 15 14 13 12 11 10
545. y Concurrent DMA using an extended hold operation Instructions for adaptive filtering FFT and extended precision arithmetic Bit reversed indexed addressing mode for radix 2 FFT On chip clock generator Single 5 V supply Power down mode TMS320C28 only Device packaging 68 pin PGA TMS320C25 68 lead PLCC 5320 25 5320 26 and TMS320C28 68 lead CER QUAD TMS320E25 80 TMS320C28 Commercial and military versions available Typical Applications 1 3 Typical Applications The TMS320 family s unique versatility and realtime performance offer flexible design approaches in a variety of applications In addition TMS320 devices can simultaneously provide the multiple functions often required in those com plex applications Table 1 2 lists typical TMS320 family applications Table 1 2 Typical Applications of the TMS320 Family General Purpose DSP Graphics Imaging Instrumentation Digital Filtering 3 D Rotation Spectrum Analysis Convolution Robot Vision Function Generation Correlation Image Transmission Pattern Matching Hilbert Transforms Compression Seismic Processing Fast Fourier Transforms Pattern Recognition Transient Analysis Adaptive Filtering Image Enhancement Digital Filtering Windowing Homomorphic Processing Phase Locked Loops Waveform Generation Workstations Animation Digital Map Voice Mail Disk Control Secure Communications Speech Vocoding Servo Control Radar Processing Speech Recognitio
546. y Inc 1969 Hamming R W Digital Filters Englewood Cliffs NJ Prentice Hall Inc 1977 IEEE ASSP DSP Committee Editor Programs for Digital Signal Processing New York NY IEEE Press 1979 Jackson Leland B Digital Filters and Signal Processing Hingham MA Kluwer Academic Publishers 1986 Jones D L and Parks T W A Digital Signal Processing Laboratory Using the TMS32010 Englewood Cliffs NJ Prentice Hall Inc 1987 Lim Jae and Oppenheim Alan V Editors Advanced Topics in Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1988 Morris L Robert Digital Signal Processing Software Ottawa Canada Carleton University 1983 Oppenheim Alan V Editor Applications of Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1978 Oppenheim Alan V and Schafer R W Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1975 Oppenheim Alan V and Willsky A N with Young I T Signals and Systems Englewood Cliffs NJ Prentice Hall Inc 1983 Parks T W and Burrus C S Digital Filter Design New York NY John Wiley and Sons Inc 1987 Rabiner Lawrence R Gold and Bernard Theory and Application of Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1975 Treichler J R Johnson Jr C R and Larimore M G A Practical Guide to Adaptive Filter Design New York NY John Wiley and Sons Inc 1987 vii Related Documentatio
547. y instructions can be downloaded from external program memory into on chip RAM and then executed The TMS320C26 allows the DMOV function in all internal data memory blocks An FIR filter programmed with the MAC or MACD instructions can use the internal program RAM for storing the coefficients 3 83 General Description of the TMS320C28 3 12 General Description of the TMS320C28 3 84 The TMS320C28 is the newest member of the TMS320C2x family Like the TMS320C26 it is also processed in CMOS technology is capable of 100 ns instruction cycle time and is object code compatible with the TMS320C25 The enhancements of the TMS320C28 over the TMS320C25 are the larger on chip ROM 8K words and a new powerdown mode The TMS320C28 comes in an 80 pin QFP package that includes three new pins PDI PDACK WAKEUP to support the powerdown feature This mode decreases the current to about 100 uA compared with the 50 mA current in the TMS320C25 idle mode See Appendix C for more details about the TMS320C28 power down feature The TMS320C28 has more on chip memory 8K word ROM and 544 word RAM than the TMS320C26 The 8K word on chip ROM re duces system cost and allows large programs to execute at full speed from memory The large internal memory and the powerdown feature of the TMS320C28 allow you to build a single chip solution with all data and pro grams internal while conserving power Architecture 3 85 Chapter 4 Assembly Language
548. y Address The MAC instruction multiplies a data memory value specified by dma by a program memory value specified by pma It also adds the previous product shifted as defined by the PM status bits to the accumulator The data and program memory locations on the TMS320C25 may be any non reserved on chip or off chip memory locations If the program memory is block BO of on chip RAM then the CNF bit must be set to one Note that the upper eight bits ofthe program memory address should be set to OFFh in order to address BO program RAM and the upper six bits of dma should be set to 0 to address a location below 1024 When used in the direct addressing mode the dma cannot be modified during repetition of the instruction 4 111 Multiply Accumulate When the MAC instruction is repeated the program memory address con tained in the PC PFC is incremented by one during its operation This enables accessing a series of operands in memory MAC is useful for long sum of products operations since MAC becomes a single cycle instruction once the RPT pipeline is started Words 2 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Table in on chip RAM 3 44d Table in on chip ROM 4 54d Table in external memory 4 54d p Cycle Timings for a Repeat Execution Table in on chip RAM 2 n 2 2n nd 2 3 2n nd 2p 2 Table on chip ROM 3 n 3 2n nd 2 2
549. y OVM and SXM Affects C Encoding 15 14 13 12 1 10 98 7 6 5 4 3 2 1 0 Direct 0 0 1 Data Memory Address Indirect 0 0 1 See Section 4 1 Description The contents of the addressed data memory location are left shifted and sub tracted from the accumulator During shifting low order bits are zero filled High order bits are sign extended if SXM is high and zero filled if SXM is low The result is stored in the accumulator Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE DE PR DI PR DE Cycle Timings for a Repeat Execution Example SUB DAT80 DP 8 or SUB If current auxiliary register contains 1104 Before Instruction After Instruction Data Data 1104 1104 C C 4 175 SUBB Subtract from Accumulator with Borrow Syntax Direct label SUBB dma Indirect abel SUBB ind next ARP Operands 0 lt dma 3127 0 lt next ARP lt 7 Execution 1 PC dma C gt Affects C and OV affected by OVM 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Direct 9 1 0 0 14 1 1 1 Data Memory Address Indirect 1 0 0 1 1 1 1 See Section 4 1 Description The contents of the addressed data memory location and the value of the carry bit are subtracted from the accumulator The carry bit is then affected in the normal manner see subsection 3 5 2 E Encoding Words 1 Cycles Cycle Timings for a Single Instruction PI DI PI DE PE DI PE D

TMS320C2X FIXED-POINT DSP USER'S GUIDE

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