Home

Xilinx UG190 Virtex

1. in 1st FIFO DI lt 3 0 gt H i DO lt 3 0 gt DO lt 3 0 gt DO lt 3 0 gt WREN WREN Mode FULL ALMOST RDEN RDEN ALMOST t gt EMPTY WRCLKJ WRCLK EMPTY RDCLK FIFO 2 N 1 RDCLK FIFON gyprTy EMPTY INTCLK RDEN RDCLK ALMOST FULL gt FULL N x 8K x 4 FIFO ugi90 4 23 090407 Figure 4 26 Example Cascading Multiple FIFOs by Depth 156 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Built in Error Correction Connecting FIFOs in Parallel to Increase Width As shown in Figure 4 27 the Virtex 5 FPGA FIFO36 can be connected to add width to the design CLB logic is used to implement the AND OR gates All the FIFO AFULL signals must be ORed together to created the output AFULL signal and all the FIFO EMPTY signals must be ORed together to created the output EMPTY signal The maximum frequency is limited by the logic gate feedback path 512 x 144 FIFO gt DIN lt 71 0 gt DOUT lt 71 0 gt WREN RDEN RDEN WRCLK WRCLK EMPTY ea EMPTY RDCLK RDCLK FIFO 41 AFULL DIN lt 71 0 gt I l DOUT lt 71 0 gt l I DOUT lt 143 72 gt DIN lt 143 72 gt DOUT lt 71 0 gt DIN lt 71 0 gt WREN WREN RDEN WRCLK RDCLK FIFO 2 AFULL EMPTY AFULL ug190_4 24 012706 Figure 4 27 Example
2. IREE Veco VREF Termination Type Output Input Input Output Input LVTTL N R N R N R LVCMOS330 N R N R N R LVDCI 33 0 N R Series N R HSLVDCI 33 0 3 3 3 3 Vcco 2 Series N R PCIX N R N R N R PCI33 3 0 N R N R N R PCI66 30 N R N R N R LVDS 25 N R N R N R LVDSEXT 25 N R N R N R HT 25 N R N R N R RSDS 25 0 N R N R N R BLVDS 25 N R N R N R Note 2 LVPECL 25 N R N R N R SSTL2_I 1 25 N R N R SSTL2_II 1 25 N R N R DIFF_SSTL2_I N R N R N R DIFF SSTL2 II 2 5 N R N R N R IVCMOgS5 NR NR NR LVDCI 25 N R Series N R HSLVDCI 25 Veco 2 Series N R LVDCI_DV2_25 N R Series N R SSTL2 I DCI 2 5 1 25 N R Split SSTL2 II DCI 1 25 Split Split SSTL2 II T DCI 1 25 N R Split DIFF SSTL2 I DCI N R N R Split DIFF SSTL2 II DCI N R Split Split 296 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Table 6 39 WO Compatibility Continued Rules for Combining I O Standards in the Same Bank Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com iG Stantiard Veco VREF Termination Type Output Input Input Output Input HSTL III 18 1 08 N R N R HSTL IV 18 1 08 N R N R HSTL I 18 0 9 N R N R HSTL II 18 0 9 N R N R DIFF HSTL I 18 N R N R N R Note 2
3. DI2 o DPRAM64 32 A5 rn SPRAM64 32 A6 A4 OSRL32 WE C gt CIN UG190_5_03_041006 Figure 5 3 Diagram of SLICEM Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 173 Chapter 5 Configurable Logic Blocks CLBs XILINX COUT Reset Type o Sync o Async OFF DLATCH o p DINT B INITO CE nSRHIGH I ck BSRLOW dq j ot SR REV SRL CE DD CLK D gt cd C IN UG190 5 04 032606 Figure 5 4 Diagram of SLICEL Each CLB can contain zero or one SLICEM Every other CLB column contains a SLICEMs In addition the two CLB columns to the left of the DSP48E columns both contain a SLICEL and a SLICEM 174 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Slice Configurations CLB Overview Table 5 1 summarizes the logic resources in one CLB Each CLB or slice can be implemented in one of the configurations listed Table 5 2 shows the available resources in
4. Symbol Description Setup Hold Ticrick TICKCF1 CE1 pin Setup Hold with respect to CLK Tisrck TICKSR SR REV pin Setup Hold with respect to CLK Tipock Tiockp D pin Setup Hold with respect to CLK Combinatorial Tipi D pin to O pin propagation delay no Delay Sequential Delays TIpLo D pin to O1 pin using flip flop as a latch without Delay Ticko CLK to Q outputs TicE10 CE1 pin to Q1 using flip flop as a latch propagation delay Tro SR REV pin to OO TO out Note The DDLY timing diagrams and parameters are identical to the D timing diagrams and parameters www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY Input Output Delay Element IODELAY Every I O block contains a programmable absolute delay element called IODELAY The IODELAY can be connected to an ILOGIC ISERDES or OLOGIC OSERDES block or both IODELAY is a 64 tap wraparound delay element with a calibrated tap resolution See the Virtex 5 FPGA Data Sheet It can be applied to the combinatorial input path registered input path combinatorial output path or registered output path It can also be accessed directly in the fabric IODELAY allows incoming signals to be delayed on an individual basis The tap delay resolution is varied by selecting an IDELAYCTRL reference clock from the range specified in the Virtex 5 FPGA Data Sheet The IODELAY resource can function as IDELAY OD
5. Attribute Value Default Value Description IDELAY_TYPE String DEFAULT DEFAULT Sets the type of tap delay line Default delay is FIXED or used to guarantee zero hold times fixed delay is VARIABLE used to set a static delay value and variable delay is used to dynamically adjust the delay value IDELAY_VALUE Integer 0 to 63 0 Specifies the fixed number of delay taps in fixed mode or the initial starting number of taps in variable mode input path ODELAY_VALUE Integer 0 to 63 0 Specifies the fixed number of delay taps output path HIGH PERFORMANCE MODE Boolean FALSE TRUE When TRUE this attribute reduces the output TRUE jitter The difference in power consumption is quantified in the Xilinx Power Estimator tool SIGNAL PATTERN String DATA DATA The SIGNAL PATTERN attribute causes the CLOCK timing analyzer to account for the appropriate amount of delay chain jitter in the data or clock path REFCLK FREQUENCY Real 190 0 to 200 IDELAYCTRL reference clock frequency MHz 210 0 DELAY SRC String I O IO or DATAIN I IODELAY chain input is IDATAIN DATAIN O IODELAY chain input is ODATAIN IO IODELAY chain input is IDATAIN and ODATAIN controlled by T DATAIN IODELAY chain input is DATAIN IDELAY TYPE Attribute The IDELAY TYPE attribute sets the type of delay used The attribute values are DEFAULT FIXED and VARIABLE When set to DEFAULT the zero hold time delay element is selected This delay element
6. IOB Vrr 075V Vq 0 75V IOB l DIFF HSTL Il DIFF HSTL Il 500 509 D C Zo DJ 1 l l Vrr 0 75V Vy 0 75V DIFF HSTL II DIFF HSTL Il 500 500 D C Zo P4 l DIFF HSTL II l DIFF HSTL Il l l l l z ug190_6_45_020306 Figure 6 46 Differential HSTL 1 5V Class II Bidirectional Termination 254 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Figure 6 47 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with bidirectional DCI termination DCI IOB IOB Veco 1 5V Veco 15V DIFF HSTL II DCI DIFF HSTL II DCI 2Rypp 2Zg 1002 DR yap 2Zo 1000 D4 40O 4 _x 2Rypn 2Zg 1000 2Rypy 2Zg 1000 DIFF HSTL Il DCI DIFF HSTL Il DCI b 92 4 Ed Veco 1 5V DIFF HSTL Il DCI Yoga 15V DIFF HSTL II DCI 2Rygp 2Zo 1002 2Rypp 2Zg 1002 2Rypn 2Zg 1000 2Rypy 2Zg 1002 ug190_6_46_020306 Figure 6 47 Differential HSTL 1 5V Class II DCI Bidirectional Termination Table 6 18 lists the differential HSTL Class II DC voltage specifications Table 6 18 Differential HSTL Class Il DC Voltage Specifications Min Typ Max Vcco 1 40 1 50 1 60 VTT Veco x 0 5 Vin DC 0 30 Veco 0 30 Vorrr DC 0 20 Veco 0 60 Vem DC
7. Parameter Function Signal Description Setup and Hold Relative to Clock CLK Trxck Setup time before clock edge Treky Hold time after clock edge Tnpck pi Data inputs DI Time before after WRCLK that D1 must be stable Treko pi TRCCK_RDEN Read enable RDEN Time before after RDCLK that RDEN must be TRCKC RDEN stable Tncck wREN Write enable WREN Time before after WRCLK that WREN must be TRCKC WREN stable Clock to Out Delays Tncko po Clock to data output DO Time after RDCLK that the output data is stable at the DO outputs of the FIFO The synchronous FIFO with DO REG 0 is different than in multirate mode Tgcko AEMPTYO Clocktoalmostempty AEMPTY Time after RDCLK that the Almost Empty signal is output stable at the ALMOSTEMPTY outputs of the FIFO TRCKO_AFULL Clock to almost full AFULL Time after WRCLK that the Almost Full signal is output stable at the ALMOSTFULL outputs of the FIFO TrcKo EMPTY Clock to empty output EMPTY Timeafter RDCLK that the Empty signal is stable at the EMPTY outputs of the FIFO TreKo_ FULL Clock to full output FULL Time after WRCLK that the Full signal is stable at the FULL outputs of the FIFO TRCKO_RDERR Clock to read error RDERR Time after RDCLK that the Read Error signal is output stable at the RDERR outputs of the FIFO TRCKO_WRERR Clock to write error WRERR Time after WRCLK that the Write Error signal is output stable at the WRERR outputs of the FIFO TrcK
8. 0 0 00005 170 Chapter 5 Configurable Logic Blocks CLBs CLB OVetview ereer reysni jaunen au bees hs She n CR Vi ee 171 Slice Description doteseusatLc n d ate rcu E pP 172 CLB Slice Configurations sese eia entau eaaa saai hh hn 175 Look Up Table GU Wis 4 dice der ore iter er deed cane ER cr eee 176 Storage Elements 4e verir b rer ead PEG ede eee E WR a 176 Distributed RAM and Memory Available in SLICEM only esses 178 Read Only Memory ROM lisse Hn 188 Shift Registers Available in SLICEM only 1 6 6 0 cece cece eee eee 188 Multiplexers s ivweneph ie seaweed Pe nexu e oe ee el 193 Designing Large Multiplexers 0 6 0 ne 194 Fast Lookahead Carry Logic 1 0 0 0 cece cece cece ee cee eee e eens 196 CLB Slice Timing Models ssec e beer en 198 General Slice Timing Model and Parameters 00 00000 e eee 199 Timing Parameterss 5 2 cad eed ed ee bed che Ped eed cesa quede d 200 Timing Characteristics 52er ps reru RE 3 E ER RR RE RYE Rr EE 201 Slice Distributed RAM Timing Model and Parameters Available in SLICEM only 202 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Distributed RAM Timing Parameters nuusan sannan rrun rrara n rrr 203 Distributed RAM Timing Characteristics n a asunu ects 204 Slice SRL Timing Model and Parameters Available in SLICEM only 205 Slice SRL Timing Paramet
9. all CLBs Table 5 1 Logic Resources in One CLB Slices LUTs Flip Flops p Distributed RAM Shift Registers 2 8 8 2 256 bits 128 bits Notes 1 SLICEM only SLICEL does not have distributed RAM or shift registers Table 5 2 Virtex 5 FPGA Logic Resources Available in All CLBs Device CLB Array Number of I Maximum Shift Number of Row x Column 6 Input LUTs Distributed RAM Kb Register Kb Flip Flops XC5VLX2OT 60 x 26 12 480 210 105 12 480 XC5VLX30 80 x 30 19 200 320 160 19 200 XC5VFX30T 80 x 38 20 480 380 190 20 480 XC5VLX30T 80 x 30 19 200 320 160 19 200 XC5VSX35T 80 x 34 21 760 520 260 21 760 XC5VLX50 120 x 30 28 800 480 240 28 800 XC5VLX50T 120 x 30 28 800 480 240 28 800 XC5VSX50T 120 x 34 32 640 780 390 32 640 XC5VFX70T 160 x 38 44 800 820 410 44 800 XC5VLX85 120 x 54 51 840 840 420 51 840 XC5VLX85T 120 x 54 51 840 840 420 51 840 XC5VSX95T 160 x 46 58 880 1 520 760 58 880 XC5VFX100T 160 x 56 64 000 1 240 620 64 000 XC5VLX110 160 x 54 69 120 1 120 560 69 120 XC5VLX110T 160 x 54 69 120 1 120 560 69 120 XC5VFX130T 200 x 56 81 920 1 580 790 81 920 XC5VTX150T 200 x 58 92 800 1 500 750 92 800 XC5VLX155 160 x 76 97 280 1 640 820 97 280 XC5VLX155T 160 x 76 97 280 1 640 820 97 280 XC5VFX200T 240 x 68 122 880 2 280 1140 122 880 XC5VLX220 160 x 108 138 240 2 280 1140 138 240 XC5VLX220T 160 x 108 138 240 2 280 1140 138 240 XC5VSX240T 240 x 78 149 760 4 200 2100 149 760 XC5VTX240T 240 x 78 149 760 2 400 1200 149 760 XC5VLX330 240 x
10. Vper 0 75V IOB IOB 2Rygp 2Zo 1002 HSTL_I_DCI HSTL_I_DCI D1 Q ED a Vper 0 75V 2Rypy 2Zg 1002 L LS ugi 90 6 38 030206 Figure 6 39 HSTL Class I Termination Table 6 15 lists the HSTL Class I DC voltage specifications Table 6 15 HSTL Class I DC Voltage Specifications Min Typ Max Veco 1 40 1 50 1 60 Vas 0 68 0 75 0 90 Vos B Veco x 05 VH V er 0 1 a E Vir Vrer 0 1 Vou Veco 04 P Yr E z 0 4 Top at Voy mA 8 E Tor at Vor mA 8 Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Virtex 5 FPGA User Guide www xilinx com 249 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Differential HSTL Class Figure 6 40 shows a sample circuit illustrating a valid termination technique for differential HSTL Class I 1 5V with unidirectional termination External Termination 7 Va 0 75V IOB IOB DIFF_HSTL_I 509 k x DIFF_HSTL_I Vr 0 75V DIFF_HSTL_I 500 ugi 90 6 39 030206 Figure 6 40 Differential HSTL 1 5V Class I Unidirectional Termination Figure 6 41 shows a sample circuit illustrating a valid termination technique for differential HSTL Class I 1 5V with unidi
11. Attribute Name Type Values Default Notes EN ECC WRITE Boolean TRUE FALSE FALSE Set to TRUE to enable ECC encoder EN ECC READ Boolean TRUE FALSE FALSE Set to TRUE to enable ECC decoder DO REG 1 bit Binary 0 1 0 Enables register mode or latch mode Table 4 24 FIFO FIFO36_72 Attributes Attribute Name Type Values Default Notes EN_ECC_WRITE Boolean TRUE FALSE FALSE Both attributes must be set to TRUE to enable ECC functionality in a EN_ECC_READ Boolean TRUE FALSE FALSE FIFO36_72 1 bit Enables register mode or latch mode DO_REG Binar 0 1 1 See Table 4 17 for details on multirate y and synchronous FIFOs When set to TRUE ties WRCLK and RDCLK together EN SYN Boolean TRUE FALSE FALSE When set to TRUE FWFT must be FALSE When set to FALSE DO REG must be 1 Setting determines the difference 9 bit between EMPTY and ALMOST EMPTY OFFSET Hex See Table 4 19 See Table 4 19 ALMOST EMPTY conditions Must be set using hexadecimal notation Setting determines the difference ALMOST FULL OFFSET TP l eetis ccc illad Pree E ULL ond ALMOST PULL Hex conditions Must be set using hexadecimal notation When set to TRUE the first word FIRST WORD FALL THROUGH Boolean TRUE FALSE FALSE WZitten into the empty FIFO36 72 appears at the FIFO36 72 output without RDEN asserted Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 163 Chapter 4 Block RAM XILINX ECC Modes of Operat
12. Tgocko o Tsccko_o iva ENSURE O l l l md Ll at l0 Begin l1 UG190 1 14 032306 Figure 1 14 Asynchronous Mux Timing Diagram In Figure 1 14 e The current clock is from IO e Sisactivated High e The Clock output immediately switches to I1 e When Ignore signals are asserted High glitch protection is disabled www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 Global Clocking Resources XILINX BUFGMUX_VIRTEX4 with a Clock Enable A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to choose between the incoming clock inputs If needed the clock enable is used to disable the output Figure 1 15 illustrates the BUFGCTRL usage design example and Figure 1 16 shows the timing diagram IGNORE1 GND 4 CE CE1 BUFGMUX_VIRTEX4 CE 2 91 Design Example n O O 10 Io S S0 GE pe anp IGNOREO ugi90 1 15 032206 Figure 1 15 BUFGMUX VIRTEXA with a CE and BUFGCTRL 1 2 3 10 SS ee 0000 0 o peto p 000 o pot m I I I I Hol I NS AMNES INNEN 1 S TBCCCK_CE CE lt TBccko o pm TBCcCKO O NN rire oe otf Lif TES Leder d M at 10 Begin 11 Clock Off ug190_1_16_040907 Figure 1 16 BUFGMUX_VIRTEX4 with a CE Timing Diagram In Figure 1 16 Virtex 5 FPGA User Guide At time event 1 output O uses input I0 Before time event 2 S is asserted Hig
13. LVCMOS Specific Guidelines for I O Supported Standards Note V is any voltage from OV to Voco ug190 6 27 022806 Figure 6 29 LVCMOS Bidirectional Termination Table 6 6 details the allowed attributes that can be applied to the LVCMOS33 and LVCMOS25 I O standards Table 6 6 Allowed Attributes for the LVCMOS33 and LVCMOS25 I O Standards Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS25 LVCMOS25 LVCMOS25 DRIVE UNUSED 2 4 6 8 12 16 24 2 4 6 8 12 16 24 SLEW UNUSED FAST SLOW FAST SLOW Table 6 7 details the allowed attributes that can be applied to the LVCMOS18 and LVCMOS15 I O standards Table 6 7 Allowed Attributes for the LVCMOS18 and LVCMOS15 I O Standard Primitives Attributes IBUFABUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS15 LVCMOS15 LVCMOS15 DRIVE UNUSED 2 4 6 8 12 16 2 4 6 8 12 16 SLEW UNUSED FAST SLOW FAST SLOW Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 239 Chapter 6 SelectlO Resources XILINX Table 6 8 details the allowed attributes that can be applied to the LVCMOS12 I O standard Table 6 8 Allowed Attributes for the LVCMOS12 I O Standard Primitives Attributes IBUFABUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS12 LVCMOS12 LVCMOS12 DRIVE UNUSED 2 4 6 8 2 4 6 8 SLEW UNU
14. IDELAYCTRL Locations IDELAYCTRL modules exist in every I O column in every clock region An IDELAYCTRL module calibrates all the IDELAY modules within its clock region See Global and Regional Clocks in Chapter 1 for the definition of a clock region Figure 7 17 illustrates the relative locations of the IDELAYCTRL modules Virtex 5 FPGA User Guide www xilinx com 335 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX Left I O Center I O Right I O Column Column Column 1 Clock Region IDELAYCTRL ug190_7_12_041206 Figure 7 17 Relative Locations of IDELAYCTRL Modules IDELAYCTRL Usage and Design Guidelines This section describes using the IDELAYCTRL modules design guidelines and recommended usage in Virtex 5 devices Instantiating IDELAYCTRL Without LOC Constraints When instantiating IDELAYCTRL without LOC constraints the user must instantiate only one instance of IDELAYCTRL in the HDL design code The implementation tools auto replicate IDELAYCTRL instances throughout the entire device When IDELAYCTRL instances are replicated to clock regions but not used the extra instances are trimmed out of the design automatically by the ISE software The signals connected to the RST and REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the corresponding input ports of the replicated IDELAYCTRL instances There are two special cases 1 When the RDY port is ignor
15. UG190 5 05 071207 Figure 5 5 Register Latch Configuration in a Slice of synchronous SYNC or asynchronous ASYNC set reset SRTYPE cannot be set individually for each storage element in a slice Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com Chapter 5 Configurable Logic Blocks CLBs XILINX The initial state after configuration or global initial state is defined by separate INITO and INIT1 attributes By default setting the SRLOW attribute sets INITO and setting the SRHIGH attribute sets INIT1 Virtex 5 devices can set INITO and INIT1 independent of SRHIGH and SRLOW The configuration options for the set and reset functionality of a register or a latch are as follows e No setor reset e Synchronous set e Synchronous reset e Synchronous set and reset e Asynchronous set preset e Asynchronous reset clear e Asynchronous set and reset preset and clear Distributed RAM and Memory Available in SLICEM only Multiple LUTs in a SLICEM can be combined in various ways to store larger amount of data The function generators LUTs in SLICEMs can be implemented as a synchronous RAM resource called a distributed RAM element RAM elements are configurable within a SLICEM to implement the following e Single Port 32 x 1 bit RAM e Dual Port 32 x 1 bit RAM e Quad Port 32 x 2 bit RAM e Simple Dual Port 32 x 6 bit RAM e Single Port 64 x 1 bit RAM e Dual Port 64 x 1 bit RAM e Q
16. l l E UG190 5 09 050506 Figure 5 9 Distributed RAM RAM64X1D If two dual port 64 x 1 bit modules are built the two RAM64X1D primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 64 x 2 bit dual port distributed RAM 182 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview RAM64X1Q psc eR CUM E l a mu DID s 0X ADDRD DI6 1 Registered l bo y Output WCLK l e RAM gt WE Optional l l l l I DOC l ADDRC Registered l Output l d Optional l l l DOB l ADDRB l Registered l Output l l l gt Optional l l l l l DOA l l ADDRA Registered l Output l d Optional l l ug190_5_10_032706 Figure 5 10 Distributed RAM RAM64X1Q Virtex 5 FPGA User Guide www xilinx com 183 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs unused unused WADDR 6 1 WCLK WED DATA 1 RADDR 6 1 DATA 2 DATA 3 RAM 64X3SDP DPRAM32 C 6 1 6 B 6 1 6 XILINX O 1 O 2 O 3 UG190 5 06 050506 Figure 5 11 Distributed RAM RAM64X3SDP Implementation of distributed RAM configurat
17. www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Simultaneous Switching Output Limits Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank LVCMOS15_2_slow 20 40 LVCMOS15_4_slow 20 40 LVCMOS15_6_slow 20 40 LVCMOS15_8_slow 20 40 LVCMOS15_12_slow 20 40 LVCMOS15_16_slow 20 40 LVCMOS15_2_fast 20 40 LVCMOS15_4_fast 20 40 LVCMOS15_6_fast 20 40 LVCMOS15_8_fast 20 40 LVCMOS15_12_fast 20 40 LVCMOS15_16_fast 20 40 LVDCI_15 50 Q 20 40 1 5V HSTL I 15 20 40 HSTL I 15 DCI 20 40 HSTL II 15 20 40 HSTL II 15 DCI 20 40 HSTL III 15 20 40 HSTL III 15 DCI 20 40 HSTL IV 15 12 25 HSTL IV 15 DCI 12 25 HSLVDCI 15 50 Q 20 40 DIFF HSIL I 15 20 40 DIFF HSTL I 15 DCI 20 40 DIFF HSIL II 15 20 40 DIFF HSIL II 15 DCI 20 40 Virtex 5 FPGA User Guide www xilinx com 305 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank LVCMOS18 2 slow 20 40 LVCMOS18 4 slow 20 40 LVCMOS18 6 slow 20 40 LVCMOS18 8 slow 20 40 LVCMOS18 12 slow 20 40 LVCMOS18 16 slow 20 40 LVCMOS
18. External Termination LVDS 25 LVDS 25 Rpirr 2Zo 1000 Dx SE X ug190_6_81_030506 Figure 6 86 LVDS_25 Receiver Termination Figure 6 87 is an example of a differential termination for an LVDS receiver on a board with 50 Q transmission lines IOB IOB LVDS_25 LVDS_25 Data in ug190_6_82_030506 Figure 6 87 LVDS_25 With DIFF_TERM Receiver Termination Table 6 36 lists the available Virtex 5 FPGA LVDS I O standards and attributes supported Table 6 36 Allowed Attributes of the LVDS I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOSTANDARD LVDS_25 LVDSEXT_25 DIFF_TERM TRUE FALSE N A 292 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards HyperTransport Protocol HT The HyperTransport protocol HT also known as Lightning Data Transport LDT is a low voltage standard for high speed interfaces Its differential signaling based interface is very similar to LVDS Virtex 5 FPGA IOBs are equipped with HT buffers Table 6 38 summarizes all the possible HT I O standards and attributes supported Table 6 37 Allowed Attributes of the HT I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOSTANDARD HT_25 DIFF_TERM TRUE FALSE N A Reduced Swing Differential Signaling RSDS Reduced Swing Differenti
19. TSCONTROL I r lore 1 l I lioppo 1 ODDR CLK to 3 state deassertion time New PAD PAD Previous PAD Input Value Output Value i 4 ODDR CLK to IDELAY ready I I IDDR CLK I I Pad to IDDR Setup Time is T IDOCKD 7 I Topi Toppo_IDaTaIN where Tioppo ipaa ISa function of IDELAY VALUE IODELAY 03 082107 Figure 7 12 Relevant Timing Signals to Examine IODELAY Timing when the IOB Switches From an Output to an Input The activities of the OBUFT pin are controlled by the propagation and state of the TSCONTROL signal from the ODDR flip flop The 3 state control data receipt on the OBUF and IDDR flip flop from a PAD are in parallel with each other depending on the IDELAY VALUE setting the final value at the IDDR flip flop input in response to a clock edge is valid before or after the pad is driven from the 3 state control After the 3 state control propagates through to the PAD and the IODELAY has been switched to an input the IDDR setup time is the sole determiner of timing based on the IDELAY VALUE and other timing parameters defined in the Xilinx speed specification and represented in the ISE tools Virtex 5 FPGA User Guide www xilinx com 331 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX The second case uses bidirectional IODELAY when the I O is an input switching to an output Figure 7 13 shows the IOB and IODELAY moving t
20. The example in Figure 4 23 reflects both standard and FWFT modes Clock event 3 is with respect to read clock while clock event 5 is with respect to write clock Clock event 5 appears three write clock cycles after clock event 3 e Read enable remains asserted at the RDEN input of the FIFO e At time Trcko Arurr after clock event 5 RDCLK Almost FULL is deasserted at the AFULL pin Virtex 5 FPGA User Guide www xilinx com 153 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX There is minimum time between a rising read clock and write clock edge to guarantee that AFULL will be deasserted If this minimum is not met the deassertion of AFULL can take an additional write clock cycle Case 4 Reading From An Empty or Almost Empty FIFO Prior to the operations performed in Figure 4 24 the FIFO is almost completely empty In this example the timing diagram reflects standard mode For FWFT mode data at DO appears one read clock cycle earlier 1 2 3 4 wack JILI L LF LS Ly Le Ly WREN RDCLK Trcck_RDEN gt TFCCK RDEN RDEN Il Trcko po TFcko po lI DO 00 X 01 X 02 X O03 X 04 EMPTY e TEcKO AEMPTY AEMPTY TFCKO_RDERR e j RDERR o g FCKO_RDERR ugi90 4 21 032506 Figure 4 24 Reading From an Empty Almost Empty FIFO Standard Mode Clock Event 1 Read Operation and Assertion of Almost EMPTY Signal During a read operation to an almost e
21. PLL Driving DCM A second option for reduce clock jitter is to use the PLL to clean up the input clock jitter before driving into the DCM This will improve the output jitter of all DCM outputs but any added jitter by the DCM will still be passed to the clock outputs Both PLL and DCM should reside in the same CMT block because dedicated resources exist between the PLL and DCM to support the zero delay mode When the PLL and DCM do not reside in the same CMT then the only connection is through a BUFG hindering the possibility of deskew One PLL can drive multiple DCMs as long as the reference frequency can be generated by a single PLL For example if a 33 MHz reference clock is driven into the PLL and the design uses one DCM to operate at 200 MHz and the other to run at 100 MEZ then the VCO can be operated at 600 MHz M1 18 The VCO frequency can be divided by three to generate a 200 MHz clock and another counter can be divided by six to generate the 100 MHz clock For the example in Figure 3 14 one PLL can drive both DCMs 1 gt CLKOUTO CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT Matches 2 LK CLKO 5 CLKFBIN CLK90 gt To Logic etc RST CLK190 3 CLK270 CLK2X B gt To Logic etc 4 CLK2X190 CLKDV 5 CLKFX is CLKFX180 a Ti ug190_3_14_092107 Figure 3 14 PLL Driving a DCM Virtex 5 FPGA User Guide www xilinx com 105 UG190 v4 4 De
22. Setup and Hold Relative to Clock CLK TrxCK_x Setup time before clock edge and Tgck x Hold time after clock edge TRDCK_DI_ECC Time before the clock that data must be stable at the Standard ECC Mode DI inputs of the block RAM Standard ECC mode Data inputs DI F TncKDp Dr ECC Time after the clock that data must be stable at the Standard ECC Mode DI inputs of the block RAM Standard ECC mode TRDCK_DI_ECC Time before the clock that data must be stable at the Encode only Mode DI inputs of the block RAM Encode only mode Data inputs DI Tnckp pi ECC Time after the clock that data must be stable at the Encode only Mode DI inputs of the block RAM Encode only mode Clock to Out Delays Tncko po Clock to CLK to DO Time after the clock that the output data is stable at latch mode Output the DO outputs of the block RAM without output register Tncko po Clock to CLK to DO Time after the clock that the output data is stable at register mode Output the DO outputs of the block RAM with output register 168 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX Built in Error Correction Table 4 25 Block RAM ECC Mode Timing Parameters Continued Control Parameter Function Signal Description Clock to ECC Delays TncCKO ECC PARITY Clockto ECC ECCPARITY Time after WRCLK that the ECC parity s
23. UG190 5 29 050506 Figure 5 29 Simplified Virtex 5 FPGA Slice SRL Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 205 Chapter 5 Configurable Logic Blocks CLBs XILINX Slice SRL Timing Parameters Table 5 9 shows the SLICEM SRL timing parameters for a majority of the paths in Figure 5 29 Table 5 9 Slice SRL Timing Parameters Parameter Function Description Sequential Delays for a Slice LUT Configured as an SRL Trec CLK to A B C D outputs Time after the CLK of a write operation that the data written to the SRL is stable on the A B C D outputs of the slice Trec mux CLK to AMUX DMUX output Time after the CLK of a write operation that the data written to the SRL is stable on the DMUX output of the slice TREG M31 CLK to DMUX output via Time after the CLK of a write operation that the MC31 output data written to the SRL is stable on the DMUX output via MC31 output Setup and Hold Times for a Slice LUT Configured SRL 2 Tws TwH CE input WE Time before after the clock that the write enable signal must be stable at the WE input of the slice LUT configured as an SRL Tps Tpg AX BX CX DX configured as Time before the clock that the data must be stable data input DI at the AX BX CX DX input of the slice configured as an SRL Notes 1 This parameter includes a LUT configured as a two bit shift register 2 Tyxck Setup Time before clock
24. Virtex 5 FPGA User Guide www xilinx com 365 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX Output Parallel to Serial Logic Resources OSERDES The OSERDES in Virtex 5 devices is a dedicated parallel to serial converter with specific clocking and logic resources designed to facilitate the implementation of high speed source synchronous interfaces Every OSERDES module includes a dedicated serializer for data and 3 state control Both Data and 3 state serializers can be configured in SDR and DDR mode Data serialization can be up to 6 1 10 1 if using OSERDES Width Expansion 3 state serialization can be up to 4 1 Figure 8 14 shows a block diagram of the OSERDES highlighting all the major components and features of the block T1 T4 3 State TCE Parallel to Serial Converter CLK CLKDIV SR Data Parallel to Serial Converter Output Driver ug190 8 14 100307 Figure 8 14 OSERDES Block Diagram Data Parallel to Serial Converter The data parallel to serial converter in one OSERDES blocks receives two to six bits of parallel data from the fabric 10 1 if using OSERDES Width Expansion serializes the data and presents it to the IOB via the OQ outputs Parallel data is serialized from lowest order data input pin to highest i e data on the D1 input pin is the first bit transmitted at the OQ pins The data parallel to serial converter is available in two modes single
25. 2Zg 1000 ug190_6_41_030206 Figure 6 42 HSTL 1 5V Class Il Unidirectional Termination Virtex 5 FPGA User Guide www xilinx com 251 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 43 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 5V with bidirectional termination External Termination ete a ee c ER E IOB I Vr 0 75V Vr 0 75V job HSTL_II HSTL_II Rp Zo Vper 0 75V l DCI IOB IOB Veco 1 5V Veco 15V 2Rygp 2Zg 1002 E 2Rygp 7 2Zg 1000 HSTL Il DCI l HSTL_II_DCI ht 2 D4d 4 l Vper 0 75V 2Ryan 2Zg 1000 l 227 Vaer 0 75V 2Rygw 2Zo 1000 l S ugi90 6 42 030306 Figure 6 43 HSTL 1 5V Class Il Bidirectional Termination 252 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Table 6 17 lists the HSTL 1 5V Class II DC voltage specifications Table 6 17 HSTL 1 5V Class Il DC Voltage Specifications Min Typ Max Vcco 140 1 50 1 60 Vggr 2 0 68 0 75 0 90 Vir 2 Vcco x 0 5 VH Veer 0 1 Va Vggr 0 1 Vou Veco 04 VoL 0 4 Tox at Voy mA 16 Ior at Vor mA 16 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vpgp is
26. Config I O Top Half Virtex 5 Config Blocks and Center Column BUFGs Config I O Bottom Half Clock I O Bottom Half CMT Blocks Bottom Half DCMs PLLs I O Banks Larger Devices Only ug190 2 01 032506 Figure 2 1 CMT Location Virtex 5 FPGA User Guide www xilinx com 43 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Table 2 1 summarizes the availability of CMTs DCMs and PLLs in each Virtex 5 device Table 2 1 Available CMT DCM and PLL Resources Number of Available Device CMTs DCMs Site Names XC5VLX20T 1 2 Bottom half DCM ADV X0Y0 DCM ADV X0Y1 PLL ADV XOYO XC5VLX30 2 4 Bottom half XCSVEXSOT DCM ADV X0Y0 DCM ADV X0Y1 PLL_LADV_XOY0 XC5VLX30T T E XC5VSX35T p DCM ADV X0Y2 DCM ADV X0Y3 PLL ADV XOY1 XC5VLX50 6 12 Bottom half dec DCM ADV X0Y0 DCM ADV X0Y1 PLL ADV X0YO 5VSX50T Mer DCM ADV X0Y2 DCM ADV X0Y3 PLL_ADV_XOY1 XC5VLX85 DCM ADV X0Y4 DCM ADV X0Y5 PLL_ADV_X0Y2 XC5VLX85T Top half Avot DCM ADV X0Y6 DCM ADV X0Y7 PLL ADV X0Y3 MAL DCM ADV X0Y8 DCM ADV X0Y9 PLL ADV XOYA XC5VLX110 SPATE PME Rp MINE CAUGPY AUS AE LL ADV XC5VLX110T DCM ADV X0Y10 DCM_ADV_X0Y11 PLL_ADV_X0Y5 XC5VEX130T XC5VTX150T XC5VLX155 XC5VLX155T XC5VEX200T XC5VLX220 XC5VLX220T XC5VSX240T XC5VTX240T XC5VLX330 XC5VLX330T DCM Summary The Digital Clock Managers DCMs in Virtex 5 FPGAs provide a wide range
27. In addition one FIFO18 and one RAMB16 can be placed in the same RAMB36 location no BEL constraint is required RAMB36 XOYO BEL RAMB36 XOYO BEL inst my_fifol8 LOC inst my_ramb18 LOC RAMB36 XO0YO RAMB36 XO0YO Block RAM Initialization in VHDL or Verilog Code Block RAM memory attributes and content can be initialized in VHDL or Verilog code for both synthesis and simulation by using generic maps VHDL or defparams Verilog within the instantiated component Modifying the values of the generic map or defparam will effect both the simulation behavior and the implemented synthesis results The Virtex 5 FPGA Libraries Guide includes the code to instantiate the RAMB36 primitive Additional RAMB18 and RAMB36 Primitive Design Considerations The RAMB18 and RAMB36 primitives are integral in the Virtex 5 FPGA block RAM solution Optional Output Registers Optional output registers can be used at either or both A B output ports of RAMB18 and RAMB36 The choice is made using the DO A B REG attribute The two independent clock enable pins are REGCE A B When using the optional output registers at port A B assertion of the synchronous set reset SSR pin of ports A B causes the value specified by the attribute SRVAL to be registered at the output Figure 4 5 shows an optional output register Virtex 5 FPGA User Guide www xilinx com 129 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Inde
28. Output Slew Rate Attributes 0 0 cee cent eee e eee 234 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 13 XILINX Output Drive Strength Attributes 0 0 ne 235 PULLUP PULLDOWN KEEDER for IBUF OBUFT and IOBUF 235 Differential Termination Attribute llle eh 235 Virtex 5 FPGA I O Resource VHDL Verilog Examples esses 235 Specific Guidelines for I O Supported Standards 236 LVTTL Low Voltage Transistor Transistor Logic 00 0000 236 LVCMOS Low Voltage Complementary Metal Oxide Semiconductor 238 LVDCI Low Voltage Digitally Controlled Impedance 0 0000000 240 LV DEI DV 2 ecetes eh ee ee ees dela ee hes eS on ek eee eR TE ie en 241 HSLVDCI High Speed Low Voltage Digitally Controlled Impedance 243 PCI X PCI 33 PCI 66 Peripheral Component Interconnect suus 244 GTL Gunning Transceiver Logic 0 6 6 6 cece e 245 GIL DGI Usage ands dia po bae Da ere dete Eie rd deside a qe is 245 GTLP Gunning Transceiver Logic Plus ssssssseeeeeeeeeeeese 246 GILP DCI Usa ge eec tie epe eee ed RP a Pre donent aad pated 246 HSTL High Speed Transceiver Logic lsssseeseeeeeeeeeeeeeeee 247 HSTL_I HSTL_ M HSTL I 18 HSTL III 18 HSTL_I_12 247 HSTL I DCI HSTL III DCI HSTL I DCI 18 HSTL III DCI 18 247 HSTL II HSTL IV HS
29. Removed general routing discussion from PLL Clock Input Signals Revised Missing Input Clock or Feedback Clock section Added waveforms to Figure 3 13 Corrected the Virtex 4 port mapping in Figure 3 17 and Table 3 8 page 108 Chapter 4 Revised and clarified Built in Error Correction Edited WE signal throughout Clarified Readback limitation in Simple Dual Port Block RAM on page 119 Edited Set Reset SSR A B page 123 Added Block RAM Retargeting page 138 Revised latency values and added Note 1 to Table 4 16 page 144 Updated Cascading FIFOs to Increase Depth page 156 Chapter 5 Clarified information about common control signals in a slice in Storage Elements on page 176 Chapter 6 Updated the DCI cascading guidelines on page 221 Removed references to HSLVDCI Controlled Impedance Driver with Unidirectional Termination since it is not supported in software Added note 3 to Table 6 17 page 253 Clarified the introduction to SSTL Stub Series Terminated Logic page 271 Revised DIFF_SSTL2_II_DCI DIFF_SSTL18_II_DCI on page 272 Fixed DIFF SSTL2 II references in Figure 6 73 page 279 Revised rules 2 and 3 in Rules for Combining I O Standards in the Same Bank page 295 Deleted of absolute maximum table from Overshoot Undershoot page 299 Chapter 7 Removed DDLY port from IDDR primitive page 317 Added the SIGNAL PATTERN DELAY SRC and REFCLK FREQUENCY attribut
30. VREF Virtex 5 DCI g UG190_6_07_021206 Figure 6 9 Input Termination Using DCI Single Termination Input Termination to Vcco 2 Split Termination Some I O standards e g HSTL Class I and II require an input termination voltage of Vcco 2 see Figure 6 10 IOB R E T gt Zo VREF Virtex 5 UG190_6_08_021206 Figure 6 10 Input Termination to Vcco 2 without DCI This is equivalent to having a split termination composed of two resistors One terminates to Vcco the other to ground The resistor values are 2R DCI provides termination to Vcco 2 using split termination The termination resistance is set by the external reference resistors i e the resistors to Vcco and ground are each twice the reference resistor value Both HSTL and SSTL standards need 50 G external reference resistors The DCI input standards supporting split termination are shown in Table 6 1 Table 6 1 DCI Input Standards Supporting Split Termination HSTL I DCI DIFF HSTL I DCI SSTL2 I DCI DIFF SSTI2 I DCI HSTL I DCI 18 DIFF HSTL I DCI 18 SSTL2 II DCI DIFF SSTI2 II DCI HSTL II DCI DIFF HSTL II DCI SSTL18 I DCI DIFF SSTL18 I DCI HSTL II DCI 18 DIFF HSTL II DCI 18 SSTL18 II DCI DIFF SSTL18 II DCI HSTL II T DCI SSTL2 II T DCI HSTL II T DCI 18 SSTL18 II T DCI 224 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines Fig
31. f ll o CLK2X Locken 978 ugi90 2 19 042406 Figure 2 18 Phase Shift Example Fixed e Clock Event 1 Clock event 1 appears after the desired phase shifts are applied to the DCM In this example the shifts are positive shifts CLKO and CLK2X are no longer aligned to CLKIN However CLKO and CLK2X are aligned to each other while CLK90 and CLK180 remain as 90 and 180 versions of CLKO The LOCK signal is also asserted once the clock outputs are ready Virtex 5 FPGA User Guide www xilinx com 81 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Variable Phase Shifting In Figure 2 19 the CLKO output is phase shifted using the dynamic phase shift adjustments in the synchronous user interface The PSDONE signal is asserted for one cycle when the DCM completes one phase adjustment After PSDONE is deasserted PSEN can be asserted again allowing an additional phase shift to occur As shown in Figure 2 19 all the variable phase shift control and status signals are synchronous to the rising edge of PSCLK ae lio T DL I L I iL 1 L ax fc Uo i 1rbE hB dE 2 1 M PSCLK PSEN gt TpMCCK PSEN U PSDONE Ln Touceo Pspone l Tpwcck PsiNCDEC PSINCDEC D C 82 D C ug190 2 20 0042406 Figure 2 19 Phase Shift Example Variable Clock Event 1 At Tpwcck psen before
32. oa J feJcfeXey eye X UG190 8 18 100307 Figure 8 18 OSERDES Data Flow and Latency in 8 1 DDR Mode Clock Event 1 On the rising edge of CLKDIV the word ABCDEFGH is driven from the FPGA logic to the D1 D6 inputs of the master OSERDES and D3 D4 of the slave OSERDES after some propagation delay Clock Event 2 On the rising edge of CLKDIV the word ABCDEFGH is sampled into the master and slave OSERDES from the D1 D6 and D3 D4 inputs respectively Clock Event 3 The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the OSERDES This latency is consistent with the Table 8 10 listing of a 8 1 DDR mode OSERDES latency of four CLK cycles Virtex 5 FPGA User Guide www xilinx com 375 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1 D6 and D3 D4 inputs respectively Clock Event 4 Between Clock Events 3 and 4 the entire word ABCDEFGH is transmitted serially on OQ a total of eight bits transmitted in one CLKDIV cycle The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the OSERDES This latency is consistent with the Table 8 10 listing of a 8 1 DDR mode OSERDES latency of four CLK cycles Timing Characteristics of 4 1 DDR 3 State Controller Serialization The operation of a 3 State Controller is illustrated in Figure 8 19 The example is a 4 1 DDR case
33. 14 5 31 0 3 0 72 RAMB36SDP 9 512 14 6 63 0 7 0 1 Cascade 16 65536 15 0 0 NA For cascadable block RAM using the RAMB36 the data width is one bit and the address bus is 16 bits 15 0 The address bit 15 is only used in cascadable block RAM For non cascading block RAM connect High Data and address pin mapping is further described in the Additional RAMB18 and RAMB36 Primitive Design Considerations section Data In Buses DI AIB lt 0 gt amp DIP AIB lt 0 gt Data in buses provide the new data value to be written into RAM The regular data in bus DI plus the parity data in bus DIP when available have a total width equal to the port width For example the 36 bit port data width is represented by DI lt 31 0 gt and DIP lt 3 0 gt as shown in Table 4 6 and Table 4 7 124 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX Block RAM Port Signals Data Out Buses DO AIB lt 0 gt and DOP AIB lt 0 gt Cascade Data out buses reflect the contents of memory cells referenced by the address bus at the last active clock edge during a read operation During a write operation WRITE_FIRST or READ FIRST configuration the data out buses reflect either the data being written or the stored value before write During a write operation in NO CHANGE mode data out buses are not changed The regular data out bus DO plus the pa
34. 2Zg 1000 L a ug190_6_50_030306 Figure 6 52 HSTL Class 1 8V Termination Table 6 21 lists the HSTL Class I 1 8V DC voltage specifications Table 6 21 HSTL Class I 1 8V DC Voltage Specifications Min Typ Max Vcco 1 7 1 8 1 9 Veger 2 0 83 0 9 1 08 Ver z Vcco x 0 5 Vie Ver 0 1 e V Vggr 0 1 Vou Veco 0 4 7 Vor 0 4 Iog at Voy mA 8 Ior at Vor mA 8 E Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Veg is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 260 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Differential HSTL Class 1 8V Figure 6 53 shows a sample circuit illustrating a valid termination technique for differential HSTL Class I 1 8V with unidirectional termination External Termination Vu 0 9V IOB TE IOB DIFF HSTL 1 18 5st XI C Zo D DIFF HSTL 1 18 Vir 0 9V DIFF HSTL 1 18 si X C Zo D ug 90 6 51 030306 Figure 6 53 Differential HSTL 1 8V Class I Unidirectional Termination Figure 6 54 shows a sample circuit illustrating a valid termination technique for differential HSTL Class I 1 8V with unidirectional DCI termination DCI IOB 1O08 Veco 1
35. CE A dynamic read access is performed through the 5 bit address bus A 4 0 The LSB of the LUT is unused and the software automatically ties it to a logic High The configurable shift registers cannot be set or reset The read is asynchronous however a storage element www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview or flip flop is available to implement a synchronous read In this case the clock to out of the flip flop determines the overall delay and improves performance However one additional cycle of clock latency is added Any of the 32 bits can be read out asynchronously at the O6 LUT outputs by varying the 5 bit address This capability is useful in creating smaller shift registers less than 32 bits For example when building a 13 bit shift register simply set the address to the 13 bit Figure 5 15 is a logic block diagram of a 32 bit shift register SRLC32E l SHIFTIN D A l l SHIFTOUT Q31 ao L 62 l CLK CLK i Output Q CE WE CE l AQ Registered l Output l l Optional Dam l ec fe Ye ug190 5 15 050506 Figure 5 15 32 bit Shift Register Configuration Figure 5 16 illustrates an example shift register configuration occupying one function generator 32 bit Shift Register SHIFTIN D gt SHIFTOUT Q31 WE CLK Address A 4 0 Q UG190 5 16 050
36. Control Engine configurable Options UG190 4 06 040606 Figure 4 5 Block RAM Logic Diagram One Port Shown Independent Read and Write Port Width Selection 118 Each block RAM port has control over data width and address depth aspect ratio The true dual port block RAM in Virtex 5 FPGAs extends this flexibility to Read and Write where each individual port can be configured with different data bit widths For example port A can have a 36 bit Read width and a 9 bit Write width and port B can have a 18 bit Read width and a 36 bit Write width See Block RAM Attributes page 126 If the Read port width differs from the Write port width and is configured in WRITE FIRST mode then DO shows valid new data for all the enabled write bytes The DO port outputs the original data stored in memory for all not enabled bytes Independent Read and Write port width selection increases the efficiency of implementing a content addressable memory CAM in block RAM This option is available for all Virtex 5 FPGA true dual port RAM port sizes and modes www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Additional Block RAM Features in Virtex 5 Devices Simple Dual Port Block RAM Each 18 Kb block and 36 Kb block can also be configured in a simple dual port RAM mode In this mode the block RAM port width doubles to 36 bits for the 18 Kb block RAM and 72 bits for the 36 Kb block RAM In simple du
37. D5 gt OSERDES m Primitive VVVVVWVVN OCE gt SHIFTIN1 gt SHIFTIN2 gt SR gt T1 gt T2 gt T3 gt T4 gt TCE gt VVVWVY Figure 8 15 UG190 v4 4 December 2 2008 OSERDES Primitive www xilinx com oQ SHIFTOUT1 SHIFTOUT2 ug190 8 15 100307 367 Chapter 8 Advanced SelectlO Logic Resources XILINX OSERDES Ports Table 8 6 lists the available ports in the OSERDES primitive Table 8 6 OSERDES Port List and Definitions Port Name Type Width Description OQ Output 1 Data path output See Data Path Output OQ SHIFTOUT1 Output 1 Carry out for data width expansion Connect to SHIFTIN1 of master OSERDES See OSERDES Width Expansion SHIFTOUT2 Output 1 Carry out for data width expansion Connect to SHIFTIN2 of master OSERDES See OSERDES Width Expansion TO Output 1 3 state control output See 3 state Control Output TO CLK Input 1 High speed clock input See High Speed Clock Input CLK CLKDIV Input 1 Divided clock input Clocks delay element deserialized data Bitslip submodule and CE unit See Divided Clock Input CLKDIV D1 D6 Input 1 each Parallel data inputs See Parallel Data Inputs D1 to D6 OCE Input 1 Output data clock enable See Output Data Clock Enable OCE REV Input 1 Reverse SR pin Not available in the OSERDES
38. EMPTY is deasserted In standard mode EMPTY is deasserted one read clock earlier than clock event 3 If the rising WRCLK edge is close to the rising RDCLK edge EMPTY could be deasserted one RDCLK period later 150 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Timing Models and Parameters Clock Event 2 and Clock Event 4 Write Operation and Deassertion of Almost EMPTY Signal Three read clock cycles after the fourth data is written into the FIFO the Almost EMPTY pin is deasserted to signify that the FIFO is not in the almost EMPTY state For the example in Figure 4 21 the timing diagram is drawn to reflect FWFT mode Clock event 2 is with respect to write clock while clock event 4 is with respect to read clock Clock event 4 appears three read clock cycles after clock event 2 e At time Tppcy pr before clock event 2 WRCLK data 03 becomes valid at the DI inputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At clock event 4 DO output pins of the FIFO remains at 00 since no read has been performed In the case of standard mode data 00 will never appear at the DO output pins of the FIFO e At time Tecko AgMprYy after clock event 4 RDCLK almost empty is deasserted at the AEMPTY pin In the case of standard mode AEMPTY deasserts in the same way as in FWFT mode If the rising WRCLK edge is close to the rising RDCLK edge AEMPTY could be deasserted one
39. For example the external components can have an input capacitance on 1 pF to 4 pF while the FPGA has an input capacitance of around 8 pF There is a difference in the signal slope which is basically skew Designers need to be aware of this effect to ensure timing DCM Driving PLL The DCM provides an excellent method for generating precision phase shifted clocks However the DCM cannot reduce the jitter on the reference clock The PLL can be used to reduce the output jitter of one DCM clock output This configuration is shown in Figure 3 13 The PLL is configured to not introduce any phase shift zero delay through the PLL The associated waveforms are shown to the right of the block diagram When the output of the DCM is used to drive the PLL directly both DCM and PLL must reside within the same CMT block This is the preferred implementation since it produces a minimal amount of noise on the local dedicated route However a connection can also be made by connecting the DCM to a BUFG and then to the CLKIN input of a PLL Matches 104 CLKO T gt CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG CLKOUTO T gt EM CLKOUT1 SUMUS CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT EO uv amp O GL qd oJ En dg Le tox L ugi90 3 13 092107 Figure 3 13 DCM Driving a PLL www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX PLL Use Models
40. Module V rst gt Bitslip L gt ug190_8_01_050906 Figure 8 1 ISERDES Block Diagram ISERDES Primitive ISERDES_NODELAY The ISERDES primitive in Virtex 5 devices shown in Figure 8 2 is ISERDES NODELAY BITSLIP y gt Q1 CE1 gt gt Q2 CE2 gt gt Q3 CLK E Q4 CLKB T gt Q5 S CLKDIV ISERDES_NODELAY ee Primitive gt gt SHIFTOUT1 E gt SHIFTOUT2 SHIFTIN1 gt SHIFTIN2 gt RST gt ug190_8_02_112607 Figure 8 2 ISERDES_NODELAY Primitive 350 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES Table 8 1 lists the available ports in the ISERDES_NODELAY primitive Table 8 1 ISERDES_NODELAY Port List and Definitions Port Name Type Width Description Q1 Q6 Output 1 each Registered outputs See Registered Outputs O1 to Q6 SHIFTOUT1 Output 1 Carry out for data width expansion Connect to SHIFTIN1 of slave IOB See ISERDES Width Expansion SHIFTOUT2 Output 1 Carry out for data width expansion Connect to SHIFTIN2 of slave IOB See ISERDES Width Expansion BITSLIP Input 1 Invokes the Bitslip operation See Bitslip Operation BITSLIP CE1 Input 1 each Clock enable inputs See Clock Enable Inputs CE1 and CF2 CE2 CLK Input 1 High speed clock input Clocks serial input dat
41. SEBEBUGNM Oulput pin is used for this purpose the software will automatically map to the correct port Synchronous output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range The PLL automatically locks after power on no extra reset is required LOCKED will be deasserted if the input clock stops or the phase alignment is violated e g input clock phase shift The PLL must be reset after LOCKED is deasserted LOCKED Output The dynamic reconfiguration output bus provides PLL data output when using DO 15 0 Output dynamic reconfiguration The dynamic reconfiguration ready output DRDY provides the response to the ud Supe DEN signal for the PLLs dynamic reconfiguration feature Notes 1 CLKOUTy and CLKOUTDCM y are utilizing the same output counters and can not be operated independently 94 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX PLL Attributes Table 3 4 PLL Attributes General Usage Description Attribute Type COMPENSATION String Allowed Values SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS Default SYSTEM_ SYNCHRONOUS Description Specifies the PLL phase compensation for the incoming clock SYSTEM_SYNCHRONOUS attempts to compensate all clock delay for 0 hold time SOURCE SYNCHRONOUS is used when a clock is provided with data and thus phased with
42. SRVALJA B attribute of 36 bits This operation does not affect RAM memory cells and does not disturb write operations on the other port Similar to the read and write operation the set reset function is active only when the enable pin of the port is active Set reset polarity is configurable active High by default Virtex 5 FPGA User Guide www xilinx com 123 UG190 v4 4 December 2 2008 Chapter 4 Block RAM Address Bus ADDR AIB lt 13 gt lt 14 4 gt lt 15 gt The address bus selects the memory cells for read or write The data bit width of the port determines the required address bus width for a single RAMB18 or RAMB36 as shown in Table 4 6 and Table 4 7 Table 4 6 Port Aspect Ratio for RAMB18 and RAMB18SDP 2 XILINX Port Data Width Port Address Width Depth ADDR Bus DI Bus DO Bus DIP Bus DOP Bus 1 14 16 384 13 0 0 NA 2 13 8 192 13 1 1 0 NA 4 12 4 096 13 2 3 0 NA 9 11 2 048 lt 13 3 gt lt 7 0 gt lt 0 gt 18 10 1 024 lt 13 4 gt lt 15 0 gt lt 1 0 gt 36 RAMB18SDP 9 512 lt 13 5 gt lt 31 0 gt lt 3 0 gt Table 4 7 Port Aspect Ratio for RAMB36 Port Data Width Port Address Width Depth ADDR Bus DI Bus DO Bus DIP Bus DOP Bus 1 15 32 768 14 0 0 NA 2 14 16 384 14 1 1 0 NA 4 13 8 192 142 3 0 NA 9 12 4 096 14 3 7 0 0 18 11 2 048 144 15 0 1 0 36 10 1 024
43. SSO Contribution I O group n quantity of drivers Bank SSO limit For a bank with drivers of multiple I O standards the SSO calculation is Bank SSO Y SSO Contribution n 1 to n A sample SSO calculation follows The system parameters used are Device XC5VLX50 FF1153 Bank 11 I O Standards Quantities SSTL2 II 12 LVCMOS25 24 Fast 6 LVCMOS25 6 Fast 19 First SSO limits for each I O standard are obtained from Table 6 40 I O Group I O Standard SSO Limit Drivers per Bank 1 SSTL2 II 40 2 LVCMOS25 24 Fast 30 3 LVCMOS25 6 Fast 40 The SSO contribution of each I O standard is calculated as SSO Contribution quantity of drivers Bank SSO limit SSO Contribution 1 12 40 30 SSO Contribution 2 6 30 20 SSO Contribution 3 19 40 48 Finally the bank SSO is calculated Bank 1 SSO SSO contribution 1 SSO contribution 2 SSO Contribution 3 30 20 48 98 Virtex 5 FPGA User Guide www xilinx com 311 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Full Device SSO Calculator A Microsoft Excel based spreadsheet the Virtex 5 FPGA SSO Calculator automates all the PFDM and SSO calculations The Virtex 5 FPGA SSO calculator uses PCB geometry board thickness via diameter and breakout trace width and length to determine power system inductance It determines the smallest undershoot and logic low threshold voltage among all input devices calculates the
44. Table 1 6 lists the BUFIO ports A location constraint is available for BUFIO BUFIO ugi 90 1 18 032306 Figure 1 18 BUFIO Primitive Table 1 6 BUFIO Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port I Input 1 Clock input port BUFIO Use Models In Figure 1 19 a BUFIO is used to drive the I O logic using the clock capable I O This implementation is ideal in source synchronous applications where a forwarded clock is used to capture incoming data Virtex 5 FPGA User Guide www xilinx com 37 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX To Adjacent Region 1 0 1 0 1 0 1 0 1 0 1 0 P IO Clock Capable I O 1 0 Clock Capable I O MC BUFIO al UJ UFR Not all available BUFIOs are shown To Fabric b Pare Clock Capable I O ze e EN ES P IO Clock Capable I O N I O 1 0 1 0 1 0 1 0 1 0 To Adjacent Region 1 0 ug190_1_19_060706 Figure 1 19 BUFIO Driving I O Logic In a Single Clock Region 38 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Regional Clocking Resources Regional Clock Buffer BUFR The regional clock buffer BUFR is another clock buffer available in Virtex 5 devices BUFRs drive clock signals to a dedicated clock net within a clock region independent from the global clock tree Each BUFR can drive the four regional clo
45. The generate signals are sourced from either the O5 output of a function generator or the BYPASS input AX BX CX or DX of a slice The former input is used to create a multiplier while the latter is used www xilinx com UG190 v4 4 December 2 2008 197 Chapter 5 Configurable Logic Blocks CLBs XILINX to create an adder accumulator CYINIT is the CIN of the first bit in a carry chain The CYINIT value can be 0 for add 1 for subtract or AX input for the dynamic first carry bit The CIN input is used to cascade slices to form a longer carry chain The O outputs contain the sum of the addition subtraction The CO outputs compute the carry out for each bit CO3 is connected to COUT output of a slice to form a longer carry chain by cascading multiple slices The propagation delay for an adder increases linearly with the number of bits in the operand as more carry chains are cascaded The carry chain can be implemented with a storage element or a flip flop in the same slice CLB Slice Timing Models Due to the large size and complexity of Virtex 5 FPGAs understanding the timing associated with the various paths and functional elements is a difficult and important task Although it is not necessary to understand the various timing parameters to implement most designs using Xilinx software a thorough timing model can assist advanced users in analyzing critical paths or planning speed sensitive designs Three timing mode
46. and resetting 3 state Register reflected at the TO output at time Trg after Clock Event 10 no change at the TO output in this case www xilinx com 347 Chapter 7 SelectlO Logic Resources XILINX 348 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Chapter 6 Advanced SelectIO Logic Resources Introduction The I O functionality in Virtex 5 FPGAs is described in Chapter 6 through Chapter 8 of this user guide Chapter 6 covers the electrical characteristics of input receivers and output drivers and their compliance with many industry standards Chapter 7 describes the register structures dedicated for sending and receiving SDR or DDR data This chapter covers additional resources Input serial to parallel converters ISERDES and output parallel to serial converters OSERDES support very fast I O data rates and allow the internal logic to run up to 10 times slower than the I O The Bitslip submodule can re align data to word boundaries detected with the help of a training pattern Input Serial to Parallel Logic Resources ISERDES The ISERDES in Virtex 5 FPGAs is a dedicated serial to parallel converter with specific clocking and logic features designed to facilitate the implementation of high speed source synchronous applications The ISERDES avoids the additional timing complexities encountered when designing deserializers in the FPGA fabric ISERDES features inclu
47. become stable at the DO pins of the block RAM e Whenever EN is asserted all address changes must meet the specified setup and hold window Asynchronous address changes can affect the memory content and block RAM functionality in an unpredictable way Virtex 5 FPGA User Guide www xilinx com 135 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Clock Event 2 Write Operation During a write operation the content of the memory at the location specified by the address on the ADDR inputs is replaced by the value on the DI pins and is immediately reflected on the output latches in WRITE_FIRST mode when Write Enable WE is High e At time Tgcck Appr before clock event 2 address OF becomes valid at the ADDR inputs of the block RAM e At time TRpcK_pi before clock event 2 data CCCC becomes valid at the DI inputs of the block RAM e At time Trccp_we before clock event 2 write enable becomes valid at the WE following the block RAM e At time Tgcko poafter clock event 2 data CCCC becomes valid at the DO outputs of the block RAM Clock Event 4 SSR Synchronous Set Reset Operation During an SSR operation initialization parameter value SRVAL is loaded into the output latches of the block RAM The SSR operation does NOT change the contents of the memory and is independent of the ADDR and DI inputs e At time TrccK ssp before clock event 4 the synchronous set reset signal becomes valid High at the SSR input of
48. purse IAT A Teccko_o n ugi90 1 04 032206 Figure 1 4 BUFG Timing Diagram Virtex 5 FPGA User Guide www xilinx com 27 UG190 v4 4 December 2 2008 28 Chapter 1 Clock Resources XILINX BUFGCE and BUFGCE 1 Unlike BUFG BUFGCE is a clock buffer with one clock input one clock output and a clock enable line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 5 illustrates the relationship of BUFGCE and BUFGCTRL A LOC constraint is available for BUFGCE and BUFGCE 1 BUFGCE as BUFGCTRL IGNORE1 Yoo ce GND BUFGCE GND 1 CE Vop 82 CE CEO GND IGNOREO ug190 1 05 032206 Figure 1 5 BUFGCE as BUFGCTRL The switching condition for BUFGCE is similar to BUFGCTRL If the CE input is Low prior to the incoming rising clock edge the following clock pulse does not pass through the clock buffer and the output stays Low Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low The output stays Low when the clock is disabled However when the clock is being disabled it completes the clock High pulse Since the clock enable line uses the CE pin of the BUFGCTRL the select signal must meet the setup time requirement Violating this setup time may result in a glitch Figure 1 6 illustrates the timing diagram for BUFGCE BUFGCE l N E s y BCCCK CE BUFGCECE 1 Nj lO BUFGCE O a
49. they do require 3 3V input output source voltage Veco A PCI undershoot overshoot specification could require Vcco to be regulated at 3 0V as discussed in Regulating Vcco at 3 0V page 301 This is not necessary if overshoot and undershoot are controlled by careful design Table 6 11 and Table 6 12 lists the DC voltage specifications Table 6 11 PCI33 3 PCl66 3 Voltage Specifications 2 Parameter Min Typ Max Vcco 3 0 33 3 5 VREF E Vor Vig 0 5 x Veco 1 5 1 65 Veco Vir 03 x Veco 0 2 0 99 1 05 Vog 09 x Veco 2 7 Vor 0 1 x Veco 0 35 Tox at Voy mA Note 1 2 B lor at Vor mA Note 1 B Notes 1 Tested according to the relevant specification 2 For complete specifications refer to the PCI specification Table 6 12 PCI X DC Voltage Specifications 2 Parameter Min Typ Max Vcco 3 0 33 3 5 VREF Vir 3 E Vig 20 5 x Veco 1 5 1 65 Veco Vi 0 35 x Veco 0 2 1 155 1 225 Vou 209 x Veco 27 E Vor 0 1 x Veco 0 35 Tox at Voy mA Note 1 E Ior at Vor mA Note 1 z Notes 1 Tested according to the relevant specification 2 For complete specifications refer to the PCI X specification Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards GTL Gunning Transceiver Logic The Gunning Transceiver Logic GTL stan
50. x18 x36 5 1019 6 1020 4 1019 x36 x72 5 507 6 508 4 507 Synchronous mode EN SYN TRUE x4 1 8190 1 8190 x4 x9 1 4094 1 4094 x9 x18 1 2046 1 2046 x18 x36 1 1022 1 1022 x36 x72 1 510 1 510 Notes 1 For limitations under certain conditions refer to Equation 4 1 on page 145 The Almost Full and Almost Empty offsets are usually set to a small value of less than 10 to provide a warning that the FIFO is about to reach its limits Since the full capacity of any FIFO is normally not critical most applications use the ALMOST_FULL flag not only as a warning but also as a signal to stop writing Similarly the ALMOST_EMPTY flag can be used to stop reading However this would make it impossible to read the very last entries remaining in the FIFO The user can ignore the Almost Empty signal and continue to read until EMPTY is asserted The Almost Full and Almost Empty offsets can also be used in unstoppable block transfer applications to signal that a complete block of data can be written or read www xilinx com 147 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX When setting the offset ranges in the design tools use hexadecimal notation FIFO VHDL and Verilog Templates VHDL and Verilog templates are available in the Libraries Guide FIFO Timing Models and Parameters Table 4 20 shows the FIFO parameters Table 4 20 FIFO Timing Parameters Control
51. 1 Clock Resources XILINX Global Clocking Resources 22 Global clocks are a dedicated network of interconnect specifically designed to reach all clock inputs to the various resources in an FPGA These networks are designed to have low skew and low duty cycle distortion low power and improved jitter tolerance They are also designed to support very high frequency signals Understanding the signal path for a global clock expands the understanding of the various global clock resources The global clocking resources and network consist of the following paths and components e Global Clock Inputs e Global Clock Buffers e Clock Tree and Nets GCLK e Clock Regions Global Clock Inputs Virtex 5 FPGAs contain specialized global clock input locations for use as regular user I Os if not used as clock inputs There are 20 global clock inputs per device Clock inputs can be configured for any I O standard including differential I O standards Each clock input can be either single ended or differential All 20 clock inputs can be differential if desired When used as outputs global clock input pins can be configured for any output standard Each global clock input pin supports any single ended output standard or any output differential standard Global Clock Input Buffer Primitives The primitives in Table 1 1 are different configurations of the input clock I O input buffer Table 1 1 Clock Buffer Primitives Primitive Input
52. 1 SDR Serialization In Figure 8 17 the timing of a 2 1 SDR data serialization is illustrated Clock Clock Clock Event 1 Event 2 Event 3 CLKDIV i i i i f i ni 45 cic XD ee oe UG190_8_17_100307 Figure 8 17 OSERDES Data Flow and Latency in 2 1 SDR Mode Clock Event 1 On the rising edge of CLKDIV the word AB is driven from the FPGA logic to the D1 and D2 inputs of the OSERDES after some propagation delay Clock Event 2 On the rising edge of CLKDIV the word AB is sampled into the OSERDES from the D1 and D2 inputs Clock Event 3 The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES This latency is consistent with the Table 8 10 listing of a 2 1 SDR mode OSERDES latency of one CLK cycle 374 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Parallel to Serial Logic Resources OSERDES Timing Characteristics of 8 1 DDR Serialization Figure 8 18 illustrates the timing of an 8 1 DDR data serialization In contrast to the 2 1 SDR example a second OSERDES is required to achieve an 8 1 serialization The two OSERDES are connected and configured using the methods described in OSERDES Width Expansion page 371 Six of the eight bits are connected to D1 D6 of the master OSERDES while the remaining two bits are connected to D3 D4 of the slave OSERDES Clock Clock Clock Clock Event 1 Event 2 Event 3 Event 4 cov f i i f
53. 108 207 360 3 420 1710 207 360 XC5VLX330T 240 x 108 207 360 3 420 1710 207 360 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 175 Chapter 5 Configurable Logic Blocks CLBs XILINX Look Up Table LUT The function generators in Virtex 5 FPGAs are implemented as six input look up tables LUTs There are six independent inputs A inputs Al to A6 and two independent outputs O5 and O6 for each of the four function generators in a slice A B C and D The function generators can implement any arbitrarily defined six input Boolean function Each function generator can also implement two arbitrarily defined five input Boolean functions as long as these two functions share common inputs Only the O6 output of the function generator is used when a six input function is implemented Both O5 and O6 are used for each of the five input function generators implemented In this case A6 is driven High by the software The propagation delay through a LUT is independent of the function implemented or whether one six input or two five input generators are implemented Signals from the function generators can exit the slice through A B C D output for O6 or AMUX BMUX CMUX DMUX output for O5 enter the XOR dedicated gate from an O6 output see Fast Lookahead Carry Logic enter the carry logic chain from an O5 output see Fast Lookahead Carry Logic enter the select line of the carry logi
54. 16 The default value is 2 In the low frequency mode any CLKDV DIVIDE value produces a CLKDV output with a 50 50 duty cycle In the high frequency mode the CLKDV_DIVIDE value must be set to an integer value to produce a CLKDV output with a 50 50 duty cycle For non integer CLKDV DIVIDE values the CLKDV output duty cycle is shown in Table 2 5 Table 2 5 Non Integer CLKDV DIVIDE CLKDV Duty Cycle in CLKDV DIVIDE Value High Frequency Mode High Pulse Low Pulse Value 1 5 1 3 2 5 2 5 3 5 3 7 4 5 4 9 5 5 5 11 6 5 6 13 7 5 7 15 CLKFX MULTIPLY and CLKFX DIVIDE Attribute The CLKFX MULTIPLY attribute sets the multiply value M of the CLKFX output The CLKFX DIVIDE attribute sets the divisor D value of the CLKFX output Both control the CLKFX output making the CLKFX frequency equal the effective CLKIN source clock frequency multiplied by M D The possible values for M are any integer from two to 33 The possible values for D are any integer from 1 to 32 The default settings are M 4 and Ded CLKIN PERIOD Attribute The CLKIN PERIOD attribute specifies the source clock period in nanoseconds The default value is 0 0 ns Setting this attribute to the input period values produces the best results 54 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Attributes CLKIN_DIVIDE_BY_2 Attribute The CLKIN DIVIDE BY 2 attribute is used to enable a toggle flip flop
55. 2 1 0 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 7 6 5 4 3 2 1 0 84113 2 1 0 3 2 1 0 1642 1 0 1 0 3244 0 0 Block RAM Attributes 126 All attribute code examples are discussed in the Block RAM Initialization in VHDL or Verilog Code section Further information on using these attributes is available in the Additional RAMB18 and RAMB36 Primitive Design Considerations section Content Initialization INIT xx INIT xx attributes define the initial memory contents By default block RAM memory is initialized with all zeros during the device configuration sequence The 64 initialization attributes from INIT 00 through INIT 3F for the RAMB18 and the 128 initialization attributes from INIT 00 through INIT 7F for the RAMB36 represent the regular memory contents Each INIT xx is a 64 digit hex encoded bit vector The memory contents can be partially initialized and are automatically completed with zeros The following formula is used for determining the bit positions for each INIT xx attribute www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Attributes Given yy conversion hex encoded to decimal xx INIT_xx corresponds to the memory cells as follows e from yy 1 x 256 1 e to yy x 256 For example for the attribute INIT_1F the conversion is as follows e yy conversion hex encoded to decimal xx 1F 31 e from 31 1 x 256 1 8191 e to 31x
56. 35 050208 Figure 4 83 Legal Block RAM and FIFO Combinations 170 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 7 XILINX Chapter 5 Configurable Logic Blocks CLBs CLB Overview The Configurable Logic Blocks CLBs are the main logic resources for implementing sequential as well as combinatorial circuits Each CLB element is connected to a switch matrix for access to the general routing matrix shown in Figure 5 1 A CLB element contains a pair of slices These two slices do not have direct connections to each other and each slice is organized as a column Each slice in a column has an independent carry chain For each CLB slices in the bottom of the CLB are labeled as SLICE 0 and slices in the top of the CLB are labeled as SLICE 1 COUT COUT Slice 1 Switch Matrix CIN CIN UG190_5_01_ 122605 Figure 5 1 Arrangement of Slices within the CLB The Xilinx tools designate slices with the following definitions An X followed by a number identifies the position of each slice in a pair as well as the column position of the slice The X number counts slices starting from the bottom in sequence 0 1 the first CLB column 2 3 the second CLB column etc A Y followed by a number identifies a row of slices The number remains the same within a CLB but counts up in sequence from one CLB row to the next CLB row starting from the bottom Figure 5 2 shows four CLBs
57. 45 63 output ports 50 phase shifting 45 64 81 ports 47 timing models 80 DDR IDDR 315 delay element See IDELAY 321 Differential 247 HSTL Class II 253 HSTL Class II 1 8V 261 264 LVPECL 294 SSTL Class II 1 8V 283 288 SSTL2 Class II 2 5V 274 278 differential termination 291 DIFF TERM 235 291 E Error Correction Code ECC 157 F FIFO 138 attributes 146 cascading 156 FWFT mode 143 operating modes 143 ports 142 primitive 141 standard mode 143 status flags 144 timing parameters 148 G GCLK 34 global clocks clock buffers 21 22 clock I O inputs 22 GSR defined 126 GTL 245 defined 245 GTL DCI 245 GTLP 246 GTLP_DCI 246 H HSTL 247 defined 247 class I 249 class I 1 8V 260 271 class II 251 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 379 X XILINX class II 1 8V 262 class III 256 class III 1 8V 267 class IV 257 class IV 1 8V 268 CSE differential HSTL class II 262 Differential HSTL class II 261 264 differential HSTL class II 253 HyperTransport HT 293 I O standards 216 bank rules 295 compatibility 296 differential I O 216 single ended I O 216 I O tile 215 ILOGIC 215 IOB 215 OLOGIC 215 IBUF 231 PULLUP PULLDOWN KEEPER 235 IBUFDS 232 IBUFG 22 231 IBUFGDS 22 232 IDDR 315 OPPOSITE EDGE mode 315 ports 317 primitive 317 SAME EDGE mode 316 SAME EDGE PIPELINED mode 316 IDELAY 321 defined 321 attributes 325 d
58. 8V DIFF_HSTL_I_DCI_18 2Rypp 2Z9 1000 D4 0O 7 E 2Rygy 7229 1000 DIFF_HSTL_I_DCI_18 Voco 18V l DIFF_HSTL_I_DCI_18 2Rypp 2Zo 1000 E 2Rypy 2Zg 1000 ugi 90 6 52 030306 Figure 6 54 Differential HSTL 1 8V Class I DCI Unidirectional Termination Virtex 5 FPGA User Guide www xilinx com 261 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 22 lists the differential HSTL Class I 1 8V DC voltage specifications Table 6 22 Differential HSTL Class I 1 8V DC Voltage Specifications Min Typ Max Vice 17 18 19 Vas Veco X 0 5 Vin DC 0 30 n Veale Vois OO 0 20 E Vero 0 60 Vom DO 0 83 1 08 vrag 0 40 z Veco 0 60 Vx Crossover 0 83 1 08 Notes 1 Common mode voltage Vem Vp Vp Vx 2 2 Crossover point Vy where Vp Vy 0 AC coupled HSTL Class II 1 8V Figure 6 55 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 8V with unidirectional termination External Termination Vy 0 9V Vr 0 9V IOB IOB HSTL_II_18 HSTL_II_18 Rp Z 502 Rp Z 509 X 2 X Vngr 0 9V L DCI IOB IOB 2Rypp 2Zo 1002 2Rygp 2Zg 1002 ir cdd HSTL Il DCI 18 xan Vggr 0 9V 2Rypy 2Zo 1000 E 2Rypn 2Zg 1000 L B ug190_6_53_030306 F
59. 91 LatnitatiOnls b dane oe eee oe eae dace PE D eun dude p ee tiq ded aed ae 91 VCO Operating RAM Ge ge steps adde tpud e dede lea ends 91 Minimum and Maximum Input Frequency 6 6 0c eee ee eee ee 91 Duty Cycle Programmability 0 0 nnne annann rnrn araara 91 Phase Shift urere Preterea e ER woe ee ce Ra ae aed 92 PLE Programuung esee ete erp hHkRR er epar E arr h e aes aoa he Res qud n dese dis 92 Determine the Input Frequency esee 92 Determine the M and D Values 0 0 0 ccc cc cent een eens 93 1d BFF Be ee PR 93 PLE ADUS at caeco dioc eei ee e e pee Eos tle d acing oud ORAT REIR 95 PLL CLKIN1 and CLKIN2 Usage 0 0 cece ee 97 PEL Clock Input Signals sece er terepe eee eee mme aie ente deese drea 98 Counter Control 4d EE HC ead de d e eu ie P e i ena oed 99 Clock Shifting ee ede tiet eren repetir eb n geb esee qb mated atop eae ees 100 Detailed VCO and Output Counter Waveforms 005 100 Reference Clock Switching iui d3 6 EU eb p FR ux Y du EP ese 101 Missing Input Clock or Feedback Clock 00 0 cece eee eee 102 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 10 XILINX PLL Use Models 0 00 0 ouaaa RR 102 Clock Network Deskew eeeeeeee eR RI n 102 PLL with Internal Feedback llli 103 Zero Delay Buffer ke e bebe ba bak 3 e seesaw i 103 DCM Driving PLL oet RR Rr Ub per DENRA Re seren
60. A Virtex 4 FPGA ECC 18K Virtex 5 FPGA User Guide www xilinx com 157 UG190 v4 4 December 2 2008 Chapter 4 Block RAM 158 XILINX block RAM mapped for a Virtex 5 FPGA design will occupy the entire RAMB36 site FIFO36_72 supports standard ECC mode only ECC Modes Overview In the standard ECC mode EN_ECC_READ TRUE and EN_ECC_WRITE TRUE both encoder and decoder are enabled During write 64 bit data and 8 bit ECC generated parity are stored in the array The external parity bits are ignored During read the 72 bit decoded data and parity are read out The encoder and decoder can be accessed separately for external use in RAMB36SDP To use the encoder by itself send the data in through the DI port and sample the ECCPARITY output port To use the decoder by itself disable the encoder write the data into the block RAM and read the corrected data and status bits out of the block RAM See Block RAM RAMB36SDP Attributes To use the decoder in ECC decode only mode set EN_ECC_WRITE FALSE and EN_ECC_READ TRUE The encoder can be used in two ways e To use the encoder in standard ECC mode set EN ECC WRITE TRUE and EN ECC READ TRUE In this mode the DI setup time is smaller but the clock to out for ECCPARITY is larger e To use the encoder only mode set EN ECC WRITE TRUE and EN ECC READ FALSE In this mode the DI setup time is larger but the clock to out for ECCPARITY is smaller The funct
61. Any inverter placed on the clock signal is automatically absorbed The CE SR and REV signals are active High All flip flop and latch primitives have CE and non CE versions The SR signal forces the storage element into the state specified by the attribute SRHIGH or SRLOW SRHIGH forces a logic High at the storage element output when SR is asserted while SRLOW forces a logic Low at the storage element output When SR is used an optional second input DX forces the storage element output into the opposite state via the REV pin The reset condition is predominant over the set condition see Figure 5 5 Table 5 3 and Table 5 4 provide truth tables for SR and REV depending on whether SRLOW or SRHIGH is used Table 5 3 Truth Table when SRLOW is Used Default Condition SR REV Function 0 0 No Logic Change 0 T 1 176 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview Table 5 3 Truth Table when SRLOW is Used Default Condition Continued SR REV Function 1 0 0 1 1 0 Table 5 4 Truth Table when SRHIGH is Used SR REV Function 0 0 No Logic Change 0 1 0 1 0 1 1 1 0 LUT D Output DQ SRHIGH and SRLOW can be set individually for each storage element in a slice The choice DX Cx SR AX C gt LUT C Output O LUT B Output ji LUT A Output d
62. Chapter 4 Added new text and equation to Almost Empty Flag page 145 Added note 1 to Table 4 19 page 147 Chapter 5 Changed RAM XM to RAM M in Figure 5 32 page 210 Chapter 6 Corrected PCI acronym definition in PCI X PCI 33 PCI 66 Peripheral Component Interconnect page 244 Added to the description of the SSTL18 II T DCI standard in SSTL18 II T DCI 1 8V Split Thevenin Termination page 290 Chapter 7 Added mode to caption of Figure 7 7 page 319 for clarification Chapter 8 Added statement about shared resources between OCLK and CLK in High Speed Clock for Strobe Based Memory Interfaces OCLK page 353 UG190 v4 4 December 2 2008 www xilinx com Virtex 5 FPGA User Guide Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 Table of Contents R vision History ap in Jolie ope dud afe Gas E en NS e aS ICE ee a ee teed ard 3 Preface About This Guide Additional Documentation ssssssssssss eee 19 Additional Support Resources eee 20 Typographical Conventions iertosodhade guerre dado dia ec deae 20 Online Document obese eed ace oe dee le dae Ve d ecko 20 Chapter 1 Clock Resources Global and Regional Clocks usse eee 21 Global Clock 5 eee ette BEDS RERO uea EE atia utn e SUPE EE 21 Regional Clocks and I O Clocks 0 0 00 e eee 21 Global Clocking Resources 22 Global Clock Inputs eoe px deeds Gk oe e e E RU ee ect 22 Global Clock
63. DBRAM DO ug190_4_29_071607 Figure 4 13 SSR Operation in Register Mode with Variable REGCE Block RAM Timing Model This section describes the timing parameters associated with the block RAM in Virtex 5 devices illustrated in Figure 4 14 The switching characteristics section in the Virtex 5 FPGA Data Sheet and the Timing Analyzer TRCE report from Xilinx software are also available for reference Virtex 5 FPGA User Guide www xilinx com 133 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Block RAM Timing Parameters Table 4 11 shows the Virtex 5 FPGA block RAM timing parameters Table 4 11 Block RAM Timing Parameters Control Parameter Function Signal Description Setup and Hold Relative to Clock CLK TrxCK_x Setup time before clock edge and Tpcy x Hold time after clock edge TRCCK_ADDR Time before the clock that address signals must be stable at the ADDR inputs of the block RAM Address inputs ADDR TRCKC_ADDR Time after the clock that address signals must be stable at the ADDR inputs of the block RAM TRDCK_DI Time before the clock that data must be stable at the DI inputs of the block RAM Data inputs DI TRCKD_DI Time after the clock that data must be stable at the DI inputs of the block RAM Tncck EN Time before the clock that the enable signal must be stable at the EN input of the block RAM Enabl
64. DO 7 0 pins of Virtex 5 FPGA DCM_ADV map to Status 7 0 of the Virtex II or Virtex II Pro FPGA DCMs DO 15 8 of DCM_ADV are not available when using Virtex II or Virtex II Pro FPGA DCMs www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Chapter 3 Phase Locked Loops PLLs Introduction The clock management tile CMT in Virtex 5 FPGAs includes two DCMs and one PLL There are dedicated routes within a CMT to couple together various components Each block within the tile can be treated separately however there exists a dedicated routing between blocks creating restrictions on certain connections Using these dedicated routes frees up global resources for other design elements Additionally the use of local routes within the CMT provides an improved clock path because the route is handled locally reducing chances for noise coupling The CMT diagram Figure 3 1 shows a high level view of the connection between the various clock input sources and the DCM to PLL and PLL to DCM dedicated routing The six total PLL output clocks are muxed into a single clock signal for use as a reference clock to the DCMs Two output clocks from the PLL can drive the DCMs These two clocks are 100 independent PLL output clock 0 could drive DCM1 while PLL output clock 1 could drive DCM2 Each DCM output can be muxed into a single clock signal for use as a reference clock to the PLL Only one DCM can be used as the referen
65. Derating Method PFDM 0 00 cece eee 309 Weighted Average Calculation of SSO 0 0 0 0 0 eee 311 Full Device SSO Calculator 0 0 ccc e 312 Other SSO Assumptions lt ra neinki cen en 312 LVDCI and HSLVDCI Drivers 0 0 0 ccc err rs 312 Bank O soos leat n pd Eu evade ne at pete LI 312 Chapter 7 SelectlO Logic Resources Introduction 2000 0 0 nee tenn e e ls 313 ILOGIC Resources obe CHR EG SEDE REED NERA RA EUER 314 Combinatorial Input Path 0 6 nee eee 315 Input DDR Overview IDDR 0 nnn 315 OPPOSITE EDGE Mode 533b eed ceed DC RR Hawa EPOR VEA Du seek eke 315 SAME EDGE Mode cece hh e hc een 316 SAME EDGE PIPELINED Mode sees n 316 Input DDR Primitive IDDR esssssssssee Ie 317 IDDR VHDL and Verilog Templates 6 0 coe 318 ILOGIC Timing Models erre era ces hae dati e ties PEE RE E es 318 ILOGIC Timing Characteristics 60 ec ne 318 ILOGIC Timing Characteristics DDR 6 eee eens 319 Input Output Delay Element IDDELAY s sess 321 IODELAY Primitive RC Oa E oa eRe eee wD 322 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 15 XILINX TODELAY POEttS 44 Rem rRRRER RU RERE SENA US RP du a RP DER sede RSS 323 IODELAY Attributes lsseleeeeeee RR RI IR lt 325 IODELAY Timing ovt C ROLE YER EE RIS ee TE PEE VERRE PS d REP oe En 326 Stability after an Increment Decrement Operati
66. Each half of the die top bottom contains 16 global clock buffers A global clock input can directly connect from the P side of the differential input pin pair to any global clock buffer input in the same half either top or bottom of the device Each differential global clock pin pair can connect to either a differential or single ended clock on the PCB If using a single ended clock then the P side of the pin pair must be used because a direct connection only exists on this pin For pin naming conventions please refer to the Virtex 5 Family Packaging Specifications A single ended clock must be connected to the positive P side of the differential global clock pins If a single ended clock is connected to the P side of a differential pin pair then the N side can not be used as another single ended clock pin However it can be used as a user I O The 20 global clock pins on Virtex 5 devices can be connected to 20 differential or 20 single ended board clocks Global clock buffers allow various clock signal sources to access the global clock trees and nets The possible sources for input to the global clock buffers include e Global clock inputs e Clock Management Tile CMT outputs including Digital Clock Managers DCMs Phase Locked Loops PLLs e Other global clock buffer outputs e General interconnect The global clock buffers can only be driven by sources in the same half of the die top bottom All global clock buffers can dr
67. FPGA PMCD Legacy Mode in Chapter 3 for more information 70 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Application Examples Application Examples The Virtex 5 FPGA DCM can be used in a variety of creative and useful applications The following examples show some of the more common applications Standard Usage The circuit in Figure 2 8 shows DCM_BASE implemented with internal feedback and access to RST and LOCKED pins This example shows the simplest use case for a DCM DCM_BASE BUFG IBUFG CLKO gt CLK90 CLK180 CLK270 IBUF CLK2X CLK2X180 CLKDV V y CLKFX CLKFX180 LOCKED gt OBUF ug190_2_08_032506 Figure 2 8 Standard Usage Board Level Clock Generation The board level clock generation example in Figure 2 9 illustrates how to use a DCM to generate output clocks for other components on the board This clock can then be used to interface with other devices In this example a DDR register is used with its inputs connected to GND and Vcc Because the output of the DCM is routed to BUFG the clock stays within global routing until it reaches the output register The quality of the clock is maintained The board level clock generation example in Figure 2 10 with internal feedback illustrates the clock generation for a forwarded clock on the board Virtex 5 FPGA User Guide www xilinx com 71 UG190 v4 4 December 2 2008 Chapter 2 Clock
68. FULL WREN EMPTY WRCLK ALMOSTFULL RST ALMOSTEMPTY RDERR WRERR ug190_4_15_021107 Figure 4 18 FIFO36 Primitive Virtex 5 FPGA User Guide www xilinx com 141 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Figure 4 19 shows the FIFO18 primitive FIFO18 DI 15 0 DO 15 0 DIP 1 0 DOP 1 0 RDEN WRCOUNT 11 0 RDCLK RDCOUNT 11 0 FULL WREN EMPTY WEEE ALMOSTFULL RST ALMOSTEMPTY RDERR WRERR ug190 4 15 040606 Figure 4 19 FIFO18 Primitive FIFO Port Descriptions Table 4 15 lists the FIFO I O port names and descriptions Table 4 15 FIFO I O Port Names and Descriptions Port Name Direction Description DI Input Data input DIP Input Parity bit input WREN Input Write enable When WREN 1 data will be written to memory When WREN 0 write is disabled WRCLK Input Clock for write domain operation RDEN Input Read enable When RDEN 1 data will be read to output register When RDEN 0 read is disabled RDCLK Input Clock for read domain operation RESET Input Asynchronous reset of all FIFO functions flags and pointers RESET must be asserted for three clock cycles DO Output Data output synchronous to RDCLK DOP Output Parity bit output synchronous to RDCLK FULL Output Allentries in FIFO memory are filled No additional writes are accepted Synchronous to WRCLK ALMOSTFULL Output Almost all entries in FIFO memory have bee
69. HSTL Class IV Figure 6 49 shows a sample circuit illustrating a valid unidirectional termination technique for HSTL Class IV External Termination Va 1 5V Vez 1 5V IOB IOB HSTL IV HSTL IV Rp2Zg250Q0 Rp Z 502 bd C zo x Vege 0 9V G DCI EE JOB IOB 7 00000 0 s Vcco 1 5V Vcco 1 5V Rypp Zo 502 Rypp Zg 500 HSTL_IV_DCI HSTL_IV_DCI x 4 _ Vggr 0 9V a ee en ee I a ee ug190_6_48_030306 Figure 6 49 HSTL Class IV Unidirectional Termination Figure 6 50 shows a sample circuit illustrating a valid bidirectional termination technique for HSTL Class IV Virtex 5 FPGA User Guide www xilinx com 257 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX External Termination TAREA enn OB Vr 1 5V Vr 1 5V P ee HSTL_IV HSTL_IV Rp Zo 500 l l l l Vper 0 9V i l l DCI IOB IOB Veco 1 5V Veco 15V Rygp Zg 500 Rypp Zg 502 HSTL IV DCI HSTL IV DCI Dq Q an l i Vpger 0 9V l l Vngr 0 9V l z ugi90 6 49 030306 Figure 6 50 HSTL Class IV Bidirectional Termination 258 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Table 6 20 lists the HSTL Class IV DC voltage specifications Table 6 20 HSTL Class IV DC Voltage Specifications Min Typ Ma
70. IDELAYCTRLs Without LOC Constraints Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited If this occurs an error is issued by the implementation tools OLOGIC Resources OLOGIC consists of two major blocks one to configure the output data path and the other to configure the 3 state control path These two blocks have a common clock CLK but different enable signals OCE and TCE Both have asynchronous and synchronous set and reset SR and REV signals controlled by an independent SRVAL attribute as described in the Table 7 1 and Table 7 2 340 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX OLOGIC Resources The Output and the 3 State paths can be configured in one of the following modes independently e Edge triggered D type flip flop e DDR mode SAME EDGE or OPPOSITE EDGE e Level Sensitive Latch e Asynchronous combinatorial Figure 7 22 illustrates the various logic resources in the OLOGIC block SR gt PEV ug190_7_17_041206 Figure 7 22 OLOGIC Block Diagram This section of the documentation discusses the various features available using the OLOGIC resources All connections between the OLOGIC resources are managed in Xilinx software Combinatorial Output Data and 3 State Control Path The combinatorial output paths create a direct connection from the FPGA fabric to the output driver or output driver control
71. III uses Veco asa parallel termination voltage Vyr HSTL I and HSTL III are intended to be used in unidirectional links HSTL l DCI HSTL Ill DCl HSTL DCI 18 HSTL Ill DCI 18 HSTL I DCI provides on chip split thevenin termination powered from V coo creating an equivalent parallel termination voltage Vrr of Vcco 2 HSTL III DCI provides on chip single termination powered from Veco HSTL I DCI and HSTL III DCI are intended to be used in unidirectional links HSTL ll HSTL IV HSTL Il 18 HSTL IV 18 HSTL II uses Vcco 2 as a parallel termination voltage Vy HSTL IV uses Vcco asa parallel termination voltage Vyr HSTL II and HSTL IV are intended to be used in bidirectional links Virtex 5 FPGA User Guide www xilinx com 247 UG190 v4 4 December 2 2008 248 Chapter 6 SelectlO Resources XILINX HSTL II_DCI HSTL IV_DCI HSTL II DCI 18 HSTL IV DCI 18 HSTL II DCI provides on chip split thevenin termination powered from Veco creating an equivalent termination voltage of Vcco 2 HSTL_IV_ DCI provides single termination to Veco Vgr HSTL II DCI and HSTL IV DCI are intended to be used in bidirectional links HSTL T DCI HSTL Il T DCI 18 HSTL II T DCI and HSTL II T DCI 18 provide on chip split thevenin termination powered from Vcco that creates an equivalent termination voltage of Vcco 2 when these standards are 3 stated When not 3 stated these two standards do not have termination DIFF HSTL l DIFF HSTL I
72. Incompatible example LVCMOSI5 input Vcco 1 5V and LVCMOS18 input Vcco 1 8V inputs Incompatible example HSTL_I_DCI_18 Vggg 0 9V and HSTL_IV_DCI_18 Vpgp 1 1V inputs 3 Combining input standards and output standards Input standards and output standards with the same Vcco requirement can be combined in the same bank Compatible example LVDS 25 output and HSTL_I input Incompatible example LVDS_25 output output Veco 2 5V and HSTL I DCI 18 input input Vcco 1 8V 4 Combining bidirectional standards with input or output standards When combining bidirectional I O with other standards make sure the bidirectional standard can meet the first three rules 5 Additional rules for combining DCI I O standards a Nomore than one Single Termination type input or output is allowed in the same bank Incompatible example HSTL IV DCI input and HSTL III DCI input b No more than one Split Termination type input or output is allowed in the same bank Incompatible example HSTL_I_DCI input and HSTL II DCI input The implementation tools enforce these design rules Virtex 5 FPGA User Guide www xilinx com 295 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 39 summarizes the Virtex 5 FPGA supported I O standards Table 6 39 VO Compatibility
73. Input Buffer Primitives 6 nuunuu sasan e 22 Clock Gating for Power Savings ssssssesesse e 22 Global Clock Buffers 2 0 0 0 0 ccc ee RI IR ne 23 Global Clock Buffer Primitives 0 0 0 ccc ccc cence eee nee 24 Additional Use Models 0 0 cee nett ne hr has 32 Clock Tree and Nets GCLK 1 0 0 0 ccc cence cee teen en ene 34 Glock R gions 5 m9 eR exer n RM RERO breed bieed eee LEN er 34 Regional Clocking Resources 21er rep ieee CER ice ple ol C Rc d e A gae 36 Clock Capable I Q sese RR nee ere rk URL PLE a eden 36 I O Clock Buffer BUFIO suseseeeeeeeese RR mn 37 BUEIO Primitive i i BA eh rac bd e duy wc e d ace dac Edd 37 BUBIO Use Models 6 eee ed 0 bole ad ob recte Wade ae EEEa n RR Mat UR tud 37 Regional Clock Buffer BUFR sssssssseseeeeee III e 39 bDUER Primitlve s zu aer hei Re rre rH RC En eie ox a GU Rete 39 BUFR Attributes and Modes 0 000 ccc eee een hr 40 BUFR Use Models der 5 ace RR RU RR CER CE e E ga 41 Regional Clock Nets a estbect he ERES CR RH Ehe e HRS Od de eee eee 42 VHDL and Verilog Templates eren edeateee eR deRr Rem dene dete a 42 Chapter 2 Clock Management Technology Clock Management Summary ssusssssssss eee 43 DCM SONDA y uccidere vr RE OR EPI UI HER I PEE EE E DEA EV er PEPPER s 44 DCM Primitives usus Re e 46 DCM BASEPrimitive leeeeeeeeee eR RR e hrs 46 DEM ADV Primitive ocsrezierierwete dee bed
74. Ir at Vor mA 48 E Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user HSTL Il T DCI 18 1 8V Split Thevenin Termination Figure 6 64 shows a sample circuit illustrating a valid termination technique for HSTL II T DCI 18 1 8V with on chip split thevenin termination In this bidirectional case when 3 stated the termination is invoked on the receiver and not on the driver DCI Not 3 stated 3 stated IOB IOB Voco 1 8V 2Rypp 2Z9 1000 HSTL_II_T_DCI_18 HSTL IIl T DCI 18 D1 Q 40 P4 4 Vper 0 9V Ver 0 9V 2Rypn 2Zg 1000 ug190_6_91_041206 Figure 6 64 HSTL II T DCI 18 Split Thevenin Termination 270 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards HSTL Class 1 2V Figure 6 65 shows a sample circuit illustrating a valid termination technique for HSTL Class I 1 2V It is used for unidirectional links External Termination Vr 0 6V IOB HSTL_I_12 HSTL_I_12 Rp Zo 509 x m Ver 0 6V ug190_6_62_030306 Figure 6 65 HSTL Class 1 2V Termination Table 6 21 lists the HSTL Class I 1 2V DC voltage specifications Table 6 27 HSTL Class I 1 2V DC V
75. LOCKED is lost the DCM needs to be reset to resume operation When the DLL portion of the DCM is not used for example when using CLKFX output only the CLKFB can be left unconnected In this case DO 3 is deasserted DO 15 4 Notassigned When LOCKED is Low during reset or the locking process all the status signals are deasserted Low Dynamic Reconfiguration Ready Output DRDY The dynamic reconfiguration ready DRDY output pin provides the response to the DEN signal for the DCM s dynamic reconfiguration feature Further information on the DRDY pin is available in the dynamic reconfiguration section in the Virtex 5 FPGA Configuration Guide Virtex 5 FPGA User Guide www xilinx com 53 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX DCM Attributes A handful of DCM attributes govern the DCM functionality Table 2 6 summarizes all the applicable DCM attributes This section provides a detailed description of each attribute For more information on applying these attributes in UCF VHDL or Verilog code refer to the Constraints Guide at http www support xilinx com support software manuals htm CLKDV DIVIDE Attribute The CLKDV DIVIDE attribute controls the CLKDV frequency The source clock frequency is divided by the value of this attribute The possible values for CLKDV DIVIDE are 1 5 2 2 5 8 8 5 4 4 5 5 5 5 6 6 5 7 7 5 8 9 10 11 12 13 14 15 or
76. LVDCI_DV2 A controlled impedance driver with half impedance source termination can also provide drivers with one half of the impedance of the reference resistors This allows reference resistors to be twice as large thus reducing static power consumption through VRN VRP The I O standards supporting a controlled impedance driver with half impedance are LVDCI_DV2_15 LVDCI_DV2_18 and LVDCI_DV2_25 Figure 6 32 and Figure 6 33 illustrate a controlled driver with half impedance unidirectional and bidirectional termination To match the drive impedance to Zo when using a driver with half impedance the reference resistor R must be twice Zp IOB l IOB LVDCI_DV2 LVDCI_DV2 gt e Ro Avan Rvpp o ug190_6_30_022806 Figure 6 32 Controlled Impedance Driver with Half Impedance Unidirectional Termination IOB IOB LVDCI_DV2 LVDCI_DV2 KAQ 4 __X Ro Rypy Rvypp Zo Ro Avan Ryrp Zo ug190_6_31_022806 Figure 6 33 Controlled Impedance Driver with Half Impedance Bidirectional Termination There are no drive strength settings for LVDCI drivers When the driver impedance is one half of the VRN VRP reference resistors it is indicated by the addition of DV2 to the attribute name Table 6 9 lists the LVCMOS LVDCI and LVDCI DV2 voltage specifications Virtex 5 FPGA User Guide www xilinx com 241 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Re
77. Management Technology XILINX Outside FPGA Inside FPGA Voc DCM_ADV IBUFG CLKO gt CLKIN CLK90 CLK180 IBUFG CLKFB CLK270 CLK2X CLK2X180 RST CLKDV CLKFX PSINCDEC CLKFX180 PSEN PSCLK V DADDR 6 0 DI 15 0 DWE DEN DCLK LOCKED DO 15 0 UG190 2 09 042308 Figure 2 9 Board Level Clock Using DDR Register with External Feedback Vcc N ODDR BUF IBUFG DCM ADV UFG CLKO CLKIN CLK90 CLK180 p CLKFB CLK270 GND CLK2X CLK2X180 RST CLKDV CLKFX PSINCDEC CLKFX180 PSEN PSCLK DADDR 6 0 LOCKED DI 15 0 DO 15 0 DWE DEN DCLK ugi90 2 11 032506 Figure 2 10 Board Level Clock with Internal Feedback 72 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Application Examples Board Deskew with Internal Deskew Some applications require board deskew with internal deskew to interface with other devices These applications can be implemented using two or more DCM The circuit shown in Figure 2 11 can be used to deskew a system clock between multiple Virtex devices in the same system Virtex 5 FPGA User Guide www xilinx com 73 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Virtex 5 FPGA Vcc ODDR A DCM_ADV D1 Q CLKIN CLKO gt ian CLKFB CLK90 CLK180 CLK270 RST CLK2X PSINCDEC CLK2X180 PSEN CLKDV PSCLK CLKFX DADDR eo CLKFX180 DI 15 0 OBUF DW
78. Read Operation and Deassertion of Read Error Signal The read error signal pin is deasserted when a user stops trying to read from an empty FIFO At time Tgcck RDEN before clock event 4 RDCLK read enable is deasserted at the RDEN input of the FIFO At time Trcko RpERR after clock event 4 RDCLK read error is deasserted at the RDERR output pin of the FIFO The read error signal is asserted deasserted at every read clock positive edge As long as both the read enable and empty signals are true read error will remain asserted Case 5 Resetting All Flags RST Lo WHeUe A 1 1 Lp LT La EF 1L rook I LI LI LI LI LIL l Trco EMPTY EMPTY gt __ TrFCcO AEMPTY AEMPTY gt l Trco FuLL FULL l Trco AFULL AFULL ugi90 4 22 032506 Figure 4 25 Resetting All Flags When the reset signal is asserted all flags are reset Virtex 5 FPGA User Guide At time Tgco Empty after reset RST empty is asserted at the EMPTY output pin of the FIFO At time Taco AgyprY after reset RST almost empty is asserted at the AEMPTY output pin of the FIFO At time Trco FULL after reset RST full is deasserted at the FULL output pin of the FIFO At time Tyco aFuLL after reset RST almost full is deasserted at the AFULL output pin of the FIFO www xilinx com 155 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Reset is an asynchronous signal used to reset all flags Hold th
79. Sceneries Settings Primitive Effective Read Width Effective Write Width Read Width Write Width RAMBI18 1 2 0r4 9 or 18 Same as setting 8 or 16 RAMBI18 9 or 18 1 2 or 4 8 or 16 Same as setting RAMB18 1 2 or 4 1 2 or 4 Same as setting Same as setting RAMB18 9 or 18 9 or 18 Same as setting Same as setting 112 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Introduction Table 4 1 Parity Use Sceneries Continued Settings Primitive Effective Read Width Effective Write Width Read Width Write Width RAMB36 1 2 0r4 9 18 or 36 Same as setting 8 16 or 32 RAMB36 9 18 or 36 1 2 0r4 8 16 or 32 Same as setting RAMB36 1 2 or 4 1 2 or 4 Same as setting Same as setting RAMB36 9 18 or 36 9 18 or 36 Same as setting Same as setting Notes 1 Donot use parity bits DIP DOP when one port widths is less than nine and another port width is nine or greater Block RAM Introduction In addition to distributed RAM memory and high speed SelectIO memory interfaces Virtex 5 devices feature a large number of 36 Kb block RAMs Each 36 Kb block RAM contains two independently controlled 18 Kb RAMs Block RAMs are placed in columns and the total number of block RAM memory depends on the size of the Virtex 5 device The 36 Kb blocks are cascadable to enable a deeper and wider memory implementation with a minimal timing
80. TRCCK EN before time T1W write enable becomes valid at the WREN input of the block RAM e Attime TRCCK ADDR before time T1W write address a becomes valid at the WRADDRJ8 0 inputs of the block RAM WRADDR input is not needed for FIFO e Attime TRDCK DI ECC standard ECC before time T1W write data A hex becomes valid at the DI 63 0 inputs of the block RAM e At time TRCKO ECC PARITY standard ECC after time T1W ECC parity data PA hex becomes valid at the ECCPARITY 7 0 output pins of the block RAM Standard ECC Read Timing Figure 4 32 e At time TRCCK EN before time T1R read enable becomes valid at the RDEN input of the block RAM e Attime TRCCK ADDR before time T1R write address a becomes valid at the RDADDR S8 0 inputs of the block RAM RDADDR input is not needed for FIFO DO REG 0 At time TRCKO DO latch mode after time T1R data A hex becomes valid at the DO 63 0 output pins of the block RAM At time TRCKO DOP latch mode after time T1R data PA hex becomes valid at the DOP 7 0 output pins of the block RAM Attime TRCKO ECC SBITERR latch mode after time TIR SBITERR is asserted if single bit error is detected and corrected on data set A At time TRCKO ECC DBITERR latch mode after time T2R DBITERR is asserted if double bit error is detected on data set B DO REG 1 At time TRCKO DO register mode after time T2R data A hex becomes valid at the DO 63 0 output pins of th
81. Table 6 33 and Table 6 34 lists the SSTL 1 8V DC voltage specifications for Class I and Class II respectively Table 6 33 SSTL 1 8V DC Voltage Specifications Class Specific Guidelines for I O Supported Standards Class Min Typ Max Veco 17 1 8 1 9 Veer 0 5x Veco 0 833 0 9 0 969 Vir Vggr NO 0 793 0 9 1 009 Ving 2 Vggr t 0 125 0 958 Veco 0 32 Vig Vggr 0 125 0 30 0 844 Von 2 Vrr 0 474 1 263 S Vor S Ver 0 474 0 539 Tox at Voy mA 6 7 Ior at Vor mA 6 7 Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Vin maximum is Veco 0 3 3 Vy minimum does not conform to the formula 4 Because SSTL I DCI uses a controlled impedance driver Voy and Vo are different Table 6 34 SSTL 1 8V DC Voltage Specifications Class Il Class Il Min Typ Max Veco 1 7 1 8 1 9 Veer 0 5x Veco 0 833 0 9 0 969 Vor Vggg NO 0 793 0 9 1 009 Vig 2 Vggrp 0 125 0 958 Veco 0 32 Vy Vggg 0 125 0 30 0 844 Vou Vrr 0 6030 1 396 VoL Vrr 0 603 0 406 Iog at Voy mA 13 4 IoL at Vor mA 13 4 a 2 Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 Fi Vin maximum is Veco 0 3 2 3 Vy minimum does not conform to the formula 4 Because SSTL I DCI uses a controlled impedance driver Voy and Vo
82. These paths is used when 1 There is direct unregistered connection from logic resources in the FPGA fabric to the output data or 3 state control 2 The pack I O register latches into IOBs is set to OFF Output DDR Overview ODDR Virtex 5 devices have dedicated registers in the OLOGIC to implement output DDR registers This feature is accessed when instantiating the ODDR primitive DDR multiplexing is automatic when using OLOGIC No manual control of the mux select is needed This control is generated from the clock There is only one clock input to the ODDR primitive Falling edge data is clocked by a locally inverted version of the input clock All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between ILOGIC or OLOGIC blocks The ODDR primitive supports the following modes of operation e OPPOSITE_EDGE mode e SAME EDGE mode Virtex 5 FPGA User Guide www xilinx com 341 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX The SAME_EDGE mode is the same as for the Virtex 4 architecture This mode allows designers to present both data inputs to the ODDR primitive on the rising edge of the ODDR clock saving CLB and clock resources and increasing performance This mode is implemented using the DDR CLK EDGE attribute It is supported for 3 state control as well The following sections describe each of the modes in detail OPPOSITE EDGE Mode In OPPOSITE EDGE
83. This eliminates the need for termination resistors on the board reduces board routing difficulties and component count and improves signal integrity by eliminating stub reflection Stub reflection occurs when termination resistors are located too far from the end of the transmission line With DCI the termination resistors are as close as possible to the output driver or the input buffer thus eliminating stub reflections DCI Cascading Previously using DCI I O standards in a bank required connecting external reference resistors to the VRN and VRP pins in that same bank The VRN VRP pins provide a reference voltage used by internal DCI circuitry to adjust the I O output impedance to match the external reference resistors As shown in Figure 6 4 a digital control bus is internally distributed throughout the bank to control the impedance of each I O To Local DCI VRN VRP Bank UG190 6 95 019507 Figure 6 4 DCI Use within a Bank www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines The Virtex 5 FPGA banks using DCI I O standards now have the option of deriving the DCI impedance values from another DCI bank With DCI cascading one bank the master bank must have its VRN VRP pins connected to external reference resistors Other banks in the same column slave banks can use DCI standards with the same impedance as the master bank without connecting the VRN VRP pins
84. Trcck_WREN WREN Tfpck DI TFDCK DI DI a m Wem xD mE 06 RDCLK l l l l l l l RDEN l x TrFcKO DO DO 00 p M TrFcko EMPTY EMPTY l TFcKO AEMPTY gt I AEMPTY i i ug190_4_18 032506 Figure 4 21 Writing to an Empty FIFO in FWFT Mode Clock Event 1 and Clock Event 3 Write Operation and Deassertion of EMPTY Signal During a write operation to an empty FIFO the content of the FIFO at the first address is replaced by the data value on the DI pins Three read clock cycles later four read clock cycles for FWFT mode the EMPTY pin is deasserted when the FIFO is no longer empty The RDCOUNT also increments by one due to an internal read preloading the data to the output registers For the example in Figure 4 21 the timing diagram is drawn to reflect FWFT mode Clock event 1 is with respect to the write clock while clock event 3 is with respect to the read clock Clock event 3 appears four read clock cycles after clock event 1 e At time Tppcy pr before clock event 1 WRCLK data 00 becomes valid at the DI inputs of the FIFO e At time Trcck wren before clock event 1 WRCLK write enable becomes valid at the WREN input of the FIFO e At time Trcko po after clock event 3 RDCLK data 00 becomes valid at the DO output pins of the FIFO In standard mode data 00 does not appear at the DO output pins of the FIFO e At time TecKo Empty after clock event 3 RDCLK
85. User Guide UG190 v4 4 December 2 2008 XILINX 8 1 Multiplexer CLB Overview Each slice has an FZAMUX and an F7BMUX These two muxes combine the output of two LUTs to form a combinatorial function up to 13 inputs or an 8 1 MUX Up to two 8 1 MUxXes can be implemented in a slice as shown in Figure 5 22 SLICE poca xD cM eT LUT I 06 D 6 1 SEL D 1 0 DATA D 3 0 c DIST 8 I Input 1 A 6 1 F7BMUX I CMUX gt 8 1 MUX l LUT j Output 1 CQ Registered l gt 06 Output SEL C 1 0 DATA C 3 0 1 C 6 1 A 6 1 P L EE se Input 1 l Optional i I I SELF7 1 Cx l CLK 4 CLK i LUT l I O6 I SEL B 1 0 DATA B 3 oj PEN s A 6 1 input a F7AMUX I VAMENS gt 8 1 MUX l LUT l Output 2 I O6 AQ _ Registered Output SEL A 1 0 DATA A 3 0 __ AI61 6 Aj6 1 p Input 2 Optional I SELF7 2 Sr I Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 Figure 5 22 Two 8 1 Multiplexers in a Slice www xilinx com UG190 5 22 090806 195 196 Chapter 5 Configurable Logic Blocks CLBs XILINX 16 1 Multiplexer Each slice has an FBEMUX F8MUX combines the outputs of FZFAMUX and F7BMUX to form a combinatorial function up to 27 inputs or a 16 1 MUX Only one 16 1 MUX can be implemented in a slice as shown in Figure 5 23 SLICE ee EE 7 l LU
86. User Guide www Xilinx com 245 UG190 v4 4 December 2 2008 2 XILINX Chapter 6 SelectlO Resources Table 6 13 GTL DC Voltage Specifications Continued Parameter Min Typ Max Vor 0 2 0 4 lon at Von mA s Toy at Vor mA at 0 4V 32 Ior at Vor mA at 0 2V 40 Notes 1 N must be greater than or equal to 0 653 and less than or equal to 0 68 GTLP Gunning Transceiver Logic Plus The Gunning Transceiver Logic Plus or GTL standard is a high speed bus standard JESD8 3 first used by the Pentium Pro Processor This standard requires a differential amplifier input buffer and a open drain output buffer The negative terminal of the differential input buffer is referenced to the Vpgr pin A sample circuit illustrating a valid termination technique for GTL with external parallel termination and unconnected Vcco is shown in Figure 6 37 7 i IOB V r 15V Vm 1 5V OR Vcco Unconnected Bpreep cu Perros IEEE Dj JL Vpr 1 0V ug190_6_36_030206 Figure 6 37 GTL with External Parallel Termination and Unconnected Vcco GTLP DCI Usage GTL does not require a Veco voltage However for GTLP_DCI Veco must be connected to 1 5V GILP DCI provides single termination to Veco for inputs or outputs A sample circuit illustrating a valid termination technique for GTLP_DCI with internal parallel driver and receiver termination is shown in Figure 6 38 IOB 7 Voc
87. XC5VLX220T to Table 1 5 Table 2 1 and Table 5 2 Chapter 4 Clarified wording in Synchronous Clocking on page 117 Chapter 6 Added DCI Cascading on page 218 Changed Vggg for SSTL18 II T DCI to 0 9 in Table 6 39 Chapter 7 Revised OQ in Figure 7 27 page 345 Chapter 8 Clock Enable Inputs CE1 and CE2 on page 352 UG190 v4 4 December 2 2008 www xilinx com Virtex 5 FPGA User Guide Date 09 11 07 Version 3 1 Revision Chapter 1 Added Clock Gating for Power Savings on page 22 Revised Figure 1 2 page 26 Revised Figure 1 16 page 33 Chapter 2 Revised DCM reset and locking process in Reset Input RST page 49 Updated DO 2 description in Table 2 4 page 52 Changed the multiply value range on page 54 Revised the description for FACTORY_JF Attribute page 57 Revised Output Clocks page 61 updated Figure 2 7 page 70 and added a BUFG to Figure 2 10 page 72 Added more steps to Dynamic Reconfiguration DRPs when loading new M and D values on page 69 Updated Figure 2 7 page 70 Revised bulleted descriptions under Figure 2 20 page 83 Chapter 3 Updated Figure 3 1 page 86 Add notes to Table 3 2 page 90 Added a note to Phase Shift page 92 Added rounding to Equation 3 3 through Equation 3 6 Revised CLKFBIN CLKFBDCM CLKFBOUT RST LOCKED and added the REL pin and note 2 to Table 3 3 page 93 Added RESET_ON_LOSS_OF_LOCK attribute to Table 3 4 page 95
88. block SHIFTIN1 Input 1 Carry input for data width expansion Connect to SHIFTOUT1 of slave OSERDES See OSERDES Width Expansion SHIFTIN2 Input 1 Carry input for data width expansion Connect to SHIFTOUT2 of slave OSERDES See OSERDES Width Expansion SR Input 1 Active High reset T1 to T4 Input 1 each Parallel 3 state inputs See Parallel 3 state Inputs T1 to T4 TCE Input 1 3 state clock enable See 3 state Signal Clock Enable TCE Data Path Output OQ The OQ portis the data output port of the OSERDES module Data at the input port D1 will appear first at OQ This port connects the output of the data parallel to serial converter to the data input of the IOB 3 state Control Output TQ This port is the 3 state control output of the OSERDES module When used this port connects the output of the 3 state parallel to serial converter to the control 3 state input of the IOB High Speed Clock Input CLK This high speed clock input drives the serial side of the parallel to serial converters Divided Clock Input CLKDIV This divided high speed clock input drives the parallel side of the parallel to serial converters This clock is the divided version of the clock connected to the CLK port 368 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Parallel to Serial Logic Resources OSERDES Parallel Data Inputs D1 to D6 All incoming parallel dat
89. counter to toggle PSINCDEC when it reaches 0 or 128 Phase Shift Characteristics 68 Offers fine phase adjustment with a resolution of 1 256 of the clock period or one DCM_TAP whichever is greater It can be dynamically changed under user control The phase shift settings affect all nine DCM outputs Vcc and temperature do not affect the phase shift except in direct phase shift mode In either fixed or variable mode the phase shift range can be extended by choosing CLK90 CLK180 or CLK270 rather than CLKO choosing CLK2X180 rather than CLK2X or choosing CLKFX180 rather than CLKFX Even at 25 MHz 40 ns period the fixed mode coupled with the various CLK phases allows shifting throughout the entire input clock period range MAX RANGE mode extends the phase shift range The phase shifting DPS function in the DCM requires the CLKFB for delay adjustment Because CLKFB must be from CLKO the DLL output is used The minimum CLKIN frequency for the DPS function is determined by DLL frequency mode www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX Connecting DCMs to Other Clock Resources in Virtex 5 Devices Dynamic Reconfiguration The Dynamic Reconfiguration Ports DRPs can update the initial DCM settings without reloading a new bit stream to the FPGA The DRP address mapping changed in Virtex 5 FPGAs The Virtex 5 FPGA Configuration Guide provides more information on using DRPs Specific to
90. delay and the DESKEW ADJUST parameter has no effect BitGen selects the appropriate DCM Tap settings These situations include www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Design Guidelines Downstream DCMs when two or more DCMs are cascaded e DCMs with external feedback e DCMs with an external CLKIN that does not come from a dedicated clock input pin Source Synchronous Setting When DESKEW ADJUST is set to source synchronous mode the DCM feedback delay element is set to zero As shown in Figure 2 4 in source synchronous mode the DCM clock feedback delay element is set to minimize the sampling window This results in a more positive hold time and a longer clock to out compared to system synchronous mode The source synchronous switching characteristics section in the Virtex 5 FPGA Data Sheet reflects the various timing parameters for the source synchronous design when the DCM is in source synchronous mode Characteristics of the Deskew Circuit e Eliminate clock distribution delay by effectively adding one clock period delay e Clocks are deskewed to within CLKOUT PHASE specified in the Virtex 5 FPGA Data Sheet e Eliminate on chip as well as off chip clock delay e No restrictions on the delay in the feedback clock path e Requires a continuously running input clock e Adapts to a wide range of frequencies However once locked to a frequency large input frequency variations are n
91. eee e AU RR dence UR RU EEEa 370 DATA WIDTH Attribute lee RR an 371 SERDES MODE Attribute sess sese yy kae ERR ADR RR RD P RR Rd 371 TRISTATE WIDTH Attribute 2 20 0 0 e an 371 OSERDES Clocking Methods ssssseseeeseeeee ee 371 OSERDES Width Expansion guie ieg a e e 371 Guidelines for Expanding the Parallel to Serial Converter Bit Width 372 OSERDES Latenicies eerdre e Pa hee eg a ee eee dl 373 OSERDES Timing Model and Parameters 00000 c cece eee eee eee 373 Timing Characteristics of 2 1 SDR Serialization lees 374 Timing Characteristics of 8 1 DDR Serialization sees 375 Timing Characteristics of 4 1 DDR 3 State Controller Serialization 376 Reset Output Tinie 22 deeekb e e eris e QR ERR peu Et Bonn sete ied 377 OSERDES VHDL and Verilog Instantiation Templates 06 378 NK seas op ee ee ee ead ei be eee 379 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 18 www xilinx com 2 XILINX Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Preface About This Guide This document describes the Virtex 5 architecture Complete and up to date documentation of the Virtex 5 family of FPGAs is available on the Xilinx website at http www xilinx com virtex5 Additional Documentation The following documents are also available for download at http www xilinx com vi
92. etre RR e ac te Pet en te RU ecu ed 272 SSTL2_I_ DCI SSTL18_T DCI c eR Rae yer yan Ren 272 SSTE2 If SSTLET8 I uem Rod ee ree Reo eem d UR ER A ORE 272 SSII2 II DCT SSTLA8 M DCI ou RR RR RR hah e geh os 272 DIBE SSTE2 D DIFF SSTEIS8 T a deeem mn eg te De n tino 272 DIFF SSTI2 I DCI DIFF SSTLI8 I DCI seeleeeeee ne 272 DIBEE SSTI2 T DIEF SSTLE18 II 52er utr Renee km n nh Rae 272 DIFF SSTI2 II DCI DIFF SSTL18 II DCI sllleeeeee e 272 SSTE2 M T DCI SSTEI8 H T DCE a one ae neir tuk eE EEEE a eR tee cete rd 272 SSTII2 ClassT 2 5V istis eene beer b 4 ead daw E Ca Idee e decise erre eng 273 Differential SSTL2 Class I 2 5V 0 ccc eee cee EAEE 274 SSTI2 Class II 2 5 V i eese teda end EE ed ree hl at od qoe ree p erg a 276 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Differential SSTL2 Class I1 2 5V ssssesssseeseese eee 278 SSTL2 II T DCI 2 5V Split Thevenin Termination sasun sess raserer 281 SSILI8 ClassI 1 8V tcc serv eR gx RARE ANEETA eR ee Nea 282 Differential SSTL Class I 1 8V r srriiii ecrin eii ittini CEE III 283 SSTLI8 Class IL 1 8V iese rrsn ect eve te DE E EE ERE Aa 285 Differential SSTL Class I 1 8V lsssssssesseeseee e e 288 SSTL18_II_T_DCI 1 8V Split Thevenin Termination 008 290 Differential Termination DIFF TERM Attribute 0 0 0 0 e 291 LVDS and Extended LVDS Low Voltag
93. exe i filb Si boaa t LT LT L cx L ULL JL LLL LL CLKFX180 eee r gewcpxa pes ae E i eee LOCKED TT Tq DLL ugi90 2 18 042406 Figure 2 17 RESET LOCK Example e Prior to Clock Event 1 Prior to clock event 1 the DCM is locked All clock outputs are in phase with the correct frequency and behavior e Clock Event 1 Some time after clock event 1 the reset signal is asserted at the RST pin While reset is asserted all clock outputs become a logic zero The reset signal is an asynchronous reset Note the diagram is not shown to scale For the DCM to operate properly the reset signal must be asserted for at least three CLKIN periods e Clock Event 2 Clock event 2 occurs a few cycles after reset is asserted and deasserted At clock event 2 the lock process begins At time LOCK_DLL after clock event 2 if no fixed phase 80 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Timing Models shift was selected then all clock outputs are stable and in phase LOCKED is also asserted to signal completion Fixed Phase Shifting In Figure 2 18 the DCM outputs the correct frequency However the clock outputs are not in phase with the desired clock phase The clock outputs are phase shifted to appear sometime later than the input clock and the LOCKED signal is asserted 1 coo 1 UO cudao 11
94. f CLKOUT2 a J CLKOUT3 CLKOUT4 4 CLKOUT5 CLKFBOUT BR e UG190 3 10 032506 Figure 3 10 Clock Deskew Using Two BUFGs There are certain restrictions on implementing the feedback The CLKFBOUT output can be used to provide the feedback clock signal The fundamental restriction is that both input frequencies to the PFD must be identical Therefore the following relationship must be met D frg VCO Equation 3 8 M As an example if f is 166 MHz D 1 M 3 and O 1 then VCO and the clock output frequency are both 498 MHz Since the M value in the feedback path is 3 both input frequencies at the PFD are 166 MHz In another more complex scenario has an input frequency of 66 66 MHz and D 2 M 15 and O 2 The VCO frequency in this case is 500 MHz and the O output frequency is 250 MHz Therefore the feedback frequency at the PFD is 500 15 or 33 33 MHz matching the 66 66MHz 2 input clock frequency at the PFD www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX PLL Use Models PLL with Internal Feedback The PLL feedback can be internal to the PLL when the PLL is used as a synthesizer or jitter filter and there is no required phase relationship between the PLL input clock and the PLL output clock The PLL performance should increase since the feedback clock is not subjected to noise on the core supply since it never passes through a block powered by this supply Of course noi
95. frequencies is less since the entire range of the M and D counters cannot be realized and there is overlap between the various settings As an example consider Fry 100 MHz If the minimum PFD frequency is 20 MHz then D can only go from 1 to 5 For D 1 M can only have values from four to 11 If D 2 M can have values from 8 to 22 In addition D 1M 4isasubsetof D 2M 8 allowing the D 1 M 4 case to be dropped For this case only D 3 4 and 5 are considered since all other D values are subsets of these cases This drastically reduces the number of possible output frequencies The output frequencies are sequentially selected The desired output frequency should be checked against the possible output frequencies generated Once the first output frequency is determined an additional constraint can be imposed on the values of M and D This can further limit the possible output frequencies www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX General Usage Description for the second output frequency Continue this process until all the output frequencies are selected The constraints used to determine the allowed M and D values are shown in the following equations DMIN ie E Equation 3 3 fprp MAX D B fin A MAX rounddownz Equation 3 4 PFD MIN Mogae roundup ces Bs Equation 3 5 D x MyMAx rounddown MAX fvcomax Equation 3 6 Determine the M and D Values Determining the input freq
96. in the 64K x 1 mode Further information on cascadeable block RAM is described in the Additional RAMB18 and RAMB36 Primitive Design Considerations section For other wider and or deeper sizes consult the Creating Larger RAM Structures section Figure 4 7 shows the block RAM with the appropriate ports connected in the Cascadable mode CASCADEOUT No Connect DI Optional Output FF A 14 0 4 gt A15 d RAM_EXTENSION P UPPER 0 Do Q B CASCADEIN of Top WE 3 0 p beh DI Opti ptional Output FE CASCADEOUT of Bottom A 14 0 gt A15 1 DO RAM EXTENSION Not Used LOWER 1 DE WE 3 0 YJ CASCADEIN Connect to logic High or Low Int t Interconnect 4 amp Block RAM ug190 4 07 071607 Figure 4 7 Cascadable Block RAM Byte wide Write Enable The byte wide write enable feature of the block RAM gives the capability to write eight bit one byte portions of incoming data There are four independent byte wide write enable inputs to the RAMB36 true dual port RAM There are eight independent byte wide write enable inputs to block RAM in simple dual port mode RAMB36SDP Table 4 4 summarizes the byte wide write enables for the 36K and 18K block RAM Each byte wide write enable is associated with one byte of input data and one parity bit All byte wide write enable inputs must be driven in all data width c
97. inputs of the slice LUT configured as RAM Tws TwH WE input Time before after the clock that the write enable signal must be stable at the WE input of the slice LUT configured as RAM Clock CLK TwpPH Minimum Pulse Width High TWPL Minimum Pulse Width Low Twc Minimum clock period to meet address write cycle time Notes 1 This parameters includes a LUT configured as a two bit distributed RAM 2 Tyxck Setup Time before clock edge and Tckxx Hold Time after clock edge 3 Parameter includes AI BI CI DI configured as a data input DI2 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 203 Chapter 5 Configurable Logic Blocks CLBs XILINX Distributed RAM Timing Characteristics The timing characteristics of a 16 bit distributed RAM implemented in a Virtex 5 FPGA slice LUT configured as RAM are shown in Figure 5 28 1 2 3 4 5 6 7 WPH TWPL lt A BIC D ADDR AX BX CX DX DI WE DATA OUT A B C D Output WRITE READ WRITE WRITE WRITE READ UG190 5 28 050506 Figure 5 28 Slice Distributed RAM Timing Characteristics Clock Event 1 Write Operation During a Write operation the contents of the memory at the address on the ADDR inputs are changed The data written to this memory location is reflected on the A B C D outputs synchronously e At time Tyg before clock event 1 the write enable signal WE becomes valid h
98. more than 100 ms to minimize the effect of device cooling otherwise the tap delays might change The clock should be stopped during a Low or a High phase and must be restored with the same input clock period frequency During this time LOCKED stays High and remains High when the clock is restored Thus a High on LOCKED does not necessarily mean that a valid clock is available When stopping the input clock CLKIN remains High or Low for one or more clock cycles one to nine more output clock cycles are still generated as the delay line is flushed When the output clock stops the CLKIN stopped DO 1 signal is asserted When the clock is restarted the output clock cycles are not generated for one to eight clocks while the delay line is filled The most common case is two or three clocks The DO 1 signal is deasserted once the output clock is generated CLKIN can be restarted with any phase relationship to the previous clock If the frequency has changed the DCM requires a reset The DO 1 is forced Low whenever LOCKED is Low When the DCM is in the locking process DO 1 status is held Low until LOCKED is achieved 60 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Design Guidelines Output Clocks Any or all of the DCM s nine clock outputs can be used to drive a global clock network The fully buffered global clock distribution network minimizes clock skew caused by loading differences By monito
99. of the replicated instances are connected to an auto generated AND gate The implementation tools assign the signal name connected to the RDY port of the non location constrained instance to the output of the AND gate e All the ports of the location constrained instances RST REFCLK and RDY are independent from each other and from the replicated instances The VHDL and Verilog use models for instantiating a mixed usage model are provided in the Libraries Guide In the example a user is instantiating a non location constrained IDELAYCTRL instance with the RDY signal connected This discussion is also valid when the RDY signal is ignored The circuitry that results from instantiating the IDELAYCTRL components is illustrated in Figure 7 21 Virtex 5 FPGA User Guide www xilinx com 339 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX Instantiated with LOC Constraint REFCLK REFCLK RDY rdy_1 IDELAYCTRL_1 T rst 1 RS REFCLK RDY rdy 2 IDELAYCTRL_2 rst_2 RST REFCLK RDY rdy_n IDELAYCTRL_n rst_n RST Instantiated without LOC Constraint REFCLK RDY IDELAYCTRL_noloc RST_NOLOC RST REFCLK RDY_NOLOC IDELAYCTRL_noloc RST Replicated for all IDELAYCTRL sites REFCLK RDY IDELAYCTRL_noloc RST Auto generated by mapper tool ug190_7_16_041306 Figure 7 21 Mixed instantiation of IDELAYCTRL Elements Instantiating Multiple
100. of the slower clock The Setup Hold requirements for SO and S1 are with respect to the falling clock edge assuming INIT OUT 0 not the rising edge as for CEO and CE1 Switching conditions for BUFGMUX_VIRTEX4 are the same as the S pin of BUFGCTRL Figure 1 12 illustrates the timing diagram for BUFGMUX_VIRTEX4 Tsccko_o m Tgccko_o ug190_1_12_032306 Figure 1 12 BUFGMUX_VIRTEX4 Timing Diagram Other capabilities of the BUFGMUX_VIRTEX4 primitive are e Pre selection of I0 and I1 input after configuration e Initial output can be selected as High or Low after configuration Virtex 5 FPGA User Guide www xilinx com 31 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX Additional Use Models Asynchronous Mux Using BUFGCTRL In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL An example is when one of the clock inputs is no longer switching If this happens the clock output would not have the proper switching conditions because the BUFGCTRL never detected a clock edge This case uses the asynchronous mux Figure 1 13 illustrates an asynchronous mux with BUFGCTRL design example Figure 1 14 shows the asynchronous mux timing diagram IGNORE1 CE1 VDD VDD Asynchronous MUX Design Example D Vpp IGNOREO ug190_1_13_032306 Figure 1 13 Asynchronous Mux with BUFGCTRL Design Example
101. on these banks to external resistors DCI impedance control in cascaded banks is received from the master bank When using DCI cascading the DCI control circuitry in the master bank creates and routes DCI control to the cascaded banks in daisy chain style DCI control for a particular bank can come from the bank immediately above or below Only the master bank s VRN VRP pins are required when using DCI cascading Also when using DCI cascading only one set of VRN VRP pins provides the DCI reference voltage for multiple banks DCI cascading e Reduces overall power since fewer voltage references are required e Frees up VRN VRP pins on slave banks for general customer use e DCIinbanks 1 and 2 is supported only through cascading These two banks do not have VRN VRP pins and therefore cannot be used as master or stand alone DCI banks Cascading is not possible through bank 0 Similarly due to the center column architecture the half size banks 1 2 3 and 4 are separated from all the other banks in the center column by the CMT tiles It is not possible to cascade across the CMT tiles This affects the larger devices that have more than four user I O center column banks plus bank 0 For instance bank 4 cannot be cascaded with bank 6 and bank 3 cannot be cascaded with bank 5 Bank 3 can only be cascaded with bank 1 and bank 4 can only be cascaded with bank 2 Virtex 5 FPGA User Guide www xilinx com 219 UG190 v4 4 December 2 2008 Chap
102. optional output registers are not enabled CASCADEINREGJ A B Cascade input for 64K x 1 mode when optional input register is enabled CASCADEOUTREG A B Cascade output for 64K x 1 mode when optional output register is enabled Notes 1 The Data In Buses DI A B lt 0 gt amp DIP A B lt 0 gt section has more information on data parity pins Read Operation Inlatch mode the read operation uses one clock edge The read address is registered on the read port and the stored data is loaded into the output latches after the RAM access time When using the output register the read operation will take one extra latency cycle Write Operation A write operation is a single clock edge operation The write address is registered on the write port and the data input is stored in memory Write Modes Three settings of the write mode determines the behavior of the data available on the output latches after a write clock edge WRITE FIRST READ FIRST and NO CHANGE Write mode selection is set by configuration The Write mode attribute can be individually selected for each port The default mode is WRITE FIRST WRITE FIRST outputs the newly written data onto the output bus READ FIRST outputs the previously stored data while new data is being written NO CHANGE maintains the output previously generated by a read operation For the simple dual port block RAM the Write mode is always READ FIRST and therefo
103. or 10 4 width This value also depends on the If DATA RATE OQ DDR DATA RATE OQ value value is limited to 4 6 8 or 10 If DATA RATE OQ SDR value is limited to 2 3 4 5 6 7 or 8 SERDES MODE Defines whether the OSERDES moduleisa String MASTER or SLAVE MASTER master or slave when using width expansion TRISTATE WIDTH Defines the parallel to serial 3 state converter Integer 1 or 4 4 DATA RATE OQ Attribute The DATA RATE OQ attribute defines whether data is processed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR and DDR The default value is DDR DATA RATE TOQ Attribute The DATA RATE TO attribute defines whether 3 state control is to be processed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR 370 and DDR The default value is DDR www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Parallel to Serial Logic Resources OSERDES DATA_WIDTH Attribute The DATA WIDTH attribute defines the parallel data input width of the parallel to serial converter The possible values for this attribute depend on the DATA RATE OQ attribute When DATA RATE OQ is set to SDR the possible values for the DATA WIDTH attribute are 2 3 4 5 6 7 and 8 When DATA RATE OQ is set to DDR the possible values for the DATA WIDTH attribute are 4 6 8 and 10 When the DATA WIDTH is
104. penalty Embedded dual or single port RAM modules ROM modules synchronous FIFOs and data width converters are easily implemented using the Xilinx CORE Generator block memory modules Multirate FIFOs can be generated using the CORE Generator FIFO Generator module The synchronous or asynchronous multirate FIFO implementation does not require additional CLB resources for the FIFO control logic since it uses dedicated hardware resources Synchronous Dual Port and Single Port RAMs Data Flow The true dual port 36 Kb block RAM dual port memories consist of a 36 Kb storage area and two completely independent access ports A and B Similarly each 18 Kb block RAM dual port memory consists of an 18 Kb storage area and two completely independent access ports A and B The structure is fully symmetrical and both ports are interchangeable Figure 4 1 illustrates the true dual port data flow Table 4 2 lists the port names and descriptions Data can be written to either or both ports and can be read from either or both ports Each write operation is synchronous each port has its own address data in data out clock clock enable and write enable The read and write operations are synchronous and require a clock edge There is no dedicated monitor to arbitrate the effect of identical addresses on both ports It is up to the user to time the two clocks appropriately Conflicting simultaneous writes to the same location never cause any physical
105. positive range with respect to CLKIN When set to VARIABLE CENTER the DCM outputs can be phase shifted in variable mode in the positive and negative range with respect to CLKIN If set to VARIABLE POSITIVE or VARIABLE CENTER each phase shift increment or decrement increases or decreases the phase shift by a period of 1 256 x CLKIN period When set to DIRECT the DCM output can be phase shifted in variable mode in the positive range with respect to CLKIN Each phase shift increment decrement will increase decrease the phase shift by one DCM TAP See the Virtex 5 FPGA Data Sheet The starting phase in the VARIABLE POSITIVE and VARIABLE CENTER modes is determined by the phase shift value The starting phase in the DIRECT mode is always zero regardless of the value specified by the PHASE SHIFT attribute Thus the PHASE SHIFT attribute should be set to zero when DIRECT mode is used A non zero phase shift value for DIRECT mode can be loaded to the DCM using Dynamic Reconfiguration Ports in the Virtex 5 FPGA Configuration Guide CLK FEEDBACK Attribute The CLK FEEDBACK attribute determines the type of feedback applied to the CLKFB The possible values are 1X or NONE The default value is 1X When set to 1X CLKFB pin must be driven by CLKO When set to NONE leave the CLKFB pin unconnected Virtex 5 FPGA User Guide www xilinx com 55 UG190 v4 4 December 2 2008 56 Chapter 2 Clock Management Technology XILINX DESKEW_ADJUST Attribu
106. purpose reference pins in each bank to control the impedance of the driver or the parallel termination value for all of the I Os of that bank The N reference pin VRN must be pulled up to Vcco by a reference resistor and the P reference pin VRP must be pulled down to ground by another reference resistor The value of each reference resistor should be equal to the characteristic impedance of the PC board traces or should be twice that value See Driver with Termination to Veco 2 Split Termination page 226 When a DCII O standard is used on a particular bank the two multi purpose reference pins cannot be used as regular I Os However if DCI I O standards are not used in the bank these pins are available as regular I O pins The Virtex 5 Family Packaging Specifications gives detailed pin descriptions DCI adjusts the impedance of the I O by selectively turning transistors in the I Os on or off The impedance is adjusted to match the external reference resistors The impedance adjustment process has two phases The first phase compensates for process variations by controlling the larger transistors in the I Os It occurs during the device startup sequence The second phase maintains the impedance in response to temperature and supply voltage changes by controlling the smaller transistors in the I Os It begins immediately after the first phase and continues indefinitely even while the device is operating By default the DONE pin does no
107. reset functionality of the port Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells Enable polarity is configurable active High by default Byte wide Write Enable WE AIB To write the content of the data input bus into the addressed memory location both EN and WE must be active within a set up time before the active clock edge The output latches are loaded or not loaded according to the write configuration WRITE FIRST READ FIRST NO CHANGE When inactive a read operation occurs and the contents of the memory cells referenced by the address bus appear on the data out bus regardless of the write mode attribute Write enable polarity is not configurable active High Register Enable REGCE AIB The register enable pin REGCE controls the optional output register When the RAM is in register mode REGCE 1 registers the output into a register at a clock edge The polarity of REGCE is not configurable active High Set Reset SSH AIB In latch mode the SSR pin forces the data output latches to contain the value SRVAL See Block RAM Attributes page 126 When the optional output registers are enabled the data output registers can also be forced by the SSR pin to contain the value SRVAL SSR does not affect the latched value The data output latches or output registers are synchronously asserted to 0 or 1 including the parity bit Each port has an independent
108. set to widths larger than six a pair of OSERDES must be configured into a master slave configuration See OSERDES Width Expansion SERDES MODE Attribute The SERDES MODE attribute defines whether the OSERDES module is a master or slave when using width expansion The possible values are MASTER and SLAVE The default value is MASTER See OSERDES Width Expansion TRISTATE WIDTH Attribute The TRISTATE WIDTH attribute defines the parallel 3 state input width of the 3 state control parallel to serial converter The possible values for this attribute depend on the DATA RATE TO attribute When DATA RATE TO is set to SDR or BUF the TRISTATE WIDTH attribute can only be set to 1 When DATA RATE TO is set to DDR the possible values for the TRISTATE WIDTH attribute is 4 TRISTATE WIDTH cannot be set to widths larger than 4 When a DATA WIDTH is larger than four set the TRISTATE WIDTH to 1 OSERDES Clocking Methods The phase relationship of CLK and CLKDIV is important in the parallel to serial conversion process CLK and CLKDIV are ideally phase aligned within a tolerance There are several clocking arrangements within the FPGA to help the design meet the phase relationship requirements of CLK and CLKDIV The only valid clocking arrangements for the OSERDES are e CLK driven by BUFIO CLKDIV driven by BUFR e CLK driven by DCM CLKDIV driven by the CLKDV output of the same DCM e CLK driven by PLL CLKDIV driven by CLKOUT 0 5 of same P
109. shown in a bidirectional system where the IOB must be frequently 3 stated E Hn D1 C KOE A A A C8 AF K lt XX D3 CS AeA A Bi ni E lt lt lt 2 a lt lt 00 v ILS ouro 9 8 UG190 8 19 100307 Figure 8 19 OSERDES Data Flow and Latency in 4 1 DDR Mode 376 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX Output Parallel to Serial Logic Resources OSERDES Clock Event 1 T1 T2 and T4 are driven Low to release the 3 state condition The serialization paths of T1 T4 and D1 D4 in the OSERDES are identical including latency such that the bits EFGH are always aligned with the 0010 presented at the T1 T4 pins during Clock Event 1 Clock Event 2 The data bit E appears at OQ one CLK cycle after EFGH is sampled into the OSERDES This latency is consistent with the Table 8 10 listing of a 4 1 DDR mode OSERDES latency of one CLK cycle The 3 state bit 0 at T1 during Clock Event 1 appears at TQ one CLK cycle after 0010 is sampled into the OSERDES 3 state block This latency is consistent with the Table 8 10 listing of a 4 1 DDR mode OSERDES latency of one CLK cycle Reset Output Timing Clock Event 1 A reset pulse is generated on the rising edge of CLKDIV Because the pulse must take two different routes to get to OSERDESO and OSERDES1 there are different propagation delays for both paths The difference in propagat
110. synchronous to CLKDIV Therefore SR should be driven High for a minimum of one CLKDIV cycle When building an interface consisting of multiple OSERDES ports all OSERDES ports must be synchronized The internal retiming of the SR input is designed so that all OSERDES blocks that receive the same reset pulse come out of reset synchronized with one another The reset timing of multiple OSERDES ports is shown in Figure 8 20 page 377 Virtex 5 FPGA User Guide www xilinx com 369 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources OSERDES Attributes Table 8 7 lists and describes the various attributes that are available for the OSERDES primitive The table includes the default values Table 8 7 OSERDES Attribute Summary XILINX width If DATA_RATE_TQ DDR DATA_WIDTH 4 and DATA_RATE_OQ DDR value is limited to 4 For all other settings of DATA_RATE_TQ DATA_WIDTH and DATA_RATE_OQ value is limited to 1 OSERDES Attribute Description Value Default Value DATA_RATE_OQ Defines whether data OQ changes at every String SDR or DDR DDR clock edge or every positive clock edge with respect to CLK DATA_RATE_TQ Defines whether the 3 state TQ changes at String BUF SDR or DDR DDR every clock edge every positive clock edge with respect to clock or is set to buffer configuration DATA WIDTH Defines the parallel to serial data converter Integer 2 3 4 5 6 7 8
111. system clock speeds get faster PC board design and manufacturing becomes more difficult With ever faster edge rates maintaining signal integrity becomes a critical issue PC board traces must be properly terminated to avoid reflections or ringing To terminate a trace resistors are traditionally added to make the output and or input match the impedance of the receiver or driver to the impedance of the trace However due to increased device I Os adding resistors close to the device pins increases the board area and component count and can in some cases be physically impossible To address these issues and to achieve better signal integrity Xilinx developed the Digitally Controlled Impedance DCI technology DCI adjusts the output impedance or input termination to accurately match the characteristic impedance of the transmission line DCI actively adjusts the impedance of the I O to equal an external reference resistance This compensates for changes in I O impedance due to process variation It also continuously adjusts the impedance of the I O to compensate for variations of temperature and supply voltage fluctuations In the case of controlled impedance drivers DCI controls the driver impedance to match two reference resistors or optionally to match half the value of these reference resistors DCI eliminates the need for external series termination resistors DCI provides the parallel or series termination for transmitters or receivers
112. the DCM DRPs allow dynamic adjustment of the CLKFX MULTIPLY M and CLKFX DIVIDE D values to produce a new CLKFX frequency The following steps are required when using DRPs to load new M and D values e Subtract the desired M and D values by one For example if the desired M D 9 4 then load M D 8 3 e Hold DCM in reset assert RST signal and release it after the new M and D values are written The CLKFX outputs can be used after LOCKED is asserted High again e Read DADDRO to restore the default status on DO e Release RST Connecting DCMs to Other Clock Resources in Virtex 5 Devices Most DCM functions require connection to dedicated clock resources including dedicated clock I O IBUFG clock buffers BUFGCTRLs and PLLs These clock resources are located in the center column of the Virtex 5 devices This section provides guidelines on connecting the DCM to dedicated clock resources IBUFG to DCM Virtex 5 devices contain 20 clock inputs These clock inputs are accessible by instantiating the IBUFG Each top and bottom half of a Virtex 5 device contains 10 IBUFGs Any of the IBUFG in top or bottom half of the Virtex 5 device can drive the clock input pins CLKIN CLKFB PSCLK or DCLK of a DCM located in the same top bottom half of the device DCM to BUFGCTRL Any DCM clock output can drive any BUFGCTRL input in the same top bottom half of the device There are no restrictions on how many DCM outputs can be used simultaneou
113. the DCM must directly drive an OBUF or a BUFG to DDR configuration 2 External to the FPGA the forwarded clock signal must be connected to the IBUFG GCLK pin or the IBUF driving the CLKFB of the DCM Both CLK and CLKFB should have identical I O buffers Figure 2 9 illustrates clock forwarding with external feedback configuration The feedback clock input signal can be driven by one of the following buffers 1 IBUFG Global Clock Input Buffer This is the preferred source for an external feedback configuration When an IBUFG drives a CLKFB pin of a DCM in the same top or bottom half of the device the pad to DCM skew is compensated for deskew 2 BUFGCTRL Internal Global Clock Buffer This is an internal feedback configuration driven by CLKO 3 IBUF Input Buffer This is an external feedback configuration When IBUF is used the PAD to DCM input skew is not compensated and performance can not be guaranteed Phase Shift Clock Input PSCLK The phase shift clock PSCLK input pin provides the source clock for the DCM phase shift The PSCLK can be asynchronous in phase and frequency to CLKIN The phase shift clock signal can be driven by any clock source external or internal including 1 IBUF Input Buffer 2 IBUFG Global Clock Input Buffer To access the dedicated routing only the IBUFGs on the same half of the device top or bottom as the DCM can be used to drive a PSCLK input of the DCM 3 BUFGCTRL An Internal Glo
114. the LUTs FFAMUX F7BMUx and F8MUX to the BMUX output eight input function Sequential Delays Tcko FF Clock CLK to Time after the clock that data is stable at the AQ BO CQ DO outputs AQ BO CQ DO outputs of the slice sequential elements configured as a flip flop TCKLO Latch Clock CLK to Time after the clock that data is stable at the AQ BQ CQ DQO outputs XQ YQ outputs of the slice sequential elements configured as a latch Setup and Hold Times for Slice Sequential Elements 2 Tpick Tckpi AX BX CX DX inputs Time before after the CLK that data from the AX BX CX DxX inputs of the slice must be stable at the D input of the slice sequential elements configured as a flip flop Tcrck TCKCE CE input Time before after the CLK that the CE input of the slice must be stable at the CE input of the slice sequential elements configured as a flip flop Tsnck Tcksn SR BY input Time before after the CLK that the SR Set Reset and the BY Rev inputs of the slice must be stable at the SR Rev inputs of the slice sequential elements configured as a flip flop Set Reset Trew Minimum Pulse Width for the SR Set Reset and BY Rev pins TRO Propagation delay for an asynchronous Set Reset of the slice sequential elements From the SR BY inputs to the AQ BQ CQ DQ outputs 200 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX CL
115. the internal series resistance 25 Qat2 5V 20 Qat1 8V The DCI receiver has an internal split thevenin termination powered from Vcco creating an equivalent Vyr voltage and termination impedance SSTL2 Il SSTL18 II Class II signaling uses Vrr Vcco 2 as a parallel termination voltage to a 50 G resistor at the receiver and transmitter respectively A series resistor 25 Qat 2 5V 20 Qat 1 8V must be connected to the transmitter output for a unidirectional link For a bidirectional link 25 Q series resistors must connected the transmitters of the transceivers SSTL2 II DCI SSTL18 Il DCI The DCI circuits have a split thevenin termination powered from Veco and an internal series resistor 25 Qat 2 5V 20 Q at 1 8V For a unidirectional link the internal series resistance is supplied only for the transmitter A bidirectional link has the internal series resistor for both transmitters DIFF SSTL2 lI DIFF SSTL18 I Differential SSTL 2 5V and 1 8V Class I pairs complementary single ended SSTL I type drivers with a differential receiver DIFF SSTL2 I DCI DIFF SSTL18 I DCI Differential SSTL 2 5V and 1 8V Class I pairs complementary single ended SSTL II type drivers with a differential receiver including on chip differential split thevenin termination DIFF SSTL2 Il DIFF SSTL18 Il Differential SSTL 2 5V and 1 8V Class II pairs complementary single ended SSTL II type drivers with a differential receiver For a bidirectional link a s
116. use DO A B pins must be 32 bits wide However valid data are only found on pins DO BIT WIDTH 1 down to 0 DOP A B pins must be 4 bits wide However valid data are only found on pins DOP BIT WIDTH 1 down to 0 DOP A B can be left unconnected when not in use ADDR A B pins must be 16 bits wide However valid addresses for non cascadable block RAM are only found on pin 14 to 15 address width The remaining pins including pin 15 should be tied High Address width is defined in Table 4 6 page 124 Cascadeable Block RAM To use the cascadeable block RAM feature 1 2 Two RAMB36 primitives must be instantiated Set the RAM EXTENSION A and RAM EXTENSION B attribute for one RAMB36 to UPPER and another to LOWER Connect the upper RAMB36 s CASCADEINA and CASCADEINB ports to the CASCADEOUTA and CASCADEOUTB ports of the lower RAMB36 The CASCADEOUT ports for the upper RAMB36 do not require a connection Connect the CASCADEIN ports for the lower RAMB36 to either logic High or Low The data output ports of the lower RAMB36 are not used These pins are unconnected If placing location constraints on the two RAMB36s they must be adjacent If no location constraint is specified the Xilinx ISE software will automatically manage the RAMB36 locations The address pins ADDR A B must be 16 bits wide Both read and write ports must be one bit wide Figure 4 7 shows the cascadeable block RAM 130 www xilinx com
117. value 4 of ALMOST EMPTY OFFSET works Read Error Flag Once the Empty flag has been asserted any further read attempts will not increment the read address pointer but will trigger the Read Error flag The Read Error flag is deasserted when Read Enable or Empty is deasserted Low The Read Error flag is synchronous to RDCLK Full Flag The Full flag is synchronous with WRCLK and is asserted when there are no more available entries in the FIFO queue When the FIFO is full the write pointer will be frozen The Virtex 5 FPGA Full flag is deasserted three write clock cycles after two subsequent read operations In Virtex 4 FPGA designs a Full flag is asserted one write clock cycle after the last write and is deasserted three write clock cycle after the first read Write Error Flag Once the Full flag has been asserted any further write attempts will not increment the write address pointer but will trigger the Write Error flag The Write Error flag is deasserted when Write Enable or Full is deasserted Low This signal is synchronous to WRCLK Almost Full Flag The Almost Full flag is set when the FIFO has the number of available empty spaces specified by the ALMOST FULL OFFSET value or fewer spaces The Almost Full flag warns the user to stop writing It deasserts when the number of empty spaces in the FIFO is greater than the ALMOST FULL OFFSET value plus one Assertion and deassertion is synchronous to WRCLK Flag latency is describe
118. various OSERDES latency values Table 8 10 OSERDES Latencies DATA RATE DATA WIDTH Latency 21 1CLK cycle 3 1 3 CLK cycles 4 1 4 CLK cycles SDR 5 1 4 CLK cycles 6 1 5 CLK cycles 71 5 CLK cycles 81 6 CLK cycles 4 1 1 CLK cycle ios 6 1 3 CLK cycles 8 1 4 CLK cycles 10 1 4 CLK cycles OSERDES Timing Model and Parameters This section discusses all timing models associated with the OSERDES primitive Table 8 11 describes the function and control signals of the OSERDES switching characteristics in the Virtex 5 FPGA Data Sheet Table 8 11 OSERDES Switching Characteristics Symbol Description Setup Hold Tospck p Tosckp p D input Setup Hold with respect to CLKDIV Tospck T Tosckp T T input Setup Hold with respect to CLK Tospck T Tosckp T T input Setup Hold with respect to CLKDIV Toscck ocE Tosckc ocE OCE input Setup Hold with respect to CLK Toscck rcE Tosckc TCE TCE input Setup Hold with respect to CLK Sequential Delays Toscko oo Clock to Out from CLK to OQ Toscko TO Clock to Out from CLK to TO Virtex 5 FPGA User Guide www xilinx com 373 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX Table 8 11 OSERDES Switching Characteristics Continued Symbol Description Combinatorial Tosco oo Asynchronous Reset to OQ Tosco_TQ Asynchronous Reset to TQ Timing Characteristics of 2
119. 0 ADDRA 4 0 l DOA 1 L UG190 5 06 032706 Figure 5 6 Distributed RAM RAM32X2Q 180 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview RAM 32X6SDP o DPRAM32 unused WADDR 5 1 L ___ gt 2 1s WADDRI6 1 WCLK WED l l unused l DATA 1 1 3 4 DATA 2 RADDR 5 1 RADDR S 1 DATA 3 DATA 4 DATA 5 DATA 6 UG190 5 06 032706 Figure 5 7 Distributed RAM RAM32X6SDP Virtex 5 FPGA User Guide www xilinx com 181 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX RAM64X1S gt Output Registered u Output Optional ugi90 5 07 032706 Figure 5 8 Distributed RAM RAM64X1S If four single port 64 x 1 bit modules are built the four RAM64XIS primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 64 x 4 bit single port distributed RAM RAM64X1D p uve mg ci E PE Es 7 l DX SPO l Registered l D 6 1 egistere A 5 0 4 len A 6 1 P Output I x WA 6 1 K WCLK e mc gt CLK i Optional we UN l l l e l l DPO T l l Registered DPRA 5 0 I M Output I i l Optional
120. 0 SSTL2_II_DCI SSTL2 Il DCI 51 9 2 P3 Vper 1 25V Ro 2250 BEF 2Rypy 2Zg 1000 3 2Rygy 2Zo 1000 L ug190_6_66_030506 Figure 6 69 SSTL2 Class II with Unidirectional Termination 276 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Figure 6 70 shows a sample circuit illustrating a valid bidirectional termination technique for SSTL2 Class II External Termination OB Vez 1 25V Vat 1 25V IOE SSTL2 II Rp Zp 500 SSTL2_II Rg 250 Rp Zp 50Q Rg 25Q khwv Qz vv q Vper 1 25V l Vggr 1 25V l l l l L DCI IOB IOB Veco 2 5V Voco 2 5V 2Rygp 2Zg 1000 2Rypp 2Zo 1000 SSTL2 II DCI SSTL2 Il DCI oon Vper 1 25V Ro 250 2Rvan 2Zo 1000 2Rygw 2Zo 1000 Vnrr 1 25V Ro 25Q ug190_6_67_030506 Figure 6 70 SSTL2 Class ll with Bidirectional Termination Virtex 5 FPGA User Guide www xilinx com 277 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 30 lists the SSTL2 DC voltage specifications for Class II Table 6 30 SSTL2 DC Voltage Specifications Class ll Min Typ Max Vcco 23 25 2 7 Veer 0 5x Veco 1 13 1 25 1 38 Ver Vrgr NO 1 09 1 25 1 42 Vin 2 Vggr 0 15 1 28 1 40 Veco 0 32 Vit Veer 0 15 0 3 1 1 1 27 Vou Vrer 0 81 1 9
121. 0 1 Sete a2 2 o 1 1 o fo 1 Jol o ISERDES e 0 0 1 1 1 0 0 1 0 Master Q4 1 0 0 1 1 1 0 0 1 Q5 0 1 0 0 1 1 1 0 0 Q6 mj 0 0 1 0 0 1 1 1 0 BITSLIP SHIFTOUT1 SHIFTOUT2 SHIFTIN1 SHIFTIN2 D Q1 ISERDES 1 0 0 1 0 0 1 1 1 Slave gt 11 1 0 0 1 0 0 1 1 BITSLIP Bitslip signal from system SERDES_MODE SLAVE BITSLIP_ENABLE TRUE i a ee a ugi90 8 11 100307 Figure 8 11 Circuit Diagram for Bitslip Configuration in 1 8 SDR Mode Guidelines for Using the Bitslip Submodule Set the BITSLIP ENABLE attribute to TRUE When BITSLIP ENABLE is set to FALSE the Bitslip pin has no effect In a master slave configuration the BITSLIP ENABLE attribute in both modules must be set to TRUE To invoke a Bitslip operation the BITSLIP port must be asserted High for one CLKDIV cycle In SDR mode Bitslip cannot be asserted for two consecutive CLKDIV cycles Bitslip must be deasserted for at least one CLKDIV cycle between two Bitslip assertions In both SDR and DDR mode the total latency from when the ISERDES captures the asserted Bitslip input to when the bit slipped ISERDES outputs Q1 O6 are sampled into the FPGA logic by CLKDIV is two CLKDIV cycles Virtex 5 FPGA User Guide www xilinx com 363 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX Bitslip Timing Model and Parameters This section discusses the timing models associated with the Bitslip controller in a 1 4 DDR configuratio
122. 0 40 DIFF SSTL II DCI 20 40 LVPECL 25 20 40 BLVDS 25 20 40 LVDS 25 20 40 LVDSEXT 25 20 40 RSDS 25 20 40 HT 25 20 40 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 307 Chapter 6 SelectlO Resources 308 XILINX Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage 3 3V IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank LVCMOS33_2_slow 20 40 LVCMOS33_4_slow 20 40 LVCMOS33_6_slow 20 40 LVCMOS33_8_slow 20 40 LVCMOS33_12_slow 20 40 LVCMOS33_16_slow 20 40 LVCMOS33_24_slow 20 40 LVCMOS33_2_fast 20 40 LVCMOS33_4_fast 20 40 LVCMOS33_6_fast 20 40 LVCMOS33_8_fast 20 40 LVCMOS33_12_fast 20 40 LVCMOS33_16_fast 20 40 LVCMOS33_24_fast 15 30 LVTTL_2_slow 20 40 LVTTL_4_slow 20 40 LVTTL_6_slow 20 40 LVTTL_8_slow 20 40 LVTTL_12_slow 20 40 LVTTL_16_slow 20 40 LVTTL_24_slow 20 40 LVTTL_2_fast 20 40 LVTTL 4 fast 20 40 LVTTL 6 fast 20 40 LVTTL 8 fast 20 40 LVTTL 12 fast 20 40 LVTTL 16 fast 20 40 LVTTL 24 fast 15 30 PCI33 3 20 40 PCI66 3 20 40 PCIX 20 40 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Simultaneous Switching Output Limits Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank GTL 12 25 GTL_
123. 0 68 0 90 Voprrr AC 0 40 Veco 0 60 Vx Crossover 0 68 0 90 Notes 1 Common mode voltage Vem Vp Vp Vn 2 2 Crossover point Vy where Vp Vy 0 AC coupled Virtex 5 FPGA User Guide www xilinx com 255 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources HSTL Class Ill XILINX Figure 6 48 shows a sample circuit illustrating a valid termination technique for HSTL Class III External Termination A IOB Vrz 15V Dig HSTL_III HSTL Ill Rp Zo 500 D4 Q 70 Dd Veer 0 9V c zt le DCI FF IOB IOB Rypp Zo 502 HSTL Ill DCI HSTL Ill DCI D1 409 4 _X Vner 0 9V SO ug190_6_47_030306 Figure 6 48 HSTL Class Ill Termination Table 6 19 lists the HSTL Class III DC voltage specifications Table 6 19 HSTL Class Ill DC Voltage Specifications Min Typ Max Veco 1 40 1 50 1 60 Veer O 0 90 Ver Veco 7 Vin VREF 0 1 Vi Vggr 0 1 VoH Veco 0 4 VoL 0 4 lou at Vou mA 8 Ior at Vor mA 24 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vpgr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 256 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards
124. 1 and 2 on the next clock cycle Q1 l Q2 l l l l Don t care D11A ug190_7_03_041206 Figure 7 3 Input DDR Timing in SAME EDGE Mode SAME EDGE PIPELINED Mode In the SAME EDGE PIPELINED mode the data is presented into the FPGA fabric on the same clock edge Unlike theSAME EDGE mode the data pair is not separated by one clock cycle However an additional clock latency is required to remove the separated effect of the SAME EDGE mode Figure 7 4 shows the timing diagram of the input DDR using the SAME EDGE PIPELINED mode The output pairs Q1 and Q2 are presented to the FPGA fabric at the same time www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX ILOGIC Resources Bod EO LB IT Ir IT E Ll CE D DIA D3A D5A D7A D9A D10A D11A D12A D13A Q1 DOA D2A D4A D6A D8A D10A Q2 D1A D3A D5A D7A D9A D11A ug190 7 04 041206 Figure 7 4 Input DDR Timing in SAME EDGE PIPELINED Mode Input DDR Primitive IDDR Figure 7 5 shows the block diagram of the IDDR primitive Table 7 3 lists the IDDR port signals Table 7 4 describes the various attributes available and default values for the IDDR primitive S D Q1 dE Q2 C R ug190_7_05_062207 Figure 7 5 DDR Primitive Block Diagram Table 7 3 IDDR Port Signals Port Function Description Name Q1 and Q2 Data outputs IDDR register outputs C Clock input port The C pin represent
125. 101 UG190 v4 4 December 2 2008 Chapter 3 Phase Locked Loops PLLs XILINX Missing Input Clock or Feedback Clock When the input clock or feedback clock is lost the PLL will drive the output clocks to a lower or higher frequency causing all of the output clocks to increase decrease in frequency The frequency increase decrease can cause the clock output frequencies to change to as much as six times the original configuration PLL Use Models 102 There are several methods to design with the PLL The PLL wizard in ISE software can assist with generating the various PLL parameters Additionally the PLL can be manually instantiated as a component It is also possible for the PLL to be merge with an IP core The IP core would contain and manage the PLL Clock Network Deskew One of the predominant uses of the PLL is for clock network deskew Figure 3 10 shows the PLL in this mode The clock output from one of the O counters is used to drive logic within the fabric and or the I Os The feedback counter is used to control the exact phase relationship between the input clock and the output clock if for example a 90 phase shift is required The associated clock waveforms are shown to the right for the case where the input clock and output clock need to be phase aligned This configuration is the most flexible but it does require two global clock networks Figure 3 10 IBUFG BUFG 1 2 3 CLKOUTO To Logic m CLKFBIN CLKOUT1 2
126. 11 Single Port Dual Port and Quad Port Distributed RAM Primitive RAM Size Type Address Inputs RAM32X1S 32 bit Single port A 4 0 read write RAM32X1D 32 bit Dual port A 4 0 read write DPRA 4 0 read RAM32M 32 bit Quad port ADDRA 4 0 read ADDRBJ 4 0 read ADDRC 4 0 read ADDRDf 4 0 read write RAM64X1S 64 bit Single port A 5 0 read write RAM64X1D 64 bit Dual port A 5 0 read write DPRA 5 0 read RAM64M 64 bit Quad port ADDRA 5 0 read ADDRBJ5 0 read ADDRC 5 0 read ADDRDJ5 0 read write RAMI128X1S 128 bit Single port A 6 0 read write RAM128X1D 128 bit Dual port A 6 0 read write DPRA 6 0 read RAM256X1S 256 bit Single port A 7 0 read write The input and output data are 1 bit wide with the exception of the 32 bit RAM Figure 5 32 shows generic single port dual port and quad port distributed RAM primitives The A ADDR and DPRA signals are address buses Virtex 5 FPGA User Guide www xilinx com 209 UG190 v4 4 December 2 2008 210 Chapter 5 Configurable Logic Blocks CLBs XILINX RAM X1S RAM X1D RAM M D o D DI A D 4 0 WE WE SPO WE DOD 0 WCLK WCLK WCLK A 0 A 0 R W Port ADDRD 0 R W Port DPO T DPRA 0 Read Port ADDROC 0 Read Port DOC 0 ADDRBI 0 Read Port DOB 0 ADDRA 0 Read Port DOA 0 UG190 5 32 112108 Figure 5 32 Single Port Dual Port and Quad Port Distributed RAM Pr
127. 18 2 fast 20 40 LVCMOS18 4 fast 20 40 LVCMOS18 6 fast 20 40 LVCMOS18 8 fast 20 40 LVCMOS18 12 fast 20 40 LVCMOS18 16 fast 20 40 LVDCI 18 50 Q 20 40 HSTL I 18 20 40 HSTL I DCI 18 20 40 HSTL II 18 20 40 HSTL II DCI 18 20 40 1 8V HSTL III 18 17 35 HSTL III DCI 18 17 35 HSTL IV 18 10 20 HSTL IV DCI 18 10 20 SSTL18 I 20 40 SSTL18 I DCI 20 40 SSTL18 II 20 40 SSTL18 II DCI 20 40 HSLVDCI 18 50 Q 20 40 DIFF HSIL I 18 20 40 DIFF HSITL I DCI 18 20 40 DIFF HSIL II 18 20 40 DIFF HSIL II DCI 18 20 40 DIFF SSTL18 I 20 40 DIFF SSTL18 I DCI 20 40 DIFF SSTL1S8 II 20 40 DIFF SSTL18 II DCI 20 40 306 www Xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX Simultaneous Switching Output Limits Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage 2 5V IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank LVCMOS25 2 slow 20 40 LVCMOS25 4 slow 20 40 LVCMOS25 6 slow 20 40 LVCMOS25 8 slow 20 40 LVCMOS25 12 slow 20 40 LVCMOS25 16 slow 20 40 LVCMOS25 24 slow 20 40 LVCMOS25 2 fast 20 40 LVCMOS25 4 fast 20 40 LVCMOS25 6 fast 20 40 LVCMOS25 8 fast 20 40 LVCMOS25 12 fast 20 40 LVCMOS25 16 fast 20 40 LVCMOS25 24 fast 15 30 LVDCI 25 50 Q 20 40 SSTL2_I 20 40 SSTL2_I_DCI 20 40 SSTL2 II 20 40 SSTL2 II DCI 20 40 HSLVDCI 25 50 Q 20 40 DIFF SSTL I 20 40 DIFF SSTL I DCI 20 40 DIFF SSTL II 2
128. 190 v4 4 December 2 2008 XILINX Virtex 5 FPGA User Guide CLB Overview carry multiplexer MUXCY can also be used to cascade function generators for implementing wide logic functions Figure 5 24 illustrates the carry chain with associated logic elements in a slice COUT To Next Slice Carry Chain Block CARRY4 pose eee coal l gt DMUX DQ O6 From LUTD l l O3 DMUX O5 From LUTD DD I C gt DQ DX D gt l l l Optional l l gt CMUX CQ O6 From LUTC CMUX O5 From LUTC CX CQ Optional gt BMUX BQ O6 From LUTB oS Are 9l MUXCYN BMUX O5 From LUTB BX BQ Optional C gt AMUX AQ O6 From LUTA AMUX O5 From LUTA AX C gt AQ Optional Can be used if unregistered registered outputs are free CIN From Previous Slice UG190 5 24 050506 Figure 5 24 Fast Carry Logic Path and Associated Elements The carry chains carry lookahead logic along with the function generators There are ten independent inputs S inputs S0 to S3 DI inputs DI to DI4 CYINIT and CIN and eight independent outputs O outputs O0 to O8 and CO outputs CO0 to CO3 The S inputs are used for the propagate signals of the carry lookahead logic The propagate signals are sourced from the O6 output of a function generator The DI inputs are used for the generate signals of the carry lookahead logic
129. 256 7936 More examples are given in Table 4 9 Table 4 9 Block RAM Initialization Attributes Memory Location Attribute From To INIT_00 255 0 INIT_01 511 256 INIT_02 767 512 INIT OE 3839 3584 INIT OF 4095 3840 INIT 10 4351 4096 INIT 1F 8191 7936 INIT 20 8447 8192 INIT 2F 12287 12032 INIT 30 12543 12288 INIT 3F 16383 16128 INIT 7F 32767 32512 Content Initialization INITP xx INITP xx attributes define the initial contents of the memory cells corresponding to DIP DOP buses parity bits By default these memory cells are also initialized to all zeros The initialization attributes represent the memory contents of the parity bits The eight initialization attributes are INITP 00 through INITP 07 for the RAMB18 The 16 initialization attributes are INITP 00 through INITP_OF for the RAMB36 Each INITP xx is a 64 digit hex encoded bit vector with a regular INIT xx attribute behavior The same formula can be used to calculate the bit positions initialized by a particular INITP xx attribute Virtex 5 FPGA User Guide www xilinx com 127 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Output Latches Initialization INIT INIT A or INIT B The INIT single port or INIT A and INIT B dual port attributes define the output latches or output register values after configuration The width of the INIT INIT A and INIT B attribute is the
130. 3 2 03 2 13 VoL Vggr 0 81 0 36 0 46 0 55 Tox at Voy mA 16 2 Io at Vor mA 16 2 Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Viy maximum is Vcco 0 3 3 Vy minimum does not conform to the formula 4 Because SSTL2 I DCI uses a controlled impedance driver Voy and Voy are different Differential SSTL2 Class II 2 5V Figure 6 71 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class II 2 5V with unidirectional termination External Termination Viz 1 25V VL 1 25V IOB nr Hr IOB DIFF SSTL2 II Rg 250 500 500 Dq vw C Zo D DIFF SSTL2 II Vr 1 25V Vyr 1 25V DIFF SSTL2 II Rg 250 500 500 Jw C Zo D ugi 90 6 68 030506 Figure 6 71 Differential SSTL2 Class II Unidirectional Termination 278 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Figure 6 72 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class II 2 5V with unidirectional DCI termination DCI IOB Veco 2 5V 10B Voco 25V DIFF SSTL2 II DCI 2Rypp 2Zo 1002 2Rypp 2Zo 1000 Dx 2Rypy 2Zg 1000 A 2Rypy 72290 1009 DIFF_SSTL2_II_DCI Ro 250 Veco 25V Voco 25V DIFF SSTL2 Il DCI 2Rypp 2Zo 1002 2Rypp 2Zg 1000 HK 2R
131. 334 339 regional clock buffers 21 36 regional clocks clock buffers 39 clock nets 42 REV 314 RSDS 293 380 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX S SelectIO IBUF 231 IBUFDS 232 IBUFG 231 IBUFGDS 232 IOBUF 232 IOBUFDS 233 OBUF 231 OBUFDS 233 OBUFT 232 OBUFTDS 233 Simultaneous Switching Output SSO 302 Slew Rate SLEW 234 SRHIGH 176 SRLOW 176 SSTL 271 Differential SSTL Class II 1 8V 283 288 Differential SSTL2 Class II 2 5V 274 278 SSTL18 Class I 1 8V 282 SSTL18 Class II 1 8V 285 SSTL2 Class I 2 5V 273 SSTL2 Class II 2 5V 276 W WRITE_FIRST mode 116 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 381
132. 4 December 2 2008 X XILINX PLL in Virtex 4 FPGA PMCD Legacy Mode Table 3 8 Mapping of Port Names Continued Virtex 4 FPGA Virtex 5 FPGA Port Name Port Name CLKB1 CLKFBOUT CLKC1 n a CLKD1 n a RST RST REL REL Table 3 9 shows the PLL attributes in Virtex 4 FPGA PMCD legacy mode Table 3 9 PLL Attributes When in Virtex 4 FPGA PMCD Legacy Mode Attribute PLL_PMCD_MODE Type Allowed Values Default Description Boolean TRUE or FALSE FALSE Enables PLL to act as PMCDs EN_REL When in PMCD mode PLL PMCD MODE TRUE Boolean TRUE or FALSE FALSE specifies release of divided clock CLKA outputs when the REL input pin is asserted RST DEASSERT CLK CLKA When in PMCD mode PLL PMCD MODE TRUE String CLKA specifies a clock to synchronize with the release of CLKB RST Table 3 10 shows the PLL ports in Virtex 4 FPGA PMCD legacy mode Table 3 10 PLL Ports in Virtex 4 FPGA PMCD Legacy Mode Port Name 1 0 Pin Description CLKFB Input Virtex 4 FPGA PMCD legacy mode CLKB input clock to the PMCD CLKIN Input Virtex 4 FPGA PMCD legacy mode CLKA input clock to the PMCD RST is the reset input to the Virtex 4 FPGA PMCD legacy mode Asserting RST signal RST Input asynchronously forces all outputs Low Deasserting RST synchronously allows all outputs to toggle REL Input REL is the release input to the Virtex 4 FPGA P
133. 4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX 300 depending on the board design The absolute maximum I O limits might be exceeded even if the clamp diode is active The IBIS models contain the voltage current characteristics of the I O drivers and clamp diodes To verify overshoot and undershoot are within the I O absolute maximum specifications Xilinx recommends proper I O termination and performing IBIS simulation Source Termination and LVDCI 33 In general the I O drivers should match the board trace impedance to within 10 to minimize overshoot and undershoot Source termination is often used for unidirectional interfaces The DCI feature has built in source termination on all user output pins It compensates for impedance changes due to voltage and or temperature fluctuations and can match the reference resistor values Assuming the reference resistor values are the same as the board trace impedance the output impedance of the driver will closely match with the board trace The LVDCI 33 standard is used to enable the DCI features for 3 3V I O operations As shown in Figure 6 91 the OBUF LVDCI 33 primitive is used to implement the source termination function in Virtex 5 FPGA output drivers The pull up resistor connected to VRN and the pull down resistor connected to VRP determine the output impedance of all the output drivers in the same bank The Virtex 5 FPGA Digitally Controlled Impedance DCI secti
134. 5 CLKFBOUT CLKIN CLKFBIN RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Figure 2 14 www xilinx com PLL Driving DCM ug190 2 15 040906 77 Chapter 2 Clock Management Technology 78 XILINX It is also possible to use the DCM to drive a PLL This setup reduces the overall jitter of both the source clock and the DCM clock output In this case only up to two of the DCM output clocks can drive the PLL Therefore only up to two DCM clocks can access the PLL and benefit from the reduced jitter Figure 2 15 and Figure 2 16 illustrate two scenarios of the DCM driving a PLL Figure 2 15 illustrates the direct connection between DCM and PLL within a CMT Only one DCM output can drive PLL using the direct connection within a CMT without routing through a global buffer BUFG The DCM and PLL can be within the same or different CMTs Figure 2 16 illustrates two DCMs driving a PLL In this case BUFG must also be inserted between the DCM clocks driving the PLL input clocks The DCM and PLL can be within the same or different CMTs Refer to Chapter 3 Phase Locked Loops PLLs for more information on PLLs IBUFG CLKO gt CLK90 CLK180 CLK270 CLK2X CLK2X180 gt CLKFBIN CLKDV CLKFX CLKFX180 BUFG CLKOUTO CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT ug190 2 16 040906 Figure 2 15 Direct Connecti
135. 506 Figure 5 16 Representation of a Shift Register Virtex 5 FPGA User Guide www xilinx com 189 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX Figure 5 17 shows two 16 bit shift registers The example shown can be implemented in a single LUT SHIFTIN1 AX A 3 0 sS A 5 2 CLK CE e SHIFTIN2 Al UG190_5_17_050506 Figure 5 17 Dual 16 bit Shift Register Configuration As mentioned earlier an additional output MC31 and a dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next without using the LUT O6 output Longer shift registers can be built with dynamic access to any bit in the chain The shift register chaining and the FZAMUX F7BMUX and FEMUX multiplexers allow up to a 128 bit shift register with addressable access to be implemented in one SLICEM Figure 5 18 through Figure 5 20 illustrate various example shift register configurations that can occupy one SLICEM SHIFTIN D DH i 5 Are 5 0 34 5 A 6 2 A5 AX CK TEE WE gt Output Q AQ Registered Optional MC31 SHIFTOUT Q63 UG190 5 18 050506 Figure 5 18 64 bit Shift Register Configuration 190 www xilinx com Virtex 5 FPGA U
136. 506 Figure 5 35 Example Static Length Shift Register Multiplexer Primitives Two primitives MUXF7 and MUXF8 are available for access to the dedicated F AMUX F7BMUX and F8MUX in each slice Combined with LUTs these multiplexer primitives are also used to build larger width multiplexers from 8 1 to 16 1 The Designing Large Multiplexers section provides more information on building larger multiplexers Port Signals Data In IO 11 The data input provides the data to be selected by the select signal S Control In S The select input signal determines the data input signal to be connected to the output O Logic 0 selects the IO input while logic 1 selects the I1 input Data Out O The data output O provides the data value one bit selected by the control inputs Carry Chain Primitive The CARRYA primitive represents the fast carry logic for a slice in the Virtex 5 architecture This primitive works in conjunction with LUTs in order to build adders and multipliers This primitive is generally inferred by synthesis tools from standard RTL code The synthesis tool can identify the arithmetic and or logic functionality that best maps to this Virtex 5 FPGA User Guide www xilinx com 213 UG190 v4 4 December 2 2008 214 Chapter 5 Configurable Logic Blocks CLBs XILINX logic in terms of performance and area It also automatically uses and connects this function properly Figure 5 24 page 197 illustrates the CA
137. 533 MHz PowerPC processor clock a 266 MHz PowerPC processor gasket clock a 178 MHz clock a 133 MHz memory interface clock a 66 MHz PCI clock and a 33 MHz PCI clock In this example there are no required phase relationships between the reference clock and the output clocks but there are required relationships between the output clocks 33 MHz Reference _ gt ipis PowerPC Processor Core Clock D0 2 PowerPC Processor Gasket i Mz 16 DO 3 CLB Fabric D0 4 Memory Interface I DO 8 PCI 66 D 16 PCI 33 UG190 3 05 111808 Figure 3 5 PLL as a Frequency Synthesizer Jitter Filter PLLs always reduce the jitter inherent on a reference clock The PLL can be instantiated as a standalone function to simply support filtering jitter from an external clock before it is driven into the another block including the DCM As a jitter filter it is usually assumed that the PLL acts as a buffer and regenerates the input frequency on the output e g F 100 MHz Four 100 MHz In general greater jitter filtering is possible by using the PLL attribute BANDWIDTH set to Low Setting the BANDWIDTH to Low can incur an increase in the static offset of the PLL Limitations The PLL has some restrictions that must be adhered to These are summarized in the PLL electrical specification in the Virtex 5 FPGA Data Sheet In general the major limitations are VCO operation range input frequency duty cycle programmability
138. 7 Built in Error Correction 00 0 0000 ccc ccc cc cee le 157 ECC Modes Overview 0 cc en en rrr 158 Top Level View of the Block RAM ECC Architecture 00000004 159 Block RAM and FIFO ECC Primitive lssssseseeeeee e 160 Block RAM and FIFO ECC Port Descriptions ssslseseeeeeeee 161 Block RAM and FIFO ECC Attributes sslleesseeeee ee 163 ECC Modes of Operation 6 ccc ene eee ees 164 Standard BCC 4 d ed a ew ra a Be o E ese Ducks ue Poe Yn 165 ECC Encode Oly poscat iedo annia pede esten Reeder heh foe ee 165 ECC Decode Only 5er tera p rd eet eie Qe d HR deae diete Se 166 ECC Timing Characteristics 0 0 cece ene 167 Standard ECC Write Timing Figure 4 31 isses 167 Standard ECC Read Timing Figure 4 32 0 6 eese 167 Encode Only ECC Write Timing Figure4 31 llle 168 Encode Only ECC Read Timing lseseeseeeeeeeee en 168 Decode Only ECC Write Timing 0 0 00 cece nn 168 Decode Only ECC Read Timing esee nnn 168 Block RAM ECC Mode Timing Parameters llssseeeeeeeeeeeeee 168 Creating a Deliberate Error ina 72 bit Word sess 169 Creating Eight Parity Bits fora 64 bit Word 00 cece eee eee 169 Inserting a Single or Double Bit Error into a 72 bit Word 0 169 Block RAM ECC VHDL and Verilog Templates 0000 c sese 169 Legal Block RAM and FIFO Combinations
139. 8 LVDCI DV2 25 4 The value of the external reference resistors should be selected to give the desired output impedance If using GTL DCI HSTL DCI or SSTL DCII O standards then the external reference resistors should be 50 Q 5 The values of the reference resistors must be within the supported range 20 Q 100 Q 6 Follow the DCI I O banking rules a Vggpmust be compatible for all of the inputs in the same bank b Veco must be compatible for all of the inputs and outputs in the same bank c No more than one DCI I O standard using single termination type is allowed per bank d No more than one DCI I O standard using split termination type is allowed per bank e Single termination and split termination controlled impedance driver and controlled impedance driver with half impedance can co exist in the same bank 7 Master DCI is not supported in Banks 1 and 2 The behavior of a DCI 3 state outputs is as follows If a LVDCI or LVDCI DV2 driver is in 3 state the driver is 3 stated If a driver with single or split termination is in 3 state the driver is 3 stated but the termination resistor remains The following section lists actions that must be taken for each DCI I O standard DCI Usage Examples e Figure 6 16 provides examples illustrating the use of the HSTL I DCI HSTL II DCI HSTL III DCI and HSTL IV DCII O standards 228 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Se
140. 8 16 Block Diagram of OSERDES Width Expansion Table 8 8 lists the data width availability for SDR and DDR mode Table 8 8 OSERDES SDR DDR Data Width Availability SDR Data Widths 2 3 4 5 6 7 8 DDR Data Widths 4 6 8 10 Guidelines for Expanding the Parallel to Serial Converter Bit Width 1 Both the OSERDES modules must be adjacent master and slave pairs 2 Setthe SERDES MODE attribute for the master OSERDES to MASTER and the slave OSERDES to SLAVE See SERDES MODE Attribute 3 The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of the SLAVE 4 The SLAVE only uses the ports D3 to D6 as an input 5 DATA WIDTH for Master and Slave are equal See DATA WIDTH Attribute The slave inputs used for data widths requiring width expansion are listed in Table 8 9 Table 8 9 Slave Inputs Used for Data Width Expansion Data Width Slave Inputs Used 7 D3 8 D3 D4 10 D3 D6 372 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Parallel to Serial Logic Resources OSERDES OSERDES Latencies The input to output latencies of OSERDES blocks depend on the DATA_RATE and DATA_WIDTH attributes Latency is defined as a period of time between the following two events a when the rising edge of CLKDIV clocks the data at inputs D1 D6 into the OSERDES and b when the first bit of the serial stream appears at OQ Table 8 10 summarizes the
141. 9 the reset pulse is generated on the rising edge of CLKDIV Because the pulse must take two different routes to get to ISERDESO and ISERDESI there are different propagation delays for both paths The difference in propagation delay is emphasized The path to ISERDESO is very long and the path to ISERDESI is very short such that each ISERDES receives the reset pulse in a different CLK cycle The internal resets for both CLK and CLKDIV are reset asynchronously when the RST input is asserted www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES Clock Clock Clock Clock Event 1 Event2 Event3 Event 4 l cov A 4 4i 4 ISERDESO Signal at 2 RST Input ISERDES1 a l ISERDESO Internal Reset CLKDIV 4 ISERDES1 ISERDESO Internal Reset 2 CLK ISERDES1 UG190 8 09 110707 Figure 8 9 Two ISERDES Coming Out of Reset Synchronously with One Another Clock Event 2 The reset pulse is deasserted on the rising edge of CLKDIV The difference in propagation delay between the two ISERDES causes the RST input to come out of reset on two different CLK cycles Without internal retiming ISERDESI finishes reset one CLK cycle before ISERDESO and both ISERDES are asynchronous Clock Event 3 The release of the reset signal at the RST input is retimed internally to CLKDIV This synchronizes ISERDESO and ISERDES1 Clo
142. 90 v4 4 December 2 2008 XILINX Synchronous Dual Port and Single Port RAMs CLK L0 A NZ SN No N WE DI ADDR EN Disable Read Write Write Read MEM bb 1111 MEM cc 2222 ugi90 4 05 032206 Figure 4 4 NO CHANGE Mode Waveforms Conflict Avoidance Virtex 5 FPGA block RAM memory is a true dual port RAM where both ports can access any memory location at any time When accessing the same memory location from both ports the user must however observe certain restrictions There are two fundamentally different situations The two ports either have a common clock synchronous clocking or the clock frequency and phase is different for the two ports asynchronous clocking Asynchronous Clocking Asynchronous clocking is the more general case where the active edges of both clocks do not occur simultaneously There are no timing constraints when both ports perform a read operation When one port performs a write operation the other port must not read or write access the same memory location The simulation model will produce an error if this condition is violated If this restriction is ignored a read or write operation will produce unpredictable results There is however no risk of physical damage to the device If a read and write operation is performed then the write will store valid data at the write location Synchronous Clocking Synchronous clocking is the special case where the active edges of bot
143. ATA RATE Attribute 354 The DATA RATE attribute defines whether the incoming data stream is processed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR and DDR The default value is DDR www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES DATA WIDTH Attribute The DATA WIDTH attribute defines the parallel data output width of the serial to parallel converter The possible values for this attribute depend on the INTERFACE TYPE and DATA RATE attributes See Table 8 3 for recommended data widths Table 8 3 Recommended Data Widths INTERFACE TYPE DATA RATE Recommended Data Widths SDR 2 3 4 5 6 7 8 NETWORKING DDR 4 6 8 10 SDR None MEMORY DDR 4 When the DATA_WIDTH is set to widths larger than six a pair of ISERDES NODELAY must be configured into a master slave configuration See ISERDES Width Expansion Width expansion is not allowed in memory mode INTERFACE TYPE Attribute The INTERFACE TYPE attribute determines whether the ISERDES NODELAY is configured in memory or networking mode The allowed values for this attribute are MEMORY or NETWORKING The default mode is MEMORY When INTERFACE TYPE is set to NETWORKING the Bitslip submodule is available and the OCLK port is unused BITSLIP_ENABLE must be set to TRUE and the Bitslip port tied Low to disable Bitslip operat
144. B Slice Timing Models Table 5 7 General Slice Timing Parameters Continued Parameter Function Description Frog Toggle Frequency Maximum frequency that a CLB flip flop can be clocked 1 Tey Tez Notes 1 This parameter includes a LUT configured as two five input functions 2 Tyxck Setup Time before clock edge and Tckxx Hold Time after clock edge Timing Characteristics Figure 5 26 illustrates the general timing characteristics of a Virtex 5 FPGA slice AX BX CX DX NE cS NN DATA ii _ TsRCK SR RESET l 7 N q Tcko l lt Tcko AQ BQ CQ DQ a 2 T OUT l ugi 90 5 26 050506 Figure 5 26 General Slice Timing Characteristics e Attime Togo before clock event 1 the clock enable signal becomes valid high at the CE input of the slice register e At time Tpjcx before clock event 1 data from either AX BX CX or DX inputs become valid high at the D input of the slice register and is reflected on either the AQ BO CQ or DQ pin at time Toyo after clock event 1 e At time Tsrcx before clock event 3 the SR signal configured as synchronous reset becomes valid high resetting the slice register This is reflected on the AQ BO CQ or DQ pin at time Toyo after clock event 3 Virtex 5 FPGA User Guide www xilinx com 201 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX Slice Distributed RAM Timing Model and Par
145. CADEINREGB ug0190 4 10 100906 Figure 4 9 Block RAM Port Signals RAMB36 Table 4 5 Virtex 5 FPGA Block RAM FIFO Simple Dual Port and ECC Primitives Primitive Description RAMB36 Supports port widths of x1 x2 x4 x9 x18 x36 RAMB36SDP Simple dual port port width x72 and 64 bit ECC primitive see Figure 4 29 FIFO36 Supports port widths of x4 x9 x18 x36 FIFO36_72 FIFO port width x72 optional ECC support RAMB18 Supports port widths of x1 x2 x4 x9 x18 RAMBI8SDP Simple dual port port width x36 FIFO18 Supports port widths of x4 x9 x18 122 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Port Signals Table 4 5 Virtex 5 FPGA Block RAM FIFO Simple Dual Port and ECC Primitives Primitive Description FIFO18_36 FIFO port width x36 Notes 1 All eight primitives are described in the software Libraries guide as well as the language templates Block RAM Port Signals Each block RAM port operates independently of the other while accessing the same set of 36K bit memory cells Clock CLK AIB Each portis fully synchronous with independent clock pins All port input pins have setup time referenced to the port CLK pin The output data bus has a clock to out time referenced to the CLK pin Clock polarity is configurable rising edge by default Enable EN AIB The enable pin affects the read write and set
146. Comparison of Synchronous FIFO Implementations Synchronous FIFO Implementations EN SYN TRUE DO REG 0 Advantages No flag uncertainty Disadvantages Longer clock to out signals EN SYN TRUE DO REG 1 Faster clock to out signals no flag uncertainty Data Latency increased by one Behaves like a synchronous FIFO with an extra data output pipeline register EN SYN FALSE DO REG 1 RDCLK WRCLK Faster clock to out signals Similar to a Virtex 4 FIFO Falling edge flag uncertainty Rising edge guaranteed on FULL and EMPTY rdclk rden DO EN_SYN TRUE DO_REG 0 DO EN_SYN TRUE DO REG 1 DO EN SYN FALSE DO REG 1 140 ugi90 c4 x1 071007 Figure 4 16 Synchronous FIFO Data Timing Diagram www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Architecture a Top Level View FIFO Architecture a Top Level View Figure 4 17 shows a top level view of the Virtex 5 FIFO architecture The read pointer write pointer and status flag logic are dedicated for FIFO use only WRCOUNT DIN DINP gt DO DOP WRCLK RDCLK WREN RDEN RST TINALSOW1V lt ug190_4_27_061906 Figure 4 17 Top Level View of FIFO in Block RAM FIFO Primitives Figure 4 18 shows the FIFO36 primitive FIFO36 DI 31 0 DO 31 0 DIP 3 0 DOP 3 0 RDEN WRCOUNT 12 0 RDCLK RDCOUNT 12 0
147. Connecting FIFOs in Parallel to Increase Width Built in Error Correction Each simple dual port block RAM can be configured as a single 512 x 64 RAM with built in Hamming code error correction using the extra eight bits in the 72 bit wide RAM The operation is transparent to the user Eight protection bits ECCPARITY are generated during each write operation and stored with the 64 bit data into the memory These ECCPARITY bits are used during each read operation to correct any single bit error or to detect but not correct any double bit error The ECCPARITY bits are written into the memory and output to the FPGA fabric at each rising edge of the WRCLK There are no optional output registers available on the ECCPARITY output bits During each read operation 72 bits of data 64 bits of data and an 8 bit parity are read from the memory and fed into the ECC decoder The ECC decoder generates two status outputs SBITERR and DBITERR that are used to indicate the three possible read results No error single bit error corrected double bit error detected In the standard ECC mode the read operation does not correct the error in the memory array it only presents corrected data on DO To improve Fmax optional registers controlled by the DO REG attribute are available for data output DO SBITERR and DBITERR This ECC configuration option is available with a 36K block RAM simple dual port primitive RAMB36SDP or a 36K FIFO primitive FIFO36 72
148. DCI 12 25 GTLP 12 25 3 3V GTLP_DCI 12 25 LVDCI_33 50 Q 20 40 HSLVDCI 33 50 Q 20 40 Actual SSO Limits versus Nominal SSO Limits The Virtex 5 FPGA SSO limits are defined for a set of nominal system conditions in Table 6 40 To compute the actual limits for a specific user s system the Parasitic Factors Derating Method PFDM must be used The PFDM allows the user to account for differences between actual and nominal PCB power systems receiver capacitive loading and maximum allowable ground bounce or Vcc bounce A spreadsheet calculator Full Device SSO Calculator automates this process Electrical Basis of SSO Noise SSO noise can manifest as power supply disturbance in the form of ground bounce or Vcc bounce GND and Vcc bounce is a deviation of the die supply voltage die GND rail or die Vcc rail with respect to the voltage of the associated PCB supply PCB GND rail or PCB Vcc rail The deviation of die supplies from PCB supplies comes from the voltage induced across power system parasitics by supply current transients One cause of current transients is output driver switching events Numerous output switching events occurring at the same time lead to bigger current transients and therefore bigger induced voltages ground bounce Vcc bounce or rail collapse Relevant transient current paths exist in the die package and PCB therefore parasitics from all three must be considered The larger the value of thes
149. DIFF HSTL II 18 N R N R N R SSTL18 I 0 9 N R N R SSTL18 II 0 9 N R N R DIFF SSTL18 I N R N R N R DIFF SSTL18 II N R N R N R LVCMOS18 N R N R N R LVDCI 18 N R Series N R HSLVDCI 18 Vcco 2 Series N R LVDCI DV2 18 m N R Series N R HSTL III DCI 18 1 08 N R Single HSTL IV DCI 18 1 08 Single Single HSTL I DCI 18 0 9 N R Split HSTL II DCI 18 0 9 Split Split HSTL II T DCI 18 n 0 9 N R Split DIFF HSTL I DCI 18 N R N R Split DIFF HSTL II DCI 18 N R Split Split SSTL18 I DCI 0 9 N R Split SSTL18 II DCI 0 9 Split Split SSTL18 II T DCI 0 9 N R Split DIFF SSTL18 I DCI N R N R Split DIFF SSTL18 II DCI N R Split Split 297 Chapter 6 SelectlO Resources XILINX Table 6 39 WO Compatibility Continued iG Standard Veco VREF Termination Type Output Input Input Output Input HSTL III 0 9 N R N R HSTL IV 0 9 N R N R HSTL I 0 75 N R N R Note 2 HSTL II 0 75 N R N R DIFF HSTL I N R N R N R DIFF HSITL II N R N R N R LVCMOS15 N R N R N R LVDCI 15 N R Series N R HSLVDCI 15 Vcco 2 Series N R LVDCI DV2 15 lt N R Series N R GTLP_DCI 1 Single Single HSTL III DCI 0 9 N R Single HSTL IV DCI d 0 9 Single Single HSTL I DCI 0 75 N R Split HSTL II DCI 0 75 Split Split HSTL II T DCI 0 75 N R Split DIFF HSTL I DCI N R N R Split DIFF HSTL II DCI N R Split Split GTL DCI 1 2 1 2 0 8 Single
150. E DEN LOCKED to RST DCM ADV CLKO CLKIN eiii CLK180 CLKFB CLK270 CLK2X RST CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 DWE LOCKED DEN DO 15 0 DCLK Virtex 5 FPGA BUFG IBUFG DCM_ADV CLKO gt gt CLKIN CLK90 CLK180 CEKER CLK270 CLK2X RST CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 BINE LOCKED DEN DO 15 0 DCLK This circuit can be duplicated to multiple Virtex devices Use CLKDLL for Virtex and Virtex E devices DCM for Virtex Il and Virtex Il Pro devices ugi90 2 12 032506 Figure 2 11 Board Deskew with Internal Deskew Interfacing to Other Virtex Devices 74 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Application Examples The example in Figure 2 12 shows an interface from Virtex 5 FPGAs to components other than Virtex FPGAs r Virtex 5 FPGA Voc ODDR Vis DCM ADV BURG Di Q gt CLKIN CLKO gt D2 CLK90 GND IBUFG CLK180 c CLK270 CLK2X RST CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK DADDR 6 0 DI 15 0 DWE DEN DCLK LOCKED DO 15 0 BUFG DCM_ADV CLKIN CLKO CLK90 CLKFB CLK180 CLK270 RST CLK2X CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 DWE DEN LOCKED DCLK DO 15 0 hon Virtex chips ugi90 2 13 032506
151. E ad eel ex Soe oes oe pus 47 DEM POTTS obo me epu e Ieri tied ind aimee qr etes EE 47 DCM Clock Input Ports ssssssseeeeeeeee Ie 47 Source Clock Inp t CEKIN aee 22 e Sota das ete a aie eae abe ao 47 Feedback Clock Input CLKFB cres lisse Ie 48 Phase Shift Clock Input PSCLK 1 0 eect eet eee 48 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 XILINX Dynamic Reconfiguration Clock Input DCLK ssseeeeeeeee ee 49 DCM Control and Data Input Ports 6 6 6 49 Reset hput RST celsegsascie amp e9eedqererretescertppscr E E ee E pda 49 Phase Shift Increment Decrement Input PSINCDEC sse 49 Phase Shift Enable Input PSEN sseeeeeeeee hn 50 Dynamic Reconfiguration Data Input DI 15 0 0 2 cece eee eee eee 50 Dynamic Reconfiguration Address Input DADDR 6 0 0 0000000 50 Dynamic Reconfiguration Write Enable Input DWE 0000 e eee eee 50 Dynamic Reconfiguration Enable Input DEN ne 50 DCM Clock Output Ports 2 0 6 Ie 50 IxOutput Clock CEK erore seca ede eben d eyes ie Pees oe eda 50 1x Output Clock 90 Phase Shift CLK90 2 0 6 eee eens 51 1x Output Clock 180 Phase Shift CLK180 6 0 sisse ne 51 1x Output Clock 270 Phase Shift CLK270 0 0 cee e 51 2x Output Clock CLK2X zi seas rere E ER E yee P WX RE d que px c vee 51 2x Output Clock 180 Phase Shift CLK2X180 cc 51 Frequency Divide Output Cl
152. E es 59 Clock Deskew Operation oosten eneretten a hn 59 Input Clock Requirements 2 aus ea ey a e eu a d c c a 60 Inp t Glock Changes see ewe pur duce and Eee et pedites 60 Qutp t Clocks iia tetas a i I ace e dette de deed erred eius 61 DCM During Configuration and Startup csse 61 Deskew Adjust eee erit eed D ede Ege Noa I d eae ioe aus 61 Characteristics of the Deskew Circuit 0 00 00 63 Frequency Synthesis er tirisin iaa eens 63 Frequency Synthesis Operation lesse ne 63 Frequency Synthesizer Characteristics 0 eee eee 64 Phase Shifting se fo ssc vea te Hepat ee heeled Mie telo d dort oe E peed 64 Phas Shiftinge Operation scese cede era bea oe ER wha bea Ede re Rees 64 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Interaction of PSEN PSINCDEC PSCLK and PSDONE 2 0 0 67 Phase Shift Overtlow eese deir eir e ed etti qo ete dox doc eed dota 68 Phase Shift Characteristics 5 26s ek lp p RU E RP ERN EIER ue av iE PAS 68 Dynamic Reconfiguration aE E E een 69 Connecting DCMs to Other Clock Resources in Virtex 5 Devices 69 IBUFG to DGM Pert 69 DCM fo BUFGCTRL i icio irie i e ie dn 69 BLIPGCTBEO DEM merieirvut neni eega aii ee eE E E ER E E a ER 69 PLL Toa nd From DCM 4 ce rete dal eee ee eee E oe d dece ar rea 70 DCM To and From PMCD ei scene eere rate apiece x eie kid ie qo gk d eda 70 Application Examples ssssss
153. ELAY or bidirectional delay When used as IDELAY the data input comes from either IBUF or the fabric and the output goes to ILOGIC ISERDES There are three modes of operation available e Zero hold time delay mode IDELAY TYPE DEFAULT This mode of operation allows backward compatibility for designs using the zero hold time delay feature in Virtex IL Virtex II Pro and Virtex 4 devices This delay element is used to provide non positive hold times when global clocks are used without DCMs to capture data pin to pin parameters When used in this mode the IDELAYCTRL primitive does not need to be instantiated See IDELAYCTRL Usage and Design Guidelines for more details e Fixed delay mode IDELAY TYPE FIXED In the fixed delay mode the delay value is preset at configuration to the tap number determined by the attribute IDELAY VALUE Once configured this value cannot be changed When used in this mode the IDELAYCTRL primitive must be instantiated See IDELAYCTRL Usage and Design Guidelines for more details e Variable delay mode IDELAY TYPE VARIABLE In the variable delay mode the delay value can be changed after configuration by manipulating the control signals CE and INC When used in this mode the IDELAYCTRL primitive must be instantiated See IDELAYCTRL Usage and Design Guidelines for more details When used as ODELAY the data input comes from OLOGIC OSERDES and the data output goes to OBUF There is a single mode of oper
154. ERR Register Mode ugi90 4 33 020707 Figure 4 32 ECC Read Operation 164 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Built in Error Correction Standard ECC Set by Attributes EN_ECC_READ TRUE EN_ECC_WRITE TRUE Standard ECC Write At time T1W DI 63 0 A is written into memory location a The corresponding 8 bits of ECC parity PA hex are generated internally appended to the 64 data bits and written into the memory Immediately after the write the parity value PA appears at output ECCPARITY 7 0 Since ECC parity is generated internally DIP 7 0 pins are not used Similarly at time T2W and T3W DI 63 0 B and C together with their corresponding parity bits PB hex and PC hex are written into memory locations b and c PB and PC appear at output ECCPARITY 7 0 shortly after T2W and T3W Standard ECC Read At time TIR the 72 bit memory content consisting 64 bits of data A and 8 bits of parity PA hex of address location a is read and decoded internally If there is no error the original data and parity are output at DO 63 0 and DOP 7 0 If there is a single bit error in either the data or the parity the error is corrected and SBITERR is High If there is a double bit error in the data and parity the error is not corrected The original data and parity is output and DBITERR is High If attribute DO REG is set to 0 DO 63 0 A and DOP 7 0 PA shortly after TIR Simila
155. FF_SSTL18_I_DCI VNAPS Ro 20 DIFF SSTL18 I DCI E 2Rypp 2Zg 1000 E 2Rypy 2Zg 1002 ugi 90 6 74 032206 Figure 6 78 Differential SSTL 1 8V Class I Unidirectional DCI Termination Virtex 5 FPGA User Guide www xilinx com 283 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 32 lists the differential SSTL 1 8V Class I DC voltage specifications Table 6 32 Differential SSTL 1 8V Class I and Class Il DC Voltage Specifications Min Typ Max Veco 1 7 1 8 1 9 Input Parameters Ver Vccox 0 5 Vin DC 0 30 Veco 0 30 Vip DC 0 25 Veco 0 60 Vip AC 0 50 Veco 0 60 Vix AC 0 675 1 125 Output Parameters Vox AC 9 0 725 1 075 Notes 1 Vi DC specifies the allowable DC excursion of each differential input 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 3 Vip DC specifies the input differential voltage required for switching 4 Vix AC indicates the voltage where the differential input signals must cross 5 Vox AC indicates the voltage where the differential output signals must cross 284 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards SSTL18 Class II 1 8V Figure 6 79 shows a sample circuit illustrating a vali
156. Figure 2 12 Board Deskew with Internal Deskew Interfacing to Other Components Virtex 5 FPGA User Guide www xilinx com 75 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Clock Switching Between Two DCMs Figure 2 13 illustrates switching between two clocks from two DCMs while keeping both DCMs locked gt CLKIN CLKO gt CLK90 CLK180 CLKA CLKFB CLK270 CLK2X RST CLK2X180 PSINCDEC CLKDV BUFGMUX PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 DWE LOCKED DEN DO 15 0 DCLK IBUFG DCM ADV BUFG gt CLKIN CLKO CLK90 CLK180 CLKB GESER CLK270 RST CLK2X CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 DWE LOCKED DEN DO 15 0 DCLK ugi90 2 14 032506 Figure 2 13 Clock Switching Between Two DCMs 76 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX DCM with PLL Application Examples The PLL can be used to drive the DCM to reduce the source clock s incoming jitter before inputting DCM This setup reduces the source clock jitter while enabling user access to all available DCM clock outputs Figure 2 14 illustrates the PLL driving a DCM within the same CMT block using the dedicated routing resource without BUFC Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 IBUFG gt gt CLKIN1 r CLKFBIN CLKOUTO CLKOUT1 CLKOUT2 CLKOUTS CLKOUT4 CLKOUT
157. Figure 6 83 shows a sample circuit illustrating a valid termination technique for differential SSTL Class II 1 8V with bidirectional termination External Termination IOB IOB Vr 0 9V Vr 0 9V DIFF SSTL18 Il iie dis DIFF SSTL18 Il 200 200 w VED wrx Vr 0 9V Vr 0 9V DIFF SSTL18 II DIFF SSTL18 Il 308 502 502 i jw 20 pd DIFF SSTL18 II DIFF SSTL18 Il ug 90 6 79 091807 Figure 6 83 Differential SSTL 1 8V Class II with Bidirectional Termination Figure 6 84 shows a sample circuit illustrating a valid termination technique for differential SSTL Class II 1 8V with bidirectional DCI termination DCI DIFF SSTL18 Il DCI Ro 20 DIFF SSTL18 Il DCI 2Rygp 2Zo 1000 2Rygw 2Zo 1002 IOB Ro 200 DIFF SSTL18 Il DCI Veco 1 8V 2Rypp 2Zg 1002 2Rygw 2Z9 1000 Figure 6 84 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 IOB 2Rypp 2Z9 1000 DIFF SSTL18 Il DCI www xilinx com z 2Rypy 2Zo 1002 Ro 20Q DIFF SSTL18 Il DCI Rp 200 DIFF SSTL18 Il DCI 2Rypp 2Zg 1000 2Rypy 2Zp 1002 ug190_6_80_030506 Differential SSTL 1 8V Class II with DCI Bidirectional Termination 289 Chapter 6 SelectlO Resources XILINX Table 6 35 lists the differential SSTL 1 8V Class II DC voltage specifications Table 6 35 Differential SSTL 1 8V Class Il DC Vo
158. GE SAME EDGE INIT 1 b0 SRTYPE SYNC TRI ODDR INST C clk CE 1 b1 D1 T1 D2 T2 R 1 b0 S 1 b0 Q TSCONTROL IDELAYCTRL IDELAYCTRL INST REFCLK refclk RST 1 b0 RDY Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 329 Chapter 7 SelectlO Logic Resources XILINX 330 Two cases that use the bidirectional IODELAY functionality are important for a given I O pin The first case uses bidirectional IODELAY when the I O is an output being switched to an input Figure 7 11 shows the IOB and IODELAY moving toward the input mode as set by the TSCONTROL net coming from the ODDR flip flop This controls the selection of MUxXes E and F for the IOB input path and IDELAY VALUE respectively Additionally the OBUF is 3 stated TSCONTROL en der hh hh essssesesesessesesesessssesesesessosesesesoseoe ODATAIN DATAOUT PAD lt pe vau Tp IODELAY_02_082107 Figure 7 11 ODELAY and IOB in Input Mode when 3 state is Disabled www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY The timing diagram in Figure 7 12 shows the relevant signal timing for the case when the I O is an output switching to an input using 3 state control The switching characteristics shown in the diagram are specified in the Virtex 5 FPGA Data Sheet ODDR CLK
159. Guide www xilinx com 49 UG190 v4 4 December 2 2008 50 Chapter 2 Clock Management Technology XILINX Phase Shift Enable Input PSEN The phase shift enable PSEN input signal must be synchronous with PSCLK A variable phase shift operation is initiated by the PSEN input signal It must be activated for one period of PSCLK After PSEN is initiated the phase change is gradual with completion indicated by a High pulse on PSDONE There are no sporadic changes or glitches on any output during the phase transition From the time PSEN is enabled until PSDONE is flagged the DCM output clock moves bit by bit from its original phase shift to the target phase shift The phase shift is complete when PSDONE is flagged PSEN must be tied to ground when the CLKOUT PHASE SHIFT attribute is set to NONE or FIXED Figure 2 6 shows the timing for this input Dynamic Reconfiguration Data Input DI 15 0 The dynamic reconfiguration data DI input bus provides reconfiguration data for dynamic reconfiguration When not used all bits must be assigned zeros See the Dynamic Reconfiguration chapter of the Virtex 5 FPGA Configuration Guide for more information Dynamic Reconfiguration Address Input DADDR 6 0 The dynamic reconfiguration address DADDR input bus provides a reconfiguration address for the dynamic reconfiguration When not used all bits must be assigned zeros and the DO output bus reflects the DCM s status See the Dynamic Reconfigurati
160. IO Logic Resources describes the input and output data registers and their Double Data Rate DDR operation and the programmable input delay IDELAY Chapter 8 Advanced SelectIO Logic Resources describes the data serializer deserializer SERDES An I O tile contains two IOBs two ILOGICs two OLOGICs and two IODELAYs Figure 6 1 shows a Virtex 5 FPGA I O tile IODELAY Chapter 7 ILOGIC Chapter 7 or ISERDES Chapter 8 OLOGIC Chapter 7 or OSERDES Chapter 8 ILOGIC Chapter 7 or ISERDES Chapter 8 OLOGIC Chapter 7 or OSERDES Chapter 8 IODELAY Chapter 7 ug190 6 01 041106 Figure 6 1 Virtex 5 FPGA I O Tile Virtex 5 FPGA User Guide www xilinx com 215 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX SelectlO Resources Introduction All Virtex 5 FPGAs have configurable high performance SelectIO drivers and receivers supporting a wide variety of standard interfaces The robust feature set includes programmable control of output strength and slew rate and on chip termination using Digitally Controlled Impedance DCI Each IOB contains both input output and 3 state SelectIO drivers These drivers can be configured to various I O standards Differential I O uses the two IOBs grouped together in one tile e Single ended I O standards LVCMOS LVTTL HSTL SSTL GTL PCI e Differential I O standards LVDS HT LVPECL BLVDS Differential HSTL and SSTL e D
161. ISERDES NODELAY Ports 0 00 0 000 ccc ce hr rh 351 Registered Outputs Q1 to Q6 2 nn 351 Bitslip Operation BITSLIP erbe bg deeded ed nente eee rcs 352 Clock Enable Inputs CE1 and CE2 0 ec eens 352 High Speed Clock Input CLK 2 co cee eens 353 High Speed Clock Input CLKB 6 0 eee eens 353 Divided Clock Input CLKDIV 0 0 ccc cece eens 353 Serial Input Data from IOB D 6 eee nn 353 High Speed Clock for Strobe Based Memory Interfaces OCLK 353 Reset Input ROT 5o eoe eta le whee acetate eate pede i ean ota eed 353 ISERDES NODELAY Attributes ssseeeeeeeee enn hn 354 BITSLIP ENABLE Attribute 0 0 ccc ce hh 354 DATA RATE Attribute 2 0 ee han 354 DATA WIDTH AH butesi eeren eke etse Ite ober pe n eta CI ecce e be Re tcn 355 INTERFACE TYPE Attribute 0 0 0 cc ee an 355 NUM CE Attribute rectore esee tese inch ga E E EE E e kena RR uy 356 SERDES MODE Attribute llle rs 356 ISERDES NODELAY Clocking Methods ssssssseeeeeeeeeeeeeeee 356 Networking Interface Type csse hn 356 Memory Interface Type 2 e RR hk ek beeen ee ated ea 357 ISERDES Width Expansion sssssseese eir tee eties 357 Guidelines for Expanding the Serial to Parallel Converter Bit Width 358 ISERDES Lateticies8 soils RR eR RR RE ARE UV ERE SOR E esa 359 ISERDES Timing Model and Parameters lsseeeee 359 Timing CharacteristiCs espos ee re
162. LKDIV for CE2 Setup Hold for Data Lines Trspck D A Trsckp D D pin Setup Hold with respect to CLK D pin Setup Hold with respect to CLK D pin Setup Hold with respect to CLK TispCK_DDR TisCKD_DDR D pin Setup Hold with respect to CLK at DDR mode D pin Setup Hold with respect to CLK at DDR mode D pin Setup Hold with respect to CLK at DDR mode Sequential Delay Trscko Qo CLKDIV to Out at Q pins Virtex 5 FPGA User Guide www xilinx com 359 UG190 v4 4 December 2 2008 360 Chapter 8 Advanced SelectlO Logic Resources XILINX Timing Characteristics Figure 8 8 illustrates an ISERDES timing diagram for the input data to the ISERDES The timing parameter names change for different modes SDR DDR However the names do not change when a different bus input width including when two ISERDES are cascaded together to form 10 bits In DDR mode the data input D switches at every CLK edge rising and falling 1 2 l o r iscck cg CE I qe Tsocko i D ug190_8_08_100307 Figure 8 8 SERDES Input Data Timing Diagram Clock Event 1 e At time Tiscck cr before Clock Event 1 the clock enable signal becomes valid High and the ISERDES can sample data Clock Event 2 e At time Trspck p before Clock Event 2 the input data pin D becomes valid and is sampled at the next positive clock edge Reset Input Timing Clock Event 1 As shown in Figure 8
163. LL OSERDES Width Expansion Two OSERDES modules are used to build a parallel to serial converter larger than 6 1 In every I O tile there are two OSERDES modules one master and one slave By connecting the SHIFTIN ports of the master OSERDES to the SHIFTOUT ports of the slave OSERDES the parallel to serial converter can be expanded to up to 10 1 DDR and 8 1 SDR For a differential output the master OSERDES must be on the positive side of the differential output pair When the output is not differential the output buffer associated with the slave OSERDES is not available and can not be used When using the OSERDES with width expansion complementary single ended standards e g DIFF HSTL and DIFF SSTL cannot be used This is because both OLOGIC blocks in an I O tile are used by the complementary single ended standards to transmit both legs of the signal leaving no OLOGIC blocks available for width expansion Virtex 5 FPGA User Guide www xilinx com 371 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX Figure 8 16 illustrates a block diagram of a 10 1 DDR parallel to serial converter using the master and slave OSERDES modules Ports Q3 Q6 are used for the last four bits of the parallel interface on the slave OSERDES LSB to MSB Data Out OSERDES Data Inputs 0 5 Master 6 SHIFTIN1 SHIFTIN2 OSERDES Data Inputs 6 9 Slave SERDES MODE SLAVE ug190 8 16 100307 Figure
164. Low asynchronously ISERDES NODELAY circuits running in the CLK domain where timing is critical use an internal dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLK domain Similarly there is a dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLKDIV domain Because there are ISERDES NODELAY circuits that retime the RST input the user is only required to provide a reset pulse to the RST input that meets timing on the CLKDIV Virtex 5 FPGA User Guide www xilinx com 353 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX frequency domain Therefore RST should be driven High for a minimum of one CLKDIV cycle When building an interface consisting of multiple ISERDES NODELAY ports all ISERDES NODELAY ports in the interface must be synchronized The internal retiming of the RST input is designed so that all ISERDES_NODELAY blocks that receive the same reset pulse come out of reset synchronized with one another The reset timing of multiple ISERDES_NODELAY ports is shown in Figure 8 9 page 361 ISERDES NODELAY Attributes Table 8 2 summarizes all the applicable ISERDES NODELAY attributes A detailed description of each attribute follows the table For more information on applying these attributes in UCF VHDL or Verilog code refer to the Xilinx ISE Software Manual Table 8 2 ISERDES NODELAY Attributes mem D
165. MCD legacy mode Asserting the REL signal releases the divided outputs synchronous to CLKA CLKOUTO Output Virtex 4 FPGA PMCD legacy mode CLKB1 CLKOUTI1 Output Virtex 4 FPGA PMCD legacy mode CLKA1 CLKOUT2 Output Virtex 4 FPGA PMCD legacy mode CLKA1D2 CLKOUT3 Output Virtex 4 FPGA PMCD legacy mode CLKA1D4 CLKOUT4 Output Virtex 4 FPGA PMCD legacy mode CLKA1D8 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 109 Chapter 3 Phase Locked Loops PLLs XILINX 110 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Chapter 4 Block RAM Block RAM Summary The block RAM in Virtex 5 FPGAs stores up to 36K bits of data and can be configured as either two independent 18 Kb RAMs or one 36 Kb RAM Each 36 Kb block RAM can be configured as a 64K x 1 when cascaded with an adjacent 36 Kb block RAM 32K x 1 16K x 2 8K x 4 4K x 9 2K x 18 or 1K x 36 memory Each 18 Kb block RAM can be configured as a 16K x 1 8K x2 4K x 4 2K x 9 or 1K x 18 memory Similar to the Virtex 4 FPGA block RAMs Write and Read are synchronous operations the two ports are symmetrical and totally independent sharing only the stored data Each port can be configured in one of the available widths independent of the other port In addition the read port width can be different from the write port width for each port The memory content can be initialized or cleared by the configur
166. Models and Parameters Case 3 Reading From a Full FIFO Prior to the operations performed in Figure 4 23 the FIFO is completely full DO 00 X 0 X 02 X 03 X 04 X l05 X 06 T F L 1 t bcheeru eM AFULL l ug190_4_19_040606 Figure 4 23 Reading From a Full FIFO Clock Event 1 and Clock Event 2 Read Operation and Deassertion of Full Signal During a read operation on a full FIFO the content of the FIFO at the first address is asserted at the DO output pins of the FIFO Two RDEN operations ensure that the FIFO is no longer full and after three WRCLK cycles the FULL pin is deasserted The example in Figure 4 23 reflects both standard and FWFT modes Clock event 1 and 2 are with respect to read clock Clock event 4 appears three write clock cycles after clock event 2 e At time Trcck RDEN before clock event 1 RDCLK read enable becomes valid at the RDEN input of the FIFO e At time Trcko po after clock event 1 RDCLK data 00 becomes valid at the DO outputs of the FIFO e Attime Trcko FULL after clock event 4 WRCLK FULL is deasserted If the rising RDCLK edge is close to the rising WRCLK edge FULL could be deasserted one WRCLK period later Clock Event 3 and Clock Event 5 Read Operation and Deassertion of Almost FULL Signal Three write clock cycles after the fourth data is read from the FIFO the Almost FULL pin is deasserted to signify that the FIFO is not in the almost FULL state
167. NX Lock Lock Monitor 8 phase taps Ipep cp te vco i 02 CLKFBOUT 8 x 03 VCO feedback phase selection for negative O4 phase shift affecting all outputs O5 e el el fe l el ug190_3_03_050906 Figure 3 3 Detailed PLL Block Diagram www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX General Usage Description General Usage Description PLL Primitives The two Virtex 5 FPGA PLL primitives PLL_BASE and PLL ADV are shown in Figure 3 4 CLKIN1 CLKOUTO CLKOUT1 CLKFBIN CLKOUT2 RST CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT CLKIN1 CLKOUTO CLKIN2 CLKOUT1 CLKFBIN CLKOUT2 RST CLKOUT3 CLKINSEL CLKOUT4 DADDR 4 0 CLKOUTS DI 15 0 CLKFBOUT DWE CLKOUTDCMO DEN CLKOUTDCM1 DCLK CLKOUTDCM2 REL CLKOUTDCM3 CLKOUTDCM4 CLKOUTDCM5 CLKFBDCM LOCKED DO 15 0 DRDY LOCKED PLL_BASE PLL_ADV ug190 3 04 050806 Figure 3 4 PLL Primitives PLL BASE Primitive The PLL BASE primitive provides access to the most frequently used features of a stand alone PLL Clock deskew frequency synthesis coarse phase shifting and duty cycle programming are available to use with the PLL BASE The ports are listed in Table 3 1 Table 3 1 PLL BASE Ports Description Port Clock Input CLKIN CLKFBIN Control Inputs RST Clock Output CLKOUTO to CLKOUTS5 CLKFBOUT Status and Data Outputs LOCKED
168. O_RDCOUNT Clock to read pointer RDCOUNT Time after RDCLK that the Read pointer signal is output stable at the RDCOUNT outputs of the FIFO TrcKO_WRCOUNT Clock to write pointer WRCOUNT Time after WRCLK that the Write pointer signal is output stable at the WRCOUNT outputs of the FIFO 148 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Table 4 20 FIFO Timing Parameters Continued FIFO Timing Models and Parameters Control a Parameter Function Signal Description Reset to Out TRCO_AEMPTY Reset to almost empty AEMPTY Time after reset that the Almost Empty signal is output stable at the ALMOSTEMPTY outputs of the FIFO TRCO_AFULL Reset to almost full AFULL Time after reset that the Almost Full signal is stable output at the ALMOSTFULL outputs of the FIFO TRCO_EMPTY Reset to empty output EMPTY Time after reset that the Empty signal is stable at the EMPTY outputs of the FIFO TRCO FULL Reset to full output FULL Time after reset that the Full signal is stable at the FULL outputs of the FIFO TRCO_RDERR Reset to read error RDERR Time after reset that the Read error signal is stable output at the RDERR outputs of the FIFO TRCO_WRERR Reset to write error WRERR Time after reset that the Write error signal is stable output at the WRERR outputs of the FIFO Tnco RDCOUNT Reset to read pointer RDCOUNT Time after reset that the Read pointer signal is output s
169. Output Description IBUFG I O Input clock buffer for single ended I O IBUFGDS I IB O Input clock buffer for differential I O These two primitives work in conjunction with the Virtex 5 I O resource by setting the IOSTANDARD attribute to the desired standard Refer to Chapter 6 I O Compatibility Table 6 39 for a complete list of possible I O standards Clock Gating for Power Savings The Virtex 5 clock architecture provides a straightforward means of implementing clock gating for the purposes of powering down portions of a design Most designs contain several unused BUFGCE resources A clock can drive a BUFGCE input and a BUFGCE output can drive distinct regions of logic For example if all the logic that is required to always be operating is constrained to a few clocking regions then the BUFGCE output can drive those regions Toggling the enable of the BUFGCE provides a simple means of stopping all dynamic power consumption in the logic regions available for power savings The Xilinx Power Estimator XPE or the Xilinx Power Analyzer XPower tools are used to estimate power savings The difference is calculated by setting the frequency on the corresponding clock net to 0 MHz or providing the appropriate stimulus data to the tool www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Global Clocking Resources Global Clock Buffers There are 32 global clock buffers in every Virtex 5 device
170. P 7 0 PA PB PC shortly after T2R T3R T4R e SBITERR lines up with the corresponding DO DOP data The ECC decoder also corrects single bit error in parity bits Using the ECC Decode Only to Inject Double Bit Error e Attime TIW T2W T3W DI 63 0 A B C with double bit error and DIP 7 0 PA hex PB hex PB hex the corresponding ECC parity bits for A B and C are written into memory location a b and c e At time TIR T2R T3R the original contents of address a b and c are read out and a double bit error is detected e Latch mode DO 63 0 A B C with double bit error DOP 7 0 PA PB PC shortly after TIR T2R T3R e Register mode DO 63 0 A B C with double bit error DOP 7 0 PA PB PC shortly after T2R T3R T4R e DBITERR lines up with the corresponding DO DOP data The ECC decoder also detects when double bit error in parity bits occurs and when a single bit error in the data bits and a single bit error in the corresponding parity bits Occurs 166 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Built in Error Correction ECC Timing Characteristics The various ECC timing parameters are also shown in Figure 4 31 and Figure 4 32 Since write clock and read clock are independent of each other all write timing in Figure 4 31 is referenced to WRCLK All read timing in Figure 4 32 is referenced to RDCLK Standard ECC Write Timing Figure 4 31 e At time
171. PGA User Guide UG190 v4 4 December 2 2008 www xilinx com 95 Chapter 3 Phase Locked Loops PLLs Table 3 4 PLL Attributes Continued XILINX Attribute CLKFBOUT_PHASE Type Real Allowed Values 0 0 to 360 0 Default 0 0 Description Specifies the phase offset in degrees of the clock feedback output Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL REF JITTER Real 0 000 to 0 999 0 100 Allows specification of the expected jitter on the reference clock in order to better optimize PLL performance A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown If known then the value provided should be specified in terms of the UI percentage the maximum peak to peak value of the expected jitter on the input clock CLKIN1 PERIOD Real 1 408 to 52 630 0 000 Specifies the input period in ns to the PLL CLKINI input Resolution is down to the ps This information is mandatory and must be supplied CLKIN2_PERIOD Real 1 408 to 52 630 0 000 Specifies the input period in ns to the PLL CLKIN2 input Resolution is down to the ps This information is mandatory and must be supplied CLKOUT 0 5 DESKEW ADJUST String PPC or None None Fixed delay used when the PLL is used in a PPC440 system See UG200 Embedded Processor Block in Virtex 5 FPGAs Reference Guid
172. PHASE SHIFT attribute range e FINE SHIFT RANGE DCM timing parameter range www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Design Guidelines In the FIXED VARIABLE_POSITIVE and VARIABLE_CENTER phase shift mode the PHASE_SHIFT attribute is in the numerator of the following equation Phase Shift ns PHASE_SHIFT 256 x PERIODCLKIN Where PERIOD xiv denotes the effective CLKIN frequency In VARIABLE CENTER and FIXED modes the full range of the PHASE SHIFT attribute is always 255 to 255 In the VARIABLE POSITIVE mode the range of the PHASE SHIFT attribute is 0 to 255 In the DIRECT phase shift mode the PHASE SHIFT attribute is the multiplication factor in the following equation Phase Shift ns PHASE SHIFT x DCM_TAP In DIRECT modes the full range of the PHASE SHIFT attribute is 0 to 1023 FINE SHIFT RANGE represents the total delay achievable by the phase shift delay line Total delay is a function of the number of delay taps used in the circuit The absolute range is specified in the DCM Timing Parameters section of the Virtex 5 FPGA Data Sheet across process voltage and temperature The different absolute ranges are outlined in this section The fixed mode allows the DCM to insert a delay line in the CLKFB or the CLKIN path This gives access to the FINE SHIFT RANGE when the PHASE SHIFT attribute is set to a positive value and CFINE SHIFT RANGE when the PHASE SHIFT attribute
173. RDCLK period later Case 2 Writing to a Full or Almost Full FIFO Prior to the operations performed in Figure 4 22 the FIFO is almost completely full In this example the timing diagram reflects of both standard and FWFT modes 1 2 3 4 gt TFCCK_WREN TFCCK_WREN WREN Trpck DI TFpcK D os TFDCK DI DI Co 7X jp X 0 X 0o 5X j KX j5 X po RDCLK l l l l l l l l RDEN TECKO_FULL l l FULL i AFULL TFCKO_WERR e TrFcko wERR k WRERR Ie TrFCKO AFULL l ug190_4_18_012605 Figure 4 22 Writing to a Full Almost Full FIFO Virtex 5 FPGA User Guide www xilinx com 151 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Clock Event 1 Write Operation and Assertion of Almost FULL Signal During a write operation to an almost full FIFO the Almost FULL signal is asserted e At time Tppcy pr before clock event 1 WRCLK data 00 becomes valid at the DI inputs of the FIFO e At time Trcck wren before clock event 1 WRCLK write enable becomes valid at the WREN input of the FIFO e At time Trcko ArurL one clock cycle after clock event 1 WRCLK Almost Full is asserted at the AFULL output pin of the FIFO Clock Event 2 Write Operation and Assertion of FULL Signal The FULL signal pin is asserted when the FIFO is full e At time Tppcy pr before clock event 2 WRCLK data 04 becomes valid at the DI i
174. RL can drive any DCM in the Virtex 5 device using dedicated global routing A BUFGCTRL can drive the DCM CLKIN pin when used to connect two DCMs in series 3 PLL Phase Locked Loop A PLL block within the same CMT can drive the CLKIN input of either DCM in the CMT block No global buffer is required in between See Application Examples page 71 for more information 4 IBUF Input Buffer When an IBUF drives the CLKIN input the PAD to DCM input skew is not compensated Virtex 5 FPGA User Guide www xilinx com 47 UG190 v4 4 December 2 2008 48 Chapter 2 Clock Management Technology XILINX Feedback Clock Input CLKFB The feedback clock CLKFB input pin provides a reference or feedback signal to the DCM to delay compensate the clock outputs and align them with the clock input To provide the necessary feedback to the DCM connect only the CLK0 DCM output to the CLKFB pin When the CLKFB pin is connected all clock outputs are deskewed to CLKIN When the CLKFB pin is not connected DCM clock outputs are not deskewed to CLKIN However the relative phase relationship between all output clocks is preserved During internal feedback configuration the CLKO output of a DCM connects to a global buffer on the same top or bottom half of the device The output of the global buffer connects to the CLKFB input of the same DCM During the external feedback configuration the following rules apply 1 To forward the clock the CLKO of
175. RRY4 block diagram Port Signals Sum Outputs O 3 0 The sum outputs provide the final result of the addition subtraction Carry Outputs CO 3 0 The carry outputs provide the carry out for each bit A longer carry chain can be created if COJ3 is connected to CI input of another CARRY4 primitive Data Inputs DI 3 0 The data inputs are used as generate signals to the carry lookahead logic The generate signals are sourced from LUT outputs Select Inputs S 3 0 The select inputs are used as propagate signals to the carry lookahead logic The propagate signals are sourced from LUT outputs Carry Initialize CYINIT The carry initialize input is used to select the first bit in a carry chain The value for this pin is either 0 for add 1 for subtract or AX input for the dynamic first carry bit Carry In Cl The carry in input is used to cascade slices to form longer carry chain To create a longer carry chain the CO 3 output of another CARRY4 is simply connected to this pin www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 7 XILINX Chapter 6 SelectIO Resources l O Tile Overview Input output characteristics and logic resources are covered in three consecutive chapters Chapter 6 SelectIO Resources describes the electrical behavior of the output drivers and input receivers and gives detailed examples of many standard interfaces Chapter 7 Select
176. Read and Write Port Width Selection 0000 118 Simple Dual Port Block RAM 0 6 66 cc III 119 Cascadable Block RAM 0 eee tenet n 120 Byt wide Write Enable 0 92 cege esee ee ebbe I er eI ane e ses 120 Block RAM Error Correction Code 0 0 cc ccc ccc cnet ete eens 121 Block RAM Library Primitives 00 0000 ccc eee eee 121 Block RAM Port Siphals s i eesuuet edema Ra reduces erro dete videri toe ban 123 Clock CEK A B 4 eR REC RE ERECU E RR DER ESI ER 123 Enable EN A B y rex Eye ry me YN Oa ey seal 123 Byte wide Write Enable WE A B sssseeeeeeseee I 123 Register Enable REGCE A B ssssssssseee e 123 Set Reset SSR A B 00 cece e e 123 Address Bus ADDR A B 13 82 14 44 15355 sess 124 Data In Buses DI A B lt 0 gt amp DIP A B lt 0 gt 0 eee eee 124 Data Out Buses DO A B lt 0 gt and DOP A B lt 0 gt 0000000 125 Cascade In CASCADEINLAT A B and CASCADEINREG A B 125 Cascade Out CASCADEOUTLATT A B and CASCADEOUTREG A B 125 Inverting Control Pins s teca eterne ertet Rae etae E oeste gi ad Uds 125 GSR eeter epena aeae E ana a aa e aa a e a a ea aa ea ea 126 Unused Ta ats care Se geste ee ae hn E pa E na iiec T 126 Block RAM Address Mapping 0 00 0 e cece cece eee 126 Block RAM Attributes 0 000 000 RII 126 Content Initialization INI
177. SED FAST SLOW FAST SLOW LVDCI Low Voltage Digitally Controlled Impedance Using these I O buffers configures the outputs as controlled impedance drivers The receiver of LVDCI is identical to a LVCMOS receiver Some I O standards such as LVTTL LVCMOS etc must have a drive impedance that matches the characteristic impedance of the driven line Virtex 5 devices provide a controlled impedance output driver to provide series termination without external source termination resistors The impedance is set by the common external reference resistors with resistance equal to the trace characteristic impedance Zp Sample circuits illustrating both unidirectional and bidirectional termination techniques for a controlled impedance driver are shown in Figure 6 30 and Figure 6 31 The DCI I O standards supporting a controlled impedance driver are LVDCI 15 LVDCI 18 LVDCI 25 and LVDCI 33 IOB l TOB LVDCI bt Ro Rynw Rynp Zo ug190_6_28 022806 Figure 6 30 Controlled Impedance Driver with Unidirectional Termination IOB 10B LVDCI LVDCI X lt t _Q _ 4 _X Ro Rygw RyppP Zo Ro Rygw Ryrp Zo ug190_6_29 022806 Figure 6 31 Controlled Impedance Driver with Bidirectional Termination Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 240 www xilinx com XILINX Specific Guidelines for I O Supported Standards
178. Single GTLP 1 N R N R N R Note 2 GTL 0 8 N R N R LVCMOS12 N R N R N R HSTL I 12 ia 0 6 N R N R Notes 1 See 3 3V I O Design Guidelines for more detailed information 2 3 4 5 298 Differential inputs and inputs using Vpggpg are powered from VccAux However pin voltage must not exceed Veco due to the presence of clamp diodes to Veco N R no requirement RSDS 25 has the same DC specifications as LVDS 25 All information pertaining to LVDS 25 is applicable to RSDS 25 I O standard is selected using the IOSTANDARD attribute www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Rules for Combining I O Standards in the Same Bank 3 3V I O Design Guidelines To achieve maximum performance in Virtex 5 devices several 3 3V I O design guidelines and techniques are highlighted in this section This includes managing overshoot undershoot with termination techniques regulating Vcco at 3 0V with a voltage regulator using external bus switches reviewing configuration methods and other design considerations I O Standard Design Rules Overshoot Undershoot Undershoot and overshoot voltages on I Os operating at 3 3V should not exceed the absolute maximum ratings of 0 3V to 4 05V respectively when Vcco is 3 75V These absolute maximum limits are stated in the absolute maximum ratings table in the Virtex 5 FPGA Data Sheet However the maximum undershoot value is directly affected b
179. T DCI SSTL2 II T DCI HSTL II T DCI 18 SSTLI18 II T DCI To correctly use DCI in a Virtex 5 device users must follow the following rules 1 Veco pins must be connected to the appropriate Vcco voltage based on the IOSTANDARDs in that bank 2 Correct DCI I O buffers must be used in the software either by using IOSTANDARD attributes or instantiations in the HDL code Virtex 5 FPGA User Guide www xilinx com 227 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX 3 Some DCI standards require connecting the external reference resistors to the multipurpose pins VRN and VRP in the bank Where this is required these two multipurpose pins cannot be used as general purpose I O Refer to the Virtex 5 FPGA pinout tables for the specific pin locations Pin VRN must be pulled up to Veco by its reference resistor Pin VRP must be pulled down to ground by its reference resistor Some DCI standards do not require connecting the external reference resistors to the VRP VRN pins When these DCI based I O standards are the only ones in a bank the the VRP and VRN pins in that bank can be used as general purpose I O DCI outputs that do not require reference resistors on VRP VRN HSTL I DCI HSTL III DCI HSTL I DCI 18 HSTL III DCI 18 SSTI2 I DCI SSTL18_I_DCI DCI inputs that do not require reference resistors on VRP VRN LVDCI 15 LVDCI 18 LVDCI 25 LVDCI 33 LVDCI DV2 15 LVDCI DV2 1
180. T PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2006 2008 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries PCI PCI Express PCle and PCI X are trademarks of PCI SIG The PowerPC name and logo are registered trademarks of IBM Corp and used under license All other trademarks are the property of their respective owners Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 Revision History The following table shows the revision history for this document Date Version Revision 04 14 06 1 0 Initial Xilinx release 05 12 06 1 1 Minor typographical edits and clarifications Chapter 1 Revised Figure 1 21 Chapter 2 Revised Figure 2 2 and Figure 2 4 Removed reference to a DCM_PS primitive Removed outdated clocking wizard section page 79 Chapter 3 Revised Figure 3 1 Figure 3 2 Table 3 2 Table 3 4 Figure 3 9 Equation 3 8 and Figure 3 12 Added PLL in Virtex 4 FPGA PMCD Legacy Mode section Chapter 4 Added a note to Table 4 5 page 122 Clarified the RAMB36 port mapping design rules on page 130 Chapter 5 Added Figure 5 7 and Figure 5 11 revised Figure 5 32 for clarity Chapter 6 Updated Simultaneous Switching Output Limits section Chapter 7 Revised ILOGIC Resources page 314 including Figure 7 1 Revised Table 7 3 Chapter 8 Revised Table 8 1 7 19 06 1 2 C
181. T l I l l O6 l I l SEL D 1 0 DATA D 3 0 ML A 6 1 F7BMUX Input I l l J l I l I LUT I I O6 I lee l SEL C 1 0 DATA C 3 0 __ C 6 1 6 A 6 1 Input i F8MUX i I l CX BMUX 16 1 MUX I SELF7 F pdt I LUT l I B j Registered I O6 Output I SEL B 1 0 DATA B 3 0 BI6 1 l il ut a ed A 6 1 F7AMUX Optional I l I I L l I ME l I l I 06 l SEL A 1 0 DATA A 3 0 A 6 1 6 Input Al6 1 i I 1 AX SELF7 secre 9 l CLK l CLK l E E a H ne J Uci90_5 23 050506 Figure 5 23 16 1 Multiplexer in a Slice It is possible to create multiplexers wider than 16 1 across more than one SLICEM However there are no direct connections between slices to form these wide multiplexers Fast Lookahead Carry Logic In addition to function generators dedicated carry logic is provided to perform fast arithmetic addition and subtraction in a slice A Virtex 5 FPGA CLB has two separate carry chains as shown in Figure 5 1 The carry chains are cascadable to form wider add subtract logic as shown in Figure 5 2 The carry chain in the Virtex 5 device is running upward and has a height of four bits per slice For each bit there is a carry multiplexer MUXCY and a dedicated XOR gate for adding subtracting the operands with a selected carry bits The dedicated carry path and www xilinx com Virtex 5 FPGA User Guide UG
182. TBccko o NET BUFGCTRL Clock O gt Tiopi NET E Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 137 Chapter 4 Block RAM XILINX Block RAM Retargeting Table 4 12 suggests the most appropriate primitives to choose when mapping a Virtex 4 FPGA block RAM design in a new Virtex 5 FPGA design Table 4 12 Block RAM Retargeting Virtex 4 Block RAM 18k Virtex 5 Block RAM 36k Virtex 5 Block RAM Port Width Port Width T Port Width Primitive Depth R W Primitive Depth R W Primitive Depth R W RAMB16 1kto 1 2 4 9 18 RAMB18 1kto 1 2 4 9 18 RAMB36 2kto 1 2 4 9 18 True dual port 16k 16k 32k RAMB16 512 36 36 N A N A N A RAMB36 1k 36 36 True dual port RAMB16 512 36 36 RAMB18 512 36 36 RAMB36 1k 36 36 Simple dual port Simple dual Simple dual port port RAMB16 Variable Use closest N A N A Use closest N A N A Simple dual port RAMB18 True RAMB36 True dual port dual port CASC of two 32k 1 N A N A N A RAMB36 32k 1 RAMB16s Built in FIFO Support Many FPGA designs use block RAMs to implement FIFOs In the Virtex 5 architecture dedicated logic in the block RAM enables users to easily implement synchronous or multirate asynchronous FIFOs This eliminates the need for additional CLB logic for counter comparator or status flag generation and uses just one block RAM resource per FIFO Both standard and first word fall through FWFT modes are suppor
183. TL II 18 HSTL_IV_18 0 0 0 cece eee 247 HSTL II DCI HSTL IV DCI HSTL II DCI 18 HSTL IV DCI 18 248 HSTL II T DCI HSTL II T DCI 18 esseeeeee e 248 DIFF HST M DIFE HSTE T 18 eeRRERR RR ER Reg eene 248 DIFF HSTL II DCI DIFF_HSTL_II_DCI18 0 0 ccc cece eee eee 248 DIFF LHS Ti DERE HSTET 18 242 rr rer eu e eee 248 DIFF HSTL I DCI DIFF HSTL I DCI 18 eeeeeeee e 248 IG EINE GIECCT IPTE 249 Differential HSTL ClassI 0 0 ccc ccc ccc nnn n eens 250 FAST Es CVASS E PEEL 251 Differential HSTL Class ID 0 ccc cece eee enn a 253 AS TEs Class TUT eea EREEREER E EERE EEEE EEEIEE EAE RAT RRA 256 HOTL Class IV erri re EEEE ak eA E tae PC Ede eade 257 HSTL II T DCI 1 5V Split Thevenin Termination 0 0000008 259 HSTL Class T 1 8V ase eka eb re pane ep Pa dece d qu eco qe ag 260 Ditterential JHSTL Class I 18V s i eicere eg e Eee ete me tee eni d 261 HSTL Class IE 18V sis teet n E rrr bs re ee e Ie oe dado e dede 262 Differential HSTL Class IL 1 8V 2 0 2 eee eee II 264 HSTL Class II 1 8V si 3i ea iat Pea aii dai lei id 267 FISTE Glass IV 18V i ot ae Rete aane be tl ehe eee hern estet eret Places 268 HSTL II T DCI 18 1 8V Split Thevenin Termination isses 270 FAST Class D 1 2M ucc ic E ec P rece ee dete a eie ier enhn 271 SSTL Stub Series Terminated Logic 0 e eee eee eee eee ee 271 SSTE2 D SSTEIS E d ndr Pur el
184. TL compatible 25 Q or 20 Q series resistor is accounted for in the DCI buffer and it is not DCI controlled 2 Zg is the recommended PCB trace impedance ug190 6 15 041106 Figure 6 17 SSTL DCI Usage Examples 230 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA SelectlO Primitives Virtex 5 FPGA SelectlO Primitives The Xilinx software library includes an extensive list of primitives to support a variety of I O standards available in the Virtex 5 FPGA I O primitives The following are five generic primitive names representing most of the available single ended I O standards IBUF input buffer IBUFG clock input buffer OBUF output buffer OBUFT 3 state output buffer IOBUF input output buffer These five generic primitive names represent most of the available differential I O standards IBUFDS input buffer IBUFGDS clock input buffer OBUFDS output buffer OBUFTDS 3 state output buffer IOBUFDS input output buffer IBUF and IBUFG Signals used as inputs to Virtex 5 devices must use an input buffer IBUF The generic Virtex 5 FPGA IBUF primitive is shown in Figure 6 18 IBUF IBUFG Input O Output From device pad into FPGA ug190_6_16_022806 Figure 6 18 Input Buffer IBUF IBUFG Primitives The IBUF and IBUFG primitives are the same IBUFGs are used when an input buffer is used as a clock input In the Xilinx software tools an IBUFG is auto
185. T_xx 0 cc RR RR eens 126 Content Initialization INITP_xx 0 0 0 ccc RR RR n 127 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Latches Initialization INIT INIT A or INIT B sssseeeeeeeee 128 Output Latches Registers Synchronous Set Reset SRVAL A B 128 Optional Output Register On Off Switch DO A B _REG 8 128 Extended Mode Address Determinant RAM_EXTENSION_ A B 128 Read Width READ_WIDTH_ A B 0 eee cece eee eee eens 128 Write Width WRITE_WIDTH_ A B 0c cece RR RR 128 Write Mode WRITE MODE A B 0 0 cece RR IIIA 129 Block RAM Location Constraints sese eh 129 Block RAM Initialization in VHDL or Verilog Code 129 Additional RAMB18 and RAMB36 Primitive Design Considerations 129 Optional Output Registers 0 00 129 Independent Read and Write Port Width 00 0 cece eee eee eee 130 RAMB18 and RAMB36 Port Mapping Design Rules 000 000 130 Cascadeable Block RAM ssseeeeeee RR RII RR e 130 Byte wide Write Enable serii 0 0 0 occ eee 131 Additional Block RAM Primitives sese 131 Block RAM Applications 013 2 dais kate ue I bar RR LEA a E a 131 Creating Larger RAM Structures 0 0 cece nen 131 Block RAM SSR in Register Mode 00 cece eee eee ee 131 Block RAM Timin
186. The DCM ADV primitive has access to all DCM features and ports available in DCM BASE plus additional ports for the dynamic reconfiguration feature It is a superset of the DCM BASE primitive DCM ADV uses all the DCM features including clock deskew frequency synthesis fixed or variable phase shifting and dynamic reconfiguration Table 2 3 lists the available ports in the DCM ADV primitive Table 2 3 DCM ADV Primitive Available Ports Port Names Clock Input CLKIN CLKFB PSCLK DCLK Control and Data Input RST PSINCDEC PSEN DADDR 6 0 DI 15 0 DWE DEN Clock Output CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Status and Data Output LOCKED PSDONE DO 15 0 DRDY DCM Ports There are four types of DCM ports available in the Virtex 5 architecture e DCM Clock Input Ports e DCM Control and Data Input Ports e DCM Clock Output Ports e DCM Status and Data Output Ports DCM Clock Input Ports Source Clock Input CLKIN The source clock CLKIN input pin provides the source clock to the DCM The CLKIN frequency must fall in the ranges specified in the Virtex 5 FPGA Data Sheet The clock input signal comes from one of the following buffers 1 IBUFG Global Clock Input Buffer The DCM compensates for the clock input path when CLKFB is connected and an IBUFG on the same half top or bottom of the device as the DCM is used 2 BUFGCTRL Internal Global Clock Buffer Any BUFGCT
187. Timing Characteristics OPPOSITE EDGE Mode Clock Event 1 e Attime Tjcgicy before Clock Event 1 the input clock enable signal becomes valid high at the CE1 input of both of the DDR input registers enabling them for incoming data Since the CE1 and D signals are common to both DDR registers care must be taken to toggle these signals between the rising edges and falling edges of CLK as well as meeting the register setup time relative to both clocks e Attime Tjypocy before Clock Event 1 rising edge of CLK the input signal becomes valid high at the D input of both registers and is reflected on the O1 output of input register 1 at time TickQ after Clock Event 1 Virtex 5 FPGA User Guide www xilinx com 319 UG190 v4 4 December 2 2008 320 Chapter 7 SelectlO Logic Resources XILINX Clock Event 2 e Attime T pocx before Clock Event 2 falling edge of CLK the input signal becomes valid low at the D input of both registers and is reflected on the Q2 output of input register 2 at time Tyco after Clock Event 2 no change in this case Clock Event 9 e At time T sgcg before Clock Event 9 the SR signal configured as synchronous reset in this case becomes valid high resetting O1 at time Tjcxg after Clock Event 9 and Q2 at time Ticko after Clock Event 10 Table 7 5 describes the function and control signals of the ILOGIC switching characteristics in the Virtex 5 FPGA Data Sheet Table 7 5 LOGIC Switching Characteristics
188. V 0 2 0 8 Vou 2 4 VoL 04 Iou at Voy mA Note 2 Ior at Vor mA Note 2 Notes 1 Voz and Voy for lower drive currents are sample tested 2 Supported DRIVE strengths are 2 4 6 8 12 16 and 24 mA Virtex 5 FPGA User Guide www xilinx com 237 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 5 details the allowed attributes that can be applied to the LVTTL I O standard Table 6 5 Allowed Attributes for the LVTTL I O Standard Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVTTL LVTTL LVTTL DRIVE UNUSED 2 4 6 8 12 16 24 2 4 6 8 12 16 24 SLEW UNUSED FAST SLOW FAST SLOW LVCMOS Low Voltage Complementary Metal Oxide Semiconductor LVCMOS is a widely used switching standard implemented in CMOS transistors This standard is defined by JEDEC JESD 8 5 The LVCMOS standards supported in Virtex 5 FPGAs are LVCMOS12 LVCMOS15 LVCMOS18 LVCMOS25 and LVCMOS33 Sample circuits illustrating both unidirectional and bidirectional LVCMOS termination techniques are shown in Figure 6 28 and Figure 6 29 IOB IOB LVCMOS LVCMOS Rs Zg Rp gt M m gt TUUS IOB VT oa LVCMOS LVCMOS Note V is any voltage from OV to Voc ug190 6 26 022806 Figure 6 28 LVCMOS Unidirectional Termination 238 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX
189. V Split Thevenin Termination Virtex 5 FPGA User Guide www xilinx com 281 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX SSTL18 Class 1 8V Figure 6 76 shows a sample circuit illustrating a valid termination technique for SSTL Class I 1 8V External Termination ar Vr 0 9V IOB SSTL18 I a SSTL18 I Rg 200 B3 Q2 X Vper 0 9V IOB IOB Veco 1 8V 2Rypp 2Zg 1000 SSTL18 DCI SSTL18 DCI 52 03 51 Vper 0 9V Ro 220 BEP 2Rypy 2Zg 1002 LE is ug190_6_72_030506 Figure 6 76 SSTL18 1 8V Class I Termination 282 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Differential SSTL Class 1 8V Figure 6 77 shows a sample circuit illustrating a valid termination technique for differential SSTL Class I 1 8V with unidirectional termination External Termination Vr 0 9V IOB IOB DIFF SSTL18 502 DIFF SSTL18 I DIFF SSTL18 I ugi 90 6 73 030506 Figure 6 77 Differential SSTL 1 8V Class I Unidirectional Termination Figure 6 78 shows a sample circuit illustrating a valid termination technique for differential SSTL Class I 1 8V with unidirectional DCI termination DCI IOB 10B DIFF SSTL18 DCI l 2Rypp 2Zg 1002 l Kaoz 2Rypy 2Zo 1002 DI
190. Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LOS
191. Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Additional Block RAM Primitives Byte wide Write Enable The following rules should be considered when using the byte wide write enable feature e Inx36 mode WE 3 0 is connected to the four user WE inputs e Inx18 mode WE 0 and WE 2 are connected and driven by the user WE 0 while WE 1 and WE 3 are driven by the user WE 1 e Inx9 x4 x2 x1 WE 3 0 are all connected to a single user WE e Inx72simple dual port mode WE 7 0 is connected to the eight user WE inputs Additional Block RAM Primitives In addition to RAMB18 and RAMB36 there are other block RAM primitives available for specific implementations RAMB18SDP and RAMB36SDP implement the simple dual port mode configurations of the block RAM Figure 4 3 page 119 shows the ports available for the 18 Kb block RAM configured in simple dual port mode The RAMB36SDP can also be configured for the built in block RAM ECC For more information on RAMB36SDP with the ECC feature see Built in Error Correction page 157 Block RAM Applications Creating Larger RAM Structures Block RAM columns have special routing to create wider deeper blocks using 36 Kb block RAMs with minimal routing delays Wider or deeper RAM structures are achieved with a smaller timing penalty than is encountered when using normal routing resources The Xilinx CORE Generator program offers the designer an easy way to generate wi
192. Virtex 5 FPGA User Guide www xilinx com 89 UG190 v4 4 December 2 2008 90 Chapter 3 Phase Locked Loops PLLs XILINX PLL ADV Primitive The PLL_ADV primitive provides access to all PLL BASE features plus additional ports for clock switching connectivity to DCMs in the same CMT and access to the Dynamic Reconfiguration Port DRP The ports are listed in Table 3 2 Table 3 2 PLL ADV Ports Description Port Clock Input CLKIN1 CLKIN2 CLKFBIN DCLK Control and Data Input RST CLKINSEL DWE DEN DADDR DI REL Clock Output CLKOUTO to CLKOUT5 CLKFBOUT CLKOUTDCM0 to CLKOUTDCM5 CLKFBDCM Status and Data Output LOCKED DO DRDY Notes 1 REL is used in PMCD mode only In PLL mode leave REL unconnected or tied Low The Virtex 5 FPGA PLL is a mixed signal block designed to support clock network deskew frequency synthesis and jitter reduction These three modes of operation are discussed in more detail within this section The Voltage Controlled Oscillator VCO operating frequency can be determined by using the following relationship M Fvco Ferxm D Equation 3 1 M ion 3 Four Panem T Equation 3 2 where the M D and O counters are shown in Figure 3 3 The six O counters can be independently programmed For example O0 can be programmed to do a divide by two while O1 is programmed for a divide by three The only constraint is that the VCO operating frequency must be the same for a
193. a enters the OSERDES module through ports D1 to D6 These ports are connected to the FPGA fabric and can be configured from two to six bits i e a 6 1 serialization Bit widths greater than six up to 10 can be supported by using a second OSERDES in SLAVE mode See OSERDES Width Expansion Refer to Figure 8 3 page 352 for bit ordering at the inputs and output of the OSERDES along with the corresponding bit order of the ISERDES_NODELAY Output Data Clock Enable OCE OCE is an active High clock enable for the data path Parallel 3 state Inputs T1 to T4 All parallel 3 state signals enter the OSERDES module through ports T1 to T4 The ports are connected to the FPGA fabric and can be configured as one two or four bits 3 state Signal Clock Enable TCE TCE is an active High clock enable for the 3 state control path Reset Input SR The reset input causes the outputs of all data flip flops in the CLK and CLKDIV domains to be driven Low asynchronously OSERDES circuits running in the CLK domain where timing is critical use an internal dedicated circuit to retime the SR input to produce a reset signal synchronous to the CLK domain Similarly there is a dedicated circuit to retime the SR input to produce a reset signal synchronous to the CLKDIV domain Because there are OSERDES circuits that retime the SR input the user is only required to provide a reset pulse to the SR input that meets timing on the CLKDIV frequency domain
194. a stream See High Speed Clock Input CLK CLKB Input 1 High speed secondary clock input Clocks serial input data stream Always connect this CLK CLKDIV Input 1 Divided clock input Clocks delay element deserialized data Bitslip submodule and CE unit See Divided Clock Input CLKDIV D Input 1 Serial input data from IOB See Serial Input Data from IOB D OCLK Input 1 High speed clock input for memory applications See High Speed Clock for Strobe Based Memory Interfaces OCLK SHIFTIN1 Input 1 Carry input for data width expansion Connect to SHIFTOUT1 of master IOB See ISERDES Width Expansion SHIFTIN2 Input 1 Carry input for data width expansion Connect to SHIFTOUT2 of master IOB See ISERDES Width Expansion RST Input 1 Active High reset See Reset Input RST ISERDES NODELAY Ports Virtex 5 FPGA User Guide Registered Outputs Q1 to Q6 The output ports Q1 to Q6 are the registered outputs of the ISERDES NODELAY module One ISERDES NODELAY block can support up to six bits i e a 1 6 deserialization Bit widths greater than six up to 10 can be supported See ISERDES Width Expansion The first data bit received appears on the highest order Q output The bit ordering at the input of an OSERDES is the opposite of the bit ordering at the output of an ISERDES NODELAY block as shown in Figure 8 3 For example the least significant bit A of the word FEDCBA is placed at t
195. ack path and delay inserted in the reference path original clock LL dT feedback added delay in feedback path dT reference added delay in reference path ug190 03 07 032506 Figure 83 7 Basic Output Clock Shifting Detailed VCO and Output Counter Waveforms Figure 3 8 shows the eight VCO phase outputs and four different counter outputs Each VCO phase is shown with the appropriate start up sequence The phase relationship and start up sequence are guaranteed to insure the correct phase is maintained This means the rising edge of the 0 phase will happen before the rising edge of the 45 phase The O0 counter is programmed to do a simple divide by two with the 0 phase tap as the reference clock The O1 counter is programmed to do a simple divide by two but uses the 180 phase tap from the VCO Phase shifts greater than one VCO period are possible This counter setting could be used to generate a clock for a DDR interface where the reference clock is edge aligned to the data transition The O2 counter is programmed to do a divide by three The O3 output has the same programming as the O2 output except the phase is set for a one cycle delay If the PLL is configured to provide a certain phase relationship and the input frequency is changed then this phase relationship is also changed since the VCO frequency changes and therefore the absolute shift in picoseconds will change This aspect must be considered when designing with
196. ad When the electrical characteristics of a design differ from the nominal values the system SSO limit changes The degree of difference determines the new effective limit for the design A figure called SSO Allowance is used as a single derating factor taking into account the combined effect of all three groups of system electrical characteristics The SSO allowance is a number ranging from 0 to 100 and is a product of three scaling factors The First Scaling Factor accounts for the PCB PDS parasitic inductance It is determined by dividing the nominal PCB PDS inductance by the user s PCB PDS inductance Lpps_ysr The PCB PDS inductance is determined based on a set of board geometries board thickness via diameter breakout trace width and length and any other additional structures including sockets The Second Scaling Factor accounts for the maximum allowable power system disturbance It is determined by dividing the user s maximum allowable power system disturbance VpISTURBANCE USER by the nominal maximum power system disturbance VDISTURBANCE USER S usually determined by taking the lesser of input undershoot voltage and input logic low threshold The Third Scaling Factor accounts for the capacitive loading of outputs driven by the FPGA Itis based on the transient current impact of every additional picofarad of load capacitance above the assumed nominal For every additional 1 pF of load capacitance over the nominal ap
197. al Signaling RSDS is similar to an LVDS high speed interface using differential signaling RSDS has a similar implementation to LVDS in Virtex 5 devices and is only intended for point to point applications Table 6 38 Allowed Attributes of the RSDS I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOSTANDARD RSDS 25 DIFF TERM TRUE FALSE N A BLVDS Bus LVDS Since LVDS is intended for point to point applications BLVDS is not an EIA TIA standard implementation and requires careful adaptation of I O and PCB layout design rules The primitive supplied in the software library for bidirectional LVDS does not use the Virtex 5 FPGA LVDS current mode driver instead it uses complementary single ended differential drivers Therefore source termination is required Figure 6 88 shows the BLVDS transmitter termination BLVDS 25 IOB 10B yop sere l 1 Rs Zo 509 IN qw BLVDS_25 1650 BLVDS 25 Riv 140 Data in I Rg I Dj 1650 i T INX l DH ee ee l ug190_6_83_030506 Figure 6 88 BLVDS Transmitter Termination Virtex 5 FPGA User Guide www xilinx com 293 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Differential LYPECL Low Voltage Positive Emitter Coupled Logic LVPECL is a very popular and powerful high speed interface in many system applications Virtex 5 FPGA I Os are designed to comply with the FIA TIA electr
198. al port mode independent Read and Write operations can occur simultaneously where port A is designated as the Read port and port B as the Write port When the Read and Write port access the same data location at the same time it is treated as a collision similar to the port collision in true dual port mode Readback through the configuration port is not supported in simple dual port block RAM mode Figure 4 6 shows the simple dual port data flow 36 Kb Memory Array ug190 4 02 041206 Figure 4 6 Simple Dual Port Data Flow Table 4 3 Simple Dual Port Names and Descriptions Port Names Descriptions DO Data Output Bus DOP Data Output Parity Bus DI Data Input Bus DIP Data Input Parity Bus RDADDR Read Data Address Bus RDCLK Read Data Clock RDEN Read Port Enable REGCE Output Register Clock Enable SSR Synchronous Set Reset WE Byte wide Write Enable WRADDR Write Data Address Bus WRCLK Write Data Clock WREN Write Port Enable Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 119 Chapter 4 Block RAM XILINX Cascadable Block RAM In the Virtex 5 block RAM architecture two 32K x 1 RAMs can be combined to form one 64K x 1 RAM without using local interconnect or additional CLB logic resources Any two adjacent block RAMs can be cascaded to generate a 64K x 1 block RAM Increasing the depth of the block RAM by cascading two block RAMs is available only
199. ameters Available in SLICEM only Figure 5 27 illustrates the details of distributed RAM implemented in a Virtex 5 FPGA slice Some elements of the slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown CI D 6 C input D BX DL BI L5 B input DL 6 AX D gt ALL A input gt UG190 5 27 050506 Figure 5 27 Simplified Virtex 5 FPGA SLICEM Distributed RAM 202 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX Distributed RAM Timing Parameters CLB Slice Timing Models Table 5 8 shows the timing parameters for the distributed RAM in SLICEM for a majority of the paths in Figure 5 27 Table 5 8 Distributed RAM Timing Parameters Parameter Function Description Sequential Delays for a Slice LUT Configured as RAM Distributed RAM Tsucko CLK to A B C D outputs Time after the CLK of a write operation that the data written to the distributed RAM is stable on the A B C D output of the slice Setup and Hold Times for a Slice LUT Configured as RAM Distributed RAM 2 Tps TpgO AX BX CX DX configured as Time before after the clock that data must be data input DI1 stable at the AX BX CX DX input of the slice TACK TCKkA A B C D address inputs Time before after the clock that address signals must be stable at the A B C D
200. and phase shift VCO Operating Range The minimum and maximum VCO operating frequencies are defined in the electrical specification of the Virtex 5 FPGA Data Sheet These values can also be extracted from the speed specification Minimum and Maximum Input Frequency The minimum and maximum CLKIN input frequency are defined in the electrical specification of the Virtex 5 FPGA Data Sheet Duty Cycle Programmability Only discrete duty cycles are possible given a VCO operating frequency The counter settings to determine the output duty cycle is further discussed under Counter Control Virtex 5 FPGA User Guide www xilinx com 91 UG190 v4 4 December 2 2008 92 Chapter 3 Phase Locked Loops PLLs XILINX Phase Shift In many cases there needs to be a phase shift between clocks The phase shift resolution in time units is defined as PS 1 8 Fyco or D 8MFyy since the VCO can provide eight phase shifted clocks at 45 each The higher the VCO frequency the smaller the phase shift resolution Since the VCO has a distinct operating range it is possible to bound the phase shift resolution using from 1 8 Fvco mn to 1 8 Fyco Max Each output counter is individually programmable allowing each counter to have a different phase shift based on the output frequency of the VCO Note Phase shifts other than 45 are possible A finer phase shift resolution depends on the output duty cycle and 0 value Consult the architecture wiz
201. apter 3 Phase Locked Loops PLLs XILINX Table 3 3 PLL Ports Continued Pin Name yo Pin Description The dynamic reconfiguration data input DI bus provides reconfiguration data DI 15 0 Input When not used all bits must be set to zero The dynamic reconfiguration write enable DWE input pin provides the write DWE Input enable control signal to write the DI data into the DADDR address When not used it must be tied Low The dynamic reconfiguration enable DEN provides the enable control signal to DEN Input access the dynamic reconfiguration feature When the dynamic reconfiguration feature is not used DEN must be tied Low DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port The release pin is used when the PLL is in PMCD mode When in PLL mode leave REL Input unconnected or tied Low Only use this pin when porting existing Virtex 4 designs containing the legacy PMCD mode User configurable clock outputs 0 through 5 that can be divided versions of the CLKOUT 0 5 Output VCO phase outputs user controllable from 1 bypassed to 128 The input clock and output clocks are phase aligned CLKFBOUT Output Dedicated PLL feedback output User configurable clocks 0 through 5 that can only connect to the DCM within the Y CLKOUTDCM O0 5 Output same CMT as the PLL PLL feedback used to compensate if the PLL is driving the DCM If the CLKFBOUT
202. ar and powerful high speed interface in many system applications Virtex 5 FPGA I Os are designed to comply with the EIA TIA electrical specifications for LVDS to make system and board design easier With the use of an LVDS current mode driver in the IOBs the need for external source termination in point to point applications is eliminated and with the choice of an extended mode Virtex 5 devices provide the most flexible solution for doing an LVDS design in an FPGA Extended LVDS provides a higher drive capability and voltage swing 350 750 mV making it ideal for long distance or cable LVDS links The output AC characteristics of the LVDS extended mode driver are not within the EIA TIA specifications The LVDS extended mode driver is intended for situations requiring higher drive capabilities to produce an LVDS signal within the EIA TIA specification at the receiver Transmitter Termination The Virtex 5 FPGA LVDS transmitter does not require any external termination Table 6 36 lists the allowed attributes corresponding to the Virtex 5 FPGA LVDS current mode drivers Virtex 5 FPGA LVDS current mode drivers are a true current source and produce the proper EIA TIA compliant LVDS signal Virtex 5 FPGA User Guide www xilinx com 291 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Receiver Termination Figure 6 86 is an example of differential termination for an LVDS receiver on a board with 50 Q transmission lines
203. ard for other phase shift settings PLL Programming Programming of the PLL must follow a set flow to ensure configuration that guarantees stability and performance This section describes how to program the PLL based on certain design requirements A design can be implement in two ways directly through the GUI interface the PLL Wizard or directly implementing the PLL through instantiation Regardless of the method selected the following information is necessary to program the PLL e Reference clock period e Output clock frequencies up to six maximum e Output clock duty cycle default is 50 e Output clock phase shift relative in number of clock cycles relative to the fastest output clock e Desired bandwidth of the PLL default is OPTIMIZED and the bandwidth is chosen in software e Compensation mode automatically determined by the software e Reference clock jitter in UI i e a percentage of the reference clock period Determine the Input Frequency The first step is to determine the input frequency This allows all possible output frequencies to be determined by using the minimum and maximum input frequencies to define the D counter range the VCO operating range to determine the M counter range and the output counter range since it has no restrictions There can be a very large number of frequencies In the worst case there will be 52 x 64 x 128 425 984 possible combinations In reality the total number of different
204. ard or lowering the Vcco to 3 0V is a good approach to address overshoot and undershoot It is also acceptable to combine both methods When Vcco is lowered to 3 0V it is not necessary to adjust the reference resistors VRP and VRN The VRP and VRN values should always be the same as the board trace impedance Virtex 5 FPGA User Guide www xilinx com 301 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Simultaneous Switching Output Limits 302 When multiple output drivers change state at the same time power supply disturbance occurs These disturbances can cause undesired transient behavior in output drivers input receivers or in internal logic These disturbances are often referred to as Simultaneous Switching Output SSO noise The SSO limits govern the number and type of I O output drivers that can be switched simultaneously while maintaining a safe level of SSO noise Sparse Chevron Packages Virtex 5 FPGA packaging utilizes a sparse chevron pinout arrangement The sparse chevron pinout style is an improvement over previous designs offering low crosstalk and SSO noise The pinout is designed to minimize PDS inductance and keep I O signal return current paths very closely coupled to their associated I O signal The maximum ratio of I O to reference pins Vcco and GND in sparse chevron packages is 4 1 For every four I O pins there is always at least one reference pin For boards that do not meet the nomina
205. are also designed for low skew and low power operation Unused branches are disconnected The clock trees also manage the load fanout when all the logic resources are used Regional clock nets do not propagate throughout the whole Virtex 5 device Instead they are limited to only one clock region One clock region contains four independent regional clock nets To access regional clock nets BUFRs must be instantiated A BUFR can drive regional clocks in up to two adjacent clock regions Figure 1 23 BUFRs in the top or bottom region can only access one adjacent region below or above respectively The left side BUFRs can feed the center column I Os ug 90 1 23 012306 Figure 1 23 BUFR Driving Multiple Regions VHDL and Verilog Templates The VHDL and Verilog code for all clocking resource primitives and ISE language templates are available in the Libraries Guide 42 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 7 XILINX Chapter 2 Clock Management Technology Clock Management Summary The Clock Management Tiles CMTs in the Virtex 5 family provide very flexible high performance clocking Each CMT contains two DCMs and one PLL Figure 2 1 shows a simplified view of the center column resources including the CMT block where the DCM is located Each CMT block contains two DCMs and one PLL I O Banks Larger Devices Only CMT Blocks Top Half DCMs PLLs Clock I O Top Half
206. are different Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 287 Chapter 6 SelectlO Resources Differential SSTL Class II 1 8V Figure 6 81 shows a sample circuit illustrating a valid termination technique for differential SSTL Class II 1 8V with unidirectional termination External Termination XILINX V 0 9V Vr 0 9V IOB g IOB DIFF_SSTL18_ll Rg 200 509 500 Pq vw 20 y DIFF SSTL18 II Vr 0 9V Vr 0 9V DIFF SSTL18 II Rg 200 500 500 Dq w Q zo Dj i m ug190_6_77_030506 Figure 6 81 Differential SSTL 1 8V Class II Unidirectional Termination Figure 6 82 shows a sample circuit illustrating a valid termination technique for differential SSTL Class II 1 8V with unidirectional DCI termination DCI IOB DIFF SSTL18 Il DCI 2Rypp 2Zo 1002 2R 2Zp 1000 Ro 200 E VRN 0 Veco 1 8V DIFF SSTL18 Il DCI 2Rypp 2Zo 1002 Ro 200 E 2Rygw 2Zg 1000 e 5 eo 5 eo 10B Veco 18V 2Rypp 2Zo 1000 A 2Rypy 2Zg 1002 Vcco 1 8V 2Rypp 2Zo 1009 DIFF SSTL18 Il DCI Dq 2Rypy 2Zg 1002 ugi90 6 78 030506 Figure 6 82 Differential SSTL 1 8V Class II Unidirectional DCI Termination www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards
207. ass Il with DCI Bidirectional Termination Table 6 31 lists the differential SSTL2 Class II DC voltage specifications Table 6 31 Differential SSTL2 Class Il DC Voltage Specifications Min Typ Max Vcco 2 3 2 5 2 7 Input Parameters VTT Veco X 0 5 Vin DO 0 30 Veco 0 30 Vip DC 2 0 3 Veco 0 60 Vip AC 0 62 Veco 0 60 Vix AC 0 95 1 55 Output Parameters Vox AC 1 0 1 5 Notes 1 Vin DC specifies the allowable DC excursion of each differential input 2 Vip DC specifies the input differential voltage required for switching 3 Vix AC indicates the voltage where the differential input signals must cross 4 Vox AC indicates the voltage where the differential output signals must cross 280 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards SSTL2 Il T DCI 2 5V Split Thevenin Termination Figure 6 75 shows a sample circuit illustrating a valid termination technique for SSTL2 II T DCI 2 5V with on chip split thevenin termination In this bidirectional I O standard when 3 stated the termination is invoked on the receiver and not on the driver DCI Not 3 stated 3 stated IOB IOB 2Rypp 2Zg 1002 SSTL2 IIT DCI SSTL2 II T DCI Ro 250 E 2Rypy 2Zg 1000 Vger 1 25V 7 Ro 250 ugi90 6 92 041206 Figure 6 75 SSTL2 II T DCI 2 5
208. ata Sheet for details It is strongly recommended to always set the DUTY CYCLE CORRECTION attribute to TRUE Setting this attribute to FALSE does not necessarily produce output clocks with the same duty cycle as the source clock DCM PERFORMANCE MODE Attribute The DCM PERFORMANCE MODE attribute allows the choice of optimizing the DCM either for high frequency and low jitter or for low frequency and a wide phase shift range The attribute values are MAX SPEED and MAX RANCGE The default value is MAX SPEED When set to MAX SPEED the DCM is optimized to produce high frequency clocks with low jitter However the phase shift range is smaller than when MAX RANGE is selected When set to MAX RANGE the DCM is optimized to produce low frequency clocks with a wider phase shift range The DCM PERFORMANCE MODE affects the following specifications DCM input and output frequency range phase shift range output jitter DCM TAP CLKIN CLKFB PHASE CLKOUT PHASE and duty cycle precision The Virtex 5 FPGA Data Sheet specifies these values For most cases the DCM PERFORMANCE MODE attribute should be set to MAX SPEED default Consider changing to MAX RANGE only in the following situations e The frequency needs to be below the low frequency limit of the MAX SPEED setting e A greater absolute phase shift range is required www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX DCM Attributes FACTORY JF Attribut
209. ata output bus DOP 7 0 Output Data output parity bus SBITERR Output Single bit error status DBITERR Output Double bit error status ECCPARITY 7 0 Output ECC encoder output bus FULL Output FIFO FULL flag ALMOSTFULL Output FIFO ALMOSTFULL flag EMPTY Output FIFO EMPTY flag ALMOSTEMPTY Output FIFO ALMOSTEMPTY flag RDCOUNT Output The FIFO data read pointer WRCOUNT Output The FIFO data write pointer WRERR Output When the FIFO is full any additional write operation generates an error flag RDERR Output When the FIFO is empty any additional read operation generates an error flag Notes 1 Hamming code implemented in the FIFO ECC logic detects one of three conditions no detectable error single bit error detected and corrected on DO but not corrected in the memory and double bit error detected without correction SBITERR and DBITERR indicate these three conditions 162 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com XILINX Block RAM and FIFO ECC Attributes In addition to the built in registers in the decode and correct logic the RAMB36SDP primitive allows the use of optional pipeline registers controlled by the DO_REG attribute to produce higher performance with one additional latency Table 4 23 and Table 4 24 list the block RAM and FIFO ECC attributes Table 4 23 Block RAM RAMB36SDP Attributes Built in Error Correction
210. ation e Fixed delay output mode In the fixed delay output mode the delay value is preset at configuration to the tap number determined by the attribute ODELAY_VALUE Once configured this value cannot be changed When used in this mode the IDELAYCTRL primitive must be instantiated See IDELAYCTRL Usage and Design Guidelines for more details When used as bidirectional delay the IOB is configured in bidirectional mode IODELAY alternately delays the data on the input path and output path There are two modes of operation e Fixed IDELAY IDELAY_TYPE FIXED and fixed ODELAY mode In this mode both the values for IDELAY and ODELAY are preset at configuration and are determined by the IDELAY VALUE and ODELAY VALUE attributes Once configured this value cannot be changed When used in this mode the IDELAYCTRL primitive must be instantiated See IDELAYCTRL Usage and Design Guidelines for more details e Variable IDELAY IDELAY TYPE VARIABLE and fixed ODELAY mode Virtex 5 FPGA User Guide www xilinx com 321 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX In this mode only the IDELAY value can be dynamically changed after configuration by manipulating the control signals CE and INC The logic level of the T pin in the IODELAY primitive dynamically determines if the block is in IDELAY or ODELAY mode When used in this mode the IDELAYCTRL primitive must be instantiated See IDELAYCTRL Usage and Design Gu
211. ation bitstream During a write operation the memory can be set to have the data output either remain unchanged reflect the new data being written or the previous data now being overwritten Virtex 5 FPGA block RAM enhancements include e Increased memory storage capability per block Each block RAM can store up to 36K bits of data e Support of two independent 18K blocks or a single 36K block RAM e Each 36K block RAM can be set to simple dual port mode doubling data width of the block RAM to 72 bits The 18K block RAM can also be set to simple dual port mode doubling data width to 36 bits Simple dual port mode is defined as having one read only port and one write only port with independent clocks e Two adjacent block RAMs can be combined to one deeper 64K x 1 memory without any external logic e One 64 bit Error Correction Coding block is provided per 36 Kb block RAM or 36 Kb FIFO Separate encode decode functionality is available e Synchronous Set Reset of the outputs to an initial value is available for both the latch and register modes of the block RAM output e An attribute to configure the block RAM as a synchronous FIFO to eliminate flag latency uncertainty e The Virtex 5 FIFO does not have FULL flag assertion latency Virtex 5 FPGA block RAM features e 18 36 or 72 bit wide ports can have an individual write enable per byte This feature is popular for interfacing to an on chip microprocessor e Each block RAM conta
212. average output capacitance and determines the SSO allowance by taking into account all of the board level design parameters mentioned in this document In addition the Virtex 5 FPGA SSO calculator checks the adjacent bank and package SSO ensuring the full device design does not exceed the SSO allowance Since bank number assignment for Virtex 5 devices is different from package to package due to its columnar architecture versus the peripheral I O architecture of previous devices there is a separate tab at the bottom of the SSO calculator display for each Virtex 5 FPGA package This customizing allows for the arrangement of physically adjacent banks as they appear clockwise on each unique package even though they are not labeled in a contiguous manner and the hard coding of the number of Vcco GND pairs per bank The Virtex 5 FPGA SSO Calculator file ug190 SSO Calculator zip is available at https secure xilinx com webreg clickthrough do cid 30154 Other SSO Assumptions LVDCI and HSLVDCI Drivers All limits for controlled impedance DCI I O standards assume a 50 Q output impedance For higher reference resistor RR values less drive strength is needed and the SSO limit increases linearly To calculate the SSO limit for a controlled impedance driver with different reference resistors the following formula is used User RR User SSO 500 a sso Limit for Q Example The designer uses LVDCI 18 driver with 65 Qreference r
213. bal Buffer 4 Internal Clock Any internal clock using general purpose routing The frequency range of PSCLK is defined by PSCLK_FREQ_LF HE See the Virtex 5 FPGA Data Sheet This input must be tied to ground when the CLKOUT PHASE SHIFT attribute is set to NONE or FIXED www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Ports Dynamic Reconfiguration Clock Input DCLK The dynamic reconfiguration clock DCLK input pin provides the source clock for the DCM s dynamic reconfiguration circuit The frequency of DCLK can be asynchronous in phase and frequency to CLKIN The dynamic reconfiguration clock signal is driven by any clock source external or internal including 1 IBUF Input Buffer 2 IBUFG Global Clock Input Buffer Only the IBUFGs on the same half of the device top or bottom as the DCM can be used to drive a CLKIN input of the DCM 3 BUFGCTRL An Internal Global Buffer 4 Internal Clock Any internal clock using general purpose routing The frequency range of DCLK is described in the Virtex 5 FPGA Data Sheet When dynamic reconfiguration is not used this input must be tied to ground See the dynamic reconfiguration chapter in the Virtex 5 FPGA Configuration Guide for more information DCM Control and Data Input Ports Reset Input RST The reset RST input pin resets the DCM circuitry The RST signal is an active High asynchronous reset Asserting the RST signal asynchr
214. ber of predetermined outputs based off the reference clock When the application requires a fine phase shift or a dynamic variable phase shift a DCM could be a better solution Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Application Guidelines PLL Application Example The following PLL attribute settings result in a wide variety of synthesized clocks IVCLK_DIVIDE 1 KIN1_PERIOD 10 0 CLKOUTO PHASE 0 CLKOUTO DUTY CYCLE 0 5 CLKOUTO DIVIDE 2 CLKOUT1 PHASE 90 CLKOUT1 DUTY CYCLE 0 5 CLKOUT1 DIVIDE 2 CLKOUT2 PHASE 0 CLKOUT2 DUTY CYCLE 0 25 CLKOUT2 DIVIDE 4 CLKOUT3 PHASE 90 CLKOUT3 DUTY CYCLE 0 5 CLKOUT3_DIVIDE 8 CLKOUT4_PHASE 0 CLKOUT4_DUTY_CYCLE 0 5 CLKOUT4_DIVIDE 8 CLKOUT5 PHASE 135 CLKOUT5 DUTY CYCLE 0 5 CLKOUT5 DIVIDE 8 CLKFBOUT PHASE 0 CLKFBOUT MULT 8 D C Figure 3 16 displays the resulting waveforms REFCLK JT 4E CLKOUT1 CLKOUT2 CLKOUT3 d Lp D Lo CLKOUT4 Jo l JP L o CLKOUT5 UG190 3 19 032506 Figure 3 16 Example Waveform Virtex 5 FPGA User Guide www xilinx com 107 UG190 v4 4 December 2 2008 Chapter 3 Phase Locked Loops PLLs XILINX PLL in Virtex 4 FPGA PMCD Legacy Mode 108 Virtex 5 devices do not have Phase Matched Clock Dividers PMCDs The Virtex 5 FPGA PLL supports th
215. c multiplexer from O6 output see Fast Lookahead Carry Logic feed the D input of the storage element or go to FAZAMUX F7BMUX from O6 output In addition to the basic LUTs slices contain three multiplexers F7AMUX F7BMUX and F8MUX These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice FF AMUX and F7BMUX are used to generate seven input functions from slice A and B or C and D while FSMUX is used to combine all slices to generate eight input functions Functions with more than eight inputs can be implemented using multiple slices There are no direct connections between slices to form function generators greater than eight inputs within a CLB or between slices Storage Elements The storage elements in a slice can be configured as either edge triggered D type flip flops or level sensitive latches The D input can be driven directly by a LUT output via AFFMUX BFFMUX CFFMUX or DFFMUX or by the BYPASS slice inputs bypassing the function generators via AX BX CX or DX input When configured as a latch the latch is transparent when the CLK is Low The control signals clock CK clock enable CE set reset SR and reverse REV are common to all storage elements in one slice When one flip flop in a slice has SR or CE enabled the other flip flops used in the slice will also have SR or CE enabled by the common signal Only the CLK signal has independent polarity
216. ce clock to the PLL at any given time A DCM can not be inserted in the feedback path of the PLL Both the PLLs or DCMs of a CMT can be used separately as stand alone functions The outputs from the PLL are not spread spectrum Virtex 5 FPGA User Guide www xilinx com 85 UG190 v4 4 December 2 2008 86 Chapter 3 Phase Locked Loops PLLs XILINX From any IBUFG implementation From any BUFG implementation To any BUFG DCM1 implementation clkout_pll lt 5 0 gt To any BUFG implementation DCM2 gt To any BUFG implementation PLL ug190_3_01_071207 Figure 3 1 Block Diagram of the Virtex 5 FPGA CMT Phase Lock Loop PLL Virtex 5 devices contain up to six CMT tiles The PLLs main purpose is to serve as a frequency synthesizer for a wide range of frequencies and to serve as a jitter filter for either external or internal clocks in conjunction with the DCMs of the CMT The PLL block diagram shown in Figure 3 2 provides a general overview of the PLL components www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA User Guide Introduction PFD CP LF VCO 00 Clock Pin MS mH o i 02 g mn f Tos 7 04 5 05 7 ug190_3_02_030506 Figure 3 2 Block Diagram of the Virtex 5 FPGA PLL Input muxes select the reference and feedback clocks from either the IBUFG BUFG IBUF PLL o
217. cember 2 2008 Chapter 3 Phase Locked Loops PLLs Application Guidelines This section summarizes when to select a DCM over a PLL or a PLL over a DCM 106 f f Mpr12 ouTPLL2 JOUTPLLYD j x Opi PLL to PLL Connection The PLL can be cascaded to allow generation of a greater range of clock frequencies The frequency range restrictions still apply Equation 3 9 shows the relationship between the final output frequency and the input frequency and counter settings of the two PLLs Figure 3 15 The phase relationship between the output clock of the second PLL and the input clock is undefined To cascade PLLs route the output of the first PLL to a BUFG and then to the CLKIN pin of the second PLL This path provides the lowest device jitter CLKIN1 CLKOUTO r CLKFBIN CLKOUT1 RST CLKOUT2 CLKOUT3 PLL CLKOUT4 CLKOUT5 CLKFBOUT M PLL1 INT e SS Dorr Oprr1 Dpxr2 Opi12 Mprr2 CLKIN1 CLKOUTO CLKFBIN CLKOUT1 RST CLKOUT2 CLKOUT3 PLL CLKOUT4 CLKOUT5 CLKFBOUT Figure 3 15 Cascading Two PLLs www xilinx com XILINX Equation 3 9 BUFG ug190_3_16_032506 Virtex 5 FPGA PLLs support up to six independent outputs Designs using several different outputs should use PLLs An example of designs using several different outputs follows The PLL is an ideal solution for this type of application because it can generate a configurable set of outputs over a wide range while the DCM has a fixed num
218. center column In the Virtex 5 Family Overview the total number of I O banks is listed by device type The XC5VLX30 has 12 usable I O banks and one configuration bank Figure 6 3 is an example of a columnar floorplan showing the XC5VLX30 I O banks BANK 20 I O BANK 20 I O BANK 20 I O BANK 20 I O ug190_6_03_021306 Figure 6 3 Virtex 5 FPGA XC5VLX30 I O Banks Reference Voltage Vref Pins Low voltage single ended I O standards with a differential amplifier input buffer require an input reference voltage Vpgp Vggg is an external input into Virtex 5 devices Within each I O bank one of every 20 I O pins is automatically configured as a Vggp input if using a single ended I O standard that requires a differential amplifier input buffer Output Drive Source Voltage Vcco Pins Many of the low voltage I O standards supported by Virtex 5 devices require a different output drive voltage Vcco As a result each device often supports multiple output drive source voltages Output buffers within a given Vcco bank must share the same output drive source voltage The following input buffers use the Vcco voltage LVTTL LVCMOS PCI LVDCI and other DCI standards Virtex 5 FPGA User Guide www xilinx com 217 UG190 v4 4 December 2 2008 218 Chapter 6 SelectlO Resources XILINX Virtex 5 FPGA Digitally Controlled Impedance DCI Introduction As FPGAs get bigger and
219. ces XILINX Table 6 28 lists the SSTL2 DC voltage specifications for Class I Table 6 28 SSTL2 DC Voltage Specifications Class Min Typ Max Vcco 2 3 25 27 Veer 7 05x Veco 1 13 1 25 1 38 Ver Vggr NO 1 09 1 25 1 42 Vg 2 Vggr 0 15 1 28 1 4 Veco 0 32 Vg Vggr 0 15 0 3 1 1 1 23 Von 2 Vrer 0 61 1 74 1 84 1 94 VoL lt Vggr 0 619 0 56 0 66 0 76 Tox at Voy mA 8 1 Io at Vor mA 8 1 B Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Vg maximum is Vcco 0 3 3 4 Because SSTL2 I DCI uses a controlled impedance driver Voy and Voy are different Vy minimum does not conform to the formula Differential SSTL2 Class 2 5V Figure 6 67 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class I 2 5V with unidirectional termination 274 External Termination Vary 1 25V IOB IOB DIFF SSTL2 I Rg 250 Sud K w m DIFF SSTL2 I Vez 1 25V DIFF_SSTL2_ Ag 250 Rp Zg 500 iw x ug190_6_64_030506 Figure 6 67 Differential SSTL2 Class I Unidirectional Termination www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Figure 6 68 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class I 2 5V with unidirectio
220. ck Event 4 The release of the reset signal at the RST input is retimed internally to CLK ISERDES VHDL and Verilog Instantiation Template VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives and submodules In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signal names Virtex 5 FPGA User Guide www xilinx com 361 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX 362 BITSLIP Submodule All ISERDES blocks in Virtex 5 devices contain a Bitslip submodule This submodule is used for word alignment purposes in source synchronous networking type applications Bitslip reorders the parallel data in the ISERDES block allowing every combination of a repeating serial pattern received by the deserializer to be presented to the FPGA fabric This repeating serial pattern is typically called a training pattern training patterns are supported by many networking and telecom standards Bitslip Operation By asserting the Bitslip pin of the ISERDES block the incoming serial data stream is reordered at the parallel side This operation is repeated until the training pattern is seen The tables in Figure 8 10 illustrate the effects of a Bitslip operation in SDR and DDR mode For illustrative pu
221. ck nets in the region it is located and the four clock nets in the adjacent clock regions up to three clock regions Unlike BUFIOs BUFRs can drive the I O logic and logic resources CLB block RAM etc in the existing and adjacent clock regions BUFRs can be driven by clock capable pins or local interconnect In addition BUFR is capable of generating divided clock outputs with respect to the clock input The divide values are an integer between one and eight BUFRs are ideal for source synchronous applications requiring clock domain crossing or serial to parallel conversion There are two BUFRs in a typical clock region four regional clock networks The center column does not have BUFRs BUFR Primitive BUFR is a clock in clock out buffer with the capability to divide the input clock frequency CE CLR ugi 90 1 20 032306 Figure 1 20 BUFR Primitive Table 1 7 BUFR Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port CE Input 1 Clock enable port Cannot be used in BYPASS mode CLR Input 1 Asynchronous clear for the divide logic and sets the output Low Cannot be used in BYPASS mode I Input 1 Clock input port Additional Notes on the CE Pin When CE is asserted deasserted the output clock signal turns on off When global set reset GSR signal is High BUFR does not toggle even if CE is held High The BUFR output toggles after the GSR signal is deasserted
222. clock event 1 PSEN is asserted PSEN must be active for exactly one clock period otherwise a single increment decrement of phase shift is not guaranteed Also the PSINCDEC value at Tpycck psincpEc before clock event 1 determines whether it is an increment logic High or a decrement logic Low Clock Event 2 At TpmcKko PSbONE after clock event 2 PSDONE is asserted to indicate one increment or decrement of the DCM outputs PSDONE is High for exactly one clock period when the phase shift is complete The time required for a complete phase shift varies As a result PSDONE must be monitored for phase shift status www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Timing Models Status Flags The example in Figure 2 20 shows the behavior of the status flags in the event of a phase shift overflow and CLKIN CLKFB CLKFX failure ckN l crB Ll DO 0 DO 1 257 260 Cycles DO 2 esck _ K psen PSDONE DO 3 ug190 2 21 042406 Figure 2 20 Status Flags Example e Clock Event 1 Prior to the beginning of this timing diagram CLKO not shown is already phase shifted at its maximum value At clock event 1 PSDONE is asserted However since the DCM has reached its maximum phase shift capability no phase adjustment is performed Instead the phase shift overflow status pin DO 0 is asserted to indicate this condition e Clock Event 2 The CLKFX output stops t
223. ctlO Logic Resources XILINX Clock Event 9 At time Tosrcx before Clock Event 9 rising edge of CLK the SR signal configured as synchronous reset in this case becomes valid high resetting ODDR register reflected at the OQ output at time Trg after Clock Event 9 no change at the OQ output in this case and resetting ODDR register reflected at the OQ output at time Trg after Clock Event 10 no change at the OQ output in this case Figure 7 28 illustrates the OLOGIC 3 state register timing 1 2 3 4 5 ox NM NAIA NAI NI NI N m ToOTck I lt TOTCECK TCE k TOSRCK oo o l TN o o ee Tocka Le I RQ TQ VY N S N UG190 7 23 041106 Figure 7 28 OLOGIC 3 State Register Timing Characteristics Clock Event 1 e At time TorcrcK before Clock Event 1 the 3 state clock enable signal becomes valid high at the TCE input of the 3 state register enabling the 3 state register for incoming data e At time Torck before Clock Event 1 the 3 state signal becomes valid high at the T input of the 3 state register returning the pad to high impedance at time Tocxg after Clock Event 1 Clock Event 2 e At time Tosrck before Clock Event 2 the SR signal configured as synchronous reset in this case becomes valid high resetting the 3 state register at time Trg after Clock Event 2 Figure 7 29 illustrates IOB DDR 3 state register timing This example is shown using DDR in opposite edge mode For oth
224. d Output Optional A6 AX F7AMUX ee r att a et i me ea ee m mel UG190 5 14 050506 Figure 5 14 Distributed RAM RAM256X1S Distributed RAM configurations greater than the provided examples require more than one SLICEM There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices Virtex 5 FPGA User Guide www xilinx com 187 UG190 v4 4 December 2 2008 188 Chapter 5 Configurable Logic Blocks CLBs XILINX Distributed RAM Data Flow Synchronous Write Operation The synchronous write operation is a single clock edge operation with an active High write enable WE feature When WE is High the input D is loaded into the memory location at address A Asynchronous Read Operation The output is determined by the address A for single port mode output SPO output of dual port mode or address DPRA DPO output of dual port mode Each time a new address is applied to the address pins the data value in the memory location of that address is available on the output after the time delay to access the LUT This operation is asynchronous and independent of the clock signal Distributed RAM Summary e Single port and dual port modes are available in SLICEMs e A write operation requires one clock edge e Read operations are asynchronous Q output e The data input has a setup to clock tim
225. d beyond 255 and incremented beyond 255 for VARIABLE CENTER mode incremented beyond 255 for VARIABLE POSITIVE mode or decremented beyond 0 and incremented beyond 1023 for DIRECT mode The DCM is phase shifted beyond the absolute range of the phase shift delay line In this case the phase shift overflow signal is asserted High when the phase shift in time ns exceeds the FINE_SHIFT_RANGE 2 in the VARIABLE_CENTER mode the FINE_SHIFT_RANGE in the VARIABLE POSITIVE mode or exceeds 0 to FINE SHIFT RANGE in the DIRECT mode The phase shift overflow signal can toggle once it is asserted The condition determining if the delay line is exceeded is calibrated dynamically Therefore at the boundary of exceeding the delay line it is possible for the phase shift overflow signal to assert and deassert without a change in phase shift Once asserted it remains asserted for at least 40 CLKIN cycles If the DCM is operating near the FINE SHIFT RANGE limit do not use the phase shift overflow signal as a flag to reverse the phase shift direction When the phase shift overflow is asserted deasserted then asserted again in a short phase shift range it can falsely reverse the phase shift direction Instead use a simple counter to track the phase shift value and reverse the phase shift direction PSINCDEC only when the counter reaches a previously determined maximum minimum phase shift value For example if the phase shift must be within 0 to 128 set the
226. d Virtex II Pro FPGAs Virtex 5 FPGA User Guide www xilinx com 25 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX The timing diagram in Figure 1 2 illustrates various clock switching conditions using the BUFGCTRL primitives Exact timing numbers are best found using the speed specification I ll 771 LM cM c x C PS ij TBCCCK CE GEM dR gg e n FR om CET 000 i do qo G S0 Lj pL pol e Y Sor a Ga IGNOREO IGNORE1 TBCCKO_O T T is BCCKO_O BCCKO_O oe nA a e at 10 Begin 11 Begin 10 ug 90 1 02 071707 Figure 1 2 BUFGCTRL Timing Diagram Before time event 1 output O uses input I0 At time Tgccck cr before the rising edge at time event 1 both CEO and SO are deasserted Low At about the same time both CE1 and S1 are asserted High At time Tpgccko o after time event 3 output O uses input I1 This occurs after a High to Low transition of I0 event 2 followed by a High to Low transition of I1 At time event 4 IGNORE is asserted At time event 5 CEO and SO are asserted High while CE1 and S1 are deasserted Low At Tpccko o after time event 6 output O has switched from I1 to I0 without requiring a High to Low transition of I1 Other capabilities of BUFGCTRL are 26 Pre selection of the I0 and I1 inputs are made after configuration but before device operation The initial output after configuration can be selected as ei
227. d in Table 4 16 Virtex 5 FPGA User Guide www xilinx com 145 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX FIFO Attributes Table 4 17 lists the FIFO18 and FIFO36 attributes The size of the multirate FIFO can be configured by setting the DATA_WIDTH attribute The FIFO VHDL and Verilog Templates section has examples for setting the attributes Table 4 17 FIFO18 and FIFO36 Attributes Attribute Name Type Values Default Notes ALMOST_FULL_OFFSET 13 bit See Table 4 19 Setting determines the difference HEX between FULL and ALMOSTFULL conditions Must be set using hexadecimal notation ALMOST_EMPTY_OFFSET 13 bit See Table 4 19 Setting determines the difference HEX between EMPTY and ALMOSTEMPTY conditions Must be set using hexadecimal notation FIRST_WORD_FALL_THROUGH Boolean FALSE FALSE If TRUE the first word written into the TRUE empty FIFO appears at the FIFO output without RDEN asserted DO_REG 1 bit 0 1 1 For multirate asynchronous FIFO Binary must be set to 1 For synchronous FIFO DO_REG must be set to 0 for flags and data to follow a standard synchronous FIFO operation When DO REG is set to 1 effectively a pipeline register is added to the output ofthe synchronous FIFO Data then has a one clock cycle latency However the clock to out timing is improved DATA WIDTH Integer 4 9 18 36 72 4 LOCC 2 String Valid FIFO18 or Sets the location of
228. d unidirectional termination technique for SSTL Class II 1 8V External Termination IOB Vr 0 9V Vr 0 9V IOB SSTL18 II SSTL18 II Rp Z9 500 Rp Zo 500 Rg 200 Vper 0 9V DCI IOB IOB 2Rypp 2Zg 1002 2Rypp 2Zg 1002 SSTL18_II_DCI SSTL18 Il DCI 1 0 2 kH V 0 9V Ro 202 and 2Rypy 2Zg 1000 2Rypy 2Zg 1002 to 7 ug190_6_75_030506 Figure 6 79 SSTL18 1 8V Class Il Unidirectional Termination Figure 6 80 shows a sample circuit illustrating a valid bidirectional termination technique for SSTL 1 8V Class II Virtex 5 FPGA User Guide www xilinx com 285 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources 2 XILINX External Termination ioB Vaz 0 9V Va 0 9V IOB SSTL18_ll l SSTL18_ll Rg 200 Rp Zo 500 Rp Zo 500 Rg 200 d Bw IED bd Vngr 0 9V l l l Veer 0 9V l DCI IOB IOB 2Rygp 2Zg 1000 2Rypp 2Zo 1000 Sere Oe SSTL18 Il DCI oH T gt Vpgr 0 9V Ro 2200 RER 2Rypy 2Zg 1000 E E 2Rypy 2Zo 1000 Vngr 0 9V lt Ro 2200 T al ugi90 6 76 071707 Figure 6 80 SSTL 1 8V Class Il Termination 286 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX
229. damage but can result in data uncertainty Virtex 5 FPGA User Guide www xilinx com 113 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX CASCADEOUTLATA CASCADEOUTREGA CASCADEOUTLATB CASCADEOUTREGB 36 Kbit Block RAM Port A ADDRA 36 Kb Memory Array Port B CASCADEINLATA CASCADEINREGA CASCADEINLATB CASCADEINREGB ug0190 4 01 032106 Figure 4 1 True Dual Port Data Flows Table 4 2 True Dual Port Names and Descriptions Port Name Description DI A B Data Input Bus DIP A BJ Data Input Parity Bus can be used for additional data inputs ADDR A B Address Bus WE A B Byte wide Write Enable EN A B When inactive no data is written to the block RAM and the output bus remains in its previous state SSR A B Synchronous Set Reset for either latch or register modes CLK A B Clock Input DO A B Data Output Bus DOP A B Data Output Parity Bus can be used for additional data outputs REGCE A B Output Register Enable 114 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com XILINX Synchronous Dual Port and Single Port RAMs Table 4 2 True Dual Port Names and Descriptions Continued Port Name Description CASCADEINLAT A B Cascade input pin for 64K x 1 mode when optional output registers are not enabled CASCADEOUTLAT A B Cascade output pin for 64K x 1 mode when
230. dard is a high speed bus standard JESD8 3 invented by Xerox Xilinx has implemented the terminated variation for this standard This standard requires a differential amplifier input buffer and an open drain output buffer The negative terminal of the differential input buffer is referenced to the Vggg pin A sample circuit illustrating a valid termination technique for GTL with external parallel termination and unconnected Vcco is shown in Figure 6 35 SS PR miners Cor em eoe ree IOB V r 1 2V Vqp2 12V IOB Rp Zg 500 Veco Unconnected 4 ug190_6_34_022806 Figure 6 35 GTL with External Parallel Termination and Unconnected Veco GTL DCI Usage GTL does not require a Veco voltage However for GTL_DCI Veco must be connected to 1 2V GTL_DCI provides single termination to Vcco for inputs or outputs A sample circuit illustrating a valid termination technique for GTL DCI with internal parallel driver and receiver termination is shown in Figure 6 36 Rypp Zo 500 JL ugi 90 6 35 030206 Figure 6 36 GTL_DCI with Internal Parallel Driver and Receiver Termination Table 6 13 lists the GTL DC voltage specifications Table 6 13 GTL DC Voltage Specifications Parameter Min Typ Max Vcco N A Veer N x Ver 0 74 0 8 0 86 Vir 1 14 1 2 1 26 Vig Veer 0 05 0 79 0 83 Vi Vggg 0 05 0 77 0 81 Vou B Virtex 5 FPGA
231. data rate SDR and double data rate DDR The OSERDES uses two clocks CLK and CLKDIV for data rate conversion CLK is the high speed serial clock CLKDIV is the divided parallel clock It is assumed that CLK and CLKDIV are phase aligned Prior to use a reset must be applied to the OSERDES The OSERDES contains an internal counter that controls dataflow Failure to synchronize the reset with the CLKDIV will produce an unexpected output Table 8 5 describes the relationship between CLK and CLKDIV in all modes 366 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Output Parallel to Serial Logic Resources OSERDES Table 8 5 CLK CLKDIV Relationship of the Data Parallel to Serial Converter Input Data Width Output in SDR Input Data Width Output in DDR CLK CLKDIV Mode Mode 2 4 2X X 3 6 3X X 4 8 4X X 5 10 5X X 6 6X X 7 7X X 8 8X X 3 State Parallel to Serial Conversion In addition to parallel to serial conversion of data an OSERDES module also contains a parallel to serial converter for 3 state control of the IOB Unlike data conversion the 3 state converter can only serialize up to four bits of parallel 3 state signals The 3 state converter cannot be cascaded OSERDES Primitive The OSERDES primitive is shown in Figure 8 15 Virtex 5 FPGA User Guide CLK gt CLKDIV gt D1 gt D2 gt D3 gt D4 gt
232. de Virtex 5 FPGA User Guide Dedicated Deserializer Serial to Parallel Converter The ISERDES deserializer enables high speed data transfer without requiring the FPGA fabric to match the input data frequency This converter supports both single data rate SDR and double data rate DDR modes In SDR mode the serial to parallel converter creates a 2 3 4 5 6 7 or 8 bit wide parallel word In DDR mode the serial to parallel converter creates a 4 6 8 or 10 bit wide parallel word Bitslip Submodule The Bitslip submodule allows designers to reorder the sequence of the parallel data stream going into the FPGA fabric This can be used for training source synchronous interfaces that include a training pattern Dedicated Support for Strobe based Memory Interfaces ISERDES contains dedicated circuitry including the OCLK input pin to handle the strobe to FPGA clock domain crossover entirely within the ISERDES block This allows for higher performance and a simplified implementation www xilinx com 349 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX e Dedicated support for Networking interfaces Figure 8 1 shows the block diagram of the ISERDES highlighting all the major components and features of the block PLI CLKDIV e Serial to Parallel L SHIFTIN1 2 CE1 L gt Converter CE CE2 Module SHIFTOUT1 2 Q 06 ock __ gt CLK BITSLIP
233. der and deeper memory structures using multiple block RAM instances This program outputs VHDL or Verilog instantiation templates and simulation models along with an EDIF file for inclusion in a design Block RAM SSR in Register Mode A block RAM SSR in register mode can be used to control the output register as a true pipeline register independent of the block RAM As shown in Figure 4 11 block RAM can be read and written independent of register enable or set reset In register mode SSR sets DO to the SRVAL and data can be read from the block RAM to DBRAM Data at DBRAM can be clocked out DO on the next cycle The timing diagrams in Figure 4 12 and Figure 4 13 show different cases of the SSR operation Virtex 5 FPGA User Guide www xilinx com 131 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Block RAM DI DERAM Output DO Register EN BRAM_RAMEN c BRAM_SSR REGCE SSR In register mode the block RAM SSR is disabled and the SSR pin only sets resets the output registers ug190 4 28 071707 Figure 4 11 Block RAM SSR in Register Mode RAMEN REGCE SSR DBRAM Block RAM can be read when SSR is active Data appears on the output of the next REGCE ug190_4 29 071607 Figure 4 12 SSR Operation in Register Mode with REGCE High 132 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Timing Model RAMEN REGCE SSR
234. des a time reference to IDELAYCTRL to calibrate all IODELAY modules in the same region This clock must be driven by a global clock buffer BUFGCTRL REFCLK must be Fipgr AycTRI REF the specified ppm tolerance IDELAYCTRL REF PRECISION to guarantee a specified IODELAY resolution T pELAYRESOLUTION REFCLK can be supplied directly from a user supplied source the PLL or from the DCM and must be routed on a global clock buffer RDY Ready The ready RDY signal indicates when the IODELAY modules in the specific region are calibrated The RDY signal is deasserted if REFCLK is held High or Low for one clock period or more If RDY is deasserted Low the IDELAYCTRL module must be reset The implementation tools allow RDY to be unconnected ignored Figure 7 16 illustrates the timing relationship between RDY and RST 334 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY IDELAYCTRL Timing Table 7 12 shows the IDELAYCTRL switching characteristics Table 7 12 IDELAYCTRL Switching Characteristics Symbol Description FIDELAYCTRL_REF REFCLK frequency IDELAYCTRL_REF_PRECISION REFCLK precision Reset Startup to Ready for IDELAYCTRL TIDELAYCTRLCO_RDY As shown in Figure 7 16 the Virtex 5 FPGA RST is an edge triggered signal a RST m TipELAYCTRLCO RDY ex MU v e ugi90 7 11 041206 Figure 7 16 Timing Relationship Between RST and RDY
235. dy 2 IDELAYCTRL 2 rst 2 RST REFCLK RDY rdy n IDELAYCTRL n T RS ug190 7 15 041306 Figure 7 20 Instantiate IDELAYCTRL with LOC Constraint Instantiating IDELAYCTRL With and Without LOC Constraints There are cases where the user instantiates an IDELAYCTRL module with a LOC constraint but also instantiates an IDELAYCTRL module without a LOC constraint In the case where an IP Core is instantiated with a non location constrained IDELAYCTRL module and also wants to instantiate an IDELAYCTRL module without a LOC constraint for another part of the design the implementation tools will perform the following e Instantiate the LOC IDELAYCTRL instances as described in the section Instantiating IDELAYCTRL with Location LOC Constraints e Replicate the non location constrained IDELAYCTRL instance to populate with an IDELAYCTRL instance in every clock region without a location constrained IDELAYCTRL instance in place e The signals connected to the RST and REFCLK input ports of the non location constrained IDELAYCTRL instance are connected to the corresponding input ports of the replicated IDELAYCTRL instances e Ifthe RDY port of the non location constrained IDELAYCTRL instance is ignored then all the RDY signals of the replicated IDELAYCTRL instances are also ignored e Ifthe RDY port of the non location constrained IDELAYCTRL instance is connected then the RDY port of the non location constrained instance plus the RDY ports
236. e The Factory JF attribute affects the DCMs jitter filter characteristics This attribute controls the DCM tap update rate The default value is OxFOFO0 corresponding to DLL FREQUENCY MODE LOW and DLL FREQUENCY MODE HIGH PHASE SHIFT Attribute The PHASE SHIFT attribute determines the amount of phase shift applied to the DCM outputs This attribute can be used in both fixed or variable phase shift mode If used with variable mode the attribute sets the starting phase shift When CLKOUT PHASE SHIFT VARIABLE POSITIVE the PHASE SHIFT value range is 0 to 255 When CLKOUT PHASE SHIFT VARIABLE CENTER or FIXED the PHASE SHIFT value range is 2255 to 255 When CLKOUT PHASE SHIFT DIRECT the PHASE SHIFT value range is 0 to 1023 The default value is 0 Refer to the Phase Shifting section for information on the phase shifting operation and its relationship with the CLKOUT PHASE SHIFT and PHASE SHIFT attributes STARTUP WAIT Attribute The STARTUP WAIT attribute determines whether the DCM waits in one of the startup cycles for the DCM to lock The possible values for this attribute are TRUE and FALSE The default value is FALSE When STARTUP WAIT is set to TRUE and the LCK cycle BitGen option is used then the configuration startup sequence waits in the startup cycle specified by LCK cycle until the DCM is locked Table 2 6 DCM Attributes DCM Attribute Name CLKDV DIVIDE Description Values Default Value This attribute contr
237. e T BCCKO_O ugi90 1 06 032206 Figure 1 6 BUFGCE Timing Diagram BUFGCE 1 is similar to BUFGCE with the exception of its switching condition If the CE input is Low prior to the incoming falling clock edge the following clock pulse does not pass through the clock buffer and the output stays High Any level change of CE during the incoming clock Low pulse has no effect until the clock transitions High The output stays High when the clock is disabled However when the clock is being disabled it completes the clock Low pulse Figure 1 7 illustrates the timing diagram for BUFGCE 1 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Global Clocking Resources BUFGCE_1 I l SNA N SA NY IET BUFGCE 1 CE rr n Ff Teeeok ge BUF amp CE 10 TN M M N f T BCCKO_O ug190_1_07_032206 Figure 1 7 BUFGCE_1 Timing Diagram BUFGMUX and BUFGMUX 1 BUFGMUX is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 8 illustrates the relationship of BUFGMUX and BUFGCTRL A LOC constraint is available for BUFGMUX and BUFGCTRL GND IGNORE1 S CE1 Vpp Si BUFGMUX Vis SO gt CEO ND IGNOREO G ug190_1_08_032206 Figure 1 8 BUFGMUX as BUFGCTRL Since the BUFGMUX uses the CE pins as select pins when using the select the setup time requireme
238. e FIFO36 72 ECC primitive The FIFO36 72 only supports standard mode RAMB36SDP DO 63 0 DOP 7 0 ECCPARITY 7 0 Standard or Encode Only SBITERR DBITERR ug190 4 26 022207 Figure 4 29 RAMB36SDP Block RAM ECC Primitive FIFO36 72 DO 63 0 DOP 7 0 ECCPARITY 7 0 SBITERR DBITERR FULL EMPTY ALMOSTFULL ALMOSTEMPTY WRERR RDERR WRCOUNT S 0 RDCOUNT S 0 ugi90 4 34 022207 Figure 4 30 FIFO36 72 FIFO ECC Primitive 160 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 X XILINX Built in Error Correction Block RAM and FIFO ECC Port Descriptions Table 4 21 lists and describes the block RAM ECC I O port names Table 4 21 Block RAM ECC Port Names and Descriptions Port Name Direction Signal Description DI 63 0 Input Data input bus DIP 7 0 Input Data input parity bus Used in decode only mode to input the precalculated ECC parity bits WRADDR S 0 Input Write address bus RDADDR S8 0 Input Read address bus WREN Input Write enable When WREN 1 data will be written into memory When WREN 0 write is disabled RDEN Input Read enable When RDEN 1 data will be read from memory When RDEN 0 read is disabled SSR Input Not supported when using the block RAM ECC primitive Always connect to GND WRCLK Input Clock for write operations RDCLK Input Clock for read operations DO 63 0 Output Data
239. e Differential Signaling 291 Transmitter Termination 0 0 0 0 ccc ehh 291 Receiver Termination 0 0 0 00 ccc cece eee eee n eee e eee n nee 292 HyperTransport Protocol HT 6 6 nee ee 293 Reduced Swing Differential Signaling RSDS 0 0 cee eee eee eee 293 BLVDS Bus LVDS csi seiri 00 0 cece cece tee ms hr 293 Differential LVPECL Low Voltage Positive Emitter Coupled Logic 294 LVPECL Transceiver Termination 000 ccc eee cece eee eee e eens 294 Rules for Combining I O Standards in the Same Bank 295 3 3V I O Design Guidelines ssssssssss eee 299 I O Standard Design Rules oi ere Led e bg depre denn 299 Mixing Techniques RE R etx E Ri quee paese que ek butt ed eara 301 Simultaneous Switching Output Limits 0 000000200 302 Sparse Chevron Packages ccc eee 302 Nominal PCB Specifications 2 6 6 ccc eee 303 PCB ConstructiOD enne etd oboe ed ob ac cde est Winds esee tate t Re ta ee in ee 303 Signal Return Current Management lisse enn 303 koad Traces 2a idee teer eren ecd eee eec te Re Me ee DR a eol 303 Power Distribution System Design csse 303 NommanalSSQ Dit ao resne aceti mete ete e Rte eat ete ed Sus t d ea e ges 304 Actual SSO Limits versus Nominal SSO Limits 0 0 0 0 0000 ce cece eee 309 Electrical Basis of SSO Noise 0 ccc ccc cece en 309 Parasitic Factors
240. e EN Tnckc EN Time after the clock that the enable signal must be stable at the EN input of the block RAM TRCCK SSR Time before the clock that the synchronous set reset signal must Synchronous aen be stable at the SSR input of the block RAM TRCKC SSR Set Reset Time after the clock that the synchronous set reset signal must be stable at the SSR input of the block RAM TRCCK_WE Time before the clock that the write enable signal must be stable at the WE input of the block RAM Write Enable WE TRCKC_WE Time after the clock that the write enable signal must be stable at the WE input of the block RAM TRCCK_REGCE Time before the CLK that the register enable signal must be stable Optional Output Bid at the REGCE input of the block RAM TnCKC REGCE Register Enable Time after the clock that the register enable signal must be stable at the REGCE input of the block RAM Clock to Out Delays Tncko po Clock to Output CLKto Time after the clock that the output data is stable at the DO latch mode DO outputs of the block RAM without output register Tncko po Clock to Output CLKto Time after the clock that the output data is stable at the DO register mode DO outputs of the block RAM with output register Notes 1 While EN is active ADDR inputs must be stable during the entire setup hold time window even if WE is inactive Violating this requirement can result in block RAM data corruption If ADDR timing could violate the specified requir
241. e OSERDES module in VHDL and Verilog 378 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 Index A asynchronous clocking 117 distributed RAM 179 global set reset 126 mux 32 set reset in register or latch 178 Bitslip 362 See ISERDES 349 guidelines for use 363 operation 362 timing 364 block RAM defined 113 asynchronous clocking 117 ECC 157 Primitive 160 ECC Port 161 operating modes NO CHANGE 116 READ FIRST 116 WRITE FIRST 116 ports 123 synchronous clocking 117 BLVDS 293 BUFG 27 BUFGCE 28 BUFGCTRL 24 BUFGMUX 29 BUFGMUX VIRTEX4 30 with CE 33 BUFIO 37 BUFR 39 C CLB 171 array size by device 175 distributed RAM 178 maximum distributed RAM 175 number of flip flops 175 number of LUTs by device 175 number of shift registers 175 register latch configuration 177 slice description 172 SLICEL 172 SLICEM 172 CLK2X 51 CLKDV 51 CLKFB 48 CLKFX 51 clock capable I O 36 clock forwarding 343 clock regions 35 clock tree 34 clocking wizard 79 clocks global clock buffers 22 23 I O clock buffer 37 regional clock buffers 36 39 regions 34 resources 25 CMT 43 allocation in device 44 combinatorial input path 315 configuration DCM 61 D DCI 218 defined 218 DCLK 49 DCM 44 allocation in device 44 attributes 54 57 clock deskew 44 59 clocking wizard 79 configuration 61 DCM ADV 47 DCM BASE 46 design guidelines 59 deskew 63 dynamic reconfiguration 45 69 frequency synthesis
242. e Virtex 4 FPGA PMCD mode of operation To take advantage of the inherently more powerful features of the Virtex 5 FPGA PLL Xilinx recommends redesigning Virtex 4 FPGA PMCDs by implementing PLLs directly The difference between the Virtex 5 FPGA PLL and the Virtex 4 FPGA PMCD block in Virtex 4 FPGA PMCD legacy mode is that only two clock inputs are supported in the Virtex 5 device implementation The Virtex 4 device implementation supported up to four clock inputs If four clock inputs must be used then two PLLs can be put into PMCD mode In this case delay matching is not optimal Figure 3 17 shows the Virtex 4 FPGA PMCD primitive implemented using a PLL A PLL can not be used as a PLL if it is already being used as a PMCD To design in the Virtex 5 FPGA PMCD functionality instantiate a Virtex 4 FPGA PMCD primitive ISE software maps the Virtex 4 FPGA PMCD primitive into a Virtex 5 FPGA PLL CLKFBIN D ST CLKIN i D E gt peura D ONE Lus ug190 3 16 022207 Figure 3 17 PMCD Primitive Implemented Using the PLL in PMCD Legacy Mode Table 3 8 shows the port mapping between Virtex 5 FPGA PLL in PMCD legacy mode and the Virtex 4 FPGA PMCD port names Table 3 8 Mapping of Port Names Virtex 4 FPGA Virtex 5 FPGA Port Name Port Name CLKA CLKIN CLKB CLKFBIN CLKC n a CLKD n a CLKA1 CLKOUT3 CLKA1D2 CLKOUT2 CLKA1D4 CLKOUTI CLKA1D8 CLKOUTO www xilinx com Virtex 5 FPGA User Guide UG190 v4
243. e been 104 PEL Driving DCM ecceeycteRO LUE EUH e esas urpis ipsi ud etus 105 PLE to PLL Connection evel widths Seek ON REE Nau Xu e ye E RES 106 Application Guidelines iaiey dae od aper doceo dC o potato E eot a o 106 PLL Application Example i 6c ceiid e iae e ne en 107 PLL in Virtex 4 FPGA PMCD Legacy Mode ssssssee 108 Chapter 4 Block RAM Block RAMIS BITEDRATY 5 oed ras Yit ANLE SR pi PEOR tar Chute ede uta Re sy gie 111 Block RAM Introduction s sess 113 Synchronous Dual Port and Single Port RAMS 0000 113 Data ElOW 5e saci PRG as trices Phew Eo ee ee PR kk we REG Bos heen oR Rackets 113 Read Operation sx c2ocsargr re A een eO Hte qe pu exp p ety pace ete 115 Write Operator psr erine auda tore rq RR cae a anta dette C edt esu 115 Write Modes 2s bled chads Gaede a Miedo i Bie Pied ae bodewee Me SES 115 WRITE FIRST or Transparent Mode Default 0 00 ccc eee ee eee 116 READ FIRST or Read Before Write Mode ccc ccc nurnerr 116 NO CHANGE Mode ccc ccc eee eee eee e eee tee enees 116 Conflict Avoidance 5s ceves vy wr REY Ru RERV FRE X an GS ENVP RERS 117 Asynchronous Clocking 3 4 4 nuu erar oct oy e E dC yu eI UE dub a eee e dea 117 Synchronous Clocking ersa sd eR EE aie EI dI DLEX RU eL EAR REA 117 Additional Block RAM Features in Virtex 5 Devices 05 118 Optional Output Registers isses 118 Independent
244. e block RAM Attime TRCKO DOP register mode after time T2R data PA hex becomes valid at the DOP 7 0 output pins of the block RAM Attime TRCKO ECCR SBITERR register mode after time T2R SBITERR is asserted if single bit error is detected and corrected on data set A Attime TRCKO ECCR DBITERR register mode after time T3R DBITERR is Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 asserted if double bit error is detected on data set B www xilinx com 167 Chapter 4 Block RAM XILINX Encode Only ECC Write Timing Figure 4 31 e Setup hold time for WREN and WRADDR are the same as standard ECC e Attime TRDCK DI ECC encode only ECC before time T1W write data A hex becomes valid at the DI 63 0 inputs of the block RAM e At time TRCKO ECC PARITY encode only ECC after time T1W ECC parity data PA hex becomes valid at the ECCPARITY 7 0 output pins of the block RAM Encode Only ECC Read Timing e Encode only ECC read timing are the same as normal block RAM read timing Decode Only ECC Write Timing e Decode only ECC write timing is the same as normal block RAM write timing Decode Only ECC Read Timing e Decode only ECC read timing is the same as standard ECC read timing Block RAM ECC Mode Timing Parameters Table 4 25 shows the Virtex 5 FPGA block RAM ECC mode timing parameters Table 4 25 Block RAM ECC Mode Timing Parameters Control T Parameter Function Signal Description
245. e for details RESET ON LOSS OF LOCK String FALSE FALSE Must be set to FALSE not supported in silicon 96 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 General Usage Description PLL CLKIN1 and CLKIN2 Usage CLKINI is the general purpose input to the PLL The CLKIN2 pin is used to dynamically switch between CLKIN1 and CLKIN2 during operation as selected by the CLKINSEL pin If both CLKIN1 and CLKIN2 are used and the PLL input clocks are driven by global clock pins there are several restrictions on the placement of both clock signal pins CLKIN1 can only come from IBUFG 4 0 CLKIN2 can only come from IBUFG 9 5 Further CLKIN2 has to be mapped to a specific location depending on the value of CLKIN1 These rules are as follows If CLKIN1 is connected to IBUFG x CLKIN2 needs to be IBUFG y of the same type Table 3 5 shows the general clock pin pairing Table 3 5 Mapping Locations CLKIN1 CLKIN2 0 5 1 6 2 7 3 8 4 9 When the PLL input clocks are driven by the global clock trees BUFGs both clock inputs must be connected to the same clock input type Driving one PLL clock input with a IBUFG and the other with a BUFG is not possible The following tables map the Virtex 5 FPGA global clock IBUFG pins with respect to CLKIN1 and CLKIN2 PLLs in the top half of the Virtex 5 device are driven by the global clock pi
246. e information see the Dynamic Reconfiguration chapter of the Virtex 5 FPGA Configuration Guide The DADDR 6 0 DI 15 0 DWE DEN DCLK inputs and DO 15 0 and DRDY outputs are available to dynamically reconfigure select DCM functions With dynamic reconfiguration DCM attributes can be changed to select a different phase shift multiply M or divide D from the currently configured settings www xilinx com 45 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology DCM Primitives XILINX The DCM primitives DCM_BASE and DCM_ADV are shown in Figure 2 2 DCM_BASE CLKO CLKFB CLK90 CLK180 gt RST CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED DCM ADV ug190 2 02 042706 Figure 2 2 DCM Primitives DCM_BASE Primitive The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies the user interface ports The clock deskew frequency synthesis and fixed phase shifting features are available to use with DCM_BASE Table 2 2 lists the available ports in the DCM_BASE primitive Table 2 2 DCM_BASE Primitive Available Ports Port Names Clock Input CLKIN CLKFB Control and Data Input RST Clock Output CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Status and Data Output LOCKED 46 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Ports DCM ADV Primitive
247. e invoked by adding the following possible constraint values to the relevant net of the buffers e PULLUP e PULLDOWN e KEEPER Differential Termination Attribute The differential termination DIFF TERM attribute is designed for the Virtex 5 FPGA supported differential input I O standards It is used to turn the built in 1000 differential termination on or off The allowed values for the DIFF TERM attribute are e TRUE e FALSE Default To specify the DIFF_TERM attribute set the appropriate value in the generic map VHDL or inline parameter Verilog of the instantiated IBUFDS or IBUGDS component Please refer to the ISE Language Templates or the Virtex 5 FPGA HDL Libraries Guide for the proper syntax for instantiating this component and setting the DIFF_TERM attribute Virtex 5 FPGA I O Resource VHDL Verilog Examples The VHDL and Verilog example syntaxes to declare a standard for Virtex 5 FPGA I O resources are found in the Virtex 5 FPGA Libraries Guide Virtex 5 FPGA User Guide www xilinx com 235 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Specific Guidelines for I O Supported Standards The following sections provide an overview of the I O standards supported by all Virtex 5 devices While most Virtex 5 FPGA I O supported standards specify a range of allowed voltages this chapter records typical voltage values only Detailed information on each specification can be found on the Electronic Ind
248. e of EMPTY must therefore artificially 144 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Operations be moved onto the RDCLK time domain Since the two clocks have an unknown phase relationship it takes several cascaded flip flops to guarantee that such a move does not cause glitches or metastable problems The falling edge of EMPTY is thus delayed by several RDCLK periods after the first write into the previously empty FIFO This delay guarantees proper operation under all circumstances and causes an insignificant loss of performance after the FIFO had gone empty Almost Empty Flag The Almost Empty flag is set when the FIFO contains the number of entries specified by the ALMOST_EMPTY_OFFSFT value or fewer entries The Almost Empty flag warns the user to stop reading It deasserts when the number of entries in the FIFO is greater than the ALMOST EMPTY OFFSET value plus one Assertion and deassertion is synchronous to RDCLK Flag latency is described in Table 4 16 When a Virtex 5 FPGA FIFO is instantiated in FWFT mode ALMOST EMPTY OFFSET must be set to a value that satisfies Equation 4 1 WRCLK frequenc 2 P ALMOST EMPTY OFFSET 2 4 x Roundup RDCLK src Equation 4 1 For example if the read frequency is 1 2 the write frequency ALMOST EMPTY OFFSET needs to be greater than 8 This equation also means that any time the read frequency is greater than or equal to the write frequency any legal
249. e parasitics the larger the voltage induced by a current transient power supply disturbance Vcc bounce affects stable high outputs Ground bounce affects stable low outputs Ground bounce also affects inputs configured as certain I O standards because they interpret incoming signals by comparing them to a threshold referenced to the die ground as opposed to I O standards with input thresholds referenced to a Vggg voltage If the die voltage disturbance exceeds the instantaneous noise margin for the interface then a non changing input or output can be erroneously interpreted as changing SSO noise can also manifest in the form of crosstalk between I Os in close proximity to one another The sparse chevron pinout of Virtex 5 devices reduces crosstalk in the pinout region to a minimum Parasitic Factors Derating Method PFDM This section describes a method to evaluate whether a design is within the SSO limits when taking into account the specific electrical characteristics of the user s unique system The SSO limits in Table 6 40 assume nominal values for the parasitic factors of the system These factors fall into three groups of electrical characteristics Virtex 5 FPGA User Guide www xilinx com 309 UG190 v4 4 December 2 2008 310 Chapter 6 SelectlO Resources XILINX e PCB PDS parasitics nominal 1 nH per via e Maximum allowable power system disturbance voltage nominal 600 mV e Capacitive loading nominal 10 pF per lo
250. e reset signal High for three read and write clock cycles to ensure that all internal states and flags are reset to the correct value Case 6 Simultaneous Read and Write for Multirate FIFO Simultaneous read and write operations for an asynchronous FIFO is not deterministic when the FIFO is at the condition to assert a status flag The FIFO logic resolves the situation either assert or not assert the flag the software simulation model can not reflect this behavior and mismatch can occur When using a single clock for RDCLK and WRCLK use the FIFO in synchronous mode EN SYN TRUE FIFO Applications A FIFO larger than a single Virtex 5 FPGA FIFO block can be created by e Cascading two or more FIFOs to form a deeper FIFO e Building a wider FIFO by connecting two or more FIFOs in parallel Cascading FIFOs to Increase Depth Figure 4 26 shows a way of cascading N FIFO36s to increase depth The application sets the first N 1 FIFOs in FWFT mode and uses external resources to connect them together The data latency of this application is the sum of the individual FIFO latencies The maximum frequency is limited by the feedback path The NOR gate is implemented using CLB logic e Ncanbe2 or more if N is 2 the middle FIFOs are not needed e IfWRCLK is faster than RDCLK then INTCLK WRCLK e IfWRCLK is equal to or slower than RDCLK then INTCLK RDCLK e ALMOST EMPTY threshold is set in the Nth FIFO ALMOST FULL threshold is set
251. ecrement is not guaranteed PSDONE is High for exactly one clock period when the phase shift is complete The time required to complete a phase shift operation varies As a result PSDONE must be monitored for phase shift status Between enabling PSEN and PSDONE is flagged the DCM output clocks gradually change from their original phase shift to the incremented decremented phase shift The completion of the increment or decrement is signaled when PSDONE asserts High After PSDONE has pulsed High another increment decrement can be initiated Figure 2 6 illustrates the interaction of phase shift ports PSEN 1 PSDONE i ugi90 2 06 032506 Figure 2 6 Phase Shift Timing Diagram When PSEN is activated after the phase shift counter has reached the maximum value of PHASE SHIFT the PSDONE is still pulsed High for one PSCLK period some time after the PSEN is activated as illustrated in Figure 2 6 However the phase shift overflow pin STATUS 0 or DO 0 is High to flag this condition and no phase adjustment is performed Virtex 5 FPGA User Guide www xilinx com 67 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Phase Shift Overflow The phase shift overflow DO 0 status signal is asserted when either of the following conditions is true The DCM is phase shifted beyond the allowed phase shift value In this case the phase shift overflow signal is asserted High when the phase shift is decremente
252. ed the RDY signals of all the replacement IDELAYCTRL instances are left unconnected The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive without LOC constraints leaving the RDY output port unconnected are provided in the Libraries Guide The resulting circuitry after instantiating the IDELAYCTRL components is illustrated in Figure 7 18 336 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX REFCLK Input Output Delay Element IODELAY Instantiated by user e REFCLK RDY IDELAYCTRL T RST Figure 7 18 REFCLK RDY IDELAYCTRL RDY signal ignored RST Replicated for all IDELAYCTRL sites REFCLK RDY IDELAYCTRL RST Auto generated by mapper tool ug190_7_13_041206 Instantiate IDELAYCTRL Without LOC Constraints RDY Unconnected 2 When RDY port is connected an AND gate of width equal to the number of clock regions is instantiated and the RDY output ports from the instantiated and replicated IDELAYCTRL instances are connected to the inputs of the AND gate The tools assign the signal name connected to the RDY port of the instantiated IDELAYCTRL instance to the output of the AND gate The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive without LOC constraints with the RDY port connected are provided in the Libraries Guide The resulting circuitry after instantiating the IDELAYCTRL compone
253. ed by Trpockp o NA NIS NI NYI NYI N i lipock E licE1CK CE1 A Tisrck SR M ug190_7_06_041206 Figure 7 6 LOGIC Input Register Timing Characteristics 318 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX ILOGIC Resources Clock Event 1 e Attime T cg ck before Clock Event 1 the input clock enable signal becomes valid high at the CE1 input of the input register enabling the input register for incoming data e Attime Typocy before Clock Event 1 the input signal becomes valid high at the D input of the input register and is reflected on the Q1 output of the input register at time Ticko after Clock Event 1 Clock Event 4 e Attime Tyspcy before Clock Event 4 the SR signal configured as synchronous reset in this case becomes valid high resetting the input register and reflected at the O1 output of the IOB at time Tyco after Clock Event 4 ILOGIC Timing Characteristics DDR Figure 7 7 illustrates the ILOGIC in IDDR mode timing characteristics When IDELAY is used Tipocy is replaced by Tipockp The example shown uses IDDR in OPPOSITE EDGE mode For other modes add the appropriate latencies as shown in Figure 7 4 page 317 ex A NA NAT NAT NY XY Ticko lt Z gt l Ticka a ix NiE 1X3 1 1 Nu E lcko T UG190 7 07 041206 Figure 7 7 LOGIC in IDDR Mode
254. ed termination circuit DCI Not 3 stated IOB SSTL18 Il T DCI 290 C Zo 3 stated IOB Veco 1 8V 2Rypp 2Zg 1002 SSTL18 Il T DCI 2Rypy 2Zp 1000 Vper 0 9V Ro 20Q www xilinx com ug190_6_93_041206 Figure 6 85 SSTL18 Il T DCI 1 8V Split Thevenin Termination Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Differential Termination DIFF_TERM Attribute Virtex 5 FPGA IOBs provide a 100Q differential termination across the input differential receiver terminals This attribute is used in conjunction with LVDS 25 LVDSEXT_25 HT 25 and RSDS 25 HT 25 replaces the Virtex 4 FPGA LDT 25 standard The on chip input differential termination in Virtex 5 devices provides major advantages over the external resistor by removing the stub at the receiver completely and therefore greatly improving signal integrity e Consumes less power than DCI termination e Does not use VRP VRN pins DCI The Vcco of the I O bank must be connected to 2 5V 5 to provide 1002 of effective differential termination DIFF TERM is only available for inputs and can only be used with a bank voltage of Veco 2 5V The Differential Termination Attribute DIFF TERM section outlines using this feature LVDS and Extended LVDS Low Voltage Differential Signaling Low Voltage Differential Signaling LVDS is a very popul
255. edge and Tckxx Hold Time after clock edge 3 Parameter includes AI BI CI DI configured as a data input DI2 or two bits with a common shift Slice SRL Timing Characteristics Figure 5 30 illustrates the timing characteristics of a 16 bit shift register implemented in a Virtex 5 FPGA slice a LUT configured as an SRL CLK Write Enable WE Shift In DI Address A B C D Data Out A B C D MSB MC31 DMUX ugi 90 5 30 050506 Figure 5 30 Slice SRL Timing Characteristics 206 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Slice Timing Models Clock Event 1 Shift In During a write Shift In operation the single bit content of the register at the address on the A B C D inputs is changed as data is shifted through the SRL The data written to this register is reflected on the A B C D outputs synchronously if the address is unchanged during the clock event If the A B C D inputs are changed during a clock event the value of the data at the addressable output A B C D outputs is invalid e At time T s before clock event 1 the write enable signal WE becomes valid High enabling the SRL for the Write operation that follows e At time Tps before clock event 1 the data becomes valid 0 at the DI input of the SRL and is reflected on the A B C D output after a delay of length Tggg after clock event 1 Since the address 0 is specified at clock ev
256. edge coincide with the input clock whenever mathematically possible For example M 9 and D 5 multiply the frequency by 1 8 and the output rising edge is coincident with the input rising edge after every fifth input period or after every ninth output period Phase Shifting The DCM allows coarse and fine grained phase shifting The coarse phase shifting uses the 90 180 and 270 phases of CLK0 to make CLK90 CLK180 and CLK270 clock outputs The 180 phase of CLK2X and CLKFX provide the respective CLK2X180 and CLKFX180 clock outputs There are also four modes of fine grained phase shifting fixed variable positive variable center and direct modes Fine grained phase shifting allows all DCM output clocks to be phase shifted with respect to CLKIN while maintaining the relationship between the coarse phase outputs With fixed mode a fixed fraction of phase shift can be defined during configuration and in multiples of the clock period divided by 256 Using the variable positive and variable center modes the phase can be dynamically and repetitively moved forward and backwards by 1 256 of the clock period With the direct mode the phase can be dynamically and repetitively moved forward and backwards by the value of one DCM TAP See the DCM Timing Parameters section in the Virtex 5 FPGA Data Sheet Dynamic Reconfiguration There is a bus connection to the DCM to change DCM attributes without reconfiguring the rest of the device For mor
257. ee bits to the left On this same edge of CLKDIV the first word sampled is presented to Q1 O4 without any realignment The actual bits from the input stream that appear at the Q1 O4 outputs during this cycle are shown in A of Figure 8 13 364 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES A Q1 Q4 During Clock Event 3 No Bitslip Q1 Q4 During Clock Event 4 1st Bitslip Rotate 1 Bit to Right Q1 Q4 During Clock Event 5 2nd Bitslip Rotate 3 Bits to Left ug 90 c8 13 100307 Figure 8 13 Bits from Data Input Stream D of Figure 8 12 Clock Event 4 The first two bits of the fourth word CD have been sampled into the input side registers of the ISERDES On this same edge of CLKDIV the second word sampled is presented to Q1 Q4 with one bit shifted to the right The actual bits from the input stream that appear at the Q1 Q4 outputs during this cycle are shown in B of Figure 8 13 The realigned bits on Q1 O4 are sampled into the FPGA logic on the CLKDIV domain The total latency from when the ISERDES captures the asserted Bitslip input to when the realigned ISERDES outputs Q1 O4 are sampled by CLKDIV is two CLKDIV cycles Clock Event 5 The third word sampled is presented to Q1 O4 with three bits shifted to the left The actual bits from the input stream that appear at the Q1 O4 outputs during this cycle are shown in C of Figure 8 13
258. efault Attribute Name Description Value Value BITSLIP_ENABLE Allows the user to use the Bitslip submodule Boolean TRUE or FALSE FALSE or bypass it See BITSLIP_ENABLE Attribute DATA_RATE Enables incoming data stream to be String SDR or DDR DDR processed as SDR or DDR data See DATA_RATE Attribute DATA_WIDTH Defines the width of the serial to parallel Integer 2 3 4 5 6 7 8 or 10 4 converter The legal value depends on the If DATA RATE DDR value is DATA RATE attribute SDR or DDR See limited to 4 6 8 or 10 DATA WIDTH Attribute If DATA RATE SDR value is limited to 2 3 4 5 6 7 or 8 INTERFACE TYPE Chooses the ISERDES_NODELAY use String MEMORY or MEMORY model See INTERFACE TYPE Attribute NETWORKING NUM CE Defines the number of clock enables See Integer 1 or 2 2 NUM CE Attribute SERDES MODE Defines whether the ISERDES NODELAY String MASTER or SLAVE MASTER module is a master or slave when using width expansion See SERDES MODE Attribute BITSLIP ENABLE Attribute The BITSLIP ENABLE attribute enables the Bitslip submodule The possible values are TRUE and FALSE default BITSLIP ENABLE must be set to TRUE when INTERFACE TYPE is NETWORKING and FALSE when INTERFACE TYPE is MEMORY When set to TRUE the Bitslip submodule responds to the BITSLIP signal When set to FALSE the Bitslip submodule is bypassed See BITSLIP Submodule D
259. elay mode fixed 321 variable 321 zero hold time 321 IDELAYCTRL 333 increment decrement 324 primitive 322 switching characteristics 326 timing 326 IDELAYCTRL 333 instantiating 336 338 RDY port 337 location 335 primitive 334 REFCLK 333 339 ILOGIC 215 314 IDDR 315 SR 314 switching characteristics 320 timing 318 IOB 215 defined 216 IOBUF 232 PULLUP PULLDOWN KEEPER 235 IOBUFDS 233 IODELAY 321 DATAIN 323 DATAOUT 323 IDATAIN 323 ODATAIN 323 ports 323 ISERDES 349 defined 349 attributes 354 bitslip 349 352 363 BITSLIP ENABLE attribute 354 IDELAY IDELAYCTRL 333 ports 351 368 primitive 350 serial to parallel converter 349 358 switching characteristics 359 timing models 359 width expansion 357 L LDT See HyperTransport 293 LVCMOS 238 defined 238 LVDCI 240 defined 240 LVDCI DV2 241 source termination 300 LVDS 291 defined 291 LVDS 25 DCI 292 LVPECL 294 defined 294 LVTTL 236 defined 236 M multirate FIFO 113 138 N NO CHANGE mode 116 O OBUF 231 OBUFDS 233 OBUFT 232 PULLUP PULLDOWN KEEPER 235 OBUFTDS 233 ODDR 341 clock forwarding 343 OPPOSITE EDGE mode 342 ports 343 primitive 343 SAME EDGE mode 342 OLOGIC 215 340 timing 344 OSERDES 366 parallel to serial converter 366 switching characteristics 373 timing 373 374 P parallel to serial converter 366 DDR 366 SDR 366 PCI 244 PFDM 309 PLL allocation in device 44 PSCLK 48 R READ FIRST mode 116 REFCLK
260. ements EN must be inactive disabled 134 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com XILINX Block RAM Timing Model Block RAM Timing Characteristics The timing diagram in Figure 4 14 describes a single port block RAM in write first mode without the optional output register The timing for read first and no change modes are similar For timing using the optional output register an additional clock latency appears at the DO pin These waveforms correspond to latch mode when the optional output pipeline register is not used 1 i 2 i 3 4 5 CLK rnan OE AYN H TRCCK ADDR ADDR Xa XX CLE OXF I TRDCK DI DI 0000 am 1RCKO DO DO 0101 j TRCCK EN EN A N TRcCK sSR ok SSR N TRcCK wE WE 7 N Disabled Read Write Read Reset Disabled Write Mode WRITE FIRST SRVAL 0101 ugi90 4 13 022207 Figure 4 14 Block RAM Timing Diagram At time 0 the block RAM is disabled EN enable is Low Clock Event 1 Read Operation During a read operation the contents of the memory at the address on the ADDR inputs remain unchanged e Tncck Appn before clock event 1 address 00 becomes valid at the ADDR inputs of the block RAM e At time TrccK EN before clock event 1 enable is asserted High at the EN input of the block RAM enabling the memory for the READ operation that follows e At time Tncko po after clock event 1 the contents of the memory at address 00
261. ent 1 the data on the DI input is reflected at A B C D output because it is written to register 0 Clock Event 2 Shift In e Attime Tps before clock event 2 the data becomes valid 1 at the DI input of the SRL and is reflected on the A B C D output after a delay of length Tpgg after clock event 2 Since the address 0 is still specified at clock event 2 the data on the DI input is reflected at the D output because it is written to register 0 Clock Event 3 Shift In Addressable Asynchronous READ All Read operations are asynchronous to the CLK signal If the address is changed between clock events the contents of the register at that address are reflected at the addressable output A B C D outputs after a delay of length Ty o propagation delay through a LUT e At time Tps before clock event 3 the data becomes valid 1 at the DI input of the SRL and is reflected on the A B C D output Tpgg time after clock event 3 e The address is changed from 0 to 2 The value stored in register 2 at this time is a 0 in this example this was the first data shifted in and it is reflected on the A B C D output after a delay of length Tjj o Clock Event 32 MSB Most Significant Bit Changes At time Tggg after clock event 32 the first bit shifted into the SRL becomes valid logical 0 in this case on the DMUX output of the slice via the MC31 output of LUT A SRL This is also applicable to the AMUX BMUX CMUX DMUX and COUT outputs at ti
262. er modes add the appropriate latencies as shown in Figure 7 4 page 317 346 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX OLOGIC Resources ug190 7 24 041106 Figure 7 29 OLOGIC ODDR 3 State Register Timing Characteristics Clock Event 1 At time Torceck before Clock Event 1 the 3 state clock enable signal becomes valid High at the TCE input of the 3 state ODDR register enabling them for incoming data Care must be taken to toggle the TCE signal of the 3 state ODDR between the rising edges and falling edges of CLK as well as meeting the register setup time relative to both clock edges At time Torck before Clock Event 1 rising edge of CLK the 3 state signal T1 becomes valid high at the T1 input of 3 state register and is reflected on the TO output at time Tocko after Clock Event 1 Clock Event 2 At time Torc before Clock Event 2 falling edge of CLK the 3 state signal T2 becomes valid high at the T2 input of 3 state register and is reflected on the TO output at time Tocko after Clock Event 2 no change at the TQ output in this case Clock Event 9 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 At time Tosgcy before Clock Event 9 rising edge of CLK the SR signal configured as synchronous reset in this case becomes valid high resetting 3 state Register reflected at the TQ output at time Tao after Clock Event 9 no change at the TQ output in this case
263. eries resistor must be connected to both transmitters DIFF SSTL2 Il DCI DIFF SSTL18 Il DCI Differential SSTL 2 5V and 1 8V Class II pairs complementary single ended SSTL II type drivers with a differential receiver including on chip differential termination DCI can be used for unidirectional and bidirectional links SSTL2 II T DCI SSTL18 Il T DCI SSTL2 II T DCIand SSTL18 II T DCI provide on chip split thevenin termination powered from Vcco that creates an equivalent termination voltage of Vcco 2 when these standards are 3 stated When not 3 stated these two standards do not have parallel termination but when invoked they have an internal series resistor 25 Qat 2 5V and 20 Qat 1 8V www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards SSTL2 Class 2 5V Figure 6 66 shows a sample circuit illustrating a valid termination technique for SSTL2 Class I External Termination ion Va 1 25V IOB SSTL2 SSTL2 Rg 250 Rp 29 500 l Bon OS E Veep 1 25V EM Ari v cerea aj L IOB IOB Veco 25V 2Rypp 2Zg 1000 SSTL2 DCI SSTL2 1 DCI B3 920 514 Vper 1 25V Ro 25Q ner E 2Rypy 2Zg 1000 ugi 90 6 63 030506 Figure 6 66 SSTL2 Class Termination Virtex 5 FPGA User Guide www xilinx com 273 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resour
264. ers i ss ke e be e e REO ned eae ee 206 Slice SRL Timing Characteristics eo essre sead seras eee 206 Slice Carry Chain Timing Model and Parameters 000000 208 Slice Carry Chain Timing Characteristics 0 6 208 CLB Primitives eere euet e eren EREMO ores RR Roe NR RR PR Redi eR s 209 Distributed RAM Primitives 0 0 0 0 e n ene n eens 209 Port Signals 2555 dotes ote eue ma Met lence die te aig edited waste Rea ds pd 210 Shift Registers SRLs Primitive eeeeee e 211 Port Signals dd rete pev oO CR erar ees uta alter ede aside d baer 211 Other Shift Register Applications lssssseeseeesee eee 212 Synchronous Shift Registers eeclesie en 212 Static Length Shift Registers cies nn 212 Multiplexer Primitives 2 0 6 e 213 Port Signals etre Sah asca ge eg de I a eee ea e puedes ad dee dete tra este 213 Carry Chain Primitive see erect eee eee prede eei eda e ka eon 213 Port Signals iste E det acetals Meet ehe beendet ed Seded 214 Chapter 6 SelectlO Resources VO Tile Overview e rer rene beber eet ee ue de eor ess dit 215 SelectIO Resources Introduction 0 cece eee eee eee eee 216 SelectIO Resources General Guidelines 0 scence eee ee 216 Virtex 5 FPGA I O Bank Rules 0 0 cee eens 217 Reference Voltage Vggp Pins 2 6 nn 217 Output Drive Source Voltage Veco Pins eee eee 217 Virtex 5 FPGA Digitally Controlled Impeda
265. ersion of the input clock signal It reflects any instability on the input clock in the output waveform The DCM input clock requirements are specified in the Virtex 5 FPGA Data Sheet Once locked the DCM can tolerate input clock period variations of up to the value specified by CLKIN PER JITT DLL HF at high frequencies or CLKIN PER JITT DLL LF at low frequencies Larger jitter period changes can cause the DCM to lose lock indicated by the LOCKED output deasserting The user must then reset the DCM The cycle to cycle input jitter must be kept to less than CLKIN CYC JITT DLL LF in the low frequencies and CLKIN CYC JITT DLL HF for the high frequencies Input Clock Changes Changing the period of the input clock beyond the maximum input period jitter specification requires a manual reset of the DCM Failure to reset the DCM produces an unreliable LOCKED signal and output clock It is possible to temporarily stop the input clock and feedback clock with little impact to the deskew circuit as long as CLKFX or CLKFX180 is not used If the input clock is stopped and CLKFX or CLKFX180 is used the CLKFX or CLKFX180 outputs might stop toggling and DO 2 CLKFX stopped is asserted The DCM must be reset to recover from this event The DO 2 CLKFX stopped status is asserted 100 us after CLKFX is stopped CLKFX does not resume and DO 2 does not deassert until the DCM is reset In any other case the clock should not be stopped for
266. es DCM_TAP Changing the ratio of Vcc temperature results in a phase shift change proportional to the size of the DCM_TAP at the specific voltage and temperature Interaction of PSEN PSINCDEC PSCLK and PSDONE The variable and direct phase shift modes are controlled by the PSEN PSINCDEC PSCLK and PSDONE ports In addition a phase shift overflow DO 0 status indicates when the phase shift counter has reached the end of the phase shift delay line or the maximum value 255 for variable mode 1023 for direct mode After the DCM locks the initial phase in the VARIABLE POSITIVE and VARIABLE CENTER modes is determined by the PHASE SHIFT value The initial phase in the DIRECT mode is always 0 regardless of the value specified by the PHASE SHIFT attribute The phase of the DCM output clock is incremented decremented according to the interaction of PSEN PSINCDEC PSCLK and PSDONE from the initial or dynamically reconfigured phase PSEN PSINCDEC and PSDONE are synchronous to PSCLK When PSEN is asserted for one PSCLK clock period a phase shift increment decrement is initiated When PSINCDEC is High an increment is initiated and when PSINCDEC is Low a decrement is initiated Each increment adds to the phase shift of DCM clock outputs by 1 256 of the CLKIN period Similarly each decrement decreases the phase shift by 1 256 of the CLKIN period PSEN must be active for exactly one PSCLK period otherwise a single phase shift increment d
267. es For more information a Constraints Guide is available on the Xilinx web site with syntax examples and VHDL Verilog reference code This guide is available inside the Software Manuals at http www support xilinx com support software manuals htm Location Constraints The location constraint LOC must be used to specify the I O location of an instantiated I O primitive The possible values for the location constraint are all the external port identifiers e g A8 M5 AM6 etc These values are device and package size dependent The LOC attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME LOC EXTERNAL PORT IDENTIFIER Example INST MY IO LOC R7 IOSTANDARD Attribute The IOSTANDARD attribute is available to choose the values for an I O standard for all I O buffers The supported I O standards are listed in Table 6 39 The IOSTANDARD attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME IOSTANDARD IOSTANDARD VALUE gt The IOSTANDARD default for single ended I O is LVCMOS25 for differential I Os the default is LVDS 25 Output Slew Rate Attributes A variety of attribute values provide the option of choosing the desired slew rate for single ended I O output buffers For LVTTL and LVCMOS output buffers OBUF OBUFT and IOBUF the desired slew rate can be specified with the SLEW attribute The allowed value
268. es to Table 7 10 page 325 Revised Figure 7 9 page 326 Removed Table 7 12 Generating Reference Clock From DCM and updated REFCLK section in IDELAYCTRL Ports on page 334 Clarified introduction in IDELAYCTRL Locations page 335 Changed ODDR Clock Forwarding page 343 Chapter 8 Updated SR and O in Figure 8 2 and Table 8 1 page 351 Updated the entire section for BITSLIP Submodule page 362 Fixed typographical errors in Figure 8 14 page 366 12 11 07 3 2 Chapter 1 Revised description in Clock Gating for Power Savings page 22 Added the XC5VLX20T XC5VLX155 and XC5VLX155T devices to Table 1 5 Chapter 2 Added the XC5VLX20T XC5VLX155 and XC5VLX155T devices to Table 2 1 Chapter 3 Revised Clock Network Deskew page 90 Removed note 2 and revised descriptions of CLKFBOUT and DEN in Table 3 3 page 93 Revised allowed value of CLKOUT 0 5 _PHASE and CLKFBOUT_MULT description in Table 3 4 page 95 Revised Figure 3 13 and Figure 3 14 including waveforms Chapter 5 Added the XC5VLX20T XC5VLX155 and XC5VLX155T devices to Table 5 2 Chapter 6 Clarified discussion of cascading across CMT tiles in DCI Cascading Changed the split termination to Vyr 0 9V in Figure 6 83 page 289 Chapter 7 Added to the descriptions of the HIGH PERFORMANCE MODE Attribute and the SIGNAL PATTERN Attribute page 326 including Table 7 10 Revised description in Instantiating IDELAYCTRL Without LOC Constraints
269. esistors The LVDCI 18 SSO limit for 50 Qimpedance is first taken from Table 6 40 The SSO limit for LVDCI 18 at 50 Qis 11 SSO per Vcco GND pin pair Therefore the SSO limit for LVDCI 18 at 65 Qis SSO Limit LVDCI 18 at 65 Q 65 Q 50 Q x 11 14 3 Bank O Bank 0 in all devices contains only configuration and dedicated signals Since there is no user I O in Bank 0 no SSO analysis is necessary for this bank 312 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Chapter 7 SelectIO Logic Resources Introduction This chapter describes the logic directly behind the I O drivers and receivers covered in Chapter 6 SelectIO Resources Virtex 5 FPGAs contain all of the basic I O logic resources from Virtex II Virtex II Pro FPGAs These resources include the following Combinatorial input output 3 state output control Registered input output Registered 3 state output control Double Data Rate DDR input output DDR output 3 state control In addition Virtex 5 FPGAs implement the following architectural features that are also supported in Virtex 4 FPGAs Virtex 5 FPGA User Guide IODELAY provides users control of an adjustable fine resolution delay element SAME_EDGE output DDR mode SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode www xilinx com 313 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX ILOGIC Resources The ILOGIC block shown in Fi
270. fference Thus the DCM output clock compensates for the delay in the clock distribution network effectively removing the delay between the source clock and its loads The size of each intrinsic delay element is a DCM_TAP see the AC Characteristics table in the Virtex 5 FPGA Data Sheet Figure 2 3 illustrates a simplified DLL circuit Variable Delay Line Figure 2 83 Simplified DLL Circuit Clock Distribution Network CLKOUT CLKIN ugi 90 2 03 032506 To provide the correct clock deskew the DCM depends on the dedicated routing and resources used at the clock source and feedback input An additional delay element see Deskew Adjust is available to compensate for the clock source or feedback path The Xilinx ISE tools analyze the routing around the DCM to determine if a delay must be Virtex 5 FPGA User Guide www xilinx com 59 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX inserted to compensate for the clock source or feedback path Thus using dedicated routing is required to achieve predictable deskew Input Clock Requirements The clock input of the DCM can be driven either by an IBUFG IBUFGDS IBUF BUFGMUx or a BUFGCTRL Since there is no dedicated routing between an IBUF and a DCM clock input using an IBUF causes additional input delay that is not compensated by the DCM and performance can not be guaranteed The DCM output clock signal is essentially a delayed v
271. fixing the dimensions of the clock region larger Virtex 5 devices can have more clock regions As a result Virtex 5 devices can support many more multiple clock domains than previous FPGA architectures Table 1 5 shows the number of clock regions in each Virtex 5 device The logic resources in the center column CMTS IOBs etc are located in the left clock regions The CMTs if used utilize the global clocks in the left regions as feedback lines Up to four CMTs can be in a specific region If used in the same region IDELAYCTRL uses another global clock in that region See Chapter 2 Clock Management Technology XC5VLX30 has 8 Clock Regions XC5VLX330 has 24 Clock Regions 10 CLBs 10 CLBs All clock regions span half the die All clock regions are 20 CLBs tall 10 CLBs above and 10 CLBs below a horizontal clock line 34 T HERE MEE HERE p a ee De f p ee Center Column Logic Resources ugi90 1 17 042406 Figure 1 17 Clock Regions www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Global Clocking Resources Table 1 5 Virtex 5 FPGA Clock Regions Device Number of Clock Regions Notes XC5VLX30 8 XC5VLX50 12 XC5VLX85 12 XC5VLX110 16 XC5VLX155 16 XC5VLX220 16 XC5VLX330 24 XC5VLX20T 6 There are 3 regions on each side of the device There are no BUFRs on the
272. following types of on chip terminations 1 Input termination to Vcco Single Termination 2 Input termination to Vcco 2 Split Termination Thevenin equivalent For bidirectional operation both ends of the line can be DCI terminated regardless of direction 1 Driver with termination to Vcco Single Termination 2 Driver with termination to Vcco 2 Split Termination Thevenin equivalent Alternatively bidirectional point to point lines can use controlled impedance drivers with 3 state buffers on both ends Controlled Impedance Driver Source Termination Some I O standards such as LVCMOS must have a drive impedance matching the characteristic impedance of the driven line DCI can provide controlled impedance output drivers to eliminate reflections without an external source termination The impedance is set by the external reference resistors with resistance equal to the trace impedance The DCI I O standards supporting the controlled impedance driver are LVDCI 15 LVDCI 18 LVDCI 25 LVDCI 33 HSLVDCI 15 HSLVDCI 18 HSLVDCI 25 and HSLVDCI 33 Figure 6 6 illustrates a controlled impedance driver in a Virtex 5 device pee E L pj Zo UG190 6 04 012706 Figure 6 6 Controlled Impedance Driver www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines Controlled Impedance Driver with Half Impedance Source Termination DCI also provides drivers wi
273. g Model suse eese 133 Block RAM Timing Parameters sssseeseesseeee nee eens 134 Block RAM Timing Characteristics nananana annann eee 135 Clock Event l esei iei eie Sent pretesa edere deed qe bet oie gar how Med Re NE Som taste 135 Clock Event 2 2er ee e uci esce euo oe bd oe P d wc NO e m 136 Clock EV CI ase dote acre dud tee eee Ree Er es PA et Ra S RR e Ree 136 Clock Ev nt S iis duae axe area ee vedo e e Er d CE P ea de ee dea ee 136 Block RAM Timing Model 0 0 00 cece e 137 Block RAM Retargeting ssssssssssssesse rrur rrur rrerrr en 138 Built in FIFO SuppotE iodeese uase dat ea Aa eie ace rode rt e dece 138 Multirate EIEQ css eben Ibex ace p E CER RC CUP IU COPAS RE 138 5ynchronous FIFO elsi ua e e ee be eA 3 x EY wx riga rad ue ee dg 139 Synchronous FIFO Implementations 6 n 140 FIFO Architecture a Top Level View 00 000 c cece eee 141 FIFO Primitives 000 0 00000 ccc eee eee rs 141 FIFO Port Descriptions uussssesessssssseses esI 142 FIFO Operations s6s5d00540se 2senedstevtereeseehesnegeenedasasaau dp dedans 143 Reset lcicseiducue ba eig ba By Sch bo Ra GEN REED BSR Bb Ba an ea RAC 143 Operating Mode iise ii e ged RR Ved ee PAGS ed ese REP EE EP oe ER 143 Standard Mode gag Pee RSE HOES SEES EES RO E RR DS 143 First Word Fall Through FWFT Mode ssesseeeeee rnnr rn nrnn 143 Status Flaps coriis iced ee egeta ds ee 144 E
274. g Templates The Libraries Guide includes templates for instantiation of the ODDR module in VHDL and Verilog OLOGIC Timing Models This section discusses all timing models associated with the OLOGIC block Table 7 15 describes the function and control signals of the OLOGIC switching characteristics in the Virtex 5 FPGA Data Sheet Table 7 15 OLOGIC Switching Characteristics Symbol Description Setup Hold Topck Tockp D1 D2 pins Setup Hold with respect to CLK ToocrecKk TOCKOCE OCE pin Setup Hold with respect to CLK TosRcKk TocksR SR REV pin Setup Hold with respect to CLK Torck Tockr T1 T2 pins Setup Hold with respect to CLK Torcrck TockTCE TCE pin Setup Hold with respect to CLK Clock to Out Tocko CLK to OQ TO out Timing Characteristics Figure 7 26 illustrates the OLOGIC output register timing 1 2 3 4 5 i Topck D1 f N S ToOCECK OCE A s s Sa d Ne ae I Tocko ug190 7 21 041206 Figure 7 26 OLOGIC Output Register Timing Characteristics 344 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX OLOGIC Resources Clock Event 1 At time Toocrck before Clock Event 1 the output clock enable signal becomes valid high at the OCE input of the output register enabling the output register for incoming data At time Topcx before Clock Event 1 the output signal becomes valid high at the D1 input of
275. gister primitive does not use the register available in the same slice To implement a fully synchronous read and write shift register output pin Q must be connected to a flip flop Both the shift register and the flip flop share the same clock as shown in Figure 5 34 SRLC32G FF Synchronous Output Address CE Write Enable CLK UG190 5 34 050506 Figure 5 34 Synchronous Shift Register This configuration provides a better timing solution and simplifies the design Because the flip flop must be considered to be the last register in the shift register chain the static or dynamic address should point to the desired length minus one If needed the cascadable output can also be registered in a flip flop Static Length Shift Registers The cascadable 32 bit shift register implements any static length mode shift register without the dedicated multiplexers F7AMUX F7BMUX and F8MUX Figure 5 35 illustrates a 72 bit shift register Only the last SRLC32E primitive needs to have its address inputs tied to 0500111 Alternatively shift register length can be limited to 71 bits address tied to 0000110 and a flip flop can be used as the last register In an SRLC32E primitive the shift register length is the address input 1 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Primitives OUT 72 bit SRL OUT 72 bit SRL Sorio UG190 5 35 050
276. gure 7 1 DDLY D c REV ug190 7 01 050906 Figure 7 1 ILOGIC Block Diagram ILOGIC can support the following operations Edge triggered D type flip flop e IDDR mode OPPOSITE EDGE or SAME EDGE or SAME EDGE PIPELINED See Input DDR Overview IDDR page 315 for further discussion on input DDR e Level sensitive latch e Asynchronous combinatorial All ILOGIC block registers have a common clock enable signal CE1 that is active High by default If left unconnected the clock enable pin for any storage element defaults to the active state All ILOGIC block registers have a common synchronous or asynchronous set and reset SR and REV signals The set reset input pin SR forces the storage element into the state specified by the SRVAL attributes When using SR a second input REV forces the storage element into the opposite state The reset condition predominates over the set condition Table 7 1 and Table 7 2 describe the operation of SR in conjunction with REV Table 7 1 Truth Table when SRVAL 0 Default Condition SR REV Function 0 0 NOP 0 1 Reset 1 0 Set 1 1 Reset 314 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX ILOGIC Resources Table 7 2 Truth Table when SRVAL 1 SR REV Function 0 0 NOP 0 1 Set 1 0 Reset 1 1 Reset The SRVAL attributes can be set ind
277. h At time Tpccko o after time event 2 output O uses input I1 This occurs after a High to Low transition of I0 followed by a High to Low transition of I1 is completed At time Tpccck cr before time event 3 CE is asserted Low The clock output is switched Low and kept at Low after a High to Low transition of I1 is completed www xilinx com 33 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX Clock Tree and Nets GCLK Virtex 5 clock trees are designed for low skew and low power operation Any unused branch is disconnected The clock trees also manage the load fanout when all the logic resources are used All global clock lines and buffers are implemented differentially This facilitates much better duty cycles and common mode noise rejection In the Virtex 5 architecture the pin access of the global clock lines are not limited to the logic resources clock pins The global clock lines can access other pins in the CLBs without using local interconnects Applications requiring a very fast signal connection and large load fanout benefit from this architecture Clock Regions Virtex 5 devices improve the clocking distribution by the use of clock regions Each clock region can have up to ten global clock domains These ten global clocks can be driven by any combination of the 32 global clock buffers The dimensions of a clock region are fixed to 20 CLBs tall 40 IOBs and spanning half of the die Figure 1 17 By
278. h Termination to Vcco 2 without DCI DCI can provide output termination to Vcco 2 using split termination DCI only controls the impedance of the termination but not the driver Both HSTL and SSTL standards need 50 Q external reference resistors The DCI output standards supporting drivers with split termination are shown in Table 6 2 Table 6 2 DCI Output Standards Supporting Split Termination HSTL II DCI DIFF HSTL II DCI SSTL2 II DCI DIFF SSTL2 II DCI HSTL II DCI 18 DIFF HSTL II DCI 18 SSTL18 II DCI DIFF SSTL18 II DCI 226 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines Figure 6 15 illustrates a driver with split termination inside a Virtex 5 device IOB Vcco 2R Q Zo 2R Virtex 5 DCI UG190_6_13_021206 Figure 6 15 Driver with Termination to Vcco 2 Using DCI Split Termination DCI in Virtex 5 Device I O Standards DCI works with single ended I O standards DCI supports the standards shown in Table 6 3 Table 6 3 VWirtex 5 Device DCI I O Standards LVDCI HSTL I DCI DIFF HSTL I DCI HSTL III DCI SSTL2 I DCI DIFF SSTL2 I DCI HSLVDCI HSTL I DCI 18 DIFF HSTL I DCI 18 HSTL III DCI 18 SSTLI2 II DCI DIFF SSTL2 II DCI LVDCI DV2 HSIL II DCI DIFF HSTL II DCI HSTL IV DCI SSTL18 I DCI DIFF SSTL18 I DCI GTL DCI HSTL II DCI 18 DIFF HSTL IH DCI 18 HSTL IV DCI 18 SSTL18 II DCI DIFF SSTL18 Ill DCI GTLP DCI HSIL II
279. h port clocks occur simultaneously Virtex 5 FPGA User Guide There are no timing constraints when both ports perform a read operation When one port performs a write operation the other port must not write into the same location unless both ports write identical data When one port performs a write operation the write operation succeeds the other port can reliably read data from the same location if the write port is in READ_FIRST mode DATA_OUT on both ports will then reflect the previously stored data If the write port is in either WRITE FIRST or in NO CHANGE mode then the DATA OUT on the read port would become invalid unreliable The mode setting of the read port does not affect this operation www xilinx com 117 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Additional Block RAM Features in Virtex 5 Devices Optional Output Registers The optional output registers improve design performance by eliminating routing delay to the CLB flip flops for pipelined operation An independent clock and clock enable input is provided for these output registers As a result the output data registers hold the value independent of the input register operation Figure 4 5 shows the optional output register Address Register Memory D Q D Q DI Array Latches Register MEE common to WE both ports Write Read Latch IL Strobe Strobe JTL Enable JTL EN CLK Optional Inverter
280. hapter 1 Revised Global Clock Buffers page 23 to clarify single ended clock pins Changed the P and N I O designations in Figure 1 19 Chapter 4 Added Block RAM SSR in Register Mode page 131 and FIFO Architecture a Top Level View page 141 Revised the FIFO operations Reset page 143 description Chapter 6 Minor clarification edits Changed to N A from unused in Table 6 36 Table 6 37 and Table 6 38 Chapter 7 Minor edits to clarify IODELAY in this chapter Chapter 8 Small clarifications in ISERDES_NODELAY Ports on page 351 9 06 06 2 0 Added the LXT platform devices throughout document Chapter 1 Revised Figure 1 22 page 41 Updated Clock Capable I O on page 36 Chapter 2 Updated Output Clocks on page 61 Chapter 4 Clarified the rules regarding FULL and EMPTY flags on page 138 Chapter 5 Revised Storage Elements on page 176 Chapter 6 Differential Termination Attribute on page 235 is updated for the latest syntax and settings Replaced the link to the SSO calculator 10 12 06 2 1 Added System Monitor User Guide reference in the Preface Added XC5VLX85T to Table 1 5 Table 2 1 and Table 5 2 Chapter 3 Revised Figure 3 1 Chapter 4 Added cascade to Table 4 7 page 124 Revised ADDR in Figure 4 9 page 122 Removed scrub mode in Built in Error Correction section Chapter 5 Revised Figure 5 22 page 195 02 02 07 3 0 Added the three SXT devices and the
281. hat data from the CIN input of the slice must be stable at the D input of the slice sequential elements configured as a flip flop Notes 1 Txxcx Setup Time before clock edge and Tckxx Hold Time after clock edge Slice Carry Chain Timing Characteristics Figure 5 31 illustrates the timing characteristics of a slice carry chain implemented in a Virtex 5 FPGA slice T CIN CINCK DATA EP SR RESET K Tcko l lt Tcko AQ BQ CQ DQ OUT ug190_5_31_050506 Figure 5 31 Slice Carry Chain Timing Characteristics 208 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Primitives e At time Tcmcg before clock event 1 data from CIN input becomes valid high at the D input of the slice register This is reflected on any of the AO BO CO DO pins at time Tcxo after clock event 1 e At time Tsrcx before clock event 3 the SR signal configured as synchronous reset becomes valid high resetting the slice register This is reflected on any of the AQ BO CQ DO pins at time Tcko after clock event 3 CLB Primitives More information on the CLB primitives are available in the software libraries guide Distributed RAM Primitives Seven primitives are available from 32 x 2 bits to 256 x 1 bit Three primitives are single port RAM two primitives are dual port RAM and two primitives are quad port RAM as shown in Table 5 11 Table 5
282. he D1 input of an OSERDES but the same bit A emerges from the ISERDES NODELAY block at the Q6 output In other words D1 is the least significant input to the OSERDES while Q6 is the least significant output of the ISERDES NODELAY block When width expansion is used D1 of the master OSERDES is the least significant input while O4 of the slave ISERDES NODELAY block is the least significant output www xilinx com 351 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX OSERDES E 5 ISERDES 5 5 D O 8 Data Bits C 9 9 9 amp 6 amp 65 9 5 9 CLKDIV TX CLK TX CLK RX CLKDIV RX UG190 8 O3 100307 Figure 8 83 Bit Ordering on Q1 Q6 Outputs of ISERDES NODELAY Ports Bitslip Operation BITSLIP The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted active High Subsequently the data seen on the Q1 to Q6 output ports will shift as in a barrel shifter operation one position every time Bitslip is invoked DDR operation is different from SDR See BITSLIP Submodule for more details Clock Enable Inputs CE1 and CE2 Each ISERDES NODELAY block contains an input clock enable module Figure 8 4 ICE To ISERDES Input Registers CE1 D Q RST AR CLKDIV a arce oov ce CE2 RST CLKDIV UG190 8 04 110707 Figure 8 4 Input Clock Enable Module When NUM CE 1 the CE2 input is not used and the CE1 input
283. he master ISERDES to MASTER and the slave ISERDES to SLAVE See SERDES MODE Attribute 3 The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the MASTER TheSLAVE only uses the ports Q3 to Q6 as an input 5 DATA WIDTH applies to both MASTER and SLAVE in Figure 8 7 358 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES ISERDES Latencies When the ISERDES interface type is MEMORY the latency through the OCLK stage is one CLKDIV cycle However the total latency through the ISERDES depends on the phase relationship between the CLK and the OCLK clock inputs When the ISERDES interface type is NETWORKING the latency is two CLKDIV cycles See Figure 8 12 page 364 and Figure 8 13 page 365 for a visualization of latency in networking mode The extra CLKDIV cycle of latency in networking mode compared to memory mode is due to the Bitslip submodule ISERDES Timing Model and Parameters Table 8 4 describes the function and control signals of the ISERDES switching characteristics in the Virtex 5 FPGA Data Sheet Table 8 4 ISERDES Switching Characteristics Symbol Description Setup Hold for Control Lines TisccK_BITSLIP Trsckc BrTsLIP BITSLIP pin Setup Hold with respect to CLKDIV Tiscck ck Trsckc cr CE pin Setup Hold with respect to CLK for CE1 Tiscck_ce Trsckc cr CE pin Setup Hold with respect to C
284. he next 10 ns CLK90 25 MHz 0 8 Use CLK180 with PHASE SHIFT 0 63 for the next 10 ns CLK1 80 25 MHz 5 o O A X Use CLK270 with PHASE SHIFT 0 63 cLk270 25 mH for the last 10 ns ug0190 2 05 032506 Figure 2 5 Fixed Phase Shift Examples In variable mode the phase shift factor is changed by activating PSEN for one period of PSCLK At the PSCLK clock cycle where PSEN is activated the level of PSINCDEC input determines whether the phase shift increases or decreases A High on PSINCDEC increases the phase shift and a Low decreases the phase shift After the deskew circuit increments or decrements the signal PSDONE is asserted High for a single PSCLK cycle This allows the next change to be performed The user interface and the physical implementation are different The user interface describes the phase shift as a fraction of the clock period N 256 The physical implementation adds the appropriate number of buffer stages each DCM_TAP to the clock delay The DCM_TAP granularity limits the phase resolution at higher clock frequencies All phase shift modes with the exception of DIRECT mode are temperature and voltage adjusted Hence a Vcc or temperature adjustment does not change the phase shift The DIRECT phase shift is not temperature or voltage adjusted since it directly controls 66 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Design Guidelin
285. hed to them The naming convention for IDELAYCTRL placement coordinates is different from the convention used in naming CLB locations This allows LOC properties to transfer easily from array to array There are two methods of attaching LOC properties to IDELAYCTRL instances 1 Insert LOC constraints in a UCF file 2 Embed LOC constraints directly into HDL design files Inserting LOC Constraints in a UCF File The following syntax is used for inserting LOC constraints in a UCF file INST instance name LOC IDELAYCTRL_X Y Embedding LOC Constraints Directly into HDL Design Files The following syntax is used to embed LOC constraints into a Verilog design file synthesis attribute loc of instance name is IDELAYCTRL_X Y0 In VHDL code the LOC constraint is described with VHDL attributes Before it can be used the constraint must be declared with the following syntax attribute loc string Once declared the LOC constraint can be specified as attribute loc of instance name label is IDELAYCTRL_X YO The Libraries Guide includes VHDL and Verilog use model templates for instantiating IDELAYCTRL primitives with LOC constraints The circuitry that results from instantiating the IDELAYCTRL components is shown in Figure 7 20 338 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY REFCLK e REFCLK RDY rdy 1 IDELAYCTRL_1 T rst 1 REFCLK RDY r
286. hin the ILOGIC block saving CLB and clock resources and increasing performance These modes are implemented using the DDR CLK EDGE attribute The following sections describe each of the modes in detail OPPOSITE EDGE Mode A traditional input DDR solution or OPPOSITE EDGE mode is accomplished via a single input in the ILOGIC The data is presented to the fabric via the output O1 on the rising edge of the clock and via the output Q2 on the falling edge of the clock This structure is similar to the Virtex II Virtex II Pro and Virtex 4 FPGA implementation Figure 7 2 shows the timing diagram of the input DDR using the OPPOSITE EDGE mode Virtex 5 FPGA User Guide www xilinx com 315 UG190 v4 4 December 2 2008 316 C CE D D1A D3A D5A D7A Chapter 7 SelectlO Logic Resources XILINX DIA D3A D5A ug190 7 02 041206 Figure 7 2 Input DDR Timing in OPPOSITE EDGE Mode SAME EDGE Mode In the SAME EDGE mode the data is presented into the FPGA fabric on the same clock edge However the data pair to be separated by one clock cycle This structure is similar to the Virtex II Virtex II Pro and Virtex 4 FPGA implementation Figure 7 3 shows the timing diagram of the input DDR using SAME EDGE mode In the timing diagram the output pairs Q1 and Q2 are no longer 0 and 1 Instead the first pair presented is pair Q1 and Q2 0 and don t care respectively followed by pair
287. hout the device and advanced clock domain control The deskew feature also functions as a clock mirror of a board level clock serving multiple devices This is achieved by driving the CLKO output off chip to the board and to other devices on the board and then bringing the clock back in as a feedback clock See the Application Examples section Taking advantage of the deskew feature greatly simplifies and improves system level design involving high fanout high performance clocks Clock Deskew Operation The deskew feature utilizes the DLL circuit in the DCM In its simplest form the DLL consists of a single variable delay line containing individual small delay elements or buffers and control logic The incoming clock drives the delay line The output of every delay element represents a version of the incoming clock CLKIN delayed at a different point The clock distribution network routes the clock to all internal registers and to the clock feedback CLKFB pin The control logic contains a phase detector and a delay line selector The phase detector compares the incoming clock signal CLKIN against a feedback input CLKFB and steers the delay line selector essentially adding delay to the DCM output until the CLKIN and CLKFB coincide putting the two clocks 360 out of phase thus in phase When the edges from the input clock line up with the edges from the feedback clock the DCM achieves a lock The two clocks have no discernible di
288. ibi i HSTLII_ 500 A 500 X Zo Dq 1 Vq 0 9V Vtr 0 9V DIFF HSTL Il 18 dni x End 500 5 2EB i DIFF_HSTL_Il_18 E S ugi90 6 57 030306 Figure 6 59 Differential HSTL 1 8V Class II Bidirectional Termination Virtex 5 FPGA User Guide www xilinx com 265 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 60 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with bidirectional DCI termination DCI IOB Veco 1 8V DIFF HSTL Il DCI 18 2Rygp 2Zo 1002 IOB Veco 1 8V DIFF HSTL Il DCI 18 2Rypp 2Zo 1002 2Rypy 2Zg 1000 DIFF HSTL Il DCI 18 x 4 2Rypy 2Zg 1000 DIFF HSTL Il DCI 18 1 8V DIFF HSTL Il DCI 18 Veco 7 1 8 2Rygp 2Zo 1002 2Rypy 2Zo 1002 Veco 1 8V cco DIFF HSTL Il DCI 18 2Rypp 2Zo 1000 2Rypy 2Zg 1002 ugi 90 6 58 030306 Figure 6 60 Differential HSTL 1 8V Class Il DCI Bidirectional Termination Table 6 24 lists the differential HSTL Class II 1 8V DC voltage specifications Table 6 24 Differential HSTL Class Il 1 8V DC Voltage Specifications Min Typ Max Vcco 17 1 8 1 9 Ver e Vcco x 0 5 Vin DC 0 30 Veco 0 30 Vprrr DC 0 20 Veco 0 60 Vom DC 0 83 1 08 Vpigg AC 0 40 Veco 0 60 Vx Crossover 0 83 1 08 Notes 1 Commo
289. ical specifications for 2 5V LVPECL to make system and board design easier LVPECL Transceiver Termination The Virtex 5 FPGA LVPECL transmitter and receiver requires the termination shown in Figure 6 89 illustrating a Virtex 5 FPGA LVPECL transmitter and receiver on a board with 50 O transmission lines The LVPECL driver is composed of two LVCMOS drivers that form a compliant LVPECL output when combined with the three resistor output termination circuit LVPECL 25 o E IOB I I i Rs 20 2500 IN Dx i i LVPECL_25 70Q I l R i LVPECL 25 MEA Rpigr 1000 x i Re Zo 502 YOO I INX I I ug190 6 84 030506 Figure 6 89 LVPECL Transmitter Termination 294 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Rules for Combining I O Standards in the Same Bank Rules for Combining I O Standards in the Same Bank The following rules must be obeyed to combine different input output and bidirectional standards in the same bank 1 Combining output standards only Output standards with the same output Vcco requirement can be combined in the same bank Compatible example SSTL2 I and LVDCI 25 outputs Incompatible example SSTL2 I output Veco 2 5V and LVCMOSS33 output Vcco 3 3V outputs 2 Combining input standards only Input standards with the same Vcco and Vggg requirements can be combined in the same bank Compatible example LVCMOSI5 and HSTL IV inputs
290. idelines for more details Figure 7 6 lists the supported IODELAY configurations Table 7 6 ODELAY Configurations Supported Input Pin IODELAY Direction of Used in the Supported Delay Mode IODELAY IODELAY Source Destination Modes Element I IDATAIN IBUF ILOGIC ISERDES Fabric Default Fixed Variable IDELAY DATAIN Fabric Fixed Variable ODELAY O ODATAIN OLOGIC OSERDES OBUF Fixed I whenT 21 IDATAIN IBUF ILOGIC ISERDES Fabric Fixed Variable Bidirectional Delay O when T 0 ODATAIN OLOGIC OSERDES OBUF Fixed IODELAY Primitive Figure 7 8 shows the IODELAY primitive IODELAY ODATAIN DATAOUT IDATAIN T INC RST CE DATAIN C ug 90 7 08 041106 Figure 7 8 ODELAY Primitive Table 7 7 lists the available ports in the IODELAY primitive All ports are 1 bit wide Table 7 7 ODELAY Primitive Ports Port Name Direction Function Delayed data from one of three data input ports IDATAIN DATAOUT Output ODATAIN DATAIN IDATAIN Input Data input for IODELAY from the IOB ODATAIN Input Data input for IODELAY from the OSERDES OLOGIC DATAIN Input Data input for IODELAY from the FPGA fabric 322 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY Table 7 7 ODELAY Primitive Ports Continued Hind Direction Function Name T Inpu
291. ifferential and Vggg dependent inputs are powered by VccAUX Each Virtex 5 FPGA I O tile contains two IOBs and also two ILOGIC blocks and two OLOGIC blocks as described in Chapter 7 SelectIO Logic Resources Figure 6 2 shows the basic IOB and its connections to the internal logic and the device Pad DIFFO IN PAD gt DIFFO_OUT T gt PADOUT oL a O gt OUTBUF INBUF DIFFI IN gt ugi 90 6 02 021306 Figure 6 2 Basic IOB Diagram Each IOB has a direct connection to an ILOGIC OLOGIC pair containing the input and output logic resources for data and 3 state control for the IOB Both ILOGIC and OLOGIC can be configured as ISERDES and OSERDES respectively as described in Chapter 8 Advanced SelectIO Logic Resources SelectlO Resources General Guidelines This section summarizes the general guidelines to be considered when designing with the SelectIO resources in Virtex 5 FPGAs 216 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines Virtex 5 FPGA I O Bank Rules In Virtex 5 devices with some exceptions in the center column an I O bank consists of 40 IOBs 20 CLBs high and a single clock region There are always four half sized banks 20 IOBs and a single configuration bank in the center column The number of banks depends upon the device size and in larger devices there are additional full sized banks in the
292. igh enabling the RAM for a Write operation e At time Tag before clock event 1 the address 2 becomes valid at the A B C D inputs of the RAM e At time Tps before clock event 1 the DATA becomes valid 1 at the DI input of the RAM and is reflected on the A B C D output at time TstycKxo after clock event 1 This is also applicable to the AMUX BMUX CMUX DMUX and COUT outputs at time Tsucko and Twosco after clock event 1 Clock Event 2 Read Operation All Read operations are asynchronous in distributed RAM As long as WE is Low the address bus can be asserted at any time The contents of the RAM on the address bus are reflected on the A B C D outputs after a delay of length Tj o propagation delay through a LUT The address F is asserted after clock event 2 and the contents of the RAM at address F are reflected at the output after a delay of length Ty 204 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Slice Timing Models Slice SRL Timing Model and Parameters Available in SLICEM only Figure 5 29 illustrates shift register implementation in a Virtex 5 FPGA slice Some elements of the slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown DX D address CLK 5 w gt CX DDO C address L BX D 4 B address gt AX L 4 A address gt
293. ignals are encode only mode Parity Output stable at the ECCPARITY outputs of the block RAM in encode only mode Tncko ECC SBITERR Clock to ECC SBITERR Time after RDCLK that the single bit error signal is Single Bit Error stable at the SBITERR output of the block RAM Output without output register Tgcko ECCR SBITERR Clock to ECC SBITERR Time after RDCLK that the single bit error signal is Single Bit Error stable at the SBITERR output of the block RAM Output with output register TRCKO_ECC_DBITERR Clock to ECC DBITERR Time after RDCLK that the double bit error signal is Double Bit Error stable at the DBITERR output of the block RAM Output without output register TRCKO_ECCR DBITERR Clock to ECC DBITERR Time after RDCLK that the double bit error signal is Double Bit Error stable at the DBITERR output of the block RAM Output with output register Notes 1 Tnpck pi Ecc Tnckp pi gcc include the parity input Trpck_pip_ecc TRCKD_DIP_ECC 2 Tncko po includes parity output Tgcko por 3 TnCKO ECC PARITY TRCKO ECC SBITERR and TRCKO ECC DBITERR are combined into the TRCKO_ECC parameter in the Virtex 5 FPGA Data Sheet 4 TRCKO ECC SBITERR and TnCKO ECC DBITERR are combined into the TRCKO_ECCR parameter in the Virtex 5 FPGA Data Sheet Creating a Deliberate Error in a 72 bit Word To deliberately create an error in a 72 bit word configure the ECC decode only mode and create a 72 bit word with one or two bi
294. igure 1 21 page 40 Removed a pad notation from the ODDR output of Figure 2 9 Removed the BUFG on the output of Figure 2 10 Updated CLKOUT 0 5 DESKEW ADJUST description in Table 3 4 page 95 Revised equations Equation 3 5 and Equation 3 6 Updated the notes in Table 4 16 page 144 Revised description of Instantiating IDELAYCTRL with Location LOC Constraints page 338 05 09 08 4 2 Revised clock routing resources in BUFGCTRL to DCM page 69 Removed example Figure 2 10 on page 72 Corrected note 1 in Table 4 5 page 122 Added Legal Block RAM and FIFO Combinations page 170 Clarified Note 7 in DCI in Virtex 5 Device I O Standards Master DCI is not supported in Banks 1 and 2 09 23 08 4 3 Added the TXT platform to Table 1 5 Table 2 1 and Table 5 2 Chapter 2 Revised Reset Input RST on page 49 and System Synchronous Setting Default page 62 Chapter 3 Updated Jitter Filter page 91 Chapter 4 Updated Write Modes on page 115 and Asynchronous Clocking on page 117 Chapter 6 Labeled all the DCI_18 standards consistently in Table 6 39 and Table 6 40 Replaced the link to the Full Device SSO Calculator Chapter 8 Updated CLKB in Table 8 1 page 351 and High Speed Clock Input CLKB page 353 12 02 08 4 4 Chapter 2 Changed edge to half in IBUFG Global Clock Input Buffer description on page 47 page 48 and page 49
295. igure 6 55 HSTL Class II 1 8V with Unidirectional Termination Figure 6 56 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 8V with bidirectional termination 262 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX External Termination HSTL Il 18 Specific Guidelines for I O Supported Standards Vr 0 9V Viste oS SSS Pee HSTL Il 18 Rp Z9 500 Rp Zo 500 Vper 0 9V DCI 2Rypp 2Zg 1000 HSTL_II_DCI_18 IOB IOB Veco 1 8V Veco 18V 7 2Rypp 2Zo 1000 HSTL_II_DCI_18 2Rypy 2Zo 1009 Vper 0 9V 2Rypn 2Zg 1002 E3 020 D1 1 gt ug190_6_54_030306 Figure 6 56 HSTL Class II 1 8V with Bidirectional Termination Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 263 Chapter 6 SelectlO Resources XILINX Table 6 23 lists the HSTL Class II 1 8V DC voltage specifications Table 6 23 HSTL Class Il 1 8V DC Voltage Specifications Min Typ Max Veco 1 7 1 8 1 9 Veer 2 0 9 di m 5 Veco x 05 p Vig Var 0 1 E V z a Vkgp 0 1 VoH Veco 0 4 Vor E 04 Tox at Voy mA 16 Ior at Vor mA 16 E Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Veg is to be selected by the user to provide optimum noise margin in the u
296. imitives Instantiating several distributed RAM primitives can be used to implement wide memory blocks Port Signals Each distributed RAM port operates independently of the other while reading the same set of memory cells Clock WCLK The clock is used for the synchronous write The data and the address input pins have setup times referenced to the WCLK pin Enable WE WED The enable pin affects the write functionality of the port An active write enable prevents any writing to memory cells An active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs Address A 0 DPRA 0 and ADDRA 4 0 ADDRD 0 The address inputs A 0 for single port and dual port DPRA 0 for dual port and ADDRA f0 ADDRD 0 for quad port select the memory cells for read or write The width of the port determines the required address inputs Some of the address inputs are not buses in VHDL or Verilog instantiations Table 5 11 summarizes the function of each address pins Data In D DID 0 The data input D for single port and dual port and DID 0 for quad port provide the new data value to be written into the RAM Data Out O SPO DPO and DOA 0 DOD 0 The data out O single port or SPO DPO dual port and DOA 0 DOD 0 quad port reflects the contents of the memory cells referenced by the address inputs Following an ac
297. in the input clock path to the DCM When set to FALSE the effective CLKIN frequency of the DCM equals the source clock frequency driving the CLKIN input When set to TRUE the CLKIN frequency is divided by two before it reaches the rest of the DCM Thus the DCM sees half the frequency applied to the CLKIN input and operates based on this frequency For example if a 100 MHz clock drives CLKIN and CLKIN DIVIDE BY 2 is set to TRUE then the effective CLKIN frequency is 50 MHz Thus CLKO output is 50 MHz and CLK2X output is 100 MHz The effective CLKIN frequency must be used to evaluate any operation or specification derived from CLKIN frequency The possible values for CLKIN DIVIDE BY 2 are TRUE and FALSE The default value is FALSE CLKOUT PHASE SHIFT Attribute The CLKOUT PHASE SHIFT attribute indicates the mode of the phase shift applied to the DCM outputs The possible values are NONE FIXED VARIABLE POSITIVE VARIABLE CENTER or DIRECT The default value is NONE When set to NONE a phase shift cannot be performed and a phase shift value has no effect on the DCM outputs When set to FIXED the DCM outputs are phase shifted by a fixed phase from the CLKIN The phase shift value is determined by the PHASE SHIFT attribute If the CLKOUT PHASE SHIFT attribute is set to FIXED or NONE then the PSEN PSINCDEC and the PSCLK inputs must be tied to ground When set to VARIABLE POSITIVE the DCM outputs can be phase shifted in variable mode in the
298. ing specification Read Only Memory ROM Each function generator in SLICEMs and SLICELs can implement a 64 x 1 bit ROM Three configurations are available ROM64x1 ROM128x1 and ROM256x1 ROM contents are loaded at each device configuration Table 5 6 shows the number of LUTs occupied by each ROM configuration Table 5 6 ROM Configuration ROM Number of LUTs 64x 1 1 128 x1 2 256 x 1 4 Shift Registers Available in SLICEM only ASLICEM function generator can also be configured as a 32 bit shift register without using the flip flops available in a slice Used in this way each LUT can delay serial data anywhere from one to 32 clock cycles The shiftin D DI1 LUT pin and shiftout Q31 MC31 LUT pin lines cascade LUTs to form larger shift registers The four LUTs in a SLICEM are thus cascaded to produce delays up to 128 clock cycles It is also possible to combine shift registers across more than one SLICEM Note that there are no direct connections between slices to form longer shift registers nor is the MC31 output at LUT B C D available The resulting programmable delays can be used to balance the timing of data pipelines Applications requiring delay or latency compensation use these shift registers to develop efficient designs Shift registers are also useful in synchronous FIFO and content addressable memory CAM designs The write operation is synchronous with a clock input CLK and an optional clock enable
299. ins optional address sequencing and control circuitry to operate as a built in multirate FIFO memory In Virtex 5 architecture the block RAM can be configured as an 18Kb or 36Kb FIFO Virtex 5 FPGA User Guide www xilinx com 111 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX All inputs are registered with the port clock and have a setup to clock timing specification All outputs have a read function or a read during write function depending on the state of the write enable WE pin The outputs are available after the clock to out timing interval The read during write outputs have one of three operating modes WRITE_FIRST READ_FIRST and NO_CHANGE A write operation requires one clock edge A read operation requires one clock edge All output ports are latched The state of the output port does not change until the port executes another read or write operation The default block RAM output is latch mode The output data path has an optional internal pipeline register Using the register mode is strongly recommended This allows a higher clock rate however it adds a clock cycle latency of one Virtex 5 FPGA block RAM usage rules The Synchronous Set Reset SSR port cannot be used when the ECC decoder is enabled EN ECC READ TRUE The setup time of the block RAM address and write enable pins must not be violated Violating the address setup time even if write enable is Low will corrupt the data content
300. ion There are three types of ECC operation standard encode only and decode only The standard ECC mode uses both the encoder and decoder The various modes of ECC operation in both block RAM and FIFO are shown in Figure 4 31 and Figure 4 32 The block RAM WRADDR and RDADDR address inputs are supplied by the user The FIFO WRADDR and RDADDR addresses are generated internally from the write counter and read counter TW T2W T3W TAW T5W l WRCLK Lo NIC A NY Now No vw WREN l gt TRCCK EN WRADDR S 0 a b c d gt TRCCK ADDR DI 63 0 A B C D TRCCK DI ECC DIP 7 0 Boc PA PB PC PD Decode Only Mode ECCPARITY 7 0 PA PB PC PD ur r TRCKO EcC PARITY ugi90 4 32 022307 Figure 4 31 ECC Write Operation TA4R T2R T3R T4R I 4 RDEN _ gt Ls TRCCK EN RDADDR 8 0 XX a x b X c x d TRCCK_ADDR DO 63 0 gt Latch Mode A X B A E TRCKO DO lLatch Mode DOPI7 0 ee Latch Modo PA X PB X PC X SBITERR SingeBitEror x Latch Mode gt le TRCKO_EQC_SBITERR Latch Mode DBITERR Double Bit rror_ 5 Latch Mode gt Le TRCKO EC DBITERR Latch Mode DO 63 0 nD A tx BK Register Mode A B C DOP 7 0 Register Mode MEN n B DX OR SBITERR I A Single Bit Error ON Register Mode i gt i TRCKO ECC SB TERR Register Mode DBITERR J Double Bit Error Register Mode l ES L TRCKO ECC DBiT
301. ion delay is emphasized in Figure 8 20 The path to OSERDESO is very long and the path to OSERDESI is very short such that each OSERDES receives the reset pulse in a different CLK cycle The internal resets for both CLK and CLKDIV go into reset asynchronously when the SR input is asserted Clock Clock Clock Clock Event 1 Event2 Event3 Event4 CLKDIV i i i i OSERDESO Signal at SR Input 1 OSERDES1 Internal Reset OpEnDES S CLKDIV 4 OSERDES1 OSERDESO Internal Reset CLK 1 OSERDES1 UGO70 c8 20 100307 rd Figure 8 20 Two OSERDES Coming Out of Reset Synchronously with One Another Virtex 5 FPGA User Guide www xilinx com 377 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX Clock Event 2 The reset pulse is deasserted on the rising edge of CLKDIV The difference in propagation delay between the two OSERDES causes the SR input to come out of reset on two different CLK cycles Without internal retiming OSERDESI finishes reset one CLK cycle before OSERDESO and both OSERDES are asynchronous Clock Event 3 The release of the reset signal at the SR input is retimed internally to CLKDIV This synchronizes OSERDESO and OSERDESI Clock Event 4 The release of the reset signal at the SR input is retimed internally to CLK OSERDES VHDL and Verilog Instantiation Templates The Libraries Guide includes instantiation templates of th
302. ion when the Bitslip module is not used in networking mode When set to MEMORY the Bitslip submodule is not available BITSLIP ENABLE must be set to FALSE and the OCLK port can be used Figure 8 5 illustrates the ISERDES NODELAY internal connections when in Memory mode Virtex 5 FPGA User Guide www xilinx com 355 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX D Q1 FF6 D Q2 FF7 CLK gt Q3 FF8 D Q4 FF9 OCLK D CLKDIV ug190 8 05 100307 Figure 8 5 Internal Connections of ISERDES NODELAY When in Memory Mode NUM CE Attribute The NUM CE attribute defines the number of clock enables CE1 and CE2 used The possible values are 1 and 2 default 2 SERDES MODE Attribute The SERDES MODE attribute defines whether the ISERDES NODELAY module is a master or slave when using width expansion The possible values are MASTER and SLAVE The default value is MASTER See ISERDES Width Expansion ISERDES NODELAY Clocking Methods Networking Interface Type The phase relationship of CLK and CLKDIV is important in the serial to parallel conversion process CLK and CLKDIV are ideally phase aligned within a tolerance There are several clocking arrangements within the FPGA to help the design meet the phase relationship requirements of CLK and CLKDIV The only valid clocking arrangements for the ISERDES NODELAY block using the networking interface type are e CLK dr
303. ionality of the block RAM when using the ECC mode is described as follows e The block RAM ports still have independent address clocks and enable inputs but one port is a dedicated write port and the other is a dedicated read port simple dual port e DO represents the read data after correction e DO stays valid until the next active read operation e Simultaneous decoding and encoding even with asynchronous clocks is allowed but requires careful clock timing if read and write addresses are identical e The READ FIRST or WRITE FIRST modes of the normal block RAM operation are not applicable to the ECC configuration www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Built in Error Correction Top Level View of the Block RAM ECC Architecture Figure 4 28 shows the top level view of a Virtex 5 FPGA block RAM in ECC mode 9 WRADDR 8 0 Adr 7 gt RDADDR amp add Ye 8 DIP 7 0 ECCPARITY 7 0 EN ECC WRITE 64 D1 63 0 gt Data In BRAM 512 x 72 DO 63 0 DBITERR Decode and Correct SBITERR DOP 7 0 EN_ECC_READ ugi90 4 25 071707 Figure 4 28 Top Level View of Block RAM ECC Virtex 5 FPGA User Guide www xilinx com 159 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Block RAM and FIFO ECC Primitive Figure 4 29 shows the block RAM RAMB36SDP ECC primitive Figure 4 30 shows th
304. ions with depth greater than 64 requires the usage of wide function multiplexers F7AMUX F7BMUX and F8MUX 184 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview RAM128X1S Output Registered Output Optional ug190_5_12_050506 Figure 5 12 Distributed RAM RAM128X1S If two single port 128 x 1 bit modules are built the two RAM128X1S primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 128 x 2 bit single port distributed RAM Virtex 5 FPGA User Guide www xilinx com 185 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX RAM128X1D D A 6 0 WCLK WE Registered F7BMUX a Output Optional l l l l l l 4 l l l l l DPRA 6 0 l l l DPO l l Registered F7AMUX l ET Output Optional l l l l l l mr l UG190_5_13_050506 Figure 5 13 Distributed RAM RAM128X1D 186 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview RAM256X1S ee ee 5 l l o SPRAM64 D l l A 7 0 l l l WCLK E A6 CX l l l F7BMUX l l l l A7 BX I l Output Registere
305. irtex5 Online Document The following conventions are used in this document Convention Blue text Meaning or Use in the current document Cross reference link to a location Example See the section Additional Documentation for details Refer to Clock Management Technology in Chapter 2 for details Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest documentation www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Chapter 1 Clock Resources Global and Regional Clocks For clocking purposes each Virtex 5 device is divided into regions The number of regions varies with device size eight regions in the smallest device to 24 regions in the largest one Global Clocks Each Virtex 5 device has 32 global clock lines that can clock all sequential resources on the whole device CLB block RAM CMTs and I O and also drive logic signals Any ten of these 32 global clock lines can be used in any region Global clock lines are only driven by a global clock buffer which can also be used as a clock enable circuit or a glitch free multiplexer It can select between two clock sources and can also switch away from a failed clock source A global clock buffer is often driven by a Clock Management Tile CMT to eliminate the clock distribution delay or to adjust its delay relative to another c
306. is an active High clock enable connected directly to the input registers in the ISERDES NODELAY When NUM CE 2 the CE1 and CE2 inputs are both used with CE1 enabling the ISERDES_NODELAY for of a CLKDIV cycle and CE2 enabling the ISERDES_NODELAY for the other 4 The internal clock enable signal ICE shown in Figure 8 4 is derived from the CE1 and CE2 inputs ICE drives the clock enable inputs of 352 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES registers FFO FF1 FF2 and FF3 shown in Figure 8 12 page 364 The remaining registers in Figure 8 18 page 365 do not have clock enable inputs The clock enable module functions as a 2 1 serial to parallel converter clocked by CLKDIV The clock enable module is needed specifically for bidirectional memory interfaces when ISERDES_NODELAY is configured for 1 4 deserialization in DDR mode When the attribute NUM CE 2 the clock enable module is enabled and both CE1 and CE2 ports are available When NUM CE 1 only CE1 is available and functions as a regular clock enable High Speed Clock Input CLK The high speed clock input CLK is used to clock in the input serial data stream High Speed Clock Input CLKB The high speed secondary clock input CLKB is used to clock in the input serial data stream CLKB should be connected to CLK in both SDR and DDR mode Divided Clock Input CLKDIV The di
307. is set to a negative value Absolute Range Variable Center Mode FINE SHIFT RANGE 2 The variable center mode allows symmetric dynamic sweeps from 255 256 to 255 256 by having the DCM set the zero phase skew point in the middle of the delay line This divides the total delay line range in half Absolute Range Fixed FINE SHIFT RANGE In the fixed mode a phase shift is set during configuration in the range of 255 256 to 255 256 Absolute Range Variable Positive and Direct Modes FINE_SHIFT_RANGE In the variable positive and direct modes the phase shift only operates in the positive range The DCM sets the zero phase skew point at the beginning of the delay line This produces a full delay line in one direction Both the PHASE SHIFT attribute and the FINE SHIFT RANGE parameter need to be considered to determine the limiting range of each application The Phase Shift Examples section illustrates possible scenarios In variable and direct mode the PHASE SHIFT value can dynamically increment or decrement as determined by PSINCDEC synchronously to PSCLK when the PSEN input is active Phase Shift Examples The following usage examples take both the PHASE SHIFT attribute and FINE SHIFT RANGE into consideration e If PERIODCLKIN 2 x FINE SHIFT RANGE then the PHASE SHIFET in fixed mode is limited to 128 In variable positive mode PHASE SHIFT is limited to 128 In variable center mode the PHASE SHIFT is limi
308. is used to guarantee non positive hold times when global clocks are used without DCMs to capture data pin to pin parameters When set to FIXED the tap delay value is fixed at the number of taps determined by the IDELAY VALUE attribute setting This value is preset and cannot be changed after configuration When set to VARIABLE the variable tap delay element is selected The tap delay can be incremented by setting CE 1 and INC 1 or decremented by CE 1 and INC 0 The increment decrement operation is synchronous to C the input clock signal IDELAY VALUE Attribute TheIDELAY VALUE attribute specifies the initial number of tap delays The possible values are any integer from 0 to 63 The default value is zero The value of the tap delay reverts to IDELAY VALUE when the tap delay is reset In variable mode this attribute determines the initial setting of the delay line Virtex 5 FPGA User Guide www xilinx com 325 UG190 v4 4 December 2 2008 326 Chapter 7 SelectlO Logic Resources XILINX ODELAY VALUE Attribute The ODELAY VALUE attribute specifies tap delays The possible values are any integer from 0 to 63 The default value is zero The value of the tap delay reverts to ODELAY VALUE when the tap delay is reset HIGH PERFORMANCE MODE Attribute When TRUE this attribute reduces the output jitter This reduction results in a slight increase in power dissipation from the IODELAY element When set to FALSE the IODELAY element co
309. istors and the output current is determined by the output impedance e If only LVDCI 33 inputs are used it is not necessary to connect VRP and VRN to external reference resistors The implementation pad report does not record VRP and VRN being used External reference resistors are required only if LVDCI 33 outputs are present in a bank e LVDCI_33 is compatible with LVTTL and LVCMOS standards only In addition changing the slew rate from fast to slow and or reducing the current drive could significantly reduce overshoot and undershoot The Virtex 5 FPGA PC Board Designers Guide contains additional design information to assist PCB designers and signal integrity engineers Regulating Vcco at 3 0V The following section discusses alternatives for managing overshoot and undershoot for LVTTL LVCMOS33 and PCI applications When Vcco is lowered to 3 0V the power clamp diode turns on at about 3 5V Therefore it limits any overshoot higher than 3 5V before reaching the absolute maximum level of 4 05V In addition instead of 0 3V when Vcco 3 75V the lower absolute maximum limit corresponding to Veco 3 0V is 1 05V In this case the ground clamp diode clips undershoot before reaching the lower absolute maximum limit As a result lowering Vcco to 3 0V addresses the overshoot and undershoot specifications for all supported 3 3 V standards including LVCMOS 33 LVTTL LVDCI 33 and PCI Mixing Techniques Either using LVDCI 33 stand
310. it is shifted out on the M31 output The bit selected by the 5 bit address port A 4 0 appears on the Q output Dynamic Read Operation The Q output is determined by the 5 bit address Each time a new address is applied to the 5 input address pins the new bit position value is available on the Q output after the time www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Overview delay to access the LUT This operation is asynchronous and independent of the clock and clock enable signals Static Read Operation If the 5 bit address is fixed the Q output always uses the same bit position This mode implements any shift register length from 1 to 16 bits in one LUT The shift register length is N 1 where N is the input address 0 31 The Q output changes synchronously with each shift operation The previous bit is shifted to the next position and appears on the Q output Shift Register Summary e A shift operation requires one clock edge e Dynamic length read operations are asynchronous Q output e Static length read operations are synchronous Q output e The data input has a setup to clock timing specification e Inacascadable configuration the Q31 output always contains the last bit value e The Q31 output changes synchronously after each shift operation Multiplexers Function generators and associated multiplexers in Virtex 5 FPGAs can implement the following e 4 1 mul
311. ive all clock regions in Virtex 5 devices The primary secondary rules from Virtex II and Virtex II Pro FPGAs do not apply However only ten different clocks can be driven in a single clock region A clock region 20 CLBs is a branch of the clock tree consisting of ten CLB rows up and ten CLB rows down A clock region only spans halfway across the device The clock buffers are designed to be configured as a synchronous or asynchronous glitch free 2 1 multiplexer with two clock inputs Virtex 5 control pins provide a wide range of functionality and robust input switching The following subsections detail the various configurations primitives and use models of the Virtex 5 clock buffers Virtex 5 FPGA User Guide www xilinx com 23 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources 24 XILINX Global Clock Buffer Primitives The primitives in Table 1 2 are different configurations of the global clock buffers Table 1 2 Global Clock Buffer Primitives Primitive Input Output Control BUFGCTRL I0 I1 O CEO CE1 IGNOREO IGNORE1 S0 S1 BUFG I O BUFGCE I O CE BUFGCE_1 I O CE BUFGMUX I0 I1 O S BUFGMUX 1 I0 I1 O S BUFGMUX VIRTEX4 2 10 11 O S Notes 1 All primitives are derived from a software preset of BUFGCTRL 2 BUFGMUX VIRTEX4 is a legacy primitive name left over from the Virtex 4 family BUFGCTRL The BUFGCTRL primitive shown in Figure 1 1 can switch between t
312. iven by BUFIO CLKDIV driven by BUFR e CLK driven by DCM CLKDIV driven by the CLKDV output of the same DCM e CLK driven by PLL CLKDIV driven by CLKOUT 0 5 of same PLL 356 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES Memory Interface Type The only valid clocking arrangements for the ISERDES_NODELAY block using the memory interface type are e CLK driven by BUFIO or BUFG e OCIK driven by DCM and CLKDIV driven by CLKDV output of same DCM e OCLK driven by PLL and CLKDIV driven by CLKOUT 0 5 of same PLL The clocking arrangement using BUFIO and BUFR is shown in Figure 8 6 The CLK and CLKDIV inputs must be nominally phase aligned For example if CLK and CLKDIV in Figure 8 6 were inverted by the designer at the ISERDES inputs then although the clocking arrangement is a legal BUFIO BUFR configuration the clocks would still be out of phase No phase relationship between CLK and OCLK is expected Calibration must be performed for reliable data transfer from CLK to OCLK domain High Speed Clock for Strobe Based Memory Interfaces OCLK gives further information about transferring data between CLK and OCLK BUFIO ISERDES NODELAY Clock Input CLK BUFR X CLKDIV Figure 8 6 Clocking Arrangement Using BUFIO and BUFR UG190 8 06 110807 ISERDES Width Expansion Two ISERDES modules are used to build a serial to parallel converter
313. ividually for each storage element in the ILOGIC block but the choice of synchronous or asynchronous set reset SRTYPE can not be set individually for each storage element in the ILOGIC block The following sections discuss the various resources within the ILOGIC blocks All connections between the ILOGIC resources are managed in Xilinx software Combinatorial Input Path The combinatorial input path is used to create a direct connection from the input driver to the FPGA fabric This path is used by software automatically when 1 There is a direct unregistered connection from input data to logic resources in the FPGA fabric 2 The pack I O register latches into IOBs is set to OFF Input DDR Overview IDDR Virtex 5 devices have dedicated registers in the ILOGIC to implement input double data rate DDR registers This feature is used by instantiating the IDDR primitive There is only one clock input to the IDDR primitive Falling edge data is clocked by a locally inverted version of the input clock All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between ILOGIC and OLOGIC blocks The IDDR primitive supports the following modes of operation e OPPOSITE EDGE mode e SAME EDGE mode e SAME EDGE PIPELINED mode The SAME EDGE and SAME EDGE PIPELINED modes are the same as for the Virtex 4 architecture These modes allow designers to transfer falling edge data to the rising edge domain wit
314. l 18 Differential HSTL class II pairs complimentary single ended HSTL II type drivers with a differential receiver Differential HSTL class II is intended to be used in bidirectional links Differential HSTL can also be used for differential clock and DQS signals in memory interface designs DIFF HSTL II DCI DIFF HSTL Il DCI 18 Differential HSTL class II pairs complimentary single ended HSTL II type drivers with a differential receiver including on chip differential split thevenin termination Differential HSTL class II is intended to be used in bidirectional links Differential HSTL can also be used for differential clock and DOS signals in memory interface designs DIFF HSTL I DIFF HSTL I 18 Differential HSTL class I pairs complimentary single ended HSTL I type drivers with a differential receiver Differential HSTL class I is intended to be used in unidirectional links DIFF HSTL I DCI DIFF HSTL I DCI 18 Differential HSTL class I pairs complimentary single ended HSTL I type drivers with a differential receiver including on chip differential split thevenin termination Differential HSTL class I is intended to be used in unidirectional links www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards HSTL Class l Figure 6 39 shows a sample circuit illustrating a valid termination technique for HSTL Class I External Termination IOB HSTL I HSTL I
315. l PCB requirements listed in Nominal PCB Specifications the Virtex 5 FPGA SSO calculator is available containing all SSO limit data for all I O standards For designs in nominal PCBs mixing limited and no limit I O standards the Virtex 5 FPGA SSO calculator must be used to ensure that I O utilization does not exceed the limit Information on the calculator is available under the Full Device SSO Calculator section Unlike devices in previous families Virtex 5 devices have only two bank sizes 20 I O and 40 I O With the ratio of signal to reference pins always constant the SSO capacity of all banks of 20 I O are the same and the capacity of all banks of 40 I O are the same The SSO limits for Virtex 5 devices are listed on a per bank basis rather than a limit per Vcco9 GND pair www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Simultaneous Switching Output Limits Nominal PCB Specifications The nominal SSO table Table 6 40 contains SSO limits for cases where the PCB parameters meet the following requirements Note In cases where PCB parameters do not meet all requirements listed below the Virtex 5 FPGA SSO Calculator must be used to determine the SSO limit according to the physical factors of the unique PCB PCB Construction e Veco and GND vias should have a drill diameter no less than 11 mils 279 y e Total board thickness must be no greater than 62 mils 1575 p Signal Return Curre
316. l sections are described e Functional element diagram basic architectural schematic illustrating pins and connections e Timing parameters definitions of Virtex 5 FPGA Data Sheet timing parameters e Timing Diagram illustrates functional element timing parameters relative to each other Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer software TRCE and the section on switching characteristics in the Virtex 5 FPGA Data Sheet All pin names parameter names and paths are consistent with the post route timing and pre route static timing reports Most of the timing parameters found in the section on switching characteristics are described in this chapter All timing parameters reported in the Virtex 5 FPGA Data Sheet are associated with slices and CLBs The following sections correspond to specific switching characteristics sections in the Virtex 5 FPGA Data Sheet e General Slice Timing Model and Parameters CLB Switching Characteristics e Slice Distributed RAM Timing Model and Parameters Available in SLICEM only CLB Distributed RAM Switching Characteristics e Slice SRL Timing Model and Parameters Available in SLICEM only CLB SRL Switching Characteristics e Slice Carry Chain Timing Model and Parameters CLB Application Switching Characteristics 198 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Slice Timing Models General S
317. larger than 1 6 In every I O tile there are two ISERDES modules one master and one slave By connecting the SHIFTOUT ports of the master ISERDES to the SHIFTIN ports of the slave ISERDES the serial to parallel converter can be expanded to up to 1 10 DDR and 1 8 SDR Figure 8 7 illustrates a block diagram of a 1 10 DDR serial to parallel converter using the master and slave ISERDES modules Ports Q3 Q6 are used for the last four bits of the parallel interface on the slave ISERDES For a differential input the master ISERDES must be on the positive side of the differential input pair When the input is not differential the input buffer associated with the slave ISERDES is not available and can not be used Virtex 5 FPGA User Guide www xilinx com 357 UG190 v4 4 December 2 2008 Chapter 8 Advanced SelectlO Logic Resources XILINX SERDES_MODE MASTER Data Input Q1 r Q2 ISERDES Q3 Master Q4 L Q5 Data internal 0 5 Q6 SHIFTOUT1 SHIFTOUT2 SHIFTIN1 SHIFTIN2 D Q1 ISERDES E Slave x Data internal 6 9 SERDES MODE SLAVE ug190 8 07 100307 Figure 8 7 Block Diagram of ISERDES Width Expansion Guidelines for Expanding the Serial to Parallel Converter Bit Width 1 Both ISERDES modules must be adjacent master and slave pairs Both ISERDES modules must bein NETWORKING mode because width expansion is not available in MEMORY mode 2 Setthe SERDES MODE attribute for t
318. lectlO Resources General Guidelines e Figure 6 17 provides examples illustrating the use of the SSTL2 I DCI and SSTL2 II DCII O standards HSTL I HSTL Il HSTL Ill HSTL IV Conventional Vcco 2 Vanal DCI Transmit L if gt 7 NEN eco Conventional z fi i Receive p E gt gt d Virtex 5 gt Virtex 5 e Virtex 5 De i SBa e BULUM ME c Conventional oa Veco ies Transmit 7 Nits Er DCI Receive A D gt Virtex 5 Virtex 5 Virtex 5 EDU DCI Transmit DCI Receive Virtex 5 _ DO Bidirectional Virtex 5 Virtex 5 Virtex 5 DO DO Reference Resistor VRN VRP R Z0 VRN VRP R Zo VRN VRP R Zo VRN VRP R Zo Recommended Zo Notes 1 Zg is the recommended PCB trace impedance ug190_6_14_021206 Figure 6 16 HSTL DCI Usage Examples Virtex 5 FPGA User Guide www xilinx com 229 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Conventional DCI Transmit Conventional Receive Conventional Transmit DCI Receive DCI Transmit DCI Receive Bidirectional Reference Resistor Recommended Z92 Notes SSTL2 I or SSTL18 I SSTL2 Il or SSTL18 Il Vcco 2 pum Vcco 2 Vcco 2 Re NN R R NAT E wn 3 L R 2 Vcco 2 Vcco sdb Virtex 5 Virtex 5 DCI Virtex 5 DCI A VRN VRP R Zg VRN VRP R Zo 50 Q 50 Q 1 The SS
319. lice Timing Model and Parameters A simplified Virtex 5 FPGA slice is shown in Figure 5 25 Some elements of the slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown LUT D 6 Inputs 06 71 D gt D O5 C gt DMUX FE LAT DX Lo F7BMUX LUT C 6 Inputs a e O5 CX E F8MUX LUT l F7AMUX f Inputs i AX CE D gt CLK SR E gt REV gt i DX UG190 5 25 050506 Figure 5 25 Simplified Virtex 5 FPGA Slice Virtex 5 FPGA User Guide www xilinx com 199 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs Timing Parameters XILINX Table 5 7 shows the general slice timing parameters for a majority of the paths in Figure 5 25 Table 5 7 General Slice Timing Parameters Parameter Function Description Combinatorial Delays Tro A B C Dinputs to A B C D Propagation delay from the A B C D inputs of outputs the slice through the look up tables LUTS to the A B C D outputs of the slice six input function Tito 2 A B C D inputs to Propagation delay from the A B C D inputs of AMUX CMUX outputs the slice through the LUTs and F7AMUX F7BMUxX to the AMUX CMUX outputs seven input function Tito 3 A B C D inputs to BMUX Propagation delay from the A B C D inputs of output the slice through
320. ll the output counters since a single VCO drives all the counters Clock Network Deskew In many cases designers do not want to incur the delay on a clock network in their I O timing budget therefore they use a PLL or DLL to compensate for the clock network delay Virtex 5 FPGA PLLs support this feature A clock output matching the reference clock CLKIN frequency usually CLKFBOUT is connected to a BUFG and fed back to the CLKPBIN feedback pin of the PLL The remaining outputs can still be used to divide the clock down for additionally synthesized frequencies In this case all output clocks have a defined phase relationship to the input reference clock Frequency Synthesis Only The PLLs can also be used for stand alone frequency synthesis In this application the PLL can not be used to deskew a clock network but rather generate an output clock frequency for other blocks In this mode the PLL feedback path should be set to INTERNAL since it keeps all the routing local and should minimize the jitter Figure 3 5 shows the PLL configured as a frequency synthesizer In this example an external 33 MHz reference clock is available The reference clock can be a crystal oscillator or the output of another PLL Setting the M counter to 16 makes the VCO oscillate at 533 MHz 33 333 MHz x 16 The six www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX General Usage Description PLL outputs are programmed to provide a
321. located in the bottom left corner of the die Virtex 5 FPGA User Guide www xilinx com 171 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX COUT COUT COUT COUT UG190 5 02 122605 Figure 5 2 Row and Column Relationship between CLBs and Slices Slice Description Every slice contains four logic function generators or look up tables four storage elements wide function multiplexers and carry logic These elements are used by all slices to provide logic arithmetic and ROM functions In addition to this some slices support two additional functions storing data using distributed RAM and shifting data with 32 bit registers Slices that support these additional functions are called SLICEM others are called SLICEL SLICEM shown in Figure 5 3 represents a superset of elements and connections found in all slices SLICEL is shown in Figure 5 4 172 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX CLB Overview DI2 n DPRAM64 32 5 Dn SPRAM64 32 o SRL32 Reset Type n Sync o Async OFF A2 Ai OROM wcai WA1 WA6 WA7 WA8 D LATCH D INITI D INITO CE OSRHIGH ck Hn SRLOW SR REV DI2 o DPRAM64 32 o SPRAM64 32 n SRL32 o SRL16 OLUT oO RAM BH ROM WA1 WA6 WA7 WA8 DI2 AS 4 DPRAM64 32 A5 n SPRAM64 32
322. lock There are more global clocks than CMTs but a CMT often drives more than one global clock Regional Clocks and I O Clocks Each region has two regional clock buffers and four regional clock trees A Virtex 5 I O bank spans exactly one region with the exception of some banks in the center column Each bank with the size identical to a region contains four clock capable clock inputs Each of these inputs can differentially or single endedly drive four I O clocks and two regional clocks in the same bank or region In addition regional clocks can drive regional clock trees in the adjacent regions When the clock capable I Os are driven by single ended clocks then the clock must be connected to the positive P side of the differential clock capable pin pair The negative N side can be used as a general purpose I O or left unconnected The regional clock buffer can be programmed to divide the incoming clock rate by any integer number from 1 to 8 This feature in conjunction with the programmable serializer deserializer in the IOB see Chapter 8 Advanced SelectIO Logic Resources allows source synchronous systems to cross clock domains without using additional logic resources A third type of clocking resource I O clocks are very fast and serve localized I O serializer deserializer circuits See Chapter 8 Advanced SelectIO Logic Resources Virtex 5 FPGA User Guide www xilinx com 21 UG190 v4 4 December 2 2008 Chapter
323. lock inputs are also clock capable I Os There are four dedicated clock capable I O sites in every bank When used as clock inputs clock capable pins can drive BUFIO and BUFR Clock capable I Os in the center column can not drive BUFRs Clock capable I Os can not directly connect to the global clock buffers When used as single ended clock pins then as described in Global Clock Buffers the P side of the pin pair must be used because a direct connection only exists on this pin www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Regional Clocking Resources I O Clock Buffer BUFIO The I O clock buffer BUFIO is a clock buffer available in Virtex 5 devices The BUFIO drives a dedicated clock net within the I O column independent of the global clock resources Thus BUFIOs are ideally suited for source synchronous data capture forwarded receiver clock distribution BUFIOs can only be driven by clock capable I Os located in the same clock region In a typical clock region there are four BUFIOs Each BUFIO can drive a single I O clock network in the same region bank as well as the regional clock buffers BUFR BUFIOs cannot drive logic resources CLB block RAM IODELAY etc because the I O clock network only reaches the I O column in the same bank or clock region BUFIO Primitive BUFIO is simply a clock in clock out buffer There is a phase delay between input and output Figure 1 18 shows the BUFIO
324. ltage Specifications Min Typ Max Vcco 17 1 8 1 9 Input Parameters Ver Veco X 0 5 Vin DC 0 30 Veco 0 30 Vip DC 0 25 Veco 0 60 Vip AC 0 50 Veco 0 60 Vix AC 0 675 1 125 Output Parameters Vox AC 9 0 725 5 1 075 Notes 1 Vix DC specifies the allowable DC excursion of each differential input 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 3 Vip DC specifies the input differential voltage required for switching 4 Vix AC indicates the voltage where the differential input signals must cross 5 Vox AC indicates the voltage where the differential output signals must cross SSTL18 ll T DCI 1 8V Split Thevenin Termination Figure 6 85 shows a sample circuit illustrating a valid termination technique for SSTL18 II T DCI 1 8V with on chip split thevenin termination In this bidirectional I O standard when 3 stated the termination is invoked on the receiver and not on the driver Because the Thevenin termination on the I O is disabled for a driving I O the line is equivalent to the SSTL18_I termination scheme This allows the line to be driven by the weaker SSTL class I driver The SSTL18 II T DCI standard behaves like a normal SSTL18 ILI O in a bidirectional environment but has the advantage of lower drive strength and lower power consumption due to the optimiz
325. matically placed at clock input sites OBUF An output buffer OBUF must be used to drive signals from Virtex 5 devices to external output pads A generic Virtex 5 FPGA OBUF primitive is shown in Figure 6 19 Virtex 5 FPGA User Guide OBUF Input O Output From FPGA to device pad ug 90 6 17 022806 Figure 6 19 Output Buffer OBUF Primitive www xilinx com 231 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX OBUFT The generic 3 state output buffer OBUFT shown in Figure 6 20 typically implements 3 state outputs or bidirectional I O OBUFT 3 state input Input O Output From FPGA to device pad ugi90 6 18 022806 Figure 6 20 3 State Output Buffer OBUFT Primitive IOBUF The IOBUF primitive is needed when bidirectional signals require both an input buffer and a 3 state output buffer with an active High 3 state pin Figure 6 21 shows a generic Virtex 5 FPGA IOBUF IOBUF T 3 state input Input 1 0 from FPGA to from device pad O Output to FPGA ug190_6_19_022806 Figure 6 21 Input Output Buffer IOBUF Primitive IBUFDS and IBUFGDS The usage and rules corresponding to the differential primitives are similar to the single ended SelectIO primitives Differential SelectIO primitives have two pins to and from the device pads to show the P and N channel pins in a differential pair N channel pins have a B suffix Figure 6 22 shows the differential input buffer primi
326. me TRgg and Twosco after clock event 1 Virtex 5 FPGA User Guide www xilinx com 207 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX Slice Carry Chain Timing Model and Parameters Figure 5 24 page 197 illustrates a carry chain in a Virtex 5 FPGA slice Some elements of the slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown Slice Carry Chain Timing Parameters Table 5 10 shows the slice carry chain timing parameters for a majority of the paths in Figure 5 24 page 197 Table 5 10 Slice Carry Chain Timing Parameters Parameter Function Description Sequential Delays for Slice LUT Configured as Carry Chain Taxcy Tgxcy Tcxcy Tpxcy AX BX CX DX input to Propagation delay from the AX BX CX DX COUT output inputs of the slice to the COUT output of the slice Tgyp CIN input to COUT output Propagation delay from the CIN input of the slice to the COUT output of the slice Topcya Topcys Topcyc Torcyp A B C D input to COUT Propagation delay from the A B C D inputs of output the slice to the COUT output of the slice Towa Tecws Tewc TcInp A B C D input to Propagation delay from the A B C D inputs of AMUX BMUX CMUX DMU the slice to AMUX BMUX CMUX DMUX X output output of the slice using XOR sum Setup and Hold Times for a Slice LUT Configured as a Carry Chain Tonck TcKCIN CIN Data inputs Time before the CLK t
327. ment decrement is controlled by the enable signal CE This interface is only available for the IDELAY mode when IDELAY TYPE VARIABLE As long as CE remains High IDELAY will increment or decrement by TIDELAYRESOLUTION every clock C cycle The state of INC determines whether IDELAY will increment or decrement INC 1 increments INC 0 decrements synchronously to the clock C If CE is Low the delay through IDELAY will not change regardless of the state of INC When CE goes High the increment decrement operation begins on the next positive clock cycle When CE goes Low the increment decrement operation ceases on the next positive clock cycle IODELAY is a wrap around programmable delay element When the end of the delay element is reached tap 63 a subsequent increment function will return to tap 0 The same applies to the decrement function decrementing below zero moves to tap 63 The increment decrement operation is summarized in Table 7 9 Table 7 9 Increment Decrement Operations Operation RST CE INC Reset to IDELAY VALUE 1 x x Increment tap count 0 1 1 Decrement tap count 0 1 0 No change 0 0 x Notes 1 RST takes precedence over CE and INC 324 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY IODELAY Attributes Table 7 10 summarizes the IODELAY attributes Table 7 10 IODELAY Attribute Summary
328. mode both the edges of the clock CLK are used to capture the data from the FPGA fabric at twice the throughput This structure is similar to the Virtex II Virtex II Pro and Virtex 4 FPGA implementation Both outputs are presented to the data input or 3 state control input of the IOB The timing diagram of the output DDR using the OPPOSITE EDGE mode is shown in Figure 7 23 CLK OCE D1 oQ D1A D1B l l l ug190_7_18_041206 Figure 7 23 Output DDR Timing in OPPOSITE_EDGE Mode SAME_EDGE Mode In SAME_EDGE mode data can be presented to the IOB on the same clock edge Presenting the data to the IOB on the same clock edge avoids setup time violations and allows the user to perform higher DDR frequency with minimal register to register delay as opposed to using the CLB registers Figure 7 24 shows the timing diagram of the output DDR using the SAME_EDGE mode CLK OCE D1 D1B D1 1 D2 D2A D2B D2C D2D oa ___ D1A D2A 01B D2B DIC D2C D10 ug190_7_19_041206 Figure 7 24 Output DDR Timing in SAME_EDGE Mode w gt O oO oO 342 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX OLOGIC Resources Clock Forwarding Output DDR can forward a copy of the clock to the output This is useful for propagating a clock and DDR data with identical delays and for multiple clock generation where every clock load has a unique clock driver This is accomplished b
329. mpty FIFO the Almost EMPTY signal is asserted e At time Trcck RDEN before clock event 1 RDCLK read enable becomes valid at the RDEN input of the FIFO e At time Trcko po after clock event 1 RDCLK data 00 becomes valid at the DO outputs of the FIFO e At time Trcko AEMPTY One clock cycle after clock event 1 RDCLK Almost Empty is asserted at the AEMPTY output pin of the FIFO Clock Event 2 Read Operation and Assertion of EMPTY Signal The EMPTY signal pin is asserted when the FIFO is empty e Read enable remains asserted at the RDEN input of the FIFO e At time Trcko po after clock event 2 RDCLK data 04 last data becomes valid at the DO outputs of the FIFO e At time Trcko Empty after clock event 2 RDCLK Empty is asserted at the EMPTY output pin of the FIFO In the event that the FIFO is empty and a write followed by a read is performed the EMPTY signal remains asserted 154 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Timing Models and Parameters Clock Event 3 Read Operation and Assertion of Read Error Signal The read error signal pin is asserted when there is no data to be read because the FIFO is in an empty state Read enable remains asserted at the RDEN input of the FIFO At time TEcCKO_RDERR after clock event 3 RDCLK read error is asserted at the RDERR output pin of the FIFO Data 04 remains unchanged at the DO outputs of the FIFO Clock Event 4
330. mpty Hlag i z ee B her eer xu ax eei kx ere a eee xe o E dx as 144 Almost Empty Flag aaa Se Saas nae reed EDU s caps dia ade am due pas 145 Read Error Flag i sa sexes sieu nea IAM CLOS Rr red ente gr dd ageless 145 Pil Flag 25 docendi dor dade dye tra cel a eet eae cesa eret ees 145 Write Error Flag ky ERR hae ee eee bee deeds Deas eve res 145 Almost Fall Flap eer hee Suns eats ae Seas d E UC ePP COE Sa eee E RE 145 FIFO Attributes sisreirrrosiki tebe hidden ep Ee Edu icEierredu vida 146 FIFO Almost Full Empty Flag Offset Range 0 00 c eee eee eee eee 146 FIFO VHDL and Verilog Templates 00 0 e cee eee ee 148 Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 11 XILINX FIFO Timing Models and Parameters n nunnana 148 FIFO Timing Characteristics sss erosen E E EOE E 149 Case 1 Writing to an Empty FIFO 6 ec nn 150 Case 2 Writing to a Full or Almost Full FIFO 0 6 0 nunnu nanara ee 151 Case 3 Reading From a Full FIFO 0 0 ee n 153 Case 4 Reading From An Empty or Almost Empty FIFO 0 0000 154 Case 5 Resetting All Flags 54 deer E b E ER eee de sore ails 155 Case 6 Simultaneous Read and Write for Multirate FIFO 00000 eee 156 FIFO Applications 1 5 cine ctha need ree eher REC Se YR ER SRE ERR E OSs 156 Cascading FIFOs to Increase Depth ssseeseee e 156 Connecting FIFOs in Parallel to Increase Width 15
331. n Data D is a repeating 4 bit training pattern ABCD ABCD could appear at the parallel outputs Q1 O4 of the ISERDES in four possible ways ABCD BCDA CDAB and DABC Only one of these four alignments of the parallel word makes sense to the user s downstream logic that reads the data from the Q1 O4 outputs of the ISERDES In this case ABCD is assumed to be the word alignment that makes sense Asserting Bitslip allows the user to see all possible configurations of ABCD and then choose the expected alignment ABCD Figure 8 12 shows the timing of two Bitslip operations and the corresponding re alignments of the ISERDES parallel outputs Q1 O4 4 5 5 JORANECO ASTE ADANEOO BITSLIP Bitslip1 Bitslip2 CLKDIV i i i f ug190_8_12_100307 Figure 8 12 Bitslip Timing Diagram Clock Event 1 The entire first word CDAB has been sampled into the input side registers of the ISERDES The Bitslip pin is not asserted the word propagates through the ISERDES without any realignment Clock Event 2 The second word CDAB has been sampled into the input side registers of the ISERDES The Bitslip pin is asserted which causes the Bitslip controller to shift all bits internally by one bit to the right Clock Event 3 The third word CDAB has been sampled into the input side registers of the ISERDES The Bitslip pin is asserted for a second time which causes the Bitslip controller to shift all bits internally by thr
332. n When the block RAM is not used in cascade mode the default value is NONE Read Width READ WIDTH AIB This attribute determines the A B read port width of the block RAM The valid values are 0 default 1 2 4 9 18 and 36 Write Width WRITE WIDTH AIB This attribute determines the A B write port width of theblock RAM The valid values are 0 default 1 2 4 9 18 and 36 128 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Initialization in VHDL or Verilog Code Write Mode WRITE MODE AIB This attribute determines the write mode of the A B input ports The possible values are WRITE FIRST default READ FIRST and NO CHANGE Additional information on the write modes is in the Write Modes section Block RAM Location Constraints Block RAM instances can have LOC properties attached to them to constrain placement Block RAM placement locations differ from the convention used for naming CLB locations allowing LOC properties to transfer easily from array to array The LOC properties use the following form LOC RAMB36_X Y The RAMB36_XOY0 is the bottom left block RAM location on the device If RAMB36 is constrained to RAMB36_X Y the FIFO cannot be constrained to FIFO36_X Y since they share a location Two RAMBISs can be placed in the same RAMB36 location by using the BEL UPPER LOWER constraint UPPER LOWER inst my_ramb18 LOC inst my_ramb18 LOC
333. n filled Synchronous to WRCLK The offset for this flag is user configurable See Table 4 16 for the clock latency for flag deassertion EMPTY Output FIFO is empty No additional reads are accepted Synchronous to RDCLK 142 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Operations Table 4 15 FIFO I O Port Names and Descriptions Continued Port Name Direction Description ALMOSTEMPTY Output Almost all valid entries in FIFO have been read Synchronous with RDCLK The offset for this flag is user configurable See Table 4 16 for the clock latency for flag deassertion RDCOUNT Output The FIFO data read pointer It is synchronous with RDCLK The value will wrap around if the maximum read pointer value has been reached WRCOUNT Output The FIFO data write pointer It is synchronous with WRCLK The value will wrap around if the maximum write pointer value has been reached WRERR Output When the FIFO is full any additional write operation generates an error flag Synchronous with WRCLK RDERR Output When the FIFO is empty any additional read operation generates an error flag Synchronous with RDCLK FIFO Operations Reset Reset is an asynchronous signal for both multirate and synchronous FIFO Reset must be asserted for three cycles to reset all read and write address counters and initialize flags after power up Reset does no
334. n mode voltage Vem Vp Vp Vn 2 2 Crossover point Vx where Vp Vy 0 AC coupled 266 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards HSTL Class III 1 8V Figure 6 61 shows a sample circuit illustrating a valid termination technique for HSTL Class III 1 8V External Termination IOB HSTL Ill 18 HSTL Ill 18 x m Veer 1 1V IOB IOB Vcco 1 8V Rygp Zg 500 HSTL Ill DCI 18 HSTL IIl DCI 18 Dq O 4 _X Vggr 1 1V ug190_6_59_030306 Figure 6 61 HSTL Class Ill 1 8V Termination Table 6 25 lists the HSTL Class III 1 8V DC voltage specifications Table 6 25 HSTL Class Ill 1 8V DC Voltage Specifications Min Typ Max Veco 1 7 1 8 19 Veep 2 1 1 Ver Veco Vig oll E V E E Varo VoH Veco 0 4 Mos 04 Top at Voy mA 8 E Ior at Vor mA 24 S Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Veg is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Virtex 5 FPGA User Guide www xilinx com 267 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX HSTL Class IV 1 8V Figure 6 62 shows a sample circuit illustrating a valid unidirectional termination technique fo
335. n the DCM is phase shifted beyond the allowed phase shift value or when the absolute delay range of the phase shift delay line is exceeded DO 0 is deasserted if the phase shift feature is not used CLKOUT PHASE SHIFT ZNONE DO 1 CLKIN stopped Asserted when the input clock is stopped CLKIN remains High or Low for one or more clock cycles When CLKIN is stopped the DO 1 CLKIN stopped status is asserted within nine CLKIN cycles When CLKIN is restarted CLKO starts toggling and DO 1 is deasserted within nine clock cycles DO 2 CLKFX stopped Asserted when CLKFX stops The DO 2 CLKFX stopped status is asserted within 260 cycles after CLKEX stopped CLKFX does not resume and DO 2 is not deasserted until the DCM is reset DO 2 is deasserted if the CLKFX CLKFX180 output is not used www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Ports Table 2 4 DCM Status Mapping to DO Bus Continued DO Bit Status Description DO 3 CLKFB stopped Asserted when the feedback clock is stopped CLKFB remains High or Low for one or more clock cycles The DO 3 CLKFB stopped status is asserted within six CLKIN cycles after CLKFB is stopped CLKFB stopped will deassert within six CLKIN cycles when CLKFB resumes after being stopped momentarily An occasionally skipped CLKFB does not affect the DCM operation However stopping CLKFB for a long time can result in the DCM losing LOCKED When
336. nal DCI termination DCI 10B Veco 2 5V DIFF SSTL2 I DCI 2Rygp 2Zg 1002 DJ 0O z P4 2R 2Zg 1000 Ro 25Q VRN 0 DIFF SSTL2 I DCI DIFF SSTL2 DCI 2Rypp 2Zg 1002 2Rypy 2Zg 1000 ugi90 6 65 030506 Figure 6 68 Differential SSTL2 2 5V Class I Unidirectional DCI Termination Table 6 29 lists the differential SSTL2 Class I DC voltage specifications Table 6 29 Differential SSTL2 Class DC Voltage Specifications Min Typ Max Vcco 2 3 2 5 2 7 Input Parameters VTT Vccox 0 5 Vin DO 0 30 Veco 0 30 Vip DC 2 0 3 Veco 0 60 Vip AC 0 62 Veco 0 60 Vix AC 0 95 1 55 Output Parameters Vox AC 1 0 1 5 Notes 1 Vp DC specifies the allowable DC excursion of each differential input Virtex 5 FPGA User Guide 2 Vip DC specifies the input differential voltage required for switching 3 4 Vox AC indicates the voltage where the differential output signals must cross Vix AC indicates the voltage where the differential input signals must cross www xilinx com 275 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX SSTL2 Class II 2 5V Figure 6 69 shows asample circuit illustrating a valid unidirectional termination technique for SSTL2 Class II External Termination rr Rei DCI IOB IOB 2Rypp 2Zg 1000 2Rygp 2Zg 100
337. nality TSCONTROL ODATAIN DATAOUT IODELAY T ERE ODELAY VALUE IDELAY VALUE IODELAY 01 081407 Figure 7 10 Basic Sections of Blocks Related to IODELAY Turnaround with Pertinent Paths Shown When DELAY SRC IO MUXE and MUXF dynamically selects ODATAIN or IDATAIN and ODELAY VALUE or IDELAY VALUE inside the IODELAY block The following Verilog code segment is used for demonstrating bidirectional IODELAY IDDR DDR CLK EDGE SAME EDGE INIT O1 1 b0 INIT O2 1 b0 SRTYPE SYNC IDDR INST C clk CE 1 b1 D DATAOUT R 1 b0 S 1 b0 Q1 Q1 Q2 Q2 IOBUF IOSTANDARD LVCMOS25 IOBUF INST I DATAOUT T TSCONTROL O IDATAIN IO IOPAD DATA 328 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY IODELAY DELAY_SRC IO IDELAY TYPE FIXED IDELAY VALUE 12 ODELAY VALUE 12 REFCLK FREQUENCY 200 0 IODELAY INST C 1 b0 CE 1 b0 DATAIN 1 Db0 IDATAIN IDATAIN INC 1 Db0 ODATAIN ODATAIN RST 1 b0 T TSCONTROL DATAOUT DATAOUT Js ODDR DDR CLK EDGE SAMI INIT 1 b0 SRTYPE SYNC ODDR INST C clk CE 1 b1 D1 D1 D2 D2 R 1 b0 S 1 b0 Q ODATAIN EDGE Er ODDR DDR CLK ED
338. nce DCI 005 218 Inttoduction 2 2 exu a eec pr ERR RR RA Sat rada YN oes Ye eee E 218 DCICascading siero tei oeta E esi eae deed Ln ista da idet ce a 218 Xalinx DCi uuu cR eR 9x be RR URPREES REY RU EOD EERU PENA Rx 221 Controlled Impedance Driver Source Termination 000 cee eee eee 222 Controlled Impedance Driver with Half Impedance Source Termination 223 Input Termination to VCCO Single Termination eese 223 Input Termination to VCCO 2 Split Termination sse 224 Driver with Termination to Vcco Single Termination 225 Driver with Termination to Vcco 2 Split Termination 226 DCI in Virtex 5 Device I O Standards 0 0 00 ccc ee eee eee 227 DCI Usage Examples sis eee cheer Ra eme REED eet aA e sees 228 Virtex 5 FPGA SelectIO Primitives 00002 c cece ete e eee 231 IBUF and IBUEG usaspa sanea eee ee gecr ede RERES seedy erento aa hee ESTO 231 OBUP pr 231 nig LEN 232 IOBUE rete ie et RE UR EEUU CORPER SUE RR UE ERE De EE 232 IBUEDS and IBUFGDS 4 essevotrep ER Ree seen C E ee kN etree Rc d 232 OBUEBDS iste ARRA RR DUX Beles aceon ha NU wa ee RE aduer eas 233 OBUBT DS EI 233 IOBUEDO 5 eade a er RE eee A ee RE Oe PRES aE a eee 233 Virtex 5 FPGA SelectIO Attributes Constraints 00 cee eee eee 234 Location Constraints i sian decides ghd bee CE a Y BRR E EE RS 234 IOSTANDARD Attribute 4 4 4 ER RR bebidas 4 X RREWAG ae ak 234
339. ncy mode of String LOW or HIGH LOW the frequency synthesizer DLL_FREQUENCY_MODE This specifies the frequency mode of String LOW or HIGH LOW the DLL DUTY_CYCLE_CORRECTION This controls the DCM 1X outputs Boolean TRUE or FALSE TRUE CLKO CLK90 CLK180 and CLK270 to exhibit a 50 50 duty cycle Leave this attribute set at the default value DCM PERFORMANCE MODE Allowsselection between maximum String MAX SPEED or MAX SPEED frequency minimum jitter and low MAX RANGE frequency maximum phase shift range FACTORY JF DLL FREQUENCY MODE LOW BIT VECTOR OxFOFO default OxFOFO DLL FREQUENCY MODE HIGH default OxFOF0 PHASE SHIFT This specifies the phase shift Integer 255 to 1023 0 numerator The value range depends on CLKOUT_PHASE_SHIFT and clock frequency STARTUP_WAIT When this attribute is set to TRUE Boolean FALSE or TRUE FALSE the configuration startup sequence waits in the specified cycle until the DCM locks 58 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Design Guidelines DCM Design Guidelines This section provides a detailed description on using the Virtex 5 FPGA DCM and design guidelines Clock Deskew The Virtex 5 FPGA DCM offers a fully digital dedicated on chip clock deskew The deskew feature provides zero propagation delay between the source clock and output clock low clock skew among output clock signals distributed throug
340. nd to Bank A Bank C or both banks DCI cascading can also extend to Bank D since Bank D is in the same column However DCI cascading must also extend to the intervening Bank C If DCI I O standards are implemented in Bank C DCI I O banking compatibility must be observed across all three banks B C and D e DCI cascading can span the entire column as long as the above guidelines are met e Locate adjacent banks Bank location information is best determined from partgen generated package files partgen v XC5VLX50TFF1136 The resulting package file with a pkg extension contains XY I O location information The X designator indicates I Os in the same column The Y designator indicates the position of an I O within a specific bank The bank number is also shown Consecutive Y locations across bank boundaries show adjacent banks For example the XC5VLXT in an FF1136 package shows bank 11 starting with I O X0Y159 end ending with I O location X0Y120 Bank 13 starts with I O X0Y119 and ends with X0Y80 Bank 15 starts with X0Y199 and ends with X0Y160 This indicates that bank 13 is to the south of bank 11 and bank 15 is to the north As the Y coordinates of these two banks are consecutive these two banks are considered consecutive banks and can be DCI cascaded It is possible to cascade through an unbonded bank e DCI cascade is enabled by using the DCI CASCADE constraint described in the constraints guide Xilinx DCI DCI uses two multi
341. ned with CLKO every D cycles of CLKO and every M cycles of CLKFX if M D is a reduced fraction Phase Shifting The DCM provides coarse and fine grained phase shifting For coarse phase control the CLKO CLK90 CLK180 and CLK270 outputs are each phase shifted by 1 4 of the input clock period relative to each other Similarly CLK2X180 and CLKFX180 provide a 180 coarse phase shift of CLK2X and CLKFX respectively The coarse phase shifted clocks are produced from the delay lines of the DLL circuit The phase relationship of these clocks is retained when CLKFB is not connected Fine grained phase shifting uses the CLKOUT PHASE SHIFT and PHASE SHIFT attributes to phase shift DCM output clocks relative to CLKIN Since the CLKIN is used as the reference clock the feedback CLKFB connection is required for the phase shifting circuit to compare the incoming clock with the phase shifted clock The rest of this section describes fine grained phase shifting in the Virtex 5 FPGA DCM Phase Shifting Operation All nine DCM output clocks are adjusted when fine grained phase shifting is activated The phase shift between the rising edges of CLKIN and CLKPB is a specified fraction of the input clock period or a specific amount of DCM_TAP All other DCM output clocks retain their phase relation to CLKO Phase Shift Range The allowed phase shift between CLKIN and CLKFB is limited by the phase shift range There are two separate phase shift ranges e
342. ng RDCLK edge Data flow control is automatic the user need not be concerned about the block RAM addressing sequence although WRCOUNT and RDCOUNT are also brought out if needed for special applications The user must however observe the FULL and EMPTY flags and stop writing when FULL is High and stop reading when EMPTY is High If these rules are violated an active WREN while FULL is High will activate the WRERR flag and an active RDEN while EMPTY is High will activate the RDERR flag In either violation the FIFO content will however be preserved and the address counters will stay valid Programmable ALMOSTFULL and ALMOSTEMPTY flags are brought out to give the user an early warning when the FIFO is approaching its limits Both these flag values can be set by configuration to almost anywhere in the FIFO address range Two operating modes affect the reading of the first word after the FIFO is emptied e Instandard mode the first word written into an empty FIFO will appear at DO after the user has activated RDEN The user must pull the data out of the FIFO e In FWFT mode the first word written into an empty FIFO will automatically appear at DO without the user activating RDEN The next RDEN will then pull the subsequent data word onto DO e Standard and FWFT mode differ only in the reading of the first word entry after the FIFO is empty Use the EN SYN FALSE setting in the following cases e when the clocks are asynchrono
343. nputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At time TEcKo FULL after clock event 2 WRCLK Full is asserted at the FULL output pin of the FIFO If the FIFO is full and a read followed by a write is performed the FULL signal remains asserted Clock Event 3 Write Operation and Assertion of Write Error Signal The write error signal pin is asserted when data going into the FIFO is not written because the FIFO is in a Full state e At time TgpcK pr before clock event 3 WRCLK data 05 becomes valid at the DI inputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At time Trcko wrerr after clock event 3 WRCLK a write error is asserted at the WRERR output pin of the FIFO Data 05 is not written into the FIFO Clock Event 4 Write Operation and Deassertion of Write Error Signal The write error signal pin is deasserted when a user stops trying to write into a full FIFO e At time Trcck wren before clock event 4 WRCLK write enable is deasserted at the WREN input of the FIFO e At time Trcko wnrnn after clock event 4 WRCLK write error is deasserted at the WRERR output pin of the FIFO The write error signal is asserted deasserted at every write clock positive edge As long as both the write enable and Full signals are true write error will remain asserted 152 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX FIFO Timing
344. ns in bank3 and can be paired as listed in Table 3 6 Table 3 6 PLLs in the Top Half Pairing CLKIN1 CLKIN2 IO L9P GC 3 IO L4P GC 3 IO L8P GC 3 IO L3P GC 3 IO L7P GC 3 IO L2P GC 3 IO L6P GC 3 IO L1P GC 3 IO L5P GC 3 IO LO0P GC 3 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 97 98 Chapter 3 Phase Locked Loops PLLs XILINX PLLs in the bottom half of the Virtex 5 device are driven by the global clock pins in bank4 and can be paired as listed in Table 3 6 Table 3 7 PLLs in the Bottom Half Pairing CLKIN1 CLKIN2 IO_L9P_GC_4 IO L4P GC 4 IO L8P GC 4 IO L3P GC 4 IO L7P GC 4 IO L2P GC 4 IO L6P GC 4 IO L1P GC 4 IO L5P GC 4 IO LOP GC 4 Other important notes on these pairings The pin description names do not contain other possible multipurpose functions such as CC VRN VRPor VREF Only the P side pins are shown For differential clock connections use the equivalent N side pin Inside the FPGA only the P side of the differential pin pair can connect to the CMT For a mapping to the actual pin numbers consult the Virtex 5 Family Packaging Specifications PLL Clock Input Signals The PLL clock source can come from several sources including IBUFG Global clock input buffer the PLL will compensate the delay of this path BUFGCTRL Internal global clock buffer the PLL will not compensate the delay of this path IBUF Not
345. nsumes less power SIGNAL PATTERN Attribute Clock and data signals have different electrical profiles and therefore accumulate different amounts of jitter in the IODELAY chain By setting the SIGNAL PATTERN attribute the user enables timing analyzer to account for jitter appropriately when calculating timing A clock signal is periodic in nature and does not have long sequences of consecutive ones or zeroes while data is random in nature and can have long and short sequences of ones and zeroes IODELAY Timing Table 7 11 shows the IODELAY switching characteristics Table 7 11 ODELAY Switching Characteristics Symbol Description TIDELAYRESOLUTION IDELAY tap resolution Ticeck TickcEe CE pin Setup Hold with respect to C Trcck TickiNc INC pin Setup Hold with respect to C TirstcK TickRst RST pin Setup Hold with respect to C Figure 7 9 shows an IDELAY timing diagram It is assumed that IDELAY VALUE 0 DATAOUT Tap 0 Tap 1 UG190_7_09_100107 Figure 7 9 IDELAY Timing Diagram www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY Clock Event 1 On the rising edge of C a reset is detected causing the output DATAOUT to select tap 0 as the output from the 64 tap chain assuming IDELAY_VALUE 0 Clock Event 2 A pulse on CE and INC is captured on the rising edge of C This indicates an increment operation The output changes
346. nt Management e Traces must be referenced to a plane on an adjacent PCB layer e The reference plane must be either GND or the Veco associated with the output driver e The reference layer must remain uninterrupted for its full length from device to device Load Traces e All IOB output buffers must drive controlled impedance traces with characteristic impedance of 509 10 e Total capacitive loading at the far end of the trace input capacitance of receiving device must be no more than 10 pF Power Distribution System Design e Designed according to the Virtex 5 FPGA PC Board Designers Guide Decoupling capacitors per the device guideline Approved solder land patterns Veco and GND planes cannot be separated by more than 5 0 mils 152 u Virtex 5 FPGA User Guide www xilinx com 303 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources 304 Nominal SSO Limit Table 6 40 provides the guidelines for the maximum number of simultaneously switching outputs allowed per bank to avoid the effects of ground bounce 2 XILINX Table 6 40 Maximum Number of Simultaneously Switching Outputs per Bank Voltage 1 2V IOSTANDARD Limit per 20 pin Bank Limit per 40 pin Bank HSTL I 12 20 40 LVCMOS12 2 slow 20 40 LVCMOS12 4 slow 20 40 LVCMOS12 6 slow 20 40 LVCMOS12 8 slow 20 40 LVCMOS12 2 fast 20 40 LVCMOS12_4 fast 20 40 LVCMOS12 6 fast 20 40 LVCMOS12 8 fast 20 40
347. nt must be met Violating this setup time may result in a glitch Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL Figure 1 9 illustrates the timing diagram for BUFGMUX T BCCCK_CE A HELL CNW Lu NN T LN l N 4 NL l O r DNE epee TIgccko o Taccko o l i begin l i switching using I1 s E MEA e eu Say T T T ugi90 1 09 032306 Figure 1 9 BUFGMUX Timing Diagram Virtex 5 FPGA User Guide www xilinx com 29 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX In Figure 1 9 e The current clock is IO e Sis activated High e IfTO is currently High the multiplexer waits for I0 to deassert Low e Once I0 is Low the multiplexer output stays Low until I1 transitions High to Low e When Il transitions from High to Low the output switches to I1 e If Setup Hold are met no glitches or short pulses can appear on the output BUFGMUX 1 is rising edge sensitive and held at High prior to input switch Figure 1 10 illustrates the timing diagram for BUFGMUX 1 A LOC constraint is available for BUFGMUX and BUFGMUX 1 TBCCCK CE TBccko O ug190 1 10 032306 Figure 1 10 BUFGMUX 1 Timing Diagram In Figure 1 10 e The current clock is IO e Sis activated High e If1I0is currently Low the multiplexer waits for IO to be asserted High e Once I0 is High the m
348. nted in the input flip flop and reduces any positive hold times required The clock path delay includes the delay through the IBUFG route DCM BUFG and clock tree to the destination flip flop If the feedback delay equals the clock path delay the effective clock path delay is zero System Synchronous Setting Default By default the feedback delay is set to system synchronous mode The primary timing requirements for a system synchronous system are non positive hold times or minimally positive hold times and minimal clock to out and setup times Faster clock to out and setup times allow shorter system clock periods Ideally the purpose of a DLL is to zero out the clock delay to produce faster clock to out and non positive hold times The system synchronous setting default for DESKEW ADJUST configures the feedback delay element to guarantee non positive hold times for all input IOB registers The exact delay number added to the feedback path is device size dependent This is determined by characterization In the timing report this is included as timing reduction to input clock path represented by the Tpcwrvo parameter As shown in Figure 2 4 the feedback path includes tap delays in the default setting red line The pin to pin timing parameters with DCM on the Virtex 5 FPGA Data Sheet reflects the setup hold and clock to out times when the DCM is in system synchronous mode In some situations the DCM does not add this extra feedback
349. nts is illustrated in Figure 7 19 REFCLK Instantiated by user e REFCLK RDY RST IDELAYCTRL RST 3 4 REFCLK RDY RDY IDELAYCTRL RST Replicated for all IDELAYCTRL sites REFCLK RDY IDELAYCTRL T Auto generated by Mapper tool Figure 7 19 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 ug190_7_14_041306 Instantiate IDELAYCTRL Without LOC Constraints RDY Connected www xilinx com 337 Chapter 7 SelectlO Logic Resources XILINX Instantiating IDELAYCTRL with Location LOC Constraints The most efficient way to use the IDELAYCTRL module is to define and lock down the placement of every IDELAYCTRL instance used in a design This is done by instantiating the IDELAYCTRL instances with location LOC constraints The user must define and lock placement of all ISERDES and IDELAY components using the delay element IDELAY TYPE attribute set to FIXED or VARIABLE Once completed IDELAYCTRL sites can be chosen and LOC constraints assigned Xilinx strongly recommends using IDELAYCTRL with a LOC constraint When not using an IDELAY with IDELAY TYPE in FIXED or VARIABLE mode do not assign a LOC constraint to the IDELAYCTRL for that clock region Location Constraints Each IDELAYCTRL module has XY location coordinates X row Y column To constrain placement IDELAYCTRL instances can have LOC properties attac
350. o 1 5V d IOB Veco 1 5V Rypp Zo 500 509 gt ANSETE ug190_6_37_030206 Figure 6 38 GTLP DCI Internal Parallel Driver and Receiver Termination Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 246 XILINX Specific Guidelines for I O Supported Standards Table 6 14 lists the GTLP DC voltage specifications Table 6 14 GTLP DC Voltage Specifications Min Typ Max Vcco E E E Vesp N x Vrr 0 88 1 0 1 12 Var 1 35 1 5 1 65 Viu Vrer 0 1 0 98 1 1 E Vi um E 0 9 1 02 VoH 7 z Vsr 0 3 0 45 0 6 Ion at Vor mA z Ior at Vor mA at 0 6V 36 Io at Vor mA at 0 3V E 48 Notes 1 N must be greater than or equal to 0 653 and less than or equal to 0 68 HSTL High Speed Transceiver Logic The High Speed Transceiver Logic HSTL standard is a general purpose high speed bus standard sponsored by IBM EIA JESD8 6 The 1 5V and 1 8V have four variations or classes To support clocking high speed memory interfaces a differential version of this standard was added Virtex 5 FPGA I O supports all four classes for 1 5V and 1 8V and the differential versions of classes I and II These differential versions of the standard require a differential amplifier input buffer and a push pull output buffer HSTL I HSTL Ill HSTL 18 HSTL ll 18 HSTL I 12 HSTL I uses Vcco 2 as a parallel termination voltage Vrr HSTL
351. o a clock edge at the ODDR CLK pin is valid before or after the pad is driven from the 3 state control After the 3 state control propagates through to the PAD and the IODELAY is turned around the clock to output time of the ODDR flip flop through the IODELAY element with the ODELAY VALUE setting solely determines the clock to output time to the pad IDELAYCTRL Overview If the IODELAY or ISERDES primitive is instantiated with the IOBDELAY TYPE attribute set to FIXED or VARIABLE the IDELAYCTRL module must be instantiated The IDELAYCTRL module continuously calibrates the individual delay elements IODELAY in its region see Figure 7 17 page 336 to reduce the effects of process voltage and temperature variations The IDELAYCTRL module calibrates IODELAY using the user supplied REFCLK Virtex 5 FPGA User Guide www xilinx com 333 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX IDELAYCTRL Primitive Figure 7 15 shows the IDELAYCTRL primitive IDELAYCTRL REFCLK RDY RST ugi 90 7 10 041206 Figure 7 15 IDELAYCTRL Primitive IDELAYCTRL Ports RST Reset The reset input pin RST is an active High asynchronous reset IDELAYCTRL must be reset after configuration and the REFCLK signal has stabilized to ensure proper IODELAY operation A reset pulse width TIDELAYCTRL gpw is required IDELAYCTRL must be reset after configuration E REFCLK Reference Clock The reference clock REFCLK provi
352. ock CLKDV 0 6 ee cee nee 51 Frequency Synthesis Output Clock CLKFX 0 6 occ eens 51 Frequency Synthesis Output Clock 180 CLKFX180 6 0 2 eee eee eee 51 DCM Status and Data Output Ports en 52 Locked Output LOCKED 6 050400 steed ovis he peer es abe TE De agen eds 52 Phase Shift Done Output PSDONE 6 oe e 52 Status or Dynamic Reconfiguration Data Output DO 15 0 000 52 Dynamic Reconfiguration Ready Output DRDY 00 00 53 DCM Attributes Ceres retur veg ial eR de toes 54 CLKDV DIVIDE Attributes eeuen iere cc ce eR e 54 CLKFX MULTIPLY and CLKFX DIVIDE Attribute 0 0 0 0 000 cee 54 CLKIN PERIOD Attribute llssseeeeeeee RR s 54 CLKIN DIVIDE BY 2 Attribute 0 0 0 0 ccc RR ne 55 CLKOUT PHASE SHIFT Attribute 0 cc ccc ne 55 CLK FEEDBACK Attribute 0 00 00 cc eee tent en 55 DESKEW ADJUST A trib tite esi ete e Re eer ec Rer ay atone a 56 DFS FREQUENCY MODE Attribute 00 0 56 DLL FREQUENCY MODE Attribute 0 0 0 00 n 56 DUTY CYCLE CORRECTION Attribute 0 0 0 0 0 0 ccc eee 56 DCM PERFORMANCE MODE Attribute sslseleeeeee ee 56 FACTORY JF Attrib te occetb eet er ed dd edo oe Ed ee ee 57 PHASE SHIFF Attribute 1 eei RASe RE brat eee E doe Eee ds dt eds 57 STARTUP WAIT Attribute sssseseeeeee RR I ls 57 DCM Design CIO DIS au sa ehe ep a ERO IRR Ud et HR eV get ie deed 59 Clock Deskew re Aa etl ade EP E
353. ode is used to detect single and double bit errors in block RAM data read out Single bit errors are then corrected in the output data Block RAM Library Primitives The Virtex 5 FPGA block RAM library primitives RAMB18 and RAMB36 are the basic building blocks for all block RAM configurations Other block RAM primitives and macros are based on these primitives Some block RAM attributes can only be configured using one of these primitives e g pipeline register cascade etc See the Block RAM Attributes section The input and output data buses are represented by two buses for 9 bit width 8 1 18 bit width 16 2 and 36 bit width 32 4 configurations The ninth bit associated with each byte can store parity error correction bits or serve as additional data bits No specific function is performed on the ninth bit The separate bus for parity bits facilitates some designs However other designs safely use a 9 bit 18 bit or 36 bit bus by merging the Virtex 5 FPGA User Guide www xilinx com 121 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX regular data bus with the parity bus Read write and storage operations are identical for all bits including the parity bits Figure 4 9 illustrates all the I O ports of the 36 Kb true dual port block RAM primitive RAMB36 Table 4 5 lists these primitives CASCADEOUTLATA CASCADEOUTLATB CASCADEOUTREGA CASCADEOUTREGB CASCADEINLATA CASCADEINLATB CASCADEINREGA CAS
354. oes not cause a glitch or disruption on the output The tap setting of the IODELAY element in the clock path can be adjusted without disrupting state machines that could be running on that clock IODELAY VHDL and Verilog Instantiation Template VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives and submodules In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signals names Fixed Delay Mode The Libraries Guide includes templates showing how to instantiate the IODELAY module in fixed delay mode with a tap setting of 31 IDELAYCTRL must also be instantiated when operating in this mode See IDELAYCTRL Overview page 333 Variable Delay Mode The Libraries Guide shows how to instantiate the IODELAY module in variable delay mode IDELAYCTRL must also be instantiated when operating in this mode See IDELAYCTRL Overview page 333 Virtex 5 FPGA User Guide www xilinx com 327 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX IODELAY Turnaround Time Usage Model When using IODELAY in bidirectional mode the turnaround time needs to be considered Figure 7 10 shows a simplified block diagram of the IODELAY in the Virtex 5 FPGA IOB that applies to one use of the bidirectional IODELAY functio
355. of powerful clock management features Clock Deskew The DCM contains a delay locked loop DLL to completely eliminate clock distribution delays by deskewing the DCM s output clocks with respect to the input clock The DLL contains delay elements individual small buffers and control logic The incoming clock drives a chain of delay elements thus the output of every delay element represents a version of the incoming clock delayed at a different point 44 The control logic contains a phase detector and a delay line selector The phase detector compares the incoming clock signal CLKIN against a feedback input CLKFB and steers the delay line selector essentially adding delay to the output of DCM until the CLKIN and CLKFB coincide www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA User Guide DCM Summary Frequency Synthesis Separate outputs provide a doubled frequency CLK2X and CLK2X180 Another output CLKDV provides a frequency that is a specified fraction of the input frequency Two other outputs CLKFX and CLKFX180 provide an output frequency derived from the input clock by simultaneous frequency division and multiplication The user can specify any integer multiplier M and divisor D within the range specified in the DCM Timing Parameters section of the Virtex 5 FPGA Data Sheet An internal calculator determines the appropriate tap selection to make the output
356. oggling Within 257 to 260 clock cycles after this event the CLKFX stopped status DO 2 is asserted to indicate that the CLKFX output stops toggling e Clock Event 3 The CLKFB input stops toggling Within 257 to 260 clock cycles after this event the CLKFB stopped status DO 3 is asserted to indicate that the CLKFB output stops toggling e Clock Event 4 The CLKIN input stops toggling Within 9 clock cycles after this event DO 1 is asserted to indicate that the CLKIN output stops toggling Virtex 5 FPGA User Guide www xilinx com 83 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX Legacy Support 84 The Virtex 5 FPGA DCMs DCM_BASE and DCM_ADV have exactly the same port names as the Virtex 4 FPGA DCMs However the DRP address mapping has changed Refer to the Virtex 5 FPGA Configuration Guide for more information The Virtex 5 device supports the Virtex II family and Virtex II Pro FPGA DCM primitives The mapping of Virtex II or Virtex II Pro FPGA DCMs to Virtex 5 FPGA DCM ADVs are as follows e CLKIN CLKFB PSCLK PSINDEC PSEN RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKFX CLKFX180 CLKDV PSDONE LOCKED of Virtex 5 FPGA primitives DCM BASE DCM ADV map to the same corresponding pins of a Virtex II or Virtex II Pro FPGA DCM e Dynamic reconfiguration pins of Virtex 5 FPGA DCM_ADV are not accessible when a Virtex II or Virtex II Pro FPGA DCM is used except for DO 15 0 e
357. ols CLKDV such Real 2 0 that the source clock is divided by 1 5 2 0 2 5 3 0 3 5 4 0 4 5 N 5 0 5 5 6 0 6 5 7 0 7 5 8 9 This feature provides automatic 10 11 12 13 14 15 16 duty cycle correction such that the CLKDV output pin has a 50 50 duty cycle always in low frequency mode as well as for all integer values of the division factor N in high frequency mode CLKFX DIVIDE Integer 1 to 32 1 CLKFX MULTIPLY Integer 2 to 32 4 CLKIN PERIOD This specifies the source clock Real in ns 0 0 period to help DCM adjust for optimum CLKFX CLKFX180 outputs CLKIN DIVIDE BY 2 This attribute allows for the input Boolean FALSE or TRUE FALSE clock frequency to be divided in half when such a reduction is necessary to meet the DCM input clock frequency requirements Virtex 5 FPGA User Guide www xilinx com 57 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology Table 2 6 DCM Attributes Continued XILINX DCM Attribute Name Description Values Default Value CLKOUT_PHASE_SHIFT This attribute specifies the phase String NONE or FIXED or NONE shift mode VARIABLE_POSITIVE or VARIABLE_CENTER or DIRECT DESKEW_ADJUST This affects the amount of delay in String SYSTEM the feedback path and should be SYSTEM SYNCHRONOUS SYNCHRONOUS used for source synchronous or interfaces SOURCE_SYNCHRONOUS DFS_FREQUENCY_MODE This specifies the freque
358. oltage Specifications Min Typ Max Vcco 1 14 1 2 1 26 Vggp 2 Veco x 0 48 0 6 Vcco x 0 52 Ver Veco x 0 5 Vin Vrer 0 08 Vit Vngr 0 08 Vou Veco 0 315 VoL 0 315 Tox at Voy mA 6 3 Tor at Vor mA 6 3 Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user SSTL Stub Series Terminated Logic The Stub Series Terminated Logic SSTL for 2 5V SSTL2 and 1 8V SSTL18 standards are for general purpose memory buses SSTL2 is defined by the JEDEC standard JESD8 9B and SSTL18 is defined by the JEDEC standard JESD8 15 The SSTL2 standard has two classes Class I is for unidirectional and class II is for bidirectional signaling Virtex 5 FPGA I O supports both standards for single ended signaling and differential signaling This standard requires a differential amplifier input buffer and a push pull output buffer Virtex 5 FPGA User Guide www xilinx com 271 UG190 v4 4 December 2 2008 272 Chapter 6 SelectlO Resources XILINX SSTL2 I SSTL18_l Class I signaling uses Vtr Vcco 2 as a parallel termination voltage to a 50 O resistor at the receiver A series resistor 25 O at 2 5V 20 O at 1 8V must be connected to the transmitter output SSTL2 I DCI SSTL18 I DCI The DCI transmitter provides
359. on lese 327 IODELAY VHDL and Verilog Instantiation Template 0 00000 327 IODELAY Turnaround Time Usage Model 6 2 0 cee 328 IDELAY CTRL Overview 5v Sida ee Bas else eae REY X REX Wu er 333 IDELAYCTRL Primitive 0 0 ce nee e eee eet ee enees 334 IDELAYCTRE Potts iis eek sess aces PEE ea eves ea dx Ee ed 334 IDELAYCTRL Timing vis 224543 22d WERDE RESIYEECEREO C E dares cee as eden 335 IDELAYCIRE Locations xx 6 840 y eae ede bees ose bie ee aes aq gr aue 335 IDELAYCTRL Usage and Design Guidelines naan 00 0c cece eee eee ee 336 OLOGIC Reso rces vedo pe Dw oR ae ea Ree HAIN ERO ND WU ES 340 Combinatorial Output Data and 3 State Control Path 0 e eee ee eee 341 Output DDR Overview ODDR sseeeeee e 341 OPPOSITE BDGE MOde 23 redes det nes deae eee e ea D C Meese t RR e 342 SAME EDGE Mode 0 ccc eee hh hrs 342 Clock Forwarding deba pate ates a am ep auteur tek s tl iura 343 Output DDR Primitive ODDR lssssseeeeeee ee 343 ODDR VHDL and Verilog Templates 1 2 2 0 666 cece eee 344 OLOGIC Timing Models 0 0 0 6 eee s 344 Timing Characteristics se s Lote bedeutete me petes bte Bieter eae ee 344 Chapter 8 Advanced SelectlO Logic Resources Introduction ssssssseeee Re e le 349 Input Serial to Parallel Logic Resources ISERDES 349 ISERDES Primitive ISERDES_NODELAY 0 000 cee cee cece eee 350
360. on chapter of the Virtex 5 FPGA Configuration Guide for more information Dynamic Reconfiguration Write Enable Input DWE The dynamic reconfiguration write enable DWE input pin provides the write enable control signal to write the DI data into the DADDR address When not used it must be tied Low See the Dynamic Reconfiguration chapter of the Virtex 5 FPGA Configuration Guide for more information Dynamic Reconfiguration Enable Input DEN The dynamic reconfiguration enable DEN input pin provides the enable control signal to access the dynamic reconfiguration feature When the dynamic reconfiguration feature is not used DEN must be tied Low When DEN is tied Low DO reflects the DCM status signals See the Dynamic Reconfiguration chapter of the Virtex 5 FPGA Configuration Guide for more information DCM Clock Output Ports A DCM provides nine clock outputs with specific frequency and phase relationships When CLKEB is connected all DCM clock outputs have a fixed phase relationship to CLKIN When CLKPB is not connected the DCM outputs are not phase aligned However the phase relationship between all output clocks is preserved 1x Output Clock CLKO The CLKO output clock provides a clock with the same frequency as the DCM s effective CLKIN frequency By default the effective input clock frequency is equal to the CLKIN frequency Set the CLKIN DIVIDE BY 2 attribute to TRUE to make the effective CLKIN frequency the actual CLKIN f
361. on between DCM and PLL www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX VHDL and Verilog Templates and the Clocking Wizard IBUFG DCM1 gt CLKIN CLKO L CLKFBIN CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG CLKOUTO CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT IBUFG DCM CLKO L gt CLKFBIN CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 ug190 2 18 040906 Figure 2 16 Two DCMs Driving a PLL VHDL and Verilog Templates and the Clocking Wizard VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives In addition VHDL and Verilog files are generated by the Clocking Wizard in the ISE software The Clocking Wizard sets appropriate DCM attributes input output clocks and buffers for general use cases Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 79 Chapter 2 Clock Management Technology XILINX DCM Timing Models The following timing diagrams describe the behavior of the DCM clock outputs under four different conditions 1 Reset Lock 2 Fixed Phase Shifting 3 Variable Phase Shifting 4 Status Flags Reset Lock In Figure 2 17 the DCM is already locked After the reset signal is applied all output clocks are stabilized to the desired values and the LOCKED signal is asserted 1 a e ENES
362. on has more details on using DCI Since the LVDCI 33 standard does not offer input termination source termination must be implemented on the driver side Figure 6 91 shows the recommended external source termination resistors to be incorporated on the external device side The total impedance of the LVTTL LVCMOS driver added to the series termination resistor Ry must match the board trace impedance 10 percent to minimize overshoot and undershoot An IBIS simulation is advised for calculating the exact value needed for Ro Veco 3 3V Veco HnEF Ro Roriver IBUF_LVDCI_33 LVTTL _ LVCMOS Zo 502 typical Virtex 5 FPGA I O Device Driver OBUF_LVDCI_33 External Device ugi90 6 86 030506 Figure 6 91 Connecting LVTTL or LVCMOS Using the LVDCI 33 Standard www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Rules for Combining I O Standards in the Same Bank The connection scheme shown in Figure 6 92 is for a bidirectional bus scenario The signal performance may be degraded by Rp Therefore it is also recommended to verify the Ro value and performance with an IBIS simulation OBUFT LVDCI 33 Ro w gt IBUF LVDCI Virtex 5 FPGA External Device ugi 90 6 87 030506 Figure 6 92 3 3V I O Configuration When designing with the LVDCI_33 standard e The output drive strength and slew rates are not programmable The output impedance references the VRP and VRN res
363. onfigurations This feature is useful when using block RAM to interface with a microprocessor Byte wide write enable is not available in the multirate FIFO or ECC mode Byte wide write enable is further described in the Additional RAMB18 and RAMB36 Primitive Design Considerations section Figure 4 8 shows the byte wide write enable timing diagram for the RAMB36 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 120 www xilinx com XILINX Block RAM Library Primitives Table 4 4 Available Byte wide Write Enables Primitive Maximum Bit Width Number of Byte wide Write Enables RAMB36 36 4 RAMB36SDP 72 8 RAMB18 18 2 RAMB18SDP 36 4 When the RAMB36 is configured for a 36 bit or 18 bit wide data path any port can restrict writing to specified byte locations within the data word If configured in READ_FIRST mode the DO bus shows the previous content of the whole addressed word In WRITE_FIRST mode DO shows a combination of the newly written enabled byte s and the initial memory contents of the unwritten bytes CLK NA NY NY N M TE ECHO GRE CAMS EET an EN Disabled Read Write Byte Write I Read MEM bb 1111 MEM bb 1122 ugi 90 4 10 032106 Figure 4 8 Byte wide Write Operation Waveforms x36 WRITE FIRST Block RAM Error Correction Code Both block RAM and FIFO implementations of the 36 Kb block RAM support a 64 bit Error Correction Code ECC implementation The c
364. onously forces all DCM outputs Low the LOCKED signal all status signals and all output clocks after some propagation delay When the reset is asserted the last cycle of the clocks can exhibit a short pulse and a severely distorted duty cycle or no longer be deskewed with respect to one another while asserting High Deasserting the RST signal starts the locking process at the next CLKIN cycle To ensure a proper DCM reset and locking process the RST signal must be held until the CLKIN signal is present and stable for at least three CLKIN cycles The time it takes for the DCM to lock after a reset is specified in the Virtex 5 FPGA Data Sheet as LOCK DLL for a DLL output and LOCK FX for a DFS output These are the CLK and CLKFX outputs described in DCM Clock Output Ports The DCM locks faster at higher frequencies The worse case numbers are specified in the Virtex 5 FPGA Data Sheet In all designs the DCM must be held in reset until CLKIN is stable Phase Shift Increment Decrement Input PSINCDEC The phase shift increment decrement PSINCDEC input signal must be synchronous with PSCLK The PSINCDEC input signal is used to increment or decrement the phase shift factor when PSEN is activated As a result the output clocks are shifted The PSINCDEC signal is asserted High for increment or deasserted Low for decrement This input must be tied to ground when the CLKOUT PHASE SHIFT attribute is set to NONE or FIXED Virtex 5 FPGA User
365. ot tolerated e Does not eliminate jitter The deskew circuit output jitter is the accumulation of input jitter and any added jitter value due to the deskew circuit e The completion of configuration can be delayed until after DCM locks to guarantee the system clock is established prior to initiating the device Frequency Synthesis The DCM provides several flexible methods for generating new clock frequencies Each method has a different operating frequency range and different AC characteristics The CLK2X and CLK2X180 outputs double the clock frequency The CLKDV output provides a divided output clock lower frequency with division options of 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 6 5 7 7 5 8 9 10 11 12 13 14 15 and 16 The DCM also offers fully digital dedicated frequency synthesizer outputs CLKFX and its opposite phase CLKFX180 The output frequency can be any function of the input clock frequency described by M D where M is the multiplier numerator and D is the divisor denominator The frequency synthesized outputs can drive the global clock routing networks within the device The well buffered global clock distribution network minimizes clock skew due to differences in distance or loading Frequency Synthesis Operation The DCM clock output CLKFX is any M D factor of the clock input to the DCM Specifications for M and D as well as input and output frequency ranges for the frequency synthesizer are provided in
366. output bus DOP 7 0 Output Data output parity bus Used in encode only mode to output the stored ECC parity bits SBITERR Output Single bit error status DBITERR Output Double bit error status ECCPARITY 7 0 Output ECC encoder output bus Notes 1 Hamming code implemented in the block RAM ECC logic detects one of three conditions no detectable error single bit error detected and corrected on DO but not corrected in the memory and double bit error detected without correction SBITERR and DBITERR indicate these three conditions Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 161 Chapter 4 Block RAM XILINX Table 4 22 lists and describes the FIFO ECC I O port names Table 4 22 FIFO ECC Port Names and Descriptions Port Name Direction Signal Description DI 63 0 Input Data input bus DIP 7 0 Input Data input parity bus Not used when standard mode is used WREN Input Write enable When WREN 1 data will be written into memory When WREN 0 write is disabled RDEN Input Read enable When RDEN 1 data will be read from memory When RDEN 0 read is disabled RST Input Asynchronous reset of FIFO counter and flags Reset must be asserted for three clock cycles Reset does not affect DO or ECC signals WRCLK Input Clock for write operations RDCLK Input Clock for read operations DO 63 0 Output D
367. oward the output mode as set by the 3 state TSCONTROL signal coming from the ODDR T flip flop This controls the selection of MUXes E and F for the output path and ODELAY VALUE respectively Additionally the OBUF changes to not being 3 stated and starts to drive the PAD TSCONTROL ODATAIN DATAOUT IODELAY Ten IODELAY_04_082107 Figure 7 13 ODELAY and IOB in Output Mode when 3 state is Enabled 332 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Output Delay Element IODELAY The timing diagram in Figure 7 14 shows the relevant signal timing for the case where the I O switches from input to an output using 3 state control The switching characteristics shown in the diagram are specified in the Virtex 5 FPGA Data Sheet I i Clock to Out with ODELAY VALUE 0 I I 1 Clock to Out with 1 ODELAY_VALUE 63 Li f T ODDR CLK Clock to DATAOUT is variable based on internal timing the ODELAY VALUE 0 63 DATAOUT TSCONTROL PD Prevous za m Clock to PAD being driven or T ocka Toppo_opatain Toop IODELAY 05 082107 Figure 7 14 Relevant Timing Signals used to Examine IODELAY Timing when an IOB Changes from an Input to an Output 3 state control activities on the OBUF of the IOB and ODDR flip flop to PAD timing are in parallel with each other depending on the ODELAY VALUE setting the final output value in response t
368. page 336 Chapter 8 Complete rewrite of the chapter Many changes to descriptions tables and figures Virtex 5 FPGA User Guide www xilinx com UG190 v4 4 December 2 2008 Date 02 05 08 Version 33 Revision Chapter 1 Updated discussion under I O Clock Buffer BUFIO on page 37 Chapter 3 Revised LOCKED description in Table 3 3 page 93 Revised discussion under Detailed VCO and Output Counter Waveforms page 100 Chapter 5 Updated description of Figure 5 17 Chapter 7 Updated description under Clock Input C on page 323 Updated default value to TRUE for HIGH PERFORMANCE MODE in Table 7 10 page 325 Chapter 8 Revised TRISTATE WIDTH in Table 8 7 page 370 Updated discussion under TRISTATE WIDTH Attribute and added section on OSERDES Clocking Methods page 371 03 31 08 4 0 Added the FXT platform to Table 1 5 Table 2 1 and Table 5 2 Revised timing event description under Figure 1 21 page 40 Revised Dynamic Reconfiguration page 69 to remove adjustment of PHASE SHIFT Added CLKOUT 0 5 DESKEW ADJUST to Table 3 4 page 95 Corrected READ WIDTH B 9 to WRITE WIDTH B 9 in the block RAM usage rules on page 112 Revised High Speed Clock for Strobe Based Memory Interfaces OCLK page 353 Corrected BITSLIP ENABLE value from string to boolean in ISERDES NODELAY Attributes page 354 04 25 08 4 1 Added the XC5VSX240T to Table 1 5 Table 2 1 and Table 5 2 Revised F
369. pendent Read and Write Port Width To specify the port widths using the dual port mode of the block RAM designers must use the READ WIDTH A B and WRITE WIDTH A B attributes The following rules should be considered Designing a single port block RAM requires the port pair widths of one write and one read to be set e g READ WIDTH A and WRITE WIDTH A Designing a dual port block RAM requires all port widths to be set When using these attributes if both write ports or both read ports are set to 0 the Xilinx ISE tools will not implement the design In simple dual port mode the port width is fixed and the read port width is equal to the write port width The RAMB18 has a data port width of 36 while the RAMB36 has a data port width of 72 RAMB18 and RAMB36 Port Mapping Design Rules The Virtex 5 FPGA block RAM are configurable to various port widths and sizes Depending on the configuration some data pins and address pins are not used Table 4 6 page 124 shows the pins used in various configurations In addition to the information in Table 4 6 the following rules are useful to determine port connections for the RAMB36 1 When using RAMB36 if the DI A B pins are less than 32 bits wide concatenate 32 DI BIT WIDTH logic zeros to the front of DI A B If the DIP A B pins are less than 4 bits wide concatenate 4 DIP BIT WIDTH logic zeros to the front of DIP A B DIP A B can be left unconnected when not in
370. pere Rer aee esee edet aee ds 360 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Reset Input Iming essnee rassid fX REX eae a eae cade sda E aa a 360 ISERDES VHDL and Verilog Instantiation Template nanana nananana 361 BITSLIP Submodule spisi suerrerd ryo cect EREE n 362 Bitslip Operation i e epa ou Sa E bi bU R E AE AEA 362 Bitslip Timing Model and Parameters ununun annann cece eens 364 Output Parallel to Serial Logic Resources OSERDES 366 Data Parallel to Serial Converter eee 366 3 State Parallel to Serial Conversion llle 367 OSERDES Primitive spres irise eg esce t ee PE Aide uo Pe ie sce ace ae aec n aed 367 OSERDES POEFIS 25 ose tane exu ue heel usus Thu us E A ea sd ss 368 Data Path Output OQ oe dieere teen Haee e H9 dete deren tee 368 3 state Control Output TO esses hne 368 High Speed ClockInput CLK 2 6 cee e 368 Divided Clock Input CLKDIV 0 ccc cere teens 368 Parallel Data Inputs D1 to D6 2 eens 369 Output Data Clock Enable OCE 1 6 eee eens 369 Parallel 3 state Inputs T1 to TA 0 eee eee 369 3 state Signal Clock Enable TCE 1 0 cee ccc ete ene 369 Reset Input 5R id cie see BP Ear d Hee eer be rere etie See 369 OSERDES Attrib tes i rex Rep goede ee a Racer TRA yaq a e s 370 DATA RATE OQ Attribute 0 eee has 370 DATA RATE TO Attributes css led ido
371. port width as shown in Table 4 10 These attributes are hex encoded bit vectors and the default value is 0 In cascade mode both the upper and lower block RAM should be initialized to the same value Output Latches Registers Synchronous Set Reset SRVAL AIB The SRVAL single port or SRVAL A and SRVAL B dual port attributes define output latch values when the SSR input is asserted The width of the SRVAL SRVAL A and SRVAL B attribute is the port width as shown in Table 4 10 These attributes are hex encoded bit vectors and the default value is 0 This attribute sets the value of the output register when the optional output register attribute is set When the register is not used the latch gets set to the SRVAL instead In the 36 bit mode SRVAL 35 32 corresponds to DP 3 0 Table 4 10 Port Width Values Port Data Width DOP Bus DO Bus INIT SRVAL 1 NA 0 1 2 NA 1 07 2 4 NA 3 0 4 9 0 7 0 1 8 9 18 lt 1 0 gt lt 15 0 gt 2 16 18 36 lt 3 0 gt lt 31 0 gt 4 32 36 Optional Output Register On Off Switch DO AIB _REG This attribute sets the number of pipeline register at A B output of the block RAM The valid values are 0 default or 1 Extended Mode Address Determinant RAM EXTENSION AIB This attribute determines whether the block RAM of interest has its A B port as UPPER LOWER address when using the cascade mode Refer to the Cascadable Block RAM sectio
372. proximately 9 mV of additional power system disturbance will occur The additional power system disturbance is compared to the nominal power system disturbance and a scale factor is derived from the relationship CLoap uspg is the user s average load capacitance 7 Example calculations show how each scale factor is computed as well as the SSO allowance The system parameters used in this example are Lpps_USER 11nH VDISTURBANCE_USER 7 9550 mV CLOAD_USER 22 pF First Scaling Factor SF1 Lpps NOM LPDS_USER 1 0 nH 1 1 nH 0 909 Second Scaling Factor SF2 VDISTURBANCE_USER V DISTURBANCE_NOM 550 mV 600 mV 0 917 Third Scaling Factor SF3 VDISTURBANCE_NOM CLOAD_USER CLOAD_NOM X 9 mV pF VDISTURBANCE_NOM 600 mV 22 pF 15 pF x 9 mV pF 600 mV 600 mV 663 mV 0 905 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Simultaneous Switching Output Limits SSO Allowance SF1 x SF2 x SF3 x 100 0 909x 0 917 x 0 905 x 100 75 496 Weighted Average Calculation of SSO This section describes the SSO calculation where the SSO contributions of all I O in a bank are combined into a single figure SSO of an individual bank is calculated by summing the SSO contributions of the individual I O standards in the bank The SSO contribution is the percentage of full utilization of any one I O standard in any one bank For drivers of each I O standard the calculation follows
373. put delay based on the direction indicated by the 3 state signal T from the OLOGIC block 3 state Input T This is the 3 state input control port For bidirectional operation the T pin signal also controls the T pin of the OBUFT Clock Input C All control inputs to IODELAY primitive RST CE and INC are synchronous to the clock input C A clock must be connected to this port when IODELAY is configured in variable mode C can be locally inverted and must be supplied by a global or regional clock buffer This clock should be connected to the same clock in the SelectIO logic resources when using ISERDES and OSERDES C is connected to CLKDIV Virtex 5 FPGA User Guide www xilinx com 323 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX Module Reset RST The IODELAY reset signal RST resets the delay element to a value set by the IDELAY_VALUE or ODELAY_VALUE attribute If these attributes are not specified a value of zero is assumed The RST signal is an active High reset and is synchronous to the input clock signal C The control pins are summarized in Table 7 8 Table 7 8 Control Pin Descriptions Pin Type Value Description INC Input 1 Increment decrement number of tap delays CE Input 1 Enable increment decrement function RST put 1 Reset delay element to pre programmed value If no value programmed reset to 0 Increment Decrement Signals CE INC The incre
374. r HSTL Class IV 1 8V External Termination Va 1 8V Va 1 8V iOB IOB HSTL IV 18 HSTL IV 18 Rp Zj 502 Rp Zg 509 i d C Zo Dd l VpRep 11V L DCI IOB IOB Veco 18V Veco 18V Rygp Zg 502 Ry ap Zo 500 HSTL_IV_DCI_18 HSTL_IV_DCI_18 Vaer 1 1V ug190_6_60_030306 Figure 6 62 HSTL Class IV 1 8V with Unidirectional Termination Figure 6 63 shows a sample circuit illustrating a valid bidirectional termination technique for HSTL Class IV 1 8V 268 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards External Termination TL Var 1 8V MersdBU p Ecce dS HSTL IV 18 HSTL IV 18 Rp Zg 500 Rp Z 509 Vaer 1 1V DCI IOB Veco 1 8V Rygp Zg 502 HSTL_IV_DCI_18 HSTL_IV_DCI_18 p n ug 90 6 61 030306 Vper 1 1V Figure 6 63 HSTL Class IV 1 8V with Bidirectional Termination Virtex 5 FPGA User Guide www xilinx com 269 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Table 6 26 lists the HSTL Class IV 1 8V DC voltage specifications Table 6 26 HSTL Class IV 1 8V DC Voltage Specifications Min Typ Max Vico 1 7 1 8 1 9 Vag 2 1 1 2 Vas Vcco E Vig Var 0 1 g V B Vee Vou Veco 0 4 Vor E 0 4 Tox at Voy mA 8
375. ration startup remains in the specified startup cycle until the DCM is locked 2 Before setting the LCK cycle option to a startup cycle in BitGen the DCM s STARTUP WAIT attribute must be set to TRUE 3 Ifthe startup sequence is altered by using the BitGen option do not place the LCK cycle wait for the DCM to lock before the GTS cycle deassert GTS Incorrect implementation results in the DCM not locking and an incomplete configuration Deskew Adjust The DESKEW ADJUST attribute sets the value for a configurable variable tap delay element to control the amount of delay added to the DCM feedback path see Figure 2 4 Virtex 5 FPGA User Guide www xilinx com 61 UG190 v4 4 December 2 2008 62 Chapter 2 Clock Management Technology XILINX Data Input Into the FPGA CLK Source IBUFG DCM Regulator 4x Feedback Tap Delays 2 System Synchronous Source Synchronous Default Setting Setting Delay set to zero Figure 2 4 DCM and Feedback Tap Delay Elements ug190 2 04 042506 This delay element allows adjustment of the effective clock delay between the clock source and CLKO to guarantee non positive hold times of IOB input flip flop in the device Adding more delay to the DCM feedback path decreases the effective delay of the actual clock path from the FPGA clock input pin to the clock input of any flip flop Decreasing the clock delay increases the setup time represe
376. re no collision can occur when used in synchronous mode Virtex 5 FPGA User Guide www xilinx com 115 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX WRITE FIRST or Transparent Mode Default In WRITE FIRST mode the input data is simultaneously written into memory and stored in the data output transparent write as shown in Figure 4 2 These waveforms correspond to latch mode when the optional output pipeline register is not used Disabled Read Write Write Read MEM bb 1111 MEM cc 2222 ug190_4 03 032206 Figure 4 2 WRITE FIRST Mode Waveforms READ_FIRST or Read Before Write Mode In READ_FIRST mode data previously stored at the write address appears on the output latches while the input data is being stored in memory read before write The waveforms in Figure 4 3 correspond to latch mode when the optional output pipeline register is not used CLK A OX FF SF x NE WE DI ADDR DO EN Disabled 1 Read 1 Write 1 Write 1 Read MEM bb 1111 MEM cc 2222 ug190_4 04 032206 Figure 4 3 READ FIRST Mode Waveforms NO CHANGE Mode In NO CHANGE mode the output latches remain unchanged during a write operation As shown in Figure 4 4 data output remains the last read data and is unaffected by a write operation on the same port These waveforms correspond to latch mode when the optional output pipeline register is not used 116 www xilinx com Virtex 5 FPGA User Guide UG1
377. recommended since the PLL can not compensate for the delay of the general route An IBUF clock input must route to a BUFG before routing to a PLL DCMOUT Any DCM output to PLL will compensate the delay of this path www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX General Usage Description Counter Control The PLL output counters provide a wide variety of synthesized clock using a combination of DIVIDE DUTY CYCLE and PHASE Figure 3 6 illustrates how the counter settings impact the counter output The top waveform represents either the output from the VCO in PLL mode Counter Clock Input DIVIDE 2 PHASE 0 DIVIDE 2 PHASE 180 DIVIDE 2 DUTY CYCLE 0 75 PHASE 180 DIVIDE 1 PHASE 0 DIVIDE 1 DUTY_CYCLE 0 5 PLE LI LE LILI LILI NATAN PHASE 360 DIVIDE 3 DUTY_CYCLE 0 33 PHASE 0 DIVIDE 3 DUTY CYCLE 0 5 PHASE 0 UG190 3 06 041406 Figure 3 6 Output Counter Clock Synthesis Examples Virtex 5 FPGA User Guide www xilinx com 99 UG190 v4 4 December 2 2008 Chapter 3 Phase Locked Loops PLLs XILINX Clock Shifting The PLL output clocks can be shifted by inserting delay by selecting one of the eight phases in either the reference or the feedback path The following figure shows the effect on a clock signal edge at the output of the PLL without any shifting versus the two cases delay inserted in the feedb
378. rectional DCI termination DCI IOB 10B Vcco 1 5V DIFF_HSTL_I_DCI i a gt 2Rypp 2Zg 1000 Bt E aa E 2Rypy 2Zg 1000 DIFF HSTL I DCI Vcco 1 5V DIFF_HSTL_I_DCI 2Rypp 2Zg 1002 AS 2Rypy 2Zg 1000 iul VVV ug190_6_40_030206 Figure 6 41 Differential HSTL 1 5V Class DCI Unidirectional Termination 250 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Table 6 16 lists the differential HSTL Class I DC voltage specifications Table 6 16 Differential HSTL Class DC Voltage Specifications Min Typ Max Vics 1 40 1 50 1 60 Vis E Vccox 05 P Vin DC 0 30 B Vorort Vom OO 0 20 Vori Vom DO 0 68 0 90 Varro 0 40 E Veco 0 60 Vx Crossover 0 68 0 90 Notes 1 Common mode voltage Vem Vp Vp Vn 2 2 Crossover point Vy where Vp Vy 0 AC coupled HSTL Class ll Figure 6 42 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 5V with unidirectional termination External Termination 108 Vr 0 75V Vat 0 75V 35g HSTL_II HSTL Il Rp Z 502 Rp Zg 509 n QA X l Veer 0 75V l L DCI IOB IOB 2Rypp 2Zg 1000 2Rypp 2Zo 1000 PISTE Del HSTL Il DCI DJ 0Q 2 D1 4 Vper 0 75V 2Rypy 2Zo 1002 i 2Rypy
379. requency The CLKIN DIVIDE BY 2 Attribute description provides further information When CLKFB is connected CLKO is phase aligned to CLKIN www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX DCM Ports 1x Output Clock 90 Phase Shift CLK90 The CLK90 output clock provides a clock with the same frequency as the DCM s CLKO phase shifted by 90 1x Output Clock 180 Phase Shift CLK180 The CLK180 output clock provides a clock with the same frequency as the DCM s CLKO phase shifted by 180 1x Output Clock 270 Phase Shift CLK270 The CLK270 output clock provides a clock with the same frequency as the DCM s CLKO phase shifted by 270 2x Output Clock CLK2X The CLK2X output clock provides a clock that is phase aligned to CLKO with twice the CLKO frequency and with an automatic 50 50 duty cycle correction Until the DCM is locked the CLK2X output appears as a 1x version of the input clock with a 25 75 duty cycle This behavior allows the DCM to lock on the correct edge with respect to the source clock 2x Output Clock 180 Phase Shift CLK2X180 The CLK2X180 output clock provides a clock with the same frequency as the DCM s CLK2X phase shifted by 180 Frequency Divide Output Clock CLKDV The CLKDV output clock provides a clock that is phase aligned to CLKO with a frequency that is a fraction of the effective CLKIN frequency The fraction is determined by the CLKDV DIVIDE attribu
380. right side of this device XC5VLX30T 8 XCS5VLX50T 12 XC5VLX85T 12 XC5VLX110T 16 XC5VLX155T 16 XC5VLX220T 16 XC5VLX330T 24 XC5VTX150T 20 XC5VTX240T 24 XC5VSX35T 8 XC5VSX50T 12 XC5VSX95T 16 XC5VSX240T 24 XC5VFX30T 8 XC5VFX70T 16 XC5VFX100T 16 XC5VFX130T 20 XCS5VFX200T 24 Virtex 5 FPGA User Guide www xilinx com 35 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX Regional Clocking Resources 36 Regional clock networks are a set of clock networks independent of the global clock network Unlike global clocks the span of a regional clock signal BUFR is limited to three clock regions while the I O clock signal drives a single region only These networks are especially useful for source synchronous interface designs The I O banks in Virtex 5 devices are the same size as a clock region To understand how regional clocking works it is important to understand the signal path of a regional clock signal The regional clocking resources and network in Virtex 5 devices consist of the following paths and components e Clock Capable I O e I O Clock Buffer BUFIO e Regional Clock Buffer BUFR e Regional Clock Nets Clock Capable I O In a typical clock region there are four clock capable I O pin pairs there are exceptions in the center column Clock capable I O pairs are regular I O pairs in select locations with special hardware connections to nearby regional clock resources Some global c
381. ring a sample of the output clock CLKO the deskew circuit compensates for the delay on the routing network effectively eliminating the delay from the external input port to the individual clock loads within the device Output pin connectivity carries some restrictions The DCM clock outputs must drive a global clock buffer BUFGCTRL The DCM clock outputs can not drive general routing To use dedicated routing the DCM clock outputs must drive BUFGCTRLs on the same top or bottom half of the device If the DCM and BUFGCTRL are not on the same top or bottom half local routing is used and the DCM might not deskew properly Do not use the DCM output clock signals until after activation of the LOCKED signal Prior to the activation of the LOCKED signal the DCM output clocks are not valid DCM During Configuration and Startup During the FPGA configuration the DCM is in reset and starts to lock at the beginning of the startup sequence A DCM requires both CLKIN and CLKFB input clocks to be present and stable when the DCM begins to lock If the device enters the configuration startup sequence without an input clock or with an unstable input clock then the DCM must be reset after configuration with a stable clock The following startup cycle dependencies are of note 1 The default value is g LCK cycle NoWait When this setting is used the startup sequence does not wait for the DCM to lock When the LCK cycle is set to other values the configu
382. rity data out bus DOP when available have a total width equal to the port width as shown in Table 4 6 and Table 4 7 In CASCADEINLAT AIB and CASCADEINREG AIB The CASCADEIN pins are used to connect two block RAMs to form the 64K x 1 mode Figure 4 10 This pin is used when the block RAM is the UPPER block RAM and is connected to the CASCADEOUT pins of the LOWER block RAM of the same port When cascade mode is not used this pin does not need to be connected Refer to the Cascadable Block RAM for further information Upper RAMB36 CASCADEINLATA B CASCADEINREGA B CASCADEOUTLATA B CASCADEOUTREGA B Lower RAMB36 ug190 4 12 040606 Figure 4 10 Two RAMB36s Cascaded Cascade Out CASCADEOUTLAT AIB and CASCADEOUTREG AIB The CASCADEOUT pins are used to connect two block RAMs to form the 64K x 1 mode This pin is used when the block RAM is the LOWER block RAM and is connected to the CASCADEIN pins of the UPPER block RAM of the same port When cascade mode is not used this pin does not need to be connected Refer to the Cascadable Block RAM for further information Inverting Control Pins For each port the six control pins CLK EN and SSR each have an individual inversion option EN and SSR control signals can be configured as active High or Low and the clock can be active on a rising or falling edge active High on rising edge by default without requiring other logic resources Virtex 5 FPGA User Guide w
383. rly at time T2R and T3R the memory content at address locations b and c are read and decoded at DO 63 0 and DOP 7 0 SBITERR DBITERR outputs can also switch after T1R if a single or double bit error is detected on dataset A Figure 4 32 shows a single bit error SBITERR being detected on data A in latch mode after clock edge T1R and a double bit error DBITERR being detected on data B in latch mode after clock edge T2R If attribute DO REG is set to 1 DO 63 0 A and DOP 7 0 PA shortly after T2R Similarly at time T3R and T4R the memory content at address locations b and c are read and decoded at DO 63 0 and DOP 7 0 SBITERR DBITERR outputs may also switch after T2R if a single or double bit error is detected on dataset A Figure 4 32 shows a single bit error SBITERR being detected on data A in register mode after clock edge T2R and a double bit error DBITERR being detected on data B in register mode after clock edge T3R In ECC mode the encode only port and the decode only port operate independently of each other ECC Encode Only Set by Attributes EN ECC READ FALSE EN ECC WRITE TRUE ECC Encode Only Write At time TIW DI 63 0 A is written into memory location a The corresponding 8 bits of ECC parity PA hex are generated internally appended to the 64 data bits and written into the memory Immediately after the write the parity value PA appears at output ECCPARITY 7 0 Since ECC parity is generated internall
384. rposes the data width is eight The Bitslip operation is synchronous to CLKDIV In SDR mode every Bitslip operation causes the output pattern to shift left by one In DDR mode every Bitslip operation causes the output pattern to alternate between a shift right by one and shift left by three In this example on the eighth Bitslip operation the output pattern reverts to the initial pattern This assumes that serial data is an eight bit repeating pattern Bitslip Operation in SDR Mode Bitslip Operation in DDR Mode Bitslip Output Bitslip Output Operations Pattern 8 1 Operations Pattern 8 1 Executed Executed 10010011 00100111 00100111 10010011 2 01001110 3 10011100 4 00111001 5 01110010 6 11100100 2 10012100 3 01002110 4 01210010 5 00111001 6 11001001 ug 90 8 10 100307 Figure 8 10 Bitslip Operation Examples www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Input Serial to Parallel Logic Resources ISERDES Figure 8 11 illustrates the ISERDES configured in 1 8 SDR mode with Bitslip ENABLE set to TRUE Two ISERDES modules are in a master slave configuration for a data width of eight IOB SERDES MODE MASTER 7 1st 2nd 3th 4th 5th 6th 7th 8th Bitslip BITSLIP_ENABLE TRUE Initial Bitslip Bitslip Bitslip Bitslip Bitslip Bitslip Bitslip Back to initial ALE RAE godi _ Q1 r 1 1 1 0 0 1 0
385. rtex5 Virtex 5 FPGA User Guide Virtex 5 Family Overview The features and product selection of the Virtex 5 family are outlined in this overview Virtex 5 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 5 family Virtex 5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIO GTP transceivers available in the Virtex 5 LXT and SXT platforms Virtex 5 FPGA RocketIO GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex 5 TXT and FXT platforms Virtex 5 FPGA Embedded Processor Block for PowerPC 440 Designs This reference guide is a description of the embedded processor block available in the Virtex 5 FXT platform Virtex 5 FPGA Tri Mode Ethernet Media Access Controller This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in the Virtex 5 LXT SXT TXT and FXT platforms Virtex 5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex 5 LXT SXT TXT and FXT platforms used for PCI Express designs XtremeDSP Design Considerations This guide describes the XtremeDSP slice and includes reference designs for using the DSP48E slice www xilinx com 19 UG190 v4 4 December 2 2008 Chapter e Virtex 5 FPGA Configuration Guide This all encompa
386. s for the SLEW attribute are e SLEW SLOW Default e SLEW FAST The SLEW attribute uses the following syntax in the UCF file INST lt I O_BUFFER_INSTANTIATION_NAME gt SLEW lt SLEW_VALUE gt By the default the slew rate for each output buffer is set to SLOW This is the default used to minimize the power bus transients when switching non critical signals 234 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA SelectlO Primitives Output Drive Strength Attributes For LVTTL and LVCMOS output buffers OBUF OBUFT and IOBUF the desired drive strength in mA can be specified with the DRIVE attribute The allowed values for the DRIVE attribute are e DRIVE 2 e DRIVE 4 e DRIVE 6 e DRIVE 8 e DRIVE 12 Default e DRIVE 16 e DRIVE 24 LVCMOS12 only supports the 2 4 6 8 mA DRIVE settings LVCMOSI15 and LVCMOS18 only support the 2 4 6 8 12 and 16 mA DRIVE settings The DRIVE attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME DRIVE lt DRIVE_VALUE gt PULLUP PULLDOWN KEEPER for IBUF OBUFT and IOBUF When using 3 state output OBUFT or bidirectional IOBUF buffers the output can have a weak pull up resistor a weak pull down resistor or a weak keeper circuit For input IBUF buffers the input can have either a weak pull up resistor or a weak pull down resistor This feature can b
387. s of the block RAM The block RAM register mode SSR requires REGCE 1 to reset the output DO register value The block RAM array data output latch does not get reset in this mode The block RAM latch mode SSR requires the block RAM enable EN 1 to reset the output DO latch value Although RAMB18SDP x36 18k block RAM and RAMB36SDP x72 36k block RAM are simple dual port primitives the true dual port primitives RAMB18 and RAMB36 can be used with one read only port and one write only port For example a RAMB18s READ WIDTH A 18 WRITE WIDTH B 9 with WEA 0 and WEB 1 is effectively a simple dual port block RAM with a smaller port width having been derived from the true dual port primitive Similarly a ROM function can be built out of either the true dual port RAMB18 or RAMB36 or the simple dual port block RAM primitives RAMB18SDP or RAMB36SDP Different read and write port width choices are available when using specific block RAM primitives The parity bits are only available for the x9 x18 and x36 port widths The parity bits should not be used when the read width is x1 x2 or x4 If the read width is x1 x2 or x4 the effective write width is x1 x2 x4 x8 x16 or x32 Similarly when a write width is x1 x2 or x4 the actual available read width is x1 x2 x4 x8 x16 or x32 even though the primitive attribute is set to 1 2 4 9 18 or 36 respectively Table 4 1 shows some possible scenarios Table 4 1 Parity Use
388. s the clock input pin CE Clock enable port The enable pin affects the loading of data into the DDR flip flop When Low clock transitions are ignored and new data is not loaded into the DDR flip flop CE must be High to load new data into the DDR flip flop D Data input DDR IDDR register input from IOB Virtex 5 FPGA User Guide www xilinx com 317 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX Table 7 3 DDR Port Signals Continued Port Function Description Name R Reset Synchronous Asynchronous reset pin Reset is asserted High S Set Synchronous Asynchronous set pin Set is asserted High Table 7 4 DDR Attributes Attribute Name Description Possible Values DDR CLK EDGE Sets the IDDR mode of operation with OPPOSITE EDGE default respect to clock edge SAME EDGE SAME EDGE PIPELINED INIT O1 Sets the initial value for Q1 port 0 default 1 INIT Q2 Sets the initial value for Q2 port 0 default 1 SRTYPE Set Reset type with respect to clock C ASYNC default SYNC IDDR VHDL and Verilog Templates The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL and Verilog ILOGIC Timing Models This section describes the timing associated with the various resources within the ILOGIC block ILOGIC Timing Characteristics Figure 7 6 illustrates ILOGIC register timing When IDELAY is used Typocy is replac
389. se conditions specified by the user Differential HSTL Class II 1 8V Figure 6 57 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with unidirectional termination External Termination Vyr 0 9V IOB DIFF HSTL Il 18 4 500 DIFF HSTL Il 18 bd Vr 0 9V 50Q x Vr 0 9V 500 IOB C 7o Vr 0 9V 50Q rj DIFF HSTL Il 18 C 7o bd ugi 90 6 55 030306 Figure 6 57 Differential HSTL 1 8V Class II Unidirectional Termination www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards Figure 6 58 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with unidirectional DCI termination DCI IOB 10B Veco 1 8V DIFF_HSTL_II_DCI_18 E 2Rypp 2Zg 1000 D1 0 2 Rygy 2Zg 1000 E 2Rypy 7229 1009 piEE nsTi pci 18 Veco 1 8V DIFF HSTL Il DCI 18 2Rypp 2Zg 1000 ug190 6 56 121506 Figure 6 58 Differential HSTL 1 8V Class Il DCI Unidirectional Termination Figure 6 59 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with bidirectional termination External Termination r oE IOB Vyr 0 9V Vr 0 9V DIFF_HSTL_II_18
390. se introduced on the CLKIN signal and the BUFG will still be present Figure 3 11 CLKIN1 CLKOUTO To Logic CLKFBIN CLKOUT1 RST CLKOUT2 CLKOUTS pl CLKOUT4 CLKOUTS CLKFBOUT UG190_3_11_040906 Figure 3 11 PLL with Internal Feedback Zero Delay Buffer The PLL can also be used to generate a zero delay buffer clock A zero delay buffer can be useful for applications where there is a single clock signal fan out to multiple destinations with a low skew between them This configuration is shown in the Figure 3 12 Here the feedback signal drives off chip and the board trace feedback is designed to match the trace to the external components In this configuration it is assumed that the clock edges are aligned at the input of the FPGA and the input of the external component There will be a limitation on the maximum delay allowed in the feedback path IBUFG BUFG OBUF Inside FPGA CLKINT CLKOUTO gt D gt To CLKOUT1 M External CLKFBIN Components CLKOUT2 ELE RST CLKOUT3 CLKOUT4 PLL CLKOUT5 BUFG CLKFBOUT gt I UG190 3 12 120108 Figure 3 12 Zero Delay Buffer Virtex 5 FPGA User Guide www xilinx com 103 UG190 v4 4 December 2 2008 Chapter 3 Phase Locked Loops PLLs XILINX In some cases precise alignment will not occur because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the FPGA
391. ser Guide UG190 v4 4 December 2 2008 XILINX CLB Overview CX A5 SHIFTIN D pt A 6 0 4 gt A 6 2 F7BMUX gx A6 CLK CLK We QWE CE N Output Q M Registered Optional AX A5 Not Used F7AMUX SHIFTOUT Q95 UG190 5 19 050506 Figure 5 19 96 bit Shift Register Configuration Virtex 5 FPGA User Guide www xilinx com 191 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX 192 5 A 6 0 A 6 2 CX A5 CLK WE F7BMUX T BX A6 Output Q Registered F8MUX Output Optional AX A5 F7AMUX MC31 SHIFTOUT Q127 UG190 5 20 050506 Figure 5 20 128 bit Shift Register Configuration It is possible to create shift registers longer than 128 bits across more than one SLICEM However there are no direct connections between slices to form these shift registers Shift Register Data Flow Shift Operation The shift operation is a single clock edge operation with an active High clock enable feature When enable is High the input D is loaded into the first bit of the shift register Each bit is also shifted to the next highest bit position In a cascadable shift register configuration the last b
392. sly BUFGCTRL to DCM Any BUFGCTRL can drive any DCM in the Virtex 5 devices However only up to ten dedicated clock routing resources exist in a particular clock region Since the clock routing is accessed via the BUFGCTRL outputs this indirectly limits the BUFGCTRL to DCM connection If ten BUFGCTRL outputs are already accessing a clock region and a DCM is in that region then no additional BUFGCTRL can be used in that region including a connection to the CLKFB pin of the DCM Virtex 5 FPGA User Guide www xilinx com 69 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX PLL To and From DCM Figure 2 7 summarizes the dedicated connection between the DCM and the PLL in the same CMT block The PLL can drive either DCM in the same CMT block using a dedicated connection Similarly the DCM can drive the PLL within the same CMT block with a dedicated connection There is no BUFGCTRL required between the PLL and the DCM From any IBUFG implementation From any BUFG implementation To Global E Routing BUFG PLL to DOM Input DOM to PLL Input J To Global Routing BUFG li DCM to PLL Input D PLL to DCM Input To Global Routing BUFG ug190_2_07_072307 Figure 2 7 DCM and PLL Connection in Same CMT Block DCM To and From PMCD The PMCD block is not available in the Virtex 5 devices However a limited retargeting using the PLL is possible Refer to PLL in Virtex 4
393. sources XILINX Table 6 9 LVCMOS LVDCI and LVDCI DV2 DC Voltage Specifications at Various Voltage References 3 3V 2 5V 1 8V 1 5V 1 2V 2 Standard Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Vcco V 30 33 345 23 25 27 17 18 1 9 14 15 1 6 11 12 13 Vin IV 20 3 45 1 7 Veco 0 3 1 105 Veco 03 0 91 Veco 0 3 0 715 Vecot0 3 Vi V 0 2 08 03 07 03 0 665 03 0 56 03 0 455 Vou V 26 19 125 105 0 825 z Vor V 7 0 4 0 4 0 45 0 4 0 325 Im nA 5 5 5 10 10 Notes 1 Vor and Vox for lower drive currents are sample tested 2 Only LVCMOS is supported at 1 2V with valid DRIVE attributes of 2 4 6 8 242 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards HSLVDCI High Speed Low Voltage Digitally Controlled Impedance The HSLVDCI standard is intended for bidirectional use The driver is identical to LVDCI while the input is identical to HSTL and SSTL By using a Vpgr referenced input HSLVDCI allows greater input sensitivity at the receiver than when using a single ended LVCMOS type receiver A sample circuit illustrating bidirectional termination techniques for an HSLVDCI controlled impedance driver is shown in Figure 6 34 The DCI I O s
394. ssing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces e Virtex 5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex 5 devices is outlined in this guide XILINX e Virtex 5 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications e Virtex 5 FPGA PCB Designer s Guide This guide provides information on PCB design for Virtex 5 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support Typographical Conventions This document uses the following typographical conventions An example illustrates each 20 convention Convention Meaning or Use Example References to other documents Bee the VS CORR 8 uud Guide for more information Italic font i The address F is asserted after Emphasis in text clock event 2 Underlined Text Indicates a link to a web page http www xilinx com v
395. sssssssss ee 71 Standard Usage scx eee tte Fee le ke Pee ERE ach e Race E Rt ec 71 Board Level Clock Generation sssseeee cece eee eee 71 Board Deskew with Internal Deskew sssse ee 73 Clock Switching Between Two DCMS 2 cece nee 76 DEM WHR PEL a ease le enn Eh nh i CR RAS ANE ps che Rea d qe Mak qed A gend A dedos 77 VHDL and Verilog Templates and the Clocking Wizard 79 DCM Taming Models xu iip y ERA tibia tei er epee eee ei ee ees 80 R set LOCK 2 REEL ceed eta ieee Se ee we de Se RR in a 80 Fixed Phase Shitting eres oy oherreee teed elude eve regere bees Es 81 pent Ve 25d ed ate fet cao 01 a 21 ag ire estos Ra Re rR Wen eee ee e 82 Status FACS s ors ee edatene be Wa ss ee Vad Ue Ra alae aly ae Be aes 83 Legacy SUP PON oe Ea xd keri QR der YU oed qa hatc Bebes dale e nese mee dite ee 84 Chapter 3 Phase Locked Loops PLLs Introduction 2 erede ecce PUR atte pate dte et ber tfe e eA e dan 85 Phase Lock Loop PLL sette Re eme Rer RII ER Rp UR ER eiaa 86 General Usage Descepll fi erue p Er rpEEP RTI ER ESEERERER nde E ames 89 PEL PRIA VS ee b eee e e e HE tee de eov e eee ae bore dee 89 PLE BASE PHMIUVE 325m ep eed deg cede Pte dec dee doa ete ode er dra tete eR s 89 PLL ADV Primitive occ ouk ede hee d ace Kex hee eee rna 90 Clock Network Deskew eee RR nent n ene 90 Frequency Synthesis Only sssssseeseesseese e 90 ludus a ee aei ae ne e a e ae
396. stimates for locking times To guarantee an established system clock at the end of the start up cycle the DCM can delay the completion of the device configuration process until after the DCM is locked The STARTUP WAIT attribute activates this feature The STARTUP WAIT Attribute description provides further information Until the LOCKED signal is asserted High the DCM output clocks are not valid and can exhibit glitches spikes or other spurious movement In particular the CLK2X output appears as a 1x clock with a 25 75 duty cycle Phase Shift Done Output PSDONE The phase shift done PSDONE output signal is synchronous to PSCLK At the completion of the requested phase shift PSDONE pulses High for one period of PSCLK This signal also indicates a new change to the phase shift can be initiated The PSDONE output signal is not valid if the phase shift feature is not being used or is in fixed mode Status or Dynamic Reconfiguration Data Output DO 15 0 The DO output bus provides DCM status or data output when using dynamic reconfiguration Table 2 4 Further information on using DO as the data output is available in the Dynamic Reconfiguration chapter of the Virtex 5 FPGA Configuration Guide for more information If the dynamic reconfiguration port is not used using DCM BASE instead of DCM_ADV is strongly recommended Table 2 4 DCM Status Mapping to DO Bus DO Bit Status Description DO 0 Phase shift overflow Asserted whe
397. t 3 state input control port This port determines dynamically pu if IODELAY is used as IDELAY or ODELAY CE Input Enable increment decrement function INC Input Increment decrement number of tap delays RST Input Reset the IODELAY element to the pre programmed value C Input Clock input used in variable mode IODELAY Ports Data Input from the IOB IDATAIN The IDATAIN input is driven by its associated IOB In IDELAY mode the data can be driven to either an ILOGIC ISERDES block directly into the FPGA fabric or to both through the DATAOUT port with a delay set by the IDELAY VALUE Data Input from the FPGA Fabric ODATAIN The ODATAIN input is driven by OLOGIC OSERDES In ODELAY mode the ODATAIN drives the DATAOUT port which is connected to an IOB with a delay set by the ODELAY VALUE Data Input for IODELAY from the FPGA Fabric DATAIN The DATAIN input is directly driven by the FPGA fabric providing a fabric logic accessible delay line The data is driven back into the fabric through the DATAOUT port with a delay set by theIDELAY VALUE DATAIN can be locally inverted The data cannot be driven to an IOB Data Output DATAOUT Delayed data from the three data input ports DATAOUT connects to the fabric IDELAY mode or an IOB ODELAY mode or both bidirectional delay mode If used in the bidirectional delay mode the T port dynamically switches between the IDATAIN and ODATAIN paths providing an alternating input out
398. t O begins toggling at the divide by three rate of the input I Tggcko o and other timing numbers are best found in the speed specification Note The duty cycle is not 50 50 for odd division The Low pulse is one cycle of I longer e At time event 2 CLR is asserted After Tggpo cr go from time event 2 O stops toggling e At time event 3 CLR is deasserted e At time TgrcKxo o after clock event 4 O begins toggling again at the divided by three rate of I www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Regional Clocking Resources BUFR Use Models BUFRs are ideal for source synchronous applications requiring clock domain crossing or serial to parallel conversion Unlike BUFIOs BUFRs are capable of clocking logic resources in the FPGAs other than the IOBs Figure 1 22 is a BUFR design example To Region Above UJ O I O Tile 4 QO jes O I O Tile 4 I O Tile 4 I O Tile 4 Oo Ww a O Tile 4 I O Tile 4 O 2 UJ o d o I O Tile 4 E ue 2 p To Center Clock Capable I O W a lie lie UJ UJ UJ o o o of Die To Region Below ugi90 1 22 072806 Figure 1 22 BUFR Driving Various Logic Resources Virtex 5 FPGA User Guide www xilinx com 41 UG190 v4 4 December 2 2008 Chapter 1 Clock Resources XILINX Regional Clock Nets In addition to global clock trees and nets Virtex 5 devices contain regional clock nets These clock trees
399. t clear the memory nor does it clear the output register When reset is asserted High EMPTY and ALMOST_EMPTY will be set to 1 FULL and ALMOST_FULL will be reset to 0 The reset signal must be High for at least three read clock and write clock cycles to ensure all internal states are reset to the correct values During RESET RDEN and WREN must be held Low Operating Mode There are two operating modes in FIFO functions They differ only in output behavior immediately after the first word is written to a previously empty FIFO Standard Mode After the first word is written into an empty FIFO the Empty flag deasserts synchronously with RDCLK After Empty is deasserted Low and RDEN is asserted the first word will appear at DO on the rising edge of RDCLK First Word Fall Through FWFT Mode After the first word is written into an empty FIFO this word automatically appears at DO before RDEN is asserted Subsequent Read operations require Empty to be Low and RDEN to be High Figure 4 20 illustrates the difference between standard mode and FWFT mode Virtex 5 FPGA User Guide www xilinx com 143 UG190 v4 4 December 2 2008 Chapter 4 Block RAM RDCLK RDEN EMPTY DO Standard DO FWFT Previous Data AEN w1 4 we XILINX w Xw ug190_4_17_032506 Figure 4 20 Read Cycle Timing Standard and FWFT Modes Status Flags Table 4 16 shows the number of clock cycles to assert or deassert each flag of a multira
400. t errors Write the word into the block RAM Reading the 72 bit word automatically corrects the single bit error and asserts the SBITERR error flag or it detects the double bit error and asserts the DBITERR error flag Creating Eight Parity Bits for a 64 bit Word Using logic external to the block RAM a large number of XOR circuits eight parity bits Virtex 5 FPGA User Guide can be created for a 64 bit word However using ECC encoder only mode the eight parity bits can be automatically created without additional logic by writing any 64 bit word into a separate block RAM The encoded 8 bit ECC parity data is immediately available or the complete 72 bit word can be read out Inserting a Single or Double Bit Error into a 72 bit Word By reading a 72 bit word and selectively modifying one or two bits then writing all 72 bits into the block RAM under test in ECC decode only mode a single or double bit error can be inserted Block RAM ECC VHDL and Verilog Templates VHDL and Verilog templates are available in the Libraries Guide www xilinx com 169 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Legal Block RAM and FIFO Combinations The block RAM FIFO combinations shown in Figure 4 33 are supported in a single RAMB36 primitive When placing block RAM and FIFO primitives in the same location the FIFO must occupy the lower port RAMB18 RAMB18SDP RAMB18 RAMB18SDP RAMB18 RAMB18SDP FIFO18 FIFO18 36 ug0190 4
401. t go High until the first phase of the impedance adjustment process is complete The coarse impedance calibration during the first phase of impedance adjustment can be invoked after configuration by instantiating the DCIRESET primitive By toggling the RST input to the DCIRESET primitive while the device is operating the DCI state machine is Virtex 5 FPGA User Guide www xilinx com 221 UG190 v4 4 December 2 2008 222 Chapter 6 SelectlO Resources XILINX reset and both phases of impedance adjustment proceed in succession All I Os using DCI will be unavailable until the LOCKED output from the DCIRESET block is asserted This functionality is useful in applications where the temperature and or supply voltage changes significantly from device power up to the nominal operating condition Once at the nominal operating temperature and voltage performing the first phase of impedance adjustment allows optimal headroom for the second phase of impedance adjustment For controlled impedance output drivers the impedance can be adjusted either to match the reference resistors or half the resistance of the reference resistors For on chip termination the termination is always adjusted to match the reference resistors DCI can configure output drivers to be the following types 1 Controlled Impedance Driver Source Termination 2 Controlled Impedance Driver with Half Impedance Source Termination It can also configure inputs to have the
402. table at the RDCOUNT outputs of the FIFO TRCO_WRCOUNT Reset to write pointer WRCOUNT Time after reset that the Write pointer signal is output stable at the WRCOUNT outputs of the FIFO Notes 1 TRCKO_DO includes parity output TrcKo_Dop 2 In the Virtex 5 FPGA Data Sheet TRCKO_AEMPTY TRCKO_AFULL TRCKO_EMPTY FRCKO_FULL TRCKO_RDERR TRCKO_WRERR ate combined into TRCKO_FLAGS 3 In the Virtex 5 FPGA Data Sheet TRCKO_RDCOUNT and TRCKO_WRCOUNT are combined into TRCKO_POINTERS 4 TRCDCK_DI includes parity inputs Tncpck prp 5 In the Virtex 5 FPGA Data Sheet WRITE and READ enables are combined into TpccK EN FIFO Timing Characteristics The various timing parameters in the FIFO are described in this section There is also additional data on FIFO functionality The timing diagrams describe the behavior in these Six cases e Case 1 Writing to an Empty FIFO e Case 2 Writing to a Full or Almost Full FIFO e Case 3 Reading From a Full FIFO e Case 4 Reading From An Empty or Almost Empty FIFO e Case 5 Resetting All Flags e Case 6 Simultaneous Read and Write for Multirate FIFO Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com 149 Chapter 4 Block RAM XILINX Case 1 Writing to an Empty FIFO Prior to the operations performed in Figure 4 21 the FIFO is completely empty 1 2 3 4 WRCLK l l l l l l l
403. tandards supporting a controlled impedance driver with a Vpgg referenced input are HSLVDCI 15 HSLVDCI 18 HSLVDCI 25 and HSLVDCI 33 IOB IOB HSLVDCI HSLVDCI D1 Q 2 b4 Vngr Vcco 2 Ro Ryan Rypp Zo Ro Aven Pygp Zo ug190_6_33_022806 Figure 6 34 HSLVDCI Controlled Impedance Driver with Bidirectional Termination For output DC voltage specifications refer to the LVDCI Voz and Voy entries in Table 6 9 LVCMOS LVDCI and LVDCI_DV2 DC Voltage Specifications at Various Voltage References Table 6 10 lists the input DC voltage specifications when using HSLVDCI Valid values of Veco are 1 5V 1 8V 2 5V and 3 3V Select Vggg to provide the optimum noise margin in specific use conditions Table 6 10 HSLVDCI Input DC Voltage Specifications Standard Min Typ Max VREF Veco 2 m Vig VREF 0 1 E Vir Vnzgr 0 1 Virtex 5 FPGA User Guide www xilinx com 243 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources 244 XILINX PCI X PCI 33 PCI 66 Peripheral Component Interconnect The PCI standard specifies support for 33 MHz and 66 MHz bus applications The PCI X standard specifies support for 66 MHz and 133 MHz bus applications These standards use an LVTTL input buffer and a push pull output buffer These standards do not require the use of a reference voltage Vpgp or a board termination voltage V7 However
404. te The DESKEW_ADJUST attribute affects the amount of delay in the feedback path The possible values are SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS 0 1 2 3 or 31 The default value is SYSTEM SYNCHRONOUS For most designs the default value is appropriate In a source synchronous design set this attribute to SOURCE SYNCHRONOUS The remaining values should only be used after consulting with Xilinx For more information consult the Source Synchronous Setting section DFS FREQUENCY MODE Attribute The DF5 FREQUENCY MODE attribute specifies the frequency mode of the digital frequency synthesizer DFS The possible values are Low and High The default value is Low The frequency ranges for both frequency modes are specified in the Virtex 5 FPGA Data Sheet DF5 FREQUENCY MODE determines the frequency range of CLKIN CLKFX and CLKFX180 DLL FREQUENCY MODE Attribute The DLL FREQUENCY MODE attribute specifies either the High or Low frequency mode of the delay locked loop DLL The default value is Low The frequency ranges for both frequency modes are specified in the Virtex 5 FPGA Data Sheet DUTY CYCLE CORRECTION Attribute The DUTY CYCLE CORRECTION attribute controls the duty cycle correction of the 1x clock outputs CLK0 CLK90 CLK180 and CLK270 The possible values are TRUE and FALSE The default value is TRUE When set to TRUE the 1x clock outputs are duty cycle corrected to be within specified limits See the Virtex 5 FPGA D
405. te FIFO Synchronous FIFOs do not have a clock cycle latency when asserting or deasserting flags Due to the asynchronous nature of the clocks the simulation model only reflects the deassertion latency cycles listed Table 4 16 Multirate FIFO Flag Assertion and Deassertion Latency Status Flag EMPTYO Clock Cycle Latency Assertion Deassertion Standard FWFT Standard FWFT FULLO ALMOST EMPTYO ALMOST FULL READ ERROR WRITE ERROR coc m Fe o o cO coc m mc o CO oO WwW WI wo Q CO oO WwW WwW wo A Notes 1 Latency is with respect to RDCLK and WRCLK 2 Depending on the offset between read and write clock edges the Empty and Full flags can deassert one cycle later 3 Depending on the offset between read and write clock edges the Almost Empty and Almost Full flags can deassert one cycle later Empty Flag The Empty flag is synchronous with RDCLK and is asserted when the last entry in the FIFO is read When there are no more valid entries in the FIFO queue the read pointer will be frozen The Empty flag is deasserted after three in standard mode or four in FWFT mode read clocks after new data is written into the FIFO The empty flag is used in the read clock domain The rising edge of EMPTY is inherently synchronous with RDCLK The empty condition can only be terminated by WRCLK usually asynchronous to RDCLK The falling edg
406. te Refer to the CLKDV DIVIDE Attribute for more information Frequency Synthesis Output Clock CLKFX The CLKFX output clock provides a clock with the following frequency definition CLKFX frequency M D x effective CLKIN frequency In this equation M is the multiplier numerator with a value defined by the CLKFX MULTIPLY attribute D is the divisor denominator with a value defined by the CLKFX DIVIDE attribute Specifications for M and D as well as input and output frequency ranges for the frequency synthesizer are provided in the Virtex 5 FPGA Data Sheet The rising edge of CLKFX output is phase aligned to the rising edges of CLKO CLK2X and CLKDV When M and D to have no common factor the alignment occurs only once every D cycles of CLKO Frequency Synthesis Output Clock 180 CLKFX180 The CLKFX180 output clock provides a clock with the same frequency as the DCM s CLKFX phase shifted by 180 Virtex 5 FPGA User Guide www xilinx com 51 UG190 v4 4 December 2 2008 52 Chapter 2 Clock Management Technology XILINX DCM Status and Data Output Ports Locked Output LOCKED The LOCKED output indicates whether the DCM clock outputs are valid i e the outputs exhibit the proper frequency and phase After a reset the DCM samples several thousand clock cycles to achieve lock After the DCM achieves lock the LOCKED signal is asserted High The DCM timing parameters section of the Virtex 5 FPGA Data Sheet provides e
407. ted In the Virtex 5 architecture the FIFO can be configured as a 18 Kb or 36 Kb memory For the 18 Kb mode the supported configurations are 4K x 4 2K x 9 1K x 18 and 512 x 36 The supported configurations for the 36 Kb FIFO are 8K x 4 4K x 9 2K x 18 1K x 36 and 512 x 72 The block RAM can be configured as first in first out FIFO memory with common or independent read and write clocks Port A of the block RAM is used as a FIFO read port and Port B is a FIFO write port Data is read from the FIFO on the rising edge of read clock and written to the FIFO on the rising edge of write clock Independent read and write port width selection is not supported in FIFO mode without the aid of external CLB logic Multirate FIFO 138 The multirate FIFO offers a very simple user interface The design relies on free running write and read clocks of identical or different frequencies up to the specified maximum frequency limit The design avoids any ambiguity glitch or metastable problems even when the two frequencies are completely unrelated The write operation is synchronous writing the data word available at DI into the FIFO whenever WREN is active a set up time before the rising WRCLK edge Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 www xilinx com XILINX Built in FIFO Support The read operation is also synchronous presenting the next data word at DO whenever the RDEN is active one set up time before the risi
408. ted to 64 Virtex 5 FPGA User Guide www xilinx com 65 UG190 v4 4 December 2 2008 Chapter 2 Clock Management Technology XILINX e If PERIODCLKIN FINE SHIFT RANGE then the PHASE SHIFT in variable positive mode is limited to 255 In fixed and variable center mode the PHASE SHIFT is limited to 255 e If PERIODCLKIN XFINE SHIFT RANGE then the PHASE SHIFT in variable positive mode is limited to 255 In fixed and variable center mode the PHASE SHIFT is limited to 255 e For all previously described cases the direct mode is always limited to 1023 If the phase shift is limited by the FINE SHIFT RANGE use the coarse grained phase shift to extend the phase shift range or set DCM PERFORMANCE MODE attribute to MAX RANGE to increase the FINE SHIFT RANGE Figure 2 5 illustrates using CLK90 CLK180 and CLK270 outputs assuming FINE SHIFT RANGE 10 ns 10 ns 10 ns 10 ns 10 ns For frequency 2 100 MHz period lt 10 ns la a ra la PR CLKO PHASE SHIFT 0 255 covers the whole range of period CLKO 100 MHz hdc For frequency between 50 100 MHz period 10 20 ns At 50 MHz use CLKO PHASE SHIFT 0 127 for the first 10 ns CLKO 50 MHz Use CLK180 with PHASE SHIFT 0 127 for the next 10 ns CLK180 50 MHz mm For frequency between 25 50 MHz period 20 40 ns At 25 MHz use CLKO PHASE SHIFT 0 63 for the first 10 ns CLKO 25 mHz Use CLK90 with PHASE SHIFT 0 63 for t
409. ter Clock Enable CE The clock enable pin affects shift functionality An inactive clock enable pin does not shift data into the shift register and does not write new data Activating the clock enable allows the data in D to be written to the first location and all data to be shifted by one location When available new data appears on output pins Q and the cascadable output pin O31 Address A 4 0 The address input selects the bit range 0 to 31 to be read The nth bit is available on the output pin Q Address inputs have no effect on the cascadable output pin Q31 It is always the last bit of the shift register bit 31 Virtex 5 FPGA User Guide www xilinx com 211 UG190 v4 4 December 2 2008 212 Chapter 5 Configurable Logic Blocks CLBs XILINX Data Out Q The data output Q provides the data value 1 bit selected by the address inputs Data Out Q31 optional The data output Q31 provides the last bit value of the 32 bit shift register New data becomes available after each shift in operation Inverting Clock Pins The clock pin CLK has an individual inversion option The clock signal can be active at the negative or positive edge of the clock without requiring other logic resources The default is positive clock edge Global Set Reset GSR The global set reset GSR signal does not affect the shift registers Other Shift Register Applications Synchronous Shift Registers The shift re
410. ter 6 SelectlO Resources XILINX Figure 6 5 shows DCI cascading support over multiple banks Bank B is the master bank To Banks Above When Cascaded To Local Bank Bank A To Local Bank DCI HM VRN VRP Bank B To Local Bank Bank C To Banks Below When Cascaded UG190 6 96 012907 Figure 6 5 DCI Cascading Supported Over Multiple Banks The guidelines when using DCI cascading are as follows e The master and slave banks must all reside on the same column left center or right on the device e Master and slave banks must have the same Vcco and Vggg if applicable voltage e DCII O banking compatibility rules must be satisfied across all master and slave banks for example only one DCI I O standard using single termination type is allowed across all master and slave banks DCI I O standard compatibility is not constrained to one bank when DCI cascading is implemented it extends across all master and slave banks 220 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX SelectlO Resources General Guidelines e DCI cascading must extend across consecutive banks in the same column It is not possible to skip banks when using DCI cascading For example consider four banks in a column A B C and D from top to bottom In this case the following are valid possibilities for DCI cascading assuming all other guidelines are met DCI cascading can exte
411. th one half of the impedance of the reference resistors This doubling of the reference resistor value reduces the static power consumption through these resistors by a factor of half The DCI I O standards supporting controlled impedance drivers with half impedance are LVDCI DV2 15 LVDCI DV2 18 and LVDCI DV2 25 Figure 6 7 illustrates a controlled driver with half impedance inside a Virtex 5 device The reference resistors R must be 2 x Zo in order to match the impedance of Zp IOB m2 gt pus Zo Virtex 5 DCI UG190_6_05_021206 Figure 6 7 Controlled Impedance Driver with Half Impedance Input Termination to Veco Single Termination Some I O standards require an input termination to Vcco see Figure 6 8 Vcco IOB R oy 7o VREF Virtex 5 UG190 6 06 021306 Figure 6 8 Input Termination to Vcco without DCI DCI can also provide input termination to Vcco using single termination The termination resistance is set by the reference resistors Both GTL and HSTL standards are controlled by 50 O reference resistors The DCI I O standards supporting single termination are GTL DCI GTLP DCI HSTL III DCI HSTL III DCI 18 HSTL IV DCI and HSTL IV DCI 18 Virtex 5 FPGA User Guide www xilinx com 223 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 9 illustrates DCI single termination inside a Virtex 5 device l IOB i Veco R go T gt Z l 0
412. the FIFO18 or FIFO36 location FIFO36 EN SYN Boolean FALSE FALSE When set to TRUE ties WRCLK and TRUE RDCLK together When set to TRUE FWFT must be FALSE When set to FALSE DO REG must be 1 Notes 1 If FIFO18 is constrained to FIFO18_X Y then RAMBIS can not be constrained to RAMB18_X Y since the same location would be used 2 If a FIFO18 is constrained to FIFO18_X Y corresponding to the lower RAMB18_X Y of the RAMBIS pair a RAMBIS can be constrained to the upper RAMB18_X Y of the pair FIFO Almost Full Empty Flag Offset Range The offset ranges for Almost Empty and Almost Full are listed in Table 4 19 146 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA User Guide FIFO Attributes Table 4 18 FIFO Data Depth Data Width Block RAM FIFO Capacity FIFO18 FIFO36 Memory Standard FWFT x4 8192 8193 8194 x4 x9 4096 4097 4098 x9 x18 2048 2049 2050 x18 x36 1024 1025 1026 x36 x72 512 513 514 Notes 1 ALMOST EMPTY OFFSET and ALMOST FULL OFFSET for any design must be less than the total FIFO depth Table 4 19 FIFO Almost Full Empty Flag Offset Range ALMOST EMPTY OFFSET Data Width ALMOST FULL OFFSET Standard FWFT FIFO18 FIFO36 Min Max Min Max Min Max Multirate Asynchronous EN_SYN FALSE x4 5 8187 6 8188 4 8187 x4 x9 5 4091 6 4092 4 4091 x9 x18 5 2043 6 2044 4 2043
413. the PLL When an important aspect of the design is to maintain a certain phase relationship amongst various clock outputs e g CLK and CLK90 then this relationship will be maintained regardless of the input frequency 100 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Reference Clock Switching ee CLAU Counter acu us One Cycle Delay ug190 O3 08 032506 Figure 3 8 Selecting VCO Phases All O counters are equivalent anything O0 can do O1 can do The PLL outputs are flexible when connecting to the global clock network since they are identical In most cases this level of detail is imperceptible to the designer as the software and PLL Wizard determines the proper settings through the PLL attributes and Wizard inputs Reference Clock Switching The PLL reference clock can be dynamically switched by using the CLKINSEL pin The switching is done asynchronously Since the clock signal can generate a narrow pulse resulting in erroneous behavior of the PLL the PLL should be held in RESET while selecting the alternate clock with the CLKINSEL CLKSRC signal The PLL clock mux switching is shown in Figure 3 9 The CLKINSEL CLKSRC signal directly controls the mux No synchronization logic is present CLKSRC BUFG IBUFG DCM CLKIN1 PLL BUFG CLKIN IBUFG DCM CLKIN2 ug190_3 09 050906 Figure 8 9 Input Clock Switching Virtex 5 FPGA User Guide www xilinx com
414. the Virtex 5 FPGA Data Sheet Virtex 5 FPGA User Guide www xilinx com 63 UG190 v4 4 December 2 2008 64 Chapter 2 Clock Management Technology XILINX Only when feedback is provided to the CLKFB input of the DCM is the frequency synthesizer output phase aligned to the clock output CLKO The internal operation of the frequency synthesizer is complex and beyond the scope of this document As long as the frequency synthesizer is within the range specified in the Virtex 5 FPGA Data Sheet it multiplies the incoming frequencies by the pre calculated quotient M D and generates the correct output frequencies For example assume an input frequency of 50 MHz M 25 and D 8 M and D values do not have common factors and cannot be reduced The output frequency is 156 25 MHz although separate calculations 25 x 50 MHz 1 25 GHz and 50 MHz 8 625 MHz seem to produce separate values outside the range of the input frequency Frequency Synthesizer Characteristics e The frequency synthesizer provides an output frequency equal to the input frequency multiplied by M and divided by D e The outputs CLKFX and CLKFX180 always have a 50 50 duty cycle e Smaller M and D values achieve faster lock times Whenever possible divide M and D by the largest common factor to get the smallest values e g if the required CLKFX 9 6 x CLKIN instead of using M 9 and D 6 use M 3 and D 2 e When CLKFB is connected CLKFX is phase alig
415. the block RAM e At time TrcKo po after clock event 4 the SRVAL 0101 becomes valid at the DO outputs of the block RAM Clock Event 5 Disable Operation Deasserting the enable signal EN disables any write read or SSR operation The disable operation does NOT change the contents of the memory or the values of the output latches e At time Tgcck EN before clock event 5 the enable signal becomes invalid Low at the EN input of the block RAM e After clock event 5 the data on the DO outputs of the block RAM is unchanged 136 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Block RAM Timing Model Block RAM Timing Model Figure 4 15 illustrates the delay paths associated with the implementation of block RAM This example takes the simplest paths on and off chip these paths can vary greatly depending on the design This timing model demonstrates how and where the block RAM timing parameters are used e NET Varying interconnect delays e Tyopr Pad to I output of IOB delay e Tyoop O input of IOB to pad delay e Tsccko o BUFGCTRL delay FPGA Data Tiopi NET TRpCK pi Address mm LL ioer NET TRcck ADDR Write Enable gt ior NET TRCCK WEN Block RAM Enable TOPI NET Trock_eEN Synchronous TOPI NET Trock_ssr TRcko po NET Tioop lt I Data ug190_4_ 14 022207 Figure 4 15 Block RAM Timing Model Set Reset
416. the clock Additional attributes automatically selected by the ISE software INTERNAL EXTERNAL DCM2PLL PLL2DCM BANDWIDTH String HIGH LOW OPTIMIZED OPTIMIZED Specifies the PLL programming algorithm affecting the jitter phase margin and other characteristics of the PLL CLKOUTT 0 5 DIVIDE Integer 1 to 128 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired This number in combination with the CLKFBOUT MULT and DIVCLK_DIVIDE values will determine the output frequency CLKOUTT 0 5 PHASE Real 360 0 to 360 0 0 0 Allows specification of the output phase relationship of the associated CLKOUT clock output in number of degrees offset i e 90 indicates a 90 or cycle offset phase offset while 180 indicates a 180 offset or 4 cycle phase offset CLKOUT 0 5 DUTY CYCLE Real 0 01 to 0 99 0 50 Specifies the Duty Cycle of the associated CLKOUT clock output in percentage i e 0 50 will generate a 50 duty cycle CLKFBOUT MULT Integer 1 to 64 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired This number in combination with the associated CLKOUT _DIVIDE value and DIVCLK DIVIDE value will determine the output frequency DIVCLK DIVIDE Integer 1 to 52 Specifies the division ratio for all output clocks with respect to the input clock Virtex 5 F
417. the output register and is reflected at the OQ output at time Tocxg after Clock Event 1 Clock Event 4 At time Tosrcx before Clock Event 4 the SR signal configured as synchronous reset in this case becomes valid high resetting the output register and reflected at the OQ output at time Trg after Clock Event 4 Figure 7 27 illustrates the OLOGIC ODDR register timing I I _ Topck k ToocEck OCE Pd TosRcK ug 90 7 22 012407 Figure 7 27 OLOGIC ODDR Register Timing Characteristics Clock Event 1 At time Toocgck before Clock Event 1 the ODDR clock enable signal becomes valid High at the OCE input of the ODDR enabling ODDR for incoming data Care must be taken to toggle the OCE signal of the ODDR register between the rising edges and falling edges of CLK as well as meeting the register setup time relative to both clock edges At time Topcx before Clock Event 1 rising edge of CLK the data signal D1 becomes valid high at the D1 input of ODDR register and is reflected on the OQ output at time Tocko after Clock Event 1 Clock Event 2 Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 At time Topcx before Clock Event 2 falling edge of CLK the data signal D2 becomes valid high at the D2 input of ODDR register and is reflected on the OQ output at time Tocxko after Clock Event 2 no change at the OQ output in this case www xilinx com 345 Chapter 7 Sele
418. ther High or Low Clock selection using CE0 and CE1 only S0 and S1 tied High can change the clock selection without waiting for a High to Low transition on the previously selected clock www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Global Clocking Resources Table 1 4 summarizes the attributes for the BUFGCTRL primitive Table 1 4 BUFGCTRL Attributes Attribute Name Description Possible Values INIT_OUT Initializes the BUFGCTRL output to the specified 0 default 1 value after configuration Sets the positive or negative edge behavior Sets the output level when changing clock selection PRESELECT IO If TRUE BUFGCTRL output will use the I0 input FALSE default after configuration TRUE PRESELECT I1 If TRUE BUFGCTRL output will use the I1 input FALSE default after configuration TRUE Notes 1 Both PRESELECT attributes cannot be TRUE at the same time 2 The LOC constraint is available BUFG BUFG is simply a clock buffer with one clock input and one clock output This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 3 illustrates the relationship of BUFG and BUFGCTRL A LOC constraint is available for BUFG va IGNORE DD anp CE GND S BUFG SO CEO IGNOREO ugi 90 1 03 032206 Figure 1 3 BUFG as BUFGCTRL The output follows the input as shown in the timing diagram in Figure 1 4 eure AX
419. tiplexers using one LUT e 8 1 multiplexers using two LUTs e 16 1 multiplexers using four LUTs These wide input multiplexers are implemented in one level or logic or LUT using the dedicated F7AMUX F7BMUX and F8MUX multiplexers These multiplexers allow LUT combinations of up to four LUTs in a slice Virtex 5 FPGA User Guide www xilinx com 193 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs 194 Designing Large Multiplexers 4 1 Multiplexer XILINX Each LUT can be configured into a 4 1 MUX The 4 1 MUX can be implemented with a flip flop in the same slice Up to four 4 1 MUXes can be implemented in a slice as shown in Figure 5 21 SLICE pu UE ETT LUT l l O6 0 t 4 1 MUX Output go l SEL D 1 0 DATA D 3 0 PIS 1D 6 AI6 DQ Registered Input Output gt l l l Optional LUT Optional O6 C gt 4 1 MUX Output SEL C 1 0 DATA C 3 0 C 6 1 6 CQ Registered mput tS Atea Pe T Output l i l l Optional I l LUT Op l l l l O6 BS 4 1 mux Output l l B 6 1 amp BQ Registered SEL B 1 0 DATA nn HY A 6 1 Output l D l l LUT Optional A i O6 A 4 1 MUX Output 1 A 6 1 AQ Registered SEL A 1 0 DATA A 3 0 6 T E l6 1 ES 17 Output l l l CLK Optional l SEA CLK Op l UG190_5_21_050506 Figure 5 21 Four 4 1 Multiplexers in a Slice www xilinx com Virtex 5 FPGA
420. tive IBUFDS IBUFGDS Output to FPGA IB Inputs from device pads ug190_6_20_022806 Figure 6 22 Differential Input Buffer Primitive IBUFDS IBUFGDS 232 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Virtex 5 FPGA SelectlO Primitives OBUFDS Figure 6 23 shows the differential output buffer primitive OBUFDS Oo l Out put to Device Pads Input from FPGA OB ugi90 6 21 022806 Figure 6 23 Differential Output Buffer Primitive OBUFDS OBUFTDS Figure 6 24 shows the differential 3 state output buffer primitive OBUFTDS 3 state Input O Loo Output to Input from Device Pads FPGA OB ug190_6_22_022806 Figure 6 24 Differential 3 state Output Buffer Primitive OBUFTDS IOBUFDS Figure 6 25 shows the differential input output buffer primitive IOBUFDS T 3 state Input IO 1 0 Input to from from FPGA 6 IOB device pad O Output to FPGA ugi 90 6 23 022806 Figure 6 25 Differential Input Output Buffer Primitive IOBUFDS Virtex 5 FPGA User Guide www xilinx com 233 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Virtex 5 FPGA SelectlO Attributes Constraints Access to some Virtex 5 FPGA I O resource features e g location constraints input delay output drive strength and slew rate is available through the attributes constraints associated with these featur
421. tive write clock edge the data out O SPO or DOD 0 reflects the newly written data www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX CLB Primitives Inverting Clock Pins The clock pin CLK has an individual inversion option The clock signal can be active at the negative edge of the clock or the positive edge for the clock without requiring other logic resources The default is at the positive clock edge Global Set Reset GSR The global set reset GSR signal does not affect distributed RAM modules Shift Registers SRLs Primitive One primitive is available for the 32 bit shift register SRLC32E Figure 5 33 shows the 32 bit shift register primitive SRLC32E UG190 5 33 050506 Figure 5 33 32 bit Shift Register Instantiating several 32 bit shift register with dedicated multiplexers F7 AMUX F7BMUX and F8MUX allows a cascadable shift register chain of up to 128 bit in a slice Figure 5 18 through Figure 5 20 in the Shift Registers Available in SLICEM only section of this document illustrate the various implementation of cascadable shift registers greater than 32 bits Port Signals Clock CLK Either the rising edge or the falling edge of the clock is used for the synchronous shift operation The data and clock enable input pins have setup times referenced to the chosen edge of CLK Data In D The data input provides new data one bit to be shifted into the shift regis
422. to be selected by the user to provide optimum noise margin in the use conditions specified by the user 3 HSTL II T DCI has a weaker driver than HSTL II DCI Differential HSTL Class II Figure 6 44 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with unidirectional termination External Termination V 0 75V V 0 75V jog TT us IOB DIFF HSTL Il TS Tm XI C Zo D DIFF HSTL Il Vr 0 75V Vr 0 75V DIFF_HSTL_II 5 bb bq C Zo bd jm ugi90 6 40 030206 Figure 6 44 Differential HSTL 1 5V Class Il Unidirectional Termination Virtex 5 FPGA User Guide www xilinx com 253 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 45 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with unidirectional DCI termination DCI IOB 10B DIFF HSTL Il DCI 2Rypp 2Zo 1000 2Rypp 2Zo 1000 Xt 2 X 2Rypy 2Zo 1000 2Rypy 72297 1000 DIFF _HSTL_II_DCI l DIFF_HSTL_II_DC 2Rypp 2Zg 1000 2Rypp 2Zo 1000 x9r 2Ryan 2Zg 1002 2Rygw 2Zg 1002 ug190_6_44 020306 Figure 6 45 Differential HSTL 1 5V Class Il DCI Unidirectional Termination Figure 6 46 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with bidirectional termination External Termination
423. uad Port 64 x 1 bit RAM e Simple Dual Port 64 x 3 bit RAM e Single Port 128 x 1 bit RAM e Dual Port 128 x 1 bit RAM e Single Port 256 x 1 bit RAM Distributed RAM modules are synchronous write resources A synchronous read can be implemented with a storage element or a flip flop in the same slice By placing this flip flop the distributed RAM performance is improved by decreasing the delay into the clock to out value of the flip flop However an additional clock latency is added The distributed elements share the same clock input For a write operation the Write Enable WE input driven by either the CE or WE pin of a SLICEM must be set High 178 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX CLB Overview Table 5 5 shows the number of LUTs four per slice occupied by each distributed RAM configuration Table 5 5 Distributed RAM Configuration RAM Number of LUTs 32x1S 1 32x1D 2 32x2Q0 4 32 x 6SDP 4 64 x 1S 1 64 x ID 64 x 10 64 x 3SDP O 128 x 1S 128 x ID 256 x 1S A A N A A N Notes 1 S single port configuration D dual port configuration Q quad port configuration SDP simple dual port configuration 2 RAM32M is the associated primitive for this configuration 3 RAM64M is the associated primitive for this configuration For single port configurations distributed RAM has a common address port for s
424. uency can result in several possible M and D values The next step is to determine the optimum M and D values The starting M value is first determined This is based off the VCO target frequency the ideal operating frequency of the VCO D min X fvcomax MrpzgArL m Equation 3 7 The goal is to find the M value closest to the ideal operating point of the VCO The minimum D value is used to start the process The goal is to make D and M values as small as possible while keeping f yco as high as possible PLL Ports Table 3 3 summarizes the PLL ports Table 3 4 lists the PLL attributes Table 3 3 PLL Ports Pin Name yo Pin Description CLKIN1 Input General clock input CLKIN2 Input Secondary clock input to dynamically switch the PLL reference clock CLKFBIN Input Feedback clock input CLKINSEL Input Signal controls the state of the input mux High CLKIN1 Low CLKIN2 Asynchronous reset signal The RST signalis an asynchronous reset for the PLL The PLL will synchronously re enable itself when this signal is released i e PLL re enabled A reset is required when the input clock conditions change e g frequency RST Input The dynamic reconfiguration address DADDR input bus provides a DADDR 4 0 Input reconfiguration address for the dynamic reconfiguration When not used all bits must be assigned zeros Virtex 5 FPGA User Guide www xilinx com 93 UG190 v4 4 December 2 2008 Ch
425. ultiplexer output stays High until I1 transitions Low to High e When Il transitions from Low to High the output switches to I1 e IfSetup Hold are met no glitches or short pulses can appear on the output BUFGMUX_VIRTEX4 BUFGMUX VIRTEXA is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 11 illustrates the relationship of BUFGMUX_VIRTEX4 and BUFGCTRL 30 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Global Clocking Resources IGNORE1 CE1 S1 GND Vpp BUFGMUX VIRTEX4 o 50 CEO Vo anp GNOREO ugi90 1 11 032206 Figure 1 11 BUFGMUX_VIRTEX4 as BUFGCTRL BUFGMUX_VIRTEX4 uses the S pins as select pins S can switch anytime without causing a glitch The Setup Hold time on S is for determining whether the output will pass an extra pulse of the previously selected clock before switching to the new clock If 5 changes as shown in Figure 1 12 prior to the setup time Tpgccck s and before I0 transitions from High to Low then the output will not pass an extra pulse of I0 If 5 changes following the hold time for S then the output will pass an extra pulse If S violates the Setup Hold requirements the output might pass the extra pulse but it will not glitch In any case the output will change to the new clock within three clock cycles
426. ure 6 11 illustrates split termination inside a Virtex 5 device IOB Vcco 2R 2 Tt pp VREF Viriex5 DCI UG190_6_09_021206 Figure 6 11 Input Termination to Vcco 2 Using DCI Split Termination Driver with Termination to Vcco Single Termination Some I O standards e g HSTL Class IV require an output termination to Veco Figure 6 12 illustrates an output termination to Vcco Vcco gt om Zo Virtex 5 UG190_6_10_021206 Figure 6 12 Driver with Termination to Vcco without DCI DCI can provide an output termination to Vcco using single termination In this case DCI only controls the impedance of the termination but not the driver Both GTL and HSTL standards need 50 Q external reference resistors The DCI I O standards supporting drivers with single termination are GTL_DCI GTLP_DCI HSTL IV DCI and HSTL IV DCI 18 Virtex 5 FPGA User Guide www xilinx com 225 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 13 illustrates a driver with single termination inside a Virtex 5 device Vcco IOB R Zo Virtex 5 DCI UG190_6_11_021206 Figure 6 13 Driver with Termination to Vcco Using DCI Single Termination Driver with Termination to Vcco 2 Split Termination Some I O standards such as HSTL Class II require an output termination to Vcco 2 see Figure 6 14 Vcco 2 gt ND Zo Virtex 5 UG190_6_12_021206 Figure 6 14 Driver wit
427. us e when the frequencies of the two clocks are the same but the phase is different e when one frequency is a multiple of the other Synchronous FIFO Virtex 4 FPGA designs used the same FIFO logic for multirate and synchronous FIFOs thus flag latency in synchronous FIFOs can vary By setting the EN SYN attribute to TRUE when using Virtex 5 FPGA synchronous FIFOs any clock cycle latency when asserting or deasserting flags is eliminated First word fall through FWFT mode is only supported in the multirate FIFO EN SYN FALSE Table 4 13 shows the FIFO capacity in the two modes Virtex 5 FPGA User Guide www xilinx com 139 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Table 4 13 FIFO Capacity Standard Mode FWFT Mode 18 Kb FIFO 36 Kb FIFO 18 Kb FIFO 36 Kb FIFO 4k 1 entries by 4bits 8k 1 entries by 4bits 4k 2 entries by 4 bits 8k 2 entries by 4 bits 2k 1 entries by 9 bits 4k 1 entries by 9 bits 2k 2 entries by 9 bits 4k 2 entries by 9 bits 1k 1 entries by 18 bits 2k 1 entries by 18 bits 1k 2 entries by 18 bits 2k 2 entries by 18 bits 512 1 entries by 36 bits 1k 1 entries by 36 bits 512 2 entries by 36 bits 1k 2 entries by 36 bits 512 1 entries by 72 bits 512 2 entries by 72 bits Synchronous FIFO Implementations Table 4 14 outlines varied implementations of synchronous FIFOs Figure 4 16 shows the timing differences Table 4 14
428. ustry Alliance JEDEC web site at http ww w jedec org LVTTL Low Voltage Transistor Transistor Logic The low voltage TTL LVTTL standard is a general purpose EIA JESDSA standard for 3 3V applications using an LVTTL input buffer and a push pull output buffer This standard requires a 3 3V input and output supply voltage Vcco but does not require the use of a reference voltage Vpgp or a termination voltage V1 Sample circuits illustrating both unidirectional and bidirectional LVTTL termination techniques are shown in Figure 6 26 and Figure 6 27 IOB IOB LVTTL LVTTL gt P4 m gt eee IOB lOB LVTTL LVTTL Rg Zg Rp gt Kw m gt s 4 IOB Yr po 5 LVTTL LVTTL Rp Zo gt x 53 gt Note V is any voltage from OV to Veco ug190 6 24 022806 Figure 6 26 LVTTL Unidirectional Termination 236 www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 XILINX Specific Guidelines for I O Supported Standards LVTTL LVTTL Pan gt 4j d 0B Vrr EE IOB LVTTL LVTTL gt M ugi90 6 25 022806 Note V is any voltage from OV to Voco Figure 6 27 LVTTL Bidirectional Termination Table 6 4 lists the LVTTL DC voltage specifications Table 6 4 LVTTL DC Voltage Specifications Parameter Min Typ Max Vcco 3 0 3 3 3 45 VREF VTT u Vin 2 0 3 45
429. ut immediately when the select pin changes while IGNORE causes the output to switch away from the I1 input immediately when the select pin changes Selection of an input clock requires a select pair SO and CEO or 1 and CE1 to be asserted High If either S or CE is not asserted High the desired input will not be selected In normal operation both S and CE pairs all four select lines are not expected to be asserted High simultaneously Typically only one pin of a select pair is used as a select line while the other pin is tied High The truth table is shown in Table 1 3 Table 1 3 Truth Table for Clock Resources CEO SO CE1 S1 O 1 1 X IO 1 1 X 0 IO 0 X 1 11 X 0 1 1 n 1 1 1 1 Old Input Notes 1 Old input refers to the valid input clock before this state is achieved 2 For all other states the output becomes the value of INIT OUT and does not toggle Although both S and CE are used to select a desired output each one of these pins behaves slightly different When using CE to switch clocks the change in clock selection can be faster than when using S Violation in Setup Hold time of the CE pins causes a glitch at the clock output On the other hand using the S pins allows the user to switch between the two clock inputs without regard to Setup Hold times It will not result in a glitch See BUFGMUX_VIRTEX4 The CE pin is designed to allow backward compatibility from Virtex II an
430. utputs or one of the DCMs Each clock input has a programmable counter D The Phase Frequency Detector PFD compares both phase and frequency of the input reference clock and the feedback clock Only the rising edges are considered because as long as a minimum High Low pulse is maintained the duty cycle is not important The PFD is used to generate a signal proportional to the phase and frequency between the two clocks This signal drives the Charge Pump CP and Loop Filter LF to generate a reference voltage to the VCO The PFD produces an up or down signal to the charge pump and loop filter to determine whether the VCO should operate at a higher or lower frequency When VCO operates at too high of a frequency the PFD activates a down signal causing the control voltage to be reduced decreasing the VCO operating frequency When the VCO operates at too low of a frequency an up signal will increase voltage The VCO produces eight output phases Each output phase can be selected as the reference clock to the output counters Figure 3 3 Each counter can be independently programmed for a given customer design A special counter M is also provided This counter controls the feedback clock of the PLL allowing a wide range of frequency synthesis www xilinx com 87 UG190 v4 4 December 2 2008 Chapter 3 Phase Locked Loops PLLs 88 General Routing Clock Switch Circuit CLKIN1 gt CLKIN2 CLKFB Lock Detect XILI
431. vided clock input CLKDIV is typically a divided version of CLK depending on the width of the implemented deserialization It drives the output of the serial to parallel converter the Bitslip submodule and the CE module Serial Input Data from IOB D The serial input data port D is the serial high speed data input port of the ISERDES NODELAY This port works in conjunction with all the Virtex 5 FPGA I O resources to accommodate the desired I O standards High Speed Clock for Strobe Based Memory Interfaces OCLK The OCLK clock input synchronizes data transfer in strobe based memory interfaces The OCLK of the ISERDES NODELAY shares the same routing as the CLK port of the OSERDES The OCLK clock input is used to transfer strobe based memory data onto a free running clock domain OCLK is a free running FPGA clock at the same frequency as the strobe on the CLK input The domain transfer from CLK to OCLK is shown in the Figure 8 5 block diagram The timing of the domain transfer is set by the user by adjusting the delay of the strobe signal to the CLK input e g using IDELAY Examples of setting the timing of this domain transfer are given in several memory related application notes including XAPP858 High Performance DDR2 SDRAM Interface in Virtex 5 Devices When INTERFACE_TYPE is NETWORKING this port is unused Reset Input RST The reset input causes the outputs of all data flip flops in the CLK and CLKDIV domains to be driven
432. when a clock is on the BUFR input port Virtex 5 FPGA User Guide www xilinx com 39 UG190 v4 4 December 2 2008 40 Chapter 1 Clock Resources XILINX BUFR Attributes and Modes Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute Table 1 8 lists the possible values when using the BUFR_DIVIDE attribute Table 1 8 BUFR_DIVIDE Attribute Attribute Name Description Possible Values BUFR_DIVIDE Defines whether the output clock is a 1 2 3 4 5 6 7 8 divided version of the input clock BYPASS default Notes 1 Location constraint is available for BUFR The propagation delay through BUFR is different for BUFR_DIVIDE 1 and BUFR_DIVIDE BYPASS When set to 1 the delay is slightly more than BYPASS All other divisors have the same delay BUFR_DIVIDE 1 The phase relationship between the input clock and the output clock is the same for all possible divisions except BYPASS The timing relationship between the inputs and output of BUFR when using the BUFR_DIVIDE attribute is illustrated in Figure 1 21 In this example the BUFR_DIVIDE attribute is set to three Sometime before this diagram CLR was asserted CLR TBRCKO_O TBRDO_CLRO TBRCKO_O z mi o TT gD ug190 1 21 041808 Figure 1 21 BUFR Timing Diagrams with BUFR DIVIDE Values In Figure 1 21 e Before clock event 1 CE is asserted High e After CE is asserted and time Tggcko o the outpu
433. without glitches from tap 0 to tap 1 See Stability after an Increment Decrement Operation Clock Event 3 CE and INC are no longer asserted thus completing the increment operation The output remains at tap 1 indefinitely until there is further activity on the RST CE or INC pins Stability after an Increment Decrement Operation Figure 7 9 shows a period of instability when the output is changing from one tap to another Clearly when the data value at tap 0 is different from the data value at tap 1 the output must change state However when the data values at tap 0 and tap 1 are the same e g both 0 or both 1 then the transition from tap 0 to tap 1 causes no glitch or disruption on the output This concept can be comprehended by imagining the receiver data signal in the IODELAY tap chain If tap 0 and tap 1 are both near the center of the receiver data eye then the data sampled at tap 0 should be no different than the data sampled at tap 1 In this case the transition from tap 0 to tap 1 causes no change to the output To ensure that this is the case the increment decrement operation of IODELAY is designed to be glitchless The user can dynamically adjust the IODELAY tap setting in real time while live user data is passing through the IODELAY element the adjustments do not disrupt the live user data The glitchless behavior also applies when an IODELAY element is used in the path of a clock signal Adjusting the tap setting d
434. wo asynchronous clocks All other global clock buffer primitives are derived from certain configurations of BUFGCTRL The ISE software tools manage the configuration of all these primitives BUFGCTRL has four select lines S0 S1 CEO and CE1 It also has two additional control lines IGNOREO and IGNORE These six control lines are used to control the input I0 and I BUFGCTRL IGNORE1 CE1 IGNOREO ugi 90 1 01 032206 Figure 1 1 BUFGCTRL Primitive www xilinx com Virtex 5 FPGA User Guide UG190 v4 4 December 2 2008 2 XILINX Global Clocking Resources BUFGCTRL is designed to switch between two clock inputs without the possibility of a glitch When the presently selected clock transitions from High to Low after S0 and S1 change the output is kept Low until the other to be selected clock has transitioned from High to Low Then the new clock starts driving the output The default configuration for BUFGCTRL is falling edge sensitive and held at Low prior to the input switching BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching In some applications the conditions previously described are not desirable Asserting the IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching between two clock inputs In other words asserting IGNORE causes the mux to switch the inputs at the instant the select pin changes IGNOREO causes the output to switch away from the I0 inp
435. ww xilinx com 125 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX GSR The global set reset GSR signal of a Virtex 5 device is an asynchronous global signal that is active at the end of device configuration The GSR can also restore the initial Virtex 5 device state at any time The GSR signal initializes the output latches to the INIT simple dual port or to the INIT A and INIT B value true dual port See Block RAM Attributes A GSR signal has no impact on internal memory contents Because it is a global signal the GSR has no input pin at the functional level block RAM primitive Unused Inputs Unused data and or address inputs should be connected High Block RAM Address Mapping Each port accesses the same set of 18 432 or 36 864 memory cells using an addressing scheme dependent on whether it is a RAMB18 or RAMB36 The physical RAM locations addressed for a particular width are determined using the following formula of interest only when the two ports use different aspect ratios END ADDR 1 x Width 1 START ADDR x Width Table 4 8 shows low order address mapping for each port width Table 4 8 Port Address Mapping IER 1 N A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
436. x Ves 1 40 1 50 1 60 V as 0 90 z Ver x Vcco s Vig Vas 0 1 E 5 V Wien 0 1 Vou Veco 04 Vor 0 4 Top at Voy mA 8 E B Tor at Vor mA 48 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vpgrg is to be selected by the user to provide optimum noise margin in the use conditions specified by the user HSTL Il T DCI 1 5V Split Thevenin Termination Figure 6 51 shows a sample circuit illustrating a valid termination technique for HSTL II T DCI 1 5V with on chip split thevenin termination In this bidirectional case when 3 stated the termination is invoked on the receiver and not on the driver DCI Not 3 stated 3 stated IOB IOB Voco 1 5V 2Rypp 2Z9 1000 HSTL_II_T_DCI HSTL II T DCI D1 Q 40 a Vper 0 75V Vgge 0 75V 2Rypy 2Zg 1002 ug190_6_90_041206 Figure 6 51 HSTL II T DCI 1 5V Split Thevenin Termination Virtex 5 FPGA User Guide www xilinx com 259 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX HSTL Class 1 8V Figure 6 52 shows a sample circuit illustrating a valid termination technique for HSTL Class I 1 8V External Termination IOB HSTL 18 HSTL 18 x m Veer 0 9V IOB IOB Veco 1 8V 2Rypp 2297 1000 HSTL I DCI 18 HSTL I DCI 18 Dq O 4 gt _XI Vper 0 9V E 2Rypy
437. y DIP 7 0 pins are not used Virtex 5 FPGA User Guide www xilinx com 165 UG190 v4 4 December 2 2008 Chapter 4 Block RAM XILINX Similarly at time T2W and T3W DI 63 0 B and C together with their corresponding parity bits PB hex and PC hex are written into memory locations b and c PB and PC appear at output ECCPARITY 7 0 shortly after T2W and T3W ECC Encode Only Read ECC encode only read is identical to normal block RAM read 64 bit data appears at DO 63 0 and 8 bit parity appears at DOP 7 0 Single bit error correction does not happen and the error flags SBITERR and DBITERR is never asserted ECC Decode Only Set by Attributes EN ECC READ TRUE EN ECC WRITE FALSE In ECC decode only only the ECC decoder is enabled The ECC encoder is disabled Decode only mode is used to inject single bit or double bit errors to test the functionality of the ECC decoder The ECC parity bits must be externally supplied using the DIP 7 0 pins Using ECC Decode Only to Inject Single Bit Error e Attime TIW T2W T3W DI 63 0 A B C with single bit error and DIP 7 0 PA hex PB hex PC hex the corresponding ECC parity bits for A B and C are written into memory locations a b and c e Attime TIR T2R T3R the contents of address a b and c are read out and corrected as needed e Latch mode DO 63 0 A B C DOP 7 0 PA PB PC shortly after TIR T2R T3R e Register mode DO 63 0 A B C DO
438. y the value of Vcco The voltage across the gate oxide at any time must not exceed 4 05V Consider the case in which the I O is either an input or a 3 stated buffer as shown in Figure 6 90 The gate of the output PMOS transistor Py and NMOS transistor Ng is connected essentially to Veco and ground respectively The amount of undershoot allowed without overstressing the PMOS transistor Pp is the gate voltage minus the gate oxide limit or Veco 4 05V Similarly the absolute maximum overshoot allowed without overstressing the NMOS transistor N is the gate voltage plus the gate oxide limit or Ground 4 05V Output Driver Input Buffer gem e mem um em e e m mi eer jme nnl mni omm mm ces ce mm Veco Veco l l l l l I Fo l l E i l Power xterna i l Clamp Pin I Diode I l Dp l l l l l l l l P l l l l l l l l No N l Ground i Clamp Diode l De l l l l l l l l l l l nd GND j l TTE GND SS E ug190_6_85_030506 Figure 6 90 Virtex 5 FPGA I O 3 State Output Driver The clamp diodes offer protection against transient voltage beyond approximately Veco 0 5V and Ground 0 5V The voltage across the diode increases proportionally to the current going through it Therefore the clamped level is not fixed and can vary Virtex 5 FPGA User Guide www xilinx com 299 UG190 v
439. y tying the D1 input of the ODDR primitive High and the D2 input Low Xilinx recommends using this scheme to forward clocks from the FPGA fabric to the output pins Output DDR Primitive ODDR Figure 7 25 shows the ODDR primitive block diagram Table 7 13 lists the ODDR port signals Table 7 14 describes the various attributes available and default values for the ODDR primitive D1 Q D2 ODDR CE R ug190_7_20_012207 Figure 7 25 ODDR Primitive Block Diagram Table 7 13 ODDR Port Signals Port Function Description Name Q Data output DDR ODDR register output C Clock input port The CLK pin represents the clock input pin CE Clock enable port CE represents the clock enable pin When asserted Low this port disables the output clock on port Q D1 and D2 Data inputs ODDR register inputs R Reset Synchronous Asynchronous reset pin Reset is asserted High S Set Synchronous Asynchronous set pin Set is asserted High Table 7 14 ODDR Attributes Attribute Name Description Possible Values DDR CLK EDGE Sets the ODDR mode of operation with OPPOSITE EDGE respect to clock edge default SAME EDGE INIT Sets the initial value for Q port 0 default 1 SRTYPE Set Reset type with respect to clock C ASYNC SYNC default Virtex 5 FPGA User Guide www xilinx com 343 UG190 v4 4 December 2 2008 Chapter 7 SelectlO Logic Resources XILINX ODDR VHDL and Verilo
440. ynchronous writes and asynchronous reads For dual port configurations distributed RAM has one port for synchronous writes and asynchronous reads and another port for asynchronous reads In simple dual port configuration there is no data out read port from the write port For quad port configurations distributed RAM has one port for synchronous writes and asynchronous reads and three additional ports for asynchronous reads In single port mode read and write addresses share the same address bus In dual port mode one function generator is connected with the shared read and write port address The second function generator has the A inputs connected to a second read only port address and the WA inputs shared with the first read write port address Figure 5 6 through Figure 5 14 illustrate various example distributed RAM configurations occupying one SLICEM When using x2 configuration RAM32X2Q A6 and WA6 are driven High by the software to keep O5 and O6 independent Virtex 5 FPGA User Guide www xilinx com 179 UG190 v4 4 December 2 2008 Chapter 5 Configurable Logic Blocks CLBs XILINX RAM 32X2Q T E MU m s ib AVBUCUDI PPE ADDRD 4 0 l ESI is t AX WA l WCLK CLK l DOD 1 NE WE i l DOC 0 ADDRC 4 0 l DOC 1 l l l i DOB O l ADDRB 4 0 l i DOB 1 l l i DOA
441. ypy 2Zg 1002 Ro 250 ug190_6_69_030506 Figure 6 72 Differential SSTL2 2 5V Class II Unidirectional DCI Termination Figure 6 73 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class II 2 5V with bidirectional termination External Termination IOB Vr 1 25V Vyr 1 25V IOB DIFF SSTL2 Il DIFF SSTL2 Il Vy 1 25V Vr 1 25V DIFF SSTL2 Il DIFF SSTL2 Il 500 500 250 DX ANN C Zo NN x DIFF SSTL2 Il DIFF SSTL2 Il ug190 6 70 071707 Figure 6 73 Differential SSTL2 2 5V Class Il with Bidirectional Termination Virtex 5 FPGA User Guide www xilinx com 279 UG190 v4 4 December 2 2008 Chapter 6 SelectlO Resources XILINX Figure 6 74 shows a sample circuit illustrating a valid termination technique for differential SSTL2 Class II 2 5V with bidirectional DCI termination DCI IOB Veco 2 5V DIFF SSTL2 Il DCI 2Rygp 2Zo 1002 IOB Veco 2 5V 2Rypp 2Zo 1002 DIFF SSTL2 Il DCI Ry 250 2Rypy 2Zg 1002 E DIFF SSTL2 Il DCI Am 2 T 2Rypy 2Zg 1000 Ro 25Q DIFF SSTL2 Il DCI Ro 250 DIFF SSTL2 Il DCI Voco 2 5V 2Rypp 2Zo 1002 2Rypy 2Zg 1000 OWH Ro 25Q DIFF SSTL2 Il DCI 2Rygp 2Zo 1002 2Rypy 2Zg 1000 ug 90 6 71 041106 Figure 6 74 Differential SSTL2 2 5V Cl

Xilinx UG190 Virtex

Contents

Download Pdf Manuals

Related Search

Related Contents