SAU-XDS510-USB Lite User's Guide
Contents
1. Enable adaptive clocking divider parameter 3 6 3 Adaptive clocking mode On default TCK is generated by the Connection Properties emulator independently of the TCKR Set the properties of the selected connection from the target The TCK frequency Board Data File auto generate owe is constant But some processors require the TCK to be below some limit The limit is set inside the processor and depends on the processor s own clock frequency Use specified emulator only Enter Serial Number Enter Serial Number again TCK Frequency divider range x1 which can change considerably TCK Frequency 15000MHz owe during the operating e g because J Enable additional 8x TCK divider of PLL programming Such processors l have JTAG return clock frequency TCKR signal mode Target provide TCKR signal output gated by the required C Enable adaptive clocking internal frequency If this output TMS TDO Output Timing Change at rising edge allows higher TCK is connected to emulator s TCKR TCKR input termination Enable 120 Ohm termination 4 input the adaptive clocking mode allows the emulator to operate at TDI input termination Enable 120 Ohm termination l j Ba the maximum frequency that is O voltage Set En value at PD pin with clamping ka possible for the processor The JTAG output level clamping 3 3V default reason is in adaptive clocking EMOQ TO pin made 45 input with pullup default mode the e2. clock source from the emulation pod This signal can be used to drive the system test clock Emulation pin 0 Input Output Input Output Emulation pin 1 Inpub OGtput Input Output 10 Copyright 2014 Sauris GmbH SAURIS www sauris de 3 1 2 20 pin ARM JTAG description User s guide SAU XDS510 USB Lite JTAG Emulator Revision 1 00 JUL2014 The pin assignment scheme is shown in Figure 3 2 And the emulation signals are described in Table 2 5 TDI 7 TMS JD TMS Ck VTref nTRSI TDI TMS TCR RUCK TDO RESET DBGRO DBGACK VDD GND GND GND GND GND GND GND GND GND Figure 3 2 20 pin ARM JTAG Connector Table 2 20 Pin ARM Header Signal Description i Emulator Target 1 VTref Power detect Indicates power and voltage levels on JTAG signal circuits It should be connected to target JTAG I O buffers 3 vp rwr o N6 RTRST Output JTAG data input of the target CPU QUIDUL JTAG mode set input of the target CPU QULDUut JTAG clock signal to target CPU QUT Dut 11 RTCK Return test clock signal from the target Copyright 2014 Sauris GmbH F 7 i 4 r JTAG Emulator User s gu ide S AURIS Revision 1 00 JUL 2014 www Ssauris de SAU XDS510 USB Lite 3 1 3 20 pin CTI JTAG description The pin assignment scheme is shown in Figure 3 3 And the emulation signals are described in Table 3 TMS IRS
3. SOT xs2 3233192959 5228 93 5 92 59 93 23 1259 99 135 55 16 3 6 1 Parameters for connection several emulators to one PC 16 Sees Pat emeeer s com SeCLIng TON SUBEGIT 42454445448 aa enue a il Ora On ba OO AOE Lye LOCK IOO MCCS ike 5 044 PUNCLIONING WienOulL Perurn Clocking TCKR gt ktoe R91 3e 3399 isi iks 3 6 5 TMS and TDO emulator signals output buffers clocking mode 18 SN CeCe Impedance matcning XG OU Ge COTES 0 ES 19 oP Pr Eo n le e Ee aa O o a ee E et bee Uh ee eee EENEN USES Eee EEE 19 300a UTAG OO Level Clamping rrr tee eee eee eee eee eee eee UR ER 20 CERE UNUU L Di 4444454655 24s eee eee eee eee eee ee eee ee ee ee eu eee eee 20 Copyright 2014 Sauris GmbH mbH SAU XDS510 USB Lite SAURIS User s guide JTAG Emulator www Ssauris de Revision 1 00 JUL2014 Dear developers 1 Sauris GmbH is pleased to recommend you to ask your technical questions on our forum You can find answers to your questions on the forum pages and add a new topic to discuss the problem with our engineers 2 We suggest you to read WiKi where you can find the full description Of Our products functionality Please register and ask your question Please don t forget to subscribe to new topics to keep track of the status of your question You will get an e mail notification as soon as our engineers respond to the message 3 Dear Friends you could join projects support program right now sending us RFQ Technica
4. equipment and software required for SAU XDS510 USB Lite JTAG emulator operation Hardware checklist o Host any PC or laptop with a hard disk system and a USB port and a CD ROM disk drive o Memory minimum of 32MB o Display color VGA or LCD o Emulator SAU XDS510 USB Lite JTAG emulator o Target system any TI DSP based or TI Microcontroller based board with power supply o Connectors 14 pin connector two rows of seven pins 20 pin connector ARM JTAG or 20 pin CTI JTAG See Section 3 for more information on connecting to target system Copyright O 2014 Sauris GmbH 7 N Fal a1 SAU XDS510 USB Lite bill JTAG Emulator User s gu ise g AURIS Revision 1 00 JUL 2014 www Ssauris de Software checklist o Operating system Microsoft Windows 2000 Windows XP Windows Vista 32 bit 64 bit Windows 7 Windows 8 Windows 8 1 Windows Server 32 64 bit Linux o Software tools Code Composer Studio o Drivers Sauris GmbH drivers for TI Code Composer Studio are included into SAU XDS510 USB Lite JTAG emulator delivery set and are also available at Sauris GmbH website www sauris de 2 2 Connecting SAU510 USB ISO PLUS JTAG v 2 Emulator Follow the steps in this section CO plug SAU XDS510 USB Lite Emulator in your PC and target board Figure 2 1 shows SAU XDS510 USB Lite connected to a target system and a PC While using standard 14 pin TI JTAG connector it is possible to connect SAU XDS5I0 USB Lite with
5. processor pins Minimum value is 3 because of the count Of synchronization filip flops inside the emulator If the delay of TMS TDO generated from the rising edge of TCKR signal exceeds one cycle of TCKR the Link Delay should be increased by one thus the value is to be 4 If the delay exceeds two cycles the Link Delay is to be increased by 2 SAU XDS510 USB Lite JTAG Emulator P x run NSN ini f User s guide S AURIS SEAS Revision 1 00 JUL 2014 3 6 8 JTAG output level clamping Connection Properties Set the properties of the selected connection auto generate 4 Use specified emulator only 15 000 MHz 4 Enable additional amp x TCK divider TCKR signal mode Target provide TEER signal Board Data File TCE Frequency Enable adaptive clocking TMS TDO Output Timing Change at rising edge allows higher TCK F Enable 120 Ohm termination Enable 120 Ohm termination F Set to value af PD pin with damping 7 JTAG output level clamping 3 3 default 0 EMUO I O pin made TCER input termination TDI input termination To voltage amp s input with pullup tdeFaulE EMOL Il pin made As input with pullup default 3 TEK clocks default Skipped IT Link delay Polling of Icepick C router TCRR input termination Enable 120 Ohm termination TDI input termination Enable 120 Ohm termination To voltage Force to speci
6. the data events and as outputs with arbitrary values which actually set through EMU I O pin mode Copyright 2014 Sauris GmbH E Embi SAU XDS510 USB Lite GS AURIS User s guide JTAG Emulator www Ssauris de Revision 1 00 JUL2014 IMPORTANT NOTICE Sauris GmbH and its subsidiaries Sauris reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Sauris s terms and conditions of sale provided at the time of order acknowledgment Sauris warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Sauris s standard warranty Testing and other quality control techniques are used to the extent Sauris deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Sauris assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Sauris devices To minimize the risks associated with customer products and applications customers should provide adequate design and operating safegu
7. Gk XURTS SAU XDS510 USB Lite JTAG Emulator 2014 SAU XDS510 USB Lite JTAG Emulator User s gu ide S AURIS Revision 1 00 JUL 2014 www Ssauris de Contents CONCENCS 44 644455546 E IUPTTTrr 2 1 Introduction to SAU XDS510 USB Lite JTAG Emulator 5 iil Overview of SAU XDSOIU USPB Lite JTAG Emuldb5OFZ s 4anh soe Se o es D Lez Key Features of SAU XDS510 USB Lite JTAG Emulator 5 9 6 UNS Key Items of GSAU XDSOILO USB Lite JTAG ENHUlSUtOP 2 229 9 ore 7 2 SAU XDS510 USB Lite JTAG Emulator Plugging 7 Zell CBIpmens X Bb RG 426 oe eee Se oe eRe Bese Ee eee eee 7 2 7 COnmectanc SAUDL DSB 100 PLUS JIAG w 2 BMULALOY eae 33 is 8 Bu UI SU UI 9 35 Specifications for Your Target System s Connection to the ENuldto E 22992309 8 2020 ds dor or ee ee eae eae ag ayy eS 9 3 1 Designing Your Target System s JTAG Connector 9 Sellele ADIN OTR dO CEIP ON 2 obo oe Bg RS ee a a a ae aa SPURS 10 Seely UPIN APRM JIAO Gec CTIE RLs4534595514229 532492915959 5999 05 55 5955 IET RU Oi 2mm SIT AC descr orton 25255546 ese sete cess 899 9 15 8 9 9 95 99 2 5 12 Dau BUS TPI l 23 39959992919 3 3 19 eaer 13 S25 uulcsorx Cable DOS SO 205a R3RmOE ee eee ene PUR REOR eie eee UR ROS eU RO EON 1 9 o Emularor Cable Pod cogno TIMING 24 50 839 oo ew 372 328 802 999 3 9 SOR RS eels 13 3 5 Buffering Signals Between the Emulator and the Target System 14 Su UTLAG cOODINGC CON
8. I TDI GND PD No pin key TDO GND CK BREI GND TOF GND EMUO EMU1 OROTI GND EMU2 EMU3 EMU4 GND Figure 3 3 20 pin CTI JTAG Connector Table 3 20 Pin CTI Header Signal Description l 6 Emulator Target Find Signal Description TAS state JTAG test mode selection Output 2 TRST JTAG test reset Output JTAG test data input Output 5 Power detect Indicates power and Input Output voltage levels on JTAG signal circuits It should be connected to target JTAG I O buffers TCR RET JTAG test clock return Test Input Output clock input to the emulator May be a buffered or unbuffered version of TCK 11 TCK JTAG test clock TCK is a 12 MHz Output Input clock source from the emulation pod This signal can be used to drive the system test clock Emulation pin 0 Inpub Outpubt Input Output Emulation pin 1 Input Output Input Output 15 SRST This is the target reference Open drain Input Output voltage It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor EMD2 Input Output Input Output EMUS Input Output Input Output EMUA JTAG data input of the target CPU rnput Output znpurt Output 12 Copyright 2014 Sauris GmbH FN i ix Y if X mih SAU XDS510 USB Lite SURIS User s guide JTAG Emulator www saur
9. I JTAG for proper communication with the emulator 3 l Designing Your Target System s JTAG Connector The emulator is connected to target systems through a dedicated port The port supports IEEE 1149 1 JTAG standard and is accessible through the emulator The board is to have a 20 pin header 2 rows of 7 pins 20 pin ARM header or 20 pin CTI header in order to communicate with the emulator NOTE Emulator outputs voltage level can be changed from 1 65 to 3 3V Check paragraph 3 6 8 for details Copyright O 2014 Sauris GmbH 9 F 7 i 4 r JTAG Emulator User s gu ide S AURIS Revision 1 00 JUL 2014 www Ssauris de SAU XDS510 USB Lite 3 1 1 14 pin JTAG description The pin assignment scheme is shown in Figure 3 1 And the emulation signals are described in Table 1 TMS TESI TDI GND PD Veo No pin key TDO GND IOR Re GND DCR GND EMUO EMU1 Figure 3 1 14 pin JTAG Connector Table 1 14 Pin Header Signal Description f f Emulator JTAG test mode selection Output 2 rRsr oraG test reset Output JTAG test data input Output 5 Presence detect Indicates power Input Output and voltage levels on JTAG signal Circuits It should be connected to target JTAG I O buffers JTAG test data output Output TOR RET JTAG test clock return Test Input Output clock input to the emulator May be a buffered or unbuffered version of TCK 11 TCK JTAG test clock TCK is a 12 MHz Output Input
10. OR and the emulator OR RET signals In some cases this may require special PCB trace routing and using termination resistors to match the trace impedance If the distance between the emulation header and the target device is longer than 15 cm the emulation signals must be buffered The need for signal buffering can be divided in two cases e No signal buffering As shown in figure 3 6 the distance between the header and the target device does not exceed 15 cm e Buffered emulation signals Figure 3 7 shows that the distance between the emulation header and the target device is longer than 15 cm The target device signals TMS TDI TDO and TCK RET are buffered through several additional Unive x Menee 15 cM Bonee 15 cM AVCC Vec VCC JTAG Device Emulator Header JTAG Device gt Emulator Header EMUO EMUO EMUO EMUO PD EMU1 EMU1 EMU1 EMUI TRST TRST TRST 1 TRST TMS TMS lt T 41 TMS Tor P lt TDI TDO TDO TCK TCK r TCK_RET GND GND Figure 3 7 No Signal Buffering Figure 3 8 Buffered Emulation Signals The EMUO and EMU1 signals must have pull ups to Vcc The signal rise time of the pull up resistors should be less than 10 uS A 4 7k Q resistor is suggested for most applications EMUO 1 are I O pins of the target device however they are inputs for the emulator only These pins are used in multiprocessor systems to provide run stop operations The emulator pod enables s
11. ards Sauris does not warrant or represent that any license either express or implied 1s granted under any Sauris patent right copyright or other Sauris intellectual property right relating to any combination machine or process in which Sauris products or services are used Information published by Sauris regarding third party products or services does not constitute a license from Sauris to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from Sauris under the patents or other intellectual property of Sauris Reproduction of information in Sauris data books is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice Sauris is not responsible or liable for such altered documentation Resale of Sauris products or services with statements different from or beyond the parameters stated by Sauris for that product or service voids all express and any implied warranties for the associated Sauris product or service and is an unfair and deceptive business practice Sauris is not responsible or liable for any such statements Copyright 2014 Sauris GmbH 1
12. board 2 Detach SAU XDS5S1LU0 USB Lite JTAG emulator s USB cable from PC 3 Detach the emulator s JTAG connector from your target board Note Be very careful with the target cable connectors Connect them gently do not force them into position or you may damage the connectors 8 Copyright 2014 Sauris GmbH X d w w N Bn SAU XDS510 USB Lite 2 mus et User s guide S AURIS JTAG Emulator www Ssauris de Revision 1 00 JUL2014 2 3 SAU XDS510 USB Lite LED SAU XDS510 USB Lite emulator has a three color indicator This indicator shows emulator working modes USB High speed 480 Mbps mode color values are shown in table Figure 2 2 LED Indicator e lights TRST signal is active JTAG is in reset TRST is activated when a target board power downs and by PC command for example while all connections are closed e short blink USB power is on but emulator is not configured e short blink there is no power on target e lights there is a power on target e blinks evenly there is a power on target but there is no ro Urn Clock signal POR BEL e PC is exchanging data with emulator If USB connected as Full Speed 12 Mbps then green and blue are reversed 3 Specifications for Your Target System s Connection to the Emulator This chapter contains the information on connecting your target system to the emulator Your target system must have a special 14 pin connector JTAG 20 pin ARM JTAG or 20 pin CT
13. dge at the TCK is formed according to not only ICK but also EMOL IO pin made 45 input with pullup default ba to the correspondence between TCKR Link delay 3 TCK clocks default ha signal and the current TCK signal Polling of Icepick C router Skipped Ihe rising or falling edge will Thus the rising or falling edge can never be generated before the previous rising falling edge goes through TCK gt TCKR circuit In this case maximum frequency is limited by divider Adaptive clocking mode is usually used with ARM Processors Copyright 2014 Sauris GmbH 17 i UN hs vom 1 SAU XDS510 USB Lite i N bn JTAG Emulator User E guide SAURIS Revision 1 00 JUL 2014 www Ssauris de To set Adaptive clocking mode check the Enable adaptive clocking parameter in the connection properties 3 6 4 Functioning without return clocking TCKR In some cases the system has to Connection Properties Set the properties of the selected connection ope rate without return cloc king Bnard Data File autogenerate O O F signal TCKR for example when D dice Specified emulator oniy operating with ARM JTAG where TCKR Fae Freeitmen Svdluldebrarise B ME signal is optional Thereto there TCK Frequency Toome F 1S a bypass way for the signal TCK gt TCRR beside all outside Enable additional 8x TCK divider GTEGUT 8 This way provides TEKER TCRKR signal mode Target doesn t provide TCKR signal A TCRKR signal mode Targ
14. e Ultra miniature design smallest XDS510 class emulator of currently produced emulation controller with buffers is placed inside of connector body It allowed to eliminate JTAG tail which significantly improved JTAG signal quality and connection stability in EMI conditions e Acceleration is up to 1 3 times versus Iso Plus emulator emulation controller similar to the one used in Iso Plus V 2 e Works with higher clock frequencies TCK without fine tuning up to 52 5MHz depending on debugging device e Supports from 1 65 volt up to 3 3 volt JTAG interfaces 5V tolerant e Controlled JTAG signal level for work with interfaces with high PD signal level e Tight JTAG signal level setting independent from PD level e Compatible with Texas Instruments XDS510 emulator e Advanced JTAG controller SAU V 2 enables high emulation performance e Compatible with USB 1 1 and USB 2 0 high speed full speed e Drastic boost performance when connected via USB 3 0 depending on host controller type and his driver e While connected to PC via USB no additional power source is required e Three color status and mode LED indicator e Supports programming and configuring FPGA and CPLD through SVE player SVF Specification Rev E Lattice Semiconductor enhancements e Supports internal and external in circuit supported processors memory programming through SauFlash TCLXDS utility shipped with drivers e Supports Adaptive Clocking w
15. ed connection Fmulators to one PC The ke y factor Board Data Fie atoes O OOOO O O is to link each connection to a Use specified emulator only de finite Emulator by lits serial merced mme p p umber Persana Select the Advanced tab in the Target Contiguration editor Select the connection After that TCK Frequency 15 000 MHz bd Connections Properties will appear TCR Frequency divider range 1 C Enable additional 8x TCK divider on the right side Set the parameter TCRR signal made Target provide TCKR signal we Use specified emulator only and Enable adaptive clocking after that enter the values into the TMS TDO Output Timing Change at rising edge allows higher TK v Enter Serial Number and Enter Serial Number again fields TCER input termination Enable 120 Ohm termination we TDI input termination Enable 120 Ohm termination we o voltage Sette value aE PD pin with damping v JTAG output level clamping 3 3V defau we EMUDT O pin made Rs put with pulup eku T EMUI Opin made Rs input with pulup efeu Link delay STK cdsa SSO Polling of Icepick router Skipped aw 16 Copyright 2014 Sauris GmbH v nil SAU XDS510 USB Lite SAURIS User s guide JTAG Emulator www Ssauris de Revision 1 00 JUL2014 3 6 2 Parameters for setting TCK frequency There are two ways to enable the clocking of the JTAG chain These are clocking at a fixed freque
16. equential termination of the TMS TCK and TDI signals Figure 3 9 shows an application with the system test clock generated in the target System The TCK signal is left unconnected in this application There are two reasons for having the target system generating the test clock o The emulator provides a 25 MHz test clock on default the actual value can be adjusted in the configuration file When using the target system test clock you can set the frequency to match your system requirements o Sometimes the test clock is required when the Emulator is switched off Figure 3 10 shows emulator mode without using return clocking TCK RET Parameter cGonfiguraLion description ais shown 19 pe2 0 4 Signal TCKR TCR BET 1s optional in ARM20 connector and may be left unconnected in pcb Example of such pcb type is IAR KickStart Kit for TMSA4A70 To work with such type of pcb it is required to use this type of connection and mode 14 Copyright 2014 Sauris GmbH Pes t Fa DM N Bil SAU XDS510 USB Lite AURIS User s guide JTAG Emulator www sauris de Revision 1 00 JUL2014 Bonee 15 cw VCC JTAG Device Emulator Header EMUO EMU EMU TRST TRST TMS 8 Ts TDI TDI TDO TCK System Test Clock Figure 3 9 Target System Generates Figure 3 10 Work without return JTAG Test Clock clocking TCK RET Figure 3 11 shows a typical multiprocessor configuration This is a daisy chained conf
17. et doesn t provide TCKR signal A Target doesn t provide TCKR signal doesn t Target doesn t provide TCKR signal TCER signal id i approximately the same delay as TMS TOO Output Timing Change at rising edge allows higher TCK outside circuit does when it Additional delay Far internal TEER bypass ii ns includes standard cable and 5 cm TERR input termination T length of TCK gt TCKR There is an TDI input termination opportunity to increase this delay I O voltage by the 4 8 ns 1 210 MHz step JTAG output level clamping GW defaub we EMLID 1 0 pin mode Asimputwihpulup defaut v To enable operating without return EMUL I O pin made As input with pullup default v clocking mode set Target doesn t abate STCkdeds ddau F provide TORR S10nal in the TICKER Signal mode parameter After that set Additional delay for internal TCKR bypass path Polling of Icenirk router Skipped 3 6 5 TMS and TDO emulator signals output buffers clocking mode Data update may occur on both Signal TCK RET falling edge and on rising edge While outputting on Board Data File autogenerate i ej falling edge the work complies Connection Properties Set Ehe properties of the selected connection Use specified emulator only with IEEE1149 1 While outputting TCK Frequency divider range xt ee a E ce ee use higher clock eres While TCE Frequenc 15 000 MHz quency E emulator is working i
18. fied value 1 654 As input with pullup default JTAG output levels EMUO TIG pin made 3206 9 EMUO 1 pin Connection Properties Set Ehe properties of the selected connection auto generate Use specified emulator only 15 000 MHz Enable additional amp x TCK divider TCKR signal mode Target provide TEER signal 4 Board Data File TCE Frequency Enable adaptive clocking TMS TDO Output Timing Change s rising edge lows higher TCK v Enable 120 Ohm termination F Enable 120 Ohm termination Set to value at PD pin with damping v saver id As input with pulp default As input wth pulup defa F TCER input termination TDI input termination TO voltage JTAG output level clamping EMUO I C pin mode EMOL I pin made 3 TCE clocks default Skipped T Link delay Polling of Icepick C router 20 www sauris de It is possible to limit JTAG Signal by value smaller or equal to voltage on PD pin For example in Case Of SV PD pin VOoLUage Je 2 5 processors compatibility is possible Force setting JTAG signal level is possible To do this it s required to set I O voltage parameter to Force to Specified value After that it is possible to force set JTAG output levels parameter value EMU pins are bidirectional and set the JTAG operation mode They can be used for transmission of data and event The emulator can be used not only as inputs for
19. gure 3 4 Emulator with adapter Figure 3 5 Emulator without adapter 3 4 Emulator Cable Pod Signal Timing Figure 3 6 shows the clock signal timings for the emulator Table 4 defines the timing parameters for the emulator The timing parameters are for reference only Sauris GmbH has not tested them and doesn t guarantee their coincidence with the given in the table The emulator pod uses MEE 5 TCE BEI ae 108 clock source for internal synchronization TCK can also TDO be used as an optional test clock source for the target system I oic nj x I TCK_RET t TCkFighen n TMS TDI Figure 3 6 Signal Timings for the Emulator Copyright O 2014 Sauris GmbH 13 F iss ST C Fi hy 3 i I I JTAG Emulator User s guide S AURIS Revision 1 00 JUL 2014 www Ssauris de SAU XDS510 USB Lite Table 4 Emulator Pod Timing Parameters No Reference Description Min Max Units TCK RET period ns TCK RET high pulse duration 9 TCK RET low pulse duration 9 TMS TDI setting time after TCK RET Ca xTMX edge TDO setup time to TCK RET high TOO hold Lime trom TCK RET Migh from positive edge of TOR RET 11 POD TDOONTCRKFALL NO and irom negative edge Of TMS TDI 12 POD TDOONTCKFALL YES 5 Buffering Signals Between the Emulator and the Target System It is extremely important to provide high quality signals between the emulator and the target system especially the processor
20. iguration TDO TDI daisy chained that meets the minimum requirements of the IEEE 1149 1 specification The emulation signals in this example are buffered to isolate the processors from the emulator and provide adequate control signal for the target system One of JTAG test interface benefits is that you can slow down the test clock to eliminate timing problems Multiprocessor systems should meet the following requirements O The processor TMS TDI TDO and TCK signals are to be buffered to control timing skew better o The input burters for TMs TDI and TCK should have pull ups to voc This will hold these signals at a required value if the emulator is switched off A pull up resistor of 4 7k Q is suggested for most applications JTAG Device JTAG Device VCC Emulator Header cn PD 1 1 m3 e GND Figure 3 11 Multiprocessor Connections Copyright O 2014 Sauris GmbH 15 SAU XDS510 USB Lite JTAG Emulator User s guide Revision 1 00 JUL 2014 www Ssauris de 3 6 JTAG connection settings The following emulator connection parameters can be configured in the tab Advanced of Target Configuration panel On the tab you can set various parameters and conditions to ensure the correct emulator operation to debug the device Below is a description of the available positions for adjustments in the integrated development environment Code Composer Studio v 6 For CCS 4 x and 5 x parameters are set sim
21. ilarly For CC4 10 for TMS320VC33 CCS 2 x and CCS3 x it 1S possible to change parameters by direct configuration file edit Visit our forum for these IDES parameter setting details NewTargetConfiguration ccxml 23 8 Target Configuration E E All Connections Connection Properties T Sauris SAU XDSS10 USB Lite Emulator D Set the properties of the selected connection C TM5320F28035_0 Board Data File auto generate e F qt C28xx O use specified emulator only B s CLA TCK Frequency divider range x1 TCK Frequency 15 000 MHz e J Enable additional 8x TCK divider TCKR signal mode Target provide TCKR signal EN C Enable adaptive clocking TMS TDO Output Timing Change at rising edge allows higher TCK TCKR input termination Enable 120 Ohm termination TDI input termination Enable 120 Ohm termination I O voltage Set to value at PD pin with clamping JTAG output level clamping 3 3V default EMUO I O pin mode 4s input with pullup default EMU1 I O pin mode 4s input with pullup default Link delay 3 TCK clocks default k Polling of Icepick C router Skipped Basic Advanced NewTargetConfiguration ccxml 3 6 1 Parameters for connection several emulators to one PC Below you will find the parameters Connection Properties required LOI connecting several Set Ehe properties of Ehe select
22. ipped aw TEER input termination TOT input termination 3 6 7 Connection tweaking Connection Properties Set the properties of the selected connection auto generate 4 Use specified emulator only 15 000 MHz ss Enable additional amp x TCK divider TCKR signal mode Target provide TEER signal 4 Board Data File TCE Frequency Enable adaptive clocking TMS TDO Output Timing Change at rising edge allows higher TCK F Enable 120 Ohm termination w Enable 120 Ohm termination w jo voltage Set to value af PO pin with damping JTAG output level clamping BBV default awe EHUO YO pinmode As input with pulup defa v As input with pulup defa STEK cons defa SSS TCER input termination TDI input termination EMOL IO pin mode Polling of Icepick C router Skipped e Copyright 2014 Sauris GmbH Enter SerialNumber again OQ Impedance matching circuits control There 1S an opportunity to connect the impedance matching circuits to TCKR and TDI pins to improve this Signals quality This connection is on by default To connect the impedance matching Circuits to TCKR and TDI you should set appropriate value in TDI input termination or HPCISES input termination parameters Link delay This parameter sets the number of TMS and TDO delay cycles after they are generated in the emulator by JTAG controller and before they come to the
23. is de Revision 1 00 JUL2014 3 2 Bus Protocol The IEEE 1149 1 specification covers the requirements for JTAG bus of the target devices such as the TMS320C6000 family and provides certain rules summarized as follows The TMS TDI inputs are sampled on the rising edge of the device TCK signal The TDO output is clocked from the falling edge of the device TCK signal When JTAG devices are daisy chained together the TDO from each of the devices in the chain has a definite period in the TCK cycle Such synchronization scheme allows to distinguish the data from different target devices included into the same chain The penalty for this timing scheme is a reduced TCK frequency The IEEE 1149 1 specification does not provide rules for JTAG bus master devices e g emulator 3 3 Emulator Cable Pod Logic SAU XDS510 USB Lite emulator set contains three adapters 14 pin TI JTAG 20 pin CTI JTAG and 20 pin ARM Figure 3 4 shows the emulator with 14 pin TI JTAG adapter In case of there is a free space on pcb it is possible to connect emulator directly without using adapter Figure 3 5 Key features of JTAG interface TMS and TDL signals are generated Irom the rising edge of TCK RET on default but the standard can be adjusted in the configuration file e The edges of TMS TDI TCK and TRST signals do not coincide in order to reduce Signal echo TOE equals Lo MUZ on OeISUubt You May also set another devel Or TCR r Fi
24. ithout additional adapters e Flexible TCK frequency adjustment e Possible LO work from target TICK source trom MORR TCR REI Possible Lo work without TCKR TCR BEI signal e Supports JTAG signal buffering including registers clocking TCK buffering e Compatible with Texas Instruments Code Composer IDE v 4 10 for TMS320C3x 4x and Code Composer Studio IDE all versions e Compatible with Microsoft Windows 2000 Windows XP Windows Vista 32 bit 64 bit Windows 7 Windows 8 Windows 8 1 Windows Server e Compatible with Linux full technical support for RHEL Centos Fedora distributions consultative for others 6 Copyright 2014 Sauris GmbH fo CN v Bil SAU XDS510 USB Lite AURIS User s guide JTAG Emulator www sauris de Revision 1 00 JUL2014 1 3 Key Items of SAU XDS510 USB Lite JTAG Emulator SAU XDS510 USB Lite view is shown in Figure 1 2 Figure 1 2 SAU XDS510 USB Lite JTAG emulator Key items are 1 Emulator with JTAG connector 2 3 color status LED indicator 3 USB cable 2 SAU XDS510 USB Lite JTAG Emulator Plugging This chapter helps you to plug SAU XDS510 USB Lite JTAG Emulator into your system Note you should have Code Composer Studio installed before installing SAU XDS510 USB Lite In order to use specific software packages such as the Code Composer Studio from TI refer to the manufacturer s documentation 2 1 Equipment required The lists below include the
25. l Questions or Samples Order Also you can find warranty terms on our web Copyright 2014 Sauris GmbH a oo Fi i pn n E Y k SAU XDS510 USB Lite JTAG Emulator User s gu ide S AURIS Revision 1 00 JUL 2014 www Ssauris de IMPORTANT NOTICE Sauris GmbH reserves the right to make changes to its products or to discontinue any product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current Sauris GmbH warrants performance of its products and related software to current specifications in accordance with our standard warranty Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty Please be aware that the products described herein are not intended for use in life support appliances devices or systems Sauris GmbH assumes no liability for applications assistance customer product design software performance or infringement of patents or Services described herein Nor does Sauris GmbH warrant or represent any license either express or implied is granted under any patent right copyright or other intellectual property right of Sauris GmbH covering or relating to any combination machine or process in which such Digital Signal Processing development products or services might be or are used WARNING This equipment is to be u
26. n Adaptive C Enable additional amp x TCK divider Clocking mode with proOOSSSOLS TCER signal made Target provide TCER signal containing ARM9 or ARM11 core use falling edge TDO TMS outputting To get maximum emulation speed use TMS TDO Output Timing Change at rising edge allows higher TCR 0 rising edge TDO TMS outputting TCKR input termination with maximum TCK clock on which TDI input termination System works stable JO vokage JTAG output level clamping EMD HO pin mode EMU 10 pin mode nk delay Polling of Icepick C router Skipped Enable adaptive clocking 18 Copyright 2014 Sauris GmbH Po a Amh GS AURIS User s guide SAU XDS510 USB Lite JTAG Emulator Revision 1 00 JUL2014 www sauris de 36 6 Connection Properties Set the properties of the selected connection auto generate E Use specified emulator only Board Data File Enter Serial Number 15 000 MHz L Enable additional 8x TEK divider Target provide TCRR signal 4 TCE Frequency TCRR signal mode Enable adaptive clocking TMS TDO Output Timing Change at rising edge allows higher TCK Enable 120 Ohm termination Enable 120 Ohm termination M Tjo voltage Set to value aE PD pin with clamping JTAG output level clamping 3 3W default oe EMUO 1 0 pin made 7s input wth pulup deFaut v EMUI O pin mode As input wth pulup defod F Link delay STCK docks teta Polling of Icepick C router Sk
27. ncy Board Data Fie ba and adaptive clocking The fixed Use specified emulator only frequency can be used for most Enter Serial Mumher OO hardware where the maximum allowed Enter Serial Number again TCK does not depend on the CPU TeKFrequeneyedertenge XP Pp frequency The adaptive clocking is used for the devices that require TCK Frequency 15 000 MHz ka dynamically changing ICK TOI L Enable additional 8x TEK divider operating in these devices the TCER signal made Target provide TCER signal TCK is based on the clock frequency of the CPU DaVinci is an example of such a device it includes ARM Pe eee UNUM LINDA dL ME and DSP cores that have different TESTE Ee lu Enable 120 Ohm termination clock frequency and the TCK in each TDI input termination Enable 120 Ohm termination we moment depends on the frequency of 1 0 voltage Set to value at PD pin with clamping v the currently active core JTAG output level clamping 3 34 default oe EMUO IMG pin mode As input with pullup default fw To Set the TCK in the CCS select EMUI I O pin made As input with pullup default owe tab Connections Properties and link delay 3 TCK docks default e set TCK Frequency Divider range and TCK Frequency You can initiate an P hee Steuer Skipped additional frequency divider by setting Enable additional 8x TCK Connection Properties Set Ehe properties of the selected connection
28. out adapter aligning conpnecLors X1rst contacts Follow these steps to connect SAU XDS510 USB Lite emulator La Turn off all antivirus software on your PC 2 Insert the Sauris GmbH USB Driver CD in the computer CD ROM drive Figure 2 1 Connecting SAU XDS510 USB Lite 3 The installer starts automatically if autoplay is turned on If it doesn t open the CD with the drivers in the File Manager window and run CD Windows sau510usb Install exe and follow the instructions on the screen 4 Turn on the antivirus software if needed 5 Connect your SAU XDS510 USB Lite JTAG emulator USB cable to PC 6 After a while Windows will detect a new hardware and prompt you with New Hardware Found screen If you want to verify the USB driver installation has been successful right click Control Panel and select Properties Hardware Device Manager You should see a new class JTAG Emulator and one emulator SAU XDS510 USB Lite JTAG emulator installed 7 Connect the emulator to the JTAG on your target board In future after the drivers are installed follow these steps to connect SAU XDS510 USB Lite JTAG emulator l Turn off the power supply of your target board 2 Connect the emulator s JTAG connector to your target board 3 Connect SAU XDS510 USB Lite JTAG emulator s USB cable to PC 4 Apply power to the target board Detach SAU XDS510 USB Lite JTAG emulator in the reverse order l Turn off the power supply of your target
29. sed in laboratory facilities only It generates uses and can radiate electromagnetic energy and has not been tested for compliance with the limits of computing devices according to clause J part 15 FCC rules that are designed to specify the acceptable level of electromagnetic interference Operation of this equipment may cause radio interference TRADEMARKS Microsoft and Windows are registered trademarks of Microsoft Corporation Code Composer and Code Composer Studio are registered trademarks of Texas Instruments Copyright 2014 Sauris GmbH 4 Copyright 2014 Sauris GmbH See UN NA N Bl SAU XDS510 USB Lite GS AURIS User s guide JTAG Emulator www sauris de Revision 1 00 JUL2014 About This Manual This manual describes SAU XDS510 USB Lite JTAG emulator designed for being used in combination with digital Signal processors DSPs and microcontrollers manufactured by Texas Instruments Incorporated TI SAU XDS510 USB Lite JTAG Emulator is a portable table top device attached to a personal computer or a laptop It allows to develop and debug applications based on DSPs and microcontrollers from TI l Introduction to SAU XDS510 USB Lite JTAG Emulator This chapter provides a description of SAU XDS510 USB Lite JTAG Emulator and its key features 1 1 Overview of SAU XDS510 USB Lite JTAG Emulator SAU XDS510 USB Lite JTAG Emulator was designed for being used with digital signal processors DSPs and microprocessors
30. that are connected through JTAG The Emulator supports connection through JTAG at the levels of 1 65 3 3 volt 5V tolerant The Emulator is connected to a PC using USB interface and draws no power from the target system Figure 1 1 shows the SAU XDS510 USB Lite JTAG Emulator SAU XDS510 USB Lite JTAG Emulator set contains SAU XDS510 USB Lite JTAG emulator 3 adapters 14 pin TI 20 pin CTI and 20 pin ARM CD ROM with drivers batteren ETT Figure 1 1 SAU XDS510 USB Lite JTAG Emulator SAU XDS510 USB Lite is designed to be compatible with the existing debuggers provided by Texas Instruments Copyright O 2014 Sauris GmbH B SAU XDS510 USB Lite N NO GIDE JTAG Emulator User s gu ide g AURIS Revision 1 00 JUL 2014 www Ssauris de 1 2 Key Features of SAU XDS510 USB Lite JTAG Emulator SAU XDS510 USB Lite JTAG Emulator has the following features e Supports Texas Instruments digital Signal processors processors and microcontrollers C2000 including LF24xx and F24x C5000 C6000 ARM7 ARMY ARM11 Cortex A Cortex R Cortex M DaVinci OMAP Sitara Tegra Integra Keystone Piccolo Delfino Hercules Stellaris Tiva TMS470 TMS570 RM4 etc TMS320VC33 It also supports any multicores and or multiprocessors combinations of listed above cores and processors both placed into one chip and connected in one JTAG chain in device with possibility of connection other devices e g FPGA in this chain
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